1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
53 #ifndef CHECK_STACK_LIMIT
54 #define CHECK_STACK_LIMIT (-1)
57 /* Return index of given mode in mult and division cost tables. */
58 #define MODE_INDEX(mode) \
59 ((mode) == QImode ? 0 \
60 : (mode) == HImode ? 1 \
61 : (mode) == SImode ? 2 \
62 : (mode) == DImode ? 3 \
65 /* Processor costs (relative to an add) */
67 struct processor_costs size_cost = { /* costs for tunning for size */
68 2, /* cost of an add instruction */
69 3, /* cost of a lea instruction */
70 2, /* variable shift costs */
71 3, /* constant shift costs */
72 {3, 3, 3, 3, 5}, /* cost of starting a multiply */
73 0, /* cost of multiply per each bit set */
74 {3, 3, 3, 3, 5}, /* cost of a divide/mod */
75 3, /* cost of movsx */
76 3, /* cost of movzx */
79 2, /* cost for loading QImode using movzbl */
80 {2, 2, 2}, /* cost of loading integer registers
81 in QImode, HImode and SImode.
82 Relative to reg-reg move (2). */
83 {2, 2, 2}, /* cost of storing integer registers */
84 2, /* cost of reg,reg fld/fst */
85 {2, 2, 2}, /* cost of loading fp registers
86 in SFmode, DFmode and XFmode */
87 {2, 2, 2}, /* cost of loading integer registers */
88 3, /* cost of moving MMX register */
89 {3, 3}, /* cost of loading MMX registers
90 in SImode and DImode */
91 {3, 3}, /* cost of storing MMX registers
92 in SImode and DImode */
93 3, /* cost of moving SSE register */
94 {3, 3, 3}, /* cost of loading SSE registers
95 in SImode, DImode and TImode */
96 {3, 3, 3}, /* cost of storing SSE registers
97 in SImode, DImode and TImode */
98 3, /* MMX or SSE register to integer */
99 0, /* size of prefetch block */
100 0, /* number of parallel prefetches */
102 2, /* cost of FADD and FSUB insns. */
103 2, /* cost of FMUL instruction. */
104 2, /* cost of FDIV instruction. */
105 2, /* cost of FABS instruction. */
106 2, /* cost of FCHS instruction. */
107 2, /* cost of FSQRT instruction. */
110 /* Processor costs (relative to an add) */
112 struct processor_costs i386_cost = { /* 386 specific costs */
113 1, /* cost of an add instruction */
114 1, /* cost of a lea instruction */
115 3, /* variable shift costs */
116 2, /* constant shift costs */
117 {6, 6, 6, 6, 6}, /* cost of starting a multiply */
118 1, /* cost of multiply per each bit set */
119 {23, 23, 23, 23, 23}, /* cost of a divide/mod */
120 3, /* cost of movsx */
121 2, /* cost of movzx */
122 15, /* "large" insn */
124 4, /* cost for loading QImode using movzbl */
125 {2, 4, 2}, /* cost of loading integer registers
126 in QImode, HImode and SImode.
127 Relative to reg-reg move (2). */
128 {2, 4, 2}, /* cost of storing integer registers */
129 2, /* cost of reg,reg fld/fst */
130 {8, 8, 8}, /* cost of loading fp registers
131 in SFmode, DFmode and XFmode */
132 {8, 8, 8}, /* cost of loading integer registers */
133 2, /* cost of moving MMX register */
134 {4, 8}, /* cost of loading MMX registers
135 in SImode and DImode */
136 {4, 8}, /* cost of storing MMX registers
137 in SImode and DImode */
138 2, /* cost of moving SSE register */
139 {4, 8, 16}, /* cost of loading SSE registers
140 in SImode, DImode and TImode */
141 {4, 8, 16}, /* cost of storing SSE registers
142 in SImode, DImode and TImode */
143 3, /* MMX or SSE register to integer */
144 0, /* size of prefetch block */
145 0, /* number of parallel prefetches */
147 23, /* cost of FADD and FSUB insns. */
148 27, /* cost of FMUL instruction. */
149 88, /* cost of FDIV instruction. */
150 22, /* cost of FABS instruction. */
151 24, /* cost of FCHS instruction. */
152 122, /* cost of FSQRT instruction. */
156 struct processor_costs i486_cost = { /* 486 specific costs */
157 1, /* cost of an add instruction */
158 1, /* cost of a lea instruction */
159 3, /* variable shift costs */
160 2, /* constant shift costs */
161 {12, 12, 12, 12, 12}, /* cost of starting a multiply */
162 1, /* cost of multiply per each bit set */
163 {40, 40, 40, 40, 40}, /* cost of a divide/mod */
164 3, /* cost of movsx */
165 2, /* cost of movzx */
166 15, /* "large" insn */
168 4, /* cost for loading QImode using movzbl */
169 {2, 4, 2}, /* cost of loading integer registers
170 in QImode, HImode and SImode.
171 Relative to reg-reg move (2). */
172 {2, 4, 2}, /* cost of storing integer registers */
173 2, /* cost of reg,reg fld/fst */
174 {8, 8, 8}, /* cost of loading fp registers
175 in SFmode, DFmode and XFmode */
176 {8, 8, 8}, /* cost of loading integer registers */
177 2, /* cost of moving MMX register */
178 {4, 8}, /* cost of loading MMX registers
179 in SImode and DImode */
180 {4, 8}, /* cost of storing MMX registers
181 in SImode and DImode */
182 2, /* cost of moving SSE register */
183 {4, 8, 16}, /* cost of loading SSE registers
184 in SImode, DImode and TImode */
185 {4, 8, 16}, /* cost of storing SSE registers
186 in SImode, DImode and TImode */
187 3, /* MMX or SSE register to integer */
188 0, /* size of prefetch block */
189 0, /* number of parallel prefetches */
191 8, /* cost of FADD and FSUB insns. */
192 16, /* cost of FMUL instruction. */
193 73, /* cost of FDIV instruction. */
194 3, /* cost of FABS instruction. */
195 3, /* cost of FCHS instruction. */
196 83, /* cost of FSQRT instruction. */
200 struct processor_costs pentium_cost = {
201 1, /* cost of an add instruction */
202 1, /* cost of a lea instruction */
203 4, /* variable shift costs */
204 1, /* constant shift costs */
205 {11, 11, 11, 11, 11}, /* cost of starting a multiply */
206 0, /* cost of multiply per each bit set */
207 {25, 25, 25, 25, 25}, /* cost of a divide/mod */
208 3, /* cost of movsx */
209 2, /* cost of movzx */
210 8, /* "large" insn */
212 6, /* cost for loading QImode using movzbl */
213 {2, 4, 2}, /* cost of loading integer registers
214 in QImode, HImode and SImode.
215 Relative to reg-reg move (2). */
216 {2, 4, 2}, /* cost of storing integer registers */
217 2, /* cost of reg,reg fld/fst */
218 {2, 2, 6}, /* cost of loading fp registers
219 in SFmode, DFmode and XFmode */
220 {4, 4, 6}, /* cost of loading integer registers */
221 8, /* cost of moving MMX register */
222 {8, 8}, /* cost of loading MMX registers
223 in SImode and DImode */
224 {8, 8}, /* cost of storing MMX registers
225 in SImode and DImode */
226 2, /* cost of moving SSE register */
227 {4, 8, 16}, /* cost of loading SSE registers
228 in SImode, DImode and TImode */
229 {4, 8, 16}, /* cost of storing SSE registers
230 in SImode, DImode and TImode */
231 3, /* MMX or SSE register to integer */
232 0, /* size of prefetch block */
233 0, /* number of parallel prefetches */
235 3, /* cost of FADD and FSUB insns. */
236 3, /* cost of FMUL instruction. */
237 39, /* cost of FDIV instruction. */
238 1, /* cost of FABS instruction. */
239 1, /* cost of FCHS instruction. */
240 70, /* cost of FSQRT instruction. */
244 struct processor_costs pentiumpro_cost = {
245 1, /* cost of an add instruction */
246 1, /* cost of a lea instruction */
247 1, /* variable shift costs */
248 1, /* constant shift costs */
249 {4, 4, 4, 4, 4}, /* cost of starting a multiply */
250 0, /* cost of multiply per each bit set */
251 {17, 17, 17, 17, 17}, /* cost of a divide/mod */
252 1, /* cost of movsx */
253 1, /* cost of movzx */
254 8, /* "large" insn */
256 2, /* cost for loading QImode using movzbl */
257 {4, 4, 4}, /* cost of loading integer registers
258 in QImode, HImode and SImode.
259 Relative to reg-reg move (2). */
260 {2, 2, 2}, /* cost of storing integer registers */
261 2, /* cost of reg,reg fld/fst */
262 {2, 2, 6}, /* cost of loading fp registers
263 in SFmode, DFmode and XFmode */
264 {4, 4, 6}, /* cost of loading integer registers */
265 2, /* cost of moving MMX register */
266 {2, 2}, /* cost of loading MMX registers
267 in SImode and DImode */
268 {2, 2}, /* cost of storing MMX registers
269 in SImode and DImode */
270 2, /* cost of moving SSE register */
271 {2, 2, 8}, /* cost of loading SSE registers
272 in SImode, DImode and TImode */
273 {2, 2, 8}, /* cost of storing SSE registers
274 in SImode, DImode and TImode */
275 3, /* MMX or SSE register to integer */
276 32, /* size of prefetch block */
277 6, /* number of parallel prefetches */
279 3, /* cost of FADD and FSUB insns. */
280 5, /* cost of FMUL instruction. */
281 56, /* cost of FDIV instruction. */
282 2, /* cost of FABS instruction. */
283 2, /* cost of FCHS instruction. */
284 56, /* cost of FSQRT instruction. */
288 struct processor_costs k6_cost = {
289 1, /* cost of an add instruction */
290 2, /* cost of a lea instruction */
291 1, /* variable shift costs */
292 1, /* constant shift costs */
293 {3, 3, 3, 3, 3}, /* cost of starting a multiply */
294 0, /* cost of multiply per each bit set */
295 {18, 18, 18, 18, 18}, /* cost of a divide/mod */
296 2, /* cost of movsx */
297 2, /* cost of movzx */
298 8, /* "large" insn */
300 3, /* cost for loading QImode using movzbl */
301 {4, 5, 4}, /* cost of loading integer registers
302 in QImode, HImode and SImode.
303 Relative to reg-reg move (2). */
304 {2, 3, 2}, /* cost of storing integer registers */
305 4, /* cost of reg,reg fld/fst */
306 {6, 6, 6}, /* cost of loading fp registers
307 in SFmode, DFmode and XFmode */
308 {4, 4, 4}, /* cost of loading integer registers */
309 2, /* cost of moving MMX register */
310 {2, 2}, /* cost of loading MMX registers
311 in SImode and DImode */
312 {2, 2}, /* cost of storing MMX registers
313 in SImode and DImode */
314 2, /* cost of moving SSE register */
315 {2, 2, 8}, /* cost of loading SSE registers
316 in SImode, DImode and TImode */
317 {2, 2, 8}, /* cost of storing SSE registers
318 in SImode, DImode and TImode */
319 6, /* MMX or SSE register to integer */
320 32, /* size of prefetch block */
321 1, /* number of parallel prefetches */
323 2, /* cost of FADD and FSUB insns. */
324 2, /* cost of FMUL instruction. */
325 56, /* cost of FDIV instruction. */
326 2, /* cost of FABS instruction. */
327 2, /* cost of FCHS instruction. */
328 56, /* cost of FSQRT instruction. */
332 struct processor_costs athlon_cost = {
333 1, /* cost of an add instruction */
334 2, /* cost of a lea instruction */
335 1, /* variable shift costs */
336 1, /* constant shift costs */
337 {5, 5, 5, 5, 5}, /* cost of starting a multiply */
338 0, /* cost of multiply per each bit set */
339 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
340 1, /* cost of movsx */
341 1, /* cost of movzx */
342 8, /* "large" insn */
344 4, /* cost for loading QImode using movzbl */
345 {3, 4, 3}, /* cost of loading integer registers
346 in QImode, HImode and SImode.
347 Relative to reg-reg move (2). */
348 {3, 4, 3}, /* cost of storing integer registers */
349 4, /* cost of reg,reg fld/fst */
350 {4, 4, 12}, /* cost of loading fp registers
351 in SFmode, DFmode and XFmode */
352 {6, 6, 8}, /* cost of loading integer registers */
353 2, /* cost of moving MMX register */
354 {4, 4}, /* cost of loading MMX registers
355 in SImode and DImode */
356 {4, 4}, /* cost of storing MMX registers
357 in SImode and DImode */
358 2, /* cost of moving SSE register */
359 {4, 4, 6}, /* cost of loading SSE registers
360 in SImode, DImode and TImode */
361 {4, 4, 5}, /* cost of storing SSE registers
362 in SImode, DImode and TImode */
363 5, /* MMX or SSE register to integer */
364 64, /* size of prefetch block */
365 6, /* number of parallel prefetches */
367 4, /* cost of FADD and FSUB insns. */
368 4, /* cost of FMUL instruction. */
369 24, /* cost of FDIV instruction. */
370 2, /* cost of FABS instruction. */
371 2, /* cost of FCHS instruction. */
372 35, /* cost of FSQRT instruction. */
376 struct processor_costs k8_cost = {
377 1, /* cost of an add instruction */
378 2, /* cost of a lea instruction */
379 1, /* variable shift costs */
380 1, /* constant shift costs */
381 {3, 4, 3, 4, 5}, /* cost of starting a multiply */
382 0, /* cost of multiply per each bit set */
383 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
384 1, /* cost of movsx */
385 1, /* cost of movzx */
386 8, /* "large" insn */
388 4, /* cost for loading QImode using movzbl */
389 {3, 4, 3}, /* cost of loading integer registers
390 in QImode, HImode and SImode.
391 Relative to reg-reg move (2). */
392 {3, 4, 3}, /* cost of storing integer registers */
393 4, /* cost of reg,reg fld/fst */
394 {4, 4, 12}, /* cost of loading fp registers
395 in SFmode, DFmode and XFmode */
396 {6, 6, 8}, /* cost of loading integer registers */
397 2, /* cost of moving MMX register */
398 {3, 3}, /* cost of loading MMX registers
399 in SImode and DImode */
400 {4, 4}, /* cost of storing MMX registers
401 in SImode and DImode */
402 2, /* cost of moving SSE register */
403 {4, 3, 6}, /* cost of loading SSE registers
404 in SImode, DImode and TImode */
405 {4, 4, 5}, /* cost of storing SSE registers
406 in SImode, DImode and TImode */
407 5, /* MMX or SSE register to integer */
408 64, /* size of prefetch block */
409 6, /* number of parallel prefetches */
411 4, /* cost of FADD and FSUB insns. */
412 4, /* cost of FMUL instruction. */
413 19, /* cost of FDIV instruction. */
414 2, /* cost of FABS instruction. */
415 2, /* cost of FCHS instruction. */
416 35, /* cost of FSQRT instruction. */
420 struct processor_costs pentium4_cost = {
421 1, /* cost of an add instruction */
422 3, /* cost of a lea instruction */
423 4, /* variable shift costs */
424 4, /* constant shift costs */
425 {15, 15, 15, 15, 15}, /* cost of starting a multiply */
426 0, /* cost of multiply per each bit set */
427 {56, 56, 56, 56, 56}, /* cost of a divide/mod */
428 1, /* cost of movsx */
429 1, /* cost of movzx */
430 16, /* "large" insn */
432 2, /* cost for loading QImode using movzbl */
433 {4, 5, 4}, /* cost of loading integer registers
434 in QImode, HImode and SImode.
435 Relative to reg-reg move (2). */
436 {2, 3, 2}, /* cost of storing integer registers */
437 2, /* cost of reg,reg fld/fst */
438 {2, 2, 6}, /* cost of loading fp registers
439 in SFmode, DFmode and XFmode */
440 {4, 4, 6}, /* cost of loading integer registers */
441 2, /* cost of moving MMX register */
442 {2, 2}, /* cost of loading MMX registers
443 in SImode and DImode */
444 {2, 2}, /* cost of storing MMX registers
445 in SImode and DImode */
446 12, /* cost of moving SSE register */
447 {12, 12, 12}, /* cost of loading SSE registers
448 in SImode, DImode and TImode */
449 {2, 2, 8}, /* cost of storing SSE registers
450 in SImode, DImode and TImode */
451 10, /* MMX or SSE register to integer */
452 64, /* size of prefetch block */
453 6, /* number of parallel prefetches */
455 5, /* cost of FADD and FSUB insns. */
456 7, /* cost of FMUL instruction. */
457 43, /* cost of FDIV instruction. */
458 2, /* cost of FABS instruction. */
459 2, /* cost of FCHS instruction. */
460 43, /* cost of FSQRT instruction. */
464 struct processor_costs nocona_cost = {
465 1, /* cost of an add instruction */
466 1, /* cost of a lea instruction */
467 1, /* variable shift costs */
468 1, /* constant shift costs */
469 {10, 10, 10, 10, 10}, /* cost of starting a multiply */
470 0, /* cost of multiply per each bit set */
471 {66, 66, 66, 66, 66}, /* cost of a divide/mod */
472 1, /* cost of movsx */
473 1, /* cost of movzx */
474 16, /* "large" insn */
476 4, /* cost for loading QImode using movzbl */
477 {4, 4, 4}, /* cost of loading integer registers
478 in QImode, HImode and SImode.
479 Relative to reg-reg move (2). */
480 {4, 4, 4}, /* cost of storing integer registers */
481 3, /* cost of reg,reg fld/fst */
482 {12, 12, 12}, /* cost of loading fp registers
483 in SFmode, DFmode and XFmode */
484 {4, 4, 4}, /* cost of loading integer registers */
485 6, /* cost of moving MMX register */
486 {12, 12}, /* cost of loading MMX registers
487 in SImode and DImode */
488 {12, 12}, /* cost of storing MMX registers
489 in SImode and DImode */
490 6, /* cost of moving SSE register */
491 {12, 12, 12}, /* cost of loading SSE registers
492 in SImode, DImode and TImode */
493 {12, 12, 12}, /* cost of storing SSE registers
494 in SImode, DImode and TImode */
495 8, /* MMX or SSE register to integer */
496 128, /* size of prefetch block */
497 8, /* number of parallel prefetches */
499 6, /* cost of FADD and FSUB insns. */
500 8, /* cost of FMUL instruction. */
501 40, /* cost of FDIV instruction. */
502 3, /* cost of FABS instruction. */
503 3, /* cost of FCHS instruction. */
504 44, /* cost of FSQRT instruction. */
507 const struct processor_costs *ix86_cost = &pentium_cost;
509 /* Processor feature/optimization bitmasks. */
510 #define m_386 (1<<PROCESSOR_I386)
511 #define m_486 (1<<PROCESSOR_I486)
512 #define m_PENT (1<<PROCESSOR_PENTIUM)
513 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
514 #define m_K6 (1<<PROCESSOR_K6)
515 #define m_ATHLON (1<<PROCESSOR_ATHLON)
516 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
517 #define m_K8 (1<<PROCESSOR_K8)
518 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
519 #define m_NOCONA (1<<PROCESSOR_NOCONA)
521 const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8;
522 const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
523 const int x86_zero_extend_with_and = m_486 | m_PENT;
524 const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA /* m_386 | m_K6 */;
525 const int x86_double_with_add = ~m_386;
526 const int x86_use_bit_test = m_386;
527 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6;
528 const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
529 const int x86_fisttp = m_NOCONA;
530 const int x86_3dnow_a = m_ATHLON_K8;
531 const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
532 /* Branch hints were put in P4 based on simulation result. But
533 after P4 was made, no performance benefit was observed with
534 branch hints. It also increases the code size. As the result,
535 icc never generates branch hints. */
536 const int x86_branch_hints = 0;
537 const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA;
538 const int x86_partial_reg_stall = m_PPRO;
539 const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
540 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT);
541 const int x86_use_mov0 = m_K6;
542 const int x86_use_cltd = ~(m_PENT | m_K6);
543 const int x86_read_modify_write = ~m_PENT;
544 const int x86_read_modify = ~(m_PENT | m_PPRO);
545 const int x86_split_long_moves = m_PPRO;
546 const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8;
547 const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
548 const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
549 const int x86_qimode_math = ~(0);
550 const int x86_promote_qi_regs = 0;
551 const int x86_himode_math = ~(m_PPRO);
552 const int x86_promote_hi_regs = m_PPRO;
553 const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA;
554 const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA;
555 const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA;
556 const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA;
557 const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO);
558 const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
559 const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
560 const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO;
561 const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO;
562 const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO;
563 const int x86_decompose_lea = m_PENT4 | m_NOCONA;
564 const int x86_shift1 = ~m_486;
565 const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
566 const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO;
567 /* Set for machines where the type and dependencies are resolved on SSE
568 register parts instead of whole registers, so we may maintain just
569 lower part of scalar values in proper format leaving the upper part
571 const int x86_sse_split_regs = m_ATHLON_K8;
572 const int x86_sse_typeless_stores = m_ATHLON_K8;
573 const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
574 const int x86_use_ffreep = m_ATHLON_K8;
575 const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
577 /* ??? Allowing interunit moves makes it all too easy for the compiler to put
578 integer data in xmm registers. Which results in pretty abysmal code. */
579 const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
581 const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO;
582 /* Some CPU cores are not able to predict more than 4 branch instructions in
583 the 16 byte window. */
584 const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
585 const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT;
586 const int x86_use_bt = m_ATHLON_K8;
587 /* Compare and exchange was added for 80486. */
588 const int x86_cmpxchg = ~m_386;
589 /* Exchange and add was added for 80486. */
590 const int x86_xadd = ~m_386;
592 /* In case the average insn count for single function invocation is
593 lower than this constant, emit fast (but longer) prologue and
595 #define FAST_PROLOGUE_INSN_COUNT 20
597 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
598 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
599 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
600 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
602 /* Array of the smallest class containing reg number REGNO, indexed by
603 REGNO. Used by REGNO_REG_CLASS in i386.h. */
605 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
608 AREG, DREG, CREG, BREG,
610 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
612 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
613 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
616 /* flags, fpsr, dirflag, frame */
617 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
618 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
620 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
622 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
623 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
624 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
628 /* The "default" register map used in 32bit mode. */
630 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
632 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
633 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
634 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
635 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
636 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
637 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
638 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
641 static int const x86_64_int_parameter_registers[6] =
643 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
644 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
647 static int const x86_64_int_return_registers[4] =
649 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
652 /* The "default" register map used in 64bit mode. */
653 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
655 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
656 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
657 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
658 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
659 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
660 8,9,10,11,12,13,14,15, /* extended integer registers */
661 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
664 /* Define the register numbers to be used in Dwarf debugging information.
665 The SVR4 reference port C compiler uses the following register numbers
666 in its Dwarf output code:
667 0 for %eax (gcc regno = 0)
668 1 for %ecx (gcc regno = 2)
669 2 for %edx (gcc regno = 1)
670 3 for %ebx (gcc regno = 3)
671 4 for %esp (gcc regno = 7)
672 5 for %ebp (gcc regno = 6)
673 6 for %esi (gcc regno = 4)
674 7 for %edi (gcc regno = 5)
675 The following three DWARF register numbers are never generated by
676 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
677 believes these numbers have these meanings.
678 8 for %eip (no gcc equivalent)
679 9 for %eflags (gcc regno = 17)
680 10 for %trapno (no gcc equivalent)
681 It is not at all clear how we should number the FP stack registers
682 for the x86 architecture. If the version of SDB on x86/svr4 were
683 a bit less brain dead with respect to floating-point then we would
684 have a precedent to follow with respect to DWARF register numbers
685 for x86 FP registers, but the SDB on x86/svr4 is so completely
686 broken with respect to FP registers that it is hardly worth thinking
687 of it as something to strive for compatibility with.
688 The version of x86/svr4 SDB I have at the moment does (partially)
689 seem to believe that DWARF register number 11 is associated with
690 the x86 register %st(0), but that's about all. Higher DWARF
691 register numbers don't seem to be associated with anything in
692 particular, and even for DWARF regno 11, SDB only seems to under-
693 stand that it should say that a variable lives in %st(0) (when
694 asked via an `=' command) if we said it was in DWARF regno 11,
695 but SDB still prints garbage when asked for the value of the
696 variable in question (via a `/' command).
697 (Also note that the labels SDB prints for various FP stack regs
698 when doing an `x' command are all wrong.)
699 Note that these problems generally don't affect the native SVR4
700 C compiler because it doesn't allow the use of -O with -g and
701 because when it is *not* optimizing, it allocates a memory
702 location for each floating-point variable, and the memory
703 location is what gets described in the DWARF AT_location
704 attribute for the variable in question.
705 Regardless of the severe mental illness of the x86/svr4 SDB, we
706 do something sensible here and we use the following DWARF
707 register numbers. Note that these are all stack-top-relative
709 11 for %st(0) (gcc regno = 8)
710 12 for %st(1) (gcc regno = 9)
711 13 for %st(2) (gcc regno = 10)
712 14 for %st(3) (gcc regno = 11)
713 15 for %st(4) (gcc regno = 12)
714 16 for %st(5) (gcc regno = 13)
715 17 for %st(6) (gcc regno = 14)
716 18 for %st(7) (gcc regno = 15)
718 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
720 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
721 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
722 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
723 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
724 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
725 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
726 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
729 /* Test and compare insns in i386.md store the information needed to
730 generate branch and scc insns here. */
732 rtx ix86_compare_op0 = NULL_RTX;
733 rtx ix86_compare_op1 = NULL_RTX;
734 rtx ix86_compare_emitted = NULL_RTX;
736 /* Size of the register save area. */
737 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
739 /* Define the structure for the machine field in struct function. */
741 struct stack_local_entry GTY(())
746 struct stack_local_entry *next;
749 /* Structure describing stack frame layout.
750 Stack grows downward:
756 saved frame pointer if frame_pointer_needed
757 <- HARD_FRAME_POINTER
763 > to_allocate <- FRAME_POINTER
775 int outgoing_arguments_size;
778 HOST_WIDE_INT to_allocate;
779 /* The offsets relative to ARG_POINTER. */
780 HOST_WIDE_INT frame_pointer_offset;
781 HOST_WIDE_INT hard_frame_pointer_offset;
782 HOST_WIDE_INT stack_pointer_offset;
784 /* When save_regs_using_mov is set, emit prologue using
785 move instead of push instructions. */
786 bool save_regs_using_mov;
789 /* Code model option. */
790 enum cmodel ix86_cmodel;
792 enum asm_dialect ix86_asm_dialect = ASM_ATT;
794 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
796 /* Which unit we are generating floating point math for. */
797 enum fpmath_unit ix86_fpmath;
799 /* Which cpu are we scheduling for. */
800 enum processor_type ix86_tune;
801 /* Which instruction set architecture to use. */
802 enum processor_type ix86_arch;
804 /* true if sse prefetch instruction is not NOOP. */
805 int x86_prefetch_sse;
807 /* ix86_regparm_string as a number */
808 static int ix86_regparm;
810 /* Preferred alignment for stack boundary in bits. */
811 unsigned int ix86_preferred_stack_boundary;
813 /* Values 1-5: see jump.c */
814 int ix86_branch_cost;
816 /* Variables which are this size or smaller are put in the data/bss
817 or ldata/lbss sections. */
819 int ix86_section_threshold = 65536;
821 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
822 char internal_label_prefix[16];
823 int internal_label_prefix_len;
825 static bool ix86_handle_option (size_t, const char *, int);
826 static void output_pic_addr_const (FILE *, rtx, int);
827 static void put_condition_code (enum rtx_code, enum machine_mode,
829 static const char *get_some_local_dynamic_name (void);
830 static int get_some_local_dynamic_name_1 (rtx *, void *);
831 static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
832 static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
834 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
835 static enum machine_mode ix86_cc_modes_compatible (enum machine_mode,
837 static rtx get_thread_pointer (int);
838 static rtx legitimize_tls_address (rtx, enum tls_model, int);
839 static void get_pc_thunk_name (char [32], unsigned int);
840 static rtx gen_push (rtx);
841 static int ix86_flags_dependant (rtx, rtx, enum attr_type);
842 static int ix86_agi_dependant (rtx, rtx, enum attr_type);
843 static struct machine_function * ix86_init_machine_status (void);
844 static int ix86_split_to_parts (rtx, rtx *, enum machine_mode);
845 static int ix86_nsaved_regs (void);
846 static void ix86_emit_save_regs (void);
847 static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT);
848 static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int);
849 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT);
850 static HOST_WIDE_INT ix86_GOT_alias_set (void);
851 static void ix86_adjust_counter (rtx, HOST_WIDE_INT);
852 static rtx ix86_expand_aligntest (rtx, int);
853 static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx);
854 static int ix86_issue_rate (void);
855 static int ix86_adjust_cost (rtx, rtx, rtx, int);
856 static int ia32_multipass_dfa_lookahead (void);
857 static void ix86_init_mmx_sse_builtins (void);
858 static rtx x86_this_parameter (tree);
859 static void x86_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
860 HOST_WIDE_INT, tree);
861 static bool x86_can_output_mi_thunk (tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
862 static void x86_file_start (void);
863 static void ix86_reorg (void);
864 static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*);
865 static tree ix86_build_builtin_va_list (void);
866 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
868 static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
869 static bool ix86_vector_mode_supported_p (enum machine_mode);
871 static int ix86_address_cost (rtx);
872 static bool ix86_cannot_force_const_mem (rtx);
873 static rtx ix86_delegitimize_address (rtx);
875 static void i386_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
877 struct builtin_description;
878 static rtx ix86_expand_sse_comi (const struct builtin_description *,
880 static rtx ix86_expand_sse_compare (const struct builtin_description *,
882 static rtx ix86_expand_unop1_builtin (enum insn_code, tree, rtx);
883 static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
884 static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
885 static rtx ix86_expand_store_builtin (enum insn_code, tree);
886 static rtx safe_vector_operand (rtx, enum machine_mode);
887 static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
888 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
889 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
890 static int ix86_fp_comparison_sahf_cost (enum rtx_code code);
891 static int ix86_fp_comparison_cost (enum rtx_code code);
892 static unsigned int ix86_select_alt_pic_regnum (void);
893 static int ix86_save_reg (unsigned int, int);
894 static void ix86_compute_frame_layout (struct ix86_frame *);
895 static int ix86_comp_type_attributes (tree, tree);
896 static int ix86_function_regparm (tree, tree);
897 const struct attribute_spec ix86_attribute_table[];
898 static bool ix86_function_ok_for_sibcall (tree, tree);
899 static tree ix86_handle_cconv_attribute (tree *, tree, tree, int, bool *);
900 static int ix86_value_regno (enum machine_mode, tree, tree);
901 static bool contains_128bit_aligned_vector_p (tree);
902 static rtx ix86_struct_value_rtx (tree, int);
903 static bool ix86_ms_bitfield_layout_p (tree);
904 static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *);
905 static int extended_reg_mentioned_1 (rtx *, void *);
906 static bool ix86_rtx_costs (rtx, int, int, int *);
907 static int min_insn_size (rtx);
908 static tree ix86_md_asm_clobbers (tree outputs, tree inputs, tree clobbers);
909 static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type);
910 static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
912 static void ix86_init_builtins (void);
913 static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
914 static const char *ix86_mangle_fundamental_type (tree);
915 static tree ix86_stack_protect_fail (void);
917 /* This function is only used on Solaris. */
918 static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
921 /* Register class used for passing given 64bit part of the argument.
922 These represent classes as documented by the PS ABI, with the exception
923 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
924 use SF or DFmode move instead of DImode to avoid reformatting penalties.
926 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
927 whenever possible (upper half does contain padding).
929 enum x86_64_reg_class
932 X86_64_INTEGER_CLASS,
933 X86_64_INTEGERSI_CLASS,
940 X86_64_COMPLEX_X87_CLASS,
943 static const char * const x86_64_reg_class_name[] = {
944 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
945 "sseup", "x87", "x87up", "cplx87", "no"
948 #define MAX_CLASSES 4
950 /* Table of constants used by fldpi, fldln2, etc.... */
951 static REAL_VALUE_TYPE ext_80387_constants_table [5];
952 static bool ext_80387_constants_init = 0;
953 static void init_ext_80387_constants (void);
954 static bool ix86_in_large_data_p (tree) ATTRIBUTE_UNUSED;
955 static void ix86_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
956 static void x86_64_elf_unique_section (tree decl, int reloc) ATTRIBUTE_UNUSED;
957 static void x86_64_elf_select_section (tree decl, int reloc,
958 unsigned HOST_WIDE_INT align)
961 /* Initialize the GCC target structure. */
962 #undef TARGET_ATTRIBUTE_TABLE
963 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
964 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
965 # undef TARGET_MERGE_DECL_ATTRIBUTES
966 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
969 #undef TARGET_COMP_TYPE_ATTRIBUTES
970 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
972 #undef TARGET_INIT_BUILTINS
973 #define TARGET_INIT_BUILTINS ix86_init_builtins
974 #undef TARGET_EXPAND_BUILTIN
975 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
977 #undef TARGET_ASM_FUNCTION_EPILOGUE
978 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
980 #undef TARGET_ENCODE_SECTION_INFO
981 #ifndef SUBTARGET_ENCODE_SECTION_INFO
982 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
984 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
987 #undef TARGET_ASM_OPEN_PAREN
988 #define TARGET_ASM_OPEN_PAREN ""
989 #undef TARGET_ASM_CLOSE_PAREN
990 #define TARGET_ASM_CLOSE_PAREN ""
992 #undef TARGET_ASM_ALIGNED_HI_OP
993 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
994 #undef TARGET_ASM_ALIGNED_SI_OP
995 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
997 #undef TARGET_ASM_ALIGNED_DI_OP
998 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1001 #undef TARGET_ASM_UNALIGNED_HI_OP
1002 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1003 #undef TARGET_ASM_UNALIGNED_SI_OP
1004 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1005 #undef TARGET_ASM_UNALIGNED_DI_OP
1006 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1008 #undef TARGET_SCHED_ADJUST_COST
1009 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1010 #undef TARGET_SCHED_ISSUE_RATE
1011 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1012 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1013 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1014 ia32_multipass_dfa_lookahead
1016 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1017 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1020 #undef TARGET_HAVE_TLS
1021 #define TARGET_HAVE_TLS true
1023 #undef TARGET_CANNOT_FORCE_CONST_MEM
1024 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1026 #undef TARGET_DELEGITIMIZE_ADDRESS
1027 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1029 #undef TARGET_MS_BITFIELD_LAYOUT_P
1030 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1033 #undef TARGET_BINDS_LOCAL_P
1034 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1037 #undef TARGET_ASM_OUTPUT_MI_THUNK
1038 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1039 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1040 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1042 #undef TARGET_ASM_FILE_START
1043 #define TARGET_ASM_FILE_START x86_file_start
1045 #undef TARGET_DEFAULT_TARGET_FLAGS
1046 #define TARGET_DEFAULT_TARGET_FLAGS \
1048 | TARGET_64BIT_DEFAULT \
1049 | TARGET_SUBTARGET_DEFAULT \
1050 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1052 #undef TARGET_HANDLE_OPTION
1053 #define TARGET_HANDLE_OPTION ix86_handle_option
1055 #undef TARGET_RTX_COSTS
1056 #define TARGET_RTX_COSTS ix86_rtx_costs
1057 #undef TARGET_ADDRESS_COST
1058 #define TARGET_ADDRESS_COST ix86_address_cost
1060 #undef TARGET_FIXED_CONDITION_CODE_REGS
1061 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1062 #undef TARGET_CC_MODES_COMPATIBLE
1063 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1065 #undef TARGET_MACHINE_DEPENDENT_REORG
1066 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1068 #undef TARGET_BUILD_BUILTIN_VA_LIST
1069 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1071 #undef TARGET_MD_ASM_CLOBBERS
1072 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1074 #undef TARGET_PROMOTE_PROTOTYPES
1075 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1076 #undef TARGET_STRUCT_VALUE_RTX
1077 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1078 #undef TARGET_SETUP_INCOMING_VARARGS
1079 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1080 #undef TARGET_MUST_PASS_IN_STACK
1081 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1082 #undef TARGET_PASS_BY_REFERENCE
1083 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1085 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1086 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1088 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1089 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1092 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1093 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
1096 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1097 #undef TARGET_INSERT_ATTRIBUTES
1098 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1101 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
1102 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
1104 #undef TARGET_STACK_PROTECT_FAIL
1105 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
1107 #undef TARGET_FUNCTION_VALUE
1108 #define TARGET_FUNCTION_VALUE ix86_function_value
1110 struct gcc_target targetm = TARGET_INITIALIZER;
1113 /* The svr4 ABI for the i386 says that records and unions are returned
1115 #ifndef DEFAULT_PCC_STRUCT_RETURN
1116 #define DEFAULT_PCC_STRUCT_RETURN 1
1119 /* Implement TARGET_HANDLE_OPTION. */
1122 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1129 target_flags &= ~MASK_3DNOW_A;
1130 target_flags_explicit |= MASK_3DNOW_A;
1137 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1138 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1145 target_flags &= ~(MASK_SSE2 | MASK_SSE3);
1146 target_flags_explicit |= MASK_SSE2 | MASK_SSE3;
1153 target_flags &= ~MASK_SSE3;
1154 target_flags_explicit |= MASK_SSE3;
1163 /* Sometimes certain combinations of command options do not make
1164 sense on a particular target machine. You can define a macro
1165 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1166 defined, is executed once just after all the command options have
1169 Don't use this macro to turn on various extra optimizations for
1170 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1173 override_options (void)
1176 int ix86_tune_defaulted = 0;
1178 /* Comes from final.c -- no real reason to change it. */
1179 #define MAX_CODE_ALIGN 16
1183 const struct processor_costs *cost; /* Processor costs */
1184 const int target_enable; /* Target flags to enable. */
1185 const int target_disable; /* Target flags to disable. */
1186 const int align_loop; /* Default alignments. */
1187 const int align_loop_max_skip;
1188 const int align_jump;
1189 const int align_jump_max_skip;
1190 const int align_func;
1192 const processor_target_table[PROCESSOR_max] =
1194 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1195 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1196 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1197 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1198 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1199 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1200 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1201 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1202 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0}
1205 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1208 const char *const name; /* processor name or nickname. */
1209 const enum processor_type processor;
1210 const enum pta_flags
1216 PTA_PREFETCH_SSE = 16,
1222 const processor_alias_table[] =
1224 {"i386", PROCESSOR_I386, 0},
1225 {"i486", PROCESSOR_I486, 0},
1226 {"i586", PROCESSOR_PENTIUM, 0},
1227 {"pentium", PROCESSOR_PENTIUM, 0},
1228 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1229 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1230 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1231 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1232 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
1233 {"i686", PROCESSOR_PENTIUMPRO, 0},
1234 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1235 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1236 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1237 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1238 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1239 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1240 | PTA_MMX | PTA_PREFETCH_SSE},
1241 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1242 | PTA_MMX | PTA_PREFETCH_SSE},
1243 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1244 | PTA_MMX | PTA_PREFETCH_SSE},
1245 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1246 | PTA_MMX | PTA_PREFETCH_SSE},
1247 {"k6", PROCESSOR_K6, PTA_MMX},
1248 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1249 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1250 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1252 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1253 | PTA_3DNOW | PTA_3DNOW_A},
1254 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1255 | PTA_3DNOW_A | PTA_SSE},
1256 {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1257 | PTA_3DNOW_A | PTA_SSE},
1258 {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1259 | PTA_3DNOW_A | PTA_SSE},
1260 {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
1261 | PTA_SSE | PTA_SSE2 },
1262 {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1263 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1264 {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1265 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1266 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1267 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1268 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1269 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1272 int const pta_size = ARRAY_SIZE (processor_alias_table);
1274 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1275 SUBTARGET_OVERRIDE_OPTIONS;
1278 /* Set the default values for switches whose default depends on TARGET_64BIT
1279 in case they weren't overwritten by command line options. */
1282 if (flag_omit_frame_pointer == 2)
1283 flag_omit_frame_pointer = 1;
1284 if (flag_asynchronous_unwind_tables == 2)
1285 flag_asynchronous_unwind_tables = 1;
1286 if (flag_pcc_struct_return == 2)
1287 flag_pcc_struct_return = 0;
1291 if (flag_omit_frame_pointer == 2)
1292 flag_omit_frame_pointer = 0;
1293 if (flag_asynchronous_unwind_tables == 2)
1294 flag_asynchronous_unwind_tables = 0;
1295 if (flag_pcc_struct_return == 2)
1296 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1299 if (!ix86_tune_string && ix86_arch_string)
1300 ix86_tune_string = ix86_arch_string;
1301 if (!ix86_tune_string)
1303 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1304 ix86_tune_defaulted = 1;
1306 if (!ix86_arch_string)
1307 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
1309 if (ix86_cmodel_string != 0)
1311 if (!strcmp (ix86_cmodel_string, "small"))
1312 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1313 else if (!strcmp (ix86_cmodel_string, "medium"))
1314 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
1316 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string);
1317 else if (!strcmp (ix86_cmodel_string, "32"))
1318 ix86_cmodel = CM_32;
1319 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
1320 ix86_cmodel = CM_KERNEL;
1321 else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic)
1322 ix86_cmodel = CM_LARGE;
1324 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
1328 ix86_cmodel = CM_32;
1330 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1332 if (ix86_asm_string != 0)
1334 if (!strcmp (ix86_asm_string, "intel"))
1335 ix86_asm_dialect = ASM_INTEL;
1336 else if (!strcmp (ix86_asm_string, "att"))
1337 ix86_asm_dialect = ASM_ATT;
1339 error ("bad value (%s) for -masm= switch", ix86_asm_string);
1341 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
1342 error ("code model %qs not supported in the %s bit mode",
1343 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
1344 if (ix86_cmodel == CM_LARGE)
1345 sorry ("code model %<large%> not supported yet");
1346 if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
1347 sorry ("%i-bit mode not compiled in",
1348 (target_flags & MASK_64BIT) ? 64 : 32);
1350 for (i = 0; i < pta_size; i++)
1351 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
1353 ix86_arch = processor_alias_table[i].processor;
1354 /* Default cpu tuning to the architecture. */
1355 ix86_tune = ix86_arch;
1356 if (processor_alias_table[i].flags & PTA_MMX
1357 && !(target_flags_explicit & MASK_MMX))
1358 target_flags |= MASK_MMX;
1359 if (processor_alias_table[i].flags & PTA_3DNOW
1360 && !(target_flags_explicit & MASK_3DNOW))
1361 target_flags |= MASK_3DNOW;
1362 if (processor_alias_table[i].flags & PTA_3DNOW_A
1363 && !(target_flags_explicit & MASK_3DNOW_A))
1364 target_flags |= MASK_3DNOW_A;
1365 if (processor_alias_table[i].flags & PTA_SSE
1366 && !(target_flags_explicit & MASK_SSE))
1367 target_flags |= MASK_SSE;
1368 if (processor_alias_table[i].flags & PTA_SSE2
1369 && !(target_flags_explicit & MASK_SSE2))
1370 target_flags |= MASK_SSE2;
1371 if (processor_alias_table[i].flags & PTA_SSE3
1372 && !(target_flags_explicit & MASK_SSE3))
1373 target_flags |= MASK_SSE3;
1374 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1375 x86_prefetch_sse = true;
1376 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1377 error ("CPU you selected does not support x86-64 "
1383 error ("bad value (%s) for -march= switch", ix86_arch_string);
1385 for (i = 0; i < pta_size; i++)
1386 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
1388 ix86_tune = processor_alias_table[i].processor;
1389 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1391 if (ix86_tune_defaulted)
1393 ix86_tune_string = "x86-64";
1394 for (i = 0; i < pta_size; i++)
1395 if (! strcmp (ix86_tune_string,
1396 processor_alias_table[i].name))
1398 ix86_tune = processor_alias_table[i].processor;
1401 error ("CPU you selected does not support x86-64 "
1404 /* Intel CPUs have always interpreted SSE prefetch instructions as
1405 NOPs; so, we can enable SSE prefetch instructions even when
1406 -mtune (rather than -march) points us to a processor that has them.
1407 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
1408 higher processors. */
1409 if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
1410 x86_prefetch_sse = true;
1414 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1417 ix86_cost = &size_cost;
1419 ix86_cost = processor_target_table[ix86_tune].cost;
1420 target_flags |= processor_target_table[ix86_tune].target_enable;
1421 target_flags &= ~processor_target_table[ix86_tune].target_disable;
1423 /* Arrange to set up i386_stack_locals for all functions. */
1424 init_machine_status = ix86_init_machine_status;
1426 /* Validate -mregparm= value. */
1427 if (ix86_regparm_string)
1429 i = atoi (ix86_regparm_string);
1430 if (i < 0 || i > REGPARM_MAX)
1431 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
1437 ix86_regparm = REGPARM_MAX;
1439 /* If the user has provided any of the -malign-* options,
1440 warn and use that value only if -falign-* is not set.
1441 Remove this code in GCC 3.2 or later. */
1442 if (ix86_align_loops_string)
1444 warning (0, "-malign-loops is obsolete, use -falign-loops");
1445 if (align_loops == 0)
1447 i = atoi (ix86_align_loops_string);
1448 if (i < 0 || i > MAX_CODE_ALIGN)
1449 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1451 align_loops = 1 << i;
1455 if (ix86_align_jumps_string)
1457 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
1458 if (align_jumps == 0)
1460 i = atoi (ix86_align_jumps_string);
1461 if (i < 0 || i > MAX_CODE_ALIGN)
1462 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1464 align_jumps = 1 << i;
1468 if (ix86_align_funcs_string)
1470 warning (0, "-malign-functions is obsolete, use -falign-functions");
1471 if (align_functions == 0)
1473 i = atoi (ix86_align_funcs_string);
1474 if (i < 0 || i > MAX_CODE_ALIGN)
1475 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1477 align_functions = 1 << i;
1481 /* Default align_* from the processor table. */
1482 if (align_loops == 0)
1484 align_loops = processor_target_table[ix86_tune].align_loop;
1485 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
1487 if (align_jumps == 0)
1489 align_jumps = processor_target_table[ix86_tune].align_jump;
1490 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
1492 if (align_functions == 0)
1494 align_functions = processor_target_table[ix86_tune].align_func;
1497 /* Validate -mpreferred-stack-boundary= value, or provide default.
1498 The default of 128 bits is for Pentium III's SSE __m128, but we
1499 don't want additional code to keep the stack aligned when
1500 optimizing for code size. */
1501 ix86_preferred_stack_boundary = (optimize_size
1502 ? TARGET_64BIT ? 128 : 32
1504 if (ix86_preferred_stack_boundary_string)
1506 i = atoi (ix86_preferred_stack_boundary_string);
1507 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
1508 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
1509 TARGET_64BIT ? 4 : 2);
1511 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
1514 /* Validate -mbranch-cost= value, or provide default. */
1515 ix86_branch_cost = processor_target_table[ix86_tune].cost->branch_cost;
1516 if (ix86_branch_cost_string)
1518 i = atoi (ix86_branch_cost_string);
1520 error ("-mbranch-cost=%d is not between 0 and 5", i);
1522 ix86_branch_cost = i;
1524 if (ix86_section_threshold_string)
1526 i = atoi (ix86_section_threshold_string);
1528 error ("-mlarge-data-threshold=%d is negative", i);
1530 ix86_section_threshold = i;
1533 if (ix86_tls_dialect_string)
1535 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
1536 ix86_tls_dialect = TLS_DIALECT_GNU;
1537 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
1538 ix86_tls_dialect = TLS_DIALECT_SUN;
1540 error ("bad value (%s) for -mtls-dialect= switch",
1541 ix86_tls_dialect_string);
1544 /* Keep nonleaf frame pointers. */
1545 if (flag_omit_frame_pointer)
1546 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
1547 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
1548 flag_omit_frame_pointer = 1;
1550 /* If we're doing fast math, we don't care about comparison order
1551 wrt NaNs. This lets us use a shorter comparison sequence. */
1552 if (flag_unsafe_math_optimizations)
1553 target_flags &= ~MASK_IEEE_FP;
1555 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
1556 since the insns won't need emulation. */
1557 if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
1558 target_flags &= ~MASK_NO_FANCY_MATH_387;
1560 /* Likewise, if the target doesn't have a 387, or we've specified
1561 software floating point, don't use 387 inline intrinsics. */
1563 target_flags |= MASK_NO_FANCY_MATH_387;
1565 /* Turn on SSE2 builtins for -msse3. */
1567 target_flags |= MASK_SSE2;
1569 /* Turn on SSE builtins for -msse2. */
1571 target_flags |= MASK_SSE;
1573 /* Turn on MMX builtins for -msse. */
1576 target_flags |= MASK_MMX & ~target_flags_explicit;
1577 x86_prefetch_sse = true;
1580 /* Turn on MMX builtins for 3Dnow. */
1582 target_flags |= MASK_MMX;
1586 if (TARGET_ALIGN_DOUBLE)
1587 error ("-malign-double makes no sense in the 64bit mode");
1589 error ("-mrtd calling convention not supported in the 64bit mode");
1591 /* Enable by default the SSE and MMX builtins. Do allow the user to
1592 explicitly disable any of these. In particular, disabling SSE and
1593 MMX for kernel code is extremely useful. */
1595 |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE)
1596 & ~target_flags_explicit);
1600 /* i386 ABI does not specify red zone. It still makes sense to use it
1601 when programmer takes care to stack from being destroyed. */
1602 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
1603 target_flags |= MASK_NO_RED_ZONE;
1606 /* Accept -msseregparm only if at least SSE support is enabled. */
1607 if (TARGET_SSEREGPARM
1609 error ("-msseregparm used without SSE enabled");
1611 ix86_fpmath = TARGET_FPMATH_DEFAULT;
1613 if (ix86_fpmath_string != 0)
1615 if (! strcmp (ix86_fpmath_string, "387"))
1616 ix86_fpmath = FPMATH_387;
1617 else if (! strcmp (ix86_fpmath_string, "sse"))
1621 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1622 ix86_fpmath = FPMATH_387;
1625 ix86_fpmath = FPMATH_SSE;
1627 else if (! strcmp (ix86_fpmath_string, "387,sse")
1628 || ! strcmp (ix86_fpmath_string, "sse,387"))
1632 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1633 ix86_fpmath = FPMATH_387;
1635 else if (!TARGET_80387)
1637 warning (0, "387 instruction set disabled, using SSE arithmetics");
1638 ix86_fpmath = FPMATH_SSE;
1641 ix86_fpmath = FPMATH_SSE | FPMATH_387;
1644 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
1647 /* If the i387 is disabled, then do not return values in it. */
1649 target_flags &= ~MASK_FLOAT_RETURNS;
1651 if ((x86_accumulate_outgoing_args & TUNEMASK)
1652 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
1654 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
1656 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
1659 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
1660 p = strchr (internal_label_prefix, 'X');
1661 internal_label_prefix_len = p - internal_label_prefix;
1665 /* When scheduling description is not available, disable scheduler pass
1666 so it won't slow down the compilation and make x87 code slower. */
1667 if (!TARGET_SCHEDULE)
1668 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
1671 /* switch to the appropriate section for output of DECL.
1672 DECL is either a `VAR_DECL' node or a constant of some sort.
1673 RELOC indicates whether forming the initial value of DECL requires
1674 link-time relocations. */
1677 x86_64_elf_select_section (tree decl, int reloc,
1678 unsigned HOST_WIDE_INT align)
1680 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1681 && ix86_in_large_data_p (decl))
1683 const char *sname = NULL;
1684 switch (categorize_decl_for_section (decl, reloc, flag_pic))
1689 case SECCAT_DATA_REL:
1690 sname = ".ldata.rel";
1692 case SECCAT_DATA_REL_LOCAL:
1693 sname = ".ldata.rel.local";
1695 case SECCAT_DATA_REL_RO:
1696 sname = ".ldata.rel.ro";
1698 case SECCAT_DATA_REL_RO_LOCAL:
1699 sname = ".ldata.rel.ro.local";
1705 case SECCAT_RODATA_MERGE_STR:
1706 case SECCAT_RODATA_MERGE_STR_INIT:
1707 case SECCAT_RODATA_MERGE_CONST:
1710 case SECCAT_SRODATA:
1717 /* We don't split these for medium model. Place them into
1718 default sections and hope for best. */
1723 named_section (decl, sname, reloc);
1727 default_elf_select_section (decl, reloc, align);
1730 /* Build up a unique section name, expressed as a
1731 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
1732 RELOC indicates whether the initial value of EXP requires
1733 link-time relocations. */
1736 x86_64_elf_unique_section (tree decl, int reloc)
1738 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1739 && ix86_in_large_data_p (decl))
1741 const char *prefix = NULL;
1742 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
1743 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
1745 switch (categorize_decl_for_section (decl, reloc, flag_pic))
1748 case SECCAT_DATA_REL:
1749 case SECCAT_DATA_REL_LOCAL:
1750 case SECCAT_DATA_REL_RO:
1751 case SECCAT_DATA_REL_RO_LOCAL:
1752 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
1755 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
1758 case SECCAT_RODATA_MERGE_STR:
1759 case SECCAT_RODATA_MERGE_STR_INIT:
1760 case SECCAT_RODATA_MERGE_CONST:
1761 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
1763 case SECCAT_SRODATA:
1770 /* We don't split these for medium model. Place them into
1771 default sections and hope for best. */
1779 plen = strlen (prefix);
1781 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
1782 name = targetm.strip_name_encoding (name);
1783 nlen = strlen (name);
1785 string = alloca (nlen + plen + 1);
1786 memcpy (string, prefix, plen);
1787 memcpy (string + plen, name, nlen + 1);
1789 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
1793 default_unique_section (decl, reloc);
1796 #ifdef COMMON_ASM_OP
1797 /* This says how to output assembler code to declare an
1798 uninitialized external linkage data object.
1800 For medium model x86-64 we need to use .largecomm opcode for
1803 x86_elf_aligned_common (FILE *file,
1804 const char *name, unsigned HOST_WIDE_INT size,
1807 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1808 && size > (unsigned int)ix86_section_threshold)
1809 fprintf (file, ".largecomm\t");
1811 fprintf (file, "%s", COMMON_ASM_OP);
1812 assemble_name (file, name);
1813 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
1814 size, align / BITS_PER_UNIT);
1817 /* Utility function for targets to use in implementing
1818 ASM_OUTPUT_ALIGNED_BSS. */
1821 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
1822 const char *name, unsigned HOST_WIDE_INT size,
1825 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1826 && size > (unsigned int)ix86_section_threshold)
1827 named_section (decl, ".lbss", 0);
1830 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
1831 #ifdef ASM_DECLARE_OBJECT_NAME
1832 last_assemble_variable_decl = decl;
1833 ASM_DECLARE_OBJECT_NAME (file, name, decl);
1835 /* Standard thing is just output label for the object. */
1836 ASM_OUTPUT_LABEL (file, name);
1837 #endif /* ASM_DECLARE_OBJECT_NAME */
1838 ASM_OUTPUT_SKIP (file, size ? size : 1);
1843 optimization_options (int level, int size ATTRIBUTE_UNUSED)
1845 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
1846 make the problem with not enough registers even worse. */
1847 #ifdef INSN_SCHEDULING
1849 flag_schedule_insns = 0;
1853 /* The Darwin libraries never set errno, so we might as well
1854 avoid calling them when that's the only reason we would. */
1855 flag_errno_math = 0;
1857 /* The default values of these switches depend on the TARGET_64BIT
1858 that is not known at this moment. Mark these values with 2 and
1859 let user the to override these. In case there is no command line option
1860 specifying them, we will set the defaults in override_options. */
1862 flag_omit_frame_pointer = 2;
1863 flag_pcc_struct_return = 2;
1864 flag_asynchronous_unwind_tables = 2;
1865 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1866 SUBTARGET_OPTIMIZATION_OPTIONS;
1870 /* Table of valid machine attributes. */
1871 const struct attribute_spec ix86_attribute_table[] =
1873 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1874 /* Stdcall attribute says callee is responsible for popping arguments
1875 if they are not variable. */
1876 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1877 /* Fastcall attribute says callee is responsible for popping arguments
1878 if they are not variable. */
1879 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1880 /* Cdecl attribute says the callee is a normal C declaration */
1881 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1882 /* Regparm attribute specifies how many integer arguments are to be
1883 passed in registers. */
1884 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
1885 /* Sseregparm attribute says we are using x86_64 calling conventions
1886 for FP arguments. */
1887 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1888 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1889 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
1890 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
1891 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
1893 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
1894 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
1895 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1896 SUBTARGET_ATTRIBUTE_TABLE,
1898 { NULL, 0, 0, false, false, false, NULL }
1901 /* Decide whether we can make a sibling call to a function. DECL is the
1902 declaration of the function being targeted by the call and EXP is the
1903 CALL_EXPR representing the call. */
1906 ix86_function_ok_for_sibcall (tree decl, tree exp)
1911 /* If we are generating position-independent code, we cannot sibcall
1912 optimize any indirect call, or a direct call to a global function,
1913 as the PLT requires %ebx be live. */
1914 if (!TARGET_64BIT && flag_pic && (!decl || TREE_PUBLIC (decl)))
1921 func = TREE_TYPE (TREE_OPERAND (exp, 0));
1922 if (POINTER_TYPE_P (func))
1923 func = TREE_TYPE (func);
1926 /* Check that the return value locations are the same. Like
1927 if we are returning floats on the 80387 register stack, we cannot
1928 make a sibcall from a function that doesn't return a float to a
1929 function that does or, conversely, from a function that does return
1930 a float to a function that doesn't; the necessary stack adjustment
1931 would not be executed. This is also the place we notice
1932 differences in the return value ABI. Note that it is ok for one
1933 of the functions to have void return type as long as the return
1934 value of the other is passed in a register. */
1935 a = ix86_function_value (TREE_TYPE (exp), func, false);
1936 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
1938 if (STACK_REG_P (a) || STACK_REG_P (b))
1940 if (!rtx_equal_p (a, b))
1943 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
1945 else if (!rtx_equal_p (a, b))
1948 /* If this call is indirect, we'll need to be able to use a call-clobbered
1949 register for the address of the target function. Make sure that all
1950 such registers are not used for passing parameters. */
1951 if (!decl && !TARGET_64BIT)
1955 /* We're looking at the CALL_EXPR, we need the type of the function. */
1956 type = TREE_OPERAND (exp, 0); /* pointer expression */
1957 type = TREE_TYPE (type); /* pointer type */
1958 type = TREE_TYPE (type); /* function type */
1960 if (ix86_function_regparm (type, NULL) >= 3)
1962 /* ??? Need to count the actual number of registers to be used,
1963 not the possible number of registers. Fix later. */
1968 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1969 /* Dllimport'd functions are also called indirectly. */
1970 if (decl && lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl))
1971 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
1975 /* Otherwise okay. That also includes certain types of indirect calls. */
1979 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
1980 calling convention attributes;
1981 arguments as in struct attribute_spec.handler. */
1984 ix86_handle_cconv_attribute (tree *node, tree name,
1986 int flags ATTRIBUTE_UNUSED,
1989 if (TREE_CODE (*node) != FUNCTION_TYPE
1990 && TREE_CODE (*node) != METHOD_TYPE
1991 && TREE_CODE (*node) != FIELD_DECL
1992 && TREE_CODE (*node) != TYPE_DECL)
1994 warning (OPT_Wattributes, "%qs attribute only applies to functions",
1995 IDENTIFIER_POINTER (name));
1996 *no_add_attrs = true;
2000 /* Can combine regparm with all attributes but fastcall. */
2001 if (is_attribute_p ("regparm", name))
2005 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2007 error ("fastcall and regparm attributes are not compatible");
2010 cst = TREE_VALUE (args);
2011 if (TREE_CODE (cst) != INTEGER_CST)
2013 warning (OPT_Wattributes,
2014 "%qs attribute requires an integer constant argument",
2015 IDENTIFIER_POINTER (name));
2016 *no_add_attrs = true;
2018 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2020 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2021 IDENTIFIER_POINTER (name), REGPARM_MAX);
2022 *no_add_attrs = true;
2030 warning (OPT_Wattributes, "%qs attribute ignored",
2031 IDENTIFIER_POINTER (name));
2032 *no_add_attrs = true;
2036 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2037 if (is_attribute_p ("fastcall", name))
2039 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2041 error ("fastcall and cdecl attributes are not compatible");
2043 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2045 error ("fastcall and stdcall attributes are not compatible");
2047 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2049 error ("fastcall and regparm attributes are not compatible");
2053 /* Can combine stdcall with fastcall (redundant), regparm and
2055 else if (is_attribute_p ("stdcall", name))
2057 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2059 error ("stdcall and cdecl attributes are not compatible");
2061 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2063 error ("stdcall and fastcall attributes are not compatible");
2067 /* Can combine cdecl with regparm and sseregparm. */
2068 else if (is_attribute_p ("cdecl", name))
2070 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2072 error ("stdcall and cdecl attributes are not compatible");
2074 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2076 error ("fastcall and cdecl attributes are not compatible");
2080 /* Can combine sseregparm with all attributes. */
2085 /* Return 0 if the attributes for two types are incompatible, 1 if they
2086 are compatible, and 2 if they are nearly compatible (which causes a
2087 warning to be generated). */
2090 ix86_comp_type_attributes (tree type1, tree type2)
2092 /* Check for mismatch of non-default calling convention. */
2093 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2095 if (TREE_CODE (type1) != FUNCTION_TYPE)
2098 /* Check for mismatched fastcall/regparm types. */
2099 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2100 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2101 || (ix86_function_regparm (type1, NULL)
2102 != ix86_function_regparm (type2, NULL)))
2105 /* Check for mismatched sseregparm types. */
2106 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2107 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2110 /* Check for mismatched return types (cdecl vs stdcall). */
2111 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2112 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2118 /* Return the regparm value for a function with the indicated TYPE and DECL.
2119 DECL may be NULL when calling function indirectly
2120 or considering a libcall. */
2123 ix86_function_regparm (tree type, tree decl)
2126 int regparm = ix86_regparm;
2127 bool user_convention = false;
2131 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
2134 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
2135 user_convention = true;
2138 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
2141 user_convention = true;
2144 /* Use register calling convention for local functions when possible. */
2145 if (!TARGET_64BIT && !user_convention && decl
2146 && flag_unit_at_a_time && !profile_flag)
2148 struct cgraph_local_info *i = cgraph_local_info (decl);
2151 int local_regparm, globals = 0, regno;
2153 /* Make sure no regparm register is taken by a global register
2155 for (local_regparm = 0; local_regparm < 3; local_regparm++)
2156 if (global_regs[local_regparm])
2158 /* We can't use regparm(3) for nested functions as these use
2159 static chain pointer in third argument. */
2160 if (local_regparm == 3
2161 && decl_function_context (decl)
2162 && !DECL_NO_STATIC_CHAIN (decl))
2164 /* Each global register variable increases register preassure,
2165 so the more global reg vars there are, the smaller regparm
2166 optimization use, unless requested by the user explicitly. */
2167 for (regno = 0; regno < 6; regno++)
2168 if (global_regs[regno])
2171 = globals < local_regparm ? local_regparm - globals : 0;
2173 if (local_regparm > regparm)
2174 regparm = local_regparm;
2181 /* Return 1 or 2, if we can pass up to 8 SFmode (1) and DFmode (2) arguments
2182 in SSE registers for a function with the indicated TYPE and DECL.
2183 DECL may be NULL when calling function indirectly
2184 or considering a libcall. Otherwise return 0. */
2187 ix86_function_sseregparm (tree type, tree decl)
2189 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2190 by the sseregparm attribute. */
2191 if (TARGET_SSEREGPARM
2193 && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
2198 error ("Calling %qD with attribute sseregparm without "
2199 "SSE/SSE2 enabled", decl);
2201 error ("Calling %qT with attribute sseregparm without "
2202 "SSE/SSE2 enabled", type);
2209 /* For local functions, pass SFmode (and DFmode for SSE2) arguments
2210 in SSE registers even for 32-bit mode and not just 3, but up to
2211 8 SSE arguments in registers. */
2212 if (!TARGET_64BIT && decl
2213 && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
2215 struct cgraph_local_info *i = cgraph_local_info (decl);
2217 return TARGET_SSE2 ? 2 : 1;
2223 /* Return true if EAX is live at the start of the function. Used by
2224 ix86_expand_prologue to determine if we need special help before
2225 calling allocate_stack_worker. */
2228 ix86_eax_live_at_start_p (void)
2230 /* Cheat. Don't bother working forward from ix86_function_regparm
2231 to the function type to whether an actual argument is located in
2232 eax. Instead just look at cfg info, which is still close enough
2233 to correct at this point. This gives false positives for broken
2234 functions that might use uninitialized data that happens to be
2235 allocated in eax, but who cares? */
2236 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end, 0);
2239 /* Value is the number of bytes of arguments automatically
2240 popped when returning from a subroutine call.
2241 FUNDECL is the declaration node of the function (as a tree),
2242 FUNTYPE is the data type of the function (as a tree),
2243 or for a library call it is an identifier node for the subroutine name.
2244 SIZE is the number of bytes of arguments passed on the stack.
2246 On the 80386, the RTD insn may be used to pop them if the number
2247 of args is fixed, but if the number is variable then the caller
2248 must pop them all. RTD can't be used for library calls now
2249 because the library is compiled with the Unix compiler.
2250 Use of RTD is a selectable option, since it is incompatible with
2251 standard Unix calling sequences. If the option is not selected,
2252 the caller must always pop the args.
2254 The attribute stdcall is equivalent to RTD on a per module basis. */
2257 ix86_return_pops_args (tree fundecl, tree funtype, int size)
2259 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
2261 /* Cdecl functions override -mrtd, and never pop the stack. */
2262 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
2264 /* Stdcall and fastcall functions will pop the stack if not
2266 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
2267 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
2271 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
2272 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
2273 == void_type_node)))
2277 /* Lose any fake structure return argument if it is passed on the stack. */
2278 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
2280 && !KEEP_AGGREGATE_RETURN_POINTER)
2282 int nregs = ix86_function_regparm (funtype, fundecl);
2285 return GET_MODE_SIZE (Pmode);
2291 /* Argument support functions. */
2293 /* Return true when register may be used to pass function parameters. */
2295 ix86_function_arg_regno_p (int regno)
2299 return (regno < REGPARM_MAX
2300 || (TARGET_MMX && MMX_REGNO_P (regno)
2301 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
2302 || (TARGET_SSE && SSE_REGNO_P (regno)
2303 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
2305 if (TARGET_SSE && SSE_REGNO_P (regno)
2306 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
2308 /* RAX is used as hidden argument to va_arg functions. */
2311 for (i = 0; i < REGPARM_MAX; i++)
2312 if (regno == x86_64_int_parameter_registers[i])
2317 /* Return if we do not know how to pass TYPE solely in registers. */
2320 ix86_must_pass_in_stack (enum machine_mode mode, tree type)
2322 if (must_pass_in_stack_var_size_or_pad (mode, type))
2325 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
2326 The layout_type routine is crafty and tries to trick us into passing
2327 currently unsupported vector types on the stack by using TImode. */
2328 return (!TARGET_64BIT && mode == TImode
2329 && type && TREE_CODE (type) != VECTOR_TYPE);
2332 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2333 for a call to a function whose data type is FNTYPE.
2334 For a library call, FNTYPE is 0. */
2337 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
2338 tree fntype, /* tree ptr for function decl */
2339 rtx libname, /* SYMBOL_REF of library name or 0 */
2342 static CUMULATIVE_ARGS zero_cum;
2343 tree param, next_param;
2345 if (TARGET_DEBUG_ARG)
2347 fprintf (stderr, "\ninit_cumulative_args (");
2349 fprintf (stderr, "fntype code = %s, ret code = %s",
2350 tree_code_name[(int) TREE_CODE (fntype)],
2351 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
2353 fprintf (stderr, "no fntype");
2356 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
2361 /* Set up the number of registers to use for passing arguments. */
2362 cum->nregs = ix86_regparm;
2364 cum->sse_nregs = SSE_REGPARM_MAX;
2366 cum->mmx_nregs = MMX_REGPARM_MAX;
2367 cum->warn_sse = true;
2368 cum->warn_mmx = true;
2369 cum->maybe_vaarg = false;
2371 /* Use ecx and edx registers if function has fastcall attribute,
2372 else look for regparm information. */
2373 if (fntype && !TARGET_64BIT)
2375 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
2381 cum->nregs = ix86_function_regparm (fntype, fndecl);
2384 /* Set up the number of SSE registers used for passing SFmode
2385 and DFmode arguments. Warn for mismatching ABI. */
2386 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
2388 /* Determine if this function has variable arguments. This is
2389 indicated by the last argument being 'void_type_mode' if there
2390 are no variable arguments. If there are variable arguments, then
2391 we won't pass anything in registers in 32-bit mode. */
2393 if (cum->nregs || cum->mmx_nregs || cum->sse_nregs)
2395 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2396 param != 0; param = next_param)
2398 next_param = TREE_CHAIN (param);
2399 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
2409 cum->float_in_sse = 0;
2411 cum->maybe_vaarg = true;
2415 if ((!fntype && !libname)
2416 || (fntype && !TYPE_ARG_TYPES (fntype)))
2417 cum->maybe_vaarg = true;
2419 if (TARGET_DEBUG_ARG)
2420 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
2425 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
2426 But in the case of vector types, it is some vector mode.
2428 When we have only some of our vector isa extensions enabled, then there
2429 are some modes for which vector_mode_supported_p is false. For these
2430 modes, the generic vector support in gcc will choose some non-vector mode
2431 in order to implement the type. By computing the natural mode, we'll
2432 select the proper ABI location for the operand and not depend on whatever
2433 the middle-end decides to do with these vector types. */
2435 static enum machine_mode
2436 type_natural_mode (tree type)
2438 enum machine_mode mode = TYPE_MODE (type);
2440 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
2442 HOST_WIDE_INT size = int_size_in_bytes (type);
2443 if ((size == 8 || size == 16)
2444 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
2445 && TYPE_VECTOR_SUBPARTS (type) > 1)
2447 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
2449 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
2450 mode = MIN_MODE_VECTOR_FLOAT;
2452 mode = MIN_MODE_VECTOR_INT;
2454 /* Get the mode which has this inner mode and number of units. */
2455 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
2456 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
2457 && GET_MODE_INNER (mode) == innermode)
2467 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
2468 this may not agree with the mode that the type system has chosen for the
2469 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
2470 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
2473 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
2478 if (orig_mode != BLKmode)
2479 tmp = gen_rtx_REG (orig_mode, regno);
2482 tmp = gen_rtx_REG (mode, regno);
2483 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
2484 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
2490 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
2491 of this code is to classify each 8bytes of incoming argument by the register
2492 class and assign registers accordingly. */
2494 /* Return the union class of CLASS1 and CLASS2.
2495 See the x86-64 PS ABI for details. */
2497 static enum x86_64_reg_class
2498 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
2500 /* Rule #1: If both classes are equal, this is the resulting class. */
2501 if (class1 == class2)
2504 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
2506 if (class1 == X86_64_NO_CLASS)
2508 if (class2 == X86_64_NO_CLASS)
2511 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
2512 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
2513 return X86_64_MEMORY_CLASS;
2515 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
2516 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
2517 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
2518 return X86_64_INTEGERSI_CLASS;
2519 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
2520 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
2521 return X86_64_INTEGER_CLASS;
2523 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
2525 if (class1 == X86_64_X87_CLASS
2526 || class1 == X86_64_X87UP_CLASS
2527 || class1 == X86_64_COMPLEX_X87_CLASS
2528 || class2 == X86_64_X87_CLASS
2529 || class2 == X86_64_X87UP_CLASS
2530 || class2 == X86_64_COMPLEX_X87_CLASS)
2531 return X86_64_MEMORY_CLASS;
2533 /* Rule #6: Otherwise class SSE is used. */
2534 return X86_64_SSE_CLASS;
2537 /* Classify the argument of type TYPE and mode MODE.
2538 CLASSES will be filled by the register class used to pass each word
2539 of the operand. The number of words is returned. In case the parameter
2540 should be passed in memory, 0 is returned. As a special case for zero
2541 sized containers, classes[0] will be NO_CLASS and 1 is returned.
2543 BIT_OFFSET is used internally for handling records and specifies offset
2544 of the offset in bits modulo 256 to avoid overflow cases.
2546 See the x86-64 PS ABI for details.
2550 classify_argument (enum machine_mode mode, tree type,
2551 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
2553 HOST_WIDE_INT bytes =
2554 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
2555 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2557 /* Variable sized entities are always passed/returned in memory. */
2561 if (mode != VOIDmode
2562 && targetm.calls.must_pass_in_stack (mode, type))
2565 if (type && AGGREGATE_TYPE_P (type))
2569 enum x86_64_reg_class subclasses[MAX_CLASSES];
2571 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
2575 for (i = 0; i < words; i++)
2576 classes[i] = X86_64_NO_CLASS;
2578 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
2579 signalize memory class, so handle it as special case. */
2582 classes[0] = X86_64_NO_CLASS;
2586 /* Classify each field of record and merge classes. */
2587 switch (TREE_CODE (type))
2590 /* For classes first merge in the field of the subclasses. */
2591 if (TYPE_BINFO (type))
2593 tree binfo, base_binfo;
2596 for (binfo = TYPE_BINFO (type), basenum = 0;
2597 BINFO_BASE_ITERATE (binfo, basenum, base_binfo); basenum++)
2600 int offset = tree_low_cst (BINFO_OFFSET (base_binfo), 0) * 8;
2601 tree type = BINFO_TYPE (base_binfo);
2603 num = classify_argument (TYPE_MODE (type),
2605 (offset + bit_offset) % 256);
2608 for (i = 0; i < num; i++)
2610 int pos = (offset + (bit_offset % 64)) / 8 / 8;
2612 merge_classes (subclasses[i], classes[i + pos]);
2616 /* And now merge the fields of structure. */
2617 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2619 if (TREE_CODE (field) == FIELD_DECL)
2623 /* Bitfields are always classified as integer. Handle them
2624 early, since later code would consider them to be
2625 misaligned integers. */
2626 if (DECL_BIT_FIELD (field))
2628 for (i = int_bit_position (field) / 8 / 8;
2629 i < (int_bit_position (field)
2630 + tree_low_cst (DECL_SIZE (field), 0)
2633 merge_classes (X86_64_INTEGER_CLASS,
2638 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
2639 TREE_TYPE (field), subclasses,
2640 (int_bit_position (field)
2641 + bit_offset) % 256);
2644 for (i = 0; i < num; i++)
2647 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
2649 merge_classes (subclasses[i], classes[i + pos]);
2657 /* Arrays are handled as small records. */
2660 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
2661 TREE_TYPE (type), subclasses, bit_offset);
2665 /* The partial classes are now full classes. */
2666 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
2667 subclasses[0] = X86_64_SSE_CLASS;
2668 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
2669 subclasses[0] = X86_64_INTEGER_CLASS;
2671 for (i = 0; i < words; i++)
2672 classes[i] = subclasses[i % num];
2677 case QUAL_UNION_TYPE:
2678 /* Unions are similar to RECORD_TYPE but offset is always 0.
2681 /* Unions are not derived. */
2682 gcc_assert (!TYPE_BINFO (type)
2683 || !BINFO_N_BASE_BINFOS (TYPE_BINFO (type)));
2684 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2686 if (TREE_CODE (field) == FIELD_DECL)
2689 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
2690 TREE_TYPE (field), subclasses,
2694 for (i = 0; i < num; i++)
2695 classes[i] = merge_classes (subclasses[i], classes[i]);
2704 /* Final merger cleanup. */
2705 for (i = 0; i < words; i++)
2707 /* If one class is MEMORY, everything should be passed in
2709 if (classes[i] == X86_64_MEMORY_CLASS)
2712 /* The X86_64_SSEUP_CLASS should be always preceded by
2713 X86_64_SSE_CLASS. */
2714 if (classes[i] == X86_64_SSEUP_CLASS
2715 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
2716 classes[i] = X86_64_SSE_CLASS;
2718 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
2719 if (classes[i] == X86_64_X87UP_CLASS
2720 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
2721 classes[i] = X86_64_SSE_CLASS;
2726 /* Compute alignment needed. We align all types to natural boundaries with
2727 exception of XFmode that is aligned to 64bits. */
2728 if (mode != VOIDmode && mode != BLKmode)
2730 int mode_alignment = GET_MODE_BITSIZE (mode);
2733 mode_alignment = 128;
2734 else if (mode == XCmode)
2735 mode_alignment = 256;
2736 if (COMPLEX_MODE_P (mode))
2737 mode_alignment /= 2;
2738 /* Misaligned fields are always returned in memory. */
2739 if (bit_offset % mode_alignment)
2743 /* for V1xx modes, just use the base mode */
2744 if (VECTOR_MODE_P (mode)
2745 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
2746 mode = GET_MODE_INNER (mode);
2748 /* Classification of atomic types. */
2758 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
2759 classes[0] = X86_64_INTEGERSI_CLASS;
2761 classes[0] = X86_64_INTEGER_CLASS;
2765 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
2770 if (!(bit_offset % 64))
2771 classes[0] = X86_64_SSESF_CLASS;
2773 classes[0] = X86_64_SSE_CLASS;
2776 classes[0] = X86_64_SSEDF_CLASS;
2779 classes[0] = X86_64_X87_CLASS;
2780 classes[1] = X86_64_X87UP_CLASS;
2783 classes[0] = X86_64_SSE_CLASS;
2784 classes[1] = X86_64_SSEUP_CLASS;
2787 classes[0] = X86_64_SSE_CLASS;
2790 classes[0] = X86_64_SSEDF_CLASS;
2791 classes[1] = X86_64_SSEDF_CLASS;
2794 classes[0] = X86_64_COMPLEX_X87_CLASS;
2797 /* This modes is larger than 16 bytes. */
2805 classes[0] = X86_64_SSE_CLASS;
2806 classes[1] = X86_64_SSEUP_CLASS;
2812 classes[0] = X86_64_SSE_CLASS;
2818 gcc_assert (VECTOR_MODE_P (mode));
2823 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
2825 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
2826 classes[0] = X86_64_INTEGERSI_CLASS;
2828 classes[0] = X86_64_INTEGER_CLASS;
2829 classes[1] = X86_64_INTEGER_CLASS;
2830 return 1 + (bytes > 8);
2834 /* Examine the argument and return set number of register required in each
2835 class. Return 0 iff parameter should be passed in memory. */
2837 examine_argument (enum machine_mode mode, tree type, int in_return,
2838 int *int_nregs, int *sse_nregs)
2840 enum x86_64_reg_class class[MAX_CLASSES];
2841 int n = classify_argument (mode, type, class, 0);
2847 for (n--; n >= 0; n--)
2850 case X86_64_INTEGER_CLASS:
2851 case X86_64_INTEGERSI_CLASS:
2854 case X86_64_SSE_CLASS:
2855 case X86_64_SSESF_CLASS:
2856 case X86_64_SSEDF_CLASS:
2859 case X86_64_NO_CLASS:
2860 case X86_64_SSEUP_CLASS:
2862 case X86_64_X87_CLASS:
2863 case X86_64_X87UP_CLASS:
2867 case X86_64_COMPLEX_X87_CLASS:
2868 return in_return ? 2 : 0;
2869 case X86_64_MEMORY_CLASS:
2875 /* Construct container for the argument used by GCC interface. See
2876 FUNCTION_ARG for the detailed description. */
2879 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
2880 tree type, int in_return, int nintregs, int nsseregs,
2881 const int *intreg, int sse_regno)
2883 enum machine_mode tmpmode;
2885 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
2886 enum x86_64_reg_class class[MAX_CLASSES];
2890 int needed_sseregs, needed_intregs;
2891 rtx exp[MAX_CLASSES];
2894 n = classify_argument (mode, type, class, 0);
2895 if (TARGET_DEBUG_ARG)
2898 fprintf (stderr, "Memory class\n");
2901 fprintf (stderr, "Classes:");
2902 for (i = 0; i < n; i++)
2904 fprintf (stderr, " %s", x86_64_reg_class_name[class[i]]);
2906 fprintf (stderr, "\n");
2911 if (!examine_argument (mode, type, in_return, &needed_intregs,
2914 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
2917 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
2918 some less clueful developer tries to use floating-point anyway. */
2919 if (needed_sseregs && !TARGET_SSE)
2921 static bool issued_error;
2924 issued_error = true;
2926 error ("SSE register return with SSE disabled");
2928 error ("SSE register argument with SSE disabled");
2933 /* First construct simple cases. Avoid SCmode, since we want to use
2934 single register to pass this type. */
2935 if (n == 1 && mode != SCmode)
2938 case X86_64_INTEGER_CLASS:
2939 case X86_64_INTEGERSI_CLASS:
2940 return gen_rtx_REG (mode, intreg[0]);
2941 case X86_64_SSE_CLASS:
2942 case X86_64_SSESF_CLASS:
2943 case X86_64_SSEDF_CLASS:
2944 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
2945 case X86_64_X87_CLASS:
2946 case X86_64_COMPLEX_X87_CLASS:
2947 return gen_rtx_REG (mode, FIRST_STACK_REG);
2948 case X86_64_NO_CLASS:
2949 /* Zero sized array, struct or class. */
2954 if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
2956 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
2958 && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
2959 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
2960 if (n == 2 && class[0] == X86_64_INTEGER_CLASS
2961 && class[1] == X86_64_INTEGER_CLASS
2962 && (mode == CDImode || mode == TImode || mode == TFmode)
2963 && intreg[0] + 1 == intreg[1])
2964 return gen_rtx_REG (mode, intreg[0]);
2966 /* Otherwise figure out the entries of the PARALLEL. */
2967 for (i = 0; i < n; i++)
2971 case X86_64_NO_CLASS:
2973 case X86_64_INTEGER_CLASS:
2974 case X86_64_INTEGERSI_CLASS:
2975 /* Merge TImodes on aligned occasions here too. */
2976 if (i * 8 + 8 > bytes)
2977 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
2978 else if (class[i] == X86_64_INTEGERSI_CLASS)
2982 /* We've requested 24 bytes we don't have mode for. Use DImode. */
2983 if (tmpmode == BLKmode)
2985 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
2986 gen_rtx_REG (tmpmode, *intreg),
2990 case X86_64_SSESF_CLASS:
2991 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
2992 gen_rtx_REG (SFmode,
2993 SSE_REGNO (sse_regno)),
2997 case X86_64_SSEDF_CLASS:
2998 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
2999 gen_rtx_REG (DFmode,
3000 SSE_REGNO (sse_regno)),
3004 case X86_64_SSE_CLASS:
3005 if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
3009 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3010 gen_rtx_REG (tmpmode,
3011 SSE_REGNO (sse_regno)),
3013 if (tmpmode == TImode)
3022 /* Empty aligned struct, union or class. */
3026 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
3027 for (i = 0; i < nexps; i++)
3028 XVECEXP (ret, 0, i) = exp [i];
3032 /* Update the data in CUM to advance over an argument
3033 of mode MODE and data type TYPE.
3034 (TYPE is null for libcalls where that information may not be available.) */
3037 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3038 tree type, int named)
3041 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3042 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3045 mode = type_natural_mode (type);
3047 if (TARGET_DEBUG_ARG)
3048 fprintf (stderr, "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, "
3049 "mode=%s, named=%d)\n\n",
3050 words, cum->words, cum->nregs, cum->sse_nregs,
3051 GET_MODE_NAME (mode), named);
3055 int int_nregs, sse_nregs;
3056 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
3057 cum->words += words;
3058 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
3060 cum->nregs -= int_nregs;
3061 cum->sse_nregs -= sse_nregs;
3062 cum->regno += int_nregs;
3063 cum->sse_regno += sse_nregs;
3066 cum->words += words;
3084 cum->words += words;
3085 cum->nregs -= words;
3086 cum->regno += words;
3088 if (cum->nregs <= 0)
3096 if (cum->float_in_sse < 2)
3099 if (cum->float_in_sse < 1)
3110 if (!type || !AGGREGATE_TYPE_P (type))
3112 cum->sse_words += words;
3113 cum->sse_nregs -= 1;
3114 cum->sse_regno += 1;
3115 if (cum->sse_nregs <= 0)
3127 if (!type || !AGGREGATE_TYPE_P (type))
3129 cum->mmx_words += words;
3130 cum->mmx_nregs -= 1;
3131 cum->mmx_regno += 1;
3132 if (cum->mmx_nregs <= 0)
3143 /* Define where to put the arguments to a function.
3144 Value is zero to push the argument on the stack,
3145 or a hard register in which to store the argument.
3147 MODE is the argument's machine mode.
3148 TYPE is the data type of the argument (as a tree).
3149 This is null for libcalls where that information may
3151 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3152 the preceding args and about the function being called.
3153 NAMED is nonzero if this argument is a named parameter
3154 (otherwise it is an extra parameter matching an ellipsis). */
3157 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode,
3158 tree type, int named)
3160 enum machine_mode mode = orig_mode;
3163 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3164 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3165 static bool warnedsse, warnedmmx;
3167 /* To simplify the code below, represent vector types with a vector mode
3168 even if MMX/SSE are not active. */
3169 if (type && TREE_CODE (type) == VECTOR_TYPE)
3170 mode = type_natural_mode (type);
3172 /* Handle a hidden AL argument containing number of registers for varargs
3173 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
3175 if (mode == VOIDmode)
3178 return GEN_INT (cum->maybe_vaarg
3179 ? (cum->sse_nregs < 0
3187 ret = construct_container (mode, orig_mode, type, 0, cum->nregs,
3189 &x86_64_int_parameter_registers [cum->regno],
3194 /* For now, pass fp/complex values on the stack. */
3206 if (words <= cum->nregs)
3208 int regno = cum->regno;
3210 /* Fastcall allocates the first two DWORD (SImode) or
3211 smaller arguments to ECX and EDX. */
3214 if (mode == BLKmode || mode == DImode)
3217 /* ECX not EAX is the first allocated register. */
3221 ret = gen_rtx_REG (mode, regno);
3225 if (cum->float_in_sse < 2)
3228 if (cum->float_in_sse < 1)
3238 if (!type || !AGGREGATE_TYPE_P (type))
3240 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
3243 warning (0, "SSE vector argument without SSE enabled "
3247 ret = gen_reg_or_parallel (mode, orig_mode,
3248 cum->sse_regno + FIRST_SSE_REG);
3255 if (!type || !AGGREGATE_TYPE_P (type))
3257 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
3260 warning (0, "MMX vector argument without MMX enabled "
3264 ret = gen_reg_or_parallel (mode, orig_mode,
3265 cum->mmx_regno + FIRST_MMX_REG);
3270 if (TARGET_DEBUG_ARG)
3273 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
3274 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
3277 print_simple_rtl (stderr, ret);
3279 fprintf (stderr, ", stack");
3281 fprintf (stderr, " )\n");
3287 /* A C expression that indicates when an argument must be passed by
3288 reference. If nonzero for an argument, a copy of that argument is
3289 made in memory and a pointer to the argument is passed instead of
3290 the argument itself. The pointer is passed in whatever way is
3291 appropriate for passing a pointer to that type. */
3294 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3295 enum machine_mode mode ATTRIBUTE_UNUSED,
3296 tree type, bool named ATTRIBUTE_UNUSED)
3301 if (type && int_size_in_bytes (type) == -1)
3303 if (TARGET_DEBUG_ARG)
3304 fprintf (stderr, "function_arg_pass_by_reference\n");
3311 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
3312 ABI. Only called if TARGET_SSE. */
3314 contains_128bit_aligned_vector_p (tree type)
3316 enum machine_mode mode = TYPE_MODE (type);
3317 if (SSE_REG_MODE_P (mode)
3318 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
3320 if (TYPE_ALIGN (type) < 128)
3323 if (AGGREGATE_TYPE_P (type))
3325 /* Walk the aggregates recursively. */
3326 switch (TREE_CODE (type))
3330 case QUAL_UNION_TYPE:
3334 if (TYPE_BINFO (type))
3336 tree binfo, base_binfo;
3339 for (binfo = TYPE_BINFO (type), i = 0;
3340 BINFO_BASE_ITERATE (binfo, i, base_binfo); i++)
3341 if (contains_128bit_aligned_vector_p
3342 (BINFO_TYPE (base_binfo)))
3345 /* And now merge the fields of structure. */
3346 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3348 if (TREE_CODE (field) == FIELD_DECL
3349 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
3356 /* Just for use if some languages passes arrays by value. */
3357 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
3368 /* Gives the alignment boundary, in bits, of an argument with the
3369 specified mode and type. */
3372 ix86_function_arg_boundary (enum machine_mode mode, tree type)
3376 align = TYPE_ALIGN (type);
3378 align = GET_MODE_ALIGNMENT (mode);
3379 if (align < PARM_BOUNDARY)
3380 align = PARM_BOUNDARY;
3383 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
3384 make an exception for SSE modes since these require 128bit
3387 The handling here differs from field_alignment. ICC aligns MMX
3388 arguments to 4 byte boundaries, while structure fields are aligned
3389 to 8 byte boundaries. */
3391 align = PARM_BOUNDARY;
3394 if (!SSE_REG_MODE_P (mode))
3395 align = PARM_BOUNDARY;
3399 if (!contains_128bit_aligned_vector_p (type))
3400 align = PARM_BOUNDARY;
3408 /* Return true if N is a possible register number of function value. */
3410 ix86_function_value_regno_p (int regno)
3413 || (regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)
3414 || (regno == FIRST_SSE_REG && TARGET_SSE))
3418 && (regno == FIRST_MMX_REG && TARGET_MMX))
3424 /* Define how to find the value returned by a function.
3425 VALTYPE is the data type of the value (as a tree).
3426 If the precise function being called is known, FUNC is its FUNCTION_DECL;
3427 otherwise, FUNC is 0. */
3429 ix86_function_value (tree valtype, tree fntype_or_decl,
3430 bool outgoing ATTRIBUTE_UNUSED)
3432 enum machine_mode natmode = type_natural_mode (valtype);
3436 rtx ret = construct_container (natmode, TYPE_MODE (valtype), valtype,
3437 1, REGPARM_MAX, SSE_REGPARM_MAX,
3438 x86_64_int_return_registers, 0);
3439 /* For zero sized structures, construct_container return NULL, but we
3440 need to keep rest of compiler happy by returning meaningful value. */
3442 ret = gen_rtx_REG (TYPE_MODE (valtype), 0);
3447 tree fn = NULL_TREE, fntype;
3449 && DECL_P (fntype_or_decl))
3450 fn = fntype_or_decl;
3451 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
3452 return gen_rtx_REG (TYPE_MODE (valtype),
3453 ix86_value_regno (natmode, fn, fntype));
3457 /* Return false iff type is returned in memory. */
3459 ix86_return_in_memory (tree type)
3461 int needed_intregs, needed_sseregs, size;
3462 enum machine_mode mode = type_natural_mode (type);
3465 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
3467 if (mode == BLKmode)
3470 size = int_size_in_bytes (type);
3472 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
3475 if (VECTOR_MODE_P (mode) || mode == TImode)
3477 /* User-created vectors small enough to fit in EAX. */
3481 /* MMX/3dNow values are returned in MM0,
3482 except when it doesn't exits. */
3484 return (TARGET_MMX ? 0 : 1);
3486 /* SSE values are returned in XMM0, except when it doesn't exist. */
3488 return (TARGET_SSE ? 0 : 1);
3499 /* When returning SSE vector types, we have a choice of either
3500 (1) being abi incompatible with a -march switch, or
3501 (2) generating an error.
3502 Given no good solution, I think the safest thing is one warning.
3503 The user won't be able to use -Werror, but....
3505 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
3506 called in response to actually generating a caller or callee that
3507 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
3508 via aggregate_value_p for general type probing from tree-ssa. */
3511 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
3513 static bool warnedsse, warnedmmx;
3517 /* Look at the return type of the function, not the function type. */
3518 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
3520 if (!TARGET_SSE && !warnedsse)
3523 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3526 warning (0, "SSE vector return without SSE enabled "
3531 if (!TARGET_MMX && !warnedmmx)
3533 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
3536 warning (0, "MMX vector return without MMX enabled "
3545 /* Define how to find the value returned by a library function
3546 assuming the value has mode MODE. */
3548 ix86_libcall_value (enum machine_mode mode)
3559 return gen_rtx_REG (mode, FIRST_SSE_REG);
3562 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
3566 return gen_rtx_REG (mode, 0);
3570 return gen_rtx_REG (mode, ix86_value_regno (mode, NULL, NULL));
3573 /* Given a mode, return the register to use for a return value. */
3576 ix86_value_regno (enum machine_mode mode, tree func, tree fntype)
3578 gcc_assert (!TARGET_64BIT);
3580 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
3581 we prevent this case when mmx is not available. */
3582 if ((VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8))
3583 return FIRST_MMX_REG;
3585 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
3586 we prevent this case when sse is not available. */
3587 if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3588 return FIRST_SSE_REG;
3590 /* Most things go in %eax, except (unless -mno-fp-ret-in-387) fp values. */
3591 if (GET_MODE_CLASS (mode) != MODE_FLOAT || !TARGET_FLOAT_RETURNS_IN_80387)
3594 /* Floating point return values in %st(0), except for local functions when
3595 SSE math is enabled or for functions with sseregparm attribute. */
3596 if ((func || fntype)
3597 && (mode == SFmode || mode == DFmode))
3599 int sse_level = ix86_function_sseregparm (fntype, func);
3600 if ((sse_level >= 1 && mode == SFmode)
3601 || (sse_level == 2 && mode == DFmode))
3602 return FIRST_SSE_REG;
3605 return FIRST_FLOAT_REG;
3608 /* Create the va_list data type. */
3611 ix86_build_builtin_va_list (void)
3613 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
3615 /* For i386 we use plain pointer to argument area. */
3617 return build_pointer_type (char_type_node);
3619 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3620 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
3622 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
3623 unsigned_type_node);
3624 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
3625 unsigned_type_node);
3626 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
3628 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
3631 va_list_gpr_counter_field = f_gpr;
3632 va_list_fpr_counter_field = f_fpr;
3634 DECL_FIELD_CONTEXT (f_gpr) = record;
3635 DECL_FIELD_CONTEXT (f_fpr) = record;
3636 DECL_FIELD_CONTEXT (f_ovf) = record;
3637 DECL_FIELD_CONTEXT (f_sav) = record;
3639 TREE_CHAIN (record) = type_decl;
3640 TYPE_NAME (record) = type_decl;
3641 TYPE_FIELDS (record) = f_gpr;
3642 TREE_CHAIN (f_gpr) = f_fpr;
3643 TREE_CHAIN (f_fpr) = f_ovf;
3644 TREE_CHAIN (f_ovf) = f_sav;
3646 layout_type (record);
3648 /* The correct type is an array type of one element. */
3649 return build_array_type (record, build_index_type (size_zero_node));
3652 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3655 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3656 tree type, int *pretend_size ATTRIBUTE_UNUSED,
3659 CUMULATIVE_ARGS next_cum;
3660 rtx save_area = NULL_RTX, mem;
3673 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
3676 /* Indicate to allocate space on the stack for varargs save area. */
3677 ix86_save_varrargs_registers = 1;
3679 cfun->stack_alignment_needed = 128;
3681 fntype = TREE_TYPE (current_function_decl);
3682 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
3683 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3684 != void_type_node));
3686 /* For varargs, we do not want to skip the dummy va_dcl argument.
3687 For stdargs, we do want to skip the last named argument. */
3690 function_arg_advance (&next_cum, mode, type, 1);
3693 save_area = frame_pointer_rtx;
3695 set = get_varargs_alias_set ();
3697 for (i = next_cum.regno;
3699 && i < next_cum.regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
3702 mem = gen_rtx_MEM (Pmode,
3703 plus_constant (save_area, i * UNITS_PER_WORD));
3704 MEM_NOTRAP_P (mem) = 1;
3705 set_mem_alias_set (mem, set);
3706 emit_move_insn (mem, gen_rtx_REG (Pmode,
3707 x86_64_int_parameter_registers[i]));
3710 if (next_cum.sse_nregs && cfun->va_list_fpr_size)
3712 /* Now emit code to save SSE registers. The AX parameter contains number
3713 of SSE parameter registers used to call this function. We use
3714 sse_prologue_save insn template that produces computed jump across
3715 SSE saves. We need some preparation work to get this working. */
3717 label = gen_label_rtx ();
3718 label_ref = gen_rtx_LABEL_REF (Pmode, label);
3720 /* Compute address to jump to :
3721 label - 5*eax + nnamed_sse_arguments*5 */
3722 tmp_reg = gen_reg_rtx (Pmode);
3723 nsse_reg = gen_reg_rtx (Pmode);
3724 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
3725 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
3726 gen_rtx_MULT (Pmode, nsse_reg,
3728 if (next_cum.sse_regno)
3731 gen_rtx_CONST (DImode,
3732 gen_rtx_PLUS (DImode,
3734 GEN_INT (next_cum.sse_regno * 4))));
3736 emit_move_insn (nsse_reg, label_ref);
3737 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
3739 /* Compute address of memory block we save into. We always use pointer
3740 pointing 127 bytes after first byte to store - this is needed to keep
3741 instruction size limited by 4 bytes. */
3742 tmp_reg = gen_reg_rtx (Pmode);
3743 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
3744 plus_constant (save_area,
3745 8 * REGPARM_MAX + 127)));
3746 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
3747 MEM_NOTRAP_P (mem) = 1;
3748 set_mem_alias_set (mem, set);
3749 set_mem_align (mem, BITS_PER_WORD);
3751 /* And finally do the dirty job! */
3752 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
3753 GEN_INT (next_cum.sse_regno), label));
3758 /* Implement va_start. */
3761 ix86_va_start (tree valist, rtx nextarg)
3763 HOST_WIDE_INT words, n_gpr, n_fpr;
3764 tree f_gpr, f_fpr, f_ovf, f_sav;
3765 tree gpr, fpr, ovf, sav, t;
3767 /* Only 64bit target needs something special. */
3770 std_expand_builtin_va_start (valist, nextarg);
3774 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
3775 f_fpr = TREE_CHAIN (f_gpr);
3776 f_ovf = TREE_CHAIN (f_fpr);
3777 f_sav = TREE_CHAIN (f_ovf);
3779 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
3780 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
3781 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
3782 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
3783 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
3785 /* Count number of gp and fp argument registers used. */
3786 words = current_function_args_info.words;
3787 n_gpr = current_function_args_info.regno;
3788 n_fpr = current_function_args_info.sse_regno;
3790 if (TARGET_DEBUG_ARG)
3791 fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
3792 (int) words, (int) n_gpr, (int) n_fpr);
3794 if (cfun->va_list_gpr_size)
3796 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
3797 build_int_cst (NULL_TREE, n_gpr * 8));
3798 TREE_SIDE_EFFECTS (t) = 1;
3799 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3802 if (cfun->va_list_fpr_size)
3804 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
3805 build_int_cst (NULL_TREE, n_fpr * 16 + 8*REGPARM_MAX));
3806 TREE_SIDE_EFFECTS (t) = 1;
3807 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3810 /* Find the overflow area. */
3811 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
3813 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
3814 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
3815 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
3816 TREE_SIDE_EFFECTS (t) = 1;
3817 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3819 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
3821 /* Find the register save area.
3822 Prologue of the function save it right above stack frame. */
3823 t = make_tree (TREE_TYPE (sav), frame_pointer_rtx);
3824 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
3825 TREE_SIDE_EFFECTS (t) = 1;
3826 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3830 /* Implement va_arg. */
3833 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
3835 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
3836 tree f_gpr, f_fpr, f_ovf, f_sav;
3837 tree gpr, fpr, ovf, sav, t;
3839 tree lab_false, lab_over = NULL_TREE;
3844 enum machine_mode nat_mode;
3846 /* Only 64bit target needs something special. */
3848 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
3850 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
3851 f_fpr = TREE_CHAIN (f_gpr);
3852 f_ovf = TREE_CHAIN (f_fpr);
3853 f_sav = TREE_CHAIN (f_ovf);
3855 valist = build_va_arg_indirect_ref (valist);
3856 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
3857 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
3858 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
3859 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
3861 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
3863 type = build_pointer_type (type);
3864 size = int_size_in_bytes (type);
3865 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3867 nat_mode = type_natural_mode (type);
3868 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
3869 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
3871 /* Pull the value out of the saved registers. */
3873 addr = create_tmp_var (ptr_type_node, "addr");
3874 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
3878 int needed_intregs, needed_sseregs;
3880 tree int_addr, sse_addr;
3882 lab_false = create_artificial_label ();
3883 lab_over = create_artificial_label ();
3885 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
3887 need_temp = (!REG_P (container)
3888 && ((needed_intregs && TYPE_ALIGN (type) > 64)
3889 || TYPE_ALIGN (type) > 128));
3891 /* In case we are passing structure, verify that it is consecutive block
3892 on the register save area. If not we need to do moves. */
3893 if (!need_temp && !REG_P (container))
3895 /* Verify that all registers are strictly consecutive */
3896 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
3900 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
3902 rtx slot = XVECEXP (container, 0, i);
3903 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
3904 || INTVAL (XEXP (slot, 1)) != i * 16)
3912 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
3914 rtx slot = XVECEXP (container, 0, i);
3915 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
3916 || INTVAL (XEXP (slot, 1)) != i * 8)
3928 int_addr = create_tmp_var (ptr_type_node, "int_addr");
3929 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
3930 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
3931 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
3934 /* First ensure that we fit completely in registers. */
3937 t = build_int_cst (TREE_TYPE (gpr),
3938 (REGPARM_MAX - needed_intregs + 1) * 8);
3939 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
3940 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
3941 t = build (COND_EXPR, void_type_node, t, t2, NULL_TREE);
3942 gimplify_and_add (t, pre_p);
3946 t = build_int_cst (TREE_TYPE (fpr),
3947 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
3949 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
3950 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
3951 t = build (COND_EXPR, void_type_node, t, t2, NULL_TREE);
3952 gimplify_and_add (t, pre_p);
3955 /* Compute index to start of area used for integer regs. */
3958 /* int_addr = gpr + sav; */
3959 t = fold_convert (ptr_type_node, gpr);
3960 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
3961 t = build2 (MODIFY_EXPR, void_type_node, int_addr, t);
3962 gimplify_and_add (t, pre_p);
3966 /* sse_addr = fpr + sav; */
3967 t = fold_convert (ptr_type_node, fpr);
3968 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
3969 t = build2 (MODIFY_EXPR, void_type_node, sse_addr, t);
3970 gimplify_and_add (t, pre_p);
3975 tree temp = create_tmp_var (type, "va_arg_tmp");
3978 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
3979 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
3980 gimplify_and_add (t, pre_p);
3982 for (i = 0; i < XVECLEN (container, 0); i++)
3984 rtx slot = XVECEXP (container, 0, i);
3985 rtx reg = XEXP (slot, 0);
3986 enum machine_mode mode = GET_MODE (reg);
3987 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
3988 tree addr_type = build_pointer_type (piece_type);
3991 tree dest_addr, dest;
3993 if (SSE_REGNO_P (REGNO (reg)))
3995 src_addr = sse_addr;
3996 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
4000 src_addr = int_addr;
4001 src_offset = REGNO (reg) * 8;
4003 src_addr = fold_convert (addr_type, src_addr);
4004 src_addr = fold (build2 (PLUS_EXPR, addr_type, src_addr,
4005 size_int (src_offset)));
4006 src = build_va_arg_indirect_ref (src_addr);
4008 dest_addr = fold_convert (addr_type, addr);
4009 dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr,
4010 size_int (INTVAL (XEXP (slot, 1)))));
4011 dest = build_va_arg_indirect_ref (dest_addr);
4013 t = build2 (MODIFY_EXPR, void_type_node, dest, src);
4014 gimplify_and_add (t, pre_p);
4020 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4021 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
4022 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4023 gimplify_and_add (t, pre_p);
4027 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
4028 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
4029 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
4030 gimplify_and_add (t, pre_p);
4033 t = build1 (GOTO_EXPR, void_type_node, lab_over);
4034 gimplify_and_add (t, pre_p);
4036 t = build1 (LABEL_EXPR, void_type_node, lab_false);
4037 append_to_statement_list (t, pre_p);
4040 /* ... otherwise out of the overflow area. */
4042 /* Care for on-stack alignment if needed. */
4043 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64)
4047 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
4048 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf,
4049 build_int_cst (TREE_TYPE (ovf), align - 1));
4050 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4051 build_int_cst (TREE_TYPE (t), -align));
4053 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
4055 t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
4056 gimplify_and_add (t2, pre_p);
4058 t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
4059 build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD));
4060 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4061 gimplify_and_add (t, pre_p);
4065 t = build1 (LABEL_EXPR, void_type_node, lab_over);
4066 append_to_statement_list (t, pre_p);
4069 ptrtype = build_pointer_type (type);
4070 addr = fold_convert (ptrtype, addr);
4073 addr = build_va_arg_indirect_ref (addr);
4074 return build_va_arg_indirect_ref (addr);
4077 /* Return nonzero if OPNUM's MEM should be matched
4078 in movabs* patterns. */
4081 ix86_check_movabs (rtx insn, int opnum)
4085 set = PATTERN (insn);
4086 if (GET_CODE (set) == PARALLEL)
4087 set = XVECEXP (set, 0, 0);
4088 gcc_assert (GET_CODE (set) == SET);
4089 mem = XEXP (set, opnum);
4090 while (GET_CODE (mem) == SUBREG)
4091 mem = SUBREG_REG (mem);
4092 gcc_assert (GET_CODE (mem) == MEM);
4093 return (volatile_ok || !MEM_VOLATILE_P (mem));
4096 /* Initialize the table of extra 80387 mathematical constants. */
4099 init_ext_80387_constants (void)
4101 static const char * cst[5] =
4103 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
4104 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
4105 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
4106 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
4107 "3.1415926535897932385128089594061862044", /* 4: fldpi */
4111 for (i = 0; i < 5; i++)
4113 real_from_string (&ext_80387_constants_table[i], cst[i]);
4114 /* Ensure each constant is rounded to XFmode precision. */
4115 real_convert (&ext_80387_constants_table[i],
4116 XFmode, &ext_80387_constants_table[i]);
4119 ext_80387_constants_init = 1;
4122 /* Return true if the constant is something that can be loaded with
4123 a special instruction. */
4126 standard_80387_constant_p (rtx x)
4128 if (GET_CODE (x) != CONST_DOUBLE || !FLOAT_MODE_P (GET_MODE (x)))
4131 if (x == CONST0_RTX (GET_MODE (x)))
4133 if (x == CONST1_RTX (GET_MODE (x)))
4136 /* For XFmode constants, try to find a special 80387 instruction when
4137 optimizing for size or on those CPUs that benefit from them. */
4138 if (GET_MODE (x) == XFmode
4139 && (optimize_size || x86_ext_80387_constants & TUNEMASK))
4144 if (! ext_80387_constants_init)
4145 init_ext_80387_constants ();
4147 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4148 for (i = 0; i < 5; i++)
4149 if (real_identical (&r, &ext_80387_constants_table[i]))
4156 /* Return the opcode of the special instruction to be used to load
4160 standard_80387_constant_opcode (rtx x)
4162 switch (standard_80387_constant_p (x))
4183 /* Return the CONST_DOUBLE representing the 80387 constant that is
4184 loaded by the specified special instruction. The argument IDX
4185 matches the return value from standard_80387_constant_p. */
4188 standard_80387_constant_rtx (int idx)
4192 if (! ext_80387_constants_init)
4193 init_ext_80387_constants ();
4209 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
4213 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
4216 standard_sse_constant_p (rtx x)
4218 if (x == const0_rtx)
4220 return (x == CONST0_RTX (GET_MODE (x)));
4223 /* Returns 1 if OP contains a symbol reference */
4226 symbolic_reference_mentioned_p (rtx op)
4231 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
4234 fmt = GET_RTX_FORMAT (GET_CODE (op));
4235 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
4241 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
4242 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
4246 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
4253 /* Return 1 if it is appropriate to emit `ret' instructions in the
4254 body of a function. Do this only if the epilogue is simple, needing a
4255 couple of insns. Prior to reloading, we can't tell how many registers
4256 must be saved, so return 0 then. Return 0 if there is no frame
4257 marker to de-allocate. */
4260 ix86_can_use_return_insn_p (void)
4262 struct ix86_frame frame;
4264 if (! reload_completed || frame_pointer_needed)
4267 /* Don't allow more than 32 pop, since that's all we can do
4268 with one instruction. */
4269 if (current_function_pops_args
4270 && current_function_args_size >= 32768)
4273 ix86_compute_frame_layout (&frame);
4274 return frame.to_allocate == 0 && frame.nregs == 0;
4277 /* Value should be nonzero if functions must have frame pointers.
4278 Zero means the frame pointer need not be set up (and parms may
4279 be accessed via the stack pointer) in functions that seem suitable. */
4282 ix86_frame_pointer_required (void)
4284 /* If we accessed previous frames, then the generated code expects
4285 to be able to access the saved ebp value in our frame. */
4286 if (cfun->machine->accesses_prev_frame)
4289 /* Several x86 os'es need a frame pointer for other reasons,
4290 usually pertaining to setjmp. */
4291 if (SUBTARGET_FRAME_POINTER_REQUIRED)
4294 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
4295 the frame pointer by default. Turn it back on now if we've not
4296 got a leaf function. */
4297 if (TARGET_OMIT_LEAF_FRAME_POINTER
4298 && (!current_function_is_leaf))
4301 if (current_function_profile)
4307 /* Record that the current function accesses previous call frames. */
4310 ix86_setup_frame_addresses (void)
4312 cfun->machine->accesses_prev_frame = 1;
4315 #if defined(HAVE_GAS_HIDDEN) && defined(SUPPORTS_ONE_ONLY)
4316 # define USE_HIDDEN_LINKONCE 1
4318 # define USE_HIDDEN_LINKONCE 0
4321 static int pic_labels_used;
4323 /* Fills in the label name that should be used for a pc thunk for
4324 the given register. */
4327 get_pc_thunk_name (char name[32], unsigned int regno)
4329 if (USE_HIDDEN_LINKONCE)
4330 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
4332 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
4336 /* This function generates code for -fpic that loads %ebx with
4337 the return address of the caller and then returns. */
4340 ix86_file_end (void)
4345 for (regno = 0; regno < 8; ++regno)
4349 if (! ((pic_labels_used >> regno) & 1))
4352 get_pc_thunk_name (name, regno);
4354 if (USE_HIDDEN_LINKONCE)
4358 decl = build_decl (FUNCTION_DECL, get_identifier (name),
4360 TREE_PUBLIC (decl) = 1;
4361 TREE_STATIC (decl) = 1;
4362 DECL_ONE_ONLY (decl) = 1;
4364 (*targetm.asm_out.unique_section) (decl, 0);
4365 named_section (decl, NULL, 0);
4367 (*targetm.asm_out.globalize_label) (asm_out_file, name);
4368 fputs ("\t.hidden\t", asm_out_file);
4369 assemble_name (asm_out_file, name);
4370 fputc ('\n', asm_out_file);
4371 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
4376 ASM_OUTPUT_LABEL (asm_out_file, name);
4379 xops[0] = gen_rtx_REG (SImode, regno);
4380 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
4381 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
4382 output_asm_insn ("ret", xops);
4385 if (NEED_INDICATE_EXEC_STACK)
4386 file_end_indicate_exec_stack ();
4389 /* Emit code for the SET_GOT patterns. */
4392 output_set_got (rtx dest)
4397 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
4399 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
4401 xops[2] = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
4404 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
4406 output_asm_insn ("call\t%a2", xops);
4409 /* Output the "canonical" label name ("Lxx$pb") here too. This
4410 is what will be referred to by the Mach-O PIC subsystem. */
4411 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
4413 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4414 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
4417 output_asm_insn ("pop{l}\t%0", xops);
4422 get_pc_thunk_name (name, REGNO (dest));
4423 pic_labels_used |= 1 << REGNO (dest);
4425 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4426 xops[2] = gen_rtx_MEM (QImode, xops[2]);
4427 output_asm_insn ("call\t%X2", xops);
4430 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
4431 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
4432 else if (!TARGET_MACHO)
4433 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
4438 /* Generate an "push" pattern for input ARG. */
4443 return gen_rtx_SET (VOIDmode,
4445 gen_rtx_PRE_DEC (Pmode,
4446 stack_pointer_rtx)),
4450 /* Return >= 0 if there is an unused call-clobbered register available
4451 for the entire function. */
4454 ix86_select_alt_pic_regnum (void)
4456 if (current_function_is_leaf && !current_function_profile)
4459 for (i = 2; i >= 0; --i)
4460 if (!regs_ever_live[i])
4464 return INVALID_REGNUM;
4467 /* Return 1 if we need to save REGNO. */
4469 ix86_save_reg (unsigned int regno, int maybe_eh_return)
4471 if (pic_offset_table_rtx
4472 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
4473 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
4474 || current_function_profile
4475 || current_function_calls_eh_return
4476 || current_function_uses_const_pool))
4478 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
4483 if (current_function_calls_eh_return && maybe_eh_return)
4488 unsigned test = EH_RETURN_DATA_REGNO (i);
4489 if (test == INVALID_REGNUM)
4496 return (regs_ever_live[regno]
4497 && !call_used_regs[regno]
4498 && !fixed_regs[regno]
4499 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
4502 /* Return number of registers to be saved on the stack. */
4505 ix86_nsaved_regs (void)
4510 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
4511 if (ix86_save_reg (regno, true))
4516 /* Return the offset between two registers, one to be eliminated, and the other
4517 its replacement, at the start of a routine. */
4520 ix86_initial_elimination_offset (int from, int to)
4522 struct ix86_frame frame;
4523 ix86_compute_frame_layout (&frame);
4525 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
4526 return frame.hard_frame_pointer_offset;
4527 else if (from == FRAME_POINTER_REGNUM
4528 && to == HARD_FRAME_POINTER_REGNUM)
4529 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
4532 gcc_assert (to == STACK_POINTER_REGNUM);
4534 if (from == ARG_POINTER_REGNUM)
4535 return frame.stack_pointer_offset;
4537 gcc_assert (from == FRAME_POINTER_REGNUM);
4538 return frame.stack_pointer_offset - frame.frame_pointer_offset;
4542 /* Fill structure ix86_frame about frame of currently computed function. */
4545 ix86_compute_frame_layout (struct ix86_frame *frame)
4547 HOST_WIDE_INT total_size;
4548 unsigned int stack_alignment_needed;
4549 HOST_WIDE_INT offset;
4550 unsigned int preferred_alignment;
4551 HOST_WIDE_INT size = get_frame_size ();
4553 frame->nregs = ix86_nsaved_regs ();
4556 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
4557 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
4559 /* During reload iteration the amount of registers saved can change.
4560 Recompute the value as needed. Do not recompute when amount of registers
4561 didn't change as reload does multiple calls to the function and does not
4562 expect the decision to change within single iteration. */
4564 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
4566 int count = frame->nregs;
4568 cfun->machine->use_fast_prologue_epilogue_nregs = count;
4569 /* The fast prologue uses move instead of push to save registers. This
4570 is significantly longer, but also executes faster as modern hardware
4571 can execute the moves in parallel, but can't do that for push/pop.
4573 Be careful about choosing what prologue to emit: When function takes
4574 many instructions to execute we may use slow version as well as in
4575 case function is known to be outside hot spot (this is known with
4576 feedback only). Weight the size of function by number of registers
4577 to save as it is cheap to use one or two push instructions but very
4578 slow to use many of them. */
4580 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
4581 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
4582 || (flag_branch_probabilities
4583 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
4584 cfun->machine->use_fast_prologue_epilogue = false;
4586 cfun->machine->use_fast_prologue_epilogue
4587 = !expensive_function_p (count);
4589 if (TARGET_PROLOGUE_USING_MOVE
4590 && cfun->machine->use_fast_prologue_epilogue)
4591 frame->save_regs_using_mov = true;
4593 frame->save_regs_using_mov = false;
4596 /* Skip return address and saved base pointer. */
4597 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
4599 frame->hard_frame_pointer_offset = offset;
4601 /* Do some sanity checking of stack_alignment_needed and
4602 preferred_alignment, since i386 port is the only using those features
4603 that may break easily. */
4605 gcc_assert (!size || stack_alignment_needed);
4606 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
4607 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
4608 gcc_assert (stack_alignment_needed
4609 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
4611 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
4612 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
4614 /* Register save area */
4615 offset += frame->nregs * UNITS_PER_WORD;
4618 if (ix86_save_varrargs_registers)
4620 offset += X86_64_VARARGS_SIZE;
4621 frame->va_arg_size = X86_64_VARARGS_SIZE;
4624 frame->va_arg_size = 0;
4626 /* Align start of frame for local function. */
4627 frame->padding1 = ((offset + stack_alignment_needed - 1)
4628 & -stack_alignment_needed) - offset;
4630 offset += frame->padding1;
4632 /* Frame pointer points here. */
4633 frame->frame_pointer_offset = offset;
4637 /* Add outgoing arguments area. Can be skipped if we eliminated
4638 all the function calls as dead code.
4639 Skipping is however impossible when function calls alloca. Alloca
4640 expander assumes that last current_function_outgoing_args_size
4641 of stack frame are unused. */
4642 if (ACCUMULATE_OUTGOING_ARGS
4643 && (!current_function_is_leaf || current_function_calls_alloca))
4645 offset += current_function_outgoing_args_size;
4646 frame->outgoing_arguments_size = current_function_outgoing_args_size;
4649 frame->outgoing_arguments_size = 0;
4651 /* Align stack boundary. Only needed if we're calling another function
4653 if (!current_function_is_leaf || current_function_calls_alloca)
4654 frame->padding2 = ((offset + preferred_alignment - 1)
4655 & -preferred_alignment) - offset;
4657 frame->padding2 = 0;
4659 offset += frame->padding2;
4661 /* We've reached end of stack frame. */
4662 frame->stack_pointer_offset = offset;
4664 /* Size prologue needs to allocate. */
4665 frame->to_allocate =
4666 (size + frame->padding1 + frame->padding2
4667 + frame->outgoing_arguments_size + frame->va_arg_size);
4669 if ((!frame->to_allocate && frame->nregs <= 1)
4670 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
4671 frame->save_regs_using_mov = false;
4673 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
4674 && current_function_is_leaf)
4676 frame->red_zone_size = frame->to_allocate;
4677 if (frame->save_regs_using_mov)
4678 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
4679 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
4680 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
4683 frame->red_zone_size = 0;
4684 frame->to_allocate -= frame->red_zone_size;
4685 frame->stack_pointer_offset -= frame->red_zone_size;
4687 fprintf (stderr, "nregs: %i\n", frame->nregs);
4688 fprintf (stderr, "size: %i\n", size);
4689 fprintf (stderr, "alignment1: %i\n", stack_alignment_needed);
4690 fprintf (stderr, "padding1: %i\n", frame->padding1);
4691 fprintf (stderr, "va_arg: %i\n", frame->va_arg_size);
4692 fprintf (stderr, "padding2: %i\n", frame->padding2);
4693 fprintf (stderr, "to_allocate: %i\n", frame->to_allocate);
4694 fprintf (stderr, "red_zone_size: %i\n", frame->red_zone_size);
4695 fprintf (stderr, "frame_pointer_offset: %i\n", frame->frame_pointer_offset);
4696 fprintf (stderr, "hard_frame_pointer_offset: %i\n",
4697 frame->hard_frame_pointer_offset);
4698 fprintf (stderr, "stack_pointer_offset: %i\n", frame->stack_pointer_offset);
4702 /* Emit code to save registers in the prologue. */
4705 ix86_emit_save_regs (void)
4710 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
4711 if (ix86_save_reg (regno, true))
4713 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
4714 RTX_FRAME_RELATED_P (insn) = 1;
4718 /* Emit code to save registers using MOV insns. First register
4719 is restored from POINTER + OFFSET. */
4721 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
4726 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4727 if (ix86_save_reg (regno, true))
4729 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
4731 gen_rtx_REG (Pmode, regno));
4732 RTX_FRAME_RELATED_P (insn) = 1;
4733 offset += UNITS_PER_WORD;
4737 /* Expand prologue or epilogue stack adjustment.
4738 The pattern exist to put a dependency on all ebp-based memory accesses.
4739 STYLE should be negative if instructions should be marked as frame related,
4740 zero if %r11 register is live and cannot be freely used and positive
4744 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
4749 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
4750 else if (x86_64_immediate_operand (offset, DImode))
4751 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
4755 /* r11 is used by indirect sibcall return as well, set before the
4756 epilogue and used after the epilogue. ATM indirect sibcall
4757 shouldn't be used together with huge frame sizes in one
4758 function because of the frame_size check in sibcall.c. */
4760 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
4761 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
4763 RTX_FRAME_RELATED_P (insn) = 1;
4764 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
4768 RTX_FRAME_RELATED_P (insn) = 1;
4771 /* Expand the prologue into a bunch of separate insns. */
4774 ix86_expand_prologue (void)
4778 struct ix86_frame frame;
4779 HOST_WIDE_INT allocate;
4781 ix86_compute_frame_layout (&frame);
4783 /* Note: AT&T enter does NOT have reversed args. Enter is probably
4784 slower on all targets. Also sdb doesn't like it. */
4786 if (frame_pointer_needed)
4788 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
4789 RTX_FRAME_RELATED_P (insn) = 1;
4791 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
4792 RTX_FRAME_RELATED_P (insn) = 1;
4795 allocate = frame.to_allocate;
4797 if (!frame.save_regs_using_mov)
4798 ix86_emit_save_regs ();
4800 allocate += frame.nregs * UNITS_PER_WORD;
4802 /* When using red zone we may start register saving before allocating
4803 the stack frame saving one cycle of the prologue. */
4804 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
4805 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
4806 : stack_pointer_rtx,
4807 -frame.nregs * UNITS_PER_WORD);
4811 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
4812 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
4813 GEN_INT (-allocate), -1);
4816 /* Only valid for Win32. */
4817 rtx eax = gen_rtx_REG (SImode, 0);
4818 bool eax_live = ix86_eax_live_at_start_p ();
4821 gcc_assert (!TARGET_64BIT);
4825 emit_insn (gen_push (eax));
4829 emit_move_insn (eax, GEN_INT (allocate));
4831 insn = emit_insn (gen_allocate_stack_worker (eax));
4832 RTX_FRAME_RELATED_P (insn) = 1;
4833 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
4834 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
4835 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4836 t, REG_NOTES (insn));
4840 if (frame_pointer_needed)
4841 t = plus_constant (hard_frame_pointer_rtx,
4844 - frame.nregs * UNITS_PER_WORD);
4846 t = plus_constant (stack_pointer_rtx, allocate);
4847 emit_move_insn (eax, gen_rtx_MEM (SImode, t));
4851 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
4853 if (!frame_pointer_needed || !frame.to_allocate)
4854 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
4856 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
4857 -frame.nregs * UNITS_PER_WORD);
4860 pic_reg_used = false;
4861 if (pic_offset_table_rtx
4862 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
4863 || current_function_profile))
4865 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
4867 if (alt_pic_reg_used != INVALID_REGNUM)
4868 REGNO (pic_offset_table_rtx) = alt_pic_reg_used;
4870 pic_reg_used = true;
4876 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
4878 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
4880 /* Even with accurate pre-reload life analysis, we can wind up
4881 deleting all references to the pic register after reload.
4882 Consider if cross-jumping unifies two sides of a branch
4883 controlled by a comparison vs the only read from a global.
4884 In which case, allow the set_got to be deleted, though we're
4885 too late to do anything about the ebx save in the prologue. */
4886 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
4889 /* Prevent function calls from be scheduled before the call to mcount.
4890 In the pic_reg_used case, make sure that the got load isn't deleted. */
4891 if (current_function_profile)
4892 emit_insn (gen_blockage (pic_reg_used ? pic_offset_table_rtx : const0_rtx));
4895 /* Emit code to restore saved registers using MOV insns. First register
4896 is restored from POINTER + OFFSET. */
4898 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
4899 int maybe_eh_return)
4902 rtx base_address = gen_rtx_MEM (Pmode, pointer);
4904 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4905 if (ix86_save_reg (regno, maybe_eh_return))
4907 /* Ensure that adjust_address won't be forced to produce pointer
4908 out of range allowed by x86-64 instruction set. */
4909 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
4913 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
4914 emit_move_insn (r11, GEN_INT (offset));
4915 emit_insn (gen_adddi3 (r11, r11, pointer));
4916 base_address = gen_rtx_MEM (Pmode, r11);
4919 emit_move_insn (gen_rtx_REG (Pmode, regno),
4920 adjust_address (base_address, Pmode, offset));
4921 offset += UNITS_PER_WORD;
4925 /* Restore function stack, frame, and registers. */
4928 ix86_expand_epilogue (int style)
4931 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
4932 struct ix86_frame frame;
4933 HOST_WIDE_INT offset;
4935 ix86_compute_frame_layout (&frame);
4937 /* Calculate start of saved registers relative to ebp. Special care
4938 must be taken for the normal return case of a function using
4939 eh_return: the eax and edx registers are marked as saved, but not
4940 restored along this path. */
4941 offset = frame.nregs;
4942 if (current_function_calls_eh_return && style != 2)
4944 offset *= -UNITS_PER_WORD;
4946 /* If we're only restoring one register and sp is not valid then
4947 using a move instruction to restore the register since it's
4948 less work than reloading sp and popping the register.
4950 The default code result in stack adjustment using add/lea instruction,
4951 while this code results in LEAVE instruction (or discrete equivalent),
4952 so it is profitable in some other cases as well. Especially when there
4953 are no registers to restore. We also use this code when TARGET_USE_LEAVE
4954 and there is exactly one register to pop. This heuristic may need some
4955 tuning in future. */
4956 if ((!sp_valid && frame.nregs <= 1)
4957 || (TARGET_EPILOGUE_USING_MOVE
4958 && cfun->machine->use_fast_prologue_epilogue
4959 && (frame.nregs > 1 || frame.to_allocate))
4960 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
4961 || (frame_pointer_needed && TARGET_USE_LEAVE
4962 && cfun->machine->use_fast_prologue_epilogue
4963 && frame.nregs == 1)
4964 || current_function_calls_eh_return)
4966 /* Restore registers. We can use ebp or esp to address the memory
4967 locations. If both are available, default to ebp, since offsets
4968 are known to be small. Only exception is esp pointing directly to the
4969 end of block of saved registers, where we may simplify addressing
4972 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
4973 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
4974 frame.to_allocate, style == 2);
4976 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
4977 offset, style == 2);
4979 /* eh_return epilogues need %ecx added to the stack pointer. */
4982 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
4984 if (frame_pointer_needed)
4986 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
4987 tmp = plus_constant (tmp, UNITS_PER_WORD);
4988 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
4990 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
4991 emit_move_insn (hard_frame_pointer_rtx, tmp);
4993 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
4998 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
4999 tmp = plus_constant (tmp, (frame.to_allocate
5000 + frame.nregs * UNITS_PER_WORD));
5001 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
5004 else if (!frame_pointer_needed)
5005 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5006 GEN_INT (frame.to_allocate
5007 + frame.nregs * UNITS_PER_WORD),
5009 /* If not an i386, mov & pop is faster than "leave". */
5010 else if (TARGET_USE_LEAVE || optimize_size
5011 || !cfun->machine->use_fast_prologue_epilogue)
5012 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5015 pro_epilogue_adjust_stack (stack_pointer_rtx,
5016 hard_frame_pointer_rtx,
5019 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5021 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5026 /* First step is to deallocate the stack frame so that we can
5027 pop the registers. */
5030 gcc_assert (frame_pointer_needed);
5031 pro_epilogue_adjust_stack (stack_pointer_rtx,
5032 hard_frame_pointer_rtx,
5033 GEN_INT (offset), style);
5035 else if (frame.to_allocate)
5036 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5037 GEN_INT (frame.to_allocate), style);
5039 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5040 if (ix86_save_reg (regno, false))
5043 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
5045 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
5047 if (frame_pointer_needed)
5049 /* Leave results in shorter dependency chains on CPUs that are
5050 able to grok it fast. */
5051 if (TARGET_USE_LEAVE)
5052 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5053 else if (TARGET_64BIT)
5054 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5056 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5060 /* Sibcall epilogues don't want a return instruction. */
5064 if (current_function_pops_args && current_function_args_size)
5066 rtx popc = GEN_INT (current_function_pops_args);
5068 /* i386 can only pop 64K bytes. If asked to pop more, pop
5069 return address, do explicit add, and jump indirectly to the
5072 if (current_function_pops_args >= 65536)
5074 rtx ecx = gen_rtx_REG (SImode, 2);
5076 /* There is no "pascal" calling convention in 64bit ABI. */
5077 gcc_assert (!TARGET_64BIT);
5079 emit_insn (gen_popsi1 (ecx));
5080 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
5081 emit_jump_insn (gen_return_indirect_internal (ecx));
5084 emit_jump_insn (gen_return_pop_internal (popc));
5087 emit_jump_insn (gen_return_internal ());
5090 /* Reset from the function's potential modifications. */
5093 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5094 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5096 if (pic_offset_table_rtx)
5097 REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM;
5100 /* Extract the parts of an RTL expression that is a valid memory address
5101 for an instruction. Return 0 if the structure of the address is
5102 grossly off. Return -1 if the address contains ASHIFT, so it is not
5103 strictly valid, but still used for computing length of lea instruction. */
5106 ix86_decompose_address (rtx addr, struct ix86_address *out)
5108 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
5109 rtx base_reg, index_reg;
5110 HOST_WIDE_INT scale = 1;
5111 rtx scale_rtx = NULL_RTX;
5113 enum ix86_address_seg seg = SEG_DEFAULT;
5115 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
5117 else if (GET_CODE (addr) == PLUS)
5127 addends[n++] = XEXP (op, 1);
5130 while (GET_CODE (op) == PLUS);
5135 for (i = n; i >= 0; --i)
5138 switch (GET_CODE (op))
5143 index = XEXP (op, 0);
5144 scale_rtx = XEXP (op, 1);
5148 if (XINT (op, 1) == UNSPEC_TP
5149 && TARGET_TLS_DIRECT_SEG_REFS
5150 && seg == SEG_DEFAULT)
5151 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
5180 else if (GET_CODE (addr) == MULT)
5182 index = XEXP (addr, 0); /* index*scale */
5183 scale_rtx = XEXP (addr, 1);
5185 else if (GET_CODE (addr) == ASHIFT)
5189 /* We're called for lea too, which implements ashift on occasion. */
5190 index = XEXP (addr, 0);
5191 tmp = XEXP (addr, 1);
5192 if (GET_CODE (tmp) != CONST_INT)
5194 scale = INTVAL (tmp);
5195 if ((unsigned HOST_WIDE_INT) scale > 3)
5201 disp = addr; /* displacement */
5203 /* Extract the integral value of scale. */
5206 if (GET_CODE (scale_rtx) != CONST_INT)
5208 scale = INTVAL (scale_rtx);
5211 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
5212 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
5214 /* Allow arg pointer and stack pointer as index if there is not scaling. */
5215 if (base_reg && index_reg && scale == 1
5216 && (index_reg == arg_pointer_rtx
5217 || index_reg == frame_pointer_rtx
5218 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
5221 tmp = base, base = index, index = tmp;
5222 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
5225 /* Special case: %ebp cannot be encoded as a base without a displacement. */
5226 if ((base_reg == hard_frame_pointer_rtx
5227 || base_reg == frame_pointer_rtx
5228 || base_reg == arg_pointer_rtx) && !disp)
5231 /* Special case: on K6, [%esi] makes the instruction vector decoded.
5232 Avoid this by transforming to [%esi+0]. */
5233 if (ix86_tune == PROCESSOR_K6 && !optimize_size
5234 && base_reg && !index_reg && !disp
5236 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
5239 /* Special case: encode reg+reg instead of reg*2. */
5240 if (!base && index && scale && scale == 2)
5241 base = index, base_reg = index_reg, scale = 1;
5243 /* Special case: scaling cannot be encoded without base or displacement. */
5244 if (!base && !disp && index && scale != 1)
5256 /* Return cost of the memory address x.
5257 For i386, it is better to use a complex address than let gcc copy
5258 the address into a reg and make a new pseudo. But not if the address
5259 requires to two regs - that would mean more pseudos with longer
5262 ix86_address_cost (rtx x)
5264 struct ix86_address parts;
5266 int ok = ix86_decompose_address (x, &parts);
5270 if (parts.base && GET_CODE (parts.base) == SUBREG)
5271 parts.base = SUBREG_REG (parts.base);
5272 if (parts.index && GET_CODE (parts.index) == SUBREG)
5273 parts.index = SUBREG_REG (parts.index);
5275 /* More complex memory references are better. */
5276 if (parts.disp && parts.disp != const0_rtx)
5278 if (parts.seg != SEG_DEFAULT)
5281 /* Attempt to minimize number of registers in the address. */
5283 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
5285 && (!REG_P (parts.index)
5286 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
5290 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
5292 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
5293 && parts.base != parts.index)
5296 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
5297 since it's predecode logic can't detect the length of instructions
5298 and it degenerates to vector decoded. Increase cost of such
5299 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
5300 to split such addresses or even refuse such addresses at all.
5302 Following addressing modes are affected:
5307 The first and last case may be avoidable by explicitly coding the zero in
5308 memory address, but I don't have AMD-K6 machine handy to check this
5312 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
5313 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
5314 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
5320 /* If X is a machine specific address (i.e. a symbol or label being
5321 referenced as a displacement from the GOT implemented using an
5322 UNSPEC), then return the base term. Otherwise return X. */
5325 ix86_find_base_term (rtx x)
5331 if (GET_CODE (x) != CONST)
5334 if (GET_CODE (term) == PLUS
5335 && (GET_CODE (XEXP (term, 1)) == CONST_INT
5336 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
5337 term = XEXP (term, 0);
5338 if (GET_CODE (term) != UNSPEC
5339 || XINT (term, 1) != UNSPEC_GOTPCREL)
5342 term = XVECEXP (term, 0, 0);
5344 if (GET_CODE (term) != SYMBOL_REF
5345 && GET_CODE (term) != LABEL_REF)
5351 term = ix86_delegitimize_address (x);
5353 if (GET_CODE (term) != SYMBOL_REF
5354 && GET_CODE (term) != LABEL_REF)
5360 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
5361 this is used for to form addresses to local data when -fPIC is in
5365 darwin_local_data_pic (rtx disp)
5367 if (GET_CODE (disp) == MINUS)
5369 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
5370 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
5371 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
5373 const char *sym_name = XSTR (XEXP (disp, 1), 0);
5374 if (! strcmp (sym_name, "<pic base>"))
5382 /* Determine if a given RTX is a valid constant. We already know this
5383 satisfies CONSTANT_P. */
5386 legitimate_constant_p (rtx x)
5388 switch (GET_CODE (x))
5393 if (GET_CODE (x) == PLUS)
5395 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5400 if (TARGET_MACHO && darwin_local_data_pic (x))
5403 /* Only some unspecs are valid as "constants". */
5404 if (GET_CODE (x) == UNSPEC)
5405 switch (XINT (x, 1))
5408 return TARGET_64BIT;
5411 return local_exec_symbolic_operand (XVECEXP (x, 0, 0), Pmode);
5413 return local_dynamic_symbolic_operand (XVECEXP (x, 0, 0), Pmode);
5418 /* We must have drilled down to a symbol. */
5419 if (!symbolic_operand (x, Pmode))
5424 /* TLS symbols are never valid. */
5425 if (tls_symbolic_operand (x, Pmode))
5433 /* Otherwise we handle everything else in the move patterns. */
5437 /* Determine if it's legal to put X into the constant pool. This
5438 is not possible for the address of thread-local symbols, which
5439 is checked above. */
5442 ix86_cannot_force_const_mem (rtx x)
5444 return !legitimate_constant_p (x);
5447 /* Determine if a given RTX is a valid constant address. */
5450 constant_address_p (rtx x)
5452 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
5455 /* Nonzero if the constant value X is a legitimate general operand
5456 when generating PIC code. It is given that flag_pic is on and
5457 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
5460 legitimate_pic_operand_p (rtx x)
5464 switch (GET_CODE (x))
5467 inner = XEXP (x, 0);
5468 if (GET_CODE (inner) == PLUS
5469 && GET_CODE (XEXP (inner, 1)) == CONST_INT)
5470 inner = XEXP (inner, 0);
5472 /* Only some unspecs are valid as "constants". */
5473 if (GET_CODE (inner) == UNSPEC)
5474 switch (XINT (inner, 1))
5477 return TARGET_64BIT;
5479 return local_exec_symbolic_operand (XVECEXP (inner, 0, 0), Pmode);
5487 return legitimate_pic_address_disp_p (x);
5494 /* Determine if a given CONST RTX is a valid memory displacement
5498 legitimate_pic_address_disp_p (rtx disp)
5502 /* In 64bit mode we can allow direct addresses of symbols and labels
5503 when they are not dynamic symbols. */
5506 /* TLS references should always be enclosed in UNSPEC. */
5507 if (tls_symbolic_operand (disp, GET_MODE (disp)))
5509 if (GET_CODE (disp) == SYMBOL_REF
5510 && !SYMBOL_REF_FAR_ADDR_P (disp)
5511 && SYMBOL_REF_LOCAL_P (disp))
5513 if (GET_CODE (disp) == LABEL_REF)
5515 if (GET_CODE (disp) == CONST
5516 && GET_CODE (XEXP (disp, 0)) == PLUS)
5518 rtx op0 = XEXP (XEXP (disp, 0), 0);
5519 rtx op1 = XEXP (XEXP (disp, 0), 1);
5521 /* TLS references should always be enclosed in UNSPEC. */
5522 if (tls_symbolic_operand (op0, GET_MODE (op0)))
5524 if (((GET_CODE (op0) == SYMBOL_REF
5525 && !SYMBOL_REF_FAR_ADDR_P (op0)
5526 && SYMBOL_REF_LOCAL_P (op0))
5527 || GET_CODE (op0) == LABEL_REF)
5528 && GET_CODE (op1) == CONST_INT
5529 && INTVAL (op1) < 16*1024*1024
5530 && INTVAL (op1) >= -16*1024*1024)
5534 if (GET_CODE (disp) != CONST)
5536 disp = XEXP (disp, 0);
5540 /* We are unsafe to allow PLUS expressions. This limit allowed distance
5541 of GOT tables. We should not need these anyway. */
5542 if (GET_CODE (disp) != UNSPEC
5543 || (XINT (disp, 1) != UNSPEC_GOTPCREL
5544 && XINT (disp, 1) != UNSPEC_GOTOFF))
5547 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
5548 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
5554 if (GET_CODE (disp) == PLUS)
5556 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
5558 disp = XEXP (disp, 0);
5562 if (TARGET_MACHO && darwin_local_data_pic (disp))
5565 if (GET_CODE (disp) != UNSPEC)
5568 switch (XINT (disp, 1))
5573 return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
5575 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
5576 While ABI specify also 32bit relocation but we don't produce it in
5577 small PIC model at all. */
5578 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
5579 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
5581 return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5583 case UNSPEC_GOTTPOFF:
5584 case UNSPEC_GOTNTPOFF:
5585 case UNSPEC_INDNTPOFF:
5588 return initial_exec_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5590 return local_exec_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5592 return local_dynamic_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5598 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
5599 memory address for an instruction. The MODE argument is the machine mode
5600 for the MEM expression that wants to use this address.
5602 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
5603 convert common non-canonical forms to canonical form so that they will
5607 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
5609 struct ix86_address parts;
5610 rtx base, index, disp;
5611 HOST_WIDE_INT scale;
5612 const char *reason = NULL;
5613 rtx reason_rtx = NULL_RTX;
5615 if (TARGET_DEBUG_ADDR)
5618 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
5619 GET_MODE_NAME (mode), strict);
5623 if (ix86_decompose_address (addr, &parts) <= 0)
5625 reason = "decomposition failed";
5630 index = parts.index;
5632 scale = parts.scale;
5634 /* Validate base register.
5636 Don't allow SUBREG's that span more than a word here. It can lead to spill
5637 failures when the base is one word out of a two word structure, which is
5638 represented internally as a DImode int. */
5647 else if (GET_CODE (base) == SUBREG
5648 && REG_P (SUBREG_REG (base))
5649 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
5651 reg = SUBREG_REG (base);
5654 reason = "base is not a register";
5658 if (GET_MODE (base) != Pmode)
5660 reason = "base is not in Pmode";
5664 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
5665 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
5667 reason = "base is not valid";
5672 /* Validate index register.
5674 Don't allow SUBREG's that span more than a word here -- same as above. */
5683 else if (GET_CODE (index) == SUBREG
5684 && REG_P (SUBREG_REG (index))
5685 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
5687 reg = SUBREG_REG (index);
5690 reason = "index is not a register";
5694 if (GET_MODE (index) != Pmode)
5696 reason = "index is not in Pmode";
5700 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
5701 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
5703 reason = "index is not valid";
5708 /* Validate scale factor. */
5711 reason_rtx = GEN_INT (scale);
5714 reason = "scale without index";
5718 if (scale != 2 && scale != 4 && scale != 8)
5720 reason = "scale is not a valid multiplier";
5725 /* Validate displacement. */
5730 if (GET_CODE (disp) == CONST
5731 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
5732 switch (XINT (XEXP (disp, 0), 1))
5734 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
5735 used. While ABI specify also 32bit relocations, we don't produce
5736 them at all and use IP relative instead. */
5739 gcc_assert (flag_pic);
5741 goto is_legitimate_pic;
5742 reason = "64bit address unspec";
5745 case UNSPEC_GOTPCREL:
5746 gcc_assert (flag_pic);
5747 goto is_legitimate_pic;
5749 case UNSPEC_GOTTPOFF:
5750 case UNSPEC_GOTNTPOFF:
5751 case UNSPEC_INDNTPOFF:
5757 reason = "invalid address unspec";
5761 else if (flag_pic && (SYMBOLIC_CONST (disp)
5763 && !machopic_operand_p (disp)
5768 if (TARGET_64BIT && (index || base))
5770 /* foo@dtpoff(%rX) is ok. */
5771 if (GET_CODE (disp) != CONST
5772 || GET_CODE (XEXP (disp, 0)) != PLUS
5773 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
5774 || GET_CODE (XEXP (XEXP (disp, 0), 1)) != CONST_INT
5775 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
5776 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
5778 reason = "non-constant pic memory reference";
5782 else if (! legitimate_pic_address_disp_p (disp))
5784 reason = "displacement is an invalid pic construct";
5788 /* This code used to verify that a symbolic pic displacement
5789 includes the pic_offset_table_rtx register.
5791 While this is good idea, unfortunately these constructs may
5792 be created by "adds using lea" optimization for incorrect
5801 This code is nonsensical, but results in addressing
5802 GOT table with pic_offset_table_rtx base. We can't
5803 just refuse it easily, since it gets matched by
5804 "addsi3" pattern, that later gets split to lea in the
5805 case output register differs from input. While this
5806 can be handled by separate addsi pattern for this case
5807 that never results in lea, this seems to be easier and
5808 correct fix for crash to disable this test. */
5810 else if (GET_CODE (disp) != LABEL_REF
5811 && GET_CODE (disp) != CONST_INT
5812 && (GET_CODE (disp) != CONST
5813 || !legitimate_constant_p (disp))
5814 && (GET_CODE (disp) != SYMBOL_REF
5815 || !legitimate_constant_p (disp)))
5817 reason = "displacement is not constant";
5820 else if (TARGET_64BIT
5821 && !x86_64_immediate_operand (disp, VOIDmode))
5823 reason = "displacement is out of range";
5828 /* Everything looks valid. */
5829 if (TARGET_DEBUG_ADDR)
5830 fprintf (stderr, "Success.\n");
5834 if (TARGET_DEBUG_ADDR)
5836 fprintf (stderr, "Error: %s\n", reason);
5837 debug_rtx (reason_rtx);
5842 /* Return a unique alias set for the GOT. */
5844 static HOST_WIDE_INT
5845 ix86_GOT_alias_set (void)
5847 static HOST_WIDE_INT set = -1;
5849 set = new_alias_set ();
5853 /* Return a legitimate reference for ORIG (an address) using the
5854 register REG. If REG is 0, a new pseudo is generated.
5856 There are two types of references that must be handled:
5858 1. Global data references must load the address from the GOT, via
5859 the PIC reg. An insn is emitted to do this load, and the reg is
5862 2. Static data references, constant pool addresses, and code labels
5863 compute the address as an offset from the GOT, whose base is in
5864 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
5865 differentiate them from global data objects. The returned
5866 address is the PIC reg + an unspec constant.
5868 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
5869 reg also appears in the address. */
5872 legitimize_pic_address (rtx orig, rtx reg)
5880 reg = gen_reg_rtx (Pmode);
5881 /* Use the generic Mach-O PIC machinery. */
5882 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
5885 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
5887 else if (TARGET_64BIT
5888 && ix86_cmodel != CM_SMALL_PIC
5889 && local_symbolic_operand (addr, Pmode))
5892 /* This symbol may be referenced via a displacement from the PIC
5893 base address (@GOTOFF). */
5895 if (reload_in_progress)
5896 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5897 if (GET_CODE (addr) == CONST)
5898 addr = XEXP (addr, 0);
5899 if (GET_CODE (addr) == PLUS)
5901 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
5902 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
5905 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
5906 new = gen_rtx_CONST (Pmode, new);
5908 tmpreg = gen_reg_rtx (Pmode);
5911 emit_move_insn (tmpreg, new);
5915 new = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
5916 tmpreg, 1, OPTAB_DIRECT);
5919 else new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
5921 else if (!TARGET_64BIT && local_symbolic_operand (addr, Pmode))
5923 /* This symbol may be referenced via a displacement from the PIC
5924 base address (@GOTOFF). */
5926 if (reload_in_progress)
5927 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5928 if (GET_CODE (addr) == CONST)
5929 addr = XEXP (addr, 0);
5930 if (GET_CODE (addr) == PLUS)
5932 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
5933 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
5936 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
5937 new = gen_rtx_CONST (Pmode, new);
5938 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
5942 emit_move_insn (reg, new);
5946 else if (GET_CODE (addr) == SYMBOL_REF)
5950 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
5951 new = gen_rtx_CONST (Pmode, new);
5952 new = gen_const_mem (Pmode, new);
5953 set_mem_alias_set (new, ix86_GOT_alias_set ());
5956 reg = gen_reg_rtx (Pmode);
5957 /* Use directly gen_movsi, otherwise the address is loaded
5958 into register for CSE. We don't want to CSE this addresses,
5959 instead we CSE addresses from the GOT table, so skip this. */
5960 emit_insn (gen_movsi (reg, new));
5965 /* This symbol must be referenced via a load from the
5966 Global Offset Table (@GOT). */
5968 if (reload_in_progress)
5969 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5970 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
5971 new = gen_rtx_CONST (Pmode, new);
5972 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
5973 new = gen_const_mem (Pmode, new);
5974 set_mem_alias_set (new, ix86_GOT_alias_set ());
5977 reg = gen_reg_rtx (Pmode);
5978 emit_move_insn (reg, new);
5984 if (GET_CODE (addr) == CONST)
5986 addr = XEXP (addr, 0);
5988 /* We must match stuff we generate before. Assume the only
5989 unspecs that can get here are ours. Not that we could do
5990 anything with them anyway.... */
5991 if (GET_CODE (addr) == UNSPEC
5992 || (GET_CODE (addr) == PLUS
5993 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
5995 gcc_assert (GET_CODE (addr) == PLUS);
5997 if (GET_CODE (addr) == PLUS)
5999 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
6001 /* Check first to see if this is a constant offset from a @GOTOFF
6002 symbol reference. */
6003 if (local_symbolic_operand (op0, Pmode)
6004 && GET_CODE (op1) == CONST_INT)
6008 if (reload_in_progress)
6009 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6010 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
6012 new = gen_rtx_PLUS (Pmode, new, op1);
6013 new = gen_rtx_CONST (Pmode, new);
6014 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
6018 emit_move_insn (reg, new);
6024 if (INTVAL (op1) < -16*1024*1024
6025 || INTVAL (op1) >= 16*1024*1024)
6026 new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
6031 base = legitimize_pic_address (XEXP (addr, 0), reg);
6032 new = legitimize_pic_address (XEXP (addr, 1),
6033 base == reg ? NULL_RTX : reg);
6035 if (GET_CODE (new) == CONST_INT)
6036 new = plus_constant (base, INTVAL (new));
6039 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
6041 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
6042 new = XEXP (new, 1);
6044 new = gen_rtx_PLUS (Pmode, base, new);
6052 /* Load the thread pointer. If TO_REG is true, force it into a register. */
6055 get_thread_pointer (int to_reg)
6059 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
6063 reg = gen_reg_rtx (Pmode);
6064 insn = gen_rtx_SET (VOIDmode, reg, tp);
6065 insn = emit_insn (insn);
6070 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
6071 false if we expect this to be used for a memory address and true if
6072 we expect to load the address into a register. */
6075 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
6077 rtx dest, base, off, pic;
6082 case TLS_MODEL_GLOBAL_DYNAMIC:
6083 dest = gen_reg_rtx (Pmode);
6086 rtx rax = gen_rtx_REG (Pmode, 0), insns;
6089 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
6090 insns = get_insns ();
6093 emit_libcall_block (insns, dest, rax, x);
6096 emit_insn (gen_tls_global_dynamic_32 (dest, x));
6099 case TLS_MODEL_LOCAL_DYNAMIC:
6100 base = gen_reg_rtx (Pmode);
6103 rtx rax = gen_rtx_REG (Pmode, 0), insns, note;
6106 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
6107 insns = get_insns ();
6110 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
6111 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
6112 emit_libcall_block (insns, base, rax, note);
6115 emit_insn (gen_tls_local_dynamic_base_32 (base));
6117 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
6118 off = gen_rtx_CONST (Pmode, off);
6120 return gen_rtx_PLUS (Pmode, base, off);
6122 case TLS_MODEL_INITIAL_EXEC:
6126 type = UNSPEC_GOTNTPOFF;
6130 if (reload_in_progress)
6131 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6132 pic = pic_offset_table_rtx;
6133 type = TARGET_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
6135 else if (!TARGET_GNU_TLS)
6137 pic = gen_reg_rtx (Pmode);
6138 emit_insn (gen_set_got (pic));
6139 type = UNSPEC_GOTTPOFF;
6144 type = UNSPEC_INDNTPOFF;
6147 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
6148 off = gen_rtx_CONST (Pmode, off);
6150 off = gen_rtx_PLUS (Pmode, pic, off);
6151 off = gen_const_mem (Pmode, off);
6152 set_mem_alias_set (off, ix86_GOT_alias_set ());
6154 if (TARGET_64BIT || TARGET_GNU_TLS)
6156 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6157 off = force_reg (Pmode, off);
6158 return gen_rtx_PLUS (Pmode, base, off);
6162 base = get_thread_pointer (true);
6163 dest = gen_reg_rtx (Pmode);
6164 emit_insn (gen_subsi3 (dest, base, off));
6168 case TLS_MODEL_LOCAL_EXEC:
6169 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
6170 (TARGET_64BIT || TARGET_GNU_TLS)
6171 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
6172 off = gen_rtx_CONST (Pmode, off);
6174 if (TARGET_64BIT || TARGET_GNU_TLS)
6176 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6177 return gen_rtx_PLUS (Pmode, base, off);
6181 base = get_thread_pointer (true);
6182 dest = gen_reg_rtx (Pmode);
6183 emit_insn (gen_subsi3 (dest, base, off));
6194 /* Try machine-dependent ways of modifying an illegitimate address
6195 to be legitimate. If we find one, return the new, valid address.
6196 This macro is used in only one place: `memory_address' in explow.c.
6198 OLDX is the address as it was before break_out_memory_refs was called.
6199 In some cases it is useful to look at this to decide what needs to be done.
6201 MODE and WIN are passed so that this macro can use
6202 GO_IF_LEGITIMATE_ADDRESS.
6204 It is always safe for this macro to do nothing. It exists to recognize
6205 opportunities to optimize the output.
6207 For the 80386, we handle X+REG by loading X into a register R and
6208 using R+REG. R will go in a general reg and indexing will be used.
6209 However, if REG is a broken-out memory address or multiplication,
6210 nothing needs to be done because REG can certainly go in a general reg.
6212 When -fpic is used, special handling is needed for symbolic references.
6213 See comments by legitimize_pic_address in i386.c for details. */
6216 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
6221 if (TARGET_DEBUG_ADDR)
6223 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
6224 GET_MODE_NAME (mode));
6228 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
6230 return legitimize_tls_address (x, log, false);
6231 if (GET_CODE (x) == CONST
6232 && GET_CODE (XEXP (x, 0)) == PLUS
6233 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
6234 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
6236 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
6237 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
6240 if (flag_pic && SYMBOLIC_CONST (x))
6241 return legitimize_pic_address (x, 0);
6243 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
6244 if (GET_CODE (x) == ASHIFT
6245 && GET_CODE (XEXP (x, 1)) == CONST_INT
6246 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
6249 log = INTVAL (XEXP (x, 1));
6250 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
6251 GEN_INT (1 << log));
6254 if (GET_CODE (x) == PLUS)
6256 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
6258 if (GET_CODE (XEXP (x, 0)) == ASHIFT
6259 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6260 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
6263 log = INTVAL (XEXP (XEXP (x, 0), 1));
6264 XEXP (x, 0) = gen_rtx_MULT (Pmode,
6265 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
6266 GEN_INT (1 << log));
6269 if (GET_CODE (XEXP (x, 1)) == ASHIFT
6270 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
6271 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
6274 log = INTVAL (XEXP (XEXP (x, 1), 1));
6275 XEXP (x, 1) = gen_rtx_MULT (Pmode,
6276 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
6277 GEN_INT (1 << log));
6280 /* Put multiply first if it isn't already. */
6281 if (GET_CODE (XEXP (x, 1)) == MULT)
6283 rtx tmp = XEXP (x, 0);
6284 XEXP (x, 0) = XEXP (x, 1);
6289 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
6290 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
6291 created by virtual register instantiation, register elimination, and
6292 similar optimizations. */
6293 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
6296 x = gen_rtx_PLUS (Pmode,
6297 gen_rtx_PLUS (Pmode, XEXP (x, 0),
6298 XEXP (XEXP (x, 1), 0)),
6299 XEXP (XEXP (x, 1), 1));
6303 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
6304 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
6305 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
6306 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
6307 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
6308 && CONSTANT_P (XEXP (x, 1)))
6311 rtx other = NULL_RTX;
6313 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6315 constant = XEXP (x, 1);
6316 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
6318 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
6320 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
6321 other = XEXP (x, 1);
6329 x = gen_rtx_PLUS (Pmode,
6330 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
6331 XEXP (XEXP (XEXP (x, 0), 1), 0)),
6332 plus_constant (other, INTVAL (constant)));
6336 if (changed && legitimate_address_p (mode, x, FALSE))
6339 if (GET_CODE (XEXP (x, 0)) == MULT)
6342 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
6345 if (GET_CODE (XEXP (x, 1)) == MULT)
6348 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
6352 && GET_CODE (XEXP (x, 1)) == REG
6353 && GET_CODE (XEXP (x, 0)) == REG)
6356 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
6359 x = legitimize_pic_address (x, 0);
6362 if (changed && legitimate_address_p (mode, x, FALSE))
6365 if (GET_CODE (XEXP (x, 0)) == REG)
6367 rtx temp = gen_reg_rtx (Pmode);
6368 rtx val = force_operand (XEXP (x, 1), temp);
6370 emit_move_insn (temp, val);
6376 else if (GET_CODE (XEXP (x, 1)) == REG)
6378 rtx temp = gen_reg_rtx (Pmode);
6379 rtx val = force_operand (XEXP (x, 0), temp);
6381 emit_move_insn (temp, val);
6391 /* Print an integer constant expression in assembler syntax. Addition
6392 and subtraction are the only arithmetic that may appear in these
6393 expressions. FILE is the stdio stream to write to, X is the rtx, and
6394 CODE is the operand print code from the output string. */
6397 output_pic_addr_const (FILE *file, rtx x, int code)
6401 switch (GET_CODE (x))
6404 gcc_assert (flag_pic);
6409 assemble_name (file, XSTR (x, 0));
6410 if (!TARGET_MACHO && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
6411 fputs ("@PLT", file);
6418 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
6419 assemble_name (asm_out_file, buf);
6423 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
6427 /* This used to output parentheses around the expression,
6428 but that does not work on the 386 (either ATT or BSD assembler). */
6429 output_pic_addr_const (file, XEXP (x, 0), code);
6433 if (GET_MODE (x) == VOIDmode)
6435 /* We can use %d if the number is <32 bits and positive. */
6436 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
6437 fprintf (file, "0x%lx%08lx",
6438 (unsigned long) CONST_DOUBLE_HIGH (x),
6439 (unsigned long) CONST_DOUBLE_LOW (x));
6441 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
6444 /* We can't handle floating point constants;
6445 PRINT_OPERAND must handle them. */
6446 output_operand_lossage ("floating constant misused");
6450 /* Some assemblers need integer constants to appear first. */
6451 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6453 output_pic_addr_const (file, XEXP (x, 0), code);
6455 output_pic_addr_const (file, XEXP (x, 1), code);
6459 gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT);
6460 output_pic_addr_const (file, XEXP (x, 1), code);
6462 output_pic_addr_const (file, XEXP (x, 0), code);
6468 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
6469 output_pic_addr_const (file, XEXP (x, 0), code);
6471 output_pic_addr_const (file, XEXP (x, 1), code);
6473 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
6477 gcc_assert (XVECLEN (x, 0) == 1);
6478 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
6479 switch (XINT (x, 1))
6482 fputs ("@GOT", file);
6485 fputs ("@GOTOFF", file);
6487 case UNSPEC_GOTPCREL:
6488 fputs ("@GOTPCREL(%rip)", file);
6490 case UNSPEC_GOTTPOFF:
6491 /* FIXME: This might be @TPOFF in Sun ld too. */
6492 fputs ("@GOTTPOFF", file);
6495 fputs ("@TPOFF", file);
6499 fputs ("@TPOFF", file);
6501 fputs ("@NTPOFF", file);
6504 fputs ("@DTPOFF", file);
6506 case UNSPEC_GOTNTPOFF:
6508 fputs ("@GOTTPOFF(%rip)", file);
6510 fputs ("@GOTNTPOFF", file);
6512 case UNSPEC_INDNTPOFF:
6513 fputs ("@INDNTPOFF", file);
6516 output_operand_lossage ("invalid UNSPEC as operand");
6522 output_operand_lossage ("invalid expression as operand");
6526 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6527 We need to emit DTP-relative relocations. */
6530 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
6532 fputs (ASM_LONG, file);
6533 output_addr_const (file, x);
6534 fputs ("@DTPOFF", file);
6540 fputs (", 0", file);
6547 /* In the name of slightly smaller debug output, and to cater to
6548 general assembler lossage, recognize PIC+GOTOFF and turn it back
6549 into a direct symbol reference. */
6552 ix86_delegitimize_address (rtx orig_x)
6556 if (GET_CODE (x) == MEM)
6561 if (GET_CODE (x) != CONST
6562 || GET_CODE (XEXP (x, 0)) != UNSPEC
6563 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
6564 || GET_CODE (orig_x) != MEM)
6566 return XVECEXP (XEXP (x, 0), 0, 0);
6569 if (GET_CODE (x) != PLUS
6570 || GET_CODE (XEXP (x, 1)) != CONST)
6573 if (GET_CODE (XEXP (x, 0)) == REG
6574 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
6575 /* %ebx + GOT/GOTOFF */
6577 else if (GET_CODE (XEXP (x, 0)) == PLUS)
6579 /* %ebx + %reg * scale + GOT/GOTOFF */
6581 if (GET_CODE (XEXP (y, 0)) == REG
6582 && REGNO (XEXP (y, 0)) == PIC_OFFSET_TABLE_REGNUM)
6584 else if (GET_CODE (XEXP (y, 1)) == REG
6585 && REGNO (XEXP (y, 1)) == PIC_OFFSET_TABLE_REGNUM)
6589 if (GET_CODE (y) != REG
6590 && GET_CODE (y) != MULT
6591 && GET_CODE (y) != ASHIFT)
6597 x = XEXP (XEXP (x, 1), 0);
6598 if (GET_CODE (x) == UNSPEC
6599 && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
6600 || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
6603 return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0));
6604 return XVECEXP (x, 0, 0);
6607 if (GET_CODE (x) == PLUS
6608 && GET_CODE (XEXP (x, 0)) == UNSPEC
6609 && GET_CODE (XEXP (x, 1)) == CONST_INT
6610 && ((XINT (XEXP (x, 0), 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
6611 || (XINT (XEXP (x, 0), 1) == UNSPEC_GOTOFF
6612 && GET_CODE (orig_x) != MEM)))
6614 x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
6616 return gen_rtx_PLUS (Pmode, y, x);
6624 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
6629 if (mode == CCFPmode || mode == CCFPUmode)
6631 enum rtx_code second_code, bypass_code;
6632 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
6633 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
6634 code = ix86_fp_compare_code_to_integer (code);
6638 code = reverse_condition (code);
6649 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
6653 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
6654 Those same assemblers have the same but opposite lossage on cmov. */
6655 gcc_assert (mode == CCmode);
6656 suffix = fp ? "nbe" : "a";
6676 gcc_assert (mode == CCmode);
6698 gcc_assert (mode == CCmode);
6699 suffix = fp ? "nb" : "ae";
6702 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
6706 gcc_assert (mode == CCmode);
6710 suffix = fp ? "u" : "p";
6713 suffix = fp ? "nu" : "np";
6718 fputs (suffix, file);
6721 /* Print the name of register X to FILE based on its machine mode and number.
6722 If CODE is 'w', pretend the mode is HImode.
6723 If CODE is 'b', pretend the mode is QImode.
6724 If CODE is 'k', pretend the mode is SImode.
6725 If CODE is 'q', pretend the mode is DImode.
6726 If CODE is 'h', pretend the reg is the 'high' byte register.
6727 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
6730 print_reg (rtx x, int code, FILE *file)
6732 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
6733 && REGNO (x) != FRAME_POINTER_REGNUM
6734 && REGNO (x) != FLAGS_REG
6735 && REGNO (x) != FPSR_REG);
6737 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
6740 if (code == 'w' || MMX_REG_P (x))
6742 else if (code == 'b')
6744 else if (code == 'k')
6746 else if (code == 'q')
6748 else if (code == 'y')
6750 else if (code == 'h')
6753 code = GET_MODE_SIZE (GET_MODE (x));
6755 /* Irritatingly, AMD extended registers use different naming convention
6756 from the normal registers. */
6757 if (REX_INT_REG_P (x))
6759 gcc_assert (TARGET_64BIT);
6763 error ("extended registers have no high halves");
6766 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
6769 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
6772 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
6775 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
6778 error ("unsupported operand size for extended register");
6786 if (STACK_TOP_P (x))
6788 fputs ("st(0)", file);
6795 if (! ANY_FP_REG_P (x))
6796 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
6801 fputs (hi_reg_name[REGNO (x)], file);
6804 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
6806 fputs (qi_reg_name[REGNO (x)], file);
6809 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
6811 fputs (qi_high_reg_name[REGNO (x)], file);
6818 /* Locate some local-dynamic symbol still in use by this function
6819 so that we can print its name in some tls_local_dynamic_base
6823 get_some_local_dynamic_name (void)
6827 if (cfun->machine->some_ld_name)
6828 return cfun->machine->some_ld_name;
6830 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
6832 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
6833 return cfun->machine->some_ld_name;
6839 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
6843 if (GET_CODE (x) == SYMBOL_REF
6844 && local_dynamic_symbolic_operand (x, Pmode))
6846 cfun->machine->some_ld_name = XSTR (x, 0);
6854 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
6855 C -- print opcode suffix for set/cmov insn.
6856 c -- like C, but print reversed condition
6857 F,f -- likewise, but for floating-point.
6858 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
6860 R -- print the prefix for register names.
6861 z -- print the opcode suffix for the size of the current operand.
6862 * -- print a star (in certain assembler syntax)
6863 A -- print an absolute memory reference.
6864 w -- print the operand as if it's a "word" (HImode) even if it isn't.
6865 s -- print a shift double count, followed by the assemblers argument
6867 b -- print the QImode name of the register for the indicated operand.
6868 %b0 would print %al if operands[0] is reg 0.
6869 w -- likewise, print the HImode name of the register.
6870 k -- likewise, print the SImode name of the register.
6871 q -- likewise, print the DImode name of the register.
6872 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
6873 y -- print "st(0)" instead of "st" as a register.
6874 D -- print condition for SSE cmp instruction.
6875 P -- if PIC, print an @PLT suffix.
6876 X -- don't print any sort of PIC '@' suffix for a symbol.
6877 & -- print some in-use local-dynamic symbol name.
6878 H -- print a memory address offset by 8; used for sse high-parts
6882 print_operand (FILE *file, rtx x, int code)
6889 if (ASSEMBLER_DIALECT == ASM_ATT)
6894 assemble_name (file, get_some_local_dynamic_name ());
6898 switch (ASSEMBLER_DIALECT)
6905 /* Intel syntax. For absolute addresses, registers should not
6906 be surrounded by braces. */
6907 if (GET_CODE (x) != REG)
6910 PRINT_OPERAND (file, x, 0);
6920 PRINT_OPERAND (file, x, 0);
6925 if (ASSEMBLER_DIALECT == ASM_ATT)
6930 if (ASSEMBLER_DIALECT == ASM_ATT)
6935 if (ASSEMBLER_DIALECT == ASM_ATT)
6940 if (ASSEMBLER_DIALECT == ASM_ATT)
6945 if (ASSEMBLER_DIALECT == ASM_ATT)
6950 if (ASSEMBLER_DIALECT == ASM_ATT)
6955 /* 387 opcodes don't get size suffixes if the operands are
6957 if (STACK_REG_P (x))
6960 /* Likewise if using Intel opcodes. */
6961 if (ASSEMBLER_DIALECT == ASM_INTEL)
6964 /* This is the size of op from size of operand. */
6965 switch (GET_MODE_SIZE (GET_MODE (x)))
6968 #ifdef HAVE_GAS_FILDS_FISTS
6974 if (GET_MODE (x) == SFmode)
6989 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
6991 #ifdef GAS_MNEMONICS
7017 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
7019 PRINT_OPERAND (file, x, 0);
7025 /* Little bit of braindamage here. The SSE compare instructions
7026 does use completely different names for the comparisons that the
7027 fp conditional moves. */
7028 switch (GET_CODE (x))
7043 fputs ("unord", file);
7047 fputs ("neq", file);
7051 fputs ("nlt", file);
7055 fputs ("nle", file);
7058 fputs ("ord", file);
7065 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7066 if (ASSEMBLER_DIALECT == ASM_ATT)
7068 switch (GET_MODE (x))
7070 case HImode: putc ('w', file); break;
7072 case SFmode: putc ('l', file); break;
7074 case DFmode: putc ('q', file); break;
7075 default: gcc_unreachable ();
7082 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
7085 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7086 if (ASSEMBLER_DIALECT == ASM_ATT)
7089 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
7092 /* Like above, but reverse condition */
7094 /* Check to see if argument to %c is really a constant
7095 and not a condition code which needs to be reversed. */
7096 if (!COMPARISON_P (x))
7098 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
7101 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
7104 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7105 if (ASSEMBLER_DIALECT == ASM_ATT)
7108 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
7112 /* It doesn't actually matter what mode we use here, as we're
7113 only going to use this for printing. */
7114 x = adjust_address_nv (x, DImode, 8);
7121 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
7124 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
7127 int pred_val = INTVAL (XEXP (x, 0));
7129 if (pred_val < REG_BR_PROB_BASE * 45 / 100
7130 || pred_val > REG_BR_PROB_BASE * 55 / 100)
7132 int taken = pred_val > REG_BR_PROB_BASE / 2;
7133 int cputaken = final_forward_branch_p (current_output_insn) == 0;
7135 /* Emit hints only in the case default branch prediction
7136 heuristics would fail. */
7137 if (taken != cputaken)
7139 /* We use 3e (DS) prefix for taken branches and
7140 2e (CS) prefix for not taken branches. */
7142 fputs ("ds ; ", file);
7144 fputs ("cs ; ", file);
7151 output_operand_lossage ("invalid operand code '%c'", code);
7155 if (GET_CODE (x) == REG)
7156 print_reg (x, code, file);
7158 else if (GET_CODE (x) == MEM)
7160 /* No `byte ptr' prefix for call instructions. */
7161 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
7164 switch (GET_MODE_SIZE (GET_MODE (x)))
7166 case 1: size = "BYTE"; break;
7167 case 2: size = "WORD"; break;
7168 case 4: size = "DWORD"; break;
7169 case 8: size = "QWORD"; break;
7170 case 12: size = "XWORD"; break;
7171 case 16: size = "XMMWORD"; break;
7176 /* Check for explicit size override (codes 'b', 'w' and 'k') */
7179 else if (code == 'w')
7181 else if (code == 'k')
7185 fputs (" PTR ", file);
7189 /* Avoid (%rip) for call operands. */
7190 if (CONSTANT_ADDRESS_P (x) && code == 'P'
7191 && GET_CODE (x) != CONST_INT)
7192 output_addr_const (file, x);
7193 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
7194 output_operand_lossage ("invalid constraints for operand");
7199 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
7204 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7205 REAL_VALUE_TO_TARGET_SINGLE (r, l);
7207 if (ASSEMBLER_DIALECT == ASM_ATT)
7209 fprintf (file, "0x%08lx", l);
7212 /* These float cases don't actually occur as immediate operands. */
7213 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
7217 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7218 fprintf (file, "%s", dstr);
7221 else if (GET_CODE (x) == CONST_DOUBLE
7222 && GET_MODE (x) == XFmode)
7226 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7227 fprintf (file, "%s", dstr);
7232 /* We have patterns that allow zero sets of memory, for instance.
7233 In 64-bit mode, we should probably support all 8-byte vectors,
7234 since we can in fact encode that into an immediate. */
7235 if (GET_CODE (x) == CONST_VECTOR)
7237 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
7243 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
7245 if (ASSEMBLER_DIALECT == ASM_ATT)
7248 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
7249 || GET_CODE (x) == LABEL_REF)
7251 if (ASSEMBLER_DIALECT == ASM_ATT)
7254 fputs ("OFFSET FLAT:", file);
7257 if (GET_CODE (x) == CONST_INT)
7258 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7260 output_pic_addr_const (file, x, code);
7262 output_addr_const (file, x);
7266 /* Print a memory operand whose address is ADDR. */
7269 print_operand_address (FILE *file, rtx addr)
7271 struct ix86_address parts;
7272 rtx base, index, disp;
7274 int ok = ix86_decompose_address (addr, &parts);
7279 index = parts.index;
7281 scale = parts.scale;
7289 if (USER_LABEL_PREFIX[0] == 0)
7291 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
7297 if (!base && !index)
7299 /* Displacement only requires special attention. */
7301 if (GET_CODE (disp) == CONST_INT)
7303 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
7305 if (USER_LABEL_PREFIX[0] == 0)
7307 fputs ("ds:", file);
7309 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
7312 output_pic_addr_const (file, disp, 0);
7314 output_addr_const (file, disp);
7316 /* Use one byte shorter RIP relative addressing for 64bit mode. */
7318 && ((GET_CODE (disp) == SYMBOL_REF
7319 && ! tls_symbolic_operand (disp, GET_MODE (disp)))
7320 || GET_CODE (disp) == LABEL_REF
7321 || (GET_CODE (disp) == CONST
7322 && GET_CODE (XEXP (disp, 0)) == PLUS
7323 && (GET_CODE (XEXP (XEXP (disp, 0), 0)) == SYMBOL_REF
7324 || GET_CODE (XEXP (XEXP (disp, 0), 0)) == LABEL_REF)
7325 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)))
7326 fputs ("(%rip)", file);
7330 if (ASSEMBLER_DIALECT == ASM_ATT)
7335 output_pic_addr_const (file, disp, 0);
7336 else if (GET_CODE (disp) == LABEL_REF)
7337 output_asm_label (disp);
7339 output_addr_const (file, disp);
7344 print_reg (base, 0, file);
7348 print_reg (index, 0, file);
7350 fprintf (file, ",%d", scale);
7356 rtx offset = NULL_RTX;
7360 /* Pull out the offset of a symbol; print any symbol itself. */
7361 if (GET_CODE (disp) == CONST
7362 && GET_CODE (XEXP (disp, 0)) == PLUS
7363 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
7365 offset = XEXP (XEXP (disp, 0), 1);
7366 disp = gen_rtx_CONST (VOIDmode,
7367 XEXP (XEXP (disp, 0), 0));
7371 output_pic_addr_const (file, disp, 0);
7372 else if (GET_CODE (disp) == LABEL_REF)
7373 output_asm_label (disp);
7374 else if (GET_CODE (disp) == CONST_INT)
7377 output_addr_const (file, disp);
7383 print_reg (base, 0, file);
7386 if (INTVAL (offset) >= 0)
7388 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
7392 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
7399 print_reg (index, 0, file);
7401 fprintf (file, "*%d", scale);
7409 output_addr_const_extra (FILE *file, rtx x)
7413 if (GET_CODE (x) != UNSPEC)
7416 op = XVECEXP (x, 0, 0);
7417 switch (XINT (x, 1))
7419 case UNSPEC_GOTTPOFF:
7420 output_addr_const (file, op);
7421 /* FIXME: This might be @TPOFF in Sun ld. */
7422 fputs ("@GOTTPOFF", file);
7425 output_addr_const (file, op);
7426 fputs ("@TPOFF", file);
7429 output_addr_const (file, op);
7431 fputs ("@TPOFF", file);
7433 fputs ("@NTPOFF", file);
7436 output_addr_const (file, op);
7437 fputs ("@DTPOFF", file);
7439 case UNSPEC_GOTNTPOFF:
7440 output_addr_const (file, op);
7442 fputs ("@GOTTPOFF(%rip)", file);
7444 fputs ("@GOTNTPOFF", file);
7446 case UNSPEC_INDNTPOFF:
7447 output_addr_const (file, op);
7448 fputs ("@INDNTPOFF", file);
7458 /* Split one or more DImode RTL references into pairs of SImode
7459 references. The RTL can be REG, offsettable MEM, integer constant, or
7460 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
7461 split and "num" is its length. lo_half and hi_half are output arrays
7462 that parallel "operands". */
7465 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
7469 rtx op = operands[num];
7471 /* simplify_subreg refuse to split volatile memory addresses,
7472 but we still have to handle it. */
7473 if (GET_CODE (op) == MEM)
7475 lo_half[num] = adjust_address (op, SImode, 0);
7476 hi_half[num] = adjust_address (op, SImode, 4);
7480 lo_half[num] = simplify_gen_subreg (SImode, op,
7481 GET_MODE (op) == VOIDmode
7482 ? DImode : GET_MODE (op), 0);
7483 hi_half[num] = simplify_gen_subreg (SImode, op,
7484 GET_MODE (op) == VOIDmode
7485 ? DImode : GET_MODE (op), 4);
7489 /* Split one or more TImode RTL references into pairs of DImode
7490 references. The RTL can be REG, offsettable MEM, integer constant, or
7491 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
7492 split and "num" is its length. lo_half and hi_half are output arrays
7493 that parallel "operands". */
7496 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
7500 rtx op = operands[num];
7502 /* simplify_subreg refuse to split volatile memory addresses, but we
7503 still have to handle it. */
7504 if (GET_CODE (op) == MEM)
7506 lo_half[num] = adjust_address (op, DImode, 0);
7507 hi_half[num] = adjust_address (op, DImode, 8);
7511 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
7512 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
7517 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
7518 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
7519 is the expression of the binary operation. The output may either be
7520 emitted here, or returned to the caller, like all output_* functions.
7522 There is no guarantee that the operands are the same mode, as they
7523 might be within FLOAT or FLOAT_EXTEND expressions. */
7525 #ifndef SYSV386_COMPAT
7526 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
7527 wants to fix the assemblers because that causes incompatibility
7528 with gcc. No-one wants to fix gcc because that causes
7529 incompatibility with assemblers... You can use the option of
7530 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
7531 #define SYSV386_COMPAT 1
7535 output_387_binary_op (rtx insn, rtx *operands)
7537 static char buf[30];
7540 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
7542 #ifdef ENABLE_CHECKING
7543 /* Even if we do not want to check the inputs, this documents input
7544 constraints. Which helps in understanding the following code. */
7545 if (STACK_REG_P (operands[0])
7546 && ((REG_P (operands[1])
7547 && REGNO (operands[0]) == REGNO (operands[1])
7548 && (STACK_REG_P (operands[2]) || GET_CODE (operands[2]) == MEM))
7549 || (REG_P (operands[2])
7550 && REGNO (operands[0]) == REGNO (operands[2])
7551 && (STACK_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)))
7552 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
7555 gcc_assert (is_sse);
7558 switch (GET_CODE (operands[3]))
7561 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7562 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7570 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7571 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7579 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7580 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7588 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7589 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7603 if (GET_MODE (operands[0]) == SFmode)
7604 strcat (buf, "ss\t{%2, %0|%0, %2}");
7606 strcat (buf, "sd\t{%2, %0|%0, %2}");
7611 switch (GET_CODE (operands[3]))
7615 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
7617 rtx temp = operands[2];
7618 operands[2] = operands[1];
7622 /* know operands[0] == operands[1]. */
7624 if (GET_CODE (operands[2]) == MEM)
7630 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
7632 if (STACK_TOP_P (operands[0]))
7633 /* How is it that we are storing to a dead operand[2]?
7634 Well, presumably operands[1] is dead too. We can't
7635 store the result to st(0) as st(0) gets popped on this
7636 instruction. Instead store to operands[2] (which I
7637 think has to be st(1)). st(1) will be popped later.
7638 gcc <= 2.8.1 didn't have this check and generated
7639 assembly code that the Unixware assembler rejected. */
7640 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7642 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7646 if (STACK_TOP_P (operands[0]))
7647 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7649 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7654 if (GET_CODE (operands[1]) == MEM)
7660 if (GET_CODE (operands[2]) == MEM)
7666 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
7669 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
7670 derived assemblers, confusingly reverse the direction of
7671 the operation for fsub{r} and fdiv{r} when the
7672 destination register is not st(0). The Intel assembler
7673 doesn't have this brain damage. Read !SYSV386_COMPAT to
7674 figure out what the hardware really does. */
7675 if (STACK_TOP_P (operands[0]))
7676 p = "{p\t%0, %2|rp\t%2, %0}";
7678 p = "{rp\t%2, %0|p\t%0, %2}";
7680 if (STACK_TOP_P (operands[0]))
7681 /* As above for fmul/fadd, we can't store to st(0). */
7682 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7684 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7689 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
7692 if (STACK_TOP_P (operands[0]))
7693 p = "{rp\t%0, %1|p\t%1, %0}";
7695 p = "{p\t%1, %0|rp\t%0, %1}";
7697 if (STACK_TOP_P (operands[0]))
7698 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
7700 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
7705 if (STACK_TOP_P (operands[0]))
7707 if (STACK_TOP_P (operands[1]))
7708 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7710 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
7713 else if (STACK_TOP_P (operands[1]))
7716 p = "{\t%1, %0|r\t%0, %1}";
7718 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
7724 p = "{r\t%2, %0|\t%0, %2}";
7726 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7739 /* Return needed mode for entity in optimize_mode_switching pass. */
7742 ix86_mode_needed (int entity, rtx insn)
7744 enum attr_i387_cw mode;
7746 /* The mode UNINITIALIZED is used to store control word after a
7747 function call or ASM pattern. The mode ANY specify that function
7748 has no requirements on the control word and make no changes in the
7749 bits we are interested in. */
7752 || (NONJUMP_INSN_P (insn)
7753 && (asm_noperands (PATTERN (insn)) >= 0
7754 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
7755 return I387_CW_UNINITIALIZED;
7757 if (recog_memoized (insn) < 0)
7760 mode = get_attr_i387_cw (insn);
7765 if (mode == I387_CW_TRUNC)
7770 if (mode == I387_CW_FLOOR)
7775 if (mode == I387_CW_CEIL)
7780 if (mode == I387_CW_MASK_PM)
7791 /* Output code to initialize control word copies used by trunc?f?i and
7792 rounding patterns. CURRENT_MODE is set to current control word,
7793 while NEW_MODE is set to new control word. */
7796 emit_i387_cw_initialization (int mode)
7798 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
7803 rtx reg = gen_reg_rtx (HImode);
7805 emit_insn (gen_x86_fnstcw_1 (stored_mode));
7806 emit_move_insn (reg, stored_mode);
7808 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
7813 /* round toward zero (truncate) */
7814 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
7815 slot = SLOT_CW_TRUNC;
7819 /* round down toward -oo */
7820 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
7821 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
7822 slot = SLOT_CW_FLOOR;
7826 /* round up toward +oo */
7827 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
7828 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
7829 slot = SLOT_CW_CEIL;
7832 case I387_CW_MASK_PM:
7833 /* mask precision exception for nearbyint() */
7834 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
7835 slot = SLOT_CW_MASK_PM;
7847 /* round toward zero (truncate) */
7848 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
7849 slot = SLOT_CW_TRUNC;
7853 /* round down toward -oo */
7854 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
7855 slot = SLOT_CW_FLOOR;
7859 /* round up toward +oo */
7860 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
7861 slot = SLOT_CW_CEIL;
7864 case I387_CW_MASK_PM:
7865 /* mask precision exception for nearbyint() */
7866 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
7867 slot = SLOT_CW_MASK_PM;
7875 gcc_assert (slot < MAX_386_STACK_LOCALS);
7877 new_mode = assign_386_stack_local (HImode, slot);
7878 emit_move_insn (new_mode, reg);
7881 /* Output code for INSN to convert a float to a signed int. OPERANDS
7882 are the insn operands. The output may be [HSD]Imode and the input
7883 operand may be [SDX]Fmode. */
7886 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
7888 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
7889 int dimode_p = GET_MODE (operands[0]) == DImode;
7890 int round_mode = get_attr_i387_cw (insn);
7892 /* Jump through a hoop or two for DImode, since the hardware has no
7893 non-popping instruction. We used to do this a different way, but
7894 that was somewhat fragile and broke with post-reload splitters. */
7895 if ((dimode_p || fisttp) && !stack_top_dies)
7896 output_asm_insn ("fld\t%y1", operands);
7898 gcc_assert (STACK_TOP_P (operands[1]));
7899 gcc_assert (GET_CODE (operands[0]) == MEM);
7902 output_asm_insn ("fisttp%z0\t%0", operands);
7905 if (round_mode != I387_CW_ANY)
7906 output_asm_insn ("fldcw\t%3", operands);
7907 if (stack_top_dies || dimode_p)
7908 output_asm_insn ("fistp%z0\t%0", operands);
7910 output_asm_insn ("fist%z0\t%0", operands);
7911 if (round_mode != I387_CW_ANY)
7912 output_asm_insn ("fldcw\t%2", operands);
7918 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
7919 should be used. UNORDERED_P is true when fucom should be used. */
7922 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
7925 rtx cmp_op0, cmp_op1;
7926 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
7930 cmp_op0 = operands[0];
7931 cmp_op1 = operands[1];
7935 cmp_op0 = operands[1];
7936 cmp_op1 = operands[2];
7941 if (GET_MODE (operands[0]) == SFmode)
7943 return "ucomiss\t{%1, %0|%0, %1}";
7945 return "comiss\t{%1, %0|%0, %1}";
7948 return "ucomisd\t{%1, %0|%0, %1}";
7950 return "comisd\t{%1, %0|%0, %1}";
7953 gcc_assert (STACK_TOP_P (cmp_op0));
7955 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
7957 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
7961 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
7962 return TARGET_USE_FFREEP ? "ffreep\t%y1" : "fstp\t%y1";
7965 return "ftst\n\tfnstsw\t%0";
7968 if (STACK_REG_P (cmp_op1)
7970 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
7971 && REGNO (cmp_op1) != FIRST_STACK_REG)
7973 /* If both the top of the 387 stack dies, and the other operand
7974 is also a stack register that dies, then this must be a
7975 `fcompp' float compare */
7979 /* There is no double popping fcomi variant. Fortunately,
7980 eflags is immune from the fstp's cc clobbering. */
7982 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
7984 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
7985 return TARGET_USE_FFREEP ? "ffreep\t%y0" : "fstp\t%y0";
7990 return "fucompp\n\tfnstsw\t%0";
7992 return "fcompp\n\tfnstsw\t%0";
7997 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
7999 static const char * const alt[16] =
8001 "fcom%z2\t%y2\n\tfnstsw\t%0",
8002 "fcomp%z2\t%y2\n\tfnstsw\t%0",
8003 "fucom%z2\t%y2\n\tfnstsw\t%0",
8004 "fucomp%z2\t%y2\n\tfnstsw\t%0",
8006 "ficom%z2\t%y2\n\tfnstsw\t%0",
8007 "ficomp%z2\t%y2\n\tfnstsw\t%0",
8011 "fcomi\t{%y1, %0|%0, %y1}",
8012 "fcomip\t{%y1, %0|%0, %y1}",
8013 "fucomi\t{%y1, %0|%0, %y1}",
8014 "fucomip\t{%y1, %0|%0, %y1}",
8025 mask = eflags_p << 3;
8026 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
8027 mask |= unordered_p << 1;
8028 mask |= stack_top_dies;
8030 gcc_assert (mask < 16);
8039 ix86_output_addr_vec_elt (FILE *file, int value)
8041 const char *directive = ASM_LONG;
8045 directive = ASM_QUAD;
8047 gcc_assert (!TARGET_64BIT);
8050 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
8054 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
8057 fprintf (file, "%s%s%d-%s%d\n",
8058 ASM_LONG, LPREFIX, value, LPREFIX, rel);
8059 else if (HAVE_AS_GOTOFF_IN_DATA)
8060 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
8062 else if (TARGET_MACHO)
8064 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
8065 machopic_output_function_base_name (file);
8066 fprintf(file, "\n");
8070 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
8071 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
8074 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
8078 ix86_expand_clear (rtx dest)
8082 /* We play register width games, which are only valid after reload. */
8083 gcc_assert (reload_completed);
8085 /* Avoid HImode and its attendant prefix byte. */
8086 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
8087 dest = gen_rtx_REG (SImode, REGNO (dest));
8089 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
8091 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
8092 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
8094 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, 17));
8095 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
8101 /* X is an unchanging MEM. If it is a constant pool reference, return
8102 the constant pool rtx, else NULL. */
8105 maybe_get_pool_constant (rtx x)
8107 x = ix86_delegitimize_address (XEXP (x, 0));
8109 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
8110 return get_pool_constant (x);
8116 ix86_expand_move (enum machine_mode mode, rtx operands[])
8118 int strict = (reload_in_progress || reload_completed);
8120 enum tls_model model;
8125 if (GET_CODE (op1) == SYMBOL_REF)
8127 model = SYMBOL_REF_TLS_MODEL (op1);
8130 op1 = legitimize_tls_address (op1, model, true);
8131 op1 = force_operand (op1, op0);
8136 else if (GET_CODE (op1) == CONST
8137 && GET_CODE (XEXP (op1, 0)) == PLUS
8138 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
8140 model = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (op1, 0), 0));
8143 rtx addend = XEXP (XEXP (op1, 0), 1);
8144 op1 = legitimize_tls_address (XEXP (XEXP (op1, 0), 0), model, true);
8145 op1 = force_operand (op1, NULL);
8146 op1 = expand_simple_binop (Pmode, PLUS, op1, addend,
8147 op0, 1, OPTAB_DIRECT);
8153 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
8158 rtx temp = ((reload_in_progress
8159 || ((op0 && GET_CODE (op0) == REG)
8161 ? op0 : gen_reg_rtx (Pmode));
8162 op1 = machopic_indirect_data_reference (op1, temp);
8163 op1 = machopic_legitimize_pic_address (op1, mode,
8164 temp == op1 ? 0 : temp);
8166 else if (MACHOPIC_INDIRECT)
8167 op1 = machopic_indirect_data_reference (op1, 0);
8171 if (GET_CODE (op0) == MEM)
8172 op1 = force_reg (Pmode, op1);
8174 op1 = legitimize_address (op1, op1, Pmode);
8175 #endif /* TARGET_MACHO */
8179 if (GET_CODE (op0) == MEM
8180 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
8181 || !push_operand (op0, mode))
8182 && GET_CODE (op1) == MEM)
8183 op1 = force_reg (mode, op1);
8185 if (push_operand (op0, mode)
8186 && ! general_no_elim_operand (op1, mode))
8187 op1 = copy_to_mode_reg (mode, op1);
8189 /* Force large constants in 64bit compilation into register
8190 to get them CSEed. */
8191 if (TARGET_64BIT && mode == DImode
8192 && immediate_operand (op1, mode)
8193 && !x86_64_zext_immediate_operand (op1, VOIDmode)
8194 && !register_operand (op0, mode)
8195 && optimize && !reload_completed && !reload_in_progress)
8196 op1 = copy_to_mode_reg (mode, op1);
8198 if (FLOAT_MODE_P (mode))
8200 /* If we are loading a floating point constant to a register,
8201 force the value to memory now, since we'll get better code
8202 out the back end. */
8206 else if (GET_CODE (op1) == CONST_DOUBLE)
8208 op1 = validize_mem (force_const_mem (mode, op1));
8209 if (!register_operand (op0, mode))
8211 rtx temp = gen_reg_rtx (mode);
8212 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
8213 emit_move_insn (op0, temp);
8220 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8224 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
8226 rtx op0 = operands[0], op1 = operands[1];
8228 /* Force constants other than zero into memory. We do not know how
8229 the instructions used to build constants modify the upper 64 bits
8230 of the register, once we have that information we may be able
8231 to handle some of them more efficiently. */
8232 if ((reload_in_progress | reload_completed) == 0
8233 && register_operand (op0, mode)
8234 && CONSTANT_P (op1) && op1 != CONST0_RTX (mode))
8235 op1 = validize_mem (force_const_mem (mode, op1));
8237 /* Make operand1 a register if it isn't already. */
8239 && !register_operand (op0, mode)
8240 && !register_operand (op1, mode))
8242 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
8246 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8249 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
8250 straight to ix86_expand_vector_move. */
8253 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
8262 /* If we're optimizing for size, movups is the smallest. */
8265 op0 = gen_lowpart (V4SFmode, op0);
8266 op1 = gen_lowpart (V4SFmode, op1);
8267 emit_insn (gen_sse_movups (op0, op1));
8271 /* ??? If we have typed data, then it would appear that using
8272 movdqu is the only way to get unaligned data loaded with
8274 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8276 op0 = gen_lowpart (V16QImode, op0);
8277 op1 = gen_lowpart (V16QImode, op1);
8278 emit_insn (gen_sse2_movdqu (op0, op1));
8282 if (TARGET_SSE2 && mode == V2DFmode)
8286 /* When SSE registers are split into halves, we can avoid
8287 writing to the top half twice. */
8288 if (TARGET_SSE_SPLIT_REGS)
8290 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8295 /* ??? Not sure about the best option for the Intel chips.
8296 The following would seem to satisfy; the register is
8297 entirely cleared, breaking the dependency chain. We
8298 then store to the upper half, with a dependency depth
8299 of one. A rumor has it that Intel recommends two movsd
8300 followed by an unpacklpd, but this is unconfirmed. And
8301 given that the dependency depth of the unpacklpd would
8302 still be one, I'm not sure why this would be better. */
8303 zero = CONST0_RTX (V2DFmode);
8306 m = adjust_address (op1, DFmode, 0);
8307 emit_insn (gen_sse2_loadlpd (op0, zero, m));
8308 m = adjust_address (op1, DFmode, 8);
8309 emit_insn (gen_sse2_loadhpd (op0, op0, m));
8313 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
8314 emit_move_insn (op0, CONST0_RTX (mode));
8316 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8318 if (mode != V4SFmode)
8319 op0 = gen_lowpart (V4SFmode, op0);
8320 m = adjust_address (op1, V2SFmode, 0);
8321 emit_insn (gen_sse_loadlps (op0, op0, m));
8322 m = adjust_address (op1, V2SFmode, 8);
8323 emit_insn (gen_sse_loadhps (op0, op0, m));
8326 else if (MEM_P (op0))
8328 /* If we're optimizing for size, movups is the smallest. */
8331 op0 = gen_lowpart (V4SFmode, op0);
8332 op1 = gen_lowpart (V4SFmode, op1);
8333 emit_insn (gen_sse_movups (op0, op1));
8337 /* ??? Similar to above, only less clear because of quote
8338 typeless stores unquote. */
8339 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
8340 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8342 op0 = gen_lowpart (V16QImode, op0);
8343 op1 = gen_lowpart (V16QImode, op1);
8344 emit_insn (gen_sse2_movdqu (op0, op1));
8348 if (TARGET_SSE2 && mode == V2DFmode)
8350 m = adjust_address (op0, DFmode, 0);
8351 emit_insn (gen_sse2_storelpd (m, op1));
8352 m = adjust_address (op0, DFmode, 8);
8353 emit_insn (gen_sse2_storehpd (m, op1));
8357 if (mode != V4SFmode)
8358 op1 = gen_lowpart (V4SFmode, op1);
8359 m = adjust_address (op0, V2SFmode, 0);
8360 emit_insn (gen_sse_storelps (m, op1));
8361 m = adjust_address (op0, V2SFmode, 8);
8362 emit_insn (gen_sse_storehps (m, op1));
8369 /* Expand a push in MODE. This is some mode for which we do not support
8370 proper push instructions, at least from the registers that we expect
8371 the value to live in. */
8374 ix86_expand_push (enum machine_mode mode, rtx x)
8378 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
8379 GEN_INT (-GET_MODE_SIZE (mode)),
8380 stack_pointer_rtx, 1, OPTAB_DIRECT);
8381 if (tmp != stack_pointer_rtx)
8382 emit_move_insn (stack_pointer_rtx, tmp);
8384 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
8385 emit_move_insn (tmp, x);
8388 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
8389 destination to use for the operation. If different from the true
8390 destination in operands[0], a copy operation will be required. */
8393 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
8396 int matching_memory;
8397 rtx src1, src2, dst;
8403 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
8404 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8405 && (rtx_equal_p (dst, src2)
8406 || immediate_operand (src1, mode)))
8413 /* If the destination is memory, and we do not have matching source
8414 operands, do things in registers. */
8415 matching_memory = 0;
8416 if (GET_CODE (dst) == MEM)
8418 if (rtx_equal_p (dst, src1))
8419 matching_memory = 1;
8420 else if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8421 && rtx_equal_p (dst, src2))
8422 matching_memory = 2;
8424 dst = gen_reg_rtx (mode);
8427 /* Both source operands cannot be in memory. */
8428 if (GET_CODE (src1) == MEM && GET_CODE (src2) == MEM)
8430 if (matching_memory != 2)
8431 src2 = force_reg (mode, src2);
8433 src1 = force_reg (mode, src1);
8436 /* If the operation is not commutable, source 1 cannot be a constant
8437 or non-matching memory. */
8438 if ((CONSTANT_P (src1)
8439 || (!matching_memory && GET_CODE (src1) == MEM))
8440 && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
8441 src1 = force_reg (mode, src1);
8443 src1 = operands[1] = src1;
8444 src2 = operands[2] = src2;
8448 /* Similarly, but assume that the destination has already been
8452 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
8453 enum machine_mode mode, rtx operands[])
8455 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
8456 gcc_assert (dst == operands[0]);
8459 /* Attempt to expand a binary operator. Make the expansion closer to the
8460 actual machine, then just general_operand, which will allow 3 separate
8461 memory references (one output, two input) in a single insn. */
8464 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
8467 rtx src1, src2, dst, op, clob;
8469 dst = ix86_fixup_binary_operands (code, mode, operands);
8473 /* Emit the instruction. */
8475 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
8476 if (reload_in_progress)
8478 /* Reload doesn't know about the flags register, and doesn't know that
8479 it doesn't want to clobber it. We can only do this with PLUS. */
8480 gcc_assert (code == PLUS);
8485 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8486 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
8489 /* Fix up the destination if needed. */
8490 if (dst != operands[0])
8491 emit_move_insn (operands[0], dst);
8494 /* Return TRUE or FALSE depending on whether the binary operator meets the
8495 appropriate constraints. */
8498 ix86_binary_operator_ok (enum rtx_code code,
8499 enum machine_mode mode ATTRIBUTE_UNUSED,
8502 /* Both source operands cannot be in memory. */
8503 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
8505 /* If the operation is not commutable, source 1 cannot be a constant. */
8506 if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
8508 /* If the destination is memory, we must have a matching source operand. */
8509 if (GET_CODE (operands[0]) == MEM
8510 && ! (rtx_equal_p (operands[0], operands[1])
8511 || (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8512 && rtx_equal_p (operands[0], operands[2]))))
8514 /* If the operation is not commutable and the source 1 is memory, we must
8515 have a matching destination. */
8516 if (GET_CODE (operands[1]) == MEM
8517 && GET_RTX_CLASS (code) != RTX_COMM_ARITH
8518 && ! rtx_equal_p (operands[0], operands[1]))
8523 /* Attempt to expand a unary operator. Make the expansion closer to the
8524 actual machine, then just general_operand, which will allow 2 separate
8525 memory references (one output, one input) in a single insn. */
8528 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
8531 int matching_memory;
8532 rtx src, dst, op, clob;
8537 /* If the destination is memory, and we do not have matching source
8538 operands, do things in registers. */
8539 matching_memory = 0;
8542 if (rtx_equal_p (dst, src))
8543 matching_memory = 1;
8545 dst = gen_reg_rtx (mode);
8548 /* When source operand is memory, destination must match. */
8549 if (MEM_P (src) && !matching_memory)
8550 src = force_reg (mode, src);
8552 /* Emit the instruction. */
8554 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
8555 if (reload_in_progress || code == NOT)
8557 /* Reload doesn't know about the flags register, and doesn't know that
8558 it doesn't want to clobber it. */
8559 gcc_assert (code == NOT);
8564 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8565 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
8568 /* Fix up the destination if needed. */
8569 if (dst != operands[0])
8570 emit_move_insn (operands[0], dst);
8573 /* Return TRUE or FALSE depending on whether the unary operator meets the
8574 appropriate constraints. */
8577 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
8578 enum machine_mode mode ATTRIBUTE_UNUSED,
8579 rtx operands[2] ATTRIBUTE_UNUSED)
8581 /* If one of operands is memory, source and destination must match. */
8582 if ((GET_CODE (operands[0]) == MEM
8583 || GET_CODE (operands[1]) == MEM)
8584 && ! rtx_equal_p (operands[0], operands[1]))
8589 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
8590 Create a mask for the sign bit in MODE for an SSE register. If VECT is
8591 true, then replicate the mask for all elements of the vector register.
8592 If INVERT is true, then create a mask excluding the sign bit. */
8595 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
8597 enum machine_mode vec_mode;
8598 HOST_WIDE_INT hi, lo;
8603 /* Find the sign bit, sign extended to 2*HWI. */
8605 lo = 0x80000000, hi = lo < 0;
8606 else if (HOST_BITS_PER_WIDE_INT >= 64)
8607 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
8609 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
8614 /* Force this value into the low part of a fp vector constant. */
8615 mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode);
8616 mask = gen_lowpart (mode, mask);
8621 v = gen_rtvec (4, mask, mask, mask, mask);
8623 v = gen_rtvec (4, mask, CONST0_RTX (SFmode),
8624 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
8625 vec_mode = V4SFmode;
8630 v = gen_rtvec (2, mask, mask);
8632 v = gen_rtvec (2, mask, CONST0_RTX (DFmode));
8633 vec_mode = V2DFmode;
8636 return force_reg (vec_mode, gen_rtx_CONST_VECTOR (vec_mode, v));
8639 /* Generate code for floating point ABS or NEG. */
8642 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
8645 rtx mask, set, use, clob, dst, src;
8646 bool matching_memory;
8647 bool use_sse = false;
8648 bool vector_mode = VECTOR_MODE_P (mode);
8649 enum machine_mode elt_mode = mode;
8653 elt_mode = GET_MODE_INNER (mode);
8656 else if (TARGET_SSE_MATH)
8657 use_sse = SSE_FLOAT_MODE_P (mode);
8659 /* NEG and ABS performed with SSE use bitwise mask operations.
8660 Create the appropriate mask now. */
8662 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
8665 /* When not using SSE, we don't use the mask, but prefer to keep the
8666 same general form of the insn pattern to reduce duplication when
8667 it comes time to split. */
8674 /* If the destination is memory, and we don't have matching source
8675 operands, do things in registers. */
8676 matching_memory = false;
8679 if (rtx_equal_p (dst, src))
8680 matching_memory = true;
8682 dst = gen_reg_rtx (mode);
8684 if (MEM_P (src) && !matching_memory)
8685 src = force_reg (mode, src);
8689 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
8690 set = gen_rtx_SET (VOIDmode, dst, set);
8695 set = gen_rtx_fmt_e (code, mode, src);
8696 set = gen_rtx_SET (VOIDmode, dst, set);
8697 use = gen_rtx_USE (VOIDmode, mask);
8698 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8699 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, set, use, clob)));
8702 if (dst != operands[0])
8703 emit_move_insn (operands[0], dst);
8706 /* Expand a copysign operation. Special case operand 0 being a constant. */
8709 ix86_expand_copysign (rtx operands[])
8711 enum machine_mode mode, vmode;
8712 rtx dest, op0, op1, mask, nmask;
8718 mode = GET_MODE (dest);
8719 vmode = mode == SFmode ? V4SFmode : V2DFmode;
8721 if (GET_CODE (op0) == CONST_DOUBLE)
8725 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
8726 op0 = simplify_unary_operation (ABS, mode, op0, mode);
8728 if (op0 == CONST0_RTX (mode))
8729 op0 = CONST0_RTX (vmode);
8733 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
8734 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
8736 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
8737 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
8740 mask = ix86_build_signbit_mask (mode, 0, 0);
8743 emit_insn (gen_copysignsf3_const (dest, op0, op1, mask));
8745 emit_insn (gen_copysigndf3_const (dest, op0, op1, mask));
8749 nmask = ix86_build_signbit_mask (mode, 0, 1);
8750 mask = ix86_build_signbit_mask (mode, 0, 0);
8753 emit_insn (gen_copysignsf3_var (dest, NULL, op0, op1, nmask, mask));
8755 emit_insn (gen_copysigndf3_var (dest, NULL, op0, op1, nmask, mask));
8759 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
8760 be a constant, and so has already been expanded into a vector constant. */
8763 ix86_split_copysign_const (rtx operands[])
8765 enum machine_mode mode, vmode;
8766 rtx dest, op0, op1, mask, x;
8773 mode = GET_MODE (dest);
8774 vmode = GET_MODE (mask);
8776 dest = simplify_gen_subreg (vmode, dest, mode, 0);
8777 x = gen_rtx_AND (vmode, dest, mask);
8778 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8780 if (op0 != CONST0_RTX (vmode))
8782 x = gen_rtx_IOR (vmode, dest, op0);
8783 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8787 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
8788 so we have to do two masks. */
8791 ix86_split_copysign_var (rtx operands[])
8793 enum machine_mode mode, vmode;
8794 rtx dest, scratch, op0, op1, mask, nmask, x;
8797 scratch = operands[1];
8800 nmask = operands[4];
8803 mode = GET_MODE (dest);
8804 vmode = GET_MODE (mask);
8806 if (rtx_equal_p (op0, op1))
8808 /* Shouldn't happen often (it's useless, obviously), but when it does
8809 we'd generate incorrect code if we continue below. */
8810 emit_move_insn (dest, op0);
8814 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
8816 gcc_assert (REGNO (op1) == REGNO (scratch));
8818 x = gen_rtx_AND (vmode, scratch, mask);
8819 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
8822 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
8823 x = gen_rtx_NOT (vmode, dest);
8824 x = gen_rtx_AND (vmode, x, op0);
8825 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8829 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
8831 x = gen_rtx_AND (vmode, scratch, mask);
8833 else /* alternative 2,4 */
8835 gcc_assert (REGNO (mask) == REGNO (scratch));
8836 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
8837 x = gen_rtx_AND (vmode, scratch, op1);
8839 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
8841 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
8843 dest = simplify_gen_subreg (vmode, op0, mode, 0);
8844 x = gen_rtx_AND (vmode, dest, nmask);
8846 else /* alternative 3,4 */
8848 gcc_assert (REGNO (nmask) == REGNO (dest));
8850 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
8851 x = gen_rtx_AND (vmode, dest, op0);
8853 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8856 x = gen_rtx_IOR (vmode, dest, scratch);
8857 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8860 /* Return TRUE or FALSE depending on whether the first SET in INSN
8861 has source and destination with matching CC modes, and that the
8862 CC mode is at least as constrained as REQ_MODE. */
8865 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
8868 enum machine_mode set_mode;
8870 set = PATTERN (insn);
8871 if (GET_CODE (set) == PARALLEL)
8872 set = XVECEXP (set, 0, 0);
8873 gcc_assert (GET_CODE (set) == SET);
8874 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
8876 set_mode = GET_MODE (SET_DEST (set));
8880 if (req_mode != CCNOmode
8881 && (req_mode != CCmode
8882 || XEXP (SET_SRC (set), 1) != const0_rtx))
8886 if (req_mode == CCGCmode)
8890 if (req_mode == CCGOCmode || req_mode == CCNOmode)
8894 if (req_mode == CCZmode)
8904 return (GET_MODE (SET_SRC (set)) == set_mode);
8907 /* Generate insn patterns to do an integer compare of OPERANDS. */
8910 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
8912 enum machine_mode cmpmode;
8915 cmpmode = SELECT_CC_MODE (code, op0, op1);
8916 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
8918 /* This is very simple, but making the interface the same as in the
8919 FP case makes the rest of the code easier. */
8920 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
8921 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
8923 /* Return the test that should be put into the flags user, i.e.
8924 the bcc, scc, or cmov instruction. */
8925 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
8928 /* Figure out whether to use ordered or unordered fp comparisons.
8929 Return the appropriate mode to use. */
8932 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
8934 /* ??? In order to make all comparisons reversible, we do all comparisons
8935 non-trapping when compiling for IEEE. Once gcc is able to distinguish
8936 all forms trapping and nontrapping comparisons, we can make inequality
8937 comparisons trapping again, since it results in better code when using
8938 FCOM based compares. */
8939 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
8943 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
8945 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
8946 return ix86_fp_compare_mode (code);
8949 /* Only zero flag is needed. */
8951 case NE: /* ZF!=0 */
8953 /* Codes needing carry flag. */
8954 case GEU: /* CF=0 */
8955 case GTU: /* CF=0 & ZF=0 */
8956 case LTU: /* CF=1 */
8957 case LEU: /* CF=1 | ZF=1 */
8959 /* Codes possibly doable only with sign flag when
8960 comparing against zero. */
8961 case GE: /* SF=OF or SF=0 */
8962 case LT: /* SF<>OF or SF=1 */
8963 if (op1 == const0_rtx)
8966 /* For other cases Carry flag is not required. */
8968 /* Codes doable only with sign flag when comparing
8969 against zero, but we miss jump instruction for it
8970 so we need to use relational tests against overflow
8971 that thus needs to be zero. */
8972 case GT: /* ZF=0 & SF=OF */
8973 case LE: /* ZF=1 | SF<>OF */
8974 if (op1 == const0_rtx)
8978 /* strcmp pattern do (use flags) and combine may ask us for proper
8987 /* Return the fixed registers used for condition codes. */
8990 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8997 /* If two condition code modes are compatible, return a condition code
8998 mode which is compatible with both. Otherwise, return
9001 static enum machine_mode
9002 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
9007 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
9010 if ((m1 == CCGCmode && m2 == CCGOCmode)
9011 || (m1 == CCGOCmode && m2 == CCGCmode))
9039 /* These are only compatible with themselves, which we already
9045 /* Return true if we should use an FCOMI instruction for this fp comparison. */
9048 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
9050 enum rtx_code swapped_code = swap_condition (code);
9051 return ((ix86_fp_comparison_cost (code) == ix86_fp_comparison_fcomi_cost (code))
9052 || (ix86_fp_comparison_cost (swapped_code)
9053 == ix86_fp_comparison_fcomi_cost (swapped_code)));
9056 /* Swap, force into registers, or otherwise massage the two operands
9057 to a fp comparison. The operands are updated in place; the new
9058 comparison code is returned. */
9060 static enum rtx_code
9061 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
9063 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
9064 rtx op0 = *pop0, op1 = *pop1;
9065 enum machine_mode op_mode = GET_MODE (op0);
9066 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
9068 /* All of the unordered compare instructions only work on registers.
9069 The same is true of the fcomi compare instructions. The XFmode
9070 compare instructions require registers except when comparing
9071 against zero or when converting operand 1 from fixed point to
9075 && (fpcmp_mode == CCFPUmode
9076 || (op_mode == XFmode
9077 && ! (standard_80387_constant_p (op0) == 1
9078 || standard_80387_constant_p (op1) == 1)
9079 && GET_CODE (op1) != FLOAT)
9080 || ix86_use_fcomi_compare (code)))
9082 op0 = force_reg (op_mode, op0);
9083 op1 = force_reg (op_mode, op1);
9087 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
9088 things around if they appear profitable, otherwise force op0
9091 if (standard_80387_constant_p (op0) == 0
9092 || (GET_CODE (op0) == MEM
9093 && ! (standard_80387_constant_p (op1) == 0
9094 || GET_CODE (op1) == MEM)))
9097 tmp = op0, op0 = op1, op1 = tmp;
9098 code = swap_condition (code);
9101 if (GET_CODE (op0) != REG)
9102 op0 = force_reg (op_mode, op0);
9104 if (CONSTANT_P (op1))
9106 int tmp = standard_80387_constant_p (op1);
9108 op1 = validize_mem (force_const_mem (op_mode, op1));
9112 op1 = force_reg (op_mode, op1);
9115 op1 = force_reg (op_mode, op1);
9119 /* Try to rearrange the comparison to make it cheaper. */
9120 if (ix86_fp_comparison_cost (code)
9121 > ix86_fp_comparison_cost (swap_condition (code))
9122 && (GET_CODE (op1) == REG || !no_new_pseudos))
9125 tmp = op0, op0 = op1, op1 = tmp;
9126 code = swap_condition (code);
9127 if (GET_CODE (op0) != REG)
9128 op0 = force_reg (op_mode, op0);
9136 /* Convert comparison codes we use to represent FP comparison to integer
9137 code that will result in proper branch. Return UNKNOWN if no such code
9141 ix86_fp_compare_code_to_integer (enum rtx_code code)
9170 /* Split comparison code CODE into comparisons we can do using branch
9171 instructions. BYPASS_CODE is comparison code for branch that will
9172 branch around FIRST_CODE and SECOND_CODE. If some of branches
9173 is not required, set value to UNKNOWN.
9174 We never require more than two branches. */
9177 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
9178 enum rtx_code *first_code,
9179 enum rtx_code *second_code)
9182 *bypass_code = UNKNOWN;
9183 *second_code = UNKNOWN;
9185 /* The fcomi comparison sets flags as follows:
9195 case GT: /* GTU - CF=0 & ZF=0 */
9196 case GE: /* GEU - CF=0 */
9197 case ORDERED: /* PF=0 */
9198 case UNORDERED: /* PF=1 */
9199 case UNEQ: /* EQ - ZF=1 */
9200 case UNLT: /* LTU - CF=1 */
9201 case UNLE: /* LEU - CF=1 | ZF=1 */
9202 case LTGT: /* EQ - ZF=0 */
9204 case LT: /* LTU - CF=1 - fails on unordered */
9206 *bypass_code = UNORDERED;
9208 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
9210 *bypass_code = UNORDERED;
9212 case EQ: /* EQ - ZF=1 - fails on unordered */
9214 *bypass_code = UNORDERED;
9216 case NE: /* NE - ZF=0 - fails on unordered */
9218 *second_code = UNORDERED;
9220 case UNGE: /* GEU - CF=0 - fails on unordered */
9222 *second_code = UNORDERED;
9224 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
9226 *second_code = UNORDERED;
9231 if (!TARGET_IEEE_FP)
9233 *second_code = UNKNOWN;
9234 *bypass_code = UNKNOWN;
9238 /* Return cost of comparison done fcom + arithmetics operations on AX.
9239 All following functions do use number of instructions as a cost metrics.
9240 In future this should be tweaked to compute bytes for optimize_size and
9241 take into account performance of various instructions on various CPUs. */
9243 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
9245 if (!TARGET_IEEE_FP)
9247 /* The cost of code output by ix86_expand_fp_compare. */
9275 /* Return cost of comparison done using fcomi operation.
9276 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9278 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
9280 enum rtx_code bypass_code, first_code, second_code;
9281 /* Return arbitrarily high cost when instruction is not supported - this
9282 prevents gcc from using it. */
9285 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9286 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
9289 /* Return cost of comparison done using sahf operation.
9290 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9292 ix86_fp_comparison_sahf_cost (enum rtx_code code)
9294 enum rtx_code bypass_code, first_code, second_code;
9295 /* Return arbitrarily high cost when instruction is not preferred - this
9296 avoids gcc from using it. */
9297 if (!TARGET_USE_SAHF && !optimize_size)
9299 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9300 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
9303 /* Compute cost of the comparison done using any method.
9304 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9306 ix86_fp_comparison_cost (enum rtx_code code)
9308 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
9311 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
9312 sahf_cost = ix86_fp_comparison_sahf_cost (code);
9314 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
9315 if (min > sahf_cost)
9317 if (min > fcomi_cost)
9322 /* Generate insn patterns to do a floating point compare of OPERANDS. */
9325 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
9326 rtx *second_test, rtx *bypass_test)
9328 enum machine_mode fpcmp_mode, intcmp_mode;
9330 int cost = ix86_fp_comparison_cost (code);
9331 enum rtx_code bypass_code, first_code, second_code;
9333 fpcmp_mode = ix86_fp_compare_mode (code);
9334 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
9337 *second_test = NULL_RTX;
9339 *bypass_test = NULL_RTX;
9341 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9343 /* Do fcomi/sahf based test when profitable. */
9344 if ((bypass_code == UNKNOWN || bypass_test)
9345 && (second_code == UNKNOWN || second_test)
9346 && ix86_fp_comparison_arithmetics_cost (code) > cost)
9350 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9351 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
9357 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9358 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9360 scratch = gen_reg_rtx (HImode);
9361 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9362 emit_insn (gen_x86_sahf_1 (scratch));
9365 /* The FP codes work out to act like unsigned. */
9366 intcmp_mode = fpcmp_mode;
9368 if (bypass_code != UNKNOWN)
9369 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
9370 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9372 if (second_code != UNKNOWN)
9373 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
9374 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9379 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
9380 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9381 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9383 scratch = gen_reg_rtx (HImode);
9384 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9386 /* In the unordered case, we have to check C2 for NaN's, which
9387 doesn't happen to work out to anything nice combination-wise.
9388 So do some bit twiddling on the value we've got in AH to come
9389 up with an appropriate set of condition codes. */
9391 intcmp_mode = CCNOmode;
9396 if (code == GT || !TARGET_IEEE_FP)
9398 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
9403 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9404 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
9405 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
9406 intcmp_mode = CCmode;
9412 if (code == LT && TARGET_IEEE_FP)
9414 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9415 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
9416 intcmp_mode = CCmode;
9421 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
9427 if (code == GE || !TARGET_IEEE_FP)
9429 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
9434 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9435 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
9442 if (code == LE && TARGET_IEEE_FP)
9444 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9445 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
9446 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
9447 intcmp_mode = CCmode;
9452 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
9458 if (code == EQ && TARGET_IEEE_FP)
9460 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9461 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
9462 intcmp_mode = CCmode;
9467 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
9474 if (code == NE && TARGET_IEEE_FP)
9476 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9477 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
9483 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
9489 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
9493 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
9502 /* Return the test that should be put into the flags user, i.e.
9503 the bcc, scc, or cmov instruction. */
9504 return gen_rtx_fmt_ee (code, VOIDmode,
9505 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9510 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
9513 op0 = ix86_compare_op0;
9514 op1 = ix86_compare_op1;
9517 *second_test = NULL_RTX;
9519 *bypass_test = NULL_RTX;
9521 if (ix86_compare_emitted)
9523 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
9524 ix86_compare_emitted = NULL_RTX;
9526 else if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
9527 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
9528 second_test, bypass_test);
9530 ret = ix86_expand_int_compare (code, op0, op1);
9535 /* Return true if the CODE will result in nontrivial jump sequence. */
9537 ix86_fp_jump_nontrivial_p (enum rtx_code code)
9539 enum rtx_code bypass_code, first_code, second_code;
9542 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9543 return bypass_code != UNKNOWN || second_code != UNKNOWN;
9547 ix86_expand_branch (enum rtx_code code, rtx label)
9551 switch (GET_MODE (ix86_compare_op0))
9557 tmp = ix86_expand_compare (code, NULL, NULL);
9558 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9559 gen_rtx_LABEL_REF (VOIDmode, label),
9561 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
9570 enum rtx_code bypass_code, first_code, second_code;
9572 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
9575 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9577 /* Check whether we will use the natural sequence with one jump. If
9578 so, we can expand jump early. Otherwise delay expansion by
9579 creating compound insn to not confuse optimizers. */
9580 if (bypass_code == UNKNOWN && second_code == UNKNOWN
9583 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
9584 gen_rtx_LABEL_REF (VOIDmode, label),
9585 pc_rtx, NULL_RTX, NULL_RTX);
9589 tmp = gen_rtx_fmt_ee (code, VOIDmode,
9590 ix86_compare_op0, ix86_compare_op1);
9591 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9592 gen_rtx_LABEL_REF (VOIDmode, label),
9594 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
9596 use_fcomi = ix86_use_fcomi_compare (code);
9597 vec = rtvec_alloc (3 + !use_fcomi);
9598 RTVEC_ELT (vec, 0) = tmp;
9600 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 18));
9602 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 17));
9605 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
9607 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
9616 /* Expand DImode branch into multiple compare+branch. */
9618 rtx lo[2], hi[2], label2;
9619 enum rtx_code code1, code2, code3;
9620 enum machine_mode submode;
9622 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
9624 tmp = ix86_compare_op0;
9625 ix86_compare_op0 = ix86_compare_op1;
9626 ix86_compare_op1 = tmp;
9627 code = swap_condition (code);
9629 if (GET_MODE (ix86_compare_op0) == DImode)
9631 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
9632 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
9637 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
9638 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
9642 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
9643 avoid two branches. This costs one extra insn, so disable when
9644 optimizing for size. */
9646 if ((code == EQ || code == NE)
9648 || hi[1] == const0_rtx || lo[1] == const0_rtx))
9653 if (hi[1] != const0_rtx)
9654 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
9655 NULL_RTX, 0, OPTAB_WIDEN);
9658 if (lo[1] != const0_rtx)
9659 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
9660 NULL_RTX, 0, OPTAB_WIDEN);
9662 tmp = expand_binop (submode, ior_optab, xor1, xor0,
9663 NULL_RTX, 0, OPTAB_WIDEN);
9665 ix86_compare_op0 = tmp;
9666 ix86_compare_op1 = const0_rtx;
9667 ix86_expand_branch (code, label);
9671 /* Otherwise, if we are doing less-than or greater-or-equal-than,
9672 op1 is a constant and the low word is zero, then we can just
9673 examine the high word. */
9675 if (GET_CODE (hi[1]) == CONST_INT && lo[1] == const0_rtx)
9678 case LT: case LTU: case GE: case GEU:
9679 ix86_compare_op0 = hi[0];
9680 ix86_compare_op1 = hi[1];
9681 ix86_expand_branch (code, label);
9687 /* Otherwise, we need two or three jumps. */
9689 label2 = gen_label_rtx ();
9692 code2 = swap_condition (code);
9693 code3 = unsigned_condition (code);
9697 case LT: case GT: case LTU: case GTU:
9700 case LE: code1 = LT; code2 = GT; break;
9701 case GE: code1 = GT; code2 = LT; break;
9702 case LEU: code1 = LTU; code2 = GTU; break;
9703 case GEU: code1 = GTU; code2 = LTU; break;
9705 case EQ: code1 = UNKNOWN; code2 = NE; break;
9706 case NE: code2 = UNKNOWN; break;
9714 * if (hi(a) < hi(b)) goto true;
9715 * if (hi(a) > hi(b)) goto false;
9716 * if (lo(a) < lo(b)) goto true;
9720 ix86_compare_op0 = hi[0];
9721 ix86_compare_op1 = hi[1];
9723 if (code1 != UNKNOWN)
9724 ix86_expand_branch (code1, label);
9725 if (code2 != UNKNOWN)
9726 ix86_expand_branch (code2, label2);
9728 ix86_compare_op0 = lo[0];
9729 ix86_compare_op1 = lo[1];
9730 ix86_expand_branch (code3, label);
9732 if (code2 != UNKNOWN)
9733 emit_label (label2);
9742 /* Split branch based on floating point condition. */
9744 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
9745 rtx target1, rtx target2, rtx tmp, rtx pushed)
9748 rtx label = NULL_RTX;
9750 int bypass_probability = -1, second_probability = -1, probability = -1;
9753 if (target2 != pc_rtx)
9756 code = reverse_condition_maybe_unordered (code);
9761 condition = ix86_expand_fp_compare (code, op1, op2,
9762 tmp, &second, &bypass);
9764 /* Remove pushed operand from stack. */
9766 ix86_free_from_memory (GET_MODE (pushed));
9768 if (split_branch_probability >= 0)
9770 /* Distribute the probabilities across the jumps.
9771 Assume the BYPASS and SECOND to be always test
9773 probability = split_branch_probability;
9775 /* Value of 1 is low enough to make no need for probability
9776 to be updated. Later we may run some experiments and see
9777 if unordered values are more frequent in practice. */
9779 bypass_probability = 1;
9781 second_probability = 1;
9783 if (bypass != NULL_RTX)
9785 label = gen_label_rtx ();
9786 i = emit_jump_insn (gen_rtx_SET
9788 gen_rtx_IF_THEN_ELSE (VOIDmode,
9790 gen_rtx_LABEL_REF (VOIDmode,
9793 if (bypass_probability >= 0)
9795 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9796 GEN_INT (bypass_probability),
9799 i = emit_jump_insn (gen_rtx_SET
9801 gen_rtx_IF_THEN_ELSE (VOIDmode,
9802 condition, target1, target2)));
9803 if (probability >= 0)
9805 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9806 GEN_INT (probability),
9808 if (second != NULL_RTX)
9810 i = emit_jump_insn (gen_rtx_SET
9812 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
9814 if (second_probability >= 0)
9816 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9817 GEN_INT (second_probability),
9820 if (label != NULL_RTX)
9825 ix86_expand_setcc (enum rtx_code code, rtx dest)
9827 rtx ret, tmp, tmpreg, equiv;
9828 rtx second_test, bypass_test;
9830 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
9831 return 0; /* FAIL */
9833 gcc_assert (GET_MODE (dest) == QImode);
9835 ret = ix86_expand_compare (code, &second_test, &bypass_test);
9836 PUT_MODE (ret, QImode);
9841 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
9842 if (bypass_test || second_test)
9844 rtx test = second_test;
9846 rtx tmp2 = gen_reg_rtx (QImode);
9849 gcc_assert (!second_test);
9852 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
9854 PUT_MODE (test, QImode);
9855 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
9858 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
9860 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
9863 /* Attach a REG_EQUAL note describing the comparison result. */
9864 if (ix86_compare_op0 && ix86_compare_op1)
9866 equiv = simplify_gen_relational (code, QImode,
9867 GET_MODE (ix86_compare_op0),
9868 ix86_compare_op0, ix86_compare_op1);
9869 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
9872 return 1; /* DONE */
9875 /* Expand comparison setting or clearing carry flag. Return true when
9876 successful and set pop for the operation. */
9878 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
9880 enum machine_mode mode =
9881 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
9883 /* Do not handle DImode compares that go trought special path. Also we can't
9884 deal with FP compares yet. This is possible to add. */
9885 if (mode == (TARGET_64BIT ? TImode : DImode))
9887 if (FLOAT_MODE_P (mode))
9889 rtx second_test = NULL, bypass_test = NULL;
9890 rtx compare_op, compare_seq;
9892 /* Shortcut: following common codes never translate into carry flag compares. */
9893 if (code == EQ || code == NE || code == UNEQ || code == LTGT
9894 || code == ORDERED || code == UNORDERED)
9897 /* These comparisons require zero flag; swap operands so they won't. */
9898 if ((code == GT || code == UNLE || code == LE || code == UNGT)
9904 code = swap_condition (code);
9907 /* Try to expand the comparison and verify that we end up with carry flag
9908 based comparison. This is fails to be true only when we decide to expand
9909 comparison using arithmetic that is not too common scenario. */
9911 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
9912 &second_test, &bypass_test);
9913 compare_seq = get_insns ();
9916 if (second_test || bypass_test)
9918 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
9919 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
9920 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
9922 code = GET_CODE (compare_op);
9923 if (code != LTU && code != GEU)
9925 emit_insn (compare_seq);
9929 if (!INTEGRAL_MODE_P (mode))
9937 /* Convert a==0 into (unsigned)a<1. */
9940 if (op1 != const0_rtx)
9943 code = (code == EQ ? LTU : GEU);
9946 /* Convert a>b into b<a or a>=b-1. */
9949 if (GET_CODE (op1) == CONST_INT)
9951 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
9952 /* Bail out on overflow. We still can swap operands but that
9953 would force loading of the constant into register. */
9954 if (op1 == const0_rtx
9955 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
9957 code = (code == GTU ? GEU : LTU);
9964 code = (code == GTU ? LTU : GEU);
9968 /* Convert a>=0 into (unsigned)a<0x80000000. */
9971 if (mode == DImode || op1 != const0_rtx)
9973 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
9974 code = (code == LT ? GEU : LTU);
9978 if (mode == DImode || op1 != constm1_rtx)
9980 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
9981 code = (code == LE ? GEU : LTU);
9987 /* Swapping operands may cause constant to appear as first operand. */
9988 if (!nonimmediate_operand (op0, VOIDmode))
9992 op0 = force_reg (mode, op0);
9994 ix86_compare_op0 = op0;
9995 ix86_compare_op1 = op1;
9996 *pop = ix86_expand_compare (code, NULL, NULL);
9997 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
10002 ix86_expand_int_movcc (rtx operands[])
10004 enum rtx_code code = GET_CODE (operands[1]), compare_code;
10005 rtx compare_seq, compare_op;
10006 rtx second_test, bypass_test;
10007 enum machine_mode mode = GET_MODE (operands[0]);
10008 bool sign_bit_compare_p = false;;
10011 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10012 compare_seq = get_insns ();
10015 compare_code = GET_CODE (compare_op);
10017 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
10018 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
10019 sign_bit_compare_p = true;
10021 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
10022 HImode insns, we'd be swallowed in word prefix ops. */
10024 if ((mode != HImode || TARGET_FAST_PREFIX)
10025 && (mode != (TARGET_64BIT ? TImode : DImode))
10026 && GET_CODE (operands[2]) == CONST_INT
10027 && GET_CODE (operands[3]) == CONST_INT)
10029 rtx out = operands[0];
10030 HOST_WIDE_INT ct = INTVAL (operands[2]);
10031 HOST_WIDE_INT cf = INTVAL (operands[3]);
10032 HOST_WIDE_INT diff;
10035 /* Sign bit compares are better done using shifts than we do by using
10037 if (sign_bit_compare_p
10038 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
10039 ix86_compare_op1, &compare_op))
10041 /* Detect overlap between destination and compare sources. */
10044 if (!sign_bit_compare_p)
10046 bool fpcmp = false;
10048 compare_code = GET_CODE (compare_op);
10050 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10051 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10054 compare_code = ix86_fp_compare_code_to_integer (compare_code);
10057 /* To simplify rest of code, restrict to the GEU case. */
10058 if (compare_code == LTU)
10060 HOST_WIDE_INT tmp = ct;
10063 compare_code = reverse_condition (compare_code);
10064 code = reverse_condition (code);
10069 PUT_CODE (compare_op,
10070 reverse_condition_maybe_unordered
10071 (GET_CODE (compare_op)));
10073 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
10077 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
10078 || reg_overlap_mentioned_p (out, ix86_compare_op1))
10079 tmp = gen_reg_rtx (mode);
10081 if (mode == DImode)
10082 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
10084 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
10088 if (code == GT || code == GE)
10089 code = reverse_condition (code);
10092 HOST_WIDE_INT tmp = ct;
10097 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
10098 ix86_compare_op1, VOIDmode, 0, -1);
10111 tmp = expand_simple_binop (mode, PLUS,
10113 copy_rtx (tmp), 1, OPTAB_DIRECT);
10124 tmp = expand_simple_binop (mode, IOR,
10126 copy_rtx (tmp), 1, OPTAB_DIRECT);
10128 else if (diff == -1 && ct)
10138 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10140 tmp = expand_simple_binop (mode, PLUS,
10141 copy_rtx (tmp), GEN_INT (cf),
10142 copy_rtx (tmp), 1, OPTAB_DIRECT);
10150 * andl cf - ct, dest
10160 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10163 tmp = expand_simple_binop (mode, AND,
10165 gen_int_mode (cf - ct, mode),
10166 copy_rtx (tmp), 1, OPTAB_DIRECT);
10168 tmp = expand_simple_binop (mode, PLUS,
10169 copy_rtx (tmp), GEN_INT (ct),
10170 copy_rtx (tmp), 1, OPTAB_DIRECT);
10173 if (!rtx_equal_p (tmp, out))
10174 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
10176 return 1; /* DONE */
10182 tmp = ct, ct = cf, cf = tmp;
10184 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10186 /* We may be reversing unordered compare to normal compare, that
10187 is not valid in general (we may convert non-trapping condition
10188 to trapping one), however on i386 we currently emit all
10189 comparisons unordered. */
10190 compare_code = reverse_condition_maybe_unordered (compare_code);
10191 code = reverse_condition_maybe_unordered (code);
10195 compare_code = reverse_condition (compare_code);
10196 code = reverse_condition (code);
10200 compare_code = UNKNOWN;
10201 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
10202 && GET_CODE (ix86_compare_op1) == CONST_INT)
10204 if (ix86_compare_op1 == const0_rtx
10205 && (code == LT || code == GE))
10206 compare_code = code;
10207 else if (ix86_compare_op1 == constm1_rtx)
10211 else if (code == GT)
10216 /* Optimize dest = (op0 < 0) ? -1 : cf. */
10217 if (compare_code != UNKNOWN
10218 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
10219 && (cf == -1 || ct == -1))
10221 /* If lea code below could be used, only optimize
10222 if it results in a 2 insn sequence. */
10224 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
10225 || diff == 3 || diff == 5 || diff == 9)
10226 || (compare_code == LT && ct == -1)
10227 || (compare_code == GE && cf == -1))
10230 * notl op1 (if necessary)
10238 code = reverse_condition (code);
10241 out = emit_store_flag (out, code, ix86_compare_op0,
10242 ix86_compare_op1, VOIDmode, 0, -1);
10244 out = expand_simple_binop (mode, IOR,
10246 out, 1, OPTAB_DIRECT);
10247 if (out != operands[0])
10248 emit_move_insn (operands[0], out);
10250 return 1; /* DONE */
10255 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
10256 || diff == 3 || diff == 5 || diff == 9)
10257 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
10259 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
10265 * lea cf(dest*(ct-cf)),dest
10269 * This also catches the degenerate setcc-only case.
10275 out = emit_store_flag (out, code, ix86_compare_op0,
10276 ix86_compare_op1, VOIDmode, 0, 1);
10279 /* On x86_64 the lea instruction operates on Pmode, so we need
10280 to get arithmetics done in proper mode to match. */
10282 tmp = copy_rtx (out);
10286 out1 = copy_rtx (out);
10287 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
10291 tmp = gen_rtx_PLUS (mode, tmp, out1);
10297 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
10300 if (!rtx_equal_p (tmp, out))
10303 out = force_operand (tmp, copy_rtx (out));
10305 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
10307 if (!rtx_equal_p (out, operands[0]))
10308 emit_move_insn (operands[0], copy_rtx (out));
10310 return 1; /* DONE */
10314 * General case: Jumpful:
10315 * xorl dest,dest cmpl op1, op2
10316 * cmpl op1, op2 movl ct, dest
10317 * setcc dest jcc 1f
10318 * decl dest movl cf, dest
10319 * andl (cf-ct),dest 1:
10322 * Size 20. Size 14.
10324 * This is reasonably steep, but branch mispredict costs are
10325 * high on modern cpus, so consider failing only if optimizing
10329 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10330 && BRANCH_COST >= 2)
10336 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10337 /* We may be reversing unordered compare to normal compare,
10338 that is not valid in general (we may convert non-trapping
10339 condition to trapping one), however on i386 we currently
10340 emit all comparisons unordered. */
10341 code = reverse_condition_maybe_unordered (code);
10344 code = reverse_condition (code);
10345 if (compare_code != UNKNOWN)
10346 compare_code = reverse_condition (compare_code);
10350 if (compare_code != UNKNOWN)
10352 /* notl op1 (if needed)
10357 For x < 0 (resp. x <= -1) there will be no notl,
10358 so if possible swap the constants to get rid of the
10360 True/false will be -1/0 while code below (store flag
10361 followed by decrement) is 0/-1, so the constants need
10362 to be exchanged once more. */
10364 if (compare_code == GE || !cf)
10366 code = reverse_condition (code);
10371 HOST_WIDE_INT tmp = cf;
10376 out = emit_store_flag (out, code, ix86_compare_op0,
10377 ix86_compare_op1, VOIDmode, 0, -1);
10381 out = emit_store_flag (out, code, ix86_compare_op0,
10382 ix86_compare_op1, VOIDmode, 0, 1);
10384 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
10385 copy_rtx (out), 1, OPTAB_DIRECT);
10388 out = expand_simple_binop (mode, AND, copy_rtx (out),
10389 gen_int_mode (cf - ct, mode),
10390 copy_rtx (out), 1, OPTAB_DIRECT);
10392 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
10393 copy_rtx (out), 1, OPTAB_DIRECT);
10394 if (!rtx_equal_p (out, operands[0]))
10395 emit_move_insn (operands[0], copy_rtx (out));
10397 return 1; /* DONE */
10401 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10403 /* Try a few things more with specific constants and a variable. */
10406 rtx var, orig_out, out, tmp;
10408 if (BRANCH_COST <= 2)
10409 return 0; /* FAIL */
10411 /* If one of the two operands is an interesting constant, load a
10412 constant with the above and mask it in with a logical operation. */
10414 if (GET_CODE (operands[2]) == CONST_INT)
10417 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
10418 operands[3] = constm1_rtx, op = and_optab;
10419 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
10420 operands[3] = const0_rtx, op = ior_optab;
10422 return 0; /* FAIL */
10424 else if (GET_CODE (operands[3]) == CONST_INT)
10427 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
10428 operands[2] = constm1_rtx, op = and_optab;
10429 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
10430 operands[2] = const0_rtx, op = ior_optab;
10432 return 0; /* FAIL */
10435 return 0; /* FAIL */
10437 orig_out = operands[0];
10438 tmp = gen_reg_rtx (mode);
10441 /* Recurse to get the constant loaded. */
10442 if (ix86_expand_int_movcc (operands) == 0)
10443 return 0; /* FAIL */
10445 /* Mask in the interesting variable. */
10446 out = expand_binop (mode, op, var, tmp, orig_out, 0,
10448 if (!rtx_equal_p (out, orig_out))
10449 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
10451 return 1; /* DONE */
10455 * For comparison with above,
10465 if (! nonimmediate_operand (operands[2], mode))
10466 operands[2] = force_reg (mode, operands[2]);
10467 if (! nonimmediate_operand (operands[3], mode))
10468 operands[3] = force_reg (mode, operands[3]);
10470 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
10472 rtx tmp = gen_reg_rtx (mode);
10473 emit_move_insn (tmp, operands[3]);
10476 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
10478 rtx tmp = gen_reg_rtx (mode);
10479 emit_move_insn (tmp, operands[2]);
10483 if (! register_operand (operands[2], VOIDmode)
10485 || ! register_operand (operands[3], VOIDmode)))
10486 operands[2] = force_reg (mode, operands[2]);
10489 && ! register_operand (operands[3], VOIDmode))
10490 operands[3] = force_reg (mode, operands[3]);
10492 emit_insn (compare_seq);
10493 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10494 gen_rtx_IF_THEN_ELSE (mode,
10495 compare_op, operands[2],
10498 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
10499 gen_rtx_IF_THEN_ELSE (mode,
10501 copy_rtx (operands[3]),
10502 copy_rtx (operands[0]))));
10504 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
10505 gen_rtx_IF_THEN_ELSE (mode,
10507 copy_rtx (operands[2]),
10508 copy_rtx (operands[0]))));
10510 return 1; /* DONE */
10513 /* Swap, force into registers, or otherwise massage the two operands
10514 to an sse comparison with a mask result. Thus we differ a bit from
10515 ix86_prepare_fp_compare_args which expects to produce a flags result.
10517 The DEST operand exists to help determine whether to commute commutative
10518 operators. The POP0/POP1 operands are updated in place. The new
10519 comparison code is returned, or UNKNOWN if not implementable. */
10521 static enum rtx_code
10522 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
10523 rtx *pop0, rtx *pop1)
10531 /* We have no LTGT as an operator. We could implement it with
10532 NE & ORDERED, but this requires an extra temporary. It's
10533 not clear that it's worth it. */
10540 /* These are supported directly. */
10547 /* For commutative operators, try to canonicalize the destination
10548 operand to be first in the comparison - this helps reload to
10549 avoid extra moves. */
10550 if (!dest || !rtx_equal_p (dest, *pop1))
10558 /* These are not supported directly. Swap the comparison operands
10559 to transform into something that is supported. */
10563 code = swap_condition (code);
10567 gcc_unreachable ();
10573 /* Detect conditional moves that exactly match min/max operational
10574 semantics. Note that this is IEEE safe, as long as we don't
10575 interchange the operands.
10577 Returns FALSE if this conditional move doesn't match a MIN/MAX,
10578 and TRUE if the operation is successful and instructions are emitted. */
10581 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
10582 rtx cmp_op1, rtx if_true, rtx if_false)
10584 enum machine_mode mode;
10590 else if (code == UNGE)
10593 if_true = if_false;
10599 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
10601 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
10606 mode = GET_MODE (dest);
10608 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
10609 but MODE may be a vector mode and thus not appropriate. */
10610 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
10612 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
10615 if_true = force_reg (mode, if_true);
10616 v = gen_rtvec (2, if_true, if_false);
10617 tmp = gen_rtx_UNSPEC (mode, v, u);
10621 code = is_min ? SMIN : SMAX;
10622 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
10625 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
10629 /* Expand an sse vector comparison. Return the register with the result. */
10632 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
10633 rtx op_true, rtx op_false)
10635 enum machine_mode mode = GET_MODE (dest);
10638 cmp_op0 = force_reg (mode, cmp_op0);
10639 if (!nonimmediate_operand (cmp_op1, mode))
10640 cmp_op1 = force_reg (mode, cmp_op1);
10643 || reg_overlap_mentioned_p (dest, op_true)
10644 || reg_overlap_mentioned_p (dest, op_false))
10645 dest = gen_reg_rtx (mode);
10647 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
10648 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10653 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
10654 operations. This is used for both scalar and vector conditional moves. */
10657 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
10659 enum machine_mode mode = GET_MODE (dest);
10662 if (op_false == CONST0_RTX (mode))
10664 op_true = force_reg (mode, op_true);
10665 x = gen_rtx_AND (mode, cmp, op_true);
10666 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10668 else if (op_true == CONST0_RTX (mode))
10670 op_false = force_reg (mode, op_false);
10671 x = gen_rtx_NOT (mode, cmp);
10672 x = gen_rtx_AND (mode, x, op_false);
10673 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10677 op_true = force_reg (mode, op_true);
10678 op_false = force_reg (mode, op_false);
10680 t2 = gen_reg_rtx (mode);
10682 t3 = gen_reg_rtx (mode);
10686 x = gen_rtx_AND (mode, op_true, cmp);
10687 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
10689 x = gen_rtx_NOT (mode, cmp);
10690 x = gen_rtx_AND (mode, x, op_false);
10691 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
10693 x = gen_rtx_IOR (mode, t3, t2);
10694 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10698 /* Expand a floating-point conditional move. Return true if successful. */
10701 ix86_expand_fp_movcc (rtx operands[])
10703 enum machine_mode mode = GET_MODE (operands[0]);
10704 enum rtx_code code = GET_CODE (operands[1]);
10705 rtx tmp, compare_op, second_test, bypass_test;
10707 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
10709 enum machine_mode cmode;
10711 /* Since we've no cmove for sse registers, don't force bad register
10712 allocation just to gain access to it. Deny movcc when the
10713 comparison mode doesn't match the move mode. */
10714 cmode = GET_MODE (ix86_compare_op0);
10715 if (cmode == VOIDmode)
10716 cmode = GET_MODE (ix86_compare_op1);
10720 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
10722 &ix86_compare_op1);
10723 if (code == UNKNOWN)
10726 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
10727 ix86_compare_op1, operands[2],
10731 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
10732 ix86_compare_op1, operands[2], operands[3]);
10733 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
10737 /* The floating point conditional move instructions don't directly
10738 support conditions resulting from a signed integer comparison. */
10740 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10742 /* The floating point conditional move instructions don't directly
10743 support signed integer comparisons. */
10745 if (!fcmov_comparison_operator (compare_op, VOIDmode))
10747 gcc_assert (!second_test && !bypass_test);
10748 tmp = gen_reg_rtx (QImode);
10749 ix86_expand_setcc (code, tmp);
10751 ix86_compare_op0 = tmp;
10752 ix86_compare_op1 = const0_rtx;
10753 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10755 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
10757 tmp = gen_reg_rtx (mode);
10758 emit_move_insn (tmp, operands[3]);
10761 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
10763 tmp = gen_reg_rtx (mode);
10764 emit_move_insn (tmp, operands[2]);
10768 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10769 gen_rtx_IF_THEN_ELSE (mode, compare_op,
10770 operands[2], operands[3])));
10772 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10773 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
10774 operands[3], operands[0])));
10776 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10777 gen_rtx_IF_THEN_ELSE (mode, second_test,
10778 operands[2], operands[0])));
10783 /* Expand a floating-point vector conditional move; a vcond operation
10784 rather than a movcc operation. */
10787 ix86_expand_fp_vcond (rtx operands[])
10789 enum rtx_code code = GET_CODE (operands[3]);
10792 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
10793 &operands[4], &operands[5]);
10794 if (code == UNKNOWN)
10797 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
10798 operands[5], operands[1], operands[2]))
10801 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
10802 operands[1], operands[2]);
10803 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
10807 /* Expand a signed integral vector conditional move. */
10810 ix86_expand_int_vcond (rtx operands[])
10812 enum machine_mode mode = GET_MODE (operands[0]);
10813 enum rtx_code code = GET_CODE (operands[3]);
10814 bool negate = false;
10817 cop0 = operands[4];
10818 cop1 = operands[5];
10820 /* Canonicalize the comparison to EQ, GT, GTU. */
10831 code = reverse_condition (code);
10837 code = reverse_condition (code);
10843 code = swap_condition (code);
10844 x = cop0, cop0 = cop1, cop1 = x;
10848 gcc_unreachable ();
10851 /* Unsigned parallel compare is not supported by the hardware. Play some
10852 tricks to turn this into a signed comparison against 0. */
10861 /* Perform a parallel modulo subtraction. */
10862 t1 = gen_reg_rtx (mode);
10863 emit_insn (gen_subv4si3 (t1, cop0, cop1));
10865 /* Extract the original sign bit of op0. */
10866 mask = GEN_INT (-0x80000000);
10867 mask = gen_rtx_CONST_VECTOR (mode,
10868 gen_rtvec (4, mask, mask, mask, mask));
10869 mask = force_reg (mode, mask);
10870 t2 = gen_reg_rtx (mode);
10871 emit_insn (gen_andv4si3 (t2, cop0, mask));
10873 /* XOR it back into the result of the subtraction. This results
10874 in the sign bit set iff we saw unsigned underflow. */
10875 x = gen_reg_rtx (mode);
10876 emit_insn (gen_xorv4si3 (x, t1, t2));
10884 /* Perform a parallel unsigned saturating subtraction. */
10885 x = gen_reg_rtx (mode);
10886 emit_insn (gen_rtx_SET (VOIDmode, x,
10887 gen_rtx_US_MINUS (mode, cop0, cop1)));
10894 gcc_unreachable ();
10898 cop1 = CONST0_RTX (mode);
10901 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
10902 operands[1+negate], operands[2-negate]);
10904 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
10905 operands[2-negate]);
10909 /* Expand conditional increment or decrement using adb/sbb instructions.
10910 The default case using setcc followed by the conditional move can be
10911 done by generic code. */
10913 ix86_expand_int_addcc (rtx operands[])
10915 enum rtx_code code = GET_CODE (operands[1]);
10917 rtx val = const0_rtx;
10918 bool fpcmp = false;
10919 enum machine_mode mode = GET_MODE (operands[0]);
10921 if (operands[3] != const1_rtx
10922 && operands[3] != constm1_rtx)
10924 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
10925 ix86_compare_op1, &compare_op))
10927 code = GET_CODE (compare_op);
10929 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10930 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10933 code = ix86_fp_compare_code_to_integer (code);
10940 PUT_CODE (compare_op,
10941 reverse_condition_maybe_unordered
10942 (GET_CODE (compare_op)));
10944 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
10946 PUT_MODE (compare_op, mode);
10948 /* Construct either adc or sbb insn. */
10949 if ((code == LTU) == (operands[3] == constm1_rtx))
10951 switch (GET_MODE (operands[0]))
10954 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
10957 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
10960 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
10963 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
10966 gcc_unreachable ();
10971 switch (GET_MODE (operands[0]))
10974 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
10977 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
10980 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
10983 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
10986 gcc_unreachable ();
10989 return 1; /* DONE */
10993 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
10994 works for floating pointer parameters and nonoffsetable memories.
10995 For pushes, it returns just stack offsets; the values will be saved
10996 in the right order. Maximally three parts are generated. */
10999 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
11004 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
11006 size = (GET_MODE_SIZE (mode) + 4) / 8;
11008 gcc_assert (GET_CODE (operand) != REG || !MMX_REGNO_P (REGNO (operand)));
11009 gcc_assert (size >= 2 && size <= 3);
11011 /* Optimize constant pool reference to immediates. This is used by fp
11012 moves, that force all constants to memory to allow combining. */
11013 if (GET_CODE (operand) == MEM && MEM_READONLY_P (operand))
11015 rtx tmp = maybe_get_pool_constant (operand);
11020 if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand))
11022 /* The only non-offsetable memories we handle are pushes. */
11023 int ok = push_operand (operand, VOIDmode);
11027 operand = copy_rtx (operand);
11028 PUT_MODE (operand, Pmode);
11029 parts[0] = parts[1] = parts[2] = operand;
11033 if (GET_CODE (operand) == CONST_VECTOR)
11035 enum machine_mode imode = int_mode_for_mode (mode);
11036 /* Caution: if we looked through a constant pool memory above,
11037 the operand may actually have a different mode now. That's
11038 ok, since we want to pun this all the way back to an integer. */
11039 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
11040 gcc_assert (operand != NULL);
11046 if (mode == DImode)
11047 split_di (&operand, 1, &parts[0], &parts[1]);
11050 if (REG_P (operand))
11052 gcc_assert (reload_completed);
11053 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
11054 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
11056 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
11058 else if (offsettable_memref_p (operand))
11060 operand = adjust_address (operand, SImode, 0);
11061 parts[0] = operand;
11062 parts[1] = adjust_address (operand, SImode, 4);
11064 parts[2] = adjust_address (operand, SImode, 8);
11066 else if (GET_CODE (operand) == CONST_DOUBLE)
11071 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11075 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
11076 parts[2] = gen_int_mode (l[2], SImode);
11079 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
11082 gcc_unreachable ();
11084 parts[1] = gen_int_mode (l[1], SImode);
11085 parts[0] = gen_int_mode (l[0], SImode);
11088 gcc_unreachable ();
11093 if (mode == TImode)
11094 split_ti (&operand, 1, &parts[0], &parts[1]);
11095 if (mode == XFmode || mode == TFmode)
11097 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
11098 if (REG_P (operand))
11100 gcc_assert (reload_completed);
11101 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
11102 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
11104 else if (offsettable_memref_p (operand))
11106 operand = adjust_address (operand, DImode, 0);
11107 parts[0] = operand;
11108 parts[1] = adjust_address (operand, upper_mode, 8);
11110 else if (GET_CODE (operand) == CONST_DOUBLE)
11115 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11116 real_to_target (l, &r, mode);
11118 /* Do not use shift by 32 to avoid warning on 32bit systems. */
11119 if (HOST_BITS_PER_WIDE_INT >= 64)
11122 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
11123 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
11126 parts[0] = immed_double_const (l[0], l[1], DImode);
11128 if (upper_mode == SImode)
11129 parts[1] = gen_int_mode (l[2], SImode);
11130 else if (HOST_BITS_PER_WIDE_INT >= 64)
11133 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
11134 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
11137 parts[1] = immed_double_const (l[2], l[3], DImode);
11140 gcc_unreachable ();
11147 /* Emit insns to perform a move or push of DI, DF, and XF values.
11148 Return false when normal moves are needed; true when all required
11149 insns have been emitted. Operands 2-4 contain the input values
11150 int the correct order; operands 5-7 contain the output values. */
11153 ix86_split_long_move (rtx operands[])
11158 int collisions = 0;
11159 enum machine_mode mode = GET_MODE (operands[0]);
11161 /* The DFmode expanders may ask us to move double.
11162 For 64bit target this is single move. By hiding the fact
11163 here we simplify i386.md splitters. */
11164 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
11166 /* Optimize constant pool reference to immediates. This is used by
11167 fp moves, that force all constants to memory to allow combining. */
11169 if (GET_CODE (operands[1]) == MEM
11170 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
11171 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
11172 operands[1] = get_pool_constant (XEXP (operands[1], 0));
11173 if (push_operand (operands[0], VOIDmode))
11175 operands[0] = copy_rtx (operands[0]);
11176 PUT_MODE (operands[0], Pmode);
11179 operands[0] = gen_lowpart (DImode, operands[0]);
11180 operands[1] = gen_lowpart (DImode, operands[1]);
11181 emit_move_insn (operands[0], operands[1]);
11185 /* The only non-offsettable memory we handle is push. */
11186 if (push_operand (operands[0], VOIDmode))
11189 gcc_assert (GET_CODE (operands[0]) != MEM
11190 || offsettable_memref_p (operands[0]));
11192 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
11193 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
11195 /* When emitting push, take care for source operands on the stack. */
11196 if (push && GET_CODE (operands[1]) == MEM
11197 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
11200 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
11201 XEXP (part[1][2], 0));
11202 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
11203 XEXP (part[1][1], 0));
11206 /* We need to do copy in the right order in case an address register
11207 of the source overlaps the destination. */
11208 if (REG_P (part[0][0]) && GET_CODE (part[1][0]) == MEM)
11210 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
11212 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11215 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
11218 /* Collision in the middle part can be handled by reordering. */
11219 if (collisions == 1 && nparts == 3
11220 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11223 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
11224 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
11227 /* If there are more collisions, we can't handle it by reordering.
11228 Do an lea to the last part and use only one colliding move. */
11229 else if (collisions > 1)
11235 base = part[0][nparts - 1];
11237 /* Handle the case when the last part isn't valid for lea.
11238 Happens in 64-bit mode storing the 12-byte XFmode. */
11239 if (GET_MODE (base) != Pmode)
11240 base = gen_rtx_REG (Pmode, REGNO (base));
11242 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
11243 part[1][0] = replace_equiv_address (part[1][0], base);
11244 part[1][1] = replace_equiv_address (part[1][1],
11245 plus_constant (base, UNITS_PER_WORD));
11247 part[1][2] = replace_equiv_address (part[1][2],
11248 plus_constant (base, 8));
11258 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
11259 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
11260 emit_move_insn (part[0][2], part[1][2]);
11265 /* In 64bit mode we don't have 32bit push available. In case this is
11266 register, it is OK - we will just use larger counterpart. We also
11267 retype memory - these comes from attempt to avoid REX prefix on
11268 moving of second half of TFmode value. */
11269 if (GET_MODE (part[1][1]) == SImode)
11271 switch (GET_CODE (part[1][1]))
11274 part[1][1] = adjust_address (part[1][1], DImode, 0);
11278 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
11282 gcc_unreachable ();
11285 if (GET_MODE (part[1][0]) == SImode)
11286 part[1][0] = part[1][1];
11289 emit_move_insn (part[0][1], part[1][1]);
11290 emit_move_insn (part[0][0], part[1][0]);
11294 /* Choose correct order to not overwrite the source before it is copied. */
11295 if ((REG_P (part[0][0])
11296 && REG_P (part[1][1])
11297 && (REGNO (part[0][0]) == REGNO (part[1][1])
11299 && REGNO (part[0][0]) == REGNO (part[1][2]))))
11301 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
11305 operands[2] = part[0][2];
11306 operands[3] = part[0][1];
11307 operands[4] = part[0][0];
11308 operands[5] = part[1][2];
11309 operands[6] = part[1][1];
11310 operands[7] = part[1][0];
11314 operands[2] = part[0][1];
11315 operands[3] = part[0][0];
11316 operands[5] = part[1][1];
11317 operands[6] = part[1][0];
11324 operands[2] = part[0][0];
11325 operands[3] = part[0][1];
11326 operands[4] = part[0][2];
11327 operands[5] = part[1][0];
11328 operands[6] = part[1][1];
11329 operands[7] = part[1][2];
11333 operands[2] = part[0][0];
11334 operands[3] = part[0][1];
11335 operands[5] = part[1][0];
11336 operands[6] = part[1][1];
11340 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
11343 if (GET_CODE (operands[5]) == CONST_INT
11344 && operands[5] != const0_rtx
11345 && REG_P (operands[2]))
11347 if (GET_CODE (operands[6]) == CONST_INT
11348 && INTVAL (operands[6]) == INTVAL (operands[5]))
11349 operands[6] = operands[2];
11352 && GET_CODE (operands[7]) == CONST_INT
11353 && INTVAL (operands[7]) == INTVAL (operands[5]))
11354 operands[7] = operands[2];
11358 && GET_CODE (operands[6]) == CONST_INT
11359 && operands[6] != const0_rtx
11360 && REG_P (operands[3])
11361 && GET_CODE (operands[7]) == CONST_INT
11362 && INTVAL (operands[7]) == INTVAL (operands[6]))
11363 operands[7] = operands[3];
11366 emit_move_insn (operands[2], operands[5]);
11367 emit_move_insn (operands[3], operands[6]);
11369 emit_move_insn (operands[4], operands[7]);
11374 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
11375 left shift by a constant, either using a single shift or
11376 a sequence of add instructions. */
11379 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
11383 emit_insn ((mode == DImode
11385 : gen_adddi3) (operand, operand, operand));
11387 else if (!optimize_size
11388 && count * ix86_cost->add <= ix86_cost->shift_const)
11391 for (i=0; i<count; i++)
11393 emit_insn ((mode == DImode
11395 : gen_adddi3) (operand, operand, operand));
11399 emit_insn ((mode == DImode
11401 : gen_ashldi3) (operand, operand, GEN_INT (count)));
11405 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
11407 rtx low[2], high[2];
11409 const int single_width = mode == DImode ? 32 : 64;
11411 if (GET_CODE (operands[2]) == CONST_INT)
11413 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11414 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11416 if (count >= single_width)
11418 emit_move_insn (high[0], low[1]);
11419 emit_move_insn (low[0], const0_rtx);
11421 if (count > single_width)
11422 ix86_expand_ashl_const (high[0], count - single_width, mode);
11426 if (!rtx_equal_p (operands[0], operands[1]))
11427 emit_move_insn (operands[0], operands[1]);
11428 emit_insn ((mode == DImode
11430 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
11431 ix86_expand_ashl_const (low[0], count, mode);
11436 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11438 if (operands[1] == const1_rtx)
11440 /* Assuming we've chosen a QImode capable registers, then 1 << N
11441 can be done with two 32/64-bit shifts, no branches, no cmoves. */
11442 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
11444 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
11446 ix86_expand_clear (low[0]);
11447 ix86_expand_clear (high[0]);
11448 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
11450 d = gen_lowpart (QImode, low[0]);
11451 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
11452 s = gen_rtx_EQ (QImode, flags, const0_rtx);
11453 emit_insn (gen_rtx_SET (VOIDmode, d, s));
11455 d = gen_lowpart (QImode, high[0]);
11456 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
11457 s = gen_rtx_NE (QImode, flags, const0_rtx);
11458 emit_insn (gen_rtx_SET (VOIDmode, d, s));
11461 /* Otherwise, we can get the same results by manually performing
11462 a bit extract operation on bit 5/6, and then performing the two
11463 shifts. The two methods of getting 0/1 into low/high are exactly
11464 the same size. Avoiding the shift in the bit extract case helps
11465 pentium4 a bit; no one else seems to care much either way. */
11470 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
11471 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
11473 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
11474 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
11476 emit_insn ((mode == DImode
11478 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
11479 emit_insn ((mode == DImode
11481 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
11482 emit_move_insn (low[0], high[0]);
11483 emit_insn ((mode == DImode
11485 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
11488 emit_insn ((mode == DImode
11490 : gen_ashldi3) (low[0], low[0], operands[2]));
11491 emit_insn ((mode == DImode
11493 : gen_ashldi3) (high[0], high[0], operands[2]));
11497 if (operands[1] == constm1_rtx)
11499 /* For -1 << N, we can avoid the shld instruction, because we
11500 know that we're shifting 0...31/63 ones into a -1. */
11501 emit_move_insn (low[0], constm1_rtx);
11503 emit_move_insn (high[0], low[0]);
11505 emit_move_insn (high[0], constm1_rtx);
11509 if (!rtx_equal_p (operands[0], operands[1]))
11510 emit_move_insn (operands[0], operands[1]);
11512 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11513 emit_insn ((mode == DImode
11515 : gen_x86_64_shld) (high[0], low[0], operands[2]));
11518 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
11520 if (TARGET_CMOVE && scratch)
11522 ix86_expand_clear (scratch);
11523 emit_insn ((mode == DImode
11524 ? gen_x86_shift_adj_1
11525 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
11528 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
11532 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
11534 rtx low[2], high[2];
11536 const int single_width = mode == DImode ? 32 : 64;
11538 if (GET_CODE (operands[2]) == CONST_INT)
11540 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11541 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11543 if (count == single_width * 2 - 1)
11545 emit_move_insn (high[0], high[1]);
11546 emit_insn ((mode == DImode
11548 : gen_ashrdi3) (high[0], high[0],
11549 GEN_INT (single_width - 1)));
11550 emit_move_insn (low[0], high[0]);
11553 else if (count >= single_width)
11555 emit_move_insn (low[0], high[1]);
11556 emit_move_insn (high[0], low[0]);
11557 emit_insn ((mode == DImode
11559 : gen_ashrdi3) (high[0], high[0],
11560 GEN_INT (single_width - 1)));
11561 if (count > single_width)
11562 emit_insn ((mode == DImode
11564 : gen_ashrdi3) (low[0], low[0],
11565 GEN_INT (count - single_width)));
11569 if (!rtx_equal_p (operands[0], operands[1]))
11570 emit_move_insn (operands[0], operands[1]);
11571 emit_insn ((mode == DImode
11573 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
11574 emit_insn ((mode == DImode
11576 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
11581 if (!rtx_equal_p (operands[0], operands[1]))
11582 emit_move_insn (operands[0], operands[1]);
11584 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11586 emit_insn ((mode == DImode
11588 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
11589 emit_insn ((mode == DImode
11591 : gen_ashrdi3) (high[0], high[0], operands[2]));
11593 if (TARGET_CMOVE && scratch)
11595 emit_move_insn (scratch, high[0]);
11596 emit_insn ((mode == DImode
11598 : gen_ashrdi3) (scratch, scratch,
11599 GEN_INT (single_width - 1)));
11600 emit_insn ((mode == DImode
11601 ? gen_x86_shift_adj_1
11602 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
11606 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
11611 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
11613 rtx low[2], high[2];
11615 const int single_width = mode == DImode ? 32 : 64;
11617 if (GET_CODE (operands[2]) == CONST_INT)
11619 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11620 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11622 if (count >= single_width)
11624 emit_move_insn (low[0], high[1]);
11625 ix86_expand_clear (high[0]);
11627 if (count > single_width)
11628 emit_insn ((mode == DImode
11630 : gen_lshrdi3) (low[0], low[0],
11631 GEN_INT (count - single_width)));
11635 if (!rtx_equal_p (operands[0], operands[1]))
11636 emit_move_insn (operands[0], operands[1]);
11637 emit_insn ((mode == DImode
11639 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
11640 emit_insn ((mode == DImode
11642 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
11647 if (!rtx_equal_p (operands[0], operands[1]))
11648 emit_move_insn (operands[0], operands[1]);
11650 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11652 emit_insn ((mode == DImode
11654 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
11655 emit_insn ((mode == DImode
11657 : gen_lshrdi3) (high[0], high[0], operands[2]));
11659 /* Heh. By reversing the arguments, we can reuse this pattern. */
11660 if (TARGET_CMOVE && scratch)
11662 ix86_expand_clear (scratch);
11663 emit_insn ((mode == DImode
11664 ? gen_x86_shift_adj_1
11665 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
11669 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
11673 /* Helper function for the string operations below. Dest VARIABLE whether
11674 it is aligned to VALUE bytes. If true, jump to the label. */
11676 ix86_expand_aligntest (rtx variable, int value)
11678 rtx label = gen_label_rtx ();
11679 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
11680 if (GET_MODE (variable) == DImode)
11681 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
11683 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
11684 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
11689 /* Adjust COUNTER by the VALUE. */
11691 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
11693 if (GET_MODE (countreg) == DImode)
11694 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
11696 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
11699 /* Zero extend possibly SImode EXP to Pmode register. */
11701 ix86_zero_extend_to_Pmode (rtx exp)
11704 if (GET_MODE (exp) == VOIDmode)
11705 return force_reg (Pmode, exp);
11706 if (GET_MODE (exp) == Pmode)
11707 return copy_to_mode_reg (Pmode, exp);
11708 r = gen_reg_rtx (Pmode);
11709 emit_insn (gen_zero_extendsidi2 (r, exp));
11713 /* Expand string move (memcpy) operation. Use i386 string operations when
11714 profitable. expand_clrmem contains similar code. */
11716 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
11718 rtx srcreg, destreg, countreg, srcexp, destexp;
11719 enum machine_mode counter_mode;
11720 HOST_WIDE_INT align = 0;
11721 unsigned HOST_WIDE_INT count = 0;
11723 if (GET_CODE (align_exp) == CONST_INT)
11724 align = INTVAL (align_exp);
11726 /* Can't use any of this if the user has appropriated esi or edi. */
11727 if (global_regs[4] || global_regs[5])
11730 /* This simple hack avoids all inlining code and simplifies code below. */
11731 if (!TARGET_ALIGN_STRINGOPS)
11734 if (GET_CODE (count_exp) == CONST_INT)
11736 count = INTVAL (count_exp);
11737 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
11741 /* Figure out proper mode for counter. For 32bits it is always SImode,
11742 for 64bits use SImode when possible, otherwise DImode.
11743 Set count to number of bytes copied when known at compile time. */
11745 || GET_MODE (count_exp) == SImode
11746 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
11747 counter_mode = SImode;
11749 counter_mode = DImode;
11751 gcc_assert (counter_mode == SImode || counter_mode == DImode);
11753 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
11754 if (destreg != XEXP (dst, 0))
11755 dst = replace_equiv_address_nv (dst, destreg);
11756 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
11757 if (srcreg != XEXP (src, 0))
11758 src = replace_equiv_address_nv (src, srcreg);
11760 /* When optimizing for size emit simple rep ; movsb instruction for
11761 counts not divisible by 4, except when (movsl;)*(movsw;)?(movsb;)?
11762 sequence is shorter than mov{b,l} $count, %{ecx,cl}; rep; movsb.
11763 Sice of (movsl;)*(movsw;)?(movsb;)? sequence is
11764 count / 4 + (count & 3), the other sequence is either 4 or 7 bytes,
11765 but we don't know whether upper 24 (resp. 56) bits of %ecx will be
11766 known to be zero or not. The rep; movsb sequence causes higher
11767 register pressure though, so take that into account. */
11769 if ((!optimize || optimize_size)
11774 || (count & 3) + count / 4 > 6))))
11776 emit_insn (gen_cld ());
11777 countreg = ix86_zero_extend_to_Pmode (count_exp);
11778 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
11779 srcexp = gen_rtx_PLUS (Pmode, srcreg, countreg);
11780 emit_insn (gen_rep_mov (destreg, dst, srcreg, src, countreg,
11784 /* For constant aligned (or small unaligned) copies use rep movsl
11785 followed by code copying the rest. For PentiumPro ensure 8 byte
11786 alignment to allow rep movsl acceleration. */
11788 else if (count != 0
11790 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
11791 || optimize_size || count < (unsigned int) 64))
11793 unsigned HOST_WIDE_INT offset = 0;
11794 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
11795 rtx srcmem, dstmem;
11797 emit_insn (gen_cld ());
11798 if (count & ~(size - 1))
11800 if ((TARGET_SINGLE_STRINGOP || optimize_size) && count < 5 * 4)
11802 enum machine_mode movs_mode = size == 4 ? SImode : DImode;
11804 while (offset < (count & ~(size - 1)))
11806 srcmem = adjust_automodify_address_nv (src, movs_mode,
11808 dstmem = adjust_automodify_address_nv (dst, movs_mode,
11810 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11816 countreg = GEN_INT ((count >> (size == 4 ? 2 : 3))
11817 & (TARGET_64BIT ? -1 : 0x3fffffff));
11818 countreg = copy_to_mode_reg (counter_mode, countreg);
11819 countreg = ix86_zero_extend_to_Pmode (countreg);
11821 destexp = gen_rtx_ASHIFT (Pmode, countreg,
11822 GEN_INT (size == 4 ? 2 : 3));
11823 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
11824 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
11826 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
11827 countreg, destexp, srcexp));
11828 offset = count & ~(size - 1);
11831 if (size == 8 && (count & 0x04))
11833 srcmem = adjust_automodify_address_nv (src, SImode, srcreg,
11835 dstmem = adjust_automodify_address_nv (dst, SImode, destreg,
11837 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11842 srcmem = adjust_automodify_address_nv (src, HImode, srcreg,
11844 dstmem = adjust_automodify_address_nv (dst, HImode, destreg,
11846 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11851 srcmem = adjust_automodify_address_nv (src, QImode, srcreg,
11853 dstmem = adjust_automodify_address_nv (dst, QImode, destreg,
11855 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11858 /* The generic code based on the glibc implementation:
11859 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
11860 allowing accelerated copying there)
11861 - copy the data using rep movsl
11862 - copy the rest. */
11867 rtx srcmem, dstmem;
11868 int desired_alignment = (TARGET_PENTIUMPRO
11869 && (count == 0 || count >= (unsigned int) 260)
11870 ? 8 : UNITS_PER_WORD);
11871 /* Get rid of MEM_OFFSETs, they won't be accurate. */
11872 dst = change_address (dst, BLKmode, destreg);
11873 src = change_address (src, BLKmode, srcreg);
11875 /* In case we don't know anything about the alignment, default to
11876 library version, since it is usually equally fast and result in
11879 Also emit call when we know that the count is large and call overhead
11880 will not be important. */
11881 if (!TARGET_INLINE_ALL_STRINGOPS
11882 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
11885 if (TARGET_SINGLE_STRINGOP)
11886 emit_insn (gen_cld ());
11888 countreg2 = gen_reg_rtx (Pmode);
11889 countreg = copy_to_mode_reg (counter_mode, count_exp);
11891 /* We don't use loops to align destination and to copy parts smaller
11892 than 4 bytes, because gcc is able to optimize such code better (in
11893 the case the destination or the count really is aligned, gcc is often
11894 able to predict the branches) and also it is friendlier to the
11895 hardware branch prediction.
11897 Using loops is beneficial for generic case, because we can
11898 handle small counts using the loops. Many CPUs (such as Athlon)
11899 have large REP prefix setup costs.
11901 This is quite costly. Maybe we can revisit this decision later or
11902 add some customizability to this code. */
11904 if (count == 0 && align < desired_alignment)
11906 label = gen_label_rtx ();
11907 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
11908 LEU, 0, counter_mode, 1, label);
11912 rtx label = ix86_expand_aligntest (destreg, 1);
11913 srcmem = change_address (src, QImode, srcreg);
11914 dstmem = change_address (dst, QImode, destreg);
11915 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11916 ix86_adjust_counter (countreg, 1);
11917 emit_label (label);
11918 LABEL_NUSES (label) = 1;
11922 rtx label = ix86_expand_aligntest (destreg, 2);
11923 srcmem = change_address (src, HImode, srcreg);
11924 dstmem = change_address (dst, HImode, destreg);
11925 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11926 ix86_adjust_counter (countreg, 2);
11927 emit_label (label);
11928 LABEL_NUSES (label) = 1;
11930 if (align <= 4 && desired_alignment > 4)
11932 rtx label = ix86_expand_aligntest (destreg, 4);
11933 srcmem = change_address (src, SImode, srcreg);
11934 dstmem = change_address (dst, SImode, destreg);
11935 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11936 ix86_adjust_counter (countreg, 4);
11937 emit_label (label);
11938 LABEL_NUSES (label) = 1;
11941 if (label && desired_alignment > 4 && !TARGET_64BIT)
11943 emit_label (label);
11944 LABEL_NUSES (label) = 1;
11947 if (!TARGET_SINGLE_STRINGOP)
11948 emit_insn (gen_cld ());
11951 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
11953 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
11957 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
11958 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
11960 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
11961 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
11962 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
11963 countreg2, destexp, srcexp));
11967 emit_label (label);
11968 LABEL_NUSES (label) = 1;
11970 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
11972 srcmem = change_address (src, SImode, srcreg);
11973 dstmem = change_address (dst, SImode, destreg);
11974 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11976 if ((align <= 4 || count == 0) && TARGET_64BIT)
11978 rtx label = ix86_expand_aligntest (countreg, 4);
11979 srcmem = change_address (src, SImode, srcreg);
11980 dstmem = change_address (dst, SImode, destreg);
11981 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11982 emit_label (label);
11983 LABEL_NUSES (label) = 1;
11985 if (align > 2 && count != 0 && (count & 2))
11987 srcmem = change_address (src, HImode, srcreg);
11988 dstmem = change_address (dst, HImode, destreg);
11989 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11991 if (align <= 2 || count == 0)
11993 rtx label = ix86_expand_aligntest (countreg, 2);
11994 srcmem = change_address (src, HImode, srcreg);
11995 dstmem = change_address (dst, HImode, destreg);
11996 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11997 emit_label (label);
11998 LABEL_NUSES (label) = 1;
12000 if (align > 1 && count != 0 && (count & 1))
12002 srcmem = change_address (src, QImode, srcreg);
12003 dstmem = change_address (dst, QImode, destreg);
12004 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12006 if (align <= 1 || count == 0)
12008 rtx label = ix86_expand_aligntest (countreg, 1);
12009 srcmem = change_address (src, QImode, srcreg);
12010 dstmem = change_address (dst, QImode, destreg);
12011 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
12012 emit_label (label);
12013 LABEL_NUSES (label) = 1;
12020 /* Expand string clear operation (bzero). Use i386 string operations when
12021 profitable. expand_movmem contains similar code. */
12023 ix86_expand_clrmem (rtx dst, rtx count_exp, rtx align_exp)
12025 rtx destreg, zeroreg, countreg, destexp;
12026 enum machine_mode counter_mode;
12027 HOST_WIDE_INT align = 0;
12028 unsigned HOST_WIDE_INT count = 0;
12030 if (GET_CODE (align_exp) == CONST_INT)
12031 align = INTVAL (align_exp);
12033 /* Can't use any of this if the user has appropriated esi. */
12034 if (global_regs[4])
12037 /* This simple hack avoids all inlining code and simplifies code below. */
12038 if (!TARGET_ALIGN_STRINGOPS)
12041 if (GET_CODE (count_exp) == CONST_INT)
12043 count = INTVAL (count_exp);
12044 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
12047 /* Figure out proper mode for counter. For 32bits it is always SImode,
12048 for 64bits use SImode when possible, otherwise DImode.
12049 Set count to number of bytes copied when known at compile time. */
12051 || GET_MODE (count_exp) == SImode
12052 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
12053 counter_mode = SImode;
12055 counter_mode = DImode;
12057 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
12058 if (destreg != XEXP (dst, 0))
12059 dst = replace_equiv_address_nv (dst, destreg);
12062 /* When optimizing for size emit simple rep ; movsb instruction for
12063 counts not divisible by 4. The movl $N, %ecx; rep; stosb
12064 sequence is 7 bytes long, so if optimizing for size and count is
12065 small enough that some stosl, stosw and stosb instructions without
12066 rep are shorter, fall back into the next if. */
12068 if ((!optimize || optimize_size)
12071 && (!optimize_size || (count & 0x03) + (count >> 2) > 7))))
12073 emit_insn (gen_cld ());
12075 countreg = ix86_zero_extend_to_Pmode (count_exp);
12076 zeroreg = copy_to_mode_reg (QImode, const0_rtx);
12077 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
12078 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg, destexp));
12080 else if (count != 0
12082 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
12083 || optimize_size || count < (unsigned int) 64))
12085 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
12086 unsigned HOST_WIDE_INT offset = 0;
12088 emit_insn (gen_cld ());
12090 zeroreg = copy_to_mode_reg (size == 4 ? SImode : DImode, const0_rtx);
12091 if (count & ~(size - 1))
12093 unsigned HOST_WIDE_INT repcount;
12094 unsigned int max_nonrep;
12096 repcount = count >> (size == 4 ? 2 : 3);
12098 repcount &= 0x3fffffff;
12100 /* movl $N, %ecx; rep; stosl is 7 bytes, while N x stosl is N bytes.
12101 movl $N, %ecx; rep; stosq is 8 bytes, while N x stosq is 2xN
12102 bytes. In both cases the latter seems to be faster for small
12104 max_nonrep = size == 4 ? 7 : 4;
12105 if (!optimize_size)
12108 case PROCESSOR_PENTIUM4:
12109 case PROCESSOR_NOCONA:
12116 if (repcount <= max_nonrep)
12117 while (repcount-- > 0)
12119 rtx mem = adjust_automodify_address_nv (dst,
12120 GET_MODE (zeroreg),
12122 emit_insn (gen_strset (destreg, mem, zeroreg));
12127 countreg = copy_to_mode_reg (counter_mode, GEN_INT (repcount));
12128 countreg = ix86_zero_extend_to_Pmode (countreg);
12129 destexp = gen_rtx_ASHIFT (Pmode, countreg,
12130 GEN_INT (size == 4 ? 2 : 3));
12131 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12132 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg,
12134 offset = count & ~(size - 1);
12137 if (size == 8 && (count & 0x04))
12139 rtx mem = adjust_automodify_address_nv (dst, SImode, destreg,
12141 emit_insn (gen_strset (destreg, mem,
12142 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12147 rtx mem = adjust_automodify_address_nv (dst, HImode, destreg,
12149 emit_insn (gen_strset (destreg, mem,
12150 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12155 rtx mem = adjust_automodify_address_nv (dst, QImode, destreg,
12157 emit_insn (gen_strset (destreg, mem,
12158 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12165 /* Compute desired alignment of the string operation. */
12166 int desired_alignment = (TARGET_PENTIUMPRO
12167 && (count == 0 || count >= (unsigned int) 260)
12168 ? 8 : UNITS_PER_WORD);
12170 /* In case we don't know anything about the alignment, default to
12171 library version, since it is usually equally fast and result in
12174 Also emit call when we know that the count is large and call overhead
12175 will not be important. */
12176 if (!TARGET_INLINE_ALL_STRINGOPS
12177 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
12180 if (TARGET_SINGLE_STRINGOP)
12181 emit_insn (gen_cld ());
12183 countreg2 = gen_reg_rtx (Pmode);
12184 countreg = copy_to_mode_reg (counter_mode, count_exp);
12185 zeroreg = copy_to_mode_reg (Pmode, const0_rtx);
12186 /* Get rid of MEM_OFFSET, it won't be accurate. */
12187 dst = change_address (dst, BLKmode, destreg);
12189 if (count == 0 && align < desired_alignment)
12191 label = gen_label_rtx ();
12192 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
12193 LEU, 0, counter_mode, 1, label);
12197 rtx label = ix86_expand_aligntest (destreg, 1);
12198 emit_insn (gen_strset (destreg, dst,
12199 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12200 ix86_adjust_counter (countreg, 1);
12201 emit_label (label);
12202 LABEL_NUSES (label) = 1;
12206 rtx label = ix86_expand_aligntest (destreg, 2);
12207 emit_insn (gen_strset (destreg, dst,
12208 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12209 ix86_adjust_counter (countreg, 2);
12210 emit_label (label);
12211 LABEL_NUSES (label) = 1;
12213 if (align <= 4 && desired_alignment > 4)
12215 rtx label = ix86_expand_aligntest (destreg, 4);
12216 emit_insn (gen_strset (destreg, dst,
12218 ? gen_rtx_SUBREG (SImode, zeroreg, 0)
12220 ix86_adjust_counter (countreg, 4);
12221 emit_label (label);
12222 LABEL_NUSES (label) = 1;
12225 if (label && desired_alignment > 4 && !TARGET_64BIT)
12227 emit_label (label);
12228 LABEL_NUSES (label) = 1;
12232 if (!TARGET_SINGLE_STRINGOP)
12233 emit_insn (gen_cld ());
12236 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
12238 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
12242 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
12243 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
12245 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12246 emit_insn (gen_rep_stos (destreg, countreg2, dst, zeroreg, destexp));
12250 emit_label (label);
12251 LABEL_NUSES (label) = 1;
12254 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
12255 emit_insn (gen_strset (destreg, dst,
12256 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12257 if (TARGET_64BIT && (align <= 4 || count == 0))
12259 rtx label = ix86_expand_aligntest (countreg, 4);
12260 emit_insn (gen_strset (destreg, dst,
12261 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12262 emit_label (label);
12263 LABEL_NUSES (label) = 1;
12265 if (align > 2 && count != 0 && (count & 2))
12266 emit_insn (gen_strset (destreg, dst,
12267 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12268 if (align <= 2 || count == 0)
12270 rtx label = ix86_expand_aligntest (countreg, 2);
12271 emit_insn (gen_strset (destreg, dst,
12272 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12273 emit_label (label);
12274 LABEL_NUSES (label) = 1;
12276 if (align > 1 && count != 0 && (count & 1))
12277 emit_insn (gen_strset (destreg, dst,
12278 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12279 if (align <= 1 || count == 0)
12281 rtx label = ix86_expand_aligntest (countreg, 1);
12282 emit_insn (gen_strset (destreg, dst,
12283 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12284 emit_label (label);
12285 LABEL_NUSES (label) = 1;
12291 /* Expand strlen. */
12293 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
12295 rtx addr, scratch1, scratch2, scratch3, scratch4;
12297 /* The generic case of strlen expander is long. Avoid it's
12298 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
12300 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12301 && !TARGET_INLINE_ALL_STRINGOPS
12303 && (GET_CODE (align) != CONST_INT || INTVAL (align) < 4))
12306 addr = force_reg (Pmode, XEXP (src, 0));
12307 scratch1 = gen_reg_rtx (Pmode);
12309 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12312 /* Well it seems that some optimizer does not combine a call like
12313 foo(strlen(bar), strlen(bar));
12314 when the move and the subtraction is done here. It does calculate
12315 the length just once when these instructions are done inside of
12316 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
12317 often used and I use one fewer register for the lifetime of
12318 output_strlen_unroll() this is better. */
12320 emit_move_insn (out, addr);
12322 ix86_expand_strlensi_unroll_1 (out, src, align);
12324 /* strlensi_unroll_1 returns the address of the zero at the end of
12325 the string, like memchr(), so compute the length by subtracting
12326 the start address. */
12328 emit_insn (gen_subdi3 (out, out, addr));
12330 emit_insn (gen_subsi3 (out, out, addr));
12335 scratch2 = gen_reg_rtx (Pmode);
12336 scratch3 = gen_reg_rtx (Pmode);
12337 scratch4 = force_reg (Pmode, constm1_rtx);
12339 emit_move_insn (scratch3, addr);
12340 eoschar = force_reg (QImode, eoschar);
12342 emit_insn (gen_cld ());
12343 src = replace_equiv_address_nv (src, scratch3);
12345 /* If .md starts supporting :P, this can be done in .md. */
12346 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
12347 scratch4), UNSPEC_SCAS);
12348 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
12351 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
12352 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
12356 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
12357 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
12363 /* Expand the appropriate insns for doing strlen if not just doing
12366 out = result, initialized with the start address
12367 align_rtx = alignment of the address.
12368 scratch = scratch register, initialized with the startaddress when
12369 not aligned, otherwise undefined
12371 This is just the body. It needs the initializations mentioned above and
12372 some address computing at the end. These things are done in i386.md. */
12375 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
12379 rtx align_2_label = NULL_RTX;
12380 rtx align_3_label = NULL_RTX;
12381 rtx align_4_label = gen_label_rtx ();
12382 rtx end_0_label = gen_label_rtx ();
12384 rtx tmpreg = gen_reg_rtx (SImode);
12385 rtx scratch = gen_reg_rtx (SImode);
12389 if (GET_CODE (align_rtx) == CONST_INT)
12390 align = INTVAL (align_rtx);
12392 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
12394 /* Is there a known alignment and is it less than 4? */
12397 rtx scratch1 = gen_reg_rtx (Pmode);
12398 emit_move_insn (scratch1, out);
12399 /* Is there a known alignment and is it not 2? */
12402 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
12403 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
12405 /* Leave just the 3 lower bits. */
12406 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
12407 NULL_RTX, 0, OPTAB_WIDEN);
12409 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
12410 Pmode, 1, align_4_label);
12411 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
12412 Pmode, 1, align_2_label);
12413 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
12414 Pmode, 1, align_3_label);
12418 /* Since the alignment is 2, we have to check 2 or 0 bytes;
12419 check if is aligned to 4 - byte. */
12421 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
12422 NULL_RTX, 0, OPTAB_WIDEN);
12424 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
12425 Pmode, 1, align_4_label);
12428 mem = change_address (src, QImode, out);
12430 /* Now compare the bytes. */
12432 /* Compare the first n unaligned byte on a byte per byte basis. */
12433 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
12434 QImode, 1, end_0_label);
12436 /* Increment the address. */
12438 emit_insn (gen_adddi3 (out, out, const1_rtx));
12440 emit_insn (gen_addsi3 (out, out, const1_rtx));
12442 /* Not needed with an alignment of 2 */
12445 emit_label (align_2_label);
12447 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
12451 emit_insn (gen_adddi3 (out, out, const1_rtx));
12453 emit_insn (gen_addsi3 (out, out, const1_rtx));
12455 emit_label (align_3_label);
12458 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
12462 emit_insn (gen_adddi3 (out, out, const1_rtx));
12464 emit_insn (gen_addsi3 (out, out, const1_rtx));
12467 /* Generate loop to check 4 bytes at a time. It is not a good idea to
12468 align this loop. It gives only huge programs, but does not help to
12470 emit_label (align_4_label);
12472 mem = change_address (src, SImode, out);
12473 emit_move_insn (scratch, mem);
12475 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
12477 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
12479 /* This formula yields a nonzero result iff one of the bytes is zero.
12480 This saves three branches inside loop and many cycles. */
12482 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
12483 emit_insn (gen_one_cmplsi2 (scratch, scratch));
12484 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
12485 emit_insn (gen_andsi3 (tmpreg, tmpreg,
12486 gen_int_mode (0x80808080, SImode)));
12487 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
12492 rtx reg = gen_reg_rtx (SImode);
12493 rtx reg2 = gen_reg_rtx (Pmode);
12494 emit_move_insn (reg, tmpreg);
12495 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
12497 /* If zero is not in the first two bytes, move two bytes forward. */
12498 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
12499 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12500 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
12501 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
12502 gen_rtx_IF_THEN_ELSE (SImode, tmp,
12505 /* Emit lea manually to avoid clobbering of flags. */
12506 emit_insn (gen_rtx_SET (SImode, reg2,
12507 gen_rtx_PLUS (Pmode, out, const2_rtx)));
12509 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12510 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
12511 emit_insn (gen_rtx_SET (VOIDmode, out,
12512 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
12519 rtx end_2_label = gen_label_rtx ();
12520 /* Is zero in the first two bytes? */
12522 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
12523 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12524 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
12525 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12526 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
12528 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12529 JUMP_LABEL (tmp) = end_2_label;
12531 /* Not in the first two. Move two bytes forward. */
12532 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
12534 emit_insn (gen_adddi3 (out, out, const2_rtx));
12536 emit_insn (gen_addsi3 (out, out, const2_rtx));
12538 emit_label (end_2_label);
12542 /* Avoid branch in fixing the byte. */
12543 tmpreg = gen_lowpart (QImode, tmpreg);
12544 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
12545 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, 17), const0_rtx);
12547 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
12549 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
12551 emit_label (end_0_label);
12555 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
12556 rtx callarg2 ATTRIBUTE_UNUSED,
12557 rtx pop, int sibcall)
12559 rtx use = NULL, call;
12561 if (pop == const0_rtx)
12563 gcc_assert (!TARGET_64BIT || !pop);
12566 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
12567 fnaddr = machopic_indirect_call_target (fnaddr);
12569 /* Static functions and indirect calls don't need the pic register. */
12570 if (! TARGET_64BIT && flag_pic
12571 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
12572 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
12573 use_reg (&use, pic_offset_table_rtx);
12575 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
12577 rtx al = gen_rtx_REG (QImode, 0);
12578 emit_move_insn (al, callarg2);
12579 use_reg (&use, al);
12581 #endif /* TARGET_MACHO */
12583 if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
12585 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
12586 fnaddr = gen_rtx_MEM (QImode, fnaddr);
12588 if (sibcall && TARGET_64BIT
12589 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
12592 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
12593 fnaddr = gen_rtx_REG (Pmode, FIRST_REX_INT_REG + 3 /* R11 */);
12594 emit_move_insn (fnaddr, addr);
12595 fnaddr = gen_rtx_MEM (QImode, fnaddr);
12598 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
12600 call = gen_rtx_SET (VOIDmode, retval, call);
12603 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
12604 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
12605 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
12608 call = emit_call_insn (call);
12610 CALL_INSN_FUNCTION_USAGE (call) = use;
12614 /* Clear stack slot assignments remembered from previous functions.
12615 This is called from INIT_EXPANDERS once before RTL is emitted for each
12618 static struct machine_function *
12619 ix86_init_machine_status (void)
12621 struct machine_function *f;
12623 f = ggc_alloc_cleared (sizeof (struct machine_function));
12624 f->use_fast_prologue_epilogue_nregs = -1;
12629 /* Return a MEM corresponding to a stack slot with mode MODE.
12630 Allocate a new slot if necessary.
12632 The RTL for a function can have several slots available: N is
12633 which slot to use. */
12636 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
12638 struct stack_local_entry *s;
12640 gcc_assert (n < MAX_386_STACK_LOCALS);
12642 for (s = ix86_stack_locals; s; s = s->next)
12643 if (s->mode == mode && s->n == n)
12646 s = (struct stack_local_entry *)
12647 ggc_alloc (sizeof (struct stack_local_entry));
12650 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
12652 s->next = ix86_stack_locals;
12653 ix86_stack_locals = s;
12657 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12659 static GTY(()) rtx ix86_tls_symbol;
12661 ix86_tls_get_addr (void)
12664 if (!ix86_tls_symbol)
12666 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
12667 (TARGET_GNU_TLS && !TARGET_64BIT)
12668 ? "___tls_get_addr"
12669 : "__tls_get_addr");
12672 return ix86_tls_symbol;
12675 /* Calculate the length of the memory address in the instruction
12676 encoding. Does not include the one-byte modrm, opcode, or prefix. */
12679 memory_address_length (rtx addr)
12681 struct ix86_address parts;
12682 rtx base, index, disp;
12686 if (GET_CODE (addr) == PRE_DEC
12687 || GET_CODE (addr) == POST_INC
12688 || GET_CODE (addr) == PRE_MODIFY
12689 || GET_CODE (addr) == POST_MODIFY)
12692 ok = ix86_decompose_address (addr, &parts);
12695 if (parts.base && GET_CODE (parts.base) == SUBREG)
12696 parts.base = SUBREG_REG (parts.base);
12697 if (parts.index && GET_CODE (parts.index) == SUBREG)
12698 parts.index = SUBREG_REG (parts.index);
12701 index = parts.index;
12706 - esp as the base always wants an index,
12707 - ebp as the base always wants a displacement. */
12709 /* Register Indirect. */
12710 if (base && !index && !disp)
12712 /* esp (for its index) and ebp (for its displacement) need
12713 the two-byte modrm form. */
12714 if (addr == stack_pointer_rtx
12715 || addr == arg_pointer_rtx
12716 || addr == frame_pointer_rtx
12717 || addr == hard_frame_pointer_rtx)
12721 /* Direct Addressing. */
12722 else if (disp && !base && !index)
12727 /* Find the length of the displacement constant. */
12730 if (GET_CODE (disp) == CONST_INT
12731 && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K')
12737 /* ebp always wants a displacement. */
12738 else if (base == hard_frame_pointer_rtx)
12741 /* An index requires the two-byte modrm form.... */
12743 /* ...like esp, which always wants an index. */
12744 || base == stack_pointer_rtx
12745 || base == arg_pointer_rtx
12746 || base == frame_pointer_rtx)
12753 /* Compute default value for "length_immediate" attribute. When SHORTFORM
12754 is set, expect that insn have 8bit immediate alternative. */
12756 ix86_attr_length_immediate_default (rtx insn, int shortform)
12760 extract_insn_cached (insn);
12761 for (i = recog_data.n_operands - 1; i >= 0; --i)
12762 if (CONSTANT_P (recog_data.operand[i]))
12766 && GET_CODE (recog_data.operand[i]) == CONST_INT
12767 && CONST_OK_FOR_LETTER_P (INTVAL (recog_data.operand[i]), 'K'))
12771 switch (get_attr_mode (insn))
12782 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
12787 fatal_insn ("unknown insn mode", insn);
12793 /* Compute default value for "length_address" attribute. */
12795 ix86_attr_length_address_default (rtx insn)
12799 if (get_attr_type (insn) == TYPE_LEA)
12801 rtx set = PATTERN (insn);
12803 if (GET_CODE (set) == PARALLEL)
12804 set = XVECEXP (set, 0, 0);
12806 gcc_assert (GET_CODE (set) == SET);
12808 return memory_address_length (SET_SRC (set));
12811 extract_insn_cached (insn);
12812 for (i = recog_data.n_operands - 1; i >= 0; --i)
12813 if (GET_CODE (recog_data.operand[i]) == MEM)
12815 return memory_address_length (XEXP (recog_data.operand[i], 0));
12821 /* Return the maximum number of instructions a cpu can issue. */
12824 ix86_issue_rate (void)
12828 case PROCESSOR_PENTIUM:
12832 case PROCESSOR_PENTIUMPRO:
12833 case PROCESSOR_PENTIUM4:
12834 case PROCESSOR_ATHLON:
12836 case PROCESSOR_NOCONA:
12844 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
12845 by DEP_INSN and nothing set by DEP_INSN. */
12848 ix86_flags_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type)
12852 /* Simplify the test for uninteresting insns. */
12853 if (insn_type != TYPE_SETCC
12854 && insn_type != TYPE_ICMOV
12855 && insn_type != TYPE_FCMOV
12856 && insn_type != TYPE_IBR)
12859 if ((set = single_set (dep_insn)) != 0)
12861 set = SET_DEST (set);
12864 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
12865 && XVECLEN (PATTERN (dep_insn), 0) == 2
12866 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
12867 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
12869 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
12870 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
12875 if (GET_CODE (set) != REG || REGNO (set) != FLAGS_REG)
12878 /* This test is true if the dependent insn reads the flags but
12879 not any other potentially set register. */
12880 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
12883 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
12889 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
12890 address with operands set by DEP_INSN. */
12893 ix86_agi_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type)
12897 if (insn_type == TYPE_LEA
12900 addr = PATTERN (insn);
12902 if (GET_CODE (addr) == PARALLEL)
12903 addr = XVECEXP (addr, 0, 0);
12905 gcc_assert (GET_CODE (addr) == SET);
12907 addr = SET_SRC (addr);
12912 extract_insn_cached (insn);
12913 for (i = recog_data.n_operands - 1; i >= 0; --i)
12914 if (GET_CODE (recog_data.operand[i]) == MEM)
12916 addr = XEXP (recog_data.operand[i], 0);
12923 return modified_in_p (addr, dep_insn);
12927 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
12929 enum attr_type insn_type, dep_insn_type;
12930 enum attr_memory memory;
12932 int dep_insn_code_number;
12934 /* Anti and output dependencies have zero cost on all CPUs. */
12935 if (REG_NOTE_KIND (link) != 0)
12938 dep_insn_code_number = recog_memoized (dep_insn);
12940 /* If we can't recognize the insns, we can't really do anything. */
12941 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
12944 insn_type = get_attr_type (insn);
12945 dep_insn_type = get_attr_type (dep_insn);
12949 case PROCESSOR_PENTIUM:
12950 /* Address Generation Interlock adds a cycle of latency. */
12951 if (ix86_agi_dependant (insn, dep_insn, insn_type))
12954 /* ??? Compares pair with jump/setcc. */
12955 if (ix86_flags_dependant (insn, dep_insn, insn_type))
12958 /* Floating point stores require value to be ready one cycle earlier. */
12959 if (insn_type == TYPE_FMOV
12960 && get_attr_memory (insn) == MEMORY_STORE
12961 && !ix86_agi_dependant (insn, dep_insn, insn_type))
12965 case PROCESSOR_PENTIUMPRO:
12966 memory = get_attr_memory (insn);
12968 /* INT->FP conversion is expensive. */
12969 if (get_attr_fp_int_src (dep_insn))
12972 /* There is one cycle extra latency between an FP op and a store. */
12973 if (insn_type == TYPE_FMOV
12974 && (set = single_set (dep_insn)) != NULL_RTX
12975 && (set2 = single_set (insn)) != NULL_RTX
12976 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
12977 && GET_CODE (SET_DEST (set2)) == MEM)
12980 /* Show ability of reorder buffer to hide latency of load by executing
12981 in parallel with previous instruction in case
12982 previous instruction is not needed to compute the address. */
12983 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
12984 && !ix86_agi_dependant (insn, dep_insn, insn_type))
12986 /* Claim moves to take one cycle, as core can issue one load
12987 at time and the next load can start cycle later. */
12988 if (dep_insn_type == TYPE_IMOV
12989 || dep_insn_type == TYPE_FMOV)
12997 memory = get_attr_memory (insn);
12999 /* The esp dependency is resolved before the instruction is really
13001 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
13002 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
13005 /* INT->FP conversion is expensive. */
13006 if (get_attr_fp_int_src (dep_insn))
13009 /* Show ability of reorder buffer to hide latency of load by executing
13010 in parallel with previous instruction in case
13011 previous instruction is not needed to compute the address. */
13012 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13013 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13015 /* Claim moves to take one cycle, as core can issue one load
13016 at time and the next load can start cycle later. */
13017 if (dep_insn_type == TYPE_IMOV
13018 || dep_insn_type == TYPE_FMOV)
13027 case PROCESSOR_ATHLON:
13029 memory = get_attr_memory (insn);
13031 /* Show ability of reorder buffer to hide latency of load by executing
13032 in parallel with previous instruction in case
13033 previous instruction is not needed to compute the address. */
13034 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
13035 && !ix86_agi_dependant (insn, dep_insn, insn_type))
13037 enum attr_unit unit = get_attr_unit (insn);
13040 /* Because of the difference between the length of integer and
13041 floating unit pipeline preparation stages, the memory operands
13042 for floating point are cheaper.
13044 ??? For Athlon it the difference is most probably 2. */
13045 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
13048 loadcost = TARGET_ATHLON ? 2 : 0;
13050 if (cost >= loadcost)
13063 /* How many alternative schedules to try. This should be as wide as the
13064 scheduling freedom in the DFA, but no wider. Making this value too
13065 large results extra work for the scheduler. */
13068 ia32_multipass_dfa_lookahead (void)
13070 if (ix86_tune == PROCESSOR_PENTIUM)
13073 if (ix86_tune == PROCESSOR_PENTIUMPRO
13074 || ix86_tune == PROCESSOR_K6)
13082 /* Compute the alignment given to a constant that is being placed in memory.
13083 EXP is the constant and ALIGN is the alignment that the object would
13085 The value of this function is used instead of that alignment to align
13089 ix86_constant_alignment (tree exp, int align)
13091 if (TREE_CODE (exp) == REAL_CST)
13093 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
13095 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
13098 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
13099 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
13100 return BITS_PER_WORD;
13105 /* Compute the alignment for a static variable.
13106 TYPE is the data type, and ALIGN is the alignment that
13107 the object would ordinarily have. The value of this function is used
13108 instead of that alignment to align the object. */
13111 ix86_data_alignment (tree type, int align)
13113 if (AGGREGATE_TYPE_P (type)
13114 && TYPE_SIZE (type)
13115 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13116 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 256
13117 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 256)
13120 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13121 to 16byte boundary. */
13124 if (AGGREGATE_TYPE_P (type)
13125 && TYPE_SIZE (type)
13126 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13127 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
13128 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13132 if (TREE_CODE (type) == ARRAY_TYPE)
13134 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13136 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13139 else if (TREE_CODE (type) == COMPLEX_TYPE)
13142 if (TYPE_MODE (type) == DCmode && align < 64)
13144 if (TYPE_MODE (type) == XCmode && align < 128)
13147 else if ((TREE_CODE (type) == RECORD_TYPE
13148 || TREE_CODE (type) == UNION_TYPE
13149 || TREE_CODE (type) == QUAL_UNION_TYPE)
13150 && TYPE_FIELDS (type))
13152 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13154 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13157 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13158 || TREE_CODE (type) == INTEGER_TYPE)
13160 if (TYPE_MODE (type) == DFmode && align < 64)
13162 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13169 /* Compute the alignment for a local variable.
13170 TYPE is the data type, and ALIGN is the alignment that
13171 the object would ordinarily have. The value of this macro is used
13172 instead of that alignment to align the object. */
13175 ix86_local_alignment (tree type, int align)
13177 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13178 to 16byte boundary. */
13181 if (AGGREGATE_TYPE_P (type)
13182 && TYPE_SIZE (type)
13183 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13184 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
13185 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13188 if (TREE_CODE (type) == ARRAY_TYPE)
13190 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13192 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13195 else if (TREE_CODE (type) == COMPLEX_TYPE)
13197 if (TYPE_MODE (type) == DCmode && align < 64)
13199 if (TYPE_MODE (type) == XCmode && align < 128)
13202 else if ((TREE_CODE (type) == RECORD_TYPE
13203 || TREE_CODE (type) == UNION_TYPE
13204 || TREE_CODE (type) == QUAL_UNION_TYPE)
13205 && TYPE_FIELDS (type))
13207 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13209 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13212 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13213 || TREE_CODE (type) == INTEGER_TYPE)
13216 if (TYPE_MODE (type) == DFmode && align < 64)
13218 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13224 /* Emit RTL insns to initialize the variable parts of a trampoline.
13225 FNADDR is an RTX for the address of the function's pure code.
13226 CXT is an RTX for the static chain value for the function. */
13228 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
13232 /* Compute offset from the end of the jmp to the target function. */
13233 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
13234 plus_constant (tramp, 10),
13235 NULL_RTX, 1, OPTAB_DIRECT);
13236 emit_move_insn (gen_rtx_MEM (QImode, tramp),
13237 gen_int_mode (0xb9, QImode));
13238 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
13239 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
13240 gen_int_mode (0xe9, QImode));
13241 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
13246 /* Try to load address using shorter movl instead of movabs.
13247 We may want to support movq for kernel mode, but kernel does not use
13248 trampolines at the moment. */
13249 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
13251 fnaddr = copy_to_mode_reg (DImode, fnaddr);
13252 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13253 gen_int_mode (0xbb41, HImode));
13254 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
13255 gen_lowpart (SImode, fnaddr));
13260 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13261 gen_int_mode (0xbb49, HImode));
13262 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13266 /* Load static chain using movabs to r10. */
13267 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13268 gen_int_mode (0xba49, HImode));
13269 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13272 /* Jump to the r11 */
13273 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13274 gen_int_mode (0xff49, HImode));
13275 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
13276 gen_int_mode (0xe3, QImode));
13278 gcc_assert (offset <= TRAMPOLINE_SIZE);
13281 #ifdef ENABLE_EXECUTE_STACK
13282 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
13283 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
13287 /* Codes for all the SSE/MMX builtins. */
13290 IX86_BUILTIN_ADDPS,
13291 IX86_BUILTIN_ADDSS,
13292 IX86_BUILTIN_DIVPS,
13293 IX86_BUILTIN_DIVSS,
13294 IX86_BUILTIN_MULPS,
13295 IX86_BUILTIN_MULSS,
13296 IX86_BUILTIN_SUBPS,
13297 IX86_BUILTIN_SUBSS,
13299 IX86_BUILTIN_CMPEQPS,
13300 IX86_BUILTIN_CMPLTPS,
13301 IX86_BUILTIN_CMPLEPS,
13302 IX86_BUILTIN_CMPGTPS,
13303 IX86_BUILTIN_CMPGEPS,
13304 IX86_BUILTIN_CMPNEQPS,
13305 IX86_BUILTIN_CMPNLTPS,
13306 IX86_BUILTIN_CMPNLEPS,
13307 IX86_BUILTIN_CMPNGTPS,
13308 IX86_BUILTIN_CMPNGEPS,
13309 IX86_BUILTIN_CMPORDPS,
13310 IX86_BUILTIN_CMPUNORDPS,
13311 IX86_BUILTIN_CMPNEPS,
13312 IX86_BUILTIN_CMPEQSS,
13313 IX86_BUILTIN_CMPLTSS,
13314 IX86_BUILTIN_CMPLESS,
13315 IX86_BUILTIN_CMPNEQSS,
13316 IX86_BUILTIN_CMPNLTSS,
13317 IX86_BUILTIN_CMPNLESS,
13318 IX86_BUILTIN_CMPNGTSS,
13319 IX86_BUILTIN_CMPNGESS,
13320 IX86_BUILTIN_CMPORDSS,
13321 IX86_BUILTIN_CMPUNORDSS,
13322 IX86_BUILTIN_CMPNESS,
13324 IX86_BUILTIN_COMIEQSS,
13325 IX86_BUILTIN_COMILTSS,
13326 IX86_BUILTIN_COMILESS,
13327 IX86_BUILTIN_COMIGTSS,
13328 IX86_BUILTIN_COMIGESS,
13329 IX86_BUILTIN_COMINEQSS,
13330 IX86_BUILTIN_UCOMIEQSS,
13331 IX86_BUILTIN_UCOMILTSS,
13332 IX86_BUILTIN_UCOMILESS,
13333 IX86_BUILTIN_UCOMIGTSS,
13334 IX86_BUILTIN_UCOMIGESS,
13335 IX86_BUILTIN_UCOMINEQSS,
13337 IX86_BUILTIN_CVTPI2PS,
13338 IX86_BUILTIN_CVTPS2PI,
13339 IX86_BUILTIN_CVTSI2SS,
13340 IX86_BUILTIN_CVTSI642SS,
13341 IX86_BUILTIN_CVTSS2SI,
13342 IX86_BUILTIN_CVTSS2SI64,
13343 IX86_BUILTIN_CVTTPS2PI,
13344 IX86_BUILTIN_CVTTSS2SI,
13345 IX86_BUILTIN_CVTTSS2SI64,
13347 IX86_BUILTIN_MAXPS,
13348 IX86_BUILTIN_MAXSS,
13349 IX86_BUILTIN_MINPS,
13350 IX86_BUILTIN_MINSS,
13352 IX86_BUILTIN_LOADUPS,
13353 IX86_BUILTIN_STOREUPS,
13354 IX86_BUILTIN_MOVSS,
13356 IX86_BUILTIN_MOVHLPS,
13357 IX86_BUILTIN_MOVLHPS,
13358 IX86_BUILTIN_LOADHPS,
13359 IX86_BUILTIN_LOADLPS,
13360 IX86_BUILTIN_STOREHPS,
13361 IX86_BUILTIN_STORELPS,
13363 IX86_BUILTIN_MASKMOVQ,
13364 IX86_BUILTIN_MOVMSKPS,
13365 IX86_BUILTIN_PMOVMSKB,
13367 IX86_BUILTIN_MOVNTPS,
13368 IX86_BUILTIN_MOVNTQ,
13370 IX86_BUILTIN_LOADDQU,
13371 IX86_BUILTIN_STOREDQU,
13373 IX86_BUILTIN_PACKSSWB,
13374 IX86_BUILTIN_PACKSSDW,
13375 IX86_BUILTIN_PACKUSWB,
13377 IX86_BUILTIN_PADDB,
13378 IX86_BUILTIN_PADDW,
13379 IX86_BUILTIN_PADDD,
13380 IX86_BUILTIN_PADDQ,
13381 IX86_BUILTIN_PADDSB,
13382 IX86_BUILTIN_PADDSW,
13383 IX86_BUILTIN_PADDUSB,
13384 IX86_BUILTIN_PADDUSW,
13385 IX86_BUILTIN_PSUBB,
13386 IX86_BUILTIN_PSUBW,
13387 IX86_BUILTIN_PSUBD,
13388 IX86_BUILTIN_PSUBQ,
13389 IX86_BUILTIN_PSUBSB,
13390 IX86_BUILTIN_PSUBSW,
13391 IX86_BUILTIN_PSUBUSB,
13392 IX86_BUILTIN_PSUBUSW,
13395 IX86_BUILTIN_PANDN,
13399 IX86_BUILTIN_PAVGB,
13400 IX86_BUILTIN_PAVGW,
13402 IX86_BUILTIN_PCMPEQB,
13403 IX86_BUILTIN_PCMPEQW,
13404 IX86_BUILTIN_PCMPEQD,
13405 IX86_BUILTIN_PCMPGTB,
13406 IX86_BUILTIN_PCMPGTW,
13407 IX86_BUILTIN_PCMPGTD,
13409 IX86_BUILTIN_PMADDWD,
13411 IX86_BUILTIN_PMAXSW,
13412 IX86_BUILTIN_PMAXUB,
13413 IX86_BUILTIN_PMINSW,
13414 IX86_BUILTIN_PMINUB,
13416 IX86_BUILTIN_PMULHUW,
13417 IX86_BUILTIN_PMULHW,
13418 IX86_BUILTIN_PMULLW,
13420 IX86_BUILTIN_PSADBW,
13421 IX86_BUILTIN_PSHUFW,
13423 IX86_BUILTIN_PSLLW,
13424 IX86_BUILTIN_PSLLD,
13425 IX86_BUILTIN_PSLLQ,
13426 IX86_BUILTIN_PSRAW,
13427 IX86_BUILTIN_PSRAD,
13428 IX86_BUILTIN_PSRLW,
13429 IX86_BUILTIN_PSRLD,
13430 IX86_BUILTIN_PSRLQ,
13431 IX86_BUILTIN_PSLLWI,
13432 IX86_BUILTIN_PSLLDI,
13433 IX86_BUILTIN_PSLLQI,
13434 IX86_BUILTIN_PSRAWI,
13435 IX86_BUILTIN_PSRADI,
13436 IX86_BUILTIN_PSRLWI,
13437 IX86_BUILTIN_PSRLDI,
13438 IX86_BUILTIN_PSRLQI,
13440 IX86_BUILTIN_PUNPCKHBW,
13441 IX86_BUILTIN_PUNPCKHWD,
13442 IX86_BUILTIN_PUNPCKHDQ,
13443 IX86_BUILTIN_PUNPCKLBW,
13444 IX86_BUILTIN_PUNPCKLWD,
13445 IX86_BUILTIN_PUNPCKLDQ,
13447 IX86_BUILTIN_SHUFPS,
13449 IX86_BUILTIN_RCPPS,
13450 IX86_BUILTIN_RCPSS,
13451 IX86_BUILTIN_RSQRTPS,
13452 IX86_BUILTIN_RSQRTSS,
13453 IX86_BUILTIN_SQRTPS,
13454 IX86_BUILTIN_SQRTSS,
13456 IX86_BUILTIN_UNPCKHPS,
13457 IX86_BUILTIN_UNPCKLPS,
13459 IX86_BUILTIN_ANDPS,
13460 IX86_BUILTIN_ANDNPS,
13462 IX86_BUILTIN_XORPS,
13465 IX86_BUILTIN_LDMXCSR,
13466 IX86_BUILTIN_STMXCSR,
13467 IX86_BUILTIN_SFENCE,
13469 /* 3DNow! Original */
13470 IX86_BUILTIN_FEMMS,
13471 IX86_BUILTIN_PAVGUSB,
13472 IX86_BUILTIN_PF2ID,
13473 IX86_BUILTIN_PFACC,
13474 IX86_BUILTIN_PFADD,
13475 IX86_BUILTIN_PFCMPEQ,
13476 IX86_BUILTIN_PFCMPGE,
13477 IX86_BUILTIN_PFCMPGT,
13478 IX86_BUILTIN_PFMAX,
13479 IX86_BUILTIN_PFMIN,
13480 IX86_BUILTIN_PFMUL,
13481 IX86_BUILTIN_PFRCP,
13482 IX86_BUILTIN_PFRCPIT1,
13483 IX86_BUILTIN_PFRCPIT2,
13484 IX86_BUILTIN_PFRSQIT1,
13485 IX86_BUILTIN_PFRSQRT,
13486 IX86_BUILTIN_PFSUB,
13487 IX86_BUILTIN_PFSUBR,
13488 IX86_BUILTIN_PI2FD,
13489 IX86_BUILTIN_PMULHRW,
13491 /* 3DNow! Athlon Extensions */
13492 IX86_BUILTIN_PF2IW,
13493 IX86_BUILTIN_PFNACC,
13494 IX86_BUILTIN_PFPNACC,
13495 IX86_BUILTIN_PI2FW,
13496 IX86_BUILTIN_PSWAPDSI,
13497 IX86_BUILTIN_PSWAPDSF,
13500 IX86_BUILTIN_ADDPD,
13501 IX86_BUILTIN_ADDSD,
13502 IX86_BUILTIN_DIVPD,
13503 IX86_BUILTIN_DIVSD,
13504 IX86_BUILTIN_MULPD,
13505 IX86_BUILTIN_MULSD,
13506 IX86_BUILTIN_SUBPD,
13507 IX86_BUILTIN_SUBSD,
13509 IX86_BUILTIN_CMPEQPD,
13510 IX86_BUILTIN_CMPLTPD,
13511 IX86_BUILTIN_CMPLEPD,
13512 IX86_BUILTIN_CMPGTPD,
13513 IX86_BUILTIN_CMPGEPD,
13514 IX86_BUILTIN_CMPNEQPD,
13515 IX86_BUILTIN_CMPNLTPD,
13516 IX86_BUILTIN_CMPNLEPD,
13517 IX86_BUILTIN_CMPNGTPD,
13518 IX86_BUILTIN_CMPNGEPD,
13519 IX86_BUILTIN_CMPORDPD,
13520 IX86_BUILTIN_CMPUNORDPD,
13521 IX86_BUILTIN_CMPNEPD,
13522 IX86_BUILTIN_CMPEQSD,
13523 IX86_BUILTIN_CMPLTSD,
13524 IX86_BUILTIN_CMPLESD,
13525 IX86_BUILTIN_CMPNEQSD,
13526 IX86_BUILTIN_CMPNLTSD,
13527 IX86_BUILTIN_CMPNLESD,
13528 IX86_BUILTIN_CMPORDSD,
13529 IX86_BUILTIN_CMPUNORDSD,
13530 IX86_BUILTIN_CMPNESD,
13532 IX86_BUILTIN_COMIEQSD,
13533 IX86_BUILTIN_COMILTSD,
13534 IX86_BUILTIN_COMILESD,
13535 IX86_BUILTIN_COMIGTSD,
13536 IX86_BUILTIN_COMIGESD,
13537 IX86_BUILTIN_COMINEQSD,
13538 IX86_BUILTIN_UCOMIEQSD,
13539 IX86_BUILTIN_UCOMILTSD,
13540 IX86_BUILTIN_UCOMILESD,
13541 IX86_BUILTIN_UCOMIGTSD,
13542 IX86_BUILTIN_UCOMIGESD,
13543 IX86_BUILTIN_UCOMINEQSD,
13545 IX86_BUILTIN_MAXPD,
13546 IX86_BUILTIN_MAXSD,
13547 IX86_BUILTIN_MINPD,
13548 IX86_BUILTIN_MINSD,
13550 IX86_BUILTIN_ANDPD,
13551 IX86_BUILTIN_ANDNPD,
13553 IX86_BUILTIN_XORPD,
13555 IX86_BUILTIN_SQRTPD,
13556 IX86_BUILTIN_SQRTSD,
13558 IX86_BUILTIN_UNPCKHPD,
13559 IX86_BUILTIN_UNPCKLPD,
13561 IX86_BUILTIN_SHUFPD,
13563 IX86_BUILTIN_LOADUPD,
13564 IX86_BUILTIN_STOREUPD,
13565 IX86_BUILTIN_MOVSD,
13567 IX86_BUILTIN_LOADHPD,
13568 IX86_BUILTIN_LOADLPD,
13570 IX86_BUILTIN_CVTDQ2PD,
13571 IX86_BUILTIN_CVTDQ2PS,
13573 IX86_BUILTIN_CVTPD2DQ,
13574 IX86_BUILTIN_CVTPD2PI,
13575 IX86_BUILTIN_CVTPD2PS,
13576 IX86_BUILTIN_CVTTPD2DQ,
13577 IX86_BUILTIN_CVTTPD2PI,
13579 IX86_BUILTIN_CVTPI2PD,
13580 IX86_BUILTIN_CVTSI2SD,
13581 IX86_BUILTIN_CVTSI642SD,
13583 IX86_BUILTIN_CVTSD2SI,
13584 IX86_BUILTIN_CVTSD2SI64,
13585 IX86_BUILTIN_CVTSD2SS,
13586 IX86_BUILTIN_CVTSS2SD,
13587 IX86_BUILTIN_CVTTSD2SI,
13588 IX86_BUILTIN_CVTTSD2SI64,
13590 IX86_BUILTIN_CVTPS2DQ,
13591 IX86_BUILTIN_CVTPS2PD,
13592 IX86_BUILTIN_CVTTPS2DQ,
13594 IX86_BUILTIN_MOVNTI,
13595 IX86_BUILTIN_MOVNTPD,
13596 IX86_BUILTIN_MOVNTDQ,
13599 IX86_BUILTIN_MASKMOVDQU,
13600 IX86_BUILTIN_MOVMSKPD,
13601 IX86_BUILTIN_PMOVMSKB128,
13603 IX86_BUILTIN_PACKSSWB128,
13604 IX86_BUILTIN_PACKSSDW128,
13605 IX86_BUILTIN_PACKUSWB128,
13607 IX86_BUILTIN_PADDB128,
13608 IX86_BUILTIN_PADDW128,
13609 IX86_BUILTIN_PADDD128,
13610 IX86_BUILTIN_PADDQ128,
13611 IX86_BUILTIN_PADDSB128,
13612 IX86_BUILTIN_PADDSW128,
13613 IX86_BUILTIN_PADDUSB128,
13614 IX86_BUILTIN_PADDUSW128,
13615 IX86_BUILTIN_PSUBB128,
13616 IX86_BUILTIN_PSUBW128,
13617 IX86_BUILTIN_PSUBD128,
13618 IX86_BUILTIN_PSUBQ128,
13619 IX86_BUILTIN_PSUBSB128,
13620 IX86_BUILTIN_PSUBSW128,
13621 IX86_BUILTIN_PSUBUSB128,
13622 IX86_BUILTIN_PSUBUSW128,
13624 IX86_BUILTIN_PAND128,
13625 IX86_BUILTIN_PANDN128,
13626 IX86_BUILTIN_POR128,
13627 IX86_BUILTIN_PXOR128,
13629 IX86_BUILTIN_PAVGB128,
13630 IX86_BUILTIN_PAVGW128,
13632 IX86_BUILTIN_PCMPEQB128,
13633 IX86_BUILTIN_PCMPEQW128,
13634 IX86_BUILTIN_PCMPEQD128,
13635 IX86_BUILTIN_PCMPGTB128,
13636 IX86_BUILTIN_PCMPGTW128,
13637 IX86_BUILTIN_PCMPGTD128,
13639 IX86_BUILTIN_PMADDWD128,
13641 IX86_BUILTIN_PMAXSW128,
13642 IX86_BUILTIN_PMAXUB128,
13643 IX86_BUILTIN_PMINSW128,
13644 IX86_BUILTIN_PMINUB128,
13646 IX86_BUILTIN_PMULUDQ,
13647 IX86_BUILTIN_PMULUDQ128,
13648 IX86_BUILTIN_PMULHUW128,
13649 IX86_BUILTIN_PMULHW128,
13650 IX86_BUILTIN_PMULLW128,
13652 IX86_BUILTIN_PSADBW128,
13653 IX86_BUILTIN_PSHUFHW,
13654 IX86_BUILTIN_PSHUFLW,
13655 IX86_BUILTIN_PSHUFD,
13657 IX86_BUILTIN_PSLLW128,
13658 IX86_BUILTIN_PSLLD128,
13659 IX86_BUILTIN_PSLLQ128,
13660 IX86_BUILTIN_PSRAW128,
13661 IX86_BUILTIN_PSRAD128,
13662 IX86_BUILTIN_PSRLW128,
13663 IX86_BUILTIN_PSRLD128,
13664 IX86_BUILTIN_PSRLQ128,
13665 IX86_BUILTIN_PSLLDQI128,
13666 IX86_BUILTIN_PSLLWI128,
13667 IX86_BUILTIN_PSLLDI128,
13668 IX86_BUILTIN_PSLLQI128,
13669 IX86_BUILTIN_PSRAWI128,
13670 IX86_BUILTIN_PSRADI128,
13671 IX86_BUILTIN_PSRLDQI128,
13672 IX86_BUILTIN_PSRLWI128,
13673 IX86_BUILTIN_PSRLDI128,
13674 IX86_BUILTIN_PSRLQI128,
13676 IX86_BUILTIN_PUNPCKHBW128,
13677 IX86_BUILTIN_PUNPCKHWD128,
13678 IX86_BUILTIN_PUNPCKHDQ128,
13679 IX86_BUILTIN_PUNPCKHQDQ128,
13680 IX86_BUILTIN_PUNPCKLBW128,
13681 IX86_BUILTIN_PUNPCKLWD128,
13682 IX86_BUILTIN_PUNPCKLDQ128,
13683 IX86_BUILTIN_PUNPCKLQDQ128,
13685 IX86_BUILTIN_CLFLUSH,
13686 IX86_BUILTIN_MFENCE,
13687 IX86_BUILTIN_LFENCE,
13689 /* Prescott New Instructions. */
13690 IX86_BUILTIN_ADDSUBPS,
13691 IX86_BUILTIN_HADDPS,
13692 IX86_BUILTIN_HSUBPS,
13693 IX86_BUILTIN_MOVSHDUP,
13694 IX86_BUILTIN_MOVSLDUP,
13695 IX86_BUILTIN_ADDSUBPD,
13696 IX86_BUILTIN_HADDPD,
13697 IX86_BUILTIN_HSUBPD,
13698 IX86_BUILTIN_LDDQU,
13700 IX86_BUILTIN_MONITOR,
13701 IX86_BUILTIN_MWAIT,
13703 IX86_BUILTIN_VEC_INIT_V2SI,
13704 IX86_BUILTIN_VEC_INIT_V4HI,
13705 IX86_BUILTIN_VEC_INIT_V8QI,
13706 IX86_BUILTIN_VEC_EXT_V2DF,
13707 IX86_BUILTIN_VEC_EXT_V2DI,
13708 IX86_BUILTIN_VEC_EXT_V4SF,
13709 IX86_BUILTIN_VEC_EXT_V4SI,
13710 IX86_BUILTIN_VEC_EXT_V8HI,
13711 IX86_BUILTIN_VEC_EXT_V2SI,
13712 IX86_BUILTIN_VEC_EXT_V4HI,
13713 IX86_BUILTIN_VEC_SET_V8HI,
13714 IX86_BUILTIN_VEC_SET_V4HI,
13719 #define def_builtin(MASK, NAME, TYPE, CODE) \
13721 if ((MASK) & target_flags \
13722 && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \
13723 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
13724 NULL, NULL_TREE); \
13727 /* Bits for builtin_description.flag. */
13729 /* Set when we don't support the comparison natively, and should
13730 swap_comparison in order to support it. */
13731 #define BUILTIN_DESC_SWAP_OPERANDS 1
13733 struct builtin_description
13735 const unsigned int mask;
13736 const enum insn_code icode;
13737 const char *const name;
13738 const enum ix86_builtins code;
13739 const enum rtx_code comparison;
13740 const unsigned int flag;
13743 static const struct builtin_description bdesc_comi[] =
13745 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
13746 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
13747 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
13748 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
13749 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
13750 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
13751 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
13752 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
13753 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
13754 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
13755 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
13756 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
13757 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
13758 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
13759 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
13760 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
13761 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
13762 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
13763 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
13764 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
13765 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
13766 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
13767 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
13768 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
13771 static const struct builtin_description bdesc_2arg[] =
13774 { MASK_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, 0, 0 },
13775 { MASK_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, 0, 0 },
13776 { MASK_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, 0, 0 },
13777 { MASK_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, 0, 0 },
13778 { MASK_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 },
13779 { MASK_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 },
13780 { MASK_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 },
13781 { MASK_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 },
13783 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
13784 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
13785 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
13786 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT,
13787 BUILTIN_DESC_SWAP_OPERANDS },
13788 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE,
13789 BUILTIN_DESC_SWAP_OPERANDS },
13790 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
13791 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
13792 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
13793 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
13794 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
13795 BUILTIN_DESC_SWAP_OPERANDS },
13796 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
13797 BUILTIN_DESC_SWAP_OPERANDS },
13798 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
13799 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
13800 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
13801 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
13802 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
13803 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
13804 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
13805 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
13806 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
13807 BUILTIN_DESC_SWAP_OPERANDS },
13808 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
13809 BUILTIN_DESC_SWAP_OPERANDS },
13810 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 },
13812 { MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 },
13813 { MASK_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, 0, 0 },
13814 { MASK_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 },
13815 { MASK_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 },
13817 { MASK_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 },
13818 { MASK_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, 0, 0 },
13819 { MASK_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 },
13820 { MASK_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 },
13822 { MASK_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, 0, 0 },
13823 { MASK_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, 0, 0 },
13824 { MASK_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, 0, 0 },
13825 { MASK_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, 0, 0 },
13826 { MASK_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, 0, 0 },
13829 { MASK_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 },
13830 { MASK_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 },
13831 { MASK_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 },
13832 { MASK_MMX, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 },
13833 { MASK_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 },
13834 { MASK_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 },
13835 { MASK_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 },
13836 { MASK_MMX, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 },
13838 { MASK_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 },
13839 { MASK_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 },
13840 { MASK_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 },
13841 { MASK_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 },
13842 { MASK_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 },
13843 { MASK_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 },
13844 { MASK_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 },
13845 { MASK_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 },
13847 { MASK_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 },
13848 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
13849 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
13851 { MASK_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 },
13852 { MASK_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 },
13853 { MASK_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 },
13854 { MASK_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 },
13856 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
13857 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
13859 { MASK_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 },
13860 { MASK_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 },
13861 { MASK_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 },
13862 { MASK_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 },
13863 { MASK_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 },
13864 { MASK_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 },
13866 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
13867 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
13868 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
13869 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
13871 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
13872 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
13873 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
13874 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
13875 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
13876 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
13879 { MASK_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, 0, 0 },
13880 { MASK_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, 0, 0 },
13881 { MASK_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, 0, 0 },
13883 { MASK_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 },
13884 { MASK_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 },
13885 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 },
13887 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 },
13888 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 },
13889 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 },
13890 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 },
13891 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, 0, 0 },
13892 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, 0, 0 },
13894 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 },
13895 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 },
13896 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 },
13897 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 },
13898 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, 0, 0 },
13899 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, 0, 0 },
13901 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 },
13902 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 },
13903 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 },
13904 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 },
13906 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, 0, 0 },
13907 { MASK_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, 0, 0 },
13910 { MASK_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, 0, 0 },
13911 { MASK_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, 0, 0 },
13912 { MASK_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, 0, 0 },
13913 { MASK_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, 0, 0 },
13914 { MASK_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 },
13915 { MASK_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 },
13916 { MASK_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 },
13917 { MASK_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 },
13919 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
13920 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
13921 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
13922 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT,
13923 BUILTIN_DESC_SWAP_OPERANDS },
13924 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE,
13925 BUILTIN_DESC_SWAP_OPERANDS },
13926 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
13927 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
13928 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
13929 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
13930 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
13931 BUILTIN_DESC_SWAP_OPERANDS },
13932 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
13933 BUILTIN_DESC_SWAP_OPERANDS },
13934 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
13935 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
13936 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
13937 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
13938 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
13939 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
13940 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
13941 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
13942 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
13944 { MASK_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, 0, 0 },
13945 { MASK_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, 0, 0 },
13946 { MASK_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 },
13947 { MASK_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 },
13949 { MASK_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 },
13950 { MASK_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, 0, 0 },
13951 { MASK_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 },
13952 { MASK_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 },
13954 { MASK_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, 0, 0 },
13955 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
13956 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
13959 { MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
13960 { MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
13961 { MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
13962 { MASK_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
13963 { MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
13964 { MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
13965 { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
13966 { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
13968 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
13969 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
13970 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
13971 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
13972 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
13973 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
13974 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
13975 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
13977 { MASK_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, 0, 0 },
13978 { MASK_SSE2, CODE_FOR_sse2_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
13980 { MASK_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 },
13981 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
13982 { MASK_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 },
13983 { MASK_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 },
13985 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
13986 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
13988 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
13989 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
13990 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
13991 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
13992 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
13993 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
13995 { MASK_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, 0, 0 },
13996 { MASK_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, 0, 0 },
13997 { MASK_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, 0, 0 },
13998 { MASK_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, 0, 0 },
14000 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
14001 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
14002 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
14003 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
14004 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
14005 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
14006 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
14007 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
14009 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
14010 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
14011 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
14013 { MASK_SSE2, CODE_FOR_sse2_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
14014 { MASK_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, 0, 0 },
14016 { MASK_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, 0, 0 },
14017 { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, 0, 0 },
14019 { MASK_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, 0, 0 },
14020 { MASK_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, 0, 0 },
14021 { MASK_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, 0, 0 },
14023 { MASK_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, 0, 0 },
14024 { MASK_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, 0, 0 },
14025 { MASK_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, 0, 0 },
14027 { MASK_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, 0, 0 },
14028 { MASK_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, 0, 0 },
14030 { MASK_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, 0, 0 },
14032 { MASK_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 },
14033 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 },
14034 { MASK_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
14035 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
14038 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
14039 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
14040 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
14041 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
14042 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
14043 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
14046 static const struct builtin_description bdesc_1arg[] =
14048 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
14049 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
14051 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },
14052 { MASK_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 },
14053 { MASK_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 },
14055 { MASK_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 },
14056 { MASK_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 },
14057 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 },
14058 { MASK_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 },
14059 { MASK_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 },
14060 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 },
14062 { MASK_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, 0, 0 },
14063 { MASK_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, 0, 0 },
14065 { MASK_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, 0, 0 },
14067 { MASK_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 },
14068 { MASK_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 },
14070 { MASK_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 },
14071 { MASK_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 },
14072 { MASK_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 },
14073 { MASK_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 },
14074 { MASK_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 },
14076 { MASK_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 },
14078 { MASK_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 },
14079 { MASK_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 },
14080 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 },
14081 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 },
14083 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
14084 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
14085 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
14088 { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
14089 { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
14093 ix86_init_builtins (void)
14096 ix86_init_mmx_sse_builtins ();
14099 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
14100 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
14103 ix86_init_mmx_sse_builtins (void)
14105 const struct builtin_description * d;
14108 tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
14109 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
14110 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
14111 tree V2DI_type_node
14112 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
14113 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
14114 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
14115 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
14116 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
14117 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
14118 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
14120 tree pchar_type_node = build_pointer_type (char_type_node);
14121 tree pcchar_type_node = build_pointer_type (
14122 build_type_variant (char_type_node, 1, 0));
14123 tree pfloat_type_node = build_pointer_type (float_type_node);
14124 tree pcfloat_type_node = build_pointer_type (
14125 build_type_variant (float_type_node, 1, 0));
14126 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
14127 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
14128 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
14131 tree int_ftype_v4sf_v4sf
14132 = build_function_type_list (integer_type_node,
14133 V4SF_type_node, V4SF_type_node, NULL_TREE);
14134 tree v4si_ftype_v4sf_v4sf
14135 = build_function_type_list (V4SI_type_node,
14136 V4SF_type_node, V4SF_type_node, NULL_TREE);
14137 /* MMX/SSE/integer conversions. */
14138 tree int_ftype_v4sf
14139 = build_function_type_list (integer_type_node,
14140 V4SF_type_node, NULL_TREE);
14141 tree int64_ftype_v4sf
14142 = build_function_type_list (long_long_integer_type_node,
14143 V4SF_type_node, NULL_TREE);
14144 tree int_ftype_v8qi
14145 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
14146 tree v4sf_ftype_v4sf_int
14147 = build_function_type_list (V4SF_type_node,
14148 V4SF_type_node, integer_type_node, NULL_TREE);
14149 tree v4sf_ftype_v4sf_int64
14150 = build_function_type_list (V4SF_type_node,
14151 V4SF_type_node, long_long_integer_type_node,
14153 tree v4sf_ftype_v4sf_v2si
14154 = build_function_type_list (V4SF_type_node,
14155 V4SF_type_node, V2SI_type_node, NULL_TREE);
14157 /* Miscellaneous. */
14158 tree v8qi_ftype_v4hi_v4hi
14159 = build_function_type_list (V8QI_type_node,
14160 V4HI_type_node, V4HI_type_node, NULL_TREE);
14161 tree v4hi_ftype_v2si_v2si
14162 = build_function_type_list (V4HI_type_node,
14163 V2SI_type_node, V2SI_type_node, NULL_TREE);
14164 tree v4sf_ftype_v4sf_v4sf_int
14165 = build_function_type_list (V4SF_type_node,
14166 V4SF_type_node, V4SF_type_node,
14167 integer_type_node, NULL_TREE);
14168 tree v2si_ftype_v4hi_v4hi
14169 = build_function_type_list (V2SI_type_node,
14170 V4HI_type_node, V4HI_type_node, NULL_TREE);
14171 tree v4hi_ftype_v4hi_int
14172 = build_function_type_list (V4HI_type_node,
14173 V4HI_type_node, integer_type_node, NULL_TREE);
14174 tree v4hi_ftype_v4hi_di
14175 = build_function_type_list (V4HI_type_node,
14176 V4HI_type_node, long_long_unsigned_type_node,
14178 tree v2si_ftype_v2si_di
14179 = build_function_type_list (V2SI_type_node,
14180 V2SI_type_node, long_long_unsigned_type_node,
14182 tree void_ftype_void
14183 = build_function_type (void_type_node, void_list_node);
14184 tree void_ftype_unsigned
14185 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
14186 tree void_ftype_unsigned_unsigned
14187 = build_function_type_list (void_type_node, unsigned_type_node,
14188 unsigned_type_node, NULL_TREE);
14189 tree void_ftype_pcvoid_unsigned_unsigned
14190 = build_function_type_list (void_type_node, const_ptr_type_node,
14191 unsigned_type_node, unsigned_type_node,
14193 tree unsigned_ftype_void
14194 = build_function_type (unsigned_type_node, void_list_node);
14195 tree v2si_ftype_v4sf
14196 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
14197 /* Loads/stores. */
14198 tree void_ftype_v8qi_v8qi_pchar
14199 = build_function_type_list (void_type_node,
14200 V8QI_type_node, V8QI_type_node,
14201 pchar_type_node, NULL_TREE);
14202 tree v4sf_ftype_pcfloat
14203 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
14204 /* @@@ the type is bogus */
14205 tree v4sf_ftype_v4sf_pv2si
14206 = build_function_type_list (V4SF_type_node,
14207 V4SF_type_node, pv2si_type_node, NULL_TREE);
14208 tree void_ftype_pv2si_v4sf
14209 = build_function_type_list (void_type_node,
14210 pv2si_type_node, V4SF_type_node, NULL_TREE);
14211 tree void_ftype_pfloat_v4sf
14212 = build_function_type_list (void_type_node,
14213 pfloat_type_node, V4SF_type_node, NULL_TREE);
14214 tree void_ftype_pdi_di
14215 = build_function_type_list (void_type_node,
14216 pdi_type_node, long_long_unsigned_type_node,
14218 tree void_ftype_pv2di_v2di
14219 = build_function_type_list (void_type_node,
14220 pv2di_type_node, V2DI_type_node, NULL_TREE);
14221 /* Normal vector unops. */
14222 tree v4sf_ftype_v4sf
14223 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
14225 /* Normal vector binops. */
14226 tree v4sf_ftype_v4sf_v4sf
14227 = build_function_type_list (V4SF_type_node,
14228 V4SF_type_node, V4SF_type_node, NULL_TREE);
14229 tree v8qi_ftype_v8qi_v8qi
14230 = build_function_type_list (V8QI_type_node,
14231 V8QI_type_node, V8QI_type_node, NULL_TREE);
14232 tree v4hi_ftype_v4hi_v4hi
14233 = build_function_type_list (V4HI_type_node,
14234 V4HI_type_node, V4HI_type_node, NULL_TREE);
14235 tree v2si_ftype_v2si_v2si
14236 = build_function_type_list (V2SI_type_node,
14237 V2SI_type_node, V2SI_type_node, NULL_TREE);
14238 tree di_ftype_di_di
14239 = build_function_type_list (long_long_unsigned_type_node,
14240 long_long_unsigned_type_node,
14241 long_long_unsigned_type_node, NULL_TREE);
14243 tree v2si_ftype_v2sf
14244 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
14245 tree v2sf_ftype_v2si
14246 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
14247 tree v2si_ftype_v2si
14248 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
14249 tree v2sf_ftype_v2sf
14250 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
14251 tree v2sf_ftype_v2sf_v2sf
14252 = build_function_type_list (V2SF_type_node,
14253 V2SF_type_node, V2SF_type_node, NULL_TREE);
14254 tree v2si_ftype_v2sf_v2sf
14255 = build_function_type_list (V2SI_type_node,
14256 V2SF_type_node, V2SF_type_node, NULL_TREE);
14257 tree pint_type_node = build_pointer_type (integer_type_node);
14258 tree pdouble_type_node = build_pointer_type (double_type_node);
14259 tree pcdouble_type_node = build_pointer_type (
14260 build_type_variant (double_type_node, 1, 0));
14261 tree int_ftype_v2df_v2df
14262 = build_function_type_list (integer_type_node,
14263 V2DF_type_node, V2DF_type_node, NULL_TREE);
14265 tree ti_ftype_ti_ti
14266 = build_function_type_list (intTI_type_node,
14267 intTI_type_node, intTI_type_node, NULL_TREE);
14268 tree void_ftype_pcvoid
14269 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
14270 tree v4sf_ftype_v4si
14271 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
14272 tree v4si_ftype_v4sf
14273 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
14274 tree v2df_ftype_v4si
14275 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
14276 tree v4si_ftype_v2df
14277 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
14278 tree v2si_ftype_v2df
14279 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
14280 tree v4sf_ftype_v2df
14281 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
14282 tree v2df_ftype_v2si
14283 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
14284 tree v2df_ftype_v4sf
14285 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
14286 tree int_ftype_v2df
14287 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
14288 tree int64_ftype_v2df
14289 = build_function_type_list (long_long_integer_type_node,
14290 V2DF_type_node, NULL_TREE);
14291 tree v2df_ftype_v2df_int
14292 = build_function_type_list (V2DF_type_node,
14293 V2DF_type_node, integer_type_node, NULL_TREE);
14294 tree v2df_ftype_v2df_int64
14295 = build_function_type_list (V2DF_type_node,
14296 V2DF_type_node, long_long_integer_type_node,
14298 tree v4sf_ftype_v4sf_v2df
14299 = build_function_type_list (V4SF_type_node,
14300 V4SF_type_node, V2DF_type_node, NULL_TREE);
14301 tree v2df_ftype_v2df_v4sf
14302 = build_function_type_list (V2DF_type_node,
14303 V2DF_type_node, V4SF_type_node, NULL_TREE);
14304 tree v2df_ftype_v2df_v2df_int
14305 = build_function_type_list (V2DF_type_node,
14306 V2DF_type_node, V2DF_type_node,
14309 tree v2df_ftype_v2df_pcdouble
14310 = build_function_type_list (V2DF_type_node,
14311 V2DF_type_node, pcdouble_type_node, NULL_TREE);
14312 tree void_ftype_pdouble_v2df
14313 = build_function_type_list (void_type_node,
14314 pdouble_type_node, V2DF_type_node, NULL_TREE);
14315 tree void_ftype_pint_int
14316 = build_function_type_list (void_type_node,
14317 pint_type_node, integer_type_node, NULL_TREE);
14318 tree void_ftype_v16qi_v16qi_pchar
14319 = build_function_type_list (void_type_node,
14320 V16QI_type_node, V16QI_type_node,
14321 pchar_type_node, NULL_TREE);
14322 tree v2df_ftype_pcdouble
14323 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
14324 tree v2df_ftype_v2df_v2df
14325 = build_function_type_list (V2DF_type_node,
14326 V2DF_type_node, V2DF_type_node, NULL_TREE);
14327 tree v16qi_ftype_v16qi_v16qi
14328 = build_function_type_list (V16QI_type_node,
14329 V16QI_type_node, V16QI_type_node, NULL_TREE);
14330 tree v8hi_ftype_v8hi_v8hi
14331 = build_function_type_list (V8HI_type_node,
14332 V8HI_type_node, V8HI_type_node, NULL_TREE);
14333 tree v4si_ftype_v4si_v4si
14334 = build_function_type_list (V4SI_type_node,
14335 V4SI_type_node, V4SI_type_node, NULL_TREE);
14336 tree v2di_ftype_v2di_v2di
14337 = build_function_type_list (V2DI_type_node,
14338 V2DI_type_node, V2DI_type_node, NULL_TREE);
14339 tree v2di_ftype_v2df_v2df
14340 = build_function_type_list (V2DI_type_node,
14341 V2DF_type_node, V2DF_type_node, NULL_TREE);
14342 tree v2df_ftype_v2df
14343 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
14344 tree v2di_ftype_v2di_int
14345 = build_function_type_list (V2DI_type_node,
14346 V2DI_type_node, integer_type_node, NULL_TREE);
14347 tree v4si_ftype_v4si_int
14348 = build_function_type_list (V4SI_type_node,
14349 V4SI_type_node, integer_type_node, NULL_TREE);
14350 tree v8hi_ftype_v8hi_int
14351 = build_function_type_list (V8HI_type_node,
14352 V8HI_type_node, integer_type_node, NULL_TREE);
14353 tree v8hi_ftype_v8hi_v2di
14354 = build_function_type_list (V8HI_type_node,
14355 V8HI_type_node, V2DI_type_node, NULL_TREE);
14356 tree v4si_ftype_v4si_v2di
14357 = build_function_type_list (V4SI_type_node,
14358 V4SI_type_node, V2DI_type_node, NULL_TREE);
14359 tree v4si_ftype_v8hi_v8hi
14360 = build_function_type_list (V4SI_type_node,
14361 V8HI_type_node, V8HI_type_node, NULL_TREE);
14362 tree di_ftype_v8qi_v8qi
14363 = build_function_type_list (long_long_unsigned_type_node,
14364 V8QI_type_node, V8QI_type_node, NULL_TREE);
14365 tree di_ftype_v2si_v2si
14366 = build_function_type_list (long_long_unsigned_type_node,
14367 V2SI_type_node, V2SI_type_node, NULL_TREE);
14368 tree v2di_ftype_v16qi_v16qi
14369 = build_function_type_list (V2DI_type_node,
14370 V16QI_type_node, V16QI_type_node, NULL_TREE);
14371 tree v2di_ftype_v4si_v4si
14372 = build_function_type_list (V2DI_type_node,
14373 V4SI_type_node, V4SI_type_node, NULL_TREE);
14374 tree int_ftype_v16qi
14375 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
14376 tree v16qi_ftype_pcchar
14377 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
14378 tree void_ftype_pchar_v16qi
14379 = build_function_type_list (void_type_node,
14380 pchar_type_node, V16QI_type_node, NULL_TREE);
14383 tree float128_type;
14386 /* The __float80 type. */
14387 if (TYPE_MODE (long_double_type_node) == XFmode)
14388 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
14392 /* The __float80 type. */
14393 float80_type = make_node (REAL_TYPE);
14394 TYPE_PRECISION (float80_type) = 80;
14395 layout_type (float80_type);
14396 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
14399 float128_type = make_node (REAL_TYPE);
14400 TYPE_PRECISION (float128_type) = 128;
14401 layout_type (float128_type);
14402 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
14404 /* Add all builtins that are more or less simple operations on two
14406 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
14408 /* Use one of the operands; the target can have a different mode for
14409 mask-generating compares. */
14410 enum machine_mode mode;
14415 mode = insn_data[d->icode].operand[1].mode;
14420 type = v16qi_ftype_v16qi_v16qi;
14423 type = v8hi_ftype_v8hi_v8hi;
14426 type = v4si_ftype_v4si_v4si;
14429 type = v2di_ftype_v2di_v2di;
14432 type = v2df_ftype_v2df_v2df;
14435 type = ti_ftype_ti_ti;
14438 type = v4sf_ftype_v4sf_v4sf;
14441 type = v8qi_ftype_v8qi_v8qi;
14444 type = v4hi_ftype_v4hi_v4hi;
14447 type = v2si_ftype_v2si_v2si;
14450 type = di_ftype_di_di;
14454 gcc_unreachable ();
14457 /* Override for comparisons. */
14458 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
14459 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
14460 type = v4si_ftype_v4sf_v4sf;
14462 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
14463 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
14464 type = v2di_ftype_v2df_v2df;
14466 def_builtin (d->mask, d->name, type, d->code);
14469 /* Add the remaining MMX insns with somewhat more complicated types. */
14470 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
14471 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
14472 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
14473 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
14475 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
14476 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
14477 def_builtin (MASK_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
14479 def_builtin (MASK_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
14480 def_builtin (MASK_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
14482 def_builtin (MASK_MMX, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
14483 def_builtin (MASK_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
14485 /* comi/ucomi insns. */
14486 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
14487 if (d->mask == MASK_SSE2)
14488 def_builtin (d->mask, d->name, int_ftype_v2df_v2df, d->code);
14490 def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
14492 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
14493 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
14494 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
14496 def_builtin (MASK_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
14497 def_builtin (MASK_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
14498 def_builtin (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
14499 def_builtin (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
14500 def_builtin (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
14501 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
14502 def_builtin (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
14503 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
14504 def_builtin (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
14505 def_builtin (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
14506 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
14508 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
14510 def_builtin (MASK_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
14511 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
14513 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
14514 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
14515 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
14516 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
14518 def_builtin (MASK_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
14519 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
14520 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
14521 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
14523 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
14525 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
14527 def_builtin (MASK_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
14528 def_builtin (MASK_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
14529 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
14530 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
14531 def_builtin (MASK_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
14532 def_builtin (MASK_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
14534 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
14536 /* Original 3DNow! */
14537 def_builtin (MASK_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
14538 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
14539 def_builtin (MASK_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
14540 def_builtin (MASK_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
14541 def_builtin (MASK_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
14542 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
14543 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
14544 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
14545 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
14546 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
14547 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
14548 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
14549 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
14550 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
14551 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
14552 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
14553 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
14554 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
14555 def_builtin (MASK_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
14556 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
14558 /* 3DNow! extension as used in the Athlon CPU. */
14559 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
14560 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
14561 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
14562 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
14563 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
14564 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
14567 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
14569 def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
14570 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
14572 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
14573 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
14575 def_builtin (MASK_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
14576 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
14577 def_builtin (MASK_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
14578 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
14579 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
14581 def_builtin (MASK_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
14582 def_builtin (MASK_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
14583 def_builtin (MASK_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
14584 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
14586 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
14587 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
14589 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
14591 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
14592 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
14594 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
14595 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
14596 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
14597 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
14598 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
14600 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
14602 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
14603 def_builtin (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
14604 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
14605 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
14607 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
14608 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
14609 def_builtin (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
14611 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
14612 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
14613 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
14614 def_builtin (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
14616 def_builtin (MASK_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
14617 def_builtin (MASK_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
14618 def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
14620 def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
14621 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
14623 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
14624 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
14626 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSLLW128);
14627 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSLLD128);
14628 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
14630 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRLW128);
14631 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRLD128);
14632 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
14634 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRAW128);
14635 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRAD128);
14637 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
14638 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
14639 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
14640 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
14642 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
14643 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
14644 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
14645 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
14647 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
14648 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
14650 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
14652 /* Prescott New Instructions. */
14653 def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
14654 void_ftype_pcvoid_unsigned_unsigned,
14655 IX86_BUILTIN_MONITOR);
14656 def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
14657 void_ftype_unsigned_unsigned,
14658 IX86_BUILTIN_MWAIT);
14659 def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
14661 IX86_BUILTIN_MOVSHDUP);
14662 def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
14664 IX86_BUILTIN_MOVSLDUP);
14665 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
14666 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
14668 /* Access to the vec_init patterns. */
14669 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
14670 integer_type_node, NULL_TREE);
14671 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
14672 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
14674 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
14675 short_integer_type_node,
14676 short_integer_type_node,
14677 short_integer_type_node, NULL_TREE);
14678 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v4hi",
14679 ftype, IX86_BUILTIN_VEC_INIT_V4HI);
14681 ftype = build_function_type_list (V8QI_type_node, char_type_node,
14682 char_type_node, char_type_node,
14683 char_type_node, char_type_node,
14684 char_type_node, char_type_node,
14685 char_type_node, NULL_TREE);
14686 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v8qi",
14687 ftype, IX86_BUILTIN_VEC_INIT_V8QI);
14689 /* Access to the vec_extract patterns. */
14690 ftype = build_function_type_list (double_type_node, V2DF_type_node,
14691 integer_type_node, NULL_TREE);
14692 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2df",
14693 ftype, IX86_BUILTIN_VEC_EXT_V2DF);
14695 ftype = build_function_type_list (long_long_integer_type_node,
14696 V2DI_type_node, integer_type_node,
14698 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2di",
14699 ftype, IX86_BUILTIN_VEC_EXT_V2DI);
14701 ftype = build_function_type_list (float_type_node, V4SF_type_node,
14702 integer_type_node, NULL_TREE);
14703 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf",
14704 ftype, IX86_BUILTIN_VEC_EXT_V4SF);
14706 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
14707 integer_type_node, NULL_TREE);
14708 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si",
14709 ftype, IX86_BUILTIN_VEC_EXT_V4SI);
14711 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
14712 integer_type_node, NULL_TREE);
14713 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi",
14714 ftype, IX86_BUILTIN_VEC_EXT_V8HI);
14716 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
14717 integer_type_node, NULL_TREE);
14718 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_ext_v4hi",
14719 ftype, IX86_BUILTIN_VEC_EXT_V4HI);
14721 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
14722 integer_type_node, NULL_TREE);
14723 def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
14724 ftype, IX86_BUILTIN_VEC_EXT_V2SI);
14726 /* Access to the vec_set patterns. */
14727 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
14729 integer_type_node, NULL_TREE);
14730 def_builtin (MASK_SSE, "__builtin_ia32_vec_set_v8hi",
14731 ftype, IX86_BUILTIN_VEC_SET_V8HI);
14733 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
14735 integer_type_node, NULL_TREE);
14736 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_set_v4hi",
14737 ftype, IX86_BUILTIN_VEC_SET_V4HI);
14740 /* Errors in the source file can cause expand_expr to return const0_rtx
14741 where we expect a vector. To avoid crashing, use one of the vector
14742 clear instructions. */
14744 safe_vector_operand (rtx x, enum machine_mode mode)
14746 if (x == const0_rtx)
14747 x = CONST0_RTX (mode);
14751 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
14754 ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
14757 tree arg0 = TREE_VALUE (arglist);
14758 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14759 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14760 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14761 enum machine_mode tmode = insn_data[icode].operand[0].mode;
14762 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
14763 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
14765 if (VECTOR_MODE_P (mode0))
14766 op0 = safe_vector_operand (op0, mode0);
14767 if (VECTOR_MODE_P (mode1))
14768 op1 = safe_vector_operand (op1, mode1);
14770 if (optimize || !target
14771 || GET_MODE (target) != tmode
14772 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14773 target = gen_reg_rtx (tmode);
14775 if (GET_MODE (op1) == SImode && mode1 == TImode)
14777 rtx x = gen_reg_rtx (V4SImode);
14778 emit_insn (gen_sse2_loadd (x, op1));
14779 op1 = gen_lowpart (TImode, x);
14782 /* The insn must want input operands in the same modes as the
14784 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
14785 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
14787 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
14788 op0 = copy_to_mode_reg (mode0, op0);
14789 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
14790 op1 = copy_to_mode_reg (mode1, op1);
14792 /* ??? Using ix86_fixup_binary_operands is problematic when
14793 we've got mismatched modes. Fake it. */
14799 if (tmode == mode0 && tmode == mode1)
14801 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
14805 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
14807 op0 = force_reg (mode0, op0);
14808 op1 = force_reg (mode1, op1);
14809 target = gen_reg_rtx (tmode);
14812 pat = GEN_FCN (icode) (target, op0, op1);
14819 /* Subroutine of ix86_expand_builtin to take care of stores. */
14822 ix86_expand_store_builtin (enum insn_code icode, tree arglist)
14825 tree arg0 = TREE_VALUE (arglist);
14826 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14827 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14828 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14829 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
14830 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
14832 if (VECTOR_MODE_P (mode1))
14833 op1 = safe_vector_operand (op1, mode1);
14835 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
14836 op1 = copy_to_mode_reg (mode1, op1);
14838 pat = GEN_FCN (icode) (op0, op1);
14844 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
14847 ix86_expand_unop_builtin (enum insn_code icode, tree arglist,
14848 rtx target, int do_load)
14851 tree arg0 = TREE_VALUE (arglist);
14852 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14853 enum machine_mode tmode = insn_data[icode].operand[0].mode;
14854 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
14856 if (optimize || !target
14857 || GET_MODE (target) != tmode
14858 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14859 target = gen_reg_rtx (tmode);
14861 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
14864 if (VECTOR_MODE_P (mode0))
14865 op0 = safe_vector_operand (op0, mode0);
14867 if ((optimize && !register_operand (op0, mode0))
14868 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14869 op0 = copy_to_mode_reg (mode0, op0);
14872 pat = GEN_FCN (icode) (target, op0);
14879 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
14880 sqrtss, rsqrtss, rcpss. */
14883 ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target)
14886 tree arg0 = TREE_VALUE (arglist);
14887 rtx op1, op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14888 enum machine_mode tmode = insn_data[icode].operand[0].mode;
14889 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
14891 if (optimize || !target
14892 || GET_MODE (target) != tmode
14893 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14894 target = gen_reg_rtx (tmode);
14896 if (VECTOR_MODE_P (mode0))
14897 op0 = safe_vector_operand (op0, mode0);
14899 if ((optimize && !register_operand (op0, mode0))
14900 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14901 op0 = copy_to_mode_reg (mode0, op0);
14904 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
14905 op1 = copy_to_mode_reg (mode0, op1);
14907 pat = GEN_FCN (icode) (target, op0, op1);
14914 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
14917 ix86_expand_sse_compare (const struct builtin_description *d, tree arglist,
14921 tree arg0 = TREE_VALUE (arglist);
14922 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14923 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14924 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14926 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
14927 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
14928 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
14929 enum rtx_code comparison = d->comparison;
14931 if (VECTOR_MODE_P (mode0))
14932 op0 = safe_vector_operand (op0, mode0);
14933 if (VECTOR_MODE_P (mode1))
14934 op1 = safe_vector_operand (op1, mode1);
14936 /* Swap operands if we have a comparison that isn't available in
14938 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
14940 rtx tmp = gen_reg_rtx (mode1);
14941 emit_move_insn (tmp, op1);
14946 if (optimize || !target
14947 || GET_MODE (target) != tmode
14948 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
14949 target = gen_reg_rtx (tmode);
14951 if ((optimize && !register_operand (op0, mode0))
14952 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
14953 op0 = copy_to_mode_reg (mode0, op0);
14954 if ((optimize && !register_operand (op1, mode1))
14955 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
14956 op1 = copy_to_mode_reg (mode1, op1);
14958 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
14959 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
14966 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
14969 ix86_expand_sse_comi (const struct builtin_description *d, tree arglist,
14973 tree arg0 = TREE_VALUE (arglist);
14974 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14975 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14976 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14978 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
14979 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
14980 enum rtx_code comparison = d->comparison;
14982 if (VECTOR_MODE_P (mode0))
14983 op0 = safe_vector_operand (op0, mode0);
14984 if (VECTOR_MODE_P (mode1))
14985 op1 = safe_vector_operand (op1, mode1);
14987 /* Swap operands if we have a comparison that isn't available in
14989 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
14996 target = gen_reg_rtx (SImode);
14997 emit_move_insn (target, const0_rtx);
14998 target = gen_rtx_SUBREG (QImode, target, 0);
15000 if ((optimize && !register_operand (op0, mode0))
15001 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15002 op0 = copy_to_mode_reg (mode0, op0);
15003 if ((optimize && !register_operand (op1, mode1))
15004 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15005 op1 = copy_to_mode_reg (mode1, op1);
15007 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
15008 pat = GEN_FCN (d->icode) (op0, op1);
15012 emit_insn (gen_rtx_SET (VOIDmode,
15013 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
15014 gen_rtx_fmt_ee (comparison, QImode,
15018 return SUBREG_REG (target);
15021 /* Return the integer constant in ARG. Constrain it to be in the range
15022 of the subparts of VEC_TYPE; issue an error if not. */
15025 get_element_number (tree vec_type, tree arg)
15027 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15029 if (!host_integerp (arg, 1)
15030 || (elt = tree_low_cst (arg, 1), elt > max))
15032 error ("selector must be an integer constant in the range 0..%wi", max);
15039 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15040 ix86_expand_vector_init. We DO have language-level syntax for this, in
15041 the form of (type){ init-list }. Except that since we can't place emms
15042 instructions from inside the compiler, we can't allow the use of MMX
15043 registers unless the user explicitly asks for it. So we do *not* define
15044 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
15045 we have builtins invoked by mmintrin.h that gives us license to emit
15046 these sorts of instructions. */
15049 ix86_expand_vec_init_builtin (tree type, tree arglist, rtx target)
15051 enum machine_mode tmode = TYPE_MODE (type);
15052 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
15053 int i, n_elt = GET_MODE_NUNITS (tmode);
15054 rtvec v = rtvec_alloc (n_elt);
15056 gcc_assert (VECTOR_MODE_P (tmode));
15058 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
15060 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
15061 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15064 gcc_assert (arglist == NULL);
15066 if (!target || !register_operand (target, tmode))
15067 target = gen_reg_rtx (tmode);
15069 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
15073 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15074 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
15075 had a language-level syntax for referencing vector elements. */
15078 ix86_expand_vec_ext_builtin (tree arglist, rtx target)
15080 enum machine_mode tmode, mode0;
15085 arg0 = TREE_VALUE (arglist);
15086 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15088 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15089 elt = get_element_number (TREE_TYPE (arg0), arg1);
15091 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15092 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15093 gcc_assert (VECTOR_MODE_P (mode0));
15095 op0 = force_reg (mode0, op0);
15097 if (optimize || !target || !register_operand (target, tmode))
15098 target = gen_reg_rtx (tmode);
15100 ix86_expand_vector_extract (true, target, op0, elt);
15105 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15106 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
15107 a language-level syntax for referencing vector elements. */
15110 ix86_expand_vec_set_builtin (tree arglist)
15112 enum machine_mode tmode, mode1;
15113 tree arg0, arg1, arg2;
15117 arg0 = TREE_VALUE (arglist);
15118 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15119 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15121 tmode = TYPE_MODE (TREE_TYPE (arg0));
15122 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15123 gcc_assert (VECTOR_MODE_P (tmode));
15125 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
15126 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
15127 elt = get_element_number (TREE_TYPE (arg0), arg2);
15129 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15130 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15132 op0 = force_reg (tmode, op0);
15133 op1 = force_reg (mode1, op1);
15135 ix86_expand_vector_set (true, op0, op1, elt);
15140 /* Expand an expression EXP that calls a built-in function,
15141 with result going to TARGET if that's convenient
15142 (and in mode MODE if that's convenient).
15143 SUBTARGET may be used as the target for computing one of EXP's operands.
15144 IGNORE is nonzero if the value is to be ignored. */
15147 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15148 enum machine_mode mode ATTRIBUTE_UNUSED,
15149 int ignore ATTRIBUTE_UNUSED)
15151 const struct builtin_description *d;
15153 enum insn_code icode;
15154 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
15155 tree arglist = TREE_OPERAND (exp, 1);
15156 tree arg0, arg1, arg2;
15157 rtx op0, op1, op2, pat;
15158 enum machine_mode tmode, mode0, mode1, mode2;
15159 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15163 case IX86_BUILTIN_EMMS:
15164 emit_insn (gen_mmx_emms ());
15167 case IX86_BUILTIN_SFENCE:
15168 emit_insn (gen_sse_sfence ());
15171 case IX86_BUILTIN_MASKMOVQ:
15172 case IX86_BUILTIN_MASKMOVDQU:
15173 icode = (fcode == IX86_BUILTIN_MASKMOVQ
15174 ? CODE_FOR_mmx_maskmovq
15175 : CODE_FOR_sse2_maskmovdqu);
15176 /* Note the arg order is different from the operand order. */
15177 arg1 = TREE_VALUE (arglist);
15178 arg2 = TREE_VALUE (TREE_CHAIN (arglist));
15179 arg0 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15180 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15181 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15182 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15183 mode0 = insn_data[icode].operand[0].mode;
15184 mode1 = insn_data[icode].operand[1].mode;
15185 mode2 = insn_data[icode].operand[2].mode;
15187 op0 = force_reg (Pmode, op0);
15188 op0 = gen_rtx_MEM (mode1, op0);
15190 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15191 op0 = copy_to_mode_reg (mode0, op0);
15192 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15193 op1 = copy_to_mode_reg (mode1, op1);
15194 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
15195 op2 = copy_to_mode_reg (mode2, op2);
15196 pat = GEN_FCN (icode) (op0, op1, op2);
15202 case IX86_BUILTIN_SQRTSS:
15203 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, arglist, target);
15204 case IX86_BUILTIN_RSQRTSS:
15205 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, arglist, target);
15206 case IX86_BUILTIN_RCPSS:
15207 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, arglist, target);
15209 case IX86_BUILTIN_LOADUPS:
15210 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, arglist, target, 1);
15212 case IX86_BUILTIN_STOREUPS:
15213 return ix86_expand_store_builtin (CODE_FOR_sse_movups, arglist);
15215 case IX86_BUILTIN_LOADHPS:
15216 case IX86_BUILTIN_LOADLPS:
15217 case IX86_BUILTIN_LOADHPD:
15218 case IX86_BUILTIN_LOADLPD:
15219 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
15220 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
15221 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
15222 : CODE_FOR_sse2_loadlpd);
15223 arg0 = TREE_VALUE (arglist);
15224 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15225 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15226 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15227 tmode = insn_data[icode].operand[0].mode;
15228 mode0 = insn_data[icode].operand[1].mode;
15229 mode1 = insn_data[icode].operand[2].mode;
15231 op0 = force_reg (mode0, op0);
15232 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
15233 if (optimize || target == 0
15234 || GET_MODE (target) != tmode
15235 || !register_operand (target, tmode))
15236 target = gen_reg_rtx (tmode);
15237 pat = GEN_FCN (icode) (target, op0, op1);
15243 case IX86_BUILTIN_STOREHPS:
15244 case IX86_BUILTIN_STORELPS:
15245 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
15246 : CODE_FOR_sse_storelps);
15247 arg0 = TREE_VALUE (arglist);
15248 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15249 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15250 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15251 mode0 = insn_data[icode].operand[0].mode;
15252 mode1 = insn_data[icode].operand[1].mode;
15254 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15255 op1 = force_reg (mode1, op1);
15257 pat = GEN_FCN (icode) (op0, op1);
15263 case IX86_BUILTIN_MOVNTPS:
15264 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, arglist);
15265 case IX86_BUILTIN_MOVNTQ:
15266 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, arglist);
15268 case IX86_BUILTIN_LDMXCSR:
15269 op0 = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
15270 target = assign_386_stack_local (SImode, SLOT_TEMP);
15271 emit_move_insn (target, op0);
15272 emit_insn (gen_sse_ldmxcsr (target));
15275 case IX86_BUILTIN_STMXCSR:
15276 target = assign_386_stack_local (SImode, SLOT_TEMP);
15277 emit_insn (gen_sse_stmxcsr (target));
15278 return copy_to_mode_reg (SImode, target);
15280 case IX86_BUILTIN_SHUFPS:
15281 case IX86_BUILTIN_SHUFPD:
15282 icode = (fcode == IX86_BUILTIN_SHUFPS
15283 ? CODE_FOR_sse_shufps
15284 : CODE_FOR_sse2_shufpd);
15285 arg0 = TREE_VALUE (arglist);
15286 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15287 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15288 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15289 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15290 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15291 tmode = insn_data[icode].operand[0].mode;
15292 mode0 = insn_data[icode].operand[1].mode;
15293 mode1 = insn_data[icode].operand[2].mode;
15294 mode2 = insn_data[icode].operand[3].mode;
15296 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15297 op0 = copy_to_mode_reg (mode0, op0);
15298 if ((optimize && !register_operand (op1, mode1))
15299 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
15300 op1 = copy_to_mode_reg (mode1, op1);
15301 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15303 /* @@@ better error message */
15304 error ("mask must be an immediate");
15305 return gen_reg_rtx (tmode);
15307 if (optimize || target == 0
15308 || GET_MODE (target) != tmode
15309 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15310 target = gen_reg_rtx (tmode);
15311 pat = GEN_FCN (icode) (target, op0, op1, op2);
15317 case IX86_BUILTIN_PSHUFW:
15318 case IX86_BUILTIN_PSHUFD:
15319 case IX86_BUILTIN_PSHUFHW:
15320 case IX86_BUILTIN_PSHUFLW:
15321 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
15322 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
15323 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
15324 : CODE_FOR_mmx_pshufw);
15325 arg0 = TREE_VALUE (arglist);
15326 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15327 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15328 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15329 tmode = insn_data[icode].operand[0].mode;
15330 mode1 = insn_data[icode].operand[1].mode;
15331 mode2 = insn_data[icode].operand[2].mode;
15333 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15334 op0 = copy_to_mode_reg (mode1, op0);
15335 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15337 /* @@@ better error message */
15338 error ("mask must be an immediate");
15342 || GET_MODE (target) != tmode
15343 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15344 target = gen_reg_rtx (tmode);
15345 pat = GEN_FCN (icode) (target, op0, op1);
15351 case IX86_BUILTIN_PSLLDQI128:
15352 case IX86_BUILTIN_PSRLDQI128:
15353 icode = ( fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
15354 : CODE_FOR_sse2_lshrti3);
15355 arg0 = TREE_VALUE (arglist);
15356 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15357 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15358 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15359 tmode = insn_data[icode].operand[0].mode;
15360 mode1 = insn_data[icode].operand[1].mode;
15361 mode2 = insn_data[icode].operand[2].mode;
15363 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15365 op0 = copy_to_reg (op0);
15366 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
15368 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15370 error ("shift must be an immediate");
15373 target = gen_reg_rtx (V2DImode);
15374 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0), op0, op1);
15380 case IX86_BUILTIN_FEMMS:
15381 emit_insn (gen_mmx_femms ());
15384 case IX86_BUILTIN_PAVGUSB:
15385 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, arglist, target);
15387 case IX86_BUILTIN_PF2ID:
15388 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, arglist, target, 0);
15390 case IX86_BUILTIN_PFACC:
15391 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, arglist, target);
15393 case IX86_BUILTIN_PFADD:
15394 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, arglist, target);
15396 case IX86_BUILTIN_PFCMPEQ:
15397 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, arglist, target);
15399 case IX86_BUILTIN_PFCMPGE:
15400 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, arglist, target);
15402 case IX86_BUILTIN_PFCMPGT:
15403 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, arglist, target);
15405 case IX86_BUILTIN_PFMAX:
15406 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, arglist, target);
15408 case IX86_BUILTIN_PFMIN:
15409 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, arglist, target);
15411 case IX86_BUILTIN_PFMUL:
15412 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, arglist, target);
15414 case IX86_BUILTIN_PFRCP:
15415 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, arglist, target, 0);
15417 case IX86_BUILTIN_PFRCPIT1:
15418 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, arglist, target);
15420 case IX86_BUILTIN_PFRCPIT2:
15421 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, arglist, target);
15423 case IX86_BUILTIN_PFRSQIT1:
15424 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, arglist, target);
15426 case IX86_BUILTIN_PFRSQRT:
15427 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, arglist, target, 0);
15429 case IX86_BUILTIN_PFSUB:
15430 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, arglist, target);
15432 case IX86_BUILTIN_PFSUBR:
15433 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, arglist, target);
15435 case IX86_BUILTIN_PI2FD:
15436 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, arglist, target, 0);
15438 case IX86_BUILTIN_PMULHRW:
15439 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, arglist, target);
15441 case IX86_BUILTIN_PF2IW:
15442 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, arglist, target, 0);
15444 case IX86_BUILTIN_PFNACC:
15445 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, arglist, target);
15447 case IX86_BUILTIN_PFPNACC:
15448 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, arglist, target);
15450 case IX86_BUILTIN_PI2FW:
15451 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, arglist, target, 0);
15453 case IX86_BUILTIN_PSWAPDSI:
15454 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, arglist, target, 0);
15456 case IX86_BUILTIN_PSWAPDSF:
15457 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, arglist, target, 0);
15459 case IX86_BUILTIN_SQRTSD:
15460 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, arglist, target);
15461 case IX86_BUILTIN_LOADUPD:
15462 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, arglist, target, 1);
15463 case IX86_BUILTIN_STOREUPD:
15464 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, arglist);
15466 case IX86_BUILTIN_MFENCE:
15467 emit_insn (gen_sse2_mfence ());
15469 case IX86_BUILTIN_LFENCE:
15470 emit_insn (gen_sse2_lfence ());
15473 case IX86_BUILTIN_CLFLUSH:
15474 arg0 = TREE_VALUE (arglist);
15475 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15476 icode = CODE_FOR_sse2_clflush;
15477 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
15478 op0 = copy_to_mode_reg (Pmode, op0);
15480 emit_insn (gen_sse2_clflush (op0));
15483 case IX86_BUILTIN_MOVNTPD:
15484 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, arglist);
15485 case IX86_BUILTIN_MOVNTDQ:
15486 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, arglist);
15487 case IX86_BUILTIN_MOVNTI:
15488 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, arglist);
15490 case IX86_BUILTIN_LOADDQU:
15491 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, arglist, target, 1);
15492 case IX86_BUILTIN_STOREDQU:
15493 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, arglist);
15495 case IX86_BUILTIN_MONITOR:
15496 arg0 = TREE_VALUE (arglist);
15497 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15498 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15499 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15500 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15501 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15503 op0 = copy_to_mode_reg (SImode, op0);
15505 op1 = copy_to_mode_reg (SImode, op1);
15507 op2 = copy_to_mode_reg (SImode, op2);
15508 emit_insn (gen_sse3_monitor (op0, op1, op2));
15511 case IX86_BUILTIN_MWAIT:
15512 arg0 = TREE_VALUE (arglist);
15513 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15514 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15515 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15517 op0 = copy_to_mode_reg (SImode, op0);
15519 op1 = copy_to_mode_reg (SImode, op1);
15520 emit_insn (gen_sse3_mwait (op0, op1));
15523 case IX86_BUILTIN_LDDQU:
15524 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
15527 case IX86_BUILTIN_VEC_INIT_V2SI:
15528 case IX86_BUILTIN_VEC_INIT_V4HI:
15529 case IX86_BUILTIN_VEC_INIT_V8QI:
15530 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
15532 case IX86_BUILTIN_VEC_EXT_V2DF:
15533 case IX86_BUILTIN_VEC_EXT_V2DI:
15534 case IX86_BUILTIN_VEC_EXT_V4SF:
15535 case IX86_BUILTIN_VEC_EXT_V4SI:
15536 case IX86_BUILTIN_VEC_EXT_V8HI:
15537 case IX86_BUILTIN_VEC_EXT_V2SI:
15538 case IX86_BUILTIN_VEC_EXT_V4HI:
15539 return ix86_expand_vec_ext_builtin (arglist, target);
15541 case IX86_BUILTIN_VEC_SET_V8HI:
15542 case IX86_BUILTIN_VEC_SET_V4HI:
15543 return ix86_expand_vec_set_builtin (arglist);
15549 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
15550 if (d->code == fcode)
15552 /* Compares are treated specially. */
15553 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
15554 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
15555 || d->icode == CODE_FOR_sse2_maskcmpv2df3
15556 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
15557 return ix86_expand_sse_compare (d, arglist, target);
15559 return ix86_expand_binop_builtin (d->icode, arglist, target);
15562 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
15563 if (d->code == fcode)
15564 return ix86_expand_unop_builtin (d->icode, arglist, target, 0);
15566 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
15567 if (d->code == fcode)
15568 return ix86_expand_sse_comi (d, arglist, target);
15570 gcc_unreachable ();
15573 /* Store OPERAND to the memory after reload is completed. This means
15574 that we can't easily use assign_stack_local. */
15576 ix86_force_to_memory (enum machine_mode mode, rtx operand)
15580 gcc_assert (reload_completed);
15581 if (TARGET_RED_ZONE)
15583 result = gen_rtx_MEM (mode,
15584 gen_rtx_PLUS (Pmode,
15586 GEN_INT (-RED_ZONE_SIZE)));
15587 emit_move_insn (result, operand);
15589 else if (!TARGET_RED_ZONE && TARGET_64BIT)
15595 operand = gen_lowpart (DImode, operand);
15599 gen_rtx_SET (VOIDmode,
15600 gen_rtx_MEM (DImode,
15601 gen_rtx_PRE_DEC (DImode,
15602 stack_pointer_rtx)),
15606 gcc_unreachable ();
15608 result = gen_rtx_MEM (mode, stack_pointer_rtx);
15617 split_di (&operand, 1, operands, operands + 1);
15619 gen_rtx_SET (VOIDmode,
15620 gen_rtx_MEM (SImode,
15621 gen_rtx_PRE_DEC (Pmode,
15622 stack_pointer_rtx)),
15625 gen_rtx_SET (VOIDmode,
15626 gen_rtx_MEM (SImode,
15627 gen_rtx_PRE_DEC (Pmode,
15628 stack_pointer_rtx)),
15633 /* It is better to store HImodes as SImodes. */
15634 if (!TARGET_PARTIAL_REG_STALL)
15635 operand = gen_lowpart (SImode, operand);
15639 gen_rtx_SET (VOIDmode,
15640 gen_rtx_MEM (GET_MODE (operand),
15641 gen_rtx_PRE_DEC (SImode,
15642 stack_pointer_rtx)),
15646 gcc_unreachable ();
15648 result = gen_rtx_MEM (mode, stack_pointer_rtx);
15653 /* Free operand from the memory. */
15655 ix86_free_from_memory (enum machine_mode mode)
15657 if (!TARGET_RED_ZONE)
15661 if (mode == DImode || TARGET_64BIT)
15663 else if (mode == HImode && TARGET_PARTIAL_REG_STALL)
15667 /* Use LEA to deallocate stack space. In peephole2 it will be converted
15668 to pop or add instruction if registers are available. */
15669 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
15670 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
15675 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
15676 QImode must go into class Q_REGS.
15677 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
15678 movdf to do mem-to-mem moves through integer regs. */
15680 ix86_preferred_reload_class (rtx x, enum reg_class class)
15682 /* We're only allowed to return a subclass of CLASS. Many of the
15683 following checks fail for NO_REGS, so eliminate that early. */
15684 if (class == NO_REGS)
15687 /* All classes can load zeros. */
15688 if (x == CONST0_RTX (GET_MODE (x)))
15691 /* Floating-point constants need more complex checks. */
15692 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
15694 /* General regs can load everything. */
15695 if (reg_class_subset_p (class, GENERAL_REGS))
15698 /* Floats can load 0 and 1 plus some others. Note that we eliminated
15699 zero above. We only want to wind up preferring 80387 registers if
15700 we plan on doing computation with them. */
15702 && (TARGET_MIX_SSE_I387
15703 || !(TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (x))))
15704 && standard_80387_constant_p (x))
15706 /* Limit class to non-sse. */
15707 if (class == FLOAT_SSE_REGS)
15709 if (class == FP_TOP_SSE_REGS)
15711 if (class == FP_SECOND_SSE_REGS)
15712 return FP_SECOND_REG;
15713 if (class == FLOAT_INT_REGS || class == FLOAT_REGS)
15719 if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x))
15721 if (MAYBE_SSE_CLASS_P (class) && CONSTANT_P (x))
15724 /* Generally when we see PLUS here, it's the function invariant
15725 (plus soft-fp const_int). Which can only be computed into general
15727 if (GET_CODE (x) == PLUS)
15728 return reg_class_subset_p (class, GENERAL_REGS) ? class : NO_REGS;
15730 /* QImode constants are easy to load, but non-constant QImode data
15731 must go into Q_REGS. */
15732 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
15734 if (reg_class_subset_p (class, Q_REGS))
15736 if (reg_class_subset_p (Q_REGS, class))
15744 /* If we are copying between general and FP registers, we need a memory
15745 location. The same is true for SSE and MMX registers.
15747 The macro can't work reliably when one of the CLASSES is class containing
15748 registers from multiple units (SSE, MMX, integer). We avoid this by never
15749 combining those units in single alternative in the machine description.
15750 Ensure that this constraint holds to avoid unexpected surprises.
15752 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
15753 enforce these sanity checks. */
15756 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
15757 enum machine_mode mode, int strict)
15759 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
15760 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
15761 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
15762 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
15763 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
15764 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
15766 gcc_assert (!strict);
15770 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
15773 /* ??? This is a lie. We do have moves between mmx/general, and for
15774 mmx/sse2. But by saying we need secondary memory we discourage the
15775 register allocator from using the mmx registers unless needed. */
15776 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
15779 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
15781 /* SSE1 doesn't have any direct moves from other classes. */
15785 /* If the target says that inter-unit moves are more expensive
15786 than moving through memory, then don't generate them. */
15787 if (!TARGET_INTER_UNIT_MOVES && !optimize_size)
15790 /* Between SSE and general, we have moves no larger than word size. */
15791 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
15794 /* ??? For the cost of one register reformat penalty, we could use
15795 the same instructions to move SFmode and DFmode data, but the
15796 relevant move patterns don't support those alternatives. */
15797 if (mode == SFmode || mode == DFmode)
15804 /* Return true if the registers in CLASS cannot represent the change from
15805 modes FROM to TO. */
15808 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
15809 enum reg_class class)
15814 /* x87 registers can't do subreg at all, as all values are reformatted
15815 to extended precision. */
15816 if (MAYBE_FLOAT_CLASS_P (class))
15819 if (MAYBE_SSE_CLASS_P (class) || MAYBE_MMX_CLASS_P (class))
15821 /* Vector registers do not support QI or HImode loads. If we don't
15822 disallow a change to these modes, reload will assume it's ok to
15823 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
15824 the vec_dupv4hi pattern. */
15825 if (GET_MODE_SIZE (from) < 4)
15828 /* Vector registers do not support subreg with nonzero offsets, which
15829 are otherwise valid for integer registers. Since we can't see
15830 whether we have a nonzero offset from here, prohibit all
15831 nonparadoxical subregs changing size. */
15832 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
15839 /* Return the cost of moving data from a register in class CLASS1 to
15840 one in class CLASS2.
15842 It is not required that the cost always equal 2 when FROM is the same as TO;
15843 on some machines it is expensive to move between registers if they are not
15844 general registers. */
15847 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
15848 enum reg_class class2)
15850 /* In case we require secondary memory, compute cost of the store followed
15851 by load. In order to avoid bad register allocation choices, we need
15852 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
15854 if (ix86_secondary_memory_needed (class1, class2, mode, 0))
15858 cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
15859 MEMORY_MOVE_COST (mode, class1, 1));
15860 cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
15861 MEMORY_MOVE_COST (mode, class2, 1));
15863 /* In case of copying from general_purpose_register we may emit multiple
15864 stores followed by single load causing memory size mismatch stall.
15865 Count this as arbitrarily high cost of 20. */
15866 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
15869 /* In the case of FP/MMX moves, the registers actually overlap, and we
15870 have to switch modes in order to treat them differently. */
15871 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
15872 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
15878 /* Moves between SSE/MMX and integer unit are expensive. */
15879 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
15880 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
15881 return ix86_cost->mmxsse_to_integer;
15882 if (MAYBE_FLOAT_CLASS_P (class1))
15883 return ix86_cost->fp_move;
15884 if (MAYBE_SSE_CLASS_P (class1))
15885 return ix86_cost->sse_move;
15886 if (MAYBE_MMX_CLASS_P (class1))
15887 return ix86_cost->mmx_move;
15891 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
15894 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
15896 /* Flags and only flags can only hold CCmode values. */
15897 if (CC_REGNO_P (regno))
15898 return GET_MODE_CLASS (mode) == MODE_CC;
15899 if (GET_MODE_CLASS (mode) == MODE_CC
15900 || GET_MODE_CLASS (mode) == MODE_RANDOM
15901 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
15903 if (FP_REGNO_P (regno))
15904 return VALID_FP_MODE_P (mode);
15905 if (SSE_REGNO_P (regno))
15907 /* We implement the move patterns for all vector modes into and
15908 out of SSE registers, even when no operation instructions
15910 return (VALID_SSE_REG_MODE (mode)
15911 || VALID_SSE2_REG_MODE (mode)
15912 || VALID_MMX_REG_MODE (mode)
15913 || VALID_MMX_REG_MODE_3DNOW (mode));
15915 if (MMX_REGNO_P (regno))
15917 /* We implement the move patterns for 3DNOW modes even in MMX mode,
15918 so if the register is available at all, then we can move data of
15919 the given mode into or out of it. */
15920 return (VALID_MMX_REG_MODE (mode)
15921 || VALID_MMX_REG_MODE_3DNOW (mode));
15924 if (mode == QImode)
15926 /* Take care for QImode values - they can be in non-QI regs,
15927 but then they do cause partial register stalls. */
15928 if (regno < 4 || TARGET_64BIT)
15930 if (!TARGET_PARTIAL_REG_STALL)
15932 return reload_in_progress || reload_completed;
15934 /* We handle both integer and floats in the general purpose registers. */
15935 else if (VALID_INT_MODE_P (mode))
15937 else if (VALID_FP_MODE_P (mode))
15939 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
15940 on to use that value in smaller contexts, this can easily force a
15941 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
15942 supporting DImode, allow it. */
15943 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
15949 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
15950 tieable integer mode. */
15953 ix86_tieable_integer_mode_p (enum machine_mode mode)
15962 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
15965 return TARGET_64BIT;
15972 /* Return true if MODE1 is accessible in a register that can hold MODE2
15973 without copying. That is, all register classes that can hold MODE2
15974 can also hold MODE1. */
15977 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
15979 if (mode1 == mode2)
15982 if (ix86_tieable_integer_mode_p (mode1)
15983 && ix86_tieable_integer_mode_p (mode2))
15986 /* MODE2 being XFmode implies fp stack or general regs, which means we
15987 can tie any smaller floating point modes to it. Note that we do not
15988 tie this with TFmode. */
15989 if (mode2 == XFmode)
15990 return mode1 == SFmode || mode1 == DFmode;
15992 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
15993 that we can tie it with SFmode. */
15994 if (mode2 == DFmode)
15995 return mode1 == SFmode;
15997 /* If MODE2 is only appropriate for an SSE register, then tie with
15998 any other mode acceptable to SSE registers. */
15999 if (GET_MODE_SIZE (mode2) >= 8
16000 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
16001 return ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1);
16003 /* If MODE2 is appropriate for an MMX (or SSE) register, then tie
16004 with any other mode acceptable to MMX registers. */
16005 if (GET_MODE_SIZE (mode2) == 8
16006 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
16007 return ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1);
16012 /* Return the cost of moving data of mode M between a
16013 register and memory. A value of 2 is the default; this cost is
16014 relative to those in `REGISTER_MOVE_COST'.
16016 If moving between registers and memory is more expensive than
16017 between two registers, you should define this macro to express the
16020 Model also increased moving costs of QImode registers in non
16024 ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
16026 if (FLOAT_CLASS_P (class))
16043 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
16045 if (SSE_CLASS_P (class))
16048 switch (GET_MODE_SIZE (mode))
16062 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
16064 if (MMX_CLASS_P (class))
16067 switch (GET_MODE_SIZE (mode))
16078 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
16080 switch (GET_MODE_SIZE (mode))
16084 return (Q_CLASS_P (class) ? ix86_cost->int_load[0]
16085 : ix86_cost->movzbl_load);
16087 return (Q_CLASS_P (class) ? ix86_cost->int_store[0]
16088 : ix86_cost->int_store[0] + 4);
16091 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
16093 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
16094 if (mode == TFmode)
16096 return ((in ? ix86_cost->int_load[2] : ix86_cost->int_store[2])
16097 * (((int) GET_MODE_SIZE (mode)
16098 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
16102 /* Compute a (partial) cost for rtx X. Return true if the complete
16103 cost has been computed, and false if subexpressions should be
16104 scanned. In either case, *TOTAL contains the cost result. */
16107 ix86_rtx_costs (rtx x, int code, int outer_code, int *total)
16109 enum machine_mode mode = GET_MODE (x);
16117 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
16119 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
16121 else if (flag_pic && SYMBOLIC_CONST (x)
16123 || (!GET_CODE (x) != LABEL_REF
16124 && (GET_CODE (x) != SYMBOL_REF
16125 || !SYMBOL_REF_LOCAL_P (x)))))
16132 if (mode == VOIDmode)
16135 switch (standard_80387_constant_p (x))
16140 default: /* Other constants */
16145 /* Start with (MEM (SYMBOL_REF)), since that's where
16146 it'll probably end up. Add a penalty for size. */
16147 *total = (COSTS_N_INSNS (1)
16148 + (flag_pic != 0 && !TARGET_64BIT)
16149 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
16155 /* The zero extensions is often completely free on x86_64, so make
16156 it as cheap as possible. */
16157 if (TARGET_64BIT && mode == DImode
16158 && GET_MODE (XEXP (x, 0)) == SImode)
16160 else if (TARGET_ZERO_EXTEND_WITH_AND)
16161 *total = COSTS_N_INSNS (ix86_cost->add);
16163 *total = COSTS_N_INSNS (ix86_cost->movzx);
16167 *total = COSTS_N_INSNS (ix86_cost->movsx);
16171 if (GET_CODE (XEXP (x, 1)) == CONST_INT
16172 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
16174 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16177 *total = COSTS_N_INSNS (ix86_cost->add);
16180 if ((value == 2 || value == 3)
16181 && ix86_cost->lea <= ix86_cost->shift_const)
16183 *total = COSTS_N_INSNS (ix86_cost->lea);
16193 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
16195 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16197 if (INTVAL (XEXP (x, 1)) > 32)
16198 *total = COSTS_N_INSNS(ix86_cost->shift_const + 2);
16200 *total = COSTS_N_INSNS(ix86_cost->shift_const * 2);
16204 if (GET_CODE (XEXP (x, 1)) == AND)
16205 *total = COSTS_N_INSNS(ix86_cost->shift_var * 2);
16207 *total = COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2);
16212 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16213 *total = COSTS_N_INSNS (ix86_cost->shift_const);
16215 *total = COSTS_N_INSNS (ix86_cost->shift_var);
16220 if (FLOAT_MODE_P (mode))
16222 *total = COSTS_N_INSNS (ix86_cost->fmul);
16227 rtx op0 = XEXP (x, 0);
16228 rtx op1 = XEXP (x, 1);
16230 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16232 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16233 for (nbits = 0; value != 0; value &= value - 1)
16237 /* This is arbitrary. */
16240 /* Compute costs correctly for widening multiplication. */
16241 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
16242 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
16243 == GET_MODE_SIZE (mode))
16245 int is_mulwiden = 0;
16246 enum machine_mode inner_mode = GET_MODE (op0);
16248 if (GET_CODE (op0) == GET_CODE (op1))
16249 is_mulwiden = 1, op1 = XEXP (op1, 0);
16250 else if (GET_CODE (op1) == CONST_INT)
16252 if (GET_CODE (op0) == SIGN_EXTEND)
16253 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
16256 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
16260 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
16263 *total = COSTS_N_INSNS (ix86_cost->mult_init[MODE_INDEX (mode)]
16264 + nbits * ix86_cost->mult_bit)
16265 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code);
16274 if (FLOAT_MODE_P (mode))
16275 *total = COSTS_N_INSNS (ix86_cost->fdiv);
16277 *total = COSTS_N_INSNS (ix86_cost->divide[MODE_INDEX (mode)]);
16281 if (FLOAT_MODE_P (mode))
16282 *total = COSTS_N_INSNS (ix86_cost->fadd);
16283 else if (GET_MODE_CLASS (mode) == MODE_INT
16284 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
16286 if (GET_CODE (XEXP (x, 0)) == PLUS
16287 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
16288 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
16289 && CONSTANT_P (XEXP (x, 1)))
16291 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
16292 if (val == 2 || val == 4 || val == 8)
16294 *total = COSTS_N_INSNS (ix86_cost->lea);
16295 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
16296 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
16298 *total += rtx_cost (XEXP (x, 1), outer_code);
16302 else if (GET_CODE (XEXP (x, 0)) == MULT
16303 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
16305 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
16306 if (val == 2 || val == 4 || val == 8)
16308 *total = COSTS_N_INSNS (ix86_cost->lea);
16309 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
16310 *total += rtx_cost (XEXP (x, 1), outer_code);
16314 else if (GET_CODE (XEXP (x, 0)) == PLUS)
16316 *total = COSTS_N_INSNS (ix86_cost->lea);
16317 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
16318 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
16319 *total += rtx_cost (XEXP (x, 1), outer_code);
16326 if (FLOAT_MODE_P (mode))
16328 *total = COSTS_N_INSNS (ix86_cost->fadd);
16336 if (!TARGET_64BIT && mode == DImode)
16338 *total = (COSTS_N_INSNS (ix86_cost->add) * 2
16339 + (rtx_cost (XEXP (x, 0), outer_code)
16340 << (GET_MODE (XEXP (x, 0)) != DImode))
16341 + (rtx_cost (XEXP (x, 1), outer_code)
16342 << (GET_MODE (XEXP (x, 1)) != DImode)));
16348 if (FLOAT_MODE_P (mode))
16350 *total = COSTS_N_INSNS (ix86_cost->fchs);
16356 if (!TARGET_64BIT && mode == DImode)
16357 *total = COSTS_N_INSNS (ix86_cost->add * 2);
16359 *total = COSTS_N_INSNS (ix86_cost->add);
16363 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
16364 && XEXP (XEXP (x, 0), 1) == const1_rtx
16365 && GET_CODE (XEXP (XEXP (x, 0), 2)) == CONST_INT
16366 && XEXP (x, 1) == const0_rtx)
16368 /* This kind of construct is implemented using test[bwl].
16369 Treat it as if we had an AND. */
16370 *total = (COSTS_N_INSNS (ix86_cost->add)
16371 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
16372 + rtx_cost (const1_rtx, outer_code));
16378 if (!TARGET_SSE_MATH
16380 || (mode == DFmode && !TARGET_SSE2))
16385 if (FLOAT_MODE_P (mode))
16386 *total = COSTS_N_INSNS (ix86_cost->fabs);
16390 if (FLOAT_MODE_P (mode))
16391 *total = COSTS_N_INSNS (ix86_cost->fsqrt);
16395 if (XINT (x, 1) == UNSPEC_TP)
16406 static int current_machopic_label_num;
16408 /* Given a symbol name and its associated stub, write out the
16409 definition of the stub. */
16412 machopic_output_stub (FILE *file, const char *symb, const char *stub)
16414 unsigned int length;
16415 char *binder_name, *symbol_name, lazy_ptr_name[32];
16416 int label = ++current_machopic_label_num;
16418 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16419 symb = (*targetm.strip_name_encoding) (symb);
16421 length = strlen (stub);
16422 binder_name = alloca (length + 32);
16423 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
16425 length = strlen (symb);
16426 symbol_name = alloca (length + 32);
16427 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16429 sprintf (lazy_ptr_name, "L%d$lz", label);
16432 machopic_picsymbol_stub_section ();
16434 machopic_symbol_stub_section ();
16436 fprintf (file, "%s:\n", stub);
16437 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16441 fprintf (file, "\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n", label, label);
16442 fprintf (file, "\tmovl %s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
16443 fprintf (file, "\tjmp %%edx\n");
16446 fprintf (file, "\tjmp *%s\n", lazy_ptr_name);
16448 fprintf (file, "%s:\n", binder_name);
16452 fprintf (file, "\tlea %s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
16453 fprintf (file, "\tpushl %%eax\n");
16456 fprintf (file, "\t pushl $%s\n", lazy_ptr_name);
16458 fprintf (file, "\tjmp dyld_stub_binding_helper\n");
16460 machopic_lazy_symbol_ptr_section ();
16461 fprintf (file, "%s:\n", lazy_ptr_name);
16462 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16463 fprintf (file, "\t.long %s\n", binder_name);
16465 #endif /* TARGET_MACHO */
16467 /* Order the registers for register allocator. */
16470 x86_order_regs_for_local_alloc (void)
16475 /* First allocate the local general purpose registers. */
16476 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16477 if (GENERAL_REGNO_P (i) && call_used_regs[i])
16478 reg_alloc_order [pos++] = i;
16480 /* Global general purpose registers. */
16481 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16482 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
16483 reg_alloc_order [pos++] = i;
16485 /* x87 registers come first in case we are doing FP math
16487 if (!TARGET_SSE_MATH)
16488 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
16489 reg_alloc_order [pos++] = i;
16491 /* SSE registers. */
16492 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
16493 reg_alloc_order [pos++] = i;
16494 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
16495 reg_alloc_order [pos++] = i;
16497 /* x87 registers. */
16498 if (TARGET_SSE_MATH)
16499 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
16500 reg_alloc_order [pos++] = i;
16502 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
16503 reg_alloc_order [pos++] = i;
16505 /* Initialize the rest of array as we do not allocate some registers
16507 while (pos < FIRST_PSEUDO_REGISTER)
16508 reg_alloc_order [pos++] = 0;
16511 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
16512 struct attribute_spec.handler. */
16514 ix86_handle_struct_attribute (tree *node, tree name,
16515 tree args ATTRIBUTE_UNUSED,
16516 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
16519 if (DECL_P (*node))
16521 if (TREE_CODE (*node) == TYPE_DECL)
16522 type = &TREE_TYPE (*node);
16527 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
16528 || TREE_CODE (*type) == UNION_TYPE)))
16530 warning (OPT_Wattributes, "%qs attribute ignored",
16531 IDENTIFIER_POINTER (name));
16532 *no_add_attrs = true;
16535 else if ((is_attribute_p ("ms_struct", name)
16536 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
16537 || ((is_attribute_p ("gcc_struct", name)
16538 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
16540 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
16541 IDENTIFIER_POINTER (name));
16542 *no_add_attrs = true;
16549 ix86_ms_bitfield_layout_p (tree record_type)
16551 return (TARGET_MS_BITFIELD_LAYOUT &&
16552 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
16553 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
16556 /* Returns an expression indicating where the this parameter is
16557 located on entry to the FUNCTION. */
16560 x86_this_parameter (tree function)
16562 tree type = TREE_TYPE (function);
16566 int n = aggregate_value_p (TREE_TYPE (type), type) != 0;
16567 return gen_rtx_REG (DImode, x86_64_int_parameter_registers[n]);
16570 if (ix86_function_regparm (type, function) > 0)
16574 parm = TYPE_ARG_TYPES (type);
16575 /* Figure out whether or not the function has a variable number of
16577 for (; parm; parm = TREE_CHAIN (parm))
16578 if (TREE_VALUE (parm) == void_type_node)
16580 /* If not, the this parameter is in the first argument. */
16584 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
16586 return gen_rtx_REG (SImode, regno);
16590 if (aggregate_value_p (TREE_TYPE (type), type))
16591 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));
16593 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));
16596 /* Determine whether x86_output_mi_thunk can succeed. */
16599 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
16600 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
16601 HOST_WIDE_INT vcall_offset, tree function)
16603 /* 64-bit can handle anything. */
16607 /* For 32-bit, everything's fine if we have one free register. */
16608 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
16611 /* Need a free register for vcall_offset. */
16615 /* Need a free register for GOT references. */
16616 if (flag_pic && !(*targetm.binds_local_p) (function))
16619 /* Otherwise ok. */
16623 /* Output the assembler code for a thunk function. THUNK_DECL is the
16624 declaration for the thunk function itself, FUNCTION is the decl for
16625 the target function. DELTA is an immediate constant offset to be
16626 added to THIS. If VCALL_OFFSET is nonzero, the word at
16627 *(*this + vcall_offset) should be added to THIS. */
16630 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
16631 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
16632 HOST_WIDE_INT vcall_offset, tree function)
16635 rtx this = x86_this_parameter (function);
16638 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
16639 pull it in now and let DELTA benefit. */
16642 else if (vcall_offset)
16644 /* Put the this parameter into %eax. */
16646 xops[1] = this_reg = gen_rtx_REG (Pmode, 0);
16647 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16650 this_reg = NULL_RTX;
16652 /* Adjust the this parameter by a fixed constant. */
16655 xops[0] = GEN_INT (delta);
16656 xops[1] = this_reg ? this_reg : this;
16659 if (!x86_64_general_operand (xops[0], DImode))
16661 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
16663 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
16667 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
16670 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
16673 /* Adjust the this parameter by a value stored in the vtable. */
16677 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
16680 int tmp_regno = 2 /* ECX */;
16681 if (lookup_attribute ("fastcall",
16682 TYPE_ATTRIBUTES (TREE_TYPE (function))))
16683 tmp_regno = 0 /* EAX */;
16684 tmp = gen_rtx_REG (SImode, tmp_regno);
16687 xops[0] = gen_rtx_MEM (Pmode, this_reg);
16690 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
16692 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16694 /* Adjust the this parameter. */
16695 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
16696 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
16698 rtx tmp2 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
16699 xops[0] = GEN_INT (vcall_offset);
16701 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
16702 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
16704 xops[1] = this_reg;
16706 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
16708 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
16711 /* If necessary, drop THIS back to its stack slot. */
16712 if (this_reg && this_reg != this)
16714 xops[0] = this_reg;
16716 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16719 xops[0] = XEXP (DECL_RTL (function), 0);
16722 if (!flag_pic || (*targetm.binds_local_p) (function))
16723 output_asm_insn ("jmp\t%P0", xops);
16726 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
16727 tmp = gen_rtx_CONST (Pmode, tmp);
16728 tmp = gen_rtx_MEM (QImode, tmp);
16730 output_asm_insn ("jmp\t%A0", xops);
16735 if (!flag_pic || (*targetm.binds_local_p) (function))
16736 output_asm_insn ("jmp\t%P0", xops);
16741 rtx sym_ref = XEXP (DECL_RTL (function), 0);
16742 tmp = (gen_rtx_SYMBOL_REF
16744 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
16745 tmp = gen_rtx_MEM (QImode, tmp);
16747 output_asm_insn ("jmp\t%0", xops);
16750 #endif /* TARGET_MACHO */
16752 tmp = gen_rtx_REG (SImode, 2 /* ECX */);
16753 output_set_got (tmp);
16756 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
16757 output_asm_insn ("jmp\t{*}%1", xops);
16763 x86_file_start (void)
16765 default_file_start ();
16766 if (X86_FILE_START_VERSION_DIRECTIVE)
16767 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
16768 if (X86_FILE_START_FLTUSED)
16769 fputs ("\t.global\t__fltused\n", asm_out_file);
16770 if (ix86_asm_dialect == ASM_INTEL)
16771 fputs ("\t.intel_syntax\n", asm_out_file);
16775 x86_field_alignment (tree field, int computed)
16777 enum machine_mode mode;
16778 tree type = TREE_TYPE (field);
16780 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
16782 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
16783 ? get_inner_array_type (type) : type);
16784 if (mode == DFmode || mode == DCmode
16785 || GET_MODE_CLASS (mode) == MODE_INT
16786 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
16787 return MIN (32, computed);
16791 /* Output assembler code to FILE to increment profiler label # LABELNO
16792 for profiling a function entry. */
16794 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
16799 #ifndef NO_PROFILE_COUNTERS
16800 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
16802 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
16806 #ifndef NO_PROFILE_COUNTERS
16807 fprintf (file, "\tmovq\t$%sP%d,%%r11\n", LPREFIX, labelno);
16809 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
16813 #ifndef NO_PROFILE_COUNTERS
16814 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
16815 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
16817 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
16821 #ifndef NO_PROFILE_COUNTERS
16822 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
16823 PROFILE_COUNT_REGISTER);
16825 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
16829 /* We don't have exact information about the insn sizes, but we may assume
16830 quite safely that we are informed about all 1 byte insns and memory
16831 address sizes. This is enough to eliminate unnecessary padding in
16835 min_insn_size (rtx insn)
16839 if (!INSN_P (insn) || !active_insn_p (insn))
16842 /* Discard alignments we've emit and jump instructions. */
16843 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
16844 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
16846 if (GET_CODE (insn) == JUMP_INSN
16847 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
16848 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
16851 /* Important case - calls are always 5 bytes.
16852 It is common to have many calls in the row. */
16853 if (GET_CODE (insn) == CALL_INSN
16854 && symbolic_reference_mentioned_p (PATTERN (insn))
16855 && !SIBLING_CALL_P (insn))
16857 if (get_attr_length (insn) <= 1)
16860 /* For normal instructions we may rely on the sizes of addresses
16861 and the presence of symbol to require 4 bytes of encoding.
16862 This is not the case for jumps where references are PC relative. */
16863 if (GET_CODE (insn) != JUMP_INSN)
16865 l = get_attr_length_address (insn);
16866 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
16875 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
16879 ix86_avoid_jump_misspredicts (void)
16881 rtx insn, start = get_insns ();
16882 int nbytes = 0, njumps = 0;
16885 /* Look for all minimal intervals of instructions containing 4 jumps.
16886 The intervals are bounded by START and INSN. NBYTES is the total
16887 size of instructions in the interval including INSN and not including
16888 START. When the NBYTES is smaller than 16 bytes, it is possible
16889 that the end of START and INSN ends up in the same 16byte page.
16891 The smallest offset in the page INSN can start is the case where START
16892 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
16893 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
16895 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16898 nbytes += min_insn_size (insn);
16900 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
16901 INSN_UID (insn), min_insn_size (insn));
16902 if ((GET_CODE (insn) == JUMP_INSN
16903 && GET_CODE (PATTERN (insn)) != ADDR_VEC
16904 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
16905 || GET_CODE (insn) == CALL_INSN)
16912 start = NEXT_INSN (start);
16913 if ((GET_CODE (start) == JUMP_INSN
16914 && GET_CODE (PATTERN (start)) != ADDR_VEC
16915 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
16916 || GET_CODE (start) == CALL_INSN)
16917 njumps--, isjump = 1;
16920 nbytes -= min_insn_size (start);
16922 gcc_assert (njumps >= 0);
16924 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
16925 INSN_UID (start), INSN_UID (insn), nbytes);
16927 if (njumps == 3 && isjump && nbytes < 16)
16929 int padsize = 15 - nbytes + min_insn_size (insn);
16932 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
16933 INSN_UID (insn), padsize);
16934 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
16939 /* AMD Athlon works faster
16940 when RET is not destination of conditional jump or directly preceded
16941 by other jump instruction. We avoid the penalty by inserting NOP just
16942 before the RET instructions in such cases. */
16944 ix86_pad_returns (void)
16949 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
16951 basic_block bb = e->src;
16952 rtx ret = BB_END (bb);
16954 bool replace = false;
16956 if (GET_CODE (ret) != JUMP_INSN || GET_CODE (PATTERN (ret)) != RETURN
16957 || !maybe_hot_bb_p (bb))
16959 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
16960 if (active_insn_p (prev) || GET_CODE (prev) == CODE_LABEL)
16962 if (prev && GET_CODE (prev) == CODE_LABEL)
16967 FOR_EACH_EDGE (e, ei, bb->preds)
16968 if (EDGE_FREQUENCY (e) && e->src->index >= 0
16969 && !(e->flags & EDGE_FALLTHRU))
16974 prev = prev_active_insn (ret);
16976 && ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev))
16977 || GET_CODE (prev) == CALL_INSN))
16979 /* Empty functions get branch mispredict even when the jump destination
16980 is not visible to us. */
16981 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
16986 emit_insn_before (gen_return_internal_long (), ret);
16992 /* Implement machine specific optimizations. We implement padding of returns
16993 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
16997 if (TARGET_ATHLON_K8 && optimize && !optimize_size)
16998 ix86_pad_returns ();
16999 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
17000 ix86_avoid_jump_misspredicts ();
17003 /* Return nonzero when QImode register that must be represented via REX prefix
17006 x86_extended_QIreg_mentioned_p (rtx insn)
17009 extract_insn_cached (insn);
17010 for (i = 0; i < recog_data.n_operands; i++)
17011 if (REG_P (recog_data.operand[i])
17012 && REGNO (recog_data.operand[i]) >= 4)
17017 /* Return nonzero when P points to register encoded via REX prefix.
17018 Called via for_each_rtx. */
17020 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
17022 unsigned int regno;
17025 regno = REGNO (*p);
17026 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
17029 /* Return true when INSN mentions register that must be encoded using REX
17032 x86_extended_reg_mentioned_p (rtx insn)
17034 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
17037 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
17038 optabs would emit if we didn't have TFmode patterns. */
17041 x86_emit_floatuns (rtx operands[2])
17043 rtx neglab, donelab, i0, i1, f0, in, out;
17044 enum machine_mode mode, inmode;
17046 inmode = GET_MODE (operands[1]);
17047 gcc_assert (inmode == SImode || inmode == DImode);
17050 in = force_reg (inmode, operands[1]);
17051 mode = GET_MODE (out);
17052 neglab = gen_label_rtx ();
17053 donelab = gen_label_rtx ();
17054 i1 = gen_reg_rtx (Pmode);
17055 f0 = gen_reg_rtx (mode);
17057 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, Pmode, 0, neglab);
17059 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
17060 emit_jump_insn (gen_jump (donelab));
17063 emit_label (neglab);
17065 i0 = expand_simple_binop (Pmode, LSHIFTRT, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17066 i1 = expand_simple_binop (Pmode, AND, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17067 i0 = expand_simple_binop (Pmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
17068 expand_float (f0, i0, 0);
17069 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
17071 emit_label (donelab);
17074 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17075 with all elements equal to VAR. Return true if successful. */
17078 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
17079 rtx target, rtx val)
17081 enum machine_mode smode, wsmode, wvmode;
17088 if (!mmx_ok && !TARGET_SSE)
17096 val = force_reg (GET_MODE_INNER (mode), val);
17097 x = gen_rtx_VEC_DUPLICATE (mode, val);
17098 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17104 if (TARGET_SSE || TARGET_3DNOW_A)
17106 val = gen_lowpart (SImode, val);
17107 x = gen_rtx_TRUNCATE (HImode, val);
17108 x = gen_rtx_VEC_DUPLICATE (mode, x);
17109 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17138 /* Replicate the value once into the next wider mode and recurse. */
17139 val = convert_modes (wsmode, smode, val, true);
17140 x = expand_simple_binop (wsmode, ASHIFT, val,
17141 GEN_INT (GET_MODE_BITSIZE (smode)),
17142 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17143 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
17145 x = gen_reg_rtx (wvmode);
17146 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
17147 gcc_unreachable ();
17148 emit_move_insn (target, gen_lowpart (mode, x));
17156 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17157 whose low element is VAR, and other elements are zero. Return true
17161 ix86_expand_vector_init_low_nonzero (bool mmx_ok, enum machine_mode mode,
17162 rtx target, rtx var)
17164 enum machine_mode vsimode;
17171 if (!mmx_ok && !TARGET_SSE)
17177 var = force_reg (GET_MODE_INNER (mode), var);
17178 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
17179 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17184 var = force_reg (GET_MODE_INNER (mode), var);
17185 x = gen_rtx_VEC_DUPLICATE (mode, var);
17186 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
17187 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17192 vsimode = V4SImode;
17198 vsimode = V2SImode;
17201 /* Zero extend the variable element to SImode and recurse. */
17202 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
17204 x = gen_reg_rtx (vsimode);
17205 if (!ix86_expand_vector_init_low_nonzero (mmx_ok, vsimode, x, var))
17206 gcc_unreachable ();
17208 emit_move_insn (target, gen_lowpart (mode, x));
17216 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17217 consisting of the values in VALS. It is known that all elements
17218 except ONE_VAR are constants. Return true if successful. */
17221 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
17222 rtx target, rtx vals, int one_var)
17224 rtx var = XVECEXP (vals, 0, one_var);
17225 enum machine_mode wmode;
17228 const_vec = copy_rtx (vals);
17229 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
17230 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
17238 /* For the two element vectors, it's just as easy to use
17239 the general case. */
17255 /* There's no way to set one QImode entry easily. Combine
17256 the variable value with its adjacent constant value, and
17257 promote to an HImode set. */
17258 x = XVECEXP (vals, 0, one_var ^ 1);
17261 var = convert_modes (HImode, QImode, var, true);
17262 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
17263 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17264 x = GEN_INT (INTVAL (x) & 0xff);
17268 var = convert_modes (HImode, QImode, var, true);
17269 x = gen_int_mode (INTVAL (x) << 8, HImode);
17271 if (x != const0_rtx)
17272 var = expand_simple_binop (HImode, IOR, var, x, var,
17273 1, OPTAB_LIB_WIDEN);
17275 x = gen_reg_rtx (wmode);
17276 emit_move_insn (x, gen_lowpart (wmode, const_vec));
17277 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
17279 emit_move_insn (target, gen_lowpart (mode, x));
17286 emit_move_insn (target, const_vec);
17287 ix86_expand_vector_set (mmx_ok, target, var, one_var);
17291 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
17292 all values variable, and none identical. */
17295 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
17296 rtx target, rtx vals)
17298 enum machine_mode half_mode = GET_MODE_INNER (mode);
17299 rtx op0 = NULL, op1 = NULL;
17300 bool use_vec_concat = false;
17306 if (!mmx_ok && !TARGET_SSE)
17312 /* For the two element vectors, we always implement VEC_CONCAT. */
17313 op0 = XVECEXP (vals, 0, 0);
17314 op1 = XVECEXP (vals, 0, 1);
17315 use_vec_concat = true;
17319 half_mode = V2SFmode;
17322 half_mode = V2SImode;
17328 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
17329 Recurse to load the two halves. */
17331 op0 = gen_reg_rtx (half_mode);
17332 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
17333 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
17335 op1 = gen_reg_rtx (half_mode);
17336 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
17337 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
17339 use_vec_concat = true;
17350 gcc_unreachable ();
17353 if (use_vec_concat)
17355 if (!register_operand (op0, half_mode))
17356 op0 = force_reg (half_mode, op0);
17357 if (!register_operand (op1, half_mode))
17358 op1 = force_reg (half_mode, op1);
17360 emit_insn (gen_rtx_SET (VOIDmode, target,
17361 gen_rtx_VEC_CONCAT (mode, op0, op1)));
17365 int i, j, n_elts, n_words, n_elt_per_word;
17366 enum machine_mode inner_mode;
17367 rtx words[4], shift;
17369 inner_mode = GET_MODE_INNER (mode);
17370 n_elts = GET_MODE_NUNITS (mode);
17371 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
17372 n_elt_per_word = n_elts / n_words;
17373 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
17375 for (i = 0; i < n_words; ++i)
17377 rtx word = NULL_RTX;
17379 for (j = 0; j < n_elt_per_word; ++j)
17381 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
17382 elt = convert_modes (word_mode, inner_mode, elt, true);
17388 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
17389 word, 1, OPTAB_LIB_WIDEN);
17390 word = expand_simple_binop (word_mode, IOR, word, elt,
17391 word, 1, OPTAB_LIB_WIDEN);
17399 emit_move_insn (target, gen_lowpart (mode, words[0]));
17400 else if (n_words == 2)
17402 rtx tmp = gen_reg_rtx (mode);
17403 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
17404 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
17405 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
17406 emit_move_insn (target, tmp);
17408 else if (n_words == 4)
17410 rtx tmp = gen_reg_rtx (V4SImode);
17411 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
17412 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
17413 emit_move_insn (target, gen_lowpart (mode, tmp));
17416 gcc_unreachable ();
17420 /* Initialize vector TARGET via VALS. Suppress the use of MMX
17421 instructions unless MMX_OK is true. */
17424 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
17426 enum machine_mode mode = GET_MODE (target);
17427 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17428 int n_elts = GET_MODE_NUNITS (mode);
17429 int n_var = 0, one_var = -1;
17430 bool all_same = true, all_const_zero = true;
17434 for (i = 0; i < n_elts; ++i)
17436 x = XVECEXP (vals, 0, i);
17437 if (!CONSTANT_P (x))
17438 n_var++, one_var = i;
17439 else if (x != CONST0_RTX (inner_mode))
17440 all_const_zero = false;
17441 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17445 /* Constants are best loaded from the constant pool. */
17448 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
17452 /* If all values are identical, broadcast the value. */
17454 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
17455 XVECEXP (vals, 0, 0)))
17458 /* Values where only one field is non-constant are best loaded from
17459 the pool and overwritten via move later. */
17462 if (all_const_zero && one_var == 0
17463 && ix86_expand_vector_init_low_nonzero (mmx_ok, mode, target,
17464 XVECEXP (vals, 0, 0)))
17467 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
17471 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
17475 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
17477 enum machine_mode mode = GET_MODE (target);
17478 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17479 bool use_vec_merge = false;
17488 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
17489 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
17491 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
17493 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
17494 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17504 /* For the two element vectors, we implement a VEC_CONCAT with
17505 the extraction of the other element. */
17507 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
17508 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
17511 op0 = val, op1 = tmp;
17513 op0 = tmp, op1 = val;
17515 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
17516 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17524 use_vec_merge = true;
17528 /* tmp = target = A B C D */
17529 tmp = copy_to_reg (target);
17530 /* target = A A B B */
17531 emit_insn (gen_sse_unpcklps (target, target, target));
17532 /* target = X A B B */
17533 ix86_expand_vector_set (false, target, val, 0);
17534 /* target = A X C D */
17535 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17536 GEN_INT (1), GEN_INT (0),
17537 GEN_INT (2+4), GEN_INT (3+4)));
17541 /* tmp = target = A B C D */
17542 tmp = copy_to_reg (target);
17543 /* tmp = X B C D */
17544 ix86_expand_vector_set (false, tmp, val, 0);
17545 /* target = A B X D */
17546 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17547 GEN_INT (0), GEN_INT (1),
17548 GEN_INT (0+4), GEN_INT (3+4)));
17552 /* tmp = target = A B C D */
17553 tmp = copy_to_reg (target);
17554 /* tmp = X B C D */
17555 ix86_expand_vector_set (false, tmp, val, 0);
17556 /* target = A B X D */
17557 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17558 GEN_INT (0), GEN_INT (1),
17559 GEN_INT (2+4), GEN_INT (0+4)));
17563 gcc_unreachable ();
17568 /* Element 0 handled by vec_merge below. */
17571 use_vec_merge = true;
17577 /* With SSE2, use integer shuffles to swap element 0 and ELT,
17578 store into element 0, then shuffle them back. */
17582 order[0] = GEN_INT (elt);
17583 order[1] = const1_rtx;
17584 order[2] = const2_rtx;
17585 order[3] = GEN_INT (3);
17586 order[elt] = const0_rtx;
17588 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
17589 order[1], order[2], order[3]));
17591 ix86_expand_vector_set (false, target, val, 0);
17593 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
17594 order[1], order[2], order[3]));
17598 /* For SSE1, we have to reuse the V4SF code. */
17599 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
17600 gen_lowpart (SFmode, val), elt);
17605 use_vec_merge = TARGET_SSE2;
17608 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
17619 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
17620 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
17621 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17625 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
17627 emit_move_insn (mem, target);
17629 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
17630 emit_move_insn (tmp, val);
17632 emit_move_insn (target, mem);
17637 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
17639 enum machine_mode mode = GET_MODE (vec);
17640 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17641 bool use_vec_extr = false;
17654 use_vec_extr = true;
17666 tmp = gen_reg_rtx (mode);
17667 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
17668 GEN_INT (elt), GEN_INT (elt),
17669 GEN_INT (elt+4), GEN_INT (elt+4)));
17673 tmp = gen_reg_rtx (mode);
17674 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
17678 gcc_unreachable ();
17681 use_vec_extr = true;
17696 tmp = gen_reg_rtx (mode);
17697 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
17698 GEN_INT (elt), GEN_INT (elt),
17699 GEN_INT (elt), GEN_INT (elt)));
17703 tmp = gen_reg_rtx (mode);
17704 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
17708 gcc_unreachable ();
17711 use_vec_extr = true;
17716 /* For SSE1, we have to reuse the V4SF code. */
17717 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
17718 gen_lowpart (V4SFmode, vec), elt);
17724 use_vec_extr = TARGET_SSE2;
17727 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
17732 /* ??? Could extract the appropriate HImode element and shift. */
17739 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
17740 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
17742 /* Let the rtl optimizers know about the zero extension performed. */
17743 if (inner_mode == HImode)
17745 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
17746 target = gen_lowpart (SImode, target);
17749 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17753 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
17755 emit_move_insn (mem, vec);
17757 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
17758 emit_move_insn (target, tmp);
17762 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
17763 pattern to reduce; DEST is the destination; IN is the input vector. */
17766 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
17768 rtx tmp1, tmp2, tmp3;
17770 tmp1 = gen_reg_rtx (V4SFmode);
17771 tmp2 = gen_reg_rtx (V4SFmode);
17772 tmp3 = gen_reg_rtx (V4SFmode);
17774 emit_insn (gen_sse_movhlps (tmp1, in, in));
17775 emit_insn (fn (tmp2, tmp1, in));
17777 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
17778 GEN_INT (1), GEN_INT (1),
17779 GEN_INT (1+4), GEN_INT (1+4)));
17780 emit_insn (fn (dest, tmp2, tmp3));
17783 /* Implements target hook vector_mode_supported_p. */
17785 ix86_vector_mode_supported_p (enum machine_mode mode)
17787 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
17789 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
17791 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
17793 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
17798 /* Worker function for TARGET_MD_ASM_CLOBBERS.
17800 We do this in the new i386 backend to maintain source compatibility
17801 with the old cc0-based compiler. */
17804 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
17805 tree inputs ATTRIBUTE_UNUSED,
17808 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
17810 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
17812 clobbers = tree_cons (NULL_TREE, build_string (7, "dirflag"),
17817 /* Return true if this goes in small data/bss. */
17820 ix86_in_large_data_p (tree exp)
17822 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
17825 /* Functions are never large data. */
17826 if (TREE_CODE (exp) == FUNCTION_DECL)
17829 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
17831 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
17832 if (strcmp (section, ".ldata") == 0
17833 || strcmp (section, ".lbss") == 0)
17839 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
17841 /* If this is an incomplete type with size 0, then we can't put it
17842 in data because it might be too big when completed. */
17843 if (!size || size > ix86_section_threshold)
17850 ix86_encode_section_info (tree decl, rtx rtl, int first)
17852 default_encode_section_info (decl, rtl, first);
17854 if (TREE_CODE (decl) == VAR_DECL
17855 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
17856 && ix86_in_large_data_p (decl))
17857 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
17860 /* Worker function for REVERSE_CONDITION. */
17863 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
17865 return (mode != CCFPmode && mode != CCFPUmode
17866 ? reverse_condition (code)
17867 : reverse_condition_maybe_unordered (code));
17870 /* Output code to perform an x87 FP register move, from OPERANDS[1]
17874 output_387_reg_move (rtx insn, rtx *operands)
17876 if (REG_P (operands[1])
17877 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
17879 if (REGNO (operands[0]) == FIRST_STACK_REG
17880 && TARGET_USE_FFREEP)
17881 return "ffreep\t%y0";
17882 return "fstp\t%y0";
17884 if (STACK_TOP_P (operands[0]))
17885 return "fld%z1\t%y1";
17889 /* Output code to perform a conditional jump to LABEL, if C2 flag in
17890 FP status register is set. */
17893 ix86_emit_fp_unordered_jump (rtx label)
17895 rtx reg = gen_reg_rtx (HImode);
17898 emit_insn (gen_x86_fnstsw_1 (reg));
17900 if (TARGET_USE_SAHF)
17902 emit_insn (gen_x86_sahf_1 (reg));
17904 temp = gen_rtx_REG (CCmode, FLAGS_REG);
17905 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
17909 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
17911 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
17912 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
17915 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
17916 gen_rtx_LABEL_REF (VOIDmode, label),
17918 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
17919 emit_jump_insn (temp);
17922 /* Output code to perform a log1p XFmode calculation. */
17924 void ix86_emit_i387_log1p (rtx op0, rtx op1)
17926 rtx label1 = gen_label_rtx ();
17927 rtx label2 = gen_label_rtx ();
17929 rtx tmp = gen_reg_rtx (XFmode);
17930 rtx tmp2 = gen_reg_rtx (XFmode);
17932 emit_insn (gen_absxf2 (tmp, op1));
17933 emit_insn (gen_cmpxf (tmp,
17934 CONST_DOUBLE_FROM_REAL_VALUE (
17935 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
17937 emit_jump_insn (gen_bge (label1));
17939 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
17940 emit_insn (gen_fyl2xp1_xf3 (op0, tmp2, op1));
17941 emit_jump (label2);
17943 emit_label (label1);
17944 emit_move_insn (tmp, CONST1_RTX (XFmode));
17945 emit_insn (gen_addxf3 (tmp, op1, tmp));
17946 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
17947 emit_insn (gen_fyl2x_xf3 (op0, tmp2, tmp));
17949 emit_label (label2);
17952 /* Solaris named-section hook. Parameters are as for
17953 named_section_real. */
17956 i386_solaris_elf_named_section (const char *name, unsigned int flags,
17959 /* With Binutils 2.15, the "@unwind" marker must be specified on
17960 every occurrence of the ".eh_frame" section, not just the first
17963 && strcmp (name, ".eh_frame") == 0)
17965 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
17966 flags & SECTION_WRITE ? "aw" : "a");
17969 default_elf_asm_named_section (name, flags, decl);
17972 /* Return the mangling of TYPE if it is an extended fundamental type. */
17974 static const char *
17975 ix86_mangle_fundamental_type (tree type)
17977 switch (TYPE_MODE (type))
17980 /* __float128 is "g". */
17983 /* "long double" or __float80 is "e". */
17990 /* For 32-bit code we can save PIC register setup by using
17991 __stack_chk_fail_local hidden function instead of calling
17992 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
17993 register, so it is better to call __stack_chk_fail directly. */
17996 ix86_stack_protect_fail (void)
17998 return TARGET_64BIT
17999 ? default_external_stack_protect_fail ()
18000 : default_hidden_stack_protect_fail ();
18003 /* Select a format to encode pointers in exception handling data. CODE
18004 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
18005 true if the symbol may be affected by dynamic relocations.
18007 ??? All x86 object file formats are capable of representing this.
18008 After all, the relocation needed is the same as for the call insn.
18009 Whether or not a particular assembler allows us to enter such, I
18010 guess we'll have to see. */
18012 asm_preferred_eh_data_format (int code, int global)
18016 int type = DW_EH_PE_sdata8;
18018 || ix86_cmodel == CM_SMALL_PIC
18019 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
18020 type = DW_EH_PE_sdata4;
18021 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
18023 if (ix86_cmodel == CM_SMALL
18024 || (ix86_cmodel == CM_MEDIUM && code))
18025 return DW_EH_PE_udata4;
18026 return DW_EH_PE_absptr;
18029 #include "gt-i386.h"