1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1558 static const unsigned int x86_accumulate_outgoing_args
1559 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1562 static const unsigned int x86_arch_always_fancy_math_387
1563 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1564 | m_NOCONA | m_CORE2 | m_GENERIC;
1566 static enum stringop_alg stringop_alg = no_stringop;
1568 /* In case the average insn count for single function invocation is
1569 lower than this constant, emit fast (but longer) prologue and
1571 #define FAST_PROLOGUE_INSN_COUNT 20
1573 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1574 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1575 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1576 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1578 /* Array of the smallest class containing reg number REGNO, indexed by
1579 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1583 /* ax, dx, cx, bx */
1584 AREG, DREG, CREG, BREG,
1585 /* si, di, bp, sp */
1586 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1588 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1589 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1592 /* flags, fpsr, fpcr, frame */
1593 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1595 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1598 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1601 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1602 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1603 /* SSE REX registers */
1604 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1608 /* The "default" register map used in 32bit mode. */
1610 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1612 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1613 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1614 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1615 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1616 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1617 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1618 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1621 /* The "default" register map used in 64bit mode. */
1623 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1625 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1626 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1627 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1628 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1629 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1630 8,9,10,11,12,13,14,15, /* extended integer registers */
1631 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1634 /* Define the register numbers to be used in Dwarf debugging information.
1635 The SVR4 reference port C compiler uses the following register numbers
1636 in its Dwarf output code:
1637 0 for %eax (gcc regno = 0)
1638 1 for %ecx (gcc regno = 2)
1639 2 for %edx (gcc regno = 1)
1640 3 for %ebx (gcc regno = 3)
1641 4 for %esp (gcc regno = 7)
1642 5 for %ebp (gcc regno = 6)
1643 6 for %esi (gcc regno = 4)
1644 7 for %edi (gcc regno = 5)
1645 The following three DWARF register numbers are never generated by
1646 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1647 believes these numbers have these meanings.
1648 8 for %eip (no gcc equivalent)
1649 9 for %eflags (gcc regno = 17)
1650 10 for %trapno (no gcc equivalent)
1651 It is not at all clear how we should number the FP stack registers
1652 for the x86 architecture. If the version of SDB on x86/svr4 were
1653 a bit less brain dead with respect to floating-point then we would
1654 have a precedent to follow with respect to DWARF register numbers
1655 for x86 FP registers, but the SDB on x86/svr4 is so completely
1656 broken with respect to FP registers that it is hardly worth thinking
1657 of it as something to strive for compatibility with.
1658 The version of x86/svr4 SDB I have at the moment does (partially)
1659 seem to believe that DWARF register number 11 is associated with
1660 the x86 register %st(0), but that's about all. Higher DWARF
1661 register numbers don't seem to be associated with anything in
1662 particular, and even for DWARF regno 11, SDB only seems to under-
1663 stand that it should say that a variable lives in %st(0) (when
1664 asked via an `=' command) if we said it was in DWARF regno 11,
1665 but SDB still prints garbage when asked for the value of the
1666 variable in question (via a `/' command).
1667 (Also note that the labels SDB prints for various FP stack regs
1668 when doing an `x' command are all wrong.)
1669 Note that these problems generally don't affect the native SVR4
1670 C compiler because it doesn't allow the use of -O with -g and
1671 because when it is *not* optimizing, it allocates a memory
1672 location for each floating-point variable, and the memory
1673 location is what gets described in the DWARF AT_location
1674 attribute for the variable in question.
1675 Regardless of the severe mental illness of the x86/svr4 SDB, we
1676 do something sensible here and we use the following DWARF
1677 register numbers. Note that these are all stack-top-relative
1679 11 for %st(0) (gcc regno = 8)
1680 12 for %st(1) (gcc regno = 9)
1681 13 for %st(2) (gcc regno = 10)
1682 14 for %st(3) (gcc regno = 11)
1683 15 for %st(4) (gcc regno = 12)
1684 16 for %st(5) (gcc regno = 13)
1685 17 for %st(6) (gcc regno = 14)
1686 18 for %st(7) (gcc regno = 15)
1688 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1690 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1691 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1692 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1693 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1694 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1695 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1696 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1699 /* Test and compare insns in i386.md store the information needed to
1700 generate branch and scc insns here. */
1702 rtx ix86_compare_op0 = NULL_RTX;
1703 rtx ix86_compare_op1 = NULL_RTX;
1705 /* Define parameter passing and return registers. */
1707 static int const x86_64_int_parameter_registers[6] =
1709 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1712 static int const x86_64_ms_abi_int_parameter_registers[4] =
1714 CX_REG, DX_REG, R8_REG, R9_REG
1717 static int const x86_64_int_return_registers[4] =
1719 AX_REG, DX_REG, DI_REG, SI_REG
1722 /* Define the structure for the machine field in struct function. */
1724 struct GTY(()) stack_local_entry {
1725 unsigned short mode;
1728 struct stack_local_entry *next;
1731 /* Structure describing stack frame layout.
1732 Stack grows downward:
1738 saved frame pointer if frame_pointer_needed
1739 <- HARD_FRAME_POINTER
1748 [va_arg registers] (
1749 > to_allocate <- FRAME_POINTER
1761 HOST_WIDE_INT frame;
1763 int outgoing_arguments_size;
1766 HOST_WIDE_INT to_allocate;
1767 /* The offsets relative to ARG_POINTER. */
1768 HOST_WIDE_INT frame_pointer_offset;
1769 HOST_WIDE_INT hard_frame_pointer_offset;
1770 HOST_WIDE_INT stack_pointer_offset;
1772 /* When save_regs_using_mov is set, emit prologue using
1773 move instead of push instructions. */
1774 bool save_regs_using_mov;
1777 /* Code model option. */
1778 enum cmodel ix86_cmodel;
1780 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1782 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1784 /* Which unit we are generating floating point math for. */
1785 enum fpmath_unit ix86_fpmath;
1787 /* Which cpu are we scheduling for. */
1788 enum attr_cpu ix86_schedule;
1790 /* Which cpu are we optimizing for. */
1791 enum processor_type ix86_tune;
1793 /* Which instruction set architecture to use. */
1794 enum processor_type ix86_arch;
1796 /* true if sse prefetch instruction is not NOOP. */
1797 int x86_prefetch_sse;
1799 /* ix86_regparm_string as a number */
1800 static int ix86_regparm;
1802 /* -mstackrealign option */
1803 extern int ix86_force_align_arg_pointer;
1804 static const char ix86_force_align_arg_pointer_string[]
1805 = "force_align_arg_pointer";
1807 static rtx (*ix86_gen_leave) (void);
1808 static rtx (*ix86_gen_pop1) (rtx);
1809 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1810 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1811 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1812 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1813 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1814 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1816 /* Preferred alignment for stack boundary in bits. */
1817 unsigned int ix86_preferred_stack_boundary;
1819 /* Alignment for incoming stack boundary in bits specified at
1821 static unsigned int ix86_user_incoming_stack_boundary;
1823 /* Default alignment for incoming stack boundary in bits. */
1824 static unsigned int ix86_default_incoming_stack_boundary;
1826 /* Alignment for incoming stack boundary in bits. */
1827 unsigned int ix86_incoming_stack_boundary;
1829 /* The abi used by target. */
1830 enum calling_abi ix86_abi;
1832 /* Values 1-5: see jump.c */
1833 int ix86_branch_cost;
1835 /* Calling abi specific va_list type nodes. */
1836 static GTY(()) tree sysv_va_list_type_node;
1837 static GTY(()) tree ms_va_list_type_node;
1839 /* Variables which are this size or smaller are put in the data/bss
1840 or ldata/lbss sections. */
1842 int ix86_section_threshold = 65536;
1844 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1845 char internal_label_prefix[16];
1846 int internal_label_prefix_len;
1848 /* Fence to use after loop using movnt. */
1851 /* Register class used for passing given 64bit part of the argument.
1852 These represent classes as documented by the PS ABI, with the exception
1853 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1854 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1856 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1857 whenever possible (upper half does contain padding). */
1858 enum x86_64_reg_class
1861 X86_64_INTEGER_CLASS,
1862 X86_64_INTEGERSI_CLASS,
1869 X86_64_COMPLEX_X87_CLASS,
1873 #define MAX_CLASSES 4
1875 /* Table of constants used by fldpi, fldln2, etc.... */
1876 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1877 static bool ext_80387_constants_init = 0;
1880 static struct machine_function * ix86_init_machine_status (void);
1881 static rtx ix86_function_value (const_tree, const_tree, bool);
1882 static rtx ix86_static_chain (const_tree, bool);
1883 static int ix86_function_regparm (const_tree, const_tree);
1884 static void ix86_compute_frame_layout (struct ix86_frame *);
1885 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1887 static void ix86_add_new_builtins (int);
1889 enum ix86_function_specific_strings
1891 IX86_FUNCTION_SPECIFIC_ARCH,
1892 IX86_FUNCTION_SPECIFIC_TUNE,
1893 IX86_FUNCTION_SPECIFIC_FPMATH,
1894 IX86_FUNCTION_SPECIFIC_MAX
1897 static char *ix86_target_string (int, int, const char *, const char *,
1898 const char *, bool);
1899 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1900 static void ix86_function_specific_save (struct cl_target_option *);
1901 static void ix86_function_specific_restore (struct cl_target_option *);
1902 static void ix86_function_specific_print (FILE *, int,
1903 struct cl_target_option *);
1904 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1905 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1906 static bool ix86_can_inline_p (tree, tree);
1907 static void ix86_set_current_function (tree);
1908 static unsigned int ix86_minimum_incoming_stack_boundary (bool);
1910 static enum calling_abi ix86_function_abi (const_tree);
1913 /* The svr4 ABI for the i386 says that records and unions are returned
1915 #ifndef DEFAULT_PCC_STRUCT_RETURN
1916 #define DEFAULT_PCC_STRUCT_RETURN 1
1919 /* Whether -mtune= or -march= were specified */
1920 static int ix86_tune_defaulted;
1921 static int ix86_arch_specified;
1923 /* Bit flags that specify the ISA we are compiling for. */
1924 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1926 /* A mask of ix86_isa_flags that includes bit X if X
1927 was set or cleared on the command line. */
1928 static int ix86_isa_flags_explicit;
1930 /* Define a set of ISAs which are available when a given ISA is
1931 enabled. MMX and SSE ISAs are handled separately. */
1933 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1934 #define OPTION_MASK_ISA_3DNOW_SET \
1935 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1937 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1938 #define OPTION_MASK_ISA_SSE2_SET \
1939 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1940 #define OPTION_MASK_ISA_SSE3_SET \
1941 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1942 #define OPTION_MASK_ISA_SSSE3_SET \
1943 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1944 #define OPTION_MASK_ISA_SSE4_1_SET \
1945 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1946 #define OPTION_MASK_ISA_SSE4_2_SET \
1947 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1948 #define OPTION_MASK_ISA_AVX_SET \
1949 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1950 #define OPTION_MASK_ISA_FMA_SET \
1951 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1953 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1955 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1957 #define OPTION_MASK_ISA_SSE4A_SET \
1958 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1959 #define OPTION_MASK_ISA_FMA4_SET \
1960 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
1961 | OPTION_MASK_ISA_AVX_SET)
1962 #define OPTION_MASK_ISA_XOP_SET \
1963 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
1964 #define OPTION_MASK_ISA_LWP_SET \
1967 /* AES and PCLMUL need SSE2 because they use xmm registers */
1968 #define OPTION_MASK_ISA_AES_SET \
1969 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1970 #define OPTION_MASK_ISA_PCLMUL_SET \
1971 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1973 #define OPTION_MASK_ISA_ABM_SET \
1974 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1976 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1977 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1978 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1979 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1980 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1982 /* Define a set of ISAs which aren't available when a given ISA is
1983 disabled. MMX and SSE ISAs are handled separately. */
1985 #define OPTION_MASK_ISA_MMX_UNSET \
1986 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1987 #define OPTION_MASK_ISA_3DNOW_UNSET \
1988 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1989 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1991 #define OPTION_MASK_ISA_SSE_UNSET \
1992 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1993 #define OPTION_MASK_ISA_SSE2_UNSET \
1994 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1995 #define OPTION_MASK_ISA_SSE3_UNSET \
1996 (OPTION_MASK_ISA_SSE3 \
1997 | OPTION_MASK_ISA_SSSE3_UNSET \
1998 | OPTION_MASK_ISA_SSE4A_UNSET )
1999 #define OPTION_MASK_ISA_SSSE3_UNSET \
2000 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
2001 #define OPTION_MASK_ISA_SSE4_1_UNSET \
2002 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
2003 #define OPTION_MASK_ISA_SSE4_2_UNSET \
2004 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2005 #define OPTION_MASK_ISA_AVX_UNSET \
2006 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2007 | OPTION_MASK_ISA_FMA4_UNSET)
2008 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2010 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2012 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2014 #define OPTION_MASK_ISA_SSE4A_UNSET \
2015 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2017 #define OPTION_MASK_ISA_FMA4_UNSET \
2018 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
2019 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
2020 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
2022 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2023 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2024 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2025 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2026 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2027 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2028 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2029 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2031 /* Vectorization library interface and handlers. */
2032 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2033 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2034 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2036 /* Processor target table, indexed by processor number */
2039 const struct processor_costs *cost; /* Processor costs */
2040 const int align_loop; /* Default alignments. */
2041 const int align_loop_max_skip;
2042 const int align_jump;
2043 const int align_jump_max_skip;
2044 const int align_func;
2047 static const struct ptt processor_target_table[PROCESSOR_max] =
2049 {&i386_cost, 4, 3, 4, 3, 4},
2050 {&i486_cost, 16, 15, 16, 15, 16},
2051 {&pentium_cost, 16, 7, 16, 7, 16},
2052 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2053 {&geode_cost, 0, 0, 0, 0, 0},
2054 {&k6_cost, 32, 7, 32, 7, 32},
2055 {&athlon_cost, 16, 7, 16, 7, 16},
2056 {&pentium4_cost, 0, 0, 0, 0, 0},
2057 {&k8_cost, 16, 7, 16, 7, 16},
2058 {&nocona_cost, 0, 0, 0, 0, 0},
2059 {&core2_cost, 16, 10, 16, 10, 16},
2060 {&generic32_cost, 16, 7, 16, 7, 16},
2061 {&generic64_cost, 16, 10, 16, 10, 16},
2062 {&amdfam10_cost, 32, 24, 32, 7, 32},
2063 {&atom_cost, 16, 7, 16, 7, 16}
2066 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2092 /* Implement TARGET_HANDLE_OPTION. */
2095 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2102 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2103 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2107 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2108 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2115 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2116 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2120 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2121 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2131 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2132 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2136 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2144 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2145 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2149 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2157 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2158 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2162 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2170 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2171 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2175 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2183 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2184 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2188 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2196 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2197 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2201 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2202 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2209 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2210 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2214 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2215 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2222 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2223 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2227 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2228 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2233 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2238 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2239 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2245 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2246 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2250 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2251 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2258 ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
2259 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
2263 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
2264 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
2271 ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
2272 ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
2276 ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
2277 ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
2284 ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
2285 ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
2289 ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
2290 ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
2297 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2298 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2302 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2303 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2310 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2311 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2315 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2316 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2323 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2324 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2328 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2329 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2336 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2337 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2341 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2342 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2349 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2350 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2354 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2355 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2362 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2363 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2367 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2368 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2375 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2376 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2380 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2381 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2388 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2389 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2393 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2394 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2403 /* Return a string the documents the current -m options. The caller is
2404 responsible for freeing the string. */
2407 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2408 const char *fpmath, bool add_nl_p)
2410 struct ix86_target_opts
2412 const char *option; /* option string */
2413 int mask; /* isa mask options */
2416 /* This table is ordered so that options like -msse4.2 that imply
2417 preceding options while match those first. */
2418 static struct ix86_target_opts isa_opts[] =
2420 { "-m64", OPTION_MASK_ISA_64BIT },
2421 { "-mfma4", OPTION_MASK_ISA_FMA4 },
2422 { "-mxop", OPTION_MASK_ISA_XOP },
2423 { "-mlwp", OPTION_MASK_ISA_LWP },
2424 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2425 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2426 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2427 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2428 { "-msse3", OPTION_MASK_ISA_SSE3 },
2429 { "-msse2", OPTION_MASK_ISA_SSE2 },
2430 { "-msse", OPTION_MASK_ISA_SSE },
2431 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2432 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2433 { "-mmmx", OPTION_MASK_ISA_MMX },
2434 { "-mabm", OPTION_MASK_ISA_ABM },
2435 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2436 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2437 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2438 { "-maes", OPTION_MASK_ISA_AES },
2439 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2443 static struct ix86_target_opts flag_opts[] =
2445 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2446 { "-m80387", MASK_80387 },
2447 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2448 { "-malign-double", MASK_ALIGN_DOUBLE },
2449 { "-mcld", MASK_CLD },
2450 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2451 { "-mieee-fp", MASK_IEEE_FP },
2452 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2453 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2454 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2455 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2456 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2457 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2458 { "-mno-red-zone", MASK_NO_RED_ZONE },
2459 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2460 { "-mrecip", MASK_RECIP },
2461 { "-mrtd", MASK_RTD },
2462 { "-msseregparm", MASK_SSEREGPARM },
2463 { "-mstack-arg-probe", MASK_STACK_PROBE },
2464 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2467 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2470 char target_other[40];
2479 memset (opts, '\0', sizeof (opts));
2481 /* Add -march= option. */
2484 opts[num][0] = "-march=";
2485 opts[num++][1] = arch;
2488 /* Add -mtune= option. */
2491 opts[num][0] = "-mtune=";
2492 opts[num++][1] = tune;
2495 /* Pick out the options in isa options. */
2496 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2498 if ((isa & isa_opts[i].mask) != 0)
2500 opts[num++][0] = isa_opts[i].option;
2501 isa &= ~ isa_opts[i].mask;
2505 if (isa && add_nl_p)
2507 opts[num++][0] = isa_other;
2508 sprintf (isa_other, "(other isa: 0x%x)", isa);
2511 /* Add flag options. */
2512 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2514 if ((flags & flag_opts[i].mask) != 0)
2516 opts[num++][0] = flag_opts[i].option;
2517 flags &= ~ flag_opts[i].mask;
2521 if (flags && add_nl_p)
2523 opts[num++][0] = target_other;
2524 sprintf (target_other, "(other flags: 0x%x)", isa);
2527 /* Add -fpmath= option. */
2530 opts[num][0] = "-mfpmath=";
2531 opts[num++][1] = fpmath;
2538 gcc_assert (num < ARRAY_SIZE (opts));
2540 /* Size the string. */
2542 sep_len = (add_nl_p) ? 3 : 1;
2543 for (i = 0; i < num; i++)
2546 for (j = 0; j < 2; j++)
2548 len += strlen (opts[i][j]);
2551 /* Build the string. */
2552 ret = ptr = (char *) xmalloc (len);
2555 for (i = 0; i < num; i++)
2559 for (j = 0; j < 2; j++)
2560 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2567 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2575 for (j = 0; j < 2; j++)
2578 memcpy (ptr, opts[i][j], len2[j]);
2580 line_len += len2[j];
2585 gcc_assert (ret + len >= ptr);
2590 /* Function that is callable from the debugger to print the current
2593 ix86_debug_options (void)
2595 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2596 ix86_arch_string, ix86_tune_string,
2597 ix86_fpmath_string, true);
2601 fprintf (stderr, "%s\n\n", opts);
2605 fputs ("<no options>\n\n", stderr);
2610 /* Sometimes certain combinations of command options do not make
2611 sense on a particular target machine. You can define a macro
2612 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2613 defined, is executed once just after all the command options have
2616 Don't use this macro to turn on various extra optimizations for
2617 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2620 override_options (bool main_args_p)
2623 unsigned int ix86_arch_mask, ix86_tune_mask;
2628 /* Comes from final.c -- no real reason to change it. */
2629 #define MAX_CODE_ALIGN 16
2637 PTA_PREFETCH_SSE = 1 << 4,
2639 PTA_3DNOW_A = 1 << 6,
2643 PTA_POPCNT = 1 << 10,
2645 PTA_SSE4A = 1 << 12,
2646 PTA_NO_SAHF = 1 << 13,
2647 PTA_SSE4_1 = 1 << 14,
2648 PTA_SSE4_2 = 1 << 15,
2650 PTA_PCLMUL = 1 << 17,
2653 PTA_MOVBE = 1 << 20,
2661 const char *const name; /* processor name or nickname. */
2662 const enum processor_type processor;
2663 const enum attr_cpu schedule;
2664 const unsigned /*enum pta_flags*/ flags;
2666 const processor_alias_table[] =
2668 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2669 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2670 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2671 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2672 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2673 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2674 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2675 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2676 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2677 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2678 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2679 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2680 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2682 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2684 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2685 PTA_MMX | PTA_SSE | PTA_SSE2},
2686 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2687 PTA_MMX |PTA_SSE | PTA_SSE2},
2688 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2689 PTA_MMX | PTA_SSE | PTA_SSE2},
2690 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2691 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2692 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2693 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2694 | PTA_CX16 | PTA_NO_SAHF},
2695 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2696 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2697 | PTA_SSSE3 | PTA_CX16},
2698 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2699 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2700 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2701 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2702 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2703 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2704 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2705 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2706 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2707 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2708 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2709 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2710 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2711 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2712 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2713 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2714 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2715 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2716 {"x86-64", PROCESSOR_K8, CPU_K8,
2717 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2718 {"k8", PROCESSOR_K8, CPU_K8,
2719 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2720 | PTA_SSE2 | PTA_NO_SAHF},
2721 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2722 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2723 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2724 {"opteron", PROCESSOR_K8, CPU_K8,
2725 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2726 | PTA_SSE2 | PTA_NO_SAHF},
2727 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2728 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2729 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2730 {"athlon64", PROCESSOR_K8, CPU_K8,
2731 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2732 | PTA_SSE2 | PTA_NO_SAHF},
2733 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2734 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2735 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2736 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2737 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2738 | PTA_SSE2 | PTA_NO_SAHF},
2739 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2740 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2741 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2742 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2743 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2744 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2745 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2746 0 /* flags are only used for -march switch. */ },
2747 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2748 PTA_64BIT /* flags are only used for -march switch. */ },
2751 int const pta_size = ARRAY_SIZE (processor_alias_table);
2753 /* Set up prefix/suffix so the error messages refer to either the command
2754 line argument, or the attribute(target). */
2763 prefix = "option(\"";
2768 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2769 SUBTARGET_OVERRIDE_OPTIONS;
2772 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2773 SUBSUBTARGET_OVERRIDE_OPTIONS;
2776 /* -fPIC is the default for x86_64. */
2777 if (TARGET_MACHO && TARGET_64BIT)
2780 /* Set the default values for switches whose default depends on TARGET_64BIT
2781 in case they weren't overwritten by command line options. */
2784 /* Mach-O doesn't support omitting the frame pointer for now. */
2785 if (flag_omit_frame_pointer == 2)
2786 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2787 if (flag_asynchronous_unwind_tables == 2)
2788 flag_asynchronous_unwind_tables = 1;
2789 if (flag_pcc_struct_return == 2)
2790 flag_pcc_struct_return = 0;
2794 if (flag_omit_frame_pointer == 2)
2795 flag_omit_frame_pointer = 0;
2796 if (flag_asynchronous_unwind_tables == 2)
2797 flag_asynchronous_unwind_tables = 0;
2798 if (flag_pcc_struct_return == 2)
2799 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2802 /* Need to check -mtune=generic first. */
2803 if (ix86_tune_string)
2805 if (!strcmp (ix86_tune_string, "generic")
2806 || !strcmp (ix86_tune_string, "i686")
2807 /* As special support for cross compilers we read -mtune=native
2808 as -mtune=generic. With native compilers we won't see the
2809 -mtune=native, as it was changed by the driver. */
2810 || !strcmp (ix86_tune_string, "native"))
2813 ix86_tune_string = "generic64";
2815 ix86_tune_string = "generic32";
2817 /* If this call is for setting the option attribute, allow the
2818 generic32/generic64 that was previously set. */
2819 else if (!main_args_p
2820 && (!strcmp (ix86_tune_string, "generic32")
2821 || !strcmp (ix86_tune_string, "generic64")))
2823 else if (!strncmp (ix86_tune_string, "generic", 7))
2824 error ("bad value (%s) for %stune=%s %s",
2825 ix86_tune_string, prefix, suffix, sw);
2829 if (ix86_arch_string)
2830 ix86_tune_string = ix86_arch_string;
2831 if (!ix86_tune_string)
2833 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2834 ix86_tune_defaulted = 1;
2837 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2838 need to use a sensible tune option. */
2839 if (!strcmp (ix86_tune_string, "generic")
2840 || !strcmp (ix86_tune_string, "x86-64")
2841 || !strcmp (ix86_tune_string, "i686"))
2844 ix86_tune_string = "generic64";
2846 ix86_tune_string = "generic32";
2849 if (ix86_stringop_string)
2851 if (!strcmp (ix86_stringop_string, "rep_byte"))
2852 stringop_alg = rep_prefix_1_byte;
2853 else if (!strcmp (ix86_stringop_string, "libcall"))
2854 stringop_alg = libcall;
2855 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2856 stringop_alg = rep_prefix_4_byte;
2857 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2859 /* rep; movq isn't available in 32-bit code. */
2860 stringop_alg = rep_prefix_8_byte;
2861 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2862 stringop_alg = loop_1_byte;
2863 else if (!strcmp (ix86_stringop_string, "loop"))
2864 stringop_alg = loop;
2865 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2866 stringop_alg = unrolled_loop;
2868 error ("bad value (%s) for %sstringop-strategy=%s %s",
2869 ix86_stringop_string, prefix, suffix, sw);
2871 if (!strcmp (ix86_tune_string, "x86-64"))
2872 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2873 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2874 prefix, suffix, prefix, suffix, prefix, suffix);
2876 if (!ix86_arch_string)
2877 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2879 ix86_arch_specified = 1;
2881 if (!strcmp (ix86_arch_string, "generic"))
2882 error ("generic CPU can be used only for %stune=%s %s",
2883 prefix, suffix, sw);
2884 if (!strncmp (ix86_arch_string, "generic", 7))
2885 error ("bad value (%s) for %sarch=%s %s",
2886 ix86_arch_string, prefix, suffix, sw);
2888 /* Validate -mabi= value. */
2889 if (ix86_abi_string)
2891 if (strcmp (ix86_abi_string, "sysv") == 0)
2892 ix86_abi = SYSV_ABI;
2893 else if (strcmp (ix86_abi_string, "ms") == 0)
2896 error ("unknown ABI (%s) for %sabi=%s %s",
2897 ix86_abi_string, prefix, suffix, sw);
2900 ix86_abi = DEFAULT_ABI;
2902 if (ix86_cmodel_string != 0)
2904 if (!strcmp (ix86_cmodel_string, "small"))
2905 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2906 else if (!strcmp (ix86_cmodel_string, "medium"))
2907 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2908 else if (!strcmp (ix86_cmodel_string, "large"))
2909 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2911 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2912 else if (!strcmp (ix86_cmodel_string, "32"))
2913 ix86_cmodel = CM_32;
2914 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2915 ix86_cmodel = CM_KERNEL;
2917 error ("bad value (%s) for %scmodel=%s %s",
2918 ix86_cmodel_string, prefix, suffix, sw);
2922 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2923 use of rip-relative addressing. This eliminates fixups that
2924 would otherwise be needed if this object is to be placed in a
2925 DLL, and is essentially just as efficient as direct addressing. */
2926 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2927 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2928 else if (TARGET_64BIT)
2929 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2931 ix86_cmodel = CM_32;
2933 if (ix86_asm_string != 0)
2936 && !strcmp (ix86_asm_string, "intel"))
2937 ix86_asm_dialect = ASM_INTEL;
2938 else if (!strcmp (ix86_asm_string, "att"))
2939 ix86_asm_dialect = ASM_ATT;
2941 error ("bad value (%s) for %sasm=%s %s",
2942 ix86_asm_string, prefix, suffix, sw);
2944 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2945 error ("code model %qs not supported in the %s bit mode",
2946 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2947 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2948 sorry ("%i-bit mode not compiled in",
2949 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2951 for (i = 0; i < pta_size; i++)
2952 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2954 ix86_schedule = processor_alias_table[i].schedule;
2955 ix86_arch = processor_alias_table[i].processor;
2956 /* Default cpu tuning to the architecture. */
2957 ix86_tune = ix86_arch;
2959 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2960 error ("CPU you selected does not support x86-64 "
2963 if (processor_alias_table[i].flags & PTA_MMX
2964 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2965 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2966 if (processor_alias_table[i].flags & PTA_3DNOW
2967 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2968 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2969 if (processor_alias_table[i].flags & PTA_3DNOW_A
2970 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2971 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2972 if (processor_alias_table[i].flags & PTA_SSE
2973 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2974 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2975 if (processor_alias_table[i].flags & PTA_SSE2
2976 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2977 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2978 if (processor_alias_table[i].flags & PTA_SSE3
2979 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2980 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2981 if (processor_alias_table[i].flags & PTA_SSSE3
2982 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2983 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2984 if (processor_alias_table[i].flags & PTA_SSE4_1
2985 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2986 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2987 if (processor_alias_table[i].flags & PTA_SSE4_2
2988 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2989 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2990 if (processor_alias_table[i].flags & PTA_AVX
2991 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2992 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2993 if (processor_alias_table[i].flags & PTA_FMA
2994 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2995 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2996 if (processor_alias_table[i].flags & PTA_SSE4A
2997 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2998 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2999 if (processor_alias_table[i].flags & PTA_FMA4
3000 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
3001 ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
3002 if (processor_alias_table[i].flags & PTA_XOP
3003 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
3004 ix86_isa_flags |= OPTION_MASK_ISA_XOP;
3005 if (processor_alias_table[i].flags & PTA_LWP
3006 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
3007 ix86_isa_flags |= OPTION_MASK_ISA_LWP;
3008 if (processor_alias_table[i].flags & PTA_ABM
3009 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
3010 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
3011 if (processor_alias_table[i].flags & PTA_CX16
3012 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
3013 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
3014 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
3015 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
3016 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
3017 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
3018 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
3019 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
3020 if (processor_alias_table[i].flags & PTA_MOVBE
3021 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
3022 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
3023 if (processor_alias_table[i].flags & PTA_AES
3024 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
3025 ix86_isa_flags |= OPTION_MASK_ISA_AES;
3026 if (processor_alias_table[i].flags & PTA_PCLMUL
3027 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
3028 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
3029 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
3030 x86_prefetch_sse = true;
3036 error ("bad value (%s) for %sarch=%s %s",
3037 ix86_arch_string, prefix, suffix, sw);
3039 ix86_arch_mask = 1u << ix86_arch;
3040 for (i = 0; i < X86_ARCH_LAST; ++i)
3041 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3043 for (i = 0; i < pta_size; i++)
3044 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
3046 ix86_schedule = processor_alias_table[i].schedule;
3047 ix86_tune = processor_alias_table[i].processor;
3048 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
3050 if (ix86_tune_defaulted)
3052 ix86_tune_string = "x86-64";
3053 for (i = 0; i < pta_size; i++)
3054 if (! strcmp (ix86_tune_string,
3055 processor_alias_table[i].name))
3057 ix86_schedule = processor_alias_table[i].schedule;
3058 ix86_tune = processor_alias_table[i].processor;
3061 error ("CPU you selected does not support x86-64 "
3064 /* Intel CPUs have always interpreted SSE prefetch instructions as
3065 NOPs; so, we can enable SSE prefetch instructions even when
3066 -mtune (rather than -march) points us to a processor that has them.
3067 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3068 higher processors. */
3070 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3071 x86_prefetch_sse = true;
3075 error ("bad value (%s) for %stune=%s %s",
3076 ix86_tune_string, prefix, suffix, sw);
3078 ix86_tune_mask = 1u << ix86_tune;
3079 for (i = 0; i < X86_TUNE_LAST; ++i)
3080 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3083 ix86_cost = &ix86_size_cost;
3085 ix86_cost = processor_target_table[ix86_tune].cost;
3087 /* Arrange to set up i386_stack_locals for all functions. */
3088 init_machine_status = ix86_init_machine_status;
3090 /* Validate -mregparm= value. */
3091 if (ix86_regparm_string)
3094 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3095 i = atoi (ix86_regparm_string);
3096 if (i < 0 || i > REGPARM_MAX)
3097 error ("%sregparm=%d%s is not between 0 and %d",
3098 prefix, i, suffix, REGPARM_MAX);
3103 ix86_regparm = REGPARM_MAX;
3105 /* If the user has provided any of the -malign-* options,
3106 warn and use that value only if -falign-* is not set.
3107 Remove this code in GCC 3.2 or later. */
3108 if (ix86_align_loops_string)
3110 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3111 prefix, suffix, suffix);
3112 if (align_loops == 0)
3114 i = atoi (ix86_align_loops_string);
3115 if (i < 0 || i > MAX_CODE_ALIGN)
3116 error ("%salign-loops=%d%s is not between 0 and %d",
3117 prefix, i, suffix, MAX_CODE_ALIGN);
3119 align_loops = 1 << i;
3123 if (ix86_align_jumps_string)
3125 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3126 prefix, suffix, suffix);
3127 if (align_jumps == 0)
3129 i = atoi (ix86_align_jumps_string);
3130 if (i < 0 || i > MAX_CODE_ALIGN)
3131 error ("%salign-loops=%d%s is not between 0 and %d",
3132 prefix, i, suffix, MAX_CODE_ALIGN);
3134 align_jumps = 1 << i;
3138 if (ix86_align_funcs_string)
3140 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3141 prefix, suffix, suffix);
3142 if (align_functions == 0)
3144 i = atoi (ix86_align_funcs_string);
3145 if (i < 0 || i > MAX_CODE_ALIGN)
3146 error ("%salign-loops=%d%s is not between 0 and %d",
3147 prefix, i, suffix, MAX_CODE_ALIGN);
3149 align_functions = 1 << i;
3153 /* Default align_* from the processor table. */
3154 if (align_loops == 0)
3156 align_loops = processor_target_table[ix86_tune].align_loop;
3157 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3159 if (align_jumps == 0)
3161 align_jumps = processor_target_table[ix86_tune].align_jump;
3162 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3164 if (align_functions == 0)
3166 align_functions = processor_target_table[ix86_tune].align_func;
3169 /* Validate -mbranch-cost= value, or provide default. */
3170 ix86_branch_cost = ix86_cost->branch_cost;
3171 if (ix86_branch_cost_string)
3173 i = atoi (ix86_branch_cost_string);
3175 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3177 ix86_branch_cost = i;
3179 if (ix86_section_threshold_string)
3181 i = atoi (ix86_section_threshold_string);
3183 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3185 ix86_section_threshold = i;
3188 if (ix86_tls_dialect_string)
3190 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3191 ix86_tls_dialect = TLS_DIALECT_GNU;
3192 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3193 ix86_tls_dialect = TLS_DIALECT_GNU2;
3194 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3195 ix86_tls_dialect = TLS_DIALECT_SUN;
3197 error ("bad value (%s) for %stls-dialect=%s %s",
3198 ix86_tls_dialect_string, prefix, suffix, sw);
3201 if (ix87_precision_string)
3203 i = atoi (ix87_precision_string);
3204 if (i != 32 && i != 64 && i != 80)
3205 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3210 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3212 /* Enable by default the SSE and MMX builtins. Do allow the user to
3213 explicitly disable any of these. In particular, disabling SSE and
3214 MMX for kernel code is extremely useful. */
3215 if (!ix86_arch_specified)
3217 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3218 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3221 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3225 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3227 if (!ix86_arch_specified)
3229 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3231 /* i386 ABI does not specify red zone. It still makes sense to use it
3232 when programmer takes care to stack from being destroyed. */
3233 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3234 target_flags |= MASK_NO_RED_ZONE;
3237 /* Keep nonleaf frame pointers. */
3238 if (flag_omit_frame_pointer)
3239 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3240 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3241 flag_omit_frame_pointer = 1;
3243 /* If we're doing fast math, we don't care about comparison order
3244 wrt NaNs. This lets us use a shorter comparison sequence. */
3245 if (flag_finite_math_only)
3246 target_flags &= ~MASK_IEEE_FP;
3248 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3249 since the insns won't need emulation. */
3250 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3251 target_flags &= ~MASK_NO_FANCY_MATH_387;
3253 /* Likewise, if the target doesn't have a 387, or we've specified
3254 software floating point, don't use 387 inline intrinsics. */
3256 target_flags |= MASK_NO_FANCY_MATH_387;
3258 /* Turn on MMX builtins for -msse. */
3261 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3262 x86_prefetch_sse = true;
3265 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3266 if (TARGET_SSE4_2 || TARGET_ABM)
3267 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3269 /* Validate -mpreferred-stack-boundary= value or default it to
3270 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3271 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3272 if (ix86_preferred_stack_boundary_string)
3274 i = atoi (ix86_preferred_stack_boundary_string);
3275 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3276 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3277 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3279 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3282 /* Set the default value for -mstackrealign. */
3283 if (ix86_force_align_arg_pointer == -1)
3284 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3286 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3288 /* Validate -mincoming-stack-boundary= value or default it to
3289 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3290 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3291 if (ix86_incoming_stack_boundary_string)
3293 i = atoi (ix86_incoming_stack_boundary_string);
3294 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3295 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3296 i, TARGET_64BIT ? 4 : 2);
3299 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3300 ix86_incoming_stack_boundary
3301 = ix86_user_incoming_stack_boundary;
3305 /* Accept -msseregparm only if at least SSE support is enabled. */
3306 if (TARGET_SSEREGPARM
3308 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3310 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3311 if (ix86_fpmath_string != 0)
3313 if (! strcmp (ix86_fpmath_string, "387"))
3314 ix86_fpmath = FPMATH_387;
3315 else if (! strcmp (ix86_fpmath_string, "sse"))
3319 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3320 ix86_fpmath = FPMATH_387;
3323 ix86_fpmath = FPMATH_SSE;
3325 else if (! strcmp (ix86_fpmath_string, "387,sse")
3326 || ! strcmp (ix86_fpmath_string, "387+sse")
3327 || ! strcmp (ix86_fpmath_string, "sse,387")
3328 || ! strcmp (ix86_fpmath_string, "sse+387")
3329 || ! strcmp (ix86_fpmath_string, "both"))
3333 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3334 ix86_fpmath = FPMATH_387;
3336 else if (!TARGET_80387)
3338 warning (0, "387 instruction set disabled, using SSE arithmetics");
3339 ix86_fpmath = FPMATH_SSE;
3342 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3345 error ("bad value (%s) for %sfpmath=%s %s",
3346 ix86_fpmath_string, prefix, suffix, sw);
3349 /* If the i387 is disabled, then do not return values in it. */
3351 target_flags &= ~MASK_FLOAT_RETURNS;
3353 /* Use external vectorized library in vectorizing intrinsics. */
3354 if (ix86_veclibabi_string)
3356 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3357 ix86_veclib_handler = ix86_veclibabi_svml;
3358 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3359 ix86_veclib_handler = ix86_veclibabi_acml;
3361 error ("unknown vectorization library ABI type (%s) for "
3362 "%sveclibabi=%s %s", ix86_veclibabi_string,
3363 prefix, suffix, sw);
3366 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3367 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3369 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3371 /* ??? Unwind info is not correct around the CFG unless either a frame
3372 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3373 unwind info generation to be aware of the CFG and propagating states
3375 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3376 || flag_exceptions || flag_non_call_exceptions)
3377 && flag_omit_frame_pointer
3378 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3380 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3381 warning (0, "unwind tables currently require either a frame pointer "
3382 "or %saccumulate-outgoing-args%s for correctness",
3384 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3387 /* If stack probes are required, the space used for large function
3388 arguments on the stack must also be probed, so enable
3389 -maccumulate-outgoing-args so this happens in the prologue. */
3390 if (TARGET_STACK_PROBE
3391 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3393 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3394 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3395 "for correctness", prefix, suffix);
3396 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3399 /* For sane SSE instruction set generation we need fcomi instruction.
3400 It is safe to enable all CMOVE instructions. */
3404 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3407 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3408 p = strchr (internal_label_prefix, 'X');
3409 internal_label_prefix_len = p - internal_label_prefix;
3413 /* When scheduling description is not available, disable scheduler pass
3414 so it won't slow down the compilation and make x87 code slower. */
3415 if (!TARGET_SCHEDULE)
3416 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3418 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3419 set_param_value ("simultaneous-prefetches",
3420 ix86_cost->simultaneous_prefetches);
3421 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3422 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3423 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3424 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3425 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3426 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3428 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3429 can be optimized to ap = __builtin_next_arg (0). */
3431 targetm.expand_builtin_va_start = NULL;
3435 ix86_gen_leave = gen_leave_rex64;
3436 ix86_gen_pop1 = gen_popdi1;
3437 ix86_gen_add3 = gen_adddi3;
3438 ix86_gen_sub3 = gen_subdi3;
3439 ix86_gen_sub3_carry = gen_subdi3_carry;
3440 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3441 ix86_gen_monitor = gen_sse3_monitor64;
3442 ix86_gen_andsp = gen_anddi3;
3446 ix86_gen_leave = gen_leave;
3447 ix86_gen_pop1 = gen_popsi1;
3448 ix86_gen_add3 = gen_addsi3;
3449 ix86_gen_sub3 = gen_subsi3;
3450 ix86_gen_sub3_carry = gen_subsi3_carry;
3451 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3452 ix86_gen_monitor = gen_sse3_monitor;
3453 ix86_gen_andsp = gen_andsi3;
3457 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3459 target_flags |= MASK_CLD & ~target_flags_explicit;
3462 /* Save the initial options in case the user does function specific options */
3464 target_option_default_node = target_option_current_node
3465 = build_target_option_node ();
3468 /* Update register usage after having seen the compiler flags. */
3471 ix86_conditional_register_usage (void)
3476 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3478 if (fixed_regs[i] > 1)
3479 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3480 if (call_used_regs[i] > 1)
3481 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3484 /* The PIC register, if it exists, is fixed. */
3485 j = PIC_OFFSET_TABLE_REGNUM;
3486 if (j != INVALID_REGNUM)
3487 fixed_regs[j] = call_used_regs[j] = 1;
3489 /* The MS_ABI changes the set of call-used registers. */
3490 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3492 call_used_regs[SI_REG] = 0;
3493 call_used_regs[DI_REG] = 0;
3494 call_used_regs[XMM6_REG] = 0;
3495 call_used_regs[XMM7_REG] = 0;
3496 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3497 call_used_regs[i] = 0;
3500 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3501 other call-clobbered regs for 64-bit. */
3504 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3506 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3507 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3508 && call_used_regs[i])
3509 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3512 /* If MMX is disabled, squash the registers. */
3514 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3515 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3516 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3518 /* If SSE is disabled, squash the registers. */
3520 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3521 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3522 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3524 /* If the FPU is disabled, squash the registers. */
3525 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3526 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3527 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3528 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3530 /* If 32-bit, squash the 64-bit registers. */
3533 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3535 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3541 /* Save the current options */
3544 ix86_function_specific_save (struct cl_target_option *ptr)
3546 ptr->arch = ix86_arch;
3547 ptr->schedule = ix86_schedule;
3548 ptr->tune = ix86_tune;
3549 ptr->fpmath = ix86_fpmath;
3550 ptr->branch_cost = ix86_branch_cost;
3551 ptr->tune_defaulted = ix86_tune_defaulted;
3552 ptr->arch_specified = ix86_arch_specified;
3553 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3554 ptr->target_flags_explicit = target_flags_explicit;
3556 /* The fields are char but the variables are not; make sure the
3557 values fit in the fields. */
3558 gcc_assert (ptr->arch == ix86_arch);
3559 gcc_assert (ptr->schedule == ix86_schedule);
3560 gcc_assert (ptr->tune == ix86_tune);
3561 gcc_assert (ptr->fpmath == ix86_fpmath);
3562 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3565 /* Restore the current options */
3568 ix86_function_specific_restore (struct cl_target_option *ptr)
3570 enum processor_type old_tune = ix86_tune;
3571 enum processor_type old_arch = ix86_arch;
3572 unsigned int ix86_arch_mask, ix86_tune_mask;
3575 ix86_arch = (enum processor_type) ptr->arch;
3576 ix86_schedule = (enum attr_cpu) ptr->schedule;
3577 ix86_tune = (enum processor_type) ptr->tune;
3578 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3579 ix86_branch_cost = ptr->branch_cost;
3580 ix86_tune_defaulted = ptr->tune_defaulted;
3581 ix86_arch_specified = ptr->arch_specified;
3582 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3583 target_flags_explicit = ptr->target_flags_explicit;
3585 /* Recreate the arch feature tests if the arch changed */
3586 if (old_arch != ix86_arch)
3588 ix86_arch_mask = 1u << ix86_arch;
3589 for (i = 0; i < X86_ARCH_LAST; ++i)
3590 ix86_arch_features[i]
3591 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3594 /* Recreate the tune optimization tests */
3595 if (old_tune != ix86_tune)
3597 ix86_tune_mask = 1u << ix86_tune;
3598 for (i = 0; i < X86_TUNE_LAST; ++i)
3599 ix86_tune_features[i]
3600 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3604 /* Print the current options */
3607 ix86_function_specific_print (FILE *file, int indent,
3608 struct cl_target_option *ptr)
3611 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3612 NULL, NULL, NULL, false);
3614 fprintf (file, "%*sarch = %d (%s)\n",
3617 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3618 ? cpu_names[ptr->arch]
3621 fprintf (file, "%*stune = %d (%s)\n",
3624 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3625 ? cpu_names[ptr->tune]
3628 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3629 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3630 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3631 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3635 fprintf (file, "%*s%s\n", indent, "", target_string);
3636 free (target_string);
3641 /* Inner function to process the attribute((target(...))), take an argument and
3642 set the current options from the argument. If we have a list, recursively go
3646 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3651 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3652 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3653 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3654 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3669 enum ix86_opt_type type;
3674 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3675 IX86_ATTR_ISA ("abm", OPT_mabm),
3676 IX86_ATTR_ISA ("aes", OPT_maes),
3677 IX86_ATTR_ISA ("avx", OPT_mavx),
3678 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3679 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3680 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3681 IX86_ATTR_ISA ("sse", OPT_msse),
3682 IX86_ATTR_ISA ("sse2", OPT_msse2),
3683 IX86_ATTR_ISA ("sse3", OPT_msse3),
3684 IX86_ATTR_ISA ("sse4", OPT_msse4),
3685 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3686 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3687 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3688 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3689 IX86_ATTR_ISA ("fma4", OPT_mfma4),
3690 IX86_ATTR_ISA ("xop", OPT_mxop),
3691 IX86_ATTR_ISA ("lwp", OPT_mlwp),
3693 /* string options */
3694 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3695 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3696 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3699 IX86_ATTR_YES ("cld",
3703 IX86_ATTR_NO ("fancy-math-387",
3704 OPT_mfancy_math_387,
3705 MASK_NO_FANCY_MATH_387),
3707 IX86_ATTR_YES ("ieee-fp",
3711 IX86_ATTR_YES ("inline-all-stringops",
3712 OPT_minline_all_stringops,
3713 MASK_INLINE_ALL_STRINGOPS),
3715 IX86_ATTR_YES ("inline-stringops-dynamically",
3716 OPT_minline_stringops_dynamically,
3717 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3719 IX86_ATTR_NO ("align-stringops",
3720 OPT_mno_align_stringops,
3721 MASK_NO_ALIGN_STRINGOPS),
3723 IX86_ATTR_YES ("recip",
3729 /* If this is a list, recurse to get the options. */
3730 if (TREE_CODE (args) == TREE_LIST)
3734 for (; args; args = TREE_CHAIN (args))
3735 if (TREE_VALUE (args)
3736 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3742 else if (TREE_CODE (args) != STRING_CST)
3745 /* Handle multiple arguments separated by commas. */
3746 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3748 while (next_optstr && *next_optstr != '\0')
3750 char *p = next_optstr;
3752 char *comma = strchr (next_optstr, ',');
3753 const char *opt_string;
3754 size_t len, opt_len;
3759 enum ix86_opt_type type = ix86_opt_unknown;
3765 len = comma - next_optstr;
3766 next_optstr = comma + 1;
3774 /* Recognize no-xxx. */
3775 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3784 /* Find the option. */
3787 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3789 type = attrs[i].type;
3790 opt_len = attrs[i].len;
3791 if (ch == attrs[i].string[0]
3792 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3793 && memcmp (p, attrs[i].string, opt_len) == 0)
3796 mask = attrs[i].mask;
3797 opt_string = attrs[i].string;
3802 /* Process the option. */
3805 error ("attribute(target(\"%s\")) is unknown", orig_p);
3809 else if (type == ix86_opt_isa)
3810 ix86_handle_option (opt, p, opt_set_p);
3812 else if (type == ix86_opt_yes || type == ix86_opt_no)
3814 if (type == ix86_opt_no)
3815 opt_set_p = !opt_set_p;
3818 target_flags |= mask;
3820 target_flags &= ~mask;
3823 else if (type == ix86_opt_str)
3827 error ("option(\"%s\") was already specified", opt_string);
3831 p_strings[opt] = xstrdup (p + opt_len);
3841 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3844 ix86_valid_target_attribute_tree (tree args)
3846 const char *orig_arch_string = ix86_arch_string;
3847 const char *orig_tune_string = ix86_tune_string;
3848 const char *orig_fpmath_string = ix86_fpmath_string;
3849 int orig_tune_defaulted = ix86_tune_defaulted;
3850 int orig_arch_specified = ix86_arch_specified;
3851 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3854 struct cl_target_option *def
3855 = TREE_TARGET_OPTION (target_option_default_node);
3857 /* Process each of the options on the chain. */
3858 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3861 /* If the changed options are different from the default, rerun override_options,
3862 and then save the options away. The string options are are attribute options,
3863 and will be undone when we copy the save structure. */
3864 if (ix86_isa_flags != def->ix86_isa_flags
3865 || target_flags != def->target_flags
3866 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3867 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3868 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3870 /* If we are using the default tune= or arch=, undo the string assigned,
3871 and use the default. */
3872 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3873 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3874 else if (!orig_arch_specified)
3875 ix86_arch_string = NULL;
3877 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3878 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3879 else if (orig_tune_defaulted)
3880 ix86_tune_string = NULL;
3882 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3883 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3884 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3885 else if (!TARGET_64BIT && TARGET_SSE)
3886 ix86_fpmath_string = "sse,387";
3888 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3889 override_options (false);
3891 /* Add any builtin functions with the new isa if any. */
3892 ix86_add_new_builtins (ix86_isa_flags);
3894 /* Save the current options unless we are validating options for
3896 t = build_target_option_node ();
3898 ix86_arch_string = orig_arch_string;
3899 ix86_tune_string = orig_tune_string;
3900 ix86_fpmath_string = orig_fpmath_string;
3902 /* Free up memory allocated to hold the strings */
3903 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3904 if (option_strings[i])
3905 free (option_strings[i]);
3911 /* Hook to validate attribute((target("string"))). */
3914 ix86_valid_target_attribute_p (tree fndecl,
3915 tree ARG_UNUSED (name),
3917 int ARG_UNUSED (flags))
3919 struct cl_target_option cur_target;
3921 tree old_optimize = build_optimization_node ();
3922 tree new_target, new_optimize;
3923 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3925 /* If the function changed the optimization levels as well as setting target
3926 options, start with the optimizations specified. */
3927 if (func_optimize && func_optimize != old_optimize)
3928 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3930 /* The target attributes may also change some optimization flags, so update
3931 the optimization options if necessary. */
3932 cl_target_option_save (&cur_target);
3933 new_target = ix86_valid_target_attribute_tree (args);
3934 new_optimize = build_optimization_node ();
3941 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3943 if (old_optimize != new_optimize)
3944 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3947 cl_target_option_restore (&cur_target);
3949 if (old_optimize != new_optimize)
3950 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3956 /* Hook to determine if one function can safely inline another. */
3959 ix86_can_inline_p (tree caller, tree callee)
3962 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3963 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3965 /* If callee has no option attributes, then it is ok to inline. */
3969 /* If caller has no option attributes, but callee does then it is not ok to
3971 else if (!caller_tree)
3976 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3977 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3979 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3980 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3982 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3983 != callee_opts->ix86_isa_flags)
3986 /* See if we have the same non-isa options. */
3987 else if (caller_opts->target_flags != callee_opts->target_flags)
3990 /* See if arch, tune, etc. are the same. */
3991 else if (caller_opts->arch != callee_opts->arch)
3994 else if (caller_opts->tune != callee_opts->tune)
3997 else if (caller_opts->fpmath != callee_opts->fpmath)
4000 else if (caller_opts->branch_cost != callee_opts->branch_cost)
4011 /* Remember the last target of ix86_set_current_function. */
4012 static GTY(()) tree ix86_previous_fndecl;
4014 /* Establish appropriate back-end context for processing the function
4015 FNDECL. The argument might be NULL to indicate processing at top
4016 level, outside of any function scope. */
4018 ix86_set_current_function (tree fndecl)
4020 /* Only change the context if the function changes. This hook is called
4021 several times in the course of compiling a function, and we don't want to
4022 slow things down too much or call target_reinit when it isn't safe. */
4023 if (fndecl && fndecl != ix86_previous_fndecl)
4025 tree old_tree = (ix86_previous_fndecl
4026 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
4029 tree new_tree = (fndecl
4030 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
4033 ix86_previous_fndecl = fndecl;
4034 if (old_tree == new_tree)
4039 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
4045 struct cl_target_option *def
4046 = TREE_TARGET_OPTION (target_option_current_node);
4048 cl_target_option_restore (def);
4055 /* Return true if this goes in large data/bss. */
4058 ix86_in_large_data_p (tree exp)
4060 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
4063 /* Functions are never large data. */
4064 if (TREE_CODE (exp) == FUNCTION_DECL)
4067 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
4069 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
4070 if (strcmp (section, ".ldata") == 0
4071 || strcmp (section, ".lbss") == 0)
4077 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4079 /* If this is an incomplete type with size 0, then we can't put it
4080 in data because it might be too big when completed. */
4081 if (!size || size > ix86_section_threshold)
4088 /* Switch to the appropriate section for output of DECL.
4089 DECL is either a `VAR_DECL' node or a constant of some sort.
4090 RELOC indicates whether forming the initial value of DECL requires
4091 link-time relocations. */
4093 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4097 x86_64_elf_select_section (tree decl, int reloc,
4098 unsigned HOST_WIDE_INT align)
4100 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4101 && ix86_in_large_data_p (decl))
4103 const char *sname = NULL;
4104 unsigned int flags = SECTION_WRITE;
4105 switch (categorize_decl_for_section (decl, reloc))
4110 case SECCAT_DATA_REL:
4111 sname = ".ldata.rel";
4113 case SECCAT_DATA_REL_LOCAL:
4114 sname = ".ldata.rel.local";
4116 case SECCAT_DATA_REL_RO:
4117 sname = ".ldata.rel.ro";
4119 case SECCAT_DATA_REL_RO_LOCAL:
4120 sname = ".ldata.rel.ro.local";
4124 flags |= SECTION_BSS;
4127 case SECCAT_RODATA_MERGE_STR:
4128 case SECCAT_RODATA_MERGE_STR_INIT:
4129 case SECCAT_RODATA_MERGE_CONST:
4133 case SECCAT_SRODATA:
4140 /* We don't split these for medium model. Place them into
4141 default sections and hope for best. */
4143 case SECCAT_EMUTLS_VAR:
4144 case SECCAT_EMUTLS_TMPL:
4149 /* We might get called with string constants, but get_named_section
4150 doesn't like them as they are not DECLs. Also, we need to set
4151 flags in that case. */
4153 return get_section (sname, flags, NULL);
4154 return get_named_section (decl, sname, reloc);
4157 return default_elf_select_section (decl, reloc, align);
4160 /* Build up a unique section name, expressed as a
4161 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4162 RELOC indicates whether the initial value of EXP requires
4163 link-time relocations. */
4165 static void ATTRIBUTE_UNUSED
4166 x86_64_elf_unique_section (tree decl, int reloc)
4168 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4169 && ix86_in_large_data_p (decl))
4171 const char *prefix = NULL;
4172 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4173 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4175 switch (categorize_decl_for_section (decl, reloc))
4178 case SECCAT_DATA_REL:
4179 case SECCAT_DATA_REL_LOCAL:
4180 case SECCAT_DATA_REL_RO:
4181 case SECCAT_DATA_REL_RO_LOCAL:
4182 prefix = one_only ? ".ld" : ".ldata";
4185 prefix = one_only ? ".lb" : ".lbss";
4188 case SECCAT_RODATA_MERGE_STR:
4189 case SECCAT_RODATA_MERGE_STR_INIT:
4190 case SECCAT_RODATA_MERGE_CONST:
4191 prefix = one_only ? ".lr" : ".lrodata";
4193 case SECCAT_SRODATA:
4200 /* We don't split these for medium model. Place them into
4201 default sections and hope for best. */
4203 case SECCAT_EMUTLS_VAR:
4204 prefix = targetm.emutls.var_section;
4206 case SECCAT_EMUTLS_TMPL:
4207 prefix = targetm.emutls.tmpl_section;
4212 const char *name, *linkonce;
4215 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4216 name = targetm.strip_name_encoding (name);
4218 /* If we're using one_only, then there needs to be a .gnu.linkonce
4219 prefix to the section name. */
4220 linkonce = one_only ? ".gnu.linkonce" : "";
4222 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4224 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4228 default_unique_section (decl, reloc);
4231 #ifdef COMMON_ASM_OP
4232 /* This says how to output assembler code to declare an
4233 uninitialized external linkage data object.
4235 For medium model x86-64 we need to use .largecomm opcode for
4238 x86_elf_aligned_common (FILE *file,
4239 const char *name, unsigned HOST_WIDE_INT size,
4242 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4243 && size > (unsigned int)ix86_section_threshold)
4244 fputs (".largecomm\t", file);
4246 fputs (COMMON_ASM_OP, file);
4247 assemble_name (file, name);
4248 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4249 size, align / BITS_PER_UNIT);
4253 /* Utility function for targets to use in implementing
4254 ASM_OUTPUT_ALIGNED_BSS. */
4257 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4258 const char *name, unsigned HOST_WIDE_INT size,
4261 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4262 && size > (unsigned int)ix86_section_threshold)
4263 switch_to_section (get_named_section (decl, ".lbss", 0));
4265 switch_to_section (bss_section);
4266 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4267 #ifdef ASM_DECLARE_OBJECT_NAME
4268 last_assemble_variable_decl = decl;
4269 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4271 /* Standard thing is just output label for the object. */
4272 ASM_OUTPUT_LABEL (file, name);
4273 #endif /* ASM_DECLARE_OBJECT_NAME */
4274 ASM_OUTPUT_SKIP (file, size ? size : 1);
4278 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4280 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4281 make the problem with not enough registers even worse. */
4282 #ifdef INSN_SCHEDULING
4284 flag_schedule_insns = 0;
4288 /* The Darwin libraries never set errno, so we might as well
4289 avoid calling them when that's the only reason we would. */
4290 flag_errno_math = 0;
4292 /* The default values of these switches depend on the TARGET_64BIT
4293 that is not known at this moment. Mark these values with 2 and
4294 let user the to override these. In case there is no command line option
4295 specifying them, we will set the defaults in override_options. */
4297 flag_omit_frame_pointer = 2;
4298 flag_pcc_struct_return = 2;
4299 flag_asynchronous_unwind_tables = 2;
4300 flag_vect_cost_model = 1;
4301 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4302 SUBTARGET_OPTIMIZATION_OPTIONS;
4306 /* Decide whether we can make a sibling call to a function. DECL is the
4307 declaration of the function being targeted by the call and EXP is the
4308 CALL_EXPR representing the call. */
4311 ix86_function_ok_for_sibcall (tree decl, tree exp)
4313 tree type, decl_or_type;
4316 /* If we are generating position-independent code, we cannot sibcall
4317 optimize any indirect call, or a direct call to a global function,
4318 as the PLT requires %ebx be live. */
4319 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4322 /* If we need to align the outgoing stack, then sibcalling would
4323 unalign the stack, which may break the called function. */
4324 if (ix86_minimum_incoming_stack_boundary (true)
4325 < PREFERRED_STACK_BOUNDARY)
4330 decl_or_type = decl;
4331 type = TREE_TYPE (decl);
4335 /* We're looking at the CALL_EXPR, we need the type of the function. */
4336 type = CALL_EXPR_FN (exp); /* pointer expression */
4337 type = TREE_TYPE (type); /* pointer type */
4338 type = TREE_TYPE (type); /* function type */
4339 decl_or_type = type;
4342 /* Check that the return value locations are the same. Like
4343 if we are returning floats on the 80387 register stack, we cannot
4344 make a sibcall from a function that doesn't return a float to a
4345 function that does or, conversely, from a function that does return
4346 a float to a function that doesn't; the necessary stack adjustment
4347 would not be executed. This is also the place we notice
4348 differences in the return value ABI. Note that it is ok for one
4349 of the functions to have void return type as long as the return
4350 value of the other is passed in a register. */
4351 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4352 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4354 if (STACK_REG_P (a) || STACK_REG_P (b))
4356 if (!rtx_equal_p (a, b))
4359 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4361 else if (!rtx_equal_p (a, b))
4366 /* The SYSV ABI has more call-clobbered registers;
4367 disallow sibcalls from MS to SYSV. */
4368 if (cfun->machine->call_abi == MS_ABI
4369 && ix86_function_type_abi (type) == SYSV_ABI)
4374 /* If this call is indirect, we'll need to be able to use a
4375 call-clobbered register for the address of the target function.
4376 Make sure that all such registers are not used for passing
4377 parameters. Note that DLLIMPORT functions are indirect. */
4379 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4381 if (ix86_function_regparm (type, NULL) >= 3)
4383 /* ??? Need to count the actual number of registers to be used,
4384 not the possible number of registers. Fix later. */
4390 /* Otherwise okay. That also includes certain types of indirect calls. */
4394 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4395 calling convention attributes;
4396 arguments as in struct attribute_spec.handler. */
4399 ix86_handle_cconv_attribute (tree *node, tree name,
4401 int flags ATTRIBUTE_UNUSED,
4404 if (TREE_CODE (*node) != FUNCTION_TYPE
4405 && TREE_CODE (*node) != METHOD_TYPE
4406 && TREE_CODE (*node) != FIELD_DECL
4407 && TREE_CODE (*node) != TYPE_DECL)
4409 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4411 *no_add_attrs = true;
4415 /* Can combine regparm with all attributes but fastcall. */
4416 if (is_attribute_p ("regparm", name))
4420 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4422 error ("fastcall and regparm attributes are not compatible");
4425 cst = TREE_VALUE (args);
4426 if (TREE_CODE (cst) != INTEGER_CST)
4428 warning (OPT_Wattributes,
4429 "%qE attribute requires an integer constant argument",
4431 *no_add_attrs = true;
4433 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4435 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4437 *no_add_attrs = true;
4445 /* Do not warn when emulating the MS ABI. */
4446 if (TREE_CODE (*node) != FUNCTION_TYPE
4447 || ix86_function_type_abi (*node) != MS_ABI)
4448 warning (OPT_Wattributes, "%qE attribute ignored",
4450 *no_add_attrs = true;
4454 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4455 if (is_attribute_p ("fastcall", name))
4457 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4459 error ("fastcall and cdecl attributes are not compatible");
4461 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4463 error ("fastcall and stdcall attributes are not compatible");
4465 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4467 error ("fastcall and regparm attributes are not compatible");
4471 /* Can combine stdcall with fastcall (redundant), regparm and
4473 else if (is_attribute_p ("stdcall", name))
4475 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4477 error ("stdcall and cdecl attributes are not compatible");
4479 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4481 error ("stdcall and fastcall attributes are not compatible");
4485 /* Can combine cdecl with regparm and sseregparm. */
4486 else if (is_attribute_p ("cdecl", name))
4488 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4490 error ("stdcall and cdecl attributes are not compatible");
4492 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4494 error ("fastcall and cdecl attributes are not compatible");
4498 /* Can combine sseregparm with all attributes. */
4503 /* Return 0 if the attributes for two types are incompatible, 1 if they
4504 are compatible, and 2 if they are nearly compatible (which causes a
4505 warning to be generated). */
4508 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4510 /* Check for mismatch of non-default calling convention. */
4511 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4513 if (TREE_CODE (type1) != FUNCTION_TYPE
4514 && TREE_CODE (type1) != METHOD_TYPE)
4517 /* Check for mismatched fastcall/regparm types. */
4518 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4519 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4520 || (ix86_function_regparm (type1, NULL)
4521 != ix86_function_regparm (type2, NULL)))
4524 /* Check for mismatched sseregparm types. */
4525 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4526 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4529 /* Check for mismatched return types (cdecl vs stdcall). */
4530 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4531 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4537 /* Return the regparm value for a function with the indicated TYPE and DECL.
4538 DECL may be NULL when calling function indirectly
4539 or considering a libcall. */
4542 ix86_function_regparm (const_tree type, const_tree decl)
4548 return (ix86_function_type_abi (type) == SYSV_ABI
4549 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4551 regparm = ix86_regparm;
4552 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4555 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4559 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4562 /* Use register calling convention for local functions when possible. */
4564 && TREE_CODE (decl) == FUNCTION_DECL
4568 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4569 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE (decl));
4572 int local_regparm, globals = 0, regno;
4574 /* Make sure no regparm register is taken by a
4575 fixed register variable. */
4576 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4577 if (fixed_regs[local_regparm])
4580 /* We don't want to use regparm(3) for nested functions as
4581 these use a static chain pointer in the third argument. */
4582 if (local_regparm == 3 && DECL_STATIC_CHAIN (decl))
4585 /* Each fixed register usage increases register pressure,
4586 so less registers should be used for argument passing.
4587 This functionality can be overriden by an explicit
4589 for (regno = 0; regno <= DI_REG; regno++)
4590 if (fixed_regs[regno])
4594 = globals < local_regparm ? local_regparm - globals : 0;
4596 if (local_regparm > regparm)
4597 regparm = local_regparm;
4604 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4605 DFmode (2) arguments in SSE registers for a function with the
4606 indicated TYPE and DECL. DECL may be NULL when calling function
4607 indirectly or considering a libcall. Otherwise return 0. */
4610 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4612 gcc_assert (!TARGET_64BIT);
4614 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4615 by the sseregparm attribute. */
4616 if (TARGET_SSEREGPARM
4617 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4624 error ("Calling %qD with attribute sseregparm without "
4625 "SSE/SSE2 enabled", decl);
4627 error ("Calling %qT with attribute sseregparm without "
4628 "SSE/SSE2 enabled", type);
4636 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4637 (and DFmode for SSE2) arguments in SSE registers. */
4638 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4640 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4641 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4643 return TARGET_SSE2 ? 2 : 1;
4649 /* Return true if EAX is live at the start of the function. Used by
4650 ix86_expand_prologue to determine if we need special help before
4651 calling allocate_stack_worker. */
4654 ix86_eax_live_at_start_p (void)
4656 /* Cheat. Don't bother working forward from ix86_function_regparm
4657 to the function type to whether an actual argument is located in
4658 eax. Instead just look at cfg info, which is still close enough
4659 to correct at this point. This gives false positives for broken
4660 functions that might use uninitialized data that happens to be
4661 allocated in eax, but who cares? */
4662 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4665 /* Value is the number of bytes of arguments automatically
4666 popped when returning from a subroutine call.
4667 FUNDECL is the declaration node of the function (as a tree),
4668 FUNTYPE is the data type of the function (as a tree),
4669 or for a library call it is an identifier node for the subroutine name.
4670 SIZE is the number of bytes of arguments passed on the stack.
4672 On the 80386, the RTD insn may be used to pop them if the number
4673 of args is fixed, but if the number is variable then the caller
4674 must pop them all. RTD can't be used for library calls now
4675 because the library is compiled with the Unix compiler.
4676 Use of RTD is a selectable option, since it is incompatible with
4677 standard Unix calling sequences. If the option is not selected,
4678 the caller must always pop the args.
4680 The attribute stdcall is equivalent to RTD on a per module basis. */
4683 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4687 /* None of the 64-bit ABIs pop arguments. */
4691 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4693 /* Cdecl functions override -mrtd, and never pop the stack. */
4694 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4696 /* Stdcall and fastcall functions will pop the stack if not
4698 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4699 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4702 if (rtd && ! stdarg_p (funtype))
4706 /* Lose any fake structure return argument if it is passed on the stack. */
4707 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4708 && !KEEP_AGGREGATE_RETURN_POINTER)
4710 int nregs = ix86_function_regparm (funtype, fundecl);
4712 return GET_MODE_SIZE (Pmode);
4718 /* Argument support functions. */
4720 /* Return true when register may be used to pass function parameters. */
4722 ix86_function_arg_regno_p (int regno)
4725 const int *parm_regs;
4730 return (regno < REGPARM_MAX
4731 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4733 return (regno < REGPARM_MAX
4734 || (TARGET_MMX && MMX_REGNO_P (regno)
4735 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4736 || (TARGET_SSE && SSE_REGNO_P (regno)
4737 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4742 if (SSE_REGNO_P (regno) && TARGET_SSE)
4747 if (TARGET_SSE && SSE_REGNO_P (regno)
4748 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4752 /* TODO: The function should depend on current function ABI but
4753 builtins.c would need updating then. Therefore we use the
4756 /* RAX is used as hidden argument to va_arg functions. */
4757 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4760 if (ix86_abi == MS_ABI)
4761 parm_regs = x86_64_ms_abi_int_parameter_registers;
4763 parm_regs = x86_64_int_parameter_registers;
4764 for (i = 0; i < (ix86_abi == MS_ABI
4765 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4766 if (regno == parm_regs[i])
4771 /* Return if we do not know how to pass TYPE solely in registers. */
4774 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4776 if (must_pass_in_stack_var_size_or_pad (mode, type))
4779 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4780 The layout_type routine is crafty and tries to trick us into passing
4781 currently unsupported vector types on the stack by using TImode. */
4782 return (!TARGET_64BIT && mode == TImode
4783 && type && TREE_CODE (type) != VECTOR_TYPE);
4786 /* It returns the size, in bytes, of the area reserved for arguments passed
4787 in registers for the function represented by fndecl dependent to the used
4790 ix86_reg_parm_stack_space (const_tree fndecl)
4792 enum calling_abi call_abi = SYSV_ABI;
4793 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4794 call_abi = ix86_function_abi (fndecl);
4796 call_abi = ix86_function_type_abi (fndecl);
4797 if (call_abi == MS_ABI)
4802 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4805 ix86_function_type_abi (const_tree fntype)
4807 if (TARGET_64BIT && fntype != NULL)
4809 enum calling_abi abi = ix86_abi;
4810 if (abi == SYSV_ABI)
4812 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4815 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4823 ix86_function_ms_hook_prologue (const_tree fntype)
4827 if (lookup_attribute ("ms_hook_prologue", DECL_ATTRIBUTES (fntype)))
4829 if (decl_function_context (fntype) != NULL_TREE)
4831 error_at (DECL_SOURCE_LOCATION (fntype),
4832 "ms_hook_prologue is not compatible with nested function");
4841 static enum calling_abi
4842 ix86_function_abi (const_tree fndecl)
4846 return ix86_function_type_abi (TREE_TYPE (fndecl));
4849 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4852 ix86_cfun_abi (void)
4854 if (! cfun || ! TARGET_64BIT)
4856 return cfun->machine->call_abi;
4860 extern void init_regs (void);
4862 /* Implementation of call abi switching target hook. Specific to FNDECL
4863 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4864 for more details. */
4866 ix86_call_abi_override (const_tree fndecl)
4868 if (fndecl == NULL_TREE)
4869 cfun->machine->call_abi = ix86_abi;
4871 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4874 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4875 re-initialization of init_regs each time we switch function context since
4876 this is needed only during RTL expansion. */
4878 ix86_maybe_switch_abi (void)
4881 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4885 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4886 for a call to a function whose data type is FNTYPE.
4887 For a library call, FNTYPE is 0. */
4890 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4891 tree fntype, /* tree ptr for function decl */
4892 rtx libname, /* SYMBOL_REF of library name or 0 */
4895 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4896 memset (cum, 0, sizeof (*cum));
4899 cum->call_abi = ix86_function_abi (fndecl);
4901 cum->call_abi = ix86_function_type_abi (fntype);
4902 /* Set up the number of registers to use for passing arguments. */
4904 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4905 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4906 "or subtarget optimization implying it");
4907 cum->nregs = ix86_regparm;
4910 if (cum->call_abi != ix86_abi)
4911 cum->nregs = (ix86_abi != SYSV_ABI
4912 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4916 cum->sse_nregs = SSE_REGPARM_MAX;
4919 if (cum->call_abi != ix86_abi)
4920 cum->sse_nregs = (ix86_abi != SYSV_ABI
4921 ? X86_64_SSE_REGPARM_MAX
4922 : X86_64_MS_SSE_REGPARM_MAX);
4926 cum->mmx_nregs = MMX_REGPARM_MAX;
4927 cum->warn_avx = true;
4928 cum->warn_sse = true;
4929 cum->warn_mmx = true;
4931 /* Because type might mismatch in between caller and callee, we need to
4932 use actual type of function for local calls.
4933 FIXME: cgraph_analyze can be told to actually record if function uses
4934 va_start so for local functions maybe_vaarg can be made aggressive
4936 FIXME: once typesytem is fixed, we won't need this code anymore. */
4938 fntype = TREE_TYPE (fndecl);
4939 cum->maybe_vaarg = (fntype
4940 ? (!prototype_p (fntype) || stdarg_p (fntype))
4945 /* If there are variable arguments, then we won't pass anything
4946 in registers in 32-bit mode. */
4947 if (stdarg_p (fntype))
4958 /* Use ecx and edx registers if function has fastcall attribute,
4959 else look for regparm information. */
4962 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4968 cum->nregs = ix86_function_regparm (fntype, fndecl);
4971 /* Set up the number of SSE registers used for passing SFmode
4972 and DFmode arguments. Warn for mismatching ABI. */
4973 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4977 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4978 But in the case of vector types, it is some vector mode.
4980 When we have only some of our vector isa extensions enabled, then there
4981 are some modes for which vector_mode_supported_p is false. For these
4982 modes, the generic vector support in gcc will choose some non-vector mode
4983 in order to implement the type. By computing the natural mode, we'll
4984 select the proper ABI location for the operand and not depend on whatever
4985 the middle-end decides to do with these vector types.
4987 The midde-end can't deal with the vector types > 16 bytes. In this
4988 case, we return the original mode and warn ABI change if CUM isn't
4991 static enum machine_mode
4992 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4994 enum machine_mode mode = TYPE_MODE (type);
4996 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4998 HOST_WIDE_INT size = int_size_in_bytes (type);
4999 if ((size == 8 || size == 16 || size == 32)
5000 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5001 && TYPE_VECTOR_SUBPARTS (type) > 1)
5003 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
5005 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5006 mode = MIN_MODE_VECTOR_FLOAT;
5008 mode = MIN_MODE_VECTOR_INT;
5010 /* Get the mode which has this inner mode and number of units. */
5011 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
5012 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
5013 && GET_MODE_INNER (mode) == innermode)
5015 if (size == 32 && !TARGET_AVX)
5017 static bool warnedavx;
5024 warning (0, "AVX vector argument without AVX "
5025 "enabled changes the ABI");
5027 return TYPE_MODE (type);
5040 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5041 this may not agree with the mode that the type system has chosen for the
5042 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5043 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5046 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
5051 if (orig_mode != BLKmode)
5052 tmp = gen_rtx_REG (orig_mode, regno);
5055 tmp = gen_rtx_REG (mode, regno);
5056 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
5057 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
5063 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5064 of this code is to classify each 8bytes of incoming argument by the register
5065 class and assign registers accordingly. */
5067 /* Return the union class of CLASS1 and CLASS2.
5068 See the x86-64 PS ABI for details. */
5070 static enum x86_64_reg_class
5071 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
5073 /* Rule #1: If both classes are equal, this is the resulting class. */
5074 if (class1 == class2)
5077 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5079 if (class1 == X86_64_NO_CLASS)
5081 if (class2 == X86_64_NO_CLASS)
5084 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5085 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
5086 return X86_64_MEMORY_CLASS;
5088 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5089 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5090 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5091 return X86_64_INTEGERSI_CLASS;
5092 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5093 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5094 return X86_64_INTEGER_CLASS;
5096 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5098 if (class1 == X86_64_X87_CLASS
5099 || class1 == X86_64_X87UP_CLASS
5100 || class1 == X86_64_COMPLEX_X87_CLASS
5101 || class2 == X86_64_X87_CLASS
5102 || class2 == X86_64_X87UP_CLASS
5103 || class2 == X86_64_COMPLEX_X87_CLASS)
5104 return X86_64_MEMORY_CLASS;
5106 /* Rule #6: Otherwise class SSE is used. */
5107 return X86_64_SSE_CLASS;
5110 /* Classify the argument of type TYPE and mode MODE.
5111 CLASSES will be filled by the register class used to pass each word
5112 of the operand. The number of words is returned. In case the parameter
5113 should be passed in memory, 0 is returned. As a special case for zero
5114 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5116 BIT_OFFSET is used internally for handling records and specifies offset
5117 of the offset in bits modulo 256 to avoid overflow cases.
5119 See the x86-64 PS ABI for details.
5123 classify_argument (enum machine_mode mode, const_tree type,
5124 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5126 HOST_WIDE_INT bytes =
5127 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5128 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5130 /* Variable sized entities are always passed/returned in memory. */
5134 if (mode != VOIDmode
5135 && targetm.calls.must_pass_in_stack (mode, type))
5138 if (type && AGGREGATE_TYPE_P (type))
5142 enum x86_64_reg_class subclasses[MAX_CLASSES];
5144 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5148 for (i = 0; i < words; i++)
5149 classes[i] = X86_64_NO_CLASS;
5151 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5152 signalize memory class, so handle it as special case. */
5155 classes[0] = X86_64_NO_CLASS;
5159 /* Classify each field of record and merge classes. */
5160 switch (TREE_CODE (type))
5163 /* And now merge the fields of structure. */
5164 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5166 if (TREE_CODE (field) == FIELD_DECL)
5170 if (TREE_TYPE (field) == error_mark_node)
5173 /* Bitfields are always classified as integer. Handle them
5174 early, since later code would consider them to be
5175 misaligned integers. */
5176 if (DECL_BIT_FIELD (field))
5178 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5179 i < ((int_bit_position (field) + (bit_offset % 64))
5180 + tree_low_cst (DECL_SIZE (field), 0)
5183 merge_classes (X86_64_INTEGER_CLASS,
5190 type = TREE_TYPE (field);
5192 /* Flexible array member is ignored. */
5193 if (TYPE_MODE (type) == BLKmode
5194 && TREE_CODE (type) == ARRAY_TYPE
5195 && TYPE_SIZE (type) == NULL_TREE
5196 && TYPE_DOMAIN (type) != NULL_TREE
5197 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5202 if (!warned && warn_psabi)
5205 inform (input_location,
5206 "The ABI of passing struct with"
5207 " a flexible array member has"
5208 " changed in GCC 4.4");
5212 num = classify_argument (TYPE_MODE (type), type,
5214 (int_bit_position (field)
5215 + bit_offset) % 256);
5218 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5219 for (i = 0; i < num && (i + pos) < words; i++)
5221 merge_classes (subclasses[i], classes[i + pos]);
5228 /* Arrays are handled as small records. */
5231 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5232 TREE_TYPE (type), subclasses, bit_offset);
5236 /* The partial classes are now full classes. */
5237 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5238 subclasses[0] = X86_64_SSE_CLASS;
5239 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5240 && !((bit_offset % 64) == 0 && bytes == 4))
5241 subclasses[0] = X86_64_INTEGER_CLASS;
5243 for (i = 0; i < words; i++)
5244 classes[i] = subclasses[i % num];
5249 case QUAL_UNION_TYPE:
5250 /* Unions are similar to RECORD_TYPE but offset is always 0.
5252 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5254 if (TREE_CODE (field) == FIELD_DECL)
5258 if (TREE_TYPE (field) == error_mark_node)
5261 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5262 TREE_TYPE (field), subclasses,
5266 for (i = 0; i < num; i++)
5267 classes[i] = merge_classes (subclasses[i], classes[i]);
5278 /* When size > 16 bytes, if the first one isn't
5279 X86_64_SSE_CLASS or any other ones aren't
5280 X86_64_SSEUP_CLASS, everything should be passed in
5282 if (classes[0] != X86_64_SSE_CLASS)
5285 for (i = 1; i < words; i++)
5286 if (classes[i] != X86_64_SSEUP_CLASS)
5290 /* Final merger cleanup. */
5291 for (i = 0; i < words; i++)
5293 /* If one class is MEMORY, everything should be passed in
5295 if (classes[i] == X86_64_MEMORY_CLASS)
5298 /* The X86_64_SSEUP_CLASS should be always preceded by
5299 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5300 if (classes[i] == X86_64_SSEUP_CLASS
5301 && classes[i - 1] != X86_64_SSE_CLASS
5302 && classes[i - 1] != X86_64_SSEUP_CLASS)
5304 /* The first one should never be X86_64_SSEUP_CLASS. */
5305 gcc_assert (i != 0);
5306 classes[i] = X86_64_SSE_CLASS;
5309 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5310 everything should be passed in memory. */
5311 if (classes[i] == X86_64_X87UP_CLASS
5312 && (classes[i - 1] != X86_64_X87_CLASS))
5316 /* The first one should never be X86_64_X87UP_CLASS. */
5317 gcc_assert (i != 0);
5318 if (!warned && warn_psabi)
5321 inform (input_location,
5322 "The ABI of passing union with long double"
5323 " has changed in GCC 4.4");
5331 /* Compute alignment needed. We align all types to natural boundaries with
5332 exception of XFmode that is aligned to 64bits. */
5333 if (mode != VOIDmode && mode != BLKmode)
5335 int mode_alignment = GET_MODE_BITSIZE (mode);
5338 mode_alignment = 128;
5339 else if (mode == XCmode)
5340 mode_alignment = 256;
5341 if (COMPLEX_MODE_P (mode))
5342 mode_alignment /= 2;
5343 /* Misaligned fields are always returned in memory. */
5344 if (bit_offset % mode_alignment)
5348 /* for V1xx modes, just use the base mode */
5349 if (VECTOR_MODE_P (mode) && mode != V1DImode
5350 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5351 mode = GET_MODE_INNER (mode);
5353 /* Classification of atomic types. */
5358 classes[0] = X86_64_SSE_CLASS;
5361 classes[0] = X86_64_SSE_CLASS;
5362 classes[1] = X86_64_SSEUP_CLASS;
5372 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5376 classes[0] = X86_64_INTEGERSI_CLASS;
5379 else if (size <= 64)
5381 classes[0] = X86_64_INTEGER_CLASS;
5384 else if (size <= 64+32)
5386 classes[0] = X86_64_INTEGER_CLASS;
5387 classes[1] = X86_64_INTEGERSI_CLASS;
5390 else if (size <= 64+64)
5392 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5400 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5404 /* OImode shouldn't be used directly. */
5409 if (!(bit_offset % 64))
5410 classes[0] = X86_64_SSESF_CLASS;
5412 classes[0] = X86_64_SSE_CLASS;
5415 classes[0] = X86_64_SSEDF_CLASS;
5418 classes[0] = X86_64_X87_CLASS;
5419 classes[1] = X86_64_X87UP_CLASS;
5422 classes[0] = X86_64_SSE_CLASS;
5423 classes[1] = X86_64_SSEUP_CLASS;
5426 classes[0] = X86_64_SSE_CLASS;
5427 if (!(bit_offset % 64))
5433 if (!warned && warn_psabi)
5436 inform (input_location,
5437 "The ABI of passing structure with complex float"
5438 " member has changed in GCC 4.4");
5440 classes[1] = X86_64_SSESF_CLASS;
5444 classes[0] = X86_64_SSEDF_CLASS;
5445 classes[1] = X86_64_SSEDF_CLASS;
5448 classes[0] = X86_64_COMPLEX_X87_CLASS;
5451 /* This modes is larger than 16 bytes. */
5459 classes[0] = X86_64_SSE_CLASS;
5460 classes[1] = X86_64_SSEUP_CLASS;
5461 classes[2] = X86_64_SSEUP_CLASS;
5462 classes[3] = X86_64_SSEUP_CLASS;
5470 classes[0] = X86_64_SSE_CLASS;
5471 classes[1] = X86_64_SSEUP_CLASS;
5478 classes[0] = X86_64_SSE_CLASS;
5484 gcc_assert (VECTOR_MODE_P (mode));
5489 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5491 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5492 classes[0] = X86_64_INTEGERSI_CLASS;
5494 classes[0] = X86_64_INTEGER_CLASS;
5495 classes[1] = X86_64_INTEGER_CLASS;
5496 return 1 + (bytes > 8);
5500 /* Examine the argument and return set number of register required in each
5501 class. Return 0 iff parameter should be passed in memory. */
5503 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5504 int *int_nregs, int *sse_nregs)
5506 enum x86_64_reg_class regclass[MAX_CLASSES];
5507 int n = classify_argument (mode, type, regclass, 0);
5513 for (n--; n >= 0; n--)
5514 switch (regclass[n])
5516 case X86_64_INTEGER_CLASS:
5517 case X86_64_INTEGERSI_CLASS:
5520 case X86_64_SSE_CLASS:
5521 case X86_64_SSESF_CLASS:
5522 case X86_64_SSEDF_CLASS:
5525 case X86_64_NO_CLASS:
5526 case X86_64_SSEUP_CLASS:
5528 case X86_64_X87_CLASS:
5529 case X86_64_X87UP_CLASS:
5533 case X86_64_COMPLEX_X87_CLASS:
5534 return in_return ? 2 : 0;
5535 case X86_64_MEMORY_CLASS:
5541 /* Construct container for the argument used by GCC interface. See
5542 FUNCTION_ARG for the detailed description. */
5545 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5546 const_tree type, int in_return, int nintregs, int nsseregs,
5547 const int *intreg, int sse_regno)
5549 /* The following variables hold the static issued_error state. */
5550 static bool issued_sse_arg_error;
5551 static bool issued_sse_ret_error;
5552 static bool issued_x87_ret_error;
5554 enum machine_mode tmpmode;
5556 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5557 enum x86_64_reg_class regclass[MAX_CLASSES];
5561 int needed_sseregs, needed_intregs;
5562 rtx exp[MAX_CLASSES];
5565 n = classify_argument (mode, type, regclass, 0);
5568 if (!examine_argument (mode, type, in_return, &needed_intregs,
5571 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5574 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5575 some less clueful developer tries to use floating-point anyway. */
5576 if (needed_sseregs && !TARGET_SSE)
5580 if (!issued_sse_ret_error)
5582 error ("SSE register return with SSE disabled");
5583 issued_sse_ret_error = true;
5586 else if (!issued_sse_arg_error)
5588 error ("SSE register argument with SSE disabled");
5589 issued_sse_arg_error = true;
5594 /* Likewise, error if the ABI requires us to return values in the
5595 x87 registers and the user specified -mno-80387. */
5596 if (!TARGET_80387 && in_return)
5597 for (i = 0; i < n; i++)
5598 if (regclass[i] == X86_64_X87_CLASS
5599 || regclass[i] == X86_64_X87UP_CLASS
5600 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5602 if (!issued_x87_ret_error)
5604 error ("x87 register return with x87 disabled");
5605 issued_x87_ret_error = true;
5610 /* First construct simple cases. Avoid SCmode, since we want to use
5611 single register to pass this type. */
5612 if (n == 1 && mode != SCmode)
5613 switch (regclass[0])
5615 case X86_64_INTEGER_CLASS:
5616 case X86_64_INTEGERSI_CLASS:
5617 return gen_rtx_REG (mode, intreg[0]);
5618 case X86_64_SSE_CLASS:
5619 case X86_64_SSESF_CLASS:
5620 case X86_64_SSEDF_CLASS:
5621 if (mode != BLKmode)
5622 return gen_reg_or_parallel (mode, orig_mode,
5623 SSE_REGNO (sse_regno));
5625 case X86_64_X87_CLASS:
5626 case X86_64_COMPLEX_X87_CLASS:
5627 return gen_rtx_REG (mode, FIRST_STACK_REG);
5628 case X86_64_NO_CLASS:
5629 /* Zero sized array, struct or class. */
5634 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5635 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5636 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5638 && regclass[0] == X86_64_SSE_CLASS
5639 && regclass[1] == X86_64_SSEUP_CLASS
5640 && regclass[2] == X86_64_SSEUP_CLASS
5641 && regclass[3] == X86_64_SSEUP_CLASS
5643 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5646 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5647 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5648 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5649 && regclass[1] == X86_64_INTEGER_CLASS
5650 && (mode == CDImode || mode == TImode || mode == TFmode)
5651 && intreg[0] + 1 == intreg[1])
5652 return gen_rtx_REG (mode, intreg[0]);
5654 /* Otherwise figure out the entries of the PARALLEL. */
5655 for (i = 0; i < n; i++)
5659 switch (regclass[i])
5661 case X86_64_NO_CLASS:
5663 case X86_64_INTEGER_CLASS:
5664 case X86_64_INTEGERSI_CLASS:
5665 /* Merge TImodes on aligned occasions here too. */
5666 if (i * 8 + 8 > bytes)
5667 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5668 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5672 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5673 if (tmpmode == BLKmode)
5675 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5676 gen_rtx_REG (tmpmode, *intreg),
5680 case X86_64_SSESF_CLASS:
5681 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5682 gen_rtx_REG (SFmode,
5683 SSE_REGNO (sse_regno)),
5687 case X86_64_SSEDF_CLASS:
5688 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5689 gen_rtx_REG (DFmode,
5690 SSE_REGNO (sse_regno)),
5694 case X86_64_SSE_CLASS:
5702 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5712 && regclass[1] == X86_64_SSEUP_CLASS
5713 && regclass[2] == X86_64_SSEUP_CLASS
5714 && regclass[3] == X86_64_SSEUP_CLASS);
5721 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5722 gen_rtx_REG (tmpmode,
5723 SSE_REGNO (sse_regno)),
5732 /* Empty aligned struct, union or class. */
5736 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5737 for (i = 0; i < nexps; i++)
5738 XVECEXP (ret, 0, i) = exp [i];
5742 /* Update the data in CUM to advance over an argument of mode MODE
5743 and data type TYPE. (TYPE is null for libcalls where that information
5744 may not be available.) */
5747 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5748 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5764 cum->words += words;
5765 cum->nregs -= words;
5766 cum->regno += words;
5768 if (cum->nregs <= 0)
5776 /* OImode shouldn't be used directly. */
5780 if (cum->float_in_sse < 2)
5783 if (cum->float_in_sse < 1)
5800 if (!type || !AGGREGATE_TYPE_P (type))
5802 cum->sse_words += words;
5803 cum->sse_nregs -= 1;
5804 cum->sse_regno += 1;
5805 if (cum->sse_nregs <= 0)
5818 if (!type || !AGGREGATE_TYPE_P (type))
5820 cum->mmx_words += words;
5821 cum->mmx_nregs -= 1;
5822 cum->mmx_regno += 1;
5823 if (cum->mmx_nregs <= 0)
5834 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5835 tree type, HOST_WIDE_INT words, int named)
5837 int int_nregs, sse_nregs;
5839 /* Unnamed 256bit vector mode parameters are passed on stack. */
5840 if (!named && VALID_AVX256_REG_MODE (mode))
5843 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5844 cum->words += words;
5845 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5847 cum->nregs -= int_nregs;
5848 cum->sse_nregs -= sse_nregs;
5849 cum->regno += int_nregs;
5850 cum->sse_regno += sse_nregs;
5853 cum->words += words;
5857 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5858 HOST_WIDE_INT words)
5860 /* Otherwise, this should be passed indirect. */
5861 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5863 cum->words += words;
5872 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5873 tree type, int named)
5875 HOST_WIDE_INT bytes, words;
5877 if (mode == BLKmode)
5878 bytes = int_size_in_bytes (type);
5880 bytes = GET_MODE_SIZE (mode);
5881 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5884 mode = type_natural_mode (type, NULL);
5886 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5887 function_arg_advance_ms_64 (cum, bytes, words);
5888 else if (TARGET_64BIT)
5889 function_arg_advance_64 (cum, mode, type, words, named);
5891 function_arg_advance_32 (cum, mode, type, bytes, words);
5894 /* Define where to put the arguments to a function.
5895 Value is zero to push the argument on the stack,
5896 or a hard register in which to store the argument.
5898 MODE is the argument's machine mode.
5899 TYPE is the data type of the argument (as a tree).
5900 This is null for libcalls where that information may
5902 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5903 the preceding args and about the function being called.
5904 NAMED is nonzero if this argument is a named parameter
5905 (otherwise it is an extra parameter matching an ellipsis). */
5908 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5909 enum machine_mode orig_mode, tree type,
5910 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5912 static bool warnedsse, warnedmmx;
5914 /* Avoid the AL settings for the Unix64 ABI. */
5915 if (mode == VOIDmode)
5931 if (words <= cum->nregs)
5933 int regno = cum->regno;
5935 /* Fastcall allocates the first two DWORD (SImode) or
5936 smaller arguments to ECX and EDX if it isn't an
5942 || (type && AGGREGATE_TYPE_P (type)))
5945 /* ECX not EAX is the first allocated register. */
5946 if (regno == AX_REG)
5949 return gen_rtx_REG (mode, regno);
5954 if (cum->float_in_sse < 2)
5957 if (cum->float_in_sse < 1)
5961 /* In 32bit, we pass TImode in xmm registers. */
5968 if (!type || !AGGREGATE_TYPE_P (type))
5970 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5973 warning (0, "SSE vector argument without SSE enabled "
5977 return gen_reg_or_parallel (mode, orig_mode,
5978 cum->sse_regno + FIRST_SSE_REG);
5983 /* OImode shouldn't be used directly. */
5992 if (!type || !AGGREGATE_TYPE_P (type))
5995 return gen_reg_or_parallel (mode, orig_mode,
5996 cum->sse_regno + FIRST_SSE_REG);
6005 if (!type || !AGGREGATE_TYPE_P (type))
6007 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
6010 warning (0, "MMX vector argument without MMX enabled "
6014 return gen_reg_or_parallel (mode, orig_mode,
6015 cum->mmx_regno + FIRST_MMX_REG);
6024 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6025 enum machine_mode orig_mode, tree type, int named)
6027 /* Handle a hidden AL argument containing number of registers
6028 for varargs x86-64 functions. */
6029 if (mode == VOIDmode)
6030 return GEN_INT (cum->maybe_vaarg
6031 ? (cum->sse_nregs < 0
6032 ? (cum->call_abi == ix86_abi
6034 : (ix86_abi != SYSV_ABI
6035 ? X86_64_SSE_REGPARM_MAX
6036 : X86_64_MS_SSE_REGPARM_MAX))
6051 /* Unnamed 256bit vector mode parameters are passed on stack. */
6057 return construct_container (mode, orig_mode, type, 0, cum->nregs,
6059 &x86_64_int_parameter_registers [cum->regno],
6064 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6065 enum machine_mode orig_mode, int named,
6066 HOST_WIDE_INT bytes)
6070 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6071 We use value of -2 to specify that current function call is MSABI. */
6072 if (mode == VOIDmode)
6073 return GEN_INT (-2);
6075 /* If we've run out of registers, it goes on the stack. */
6076 if (cum->nregs == 0)
6079 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
6081 /* Only floating point modes are passed in anything but integer regs. */
6082 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
6085 regno = cum->regno + FIRST_SSE_REG;
6090 /* Unnamed floating parameters are passed in both the
6091 SSE and integer registers. */
6092 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6093 t2 = gen_rtx_REG (mode, regno);
6094 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6095 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6096 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6099 /* Handle aggregated types passed in register. */
6100 if (orig_mode == BLKmode)
6102 if (bytes > 0 && bytes <= 8)
6103 mode = (bytes > 4 ? DImode : SImode);
6104 if (mode == BLKmode)
6108 return gen_reg_or_parallel (mode, orig_mode, regno);
6112 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6113 tree type, int named)
6115 enum machine_mode mode = omode;
6116 HOST_WIDE_INT bytes, words;
6118 if (mode == BLKmode)
6119 bytes = int_size_in_bytes (type);
6121 bytes = GET_MODE_SIZE (mode);
6122 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6124 /* To simplify the code below, represent vector types with a vector mode
6125 even if MMX/SSE are not active. */
6126 if (type && TREE_CODE (type) == VECTOR_TYPE)
6127 mode = type_natural_mode (type, cum);
6129 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6130 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6131 else if (TARGET_64BIT)
6132 return function_arg_64 (cum, mode, omode, type, named);
6134 return function_arg_32 (cum, mode, omode, type, bytes, words);
6137 /* A C expression that indicates when an argument must be passed by
6138 reference. If nonzero for an argument, a copy of that argument is
6139 made in memory and a pointer to the argument is passed instead of
6140 the argument itself. The pointer is passed in whatever way is
6141 appropriate for passing a pointer to that type. */
6144 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6145 enum machine_mode mode ATTRIBUTE_UNUSED,
6146 const_tree type, bool named ATTRIBUTE_UNUSED)
6148 /* See Windows x64 Software Convention. */
6149 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6151 int msize = (int) GET_MODE_SIZE (mode);
6154 /* Arrays are passed by reference. */
6155 if (TREE_CODE (type) == ARRAY_TYPE)
6158 if (AGGREGATE_TYPE_P (type))
6160 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6161 are passed by reference. */
6162 msize = int_size_in_bytes (type);
6166 /* __m128 is passed by reference. */
6168 case 1: case 2: case 4: case 8:
6174 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6180 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6183 contains_aligned_value_p (tree type)
6185 enum machine_mode mode = TYPE_MODE (type);
6186 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6190 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6192 if (TYPE_ALIGN (type) < 128)
6195 if (AGGREGATE_TYPE_P (type))
6197 /* Walk the aggregates recursively. */
6198 switch (TREE_CODE (type))
6202 case QUAL_UNION_TYPE:
6206 /* Walk all the structure fields. */
6207 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6209 if (TREE_CODE (field) == FIELD_DECL
6210 && contains_aligned_value_p (TREE_TYPE (field)))
6217 /* Just for use if some languages passes arrays by value. */
6218 if (contains_aligned_value_p (TREE_TYPE (type)))
6229 /* Gives the alignment boundary, in bits, of an argument with the
6230 specified mode and type. */
6233 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6238 /* Since canonical type is used for call, we convert it to
6239 canonical type if needed. */
6240 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6241 type = TYPE_CANONICAL (type);
6242 align = TYPE_ALIGN (type);
6245 align = GET_MODE_ALIGNMENT (mode);
6246 if (align < PARM_BOUNDARY)
6247 align = PARM_BOUNDARY;
6248 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6249 natural boundaries. */
6250 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6252 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6253 make an exception for SSE modes since these require 128bit
6256 The handling here differs from field_alignment. ICC aligns MMX
6257 arguments to 4 byte boundaries, while structure fields are aligned
6258 to 8 byte boundaries. */
6261 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6262 align = PARM_BOUNDARY;
6266 if (!contains_aligned_value_p (type))
6267 align = PARM_BOUNDARY;
6270 if (align > BIGGEST_ALIGNMENT)
6271 align = BIGGEST_ALIGNMENT;
6275 /* Return true if N is a possible register number of function value. */
6278 ix86_function_value_regno_p (int regno)
6285 case FIRST_FLOAT_REG:
6286 /* TODO: The function should depend on current function ABI but
6287 builtins.c would need updating then. Therefore we use the
6289 if (TARGET_64BIT && ix86_abi == MS_ABI)
6291 return TARGET_FLOAT_RETURNS_IN_80387;
6297 if (TARGET_MACHO || TARGET_64BIT)
6305 /* Define how to find the value returned by a function.
6306 VALTYPE is the data type of the value (as a tree).
6307 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6308 otherwise, FUNC is 0. */
6311 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6312 const_tree fntype, const_tree fn)
6316 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6317 we normally prevent this case when mmx is not available. However
6318 some ABIs may require the result to be returned like DImode. */
6319 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6320 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6322 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6323 we prevent this case when sse is not available. However some ABIs
6324 may require the result to be returned like integer TImode. */
6325 else if (mode == TImode
6326 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6327 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6329 /* 32-byte vector modes in %ymm0. */
6330 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6331 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6333 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6334 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6335 regno = FIRST_FLOAT_REG;
6337 /* Most things go in %eax. */
6340 /* Override FP return register with %xmm0 for local functions when
6341 SSE math is enabled or for functions with sseregparm attribute. */
6342 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6344 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6345 if ((sse_level >= 1 && mode == SFmode)
6346 || (sse_level == 2 && mode == DFmode))
6347 regno = FIRST_SSE_REG;
6350 /* OImode shouldn't be used directly. */
6351 gcc_assert (mode != OImode);
6353 return gen_rtx_REG (orig_mode, regno);
6357 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6362 /* Handle libcalls, which don't provide a type node. */
6363 if (valtype == NULL)
6375 return gen_rtx_REG (mode, FIRST_SSE_REG);
6378 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6382 return gen_rtx_REG (mode, AX_REG);
6386 ret = construct_container (mode, orig_mode, valtype, 1,
6387 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6388 x86_64_int_return_registers, 0);
6390 /* For zero sized structures, construct_container returns NULL, but we
6391 need to keep rest of compiler happy by returning meaningful value. */
6393 ret = gen_rtx_REG (orig_mode, AX_REG);
6399 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6401 unsigned int regno = AX_REG;
6405 switch (GET_MODE_SIZE (mode))
6408 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6409 && !COMPLEX_MODE_P (mode))
6410 regno = FIRST_SSE_REG;
6414 if (mode == SFmode || mode == DFmode)
6415 regno = FIRST_SSE_REG;
6421 return gen_rtx_REG (orig_mode, regno);
6425 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6426 enum machine_mode orig_mode, enum machine_mode mode)
6428 const_tree fn, fntype;
6431 if (fntype_or_decl && DECL_P (fntype_or_decl))
6432 fn = fntype_or_decl;
6433 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6435 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6436 return function_value_ms_64 (orig_mode, mode);
6437 else if (TARGET_64BIT)
6438 return function_value_64 (orig_mode, mode, valtype);
6440 return function_value_32 (orig_mode, mode, fntype, fn);
6444 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6445 bool outgoing ATTRIBUTE_UNUSED)
6447 enum machine_mode mode, orig_mode;
6449 orig_mode = TYPE_MODE (valtype);
6450 mode = type_natural_mode (valtype, NULL);
6451 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6455 ix86_libcall_value (enum machine_mode mode)
6457 return ix86_function_value_1 (NULL, NULL, mode, mode);
6460 /* Return true iff type is returned in memory. */
6462 static int ATTRIBUTE_UNUSED
6463 return_in_memory_32 (const_tree type, enum machine_mode mode)
6467 if (mode == BLKmode)
6470 size = int_size_in_bytes (type);
6472 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6475 if (VECTOR_MODE_P (mode) || mode == TImode)
6477 /* User-created vectors small enough to fit in EAX. */
6481 /* MMX/3dNow values are returned in MM0,
6482 except when it doesn't exits. */
6484 return (TARGET_MMX ? 0 : 1);
6486 /* SSE values are returned in XMM0, except when it doesn't exist. */
6488 return (TARGET_SSE ? 0 : 1);
6490 /* AVX values are returned in YMM0, except when it doesn't exist. */
6492 return TARGET_AVX ? 0 : 1;
6501 /* OImode shouldn't be used directly. */
6502 gcc_assert (mode != OImode);
6507 static int ATTRIBUTE_UNUSED
6508 return_in_memory_64 (const_tree type, enum machine_mode mode)
6510 int needed_intregs, needed_sseregs;
6511 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6514 static int ATTRIBUTE_UNUSED
6515 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6517 HOST_WIDE_INT size = int_size_in_bytes (type);
6519 /* __m128 is returned in xmm0. */
6520 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6521 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6524 /* Otherwise, the size must be exactly in [1248]. */
6525 return (size != 1 && size != 2 && size != 4 && size != 8);
6529 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6531 #ifdef SUBTARGET_RETURN_IN_MEMORY
6532 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6534 const enum machine_mode mode = type_natural_mode (type, NULL);
6538 if (ix86_function_type_abi (fntype) == MS_ABI)
6539 return return_in_memory_ms_64 (type, mode);
6541 return return_in_memory_64 (type, mode);
6544 return return_in_memory_32 (type, mode);
6548 /* Return false iff TYPE is returned in memory. This version is used
6549 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6550 but differs notably in that when MMX is available, 8-byte vectors
6551 are returned in memory, rather than in MMX registers. */
6554 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6557 enum machine_mode mode = type_natural_mode (type, NULL);
6560 return return_in_memory_64 (type, mode);
6562 if (mode == BLKmode)
6565 size = int_size_in_bytes (type);
6567 if (VECTOR_MODE_P (mode))
6569 /* Return in memory only if MMX registers *are* available. This
6570 seems backwards, but it is consistent with the existing
6577 else if (mode == TImode)
6579 else if (mode == XFmode)
6585 /* When returning SSE vector types, we have a choice of either
6586 (1) being abi incompatible with a -march switch, or
6587 (2) generating an error.
6588 Given no good solution, I think the safest thing is one warning.
6589 The user won't be able to use -Werror, but....
6591 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6592 called in response to actually generating a caller or callee that
6593 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6594 via aggregate_value_p for general type probing from tree-ssa. */
6597 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6599 static bool warnedsse, warnedmmx;
6601 if (!TARGET_64BIT && type)
6603 /* Look at the return type of the function, not the function type. */
6604 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6606 if (!TARGET_SSE && !warnedsse)
6609 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6612 warning (0, "SSE vector return without SSE enabled "
6617 if (!TARGET_MMX && !warnedmmx)
6619 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6622 warning (0, "MMX vector return without MMX enabled "
6632 /* Create the va_list data type. */
6634 /* Returns the calling convention specific va_list date type.
6635 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6638 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6640 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6642 /* For i386 we use plain pointer to argument area. */
6643 if (!TARGET_64BIT || abi == MS_ABI)
6644 return build_pointer_type (char_type_node);
6646 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6647 type_decl = build_decl (BUILTINS_LOCATION,
6648 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6650 f_gpr = build_decl (BUILTINS_LOCATION,
6651 FIELD_DECL, get_identifier ("gp_offset"),
6652 unsigned_type_node);
6653 f_fpr = build_decl (BUILTINS_LOCATION,
6654 FIELD_DECL, get_identifier ("fp_offset"),
6655 unsigned_type_node);
6656 f_ovf = build_decl (BUILTINS_LOCATION,
6657 FIELD_DECL, get_identifier ("overflow_arg_area"),
6659 f_sav = build_decl (BUILTINS_LOCATION,
6660 FIELD_DECL, get_identifier ("reg_save_area"),
6663 va_list_gpr_counter_field = f_gpr;
6664 va_list_fpr_counter_field = f_fpr;
6666 DECL_FIELD_CONTEXT (f_gpr) = record;
6667 DECL_FIELD_CONTEXT (f_fpr) = record;
6668 DECL_FIELD_CONTEXT (f_ovf) = record;
6669 DECL_FIELD_CONTEXT (f_sav) = record;
6671 TREE_CHAIN (record) = type_decl;
6672 TYPE_NAME (record) = type_decl;
6673 TYPE_FIELDS (record) = f_gpr;
6674 TREE_CHAIN (f_gpr) = f_fpr;
6675 TREE_CHAIN (f_fpr) = f_ovf;
6676 TREE_CHAIN (f_ovf) = f_sav;
6678 layout_type (record);
6680 /* The correct type is an array type of one element. */
6681 return build_array_type (record, build_index_type (size_zero_node));
6684 /* Setup the builtin va_list data type and for 64-bit the additional
6685 calling convention specific va_list data types. */
6688 ix86_build_builtin_va_list (void)
6690 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6692 /* Initialize abi specific va_list builtin types. */
6696 if (ix86_abi == MS_ABI)
6698 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6699 if (TREE_CODE (t) != RECORD_TYPE)
6700 t = build_variant_type_copy (t);
6701 sysv_va_list_type_node = t;
6706 if (TREE_CODE (t) != RECORD_TYPE)
6707 t = build_variant_type_copy (t);
6708 sysv_va_list_type_node = t;
6710 if (ix86_abi != MS_ABI)
6712 t = ix86_build_builtin_va_list_abi (MS_ABI);
6713 if (TREE_CODE (t) != RECORD_TYPE)
6714 t = build_variant_type_copy (t);
6715 ms_va_list_type_node = t;
6720 if (TREE_CODE (t) != RECORD_TYPE)
6721 t = build_variant_type_copy (t);
6722 ms_va_list_type_node = t;
6729 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6732 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6741 int regparm = ix86_regparm;
6743 if (cum->call_abi != ix86_abi)
6744 regparm = (ix86_abi != SYSV_ABI
6745 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6747 /* GPR size of varargs save area. */
6748 if (cfun->va_list_gpr_size)
6749 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6751 ix86_varargs_gpr_size = 0;
6753 /* FPR size of varargs save area. We don't need it if we don't pass
6754 anything in SSE registers. */
6755 if (cum->sse_nregs && cfun->va_list_fpr_size)
6756 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6758 ix86_varargs_fpr_size = 0;
6760 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6763 save_area = frame_pointer_rtx;
6764 set = get_varargs_alias_set ();
6766 for (i = cum->regno;
6768 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6771 mem = gen_rtx_MEM (Pmode,
6772 plus_constant (save_area, i * UNITS_PER_WORD));
6773 MEM_NOTRAP_P (mem) = 1;
6774 set_mem_alias_set (mem, set);
6775 emit_move_insn (mem, gen_rtx_REG (Pmode,
6776 x86_64_int_parameter_registers[i]));
6779 if (ix86_varargs_fpr_size)
6781 /* Now emit code to save SSE registers. The AX parameter contains number
6782 of SSE parameter registers used to call this function. We use
6783 sse_prologue_save insn template that produces computed jump across
6784 SSE saves. We need some preparation work to get this working. */
6786 label = gen_label_rtx ();
6787 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6789 /* Compute address to jump to :
6790 label - eax*4 + nnamed_sse_arguments*4 Or
6791 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6792 tmp_reg = gen_reg_rtx (Pmode);
6793 nsse_reg = gen_reg_rtx (Pmode);
6794 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6795 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6796 gen_rtx_MULT (Pmode, nsse_reg,
6799 /* vmovaps is one byte longer than movaps. */
6801 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6802 gen_rtx_PLUS (Pmode, tmp_reg,
6808 gen_rtx_CONST (DImode,
6809 gen_rtx_PLUS (DImode,
6811 GEN_INT (cum->sse_regno
6812 * (TARGET_AVX ? 5 : 4)))));
6814 emit_move_insn (nsse_reg, label_ref);
6815 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6817 /* Compute address of memory block we save into. We always use pointer
6818 pointing 127 bytes after first byte to store - this is needed to keep
6819 instruction size limited by 4 bytes (5 bytes for AVX) with one
6820 byte displacement. */
6821 tmp_reg = gen_reg_rtx (Pmode);
6822 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6823 plus_constant (save_area,
6824 ix86_varargs_gpr_size + 127)));
6825 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6826 MEM_NOTRAP_P (mem) = 1;
6827 set_mem_alias_set (mem, set);
6828 set_mem_align (mem, BITS_PER_WORD);
6830 /* And finally do the dirty job! */
6831 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6832 GEN_INT (cum->sse_regno), label));
6837 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6839 alias_set_type set = get_varargs_alias_set ();
6842 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6846 mem = gen_rtx_MEM (Pmode,
6847 plus_constant (virtual_incoming_args_rtx,
6848 i * UNITS_PER_WORD));
6849 MEM_NOTRAP_P (mem) = 1;
6850 set_mem_alias_set (mem, set);
6852 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6853 emit_move_insn (mem, reg);
6858 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6859 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6862 CUMULATIVE_ARGS next_cum;
6865 /* This argument doesn't appear to be used anymore. Which is good,
6866 because the old code here didn't suppress rtl generation. */
6867 gcc_assert (!no_rtl);
6872 fntype = TREE_TYPE (current_function_decl);
6874 /* For varargs, we do not want to skip the dummy va_dcl argument.
6875 For stdargs, we do want to skip the last named argument. */
6877 if (stdarg_p (fntype))
6878 function_arg_advance (&next_cum, mode, type, 1);
6880 if (cum->call_abi == MS_ABI)
6881 setup_incoming_varargs_ms_64 (&next_cum);
6883 setup_incoming_varargs_64 (&next_cum);
6886 /* Checks if TYPE is of kind va_list char *. */
6889 is_va_list_char_pointer (tree type)
6893 /* For 32-bit it is always true. */
6896 canonic = ix86_canonical_va_list_type (type);
6897 return (canonic == ms_va_list_type_node
6898 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6901 /* Implement va_start. */
6904 ix86_va_start (tree valist, rtx nextarg)
6906 HOST_WIDE_INT words, n_gpr, n_fpr;
6907 tree f_gpr, f_fpr, f_ovf, f_sav;
6908 tree gpr, fpr, ovf, sav, t;
6911 /* Only 64bit target needs something special. */
6912 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6914 std_expand_builtin_va_start (valist, nextarg);
6918 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6919 f_fpr = TREE_CHAIN (f_gpr);
6920 f_ovf = TREE_CHAIN (f_fpr);
6921 f_sav = TREE_CHAIN (f_ovf);
6923 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6924 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6925 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6926 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6927 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6929 /* Count number of gp and fp argument registers used. */
6930 words = crtl->args.info.words;
6931 n_gpr = crtl->args.info.regno;
6932 n_fpr = crtl->args.info.sse_regno;
6934 if (cfun->va_list_gpr_size)
6936 type = TREE_TYPE (gpr);
6937 t = build2 (MODIFY_EXPR, type,
6938 gpr, build_int_cst (type, n_gpr * 8));
6939 TREE_SIDE_EFFECTS (t) = 1;
6940 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6943 if (TARGET_SSE && cfun->va_list_fpr_size)
6945 type = TREE_TYPE (fpr);
6946 t = build2 (MODIFY_EXPR, type, fpr,
6947 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6948 TREE_SIDE_EFFECTS (t) = 1;
6949 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6952 /* Find the overflow area. */
6953 type = TREE_TYPE (ovf);
6954 t = make_tree (type, crtl->args.internal_arg_pointer);
6956 t = build2 (POINTER_PLUS_EXPR, type, t,
6957 size_int (words * UNITS_PER_WORD));
6958 t = build2 (MODIFY_EXPR, type, ovf, t);
6959 TREE_SIDE_EFFECTS (t) = 1;
6960 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6962 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6964 /* Find the register save area.
6965 Prologue of the function save it right above stack frame. */
6966 type = TREE_TYPE (sav);
6967 t = make_tree (type, frame_pointer_rtx);
6968 if (!ix86_varargs_gpr_size)
6969 t = build2 (POINTER_PLUS_EXPR, type, t,
6970 size_int (-8 * X86_64_REGPARM_MAX));
6971 t = build2 (MODIFY_EXPR, type, sav, t);
6972 TREE_SIDE_EFFECTS (t) = 1;
6973 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6977 /* Implement va_arg. */
6980 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6983 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6984 tree f_gpr, f_fpr, f_ovf, f_sav;
6985 tree gpr, fpr, ovf, sav, t;
6987 tree lab_false, lab_over = NULL_TREE;
6992 enum machine_mode nat_mode;
6995 /* Only 64bit target needs something special. */
6996 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6997 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6999 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
7000 f_fpr = TREE_CHAIN (f_gpr);
7001 f_ovf = TREE_CHAIN (f_fpr);
7002 f_sav = TREE_CHAIN (f_ovf);
7004 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
7005 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
7006 valist = build_va_arg_indirect_ref (valist);
7007 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
7008 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
7009 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
7011 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
7013 type = build_pointer_type (type);
7014 size = int_size_in_bytes (type);
7015 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7017 nat_mode = type_natural_mode (type, NULL);
7026 /* Unnamed 256bit vector mode parameters are passed on stack. */
7027 if (ix86_cfun_abi () == SYSV_ABI)
7034 container = construct_container (nat_mode, TYPE_MODE (type),
7035 type, 0, X86_64_REGPARM_MAX,
7036 X86_64_SSE_REGPARM_MAX, intreg,
7041 /* Pull the value out of the saved registers. */
7043 addr = create_tmp_var (ptr_type_node, "addr");
7047 int needed_intregs, needed_sseregs;
7049 tree int_addr, sse_addr;
7051 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7052 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7054 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
7056 need_temp = (!REG_P (container)
7057 && ((needed_intregs && TYPE_ALIGN (type) > 64)
7058 || TYPE_ALIGN (type) > 128));
7060 /* In case we are passing structure, verify that it is consecutive block
7061 on the register save area. If not we need to do moves. */
7062 if (!need_temp && !REG_P (container))
7064 /* Verify that all registers are strictly consecutive */
7065 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
7069 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7071 rtx slot = XVECEXP (container, 0, i);
7072 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
7073 || INTVAL (XEXP (slot, 1)) != i * 16)
7081 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7083 rtx slot = XVECEXP (container, 0, i);
7084 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
7085 || INTVAL (XEXP (slot, 1)) != i * 8)
7097 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7098 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7101 /* First ensure that we fit completely in registers. */
7104 t = build_int_cst (TREE_TYPE (gpr),
7105 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7106 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7107 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7108 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7109 gimplify_and_add (t, pre_p);
7113 t = build_int_cst (TREE_TYPE (fpr),
7114 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7115 + X86_64_REGPARM_MAX * 8);
7116 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7117 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7118 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7119 gimplify_and_add (t, pre_p);
7122 /* Compute index to start of area used for integer regs. */
7125 /* int_addr = gpr + sav; */
7126 t = fold_convert (sizetype, gpr);
7127 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7128 gimplify_assign (int_addr, t, pre_p);
7132 /* sse_addr = fpr + sav; */
7133 t = fold_convert (sizetype, fpr);
7134 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7135 gimplify_assign (sse_addr, t, pre_p);
7140 tree temp = create_tmp_var (type, "va_arg_tmp");
7143 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7144 gimplify_assign (addr, t, pre_p);
7146 for (i = 0; i < XVECLEN (container, 0); i++)
7148 rtx slot = XVECEXP (container, 0, i);
7149 rtx reg = XEXP (slot, 0);
7150 enum machine_mode mode = GET_MODE (reg);
7151 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7152 tree addr_type = build_pointer_type (piece_type);
7153 tree daddr_type = build_pointer_type_for_mode (piece_type,
7157 tree dest_addr, dest;
7159 if (SSE_REGNO_P (REGNO (reg)))
7161 src_addr = sse_addr;
7162 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7166 src_addr = int_addr;
7167 src_offset = REGNO (reg) * 8;
7169 src_addr = fold_convert (addr_type, src_addr);
7170 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7171 size_int (src_offset));
7172 src = build_va_arg_indirect_ref (src_addr);
7174 dest_addr = fold_convert (daddr_type, addr);
7175 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7176 size_int (INTVAL (XEXP (slot, 1))));
7177 dest = build_va_arg_indirect_ref (dest_addr);
7179 gimplify_assign (dest, src, pre_p);
7185 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7186 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7187 gimplify_assign (gpr, t, pre_p);
7192 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7193 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7194 gimplify_assign (fpr, t, pre_p);
7197 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7199 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7202 /* ... otherwise out of the overflow area. */
7204 /* When we align parameter on stack for caller, if the parameter
7205 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7206 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7207 here with caller. */
7208 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7209 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7210 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7212 /* Care for on-stack alignment if needed. */
7213 if (arg_boundary <= 64
7214 || integer_zerop (TYPE_SIZE (type)))
7218 HOST_WIDE_INT align = arg_boundary / 8;
7219 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7220 size_int (align - 1));
7221 t = fold_convert (sizetype, t);
7222 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7224 t = fold_convert (TREE_TYPE (ovf), t);
7226 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7227 gimplify_assign (addr, t, pre_p);
7229 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7230 size_int (rsize * UNITS_PER_WORD));
7231 gimplify_assign (unshare_expr (ovf), t, pre_p);
7234 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7236 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7237 addr = fold_convert (ptrtype, addr);
7240 addr = build_va_arg_indirect_ref (addr);
7241 return build_va_arg_indirect_ref (addr);
7244 /* Return nonzero if OPNUM's MEM should be matched
7245 in movabs* patterns. */
7248 ix86_check_movabs (rtx insn, int opnum)
7252 set = PATTERN (insn);
7253 if (GET_CODE (set) == PARALLEL)
7254 set = XVECEXP (set, 0, 0);
7255 gcc_assert (GET_CODE (set) == SET);
7256 mem = XEXP (set, opnum);
7257 while (GET_CODE (mem) == SUBREG)
7258 mem = SUBREG_REG (mem);
7259 gcc_assert (MEM_P (mem));
7260 return (volatile_ok || !MEM_VOLATILE_P (mem));
7263 /* Initialize the table of extra 80387 mathematical constants. */
7266 init_ext_80387_constants (void)
7268 static const char * cst[5] =
7270 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7271 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7272 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7273 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7274 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7278 for (i = 0; i < 5; i++)
7280 real_from_string (&ext_80387_constants_table[i], cst[i]);
7281 /* Ensure each constant is rounded to XFmode precision. */
7282 real_convert (&ext_80387_constants_table[i],
7283 XFmode, &ext_80387_constants_table[i]);
7286 ext_80387_constants_init = 1;
7289 /* Return true if the constant is something that can be loaded with
7290 a special instruction. */
7293 standard_80387_constant_p (rtx x)
7295 enum machine_mode mode = GET_MODE (x);
7299 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7302 if (x == CONST0_RTX (mode))
7304 if (x == CONST1_RTX (mode))
7307 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7309 /* For XFmode constants, try to find a special 80387 instruction when
7310 optimizing for size or on those CPUs that benefit from them. */
7312 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7316 if (! ext_80387_constants_init)
7317 init_ext_80387_constants ();
7319 for (i = 0; i < 5; i++)
7320 if (real_identical (&r, &ext_80387_constants_table[i]))
7324 /* Load of the constant -0.0 or -1.0 will be split as
7325 fldz;fchs or fld1;fchs sequence. */
7326 if (real_isnegzero (&r))
7328 if (real_identical (&r, &dconstm1))
7334 /* Return the opcode of the special instruction to be used to load
7338 standard_80387_constant_opcode (rtx x)
7340 switch (standard_80387_constant_p (x))
7364 /* Return the CONST_DOUBLE representing the 80387 constant that is
7365 loaded by the specified special instruction. The argument IDX
7366 matches the return value from standard_80387_constant_p. */
7369 standard_80387_constant_rtx (int idx)
7373 if (! ext_80387_constants_init)
7374 init_ext_80387_constants ();
7390 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7394 /* Return 1 if X is all 0s and 2 if x is all 1s
7395 in supported SSE vector mode. */
7398 standard_sse_constant_p (rtx x)
7400 enum machine_mode mode = GET_MODE (x);
7402 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7404 if (vector_all_ones_operand (x, mode))
7420 /* Return the opcode of the special instruction to be used to load
7424 standard_sse_constant_opcode (rtx insn, rtx x)
7426 switch (standard_sse_constant_p (x))
7429 switch (get_attr_mode (insn))
7432 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7434 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7436 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7438 return "vxorps\t%x0, %x0, %x0";
7440 return "vxorpd\t%x0, %x0, %x0";
7442 return "vpxor\t%x0, %x0, %x0";
7447 return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
7454 /* Returns 1 if OP contains a symbol reference */
7457 symbolic_reference_mentioned_p (rtx op)
7462 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7465 fmt = GET_RTX_FORMAT (GET_CODE (op));
7466 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7472 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7473 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7477 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7484 /* Return 1 if it is appropriate to emit `ret' instructions in the
7485 body of a function. Do this only if the epilogue is simple, needing a
7486 couple of insns. Prior to reloading, we can't tell how many registers
7487 must be saved, so return 0 then. Return 0 if there is no frame
7488 marker to de-allocate. */
7491 ix86_can_use_return_insn_p (void)
7493 struct ix86_frame frame;
7495 if (! reload_completed || frame_pointer_needed)
7498 /* Don't allow more than 32 pop, since that's all we can do
7499 with one instruction. */
7500 if (crtl->args.pops_args
7501 && crtl->args.size >= 32768)
7504 ix86_compute_frame_layout (&frame);
7505 return frame.to_allocate == 0 && frame.padding0 == 0
7506 && (frame.nregs + frame.nsseregs) == 0;
7509 /* Value should be nonzero if functions must have frame pointers.
7510 Zero means the frame pointer need not be set up (and parms may
7511 be accessed via the stack pointer) in functions that seem suitable. */
7514 ix86_frame_pointer_required (void)
7516 /* If we accessed previous frames, then the generated code expects
7517 to be able to access the saved ebp value in our frame. */
7518 if (cfun->machine->accesses_prev_frame)
7521 /* Several x86 os'es need a frame pointer for other reasons,
7522 usually pertaining to setjmp. */
7523 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7526 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7527 the frame pointer by default. Turn it back on now if we've not
7528 got a leaf function. */
7529 if (TARGET_OMIT_LEAF_FRAME_POINTER
7530 && (!current_function_is_leaf
7531 || ix86_current_function_calls_tls_descriptor))
7540 /* Record that the current function accesses previous call frames. */
7543 ix86_setup_frame_addresses (void)
7545 cfun->machine->accesses_prev_frame = 1;
7548 #ifndef USE_HIDDEN_LINKONCE
7549 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7550 # define USE_HIDDEN_LINKONCE 1
7552 # define USE_HIDDEN_LINKONCE 0
7556 static int pic_labels_used;
7558 /* Fills in the label name that should be used for a pc thunk for
7559 the given register. */
7562 get_pc_thunk_name (char name[32], unsigned int regno)
7564 gcc_assert (!TARGET_64BIT);
7566 if (USE_HIDDEN_LINKONCE)
7567 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7569 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7573 /* This function generates code for -fpic that loads %ebx with
7574 the return address of the caller and then returns. */
7577 ix86_file_end (void)
7582 for (regno = 0; regno < 8; ++regno)
7586 if (! ((pic_labels_used >> regno) & 1))
7589 get_pc_thunk_name (name, regno);
7594 switch_to_section (darwin_sections[text_coal_section]);
7595 fputs ("\t.weak_definition\t", asm_out_file);
7596 assemble_name (asm_out_file, name);
7597 fputs ("\n\t.private_extern\t", asm_out_file);
7598 assemble_name (asm_out_file, name);
7599 fputs ("\n", asm_out_file);
7600 ASM_OUTPUT_LABEL (asm_out_file, name);
7604 if (USE_HIDDEN_LINKONCE)
7608 decl = build_decl (BUILTINS_LOCATION,
7609 FUNCTION_DECL, get_identifier (name),
7611 TREE_PUBLIC (decl) = 1;
7612 TREE_STATIC (decl) = 1;
7613 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7615 (*targetm.asm_out.unique_section) (decl, 0);
7616 switch_to_section (get_named_section (decl, NULL, 0));
7618 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7619 fputs ("\t.hidden\t", asm_out_file);
7620 assemble_name (asm_out_file, name);
7621 putc ('\n', asm_out_file);
7622 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7626 switch_to_section (text_section);
7627 ASM_OUTPUT_LABEL (asm_out_file, name);
7630 xops[0] = gen_rtx_REG (Pmode, regno);
7631 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7632 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7633 output_asm_insn ("ret", xops);
7636 if (NEED_INDICATE_EXEC_STACK)
7637 file_end_indicate_exec_stack ();
7640 /* Emit code for the SET_GOT patterns. */
7643 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7649 if (TARGET_VXWORKS_RTP && flag_pic)
7651 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7652 xops[2] = gen_rtx_MEM (Pmode,
7653 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7654 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7656 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7657 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7658 an unadorned address. */
7659 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7660 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7661 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7665 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7667 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7669 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7672 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7674 output_asm_insn ("call\t%a2", xops);
7677 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7678 is what will be referenced by the Mach-O PIC subsystem. */
7680 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7683 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7684 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7687 output_asm_insn ("pop%z0\t%0", xops);
7692 get_pc_thunk_name (name, REGNO (dest));
7693 pic_labels_used |= 1 << REGNO (dest);
7695 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7696 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7697 output_asm_insn ("call\t%X2", xops);
7698 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7699 is what will be referenced by the Mach-O PIC subsystem. */
7702 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7704 targetm.asm_out.internal_label (asm_out_file, "L",
7705 CODE_LABEL_NUMBER (label));
7712 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7713 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7715 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7720 /* Generate an "push" pattern for input ARG. */
7725 if (ix86_cfa_state->reg == stack_pointer_rtx)
7726 ix86_cfa_state->offset += UNITS_PER_WORD;
7728 return gen_rtx_SET (VOIDmode,
7730 gen_rtx_PRE_DEC (Pmode,
7731 stack_pointer_rtx)),
7735 /* Return >= 0 if there is an unused call-clobbered register available
7736 for the entire function. */
7739 ix86_select_alt_pic_regnum (void)
7741 if (current_function_is_leaf && !crtl->profile
7742 && !ix86_current_function_calls_tls_descriptor)
7745 /* Can't use the same register for both PIC and DRAP. */
7747 drap = REGNO (crtl->drap_reg);
7750 for (i = 2; i >= 0; --i)
7751 if (i != drap && !df_regs_ever_live_p (i))
7755 return INVALID_REGNUM;
7758 /* Return 1 if we need to save REGNO. */
7760 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7762 if (pic_offset_table_rtx
7763 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7764 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7766 || crtl->calls_eh_return
7767 || crtl->uses_const_pool))
7769 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7774 if (crtl->calls_eh_return && maybe_eh_return)
7779 unsigned test = EH_RETURN_DATA_REGNO (i);
7780 if (test == INVALID_REGNUM)
7787 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7790 return (df_regs_ever_live_p (regno)
7791 && !call_used_regs[regno]
7792 && !fixed_regs[regno]
7793 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7796 /* Return number of saved general prupose registers. */
7799 ix86_nsaved_regs (void)
7804 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7805 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7810 /* Return number of saved SSE registrers. */
7813 ix86_nsaved_sseregs (void)
7818 if (ix86_cfun_abi () != MS_ABI)
7820 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7821 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7826 /* Given FROM and TO register numbers, say whether this elimination is
7827 allowed. If stack alignment is needed, we can only replace argument
7828 pointer with hard frame pointer, or replace frame pointer with stack
7829 pointer. Otherwise, frame pointer elimination is automatically
7830 handled and all other eliminations are valid. */
7833 ix86_can_eliminate (const int from, const int to)
7835 if (stack_realign_fp)
7836 return ((from == ARG_POINTER_REGNUM
7837 && to == HARD_FRAME_POINTER_REGNUM)
7838 || (from == FRAME_POINTER_REGNUM
7839 && to == STACK_POINTER_REGNUM));
7841 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
7844 /* Return the offset between two registers, one to be eliminated, and the other
7845 its replacement, at the start of a routine. */
7848 ix86_initial_elimination_offset (int from, int to)
7850 struct ix86_frame frame;
7851 ix86_compute_frame_layout (&frame);
7853 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7854 return frame.hard_frame_pointer_offset;
7855 else if (from == FRAME_POINTER_REGNUM
7856 && to == HARD_FRAME_POINTER_REGNUM)
7857 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7860 gcc_assert (to == STACK_POINTER_REGNUM);
7862 if (from == ARG_POINTER_REGNUM)
7863 return frame.stack_pointer_offset;
7865 gcc_assert (from == FRAME_POINTER_REGNUM);
7866 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7870 /* In a dynamically-aligned function, we can't know the offset from
7871 stack pointer to frame pointer, so we must ensure that setjmp
7872 eliminates fp against the hard fp (%ebp) rather than trying to
7873 index from %esp up to the top of the frame across a gap that is
7874 of unknown (at compile-time) size. */
7876 ix86_builtin_setjmp_frame_value (void)
7878 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7881 /* Fill structure ix86_frame about frame of currently computed function. */
7884 ix86_compute_frame_layout (struct ix86_frame *frame)
7886 unsigned int stack_alignment_needed;
7887 HOST_WIDE_INT offset;
7888 unsigned int preferred_alignment;
7889 HOST_WIDE_INT size = get_frame_size ();
7891 frame->nregs = ix86_nsaved_regs ();
7892 frame->nsseregs = ix86_nsaved_sseregs ();
7894 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7895 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7897 /* MS ABI seem to require stack alignment to be always 16 except for function
7899 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7901 preferred_alignment = 16;
7902 stack_alignment_needed = 16;
7903 crtl->preferred_stack_boundary = 128;
7904 crtl->stack_alignment_needed = 128;
7907 gcc_assert (!size || stack_alignment_needed);
7908 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7909 gcc_assert (preferred_alignment <= stack_alignment_needed);
7911 /* During reload iteration the amount of registers saved can change.
7912 Recompute the value as needed. Do not recompute when amount of registers
7913 didn't change as reload does multiple calls to the function and does not
7914 expect the decision to change within single iteration. */
7915 if (!optimize_function_for_size_p (cfun)
7916 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7918 int count = frame->nregs;
7920 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7921 /* The fast prologue uses move instead of push to save registers. This
7922 is significantly longer, but also executes faster as modern hardware
7923 can execute the moves in parallel, but can't do that for push/pop.
7925 Be careful about choosing what prologue to emit: When function takes
7926 many instructions to execute we may use slow version as well as in
7927 case function is known to be outside hot spot (this is known with
7928 feedback only). Weight the size of function by number of registers
7929 to save as it is cheap to use one or two push instructions but very
7930 slow to use many of them. */
7932 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7933 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7934 || (flag_branch_probabilities
7935 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7936 cfun->machine->use_fast_prologue_epilogue = false;
7938 cfun->machine->use_fast_prologue_epilogue
7939 = !expensive_function_p (count);
7941 if (TARGET_PROLOGUE_USING_MOVE
7942 && cfun->machine->use_fast_prologue_epilogue)
7943 frame->save_regs_using_mov = true;
7945 frame->save_regs_using_mov = false;
7947 /* Skip return address. */
7948 offset = UNITS_PER_WORD;
7950 /* Skip pushed static chain. */
7951 if (ix86_static_chain_on_stack)
7952 offset += UNITS_PER_WORD;
7954 /* Skip saved base pointer. */
7955 if (frame_pointer_needed)
7956 offset += UNITS_PER_WORD;
7958 frame->hard_frame_pointer_offset = offset;
7960 /* Set offset to aligned because the realigned frame starts from
7962 if (stack_realign_fp)
7963 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7965 /* Register save area */
7966 offset += frame->nregs * UNITS_PER_WORD;
7968 /* Align SSE reg save area. */
7969 if (frame->nsseregs)
7970 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7972 frame->padding0 = 0;
7974 /* SSE register save area. */
7975 offset += frame->padding0 + frame->nsseregs * 16;
7978 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7979 offset += frame->va_arg_size;
7981 /* Align start of frame for local function. */
7982 frame->padding1 = ((offset + stack_alignment_needed - 1)
7983 & -stack_alignment_needed) - offset;
7985 offset += frame->padding1;
7987 /* Frame pointer points here. */
7988 frame->frame_pointer_offset = offset;
7992 /* Add outgoing arguments area. Can be skipped if we eliminated
7993 all the function calls as dead code.
7994 Skipping is however impossible when function calls alloca. Alloca
7995 expander assumes that last crtl->outgoing_args_size
7996 of stack frame are unused. */
7997 if (ACCUMULATE_OUTGOING_ARGS
7998 && (!current_function_is_leaf || cfun->calls_alloca
7999 || ix86_current_function_calls_tls_descriptor))
8001 offset += crtl->outgoing_args_size;
8002 frame->outgoing_arguments_size = crtl->outgoing_args_size;
8005 frame->outgoing_arguments_size = 0;
8007 /* Align stack boundary. Only needed if we're calling another function
8009 if (!current_function_is_leaf || cfun->calls_alloca
8010 || ix86_current_function_calls_tls_descriptor)
8011 frame->padding2 = ((offset + preferred_alignment - 1)
8012 & -preferred_alignment) - offset;
8014 frame->padding2 = 0;
8016 offset += frame->padding2;
8018 /* We've reached end of stack frame. */
8019 frame->stack_pointer_offset = offset;
8021 /* Size prologue needs to allocate. */
8022 frame->to_allocate =
8023 (size + frame->padding1 + frame->padding2
8024 + frame->outgoing_arguments_size + frame->va_arg_size);
8026 if ((!frame->to_allocate && frame->nregs <= 1)
8027 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
8028 frame->save_regs_using_mov = false;
8030 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8031 && current_function_sp_is_unchanging
8032 && current_function_is_leaf
8033 && !ix86_current_function_calls_tls_descriptor)
8035 frame->red_zone_size = frame->to_allocate;
8036 if (frame->save_regs_using_mov)
8037 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
8038 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
8039 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
8042 frame->red_zone_size = 0;
8043 frame->to_allocate -= frame->red_zone_size;
8044 frame->stack_pointer_offset -= frame->red_zone_size;
8047 /* Emit code to save registers in the prologue. */
8050 ix86_emit_save_regs (void)
8055 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
8056 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8058 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
8059 RTX_FRAME_RELATED_P (insn) = 1;
8063 /* Emit code to save registers using MOV insns. First register
8064 is restored from POINTER + OFFSET. */
8066 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8071 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8072 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8074 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
8076 gen_rtx_REG (Pmode, regno));
8077 RTX_FRAME_RELATED_P (insn) = 1;
8078 offset += UNITS_PER_WORD;
8082 /* Emit code to save registers using MOV insns. First register
8083 is restored from POINTER + OFFSET. */
8085 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8091 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8092 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8094 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8095 set_mem_align (mem, 128);
8096 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8097 RTX_FRAME_RELATED_P (insn) = 1;
8102 static GTY(()) rtx queued_cfa_restores;
8104 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8105 manipulation insn. Don't add it if the previously
8106 saved value will be left untouched within stack red-zone till return,
8107 as unwinders can find the same value in the register and
8111 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8114 && !TARGET_64BIT_MS_ABI
8115 && red_offset + RED_ZONE_SIZE >= 0
8116 && crtl->args.pops_args < 65536)
8121 add_reg_note (insn, REG_CFA_RESTORE, reg);
8122 RTX_FRAME_RELATED_P (insn) = 1;
8126 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8129 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8132 ix86_add_queued_cfa_restore_notes (rtx insn)
8135 if (!queued_cfa_restores)
8137 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8139 XEXP (last, 1) = REG_NOTES (insn);
8140 REG_NOTES (insn) = queued_cfa_restores;
8141 queued_cfa_restores = NULL_RTX;
8142 RTX_FRAME_RELATED_P (insn) = 1;
8145 /* Expand prologue or epilogue stack adjustment.
8146 The pattern exist to put a dependency on all ebp-based memory accesses.
8147 STYLE should be negative if instructions should be marked as frame related,
8148 zero if %r11 register is live and cannot be freely used and positive
8152 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8153 int style, bool set_cfa)
8158 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8159 else if (x86_64_immediate_operand (offset, DImode))
8160 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8164 /* r11 is used by indirect sibcall return as well, set before the
8165 epilogue and used after the epilogue. ATM indirect sibcall
8166 shouldn't be used together with huge frame sizes in one
8167 function because of the frame_size check in sibcall.c. */
8169 r11 = gen_rtx_REG (DImode, R11_REG);
8170 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8172 RTX_FRAME_RELATED_P (insn) = 1;
8173 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8178 ix86_add_queued_cfa_restore_notes (insn);
8184 gcc_assert (ix86_cfa_state->reg == src);
8185 ix86_cfa_state->offset += INTVAL (offset);
8186 ix86_cfa_state->reg = dest;
8188 r = gen_rtx_PLUS (Pmode, src, offset);
8189 r = gen_rtx_SET (VOIDmode, dest, r);
8190 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8191 RTX_FRAME_RELATED_P (insn) = 1;
8194 RTX_FRAME_RELATED_P (insn) = 1;
8197 /* Find an available register to be used as dynamic realign argument
8198 pointer regsiter. Such a register will be written in prologue and
8199 used in begin of body, so it must not be
8200 1. parameter passing register.
8202 We reuse static-chain register if it is available. Otherwise, we
8203 use DI for i386 and R13 for x86-64. We chose R13 since it has
8206 Return: the regno of chosen register. */
8209 find_drap_reg (void)
8211 tree decl = cfun->decl;
8215 /* Use R13 for nested function or function need static chain.
8216 Since function with tail call may use any caller-saved
8217 registers in epilogue, DRAP must not use caller-saved
8218 register in such case. */
8219 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8226 /* Use DI for nested function or function need static chain.
8227 Since function with tail call may use any caller-saved
8228 registers in epilogue, DRAP must not use caller-saved
8229 register in such case. */
8230 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8233 /* Reuse static chain register if it isn't used for parameter
8235 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8236 && !lookup_attribute ("fastcall",
8237 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8244 /* Return minimum incoming stack alignment. */
8247 ix86_minimum_incoming_stack_boundary (bool sibcall)
8249 unsigned int incoming_stack_boundary;
8251 /* Prefer the one specified at command line. */
8252 if (ix86_user_incoming_stack_boundary)
8253 incoming_stack_boundary = ix86_user_incoming_stack_boundary;
8254 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
8255 if -mstackrealign is used, it isn't used for sibcall check and
8256 estimated stack alignment is 128bit. */
8259 && ix86_force_align_arg_pointer
8260 && crtl->stack_alignment_estimated == 128)
8261 incoming_stack_boundary = MIN_STACK_BOUNDARY;
8263 incoming_stack_boundary = ix86_default_incoming_stack_boundary;
8265 /* Incoming stack alignment can be changed on individual functions
8266 via force_align_arg_pointer attribute. We use the smallest
8267 incoming stack boundary. */
8268 if (incoming_stack_boundary > MIN_STACK_BOUNDARY
8269 && lookup_attribute (ix86_force_align_arg_pointer_string,
8270 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8271 incoming_stack_boundary = MIN_STACK_BOUNDARY;
8273 /* The incoming stack frame has to be aligned at least at
8274 parm_stack_boundary. */
8275 if (incoming_stack_boundary < crtl->parm_stack_boundary)
8276 incoming_stack_boundary = crtl->parm_stack_boundary;
8278 /* Stack at entrance of main is aligned by runtime. We use the
8279 smallest incoming stack boundary. */
8280 if (incoming_stack_boundary > MAIN_STACK_BOUNDARY
8281 && DECL_NAME (current_function_decl)
8282 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8283 && DECL_FILE_SCOPE_P (current_function_decl))
8284 incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8286 return incoming_stack_boundary;
8289 /* Update incoming stack boundary and estimated stack alignment. */
8292 ix86_update_stack_boundary (void)
8294 ix86_incoming_stack_boundary
8295 = ix86_minimum_incoming_stack_boundary (false);
8297 /* x86_64 vararg needs 16byte stack alignment for register save
8301 && crtl->stack_alignment_estimated < 128)
8302 crtl->stack_alignment_estimated = 128;
8305 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8306 needed or an rtx for DRAP otherwise. */
8309 ix86_get_drap_rtx (void)
8311 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8312 crtl->need_drap = true;
8314 if (stack_realign_drap)
8316 /* Assign DRAP to vDRAP and returns vDRAP */
8317 unsigned int regno = find_drap_reg ();
8322 arg_ptr = gen_rtx_REG (Pmode, regno);
8323 crtl->drap_reg = arg_ptr;
8326 drap_vreg = copy_to_reg (arg_ptr);
8330 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8331 RTX_FRAME_RELATED_P (insn) = 1;
8338 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8341 ix86_internal_arg_pointer (void)
8343 return virtual_incoming_args_rtx;
8346 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8347 to be generated in correct form. */
8349 ix86_finalize_stack_realign_flags (void)
8351 /* Check if stack realign is really needed after reload, and
8352 stores result in cfun */
8353 unsigned int incoming_stack_boundary
8354 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8355 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8356 unsigned int stack_realign = (incoming_stack_boundary
8357 < (current_function_is_leaf
8358 ? crtl->max_used_stack_slot_alignment
8359 : crtl->stack_alignment_needed));
8361 if (crtl->stack_realign_finalized)
8363 /* After stack_realign_needed is finalized, we can't no longer
8365 gcc_assert (crtl->stack_realign_needed == stack_realign);
8369 crtl->stack_realign_needed = stack_realign;
8370 crtl->stack_realign_finalized = true;
8374 /* Expand the prologue into a bunch of separate insns. */
8377 ix86_expand_prologue (void)
8381 struct ix86_frame frame;
8382 HOST_WIDE_INT allocate;
8383 int gen_frame_pointer = frame_pointer_needed;
8385 ix86_finalize_stack_realign_flags ();
8387 /* DRAP should not coexist with stack_realign_fp */
8388 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8390 /* Initialize CFA state for before the prologue. */
8391 ix86_cfa_state->reg = stack_pointer_rtx;
8392 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8394 ix86_compute_frame_layout (&frame);
8396 if (ix86_function_ms_hook_prologue (current_function_decl))
8400 /* Make sure the function starts with
8401 8b ff movl.s %edi,%edi
8403 8b ec movl.s %esp,%ebp
8405 This matches the hookable function prologue in Win32 API
8406 functions in Microsoft Windows XP Service Pack 2 and newer.
8407 Wine uses this to enable Windows apps to hook the Win32 API
8408 functions provided by Wine. */
8409 insn = emit_insn (gen_vswapmov (gen_rtx_REG (SImode, DI_REG),
8410 gen_rtx_REG (SImode, DI_REG)));
8411 push = emit_insn (gen_push (hard_frame_pointer_rtx));
8412 mov = emit_insn (gen_vswapmov (hard_frame_pointer_rtx,
8413 stack_pointer_rtx));
8415 if (frame_pointer_needed && !(crtl->drap_reg
8416 && crtl->stack_realign_needed))
8418 /* The push %ebp and movl.s %esp, %ebp already set up
8419 the frame pointer. No need to do this again. */
8420 gen_frame_pointer = 0;
8421 RTX_FRAME_RELATED_P (push) = 1;
8422 RTX_FRAME_RELATED_P (mov) = 1;
8423 if (ix86_cfa_state->reg == stack_pointer_rtx)
8424 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8427 /* If the frame pointer is not needed, pop %ebp again. This
8428 could be optimized for cases where ebp needs to be backed up
8429 for some other reason. If stack realignment is needed, pop
8430 the base pointer again, align the stack, and later regenerate
8431 the frame pointer setup. The frame pointer generated by the
8432 hook prologue is not aligned, so it can't be used. */
8433 insn = emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8436 /* The first insn of a function that accepts its static chain on the
8437 stack is to push the register that would be filled in by a direct
8438 call. This insn will be skipped by the trampoline. */
8439 if (ix86_static_chain_on_stack)
8443 insn = emit_insn (gen_push (ix86_static_chain (cfun->decl, false)));
8444 emit_insn (gen_blockage ());
8446 /* We don't want to interpret this push insn as a register save,
8447 only as a stack adjustment. The real copy of the register as
8448 a save will be done later, if needed. */
8449 t = plus_constant (stack_pointer_rtx, -UNITS_PER_WORD);
8450 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8451 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8452 RTX_FRAME_RELATED_P (insn) = 1;
8455 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8456 of DRAP is needed and stack realignment is really needed after reload */
8457 if (crtl->drap_reg && crtl->stack_realign_needed)
8460 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8461 int param_ptr_offset = UNITS_PER_WORD;
8463 if (ix86_static_chain_on_stack)
8464 param_ptr_offset += UNITS_PER_WORD;
8465 if (!call_used_regs[REGNO (crtl->drap_reg)])
8466 param_ptr_offset += UNITS_PER_WORD;
8468 gcc_assert (stack_realign_drap);
8470 /* Grab the argument pointer. */
8471 x = plus_constant (stack_pointer_rtx, param_ptr_offset);
8474 /* Only need to push parameter pointer reg if it is caller
8476 if (!call_used_regs[REGNO (crtl->drap_reg)])
8478 /* Push arg pointer reg */
8479 insn = emit_insn (gen_push (y));
8480 RTX_FRAME_RELATED_P (insn) = 1;
8483 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8484 RTX_FRAME_RELATED_P (insn) = 1;
8485 ix86_cfa_state->reg = crtl->drap_reg;
8487 /* Align the stack. */
8488 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8490 GEN_INT (-align_bytes)));
8491 RTX_FRAME_RELATED_P (insn) = 1;
8493 /* Replicate the return address on the stack so that return
8494 address can be reached via (argp - 1) slot. This is needed
8495 to implement macro RETURN_ADDR_RTX and intrinsic function
8496 expand_builtin_return_addr etc. */
8498 x = gen_frame_mem (Pmode,
8499 plus_constant (x, -UNITS_PER_WORD));
8500 insn = emit_insn (gen_push (x));
8501 RTX_FRAME_RELATED_P (insn) = 1;
8504 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8505 slower on all targets. Also sdb doesn't like it. */
8507 if (gen_frame_pointer)
8509 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8510 RTX_FRAME_RELATED_P (insn) = 1;
8512 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8513 RTX_FRAME_RELATED_P (insn) = 1;
8515 if (ix86_cfa_state->reg == stack_pointer_rtx)
8516 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8519 if (stack_realign_fp)
8521 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8522 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8524 /* Align the stack. */
8525 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8527 GEN_INT (-align_bytes)));
8528 RTX_FRAME_RELATED_P (insn) = 1;
8531 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8533 if (!frame.save_regs_using_mov)
8534 ix86_emit_save_regs ();
8536 allocate += frame.nregs * UNITS_PER_WORD;
8538 /* When using red zone we may start register saving before allocating
8539 the stack frame saving one cycle of the prologue. However I will
8540 avoid doing this if I am going to have to probe the stack since
8541 at least on x86_64 the stack probe can turn into a call that clobbers
8542 a red zone location */
8543 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8544 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8545 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8546 && !crtl->stack_realign_needed)
8547 ? hard_frame_pointer_rtx
8548 : stack_pointer_rtx,
8549 -frame.nregs * UNITS_PER_WORD);
8553 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8554 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8555 GEN_INT (-allocate), -1,
8556 ix86_cfa_state->reg == stack_pointer_rtx);
8559 /* Only valid for Win32. */
8560 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8564 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8566 if (cfun->machine->call_abi == MS_ABI)
8569 eax_live = ix86_eax_live_at_start_p ();
8573 emit_insn (gen_push (eax));
8574 allocate -= UNITS_PER_WORD;
8577 emit_move_insn (eax, GEN_INT (allocate));
8580 insn = gen_allocate_stack_worker_64 (eax, eax);
8582 insn = gen_allocate_stack_worker_32 (eax, eax);
8583 insn = emit_insn (insn);
8585 if (ix86_cfa_state->reg == stack_pointer_rtx)
8587 ix86_cfa_state->offset += allocate;
8588 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8589 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8590 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8591 RTX_FRAME_RELATED_P (insn) = 1;
8596 if (frame_pointer_needed)
8597 t = plus_constant (hard_frame_pointer_rtx,
8600 - frame.nregs * UNITS_PER_WORD);
8602 t = plus_constant (stack_pointer_rtx, allocate);
8603 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8607 if (frame.save_regs_using_mov
8608 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8609 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8611 if (!frame_pointer_needed
8612 || !(frame.to_allocate + frame.padding0)
8613 || crtl->stack_realign_needed)
8614 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8616 + frame.nsseregs * 16 + frame.padding0);
8618 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8619 -frame.nregs * UNITS_PER_WORD);
8621 if (!frame_pointer_needed
8622 || !(frame.to_allocate + frame.padding0)
8623 || crtl->stack_realign_needed)
8624 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8627 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8628 - frame.nregs * UNITS_PER_WORD
8629 - frame.nsseregs * 16
8632 pic_reg_used = false;
8633 if (pic_offset_table_rtx
8634 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8637 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8639 if (alt_pic_reg_used != INVALID_REGNUM)
8640 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8642 pic_reg_used = true;
8649 if (ix86_cmodel == CM_LARGE_PIC)
8651 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8652 rtx label = gen_label_rtx ();
8654 LABEL_PRESERVE_P (label) = 1;
8655 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8656 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8657 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8658 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8659 pic_offset_table_rtx, tmp_reg));
8662 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8665 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8668 /* In the pic_reg_used case, make sure that the got load isn't deleted
8669 when mcount needs it. Blockage to avoid call movement across mcount
8670 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8672 if (crtl->profile && pic_reg_used)
8673 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8675 if (crtl->drap_reg && !crtl->stack_realign_needed)
8677 /* vDRAP is setup but after reload it turns out stack realign
8678 isn't necessary, here we will emit prologue to setup DRAP
8679 without stack realign adjustment */
8681 int drap_bp_offset = UNITS_PER_WORD * 2;
8683 if (ix86_static_chain_on_stack)
8684 drap_bp_offset += UNITS_PER_WORD;
8685 x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8686 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8689 /* Prevent instructions from being scheduled into register save push
8690 sequence when access to the redzone area is done through frame pointer.
8691 The offset between the frame pointer and the stack pointer is calculated
8692 relative to the value of the stack pointer at the end of the function
8693 prologue, and moving instructions that access redzone area via frame
8694 pointer inside push sequence violates this assumption. */
8695 if (frame_pointer_needed && frame.red_zone_size)
8696 emit_insn (gen_memory_blockage ());
8698 /* Emit cld instruction if stringops are used in the function. */
8699 if (TARGET_CLD && ix86_current_function_needs_cld)
8700 emit_insn (gen_cld ());
8703 /* Emit code to restore REG using a POP insn. */
8706 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8708 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8710 if (ix86_cfa_state->reg == crtl->drap_reg
8711 && REGNO (reg) == REGNO (crtl->drap_reg))
8713 /* Previously we'd represented the CFA as an expression
8714 like *(%ebp - 8). We've just popped that value from
8715 the stack, which means we need to reset the CFA to
8716 the drap register. This will remain until we restore
8717 the stack pointer. */
8718 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8719 RTX_FRAME_RELATED_P (insn) = 1;
8723 if (ix86_cfa_state->reg == stack_pointer_rtx)
8725 ix86_cfa_state->offset -= UNITS_PER_WORD;
8726 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8727 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8728 RTX_FRAME_RELATED_P (insn) = 1;
8731 /* When the frame pointer is the CFA, and we pop it, we are
8732 swapping back to the stack pointer as the CFA. This happens
8733 for stack frames that don't allocate other data, so we assume
8734 the stack pointer is now pointing at the return address, i.e.
8735 the function entry state, which makes the offset be 1 word. */
8736 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8737 && reg == hard_frame_pointer_rtx)
8739 ix86_cfa_state->reg = stack_pointer_rtx;
8740 ix86_cfa_state->offset -= UNITS_PER_WORD;
8742 add_reg_note (insn, REG_CFA_DEF_CFA,
8743 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8744 GEN_INT (ix86_cfa_state->offset)));
8745 RTX_FRAME_RELATED_P (insn) = 1;
8748 ix86_add_cfa_restore_note (insn, reg, red_offset);
8751 /* Emit code to restore saved registers using POP insns. */
8754 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8758 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8759 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8761 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8763 red_offset += UNITS_PER_WORD;
8767 /* Emit code and notes for the LEAVE instruction. */
8770 ix86_emit_leave (HOST_WIDE_INT red_offset)
8772 rtx insn = emit_insn (ix86_gen_leave ());
8774 ix86_add_queued_cfa_restore_notes (insn);
8776 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8778 ix86_cfa_state->reg = stack_pointer_rtx;
8779 ix86_cfa_state->offset -= UNITS_PER_WORD;
8781 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8782 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8783 RTX_FRAME_RELATED_P (insn) = 1;
8784 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8788 /* Emit code to restore saved registers using MOV insns. First register
8789 is restored from POINTER + OFFSET. */
8791 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8792 HOST_WIDE_INT red_offset,
8793 int maybe_eh_return)
8796 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8799 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8800 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8802 rtx reg = gen_rtx_REG (Pmode, regno);
8804 /* Ensure that adjust_address won't be forced to produce pointer
8805 out of range allowed by x86-64 instruction set. */
8806 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8810 r11 = gen_rtx_REG (DImode, R11_REG);
8811 emit_move_insn (r11, GEN_INT (offset));
8812 emit_insn (gen_adddi3 (r11, r11, pointer));
8813 base_address = gen_rtx_MEM (Pmode, r11);
8816 insn = emit_move_insn (reg,
8817 adjust_address (base_address, Pmode, offset));
8818 offset += UNITS_PER_WORD;
8820 if (ix86_cfa_state->reg == crtl->drap_reg
8821 && regno == REGNO (crtl->drap_reg))
8823 /* Previously we'd represented the CFA as an expression
8824 like *(%ebp - 8). We've just popped that value from
8825 the stack, which means we need to reset the CFA to
8826 the drap register. This will remain until we restore
8827 the stack pointer. */
8828 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8829 RTX_FRAME_RELATED_P (insn) = 1;
8832 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8834 red_offset += UNITS_PER_WORD;
8838 /* Emit code to restore saved registers using MOV insns. First register
8839 is restored from POINTER + OFFSET. */
8841 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8842 HOST_WIDE_INT red_offset,
8843 int maybe_eh_return)
8846 rtx base_address = gen_rtx_MEM (TImode, pointer);
8849 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8850 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8852 rtx reg = gen_rtx_REG (TImode, regno);
8854 /* Ensure that adjust_address won't be forced to produce pointer
8855 out of range allowed by x86-64 instruction set. */
8856 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8860 r11 = gen_rtx_REG (DImode, R11_REG);
8861 emit_move_insn (r11, GEN_INT (offset));
8862 emit_insn (gen_adddi3 (r11, r11, pointer));
8863 base_address = gen_rtx_MEM (TImode, r11);
8866 mem = adjust_address (base_address, TImode, offset);
8867 set_mem_align (mem, 128);
8868 insn = emit_move_insn (reg, mem);
8871 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8877 /* Restore function stack, frame, and registers. */
8880 ix86_expand_epilogue (int style)
8883 struct ix86_frame frame;
8884 HOST_WIDE_INT offset, red_offset;
8885 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8888 ix86_finalize_stack_realign_flags ();
8890 /* When stack is realigned, SP must be valid. */
8891 sp_valid = (!frame_pointer_needed
8892 || current_function_sp_is_unchanging
8893 || stack_realign_fp);
8895 ix86_compute_frame_layout (&frame);
8897 /* See the comment about red zone and frame
8898 pointer usage in ix86_expand_prologue. */
8899 if (frame_pointer_needed && frame.red_zone_size)
8900 emit_insn (gen_memory_blockage ());
8902 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8903 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8905 /* Calculate start of saved registers relative to ebp. Special care
8906 must be taken for the normal return case of a function using
8907 eh_return: the eax and edx registers are marked as saved, but not
8908 restored along this path. */
8909 offset = frame.nregs;
8910 if (crtl->calls_eh_return && style != 2)
8912 offset *= -UNITS_PER_WORD;
8913 offset -= frame.nsseregs * 16 + frame.padding0;
8915 /* Calculate start of saved registers relative to esp on entry of the
8916 function. When realigning stack, this needs to be the most negative
8917 value possible at runtime. */
8918 red_offset = offset;
8920 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8922 else if (stack_realign_fp)
8923 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8925 if (ix86_static_chain_on_stack)
8926 red_offset -= UNITS_PER_WORD;
8927 if (frame_pointer_needed)
8928 red_offset -= UNITS_PER_WORD;
8930 /* If we're only restoring one register and sp is not valid then
8931 using a move instruction to restore the register since it's
8932 less work than reloading sp and popping the register.
8934 The default code result in stack adjustment using add/lea instruction,
8935 while this code results in LEAVE instruction (or discrete equivalent),
8936 so it is profitable in some other cases as well. Especially when there
8937 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8938 and there is exactly one register to pop. This heuristic may need some
8939 tuning in future. */
8940 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8941 || (TARGET_EPILOGUE_USING_MOVE
8942 && cfun->machine->use_fast_prologue_epilogue
8943 && ((frame.nregs + frame.nsseregs) > 1
8944 || (frame.to_allocate + frame.padding0) != 0))
8945 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8946 && (frame.to_allocate + frame.padding0) != 0)
8947 || (frame_pointer_needed && TARGET_USE_LEAVE
8948 && cfun->machine->use_fast_prologue_epilogue
8949 && (frame.nregs + frame.nsseregs) == 1)
8950 || crtl->calls_eh_return)
8952 /* Restore registers. We can use ebp or esp to address the memory
8953 locations. If both are available, default to ebp, since offsets
8954 are known to be small. Only exception is esp pointing directly
8955 to the end of block of saved registers, where we may simplify
8958 If we are realigning stack with bp and sp, regs restore can't
8959 be addressed by bp. sp must be used instead. */
8961 if (!frame_pointer_needed
8962 || (sp_valid && !(frame.to_allocate + frame.padding0))
8963 || stack_realign_fp)
8965 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8966 frame.to_allocate, red_offset,
8968 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8970 + frame.nsseregs * 16
8973 + frame.nsseregs * 16
8974 + frame.padding0, style == 2);
8978 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8981 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8983 + frame.nsseregs * 16
8986 + frame.nsseregs * 16
8987 + frame.padding0, style == 2);
8990 red_offset -= offset;
8992 /* eh_return epilogues need %ecx added to the stack pointer. */
8995 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8997 /* Stack align doesn't work with eh_return. */
8998 gcc_assert (!crtl->stack_realign_needed);
8999 /* Neither does regparm nested functions. */
9000 gcc_assert (!ix86_static_chain_on_stack);
9002 if (frame_pointer_needed)
9004 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
9005 tmp = plus_constant (tmp, UNITS_PER_WORD);
9006 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
9008 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
9009 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
9011 /* Note that we use SA as a temporary CFA, as the return
9012 address is at the proper place relative to it. We
9013 pretend this happens at the FP restore insn because
9014 prior to this insn the FP would be stored at the wrong
9015 offset relative to SA, and after this insn we have no
9016 other reasonable register to use for the CFA. We don't
9017 bother resetting the CFA to the SP for the duration of
9019 add_reg_note (tmp, REG_CFA_DEF_CFA,
9020 plus_constant (sa, UNITS_PER_WORD));
9021 ix86_add_queued_cfa_restore_notes (tmp);
9022 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
9023 RTX_FRAME_RELATED_P (tmp) = 1;
9024 ix86_cfa_state->reg = sa;
9025 ix86_cfa_state->offset = UNITS_PER_WORD;
9027 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
9028 const0_rtx, style, false);
9032 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
9033 tmp = plus_constant (tmp, (frame.to_allocate
9034 + frame.nregs * UNITS_PER_WORD
9035 + frame.nsseregs * 16
9037 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
9038 ix86_add_queued_cfa_restore_notes (tmp);
9040 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9041 if (ix86_cfa_state->offset != UNITS_PER_WORD)
9043 ix86_cfa_state->offset = UNITS_PER_WORD;
9044 add_reg_note (tmp, REG_CFA_DEF_CFA,
9045 plus_constant (stack_pointer_rtx,
9047 RTX_FRAME_RELATED_P (tmp) = 1;
9051 else if (!frame_pointer_needed)
9052 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9053 GEN_INT (frame.to_allocate
9054 + frame.nregs * UNITS_PER_WORD
9055 + frame.nsseregs * 16
9057 style, !using_drap);
9058 /* If not an i386, mov & pop is faster than "leave". */
9059 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
9060 || !cfun->machine->use_fast_prologue_epilogue)
9061 ix86_emit_leave (red_offset);
9064 pro_epilogue_adjust_stack (stack_pointer_rtx,
9065 hard_frame_pointer_rtx,
9066 const0_rtx, style, !using_drap);
9068 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
9073 /* First step is to deallocate the stack frame so that we can
9076 If we realign stack with frame pointer, then stack pointer
9077 won't be able to recover via lea $offset(%bp), %sp, because
9078 there is a padding area between bp and sp for realign.
9079 "add $to_allocate, %sp" must be used instead. */
9082 gcc_assert (frame_pointer_needed);
9083 gcc_assert (!stack_realign_fp);
9084 pro_epilogue_adjust_stack (stack_pointer_rtx,
9085 hard_frame_pointer_rtx,
9086 GEN_INT (offset), style, false);
9087 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
9090 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9091 GEN_INT (frame.nsseregs * 16
9095 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
9097 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
9098 frame.to_allocate, red_offset,
9100 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9101 GEN_INT (frame.to_allocate
9102 + frame.nsseregs * 16
9103 + frame.padding0), style,
9104 !using_drap && !frame_pointer_needed);
9107 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
9109 red_offset -= offset;
9111 if (frame_pointer_needed)
9113 /* Leave results in shorter dependency chains on CPUs that are
9114 able to grok it fast. */
9115 if (TARGET_USE_LEAVE)
9116 ix86_emit_leave (red_offset);
9119 /* For stack realigned really happens, recover stack
9120 pointer to hard frame pointer is a must, if not using
9122 if (stack_realign_fp)
9123 pro_epilogue_adjust_stack (stack_pointer_rtx,
9124 hard_frame_pointer_rtx,
9125 const0_rtx, style, !using_drap);
9126 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
9134 int param_ptr_offset = UNITS_PER_WORD;
9137 gcc_assert (stack_realign_drap);
9139 if (ix86_static_chain_on_stack)
9140 param_ptr_offset += UNITS_PER_WORD;
9141 if (!call_used_regs[REGNO (crtl->drap_reg)])
9142 param_ptr_offset += UNITS_PER_WORD;
9144 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
9146 GEN_INT (-param_ptr_offset)));
9148 ix86_cfa_state->reg = stack_pointer_rtx;
9149 ix86_cfa_state->offset = param_ptr_offset;
9151 add_reg_note (insn, REG_CFA_DEF_CFA,
9152 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
9153 GEN_INT (ix86_cfa_state->offset)));
9154 RTX_FRAME_RELATED_P (insn) = 1;
9156 if (!call_used_regs[REGNO (crtl->drap_reg)])
9157 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
9160 /* Remove the saved static chain from the stack. The use of ECX is
9161 merely as a scratch register, not as the actual static chain. */
9162 if (ix86_static_chain_on_stack)
9166 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9167 ix86_cfa_state->offset += UNITS_PER_WORD;
9169 r = gen_rtx_REG (Pmode, CX_REG);
9170 insn = emit_insn (ix86_gen_pop1 (r));
9172 r = plus_constant (stack_pointer_rtx, UNITS_PER_WORD);
9173 r = gen_rtx_SET (VOIDmode, stack_pointer_rtx, r);
9174 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
9175 RTX_FRAME_RELATED_P (insn) = 1;
9178 /* Sibcall epilogues don't want a return instruction. */
9181 *ix86_cfa_state = cfa_state_save;
9185 if (crtl->args.pops_args && crtl->args.size)
9187 rtx popc = GEN_INT (crtl->args.pops_args);
9189 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9190 address, do explicit add, and jump indirectly to the caller. */
9192 if (crtl->args.pops_args >= 65536)
9194 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9197 /* There is no "pascal" calling convention in any 64bit ABI. */
9198 gcc_assert (!TARGET_64BIT);
9200 insn = emit_insn (gen_popsi1 (ecx));
9201 ix86_cfa_state->offset -= UNITS_PER_WORD;
9203 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9204 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9205 add_reg_note (insn, REG_CFA_REGISTER,
9206 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9207 RTX_FRAME_RELATED_P (insn) = 1;
9209 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9211 emit_jump_insn (gen_return_indirect_internal (ecx));
9214 emit_jump_insn (gen_return_pop_internal (popc));
9217 emit_jump_insn (gen_return_internal ());
9219 /* Restore the state back to the state from the prologue,
9220 so that it's correct for the next epilogue. */
9221 *ix86_cfa_state = cfa_state_save;
9224 /* Reset from the function's potential modifications. */
9227 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9228 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9230 if (pic_offset_table_rtx)
9231 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9233 /* Mach-O doesn't support labels at the end of objects, so if
9234 it looks like we might want one, insert a NOP. */
9236 rtx insn = get_last_insn ();
9239 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9240 insn = PREV_INSN (insn);
9244 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9245 fputs ("\tnop\n", file);
9251 /* Extract the parts of an RTL expression that is a valid memory address
9252 for an instruction. Return 0 if the structure of the address is
9253 grossly off. Return -1 if the address contains ASHIFT, so it is not
9254 strictly valid, but still used for computing length of lea instruction. */
9257 ix86_decompose_address (rtx addr, struct ix86_address *out)
9259 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9260 rtx base_reg, index_reg;
9261 HOST_WIDE_INT scale = 1;
9262 rtx scale_rtx = NULL_RTX;
9264 enum ix86_address_seg seg = SEG_DEFAULT;
9266 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9268 else if (GET_CODE (addr) == PLUS)
9278 addends[n++] = XEXP (op, 1);
9281 while (GET_CODE (op) == PLUS);
9286 for (i = n; i >= 0; --i)
9289 switch (GET_CODE (op))
9294 index = XEXP (op, 0);
9295 scale_rtx = XEXP (op, 1);
9299 if (XINT (op, 1) == UNSPEC_TP
9300 && TARGET_TLS_DIRECT_SEG_REFS
9301 && seg == SEG_DEFAULT)
9302 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9331 else if (GET_CODE (addr) == MULT)
9333 index = XEXP (addr, 0); /* index*scale */
9334 scale_rtx = XEXP (addr, 1);
9336 else if (GET_CODE (addr) == ASHIFT)
9340 /* We're called for lea too, which implements ashift on occasion. */
9341 index = XEXP (addr, 0);
9342 tmp = XEXP (addr, 1);
9343 if (!CONST_INT_P (tmp))
9345 scale = INTVAL (tmp);
9346 if ((unsigned HOST_WIDE_INT) scale > 3)
9352 disp = addr; /* displacement */
9354 /* Extract the integral value of scale. */
9357 if (!CONST_INT_P (scale_rtx))
9359 scale = INTVAL (scale_rtx);
9362 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9363 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9365 /* Avoid useless 0 displacement. */
9366 if (disp == const0_rtx && (base || index))
9369 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9370 if (base_reg && index_reg && scale == 1
9371 && (index_reg == arg_pointer_rtx
9372 || index_reg == frame_pointer_rtx
9373 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9376 tmp = base, base = index, index = tmp;
9377 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9380 /* Special case: %ebp cannot be encoded as a base without a displacement.
9384 && (base_reg == hard_frame_pointer_rtx
9385 || base_reg == frame_pointer_rtx
9386 || base_reg == arg_pointer_rtx
9387 || (REG_P (base_reg)
9388 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9389 || REGNO (base_reg) == R13_REG))))
9392 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9393 Avoid this by transforming to [%esi+0].
9394 Reload calls address legitimization without cfun defined, so we need
9395 to test cfun for being non-NULL. */
9396 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9397 && base_reg && !index_reg && !disp
9399 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9402 /* Special case: encode reg+reg instead of reg*2. */
9403 if (!base && index && scale == 2)
9404 base = index, base_reg = index_reg, scale = 1;
9406 /* Special case: scaling cannot be encoded without base or displacement. */
9407 if (!base && !disp && index && scale != 1)
9419 /* Return cost of the memory address x.
9420 For i386, it is better to use a complex address than let gcc copy
9421 the address into a reg and make a new pseudo. But not if the address
9422 requires to two regs - that would mean more pseudos with longer
9425 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9427 struct ix86_address parts;
9429 int ok = ix86_decompose_address (x, &parts);
9433 if (parts.base && GET_CODE (parts.base) == SUBREG)
9434 parts.base = SUBREG_REG (parts.base);
9435 if (parts.index && GET_CODE (parts.index) == SUBREG)
9436 parts.index = SUBREG_REG (parts.index);
9438 /* Attempt to minimize number of registers in the address. */
9440 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9442 && (!REG_P (parts.index)
9443 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9447 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9449 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9450 && parts.base != parts.index)
9453 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9454 since it's predecode logic can't detect the length of instructions
9455 and it degenerates to vector decoded. Increase cost of such
9456 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9457 to split such addresses or even refuse such addresses at all.
9459 Following addressing modes are affected:
9464 The first and last case may be avoidable by explicitly coding the zero in
9465 memory address, but I don't have AMD-K6 machine handy to check this
9469 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9470 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9471 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9477 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9478 this is used for to form addresses to local data when -fPIC is in
9482 darwin_local_data_pic (rtx disp)
9484 return (GET_CODE (disp) == UNSPEC
9485 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9488 /* Determine if a given RTX is a valid constant. We already know this
9489 satisfies CONSTANT_P. */
9492 legitimate_constant_p (rtx x)
9494 switch (GET_CODE (x))
9499 if (GET_CODE (x) == PLUS)
9501 if (!CONST_INT_P (XEXP (x, 1)))
9506 if (TARGET_MACHO && darwin_local_data_pic (x))
9509 /* Only some unspecs are valid as "constants". */
9510 if (GET_CODE (x) == UNSPEC)
9511 switch (XINT (x, 1))
9516 return TARGET_64BIT;
9519 x = XVECEXP (x, 0, 0);
9520 return (GET_CODE (x) == SYMBOL_REF
9521 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9523 x = XVECEXP (x, 0, 0);
9524 return (GET_CODE (x) == SYMBOL_REF
9525 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9530 /* We must have drilled down to a symbol. */
9531 if (GET_CODE (x) == LABEL_REF)
9533 if (GET_CODE (x) != SYMBOL_REF)
9538 /* TLS symbols are never valid. */
9539 if (SYMBOL_REF_TLS_MODEL (x))
9542 /* DLLIMPORT symbols are never valid. */
9543 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9544 && SYMBOL_REF_DLLIMPORT_P (x))
9549 if (GET_MODE (x) == TImode
9550 && x != CONST0_RTX (TImode)
9556 if (!standard_sse_constant_p (x))
9563 /* Otherwise we handle everything else in the move patterns. */
9567 /* Determine if it's legal to put X into the constant pool. This
9568 is not possible for the address of thread-local symbols, which
9569 is checked above. */
9572 ix86_cannot_force_const_mem (rtx x)
9574 /* We can always put integral constants and vectors in memory. */
9575 switch (GET_CODE (x))
9585 return !legitimate_constant_p (x);
9589 /* Nonzero if the constant value X is a legitimate general operand
9590 when generating PIC code. It is given that flag_pic is on and
9591 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9594 legitimate_pic_operand_p (rtx x)
9598 switch (GET_CODE (x))
9601 inner = XEXP (x, 0);
9602 if (GET_CODE (inner) == PLUS
9603 && CONST_INT_P (XEXP (inner, 1)))
9604 inner = XEXP (inner, 0);
9606 /* Only some unspecs are valid as "constants". */
9607 if (GET_CODE (inner) == UNSPEC)
9608 switch (XINT (inner, 1))
9613 return TARGET_64BIT;
9615 x = XVECEXP (inner, 0, 0);
9616 return (GET_CODE (x) == SYMBOL_REF
9617 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9618 case UNSPEC_MACHOPIC_OFFSET:
9619 return legitimate_pic_address_disp_p (x);
9627 return legitimate_pic_address_disp_p (x);
9634 /* Determine if a given CONST RTX is a valid memory displacement
9638 legitimate_pic_address_disp_p (rtx disp)
9642 /* In 64bit mode we can allow direct addresses of symbols and labels
9643 when they are not dynamic symbols. */
9646 rtx op0 = disp, op1;
9648 switch (GET_CODE (disp))
9654 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9656 op0 = XEXP (XEXP (disp, 0), 0);
9657 op1 = XEXP (XEXP (disp, 0), 1);
9658 if (!CONST_INT_P (op1)
9659 || INTVAL (op1) >= 16*1024*1024
9660 || INTVAL (op1) < -16*1024*1024)
9662 if (GET_CODE (op0) == LABEL_REF)
9664 if (GET_CODE (op0) != SYMBOL_REF)
9669 /* TLS references should always be enclosed in UNSPEC. */
9670 if (SYMBOL_REF_TLS_MODEL (op0))
9672 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9673 && ix86_cmodel != CM_LARGE_PIC)
9681 if (GET_CODE (disp) != CONST)
9683 disp = XEXP (disp, 0);
9687 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9688 of GOT tables. We should not need these anyway. */
9689 if (GET_CODE (disp) != UNSPEC
9690 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9691 && XINT (disp, 1) != UNSPEC_GOTOFF
9692 && XINT (disp, 1) != UNSPEC_PLTOFF))
9695 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9696 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9702 if (GET_CODE (disp) == PLUS)
9704 if (!CONST_INT_P (XEXP (disp, 1)))
9706 disp = XEXP (disp, 0);
9710 if (TARGET_MACHO && darwin_local_data_pic (disp))
9713 if (GET_CODE (disp) != UNSPEC)
9716 switch (XINT (disp, 1))
9721 /* We need to check for both symbols and labels because VxWorks loads
9722 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9724 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9725 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9727 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9728 While ABI specify also 32bit relocation but we don't produce it in
9729 small PIC model at all. */
9730 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9731 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9733 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9735 case UNSPEC_GOTTPOFF:
9736 case UNSPEC_GOTNTPOFF:
9737 case UNSPEC_INDNTPOFF:
9740 disp = XVECEXP (disp, 0, 0);
9741 return (GET_CODE (disp) == SYMBOL_REF
9742 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9744 disp = XVECEXP (disp, 0, 0);
9745 return (GET_CODE (disp) == SYMBOL_REF
9746 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9748 disp = XVECEXP (disp, 0, 0);
9749 return (GET_CODE (disp) == SYMBOL_REF
9750 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9756 /* Recognizes RTL expressions that are valid memory addresses for an
9757 instruction. The MODE argument is the machine mode for the MEM
9758 expression that wants to use this address.
9760 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9761 convert common non-canonical forms to canonical form so that they will
9765 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9766 rtx addr, bool strict)
9768 struct ix86_address parts;
9769 rtx base, index, disp;
9770 HOST_WIDE_INT scale;
9772 if (ix86_decompose_address (addr, &parts) <= 0)
9773 /* Decomposition failed. */
9777 index = parts.index;
9779 scale = parts.scale;
9781 /* Validate base register.
9783 Don't allow SUBREG's that span more than a word here. It can lead to spill
9784 failures when the base is one word out of a two word structure, which is
9785 represented internally as a DImode int. */
9793 else if (GET_CODE (base) == SUBREG
9794 && REG_P (SUBREG_REG (base))
9795 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9797 reg = SUBREG_REG (base);
9799 /* Base is not a register. */
9802 if (GET_MODE (base) != Pmode)
9803 /* Base is not in Pmode. */
9806 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9807 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9808 /* Base is not valid. */
9812 /* Validate index register.
9814 Don't allow SUBREG's that span more than a word here -- same as above. */
9822 else if (GET_CODE (index) == SUBREG
9823 && REG_P (SUBREG_REG (index))
9824 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9826 reg = SUBREG_REG (index);
9828 /* Index is not a register. */
9831 if (GET_MODE (index) != Pmode)
9832 /* Index is not in Pmode. */
9835 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9836 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9837 /* Index is not valid. */
9841 /* Validate scale factor. */
9845 /* Scale without index. */
9848 if (scale != 2 && scale != 4 && scale != 8)
9849 /* Scale is not a valid multiplier. */
9853 /* Validate displacement. */
9856 if (GET_CODE (disp) == CONST
9857 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9858 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9859 switch (XINT (XEXP (disp, 0), 1))
9861 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9862 used. While ABI specify also 32bit relocations, we don't produce
9863 them at all and use IP relative instead. */
9866 gcc_assert (flag_pic);
9868 goto is_legitimate_pic;
9870 /* 64bit address unspec. */
9873 case UNSPEC_GOTPCREL:
9874 gcc_assert (flag_pic);
9875 goto is_legitimate_pic;
9877 case UNSPEC_GOTTPOFF:
9878 case UNSPEC_GOTNTPOFF:
9879 case UNSPEC_INDNTPOFF:
9885 /* Invalid address unspec. */
9889 else if (SYMBOLIC_CONST (disp)
9893 && MACHOPIC_INDIRECT
9894 && !machopic_operand_p (disp)
9900 if (TARGET_64BIT && (index || base))
9902 /* foo@dtpoff(%rX) is ok. */
9903 if (GET_CODE (disp) != CONST
9904 || GET_CODE (XEXP (disp, 0)) != PLUS
9905 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9906 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9907 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9908 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9909 /* Non-constant pic memory reference. */
9912 else if (! legitimate_pic_address_disp_p (disp))
9913 /* Displacement is an invalid pic construct. */
9916 /* This code used to verify that a symbolic pic displacement
9917 includes the pic_offset_table_rtx register.
9919 While this is good idea, unfortunately these constructs may
9920 be created by "adds using lea" optimization for incorrect
9929 This code is nonsensical, but results in addressing
9930 GOT table with pic_offset_table_rtx base. We can't
9931 just refuse it easily, since it gets matched by
9932 "addsi3" pattern, that later gets split to lea in the
9933 case output register differs from input. While this
9934 can be handled by separate addsi pattern for this case
9935 that never results in lea, this seems to be easier and
9936 correct fix for crash to disable this test. */
9938 else if (GET_CODE (disp) != LABEL_REF
9939 && !CONST_INT_P (disp)
9940 && (GET_CODE (disp) != CONST
9941 || !legitimate_constant_p (disp))
9942 && (GET_CODE (disp) != SYMBOL_REF
9943 || !legitimate_constant_p (disp)))
9944 /* Displacement is not constant. */
9946 else if (TARGET_64BIT
9947 && !x86_64_immediate_operand (disp, VOIDmode))
9948 /* Displacement is out of range. */
9952 /* Everything looks valid. */
9956 /* Determine if a given RTX is a valid constant address. */
9959 constant_address_p (rtx x)
9961 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9964 /* Return a unique alias set for the GOT. */
9966 static alias_set_type
9967 ix86_GOT_alias_set (void)
9969 static alias_set_type set = -1;
9971 set = new_alias_set ();
9975 /* Return a legitimate reference for ORIG (an address) using the
9976 register REG. If REG is 0, a new pseudo is generated.
9978 There are two types of references that must be handled:
9980 1. Global data references must load the address from the GOT, via
9981 the PIC reg. An insn is emitted to do this load, and the reg is
9984 2. Static data references, constant pool addresses, and code labels
9985 compute the address as an offset from the GOT, whose base is in
9986 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9987 differentiate them from global data objects. The returned
9988 address is the PIC reg + an unspec constant.
9990 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9991 reg also appears in the address. */
9994 legitimize_pic_address (rtx orig, rtx reg)
10001 if (TARGET_MACHO && !TARGET_64BIT)
10004 reg = gen_reg_rtx (Pmode);
10005 /* Use the generic Mach-O PIC machinery. */
10006 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
10010 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
10012 else if (TARGET_64BIT
10013 && ix86_cmodel != CM_SMALL_PIC
10014 && gotoff_operand (addr, Pmode))
10017 /* This symbol may be referenced via a displacement from the PIC
10018 base address (@GOTOFF). */
10020 if (reload_in_progress)
10021 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10022 if (GET_CODE (addr) == CONST)
10023 addr = XEXP (addr, 0);
10024 if (GET_CODE (addr) == PLUS)
10026 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
10028 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
10031 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
10032 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10034 tmpreg = gen_reg_rtx (Pmode);
10037 emit_move_insn (tmpreg, new_rtx);
10041 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
10042 tmpreg, 1, OPTAB_DIRECT);
10045 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
10047 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
10049 /* This symbol may be referenced via a displacement from the PIC
10050 base address (@GOTOFF). */
10052 if (reload_in_progress)
10053 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10054 if (GET_CODE (addr) == CONST)
10055 addr = XEXP (addr, 0);
10056 if (GET_CODE (addr) == PLUS)
10058 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
10060 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
10063 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
10064 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10065 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10069 emit_move_insn (reg, new_rtx);
10073 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
10074 /* We can't use @GOTOFF for text labels on VxWorks;
10075 see gotoff_operand. */
10076 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
10078 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10080 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
10081 return legitimize_dllimport_symbol (addr, true);
10082 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
10083 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
10084 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
10086 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
10087 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
10091 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
10093 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
10094 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10095 new_rtx = gen_const_mem (Pmode, new_rtx);
10096 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
10099 reg = gen_reg_rtx (Pmode);
10100 /* Use directly gen_movsi, otherwise the address is loaded
10101 into register for CSE. We don't want to CSE this addresses,
10102 instead we CSE addresses from the GOT table, so skip this. */
10103 emit_insn (gen_movsi (reg, new_rtx));
10108 /* This symbol must be referenced via a load from the
10109 Global Offset Table (@GOT). */
10111 if (reload_in_progress)
10112 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10113 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
10114 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10116 new_rtx = force_reg (Pmode, new_rtx);
10117 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10118 new_rtx = gen_const_mem (Pmode, new_rtx);
10119 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
10122 reg = gen_reg_rtx (Pmode);
10123 emit_move_insn (reg, new_rtx);
10129 if (CONST_INT_P (addr)
10130 && !x86_64_immediate_operand (addr, VOIDmode))
10134 emit_move_insn (reg, addr);
10138 new_rtx = force_reg (Pmode, addr);
10140 else if (GET_CODE (addr) == CONST)
10142 addr = XEXP (addr, 0);
10144 /* We must match stuff we generate before. Assume the only
10145 unspecs that can get here are ours. Not that we could do
10146 anything with them anyway.... */
10147 if (GET_CODE (addr) == UNSPEC
10148 || (GET_CODE (addr) == PLUS
10149 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10151 gcc_assert (GET_CODE (addr) == PLUS);
10153 if (GET_CODE (addr) == PLUS)
10155 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10157 /* Check first to see if this is a constant offset from a @GOTOFF
10158 symbol reference. */
10159 if (gotoff_operand (op0, Pmode)
10160 && CONST_INT_P (op1))
10164 if (reload_in_progress)
10165 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10166 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10168 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10169 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10170 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10174 emit_move_insn (reg, new_rtx);
10180 if (INTVAL (op1) < -16*1024*1024
10181 || INTVAL (op1) >= 16*1024*1024)
10183 if (!x86_64_immediate_operand (op1, Pmode))
10184 op1 = force_reg (Pmode, op1);
10185 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10191 base = legitimize_pic_address (XEXP (addr, 0), reg);
10192 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10193 base == reg ? NULL_RTX : reg);
10195 if (CONST_INT_P (new_rtx))
10196 new_rtx = plus_constant (base, INTVAL (new_rtx));
10199 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10201 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10202 new_rtx = XEXP (new_rtx, 1);
10204 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10212 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10215 get_thread_pointer (int to_reg)
10219 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10223 reg = gen_reg_rtx (Pmode);
10224 insn = gen_rtx_SET (VOIDmode, reg, tp);
10225 insn = emit_insn (insn);
10230 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10231 false if we expect this to be used for a memory address and true if
10232 we expect to load the address into a register. */
10235 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10237 rtx dest, base, off, pic, tp;
10242 case TLS_MODEL_GLOBAL_DYNAMIC:
10243 dest = gen_reg_rtx (Pmode);
10244 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10246 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10248 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10251 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10252 insns = get_insns ();
10255 RTL_CONST_CALL_P (insns) = 1;
10256 emit_libcall_block (insns, dest, rax, x);
10258 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10259 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10261 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10263 if (TARGET_GNU2_TLS)
10265 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10267 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10271 case TLS_MODEL_LOCAL_DYNAMIC:
10272 base = gen_reg_rtx (Pmode);
10273 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10275 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10277 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10280 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10281 insns = get_insns ();
10284 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10285 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10286 RTL_CONST_CALL_P (insns) = 1;
10287 emit_libcall_block (insns, base, rax, note);
10289 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10290 emit_insn (gen_tls_local_dynamic_base_64 (base));
10292 emit_insn (gen_tls_local_dynamic_base_32 (base));
10294 if (TARGET_GNU2_TLS)
10296 rtx x = ix86_tls_module_base ();
10298 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10299 gen_rtx_MINUS (Pmode, x, tp));
10302 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10303 off = gen_rtx_CONST (Pmode, off);
10305 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10307 if (TARGET_GNU2_TLS)
10309 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10311 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10316 case TLS_MODEL_INITIAL_EXEC:
10320 type = UNSPEC_GOTNTPOFF;
10324 if (reload_in_progress)
10325 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10326 pic = pic_offset_table_rtx;
10327 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10329 else if (!TARGET_ANY_GNU_TLS)
10331 pic = gen_reg_rtx (Pmode);
10332 emit_insn (gen_set_got (pic));
10333 type = UNSPEC_GOTTPOFF;
10338 type = UNSPEC_INDNTPOFF;
10341 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10342 off = gen_rtx_CONST (Pmode, off);
10344 off = gen_rtx_PLUS (Pmode, pic, off);
10345 off = gen_const_mem (Pmode, off);
10346 set_mem_alias_set (off, ix86_GOT_alias_set ());
10348 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10350 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10351 off = force_reg (Pmode, off);
10352 return gen_rtx_PLUS (Pmode, base, off);
10356 base = get_thread_pointer (true);
10357 dest = gen_reg_rtx (Pmode);
10358 emit_insn (gen_subsi3 (dest, base, off));
10362 case TLS_MODEL_LOCAL_EXEC:
10363 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10364 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10365 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10366 off = gen_rtx_CONST (Pmode, off);
10368 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10370 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10371 return gen_rtx_PLUS (Pmode, base, off);
10375 base = get_thread_pointer (true);
10376 dest = gen_reg_rtx (Pmode);
10377 emit_insn (gen_subsi3 (dest, base, off));
10382 gcc_unreachable ();
10388 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10391 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10392 htab_t dllimport_map;
10395 get_dllimport_decl (tree decl)
10397 struct tree_map *h, in;
10400 const char *prefix;
10401 size_t namelen, prefixlen;
10406 if (!dllimport_map)
10407 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10409 in.hash = htab_hash_pointer (decl);
10410 in.base.from = decl;
10411 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10412 h = (struct tree_map *) *loc;
10416 *loc = h = GGC_NEW (struct tree_map);
10418 h->base.from = decl;
10419 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10420 VAR_DECL, NULL, ptr_type_node);
10421 DECL_ARTIFICIAL (to) = 1;
10422 DECL_IGNORED_P (to) = 1;
10423 DECL_EXTERNAL (to) = 1;
10424 TREE_READONLY (to) = 1;
10426 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10427 name = targetm.strip_name_encoding (name);
10428 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10429 ? "*__imp_" : "*__imp__";
10430 namelen = strlen (name);
10431 prefixlen = strlen (prefix);
10432 imp_name = (char *) alloca (namelen + prefixlen + 1);
10433 memcpy (imp_name, prefix, prefixlen);
10434 memcpy (imp_name + prefixlen, name, namelen + 1);
10436 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10437 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10438 SET_SYMBOL_REF_DECL (rtl, to);
10439 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10441 rtl = gen_const_mem (Pmode, rtl);
10442 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10444 SET_DECL_RTL (to, rtl);
10445 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10450 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10451 true if we require the result be a register. */
10454 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10459 gcc_assert (SYMBOL_REF_DECL (symbol));
10460 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10462 x = DECL_RTL (imp_decl);
10464 x = force_reg (Pmode, x);
10468 /* Try machine-dependent ways of modifying an illegitimate address
10469 to be legitimate. If we find one, return the new, valid address.
10470 This macro is used in only one place: `memory_address' in explow.c.
10472 OLDX is the address as it was before break_out_memory_refs was called.
10473 In some cases it is useful to look at this to decide what needs to be done.
10475 It is always safe for this macro to do nothing. It exists to recognize
10476 opportunities to optimize the output.
10478 For the 80386, we handle X+REG by loading X into a register R and
10479 using R+REG. R will go in a general reg and indexing will be used.
10480 However, if REG is a broken-out memory address or multiplication,
10481 nothing needs to be done because REG can certainly go in a general reg.
10483 When -fpic is used, special handling is needed for symbolic references.
10484 See comments by legitimize_pic_address in i386.c for details. */
10487 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10488 enum machine_mode mode)
10493 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10495 return legitimize_tls_address (x, (enum tls_model) log, false);
10496 if (GET_CODE (x) == CONST
10497 && GET_CODE (XEXP (x, 0)) == PLUS
10498 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10499 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10501 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10502 (enum tls_model) log, false);
10503 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10506 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10508 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10509 return legitimize_dllimport_symbol (x, true);
10510 if (GET_CODE (x) == CONST
10511 && GET_CODE (XEXP (x, 0)) == PLUS
10512 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10513 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10515 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10516 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10520 if (flag_pic && SYMBOLIC_CONST (x))
10521 return legitimize_pic_address (x, 0);
10523 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10524 if (GET_CODE (x) == ASHIFT
10525 && CONST_INT_P (XEXP (x, 1))
10526 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10529 log = INTVAL (XEXP (x, 1));
10530 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10531 GEN_INT (1 << log));
10534 if (GET_CODE (x) == PLUS)
10536 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10538 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10539 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10540 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10543 log = INTVAL (XEXP (XEXP (x, 0), 1));
10544 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10545 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10546 GEN_INT (1 << log));
10549 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10550 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10551 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10554 log = INTVAL (XEXP (XEXP (x, 1), 1));
10555 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10556 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10557 GEN_INT (1 << log));
10560 /* Put multiply first if it isn't already. */
10561 if (GET_CODE (XEXP (x, 1)) == MULT)
10563 rtx tmp = XEXP (x, 0);
10564 XEXP (x, 0) = XEXP (x, 1);
10569 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10570 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10571 created by virtual register instantiation, register elimination, and
10572 similar optimizations. */
10573 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10576 x = gen_rtx_PLUS (Pmode,
10577 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10578 XEXP (XEXP (x, 1), 0)),
10579 XEXP (XEXP (x, 1), 1));
10583 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10584 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10585 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10586 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10587 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10588 && CONSTANT_P (XEXP (x, 1)))
10591 rtx other = NULL_RTX;
10593 if (CONST_INT_P (XEXP (x, 1)))
10595 constant = XEXP (x, 1);
10596 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10598 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10600 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10601 other = XEXP (x, 1);
10609 x = gen_rtx_PLUS (Pmode,
10610 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10611 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10612 plus_constant (other, INTVAL (constant)));
10616 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10619 if (GET_CODE (XEXP (x, 0)) == MULT)
10622 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10625 if (GET_CODE (XEXP (x, 1)) == MULT)
10628 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10632 && REG_P (XEXP (x, 1))
10633 && REG_P (XEXP (x, 0)))
10636 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10639 x = legitimize_pic_address (x, 0);
10642 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10645 if (REG_P (XEXP (x, 0)))
10647 rtx temp = gen_reg_rtx (Pmode);
10648 rtx val = force_operand (XEXP (x, 1), temp);
10650 emit_move_insn (temp, val);
10652 XEXP (x, 1) = temp;
10656 else if (REG_P (XEXP (x, 1)))
10658 rtx temp = gen_reg_rtx (Pmode);
10659 rtx val = force_operand (XEXP (x, 0), temp);
10661 emit_move_insn (temp, val);
10663 XEXP (x, 0) = temp;
10671 /* Print an integer constant expression in assembler syntax. Addition
10672 and subtraction are the only arithmetic that may appear in these
10673 expressions. FILE is the stdio stream to write to, X is the rtx, and
10674 CODE is the operand print code from the output string. */
10677 output_pic_addr_const (FILE *file, rtx x, int code)
10681 switch (GET_CODE (x))
10684 gcc_assert (flag_pic);
10689 if (! TARGET_MACHO || TARGET_64BIT)
10690 output_addr_const (file, x);
10693 const char *name = XSTR (x, 0);
10695 /* Mark the decl as referenced so that cgraph will
10696 output the function. */
10697 if (SYMBOL_REF_DECL (x))
10698 mark_decl_referenced (SYMBOL_REF_DECL (x));
10701 if (MACHOPIC_INDIRECT
10702 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10703 name = machopic_indirection_name (x, /*stub_p=*/true);
10705 assemble_name (file, name);
10707 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10708 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10709 fputs ("@PLT", file);
10716 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10717 assemble_name (asm_out_file, buf);
10721 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10725 /* This used to output parentheses around the expression,
10726 but that does not work on the 386 (either ATT or BSD assembler). */
10727 output_pic_addr_const (file, XEXP (x, 0), code);
10731 if (GET_MODE (x) == VOIDmode)
10733 /* We can use %d if the number is <32 bits and positive. */
10734 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10735 fprintf (file, "0x%lx%08lx",
10736 (unsigned long) CONST_DOUBLE_HIGH (x),
10737 (unsigned long) CONST_DOUBLE_LOW (x));
10739 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10742 /* We can't handle floating point constants;
10743 PRINT_OPERAND must handle them. */
10744 output_operand_lossage ("floating constant misused");
10748 /* Some assemblers need integer constants to appear first. */
10749 if (CONST_INT_P (XEXP (x, 0)))
10751 output_pic_addr_const (file, XEXP (x, 0), code);
10753 output_pic_addr_const (file, XEXP (x, 1), code);
10757 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10758 output_pic_addr_const (file, XEXP (x, 1), code);
10760 output_pic_addr_const (file, XEXP (x, 0), code);
10766 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10767 output_pic_addr_const (file, XEXP (x, 0), code);
10769 output_pic_addr_const (file, XEXP (x, 1), code);
10771 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10775 gcc_assert (XVECLEN (x, 0) == 1);
10776 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10777 switch (XINT (x, 1))
10780 fputs ("@GOT", file);
10782 case UNSPEC_GOTOFF:
10783 fputs ("@GOTOFF", file);
10785 case UNSPEC_PLTOFF:
10786 fputs ("@PLTOFF", file);
10788 case UNSPEC_GOTPCREL:
10789 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10790 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10792 case UNSPEC_GOTTPOFF:
10793 /* FIXME: This might be @TPOFF in Sun ld too. */
10794 fputs ("@GOTTPOFF", file);
10797 fputs ("@TPOFF", file);
10799 case UNSPEC_NTPOFF:
10801 fputs ("@TPOFF", file);
10803 fputs ("@NTPOFF", file);
10805 case UNSPEC_DTPOFF:
10806 fputs ("@DTPOFF", file);
10808 case UNSPEC_GOTNTPOFF:
10810 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10811 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10813 fputs ("@GOTNTPOFF", file);
10815 case UNSPEC_INDNTPOFF:
10816 fputs ("@INDNTPOFF", file);
10819 case UNSPEC_MACHOPIC_OFFSET:
10821 machopic_output_function_base_name (file);
10825 output_operand_lossage ("invalid UNSPEC as operand");
10831 output_operand_lossage ("invalid expression as operand");
10835 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10836 We need to emit DTP-relative relocations. */
10838 static void ATTRIBUTE_UNUSED
10839 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10841 fputs (ASM_LONG, file);
10842 output_addr_const (file, x);
10843 fputs ("@DTPOFF", file);
10849 fputs (", 0", file);
10852 gcc_unreachable ();
10856 /* Return true if X is a representation of the PIC register. This copes
10857 with calls from ix86_find_base_term, where the register might have
10858 been replaced by a cselib value. */
10861 ix86_pic_register_p (rtx x)
10863 if (GET_CODE (x) == VALUE && CSELIB_VAL_PTR (x))
10864 return (pic_offset_table_rtx
10865 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10867 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10870 /* In the name of slightly smaller debug output, and to cater to
10871 general assembler lossage, recognize PIC+GOTOFF and turn it back
10872 into a direct symbol reference.
10874 On Darwin, this is necessary to avoid a crash, because Darwin
10875 has a different PIC label for each routine but the DWARF debugging
10876 information is not associated with any particular routine, so it's
10877 necessary to remove references to the PIC label from RTL stored by
10878 the DWARF output code. */
10881 ix86_delegitimize_address (rtx x)
10883 rtx orig_x = delegitimize_mem_from_attrs (x);
10884 /* reg_addend is NULL or a multiple of some register. */
10885 rtx reg_addend = NULL_RTX;
10886 /* const_addend is NULL or a const_int. */
10887 rtx const_addend = NULL_RTX;
10888 /* This is the result, or NULL. */
10889 rtx result = NULL_RTX;
10898 if (GET_CODE (x) != CONST
10899 || GET_CODE (XEXP (x, 0)) != UNSPEC
10900 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10901 || !MEM_P (orig_x))
10903 return XVECEXP (XEXP (x, 0), 0, 0);
10906 if (GET_CODE (x) != PLUS
10907 || GET_CODE (XEXP (x, 1)) != CONST)
10910 if (ix86_pic_register_p (XEXP (x, 0)))
10911 /* %ebx + GOT/GOTOFF */
10913 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10915 /* %ebx + %reg * scale + GOT/GOTOFF */
10916 reg_addend = XEXP (x, 0);
10917 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10918 reg_addend = XEXP (reg_addend, 1);
10919 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10920 reg_addend = XEXP (reg_addend, 0);
10923 if (!REG_P (reg_addend)
10924 && GET_CODE (reg_addend) != MULT
10925 && GET_CODE (reg_addend) != ASHIFT)
10931 x = XEXP (XEXP (x, 1), 0);
10932 if (GET_CODE (x) == PLUS
10933 && CONST_INT_P (XEXP (x, 1)))
10935 const_addend = XEXP (x, 1);
10939 if (GET_CODE (x) == UNSPEC
10940 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10941 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10942 result = XVECEXP (x, 0, 0);
10944 if (TARGET_MACHO && darwin_local_data_pic (x)
10945 && !MEM_P (orig_x))
10946 result = XVECEXP (x, 0, 0);
10952 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10954 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10958 /* If X is a machine specific address (i.e. a symbol or label being
10959 referenced as a displacement from the GOT implemented using an
10960 UNSPEC), then return the base term. Otherwise return X. */
10963 ix86_find_base_term (rtx x)
10969 if (GET_CODE (x) != CONST)
10971 term = XEXP (x, 0);
10972 if (GET_CODE (term) == PLUS
10973 && (CONST_INT_P (XEXP (term, 1))
10974 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10975 term = XEXP (term, 0);
10976 if (GET_CODE (term) != UNSPEC
10977 || XINT (term, 1) != UNSPEC_GOTPCREL)
10980 return XVECEXP (term, 0, 0);
10983 return ix86_delegitimize_address (x);
10987 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10988 int fp, FILE *file)
10990 const char *suffix;
10992 if (mode == CCFPmode || mode == CCFPUmode)
10994 code = ix86_fp_compare_code_to_integer (code);
10998 code = reverse_condition (code);
11049 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
11053 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
11054 Those same assemblers have the same but opposite lossage on cmov. */
11055 if (mode == CCmode)
11056 suffix = fp ? "nbe" : "a";
11057 else if (mode == CCCmode)
11060 gcc_unreachable ();
11076 gcc_unreachable ();
11080 gcc_assert (mode == CCmode || mode == CCCmode);
11097 gcc_unreachable ();
11101 /* ??? As above. */
11102 gcc_assert (mode == CCmode || mode == CCCmode);
11103 suffix = fp ? "nb" : "ae";
11106 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
11110 /* ??? As above. */
11111 if (mode == CCmode)
11113 else if (mode == CCCmode)
11114 suffix = fp ? "nb" : "ae";
11116 gcc_unreachable ();
11119 suffix = fp ? "u" : "p";
11122 suffix = fp ? "nu" : "np";
11125 gcc_unreachable ();
11127 fputs (suffix, file);
11130 /* Print the name of register X to FILE based on its machine mode and number.
11131 If CODE is 'w', pretend the mode is HImode.
11132 If CODE is 'b', pretend the mode is QImode.
11133 If CODE is 'k', pretend the mode is SImode.
11134 If CODE is 'q', pretend the mode is DImode.
11135 If CODE is 'x', pretend the mode is V4SFmode.
11136 If CODE is 't', pretend the mode is V8SFmode.
11137 If CODE is 'h', pretend the reg is the 'high' byte register.
11138 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11139 If CODE is 'd', duplicate the operand for AVX instruction.
11143 print_reg (rtx x, int code, FILE *file)
11146 bool duplicated = code == 'd' && TARGET_AVX;
11148 gcc_assert (x == pc_rtx
11149 || (REGNO (x) != ARG_POINTER_REGNUM
11150 && REGNO (x) != FRAME_POINTER_REGNUM
11151 && REGNO (x) != FLAGS_REG
11152 && REGNO (x) != FPSR_REG
11153 && REGNO (x) != FPCR_REG));
11155 if (ASSEMBLER_DIALECT == ASM_ATT)
11160 gcc_assert (TARGET_64BIT);
11161 fputs ("rip", file);
11165 if (code == 'w' || MMX_REG_P (x))
11167 else if (code == 'b')
11169 else if (code == 'k')
11171 else if (code == 'q')
11173 else if (code == 'y')
11175 else if (code == 'h')
11177 else if (code == 'x')
11179 else if (code == 't')
11182 code = GET_MODE_SIZE (GET_MODE (x));
11184 /* Irritatingly, AMD extended registers use different naming convention
11185 from the normal registers. */
11186 if (REX_INT_REG_P (x))
11188 gcc_assert (TARGET_64BIT);
11192 error ("extended registers have no high halves");
11195 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11198 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11201 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11204 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11207 error ("unsupported operand size for extended register");
11217 if (STACK_TOP_P (x))
11226 if (! ANY_FP_REG_P (x))
11227 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11232 reg = hi_reg_name[REGNO (x)];
11235 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11237 reg = qi_reg_name[REGNO (x)];
11240 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11242 reg = qi_high_reg_name[REGNO (x)];
11247 gcc_assert (!duplicated);
11249 fputs (hi_reg_name[REGNO (x)] + 1, file);
11254 gcc_unreachable ();
11260 if (ASSEMBLER_DIALECT == ASM_ATT)
11261 fprintf (file, ", %%%s", reg);
11263 fprintf (file, ", %s", reg);
11267 /* Locate some local-dynamic symbol still in use by this function
11268 so that we can print its name in some tls_local_dynamic_base
11272 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11276 if (GET_CODE (x) == SYMBOL_REF
11277 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11279 cfun->machine->some_ld_name = XSTR (x, 0);
11286 static const char *
11287 get_some_local_dynamic_name (void)
11291 if (cfun->machine->some_ld_name)
11292 return cfun->machine->some_ld_name;
11294 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11296 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11297 return cfun->machine->some_ld_name;
11302 /* Meaning of CODE:
11303 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11304 C -- print opcode suffix for set/cmov insn.
11305 c -- like C, but print reversed condition
11306 E,e -- likewise, but for compare-and-branch fused insn.
11307 F,f -- likewise, but for floating-point.
11308 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11310 R -- print the prefix for register names.
11311 z -- print the opcode suffix for the size of the current operand.
11312 Z -- likewise, with special suffixes for x87 instructions.
11313 * -- print a star (in certain assembler syntax)
11314 A -- print an absolute memory reference.
11315 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11316 s -- print a shift double count, followed by the assemblers argument
11318 b -- print the QImode name of the register for the indicated operand.
11319 %b0 would print %al if operands[0] is reg 0.
11320 w -- likewise, print the HImode name of the register.
11321 k -- likewise, print the SImode name of the register.
11322 q -- likewise, print the DImode name of the register.
11323 x -- likewise, print the V4SFmode name of the register.
11324 t -- likewise, print the V8SFmode name of the register.
11325 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11326 y -- print "st(0)" instead of "st" as a register.
11327 d -- print duplicated register operand for AVX instruction.
11328 D -- print condition for SSE cmp instruction.
11329 P -- if PIC, print an @PLT suffix.
11330 X -- don't print any sort of PIC '@' suffix for a symbol.
11331 & -- print some in-use local-dynamic symbol name.
11332 H -- print a memory address offset by 8; used for sse high-parts
11333 Y -- print condition for XOP pcom* instruction.
11334 + -- print a branch hint as 'cs' or 'ds' prefix
11335 ; -- print a semicolon (after prefixes due to bug in older gas).
11339 print_operand (FILE *file, rtx x, int code)
11346 if (ASSEMBLER_DIALECT == ASM_ATT)
11352 const char *name = get_some_local_dynamic_name ();
11354 output_operand_lossage ("'%%&' used without any "
11355 "local dynamic TLS references");
11357 assemble_name (file, name);
11362 switch (ASSEMBLER_DIALECT)
11369 /* Intel syntax. For absolute addresses, registers should not
11370 be surrounded by braces. */
11374 PRINT_OPERAND (file, x, 0);
11381 gcc_unreachable ();
11384 PRINT_OPERAND (file, x, 0);
11389 if (ASSEMBLER_DIALECT == ASM_ATT)
11394 if (ASSEMBLER_DIALECT == ASM_ATT)
11399 if (ASSEMBLER_DIALECT == ASM_ATT)
11404 if (ASSEMBLER_DIALECT == ASM_ATT)
11409 if (ASSEMBLER_DIALECT == ASM_ATT)
11414 if (ASSEMBLER_DIALECT == ASM_ATT)
11419 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11421 /* Opcodes don't get size suffixes if using Intel opcodes. */
11422 if (ASSEMBLER_DIALECT == ASM_INTEL)
11425 switch (GET_MODE_SIZE (GET_MODE (x)))
11444 output_operand_lossage
11445 ("invalid operand size for operand code '%c'", code);
11450 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11452 (0, "non-integer operand used with operand code '%c'", code);
11456 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11457 if (ASSEMBLER_DIALECT == ASM_INTEL)
11460 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11462 switch (GET_MODE_SIZE (GET_MODE (x)))
11465 #ifdef HAVE_AS_IX86_FILDS
11475 #ifdef HAVE_AS_IX86_FILDQ
11478 fputs ("ll", file);
11486 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11488 /* 387 opcodes don't get size suffixes
11489 if the operands are registers. */
11490 if (STACK_REG_P (x))
11493 switch (GET_MODE_SIZE (GET_MODE (x)))
11514 output_operand_lossage
11515 ("invalid operand type used with operand code '%c'", code);
11519 output_operand_lossage
11520 ("invalid operand size for operand code '%c'", code);
11537 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11539 PRINT_OPERAND (file, x, 0);
11540 fputs (", ", file);
11545 /* Little bit of braindamage here. The SSE compare instructions
11546 does use completely different names for the comparisons that the
11547 fp conditional moves. */
11550 switch (GET_CODE (x))
11553 fputs ("eq", file);
11556 fputs ("eq_us", file);
11559 fputs ("lt", file);
11562 fputs ("nge", file);
11565 fputs ("le", file);
11568 fputs ("ngt", file);
11571 fputs ("unord", file);
11574 fputs ("neq", file);
11577 fputs ("neq_oq", file);
11580 fputs ("ge", file);
11583 fputs ("nlt", file);
11586 fputs ("gt", file);
11589 fputs ("nle", file);
11592 fputs ("ord", file);
11595 output_operand_lossage ("operand is not a condition code, "
11596 "invalid operand code 'D'");
11602 switch (GET_CODE (x))
11606 fputs ("eq", file);
11610 fputs ("lt", file);
11614 fputs ("le", file);
11617 fputs ("unord", file);
11621 fputs ("neq", file);
11625 fputs ("nlt", file);
11629 fputs ("nle", file);
11632 fputs ("ord", file);
11635 output_operand_lossage ("operand is not a condition code, "
11636 "invalid operand code 'D'");
11642 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11643 if (ASSEMBLER_DIALECT == ASM_ATT)
11645 switch (GET_MODE (x))
11647 case HImode: putc ('w', file); break;
11649 case SFmode: putc ('l', file); break;
11651 case DFmode: putc ('q', file); break;
11652 default: gcc_unreachable ();
11659 if (!COMPARISON_P (x))
11661 output_operand_lossage ("operand is neither a constant nor a "
11662 "condition code, invalid operand code "
11666 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11669 if (!COMPARISON_P (x))
11671 output_operand_lossage ("operand is neither a constant nor a "
11672 "condition code, invalid operand code "
11676 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11677 if (ASSEMBLER_DIALECT == ASM_ATT)
11680 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11683 /* Like above, but reverse condition */
11685 /* Check to see if argument to %c is really a constant
11686 and not a condition code which needs to be reversed. */
11687 if (!COMPARISON_P (x))
11689 output_operand_lossage ("operand is neither a constant nor a "
11690 "condition code, invalid operand "
11694 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11697 if (!COMPARISON_P (x))
11699 output_operand_lossage ("operand is neither a constant nor a "
11700 "condition code, invalid operand "
11704 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11705 if (ASSEMBLER_DIALECT == ASM_ATT)
11708 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11712 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11716 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11720 /* It doesn't actually matter what mode we use here, as we're
11721 only going to use this for printing. */
11722 x = adjust_address_nv (x, DImode, 8);
11730 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11733 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11736 int pred_val = INTVAL (XEXP (x, 0));
11738 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11739 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11741 int taken = pred_val > REG_BR_PROB_BASE / 2;
11742 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11744 /* Emit hints only in the case default branch prediction
11745 heuristics would fail. */
11746 if (taken != cputaken)
11748 /* We use 3e (DS) prefix for taken branches and
11749 2e (CS) prefix for not taken branches. */
11751 fputs ("ds ; ", file);
11753 fputs ("cs ; ", file);
11761 switch (GET_CODE (x))
11764 fputs ("neq", file);
11767 fputs ("eq", file);
11771 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11775 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11779 fputs ("le", file);
11783 fputs ("lt", file);
11786 fputs ("unord", file);
11789 fputs ("ord", file);
11792 fputs ("ueq", file);
11795 fputs ("nlt", file);
11798 fputs ("nle", file);
11801 fputs ("ule", file);
11804 fputs ("ult", file);
11807 fputs ("une", file);
11810 output_operand_lossage ("operand is not a condition code, "
11811 "invalid operand code 'Y'");
11818 fputs (" ; ", file);
11825 output_operand_lossage ("invalid operand code '%c'", code);
11830 print_reg (x, code, file);
11832 else if (MEM_P (x))
11834 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11835 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11836 && GET_MODE (x) != BLKmode)
11839 switch (GET_MODE_SIZE (GET_MODE (x)))
11841 case 1: size = "BYTE"; break;
11842 case 2: size = "WORD"; break;
11843 case 4: size = "DWORD"; break;
11844 case 8: size = "QWORD"; break;
11845 case 12: size = "XWORD"; break;
11847 if (GET_MODE (x) == XFmode)
11853 gcc_unreachable ();
11856 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11859 else if (code == 'w')
11861 else if (code == 'k')
11864 fputs (size, file);
11865 fputs (" PTR ", file);
11869 /* Avoid (%rip) for call operands. */
11870 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11871 && !CONST_INT_P (x))
11872 output_addr_const (file, x);
11873 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11874 output_operand_lossage ("invalid constraints for operand");
11876 output_address (x);
11879 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11884 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11885 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11887 if (ASSEMBLER_DIALECT == ASM_ATT)
11889 fprintf (file, "0x%08lx", (long unsigned int) l);
11892 /* These float cases don't actually occur as immediate operands. */
11893 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11897 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11898 fputs (dstr, file);
11901 else if (GET_CODE (x) == CONST_DOUBLE
11902 && GET_MODE (x) == XFmode)
11906 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11907 fputs (dstr, file);
11912 /* We have patterns that allow zero sets of memory, for instance.
11913 In 64-bit mode, we should probably support all 8-byte vectors,
11914 since we can in fact encode that into an immediate. */
11915 if (GET_CODE (x) == CONST_VECTOR)
11917 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11923 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11925 if (ASSEMBLER_DIALECT == ASM_ATT)
11928 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11929 || GET_CODE (x) == LABEL_REF)
11931 if (ASSEMBLER_DIALECT == ASM_ATT)
11934 fputs ("OFFSET FLAT:", file);
11937 if (CONST_INT_P (x))
11938 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11940 output_pic_addr_const (file, x, code);
11942 output_addr_const (file, x);
11946 /* Print a memory operand whose address is ADDR. */
11949 print_operand_address (FILE *file, rtx addr)
11951 struct ix86_address parts;
11952 rtx base, index, disp;
11954 int ok = ix86_decompose_address (addr, &parts);
11959 index = parts.index;
11961 scale = parts.scale;
11969 if (ASSEMBLER_DIALECT == ASM_ATT)
11971 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11974 gcc_unreachable ();
11977 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11978 if (TARGET_64BIT && !base && !index)
11982 if (GET_CODE (disp) == CONST
11983 && GET_CODE (XEXP (disp, 0)) == PLUS
11984 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11985 symbol = XEXP (XEXP (disp, 0), 0);
11987 if (GET_CODE (symbol) == LABEL_REF
11988 || (GET_CODE (symbol) == SYMBOL_REF
11989 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11992 if (!base && !index)
11994 /* Displacement only requires special attention. */
11996 if (CONST_INT_P (disp))
11998 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11999 fputs ("ds:", file);
12000 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
12003 output_pic_addr_const (file, disp, 0);
12005 output_addr_const (file, disp);
12009 if (ASSEMBLER_DIALECT == ASM_ATT)
12014 output_pic_addr_const (file, disp, 0);
12015 else if (GET_CODE (disp) == LABEL_REF)
12016 output_asm_label (disp);
12018 output_addr_const (file, disp);
12023 print_reg (base, 0, file);
12027 print_reg (index, 0, file);
12029 fprintf (file, ",%d", scale);
12035 rtx offset = NULL_RTX;
12039 /* Pull out the offset of a symbol; print any symbol itself. */
12040 if (GET_CODE (disp) == CONST
12041 && GET_CODE (XEXP (disp, 0)) == PLUS
12042 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
12044 offset = XEXP (XEXP (disp, 0), 1);
12045 disp = gen_rtx_CONST (VOIDmode,
12046 XEXP (XEXP (disp, 0), 0));
12050 output_pic_addr_const (file, disp, 0);
12051 else if (GET_CODE (disp) == LABEL_REF)
12052 output_asm_label (disp);
12053 else if (CONST_INT_P (disp))
12056 output_addr_const (file, disp);
12062 print_reg (base, 0, file);
12065 if (INTVAL (offset) >= 0)
12067 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
12071 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
12078 print_reg (index, 0, file);
12080 fprintf (file, "*%d", scale);
12088 output_addr_const_extra (FILE *file, rtx x)
12092 if (GET_CODE (x) != UNSPEC)
12095 op = XVECEXP (x, 0, 0);
12096 switch (XINT (x, 1))
12098 case UNSPEC_GOTTPOFF:
12099 output_addr_const (file, op);
12100 /* FIXME: This might be @TPOFF in Sun ld. */
12101 fputs ("@GOTTPOFF", file);
12104 output_addr_const (file, op);
12105 fputs ("@TPOFF", file);
12107 case UNSPEC_NTPOFF:
12108 output_addr_const (file, op);
12110 fputs ("@TPOFF", file);
12112 fputs ("@NTPOFF", file);
12114 case UNSPEC_DTPOFF:
12115 output_addr_const (file, op);
12116 fputs ("@DTPOFF", file);
12118 case UNSPEC_GOTNTPOFF:
12119 output_addr_const (file, op);
12121 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
12122 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
12124 fputs ("@GOTNTPOFF", file);
12126 case UNSPEC_INDNTPOFF:
12127 output_addr_const (file, op);
12128 fputs ("@INDNTPOFF", file);
12131 case UNSPEC_MACHOPIC_OFFSET:
12132 output_addr_const (file, op);
12134 machopic_output_function_base_name (file);
12145 /* Split one or more DImode RTL references into pairs of SImode
12146 references. The RTL can be REG, offsettable MEM, integer constant, or
12147 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12148 split and "num" is its length. lo_half and hi_half are output arrays
12149 that parallel "operands". */
12152 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12156 rtx op = operands[num];
12158 /* simplify_subreg refuse to split volatile memory addresses,
12159 but we still have to handle it. */
12162 lo_half[num] = adjust_address (op, SImode, 0);
12163 hi_half[num] = adjust_address (op, SImode, 4);
12167 lo_half[num] = simplify_gen_subreg (SImode, op,
12168 GET_MODE (op) == VOIDmode
12169 ? DImode : GET_MODE (op), 0);
12170 hi_half[num] = simplify_gen_subreg (SImode, op,
12171 GET_MODE (op) == VOIDmode
12172 ? DImode : GET_MODE (op), 4);
12176 /* Split one or more TImode RTL references into pairs of DImode
12177 references. The RTL can be REG, offsettable MEM, integer constant, or
12178 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12179 split and "num" is its length. lo_half and hi_half are output arrays
12180 that parallel "operands". */
12183 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12187 rtx op = operands[num];
12189 /* simplify_subreg refuse to split volatile memory addresses, but we
12190 still have to handle it. */
12193 lo_half[num] = adjust_address (op, DImode, 0);
12194 hi_half[num] = adjust_address (op, DImode, 8);
12198 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
12199 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
12204 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12205 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12206 is the expression of the binary operation. The output may either be
12207 emitted here, or returned to the caller, like all output_* functions.
12209 There is no guarantee that the operands are the same mode, as they
12210 might be within FLOAT or FLOAT_EXTEND expressions. */
12212 #ifndef SYSV386_COMPAT
12213 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12214 wants to fix the assemblers because that causes incompatibility
12215 with gcc. No-one wants to fix gcc because that causes
12216 incompatibility with assemblers... You can use the option of
12217 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12218 #define SYSV386_COMPAT 1
12222 output_387_binary_op (rtx insn, rtx *operands)
12224 static char buf[40];
12227 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12229 #ifdef ENABLE_CHECKING
12230 /* Even if we do not want to check the inputs, this documents input
12231 constraints. Which helps in understanding the following code. */
12232 if (STACK_REG_P (operands[0])
12233 && ((REG_P (operands[1])
12234 && REGNO (operands[0]) == REGNO (operands[1])
12235 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12236 || (REG_P (operands[2])
12237 && REGNO (operands[0]) == REGNO (operands[2])
12238 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12239 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12242 gcc_assert (is_sse);
12245 switch (GET_CODE (operands[3]))
12248 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12249 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12257 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12258 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12266 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12267 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12275 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12276 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12284 gcc_unreachable ();
12291 strcpy (buf, ssep);
12292 if (GET_MODE (operands[0]) == SFmode)
12293 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12295 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12299 strcpy (buf, ssep + 1);
12300 if (GET_MODE (operands[0]) == SFmode)
12301 strcat (buf, "ss\t{%2, %0|%0, %2}");
12303 strcat (buf, "sd\t{%2, %0|%0, %2}");
12309 switch (GET_CODE (operands[3]))
12313 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12315 rtx temp = operands[2];
12316 operands[2] = operands[1];
12317 operands[1] = temp;
12320 /* know operands[0] == operands[1]. */
12322 if (MEM_P (operands[2]))
12328 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12330 if (STACK_TOP_P (operands[0]))
12331 /* How is it that we are storing to a dead operand[2]?
12332 Well, presumably operands[1] is dead too. We can't
12333 store the result to st(0) as st(0) gets popped on this
12334 instruction. Instead store to operands[2] (which I
12335 think has to be st(1)). st(1) will be popped later.
12336 gcc <= 2.8.1 didn't have this check and generated
12337 assembly code that the Unixware assembler rejected. */
12338 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12340 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12344 if (STACK_TOP_P (operands[0]))
12345 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12347 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12352 if (MEM_P (operands[1]))
12358 if (MEM_P (operands[2]))
12364 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12367 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12368 derived assemblers, confusingly reverse the direction of
12369 the operation for fsub{r} and fdiv{r} when the
12370 destination register is not st(0). The Intel assembler
12371 doesn't have this brain damage. Read !SYSV386_COMPAT to
12372 figure out what the hardware really does. */
12373 if (STACK_TOP_P (operands[0]))
12374 p = "{p\t%0, %2|rp\t%2, %0}";
12376 p = "{rp\t%2, %0|p\t%0, %2}";
12378 if (STACK_TOP_P (operands[0]))
12379 /* As above for fmul/fadd, we can't store to st(0). */
12380 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12382 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12387 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12390 if (STACK_TOP_P (operands[0]))
12391 p = "{rp\t%0, %1|p\t%1, %0}";
12393 p = "{p\t%1, %0|rp\t%0, %1}";
12395 if (STACK_TOP_P (operands[0]))
12396 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12398 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12403 if (STACK_TOP_P (operands[0]))
12405 if (STACK_TOP_P (operands[1]))
12406 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12408 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12411 else if (STACK_TOP_P (operands[1]))
12414 p = "{\t%1, %0|r\t%0, %1}";
12416 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12422 p = "{r\t%2, %0|\t%0, %2}";
12424 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12430 gcc_unreachable ();
12437 /* Return needed mode for entity in optimize_mode_switching pass. */
12440 ix86_mode_needed (int entity, rtx insn)
12442 enum attr_i387_cw mode;
12444 /* The mode UNINITIALIZED is used to store control word after a
12445 function call or ASM pattern. The mode ANY specify that function
12446 has no requirements on the control word and make no changes in the
12447 bits we are interested in. */
12450 || (NONJUMP_INSN_P (insn)
12451 && (asm_noperands (PATTERN (insn)) >= 0
12452 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12453 return I387_CW_UNINITIALIZED;
12455 if (recog_memoized (insn) < 0)
12456 return I387_CW_ANY;
12458 mode = get_attr_i387_cw (insn);
12463 if (mode == I387_CW_TRUNC)
12468 if (mode == I387_CW_FLOOR)
12473 if (mode == I387_CW_CEIL)
12478 if (mode == I387_CW_MASK_PM)
12483 gcc_unreachable ();
12486 return I387_CW_ANY;
12489 /* Output code to initialize control word copies used by trunc?f?i and
12490 rounding patterns. CURRENT_MODE is set to current control word,
12491 while NEW_MODE is set to new control word. */
12494 emit_i387_cw_initialization (int mode)
12496 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12499 enum ix86_stack_slot slot;
12501 rtx reg = gen_reg_rtx (HImode);
12503 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12504 emit_move_insn (reg, copy_rtx (stored_mode));
12506 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12507 || optimize_function_for_size_p (cfun))
12511 case I387_CW_TRUNC:
12512 /* round toward zero (truncate) */
12513 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12514 slot = SLOT_CW_TRUNC;
12517 case I387_CW_FLOOR:
12518 /* round down toward -oo */
12519 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12520 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12521 slot = SLOT_CW_FLOOR;
12525 /* round up toward +oo */
12526 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12527 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12528 slot = SLOT_CW_CEIL;
12531 case I387_CW_MASK_PM:
12532 /* mask precision exception for nearbyint() */
12533 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12534 slot = SLOT_CW_MASK_PM;
12538 gcc_unreachable ();
12545 case I387_CW_TRUNC:
12546 /* round toward zero (truncate) */
12547 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12548 slot = SLOT_CW_TRUNC;
12551 case I387_CW_FLOOR:
12552 /* round down toward -oo */
12553 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12554 slot = SLOT_CW_FLOOR;
12558 /* round up toward +oo */
12559 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12560 slot = SLOT_CW_CEIL;
12563 case I387_CW_MASK_PM:
12564 /* mask precision exception for nearbyint() */
12565 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12566 slot = SLOT_CW_MASK_PM;
12570 gcc_unreachable ();
12574 gcc_assert (slot < MAX_386_STACK_LOCALS);
12576 new_mode = assign_386_stack_local (HImode, slot);
12577 emit_move_insn (new_mode, reg);
12580 /* Output code for INSN to convert a float to a signed int. OPERANDS
12581 are the insn operands. The output may be [HSD]Imode and the input
12582 operand may be [SDX]Fmode. */
12585 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12587 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12588 int dimode_p = GET_MODE (operands[0]) == DImode;
12589 int round_mode = get_attr_i387_cw (insn);
12591 /* Jump through a hoop or two for DImode, since the hardware has no
12592 non-popping instruction. We used to do this a different way, but
12593 that was somewhat fragile and broke with post-reload splitters. */
12594 if ((dimode_p || fisttp) && !stack_top_dies)
12595 output_asm_insn ("fld\t%y1", operands);
12597 gcc_assert (STACK_TOP_P (operands[1]));
12598 gcc_assert (MEM_P (operands[0]));
12599 gcc_assert (GET_MODE (operands[1]) != TFmode);
12602 output_asm_insn ("fisttp%Z0\t%0", operands);
12605 if (round_mode != I387_CW_ANY)
12606 output_asm_insn ("fldcw\t%3", operands);
12607 if (stack_top_dies || dimode_p)
12608 output_asm_insn ("fistp%Z0\t%0", operands);
12610 output_asm_insn ("fist%Z0\t%0", operands);
12611 if (round_mode != I387_CW_ANY)
12612 output_asm_insn ("fldcw\t%2", operands);
12618 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12619 have the values zero or one, indicates the ffreep insn's operand
12620 from the OPERANDS array. */
12622 static const char *
12623 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12625 if (TARGET_USE_FFREEP)
12626 #ifdef HAVE_AS_IX86_FFREEP
12627 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12630 static char retval[32];
12631 int regno = REGNO (operands[opno]);
12633 gcc_assert (FP_REGNO_P (regno));
12635 regno -= FIRST_STACK_REG;
12637 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12642 return opno ? "fstp\t%y1" : "fstp\t%y0";
12646 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12647 should be used. UNORDERED_P is true when fucom should be used. */
12650 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12652 int stack_top_dies;
12653 rtx cmp_op0, cmp_op1;
12654 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12658 cmp_op0 = operands[0];
12659 cmp_op1 = operands[1];
12663 cmp_op0 = operands[1];
12664 cmp_op1 = operands[2];
12669 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12670 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12671 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12672 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12674 if (GET_MODE (operands[0]) == SFmode)
12676 return &ucomiss[TARGET_AVX ? 0 : 1];
12678 return &comiss[TARGET_AVX ? 0 : 1];
12681 return &ucomisd[TARGET_AVX ? 0 : 1];
12683 return &comisd[TARGET_AVX ? 0 : 1];
12686 gcc_assert (STACK_TOP_P (cmp_op0));
12688 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12690 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12692 if (stack_top_dies)
12694 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12695 return output_387_ffreep (operands, 1);
12698 return "ftst\n\tfnstsw\t%0";
12701 if (STACK_REG_P (cmp_op1)
12703 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12704 && REGNO (cmp_op1) != FIRST_STACK_REG)
12706 /* If both the top of the 387 stack dies, and the other operand
12707 is also a stack register that dies, then this must be a
12708 `fcompp' float compare */
12712 /* There is no double popping fcomi variant. Fortunately,
12713 eflags is immune from the fstp's cc clobbering. */
12715 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12717 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12718 return output_387_ffreep (operands, 0);
12723 return "fucompp\n\tfnstsw\t%0";
12725 return "fcompp\n\tfnstsw\t%0";
12730 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12732 static const char * const alt[16] =
12734 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12735 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12736 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12737 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12739 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12740 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12744 "fcomi\t{%y1, %0|%0, %y1}",
12745 "fcomip\t{%y1, %0|%0, %y1}",
12746 "fucomi\t{%y1, %0|%0, %y1}",
12747 "fucomip\t{%y1, %0|%0, %y1}",
12758 mask = eflags_p << 3;
12759 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12760 mask |= unordered_p << 1;
12761 mask |= stack_top_dies;
12763 gcc_assert (mask < 16);
12772 ix86_output_addr_vec_elt (FILE *file, int value)
12774 const char *directive = ASM_LONG;
12778 directive = ASM_QUAD;
12780 gcc_assert (!TARGET_64BIT);
12783 fprintf (file, "%s" LPREFIX "%d\n", directive, value);
12787 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12789 const char *directive = ASM_LONG;
12792 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12793 directive = ASM_QUAD;
12795 gcc_assert (!TARGET_64BIT);
12797 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12798 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12799 fprintf (file, "%s" LPREFIX "%d-" LPREFIX "%d\n",
12800 directive, value, rel);
12801 else if (HAVE_AS_GOTOFF_IN_DATA)
12802 fprintf (file, ASM_LONG LPREFIX "%d@GOTOFF\n", value);
12804 else if (TARGET_MACHO)
12806 fprintf (file, ASM_LONG LPREFIX "%d-", value);
12807 machopic_output_function_base_name (file);
12812 asm_fprintf (file, ASM_LONG "%U%s+[.-" LPREFIX "%d]\n",
12813 GOT_SYMBOL_NAME, value);
12816 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12820 ix86_expand_clear (rtx dest)
12824 /* We play register width games, which are only valid after reload. */
12825 gcc_assert (reload_completed);
12827 /* Avoid HImode and its attendant prefix byte. */
12828 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12829 dest = gen_rtx_REG (SImode, REGNO (dest));
12830 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12832 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12833 if (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ())
12835 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12836 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12842 /* X is an unchanging MEM. If it is a constant pool reference, return
12843 the constant pool rtx, else NULL. */
12846 maybe_get_pool_constant (rtx x)
12848 x = ix86_delegitimize_address (XEXP (x, 0));
12850 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12851 return get_pool_constant (x);
12857 ix86_expand_move (enum machine_mode mode, rtx operands[])
12860 enum tls_model model;
12865 if (GET_CODE (op1) == SYMBOL_REF)
12867 model = SYMBOL_REF_TLS_MODEL (op1);
12870 op1 = legitimize_tls_address (op1, model, true);
12871 op1 = force_operand (op1, op0);
12875 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12876 && SYMBOL_REF_DLLIMPORT_P (op1))
12877 op1 = legitimize_dllimport_symbol (op1, false);
12879 else if (GET_CODE (op1) == CONST
12880 && GET_CODE (XEXP (op1, 0)) == PLUS
12881 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12883 rtx addend = XEXP (XEXP (op1, 0), 1);
12884 rtx symbol = XEXP (XEXP (op1, 0), 0);
12887 model = SYMBOL_REF_TLS_MODEL (symbol);
12889 tmp = legitimize_tls_address (symbol, model, true);
12890 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12891 && SYMBOL_REF_DLLIMPORT_P (symbol))
12892 tmp = legitimize_dllimport_symbol (symbol, true);
12896 tmp = force_operand (tmp, NULL);
12897 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12898 op0, 1, OPTAB_DIRECT);
12904 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12906 if (TARGET_MACHO && !TARGET_64BIT)
12911 rtx temp = ((reload_in_progress
12912 || ((op0 && REG_P (op0))
12914 ? op0 : gen_reg_rtx (Pmode));
12915 op1 = machopic_indirect_data_reference (op1, temp);
12916 op1 = machopic_legitimize_pic_address (op1, mode,
12917 temp == op1 ? 0 : temp);
12919 else if (MACHOPIC_INDIRECT)
12920 op1 = machopic_indirect_data_reference (op1, 0);
12928 op1 = force_reg (Pmode, op1);
12929 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12931 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
12932 op1 = legitimize_pic_address (op1, reg);
12941 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12942 || !push_operand (op0, mode))
12944 op1 = force_reg (mode, op1);
12946 if (push_operand (op0, mode)
12947 && ! general_no_elim_operand (op1, mode))
12948 op1 = copy_to_mode_reg (mode, op1);
12950 /* Force large constants in 64bit compilation into register
12951 to get them CSEed. */
12952 if (can_create_pseudo_p ()
12953 && (mode == DImode) && TARGET_64BIT
12954 && immediate_operand (op1, mode)
12955 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12956 && !register_operand (op0, mode)
12958 op1 = copy_to_mode_reg (mode, op1);
12960 if (can_create_pseudo_p ()
12961 && FLOAT_MODE_P (mode)
12962 && GET_CODE (op1) == CONST_DOUBLE)
12964 /* If we are loading a floating point constant to a register,
12965 force the value to memory now, since we'll get better code
12966 out the back end. */
12968 op1 = validize_mem (force_const_mem (mode, op1));
12969 if (!register_operand (op0, mode))
12971 rtx temp = gen_reg_rtx (mode);
12972 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12973 emit_move_insn (op0, temp);
12979 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12983 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12985 rtx op0 = operands[0], op1 = operands[1];
12986 unsigned int align = GET_MODE_ALIGNMENT (mode);
12988 /* Force constants other than zero into memory. We do not know how
12989 the instructions used to build constants modify the upper 64 bits
12990 of the register, once we have that information we may be able
12991 to handle some of them more efficiently. */
12992 if (can_create_pseudo_p ()
12993 && register_operand (op0, mode)
12994 && (CONSTANT_P (op1)
12995 || (GET_CODE (op1) == SUBREG
12996 && CONSTANT_P (SUBREG_REG (op1))))
12997 && !standard_sse_constant_p (op1))
12998 op1 = validize_mem (force_const_mem (mode, op1));
13000 /* We need to check memory alignment for SSE mode since attribute
13001 can make operands unaligned. */
13002 if (can_create_pseudo_p ()
13003 && SSE_REG_MODE_P (mode)
13004 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
13005 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
13009 /* ix86_expand_vector_move_misalign() does not like constants ... */
13010 if (CONSTANT_P (op1)
13011 || (GET_CODE (op1) == SUBREG
13012 && CONSTANT_P (SUBREG_REG (op1))))
13013 op1 = validize_mem (force_const_mem (mode, op1));
13015 /* ... nor both arguments in memory. */
13016 if (!register_operand (op0, mode)
13017 && !register_operand (op1, mode))
13018 op1 = force_reg (mode, op1);
13020 tmp[0] = op0; tmp[1] = op1;
13021 ix86_expand_vector_move_misalign (mode, tmp);
13025 /* Make operand1 a register if it isn't already. */
13026 if (can_create_pseudo_p ()
13027 && !register_operand (op0, mode)
13028 && !register_operand (op1, mode))
13030 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
13034 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
13037 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
13038 straight to ix86_expand_vector_move. */
13039 /* Code generation for scalar reg-reg moves of single and double precision data:
13040 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
13044 if (x86_sse_partial_reg_dependency == true)
13049 Code generation for scalar loads of double precision data:
13050 if (x86_sse_split_regs == true)
13051 movlpd mem, reg (gas syntax)
13055 Code generation for unaligned packed loads of single precision data
13056 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
13057 if (x86_sse_unaligned_move_optimal)
13060 if (x86_sse_partial_reg_dependency == true)
13072 Code generation for unaligned packed loads of double precision data
13073 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
13074 if (x86_sse_unaligned_move_optimal)
13077 if (x86_sse_split_regs == true)
13090 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
13099 switch (GET_MODE_CLASS (mode))
13101 case MODE_VECTOR_INT:
13103 switch (GET_MODE_SIZE (mode))
13106 op0 = gen_lowpart (V16QImode, op0);
13107 op1 = gen_lowpart (V16QImode, op1);
13108 emit_insn (gen_avx_movdqu (op0, op1));
13111 op0 = gen_lowpart (V32QImode, op0);
13112 op1 = gen_lowpart (V32QImode, op1);
13113 emit_insn (gen_avx_movdqu256 (op0, op1));
13116 gcc_unreachable ();
13119 case MODE_VECTOR_FLOAT:
13120 op0 = gen_lowpart (mode, op0);
13121 op1 = gen_lowpart (mode, op1);
13126 emit_insn (gen_avx_movups (op0, op1));
13129 emit_insn (gen_avx_movups256 (op0, op1));
13132 emit_insn (gen_avx_movupd (op0, op1));
13135 emit_insn (gen_avx_movupd256 (op0, op1));
13138 gcc_unreachable ();
13143 gcc_unreachable ();
13151 /* If we're optimizing for size, movups is the smallest. */
13152 if (optimize_insn_for_size_p ())
13154 op0 = gen_lowpart (V4SFmode, op0);
13155 op1 = gen_lowpart (V4SFmode, op1);
13156 emit_insn (gen_sse_movups (op0, op1));
13160 /* ??? If we have typed data, then it would appear that using
13161 movdqu is the only way to get unaligned data loaded with
13163 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13165 op0 = gen_lowpart (V16QImode, op0);
13166 op1 = gen_lowpart (V16QImode, op1);
13167 emit_insn (gen_sse2_movdqu (op0, op1));
13171 if (TARGET_SSE2 && mode == V2DFmode)
13175 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13177 op0 = gen_lowpart (V2DFmode, op0);
13178 op1 = gen_lowpart (V2DFmode, op1);
13179 emit_insn (gen_sse2_movupd (op0, op1));
13183 /* When SSE registers are split into halves, we can avoid
13184 writing to the top half twice. */
13185 if (TARGET_SSE_SPLIT_REGS)
13187 emit_clobber (op0);
13192 /* ??? Not sure about the best option for the Intel chips.
13193 The following would seem to satisfy; the register is
13194 entirely cleared, breaking the dependency chain. We
13195 then store to the upper half, with a dependency depth
13196 of one. A rumor has it that Intel recommends two movsd
13197 followed by an unpacklpd, but this is unconfirmed. And
13198 given that the dependency depth of the unpacklpd would
13199 still be one, I'm not sure why this would be better. */
13200 zero = CONST0_RTX (V2DFmode);
13203 m = adjust_address (op1, DFmode, 0);
13204 emit_insn (gen_sse2_loadlpd (op0, zero, m));
13205 m = adjust_address (op1, DFmode, 8);
13206 emit_insn (gen_sse2_loadhpd (op0, op0, m));
13210 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13212 op0 = gen_lowpart (V4SFmode, op0);
13213 op1 = gen_lowpart (V4SFmode, op1);
13214 emit_insn (gen_sse_movups (op0, op1));
13218 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13219 emit_move_insn (op0, CONST0_RTX (mode));
13221 emit_clobber (op0);
13223 if (mode != V4SFmode)
13224 op0 = gen_lowpart (V4SFmode, op0);
13225 m = adjust_address (op1, V2SFmode, 0);
13226 emit_insn (gen_sse_loadlps (op0, op0, m));
13227 m = adjust_address (op1, V2SFmode, 8);
13228 emit_insn (gen_sse_loadhps (op0, op0, m));
13231 else if (MEM_P (op0))
13233 /* If we're optimizing for size, movups is the smallest. */
13234 if (optimize_insn_for_size_p ())
13236 op0 = gen_lowpart (V4SFmode, op0);
13237 op1 = gen_lowpart (V4SFmode, op1);
13238 emit_insn (gen_sse_movups (op0, op1));
13242 /* ??? Similar to above, only less clear because of quote
13243 typeless stores unquote. */
13244 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13245 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13247 op0 = gen_lowpart (V16QImode, op0);
13248 op1 = gen_lowpart (V16QImode, op1);
13249 emit_insn (gen_sse2_movdqu (op0, op1));
13253 if (TARGET_SSE2 && mode == V2DFmode)
13255 m = adjust_address (op0, DFmode, 0);
13256 emit_insn (gen_sse2_storelpd (m, op1));
13257 m = adjust_address (op0, DFmode, 8);
13258 emit_insn (gen_sse2_storehpd (m, op1));
13262 if (mode != V4SFmode)
13263 op1 = gen_lowpart (V4SFmode, op1);
13264 m = adjust_address (op0, V2SFmode, 0);
13265 emit_insn (gen_sse_storelps (m, op1));
13266 m = adjust_address (op0, V2SFmode, 8);
13267 emit_insn (gen_sse_storehps (m, op1));
13271 gcc_unreachable ();
13274 /* Expand a push in MODE. This is some mode for which we do not support
13275 proper push instructions, at least from the registers that we expect
13276 the value to live in. */
13279 ix86_expand_push (enum machine_mode mode, rtx x)
13283 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13284 GEN_INT (-GET_MODE_SIZE (mode)),
13285 stack_pointer_rtx, 1, OPTAB_DIRECT);
13286 if (tmp != stack_pointer_rtx)
13287 emit_move_insn (stack_pointer_rtx, tmp);
13289 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13291 /* When we push an operand onto stack, it has to be aligned at least
13292 at the function argument boundary. However since we don't have
13293 the argument type, we can't determine the actual argument
13295 emit_move_insn (tmp, x);
13298 /* Helper function of ix86_fixup_binary_operands to canonicalize
13299 operand order. Returns true if the operands should be swapped. */
13302 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13305 rtx dst = operands[0];
13306 rtx src1 = operands[1];
13307 rtx src2 = operands[2];
13309 /* If the operation is not commutative, we can't do anything. */
13310 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13313 /* Highest priority is that src1 should match dst. */
13314 if (rtx_equal_p (dst, src1))
13316 if (rtx_equal_p (dst, src2))
13319 /* Next highest priority is that immediate constants come second. */
13320 if (immediate_operand (src2, mode))
13322 if (immediate_operand (src1, mode))
13325 /* Lowest priority is that memory references should come second. */
13335 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13336 destination to use for the operation. If different from the true
13337 destination in operands[0], a copy operation will be required. */
13340 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13343 rtx dst = operands[0];
13344 rtx src1 = operands[1];
13345 rtx src2 = operands[2];
13347 /* Canonicalize operand order. */
13348 if (ix86_swap_binary_operands_p (code, mode, operands))
13352 /* It is invalid to swap operands of different modes. */
13353 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13360 /* Both source operands cannot be in memory. */
13361 if (MEM_P (src1) && MEM_P (src2))
13363 /* Optimization: Only read from memory once. */
13364 if (rtx_equal_p (src1, src2))
13366 src2 = force_reg (mode, src2);
13370 src2 = force_reg (mode, src2);
13373 /* If the destination is memory, and we do not have matching source
13374 operands, do things in registers. */
13375 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13376 dst = gen_reg_rtx (mode);
13378 /* Source 1 cannot be a constant. */
13379 if (CONSTANT_P (src1))
13380 src1 = force_reg (mode, src1);
13382 /* Source 1 cannot be a non-matching memory. */
13383 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13384 src1 = force_reg (mode, src1);
13386 operands[1] = src1;
13387 operands[2] = src2;
13391 /* Similarly, but assume that the destination has already been
13392 set up properly. */
13395 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13396 enum machine_mode mode, rtx operands[])
13398 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13399 gcc_assert (dst == operands[0]);
13402 /* Attempt to expand a binary operator. Make the expansion closer to the
13403 actual machine, then just general_operand, which will allow 3 separate
13404 memory references (one output, two input) in a single insn. */
13407 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13410 rtx src1, src2, dst, op, clob;
13412 dst = ix86_fixup_binary_operands (code, mode, operands);
13413 src1 = operands[1];
13414 src2 = operands[2];
13416 /* Emit the instruction. */
13418 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13419 if (reload_in_progress)
13421 /* Reload doesn't know about the flags register, and doesn't know that
13422 it doesn't want to clobber it. We can only do this with PLUS. */
13423 gcc_assert (code == PLUS);
13428 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13429 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13432 /* Fix up the destination if needed. */
13433 if (dst != operands[0])
13434 emit_move_insn (operands[0], dst);
13437 /* Return TRUE or FALSE depending on whether the binary operator meets the
13438 appropriate constraints. */
13441 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13444 rtx dst = operands[0];
13445 rtx src1 = operands[1];
13446 rtx src2 = operands[2];
13448 /* Both source operands cannot be in memory. */
13449 if (MEM_P (src1) && MEM_P (src2))
13452 /* Canonicalize operand order for commutative operators. */
13453 if (ix86_swap_binary_operands_p (code, mode, operands))
13460 /* If the destination is memory, we must have a matching source operand. */
13461 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13464 /* Source 1 cannot be a constant. */
13465 if (CONSTANT_P (src1))
13468 /* Source 1 cannot be a non-matching memory. */
13469 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13475 /* Attempt to expand a unary operator. Make the expansion closer to the
13476 actual machine, then just general_operand, which will allow 2 separate
13477 memory references (one output, one input) in a single insn. */
13480 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13483 int matching_memory;
13484 rtx src, dst, op, clob;
13489 /* If the destination is memory, and we do not have matching source
13490 operands, do things in registers. */
13491 matching_memory = 0;
13494 if (rtx_equal_p (dst, src))
13495 matching_memory = 1;
13497 dst = gen_reg_rtx (mode);
13500 /* When source operand is memory, destination must match. */
13501 if (MEM_P (src) && !matching_memory)
13502 src = force_reg (mode, src);
13504 /* Emit the instruction. */
13506 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13507 if (reload_in_progress || code == NOT)
13509 /* Reload doesn't know about the flags register, and doesn't know that
13510 it doesn't want to clobber it. */
13511 gcc_assert (code == NOT);
13516 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13517 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13520 /* Fix up the destination if needed. */
13521 if (dst != operands[0])
13522 emit_move_insn (operands[0], dst);
13525 #define LEA_SEARCH_THRESHOLD 12
13527 /* Search backward for non-agu definition of register number REGNO1
13528 or register number REGNO2 in INSN's basic block until
13529 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13530 2. Reach BB boundary, or
13531 3. Reach agu definition.
13532 Returns the distance between the non-agu definition point and INSN.
13533 If no definition point, returns -1. */
13536 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13539 basic_block bb = BLOCK_FOR_INSN (insn);
13542 enum attr_type insn_type;
13544 if (insn != BB_HEAD (bb))
13546 rtx prev = PREV_INSN (insn);
13547 while (prev && distance < LEA_SEARCH_THRESHOLD)
13552 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13553 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13554 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13555 && (regno1 == DF_REF_REGNO (*def_rec)
13556 || regno2 == DF_REF_REGNO (*def_rec)))
13558 insn_type = get_attr_type (prev);
13559 if (insn_type != TYPE_LEA)
13563 if (prev == BB_HEAD (bb))
13565 prev = PREV_INSN (prev);
13569 if (distance < LEA_SEARCH_THRESHOLD)
13573 bool simple_loop = false;
13575 FOR_EACH_EDGE (e, ei, bb->preds)
13578 simple_loop = true;
13584 rtx prev = BB_END (bb);
13587 && distance < LEA_SEARCH_THRESHOLD)
13592 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13593 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13594 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13595 && (regno1 == DF_REF_REGNO (*def_rec)
13596 || regno2 == DF_REF_REGNO (*def_rec)))
13598 insn_type = get_attr_type (prev);
13599 if (insn_type != TYPE_LEA)
13603 prev = PREV_INSN (prev);
13611 /* get_attr_type may modify recog data. We want to make sure
13612 that recog data is valid for instruction INSN, on which
13613 distance_non_agu_define is called. INSN is unchanged here. */
13614 extract_insn_cached (insn);
13618 /* Return the distance between INSN and the next insn that uses
13619 register number REGNO0 in memory address. Return -1 if no such
13620 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13623 distance_agu_use (unsigned int regno0, rtx insn)
13625 basic_block bb = BLOCK_FOR_INSN (insn);
13630 if (insn != BB_END (bb))
13632 rtx next = NEXT_INSN (insn);
13633 while (next && distance < LEA_SEARCH_THRESHOLD)
13639 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13640 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13641 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13642 && regno0 == DF_REF_REGNO (*use_rec))
13644 /* Return DISTANCE if OP0 is used in memory
13645 address in NEXT. */
13649 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13650 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13651 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13652 && regno0 == DF_REF_REGNO (*def_rec))
13654 /* Return -1 if OP0 is set in NEXT. */
13658 if (next == BB_END (bb))
13660 next = NEXT_INSN (next);
13664 if (distance < LEA_SEARCH_THRESHOLD)
13668 bool simple_loop = false;
13670 FOR_EACH_EDGE (e, ei, bb->succs)
13673 simple_loop = true;
13679 rtx next = BB_HEAD (bb);
13682 && distance < LEA_SEARCH_THRESHOLD)
13688 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13689 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13690 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13691 && regno0 == DF_REF_REGNO (*use_rec))
13693 /* Return DISTANCE if OP0 is used in memory
13694 address in NEXT. */
13698 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13699 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13700 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13701 && regno0 == DF_REF_REGNO (*def_rec))
13703 /* Return -1 if OP0 is set in NEXT. */
13708 next = NEXT_INSN (next);
13716 /* Define this macro to tune LEA priority vs ADD, it take effect when
13717 there is a dilemma of choicing LEA or ADD
13718 Negative value: ADD is more preferred than LEA
13720 Positive value: LEA is more preferred than ADD*/
13721 #define IX86_LEA_PRIORITY 2
13723 /* Return true if it is ok to optimize an ADD operation to LEA
13724 operation to avoid flag register consumation. For the processors
13725 like ATOM, if the destination register of LEA holds an actual
13726 address which will be used soon, LEA is better and otherwise ADD
13730 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13731 rtx insn, rtx operands[])
13733 unsigned int regno0 = true_regnum (operands[0]);
13734 unsigned int regno1 = true_regnum (operands[1]);
13735 unsigned int regno2;
13737 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13738 return regno0 != regno1;
13740 regno2 = true_regnum (operands[2]);
13742 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13743 if (regno0 != regno1 && regno0 != regno2)
13747 int dist_define, dist_use;
13748 dist_define = distance_non_agu_define (regno1, regno2, insn);
13749 if (dist_define <= 0)
13752 /* If this insn has both backward non-agu dependence and forward
13753 agu dependence, the one with short distance take effect. */
13754 dist_use = distance_agu_use (regno0, insn);
13756 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13763 /* Return true if destination reg of SET_BODY is shift count of
13767 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13773 /* Retrieve destination of SET_BODY. */
13774 switch (GET_CODE (set_body))
13777 set_dest = SET_DEST (set_body);
13778 if (!set_dest || !REG_P (set_dest))
13782 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13783 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13791 /* Retrieve shift count of USE_BODY. */
13792 switch (GET_CODE (use_body))
13795 shift_rtx = XEXP (use_body, 1);
13798 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13799 if (ix86_dep_by_shift_count_body (set_body,
13800 XVECEXP (use_body, 0, i)))
13808 && (GET_CODE (shift_rtx) == ASHIFT
13809 || GET_CODE (shift_rtx) == LSHIFTRT
13810 || GET_CODE (shift_rtx) == ASHIFTRT
13811 || GET_CODE (shift_rtx) == ROTATE
13812 || GET_CODE (shift_rtx) == ROTATERT))
13814 rtx shift_count = XEXP (shift_rtx, 1);
13816 /* Return true if shift count is dest of SET_BODY. */
13817 if (REG_P (shift_count)
13818 && true_regnum (set_dest) == true_regnum (shift_count))
13825 /* Return true if destination reg of SET_INSN is shift count of
13829 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13831 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13832 PATTERN (use_insn));
13835 /* Return TRUE or FALSE depending on whether the unary operator meets the
13836 appropriate constraints. */
13839 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13840 enum machine_mode mode ATTRIBUTE_UNUSED,
13841 rtx operands[2] ATTRIBUTE_UNUSED)
13843 /* If one of operands is memory, source and destination must match. */
13844 if ((MEM_P (operands[0])
13845 || MEM_P (operands[1]))
13846 && ! rtx_equal_p (operands[0], operands[1]))
13851 /* Post-reload splitter for converting an SF or DFmode value in an
13852 SSE register into an unsigned SImode. */
13855 ix86_split_convert_uns_si_sse (rtx operands[])
13857 enum machine_mode vecmode;
13858 rtx value, large, zero_or_two31, input, two31, x;
13860 large = operands[1];
13861 zero_or_two31 = operands[2];
13862 input = operands[3];
13863 two31 = operands[4];
13864 vecmode = GET_MODE (large);
13865 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13867 /* Load up the value into the low element. We must ensure that the other
13868 elements are valid floats -- zero is the easiest such value. */
13871 if (vecmode == V4SFmode)
13872 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13874 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13878 input = gen_rtx_REG (vecmode, REGNO (input));
13879 emit_move_insn (value, CONST0_RTX (vecmode));
13880 if (vecmode == V4SFmode)
13881 emit_insn (gen_sse_movss (value, value, input));
13883 emit_insn (gen_sse2_movsd (value, value, input));
13886 emit_move_insn (large, two31);
13887 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13889 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13890 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13892 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13893 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13895 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13896 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13898 large = gen_rtx_REG (V4SImode, REGNO (large));
13899 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13901 x = gen_rtx_REG (V4SImode, REGNO (value));
13902 if (vecmode == V4SFmode)
13903 emit_insn (gen_sse2_cvttps2dq (x, value));
13905 emit_insn (gen_sse2_cvttpd2dq (x, value));
13908 emit_insn (gen_xorv4si3 (value, value, large));
13911 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13912 Expects the 64-bit DImode to be supplied in a pair of integral
13913 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13914 -mfpmath=sse, !optimize_size only. */
13917 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13919 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13920 rtx int_xmm, fp_xmm;
13921 rtx biases, exponents;
13924 int_xmm = gen_reg_rtx (V4SImode);
13925 if (TARGET_INTER_UNIT_MOVES)
13926 emit_insn (gen_movdi_to_sse (int_xmm, input));
13927 else if (TARGET_SSE_SPLIT_REGS)
13929 emit_clobber (int_xmm);
13930 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13934 x = gen_reg_rtx (V2DImode);
13935 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13936 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13939 x = gen_rtx_CONST_VECTOR (V4SImode,
13940 gen_rtvec (4, GEN_INT (0x43300000UL),
13941 GEN_INT (0x45300000UL),
13942 const0_rtx, const0_rtx));
13943 exponents = validize_mem (force_const_mem (V4SImode, x));
13945 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13946 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13948 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13949 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13950 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13951 (0x1.0p84 + double(fp_value_hi_xmm)).
13952 Note these exponents differ by 32. */
13954 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13956 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13957 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13958 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13959 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13960 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13961 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13962 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13963 biases = validize_mem (force_const_mem (V2DFmode, biases));
13964 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13966 /* Add the upper and lower DFmode values together. */
13968 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13971 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13972 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13973 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13976 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13979 /* Not used, but eases macroization of patterns. */
13981 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13982 rtx input ATTRIBUTE_UNUSED)
13984 gcc_unreachable ();
13987 /* Convert an unsigned SImode value into a DFmode. Only currently used
13988 for SSE, but applicable anywhere. */
13991 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13993 REAL_VALUE_TYPE TWO31r;
13996 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13997 NULL, 1, OPTAB_DIRECT);
13999 fp = gen_reg_rtx (DFmode);
14000 emit_insn (gen_floatsidf2 (fp, x));
14002 real_ldexp (&TWO31r, &dconst1, 31);
14003 x = const_double_from_real_value (TWO31r, DFmode);
14005 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
14007 emit_move_insn (target, x);
14010 /* Convert a signed DImode value into a DFmode. Only used for SSE in
14011 32-bit mode; otherwise we have a direct convert instruction. */
14014 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
14016 REAL_VALUE_TYPE TWO32r;
14017 rtx fp_lo, fp_hi, x;
14019 fp_lo = gen_reg_rtx (DFmode);
14020 fp_hi = gen_reg_rtx (DFmode);
14022 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
14024 real_ldexp (&TWO32r, &dconst1, 32);
14025 x = const_double_from_real_value (TWO32r, DFmode);
14026 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
14028 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
14030 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
14033 emit_move_insn (target, x);
14036 /* Convert an unsigned SImode value into a SFmode, using only SSE.
14037 For x86_32, -mfpmath=sse, !optimize_size only. */
14039 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
14041 REAL_VALUE_TYPE ONE16r;
14042 rtx fp_hi, fp_lo, int_hi, int_lo, x;
14044 real_ldexp (&ONE16r, &dconst1, 16);
14045 x = const_double_from_real_value (ONE16r, SFmode);
14046 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
14047 NULL, 0, OPTAB_DIRECT);
14048 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
14049 NULL, 0, OPTAB_DIRECT);
14050 fp_hi = gen_reg_rtx (SFmode);
14051 fp_lo = gen_reg_rtx (SFmode);
14052 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
14053 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
14054 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
14056 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
14058 if (!rtx_equal_p (target, fp_hi))
14059 emit_move_insn (target, fp_hi);
14062 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
14063 then replicate the value for all elements of the vector
14067 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
14074 v = gen_rtvec (4, value, value, value, value);
14075 return gen_rtx_CONST_VECTOR (V4SImode, v);
14079 v = gen_rtvec (2, value, value);
14080 return gen_rtx_CONST_VECTOR (V2DImode, v);
14084 v = gen_rtvec (4, value, value, value, value);
14086 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
14087 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
14088 return gen_rtx_CONST_VECTOR (V4SFmode, v);
14092 v = gen_rtvec (2, value, value);
14094 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
14095 return gen_rtx_CONST_VECTOR (V2DFmode, v);
14098 gcc_unreachable ();
14102 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
14103 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
14104 for an SSE register. If VECT is true, then replicate the mask for
14105 all elements of the vector register. If INVERT is true, then create
14106 a mask excluding the sign bit. */
14109 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
14111 enum machine_mode vec_mode, imode;
14112 HOST_WIDE_INT hi, lo;
14117 /* Find the sign bit, sign extended to 2*HWI. */
14123 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
14124 lo = 0x80000000, hi = lo < 0;
14130 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
14131 if (HOST_BITS_PER_WIDE_INT >= 64)
14132 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
14134 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
14139 vec_mode = VOIDmode;
14140 if (HOST_BITS_PER_WIDE_INT >= 64)
14143 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
14150 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
14154 lo = ~lo, hi = ~hi;
14160 mask = immed_double_const (lo, hi, imode);
14162 vec = gen_rtvec (2, v, mask);
14163 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
14164 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
14171 gcc_unreachable ();
14175 lo = ~lo, hi = ~hi;
14177 /* Force this value into the low part of a fp vector constant. */
14178 mask = immed_double_const (lo, hi, imode);
14179 mask = gen_lowpart (mode, mask);
14181 if (vec_mode == VOIDmode)
14182 return force_reg (mode, mask);
14184 v = ix86_build_const_vector (mode, vect, mask);
14185 return force_reg (vec_mode, v);
14188 /* Generate code for floating point ABS or NEG. */
14191 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
14194 rtx mask, set, use, clob, dst, src;
14195 bool use_sse = false;
14196 bool vector_mode = VECTOR_MODE_P (mode);
14197 enum machine_mode elt_mode = mode;
14201 elt_mode = GET_MODE_INNER (mode);
14204 else if (mode == TFmode)
14206 else if (TARGET_SSE_MATH)
14207 use_sse = SSE_FLOAT_MODE_P (mode);
14209 /* NEG and ABS performed with SSE use bitwise mask operations.
14210 Create the appropriate mask now. */
14212 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14221 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14222 set = gen_rtx_SET (VOIDmode, dst, set);
14227 set = gen_rtx_fmt_e (code, mode, src);
14228 set = gen_rtx_SET (VOIDmode, dst, set);
14231 use = gen_rtx_USE (VOIDmode, mask);
14232 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14233 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14234 gen_rtvec (3, set, use, clob)));
14241 /* Expand a copysign operation. Special case operand 0 being a constant. */
14244 ix86_expand_copysign (rtx operands[])
14246 enum machine_mode mode;
14247 rtx dest, op0, op1, mask, nmask;
14249 dest = operands[0];
14253 mode = GET_MODE (dest);
14255 if (GET_CODE (op0) == CONST_DOUBLE)
14257 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14259 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14260 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14262 if (mode == SFmode || mode == DFmode)
14264 enum machine_mode vmode;
14266 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14268 if (op0 == CONST0_RTX (mode))
14269 op0 = CONST0_RTX (vmode);
14272 rtx v = ix86_build_const_vector (mode, false, op0);
14274 op0 = force_reg (vmode, v);
14277 else if (op0 != CONST0_RTX (mode))
14278 op0 = force_reg (mode, op0);
14280 mask = ix86_build_signbit_mask (mode, 0, 0);
14282 if (mode == SFmode)
14283 copysign_insn = gen_copysignsf3_const;
14284 else if (mode == DFmode)
14285 copysign_insn = gen_copysigndf3_const;
14287 copysign_insn = gen_copysigntf3_const;
14289 emit_insn (copysign_insn (dest, op0, op1, mask));
14293 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14295 nmask = ix86_build_signbit_mask (mode, 0, 1);
14296 mask = ix86_build_signbit_mask (mode, 0, 0);
14298 if (mode == SFmode)
14299 copysign_insn = gen_copysignsf3_var;
14300 else if (mode == DFmode)
14301 copysign_insn = gen_copysigndf3_var;
14303 copysign_insn = gen_copysigntf3_var;
14305 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14309 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14310 be a constant, and so has already been expanded into a vector constant. */
14313 ix86_split_copysign_const (rtx operands[])
14315 enum machine_mode mode, vmode;
14316 rtx dest, op0, mask, x;
14318 dest = operands[0];
14320 mask = operands[3];
14322 mode = GET_MODE (dest);
14323 vmode = GET_MODE (mask);
14325 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14326 x = gen_rtx_AND (vmode, dest, mask);
14327 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14329 if (op0 != CONST0_RTX (vmode))
14331 x = gen_rtx_IOR (vmode, dest, op0);
14332 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14336 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14337 so we have to do two masks. */
14340 ix86_split_copysign_var (rtx operands[])
14342 enum machine_mode mode, vmode;
14343 rtx dest, scratch, op0, op1, mask, nmask, x;
14345 dest = operands[0];
14346 scratch = operands[1];
14349 nmask = operands[4];
14350 mask = operands[5];
14352 mode = GET_MODE (dest);
14353 vmode = GET_MODE (mask);
14355 if (rtx_equal_p (op0, op1))
14357 /* Shouldn't happen often (it's useless, obviously), but when it does
14358 we'd generate incorrect code if we continue below. */
14359 emit_move_insn (dest, op0);
14363 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14365 gcc_assert (REGNO (op1) == REGNO (scratch));
14367 x = gen_rtx_AND (vmode, scratch, mask);
14368 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14371 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14372 x = gen_rtx_NOT (vmode, dest);
14373 x = gen_rtx_AND (vmode, x, op0);
14374 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14378 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14380 x = gen_rtx_AND (vmode, scratch, mask);
14382 else /* alternative 2,4 */
14384 gcc_assert (REGNO (mask) == REGNO (scratch));
14385 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14386 x = gen_rtx_AND (vmode, scratch, op1);
14388 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14390 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14392 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14393 x = gen_rtx_AND (vmode, dest, nmask);
14395 else /* alternative 3,4 */
14397 gcc_assert (REGNO (nmask) == REGNO (dest));
14399 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14400 x = gen_rtx_AND (vmode, dest, op0);
14402 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14405 x = gen_rtx_IOR (vmode, dest, scratch);
14406 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14409 /* Return TRUE or FALSE depending on whether the first SET in INSN
14410 has source and destination with matching CC modes, and that the
14411 CC mode is at least as constrained as REQ_MODE. */
14414 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14417 enum machine_mode set_mode;
14419 set = PATTERN (insn);
14420 if (GET_CODE (set) == PARALLEL)
14421 set = XVECEXP (set, 0, 0);
14422 gcc_assert (GET_CODE (set) == SET);
14423 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14425 set_mode = GET_MODE (SET_DEST (set));
14429 if (req_mode != CCNOmode
14430 && (req_mode != CCmode
14431 || XEXP (SET_SRC (set), 1) != const0_rtx))
14435 if (req_mode == CCGCmode)
14439 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14443 if (req_mode == CCZmode)
14454 gcc_unreachable ();
14457 return (GET_MODE (SET_SRC (set)) == set_mode);
14460 /* Generate insn patterns to do an integer compare of OPERANDS. */
14463 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14465 enum machine_mode cmpmode;
14468 cmpmode = SELECT_CC_MODE (code, op0, op1);
14469 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14471 /* This is very simple, but making the interface the same as in the
14472 FP case makes the rest of the code easier. */
14473 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14474 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14476 /* Return the test that should be put into the flags user, i.e.
14477 the bcc, scc, or cmov instruction. */
14478 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14481 /* Figure out whether to use ordered or unordered fp comparisons.
14482 Return the appropriate mode to use. */
14485 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14487 /* ??? In order to make all comparisons reversible, we do all comparisons
14488 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14489 all forms trapping and nontrapping comparisons, we can make inequality
14490 comparisons trapping again, since it results in better code when using
14491 FCOM based compares. */
14492 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14496 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14498 enum machine_mode mode = GET_MODE (op0);
14500 if (SCALAR_FLOAT_MODE_P (mode))
14502 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14503 return ix86_fp_compare_mode (code);
14508 /* Only zero flag is needed. */
14509 case EQ: /* ZF=0 */
14510 case NE: /* ZF!=0 */
14512 /* Codes needing carry flag. */
14513 case GEU: /* CF=0 */
14514 case LTU: /* CF=1 */
14515 /* Detect overflow checks. They need just the carry flag. */
14516 if (GET_CODE (op0) == PLUS
14517 && rtx_equal_p (op1, XEXP (op0, 0)))
14521 case GTU: /* CF=0 & ZF=0 */
14522 case LEU: /* CF=1 | ZF=1 */
14523 /* Detect overflow checks. They need just the carry flag. */
14524 if (GET_CODE (op0) == MINUS
14525 && rtx_equal_p (op1, XEXP (op0, 0)))
14529 /* Codes possibly doable only with sign flag when
14530 comparing against zero. */
14531 case GE: /* SF=OF or SF=0 */
14532 case LT: /* SF<>OF or SF=1 */
14533 if (op1 == const0_rtx)
14536 /* For other cases Carry flag is not required. */
14538 /* Codes doable only with sign flag when comparing
14539 against zero, but we miss jump instruction for it
14540 so we need to use relational tests against overflow
14541 that thus needs to be zero. */
14542 case GT: /* ZF=0 & SF=OF */
14543 case LE: /* ZF=1 | SF<>OF */
14544 if (op1 == const0_rtx)
14548 /* strcmp pattern do (use flags) and combine may ask us for proper
14553 gcc_unreachable ();
14557 /* Return the fixed registers used for condition codes. */
14560 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14567 /* If two condition code modes are compatible, return a condition code
14568 mode which is compatible with both. Otherwise, return
14571 static enum machine_mode
14572 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14577 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14580 if ((m1 == CCGCmode && m2 == CCGOCmode)
14581 || (m1 == CCGOCmode && m2 == CCGCmode))
14587 gcc_unreachable ();
14617 /* These are only compatible with themselves, which we already
14624 /* Return a comparison we can do and that it is equivalent to
14625 swap_condition (code) apart possibly from orderedness.
14626 But, never change orderedness if TARGET_IEEE_FP, returning
14627 UNKNOWN in that case if necessary. */
14629 static enum rtx_code
14630 ix86_fp_swap_condition (enum rtx_code code)
14634 case GT: /* GTU - CF=0 & ZF=0 */
14635 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
14636 case GE: /* GEU - CF=0 */
14637 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
14638 case UNLT: /* LTU - CF=1 */
14639 return TARGET_IEEE_FP ? UNKNOWN : GT;
14640 case UNLE: /* LEU - CF=1 | ZF=1 */
14641 return TARGET_IEEE_FP ? UNKNOWN : GE;
14643 return swap_condition (code);
14647 /* Return cost of comparison CODE using the best strategy for performance.
14648 All following functions do use number of instructions as a cost metrics.
14649 In future this should be tweaked to compute bytes for optimize_size and
14650 take into account performance of various instructions on various CPUs. */
14653 ix86_fp_comparison_cost (enum rtx_code code)
14657 /* The cost of code using bit-twiddling on %ah. */
14674 arith_cost = TARGET_IEEE_FP ? 5 : 4;
14678 arith_cost = TARGET_IEEE_FP ? 6 : 4;
14681 gcc_unreachable ();
14684 switch (ix86_fp_comparison_strategy (code))
14686 case IX86_FPCMP_COMI:
14687 return arith_cost > 4 ? 3 : 2;
14688 case IX86_FPCMP_SAHF:
14689 return arith_cost > 4 ? 4 : 3;
14695 /* Return strategy to use for floating-point. We assume that fcomi is always
14696 preferrable where available, since that is also true when looking at size
14697 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14699 enum ix86_fpcmp_strategy
14700 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
14702 /* Do fcomi/sahf based test when profitable. */
14705 return IX86_FPCMP_COMI;
14707 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
14708 return IX86_FPCMP_SAHF;
14710 return IX86_FPCMP_ARITH;
14713 /* Swap, force into registers, or otherwise massage the two operands
14714 to a fp comparison. The operands are updated in place; the new
14715 comparison code is returned. */
14717 static enum rtx_code
14718 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14720 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14721 rtx op0 = *pop0, op1 = *pop1;
14722 enum machine_mode op_mode = GET_MODE (op0);
14723 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14725 /* All of the unordered compare instructions only work on registers.
14726 The same is true of the fcomi compare instructions. The XFmode
14727 compare instructions require registers except when comparing
14728 against zero or when converting operand 1 from fixed point to
14732 && (fpcmp_mode == CCFPUmode
14733 || (op_mode == XFmode
14734 && ! (standard_80387_constant_p (op0) == 1
14735 || standard_80387_constant_p (op1) == 1)
14736 && GET_CODE (op1) != FLOAT)
14737 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
14739 op0 = force_reg (op_mode, op0);
14740 op1 = force_reg (op_mode, op1);
14744 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14745 things around if they appear profitable, otherwise force op0
14746 into a register. */
14748 if (standard_80387_constant_p (op0) == 0
14750 && ! (standard_80387_constant_p (op1) == 0
14753 enum rtx_code new_code = ix86_fp_swap_condition (code);
14754 if (new_code != UNKNOWN)
14757 tmp = op0, op0 = op1, op1 = tmp;
14763 op0 = force_reg (op_mode, op0);
14765 if (CONSTANT_P (op1))
14767 int tmp = standard_80387_constant_p (op1);
14769 op1 = validize_mem (force_const_mem (op_mode, op1));
14773 op1 = force_reg (op_mode, op1);
14776 op1 = force_reg (op_mode, op1);
14780 /* Try to rearrange the comparison to make it cheaper. */
14781 if (ix86_fp_comparison_cost (code)
14782 > ix86_fp_comparison_cost (swap_condition (code))
14783 && (REG_P (op1) || can_create_pseudo_p ()))
14786 tmp = op0, op0 = op1, op1 = tmp;
14787 code = swap_condition (code);
14789 op0 = force_reg (op_mode, op0);
14797 /* Convert comparison codes we use to represent FP comparison to integer
14798 code that will result in proper branch. Return UNKNOWN if no such code
14802 ix86_fp_compare_code_to_integer (enum rtx_code code)
14831 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14834 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
14836 enum machine_mode fpcmp_mode, intcmp_mode;
14839 fpcmp_mode = ix86_fp_compare_mode (code);
14840 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14842 /* Do fcomi/sahf based test when profitable. */
14843 switch (ix86_fp_comparison_strategy (code))
14845 case IX86_FPCMP_COMI:
14846 intcmp_mode = fpcmp_mode;
14847 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14848 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14853 case IX86_FPCMP_SAHF:
14854 intcmp_mode = fpcmp_mode;
14855 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14856 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14860 scratch = gen_reg_rtx (HImode);
14861 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14862 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14865 case IX86_FPCMP_ARITH:
14866 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14867 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14868 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14870 scratch = gen_reg_rtx (HImode);
14871 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14873 /* In the unordered case, we have to check C2 for NaN's, which
14874 doesn't happen to work out to anything nice combination-wise.
14875 So do some bit twiddling on the value we've got in AH to come
14876 up with an appropriate set of condition codes. */
14878 intcmp_mode = CCNOmode;
14883 if (code == GT || !TARGET_IEEE_FP)
14885 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14890 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14891 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14892 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14893 intcmp_mode = CCmode;
14899 if (code == LT && TARGET_IEEE_FP)
14901 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14902 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
14903 intcmp_mode = CCmode;
14908 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
14914 if (code == GE || !TARGET_IEEE_FP)
14916 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14921 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14922 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
14928 if (code == LE && TARGET_IEEE_FP)
14930 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14931 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14932 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14933 intcmp_mode = CCmode;
14938 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14944 if (code == EQ && TARGET_IEEE_FP)
14946 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14947 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14948 intcmp_mode = CCmode;
14953 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14959 if (code == NE && TARGET_IEEE_FP)
14961 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14962 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14968 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14974 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14978 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14983 gcc_unreachable ();
14991 /* Return the test that should be put into the flags user, i.e.
14992 the bcc, scc, or cmov instruction. */
14993 return gen_rtx_fmt_ee (code, VOIDmode,
14994 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14999 ix86_expand_compare (enum rtx_code code)
15002 op0 = ix86_compare_op0;
15003 op1 = ix86_compare_op1;
15005 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
15006 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
15008 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
15010 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
15011 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15014 ret = ix86_expand_int_compare (code, op0, op1);
15020 ix86_expand_branch (enum rtx_code code, rtx label)
15024 switch (GET_MODE (ix86_compare_op0))
15033 tmp = ix86_expand_compare (code);
15034 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15035 gen_rtx_LABEL_REF (VOIDmode, label),
15037 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
15044 /* Expand DImode branch into multiple compare+branch. */
15046 rtx lo[2], hi[2], label2;
15047 enum rtx_code code1, code2, code3;
15048 enum machine_mode submode;
15050 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
15052 tmp = ix86_compare_op0;
15053 ix86_compare_op0 = ix86_compare_op1;
15054 ix86_compare_op1 = tmp;
15055 code = swap_condition (code);
15057 if (GET_MODE (ix86_compare_op0) == DImode)
15059 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
15060 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
15065 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
15066 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
15070 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
15071 avoid two branches. This costs one extra insn, so disable when
15072 optimizing for size. */
15074 if ((code == EQ || code == NE)
15075 && (!optimize_insn_for_size_p ()
15076 || hi[1] == const0_rtx || lo[1] == const0_rtx))
15081 if (hi[1] != const0_rtx)
15082 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
15083 NULL_RTX, 0, OPTAB_WIDEN);
15086 if (lo[1] != const0_rtx)
15087 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
15088 NULL_RTX, 0, OPTAB_WIDEN);
15090 tmp = expand_binop (submode, ior_optab, xor1, xor0,
15091 NULL_RTX, 0, OPTAB_WIDEN);
15093 ix86_compare_op0 = tmp;
15094 ix86_compare_op1 = const0_rtx;
15095 ix86_expand_branch (code, label);
15099 /* Otherwise, if we are doing less-than or greater-or-equal-than,
15100 op1 is a constant and the low word is zero, then we can just
15101 examine the high word. Similarly for low word -1 and
15102 less-or-equal-than or greater-than. */
15104 if (CONST_INT_P (hi[1]))
15107 case LT: case LTU: case GE: case GEU:
15108 if (lo[1] == const0_rtx)
15110 ix86_compare_op0 = hi[0];
15111 ix86_compare_op1 = hi[1];
15112 ix86_expand_branch (code, label);
15116 case LE: case LEU: case GT: case GTU:
15117 if (lo[1] == constm1_rtx)
15119 ix86_compare_op0 = hi[0];
15120 ix86_compare_op1 = hi[1];
15121 ix86_expand_branch (code, label);
15129 /* Otherwise, we need two or three jumps. */
15131 label2 = gen_label_rtx ();
15134 code2 = swap_condition (code);
15135 code3 = unsigned_condition (code);
15139 case LT: case GT: case LTU: case GTU:
15142 case LE: code1 = LT; code2 = GT; break;
15143 case GE: code1 = GT; code2 = LT; break;
15144 case LEU: code1 = LTU; code2 = GTU; break;
15145 case GEU: code1 = GTU; code2 = LTU; break;
15147 case EQ: code1 = UNKNOWN; code2 = NE; break;
15148 case NE: code2 = UNKNOWN; break;
15151 gcc_unreachable ();
15156 * if (hi(a) < hi(b)) goto true;
15157 * if (hi(a) > hi(b)) goto false;
15158 * if (lo(a) < lo(b)) goto true;
15162 ix86_compare_op0 = hi[0];
15163 ix86_compare_op1 = hi[1];
15165 if (code1 != UNKNOWN)
15166 ix86_expand_branch (code1, label);
15167 if (code2 != UNKNOWN)
15168 ix86_expand_branch (code2, label2);
15170 ix86_compare_op0 = lo[0];
15171 ix86_compare_op1 = lo[1];
15172 ix86_expand_branch (code3, label);
15174 if (code2 != UNKNOWN)
15175 emit_label (label2);
15180 /* If we have already emitted a compare insn, go straight to simple.
15181 ix86_expand_compare won't emit anything if ix86_compare_emitted
15183 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
15188 /* Split branch based on floating point condition. */
15190 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
15191 rtx target1, rtx target2, rtx tmp, rtx pushed)
15196 if (target2 != pc_rtx)
15199 code = reverse_condition_maybe_unordered (code);
15204 condition = ix86_expand_fp_compare (code, op1, op2,
15207 /* Remove pushed operand from stack. */
15209 ix86_free_from_memory (GET_MODE (pushed));
15211 i = emit_jump_insn (gen_rtx_SET
15213 gen_rtx_IF_THEN_ELSE (VOIDmode,
15214 condition, target1, target2)));
15215 if (split_branch_probability >= 0)
15216 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
15220 ix86_expand_setcc (enum rtx_code code, rtx dest)
15224 gcc_assert (GET_MODE (dest) == QImode);
15226 ret = ix86_expand_compare (code);
15227 PUT_MODE (ret, QImode);
15228 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
15231 /* Expand comparison setting or clearing carry flag. Return true when
15232 successful and set pop for the operation. */
15234 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15236 enum machine_mode mode =
15237 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15239 /* Do not handle DImode compares that go through special path. */
15240 if (mode == (TARGET_64BIT ? TImode : DImode))
15243 if (SCALAR_FLOAT_MODE_P (mode))
15245 rtx compare_op, compare_seq;
15247 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15249 /* Shortcut: following common codes never translate
15250 into carry flag compares. */
15251 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15252 || code == ORDERED || code == UNORDERED)
15255 /* These comparisons require zero flag; swap operands so they won't. */
15256 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15257 && !TARGET_IEEE_FP)
15262 code = swap_condition (code);
15265 /* Try to expand the comparison and verify that we end up with
15266 carry flag based comparison. This fails to be true only when
15267 we decide to expand comparison using arithmetic that is not
15268 too common scenario. */
15270 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15271 compare_seq = get_insns ();
15274 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15275 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15276 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15278 code = GET_CODE (compare_op);
15280 if (code != LTU && code != GEU)
15283 emit_insn (compare_seq);
15288 if (!INTEGRAL_MODE_P (mode))
15297 /* Convert a==0 into (unsigned)a<1. */
15300 if (op1 != const0_rtx)
15303 code = (code == EQ ? LTU : GEU);
15306 /* Convert a>b into b<a or a>=b-1. */
15309 if (CONST_INT_P (op1))
15311 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15312 /* Bail out on overflow. We still can swap operands but that
15313 would force loading of the constant into register. */
15314 if (op1 == const0_rtx
15315 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15317 code = (code == GTU ? GEU : LTU);
15324 code = (code == GTU ? LTU : GEU);
15328 /* Convert a>=0 into (unsigned)a<0x80000000. */
15331 if (mode == DImode || op1 != const0_rtx)
15333 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15334 code = (code == LT ? GEU : LTU);
15338 if (mode == DImode || op1 != constm1_rtx)
15340 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15341 code = (code == LE ? GEU : LTU);
15347 /* Swapping operands may cause constant to appear as first operand. */
15348 if (!nonimmediate_operand (op0, VOIDmode))
15350 if (!can_create_pseudo_p ())
15352 op0 = force_reg (mode, op0);
15354 ix86_compare_op0 = op0;
15355 ix86_compare_op1 = op1;
15356 *pop = ix86_expand_compare (code);
15357 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15362 ix86_expand_int_movcc (rtx operands[])
15364 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15365 rtx compare_seq, compare_op;
15366 enum machine_mode mode = GET_MODE (operands[0]);
15367 bool sign_bit_compare_p = false;;
15370 ix86_compare_op0 = XEXP (operands[1], 0);
15371 ix86_compare_op1 = XEXP (operands[1], 1);
15372 compare_op = ix86_expand_compare (code);
15373 compare_seq = get_insns ();
15376 compare_code = GET_CODE (compare_op);
15378 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15379 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15380 sign_bit_compare_p = true;
15382 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15383 HImode insns, we'd be swallowed in word prefix ops. */
15385 if ((mode != HImode || TARGET_FAST_PREFIX)
15386 && (mode != (TARGET_64BIT ? TImode : DImode))
15387 && CONST_INT_P (operands[2])
15388 && CONST_INT_P (operands[3]))
15390 rtx out = operands[0];
15391 HOST_WIDE_INT ct = INTVAL (operands[2]);
15392 HOST_WIDE_INT cf = INTVAL (operands[3]);
15393 HOST_WIDE_INT diff;
15396 /* Sign bit compares are better done using shifts than we do by using
15398 if (sign_bit_compare_p
15399 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15400 ix86_compare_op1, &compare_op))
15402 /* Detect overlap between destination and compare sources. */
15405 if (!sign_bit_compare_p)
15407 bool fpcmp = false;
15409 compare_code = GET_CODE (compare_op);
15411 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15412 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15415 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15418 /* To simplify rest of code, restrict to the GEU case. */
15419 if (compare_code == LTU)
15421 HOST_WIDE_INT tmp = ct;
15424 compare_code = reverse_condition (compare_code);
15425 code = reverse_condition (code);
15430 PUT_CODE (compare_op,
15431 reverse_condition_maybe_unordered
15432 (GET_CODE (compare_op)));
15434 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15438 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15439 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15440 tmp = gen_reg_rtx (mode);
15442 if (mode == DImode)
15443 emit_insn (gen_x86_movdicc_0_m1 (tmp, compare_op));
15445 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp),
15450 if (code == GT || code == GE)
15451 code = reverse_condition (code);
15454 HOST_WIDE_INT tmp = ct;
15459 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15460 ix86_compare_op1, VOIDmode, 0, -1);
15473 tmp = expand_simple_binop (mode, PLUS,
15475 copy_rtx (tmp), 1, OPTAB_DIRECT);
15486 tmp = expand_simple_binop (mode, IOR,
15488 copy_rtx (tmp), 1, OPTAB_DIRECT);
15490 else if (diff == -1 && ct)
15500 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15502 tmp = expand_simple_binop (mode, PLUS,
15503 copy_rtx (tmp), GEN_INT (cf),
15504 copy_rtx (tmp), 1, OPTAB_DIRECT);
15512 * andl cf - ct, dest
15522 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15525 tmp = expand_simple_binop (mode, AND,
15527 gen_int_mode (cf - ct, mode),
15528 copy_rtx (tmp), 1, OPTAB_DIRECT);
15530 tmp = expand_simple_binop (mode, PLUS,
15531 copy_rtx (tmp), GEN_INT (ct),
15532 copy_rtx (tmp), 1, OPTAB_DIRECT);
15535 if (!rtx_equal_p (tmp, out))
15536 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15538 return 1; /* DONE */
15543 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15546 tmp = ct, ct = cf, cf = tmp;
15549 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15551 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15553 /* We may be reversing unordered compare to normal compare, that
15554 is not valid in general (we may convert non-trapping condition
15555 to trapping one), however on i386 we currently emit all
15556 comparisons unordered. */
15557 compare_code = reverse_condition_maybe_unordered (compare_code);
15558 code = reverse_condition_maybe_unordered (code);
15562 compare_code = reverse_condition (compare_code);
15563 code = reverse_condition (code);
15567 compare_code = UNKNOWN;
15568 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15569 && CONST_INT_P (ix86_compare_op1))
15571 if (ix86_compare_op1 == const0_rtx
15572 && (code == LT || code == GE))
15573 compare_code = code;
15574 else if (ix86_compare_op1 == constm1_rtx)
15578 else if (code == GT)
15583 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15584 if (compare_code != UNKNOWN
15585 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15586 && (cf == -1 || ct == -1))
15588 /* If lea code below could be used, only optimize
15589 if it results in a 2 insn sequence. */
15591 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15592 || diff == 3 || diff == 5 || diff == 9)
15593 || (compare_code == LT && ct == -1)
15594 || (compare_code == GE && cf == -1))
15597 * notl op1 (if necessary)
15605 code = reverse_condition (code);
15608 out = emit_store_flag (out, code, ix86_compare_op0,
15609 ix86_compare_op1, VOIDmode, 0, -1);
15611 out = expand_simple_binop (mode, IOR,
15613 out, 1, OPTAB_DIRECT);
15614 if (out != operands[0])
15615 emit_move_insn (operands[0], out);
15617 return 1; /* DONE */
15622 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15623 || diff == 3 || diff == 5 || diff == 9)
15624 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15626 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15632 * lea cf(dest*(ct-cf)),dest
15636 * This also catches the degenerate setcc-only case.
15642 out = emit_store_flag (out, code, ix86_compare_op0,
15643 ix86_compare_op1, VOIDmode, 0, 1);
15646 /* On x86_64 the lea instruction operates on Pmode, so we need
15647 to get arithmetics done in proper mode to match. */
15649 tmp = copy_rtx (out);
15653 out1 = copy_rtx (out);
15654 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15658 tmp = gen_rtx_PLUS (mode, tmp, out1);
15664 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15667 if (!rtx_equal_p (tmp, out))
15670 out = force_operand (tmp, copy_rtx (out));
15672 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15674 if (!rtx_equal_p (out, operands[0]))
15675 emit_move_insn (operands[0], copy_rtx (out));
15677 return 1; /* DONE */
15681 * General case: Jumpful:
15682 * xorl dest,dest cmpl op1, op2
15683 * cmpl op1, op2 movl ct, dest
15684 * setcc dest jcc 1f
15685 * decl dest movl cf, dest
15686 * andl (cf-ct),dest 1:
15689 * Size 20. Size 14.
15691 * This is reasonably steep, but branch mispredict costs are
15692 * high on modern cpus, so consider failing only if optimizing
15696 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15697 && BRANCH_COST (optimize_insn_for_speed_p (),
15702 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15707 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15709 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15711 /* We may be reversing unordered compare to normal compare,
15712 that is not valid in general (we may convert non-trapping
15713 condition to trapping one), however on i386 we currently
15714 emit all comparisons unordered. */
15715 code = reverse_condition_maybe_unordered (code);
15719 code = reverse_condition (code);
15720 if (compare_code != UNKNOWN)
15721 compare_code = reverse_condition (compare_code);
15725 if (compare_code != UNKNOWN)
15727 /* notl op1 (if needed)
15732 For x < 0 (resp. x <= -1) there will be no notl,
15733 so if possible swap the constants to get rid of the
15735 True/false will be -1/0 while code below (store flag
15736 followed by decrement) is 0/-1, so the constants need
15737 to be exchanged once more. */
15739 if (compare_code == GE || !cf)
15741 code = reverse_condition (code);
15746 HOST_WIDE_INT tmp = cf;
15751 out = emit_store_flag (out, code, ix86_compare_op0,
15752 ix86_compare_op1, VOIDmode, 0, -1);
15756 out = emit_store_flag (out, code, ix86_compare_op0,
15757 ix86_compare_op1, VOIDmode, 0, 1);
15759 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15760 copy_rtx (out), 1, OPTAB_DIRECT);
15763 out = expand_simple_binop (mode, AND, copy_rtx (out),
15764 gen_int_mode (cf - ct, mode),
15765 copy_rtx (out), 1, OPTAB_DIRECT);
15767 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15768 copy_rtx (out), 1, OPTAB_DIRECT);
15769 if (!rtx_equal_p (out, operands[0]))
15770 emit_move_insn (operands[0], copy_rtx (out));
15772 return 1; /* DONE */
15776 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15778 /* Try a few things more with specific constants and a variable. */
15781 rtx var, orig_out, out, tmp;
15783 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15784 return 0; /* FAIL */
15786 /* If one of the two operands is an interesting constant, load a
15787 constant with the above and mask it in with a logical operation. */
15789 if (CONST_INT_P (operands[2]))
15792 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15793 operands[3] = constm1_rtx, op = and_optab;
15794 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15795 operands[3] = const0_rtx, op = ior_optab;
15797 return 0; /* FAIL */
15799 else if (CONST_INT_P (operands[3]))
15802 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15803 operands[2] = constm1_rtx, op = and_optab;
15804 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15805 operands[2] = const0_rtx, op = ior_optab;
15807 return 0; /* FAIL */
15810 return 0; /* FAIL */
15812 orig_out = operands[0];
15813 tmp = gen_reg_rtx (mode);
15816 /* Recurse to get the constant loaded. */
15817 if (ix86_expand_int_movcc (operands) == 0)
15818 return 0; /* FAIL */
15820 /* Mask in the interesting variable. */
15821 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15823 if (!rtx_equal_p (out, orig_out))
15824 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15826 return 1; /* DONE */
15830 * For comparison with above,
15840 if (! nonimmediate_operand (operands[2], mode))
15841 operands[2] = force_reg (mode, operands[2]);
15842 if (! nonimmediate_operand (operands[3], mode))
15843 operands[3] = force_reg (mode, operands[3]);
15845 if (! register_operand (operands[2], VOIDmode)
15847 || ! register_operand (operands[3], VOIDmode)))
15848 operands[2] = force_reg (mode, operands[2]);
15851 && ! register_operand (operands[3], VOIDmode))
15852 operands[3] = force_reg (mode, operands[3]);
15854 emit_insn (compare_seq);
15855 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15856 gen_rtx_IF_THEN_ELSE (mode,
15857 compare_op, operands[2],
15860 return 1; /* DONE */
15863 /* Swap, force into registers, or otherwise massage the two operands
15864 to an sse comparison with a mask result. Thus we differ a bit from
15865 ix86_prepare_fp_compare_args which expects to produce a flags result.
15867 The DEST operand exists to help determine whether to commute commutative
15868 operators. The POP0/POP1 operands are updated in place. The new
15869 comparison code is returned, or UNKNOWN if not implementable. */
15871 static enum rtx_code
15872 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15873 rtx *pop0, rtx *pop1)
15881 /* We have no LTGT as an operator. We could implement it with
15882 NE & ORDERED, but this requires an extra temporary. It's
15883 not clear that it's worth it. */
15890 /* These are supported directly. */
15897 /* For commutative operators, try to canonicalize the destination
15898 operand to be first in the comparison - this helps reload to
15899 avoid extra moves. */
15900 if (!dest || !rtx_equal_p (dest, *pop1))
15908 /* These are not supported directly. Swap the comparison operands
15909 to transform into something that is supported. */
15913 code = swap_condition (code);
15917 gcc_unreachable ();
15923 /* Detect conditional moves that exactly match min/max operational
15924 semantics. Note that this is IEEE safe, as long as we don't
15925 interchange the operands.
15927 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15928 and TRUE if the operation is successful and instructions are emitted. */
15931 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15932 rtx cmp_op1, rtx if_true, rtx if_false)
15934 enum machine_mode mode;
15940 else if (code == UNGE)
15943 if_true = if_false;
15949 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15951 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15956 mode = GET_MODE (dest);
15958 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15959 but MODE may be a vector mode and thus not appropriate. */
15960 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15962 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15965 if_true = force_reg (mode, if_true);
15966 v = gen_rtvec (2, if_true, if_false);
15967 tmp = gen_rtx_UNSPEC (mode, v, u);
15971 code = is_min ? SMIN : SMAX;
15972 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15975 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15979 /* Expand an sse vector comparison. Return the register with the result. */
15982 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15983 rtx op_true, rtx op_false)
15985 enum machine_mode mode = GET_MODE (dest);
15988 cmp_op0 = force_reg (mode, cmp_op0);
15989 if (!nonimmediate_operand (cmp_op1, mode))
15990 cmp_op1 = force_reg (mode, cmp_op1);
15993 || reg_overlap_mentioned_p (dest, op_true)
15994 || reg_overlap_mentioned_p (dest, op_false))
15995 dest = gen_reg_rtx (mode);
15997 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15998 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16003 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
16004 operations. This is used for both scalar and vector conditional moves. */
16007 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
16009 enum machine_mode mode = GET_MODE (dest);
16012 if (op_false == CONST0_RTX (mode))
16014 op_true = force_reg (mode, op_true);
16015 x = gen_rtx_AND (mode, cmp, op_true);
16016 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16018 else if (op_true == CONST0_RTX (mode))
16020 op_false = force_reg (mode, op_false);
16021 x = gen_rtx_NOT (mode, cmp);
16022 x = gen_rtx_AND (mode, x, op_false);
16023 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16025 else if (TARGET_XOP)
16027 rtx pcmov = gen_rtx_SET (mode, dest,
16028 gen_rtx_IF_THEN_ELSE (mode, cmp,
16035 op_true = force_reg (mode, op_true);
16036 op_false = force_reg (mode, op_false);
16038 t2 = gen_reg_rtx (mode);
16040 t3 = gen_reg_rtx (mode);
16044 x = gen_rtx_AND (mode, op_true, cmp);
16045 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
16047 x = gen_rtx_NOT (mode, cmp);
16048 x = gen_rtx_AND (mode, x, op_false);
16049 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
16051 x = gen_rtx_IOR (mode, t3, t2);
16052 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
16056 /* Expand a floating-point conditional move. Return true if successful. */
16059 ix86_expand_fp_movcc (rtx operands[])
16061 enum machine_mode mode = GET_MODE (operands[0]);
16062 enum rtx_code code = GET_CODE (operands[1]);
16063 rtx tmp, compare_op;
16065 ix86_compare_op0 = XEXP (operands[1], 0);
16066 ix86_compare_op1 = XEXP (operands[1], 1);
16067 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
16069 enum machine_mode cmode;
16071 /* Since we've no cmove for sse registers, don't force bad register
16072 allocation just to gain access to it. Deny movcc when the
16073 comparison mode doesn't match the move mode. */
16074 cmode = GET_MODE (ix86_compare_op0);
16075 if (cmode == VOIDmode)
16076 cmode = GET_MODE (ix86_compare_op1);
16080 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
16082 &ix86_compare_op1);
16083 if (code == UNKNOWN)
16086 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
16087 ix86_compare_op1, operands[2],
16091 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
16092 ix86_compare_op1, operands[2], operands[3]);
16093 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
16097 /* The floating point conditional move instructions don't directly
16098 support conditions resulting from a signed integer comparison. */
16100 compare_op = ix86_expand_compare (code);
16101 if (!fcmov_comparison_operator (compare_op, VOIDmode))
16103 tmp = gen_reg_rtx (QImode);
16104 ix86_expand_setcc (code, tmp);
16106 ix86_compare_op0 = tmp;
16107 ix86_compare_op1 = const0_rtx;
16108 compare_op = ix86_expand_compare (code);
16111 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
16112 gen_rtx_IF_THEN_ELSE (mode, compare_op,
16113 operands[2], operands[3])));
16118 /* Expand a floating-point vector conditional move; a vcond operation
16119 rather than a movcc operation. */
16122 ix86_expand_fp_vcond (rtx operands[])
16124 enum rtx_code code = GET_CODE (operands[3]);
16127 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
16128 &operands[4], &operands[5]);
16129 if (code == UNKNOWN)
16132 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
16133 operands[5], operands[1], operands[2]))
16136 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
16137 operands[1], operands[2]);
16138 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
16142 /* Expand a signed/unsigned integral vector conditional move. */
16145 ix86_expand_int_vcond (rtx operands[])
16147 enum machine_mode mode = GET_MODE (operands[0]);
16148 enum rtx_code code = GET_CODE (operands[3]);
16149 bool negate = false;
16152 cop0 = operands[4];
16153 cop1 = operands[5];
16155 /* XOP supports all of the comparisons on all vector int types. */
16158 /* Canonicalize the comparison to EQ, GT, GTU. */
16169 code = reverse_condition (code);
16175 code = reverse_condition (code);
16181 code = swap_condition (code);
16182 x = cop0, cop0 = cop1, cop1 = x;
16186 gcc_unreachable ();
16189 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16190 if (mode == V2DImode)
16195 /* SSE4.1 supports EQ. */
16196 if (!TARGET_SSE4_1)
16202 /* SSE4.2 supports GT/GTU. */
16203 if (!TARGET_SSE4_2)
16208 gcc_unreachable ();
16212 /* Unsigned parallel compare is not supported by the hardware. Play some
16213 tricks to turn this into a signed comparison against 0. */
16216 cop0 = force_reg (mode, cop0);
16225 /* Perform a parallel modulo subtraction. */
16226 t1 = gen_reg_rtx (mode);
16227 emit_insn ((mode == V4SImode
16229 : gen_subv2di3) (t1, cop0, cop1));
16231 /* Extract the original sign bit of op0. */
16232 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16234 t2 = gen_reg_rtx (mode);
16235 emit_insn ((mode == V4SImode
16237 : gen_andv2di3) (t2, cop0, mask));
16239 /* XOR it back into the result of the subtraction. This results
16240 in the sign bit set iff we saw unsigned underflow. */
16241 x = gen_reg_rtx (mode);
16242 emit_insn ((mode == V4SImode
16244 : gen_xorv2di3) (x, t1, t2));
16252 /* Perform a parallel unsigned saturating subtraction. */
16253 x = gen_reg_rtx (mode);
16254 emit_insn (gen_rtx_SET (VOIDmode, x,
16255 gen_rtx_US_MINUS (mode, cop0, cop1)));
16262 gcc_unreachable ();
16266 cop1 = CONST0_RTX (mode);
16270 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16271 operands[1+negate], operands[2-negate]);
16273 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16274 operands[2-negate]);
16278 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16279 true if we should do zero extension, else sign extension. HIGH_P is
16280 true if we want the N/2 high elements, else the low elements. */
16283 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16285 enum machine_mode imode = GET_MODE (operands[1]);
16286 rtx (*unpack)(rtx, rtx, rtx);
16293 unpack = gen_vec_interleave_highv16qi;
16295 unpack = gen_vec_interleave_lowv16qi;
16299 unpack = gen_vec_interleave_highv8hi;
16301 unpack = gen_vec_interleave_lowv8hi;
16305 unpack = gen_vec_interleave_highv4si;
16307 unpack = gen_vec_interleave_lowv4si;
16310 gcc_unreachable ();
16313 dest = gen_lowpart (imode, operands[0]);
16316 se = force_reg (imode, CONST0_RTX (imode));
16318 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16319 operands[1], pc_rtx, pc_rtx);
16321 emit_insn (unpack (dest, operands[1], se));
16324 /* This function performs the same task as ix86_expand_sse_unpack,
16325 but with SSE4.1 instructions. */
16328 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16330 enum machine_mode imode = GET_MODE (operands[1]);
16331 rtx (*unpack)(rtx, rtx);
16338 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16340 unpack = gen_sse4_1_extendv8qiv8hi2;
16344 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16346 unpack = gen_sse4_1_extendv4hiv4si2;
16350 unpack = gen_sse4_1_zero_extendv2siv2di2;
16352 unpack = gen_sse4_1_extendv2siv2di2;
16355 gcc_unreachable ();
16358 dest = operands[0];
16361 /* Shift higher 8 bytes to lower 8 bytes. */
16362 src = gen_reg_rtx (imode);
16363 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16364 gen_lowpart (TImode, operands[1]),
16370 emit_insn (unpack (dest, src));
16373 /* Expand conditional increment or decrement using adb/sbb instructions.
16374 The default case using setcc followed by the conditional move can be
16375 done by generic code. */
16377 ix86_expand_int_addcc (rtx operands[])
16379 enum rtx_code code = GET_CODE (operands[1]);
16380 rtx (*insn)(rtx, rtx, rtx, rtx);
16382 rtx val = const0_rtx;
16383 bool fpcmp = false;
16384 enum machine_mode mode = GET_MODE (operands[0]);
16386 ix86_compare_op0 = XEXP (operands[1], 0);
16387 ix86_compare_op1 = XEXP (operands[1], 1);
16388 if (operands[3] != const1_rtx
16389 && operands[3] != constm1_rtx)
16391 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16392 ix86_compare_op1, &compare_op))
16394 code = GET_CODE (compare_op);
16396 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16397 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16400 code = ix86_fp_compare_code_to_integer (code);
16407 PUT_CODE (compare_op,
16408 reverse_condition_maybe_unordered
16409 (GET_CODE (compare_op)));
16411 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16413 PUT_MODE (compare_op, mode);
16415 /* Construct either adc or sbb insn. */
16416 if ((code == LTU) == (operands[3] == constm1_rtx))
16418 switch (GET_MODE (operands[0]))
16421 insn = gen_subqi3_carry;
16424 insn = gen_subhi3_carry;
16427 insn = gen_subsi3_carry;
16430 insn = gen_subdi3_carry;
16433 gcc_unreachable ();
16438 switch (GET_MODE (operands[0]))
16441 insn = gen_addqi3_carry;
16444 insn = gen_addhi3_carry;
16447 insn = gen_addsi3_carry;
16450 insn = gen_adddi3_carry;
16453 gcc_unreachable ();
16456 emit_insn (insn (operands[0], operands[2], val, compare_op));
16458 return 1; /* DONE */
16462 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16463 works for floating pointer parameters and nonoffsetable memories.
16464 For pushes, it returns just stack offsets; the values will be saved
16465 in the right order. Maximally three parts are generated. */
16468 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16473 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16475 size = (GET_MODE_SIZE (mode) + 4) / 8;
16477 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16478 gcc_assert (size >= 2 && size <= 4);
16480 /* Optimize constant pool reference to immediates. This is used by fp
16481 moves, that force all constants to memory to allow combining. */
16482 if (MEM_P (operand) && MEM_READONLY_P (operand))
16484 rtx tmp = maybe_get_pool_constant (operand);
16489 if (MEM_P (operand) && !offsettable_memref_p (operand))
16491 /* The only non-offsetable memories we handle are pushes. */
16492 int ok = push_operand (operand, VOIDmode);
16496 operand = copy_rtx (operand);
16497 PUT_MODE (operand, Pmode);
16498 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16502 if (GET_CODE (operand) == CONST_VECTOR)
16504 enum machine_mode imode = int_mode_for_mode (mode);
16505 /* Caution: if we looked through a constant pool memory above,
16506 the operand may actually have a different mode now. That's
16507 ok, since we want to pun this all the way back to an integer. */
16508 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16509 gcc_assert (operand != NULL);
16515 if (mode == DImode)
16516 split_di (&operand, 1, &parts[0], &parts[1]);
16521 if (REG_P (operand))
16523 gcc_assert (reload_completed);
16524 for (i = 0; i < size; i++)
16525 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16527 else if (offsettable_memref_p (operand))
16529 operand = adjust_address (operand, SImode, 0);
16530 parts[0] = operand;
16531 for (i = 1; i < size; i++)
16532 parts[i] = adjust_address (operand, SImode, 4 * i);
16534 else if (GET_CODE (operand) == CONST_DOUBLE)
16539 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16543 real_to_target (l, &r, mode);
16544 parts[3] = gen_int_mode (l[3], SImode);
16545 parts[2] = gen_int_mode (l[2], SImode);
16548 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16549 parts[2] = gen_int_mode (l[2], SImode);
16552 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16555 gcc_unreachable ();
16557 parts[1] = gen_int_mode (l[1], SImode);
16558 parts[0] = gen_int_mode (l[0], SImode);
16561 gcc_unreachable ();
16566 if (mode == TImode)
16567 split_ti (&operand, 1, &parts[0], &parts[1]);
16568 if (mode == XFmode || mode == TFmode)
16570 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16571 if (REG_P (operand))
16573 gcc_assert (reload_completed);
16574 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16575 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16577 else if (offsettable_memref_p (operand))
16579 operand = adjust_address (operand, DImode, 0);
16580 parts[0] = operand;
16581 parts[1] = adjust_address (operand, upper_mode, 8);
16583 else if (GET_CODE (operand) == CONST_DOUBLE)
16588 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16589 real_to_target (l, &r, mode);
16591 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16592 if (HOST_BITS_PER_WIDE_INT >= 64)
16595 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16596 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16599 parts[0] = immed_double_const (l[0], l[1], DImode);
16601 if (upper_mode == SImode)
16602 parts[1] = gen_int_mode (l[2], SImode);
16603 else if (HOST_BITS_PER_WIDE_INT >= 64)
16606 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16607 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16610 parts[1] = immed_double_const (l[2], l[3], DImode);
16613 gcc_unreachable ();
16620 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16621 Return false when normal moves are needed; true when all required
16622 insns have been emitted. Operands 2-4 contain the input values
16623 int the correct order; operands 5-7 contain the output values. */
16626 ix86_split_long_move (rtx operands[])
16631 int collisions = 0;
16632 enum machine_mode mode = GET_MODE (operands[0]);
16633 bool collisionparts[4];
16635 /* The DFmode expanders may ask us to move double.
16636 For 64bit target this is single move. By hiding the fact
16637 here we simplify i386.md splitters. */
16638 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16640 /* Optimize constant pool reference to immediates. This is used by
16641 fp moves, that force all constants to memory to allow combining. */
16643 if (MEM_P (operands[1])
16644 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16645 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16646 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16647 if (push_operand (operands[0], VOIDmode))
16649 operands[0] = copy_rtx (operands[0]);
16650 PUT_MODE (operands[0], Pmode);
16653 operands[0] = gen_lowpart (DImode, operands[0]);
16654 operands[1] = gen_lowpart (DImode, operands[1]);
16655 emit_move_insn (operands[0], operands[1]);
16659 /* The only non-offsettable memory we handle is push. */
16660 if (push_operand (operands[0], VOIDmode))
16663 gcc_assert (!MEM_P (operands[0])
16664 || offsettable_memref_p (operands[0]));
16666 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16667 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16669 /* When emitting push, take care for source operands on the stack. */
16670 if (push && MEM_P (operands[1])
16671 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16673 rtx src_base = XEXP (part[1][nparts - 1], 0);
16675 /* Compensate for the stack decrement by 4. */
16676 if (!TARGET_64BIT && nparts == 3
16677 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16678 src_base = plus_constant (src_base, 4);
16680 /* src_base refers to the stack pointer and is
16681 automatically decreased by emitted push. */
16682 for (i = 0; i < nparts; i++)
16683 part[1][i] = change_address (part[1][i],
16684 GET_MODE (part[1][i]), src_base);
16687 /* We need to do copy in the right order in case an address register
16688 of the source overlaps the destination. */
16689 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16693 for (i = 0; i < nparts; i++)
16696 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16697 if (collisionparts[i])
16701 /* Collision in the middle part can be handled by reordering. */
16702 if (collisions == 1 && nparts == 3 && collisionparts [1])
16704 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16705 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16707 else if (collisions == 1
16709 && (collisionparts [1] || collisionparts [2]))
16711 if (collisionparts [1])
16713 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16714 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16718 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16719 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16723 /* If there are more collisions, we can't handle it by reordering.
16724 Do an lea to the last part and use only one colliding move. */
16725 else if (collisions > 1)
16731 base = part[0][nparts - 1];
16733 /* Handle the case when the last part isn't valid for lea.
16734 Happens in 64-bit mode storing the 12-byte XFmode. */
16735 if (GET_MODE (base) != Pmode)
16736 base = gen_rtx_REG (Pmode, REGNO (base));
16738 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16739 part[1][0] = replace_equiv_address (part[1][0], base);
16740 for (i = 1; i < nparts; i++)
16742 tmp = plus_constant (base, UNITS_PER_WORD * i);
16743 part[1][i] = replace_equiv_address (part[1][i], tmp);
16754 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16755 emit_insn (gen_addsi3 (stack_pointer_rtx,
16756 stack_pointer_rtx, GEN_INT (-4)));
16757 emit_move_insn (part[0][2], part[1][2]);
16759 else if (nparts == 4)
16761 emit_move_insn (part[0][3], part[1][3]);
16762 emit_move_insn (part[0][2], part[1][2]);
16767 /* In 64bit mode we don't have 32bit push available. In case this is
16768 register, it is OK - we will just use larger counterpart. We also
16769 retype memory - these comes from attempt to avoid REX prefix on
16770 moving of second half of TFmode value. */
16771 if (GET_MODE (part[1][1]) == SImode)
16773 switch (GET_CODE (part[1][1]))
16776 part[1][1] = adjust_address (part[1][1], DImode, 0);
16780 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16784 gcc_unreachable ();
16787 if (GET_MODE (part[1][0]) == SImode)
16788 part[1][0] = part[1][1];
16791 emit_move_insn (part[0][1], part[1][1]);
16792 emit_move_insn (part[0][0], part[1][0]);
16796 /* Choose correct order to not overwrite the source before it is copied. */
16797 if ((REG_P (part[0][0])
16798 && REG_P (part[1][1])
16799 && (REGNO (part[0][0]) == REGNO (part[1][1])
16801 && REGNO (part[0][0]) == REGNO (part[1][2]))
16803 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16805 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16807 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16809 operands[2 + i] = part[0][j];
16810 operands[6 + i] = part[1][j];
16815 for (i = 0; i < nparts; i++)
16817 operands[2 + i] = part[0][i];
16818 operands[6 + i] = part[1][i];
16822 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16823 if (optimize_insn_for_size_p ())
16825 for (j = 0; j < nparts - 1; j++)
16826 if (CONST_INT_P (operands[6 + j])
16827 && operands[6 + j] != const0_rtx
16828 && REG_P (operands[2 + j]))
16829 for (i = j; i < nparts - 1; i++)
16830 if (CONST_INT_P (operands[7 + i])
16831 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16832 operands[7 + i] = operands[2 + j];
16835 for (i = 0; i < nparts; i++)
16836 emit_move_insn (operands[2 + i], operands[6 + i]);
16841 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16842 left shift by a constant, either using a single shift or
16843 a sequence of add instructions. */
16846 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16850 emit_insn ((mode == DImode
16852 : gen_adddi3) (operand, operand, operand));
16854 else if (!optimize_insn_for_size_p ()
16855 && count * ix86_cost->add <= ix86_cost->shift_const)
16858 for (i=0; i<count; i++)
16860 emit_insn ((mode == DImode
16862 : gen_adddi3) (operand, operand, operand));
16866 emit_insn ((mode == DImode
16868 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16872 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16874 rtx low[2], high[2];
16876 const int single_width = mode == DImode ? 32 : 64;
16878 if (CONST_INT_P (operands[2]))
16880 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16881 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16883 if (count >= single_width)
16885 emit_move_insn (high[0], low[1]);
16886 emit_move_insn (low[0], const0_rtx);
16888 if (count > single_width)
16889 ix86_expand_ashl_const (high[0], count - single_width, mode);
16893 if (!rtx_equal_p (operands[0], operands[1]))
16894 emit_move_insn (operands[0], operands[1]);
16895 emit_insn ((mode == DImode
16897 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16898 ix86_expand_ashl_const (low[0], count, mode);
16903 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16905 if (operands[1] == const1_rtx)
16907 /* Assuming we've chosen a QImode capable registers, then 1 << N
16908 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16909 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16911 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16913 ix86_expand_clear (low[0]);
16914 ix86_expand_clear (high[0]);
16915 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16917 d = gen_lowpart (QImode, low[0]);
16918 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16919 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16920 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16922 d = gen_lowpart (QImode, high[0]);
16923 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16924 s = gen_rtx_NE (QImode, flags, const0_rtx);
16925 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16928 /* Otherwise, we can get the same results by manually performing
16929 a bit extract operation on bit 5/6, and then performing the two
16930 shifts. The two methods of getting 0/1 into low/high are exactly
16931 the same size. Avoiding the shift in the bit extract case helps
16932 pentium4 a bit; no one else seems to care much either way. */
16937 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16938 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16940 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16941 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16943 emit_insn ((mode == DImode
16945 : gen_lshrdi3) (high[0], high[0],
16946 GEN_INT (mode == DImode ? 5 : 6)));
16947 emit_insn ((mode == DImode
16949 : gen_anddi3) (high[0], high[0], const1_rtx));
16950 emit_move_insn (low[0], high[0]);
16951 emit_insn ((mode == DImode
16953 : gen_xordi3) (low[0], low[0], const1_rtx));
16956 emit_insn ((mode == DImode
16958 : gen_ashldi3) (low[0], low[0], operands[2]));
16959 emit_insn ((mode == DImode
16961 : gen_ashldi3) (high[0], high[0], operands[2]));
16965 if (operands[1] == constm1_rtx)
16967 /* For -1 << N, we can avoid the shld instruction, because we
16968 know that we're shifting 0...31/63 ones into a -1. */
16969 emit_move_insn (low[0], constm1_rtx);
16970 if (optimize_insn_for_size_p ())
16971 emit_move_insn (high[0], low[0]);
16973 emit_move_insn (high[0], constm1_rtx);
16977 if (!rtx_equal_p (operands[0], operands[1]))
16978 emit_move_insn (operands[0], operands[1]);
16980 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16981 emit_insn ((mode == DImode
16983 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16986 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16988 if (TARGET_CMOVE && scratch)
16990 ix86_expand_clear (scratch);
16991 emit_insn ((mode == DImode
16992 ? gen_x86_shift_adj_1
16993 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16997 emit_insn ((mode == DImode
16998 ? gen_x86_shift_adj_2
16999 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
17003 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
17005 rtx low[2], high[2];
17007 const int single_width = mode == DImode ? 32 : 64;
17009 if (CONST_INT_P (operands[2]))
17011 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17012 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17014 if (count == single_width * 2 - 1)
17016 emit_move_insn (high[0], high[1]);
17017 emit_insn ((mode == DImode
17019 : gen_ashrdi3) (high[0], high[0],
17020 GEN_INT (single_width - 1)));
17021 emit_move_insn (low[0], high[0]);
17024 else if (count >= single_width)
17026 emit_move_insn (low[0], high[1]);
17027 emit_move_insn (high[0], low[0]);
17028 emit_insn ((mode == DImode
17030 : gen_ashrdi3) (high[0], high[0],
17031 GEN_INT (single_width - 1)));
17032 if (count > single_width)
17033 emit_insn ((mode == DImode
17035 : gen_ashrdi3) (low[0], low[0],
17036 GEN_INT (count - single_width)));
17040 if (!rtx_equal_p (operands[0], operands[1]))
17041 emit_move_insn (operands[0], operands[1]);
17042 emit_insn ((mode == DImode
17044 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17045 emit_insn ((mode == DImode
17047 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
17052 if (!rtx_equal_p (operands[0], operands[1]))
17053 emit_move_insn (operands[0], operands[1]);
17055 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17057 emit_insn ((mode == DImode
17059 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17060 emit_insn ((mode == DImode
17062 : gen_ashrdi3) (high[0], high[0], operands[2]));
17064 if (TARGET_CMOVE && scratch)
17066 emit_move_insn (scratch, high[0]);
17067 emit_insn ((mode == DImode
17069 : gen_ashrdi3) (scratch, scratch,
17070 GEN_INT (single_width - 1)));
17071 emit_insn ((mode == DImode
17072 ? gen_x86_shift_adj_1
17073 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17077 emit_insn ((mode == DImode
17078 ? gen_x86_shift_adj_3
17079 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
17084 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
17086 rtx low[2], high[2];
17088 const int single_width = mode == DImode ? 32 : 64;
17090 if (CONST_INT_P (operands[2]))
17092 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
17093 count = INTVAL (operands[2]) & (single_width * 2 - 1);
17095 if (count >= single_width)
17097 emit_move_insn (low[0], high[1]);
17098 ix86_expand_clear (high[0]);
17100 if (count > single_width)
17101 emit_insn ((mode == DImode
17103 : gen_lshrdi3) (low[0], low[0],
17104 GEN_INT (count - single_width)));
17108 if (!rtx_equal_p (operands[0], operands[1]))
17109 emit_move_insn (operands[0], operands[1]);
17110 emit_insn ((mode == DImode
17112 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
17113 emit_insn ((mode == DImode
17115 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
17120 if (!rtx_equal_p (operands[0], operands[1]))
17121 emit_move_insn (operands[0], operands[1]);
17123 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
17125 emit_insn ((mode == DImode
17127 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
17128 emit_insn ((mode == DImode
17130 : gen_lshrdi3) (high[0], high[0], operands[2]));
17132 /* Heh. By reversing the arguments, we can reuse this pattern. */
17133 if (TARGET_CMOVE && scratch)
17135 ix86_expand_clear (scratch);
17136 emit_insn ((mode == DImode
17137 ? gen_x86_shift_adj_1
17138 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
17142 emit_insn ((mode == DImode
17143 ? gen_x86_shift_adj_2
17144 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
17148 /* Predict just emitted jump instruction to be taken with probability PROB. */
17150 predict_jump (int prob)
17152 rtx insn = get_last_insn ();
17153 gcc_assert (JUMP_P (insn));
17154 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
17157 /* Helper function for the string operations below. Dest VARIABLE whether
17158 it is aligned to VALUE bytes. If true, jump to the label. */
17160 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
17162 rtx label = gen_label_rtx ();
17163 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
17164 if (GET_MODE (variable) == DImode)
17165 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
17167 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
17168 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
17171 predict_jump (REG_BR_PROB_BASE * 50 / 100);
17173 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17177 /* Adjust COUNTER by the VALUE. */
17179 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
17181 if (GET_MODE (countreg) == DImode)
17182 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
17184 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
17187 /* Zero extend possibly SImode EXP to Pmode register. */
17189 ix86_zero_extend_to_Pmode (rtx exp)
17192 if (GET_MODE (exp) == VOIDmode)
17193 return force_reg (Pmode, exp);
17194 if (GET_MODE (exp) == Pmode)
17195 return copy_to_mode_reg (Pmode, exp);
17196 r = gen_reg_rtx (Pmode);
17197 emit_insn (gen_zero_extendsidi2 (r, exp));
17201 /* Divide COUNTREG by SCALE. */
17203 scale_counter (rtx countreg, int scale)
17209 if (CONST_INT_P (countreg))
17210 return GEN_INT (INTVAL (countreg) / scale);
17211 gcc_assert (REG_P (countreg));
17213 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17214 GEN_INT (exact_log2 (scale)),
17215 NULL, 1, OPTAB_DIRECT);
17219 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17220 DImode for constant loop counts. */
17222 static enum machine_mode
17223 counter_mode (rtx count_exp)
17225 if (GET_MODE (count_exp) != VOIDmode)
17226 return GET_MODE (count_exp);
17227 if (!CONST_INT_P (count_exp))
17229 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17234 /* When SRCPTR is non-NULL, output simple loop to move memory
17235 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17236 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17237 equivalent loop to set memory by VALUE (supposed to be in MODE).
17239 The size is rounded down to whole number of chunk size moved at once.
17240 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17244 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17245 rtx destptr, rtx srcptr, rtx value,
17246 rtx count, enum machine_mode mode, int unroll,
17249 rtx out_label, top_label, iter, tmp;
17250 enum machine_mode iter_mode = counter_mode (count);
17251 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17252 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17258 top_label = gen_label_rtx ();
17259 out_label = gen_label_rtx ();
17260 iter = gen_reg_rtx (iter_mode);
17262 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17263 NULL, 1, OPTAB_DIRECT);
17264 /* Those two should combine. */
17265 if (piece_size == const1_rtx)
17267 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17269 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17271 emit_move_insn (iter, const0_rtx);
17273 emit_label (top_label);
17275 tmp = convert_modes (Pmode, iter_mode, iter, true);
17276 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17277 destmem = change_address (destmem, mode, x_addr);
17281 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17282 srcmem = change_address (srcmem, mode, y_addr);
17284 /* When unrolling for chips that reorder memory reads and writes,
17285 we can save registers by using single temporary.
17286 Also using 4 temporaries is overkill in 32bit mode. */
17287 if (!TARGET_64BIT && 0)
17289 for (i = 0; i < unroll; i++)
17294 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17296 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17298 emit_move_insn (destmem, srcmem);
17304 gcc_assert (unroll <= 4);
17305 for (i = 0; i < unroll; i++)
17307 tmpreg[i] = gen_reg_rtx (mode);
17311 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17313 emit_move_insn (tmpreg[i], srcmem);
17315 for (i = 0; i < unroll; i++)
17320 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17322 emit_move_insn (destmem, tmpreg[i]);
17327 for (i = 0; i < unroll; i++)
17331 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17332 emit_move_insn (destmem, value);
17335 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17336 true, OPTAB_LIB_WIDEN);
17338 emit_move_insn (iter, tmp);
17340 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17342 if (expected_size != -1)
17344 expected_size /= GET_MODE_SIZE (mode) * unroll;
17345 if (expected_size == 0)
17347 else if (expected_size > REG_BR_PROB_BASE)
17348 predict_jump (REG_BR_PROB_BASE - 1);
17350 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17353 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17354 iter = ix86_zero_extend_to_Pmode (iter);
17355 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17356 true, OPTAB_LIB_WIDEN);
17357 if (tmp != destptr)
17358 emit_move_insn (destptr, tmp);
17361 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17362 true, OPTAB_LIB_WIDEN);
17364 emit_move_insn (srcptr, tmp);
17366 emit_label (out_label);
17369 /* Output "rep; mov" instruction.
17370 Arguments have same meaning as for previous function */
17372 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17373 rtx destptr, rtx srcptr,
17375 enum machine_mode mode)
17381 /* If the size is known, it is shorter to use rep movs. */
17382 if (mode == QImode && CONST_INT_P (count)
17383 && !(INTVAL (count) & 3))
17386 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17387 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17388 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17389 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17390 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17391 if (mode != QImode)
17393 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17394 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17395 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17396 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17397 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17398 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17402 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17403 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17405 if (CONST_INT_P (count))
17407 count = GEN_INT (INTVAL (count)
17408 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17409 destmem = shallow_copy_rtx (destmem);
17410 srcmem = shallow_copy_rtx (srcmem);
17411 set_mem_size (destmem, count);
17412 set_mem_size (srcmem, count);
17416 if (MEM_SIZE (destmem))
17417 set_mem_size (destmem, NULL_RTX);
17418 if (MEM_SIZE (srcmem))
17419 set_mem_size (srcmem, NULL_RTX);
17421 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17425 /* Output "rep; stos" instruction.
17426 Arguments have same meaning as for previous function */
17428 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17429 rtx count, enum machine_mode mode,
17435 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17436 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17437 value = force_reg (mode, gen_lowpart (mode, value));
17438 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17439 if (mode != QImode)
17441 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17442 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17443 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17446 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17447 if (orig_value == const0_rtx && CONST_INT_P (count))
17449 count = GEN_INT (INTVAL (count)
17450 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17451 destmem = shallow_copy_rtx (destmem);
17452 set_mem_size (destmem, count);
17454 else if (MEM_SIZE (destmem))
17455 set_mem_size (destmem, NULL_RTX);
17456 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17460 emit_strmov (rtx destmem, rtx srcmem,
17461 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17463 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17464 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17465 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17468 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17470 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17471 rtx destptr, rtx srcptr, rtx count, int max_size)
17474 if (CONST_INT_P (count))
17476 HOST_WIDE_INT countval = INTVAL (count);
17479 if ((countval & 0x10) && max_size > 16)
17483 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17484 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17487 gcc_unreachable ();
17490 if ((countval & 0x08) && max_size > 8)
17493 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17496 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17497 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17501 if ((countval & 0x04) && max_size > 4)
17503 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17506 if ((countval & 0x02) && max_size > 2)
17508 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17511 if ((countval & 0x01) && max_size > 1)
17513 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17520 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17521 count, 1, OPTAB_DIRECT);
17522 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17523 count, QImode, 1, 4);
17527 /* When there are stringops, we can cheaply increase dest and src pointers.
17528 Otherwise we save code size by maintaining offset (zero is readily
17529 available from preceding rep operation) and using x86 addressing modes.
17531 if (TARGET_SINGLE_STRINGOP)
17535 rtx label = ix86_expand_aligntest (count, 4, true);
17536 src = change_address (srcmem, SImode, srcptr);
17537 dest = change_address (destmem, SImode, destptr);
17538 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17539 emit_label (label);
17540 LABEL_NUSES (label) = 1;
17544 rtx label = ix86_expand_aligntest (count, 2, true);
17545 src = change_address (srcmem, HImode, srcptr);
17546 dest = change_address (destmem, HImode, destptr);
17547 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17548 emit_label (label);
17549 LABEL_NUSES (label) = 1;
17553 rtx label = ix86_expand_aligntest (count, 1, true);
17554 src = change_address (srcmem, QImode, srcptr);
17555 dest = change_address (destmem, QImode, destptr);
17556 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17557 emit_label (label);
17558 LABEL_NUSES (label) = 1;
17563 rtx offset = force_reg (Pmode, const0_rtx);
17568 rtx label = ix86_expand_aligntest (count, 4, true);
17569 src = change_address (srcmem, SImode, srcptr);
17570 dest = change_address (destmem, SImode, destptr);
17571 emit_move_insn (dest, src);
17572 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17573 true, OPTAB_LIB_WIDEN);
17575 emit_move_insn (offset, tmp);
17576 emit_label (label);
17577 LABEL_NUSES (label) = 1;
17581 rtx label = ix86_expand_aligntest (count, 2, true);
17582 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17583 src = change_address (srcmem, HImode, tmp);
17584 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17585 dest = change_address (destmem, HImode, tmp);
17586 emit_move_insn (dest, src);
17587 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17588 true, OPTAB_LIB_WIDEN);
17590 emit_move_insn (offset, tmp);
17591 emit_label (label);
17592 LABEL_NUSES (label) = 1;
17596 rtx label = ix86_expand_aligntest (count, 1, true);
17597 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17598 src = change_address (srcmem, QImode, tmp);
17599 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17600 dest = change_address (destmem, QImode, tmp);
17601 emit_move_insn (dest, src);
17602 emit_label (label);
17603 LABEL_NUSES (label) = 1;
17608 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17610 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17611 rtx count, int max_size)
17614 expand_simple_binop (counter_mode (count), AND, count,
17615 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17616 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17617 gen_lowpart (QImode, value), count, QImode,
17621 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17623 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17627 if (CONST_INT_P (count))
17629 HOST_WIDE_INT countval = INTVAL (count);
17632 if ((countval & 0x10) && max_size > 16)
17636 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17637 emit_insn (gen_strset (destptr, dest, value));
17638 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17639 emit_insn (gen_strset (destptr, dest, value));
17642 gcc_unreachable ();
17645 if ((countval & 0x08) && max_size > 8)
17649 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17650 emit_insn (gen_strset (destptr, dest, value));
17654 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17655 emit_insn (gen_strset (destptr, dest, value));
17656 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17657 emit_insn (gen_strset (destptr, dest, value));
17661 if ((countval & 0x04) && max_size > 4)
17663 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17664 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17667 if ((countval & 0x02) && max_size > 2)
17669 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17670 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17673 if ((countval & 0x01) && max_size > 1)
17675 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17676 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17683 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17688 rtx label = ix86_expand_aligntest (count, 16, true);
17691 dest = change_address (destmem, DImode, destptr);
17692 emit_insn (gen_strset (destptr, dest, value));
17693 emit_insn (gen_strset (destptr, dest, value));
17697 dest = change_address (destmem, SImode, destptr);
17698 emit_insn (gen_strset (destptr, dest, value));
17699 emit_insn (gen_strset (destptr, dest, value));
17700 emit_insn (gen_strset (destptr, dest, value));
17701 emit_insn (gen_strset (destptr, dest, value));
17703 emit_label (label);
17704 LABEL_NUSES (label) = 1;
17708 rtx label = ix86_expand_aligntest (count, 8, true);
17711 dest = change_address (destmem, DImode, destptr);
17712 emit_insn (gen_strset (destptr, dest, value));
17716 dest = change_address (destmem, SImode, destptr);
17717 emit_insn (gen_strset (destptr, dest, value));
17718 emit_insn (gen_strset (destptr, dest, value));
17720 emit_label (label);
17721 LABEL_NUSES (label) = 1;
17725 rtx label = ix86_expand_aligntest (count, 4, true);
17726 dest = change_address (destmem, SImode, destptr);
17727 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17728 emit_label (label);
17729 LABEL_NUSES (label) = 1;
17733 rtx label = ix86_expand_aligntest (count, 2, true);
17734 dest = change_address (destmem, HImode, destptr);
17735 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17736 emit_label (label);
17737 LABEL_NUSES (label) = 1;
17741 rtx label = ix86_expand_aligntest (count, 1, true);
17742 dest = change_address (destmem, QImode, destptr);
17743 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17744 emit_label (label);
17745 LABEL_NUSES (label) = 1;
17749 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17750 DESIRED_ALIGNMENT. */
17752 expand_movmem_prologue (rtx destmem, rtx srcmem,
17753 rtx destptr, rtx srcptr, rtx count,
17754 int align, int desired_alignment)
17756 if (align <= 1 && desired_alignment > 1)
17758 rtx label = ix86_expand_aligntest (destptr, 1, false);
17759 srcmem = change_address (srcmem, QImode, srcptr);
17760 destmem = change_address (destmem, QImode, destptr);
17761 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17762 ix86_adjust_counter (count, 1);
17763 emit_label (label);
17764 LABEL_NUSES (label) = 1;
17766 if (align <= 2 && desired_alignment > 2)
17768 rtx label = ix86_expand_aligntest (destptr, 2, false);
17769 srcmem = change_address (srcmem, HImode, srcptr);
17770 destmem = change_address (destmem, HImode, destptr);
17771 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17772 ix86_adjust_counter (count, 2);
17773 emit_label (label);
17774 LABEL_NUSES (label) = 1;
17776 if (align <= 4 && desired_alignment > 4)
17778 rtx label = ix86_expand_aligntest (destptr, 4, false);
17779 srcmem = change_address (srcmem, SImode, srcptr);
17780 destmem = change_address (destmem, SImode, destptr);
17781 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17782 ix86_adjust_counter (count, 4);
17783 emit_label (label);
17784 LABEL_NUSES (label) = 1;
17786 gcc_assert (desired_alignment <= 8);
17789 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17790 ALIGN_BYTES is how many bytes need to be copied. */
17792 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17793 int desired_align, int align_bytes)
17796 rtx src_size, dst_size;
17798 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17799 if (src_align_bytes >= 0)
17800 src_align_bytes = desired_align - src_align_bytes;
17801 src_size = MEM_SIZE (src);
17802 dst_size = MEM_SIZE (dst);
17803 if (align_bytes & 1)
17805 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17806 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17808 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17810 if (align_bytes & 2)
17812 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17813 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17814 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17815 set_mem_align (dst, 2 * BITS_PER_UNIT);
17816 if (src_align_bytes >= 0
17817 && (src_align_bytes & 1) == (align_bytes & 1)
17818 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17819 set_mem_align (src, 2 * BITS_PER_UNIT);
17821 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17823 if (align_bytes & 4)
17825 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17826 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17827 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17828 set_mem_align (dst, 4 * BITS_PER_UNIT);
17829 if (src_align_bytes >= 0)
17831 unsigned int src_align = 0;
17832 if ((src_align_bytes & 3) == (align_bytes & 3))
17834 else if ((src_align_bytes & 1) == (align_bytes & 1))
17836 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17837 set_mem_align (src, src_align * BITS_PER_UNIT);
17840 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17842 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17843 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17844 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17845 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17846 if (src_align_bytes >= 0)
17848 unsigned int src_align = 0;
17849 if ((src_align_bytes & 7) == (align_bytes & 7))
17851 else if ((src_align_bytes & 3) == (align_bytes & 3))
17853 else if ((src_align_bytes & 1) == (align_bytes & 1))
17855 if (src_align > (unsigned int) desired_align)
17856 src_align = desired_align;
17857 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17858 set_mem_align (src, src_align * BITS_PER_UNIT);
17861 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17863 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17868 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17869 DESIRED_ALIGNMENT. */
17871 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17872 int align, int desired_alignment)
17874 if (align <= 1 && desired_alignment > 1)
17876 rtx label = ix86_expand_aligntest (destptr, 1, false);
17877 destmem = change_address (destmem, QImode, destptr);
17878 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17879 ix86_adjust_counter (count, 1);
17880 emit_label (label);
17881 LABEL_NUSES (label) = 1;
17883 if (align <= 2 && desired_alignment > 2)
17885 rtx label = ix86_expand_aligntest (destptr, 2, false);
17886 destmem = change_address (destmem, HImode, destptr);
17887 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17888 ix86_adjust_counter (count, 2);
17889 emit_label (label);
17890 LABEL_NUSES (label) = 1;
17892 if (align <= 4 && desired_alignment > 4)
17894 rtx label = ix86_expand_aligntest (destptr, 4, false);
17895 destmem = change_address (destmem, SImode, destptr);
17896 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17897 ix86_adjust_counter (count, 4);
17898 emit_label (label);
17899 LABEL_NUSES (label) = 1;
17901 gcc_assert (desired_alignment <= 8);
17904 /* Set enough from DST to align DST known to by aligned by ALIGN to
17905 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17907 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17908 int desired_align, int align_bytes)
17911 rtx dst_size = MEM_SIZE (dst);
17912 if (align_bytes & 1)
17914 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17916 emit_insn (gen_strset (destreg, dst,
17917 gen_lowpart (QImode, value)));
17919 if (align_bytes & 2)
17921 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17922 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17923 set_mem_align (dst, 2 * BITS_PER_UNIT);
17925 emit_insn (gen_strset (destreg, dst,
17926 gen_lowpart (HImode, value)));
17928 if (align_bytes & 4)
17930 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17931 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17932 set_mem_align (dst, 4 * BITS_PER_UNIT);
17934 emit_insn (gen_strset (destreg, dst,
17935 gen_lowpart (SImode, value)));
17937 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17938 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17939 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17941 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17945 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17946 static enum stringop_alg
17947 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17948 int *dynamic_check)
17950 const struct stringop_algs * algs;
17951 bool optimize_for_speed;
17952 /* Algorithms using the rep prefix want at least edi and ecx;
17953 additionally, memset wants eax and memcpy wants esi. Don't
17954 consider such algorithms if the user has appropriated those
17955 registers for their own purposes. */
17956 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17958 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17960 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17961 || (alg != rep_prefix_1_byte \
17962 && alg != rep_prefix_4_byte \
17963 && alg != rep_prefix_8_byte))
17964 const struct processor_costs *cost;
17966 /* Even if the string operation call is cold, we still might spend a lot
17967 of time processing large blocks. */
17968 if (optimize_function_for_size_p (cfun)
17969 || (optimize_insn_for_size_p ()
17970 && expected_size != -1 && expected_size < 256))
17971 optimize_for_speed = false;
17973 optimize_for_speed = true;
17975 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17977 *dynamic_check = -1;
17979 algs = &cost->memset[TARGET_64BIT != 0];
17981 algs = &cost->memcpy[TARGET_64BIT != 0];
17982 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17983 return stringop_alg;
17984 /* rep; movq or rep; movl is the smallest variant. */
17985 else if (!optimize_for_speed)
17987 if (!count || (count & 3))
17988 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17990 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17992 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17994 else if (expected_size != -1 && expected_size < 4)
17995 return loop_1_byte;
17996 else if (expected_size != -1)
17999 enum stringop_alg alg = libcall;
18000 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18002 /* We get here if the algorithms that were not libcall-based
18003 were rep-prefix based and we are unable to use rep prefixes
18004 based on global register usage. Break out of the loop and
18005 use the heuristic below. */
18006 if (algs->size[i].max == 0)
18008 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
18010 enum stringop_alg candidate = algs->size[i].alg;
18012 if (candidate != libcall && ALG_USABLE_P (candidate))
18014 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
18015 last non-libcall inline algorithm. */
18016 if (TARGET_INLINE_ALL_STRINGOPS)
18018 /* When the current size is best to be copied by a libcall,
18019 but we are still forced to inline, run the heuristic below
18020 that will pick code for medium sized blocks. */
18021 if (alg != libcall)
18025 else if (ALG_USABLE_P (candidate))
18029 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
18031 /* When asked to inline the call anyway, try to pick meaningful choice.
18032 We look for maximal size of block that is faster to copy by hand and
18033 take blocks of at most of that size guessing that average size will
18034 be roughly half of the block.
18036 If this turns out to be bad, we might simply specify the preferred
18037 choice in ix86_costs. */
18038 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18039 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
18042 enum stringop_alg alg;
18044 bool any_alg_usable_p = true;
18046 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
18048 enum stringop_alg candidate = algs->size[i].alg;
18049 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
18051 if (candidate != libcall && candidate
18052 && ALG_USABLE_P (candidate))
18053 max = algs->size[i].max;
18055 /* If there aren't any usable algorithms, then recursing on
18056 smaller sizes isn't going to find anything. Just return the
18057 simple byte-at-a-time copy loop. */
18058 if (!any_alg_usable_p)
18060 /* Pick something reasonable. */
18061 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18062 *dynamic_check = 128;
18063 return loop_1_byte;
18067 alg = decide_alg (count, max / 2, memset, dynamic_check);
18068 gcc_assert (*dynamic_check == -1);
18069 gcc_assert (alg != libcall);
18070 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
18071 *dynamic_check = max;
18074 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
18075 #undef ALG_USABLE_P
18078 /* Decide on alignment. We know that the operand is already aligned to ALIGN
18079 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
18081 decide_alignment (int align,
18082 enum stringop_alg alg,
18085 int desired_align = 0;
18089 gcc_unreachable ();
18091 case unrolled_loop:
18092 desired_align = GET_MODE_SIZE (Pmode);
18094 case rep_prefix_8_byte:
18097 case rep_prefix_4_byte:
18098 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18099 copying whole cacheline at once. */
18100 if (TARGET_PENTIUMPRO)
18105 case rep_prefix_1_byte:
18106 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
18107 copying whole cacheline at once. */
18108 if (TARGET_PENTIUMPRO)
18122 if (desired_align < align)
18123 desired_align = align;
18124 if (expected_size != -1 && expected_size < 4)
18125 desired_align = align;
18126 return desired_align;
18129 /* Return the smallest power of 2 greater than VAL. */
18131 smallest_pow2_greater_than (int val)
18139 /* Expand string move (memcpy) operation. Use i386 string operations when
18140 profitable. expand_setmem contains similar code. The code depends upon
18141 architecture, block size and alignment, but always has the same
18144 1) Prologue guard: Conditional that jumps up to epilogues for small
18145 blocks that can be handled by epilogue alone. This is faster but
18146 also needed for correctness, since prologue assume the block is larger
18147 than the desired alignment.
18149 Optional dynamic check for size and libcall for large
18150 blocks is emitted here too, with -minline-stringops-dynamically.
18152 2) Prologue: copy first few bytes in order to get destination aligned
18153 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18154 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18155 We emit either a jump tree on power of two sized blocks, or a byte loop.
18157 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18158 with specified algorithm.
18160 4) Epilogue: code copying tail of the block that is too small to be
18161 handled by main body (or up to size guarded by prologue guard). */
18164 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
18165 rtx expected_align_exp, rtx expected_size_exp)
18171 rtx jump_around_label = NULL;
18172 HOST_WIDE_INT align = 1;
18173 unsigned HOST_WIDE_INT count = 0;
18174 HOST_WIDE_INT expected_size = -1;
18175 int size_needed = 0, epilogue_size_needed;
18176 int desired_align = 0, align_bytes = 0;
18177 enum stringop_alg alg;
18179 bool need_zero_guard = false;
18181 if (CONST_INT_P (align_exp))
18182 align = INTVAL (align_exp);
18183 /* i386 can do misaligned access on reasonably increased cost. */
18184 if (CONST_INT_P (expected_align_exp)
18185 && INTVAL (expected_align_exp) > align)
18186 align = INTVAL (expected_align_exp);
18187 /* ALIGN is the minimum of destination and source alignment, but we care here
18188 just about destination alignment. */
18189 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
18190 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
18192 if (CONST_INT_P (count_exp))
18193 count = expected_size = INTVAL (count_exp);
18194 if (CONST_INT_P (expected_size_exp) && count == 0)
18195 expected_size = INTVAL (expected_size_exp);
18197 /* Make sure we don't need to care about overflow later on. */
18198 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18201 /* Step 0: Decide on preferred algorithm, desired alignment and
18202 size of chunks to be copied by main loop. */
18204 alg = decide_alg (count, expected_size, false, &dynamic_check);
18205 desired_align = decide_alignment (align, alg, expected_size);
18207 if (!TARGET_ALIGN_STRINGOPS)
18208 align = desired_align;
18210 if (alg == libcall)
18212 gcc_assert (alg != no_stringop);
18214 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18215 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18216 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18221 gcc_unreachable ();
18223 need_zero_guard = true;
18224 size_needed = GET_MODE_SIZE (Pmode);
18226 case unrolled_loop:
18227 need_zero_guard = true;
18228 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18230 case rep_prefix_8_byte:
18233 case rep_prefix_4_byte:
18236 case rep_prefix_1_byte:
18240 need_zero_guard = true;
18245 epilogue_size_needed = size_needed;
18247 /* Step 1: Prologue guard. */
18249 /* Alignment code needs count to be in register. */
18250 if (CONST_INT_P (count_exp) && desired_align > align)
18252 if (INTVAL (count_exp) > desired_align
18253 && INTVAL (count_exp) > size_needed)
18256 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18257 if (align_bytes <= 0)
18260 align_bytes = desired_align - align_bytes;
18262 if (align_bytes == 0)
18263 count_exp = force_reg (counter_mode (count_exp), count_exp);
18265 gcc_assert (desired_align >= 1 && align >= 1);
18267 /* Ensure that alignment prologue won't copy past end of block. */
18268 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18270 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18271 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18272 Make sure it is power of 2. */
18273 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18277 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18279 /* If main algorithm works on QImode, no epilogue is needed.
18280 For small sizes just don't align anything. */
18281 if (size_needed == 1)
18282 desired_align = align;
18289 label = gen_label_rtx ();
18290 emit_cmp_and_jump_insns (count_exp,
18291 GEN_INT (epilogue_size_needed),
18292 LTU, 0, counter_mode (count_exp), 1, label);
18293 if (expected_size == -1 || expected_size < epilogue_size_needed)
18294 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18296 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18300 /* Emit code to decide on runtime whether library call or inline should be
18302 if (dynamic_check != -1)
18304 if (CONST_INT_P (count_exp))
18306 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18308 emit_block_move_via_libcall (dst, src, count_exp, false);
18309 count_exp = const0_rtx;
18315 rtx hot_label = gen_label_rtx ();
18316 jump_around_label = gen_label_rtx ();
18317 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18318 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18319 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18320 emit_block_move_via_libcall (dst, src, count_exp, false);
18321 emit_jump (jump_around_label);
18322 emit_label (hot_label);
18326 /* Step 2: Alignment prologue. */
18328 if (desired_align > align)
18330 if (align_bytes == 0)
18332 /* Except for the first move in epilogue, we no longer know
18333 constant offset in aliasing info. It don't seems to worth
18334 the pain to maintain it for the first move, so throw away
18336 src = change_address (src, BLKmode, srcreg);
18337 dst = change_address (dst, BLKmode, destreg);
18338 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18343 /* If we know how many bytes need to be stored before dst is
18344 sufficiently aligned, maintain aliasing info accurately. */
18345 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18346 desired_align, align_bytes);
18347 count_exp = plus_constant (count_exp, -align_bytes);
18348 count -= align_bytes;
18350 if (need_zero_guard
18351 && (count < (unsigned HOST_WIDE_INT) size_needed
18352 || (align_bytes == 0
18353 && count < ((unsigned HOST_WIDE_INT) size_needed
18354 + desired_align - align))))
18356 /* It is possible that we copied enough so the main loop will not
18358 gcc_assert (size_needed > 1);
18359 if (label == NULL_RTX)
18360 label = gen_label_rtx ();
18361 emit_cmp_and_jump_insns (count_exp,
18362 GEN_INT (size_needed),
18363 LTU, 0, counter_mode (count_exp), 1, label);
18364 if (expected_size == -1
18365 || expected_size < (desired_align - align) / 2 + size_needed)
18366 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18368 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18371 if (label && size_needed == 1)
18373 emit_label (label);
18374 LABEL_NUSES (label) = 1;
18376 epilogue_size_needed = 1;
18378 else if (label == NULL_RTX)
18379 epilogue_size_needed = size_needed;
18381 /* Step 3: Main loop. */
18387 gcc_unreachable ();
18389 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18390 count_exp, QImode, 1, expected_size);
18393 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18394 count_exp, Pmode, 1, expected_size);
18396 case unrolled_loop:
18397 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18398 registers for 4 temporaries anyway. */
18399 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18400 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18403 case rep_prefix_8_byte:
18404 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18407 case rep_prefix_4_byte:
18408 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18411 case rep_prefix_1_byte:
18412 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18416 /* Adjust properly the offset of src and dest memory for aliasing. */
18417 if (CONST_INT_P (count_exp))
18419 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18420 (count / size_needed) * size_needed);
18421 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18422 (count / size_needed) * size_needed);
18426 src = change_address (src, BLKmode, srcreg);
18427 dst = change_address (dst, BLKmode, destreg);
18430 /* Step 4: Epilogue to copy the remaining bytes. */
18434 /* When the main loop is done, COUNT_EXP might hold original count,
18435 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18436 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18437 bytes. Compensate if needed. */
18439 if (size_needed < epilogue_size_needed)
18442 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18443 GEN_INT (size_needed - 1), count_exp, 1,
18445 if (tmp != count_exp)
18446 emit_move_insn (count_exp, tmp);
18448 emit_label (label);
18449 LABEL_NUSES (label) = 1;
18452 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18453 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18454 epilogue_size_needed);
18455 if (jump_around_label)
18456 emit_label (jump_around_label);
18460 /* Helper function for memcpy. For QImode value 0xXY produce
18461 0xXYXYXYXY of wide specified by MODE. This is essentially
18462 a * 0x10101010, but we can do slightly better than
18463 synth_mult by unwinding the sequence by hand on CPUs with
18466 promote_duplicated_reg (enum machine_mode mode, rtx val)
18468 enum machine_mode valmode = GET_MODE (val);
18470 int nops = mode == DImode ? 3 : 2;
18472 gcc_assert (mode == SImode || mode == DImode);
18473 if (val == const0_rtx)
18474 return copy_to_mode_reg (mode, const0_rtx);
18475 if (CONST_INT_P (val))
18477 HOST_WIDE_INT v = INTVAL (val) & 255;
18481 if (mode == DImode)
18482 v |= (v << 16) << 16;
18483 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18486 if (valmode == VOIDmode)
18488 if (valmode != QImode)
18489 val = gen_lowpart (QImode, val);
18490 if (mode == QImode)
18492 if (!TARGET_PARTIAL_REG_STALL)
18494 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18495 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18496 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18497 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18499 rtx reg = convert_modes (mode, QImode, val, true);
18500 tmp = promote_duplicated_reg (mode, const1_rtx);
18501 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18506 rtx reg = convert_modes (mode, QImode, val, true);
18508 if (!TARGET_PARTIAL_REG_STALL)
18509 if (mode == SImode)
18510 emit_insn (gen_movsi_insv_1 (reg, reg));
18512 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18515 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18516 NULL, 1, OPTAB_DIRECT);
18518 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18520 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18521 NULL, 1, OPTAB_DIRECT);
18522 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18523 if (mode == SImode)
18525 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18526 NULL, 1, OPTAB_DIRECT);
18527 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18532 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18533 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18534 alignment from ALIGN to DESIRED_ALIGN. */
18536 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18541 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18542 promoted_val = promote_duplicated_reg (DImode, val);
18543 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18544 promoted_val = promote_duplicated_reg (SImode, val);
18545 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18546 promoted_val = promote_duplicated_reg (HImode, val);
18548 promoted_val = val;
18550 return promoted_val;
18553 /* Expand string clear operation (bzero). Use i386 string operations when
18554 profitable. See expand_movmem comment for explanation of individual
18555 steps performed. */
18557 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18558 rtx expected_align_exp, rtx expected_size_exp)
18563 rtx jump_around_label = NULL;
18564 HOST_WIDE_INT align = 1;
18565 unsigned HOST_WIDE_INT count = 0;
18566 HOST_WIDE_INT expected_size = -1;
18567 int size_needed = 0, epilogue_size_needed;
18568 int desired_align = 0, align_bytes = 0;
18569 enum stringop_alg alg;
18570 rtx promoted_val = NULL;
18571 bool force_loopy_epilogue = false;
18573 bool need_zero_guard = false;
18575 if (CONST_INT_P (align_exp))
18576 align = INTVAL (align_exp);
18577 /* i386 can do misaligned access on reasonably increased cost. */
18578 if (CONST_INT_P (expected_align_exp)
18579 && INTVAL (expected_align_exp) > align)
18580 align = INTVAL (expected_align_exp);
18581 if (CONST_INT_P (count_exp))
18582 count = expected_size = INTVAL (count_exp);
18583 if (CONST_INT_P (expected_size_exp) && count == 0)
18584 expected_size = INTVAL (expected_size_exp);
18586 /* Make sure we don't need to care about overflow later on. */
18587 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18590 /* Step 0: Decide on preferred algorithm, desired alignment and
18591 size of chunks to be copied by main loop. */
18593 alg = decide_alg (count, expected_size, true, &dynamic_check);
18594 desired_align = decide_alignment (align, alg, expected_size);
18596 if (!TARGET_ALIGN_STRINGOPS)
18597 align = desired_align;
18599 if (alg == libcall)
18601 gcc_assert (alg != no_stringop);
18603 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18604 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18609 gcc_unreachable ();
18611 need_zero_guard = true;
18612 size_needed = GET_MODE_SIZE (Pmode);
18614 case unrolled_loop:
18615 need_zero_guard = true;
18616 size_needed = GET_MODE_SIZE (Pmode) * 4;
18618 case rep_prefix_8_byte:
18621 case rep_prefix_4_byte:
18624 case rep_prefix_1_byte:
18628 need_zero_guard = true;
18632 epilogue_size_needed = size_needed;
18634 /* Step 1: Prologue guard. */
18636 /* Alignment code needs count to be in register. */
18637 if (CONST_INT_P (count_exp) && desired_align > align)
18639 if (INTVAL (count_exp) > desired_align
18640 && INTVAL (count_exp) > size_needed)
18643 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18644 if (align_bytes <= 0)
18647 align_bytes = desired_align - align_bytes;
18649 if (align_bytes == 0)
18651 enum machine_mode mode = SImode;
18652 if (TARGET_64BIT && (count & ~0xffffffff))
18654 count_exp = force_reg (mode, count_exp);
18657 /* Do the cheap promotion to allow better CSE across the
18658 main loop and epilogue (ie one load of the big constant in the
18659 front of all code. */
18660 if (CONST_INT_P (val_exp))
18661 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18662 desired_align, align);
18663 /* Ensure that alignment prologue won't copy past end of block. */
18664 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18666 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18667 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18668 Make sure it is power of 2. */
18669 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18671 /* To improve performance of small blocks, we jump around the VAL
18672 promoting mode. This mean that if the promoted VAL is not constant,
18673 we might not use it in the epilogue and have to use byte
18675 if (epilogue_size_needed > 2 && !promoted_val)
18676 force_loopy_epilogue = true;
18679 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18681 /* If main algorithm works on QImode, no epilogue is needed.
18682 For small sizes just don't align anything. */
18683 if (size_needed == 1)
18684 desired_align = align;
18691 label = gen_label_rtx ();
18692 emit_cmp_and_jump_insns (count_exp,
18693 GEN_INT (epilogue_size_needed),
18694 LTU, 0, counter_mode (count_exp), 1, label);
18695 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18696 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18698 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18701 if (dynamic_check != -1)
18703 rtx hot_label = gen_label_rtx ();
18704 jump_around_label = gen_label_rtx ();
18705 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18706 LEU, 0, counter_mode (count_exp), 1, hot_label);
18707 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18708 set_storage_via_libcall (dst, count_exp, val_exp, false);
18709 emit_jump (jump_around_label);
18710 emit_label (hot_label);
18713 /* Step 2: Alignment prologue. */
18715 /* Do the expensive promotion once we branched off the small blocks. */
18717 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18718 desired_align, align);
18719 gcc_assert (desired_align >= 1 && align >= 1);
18721 if (desired_align > align)
18723 if (align_bytes == 0)
18725 /* Except for the first move in epilogue, we no longer know
18726 constant offset in aliasing info. It don't seems to worth
18727 the pain to maintain it for the first move, so throw away
18729 dst = change_address (dst, BLKmode, destreg);
18730 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18735 /* If we know how many bytes need to be stored before dst is
18736 sufficiently aligned, maintain aliasing info accurately. */
18737 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18738 desired_align, align_bytes);
18739 count_exp = plus_constant (count_exp, -align_bytes);
18740 count -= align_bytes;
18742 if (need_zero_guard
18743 && (count < (unsigned HOST_WIDE_INT) size_needed
18744 || (align_bytes == 0
18745 && count < ((unsigned HOST_WIDE_INT) size_needed
18746 + desired_align - align))))
18748 /* It is possible that we copied enough so the main loop will not
18750 gcc_assert (size_needed > 1);
18751 if (label == NULL_RTX)
18752 label = gen_label_rtx ();
18753 emit_cmp_and_jump_insns (count_exp,
18754 GEN_INT (size_needed),
18755 LTU, 0, counter_mode (count_exp), 1, label);
18756 if (expected_size == -1
18757 || expected_size < (desired_align - align) / 2 + size_needed)
18758 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18760 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18763 if (label && size_needed == 1)
18765 emit_label (label);
18766 LABEL_NUSES (label) = 1;
18768 promoted_val = val_exp;
18769 epilogue_size_needed = 1;
18771 else if (label == NULL_RTX)
18772 epilogue_size_needed = size_needed;
18774 /* Step 3: Main loop. */
18780 gcc_unreachable ();
18782 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18783 count_exp, QImode, 1, expected_size);
18786 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18787 count_exp, Pmode, 1, expected_size);
18789 case unrolled_loop:
18790 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18791 count_exp, Pmode, 4, expected_size);
18793 case rep_prefix_8_byte:
18794 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18797 case rep_prefix_4_byte:
18798 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18801 case rep_prefix_1_byte:
18802 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18806 /* Adjust properly the offset of src and dest memory for aliasing. */
18807 if (CONST_INT_P (count_exp))
18808 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18809 (count / size_needed) * size_needed);
18811 dst = change_address (dst, BLKmode, destreg);
18813 /* Step 4: Epilogue to copy the remaining bytes. */
18817 /* When the main loop is done, COUNT_EXP might hold original count,
18818 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18819 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18820 bytes. Compensate if needed. */
18822 if (size_needed < epilogue_size_needed)
18825 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18826 GEN_INT (size_needed - 1), count_exp, 1,
18828 if (tmp != count_exp)
18829 emit_move_insn (count_exp, tmp);
18831 emit_label (label);
18832 LABEL_NUSES (label) = 1;
18835 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18837 if (force_loopy_epilogue)
18838 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18839 epilogue_size_needed);
18841 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18842 epilogue_size_needed);
18844 if (jump_around_label)
18845 emit_label (jump_around_label);
18849 /* Expand the appropriate insns for doing strlen if not just doing
18852 out = result, initialized with the start address
18853 align_rtx = alignment of the address.
18854 scratch = scratch register, initialized with the startaddress when
18855 not aligned, otherwise undefined
18857 This is just the body. It needs the initializations mentioned above and
18858 some address computing at the end. These things are done in i386.md. */
18861 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18865 rtx align_2_label = NULL_RTX;
18866 rtx align_3_label = NULL_RTX;
18867 rtx align_4_label = gen_label_rtx ();
18868 rtx end_0_label = gen_label_rtx ();
18870 rtx tmpreg = gen_reg_rtx (SImode);
18871 rtx scratch = gen_reg_rtx (SImode);
18875 if (CONST_INT_P (align_rtx))
18876 align = INTVAL (align_rtx);
18878 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18880 /* Is there a known alignment and is it less than 4? */
18883 rtx scratch1 = gen_reg_rtx (Pmode);
18884 emit_move_insn (scratch1, out);
18885 /* Is there a known alignment and is it not 2? */
18888 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18889 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18891 /* Leave just the 3 lower bits. */
18892 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18893 NULL_RTX, 0, OPTAB_WIDEN);
18895 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18896 Pmode, 1, align_4_label);
18897 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18898 Pmode, 1, align_2_label);
18899 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18900 Pmode, 1, align_3_label);
18904 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18905 check if is aligned to 4 - byte. */
18907 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18908 NULL_RTX, 0, OPTAB_WIDEN);
18910 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18911 Pmode, 1, align_4_label);
18914 mem = change_address (src, QImode, out);
18916 /* Now compare the bytes. */
18918 /* Compare the first n unaligned byte on a byte per byte basis. */
18919 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18920 QImode, 1, end_0_label);
18922 /* Increment the address. */
18923 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18925 /* Not needed with an alignment of 2 */
18928 emit_label (align_2_label);
18930 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18933 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18935 emit_label (align_3_label);
18938 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18941 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18944 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18945 align this loop. It gives only huge programs, but does not help to
18947 emit_label (align_4_label);
18949 mem = change_address (src, SImode, out);
18950 emit_move_insn (scratch, mem);
18951 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18953 /* This formula yields a nonzero result iff one of the bytes is zero.
18954 This saves three branches inside loop and many cycles. */
18956 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18957 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18958 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18959 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18960 gen_int_mode (0x80808080, SImode)));
18961 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18966 rtx reg = gen_reg_rtx (SImode);
18967 rtx reg2 = gen_reg_rtx (Pmode);
18968 emit_move_insn (reg, tmpreg);
18969 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18971 /* If zero is not in the first two bytes, move two bytes forward. */
18972 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18973 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18974 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18975 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18976 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18979 /* Emit lea manually to avoid clobbering of flags. */
18980 emit_insn (gen_rtx_SET (SImode, reg2,
18981 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18983 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18984 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18985 emit_insn (gen_rtx_SET (VOIDmode, out,
18986 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18993 rtx end_2_label = gen_label_rtx ();
18994 /* Is zero in the first two bytes? */
18996 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18997 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18998 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18999 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
19000 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
19002 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
19003 JUMP_LABEL (tmp) = end_2_label;
19005 /* Not in the first two. Move two bytes forward. */
19006 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
19007 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
19009 emit_label (end_2_label);
19013 /* Avoid branch in fixing the byte. */
19014 tmpreg = gen_lowpart (QImode, tmpreg);
19015 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
19016 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
19017 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
19019 emit_label (end_0_label);
19022 /* Expand strlen. */
19025 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
19027 rtx addr, scratch1, scratch2, scratch3, scratch4;
19029 /* The generic case of strlen expander is long. Avoid it's
19030 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
19032 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19033 && !TARGET_INLINE_ALL_STRINGOPS
19034 && !optimize_insn_for_size_p ()
19035 && (!CONST_INT_P (align) || INTVAL (align) < 4))
19038 addr = force_reg (Pmode, XEXP (src, 0));
19039 scratch1 = gen_reg_rtx (Pmode);
19041 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
19042 && !optimize_insn_for_size_p ())
19044 /* Well it seems that some optimizer does not combine a call like
19045 foo(strlen(bar), strlen(bar));
19046 when the move and the subtraction is done here. It does calculate
19047 the length just once when these instructions are done inside of
19048 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
19049 often used and I use one fewer register for the lifetime of
19050 output_strlen_unroll() this is better. */
19052 emit_move_insn (out, addr);
19054 ix86_expand_strlensi_unroll_1 (out, src, align);
19056 /* strlensi_unroll_1 returns the address of the zero at the end of
19057 the string, like memchr(), so compute the length by subtracting
19058 the start address. */
19059 emit_insn ((*ix86_gen_sub3) (out, out, addr));
19065 /* Can't use this if the user has appropriated eax, ecx, or edi. */
19066 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
19069 scratch2 = gen_reg_rtx (Pmode);
19070 scratch3 = gen_reg_rtx (Pmode);
19071 scratch4 = force_reg (Pmode, constm1_rtx);
19073 emit_move_insn (scratch3, addr);
19074 eoschar = force_reg (QImode, eoschar);
19076 src = replace_equiv_address_nv (src, scratch3);
19078 /* If .md starts supporting :P, this can be done in .md. */
19079 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
19080 scratch4), UNSPEC_SCAS);
19081 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
19082 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
19083 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
19088 /* For given symbol (function) construct code to compute address of it's PLT
19089 entry in large x86-64 PIC model. */
19091 construct_plt_address (rtx symbol)
19093 rtx tmp = gen_reg_rtx (Pmode);
19094 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
19096 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
19097 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
19099 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
19100 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
19105 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
19107 rtx pop, int sibcall)
19109 rtx use = NULL, call;
19111 if (pop == const0_rtx)
19113 gcc_assert (!TARGET_64BIT || !pop);
19115 if (TARGET_MACHO && !TARGET_64BIT)
19118 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
19119 fnaddr = machopic_indirect_call_target (fnaddr);
19124 /* Static functions and indirect calls don't need the pic register. */
19125 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
19126 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19127 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
19128 use_reg (&use, pic_offset_table_rtx);
19131 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
19133 rtx al = gen_rtx_REG (QImode, AX_REG);
19134 emit_move_insn (al, callarg2);
19135 use_reg (&use, al);
19138 if (ix86_cmodel == CM_LARGE_PIC
19140 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
19141 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
19142 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
19144 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
19145 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
19147 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
19148 fnaddr = gen_rtx_MEM (QImode, fnaddr);
19151 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
19153 call = gen_rtx_SET (VOIDmode, retval, call);
19156 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
19157 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
19158 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
19161 && ix86_cfun_abi () == MS_ABI
19162 && (!callarg2 || INTVAL (callarg2) != -2))
19164 /* We need to represent that SI and DI registers are clobbered
19166 static int clobbered_registers[] = {
19167 XMM6_REG, XMM7_REG, XMM8_REG,
19168 XMM9_REG, XMM10_REG, XMM11_REG,
19169 XMM12_REG, XMM13_REG, XMM14_REG,
19170 XMM15_REG, SI_REG, DI_REG
19173 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
19174 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
19175 UNSPEC_MS_TO_SYSV_CALL);
19179 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
19180 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
19183 (SSE_REGNO_P (clobbered_registers[i])
19185 clobbered_registers[i]));
19187 call = gen_rtx_PARALLEL (VOIDmode,
19188 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
19192 call = emit_call_insn (call);
19194 CALL_INSN_FUNCTION_USAGE (call) = use;
19198 /* Clear stack slot assignments remembered from previous functions.
19199 This is called from INIT_EXPANDERS once before RTL is emitted for each
19202 static struct machine_function *
19203 ix86_init_machine_status (void)
19205 struct machine_function *f;
19207 f = GGC_CNEW (struct machine_function);
19208 f->use_fast_prologue_epilogue_nregs = -1;
19209 f->tls_descriptor_call_expanded_p = 0;
19210 f->call_abi = ix86_abi;
19215 /* Return a MEM corresponding to a stack slot with mode MODE.
19216 Allocate a new slot if necessary.
19218 The RTL for a function can have several slots available: N is
19219 which slot to use. */
19222 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19224 struct stack_local_entry *s;
19226 gcc_assert (n < MAX_386_STACK_LOCALS);
19228 /* Virtual slot is valid only before vregs are instantiated. */
19229 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19231 for (s = ix86_stack_locals; s; s = s->next)
19232 if (s->mode == mode && s->n == n)
19233 return copy_rtx (s->rtl);
19235 s = (struct stack_local_entry *)
19236 ggc_alloc (sizeof (struct stack_local_entry));
19239 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19241 s->next = ix86_stack_locals;
19242 ix86_stack_locals = s;
19246 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19248 static GTY(()) rtx ix86_tls_symbol;
19250 ix86_tls_get_addr (void)
19253 if (!ix86_tls_symbol)
19255 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19256 (TARGET_ANY_GNU_TLS
19258 ? "___tls_get_addr"
19259 : "__tls_get_addr");
19262 return ix86_tls_symbol;
19265 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19267 static GTY(()) rtx ix86_tls_module_base_symbol;
19269 ix86_tls_module_base (void)
19272 if (!ix86_tls_module_base_symbol)
19274 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19275 "_TLS_MODULE_BASE_");
19276 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19277 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19280 return ix86_tls_module_base_symbol;
19283 /* Calculate the length of the memory address in the instruction
19284 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19287 memory_address_length (rtx addr)
19289 struct ix86_address parts;
19290 rtx base, index, disp;
19294 if (GET_CODE (addr) == PRE_DEC
19295 || GET_CODE (addr) == POST_INC
19296 || GET_CODE (addr) == PRE_MODIFY
19297 || GET_CODE (addr) == POST_MODIFY)
19300 ok = ix86_decompose_address (addr, &parts);
19303 if (parts.base && GET_CODE (parts.base) == SUBREG)
19304 parts.base = SUBREG_REG (parts.base);
19305 if (parts.index && GET_CODE (parts.index) == SUBREG)
19306 parts.index = SUBREG_REG (parts.index);
19309 index = parts.index;
19314 - esp as the base always wants an index,
19315 - ebp as the base always wants a displacement,
19316 - r12 as the base always wants an index,
19317 - r13 as the base always wants a displacement. */
19319 /* Register Indirect. */
19320 if (base && !index && !disp)
19322 /* esp (for its index) and ebp (for its displacement) need
19323 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19326 && (addr == arg_pointer_rtx
19327 || addr == frame_pointer_rtx
19328 || REGNO (addr) == SP_REG
19329 || REGNO (addr) == BP_REG
19330 || REGNO (addr) == R12_REG
19331 || REGNO (addr) == R13_REG))
19335 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19336 is not disp32, but disp32(%rip), so for disp32
19337 SIB byte is needed, unless print_operand_address
19338 optimizes it into disp32(%rip) or (%rip) is implied
19340 else if (disp && !base && !index)
19347 if (GET_CODE (disp) == CONST)
19348 symbol = XEXP (disp, 0);
19349 if (GET_CODE (symbol) == PLUS
19350 && CONST_INT_P (XEXP (symbol, 1)))
19351 symbol = XEXP (symbol, 0);
19353 if (GET_CODE (symbol) != LABEL_REF
19354 && (GET_CODE (symbol) != SYMBOL_REF
19355 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19356 && (GET_CODE (symbol) != UNSPEC
19357 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19358 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19365 /* Find the length of the displacement constant. */
19368 if (base && satisfies_constraint_K (disp))
19373 /* ebp always wants a displacement. Similarly r13. */
19374 else if (base && REG_P (base)
19375 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19378 /* An index requires the two-byte modrm form.... */
19380 /* ...like esp (or r12), which always wants an index. */
19381 || base == arg_pointer_rtx
19382 || base == frame_pointer_rtx
19383 || (base && REG_P (base)
19384 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19401 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19402 is set, expect that insn have 8bit immediate alternative. */
19404 ix86_attr_length_immediate_default (rtx insn, int shortform)
19408 extract_insn_cached (insn);
19409 for (i = recog_data.n_operands - 1; i >= 0; --i)
19410 if (CONSTANT_P (recog_data.operand[i]))
19412 enum attr_mode mode = get_attr_mode (insn);
19415 if (shortform && CONST_INT_P (recog_data.operand[i]))
19417 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19424 ival = trunc_int_for_mode (ival, HImode);
19427 ival = trunc_int_for_mode (ival, SImode);
19432 if (IN_RANGE (ival, -128, 127))
19449 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19454 fatal_insn ("unknown insn mode", insn);
19459 /* Compute default value for "length_address" attribute. */
19461 ix86_attr_length_address_default (rtx insn)
19465 if (get_attr_type (insn) == TYPE_LEA)
19467 rtx set = PATTERN (insn), addr;
19469 if (GET_CODE (set) == PARALLEL)
19470 set = XVECEXP (set, 0, 0);
19472 gcc_assert (GET_CODE (set) == SET);
19474 addr = SET_SRC (set);
19475 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19477 if (GET_CODE (addr) == ZERO_EXTEND)
19478 addr = XEXP (addr, 0);
19479 if (GET_CODE (addr) == SUBREG)
19480 addr = SUBREG_REG (addr);
19483 return memory_address_length (addr);
19486 extract_insn_cached (insn);
19487 for (i = recog_data.n_operands - 1; i >= 0; --i)
19488 if (MEM_P (recog_data.operand[i]))
19490 constrain_operands_cached (reload_completed);
19491 if (which_alternative != -1)
19493 const char *constraints = recog_data.constraints[i];
19494 int alt = which_alternative;
19496 while (*constraints == '=' || *constraints == '+')
19499 while (*constraints++ != ',')
19501 /* Skip ignored operands. */
19502 if (*constraints == 'X')
19505 return memory_address_length (XEXP (recog_data.operand[i], 0));
19510 /* Compute default value for "length_vex" attribute. It includes
19511 2 or 3 byte VEX prefix and 1 opcode byte. */
19514 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19519 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19520 byte VEX prefix. */
19521 if (!has_0f_opcode || has_vex_w)
19524 /* We can always use 2 byte VEX prefix in 32bit. */
19528 extract_insn_cached (insn);
19530 for (i = recog_data.n_operands - 1; i >= 0; --i)
19531 if (REG_P (recog_data.operand[i]))
19533 /* REX.W bit uses 3 byte VEX prefix. */
19534 if (GET_MODE (recog_data.operand[i]) == DImode
19535 && GENERAL_REG_P (recog_data.operand[i]))
19540 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19541 if (MEM_P (recog_data.operand[i])
19542 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19549 /* Return the maximum number of instructions a cpu can issue. */
19552 ix86_issue_rate (void)
19556 case PROCESSOR_PENTIUM:
19557 case PROCESSOR_ATOM:
19561 case PROCESSOR_PENTIUMPRO:
19562 case PROCESSOR_PENTIUM4:
19563 case PROCESSOR_ATHLON:
19565 case PROCESSOR_AMDFAM10:
19566 case PROCESSOR_NOCONA:
19567 case PROCESSOR_GENERIC32:
19568 case PROCESSOR_GENERIC64:
19571 case PROCESSOR_CORE2:
19579 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19580 by DEP_INSN and nothing set by DEP_INSN. */
19583 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19587 /* Simplify the test for uninteresting insns. */
19588 if (insn_type != TYPE_SETCC
19589 && insn_type != TYPE_ICMOV
19590 && insn_type != TYPE_FCMOV
19591 && insn_type != TYPE_IBR)
19594 if ((set = single_set (dep_insn)) != 0)
19596 set = SET_DEST (set);
19599 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19600 && XVECLEN (PATTERN (dep_insn), 0) == 2
19601 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19602 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19604 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19605 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19610 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19613 /* This test is true if the dependent insn reads the flags but
19614 not any other potentially set register. */
19615 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19618 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19624 /* Return true iff USE_INSN has a memory address with operands set by
19628 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19631 extract_insn_cached (use_insn);
19632 for (i = recog_data.n_operands - 1; i >= 0; --i)
19633 if (MEM_P (recog_data.operand[i]))
19635 rtx addr = XEXP (recog_data.operand[i], 0);
19636 return modified_in_p (addr, set_insn) != 0;
19642 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19644 enum attr_type insn_type, dep_insn_type;
19645 enum attr_memory memory;
19647 int dep_insn_code_number;
19649 /* Anti and output dependencies have zero cost on all CPUs. */
19650 if (REG_NOTE_KIND (link) != 0)
19653 dep_insn_code_number = recog_memoized (dep_insn);
19655 /* If we can't recognize the insns, we can't really do anything. */
19656 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19659 insn_type = get_attr_type (insn);
19660 dep_insn_type = get_attr_type (dep_insn);
19664 case PROCESSOR_PENTIUM:
19665 /* Address Generation Interlock adds a cycle of latency. */
19666 if (insn_type == TYPE_LEA)
19668 rtx addr = PATTERN (insn);
19670 if (GET_CODE (addr) == PARALLEL)
19671 addr = XVECEXP (addr, 0, 0);
19673 gcc_assert (GET_CODE (addr) == SET);
19675 addr = SET_SRC (addr);
19676 if (modified_in_p (addr, dep_insn))
19679 else if (ix86_agi_dependent (dep_insn, insn))
19682 /* ??? Compares pair with jump/setcc. */
19683 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19686 /* Floating point stores require value to be ready one cycle earlier. */
19687 if (insn_type == TYPE_FMOV
19688 && get_attr_memory (insn) == MEMORY_STORE
19689 && !ix86_agi_dependent (dep_insn, insn))
19693 case PROCESSOR_PENTIUMPRO:
19694 memory = get_attr_memory (insn);
19696 /* INT->FP conversion is expensive. */
19697 if (get_attr_fp_int_src (dep_insn))
19700 /* There is one cycle extra latency between an FP op and a store. */
19701 if (insn_type == TYPE_FMOV
19702 && (set = single_set (dep_insn)) != NULL_RTX
19703 && (set2 = single_set (insn)) != NULL_RTX
19704 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19705 && MEM_P (SET_DEST (set2)))
19708 /* Show ability of reorder buffer to hide latency of load by executing
19709 in parallel with previous instruction in case
19710 previous instruction is not needed to compute the address. */
19711 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19712 && !ix86_agi_dependent (dep_insn, insn))
19714 /* Claim moves to take one cycle, as core can issue one load
19715 at time and the next load can start cycle later. */
19716 if (dep_insn_type == TYPE_IMOV
19717 || dep_insn_type == TYPE_FMOV)
19725 memory = get_attr_memory (insn);
19727 /* The esp dependency is resolved before the instruction is really
19729 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19730 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19733 /* INT->FP conversion is expensive. */
19734 if (get_attr_fp_int_src (dep_insn))
19737 /* Show ability of reorder buffer to hide latency of load by executing
19738 in parallel with previous instruction in case
19739 previous instruction is not needed to compute the address. */
19740 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19741 && !ix86_agi_dependent (dep_insn, insn))
19743 /* Claim moves to take one cycle, as core can issue one load
19744 at time and the next load can start cycle later. */
19745 if (dep_insn_type == TYPE_IMOV
19746 || dep_insn_type == TYPE_FMOV)
19755 case PROCESSOR_ATHLON:
19757 case PROCESSOR_AMDFAM10:
19758 case PROCESSOR_ATOM:
19759 case PROCESSOR_GENERIC32:
19760 case PROCESSOR_GENERIC64:
19761 memory = get_attr_memory (insn);
19763 /* Show ability of reorder buffer to hide latency of load by executing
19764 in parallel with previous instruction in case
19765 previous instruction is not needed to compute the address. */
19766 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19767 && !ix86_agi_dependent (dep_insn, insn))
19769 enum attr_unit unit = get_attr_unit (insn);
19772 /* Because of the difference between the length of integer and
19773 floating unit pipeline preparation stages, the memory operands
19774 for floating point are cheaper.
19776 ??? For Athlon it the difference is most probably 2. */
19777 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19780 loadcost = TARGET_ATHLON ? 2 : 0;
19782 if (cost >= loadcost)
19795 /* How many alternative schedules to try. This should be as wide as the
19796 scheduling freedom in the DFA, but no wider. Making this value too
19797 large results extra work for the scheduler. */
19800 ia32_multipass_dfa_lookahead (void)
19804 case PROCESSOR_PENTIUM:
19807 case PROCESSOR_PENTIUMPRO:
19817 /* Compute the alignment given to a constant that is being placed in memory.
19818 EXP is the constant and ALIGN is the alignment that the object would
19820 The value of this function is used instead of that alignment to align
19824 ix86_constant_alignment (tree exp, int align)
19826 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19827 || TREE_CODE (exp) == INTEGER_CST)
19829 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19831 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19834 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19835 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19836 return BITS_PER_WORD;
19841 /* Compute the alignment for a static variable.
19842 TYPE is the data type, and ALIGN is the alignment that
19843 the object would ordinarily have. The value of this function is used
19844 instead of that alignment to align the object. */
19847 ix86_data_alignment (tree type, int align)
19849 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19851 if (AGGREGATE_TYPE_P (type)
19852 && TYPE_SIZE (type)
19853 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19854 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19855 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19856 && align < max_align)
19859 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19860 to 16byte boundary. */
19863 if (AGGREGATE_TYPE_P (type)
19864 && TYPE_SIZE (type)
19865 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19866 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19867 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19871 if (TREE_CODE (type) == ARRAY_TYPE)
19873 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19875 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19878 else if (TREE_CODE (type) == COMPLEX_TYPE)
19881 if (TYPE_MODE (type) == DCmode && align < 64)
19883 if ((TYPE_MODE (type) == XCmode
19884 || TYPE_MODE (type) == TCmode) && align < 128)
19887 else if ((TREE_CODE (type) == RECORD_TYPE
19888 || TREE_CODE (type) == UNION_TYPE
19889 || TREE_CODE (type) == QUAL_UNION_TYPE)
19890 && TYPE_FIELDS (type))
19892 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19894 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19897 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19898 || TREE_CODE (type) == INTEGER_TYPE)
19900 if (TYPE_MODE (type) == DFmode && align < 64)
19902 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19909 /* Compute the alignment for a local variable or a stack slot. EXP is
19910 the data type or decl itself, MODE is the widest mode available and
19911 ALIGN is the alignment that the object would ordinarily have. The
19912 value of this macro is used instead of that alignment to align the
19916 ix86_local_alignment (tree exp, enum machine_mode mode,
19917 unsigned int align)
19921 if (exp && DECL_P (exp))
19923 type = TREE_TYPE (exp);
19932 /* Don't do dynamic stack realignment for long long objects with
19933 -mpreferred-stack-boundary=2. */
19936 && ix86_preferred_stack_boundary < 64
19937 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19938 && (!type || !TYPE_USER_ALIGN (type))
19939 && (!decl || !DECL_USER_ALIGN (decl)))
19942 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19943 register in MODE. We will return the largest alignment of XF
19947 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19948 align = GET_MODE_ALIGNMENT (DFmode);
19952 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19953 to 16byte boundary. */
19956 if (AGGREGATE_TYPE_P (type)
19957 && TYPE_SIZE (type)
19958 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19959 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19960 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19963 if (TREE_CODE (type) == ARRAY_TYPE)
19965 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19967 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19970 else if (TREE_CODE (type) == COMPLEX_TYPE)
19972 if (TYPE_MODE (type) == DCmode && align < 64)
19974 if ((TYPE_MODE (type) == XCmode
19975 || TYPE_MODE (type) == TCmode) && align < 128)
19978 else if ((TREE_CODE (type) == RECORD_TYPE
19979 || TREE_CODE (type) == UNION_TYPE
19980 || TREE_CODE (type) == QUAL_UNION_TYPE)
19981 && TYPE_FIELDS (type))
19983 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19985 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19988 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19989 || TREE_CODE (type) == INTEGER_TYPE)
19992 if (TYPE_MODE (type) == DFmode && align < 64)
19994 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
20000 /* Compute the minimum required alignment for dynamic stack realignment
20001 purposes for a local variable, parameter or a stack slot. EXP is
20002 the data type or decl itself, MODE is its mode and ALIGN is the
20003 alignment that the object would ordinarily have. */
20006 ix86_minimum_alignment (tree exp, enum machine_mode mode,
20007 unsigned int align)
20011 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
20014 if (exp && DECL_P (exp))
20016 type = TREE_TYPE (exp);
20025 /* Don't do dynamic stack realignment for long long objects with
20026 -mpreferred-stack-boundary=2. */
20027 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
20028 && (!type || !TYPE_USER_ALIGN (type))
20029 && (!decl || !DECL_USER_ALIGN (decl)))
20035 /* Find a location for the static chain incoming to a nested function.
20036 This is a register, unless all free registers are used by arguments. */
20039 ix86_static_chain (const_tree fndecl, bool incoming_p)
20043 if (!DECL_STATIC_CHAIN (fndecl))
20048 /* We always use R10 in 64-bit mode. */
20054 /* By default in 32-bit mode we use ECX to pass the static chain. */
20057 fntype = TREE_TYPE (fndecl);
20058 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
20060 /* Fastcall functions use ecx/edx for arguments, which leaves
20061 us with EAX for the static chain. */
20064 else if (ix86_function_regparm (fntype, fndecl) == 3)
20066 /* For regparm 3, we have no free call-clobbered registers in
20067 which to store the static chain. In order to implement this,
20068 we have the trampoline push the static chain to the stack.
20069 However, we can't push a value below the return address when
20070 we call the nested function directly, so we have to use an
20071 alternate entry point. For this we use ESI, and have the
20072 alternate entry point push ESI, so that things appear the
20073 same once we're executing the nested function. */
20076 if (fndecl == current_function_decl)
20077 ix86_static_chain_on_stack = true;
20078 return gen_frame_mem (SImode,
20079 plus_constant (arg_pointer_rtx, -8));
20085 return gen_rtx_REG (Pmode, regno);
20088 /* Emit RTL insns to initialize the variable parts of a trampoline.
20089 FNDECL is the decl of the target address; M_TRAMP is a MEM for
20090 the trampoline, and CHAIN_VALUE is an RTX for the static chain
20091 to be passed to the target function. */
20094 ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
20098 fnaddr = XEXP (DECL_RTL (fndecl), 0);
20105 /* Depending on the static chain location, either load a register
20106 with a constant, or push the constant to the stack. All of the
20107 instructions are the same size. */
20108 chain = ix86_static_chain (fndecl, true);
20111 if (REGNO (chain) == CX_REG)
20113 else if (REGNO (chain) == AX_REG)
20116 gcc_unreachable ();
20121 mem = adjust_address (m_tramp, QImode, 0);
20122 emit_move_insn (mem, gen_int_mode (opcode, QImode));
20124 mem = adjust_address (m_tramp, SImode, 1);
20125 emit_move_insn (mem, chain_value);
20127 /* Compute offset from the end of the jmp to the target function.
20128 In the case in which the trampoline stores the static chain on
20129 the stack, we need to skip the first insn which pushes the
20130 (call-saved) register static chain; this push is 1 byte. */
20131 disp = expand_binop (SImode, sub_optab, fnaddr,
20132 plus_constant (XEXP (m_tramp, 0),
20133 MEM_P (chain) ? 9 : 10),
20134 NULL_RTX, 1, OPTAB_DIRECT);
20136 mem = adjust_address (m_tramp, QImode, 5);
20137 emit_move_insn (mem, gen_int_mode (0xe9, QImode));
20139 mem = adjust_address (m_tramp, SImode, 6);
20140 emit_move_insn (mem, disp);
20146 /* Load the function address to r11. Try to load address using
20147 the shorter movl instead of movabs. We may want to support
20148 movq for kernel mode, but kernel does not use trampolines at
20150 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
20152 fnaddr = copy_to_mode_reg (DImode, fnaddr);
20154 mem = adjust_address (m_tramp, HImode, offset);
20155 emit_move_insn (mem, gen_int_mode (0xbb41, HImode));
20157 mem = adjust_address (m_tramp, SImode, offset + 2);
20158 emit_move_insn (mem, gen_lowpart (SImode, fnaddr));
20163 mem = adjust_address (m_tramp, HImode, offset);
20164 emit_move_insn (mem, gen_int_mode (0xbb49, HImode));
20166 mem = adjust_address (m_tramp, DImode, offset + 2);
20167 emit_move_insn (mem, fnaddr);
20171 /* Load static chain using movabs to r10. */
20172 mem = adjust_address (m_tramp, HImode, offset);
20173 emit_move_insn (mem, gen_int_mode (0xba49, HImode));
20175 mem = adjust_address (m_tramp, DImode, offset + 2);
20176 emit_move_insn (mem, chain_value);
20179 /* Jump to r11; the last (unused) byte is a nop, only there to
20180 pad the write out to a single 32-bit store. */
20181 mem = adjust_address (m_tramp, SImode, offset);
20182 emit_move_insn (mem, gen_int_mode (0x90e3ff49, SImode));
20185 gcc_assert (offset <= TRAMPOLINE_SIZE);
20188 #ifdef ENABLE_EXECUTE_STACK
20189 #ifdef CHECK_EXECUTE_STACK_ENABLED
20190 if (CHECK_EXECUTE_STACK_ENABLED)
20192 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
20193 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
20197 /* Codes for all the SSE/MMX builtins. */
20200 IX86_BUILTIN_ADDPS,
20201 IX86_BUILTIN_ADDSS,
20202 IX86_BUILTIN_DIVPS,
20203 IX86_BUILTIN_DIVSS,
20204 IX86_BUILTIN_MULPS,
20205 IX86_BUILTIN_MULSS,
20206 IX86_BUILTIN_SUBPS,
20207 IX86_BUILTIN_SUBSS,
20209 IX86_BUILTIN_CMPEQPS,
20210 IX86_BUILTIN_CMPLTPS,
20211 IX86_BUILTIN_CMPLEPS,
20212 IX86_BUILTIN_CMPGTPS,
20213 IX86_BUILTIN_CMPGEPS,
20214 IX86_BUILTIN_CMPNEQPS,
20215 IX86_BUILTIN_CMPNLTPS,
20216 IX86_BUILTIN_CMPNLEPS,
20217 IX86_BUILTIN_CMPNGTPS,
20218 IX86_BUILTIN_CMPNGEPS,
20219 IX86_BUILTIN_CMPORDPS,
20220 IX86_BUILTIN_CMPUNORDPS,
20221 IX86_BUILTIN_CMPEQSS,
20222 IX86_BUILTIN_CMPLTSS,
20223 IX86_BUILTIN_CMPLESS,
20224 IX86_BUILTIN_CMPNEQSS,
20225 IX86_BUILTIN_CMPNLTSS,
20226 IX86_BUILTIN_CMPNLESS,
20227 IX86_BUILTIN_CMPNGTSS,
20228 IX86_BUILTIN_CMPNGESS,
20229 IX86_BUILTIN_CMPORDSS,
20230 IX86_BUILTIN_CMPUNORDSS,
20232 IX86_BUILTIN_COMIEQSS,
20233 IX86_BUILTIN_COMILTSS,
20234 IX86_BUILTIN_COMILESS,
20235 IX86_BUILTIN_COMIGTSS,
20236 IX86_BUILTIN_COMIGESS,
20237 IX86_BUILTIN_COMINEQSS,
20238 IX86_BUILTIN_UCOMIEQSS,
20239 IX86_BUILTIN_UCOMILTSS,
20240 IX86_BUILTIN_UCOMILESS,
20241 IX86_BUILTIN_UCOMIGTSS,
20242 IX86_BUILTIN_UCOMIGESS,
20243 IX86_BUILTIN_UCOMINEQSS,
20245 IX86_BUILTIN_CVTPI2PS,
20246 IX86_BUILTIN_CVTPS2PI,
20247 IX86_BUILTIN_CVTSI2SS,
20248 IX86_BUILTIN_CVTSI642SS,
20249 IX86_BUILTIN_CVTSS2SI,
20250 IX86_BUILTIN_CVTSS2SI64,
20251 IX86_BUILTIN_CVTTPS2PI,
20252 IX86_BUILTIN_CVTTSS2SI,
20253 IX86_BUILTIN_CVTTSS2SI64,
20255 IX86_BUILTIN_MAXPS,
20256 IX86_BUILTIN_MAXSS,
20257 IX86_BUILTIN_MINPS,
20258 IX86_BUILTIN_MINSS,
20260 IX86_BUILTIN_LOADUPS,
20261 IX86_BUILTIN_STOREUPS,
20262 IX86_BUILTIN_MOVSS,
20264 IX86_BUILTIN_MOVHLPS,
20265 IX86_BUILTIN_MOVLHPS,
20266 IX86_BUILTIN_LOADHPS,
20267 IX86_BUILTIN_LOADLPS,
20268 IX86_BUILTIN_STOREHPS,
20269 IX86_BUILTIN_STORELPS,
20271 IX86_BUILTIN_MASKMOVQ,
20272 IX86_BUILTIN_MOVMSKPS,
20273 IX86_BUILTIN_PMOVMSKB,
20275 IX86_BUILTIN_MOVNTPS,
20276 IX86_BUILTIN_MOVNTQ,
20278 IX86_BUILTIN_LOADDQU,
20279 IX86_BUILTIN_STOREDQU,
20281 IX86_BUILTIN_PACKSSWB,
20282 IX86_BUILTIN_PACKSSDW,
20283 IX86_BUILTIN_PACKUSWB,
20285 IX86_BUILTIN_PADDB,
20286 IX86_BUILTIN_PADDW,
20287 IX86_BUILTIN_PADDD,
20288 IX86_BUILTIN_PADDQ,
20289 IX86_BUILTIN_PADDSB,
20290 IX86_BUILTIN_PADDSW,
20291 IX86_BUILTIN_PADDUSB,
20292 IX86_BUILTIN_PADDUSW,
20293 IX86_BUILTIN_PSUBB,
20294 IX86_BUILTIN_PSUBW,
20295 IX86_BUILTIN_PSUBD,
20296 IX86_BUILTIN_PSUBQ,
20297 IX86_BUILTIN_PSUBSB,
20298 IX86_BUILTIN_PSUBSW,
20299 IX86_BUILTIN_PSUBUSB,
20300 IX86_BUILTIN_PSUBUSW,
20303 IX86_BUILTIN_PANDN,
20307 IX86_BUILTIN_PAVGB,
20308 IX86_BUILTIN_PAVGW,
20310 IX86_BUILTIN_PCMPEQB,
20311 IX86_BUILTIN_PCMPEQW,
20312 IX86_BUILTIN_PCMPEQD,
20313 IX86_BUILTIN_PCMPGTB,
20314 IX86_BUILTIN_PCMPGTW,
20315 IX86_BUILTIN_PCMPGTD,
20317 IX86_BUILTIN_PMADDWD,
20319 IX86_BUILTIN_PMAXSW,
20320 IX86_BUILTIN_PMAXUB,
20321 IX86_BUILTIN_PMINSW,
20322 IX86_BUILTIN_PMINUB,
20324 IX86_BUILTIN_PMULHUW,
20325 IX86_BUILTIN_PMULHW,
20326 IX86_BUILTIN_PMULLW,
20328 IX86_BUILTIN_PSADBW,
20329 IX86_BUILTIN_PSHUFW,
20331 IX86_BUILTIN_PSLLW,
20332 IX86_BUILTIN_PSLLD,
20333 IX86_BUILTIN_PSLLQ,
20334 IX86_BUILTIN_PSRAW,
20335 IX86_BUILTIN_PSRAD,
20336 IX86_BUILTIN_PSRLW,
20337 IX86_BUILTIN_PSRLD,
20338 IX86_BUILTIN_PSRLQ,
20339 IX86_BUILTIN_PSLLWI,
20340 IX86_BUILTIN_PSLLDI,
20341 IX86_BUILTIN_PSLLQI,
20342 IX86_BUILTIN_PSRAWI,
20343 IX86_BUILTIN_PSRADI,
20344 IX86_BUILTIN_PSRLWI,
20345 IX86_BUILTIN_PSRLDI,
20346 IX86_BUILTIN_PSRLQI,
20348 IX86_BUILTIN_PUNPCKHBW,
20349 IX86_BUILTIN_PUNPCKHWD,
20350 IX86_BUILTIN_PUNPCKHDQ,
20351 IX86_BUILTIN_PUNPCKLBW,
20352 IX86_BUILTIN_PUNPCKLWD,
20353 IX86_BUILTIN_PUNPCKLDQ,
20355 IX86_BUILTIN_SHUFPS,
20357 IX86_BUILTIN_RCPPS,
20358 IX86_BUILTIN_RCPSS,
20359 IX86_BUILTIN_RSQRTPS,
20360 IX86_BUILTIN_RSQRTPS_NR,
20361 IX86_BUILTIN_RSQRTSS,
20362 IX86_BUILTIN_RSQRTF,
20363 IX86_BUILTIN_SQRTPS,
20364 IX86_BUILTIN_SQRTPS_NR,
20365 IX86_BUILTIN_SQRTSS,
20367 IX86_BUILTIN_UNPCKHPS,
20368 IX86_BUILTIN_UNPCKLPS,
20370 IX86_BUILTIN_ANDPS,
20371 IX86_BUILTIN_ANDNPS,
20373 IX86_BUILTIN_XORPS,
20376 IX86_BUILTIN_LDMXCSR,
20377 IX86_BUILTIN_STMXCSR,
20378 IX86_BUILTIN_SFENCE,
20380 /* 3DNow! Original */
20381 IX86_BUILTIN_FEMMS,
20382 IX86_BUILTIN_PAVGUSB,
20383 IX86_BUILTIN_PF2ID,
20384 IX86_BUILTIN_PFACC,
20385 IX86_BUILTIN_PFADD,
20386 IX86_BUILTIN_PFCMPEQ,
20387 IX86_BUILTIN_PFCMPGE,
20388 IX86_BUILTIN_PFCMPGT,
20389 IX86_BUILTIN_PFMAX,
20390 IX86_BUILTIN_PFMIN,
20391 IX86_BUILTIN_PFMUL,
20392 IX86_BUILTIN_PFRCP,
20393 IX86_BUILTIN_PFRCPIT1,
20394 IX86_BUILTIN_PFRCPIT2,
20395 IX86_BUILTIN_PFRSQIT1,
20396 IX86_BUILTIN_PFRSQRT,
20397 IX86_BUILTIN_PFSUB,
20398 IX86_BUILTIN_PFSUBR,
20399 IX86_BUILTIN_PI2FD,
20400 IX86_BUILTIN_PMULHRW,
20402 /* 3DNow! Athlon Extensions */
20403 IX86_BUILTIN_PF2IW,
20404 IX86_BUILTIN_PFNACC,
20405 IX86_BUILTIN_PFPNACC,
20406 IX86_BUILTIN_PI2FW,
20407 IX86_BUILTIN_PSWAPDSI,
20408 IX86_BUILTIN_PSWAPDSF,
20411 IX86_BUILTIN_ADDPD,
20412 IX86_BUILTIN_ADDSD,
20413 IX86_BUILTIN_DIVPD,
20414 IX86_BUILTIN_DIVSD,
20415 IX86_BUILTIN_MULPD,
20416 IX86_BUILTIN_MULSD,
20417 IX86_BUILTIN_SUBPD,
20418 IX86_BUILTIN_SUBSD,
20420 IX86_BUILTIN_CMPEQPD,
20421 IX86_BUILTIN_CMPLTPD,
20422 IX86_BUILTIN_CMPLEPD,
20423 IX86_BUILTIN_CMPGTPD,
20424 IX86_BUILTIN_CMPGEPD,
20425 IX86_BUILTIN_CMPNEQPD,
20426 IX86_BUILTIN_CMPNLTPD,
20427 IX86_BUILTIN_CMPNLEPD,
20428 IX86_BUILTIN_CMPNGTPD,
20429 IX86_BUILTIN_CMPNGEPD,
20430 IX86_BUILTIN_CMPORDPD,
20431 IX86_BUILTIN_CMPUNORDPD,
20432 IX86_BUILTIN_CMPEQSD,
20433 IX86_BUILTIN_CMPLTSD,
20434 IX86_BUILTIN_CMPLESD,
20435 IX86_BUILTIN_CMPNEQSD,
20436 IX86_BUILTIN_CMPNLTSD,
20437 IX86_BUILTIN_CMPNLESD,
20438 IX86_BUILTIN_CMPORDSD,
20439 IX86_BUILTIN_CMPUNORDSD,
20441 IX86_BUILTIN_COMIEQSD,
20442 IX86_BUILTIN_COMILTSD,
20443 IX86_BUILTIN_COMILESD,
20444 IX86_BUILTIN_COMIGTSD,
20445 IX86_BUILTIN_COMIGESD,
20446 IX86_BUILTIN_COMINEQSD,
20447 IX86_BUILTIN_UCOMIEQSD,
20448 IX86_BUILTIN_UCOMILTSD,
20449 IX86_BUILTIN_UCOMILESD,
20450 IX86_BUILTIN_UCOMIGTSD,
20451 IX86_BUILTIN_UCOMIGESD,
20452 IX86_BUILTIN_UCOMINEQSD,
20454 IX86_BUILTIN_MAXPD,
20455 IX86_BUILTIN_MAXSD,
20456 IX86_BUILTIN_MINPD,
20457 IX86_BUILTIN_MINSD,
20459 IX86_BUILTIN_ANDPD,
20460 IX86_BUILTIN_ANDNPD,
20462 IX86_BUILTIN_XORPD,
20464 IX86_BUILTIN_SQRTPD,
20465 IX86_BUILTIN_SQRTSD,
20467 IX86_BUILTIN_UNPCKHPD,
20468 IX86_BUILTIN_UNPCKLPD,
20470 IX86_BUILTIN_SHUFPD,
20472 IX86_BUILTIN_LOADUPD,
20473 IX86_BUILTIN_STOREUPD,
20474 IX86_BUILTIN_MOVSD,
20476 IX86_BUILTIN_LOADHPD,
20477 IX86_BUILTIN_LOADLPD,
20479 IX86_BUILTIN_CVTDQ2PD,
20480 IX86_BUILTIN_CVTDQ2PS,
20482 IX86_BUILTIN_CVTPD2DQ,
20483 IX86_BUILTIN_CVTPD2PI,
20484 IX86_BUILTIN_CVTPD2PS,
20485 IX86_BUILTIN_CVTTPD2DQ,
20486 IX86_BUILTIN_CVTTPD2PI,
20488 IX86_BUILTIN_CVTPI2PD,
20489 IX86_BUILTIN_CVTSI2SD,
20490 IX86_BUILTIN_CVTSI642SD,
20492 IX86_BUILTIN_CVTSD2SI,
20493 IX86_BUILTIN_CVTSD2SI64,
20494 IX86_BUILTIN_CVTSD2SS,
20495 IX86_BUILTIN_CVTSS2SD,
20496 IX86_BUILTIN_CVTTSD2SI,
20497 IX86_BUILTIN_CVTTSD2SI64,
20499 IX86_BUILTIN_CVTPS2DQ,
20500 IX86_BUILTIN_CVTPS2PD,
20501 IX86_BUILTIN_CVTTPS2DQ,
20503 IX86_BUILTIN_MOVNTI,
20504 IX86_BUILTIN_MOVNTPD,
20505 IX86_BUILTIN_MOVNTDQ,
20507 IX86_BUILTIN_MOVQ128,
20510 IX86_BUILTIN_MASKMOVDQU,
20511 IX86_BUILTIN_MOVMSKPD,
20512 IX86_BUILTIN_PMOVMSKB128,
20514 IX86_BUILTIN_PACKSSWB128,
20515 IX86_BUILTIN_PACKSSDW128,
20516 IX86_BUILTIN_PACKUSWB128,
20518 IX86_BUILTIN_PADDB128,
20519 IX86_BUILTIN_PADDW128,
20520 IX86_BUILTIN_PADDD128,
20521 IX86_BUILTIN_PADDQ128,
20522 IX86_BUILTIN_PADDSB128,
20523 IX86_BUILTIN_PADDSW128,
20524 IX86_BUILTIN_PADDUSB128,
20525 IX86_BUILTIN_PADDUSW128,
20526 IX86_BUILTIN_PSUBB128,
20527 IX86_BUILTIN_PSUBW128,
20528 IX86_BUILTIN_PSUBD128,
20529 IX86_BUILTIN_PSUBQ128,
20530 IX86_BUILTIN_PSUBSB128,
20531 IX86_BUILTIN_PSUBSW128,
20532 IX86_BUILTIN_PSUBUSB128,
20533 IX86_BUILTIN_PSUBUSW128,
20535 IX86_BUILTIN_PAND128,
20536 IX86_BUILTIN_PANDN128,
20537 IX86_BUILTIN_POR128,
20538 IX86_BUILTIN_PXOR128,
20540 IX86_BUILTIN_PAVGB128,
20541 IX86_BUILTIN_PAVGW128,
20543 IX86_BUILTIN_PCMPEQB128,
20544 IX86_BUILTIN_PCMPEQW128,
20545 IX86_BUILTIN_PCMPEQD128,
20546 IX86_BUILTIN_PCMPGTB128,
20547 IX86_BUILTIN_PCMPGTW128,
20548 IX86_BUILTIN_PCMPGTD128,
20550 IX86_BUILTIN_PMADDWD128,
20552 IX86_BUILTIN_PMAXSW128,
20553 IX86_BUILTIN_PMAXUB128,
20554 IX86_BUILTIN_PMINSW128,
20555 IX86_BUILTIN_PMINUB128,
20557 IX86_BUILTIN_PMULUDQ,
20558 IX86_BUILTIN_PMULUDQ128,
20559 IX86_BUILTIN_PMULHUW128,
20560 IX86_BUILTIN_PMULHW128,
20561 IX86_BUILTIN_PMULLW128,
20563 IX86_BUILTIN_PSADBW128,
20564 IX86_BUILTIN_PSHUFHW,
20565 IX86_BUILTIN_PSHUFLW,
20566 IX86_BUILTIN_PSHUFD,
20568 IX86_BUILTIN_PSLLDQI128,
20569 IX86_BUILTIN_PSLLWI128,
20570 IX86_BUILTIN_PSLLDI128,
20571 IX86_BUILTIN_PSLLQI128,
20572 IX86_BUILTIN_PSRAWI128,
20573 IX86_BUILTIN_PSRADI128,
20574 IX86_BUILTIN_PSRLDQI128,
20575 IX86_BUILTIN_PSRLWI128,
20576 IX86_BUILTIN_PSRLDI128,
20577 IX86_BUILTIN_PSRLQI128,
20579 IX86_BUILTIN_PSLLDQ128,
20580 IX86_BUILTIN_PSLLW128,
20581 IX86_BUILTIN_PSLLD128,
20582 IX86_BUILTIN_PSLLQ128,
20583 IX86_BUILTIN_PSRAW128,
20584 IX86_BUILTIN_PSRAD128,
20585 IX86_BUILTIN_PSRLW128,
20586 IX86_BUILTIN_PSRLD128,
20587 IX86_BUILTIN_PSRLQ128,
20589 IX86_BUILTIN_PUNPCKHBW128,
20590 IX86_BUILTIN_PUNPCKHWD128,
20591 IX86_BUILTIN_PUNPCKHDQ128,
20592 IX86_BUILTIN_PUNPCKHQDQ128,
20593 IX86_BUILTIN_PUNPCKLBW128,
20594 IX86_BUILTIN_PUNPCKLWD128,
20595 IX86_BUILTIN_PUNPCKLDQ128,
20596 IX86_BUILTIN_PUNPCKLQDQ128,
20598 IX86_BUILTIN_CLFLUSH,
20599 IX86_BUILTIN_MFENCE,
20600 IX86_BUILTIN_LFENCE,
20602 IX86_BUILTIN_BSRSI,
20603 IX86_BUILTIN_BSRDI,
20604 IX86_BUILTIN_RDPMC,
20605 IX86_BUILTIN_RDTSC,
20606 IX86_BUILTIN_RDTSCP,
20607 IX86_BUILTIN_ROLQI,
20608 IX86_BUILTIN_ROLHI,
20609 IX86_BUILTIN_RORQI,
20610 IX86_BUILTIN_RORHI,
20613 IX86_BUILTIN_ADDSUBPS,
20614 IX86_BUILTIN_HADDPS,
20615 IX86_BUILTIN_HSUBPS,
20616 IX86_BUILTIN_MOVSHDUP,
20617 IX86_BUILTIN_MOVSLDUP,
20618 IX86_BUILTIN_ADDSUBPD,
20619 IX86_BUILTIN_HADDPD,
20620 IX86_BUILTIN_HSUBPD,
20621 IX86_BUILTIN_LDDQU,
20623 IX86_BUILTIN_MONITOR,
20624 IX86_BUILTIN_MWAIT,
20627 IX86_BUILTIN_PHADDW,
20628 IX86_BUILTIN_PHADDD,
20629 IX86_BUILTIN_PHADDSW,
20630 IX86_BUILTIN_PHSUBW,
20631 IX86_BUILTIN_PHSUBD,
20632 IX86_BUILTIN_PHSUBSW,
20633 IX86_BUILTIN_PMADDUBSW,
20634 IX86_BUILTIN_PMULHRSW,
20635 IX86_BUILTIN_PSHUFB,
20636 IX86_BUILTIN_PSIGNB,
20637 IX86_BUILTIN_PSIGNW,
20638 IX86_BUILTIN_PSIGND,
20639 IX86_BUILTIN_PALIGNR,
20640 IX86_BUILTIN_PABSB,
20641 IX86_BUILTIN_PABSW,
20642 IX86_BUILTIN_PABSD,
20644 IX86_BUILTIN_PHADDW128,
20645 IX86_BUILTIN_PHADDD128,
20646 IX86_BUILTIN_PHADDSW128,
20647 IX86_BUILTIN_PHSUBW128,
20648 IX86_BUILTIN_PHSUBD128,
20649 IX86_BUILTIN_PHSUBSW128,
20650 IX86_BUILTIN_PMADDUBSW128,
20651 IX86_BUILTIN_PMULHRSW128,
20652 IX86_BUILTIN_PSHUFB128,
20653 IX86_BUILTIN_PSIGNB128,
20654 IX86_BUILTIN_PSIGNW128,
20655 IX86_BUILTIN_PSIGND128,
20656 IX86_BUILTIN_PALIGNR128,
20657 IX86_BUILTIN_PABSB128,
20658 IX86_BUILTIN_PABSW128,
20659 IX86_BUILTIN_PABSD128,
20661 /* AMDFAM10 - SSE4A New Instructions. */
20662 IX86_BUILTIN_MOVNTSD,
20663 IX86_BUILTIN_MOVNTSS,
20664 IX86_BUILTIN_EXTRQI,
20665 IX86_BUILTIN_EXTRQ,
20666 IX86_BUILTIN_INSERTQI,
20667 IX86_BUILTIN_INSERTQ,
20670 IX86_BUILTIN_BLENDPD,
20671 IX86_BUILTIN_BLENDPS,
20672 IX86_BUILTIN_BLENDVPD,
20673 IX86_BUILTIN_BLENDVPS,
20674 IX86_BUILTIN_PBLENDVB128,
20675 IX86_BUILTIN_PBLENDW128,
20680 IX86_BUILTIN_INSERTPS128,
20682 IX86_BUILTIN_MOVNTDQA,
20683 IX86_BUILTIN_MPSADBW128,
20684 IX86_BUILTIN_PACKUSDW128,
20685 IX86_BUILTIN_PCMPEQQ,
20686 IX86_BUILTIN_PHMINPOSUW128,
20688 IX86_BUILTIN_PMAXSB128,
20689 IX86_BUILTIN_PMAXSD128,
20690 IX86_BUILTIN_PMAXUD128,
20691 IX86_BUILTIN_PMAXUW128,
20693 IX86_BUILTIN_PMINSB128,
20694 IX86_BUILTIN_PMINSD128,
20695 IX86_BUILTIN_PMINUD128,
20696 IX86_BUILTIN_PMINUW128,
20698 IX86_BUILTIN_PMOVSXBW128,
20699 IX86_BUILTIN_PMOVSXBD128,
20700 IX86_BUILTIN_PMOVSXBQ128,
20701 IX86_BUILTIN_PMOVSXWD128,
20702 IX86_BUILTIN_PMOVSXWQ128,
20703 IX86_BUILTIN_PMOVSXDQ128,
20705 IX86_BUILTIN_PMOVZXBW128,
20706 IX86_BUILTIN_PMOVZXBD128,
20707 IX86_BUILTIN_PMOVZXBQ128,
20708 IX86_BUILTIN_PMOVZXWD128,
20709 IX86_BUILTIN_PMOVZXWQ128,
20710 IX86_BUILTIN_PMOVZXDQ128,
20712 IX86_BUILTIN_PMULDQ128,
20713 IX86_BUILTIN_PMULLD128,
20715 IX86_BUILTIN_ROUNDPD,
20716 IX86_BUILTIN_ROUNDPS,
20717 IX86_BUILTIN_ROUNDSD,
20718 IX86_BUILTIN_ROUNDSS,
20720 IX86_BUILTIN_PTESTZ,
20721 IX86_BUILTIN_PTESTC,
20722 IX86_BUILTIN_PTESTNZC,
20724 IX86_BUILTIN_VEC_INIT_V2SI,
20725 IX86_BUILTIN_VEC_INIT_V4HI,
20726 IX86_BUILTIN_VEC_INIT_V8QI,
20727 IX86_BUILTIN_VEC_EXT_V2DF,
20728 IX86_BUILTIN_VEC_EXT_V2DI,
20729 IX86_BUILTIN_VEC_EXT_V4SF,
20730 IX86_BUILTIN_VEC_EXT_V4SI,
20731 IX86_BUILTIN_VEC_EXT_V8HI,
20732 IX86_BUILTIN_VEC_EXT_V2SI,
20733 IX86_BUILTIN_VEC_EXT_V4HI,
20734 IX86_BUILTIN_VEC_EXT_V16QI,
20735 IX86_BUILTIN_VEC_SET_V2DI,
20736 IX86_BUILTIN_VEC_SET_V4SF,
20737 IX86_BUILTIN_VEC_SET_V4SI,
20738 IX86_BUILTIN_VEC_SET_V8HI,
20739 IX86_BUILTIN_VEC_SET_V4HI,
20740 IX86_BUILTIN_VEC_SET_V16QI,
20742 IX86_BUILTIN_VEC_PACK_SFIX,
20745 IX86_BUILTIN_CRC32QI,
20746 IX86_BUILTIN_CRC32HI,
20747 IX86_BUILTIN_CRC32SI,
20748 IX86_BUILTIN_CRC32DI,
20750 IX86_BUILTIN_PCMPESTRI128,
20751 IX86_BUILTIN_PCMPESTRM128,
20752 IX86_BUILTIN_PCMPESTRA128,
20753 IX86_BUILTIN_PCMPESTRC128,
20754 IX86_BUILTIN_PCMPESTRO128,
20755 IX86_BUILTIN_PCMPESTRS128,
20756 IX86_BUILTIN_PCMPESTRZ128,
20757 IX86_BUILTIN_PCMPISTRI128,
20758 IX86_BUILTIN_PCMPISTRM128,
20759 IX86_BUILTIN_PCMPISTRA128,
20760 IX86_BUILTIN_PCMPISTRC128,
20761 IX86_BUILTIN_PCMPISTRO128,
20762 IX86_BUILTIN_PCMPISTRS128,
20763 IX86_BUILTIN_PCMPISTRZ128,
20765 IX86_BUILTIN_PCMPGTQ,
20767 /* AES instructions */
20768 IX86_BUILTIN_AESENC128,
20769 IX86_BUILTIN_AESENCLAST128,
20770 IX86_BUILTIN_AESDEC128,
20771 IX86_BUILTIN_AESDECLAST128,
20772 IX86_BUILTIN_AESIMC128,
20773 IX86_BUILTIN_AESKEYGENASSIST128,
20775 /* PCLMUL instruction */
20776 IX86_BUILTIN_PCLMULQDQ128,
20779 IX86_BUILTIN_ADDPD256,
20780 IX86_BUILTIN_ADDPS256,
20781 IX86_BUILTIN_ADDSUBPD256,
20782 IX86_BUILTIN_ADDSUBPS256,
20783 IX86_BUILTIN_ANDPD256,
20784 IX86_BUILTIN_ANDPS256,
20785 IX86_BUILTIN_ANDNPD256,
20786 IX86_BUILTIN_ANDNPS256,
20787 IX86_BUILTIN_BLENDPD256,
20788 IX86_BUILTIN_BLENDPS256,
20789 IX86_BUILTIN_BLENDVPD256,
20790 IX86_BUILTIN_BLENDVPS256,
20791 IX86_BUILTIN_DIVPD256,
20792 IX86_BUILTIN_DIVPS256,
20793 IX86_BUILTIN_DPPS256,
20794 IX86_BUILTIN_HADDPD256,
20795 IX86_BUILTIN_HADDPS256,
20796 IX86_BUILTIN_HSUBPD256,
20797 IX86_BUILTIN_HSUBPS256,
20798 IX86_BUILTIN_MAXPD256,
20799 IX86_BUILTIN_MAXPS256,
20800 IX86_BUILTIN_MINPD256,
20801 IX86_BUILTIN_MINPS256,
20802 IX86_BUILTIN_MULPD256,
20803 IX86_BUILTIN_MULPS256,
20804 IX86_BUILTIN_ORPD256,
20805 IX86_BUILTIN_ORPS256,
20806 IX86_BUILTIN_SHUFPD256,
20807 IX86_BUILTIN_SHUFPS256,
20808 IX86_BUILTIN_SUBPD256,
20809 IX86_BUILTIN_SUBPS256,
20810 IX86_BUILTIN_XORPD256,
20811 IX86_BUILTIN_XORPS256,
20812 IX86_BUILTIN_CMPSD,
20813 IX86_BUILTIN_CMPSS,
20814 IX86_BUILTIN_CMPPD,
20815 IX86_BUILTIN_CMPPS,
20816 IX86_BUILTIN_CMPPD256,
20817 IX86_BUILTIN_CMPPS256,
20818 IX86_BUILTIN_CVTDQ2PD256,
20819 IX86_BUILTIN_CVTDQ2PS256,
20820 IX86_BUILTIN_CVTPD2PS256,
20821 IX86_BUILTIN_CVTPS2DQ256,
20822 IX86_BUILTIN_CVTPS2PD256,
20823 IX86_BUILTIN_CVTTPD2DQ256,
20824 IX86_BUILTIN_CVTPD2DQ256,
20825 IX86_BUILTIN_CVTTPS2DQ256,
20826 IX86_BUILTIN_EXTRACTF128PD256,
20827 IX86_BUILTIN_EXTRACTF128PS256,
20828 IX86_BUILTIN_EXTRACTF128SI256,
20829 IX86_BUILTIN_VZEROALL,
20830 IX86_BUILTIN_VZEROUPPER,
20831 IX86_BUILTIN_VZEROUPPER_REX64,
20832 IX86_BUILTIN_VPERMILVARPD,
20833 IX86_BUILTIN_VPERMILVARPS,
20834 IX86_BUILTIN_VPERMILVARPD256,
20835 IX86_BUILTIN_VPERMILVARPS256,
20836 IX86_BUILTIN_VPERMILPD,
20837 IX86_BUILTIN_VPERMILPS,
20838 IX86_BUILTIN_VPERMILPD256,
20839 IX86_BUILTIN_VPERMILPS256,
20840 IX86_BUILTIN_VPERM2F128PD256,
20841 IX86_BUILTIN_VPERM2F128PS256,
20842 IX86_BUILTIN_VPERM2F128SI256,
20843 IX86_BUILTIN_VBROADCASTSS,
20844 IX86_BUILTIN_VBROADCASTSD256,
20845 IX86_BUILTIN_VBROADCASTSS256,
20846 IX86_BUILTIN_VBROADCASTPD256,
20847 IX86_BUILTIN_VBROADCASTPS256,
20848 IX86_BUILTIN_VINSERTF128PD256,
20849 IX86_BUILTIN_VINSERTF128PS256,
20850 IX86_BUILTIN_VINSERTF128SI256,
20851 IX86_BUILTIN_LOADUPD256,
20852 IX86_BUILTIN_LOADUPS256,
20853 IX86_BUILTIN_STOREUPD256,
20854 IX86_BUILTIN_STOREUPS256,
20855 IX86_BUILTIN_LDDQU256,
20856 IX86_BUILTIN_MOVNTDQ256,
20857 IX86_BUILTIN_MOVNTPD256,
20858 IX86_BUILTIN_MOVNTPS256,
20859 IX86_BUILTIN_LOADDQU256,
20860 IX86_BUILTIN_STOREDQU256,
20861 IX86_BUILTIN_MASKLOADPD,
20862 IX86_BUILTIN_MASKLOADPS,
20863 IX86_BUILTIN_MASKSTOREPD,
20864 IX86_BUILTIN_MASKSTOREPS,
20865 IX86_BUILTIN_MASKLOADPD256,
20866 IX86_BUILTIN_MASKLOADPS256,
20867 IX86_BUILTIN_MASKSTOREPD256,
20868 IX86_BUILTIN_MASKSTOREPS256,
20869 IX86_BUILTIN_MOVSHDUP256,
20870 IX86_BUILTIN_MOVSLDUP256,
20871 IX86_BUILTIN_MOVDDUP256,
20873 IX86_BUILTIN_SQRTPD256,
20874 IX86_BUILTIN_SQRTPS256,
20875 IX86_BUILTIN_SQRTPS_NR256,
20876 IX86_BUILTIN_RSQRTPS256,
20877 IX86_BUILTIN_RSQRTPS_NR256,
20879 IX86_BUILTIN_RCPPS256,
20881 IX86_BUILTIN_ROUNDPD256,
20882 IX86_BUILTIN_ROUNDPS256,
20884 IX86_BUILTIN_UNPCKHPD256,
20885 IX86_BUILTIN_UNPCKLPD256,
20886 IX86_BUILTIN_UNPCKHPS256,
20887 IX86_BUILTIN_UNPCKLPS256,
20889 IX86_BUILTIN_SI256_SI,
20890 IX86_BUILTIN_PS256_PS,
20891 IX86_BUILTIN_PD256_PD,
20892 IX86_BUILTIN_SI_SI256,
20893 IX86_BUILTIN_PS_PS256,
20894 IX86_BUILTIN_PD_PD256,
20896 IX86_BUILTIN_VTESTZPD,
20897 IX86_BUILTIN_VTESTCPD,
20898 IX86_BUILTIN_VTESTNZCPD,
20899 IX86_BUILTIN_VTESTZPS,
20900 IX86_BUILTIN_VTESTCPS,
20901 IX86_BUILTIN_VTESTNZCPS,
20902 IX86_BUILTIN_VTESTZPD256,
20903 IX86_BUILTIN_VTESTCPD256,
20904 IX86_BUILTIN_VTESTNZCPD256,
20905 IX86_BUILTIN_VTESTZPS256,
20906 IX86_BUILTIN_VTESTCPS256,
20907 IX86_BUILTIN_VTESTNZCPS256,
20908 IX86_BUILTIN_PTESTZ256,
20909 IX86_BUILTIN_PTESTC256,
20910 IX86_BUILTIN_PTESTNZC256,
20912 IX86_BUILTIN_MOVMSKPD256,
20913 IX86_BUILTIN_MOVMSKPS256,
20915 /* TFmode support builtins. */
20917 IX86_BUILTIN_HUGE_VALQ,
20918 IX86_BUILTIN_FABSQ,
20919 IX86_BUILTIN_COPYSIGNQ,
20921 /* Vectorizer support builtins. */
20922 IX86_BUILTIN_CPYSGNPS,
20923 IX86_BUILTIN_CPYSGNPD,
20925 IX86_BUILTIN_CVTUDQ2PS,
20927 /* FMA4 and XOP instructions. */
20928 IX86_BUILTIN_VFMADDSS,
20929 IX86_BUILTIN_VFMADDSD,
20930 IX86_BUILTIN_VFMADDPS,
20931 IX86_BUILTIN_VFMADDPD,
20932 IX86_BUILTIN_VFMSUBSS,
20933 IX86_BUILTIN_VFMSUBSD,
20934 IX86_BUILTIN_VFMSUBPS,
20935 IX86_BUILTIN_VFMSUBPD,
20936 IX86_BUILTIN_VFMADDSUBPS,
20937 IX86_BUILTIN_VFMADDSUBPD,
20938 IX86_BUILTIN_VFMSUBADDPS,
20939 IX86_BUILTIN_VFMSUBADDPD,
20940 IX86_BUILTIN_VFNMADDSS,
20941 IX86_BUILTIN_VFNMADDSD,
20942 IX86_BUILTIN_VFNMADDPS,
20943 IX86_BUILTIN_VFNMADDPD,
20944 IX86_BUILTIN_VFNMSUBSS,
20945 IX86_BUILTIN_VFNMSUBSD,
20946 IX86_BUILTIN_VFNMSUBPS,
20947 IX86_BUILTIN_VFNMSUBPD,
20948 IX86_BUILTIN_VFMADDPS256,
20949 IX86_BUILTIN_VFMADDPD256,
20950 IX86_BUILTIN_VFMSUBPS256,
20951 IX86_BUILTIN_VFMSUBPD256,
20952 IX86_BUILTIN_VFMADDSUBPS256,
20953 IX86_BUILTIN_VFMADDSUBPD256,
20954 IX86_BUILTIN_VFMSUBADDPS256,
20955 IX86_BUILTIN_VFMSUBADDPD256,
20956 IX86_BUILTIN_VFNMADDPS256,
20957 IX86_BUILTIN_VFNMADDPD256,
20958 IX86_BUILTIN_VFNMSUBPS256,
20959 IX86_BUILTIN_VFNMSUBPD256,
20961 IX86_BUILTIN_VPCMOV,
20962 IX86_BUILTIN_VPCMOV_V2DI,
20963 IX86_BUILTIN_VPCMOV_V4SI,
20964 IX86_BUILTIN_VPCMOV_V8HI,
20965 IX86_BUILTIN_VPCMOV_V16QI,
20966 IX86_BUILTIN_VPCMOV_V4SF,
20967 IX86_BUILTIN_VPCMOV_V2DF,
20968 IX86_BUILTIN_VPCMOV256,
20969 IX86_BUILTIN_VPCMOV_V4DI256,
20970 IX86_BUILTIN_VPCMOV_V8SI256,
20971 IX86_BUILTIN_VPCMOV_V16HI256,
20972 IX86_BUILTIN_VPCMOV_V32QI256,
20973 IX86_BUILTIN_VPCMOV_V8SF256,
20974 IX86_BUILTIN_VPCMOV_V4DF256,
20976 IX86_BUILTIN_VPPERM,
20978 IX86_BUILTIN_VPMACSSWW,
20979 IX86_BUILTIN_VPMACSWW,
20980 IX86_BUILTIN_VPMACSSWD,
20981 IX86_BUILTIN_VPMACSWD,
20982 IX86_BUILTIN_VPMACSSDD,
20983 IX86_BUILTIN_VPMACSDD,
20984 IX86_BUILTIN_VPMACSSDQL,
20985 IX86_BUILTIN_VPMACSSDQH,
20986 IX86_BUILTIN_VPMACSDQL,
20987 IX86_BUILTIN_VPMACSDQH,
20988 IX86_BUILTIN_VPMADCSSWD,
20989 IX86_BUILTIN_VPMADCSWD,
20991 IX86_BUILTIN_VPHADDBW,
20992 IX86_BUILTIN_VPHADDBD,
20993 IX86_BUILTIN_VPHADDBQ,
20994 IX86_BUILTIN_VPHADDWD,
20995 IX86_BUILTIN_VPHADDWQ,
20996 IX86_BUILTIN_VPHADDDQ,
20997 IX86_BUILTIN_VPHADDUBW,
20998 IX86_BUILTIN_VPHADDUBD,
20999 IX86_BUILTIN_VPHADDUBQ,
21000 IX86_BUILTIN_VPHADDUWD,
21001 IX86_BUILTIN_VPHADDUWQ,
21002 IX86_BUILTIN_VPHADDUDQ,
21003 IX86_BUILTIN_VPHSUBBW,
21004 IX86_BUILTIN_VPHSUBWD,
21005 IX86_BUILTIN_VPHSUBDQ,
21007 IX86_BUILTIN_VPROTB,
21008 IX86_BUILTIN_VPROTW,
21009 IX86_BUILTIN_VPROTD,
21010 IX86_BUILTIN_VPROTQ,
21011 IX86_BUILTIN_VPROTB_IMM,
21012 IX86_BUILTIN_VPROTW_IMM,
21013 IX86_BUILTIN_VPROTD_IMM,
21014 IX86_BUILTIN_VPROTQ_IMM,
21016 IX86_BUILTIN_VPSHLB,
21017 IX86_BUILTIN_VPSHLW,
21018 IX86_BUILTIN_VPSHLD,
21019 IX86_BUILTIN_VPSHLQ,
21020 IX86_BUILTIN_VPSHAB,
21021 IX86_BUILTIN_VPSHAW,
21022 IX86_BUILTIN_VPSHAD,
21023 IX86_BUILTIN_VPSHAQ,
21025 IX86_BUILTIN_VFRCZSS,
21026 IX86_BUILTIN_VFRCZSD,
21027 IX86_BUILTIN_VFRCZPS,
21028 IX86_BUILTIN_VFRCZPD,
21029 IX86_BUILTIN_VFRCZPS256,
21030 IX86_BUILTIN_VFRCZPD256,
21032 IX86_BUILTIN_VPCOMEQUB,
21033 IX86_BUILTIN_VPCOMNEUB,
21034 IX86_BUILTIN_VPCOMLTUB,
21035 IX86_BUILTIN_VPCOMLEUB,
21036 IX86_BUILTIN_VPCOMGTUB,
21037 IX86_BUILTIN_VPCOMGEUB,
21038 IX86_BUILTIN_VPCOMFALSEUB,
21039 IX86_BUILTIN_VPCOMTRUEUB,
21041 IX86_BUILTIN_VPCOMEQUW,
21042 IX86_BUILTIN_VPCOMNEUW,
21043 IX86_BUILTIN_VPCOMLTUW,
21044 IX86_BUILTIN_VPCOMLEUW,
21045 IX86_BUILTIN_VPCOMGTUW,
21046 IX86_BUILTIN_VPCOMGEUW,
21047 IX86_BUILTIN_VPCOMFALSEUW,
21048 IX86_BUILTIN_VPCOMTRUEUW,
21050 IX86_BUILTIN_VPCOMEQUD,
21051 IX86_BUILTIN_VPCOMNEUD,
21052 IX86_BUILTIN_VPCOMLTUD,
21053 IX86_BUILTIN_VPCOMLEUD,
21054 IX86_BUILTIN_VPCOMGTUD,
21055 IX86_BUILTIN_VPCOMGEUD,
21056 IX86_BUILTIN_VPCOMFALSEUD,
21057 IX86_BUILTIN_VPCOMTRUEUD,
21059 IX86_BUILTIN_VPCOMEQUQ,
21060 IX86_BUILTIN_VPCOMNEUQ,
21061 IX86_BUILTIN_VPCOMLTUQ,
21062 IX86_BUILTIN_VPCOMLEUQ,
21063 IX86_BUILTIN_VPCOMGTUQ,
21064 IX86_BUILTIN_VPCOMGEUQ,
21065 IX86_BUILTIN_VPCOMFALSEUQ,
21066 IX86_BUILTIN_VPCOMTRUEUQ,
21068 IX86_BUILTIN_VPCOMEQB,
21069 IX86_BUILTIN_VPCOMNEB,
21070 IX86_BUILTIN_VPCOMLTB,
21071 IX86_BUILTIN_VPCOMLEB,
21072 IX86_BUILTIN_VPCOMGTB,
21073 IX86_BUILTIN_VPCOMGEB,
21074 IX86_BUILTIN_VPCOMFALSEB,
21075 IX86_BUILTIN_VPCOMTRUEB,
21077 IX86_BUILTIN_VPCOMEQW,
21078 IX86_BUILTIN_VPCOMNEW,
21079 IX86_BUILTIN_VPCOMLTW,
21080 IX86_BUILTIN_VPCOMLEW,
21081 IX86_BUILTIN_VPCOMGTW,
21082 IX86_BUILTIN_VPCOMGEW,
21083 IX86_BUILTIN_VPCOMFALSEW,
21084 IX86_BUILTIN_VPCOMTRUEW,
21086 IX86_BUILTIN_VPCOMEQD,
21087 IX86_BUILTIN_VPCOMNED,
21088 IX86_BUILTIN_VPCOMLTD,
21089 IX86_BUILTIN_VPCOMLED,
21090 IX86_BUILTIN_VPCOMGTD,
21091 IX86_BUILTIN_VPCOMGED,
21092 IX86_BUILTIN_VPCOMFALSED,
21093 IX86_BUILTIN_VPCOMTRUED,
21095 IX86_BUILTIN_VPCOMEQQ,
21096 IX86_BUILTIN_VPCOMNEQ,
21097 IX86_BUILTIN_VPCOMLTQ,
21098 IX86_BUILTIN_VPCOMLEQ,
21099 IX86_BUILTIN_VPCOMGTQ,
21100 IX86_BUILTIN_VPCOMGEQ,
21101 IX86_BUILTIN_VPCOMFALSEQ,
21102 IX86_BUILTIN_VPCOMTRUEQ,
21104 /* LWP instructions. */
21105 IX86_BUILTIN_LLWPCB16,
21106 IX86_BUILTIN_LLWPCB32,
21107 IX86_BUILTIN_LLWPCB64,
21108 IX86_BUILTIN_SLWPCB16,
21109 IX86_BUILTIN_SLWPCB32,
21110 IX86_BUILTIN_SLWPCB64,
21111 IX86_BUILTIN_LWPVAL16,
21112 IX86_BUILTIN_LWPVAL32,
21113 IX86_BUILTIN_LWPVAL64,
21114 IX86_BUILTIN_LWPINS16,
21115 IX86_BUILTIN_LWPINS32,
21116 IX86_BUILTIN_LWPINS64,
21121 /* Table for the ix86 builtin decls. */
21122 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
21124 /* Table of all of the builtin functions that are possible with different ISA's
21125 but are waiting to be built until a function is declared to use that
21127 struct GTY(()) builtin_isa {
21128 tree type; /* builtin type to use in the declaration */
21129 const char *name; /* function name */
21130 int isa; /* isa_flags this builtin is defined for */
21131 bool const_p; /* true if the declaration is constant */
21134 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
21137 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
21138 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
21139 * function decl in the ix86_builtins array. Returns the function decl or
21140 * NULL_TREE, if the builtin was not added.
21142 * If the front end has a special hook for builtin functions, delay adding
21143 * builtin functions that aren't in the current ISA until the ISA is changed
21144 * with function specific optimization. Doing so, can save about 300K for the
21145 * default compiler. When the builtin is expanded, check at that time whether
21148 * If the front end doesn't have a special hook, record all builtins, even if
21149 * it isn't an instruction set in the current ISA in case the user uses
21150 * function specific options for a different ISA, so that we don't get scope
21151 * errors if a builtin is added in the middle of a function scope. */
21154 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
21156 tree decl = NULL_TREE;
21158 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
21160 ix86_builtins_isa[(int) code].isa = mask;
21162 if ((mask & ix86_isa_flags) != 0
21163 || (lang_hooks.builtin_function
21164 == lang_hooks.builtin_function_ext_scope))
21167 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
21169 ix86_builtins[(int) code] = decl;
21170 ix86_builtins_isa[(int) code].type = NULL_TREE;
21174 ix86_builtins[(int) code] = NULL_TREE;
21175 ix86_builtins_isa[(int) code].const_p = false;
21176 ix86_builtins_isa[(int) code].type = type;
21177 ix86_builtins_isa[(int) code].name = name;
21184 /* Like def_builtin, but also marks the function decl "const". */
21187 def_builtin_const (int mask, const char *name, tree type,
21188 enum ix86_builtins code)
21190 tree decl = def_builtin (mask, name, type, code);
21192 TREE_READONLY (decl) = 1;
21194 ix86_builtins_isa[(int) code].const_p = true;
21199 /* Add any new builtin functions for a given ISA that may not have been
21200 declared. This saves a bit of space compared to adding all of the
21201 declarations to the tree, even if we didn't use them. */
21204 ix86_add_new_builtins (int isa)
21209 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
21211 if ((ix86_builtins_isa[i].isa & isa) != 0
21212 && ix86_builtins_isa[i].type != NULL_TREE)
21214 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
21215 ix86_builtins_isa[i].type,
21216 i, BUILT_IN_MD, NULL,
21219 ix86_builtins[i] = decl;
21220 ix86_builtins_isa[i].type = NULL_TREE;
21221 if (ix86_builtins_isa[i].const_p)
21222 TREE_READONLY (decl) = 1;
21227 /* Bits for builtin_description.flag. */
21229 /* Set when we don't support the comparison natively, and should
21230 swap_comparison in order to support it. */
21231 #define BUILTIN_DESC_SWAP_OPERANDS 1
21233 struct builtin_description
21235 const unsigned int mask;
21236 const enum insn_code icode;
21237 const char *const name;
21238 const enum ix86_builtins code;
21239 const enum rtx_code comparison;
21243 static const struct builtin_description bdesc_comi[] =
21245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
21246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
21247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
21248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
21249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
21250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
21251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
21252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
21253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
21254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
21255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
21256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
21257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
21258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
21259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
21260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
21261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
21262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
21263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
21264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
21265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
21266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
21267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
21268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
21271 static const struct builtin_description bdesc_pcmpestr[] =
21274 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
21275 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
21276 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
21277 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
21278 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
21279 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
21280 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
21283 static const struct builtin_description bdesc_pcmpistr[] =
21286 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
21287 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
21288 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
21289 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
21290 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
21291 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
21292 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
21295 /* Special builtin types */
21296 enum ix86_special_builtin_type
21298 SPECIAL_FTYPE_UNKNOWN,
21301 UINT64_FTYPE_PUNSIGNED,
21302 V32QI_FTYPE_PCCHAR,
21303 V16QI_FTYPE_PCCHAR,
21305 V8SF_FTYPE_PCFLOAT,
21307 V4DF_FTYPE_PCDOUBLE,
21308 V4SF_FTYPE_PCFLOAT,
21309 V2DF_FTYPE_PCDOUBLE,
21310 V8SF_FTYPE_PCV8SF_V8SF,
21311 V4DF_FTYPE_PCV4DF_V4DF,
21312 V4SF_FTYPE_V4SF_PCV2SF,
21313 V4SF_FTYPE_PCV4SF_V4SF,
21314 V2DF_FTYPE_V2DF_PCDOUBLE,
21315 V2DF_FTYPE_PCV2DF_V2DF,
21317 VOID_FTYPE_PV2SF_V4SF,
21318 VOID_FTYPE_PV4DI_V4DI,
21319 VOID_FTYPE_PV2DI_V2DI,
21320 VOID_FTYPE_PCHAR_V32QI,
21321 VOID_FTYPE_PCHAR_V16QI,
21322 VOID_FTYPE_PFLOAT_V8SF,
21323 VOID_FTYPE_PFLOAT_V4SF,
21324 VOID_FTYPE_PDOUBLE_V4DF,
21325 VOID_FTYPE_PDOUBLE_V2DF,
21327 VOID_FTYPE_PINT_INT,
21328 VOID_FTYPE_PV8SF_V8SF_V8SF,
21329 VOID_FTYPE_PV4DF_V4DF_V4DF,
21330 VOID_FTYPE_PV4SF_V4SF_V4SF,
21331 VOID_FTYPE_PV2DF_V2DF_V2DF,
21332 VOID_FTYPE_USHORT_UINT_USHORT,
21333 VOID_FTYPE_UINT_UINT_UINT,
21334 VOID_FTYPE_UINT64_UINT_UINT,
21335 UCHAR_FTYPE_USHORT_UINT_USHORT,
21336 UCHAR_FTYPE_UINT_UINT_UINT,
21337 UCHAR_FTYPE_UINT64_UINT_UINT
21340 /* Builtin types */
21341 enum ix86_builtin_type
21344 FLOAT128_FTYPE_FLOAT128,
21346 FLOAT128_FTYPE_FLOAT128_FLOAT128,
21347 INT_FTYPE_V8SF_V8SF_PTEST,
21348 INT_FTYPE_V4DI_V4DI_PTEST,
21349 INT_FTYPE_V4DF_V4DF_PTEST,
21350 INT_FTYPE_V4SF_V4SF_PTEST,
21351 INT_FTYPE_V2DI_V2DI_PTEST,
21352 INT_FTYPE_V2DF_V2DF_PTEST,
21387 V4SF_FTYPE_V4SF_VEC_MERGE,
21396 V2DF_FTYPE_V2DF_VEC_MERGE,
21407 V16QI_FTYPE_V16QI_V16QI,
21408 V16QI_FTYPE_V8HI_V8HI,
21409 V8QI_FTYPE_V8QI_V8QI,
21410 V8QI_FTYPE_V4HI_V4HI,
21411 V8HI_FTYPE_V8HI_V8HI,
21412 V8HI_FTYPE_V8HI_V8HI_COUNT,
21413 V8HI_FTYPE_V16QI_V16QI,
21414 V8HI_FTYPE_V4SI_V4SI,
21415 V8HI_FTYPE_V8HI_SI_COUNT,
21416 V8SF_FTYPE_V8SF_V8SF,
21417 V8SF_FTYPE_V8SF_V8SI,
21418 V4SI_FTYPE_V4SI_V4SI,
21419 V4SI_FTYPE_V4SI_V4SI_COUNT,
21420 V4SI_FTYPE_V8HI_V8HI,
21421 V4SI_FTYPE_V4SF_V4SF,
21422 V4SI_FTYPE_V2DF_V2DF,
21423 V4SI_FTYPE_V4SI_SI_COUNT,
21424 V4HI_FTYPE_V4HI_V4HI,
21425 V4HI_FTYPE_V4HI_V4HI_COUNT,
21426 V4HI_FTYPE_V8QI_V8QI,
21427 V4HI_FTYPE_V2SI_V2SI,
21428 V4HI_FTYPE_V4HI_SI_COUNT,
21429 V4DF_FTYPE_V4DF_V4DF,
21430 V4DF_FTYPE_V4DF_V4DI,
21431 V4SF_FTYPE_V4SF_V4SF,
21432 V4SF_FTYPE_V4SF_V4SF_SWAP,
21433 V4SF_FTYPE_V4SF_V4SI,
21434 V4SF_FTYPE_V4SF_V2SI,
21435 V4SF_FTYPE_V4SF_V2DF,
21436 V4SF_FTYPE_V4SF_DI,
21437 V4SF_FTYPE_V4SF_SI,
21438 V2DI_FTYPE_V2DI_V2DI,
21439 V2DI_FTYPE_V2DI_V2DI_COUNT,
21440 V2DI_FTYPE_V16QI_V16QI,
21441 V2DI_FTYPE_V4SI_V4SI,
21442 V2DI_FTYPE_V2DI_V16QI,
21443 V2DI_FTYPE_V2DF_V2DF,
21444 V2DI_FTYPE_V2DI_SI_COUNT,
21445 V2SI_FTYPE_V2SI_V2SI,
21446 V2SI_FTYPE_V2SI_V2SI_COUNT,
21447 V2SI_FTYPE_V4HI_V4HI,
21448 V2SI_FTYPE_V2SF_V2SF,
21449 V2SI_FTYPE_V2SI_SI_COUNT,
21450 V2DF_FTYPE_V2DF_V2DF,
21451 V2DF_FTYPE_V2DF_V2DF_SWAP,
21452 V2DF_FTYPE_V2DF_V4SF,
21453 V2DF_FTYPE_V2DF_V2DI,
21454 V2DF_FTYPE_V2DF_DI,
21455 V2DF_FTYPE_V2DF_SI,
21456 V2SF_FTYPE_V2SF_V2SF,
21457 V1DI_FTYPE_V1DI_V1DI,
21458 V1DI_FTYPE_V1DI_V1DI_COUNT,
21459 V1DI_FTYPE_V8QI_V8QI,
21460 V1DI_FTYPE_V2SI_V2SI,
21461 V1DI_FTYPE_V1DI_SI_COUNT,
21462 UINT64_FTYPE_UINT64_UINT64,
21463 UINT_FTYPE_UINT_UINT,
21464 UINT_FTYPE_UINT_USHORT,
21465 UINT_FTYPE_UINT_UCHAR,
21466 UINT16_FTYPE_UINT16_INT,
21467 UINT8_FTYPE_UINT8_INT,
21468 V8HI_FTYPE_V8HI_INT,
21469 V4SI_FTYPE_V4SI_INT,
21470 V4HI_FTYPE_V4HI_INT,
21471 V8SF_FTYPE_V8SF_INT,
21472 V4SI_FTYPE_V8SI_INT,
21473 V4SF_FTYPE_V8SF_INT,
21474 V2DF_FTYPE_V4DF_INT,
21475 V4DF_FTYPE_V4DF_INT,
21476 V4SF_FTYPE_V4SF_INT,
21477 V2DI_FTYPE_V2DI_INT,
21478 V2DI2TI_FTYPE_V2DI_INT,
21479 V2DF_FTYPE_V2DF_INT,
21480 V16QI_FTYPE_V16QI_V16QI_V16QI,
21481 V8SF_FTYPE_V8SF_V8SF_V8SF,
21482 V4DF_FTYPE_V4DF_V4DF_V4DF,
21483 V4SF_FTYPE_V4SF_V4SF_V4SF,
21484 V2DF_FTYPE_V2DF_V2DF_V2DF,
21485 V16QI_FTYPE_V16QI_V16QI_INT,
21486 V8SI_FTYPE_V8SI_V8SI_INT,
21487 V8SI_FTYPE_V8SI_V4SI_INT,
21488 V8HI_FTYPE_V8HI_V8HI_INT,
21489 V8SF_FTYPE_V8SF_V8SF_INT,
21490 V8SF_FTYPE_V8SF_V4SF_INT,
21491 V4SI_FTYPE_V4SI_V4SI_INT,
21492 V4DF_FTYPE_V4DF_V4DF_INT,
21493 V4DF_FTYPE_V4DF_V2DF_INT,
21494 V4SF_FTYPE_V4SF_V4SF_INT,
21495 V2DI_FTYPE_V2DI_V2DI_INT,
21496 V2DI2TI_FTYPE_V2DI_V2DI_INT,
21497 V1DI2DI_FTYPE_V1DI_V1DI_INT,
21498 V2DF_FTYPE_V2DF_V2DF_INT,
21499 V2DI_FTYPE_V2DI_UINT_UINT,
21500 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21503 /* Special builtins with variable number of arguments. */
21504 static const struct builtin_description bdesc_special_args[] =
21506 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21507 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21510 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21513 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21516 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21517 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21518 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21520 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21521 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21522 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21523 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21525 /* SSE or 3DNow!A */
21526 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21527 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21530 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21532 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21540 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21544 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21547 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21550 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21551 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21556 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21582 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21585 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbhi1, "__builtin_ia32_llwpcb16", IX86_BUILTIN_LLWPCB16, UNKNOWN, (int) VOID_FTYPE_VOID },
21586 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbsi1, "__builtin_ia32_llwpcb32", IX86_BUILTIN_LLWPCB32, UNKNOWN, (int) VOID_FTYPE_VOID },
21587 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbdi1, "__builtin_ia32_llwpcb64", IX86_BUILTIN_LLWPCB64, UNKNOWN, (int) VOID_FTYPE_VOID },
21589 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbhi1, "__builtin_ia32_slwpcb16", IX86_BUILTIN_SLWPCB16, UNKNOWN, (int) VOID_FTYPE_VOID },
21590 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbsi1, "__builtin_ia32_slwpcb32", IX86_BUILTIN_SLWPCB32, UNKNOWN, (int) VOID_FTYPE_VOID },
21591 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbdi1, "__builtin_ia32_slwpcb64", IX86_BUILTIN_SLWPCB64, UNKNOWN, (int) VOID_FTYPE_VOID },
21593 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalhi3, "__builtin_ia32_lwpval16", IX86_BUILTIN_LWPVAL16, UNKNOWN, (int) VOID_FTYPE_USHORT_UINT_USHORT },
21594 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
21595 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
21596 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinshi3, "__builtin_ia32_lwpins16", IX86_BUILTIN_LWPINS16, UNKNOWN, (int) UCHAR_FTYPE_USHORT_UINT_USHORT },
21597 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
21598 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
21602 /* Builtins with variable number of arguments. */
21603 static const struct builtin_description bdesc_args[] =
21605 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21606 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21607 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21608 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21609 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21610 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21611 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21614 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21615 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21616 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21617 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21618 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21619 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21621 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21622 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21623 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21624 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21625 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21626 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21627 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21628 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21630 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21631 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21633 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21634 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21635 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21636 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21638 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21639 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21640 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21641 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21642 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21643 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21645 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21646 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21647 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21648 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21649 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21650 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21652 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21653 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21654 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21656 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21658 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21659 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21660 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21661 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21662 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21663 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21665 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21666 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21667 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21668 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21669 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21670 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21672 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21673 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21674 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21675 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21678 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21679 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21680 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21681 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21683 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21684 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21685 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21686 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21687 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21688 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21689 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21690 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21691 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21692 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21693 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21694 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21695 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21696 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21697 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21700 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21701 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21702 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21703 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21704 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21705 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21708 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21709 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21710 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21711 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21712 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21713 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21714 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21715 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21716 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21717 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21718 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21719 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21721 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21723 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21724 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21725 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21726 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21727 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21728 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21729 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21730 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21732 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21733 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21734 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21735 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21736 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21737 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21738 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21739 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21740 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21741 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21742 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21743 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21744 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21745 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21746 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21747 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21748 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21749 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21750 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21751 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21755 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21756 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21757 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21758 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21760 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21761 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21762 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21763 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21765 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21774 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21775 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21777 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21779 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21780 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21781 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21783 /* SSE MMX or 3Dnow!A */
21784 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21785 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21786 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21788 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21789 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21790 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21791 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21793 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21794 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21796 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21799 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21801 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21802 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21803 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21804 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21805 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21812 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21817 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21818 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21819 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21822 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21823 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21825 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21826 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21827 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21828 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21829 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21830 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21831 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21832 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21846 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21847 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21848 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21849 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21850 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21851 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21855 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21856 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21857 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21858 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21860 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21861 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21862 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21863 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21865 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21871 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21873 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21874 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21875 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21876 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21877 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21878 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21879 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21880 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21882 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21883 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21884 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21885 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21886 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21887 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21888 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21889 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21891 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21892 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21894 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21896 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21897 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21899 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21902 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21903 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21906 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21909 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21910 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21911 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21914 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21915 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21916 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21917 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21920 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21921 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21924 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21925 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21927 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21928 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21930 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21931 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21933 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21935 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21936 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21937 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21938 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21941 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21942 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21943 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21944 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21945 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21946 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21948 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21949 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21950 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21951 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21952 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21953 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21954 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21956 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21957 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21958 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21959 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21962 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21967 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21968 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21970 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21973 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21974 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21977 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21978 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21980 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21981 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21982 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21983 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21984 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21985 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21988 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21989 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21990 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21991 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21992 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21993 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21995 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21996 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21997 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21998 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21999 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22000 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22001 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22002 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22003 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22004 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22005 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22006 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22007 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
22008 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
22009 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22010 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22011 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22012 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22013 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22014 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
22015 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22016 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
22017 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22018 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
22021 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
22022 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
22025 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22026 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22027 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
22028 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
22029 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22030 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22031 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22032 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
22033 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
22034 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
22036 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22037 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22038 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22039 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22040 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22041 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22042 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
22043 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
22044 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
22045 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
22046 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
22047 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
22048 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
22050 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
22051 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22052 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22053 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22054 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22055 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22056 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
22057 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22058 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22059 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
22060 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
22061 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
22064 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22065 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22066 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22067 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22069 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22070 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22071 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
22074 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22075 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
22076 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
22077 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
22078 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
22081 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
22082 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
22083 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
22084 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22087 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
22088 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
22090 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22091 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22092 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22093 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
22096 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
22099 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22100 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22101 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22102 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22103 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22104 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22105 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22106 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22107 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22108 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22109 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22110 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22111 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22112 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22113 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22114 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22115 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22116 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22117 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22118 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22119 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22120 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22121 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22122 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22123 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22124 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22126 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
22127 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
22128 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
22129 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
22131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
22134 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
22135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22139 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22140 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
22141 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
22142 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22143 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22144 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
22145 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
22146 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
22147 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
22148 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
22149 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
22150 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22151 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
22152 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22153 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
22154 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
22155 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
22156 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
22157 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
22158 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
22159 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
22160 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22161 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22162 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
22163 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
22164 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
22166 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22167 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22168 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22170 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
22171 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22172 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22173 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22174 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22176 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
22178 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
22179 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
22181 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22182 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
22183 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22184 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
22186 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
22187 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
22188 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
22189 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
22190 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
22191 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
22193 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22194 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22195 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
22196 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22197 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22198 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
22199 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22200 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22201 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
22202 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22203 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22204 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
22205 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22206 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22207 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
22209 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
22210 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
22213 /* FMA4 and XOP. */
22214 enum multi_arg_type {
22236 MULTI_ARG_2_DI_IMM,
22237 MULTI_ARG_2_SI_IMM,
22238 MULTI_ARG_2_HI_IMM,
22239 MULTI_ARG_2_QI_IMM,
22240 MULTI_ARG_2_DI_CMP,
22241 MULTI_ARG_2_SI_CMP,
22242 MULTI_ARG_2_HI_CMP,
22243 MULTI_ARG_2_QI_CMP,
22267 static const struct builtin_description bdesc_multi_arg[] =
22269 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22270 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22271 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22272 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22273 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22274 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22275 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22276 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22278 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22279 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22280 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22281 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22282 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
22283 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
22284 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22285 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22287 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22288 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22289 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
22290 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
22292 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22293 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22294 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22295 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22297 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22298 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22299 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22300 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22302 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22303 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22304 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22305 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22307 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
22308 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
22309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
22310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
22311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
22312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
22313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
22315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
22317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
22318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
22319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
22320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
22321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
22323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
22325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
22327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
22331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
22335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
22338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22339 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
22340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
22341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
22342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
22343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
22344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
22345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
22346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
22348 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
22349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
22350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
22351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
22352 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
22353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
22355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
22356 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
22357 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
22358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
22359 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2256, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
22360 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2256, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
22362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22363 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22364 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22366 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22367 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22368 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22369 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
22370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
22371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22372 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
22373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
22375 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
22376 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
22378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
22379 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22380 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
22381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
22382 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
22383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
22384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
22386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
22387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
22389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
22390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
22391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
22392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
22394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
22395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
22397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
22398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
22399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
22400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
22402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
22405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
22406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
22407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
22408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
22410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
22411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
22413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
22414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
22415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
22416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
22418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
22419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
22421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
22422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
22423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
22424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
22426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
22427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
22429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
22430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
22431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
22432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
22434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
22435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
22437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
22438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
22439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
22440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
22442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
22447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
22448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
22449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
22451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
22456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
22457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
22458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
22462 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
22463 in the current target ISA to allow the user to compile particular modules
22464 with different target specific options that differ from the command line
22467 ix86_init_mmx_sse_builtins (void)
22469 const struct builtin_description * d;
22472 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
22473 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
22474 tree V1DI_type_node
22475 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
22476 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
22477 tree V2DI_type_node
22478 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
22479 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
22480 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
22481 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
22482 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
22483 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
22484 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
22486 tree pchar_type_node = build_pointer_type (char_type_node);
22487 tree pcchar_type_node
22488 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
22489 tree pfloat_type_node = build_pointer_type (float_type_node);
22490 tree pcfloat_type_node
22491 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
22492 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
22493 tree pcv2sf_type_node
22494 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
22495 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
22496 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
22499 tree int_ftype_v4sf_v4sf
22500 = build_function_type_list (integer_type_node,
22501 V4SF_type_node, V4SF_type_node, NULL_TREE);
22502 tree v4si_ftype_v4sf_v4sf
22503 = build_function_type_list (V4SI_type_node,
22504 V4SF_type_node, V4SF_type_node, NULL_TREE);
22505 /* MMX/SSE/integer conversions. */
22506 tree int_ftype_v4sf
22507 = build_function_type_list (integer_type_node,
22508 V4SF_type_node, NULL_TREE);
22509 tree int64_ftype_v4sf
22510 = build_function_type_list (long_long_integer_type_node,
22511 V4SF_type_node, NULL_TREE);
22512 tree int_ftype_v8qi
22513 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
22514 tree v4sf_ftype_v4sf_int
22515 = build_function_type_list (V4SF_type_node,
22516 V4SF_type_node, integer_type_node, NULL_TREE);
22517 tree v4sf_ftype_v4sf_int64
22518 = build_function_type_list (V4SF_type_node,
22519 V4SF_type_node, long_long_integer_type_node,
22521 tree v4sf_ftype_v4sf_v2si
22522 = build_function_type_list (V4SF_type_node,
22523 V4SF_type_node, V2SI_type_node, NULL_TREE);
22525 /* Miscellaneous. */
22526 tree v8qi_ftype_v4hi_v4hi
22527 = build_function_type_list (V8QI_type_node,
22528 V4HI_type_node, V4HI_type_node, NULL_TREE);
22529 tree v4hi_ftype_v2si_v2si
22530 = build_function_type_list (V4HI_type_node,
22531 V2SI_type_node, V2SI_type_node, NULL_TREE);
22532 tree v4sf_ftype_v4sf_v4sf_int
22533 = build_function_type_list (V4SF_type_node,
22534 V4SF_type_node, V4SF_type_node,
22535 integer_type_node, NULL_TREE);
22536 tree v2si_ftype_v4hi_v4hi
22537 = build_function_type_list (V2SI_type_node,
22538 V4HI_type_node, V4HI_type_node, NULL_TREE);
22539 tree v4hi_ftype_v4hi_int
22540 = build_function_type_list (V4HI_type_node,
22541 V4HI_type_node, integer_type_node, NULL_TREE);
22542 tree v2si_ftype_v2si_int
22543 = build_function_type_list (V2SI_type_node,
22544 V2SI_type_node, integer_type_node, NULL_TREE);
22545 tree v1di_ftype_v1di_int
22546 = build_function_type_list (V1DI_type_node,
22547 V1DI_type_node, integer_type_node, NULL_TREE);
22549 tree void_ftype_void
22550 = build_function_type (void_type_node, void_list_node);
22551 tree void_ftype_unsigned
22552 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22553 tree void_ftype_unsigned_unsigned
22554 = build_function_type_list (void_type_node, unsigned_type_node,
22555 unsigned_type_node, NULL_TREE);
22556 tree void_ftype_pcvoid_unsigned_unsigned
22557 = build_function_type_list (void_type_node, const_ptr_type_node,
22558 unsigned_type_node, unsigned_type_node,
22560 tree unsigned_ftype_void
22561 = build_function_type (unsigned_type_node, void_list_node);
22562 tree v2si_ftype_v4sf
22563 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22564 /* Loads/stores. */
22565 tree void_ftype_v8qi_v8qi_pchar
22566 = build_function_type_list (void_type_node,
22567 V8QI_type_node, V8QI_type_node,
22568 pchar_type_node, NULL_TREE);
22569 tree v4sf_ftype_pcfloat
22570 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22571 tree v4sf_ftype_v4sf_pcv2sf
22572 = build_function_type_list (V4SF_type_node,
22573 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22574 tree void_ftype_pv2sf_v4sf
22575 = build_function_type_list (void_type_node,
22576 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22577 tree void_ftype_pfloat_v4sf
22578 = build_function_type_list (void_type_node,
22579 pfloat_type_node, V4SF_type_node, NULL_TREE);
22580 tree void_ftype_pdi_di
22581 = build_function_type_list (void_type_node,
22582 pdi_type_node, long_long_unsigned_type_node,
22584 tree void_ftype_pv2di_v2di
22585 = build_function_type_list (void_type_node,
22586 pv2di_type_node, V2DI_type_node, NULL_TREE);
22587 /* Normal vector unops. */
22588 tree v4sf_ftype_v4sf
22589 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22590 tree v16qi_ftype_v16qi
22591 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22592 tree v8hi_ftype_v8hi
22593 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22594 tree v4si_ftype_v4si
22595 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22596 tree v8qi_ftype_v8qi
22597 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22598 tree v4hi_ftype_v4hi
22599 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22601 /* Normal vector binops. */
22602 tree v4sf_ftype_v4sf_v4sf
22603 = build_function_type_list (V4SF_type_node,
22604 V4SF_type_node, V4SF_type_node, NULL_TREE);
22605 tree v8qi_ftype_v8qi_v8qi
22606 = build_function_type_list (V8QI_type_node,
22607 V8QI_type_node, V8QI_type_node, NULL_TREE);
22608 tree v4hi_ftype_v4hi_v4hi
22609 = build_function_type_list (V4HI_type_node,
22610 V4HI_type_node, V4HI_type_node, NULL_TREE);
22611 tree v2si_ftype_v2si_v2si
22612 = build_function_type_list (V2SI_type_node,
22613 V2SI_type_node, V2SI_type_node, NULL_TREE);
22614 tree v1di_ftype_v1di_v1di
22615 = build_function_type_list (V1DI_type_node,
22616 V1DI_type_node, V1DI_type_node, NULL_TREE);
22617 tree v1di_ftype_v1di_v1di_int
22618 = build_function_type_list (V1DI_type_node,
22619 V1DI_type_node, V1DI_type_node,
22620 integer_type_node, NULL_TREE);
22621 tree v2si_ftype_v2sf
22622 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22623 tree v2sf_ftype_v2si
22624 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22625 tree v2si_ftype_v2si
22626 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22627 tree v2sf_ftype_v2sf
22628 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22629 tree v2sf_ftype_v2sf_v2sf
22630 = build_function_type_list (V2SF_type_node,
22631 V2SF_type_node, V2SF_type_node, NULL_TREE);
22632 tree v2si_ftype_v2sf_v2sf
22633 = build_function_type_list (V2SI_type_node,
22634 V2SF_type_node, V2SF_type_node, NULL_TREE);
22635 tree pint_type_node = build_pointer_type (integer_type_node);
22636 tree pdouble_type_node = build_pointer_type (double_type_node);
22637 tree pcdouble_type_node = build_pointer_type (
22638 build_type_variant (double_type_node, 1, 0));
22639 tree int_ftype_v2df_v2df
22640 = build_function_type_list (integer_type_node,
22641 V2DF_type_node, V2DF_type_node, NULL_TREE);
22643 tree void_ftype_pcvoid
22644 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22645 tree v4sf_ftype_v4si
22646 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22647 tree v4si_ftype_v4sf
22648 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22649 tree v2df_ftype_v4si
22650 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22651 tree v4si_ftype_v2df
22652 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22653 tree v4si_ftype_v2df_v2df
22654 = build_function_type_list (V4SI_type_node,
22655 V2DF_type_node, V2DF_type_node, NULL_TREE);
22656 tree v2si_ftype_v2df
22657 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22658 tree v4sf_ftype_v2df
22659 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22660 tree v2df_ftype_v2si
22661 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22662 tree v2df_ftype_v4sf
22663 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22664 tree int_ftype_v2df
22665 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22666 tree int64_ftype_v2df
22667 = build_function_type_list (long_long_integer_type_node,
22668 V2DF_type_node, NULL_TREE);
22669 tree v2df_ftype_v2df_int
22670 = build_function_type_list (V2DF_type_node,
22671 V2DF_type_node, integer_type_node, NULL_TREE);
22672 tree v2df_ftype_v2df_int64
22673 = build_function_type_list (V2DF_type_node,
22674 V2DF_type_node, long_long_integer_type_node,
22676 tree v4sf_ftype_v4sf_v2df
22677 = build_function_type_list (V4SF_type_node,
22678 V4SF_type_node, V2DF_type_node, NULL_TREE);
22679 tree v2df_ftype_v2df_v4sf
22680 = build_function_type_list (V2DF_type_node,
22681 V2DF_type_node, V4SF_type_node, NULL_TREE);
22682 tree v2df_ftype_v2df_v2df_int
22683 = build_function_type_list (V2DF_type_node,
22684 V2DF_type_node, V2DF_type_node,
22687 tree v2df_ftype_v2df_pcdouble
22688 = build_function_type_list (V2DF_type_node,
22689 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22690 tree void_ftype_pdouble_v2df
22691 = build_function_type_list (void_type_node,
22692 pdouble_type_node, V2DF_type_node, NULL_TREE);
22693 tree void_ftype_pint_int
22694 = build_function_type_list (void_type_node,
22695 pint_type_node, integer_type_node, NULL_TREE);
22696 tree void_ftype_v16qi_v16qi_pchar
22697 = build_function_type_list (void_type_node,
22698 V16QI_type_node, V16QI_type_node,
22699 pchar_type_node, NULL_TREE);
22700 tree v2df_ftype_pcdouble
22701 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22702 tree v2df_ftype_v2df_v2df
22703 = build_function_type_list (V2DF_type_node,
22704 V2DF_type_node, V2DF_type_node, NULL_TREE);
22705 tree v16qi_ftype_v16qi_v16qi
22706 = build_function_type_list (V16QI_type_node,
22707 V16QI_type_node, V16QI_type_node, NULL_TREE);
22708 tree v8hi_ftype_v8hi_v8hi
22709 = build_function_type_list (V8HI_type_node,
22710 V8HI_type_node, V8HI_type_node, NULL_TREE);
22711 tree v4si_ftype_v4si_v4si
22712 = build_function_type_list (V4SI_type_node,
22713 V4SI_type_node, V4SI_type_node, NULL_TREE);
22714 tree v2di_ftype_v2di_v2di
22715 = build_function_type_list (V2DI_type_node,
22716 V2DI_type_node, V2DI_type_node, NULL_TREE);
22717 tree v2di_ftype_v2df_v2df
22718 = build_function_type_list (V2DI_type_node,
22719 V2DF_type_node, V2DF_type_node, NULL_TREE);
22720 tree v2df_ftype_v2df
22721 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22722 tree v2di_ftype_v2di_int
22723 = build_function_type_list (V2DI_type_node,
22724 V2DI_type_node, integer_type_node, NULL_TREE);
22725 tree v2di_ftype_v2di_v2di_int
22726 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22727 V2DI_type_node, integer_type_node, NULL_TREE);
22728 tree v4si_ftype_v4si_int
22729 = build_function_type_list (V4SI_type_node,
22730 V4SI_type_node, integer_type_node, NULL_TREE);
22731 tree v8hi_ftype_v8hi_int
22732 = build_function_type_list (V8HI_type_node,
22733 V8HI_type_node, integer_type_node, NULL_TREE);
22734 tree v4si_ftype_v8hi_v8hi
22735 = build_function_type_list (V4SI_type_node,
22736 V8HI_type_node, V8HI_type_node, NULL_TREE);
22737 tree v1di_ftype_v8qi_v8qi
22738 = build_function_type_list (V1DI_type_node,
22739 V8QI_type_node, V8QI_type_node, NULL_TREE);
22740 tree v1di_ftype_v2si_v2si
22741 = build_function_type_list (V1DI_type_node,
22742 V2SI_type_node, V2SI_type_node, NULL_TREE);
22743 tree v2di_ftype_v16qi_v16qi
22744 = build_function_type_list (V2DI_type_node,
22745 V16QI_type_node, V16QI_type_node, NULL_TREE);
22746 tree v2di_ftype_v4si_v4si
22747 = build_function_type_list (V2DI_type_node,
22748 V4SI_type_node, V4SI_type_node, NULL_TREE);
22749 tree int_ftype_v16qi
22750 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22751 tree v16qi_ftype_pcchar
22752 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22753 tree void_ftype_pchar_v16qi
22754 = build_function_type_list (void_type_node,
22755 pchar_type_node, V16QI_type_node, NULL_TREE);
22757 tree v2di_ftype_v2di_unsigned_unsigned
22758 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22759 unsigned_type_node, unsigned_type_node,
22761 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22762 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22763 unsigned_type_node, unsigned_type_node,
22765 tree v2di_ftype_v2di_v16qi
22766 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22768 tree v2df_ftype_v2df_v2df_v2df
22769 = build_function_type_list (V2DF_type_node,
22770 V2DF_type_node, V2DF_type_node,
22771 V2DF_type_node, NULL_TREE);
22772 tree v4sf_ftype_v4sf_v4sf_v4sf
22773 = build_function_type_list (V4SF_type_node,
22774 V4SF_type_node, V4SF_type_node,
22775 V4SF_type_node, NULL_TREE);
22776 tree v8hi_ftype_v16qi
22777 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22779 tree v4si_ftype_v16qi
22780 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22782 tree v2di_ftype_v16qi
22783 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22785 tree v4si_ftype_v8hi
22786 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22788 tree v2di_ftype_v8hi
22789 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22791 tree v2di_ftype_v4si
22792 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22794 tree v2di_ftype_pv2di
22795 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22797 tree v16qi_ftype_v16qi_v16qi_int
22798 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22799 V16QI_type_node, integer_type_node,
22801 tree v16qi_ftype_v16qi_v16qi_v16qi
22802 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22803 V16QI_type_node, V16QI_type_node,
22805 tree v8hi_ftype_v8hi_v8hi_int
22806 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22807 V8HI_type_node, integer_type_node,
22809 tree v4si_ftype_v4si_v4si_int
22810 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22811 V4SI_type_node, integer_type_node,
22813 tree int_ftype_v2di_v2di
22814 = build_function_type_list (integer_type_node,
22815 V2DI_type_node, V2DI_type_node,
22817 tree int_ftype_v16qi_int_v16qi_int_int
22818 = build_function_type_list (integer_type_node,
22825 tree v16qi_ftype_v16qi_int_v16qi_int_int
22826 = build_function_type_list (V16QI_type_node,
22833 tree int_ftype_v16qi_v16qi_int
22834 = build_function_type_list (integer_type_node,
22841 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22843 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22845 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22847 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22849 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22851 tree V16HI_type_node = build_vector_type_for_mode (intHI_type_node,
22853 tree v8sf_ftype_v8sf
22854 = build_function_type_list (V8SF_type_node,
22857 tree v8si_ftype_v8sf
22858 = build_function_type_list (V8SI_type_node,
22861 tree v8sf_ftype_v8si
22862 = build_function_type_list (V8SF_type_node,
22865 tree v4si_ftype_v4df
22866 = build_function_type_list (V4SI_type_node,
22869 tree v4df_ftype_v4df
22870 = build_function_type_list (V4DF_type_node,
22873 tree v4df_ftype_v4si
22874 = build_function_type_list (V4DF_type_node,
22877 tree v4df_ftype_v4sf
22878 = build_function_type_list (V4DF_type_node,
22881 tree v4sf_ftype_v4df
22882 = build_function_type_list (V4SF_type_node,
22885 tree v8sf_ftype_v8sf_v8sf
22886 = build_function_type_list (V8SF_type_node,
22887 V8SF_type_node, V8SF_type_node,
22889 tree v4df_ftype_v4df_v4df
22890 = build_function_type_list (V4DF_type_node,
22891 V4DF_type_node, V4DF_type_node,
22893 tree v8sf_ftype_v8sf_int
22894 = build_function_type_list (V8SF_type_node,
22895 V8SF_type_node, integer_type_node,
22897 tree v4si_ftype_v8si_int
22898 = build_function_type_list (V4SI_type_node,
22899 V8SI_type_node, integer_type_node,
22901 tree v4df_ftype_v4df_int
22902 = build_function_type_list (V4DF_type_node,
22903 V4DF_type_node, integer_type_node,
22905 tree v4sf_ftype_v8sf_int
22906 = build_function_type_list (V4SF_type_node,
22907 V8SF_type_node, integer_type_node,
22909 tree v2df_ftype_v4df_int
22910 = build_function_type_list (V2DF_type_node,
22911 V4DF_type_node, integer_type_node,
22913 tree v8sf_ftype_v8sf_v8sf_int
22914 = build_function_type_list (V8SF_type_node,
22915 V8SF_type_node, V8SF_type_node,
22918 tree v8sf_ftype_v8sf_v8sf_v8sf
22919 = build_function_type_list (V8SF_type_node,
22920 V8SF_type_node, V8SF_type_node,
22923 tree v4df_ftype_v4df_v4df_v4df
22924 = build_function_type_list (V4DF_type_node,
22925 V4DF_type_node, V4DF_type_node,
22928 tree v8si_ftype_v8si_v8si_int
22929 = build_function_type_list (V8SI_type_node,
22930 V8SI_type_node, V8SI_type_node,
22933 tree v4df_ftype_v4df_v4df_int
22934 = build_function_type_list (V4DF_type_node,
22935 V4DF_type_node, V4DF_type_node,
22938 tree v8sf_ftype_pcfloat
22939 = build_function_type_list (V8SF_type_node,
22942 tree v4df_ftype_pcdouble
22943 = build_function_type_list (V4DF_type_node,
22944 pcdouble_type_node,
22946 tree pcv4sf_type_node
22947 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22948 tree pcv2df_type_node
22949 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22950 tree v8sf_ftype_pcv4sf
22951 = build_function_type_list (V8SF_type_node,
22954 tree v4df_ftype_pcv2df
22955 = build_function_type_list (V4DF_type_node,
22958 tree v32qi_ftype_pcchar
22959 = build_function_type_list (V32QI_type_node,
22962 tree void_ftype_pchar_v32qi
22963 = build_function_type_list (void_type_node,
22964 pchar_type_node, V32QI_type_node,
22966 tree v8si_ftype_v8si_v4si_int
22967 = build_function_type_list (V8SI_type_node,
22968 V8SI_type_node, V4SI_type_node,
22971 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22972 tree void_ftype_pv4di_v4di
22973 = build_function_type_list (void_type_node,
22974 pv4di_type_node, V4DI_type_node,
22976 tree v8sf_ftype_v8sf_v4sf_int
22977 = build_function_type_list (V8SF_type_node,
22978 V8SF_type_node, V4SF_type_node,
22981 tree v4df_ftype_v4df_v2df_int
22982 = build_function_type_list (V4DF_type_node,
22983 V4DF_type_node, V2DF_type_node,
22986 tree void_ftype_pfloat_v8sf
22987 = build_function_type_list (void_type_node,
22988 pfloat_type_node, V8SF_type_node,
22990 tree void_ftype_pdouble_v4df
22991 = build_function_type_list (void_type_node,
22992 pdouble_type_node, V4DF_type_node,
22994 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22995 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22996 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22997 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22998 tree pcv8sf_type_node
22999 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
23000 tree pcv4df_type_node
23001 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
23002 tree v8sf_ftype_pcv8sf_v8sf
23003 = build_function_type_list (V8SF_type_node,
23004 pcv8sf_type_node, V8SF_type_node,
23006 tree v4df_ftype_pcv4df_v4df
23007 = build_function_type_list (V4DF_type_node,
23008 pcv4df_type_node, V4DF_type_node,
23010 tree v4sf_ftype_pcv4sf_v4sf
23011 = build_function_type_list (V4SF_type_node,
23012 pcv4sf_type_node, V4SF_type_node,
23014 tree v2df_ftype_pcv2df_v2df
23015 = build_function_type_list (V2DF_type_node,
23016 pcv2df_type_node, V2DF_type_node,
23018 tree void_ftype_pv8sf_v8sf_v8sf
23019 = build_function_type_list (void_type_node,
23020 pv8sf_type_node, V8SF_type_node,
23023 tree void_ftype_pv4df_v4df_v4df
23024 = build_function_type_list (void_type_node,
23025 pv4df_type_node, V4DF_type_node,
23028 tree void_ftype_pv4sf_v4sf_v4sf
23029 = build_function_type_list (void_type_node,
23030 pv4sf_type_node, V4SF_type_node,
23033 tree void_ftype_pv2df_v2df_v2df
23034 = build_function_type_list (void_type_node,
23035 pv2df_type_node, V2DF_type_node,
23038 tree v4df_ftype_v2df
23039 = build_function_type_list (V4DF_type_node,
23042 tree v8sf_ftype_v4sf
23043 = build_function_type_list (V8SF_type_node,
23046 tree v8si_ftype_v4si
23047 = build_function_type_list (V8SI_type_node,
23050 tree v2df_ftype_v4df
23051 = build_function_type_list (V2DF_type_node,
23054 tree v4sf_ftype_v8sf
23055 = build_function_type_list (V4SF_type_node,
23058 tree v4si_ftype_v8si
23059 = build_function_type_list (V4SI_type_node,
23062 tree int_ftype_v4df
23063 = build_function_type_list (integer_type_node,
23066 tree int_ftype_v8sf
23067 = build_function_type_list (integer_type_node,
23070 tree int_ftype_v8sf_v8sf
23071 = build_function_type_list (integer_type_node,
23072 V8SF_type_node, V8SF_type_node,
23074 tree int_ftype_v4di_v4di
23075 = build_function_type_list (integer_type_node,
23076 V4DI_type_node, V4DI_type_node,
23078 tree int_ftype_v4df_v4df
23079 = build_function_type_list (integer_type_node,
23080 V4DF_type_node, V4DF_type_node,
23082 tree v8sf_ftype_v8sf_v8si
23083 = build_function_type_list (V8SF_type_node,
23084 V8SF_type_node, V8SI_type_node,
23086 tree v4df_ftype_v4df_v4di
23087 = build_function_type_list (V4DF_type_node,
23088 V4DF_type_node, V4DI_type_node,
23090 tree v4sf_ftype_v4sf_v4si
23091 = build_function_type_list (V4SF_type_node,
23092 V4SF_type_node, V4SI_type_node, NULL_TREE);
23093 tree v2df_ftype_v2df_v2di
23094 = build_function_type_list (V2DF_type_node,
23095 V2DF_type_node, V2DI_type_node, NULL_TREE);
23097 /* XOP instructions */
23098 tree v2di_ftype_v2di_v2di_v2di
23099 = build_function_type_list (V2DI_type_node,
23105 tree v4di_ftype_v4di_v4di_v4di
23106 = build_function_type_list (V4DI_type_node,
23112 tree v4si_ftype_v4si_v4si_v4si
23113 = build_function_type_list (V4SI_type_node,
23119 tree v8si_ftype_v8si_v8si_v8si
23120 = build_function_type_list (V8SI_type_node,
23126 tree v32qi_ftype_v32qi_v32qi_v32qi
23127 = build_function_type_list (V32QI_type_node,
23133 tree v4si_ftype_v4si_v4si_v2di
23134 = build_function_type_list (V4SI_type_node,
23140 tree v8hi_ftype_v8hi_v8hi_v8hi
23141 = build_function_type_list (V8HI_type_node,
23147 tree v16hi_ftype_v16hi_v16hi_v16hi
23148 = build_function_type_list (V16HI_type_node,
23154 tree v8hi_ftype_v8hi_v8hi_v4si
23155 = build_function_type_list (V8HI_type_node,
23161 tree v2di_ftype_v2di_si
23162 = build_function_type_list (V2DI_type_node,
23167 tree v4si_ftype_v4si_si
23168 = build_function_type_list (V4SI_type_node,
23173 tree v8hi_ftype_v8hi_si
23174 = build_function_type_list (V8HI_type_node,
23179 tree v16qi_ftype_v16qi_si
23180 = build_function_type_list (V16QI_type_node,
23185 tree v2di_ftype_v2di
23186 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
23188 tree v16qi_ftype_v8hi_v8hi
23189 = build_function_type_list (V16QI_type_node,
23190 V8HI_type_node, V8HI_type_node,
23192 tree v8hi_ftype_v4si_v4si
23193 = build_function_type_list (V8HI_type_node,
23194 V4SI_type_node, V4SI_type_node,
23196 tree v8hi_ftype_v16qi_v16qi
23197 = build_function_type_list (V8HI_type_node,
23198 V16QI_type_node, V16QI_type_node,
23200 tree v4hi_ftype_v8qi_v8qi
23201 = build_function_type_list (V4HI_type_node,
23202 V8QI_type_node, V8QI_type_node,
23204 tree unsigned_ftype_unsigned_uchar
23205 = build_function_type_list (unsigned_type_node,
23206 unsigned_type_node,
23207 unsigned_char_type_node,
23209 tree unsigned_ftype_unsigned_ushort
23210 = build_function_type_list (unsigned_type_node,
23211 unsigned_type_node,
23212 short_unsigned_type_node,
23214 tree unsigned_ftype_unsigned_unsigned
23215 = build_function_type_list (unsigned_type_node,
23216 unsigned_type_node,
23217 unsigned_type_node,
23219 tree uint64_ftype_uint64_uint64
23220 = build_function_type_list (long_long_unsigned_type_node,
23221 long_long_unsigned_type_node,
23222 long_long_unsigned_type_node,
23224 tree float_ftype_float
23225 = build_function_type_list (float_type_node,
23229 /* Integer intrinsics. */
23230 tree uint64_ftype_void
23231 = build_function_type (long_long_unsigned_type_node,
23234 = build_function_type_list (integer_type_node,
23235 integer_type_node, NULL_TREE);
23236 tree int64_ftype_int64
23237 = build_function_type_list (long_long_integer_type_node,
23238 long_long_integer_type_node,
23240 tree uint64_ftype_int
23241 = build_function_type_list (long_long_unsigned_type_node,
23242 integer_type_node, NULL_TREE);
23243 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
23244 tree uint64_ftype_punsigned
23245 = build_function_type_list (long_long_unsigned_type_node,
23246 punsigned_type_node, NULL_TREE);
23247 tree ushort_ftype_ushort_int
23248 = build_function_type_list (short_unsigned_type_node,
23249 short_unsigned_type_node,
23252 tree uchar_ftype_uchar_int
23253 = build_function_type_list (unsigned_char_type_node,
23254 unsigned_char_type_node,
23258 /* LWP instructions. */
23260 tree void_ftype_ushort_unsigned_ushort
23261 = build_function_type_list (void_type_node,
23262 short_unsigned_type_node,
23263 unsigned_type_node,
23264 short_unsigned_type_node,
23267 tree void_ftype_unsigned_unsigned_unsigned
23268 = build_function_type_list (void_type_node,
23269 unsigned_type_node,
23270 unsigned_type_node,
23271 unsigned_type_node,
23274 tree void_ftype_uint64_unsigned_unsigned
23275 = build_function_type_list (void_type_node,
23276 long_long_unsigned_type_node,
23277 unsigned_type_node,
23278 unsigned_type_node,
23281 tree uchar_ftype_ushort_unsigned_ushort
23282 = build_function_type_list (unsigned_char_type_node,
23283 short_unsigned_type_node,
23284 unsigned_type_node,
23285 short_unsigned_type_node,
23288 tree uchar_ftype_unsigned_unsigned_unsigned
23289 = build_function_type_list (unsigned_char_type_node,
23290 unsigned_type_node,
23291 unsigned_type_node,
23292 unsigned_type_node,
23295 tree uchar_ftype_uint64_unsigned_unsigned
23296 = build_function_type_list (unsigned_char_type_node,
23297 long_long_unsigned_type_node,
23298 unsigned_type_node,
23299 unsigned_type_node,
23304 /* Add all special builtins with variable number of operands. */
23305 for (i = 0, d = bdesc_special_args;
23306 i < ARRAY_SIZE (bdesc_special_args);
23314 switch ((enum ix86_special_builtin_type) d->flag)
23316 case VOID_FTYPE_VOID:
23317 type = void_ftype_void;
23319 case UINT64_FTYPE_VOID:
23320 type = uint64_ftype_void;
23322 case UINT64_FTYPE_PUNSIGNED:
23323 type = uint64_ftype_punsigned;
23325 case V32QI_FTYPE_PCCHAR:
23326 type = v32qi_ftype_pcchar;
23328 case V16QI_FTYPE_PCCHAR:
23329 type = v16qi_ftype_pcchar;
23331 case V8SF_FTYPE_PCV4SF:
23332 type = v8sf_ftype_pcv4sf;
23334 case V8SF_FTYPE_PCFLOAT:
23335 type = v8sf_ftype_pcfloat;
23337 case V4DF_FTYPE_PCV2DF:
23338 type = v4df_ftype_pcv2df;
23340 case V4DF_FTYPE_PCDOUBLE:
23341 type = v4df_ftype_pcdouble;
23343 case V4SF_FTYPE_PCFLOAT:
23344 type = v4sf_ftype_pcfloat;
23346 case V2DI_FTYPE_PV2DI:
23347 type = v2di_ftype_pv2di;
23349 case V2DF_FTYPE_PCDOUBLE:
23350 type = v2df_ftype_pcdouble;
23352 case V8SF_FTYPE_PCV8SF_V8SF:
23353 type = v8sf_ftype_pcv8sf_v8sf;
23355 case V4DF_FTYPE_PCV4DF_V4DF:
23356 type = v4df_ftype_pcv4df_v4df;
23358 case V4SF_FTYPE_V4SF_PCV2SF:
23359 type = v4sf_ftype_v4sf_pcv2sf;
23361 case V4SF_FTYPE_PCV4SF_V4SF:
23362 type = v4sf_ftype_pcv4sf_v4sf;
23364 case V2DF_FTYPE_V2DF_PCDOUBLE:
23365 type = v2df_ftype_v2df_pcdouble;
23367 case V2DF_FTYPE_PCV2DF_V2DF:
23368 type = v2df_ftype_pcv2df_v2df;
23370 case VOID_FTYPE_PV2SF_V4SF:
23371 type = void_ftype_pv2sf_v4sf;
23373 case VOID_FTYPE_PV4DI_V4DI:
23374 type = void_ftype_pv4di_v4di;
23376 case VOID_FTYPE_PV2DI_V2DI:
23377 type = void_ftype_pv2di_v2di;
23379 case VOID_FTYPE_PCHAR_V32QI:
23380 type = void_ftype_pchar_v32qi;
23382 case VOID_FTYPE_PCHAR_V16QI:
23383 type = void_ftype_pchar_v16qi;
23385 case VOID_FTYPE_PFLOAT_V8SF:
23386 type = void_ftype_pfloat_v8sf;
23388 case VOID_FTYPE_PFLOAT_V4SF:
23389 type = void_ftype_pfloat_v4sf;
23391 case VOID_FTYPE_PDOUBLE_V4DF:
23392 type = void_ftype_pdouble_v4df;
23394 case VOID_FTYPE_PDOUBLE_V2DF:
23395 type = void_ftype_pdouble_v2df;
23397 case VOID_FTYPE_PDI_DI:
23398 type = void_ftype_pdi_di;
23400 case VOID_FTYPE_PINT_INT:
23401 type = void_ftype_pint_int;
23403 case VOID_FTYPE_PV8SF_V8SF_V8SF:
23404 type = void_ftype_pv8sf_v8sf_v8sf;
23406 case VOID_FTYPE_PV4DF_V4DF_V4DF:
23407 type = void_ftype_pv4df_v4df_v4df;
23409 case VOID_FTYPE_PV4SF_V4SF_V4SF:
23410 type = void_ftype_pv4sf_v4sf_v4sf;
23412 case VOID_FTYPE_PV2DF_V2DF_V2DF:
23413 type = void_ftype_pv2df_v2df_v2df;
23415 case VOID_FTYPE_USHORT_UINT_USHORT:
23416 type = void_ftype_ushort_unsigned_ushort;
23418 case VOID_FTYPE_UINT_UINT_UINT:
23419 type = void_ftype_unsigned_unsigned_unsigned;
23421 case VOID_FTYPE_UINT64_UINT_UINT:
23422 type = void_ftype_uint64_unsigned_unsigned;
23424 case UCHAR_FTYPE_USHORT_UINT_USHORT:
23425 type = uchar_ftype_ushort_unsigned_ushort;
23427 case UCHAR_FTYPE_UINT_UINT_UINT:
23428 type = uchar_ftype_unsigned_unsigned_unsigned;
23430 case UCHAR_FTYPE_UINT64_UINT_UINT:
23431 type = uchar_ftype_uint64_unsigned_unsigned;
23435 gcc_unreachable ();
23438 def_builtin (d->mask, d->name, type, d->code);
23441 /* Add all builtins with variable number of operands. */
23442 for (i = 0, d = bdesc_args;
23443 i < ARRAY_SIZE (bdesc_args);
23451 switch ((enum ix86_builtin_type) d->flag)
23453 case FLOAT_FTYPE_FLOAT:
23454 type = float_ftype_float;
23456 case INT_FTYPE_V8SF_V8SF_PTEST:
23457 type = int_ftype_v8sf_v8sf;
23459 case INT_FTYPE_V4DI_V4DI_PTEST:
23460 type = int_ftype_v4di_v4di;
23462 case INT_FTYPE_V4DF_V4DF_PTEST:
23463 type = int_ftype_v4df_v4df;
23465 case INT_FTYPE_V4SF_V4SF_PTEST:
23466 type = int_ftype_v4sf_v4sf;
23468 case INT_FTYPE_V2DI_V2DI_PTEST:
23469 type = int_ftype_v2di_v2di;
23471 case INT_FTYPE_V2DF_V2DF_PTEST:
23472 type = int_ftype_v2df_v2df;
23474 case INT_FTYPE_INT:
23475 type = int_ftype_int;
23477 case UINT64_FTYPE_INT:
23478 type = uint64_ftype_int;
23480 case INT64_FTYPE_INT64:
23481 type = int64_ftype_int64;
23483 case INT64_FTYPE_V4SF:
23484 type = int64_ftype_v4sf;
23486 case INT64_FTYPE_V2DF:
23487 type = int64_ftype_v2df;
23489 case INT_FTYPE_V16QI:
23490 type = int_ftype_v16qi;
23492 case INT_FTYPE_V8QI:
23493 type = int_ftype_v8qi;
23495 case INT_FTYPE_V8SF:
23496 type = int_ftype_v8sf;
23498 case INT_FTYPE_V4DF:
23499 type = int_ftype_v4df;
23501 case INT_FTYPE_V4SF:
23502 type = int_ftype_v4sf;
23504 case INT_FTYPE_V2DF:
23505 type = int_ftype_v2df;
23507 case V16QI_FTYPE_V16QI:
23508 type = v16qi_ftype_v16qi;
23510 case V8SI_FTYPE_V8SF:
23511 type = v8si_ftype_v8sf;
23513 case V8SI_FTYPE_V4SI:
23514 type = v8si_ftype_v4si;
23516 case V8HI_FTYPE_V8HI:
23517 type = v8hi_ftype_v8hi;
23519 case V8HI_FTYPE_V16QI:
23520 type = v8hi_ftype_v16qi;
23522 case V8QI_FTYPE_V8QI:
23523 type = v8qi_ftype_v8qi;
23525 case V8SF_FTYPE_V8SF:
23526 type = v8sf_ftype_v8sf;
23528 case V8SF_FTYPE_V8SI:
23529 type = v8sf_ftype_v8si;
23531 case V8SF_FTYPE_V4SF:
23532 type = v8sf_ftype_v4sf;
23534 case V4SI_FTYPE_V4DF:
23535 type = v4si_ftype_v4df;
23537 case V4SI_FTYPE_V4SI:
23538 type = v4si_ftype_v4si;
23540 case V4SI_FTYPE_V16QI:
23541 type = v4si_ftype_v16qi;
23543 case V4SI_FTYPE_V8SI:
23544 type = v4si_ftype_v8si;
23546 case V4SI_FTYPE_V8HI:
23547 type = v4si_ftype_v8hi;
23549 case V4SI_FTYPE_V4SF:
23550 type = v4si_ftype_v4sf;
23552 case V4SI_FTYPE_V2DF:
23553 type = v4si_ftype_v2df;
23555 case V4HI_FTYPE_V4HI:
23556 type = v4hi_ftype_v4hi;
23558 case V4DF_FTYPE_V4DF:
23559 type = v4df_ftype_v4df;
23561 case V4DF_FTYPE_V4SI:
23562 type = v4df_ftype_v4si;
23564 case V4DF_FTYPE_V4SF:
23565 type = v4df_ftype_v4sf;
23567 case V4DF_FTYPE_V2DF:
23568 type = v4df_ftype_v2df;
23570 case V4SF_FTYPE_V4SF:
23571 case V4SF_FTYPE_V4SF_VEC_MERGE:
23572 type = v4sf_ftype_v4sf;
23574 case V4SF_FTYPE_V8SF:
23575 type = v4sf_ftype_v8sf;
23577 case V4SF_FTYPE_V4SI:
23578 type = v4sf_ftype_v4si;
23580 case V4SF_FTYPE_V4DF:
23581 type = v4sf_ftype_v4df;
23583 case V4SF_FTYPE_V2DF:
23584 type = v4sf_ftype_v2df;
23586 case V2DI_FTYPE_V2DI:
23587 type = v2di_ftype_v2di;
23589 case V2DI_FTYPE_V16QI:
23590 type = v2di_ftype_v16qi;
23592 case V2DI_FTYPE_V8HI:
23593 type = v2di_ftype_v8hi;
23595 case V2DI_FTYPE_V4SI:
23596 type = v2di_ftype_v4si;
23598 case V2SI_FTYPE_V2SI:
23599 type = v2si_ftype_v2si;
23601 case V2SI_FTYPE_V4SF:
23602 type = v2si_ftype_v4sf;
23604 case V2SI_FTYPE_V2DF:
23605 type = v2si_ftype_v2df;
23607 case V2SI_FTYPE_V2SF:
23608 type = v2si_ftype_v2sf;
23610 case V2DF_FTYPE_V4DF:
23611 type = v2df_ftype_v4df;
23613 case V2DF_FTYPE_V4SF:
23614 type = v2df_ftype_v4sf;
23616 case V2DF_FTYPE_V2DF:
23617 case V2DF_FTYPE_V2DF_VEC_MERGE:
23618 type = v2df_ftype_v2df;
23620 case V2DF_FTYPE_V2SI:
23621 type = v2df_ftype_v2si;
23623 case V2DF_FTYPE_V4SI:
23624 type = v2df_ftype_v4si;
23626 case V2SF_FTYPE_V2SF:
23627 type = v2sf_ftype_v2sf;
23629 case V2SF_FTYPE_V2SI:
23630 type = v2sf_ftype_v2si;
23632 case V16QI_FTYPE_V16QI_V16QI:
23633 type = v16qi_ftype_v16qi_v16qi;
23635 case V16QI_FTYPE_V8HI_V8HI:
23636 type = v16qi_ftype_v8hi_v8hi;
23638 case V8QI_FTYPE_V8QI_V8QI:
23639 type = v8qi_ftype_v8qi_v8qi;
23641 case V8QI_FTYPE_V4HI_V4HI:
23642 type = v8qi_ftype_v4hi_v4hi;
23644 case V8HI_FTYPE_V8HI_V8HI:
23645 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23646 type = v8hi_ftype_v8hi_v8hi;
23648 case V8HI_FTYPE_V16QI_V16QI:
23649 type = v8hi_ftype_v16qi_v16qi;
23651 case V8HI_FTYPE_V4SI_V4SI:
23652 type = v8hi_ftype_v4si_v4si;
23654 case V8HI_FTYPE_V8HI_SI_COUNT:
23655 type = v8hi_ftype_v8hi_int;
23657 case V8SF_FTYPE_V8SF_V8SF:
23658 type = v8sf_ftype_v8sf_v8sf;
23660 case V8SF_FTYPE_V8SF_V8SI:
23661 type = v8sf_ftype_v8sf_v8si;
23663 case V4SI_FTYPE_V4SI_V4SI:
23664 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23665 type = v4si_ftype_v4si_v4si;
23667 case V4SI_FTYPE_V8HI_V8HI:
23668 type = v4si_ftype_v8hi_v8hi;
23670 case V4SI_FTYPE_V4SF_V4SF:
23671 type = v4si_ftype_v4sf_v4sf;
23673 case V4SI_FTYPE_V2DF_V2DF:
23674 type = v4si_ftype_v2df_v2df;
23676 case V4SI_FTYPE_V4SI_SI_COUNT:
23677 type = v4si_ftype_v4si_int;
23679 case V4HI_FTYPE_V4HI_V4HI:
23680 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23681 type = v4hi_ftype_v4hi_v4hi;
23683 case V4HI_FTYPE_V8QI_V8QI:
23684 type = v4hi_ftype_v8qi_v8qi;
23686 case V4HI_FTYPE_V2SI_V2SI:
23687 type = v4hi_ftype_v2si_v2si;
23689 case V4HI_FTYPE_V4HI_SI_COUNT:
23690 type = v4hi_ftype_v4hi_int;
23692 case V4DF_FTYPE_V4DF_V4DF:
23693 type = v4df_ftype_v4df_v4df;
23695 case V4DF_FTYPE_V4DF_V4DI:
23696 type = v4df_ftype_v4df_v4di;
23698 case V4SF_FTYPE_V4SF_V4SF:
23699 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23700 type = v4sf_ftype_v4sf_v4sf;
23702 case V4SF_FTYPE_V4SF_V4SI:
23703 type = v4sf_ftype_v4sf_v4si;
23705 case V4SF_FTYPE_V4SF_V2SI:
23706 type = v4sf_ftype_v4sf_v2si;
23708 case V4SF_FTYPE_V4SF_V2DF:
23709 type = v4sf_ftype_v4sf_v2df;
23711 case V4SF_FTYPE_V4SF_DI:
23712 type = v4sf_ftype_v4sf_int64;
23714 case V4SF_FTYPE_V4SF_SI:
23715 type = v4sf_ftype_v4sf_int;
23717 case V2DI_FTYPE_V2DI_V2DI:
23718 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23719 type = v2di_ftype_v2di_v2di;
23721 case V2DI_FTYPE_V16QI_V16QI:
23722 type = v2di_ftype_v16qi_v16qi;
23724 case V2DI_FTYPE_V4SI_V4SI:
23725 type = v2di_ftype_v4si_v4si;
23727 case V2DI_FTYPE_V2DI_V16QI:
23728 type = v2di_ftype_v2di_v16qi;
23730 case V2DI_FTYPE_V2DF_V2DF:
23731 type = v2di_ftype_v2df_v2df;
23733 case V2DI_FTYPE_V2DI_SI_COUNT:
23734 type = v2di_ftype_v2di_int;
23736 case V2SI_FTYPE_V2SI_V2SI:
23737 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23738 type = v2si_ftype_v2si_v2si;
23740 case V2SI_FTYPE_V4HI_V4HI:
23741 type = v2si_ftype_v4hi_v4hi;
23743 case V2SI_FTYPE_V2SF_V2SF:
23744 type = v2si_ftype_v2sf_v2sf;
23746 case V2SI_FTYPE_V2SI_SI_COUNT:
23747 type = v2si_ftype_v2si_int;
23749 case V2DF_FTYPE_V2DF_V2DF:
23750 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23751 type = v2df_ftype_v2df_v2df;
23753 case V2DF_FTYPE_V2DF_V4SF:
23754 type = v2df_ftype_v2df_v4sf;
23756 case V2DF_FTYPE_V2DF_V2DI:
23757 type = v2df_ftype_v2df_v2di;
23759 case V2DF_FTYPE_V2DF_DI:
23760 type = v2df_ftype_v2df_int64;
23762 case V2DF_FTYPE_V2DF_SI:
23763 type = v2df_ftype_v2df_int;
23765 case V2SF_FTYPE_V2SF_V2SF:
23766 type = v2sf_ftype_v2sf_v2sf;
23768 case V1DI_FTYPE_V1DI_V1DI:
23769 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23770 type = v1di_ftype_v1di_v1di;
23772 case V1DI_FTYPE_V8QI_V8QI:
23773 type = v1di_ftype_v8qi_v8qi;
23775 case V1DI_FTYPE_V2SI_V2SI:
23776 type = v1di_ftype_v2si_v2si;
23778 case V1DI_FTYPE_V1DI_SI_COUNT:
23779 type = v1di_ftype_v1di_int;
23781 case UINT64_FTYPE_UINT64_UINT64:
23782 type = uint64_ftype_uint64_uint64;
23784 case UINT_FTYPE_UINT_UINT:
23785 type = unsigned_ftype_unsigned_unsigned;
23787 case UINT_FTYPE_UINT_USHORT:
23788 type = unsigned_ftype_unsigned_ushort;
23790 case UINT_FTYPE_UINT_UCHAR:
23791 type = unsigned_ftype_unsigned_uchar;
23793 case UINT16_FTYPE_UINT16_INT:
23794 type = ushort_ftype_ushort_int;
23796 case UINT8_FTYPE_UINT8_INT:
23797 type = uchar_ftype_uchar_int;
23799 case V8HI_FTYPE_V8HI_INT:
23800 type = v8hi_ftype_v8hi_int;
23802 case V8SF_FTYPE_V8SF_INT:
23803 type = v8sf_ftype_v8sf_int;
23805 case V4SI_FTYPE_V4SI_INT:
23806 type = v4si_ftype_v4si_int;
23808 case V4SI_FTYPE_V8SI_INT:
23809 type = v4si_ftype_v8si_int;
23811 case V4HI_FTYPE_V4HI_INT:
23812 type = v4hi_ftype_v4hi_int;
23814 case V4DF_FTYPE_V4DF_INT:
23815 type = v4df_ftype_v4df_int;
23817 case V4SF_FTYPE_V4SF_INT:
23818 type = v4sf_ftype_v4sf_int;
23820 case V4SF_FTYPE_V8SF_INT:
23821 type = v4sf_ftype_v8sf_int;
23823 case V2DI_FTYPE_V2DI_INT:
23824 case V2DI2TI_FTYPE_V2DI_INT:
23825 type = v2di_ftype_v2di_int;
23827 case V2DF_FTYPE_V2DF_INT:
23828 type = v2df_ftype_v2df_int;
23830 case V2DF_FTYPE_V4DF_INT:
23831 type = v2df_ftype_v4df_int;
23833 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23834 type = v16qi_ftype_v16qi_v16qi_v16qi;
23836 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23837 type = v8sf_ftype_v8sf_v8sf_v8sf;
23839 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23840 type = v4df_ftype_v4df_v4df_v4df;
23842 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23843 type = v4sf_ftype_v4sf_v4sf_v4sf;
23845 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23846 type = v2df_ftype_v2df_v2df_v2df;
23848 case V16QI_FTYPE_V16QI_V16QI_INT:
23849 type = v16qi_ftype_v16qi_v16qi_int;
23851 case V8SI_FTYPE_V8SI_V8SI_INT:
23852 type = v8si_ftype_v8si_v8si_int;
23854 case V8SI_FTYPE_V8SI_V4SI_INT:
23855 type = v8si_ftype_v8si_v4si_int;
23857 case V8HI_FTYPE_V8HI_V8HI_INT:
23858 type = v8hi_ftype_v8hi_v8hi_int;
23860 case V8SF_FTYPE_V8SF_V8SF_INT:
23861 type = v8sf_ftype_v8sf_v8sf_int;
23863 case V8SF_FTYPE_V8SF_V4SF_INT:
23864 type = v8sf_ftype_v8sf_v4sf_int;
23866 case V4SI_FTYPE_V4SI_V4SI_INT:
23867 type = v4si_ftype_v4si_v4si_int;
23869 case V4DF_FTYPE_V4DF_V4DF_INT:
23870 type = v4df_ftype_v4df_v4df_int;
23872 case V4DF_FTYPE_V4DF_V2DF_INT:
23873 type = v4df_ftype_v4df_v2df_int;
23875 case V4SF_FTYPE_V4SF_V4SF_INT:
23876 type = v4sf_ftype_v4sf_v4sf_int;
23878 case V2DI_FTYPE_V2DI_V2DI_INT:
23879 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23880 type = v2di_ftype_v2di_v2di_int;
23882 case V2DF_FTYPE_V2DF_V2DF_INT:
23883 type = v2df_ftype_v2df_v2df_int;
23885 case V2DI_FTYPE_V2DI_UINT_UINT:
23886 type = v2di_ftype_v2di_unsigned_unsigned;
23888 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23889 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23891 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23892 type = v1di_ftype_v1di_v1di_int;
23895 gcc_unreachable ();
23898 def_builtin_const (d->mask, d->name, type, d->code);
23901 /* pcmpestr[im] insns. */
23902 for (i = 0, d = bdesc_pcmpestr;
23903 i < ARRAY_SIZE (bdesc_pcmpestr);
23906 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23907 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23909 ftype = int_ftype_v16qi_int_v16qi_int_int;
23910 def_builtin_const (d->mask, d->name, ftype, d->code);
23913 /* pcmpistr[im] insns. */
23914 for (i = 0, d = bdesc_pcmpistr;
23915 i < ARRAY_SIZE (bdesc_pcmpistr);
23918 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23919 ftype = v16qi_ftype_v16qi_v16qi_int;
23921 ftype = int_ftype_v16qi_v16qi_int;
23922 def_builtin_const (d->mask, d->name, ftype, d->code);
23925 /* comi/ucomi insns. */
23926 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23927 if (d->mask == OPTION_MASK_ISA_SSE2)
23928 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23930 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23933 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23934 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23936 /* SSE or 3DNow!A */
23937 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23940 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23942 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23943 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23946 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23947 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23950 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23951 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23952 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23953 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23954 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23955 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23958 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23961 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23962 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23964 /* Access to the vec_init patterns. */
23965 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23966 integer_type_node, NULL_TREE);
23967 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23969 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23970 short_integer_type_node,
23971 short_integer_type_node,
23972 short_integer_type_node, NULL_TREE);
23973 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23975 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23976 char_type_node, char_type_node,
23977 char_type_node, char_type_node,
23978 char_type_node, char_type_node,
23979 char_type_node, NULL_TREE);
23980 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23982 /* Access to the vec_extract patterns. */
23983 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23984 integer_type_node, NULL_TREE);
23985 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23987 ftype = build_function_type_list (long_long_integer_type_node,
23988 V2DI_type_node, integer_type_node,
23990 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23992 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23993 integer_type_node, NULL_TREE);
23994 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23996 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23997 integer_type_node, NULL_TREE);
23998 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
24000 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
24001 integer_type_node, NULL_TREE);
24002 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
24004 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
24005 integer_type_node, NULL_TREE);
24006 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
24008 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
24009 integer_type_node, NULL_TREE);
24010 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
24012 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
24013 integer_type_node, NULL_TREE);
24014 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
24016 /* Access to the vec_set patterns. */
24017 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
24019 integer_type_node, NULL_TREE);
24020 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
24022 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
24024 integer_type_node, NULL_TREE);
24025 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
24027 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
24029 integer_type_node, NULL_TREE);
24030 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
24032 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
24034 integer_type_node, NULL_TREE);
24035 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
24037 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
24039 integer_type_node, NULL_TREE);
24040 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
24042 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
24044 integer_type_node, NULL_TREE);
24045 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
24046 /* Add FMA4 multi-arg argument instructions */
24047 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24049 tree mtype = NULL_TREE;
24054 switch ((enum multi_arg_type)d->flag)
24056 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
24057 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
24058 case MULTI_ARG_3_SF2: mtype = v8sf_ftype_v8sf_v8sf_v8sf; break;
24059 case MULTI_ARG_3_DF2: mtype = v4df_ftype_v4df_v4df_v4df; break;
24060 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
24061 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
24062 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
24063 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
24064 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
24065 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
24066 case MULTI_ARG_3_DI2: mtype = v4di_ftype_v4di_v4di_v4di; break;
24067 case MULTI_ARG_3_SI2: mtype = v8si_ftype_v8si_v8si_v8si; break;
24068 case MULTI_ARG_3_HI2: mtype = v16hi_ftype_v16hi_v16hi_v16hi; break;
24069 case MULTI_ARG_3_QI2: mtype = v32qi_ftype_v32qi_v32qi_v32qi; break;
24070 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
24071 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
24072 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
24073 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
24074 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
24075 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
24076 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
24077 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
24078 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
24079 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
24080 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
24081 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
24082 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
24083 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
24084 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
24085 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
24086 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
24087 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
24088 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
24089 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
24090 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
24091 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
24092 case MULTI_ARG_1_SF2: mtype = v8sf_ftype_v8sf; break;
24093 case MULTI_ARG_1_DF2: mtype = v4df_ftype_v4df; break;
24094 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
24095 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
24096 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
24097 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
24098 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
24099 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
24100 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
24101 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
24102 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
24103 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
24105 case MULTI_ARG_UNKNOWN:
24107 gcc_unreachable ();
24111 def_builtin_const (d->mask, d->name, mtype, d->code);
24115 /* Internal method for ix86_init_builtins. */
24118 ix86_init_builtins_va_builtins_abi (void)
24120 tree ms_va_ref, sysv_va_ref;
24121 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
24122 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
24123 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
24124 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
24128 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
24129 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
24130 ms_va_ref = build_reference_type (ms_va_list_type_node);
24132 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
24135 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
24136 fnvoid_va_start_ms =
24137 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
24138 fnvoid_va_end_sysv =
24139 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
24140 fnvoid_va_start_sysv =
24141 build_varargs_function_type_list (void_type_node, sysv_va_ref,
24143 fnvoid_va_copy_ms =
24144 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
24146 fnvoid_va_copy_sysv =
24147 build_function_type_list (void_type_node, sysv_va_ref,
24148 sysv_va_ref, NULL_TREE);
24150 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
24151 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
24152 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
24153 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
24154 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
24155 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
24156 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
24157 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24158 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
24159 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24160 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
24161 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
24165 ix86_init_builtins (void)
24167 tree float128_type_node = make_node (REAL_TYPE);
24170 /* The __float80 type. */
24171 if (TYPE_MODE (long_double_type_node) == XFmode)
24172 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
24176 /* The __float80 type. */
24177 tree float80_type_node = make_node (REAL_TYPE);
24179 TYPE_PRECISION (float80_type_node) = 80;
24180 layout_type (float80_type_node);
24181 (*lang_hooks.types.register_builtin_type) (float80_type_node,
24185 /* The __float128 type. */
24186 TYPE_PRECISION (float128_type_node) = 128;
24187 layout_type (float128_type_node);
24188 (*lang_hooks.types.register_builtin_type) (float128_type_node,
24191 /* TFmode support builtins. */
24192 ftype = build_function_type (float128_type_node, void_list_node);
24193 decl = add_builtin_function ("__builtin_infq", ftype,
24194 IX86_BUILTIN_INFQ, BUILT_IN_MD,
24196 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
24198 decl = add_builtin_function ("__builtin_huge_valq", ftype,
24199 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
24201 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
24203 /* We will expand them to normal call if SSE2 isn't available since
24204 they are used by libgcc. */
24205 ftype = build_function_type_list (float128_type_node,
24206 float128_type_node,
24208 decl = add_builtin_function ("__builtin_fabsq", ftype,
24209 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
24210 "__fabstf2", NULL_TREE);
24211 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
24212 TREE_READONLY (decl) = 1;
24214 ftype = build_function_type_list (float128_type_node,
24215 float128_type_node,
24216 float128_type_node,
24218 decl = add_builtin_function ("__builtin_copysignq", ftype,
24219 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
24220 "__copysigntf3", NULL_TREE);
24221 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
24222 TREE_READONLY (decl) = 1;
24224 ix86_init_mmx_sse_builtins ();
24226 ix86_init_builtins_va_builtins_abi ();
24229 /* Return the ix86 builtin for CODE. */
24232 ix86_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
24234 if (code >= IX86_BUILTIN_MAX)
24235 return error_mark_node;
24237 return ix86_builtins[code];
24240 /* Errors in the source file can cause expand_expr to return const0_rtx
24241 where we expect a vector. To avoid crashing, use one of the vector
24242 clear instructions. */
24244 safe_vector_operand (rtx x, enum machine_mode mode)
24246 if (x == const0_rtx)
24247 x = CONST0_RTX (mode);
24251 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
24254 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
24257 tree arg0 = CALL_EXPR_ARG (exp, 0);
24258 tree arg1 = CALL_EXPR_ARG (exp, 1);
24259 rtx op0 = expand_normal (arg0);
24260 rtx op1 = expand_normal (arg1);
24261 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24262 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24263 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
24265 if (VECTOR_MODE_P (mode0))
24266 op0 = safe_vector_operand (op0, mode0);
24267 if (VECTOR_MODE_P (mode1))
24268 op1 = safe_vector_operand (op1, mode1);
24270 if (optimize || !target
24271 || GET_MODE (target) != tmode
24272 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24273 target = gen_reg_rtx (tmode);
24275 if (GET_MODE (op1) == SImode && mode1 == TImode)
24277 rtx x = gen_reg_rtx (V4SImode);
24278 emit_insn (gen_sse2_loadd (x, op1));
24279 op1 = gen_lowpart (TImode, x);
24282 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
24283 op0 = copy_to_mode_reg (mode0, op0);
24284 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
24285 op1 = copy_to_mode_reg (mode1, op1);
24287 pat = GEN_FCN (icode) (target, op0, op1);
24296 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
24299 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
24300 enum multi_arg_type m_type,
24301 enum rtx_code sub_code)
24306 bool comparison_p = false;
24308 bool last_arg_constant = false;
24309 int num_memory = 0;
24312 enum machine_mode mode;
24315 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24319 case MULTI_ARG_3_SF:
24320 case MULTI_ARG_3_DF:
24321 case MULTI_ARG_3_SF2:
24322 case MULTI_ARG_3_DF2:
24323 case MULTI_ARG_3_DI:
24324 case MULTI_ARG_3_SI:
24325 case MULTI_ARG_3_SI_DI:
24326 case MULTI_ARG_3_HI:
24327 case MULTI_ARG_3_HI_SI:
24328 case MULTI_ARG_3_QI:
24329 case MULTI_ARG_3_DI2:
24330 case MULTI_ARG_3_SI2:
24331 case MULTI_ARG_3_HI2:
24332 case MULTI_ARG_3_QI2:
24336 case MULTI_ARG_2_SF:
24337 case MULTI_ARG_2_DF:
24338 case MULTI_ARG_2_DI:
24339 case MULTI_ARG_2_SI:
24340 case MULTI_ARG_2_HI:
24341 case MULTI_ARG_2_QI:
24345 case MULTI_ARG_2_DI_IMM:
24346 case MULTI_ARG_2_SI_IMM:
24347 case MULTI_ARG_2_HI_IMM:
24348 case MULTI_ARG_2_QI_IMM:
24350 last_arg_constant = true;
24353 case MULTI_ARG_1_SF:
24354 case MULTI_ARG_1_DF:
24355 case MULTI_ARG_1_SF2:
24356 case MULTI_ARG_1_DF2:
24357 case MULTI_ARG_1_DI:
24358 case MULTI_ARG_1_SI:
24359 case MULTI_ARG_1_HI:
24360 case MULTI_ARG_1_QI:
24361 case MULTI_ARG_1_SI_DI:
24362 case MULTI_ARG_1_HI_DI:
24363 case MULTI_ARG_1_HI_SI:
24364 case MULTI_ARG_1_QI_DI:
24365 case MULTI_ARG_1_QI_SI:
24366 case MULTI_ARG_1_QI_HI:
24370 case MULTI_ARG_2_DI_CMP:
24371 case MULTI_ARG_2_SI_CMP:
24372 case MULTI_ARG_2_HI_CMP:
24373 case MULTI_ARG_2_QI_CMP:
24375 comparison_p = true;
24378 case MULTI_ARG_2_SF_TF:
24379 case MULTI_ARG_2_DF_TF:
24380 case MULTI_ARG_2_DI_TF:
24381 case MULTI_ARG_2_SI_TF:
24382 case MULTI_ARG_2_HI_TF:
24383 case MULTI_ARG_2_QI_TF:
24388 case MULTI_ARG_UNKNOWN:
24390 gcc_unreachable ();
24393 if (optimize || !target
24394 || GET_MODE (target) != tmode
24395 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24396 target = gen_reg_rtx (tmode);
24398 gcc_assert (nargs <= 4);
24400 for (i = 0; i < nargs; i++)
24402 tree arg = CALL_EXPR_ARG (exp, i);
24403 rtx op = expand_normal (arg);
24404 int adjust = (comparison_p) ? 1 : 0;
24405 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
24407 if (last_arg_constant && i == nargs-1)
24409 if (!CONST_INT_P (op))
24411 error ("last argument must be an immediate");
24412 return gen_reg_rtx (tmode);
24417 if (VECTOR_MODE_P (mode))
24418 op = safe_vector_operand (op, mode);
24420 /* If we aren't optimizing, only allow one memory operand to be
24422 if (memory_operand (op, mode))
24425 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
24428 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
24430 op = force_reg (mode, op);
24434 args[i].mode = mode;
24440 pat = GEN_FCN (icode) (target, args[0].op);
24445 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
24446 GEN_INT ((int)sub_code));
24447 else if (! comparison_p)
24448 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24451 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
24455 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
24460 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
24464 gcc_unreachable ();
24474 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
24475 insns with vec_merge. */
24478 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
24482 tree arg0 = CALL_EXPR_ARG (exp, 0);
24483 rtx op1, op0 = expand_normal (arg0);
24484 enum machine_mode tmode = insn_data[icode].operand[0].mode;
24485 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
24487 if (optimize || !target
24488 || GET_MODE (target) != tmode
24489 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
24490 target = gen_reg_rtx (tmode);
24492 if (VECTOR_MODE_P (mode0))
24493 op0 = safe_vector_operand (op0, mode0);
24495 if ((optimize && !register_operand (op0, mode0))
24496 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
24497 op0 = copy_to_mode_reg (mode0, op0);
24500 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
24501 op1 = copy_to_mode_reg (mode0, op1);
24503 pat = GEN_FCN (icode) (target, op0, op1);
24510 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
24513 ix86_expand_sse_compare (const struct builtin_description *d,
24514 tree exp, rtx target, bool swap)
24517 tree arg0 = CALL_EXPR_ARG (exp, 0);
24518 tree arg1 = CALL_EXPR_ARG (exp, 1);
24519 rtx op0 = expand_normal (arg0);
24520 rtx op1 = expand_normal (arg1);
24522 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
24523 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
24524 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
24525 enum rtx_code comparison = d->comparison;
24527 if (VECTOR_MODE_P (mode0))
24528 op0 = safe_vector_operand (op0, mode0);
24529 if (VECTOR_MODE_P (mode1))
24530 op1 = safe_vector_operand (op1, mode1);
24532 /* Swap operands if we have a comparison that isn't available in
24536 rtx tmp = gen_reg_rtx (mode1);
24537 emit_move_insn (tmp, op1);
24542 if (optimize || !target
24543 || GET_MODE (target) != tmode
24544 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
24545 target = gen_reg_rtx (tmode);
24547 if ((optimize && !register_operand (op0, mode0))
24548 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
24549 op0 = copy_to_mode_reg (mode0, op0);
24550 if ((optimize && !register_operand (op1, mode1))
24551 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
24552 op1 = copy_to_mode_reg (mode1, op1);
24554 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
24555 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
24562 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
24565 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
24569 tree arg0 = CALL_EXPR_ARG (exp, 0);
24570 tree arg1 = CALL_EXPR_ARG (exp, 1);
24571 rtx op0 = expand_normal (arg0);
24572 rtx op1 = expand_normal (arg1);
24573 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24574 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24575 enum rtx_code comparison = d->comparison;
24577 if (VECTOR_MODE_P (mode0))
24578 op0 = safe_vector_operand (op0, mode0);
24579 if (VECTOR_MODE_P (mode1))
24580 op1 = safe_vector_operand (op1, mode1);
24582 /* Swap operands if we have a comparison that isn't available in
24584 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
24591 target = gen_reg_rtx (SImode);
24592 emit_move_insn (target, const0_rtx);
24593 target = gen_rtx_SUBREG (QImode, target, 0);
24595 if ((optimize && !register_operand (op0, mode0))
24596 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24597 op0 = copy_to_mode_reg (mode0, op0);
24598 if ((optimize && !register_operand (op1, mode1))
24599 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24600 op1 = copy_to_mode_reg (mode1, op1);
24602 pat = GEN_FCN (d->icode) (op0, op1);
24606 emit_insn (gen_rtx_SET (VOIDmode,
24607 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24608 gen_rtx_fmt_ee (comparison, QImode,
24612 return SUBREG_REG (target);
24615 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
24618 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
24622 tree arg0 = CALL_EXPR_ARG (exp, 0);
24623 tree arg1 = CALL_EXPR_ARG (exp, 1);
24624 rtx op0 = expand_normal (arg0);
24625 rtx op1 = expand_normal (arg1);
24626 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
24627 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
24628 enum rtx_code comparison = d->comparison;
24630 if (VECTOR_MODE_P (mode0))
24631 op0 = safe_vector_operand (op0, mode0);
24632 if (VECTOR_MODE_P (mode1))
24633 op1 = safe_vector_operand (op1, mode1);
24635 target = gen_reg_rtx (SImode);
24636 emit_move_insn (target, const0_rtx);
24637 target = gen_rtx_SUBREG (QImode, target, 0);
24639 if ((optimize && !register_operand (op0, mode0))
24640 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
24641 op0 = copy_to_mode_reg (mode0, op0);
24642 if ((optimize && !register_operand (op1, mode1))
24643 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
24644 op1 = copy_to_mode_reg (mode1, op1);
24646 pat = GEN_FCN (d->icode) (op0, op1);
24650 emit_insn (gen_rtx_SET (VOIDmode,
24651 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24652 gen_rtx_fmt_ee (comparison, QImode,
24656 return SUBREG_REG (target);
24659 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
24662 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
24663 tree exp, rtx target)
24666 tree arg0 = CALL_EXPR_ARG (exp, 0);
24667 tree arg1 = CALL_EXPR_ARG (exp, 1);
24668 tree arg2 = CALL_EXPR_ARG (exp, 2);
24669 tree arg3 = CALL_EXPR_ARG (exp, 3);
24670 tree arg4 = CALL_EXPR_ARG (exp, 4);
24671 rtx scratch0, scratch1;
24672 rtx op0 = expand_normal (arg0);
24673 rtx op1 = expand_normal (arg1);
24674 rtx op2 = expand_normal (arg2);
24675 rtx op3 = expand_normal (arg3);
24676 rtx op4 = expand_normal (arg4);
24677 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
24679 tmode0 = insn_data[d->icode].operand[0].mode;
24680 tmode1 = insn_data[d->icode].operand[1].mode;
24681 modev2 = insn_data[d->icode].operand[2].mode;
24682 modei3 = insn_data[d->icode].operand[3].mode;
24683 modev4 = insn_data[d->icode].operand[4].mode;
24684 modei5 = insn_data[d->icode].operand[5].mode;
24685 modeimm = insn_data[d->icode].operand[6].mode;
24687 if (VECTOR_MODE_P (modev2))
24688 op0 = safe_vector_operand (op0, modev2);
24689 if (VECTOR_MODE_P (modev4))
24690 op2 = safe_vector_operand (op2, modev4);
24692 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24693 op0 = copy_to_mode_reg (modev2, op0);
24694 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
24695 op1 = copy_to_mode_reg (modei3, op1);
24696 if ((optimize && !register_operand (op2, modev4))
24697 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
24698 op2 = copy_to_mode_reg (modev4, op2);
24699 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
24700 op3 = copy_to_mode_reg (modei5, op3);
24702 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
24704 error ("the fifth argument must be a 8-bit immediate");
24708 if (d->code == IX86_BUILTIN_PCMPESTRI128)
24710 if (optimize || !target
24711 || GET_MODE (target) != tmode0
24712 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24713 target = gen_reg_rtx (tmode0);
24715 scratch1 = gen_reg_rtx (tmode1);
24717 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
24719 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
24721 if (optimize || !target
24722 || GET_MODE (target) != tmode1
24723 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24724 target = gen_reg_rtx (tmode1);
24726 scratch0 = gen_reg_rtx (tmode0);
24728 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
24732 gcc_assert (d->flag);
24734 scratch0 = gen_reg_rtx (tmode0);
24735 scratch1 = gen_reg_rtx (tmode1);
24737 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
24747 target = gen_reg_rtx (SImode);
24748 emit_move_insn (target, const0_rtx);
24749 target = gen_rtx_SUBREG (QImode, target, 0);
24752 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24753 gen_rtx_fmt_ee (EQ, QImode,
24754 gen_rtx_REG ((enum machine_mode) d->flag,
24757 return SUBREG_REG (target);
24764 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24767 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
24768 tree exp, rtx target)
24771 tree arg0 = CALL_EXPR_ARG (exp, 0);
24772 tree arg1 = CALL_EXPR_ARG (exp, 1);
24773 tree arg2 = CALL_EXPR_ARG (exp, 2);
24774 rtx scratch0, scratch1;
24775 rtx op0 = expand_normal (arg0);
24776 rtx op1 = expand_normal (arg1);
24777 rtx op2 = expand_normal (arg2);
24778 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24780 tmode0 = insn_data[d->icode].operand[0].mode;
24781 tmode1 = insn_data[d->icode].operand[1].mode;
24782 modev2 = insn_data[d->icode].operand[2].mode;
24783 modev3 = insn_data[d->icode].operand[3].mode;
24784 modeimm = insn_data[d->icode].operand[4].mode;
24786 if (VECTOR_MODE_P (modev2))
24787 op0 = safe_vector_operand (op0, modev2);
24788 if (VECTOR_MODE_P (modev3))
24789 op1 = safe_vector_operand (op1, modev3);
24791 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24792 op0 = copy_to_mode_reg (modev2, op0);
24793 if ((optimize && !register_operand (op1, modev3))
24794 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24795 op1 = copy_to_mode_reg (modev3, op1);
24797 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24799 error ("the third argument must be a 8-bit immediate");
24803 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24805 if (optimize || !target
24806 || GET_MODE (target) != tmode0
24807 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24808 target = gen_reg_rtx (tmode0);
24810 scratch1 = gen_reg_rtx (tmode1);
24812 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24814 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24816 if (optimize || !target
24817 || GET_MODE (target) != tmode1
24818 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24819 target = gen_reg_rtx (tmode1);
24821 scratch0 = gen_reg_rtx (tmode0);
24823 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24827 gcc_assert (d->flag);
24829 scratch0 = gen_reg_rtx (tmode0);
24830 scratch1 = gen_reg_rtx (tmode1);
24832 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24842 target = gen_reg_rtx (SImode);
24843 emit_move_insn (target, const0_rtx);
24844 target = gen_rtx_SUBREG (QImode, target, 0);
24847 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24848 gen_rtx_fmt_ee (EQ, QImode,
24849 gen_rtx_REG ((enum machine_mode) d->flag,
24852 return SUBREG_REG (target);
24858 /* Subroutine of ix86_expand_builtin to take care of insns with
24859 variable number of operands. */
24862 ix86_expand_args_builtin (const struct builtin_description *d,
24863 tree exp, rtx target)
24865 rtx pat, real_target;
24866 unsigned int i, nargs;
24867 unsigned int nargs_constant = 0;
24868 int num_memory = 0;
24872 enum machine_mode mode;
24874 bool last_arg_count = false;
24875 enum insn_code icode = d->icode;
24876 const struct insn_data *insn_p = &insn_data[icode];
24877 enum machine_mode tmode = insn_p->operand[0].mode;
24878 enum machine_mode rmode = VOIDmode;
24880 enum rtx_code comparison = d->comparison;
24882 switch ((enum ix86_builtin_type) d->flag)
24884 case INT_FTYPE_V8SF_V8SF_PTEST:
24885 case INT_FTYPE_V4DI_V4DI_PTEST:
24886 case INT_FTYPE_V4DF_V4DF_PTEST:
24887 case INT_FTYPE_V4SF_V4SF_PTEST:
24888 case INT_FTYPE_V2DI_V2DI_PTEST:
24889 case INT_FTYPE_V2DF_V2DF_PTEST:
24890 return ix86_expand_sse_ptest (d, exp, target);
24891 case FLOAT128_FTYPE_FLOAT128:
24892 case FLOAT_FTYPE_FLOAT:
24893 case INT_FTYPE_INT:
24894 case UINT64_FTYPE_INT:
24895 case INT64_FTYPE_INT64:
24896 case INT64_FTYPE_V4SF:
24897 case INT64_FTYPE_V2DF:
24898 case INT_FTYPE_V16QI:
24899 case INT_FTYPE_V8QI:
24900 case INT_FTYPE_V8SF:
24901 case INT_FTYPE_V4DF:
24902 case INT_FTYPE_V4SF:
24903 case INT_FTYPE_V2DF:
24904 case V16QI_FTYPE_V16QI:
24905 case V8SI_FTYPE_V8SF:
24906 case V8SI_FTYPE_V4SI:
24907 case V8HI_FTYPE_V8HI:
24908 case V8HI_FTYPE_V16QI:
24909 case V8QI_FTYPE_V8QI:
24910 case V8SF_FTYPE_V8SF:
24911 case V8SF_FTYPE_V8SI:
24912 case V8SF_FTYPE_V4SF:
24913 case V4SI_FTYPE_V4SI:
24914 case V4SI_FTYPE_V16QI:
24915 case V4SI_FTYPE_V4SF:
24916 case V4SI_FTYPE_V8SI:
24917 case V4SI_FTYPE_V8HI:
24918 case V4SI_FTYPE_V4DF:
24919 case V4SI_FTYPE_V2DF:
24920 case V4HI_FTYPE_V4HI:
24921 case V4DF_FTYPE_V4DF:
24922 case V4DF_FTYPE_V4SI:
24923 case V4DF_FTYPE_V4SF:
24924 case V4DF_FTYPE_V2DF:
24925 case V4SF_FTYPE_V4SF:
24926 case V4SF_FTYPE_V4SI:
24927 case V4SF_FTYPE_V8SF:
24928 case V4SF_FTYPE_V4DF:
24929 case V4SF_FTYPE_V2DF:
24930 case V2DI_FTYPE_V2DI:
24931 case V2DI_FTYPE_V16QI:
24932 case V2DI_FTYPE_V8HI:
24933 case V2DI_FTYPE_V4SI:
24934 case V2DF_FTYPE_V2DF:
24935 case V2DF_FTYPE_V4SI:
24936 case V2DF_FTYPE_V4DF:
24937 case V2DF_FTYPE_V4SF:
24938 case V2DF_FTYPE_V2SI:
24939 case V2SI_FTYPE_V2SI:
24940 case V2SI_FTYPE_V4SF:
24941 case V2SI_FTYPE_V2SF:
24942 case V2SI_FTYPE_V2DF:
24943 case V2SF_FTYPE_V2SF:
24944 case V2SF_FTYPE_V2SI:
24947 case V4SF_FTYPE_V4SF_VEC_MERGE:
24948 case V2DF_FTYPE_V2DF_VEC_MERGE:
24949 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24950 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24951 case V16QI_FTYPE_V16QI_V16QI:
24952 case V16QI_FTYPE_V8HI_V8HI:
24953 case V8QI_FTYPE_V8QI_V8QI:
24954 case V8QI_FTYPE_V4HI_V4HI:
24955 case V8HI_FTYPE_V8HI_V8HI:
24956 case V8HI_FTYPE_V16QI_V16QI:
24957 case V8HI_FTYPE_V4SI_V4SI:
24958 case V8SF_FTYPE_V8SF_V8SF:
24959 case V8SF_FTYPE_V8SF_V8SI:
24960 case V4SI_FTYPE_V4SI_V4SI:
24961 case V4SI_FTYPE_V8HI_V8HI:
24962 case V4SI_FTYPE_V4SF_V4SF:
24963 case V4SI_FTYPE_V2DF_V2DF:
24964 case V4HI_FTYPE_V4HI_V4HI:
24965 case V4HI_FTYPE_V8QI_V8QI:
24966 case V4HI_FTYPE_V2SI_V2SI:
24967 case V4DF_FTYPE_V4DF_V4DF:
24968 case V4DF_FTYPE_V4DF_V4DI:
24969 case V4SF_FTYPE_V4SF_V4SF:
24970 case V4SF_FTYPE_V4SF_V4SI:
24971 case V4SF_FTYPE_V4SF_V2SI:
24972 case V4SF_FTYPE_V4SF_V2DF:
24973 case V4SF_FTYPE_V4SF_DI:
24974 case V4SF_FTYPE_V4SF_SI:
24975 case V2DI_FTYPE_V2DI_V2DI:
24976 case V2DI_FTYPE_V16QI_V16QI:
24977 case V2DI_FTYPE_V4SI_V4SI:
24978 case V2DI_FTYPE_V2DI_V16QI:
24979 case V2DI_FTYPE_V2DF_V2DF:
24980 case V2SI_FTYPE_V2SI_V2SI:
24981 case V2SI_FTYPE_V4HI_V4HI:
24982 case V2SI_FTYPE_V2SF_V2SF:
24983 case V2DF_FTYPE_V2DF_V2DF:
24984 case V2DF_FTYPE_V2DF_V4SF:
24985 case V2DF_FTYPE_V2DF_V2DI:
24986 case V2DF_FTYPE_V2DF_DI:
24987 case V2DF_FTYPE_V2DF_SI:
24988 case V2SF_FTYPE_V2SF_V2SF:
24989 case V1DI_FTYPE_V1DI_V1DI:
24990 case V1DI_FTYPE_V8QI_V8QI:
24991 case V1DI_FTYPE_V2SI_V2SI:
24992 if (comparison == UNKNOWN)
24993 return ix86_expand_binop_builtin (icode, exp, target);
24996 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24997 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24998 gcc_assert (comparison != UNKNOWN);
25002 case V8HI_FTYPE_V8HI_V8HI_COUNT:
25003 case V8HI_FTYPE_V8HI_SI_COUNT:
25004 case V4SI_FTYPE_V4SI_V4SI_COUNT:
25005 case V4SI_FTYPE_V4SI_SI_COUNT:
25006 case V4HI_FTYPE_V4HI_V4HI_COUNT:
25007 case V4HI_FTYPE_V4HI_SI_COUNT:
25008 case V2DI_FTYPE_V2DI_V2DI_COUNT:
25009 case V2DI_FTYPE_V2DI_SI_COUNT:
25010 case V2SI_FTYPE_V2SI_V2SI_COUNT:
25011 case V2SI_FTYPE_V2SI_SI_COUNT:
25012 case V1DI_FTYPE_V1DI_V1DI_COUNT:
25013 case V1DI_FTYPE_V1DI_SI_COUNT:
25015 last_arg_count = true;
25017 case UINT64_FTYPE_UINT64_UINT64:
25018 case UINT_FTYPE_UINT_UINT:
25019 case UINT_FTYPE_UINT_USHORT:
25020 case UINT_FTYPE_UINT_UCHAR:
25021 case UINT16_FTYPE_UINT16_INT:
25022 case UINT8_FTYPE_UINT8_INT:
25025 case V2DI2TI_FTYPE_V2DI_INT:
25028 nargs_constant = 1;
25030 case V8HI_FTYPE_V8HI_INT:
25031 case V8SF_FTYPE_V8SF_INT:
25032 case V4SI_FTYPE_V4SI_INT:
25033 case V4SI_FTYPE_V8SI_INT:
25034 case V4HI_FTYPE_V4HI_INT:
25035 case V4DF_FTYPE_V4DF_INT:
25036 case V4SF_FTYPE_V4SF_INT:
25037 case V4SF_FTYPE_V8SF_INT:
25038 case V2DI_FTYPE_V2DI_INT:
25039 case V2DF_FTYPE_V2DF_INT:
25040 case V2DF_FTYPE_V4DF_INT:
25042 nargs_constant = 1;
25044 case V16QI_FTYPE_V16QI_V16QI_V16QI:
25045 case V8SF_FTYPE_V8SF_V8SF_V8SF:
25046 case V4DF_FTYPE_V4DF_V4DF_V4DF:
25047 case V4SF_FTYPE_V4SF_V4SF_V4SF:
25048 case V2DF_FTYPE_V2DF_V2DF_V2DF:
25051 case V16QI_FTYPE_V16QI_V16QI_INT:
25052 case V8HI_FTYPE_V8HI_V8HI_INT:
25053 case V8SI_FTYPE_V8SI_V8SI_INT:
25054 case V8SI_FTYPE_V8SI_V4SI_INT:
25055 case V8SF_FTYPE_V8SF_V8SF_INT:
25056 case V8SF_FTYPE_V8SF_V4SF_INT:
25057 case V4SI_FTYPE_V4SI_V4SI_INT:
25058 case V4DF_FTYPE_V4DF_V4DF_INT:
25059 case V4DF_FTYPE_V4DF_V2DF_INT:
25060 case V4SF_FTYPE_V4SF_V4SF_INT:
25061 case V2DI_FTYPE_V2DI_V2DI_INT:
25062 case V2DF_FTYPE_V2DF_V2DF_INT:
25064 nargs_constant = 1;
25066 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
25069 nargs_constant = 1;
25071 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
25074 nargs_constant = 1;
25076 case V2DI_FTYPE_V2DI_UINT_UINT:
25078 nargs_constant = 2;
25080 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
25082 nargs_constant = 2;
25085 gcc_unreachable ();
25088 gcc_assert (nargs <= ARRAY_SIZE (args));
25090 if (comparison != UNKNOWN)
25092 gcc_assert (nargs == 2);
25093 return ix86_expand_sse_compare (d, exp, target, swap);
25096 if (rmode == VOIDmode || rmode == tmode)
25100 || GET_MODE (target) != tmode
25101 || ! (*insn_p->operand[0].predicate) (target, tmode))
25102 target = gen_reg_rtx (tmode);
25103 real_target = target;
25107 target = gen_reg_rtx (rmode);
25108 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
25111 for (i = 0; i < nargs; i++)
25113 tree arg = CALL_EXPR_ARG (exp, i);
25114 rtx op = expand_normal (arg);
25115 enum machine_mode mode = insn_p->operand[i + 1].mode;
25116 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
25118 if (last_arg_count && (i + 1) == nargs)
25120 /* SIMD shift insns take either an 8-bit immediate or
25121 register as count. But builtin functions take int as
25122 count. If count doesn't match, we put it in register. */
25125 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
25126 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
25127 op = copy_to_reg (op);
25130 else if ((nargs - i) <= nargs_constant)
25135 case CODE_FOR_sse4_1_roundpd:
25136 case CODE_FOR_sse4_1_roundps:
25137 case CODE_FOR_sse4_1_roundsd:
25138 case CODE_FOR_sse4_1_roundss:
25139 case CODE_FOR_sse4_1_blendps:
25140 case CODE_FOR_avx_blendpd256:
25141 case CODE_FOR_avx_vpermilv4df:
25142 case CODE_FOR_avx_roundpd256:
25143 case CODE_FOR_avx_roundps256:
25144 error ("the last argument must be a 4-bit immediate");
25147 case CODE_FOR_sse4_1_blendpd:
25148 case CODE_FOR_avx_vpermilv2df:
25149 error ("the last argument must be a 2-bit immediate");
25152 case CODE_FOR_avx_vextractf128v4df:
25153 case CODE_FOR_avx_vextractf128v8sf:
25154 case CODE_FOR_avx_vextractf128v8si:
25155 case CODE_FOR_avx_vinsertf128v4df:
25156 case CODE_FOR_avx_vinsertf128v8sf:
25157 case CODE_FOR_avx_vinsertf128v8si:
25158 error ("the last argument must be a 1-bit immediate");
25161 case CODE_FOR_avx_cmpsdv2df3:
25162 case CODE_FOR_avx_cmpssv4sf3:
25163 case CODE_FOR_avx_cmppdv2df3:
25164 case CODE_FOR_avx_cmppsv4sf3:
25165 case CODE_FOR_avx_cmppdv4df3:
25166 case CODE_FOR_avx_cmppsv8sf3:
25167 error ("the last argument must be a 5-bit immediate");
25171 switch (nargs_constant)
25174 if ((nargs - i) == nargs_constant)
25176 error ("the next to last argument must be an 8-bit immediate");
25180 error ("the last argument must be an 8-bit immediate");
25183 gcc_unreachable ();
25190 if (VECTOR_MODE_P (mode))
25191 op = safe_vector_operand (op, mode);
25193 /* If we aren't optimizing, only allow one memory operand to
25195 if (memory_operand (op, mode))
25198 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
25200 if (optimize || !match || num_memory > 1)
25201 op = copy_to_mode_reg (mode, op);
25205 op = copy_to_reg (op);
25206 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
25211 args[i].mode = mode;
25217 pat = GEN_FCN (icode) (real_target, args[0].op);
25220 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
25223 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
25227 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
25228 args[2].op, args[3].op);
25231 gcc_unreachable ();
25241 /* Subroutine of ix86_expand_builtin to take care of special insns
25242 with variable number of operands. */
25245 ix86_expand_special_args_builtin (const struct builtin_description *d,
25246 tree exp, rtx target)
25250 unsigned int i, nargs, arg_adjust, memory;
25254 enum machine_mode mode;
25256 enum insn_code icode = d->icode;
25257 bool last_arg_constant = false;
25258 const struct insn_data *insn_p = &insn_data[icode];
25259 enum machine_mode tmode = insn_p->operand[0].mode;
25260 enum { load, store } klass;
25262 switch ((enum ix86_special_builtin_type) d->flag)
25264 case VOID_FTYPE_VOID:
25265 emit_insn (GEN_FCN (icode) (target));
25267 case UINT64_FTYPE_VOID:
25272 case UINT64_FTYPE_PUNSIGNED:
25273 case V2DI_FTYPE_PV2DI:
25274 case V32QI_FTYPE_PCCHAR:
25275 case V16QI_FTYPE_PCCHAR:
25276 case V8SF_FTYPE_PCV4SF:
25277 case V8SF_FTYPE_PCFLOAT:
25278 case V4SF_FTYPE_PCFLOAT:
25279 case V4DF_FTYPE_PCV2DF:
25280 case V4DF_FTYPE_PCDOUBLE:
25281 case V2DF_FTYPE_PCDOUBLE:
25286 case VOID_FTYPE_PV2SF_V4SF:
25287 case VOID_FTYPE_PV4DI_V4DI:
25288 case VOID_FTYPE_PV2DI_V2DI:
25289 case VOID_FTYPE_PCHAR_V32QI:
25290 case VOID_FTYPE_PCHAR_V16QI:
25291 case VOID_FTYPE_PFLOAT_V8SF:
25292 case VOID_FTYPE_PFLOAT_V4SF:
25293 case VOID_FTYPE_PDOUBLE_V4DF:
25294 case VOID_FTYPE_PDOUBLE_V2DF:
25295 case VOID_FTYPE_PDI_DI:
25296 case VOID_FTYPE_PINT_INT:
25299 /* Reserve memory operand for target. */
25300 memory = ARRAY_SIZE (args);
25302 case V4SF_FTYPE_V4SF_PCV2SF:
25303 case V2DF_FTYPE_V2DF_PCDOUBLE:
25308 case V8SF_FTYPE_PCV8SF_V8SF:
25309 case V4DF_FTYPE_PCV4DF_V4DF:
25310 case V4SF_FTYPE_PCV4SF_V4SF:
25311 case V2DF_FTYPE_PCV2DF_V2DF:
25316 case VOID_FTYPE_PV8SF_V8SF_V8SF:
25317 case VOID_FTYPE_PV4DF_V4DF_V4DF:
25318 case VOID_FTYPE_PV4SF_V4SF_V4SF:
25319 case VOID_FTYPE_PV2DF_V2DF_V2DF:
25322 /* Reserve memory operand for target. */
25323 memory = ARRAY_SIZE (args);
25325 case VOID_FTYPE_USHORT_UINT_USHORT:
25326 case VOID_FTYPE_UINT_UINT_UINT:
25327 case VOID_FTYPE_UINT64_UINT_UINT:
25328 case UCHAR_FTYPE_USHORT_UINT_USHORT:
25329 case UCHAR_FTYPE_UINT_UINT_UINT:
25330 case UCHAR_FTYPE_UINT64_UINT_UINT:
25336 gcc_unreachable ();
25339 gcc_assert (nargs <= ARRAY_SIZE (args));
25341 if (klass == store)
25343 arg = CALL_EXPR_ARG (exp, 0);
25344 op = expand_normal (arg);
25345 gcc_assert (target == 0);
25346 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
25354 || GET_MODE (target) != tmode
25355 || ! (*insn_p->operand[0].predicate) (target, tmode))
25356 target = gen_reg_rtx (tmode);
25359 for (i = 0; i < nargs; i++)
25361 enum machine_mode mode = insn_p->operand[i + 1].mode;
25364 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
25365 op = expand_normal (arg);
25366 match = (*insn_p->operand[i + 1].predicate) (op, mode);
25368 if (last_arg_constant && (i + 1) == nargs)
25374 error ("the last argument must be an 8-bit immediate");
25382 /* This must be the memory operand. */
25383 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
25384 gcc_assert (GET_MODE (op) == mode
25385 || GET_MODE (op) == VOIDmode);
25389 /* This must be register. */
25390 if (VECTOR_MODE_P (mode))
25391 op = safe_vector_operand (op, mode);
25393 gcc_assert (GET_MODE (op) == mode
25394 || GET_MODE (op) == VOIDmode);
25395 op = copy_to_mode_reg (mode, op);
25400 args[i].mode = mode;
25406 pat = GEN_FCN (icode) (target);
25409 pat = GEN_FCN (icode) (target, args[0].op);
25412 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
25415 gcc_unreachable ();
25421 return klass == store ? 0 : target;
25424 /* Return the integer constant in ARG. Constrain it to be in the range
25425 of the subparts of VEC_TYPE; issue an error if not. */
25428 get_element_number (tree vec_type, tree arg)
25430 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
25432 if (!host_integerp (arg, 1)
25433 || (elt = tree_low_cst (arg, 1), elt > max))
25435 error ("selector must be an integer constant in the range 0..%wi", max);
25442 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25443 ix86_expand_vector_init. We DO have language-level syntax for this, in
25444 the form of (type){ init-list }. Except that since we can't place emms
25445 instructions from inside the compiler, we can't allow the use of MMX
25446 registers unless the user explicitly asks for it. So we do *not* define
25447 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
25448 we have builtins invoked by mmintrin.h that gives us license to emit
25449 these sorts of instructions. */
25452 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
25454 enum machine_mode tmode = TYPE_MODE (type);
25455 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
25456 int i, n_elt = GET_MODE_NUNITS (tmode);
25457 rtvec v = rtvec_alloc (n_elt);
25459 gcc_assert (VECTOR_MODE_P (tmode));
25460 gcc_assert (call_expr_nargs (exp) == n_elt);
25462 for (i = 0; i < n_elt; ++i)
25464 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
25465 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
25468 if (!target || !register_operand (target, tmode))
25469 target = gen_reg_rtx (tmode);
25471 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
25475 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25476 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
25477 had a language-level syntax for referencing vector elements. */
25480 ix86_expand_vec_ext_builtin (tree exp, rtx target)
25482 enum machine_mode tmode, mode0;
25487 arg0 = CALL_EXPR_ARG (exp, 0);
25488 arg1 = CALL_EXPR_ARG (exp, 1);
25490 op0 = expand_normal (arg0);
25491 elt = get_element_number (TREE_TYPE (arg0), arg1);
25493 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25494 mode0 = TYPE_MODE (TREE_TYPE (arg0));
25495 gcc_assert (VECTOR_MODE_P (mode0));
25497 op0 = force_reg (mode0, op0);
25499 if (optimize || !target || !register_operand (target, tmode))
25500 target = gen_reg_rtx (tmode);
25502 ix86_expand_vector_extract (true, target, op0, elt);
25507 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
25508 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
25509 a language-level syntax for referencing vector elements. */
25512 ix86_expand_vec_set_builtin (tree exp)
25514 enum machine_mode tmode, mode1;
25515 tree arg0, arg1, arg2;
25517 rtx op0, op1, target;
25519 arg0 = CALL_EXPR_ARG (exp, 0);
25520 arg1 = CALL_EXPR_ARG (exp, 1);
25521 arg2 = CALL_EXPR_ARG (exp, 2);
25523 tmode = TYPE_MODE (TREE_TYPE (arg0));
25524 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
25525 gcc_assert (VECTOR_MODE_P (tmode));
25527 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
25528 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
25529 elt = get_element_number (TREE_TYPE (arg0), arg2);
25531 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
25532 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
25534 op0 = force_reg (tmode, op0);
25535 op1 = force_reg (mode1, op1);
25537 /* OP0 is the source of these builtin functions and shouldn't be
25538 modified. Create a copy, use it and return it as target. */
25539 target = gen_reg_rtx (tmode);
25540 emit_move_insn (target, op0);
25541 ix86_expand_vector_set (true, target, op1, elt);
25546 /* Expand an expression EXP that calls a built-in function,
25547 with result going to TARGET if that's convenient
25548 (and in mode MODE if that's convenient).
25549 SUBTARGET may be used as the target for computing one of EXP's operands.
25550 IGNORE is nonzero if the value is to be ignored. */
25553 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
25554 enum machine_mode mode ATTRIBUTE_UNUSED,
25555 int ignore ATTRIBUTE_UNUSED)
25557 const struct builtin_description *d;
25559 enum insn_code icode;
25560 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
25561 tree arg0, arg1, arg2;
25562 rtx op0, op1, op2, pat;
25563 enum machine_mode mode0, mode1, mode2;
25564 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
25566 /* Determine whether the builtin function is available under the current ISA.
25567 Originally the builtin was not created if it wasn't applicable to the
25568 current ISA based on the command line switches. With function specific
25569 options, we need to check in the context of the function making the call
25570 whether it is supported. */
25571 if (ix86_builtins_isa[fcode].isa
25572 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
25574 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
25575 NULL, NULL, false);
25578 error ("%qE needs unknown isa option", fndecl);
25581 gcc_assert (opts != NULL);
25582 error ("%qE needs isa option %s", fndecl, opts);
25590 case IX86_BUILTIN_MASKMOVQ:
25591 case IX86_BUILTIN_MASKMOVDQU:
25592 icode = (fcode == IX86_BUILTIN_MASKMOVQ
25593 ? CODE_FOR_mmx_maskmovq
25594 : CODE_FOR_sse2_maskmovdqu);
25595 /* Note the arg order is different from the operand order. */
25596 arg1 = CALL_EXPR_ARG (exp, 0);
25597 arg2 = CALL_EXPR_ARG (exp, 1);
25598 arg0 = CALL_EXPR_ARG (exp, 2);
25599 op0 = expand_normal (arg0);
25600 op1 = expand_normal (arg1);
25601 op2 = expand_normal (arg2);
25602 mode0 = insn_data[icode].operand[0].mode;
25603 mode1 = insn_data[icode].operand[1].mode;
25604 mode2 = insn_data[icode].operand[2].mode;
25606 op0 = force_reg (Pmode, op0);
25607 op0 = gen_rtx_MEM (mode1, op0);
25609 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
25610 op0 = copy_to_mode_reg (mode0, op0);
25611 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
25612 op1 = copy_to_mode_reg (mode1, op1);
25613 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
25614 op2 = copy_to_mode_reg (mode2, op2);
25615 pat = GEN_FCN (icode) (op0, op1, op2);
25621 case IX86_BUILTIN_LDMXCSR:
25622 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
25623 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25624 emit_move_insn (target, op0);
25625 emit_insn (gen_sse_ldmxcsr (target));
25628 case IX86_BUILTIN_STMXCSR:
25629 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
25630 emit_insn (gen_sse_stmxcsr (target));
25631 return copy_to_mode_reg (SImode, target);
25633 case IX86_BUILTIN_CLFLUSH:
25634 arg0 = CALL_EXPR_ARG (exp, 0);
25635 op0 = expand_normal (arg0);
25636 icode = CODE_FOR_sse2_clflush;
25637 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
25638 op0 = copy_to_mode_reg (Pmode, op0);
25640 emit_insn (gen_sse2_clflush (op0));
25643 case IX86_BUILTIN_MONITOR:
25644 arg0 = CALL_EXPR_ARG (exp, 0);
25645 arg1 = CALL_EXPR_ARG (exp, 1);
25646 arg2 = CALL_EXPR_ARG (exp, 2);
25647 op0 = expand_normal (arg0);
25648 op1 = expand_normal (arg1);
25649 op2 = expand_normal (arg2);
25651 op0 = copy_to_mode_reg (Pmode, op0);
25653 op1 = copy_to_mode_reg (SImode, op1);
25655 op2 = copy_to_mode_reg (SImode, op2);
25656 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
25659 case IX86_BUILTIN_MWAIT:
25660 arg0 = CALL_EXPR_ARG (exp, 0);
25661 arg1 = CALL_EXPR_ARG (exp, 1);
25662 op0 = expand_normal (arg0);
25663 op1 = expand_normal (arg1);
25665 op0 = copy_to_mode_reg (SImode, op0);
25667 op1 = copy_to_mode_reg (SImode, op1);
25668 emit_insn (gen_sse3_mwait (op0, op1));
25671 case IX86_BUILTIN_VEC_INIT_V2SI:
25672 case IX86_BUILTIN_VEC_INIT_V4HI:
25673 case IX86_BUILTIN_VEC_INIT_V8QI:
25674 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
25676 case IX86_BUILTIN_VEC_EXT_V2DF:
25677 case IX86_BUILTIN_VEC_EXT_V2DI:
25678 case IX86_BUILTIN_VEC_EXT_V4SF:
25679 case IX86_BUILTIN_VEC_EXT_V4SI:
25680 case IX86_BUILTIN_VEC_EXT_V8HI:
25681 case IX86_BUILTIN_VEC_EXT_V2SI:
25682 case IX86_BUILTIN_VEC_EXT_V4HI:
25683 case IX86_BUILTIN_VEC_EXT_V16QI:
25684 return ix86_expand_vec_ext_builtin (exp, target);
25686 case IX86_BUILTIN_VEC_SET_V2DI:
25687 case IX86_BUILTIN_VEC_SET_V4SF:
25688 case IX86_BUILTIN_VEC_SET_V4SI:
25689 case IX86_BUILTIN_VEC_SET_V8HI:
25690 case IX86_BUILTIN_VEC_SET_V4HI:
25691 case IX86_BUILTIN_VEC_SET_V16QI:
25692 return ix86_expand_vec_set_builtin (exp);
25694 case IX86_BUILTIN_INFQ:
25695 case IX86_BUILTIN_HUGE_VALQ:
25697 REAL_VALUE_TYPE inf;
25701 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
25703 tmp = validize_mem (force_const_mem (mode, tmp));
25706 target = gen_reg_rtx (mode);
25708 emit_move_insn (target, tmp);
25716 for (i = 0, d = bdesc_special_args;
25717 i < ARRAY_SIZE (bdesc_special_args);
25719 if (d->code == fcode)
25720 return ix86_expand_special_args_builtin (d, exp, target);
25722 for (i = 0, d = bdesc_args;
25723 i < ARRAY_SIZE (bdesc_args);
25725 if (d->code == fcode)
25728 case IX86_BUILTIN_FABSQ:
25729 case IX86_BUILTIN_COPYSIGNQ:
25731 /* Emit a normal call if SSE2 isn't available. */
25732 return expand_call (exp, target, ignore);
25734 return ix86_expand_args_builtin (d, exp, target);
25737 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
25738 if (d->code == fcode)
25739 return ix86_expand_sse_comi (d, exp, target);
25741 for (i = 0, d = bdesc_pcmpestr;
25742 i < ARRAY_SIZE (bdesc_pcmpestr);
25744 if (d->code == fcode)
25745 return ix86_expand_sse_pcmpestr (d, exp, target);
25747 for (i = 0, d = bdesc_pcmpistr;
25748 i < ARRAY_SIZE (bdesc_pcmpistr);
25750 if (d->code == fcode)
25751 return ix86_expand_sse_pcmpistr (d, exp, target);
25753 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
25754 if (d->code == fcode)
25755 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
25756 (enum multi_arg_type)d->flag,
25759 gcc_unreachable ();
25762 /* Returns a function decl for a vectorized version of the builtin function
25763 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25764 if it is not available. */
25767 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
25770 enum machine_mode in_mode, out_mode;
25773 if (TREE_CODE (type_out) != VECTOR_TYPE
25774 || TREE_CODE (type_in) != VECTOR_TYPE)
25777 out_mode = TYPE_MODE (TREE_TYPE (type_out));
25778 out_n = TYPE_VECTOR_SUBPARTS (type_out);
25779 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25780 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25784 case BUILT_IN_SQRT:
25785 if (out_mode == DFmode && out_n == 2
25786 && in_mode == DFmode && in_n == 2)
25787 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25790 case BUILT_IN_SQRTF:
25791 if (out_mode == SFmode && out_n == 4
25792 && in_mode == SFmode && in_n == 4)
25793 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25796 case BUILT_IN_LRINT:
25797 if (out_mode == SImode && out_n == 4
25798 && in_mode == DFmode && in_n == 2)
25799 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25802 case BUILT_IN_LRINTF:
25803 if (out_mode == SImode && out_n == 4
25804 && in_mode == SFmode && in_n == 4)
25805 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25808 case BUILT_IN_COPYSIGN:
25809 if (out_mode == DFmode && out_n == 2
25810 && in_mode == DFmode && in_n == 2)
25811 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
25814 case BUILT_IN_COPYSIGNF:
25815 if (out_mode == SFmode && out_n == 4
25816 && in_mode == SFmode && in_n == 4)
25817 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
25824 /* Dispatch to a handler for a vectorization library. */
25825 if (ix86_veclib_handler)
25826 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
25832 /* Handler for an SVML-style interface to
25833 a library with vectorized intrinsics. */
25836 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25839 tree fntype, new_fndecl, args;
25842 enum machine_mode el_mode, in_mode;
25845 /* The SVML is suitable for unsafe math only. */
25846 if (!flag_unsafe_math_optimizations)
25849 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25850 n = TYPE_VECTOR_SUBPARTS (type_out);
25851 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25852 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25853 if (el_mode != in_mode
25861 case BUILT_IN_LOG10:
25863 case BUILT_IN_TANH:
25865 case BUILT_IN_ATAN:
25866 case BUILT_IN_ATAN2:
25867 case BUILT_IN_ATANH:
25868 case BUILT_IN_CBRT:
25869 case BUILT_IN_SINH:
25871 case BUILT_IN_ASINH:
25872 case BUILT_IN_ASIN:
25873 case BUILT_IN_COSH:
25875 case BUILT_IN_ACOSH:
25876 case BUILT_IN_ACOS:
25877 if (el_mode != DFmode || n != 2)
25881 case BUILT_IN_EXPF:
25882 case BUILT_IN_LOGF:
25883 case BUILT_IN_LOG10F:
25884 case BUILT_IN_POWF:
25885 case BUILT_IN_TANHF:
25886 case BUILT_IN_TANF:
25887 case BUILT_IN_ATANF:
25888 case BUILT_IN_ATAN2F:
25889 case BUILT_IN_ATANHF:
25890 case BUILT_IN_CBRTF:
25891 case BUILT_IN_SINHF:
25892 case BUILT_IN_SINF:
25893 case BUILT_IN_ASINHF:
25894 case BUILT_IN_ASINF:
25895 case BUILT_IN_COSHF:
25896 case BUILT_IN_COSF:
25897 case BUILT_IN_ACOSHF:
25898 case BUILT_IN_ACOSF:
25899 if (el_mode != SFmode || n != 4)
25907 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25909 if (fn == BUILT_IN_LOGF)
25910 strcpy (name, "vmlsLn4");
25911 else if (fn == BUILT_IN_LOG)
25912 strcpy (name, "vmldLn2");
25915 sprintf (name, "vmls%s", bname+10);
25916 name[strlen (name)-1] = '4';
25919 sprintf (name, "vmld%s2", bname+10);
25921 /* Convert to uppercase. */
25925 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25926 args = TREE_CHAIN (args))
25930 fntype = build_function_type_list (type_out, type_in, NULL);
25932 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25934 /* Build a function declaration for the vectorized function. */
25935 new_fndecl = build_decl (BUILTINS_LOCATION,
25936 FUNCTION_DECL, get_identifier (name), fntype);
25937 TREE_PUBLIC (new_fndecl) = 1;
25938 DECL_EXTERNAL (new_fndecl) = 1;
25939 DECL_IS_NOVOPS (new_fndecl) = 1;
25940 TREE_READONLY (new_fndecl) = 1;
25945 /* Handler for an ACML-style interface to
25946 a library with vectorized intrinsics. */
25949 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25951 char name[20] = "__vr.._";
25952 tree fntype, new_fndecl, args;
25955 enum machine_mode el_mode, in_mode;
25958 /* The ACML is 64bits only and suitable for unsafe math only as
25959 it does not correctly support parts of IEEE with the required
25960 precision such as denormals. */
25962 || !flag_unsafe_math_optimizations)
25965 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25966 n = TYPE_VECTOR_SUBPARTS (type_out);
25967 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25968 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25969 if (el_mode != in_mode
25979 case BUILT_IN_LOG2:
25980 case BUILT_IN_LOG10:
25983 if (el_mode != DFmode
25988 case BUILT_IN_SINF:
25989 case BUILT_IN_COSF:
25990 case BUILT_IN_EXPF:
25991 case BUILT_IN_POWF:
25992 case BUILT_IN_LOGF:
25993 case BUILT_IN_LOG2F:
25994 case BUILT_IN_LOG10F:
25997 if (el_mode != SFmode
26006 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
26007 sprintf (name + 7, "%s", bname+10);
26010 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
26011 args = TREE_CHAIN (args))
26015 fntype = build_function_type_list (type_out, type_in, NULL);
26017 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
26019 /* Build a function declaration for the vectorized function. */
26020 new_fndecl = build_decl (BUILTINS_LOCATION,
26021 FUNCTION_DECL, get_identifier (name), fntype);
26022 TREE_PUBLIC (new_fndecl) = 1;
26023 DECL_EXTERNAL (new_fndecl) = 1;
26024 DECL_IS_NOVOPS (new_fndecl) = 1;
26025 TREE_READONLY (new_fndecl) = 1;
26031 /* Returns a decl of a function that implements conversion of an integer vector
26032 into a floating-point vector, or vice-versa. TYPE is the type of the integer
26033 side of the conversion.
26034 Return NULL_TREE if it is not available. */
26037 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
26039 if (! (TARGET_SSE2 && TREE_CODE (type) == VECTOR_TYPE))
26045 switch (TYPE_MODE (type))
26048 return TYPE_UNSIGNED (type)
26049 ? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
26050 : ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
26055 case FIX_TRUNC_EXPR:
26056 switch (TYPE_MODE (type))
26059 return TYPE_UNSIGNED (type)
26061 : ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
26071 /* Returns a code for a target-specific builtin that implements
26072 reciprocal of the function, or NULL_TREE if not available. */
26075 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
26076 bool sqrt ATTRIBUTE_UNUSED)
26078 if (! (TARGET_SSE_MATH && !optimize_insn_for_size_p ()
26079 && flag_finite_math_only && !flag_trapping_math
26080 && flag_unsafe_math_optimizations))
26084 /* Machine dependent builtins. */
26087 /* Vectorized version of sqrt to rsqrt conversion. */
26088 case IX86_BUILTIN_SQRTPS_NR:
26089 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
26095 /* Normal builtins. */
26098 /* Sqrt to rsqrt conversion. */
26099 case BUILT_IN_SQRTF:
26100 return ix86_builtins[IX86_BUILTIN_RSQRTF];
26107 /* Store OPERAND to the memory after reload is completed. This means
26108 that we can't easily use assign_stack_local. */
26110 ix86_force_to_memory (enum machine_mode mode, rtx operand)
26114 gcc_assert (reload_completed);
26115 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
26117 result = gen_rtx_MEM (mode,
26118 gen_rtx_PLUS (Pmode,
26120 GEN_INT (-RED_ZONE_SIZE)));
26121 emit_move_insn (result, operand);
26123 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
26129 operand = gen_lowpart (DImode, operand);
26133 gen_rtx_SET (VOIDmode,
26134 gen_rtx_MEM (DImode,
26135 gen_rtx_PRE_DEC (DImode,
26136 stack_pointer_rtx)),
26140 gcc_unreachable ();
26142 result = gen_rtx_MEM (mode, stack_pointer_rtx);
26151 split_di (&operand, 1, operands, operands + 1);
26153 gen_rtx_SET (VOIDmode,
26154 gen_rtx_MEM (SImode,
26155 gen_rtx_PRE_DEC (Pmode,
26156 stack_pointer_rtx)),
26159 gen_rtx_SET (VOIDmode,
26160 gen_rtx_MEM (SImode,
26161 gen_rtx_PRE_DEC (Pmode,
26162 stack_pointer_rtx)),
26167 /* Store HImodes as SImodes. */
26168 operand = gen_lowpart (SImode, operand);
26172 gen_rtx_SET (VOIDmode,
26173 gen_rtx_MEM (GET_MODE (operand),
26174 gen_rtx_PRE_DEC (SImode,
26175 stack_pointer_rtx)),
26179 gcc_unreachable ();
26181 result = gen_rtx_MEM (mode, stack_pointer_rtx);
26186 /* Free operand from the memory. */
26188 ix86_free_from_memory (enum machine_mode mode)
26190 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
26194 if (mode == DImode || TARGET_64BIT)
26198 /* Use LEA to deallocate stack space. In peephole2 it will be converted
26199 to pop or add instruction if registers are available. */
26200 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
26201 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
26206 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
26207 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
26209 static const enum reg_class *
26210 i386_ira_cover_classes (void)
26212 static const enum reg_class sse_fpmath_classes[] = {
26213 GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
26215 static const enum reg_class no_sse_fpmath_classes[] = {
26216 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
26219 return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes;
26222 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
26223 QImode must go into class Q_REGS.
26224 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
26225 movdf to do mem-to-mem moves through integer regs. */
26227 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
26229 enum machine_mode mode = GET_MODE (x);
26231 /* We're only allowed to return a subclass of CLASS. Many of the
26232 following checks fail for NO_REGS, so eliminate that early. */
26233 if (regclass == NO_REGS)
26236 /* All classes can load zeros. */
26237 if (x == CONST0_RTX (mode))
26240 /* Force constants into memory if we are loading a (nonzero) constant into
26241 an MMX or SSE register. This is because there are no MMX/SSE instructions
26242 to load from a constant. */
26244 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
26247 /* Prefer SSE regs only, if we can use them for math. */
26248 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
26249 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
26251 /* Floating-point constants need more complex checks. */
26252 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
26254 /* General regs can load everything. */
26255 if (reg_class_subset_p (regclass, GENERAL_REGS))
26258 /* Floats can load 0 and 1 plus some others. Note that we eliminated
26259 zero above. We only want to wind up preferring 80387 registers if
26260 we plan on doing computation with them. */
26262 && standard_80387_constant_p (x))
26264 /* Limit class to non-sse. */
26265 if (regclass == FLOAT_SSE_REGS)
26267 if (regclass == FP_TOP_SSE_REGS)
26269 if (regclass == FP_SECOND_SSE_REGS)
26270 return FP_SECOND_REG;
26271 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
26278 /* Generally when we see PLUS here, it's the function invariant
26279 (plus soft-fp const_int). Which can only be computed into general
26281 if (GET_CODE (x) == PLUS)
26282 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
26284 /* QImode constants are easy to load, but non-constant QImode data
26285 must go into Q_REGS. */
26286 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
26288 if (reg_class_subset_p (regclass, Q_REGS))
26290 if (reg_class_subset_p (Q_REGS, regclass))
26298 /* Discourage putting floating-point values in SSE registers unless
26299 SSE math is being used, and likewise for the 387 registers. */
26301 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
26303 enum machine_mode mode = GET_MODE (x);
26305 /* Restrict the output reload class to the register bank that we are doing
26306 math on. If we would like not to return a subset of CLASS, reject this
26307 alternative: if reload cannot do this, it will still use its choice. */
26308 mode = GET_MODE (x);
26309 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
26310 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
26312 if (X87_FLOAT_MODE_P (mode))
26314 if (regclass == FP_TOP_SSE_REGS)
26316 else if (regclass == FP_SECOND_SSE_REGS)
26317 return FP_SECOND_REG;
26319 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
26325 static enum reg_class
26326 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
26327 enum machine_mode mode,
26328 secondary_reload_info *sri ATTRIBUTE_UNUSED)
26330 /* QImode spills from non-QI registers require
26331 intermediate register on 32bit targets. */
26332 if (!in_p && mode == QImode && !TARGET_64BIT
26333 && (rclass == GENERAL_REGS
26334 || rclass == LEGACY_REGS
26335 || rclass == INDEX_REGS))
26344 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
26345 regno = true_regnum (x);
26347 /* Return Q_REGS if the operand is in memory. */
26355 /* If we are copying between general and FP registers, we need a memory
26356 location. The same is true for SSE and MMX registers.
26358 To optimize register_move_cost performance, allow inline variant.
26360 The macro can't work reliably when one of the CLASSES is class containing
26361 registers from multiple units (SSE, MMX, integer). We avoid this by never
26362 combining those units in single alternative in the machine description.
26363 Ensure that this constraint holds to avoid unexpected surprises.
26365 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
26366 enforce these sanity checks. */
26369 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26370 enum machine_mode mode, int strict)
26372 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
26373 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
26374 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
26375 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
26376 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
26377 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
26379 gcc_assert (!strict);
26383 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
26386 /* ??? This is a lie. We do have moves between mmx/general, and for
26387 mmx/sse2. But by saying we need secondary memory we discourage the
26388 register allocator from using the mmx registers unless needed. */
26389 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
26392 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26394 /* SSE1 doesn't have any direct moves from other classes. */
26398 /* If the target says that inter-unit moves are more expensive
26399 than moving through memory, then don't generate them. */
26400 if (!TARGET_INTER_UNIT_MOVES)
26403 /* Between SSE and general, we have moves no larger than word size. */
26404 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
26412 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
26413 enum machine_mode mode, int strict)
26415 return inline_secondary_memory_needed (class1, class2, mode, strict);
26418 /* Return true if the registers in CLASS cannot represent the change from
26419 modes FROM to TO. */
26422 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
26423 enum reg_class regclass)
26428 /* x87 registers can't do subreg at all, as all values are reformatted
26429 to extended precision. */
26430 if (MAYBE_FLOAT_CLASS_P (regclass))
26433 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
26435 /* Vector registers do not support QI or HImode loads. If we don't
26436 disallow a change to these modes, reload will assume it's ok to
26437 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
26438 the vec_dupv4hi pattern. */
26439 if (GET_MODE_SIZE (from) < 4)
26442 /* Vector registers do not support subreg with nonzero offsets, which
26443 are otherwise valid for integer registers. Since we can't see
26444 whether we have a nonzero offset from here, prohibit all
26445 nonparadoxical subregs changing size. */
26446 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
26453 /* Return the cost of moving data of mode M between a
26454 register and memory. A value of 2 is the default; this cost is
26455 relative to those in `REGISTER_MOVE_COST'.
26457 This function is used extensively by register_move_cost that is used to
26458 build tables at startup. Make it inline in this case.
26459 When IN is 2, return maximum of in and out move cost.
26461 If moving between registers and memory is more expensive than
26462 between two registers, you should define this macro to express the
26465 Model also increased moving costs of QImode registers in non
26469 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
26473 if (FLOAT_CLASS_P (regclass))
26491 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
26492 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
26494 if (SSE_CLASS_P (regclass))
26497 switch (GET_MODE_SIZE (mode))
26512 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
26513 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
26515 if (MMX_CLASS_P (regclass))
26518 switch (GET_MODE_SIZE (mode))
26530 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
26531 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
26533 switch (GET_MODE_SIZE (mode))
26536 if (Q_CLASS_P (regclass) || TARGET_64BIT)
26539 return ix86_cost->int_store[0];
26540 if (TARGET_PARTIAL_REG_DEPENDENCY
26541 && optimize_function_for_speed_p (cfun))
26542 cost = ix86_cost->movzbl_load;
26544 cost = ix86_cost->int_load[0];
26546 return MAX (cost, ix86_cost->int_store[0]);
26552 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
26554 return ix86_cost->movzbl_load;
26556 return ix86_cost->int_store[0] + 4;
26561 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
26562 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
26564 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
26565 if (mode == TFmode)
26568 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
26570 cost = ix86_cost->int_load[2];
26572 cost = ix86_cost->int_store[2];
26573 return (cost * (((int) GET_MODE_SIZE (mode)
26574 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
26579 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
26581 return inline_memory_move_cost (mode, regclass, in);
26585 /* Return the cost of moving data from a register in class CLASS1 to
26586 one in class CLASS2.
26588 It is not required that the cost always equal 2 when FROM is the same as TO;
26589 on some machines it is expensive to move between registers if they are not
26590 general registers. */
26593 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
26594 enum reg_class class2)
26596 /* In case we require secondary memory, compute cost of the store followed
26597 by load. In order to avoid bad register allocation choices, we need
26598 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
26600 if (inline_secondary_memory_needed (class1, class2, mode, 0))
26604 cost += inline_memory_move_cost (mode, class1, 2);
26605 cost += inline_memory_move_cost (mode, class2, 2);
26607 /* In case of copying from general_purpose_register we may emit multiple
26608 stores followed by single load causing memory size mismatch stall.
26609 Count this as arbitrarily high cost of 20. */
26610 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
26613 /* In the case of FP/MMX moves, the registers actually overlap, and we
26614 have to switch modes in order to treat them differently. */
26615 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
26616 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
26622 /* Moves between SSE/MMX and integer unit are expensive. */
26623 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
26624 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
26626 /* ??? By keeping returned value relatively high, we limit the number
26627 of moves between integer and MMX/SSE registers for all targets.
26628 Additionally, high value prevents problem with x86_modes_tieable_p(),
26629 where integer modes in MMX/SSE registers are not tieable
26630 because of missing QImode and HImode moves to, from or between
26631 MMX/SSE registers. */
26632 return MAX (8, ix86_cost->mmxsse_to_integer);
26634 if (MAYBE_FLOAT_CLASS_P (class1))
26635 return ix86_cost->fp_move;
26636 if (MAYBE_SSE_CLASS_P (class1))
26637 return ix86_cost->sse_move;
26638 if (MAYBE_MMX_CLASS_P (class1))
26639 return ix86_cost->mmx_move;
26643 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
26646 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
26648 /* Flags and only flags can only hold CCmode values. */
26649 if (CC_REGNO_P (regno))
26650 return GET_MODE_CLASS (mode) == MODE_CC;
26651 if (GET_MODE_CLASS (mode) == MODE_CC
26652 || GET_MODE_CLASS (mode) == MODE_RANDOM
26653 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
26655 if (FP_REGNO_P (regno))
26656 return VALID_FP_MODE_P (mode);
26657 if (SSE_REGNO_P (regno))
26659 /* We implement the move patterns for all vector modes into and
26660 out of SSE registers, even when no operation instructions
26661 are available. OImode move is available only when AVX is
26663 return ((TARGET_AVX && mode == OImode)
26664 || VALID_AVX256_REG_MODE (mode)
26665 || VALID_SSE_REG_MODE (mode)
26666 || VALID_SSE2_REG_MODE (mode)
26667 || VALID_MMX_REG_MODE (mode)
26668 || VALID_MMX_REG_MODE_3DNOW (mode));
26670 if (MMX_REGNO_P (regno))
26672 /* We implement the move patterns for 3DNOW modes even in MMX mode,
26673 so if the register is available at all, then we can move data of
26674 the given mode into or out of it. */
26675 return (VALID_MMX_REG_MODE (mode)
26676 || VALID_MMX_REG_MODE_3DNOW (mode));
26679 if (mode == QImode)
26681 /* Take care for QImode values - they can be in non-QI regs,
26682 but then they do cause partial register stalls. */
26683 if (regno <= BX_REG || TARGET_64BIT)
26685 if (!TARGET_PARTIAL_REG_STALL)
26687 return reload_in_progress || reload_completed;
26689 /* We handle both integer and floats in the general purpose registers. */
26690 else if (VALID_INT_MODE_P (mode))
26692 else if (VALID_FP_MODE_P (mode))
26694 else if (VALID_DFP_MODE_P (mode))
26696 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
26697 on to use that value in smaller contexts, this can easily force a
26698 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
26699 supporting DImode, allow it. */
26700 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
26706 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
26707 tieable integer mode. */
26710 ix86_tieable_integer_mode_p (enum machine_mode mode)
26719 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
26722 return TARGET_64BIT;
26729 /* Return true if MODE1 is accessible in a register that can hold MODE2
26730 without copying. That is, all register classes that can hold MODE2
26731 can also hold MODE1. */
26734 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
26736 if (mode1 == mode2)
26739 if (ix86_tieable_integer_mode_p (mode1)
26740 && ix86_tieable_integer_mode_p (mode2))
26743 /* MODE2 being XFmode implies fp stack or general regs, which means we
26744 can tie any smaller floating point modes to it. Note that we do not
26745 tie this with TFmode. */
26746 if (mode2 == XFmode)
26747 return mode1 == SFmode || mode1 == DFmode;
26749 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
26750 that we can tie it with SFmode. */
26751 if (mode2 == DFmode)
26752 return mode1 == SFmode;
26754 /* If MODE2 is only appropriate for an SSE register, then tie with
26755 any other mode acceptable to SSE registers. */
26756 if (GET_MODE_SIZE (mode2) == 16
26757 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
26758 return (GET_MODE_SIZE (mode1) == 16
26759 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
26761 /* If MODE2 is appropriate for an MMX register, then tie
26762 with any other mode acceptable to MMX registers. */
26763 if (GET_MODE_SIZE (mode2) == 8
26764 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
26765 return (GET_MODE_SIZE (mode1) == 8
26766 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
26771 /* Compute a (partial) cost for rtx X. Return true if the complete
26772 cost has been computed, and false if subexpressions should be
26773 scanned. In either case, *TOTAL contains the cost result. */
26776 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
26778 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
26779 enum machine_mode mode = GET_MODE (x);
26780 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
26788 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26790 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26792 else if (flag_pic && SYMBOLIC_CONST (x)
26794 || (!GET_CODE (x) != LABEL_REF
26795 && (GET_CODE (x) != SYMBOL_REF
26796 || !SYMBOL_REF_LOCAL_P (x)))))
26803 if (mode == VOIDmode)
26806 switch (standard_80387_constant_p (x))
26811 default: /* Other constants */
26816 /* Start with (MEM (SYMBOL_REF)), since that's where
26817 it'll probably end up. Add a penalty for size. */
26818 *total = (COSTS_N_INSNS (1)
26819 + (flag_pic != 0 && !TARGET_64BIT)
26820 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26826 /* The zero extensions is often completely free on x86_64, so make
26827 it as cheap as possible. */
26828 if (TARGET_64BIT && mode == DImode
26829 && GET_MODE (XEXP (x, 0)) == SImode)
26831 else if (TARGET_ZERO_EXTEND_WITH_AND)
26832 *total = cost->add;
26834 *total = cost->movzx;
26838 *total = cost->movsx;
26842 if (CONST_INT_P (XEXP (x, 1))
26843 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26845 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26848 *total = cost->add;
26851 if ((value == 2 || value == 3)
26852 && cost->lea <= cost->shift_const)
26854 *total = cost->lea;
26864 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26866 if (CONST_INT_P (XEXP (x, 1)))
26868 if (INTVAL (XEXP (x, 1)) > 32)
26869 *total = cost->shift_const + COSTS_N_INSNS (2);
26871 *total = cost->shift_const * 2;
26875 if (GET_CODE (XEXP (x, 1)) == AND)
26876 *total = cost->shift_var * 2;
26878 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26883 if (CONST_INT_P (XEXP (x, 1)))
26884 *total = cost->shift_const;
26886 *total = cost->shift_var;
26891 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26893 /* ??? SSE scalar cost should be used here. */
26894 *total = cost->fmul;
26897 else if (X87_FLOAT_MODE_P (mode))
26899 *total = cost->fmul;
26902 else if (FLOAT_MODE_P (mode))
26904 /* ??? SSE vector cost should be used here. */
26905 *total = cost->fmul;
26910 rtx op0 = XEXP (x, 0);
26911 rtx op1 = XEXP (x, 1);
26913 if (CONST_INT_P (XEXP (x, 1)))
26915 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26916 for (nbits = 0; value != 0; value &= value - 1)
26920 /* This is arbitrary. */
26923 /* Compute costs correctly for widening multiplication. */
26924 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26925 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26926 == GET_MODE_SIZE (mode))
26928 int is_mulwiden = 0;
26929 enum machine_mode inner_mode = GET_MODE (op0);
26931 if (GET_CODE (op0) == GET_CODE (op1))
26932 is_mulwiden = 1, op1 = XEXP (op1, 0);
26933 else if (CONST_INT_P (op1))
26935 if (GET_CODE (op0) == SIGN_EXTEND)
26936 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26939 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26943 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26946 *total = (cost->mult_init[MODE_INDEX (mode)]
26947 + nbits * cost->mult_bit
26948 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26957 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26958 /* ??? SSE cost should be used here. */
26959 *total = cost->fdiv;
26960 else if (X87_FLOAT_MODE_P (mode))
26961 *total = cost->fdiv;
26962 else if (FLOAT_MODE_P (mode))
26963 /* ??? SSE vector cost should be used here. */
26964 *total = cost->fdiv;
26966 *total = cost->divide[MODE_INDEX (mode)];
26970 if (GET_MODE_CLASS (mode) == MODE_INT
26971 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26973 if (GET_CODE (XEXP (x, 0)) == PLUS
26974 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26975 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26976 && CONSTANT_P (XEXP (x, 1)))
26978 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26979 if (val == 2 || val == 4 || val == 8)
26981 *total = cost->lea;
26982 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26983 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26984 outer_code, speed);
26985 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26989 else if (GET_CODE (XEXP (x, 0)) == MULT
26990 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26992 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26993 if (val == 2 || val == 4 || val == 8)
26995 *total = cost->lea;
26996 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26997 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27001 else if (GET_CODE (XEXP (x, 0)) == PLUS)
27003 *total = cost->lea;
27004 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
27005 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
27006 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
27013 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27015 /* ??? SSE cost should be used here. */
27016 *total = cost->fadd;
27019 else if (X87_FLOAT_MODE_P (mode))
27021 *total = cost->fadd;
27024 else if (FLOAT_MODE_P (mode))
27026 /* ??? SSE vector cost should be used here. */
27027 *total = cost->fadd;
27035 if (!TARGET_64BIT && mode == DImode)
27037 *total = (cost->add * 2
27038 + (rtx_cost (XEXP (x, 0), outer_code, speed)
27039 << (GET_MODE (XEXP (x, 0)) != DImode))
27040 + (rtx_cost (XEXP (x, 1), outer_code, speed)
27041 << (GET_MODE (XEXP (x, 1)) != DImode)));
27047 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27049 /* ??? SSE cost should be used here. */
27050 *total = cost->fchs;
27053 else if (X87_FLOAT_MODE_P (mode))
27055 *total = cost->fchs;
27058 else if (FLOAT_MODE_P (mode))
27060 /* ??? SSE vector cost should be used here. */
27061 *total = cost->fchs;
27067 if (!TARGET_64BIT && mode == DImode)
27068 *total = cost->add * 2;
27070 *total = cost->add;
27074 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
27075 && XEXP (XEXP (x, 0), 1) == const1_rtx
27076 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
27077 && XEXP (x, 1) == const0_rtx)
27079 /* This kind of construct is implemented using test[bwl].
27080 Treat it as if we had an AND. */
27081 *total = (cost->add
27082 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
27083 + rtx_cost (const1_rtx, outer_code, speed));
27089 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
27094 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27095 /* ??? SSE cost should be used here. */
27096 *total = cost->fabs;
27097 else if (X87_FLOAT_MODE_P (mode))
27098 *total = cost->fabs;
27099 else if (FLOAT_MODE_P (mode))
27100 /* ??? SSE vector cost should be used here. */
27101 *total = cost->fabs;
27105 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
27106 /* ??? SSE cost should be used here. */
27107 *total = cost->fsqrt;
27108 else if (X87_FLOAT_MODE_P (mode))
27109 *total = cost->fsqrt;
27110 else if (FLOAT_MODE_P (mode))
27111 /* ??? SSE vector cost should be used here. */
27112 *total = cost->fsqrt;
27116 if (XINT (x, 1) == UNSPEC_TP)
27127 static int current_machopic_label_num;
27129 /* Given a symbol name and its associated stub, write out the
27130 definition of the stub. */
27133 machopic_output_stub (FILE *file, const char *symb, const char *stub)
27135 unsigned int length;
27136 char *binder_name, *symbol_name, lazy_ptr_name[32];
27137 int label = ++current_machopic_label_num;
27139 /* For 64-bit we shouldn't get here. */
27140 gcc_assert (!TARGET_64BIT);
27142 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
27143 symb = (*targetm.strip_name_encoding) (symb);
27145 length = strlen (stub);
27146 binder_name = XALLOCAVEC (char, length + 32);
27147 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
27149 length = strlen (symb);
27150 symbol_name = XALLOCAVEC (char, length + 32);
27151 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
27153 sprintf (lazy_ptr_name, "L%d$lz", label);
27156 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
27158 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
27160 fprintf (file, "%s:\n", stub);
27161 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
27165 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
27166 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
27167 fprintf (file, "\tjmp\t*%%edx\n");
27170 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
27172 fprintf (file, "%s:\n", binder_name);
27176 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
27177 fputs ("\tpushl\t%eax\n", file);
27180 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
27182 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
27184 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
27185 fprintf (file, "%s:\n", lazy_ptr_name);
27186 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
27187 fprintf (file, ASM_LONG "%s\n", binder_name);
27191 darwin_x86_file_end (void)
27193 darwin_file_end ();
27196 #endif /* TARGET_MACHO */
27198 /* Order the registers for register allocator. */
27201 x86_order_regs_for_local_alloc (void)
27206 /* First allocate the local general purpose registers. */
27207 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
27208 if (GENERAL_REGNO_P (i) && call_used_regs[i])
27209 reg_alloc_order [pos++] = i;
27211 /* Global general purpose registers. */
27212 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
27213 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
27214 reg_alloc_order [pos++] = i;
27216 /* x87 registers come first in case we are doing FP math
27218 if (!TARGET_SSE_MATH)
27219 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
27220 reg_alloc_order [pos++] = i;
27222 /* SSE registers. */
27223 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
27224 reg_alloc_order [pos++] = i;
27225 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
27226 reg_alloc_order [pos++] = i;
27228 /* x87 registers. */
27229 if (TARGET_SSE_MATH)
27230 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
27231 reg_alloc_order [pos++] = i;
27233 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
27234 reg_alloc_order [pos++] = i;
27236 /* Initialize the rest of array as we do not allocate some registers
27238 while (pos < FIRST_PSEUDO_REGISTER)
27239 reg_alloc_order [pos++] = 0;
27242 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
27243 struct attribute_spec.handler. */
27245 ix86_handle_abi_attribute (tree *node, tree name,
27246 tree args ATTRIBUTE_UNUSED,
27247 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27249 if (TREE_CODE (*node) != FUNCTION_TYPE
27250 && TREE_CODE (*node) != METHOD_TYPE
27251 && TREE_CODE (*node) != FIELD_DECL
27252 && TREE_CODE (*node) != TYPE_DECL)
27254 warning (OPT_Wattributes, "%qE attribute only applies to functions",
27256 *no_add_attrs = true;
27261 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
27263 *no_add_attrs = true;
27267 /* Can combine regparm with all attributes but fastcall. */
27268 if (is_attribute_p ("ms_abi", name))
27270 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
27272 error ("ms_abi and sysv_abi attributes are not compatible");
27277 else if (is_attribute_p ("sysv_abi", name))
27279 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
27281 error ("ms_abi and sysv_abi attributes are not compatible");
27290 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
27291 struct attribute_spec.handler. */
27293 ix86_handle_struct_attribute (tree *node, tree name,
27294 tree args ATTRIBUTE_UNUSED,
27295 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27298 if (DECL_P (*node))
27300 if (TREE_CODE (*node) == TYPE_DECL)
27301 type = &TREE_TYPE (*node);
27306 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
27307 || TREE_CODE (*type) == UNION_TYPE)))
27309 warning (OPT_Wattributes, "%qE attribute ignored",
27311 *no_add_attrs = true;
27314 else if ((is_attribute_p ("ms_struct", name)
27315 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
27316 || ((is_attribute_p ("gcc_struct", name)
27317 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
27319 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
27321 *no_add_attrs = true;
27328 ix86_handle_fndecl_attribute (tree *node, tree name,
27329 tree args ATTRIBUTE_UNUSED,
27330 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
27332 if (TREE_CODE (*node) != FUNCTION_DECL)
27334 warning (OPT_Wattributes, "%qE attribute only applies to functions",
27336 *no_add_attrs = true;
27342 warning (OPT_Wattributes, "%qE attribute only available for 32-bit",
27347 #ifndef HAVE_AS_IX86_SWAP
27348 sorry ("ms_hook_prologue attribute needs assembler swap suffix support");
27355 ix86_ms_bitfield_layout_p (const_tree record_type)
27357 return (TARGET_MS_BITFIELD_LAYOUT &&
27358 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
27359 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
27362 /* Returns an expression indicating where the this parameter is
27363 located on entry to the FUNCTION. */
27366 x86_this_parameter (tree function)
27368 tree type = TREE_TYPE (function);
27369 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
27374 const int *parm_regs;
27376 if (ix86_function_type_abi (type) == MS_ABI)
27377 parm_regs = x86_64_ms_abi_int_parameter_registers;
27379 parm_regs = x86_64_int_parameter_registers;
27380 return gen_rtx_REG (DImode, parm_regs[aggr]);
27383 nregs = ix86_function_regparm (type, function);
27385 if (nregs > 0 && !stdarg_p (type))
27389 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
27390 regno = aggr ? DX_REG : CX_REG;
27398 return gen_rtx_MEM (SImode,
27399 plus_constant (stack_pointer_rtx, 4));
27402 return gen_rtx_REG (SImode, regno);
27405 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
27408 /* Determine whether x86_output_mi_thunk can succeed. */
27411 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
27412 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
27413 HOST_WIDE_INT vcall_offset, const_tree function)
27415 /* 64-bit can handle anything. */
27419 /* For 32-bit, everything's fine if we have one free register. */
27420 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
27423 /* Need a free register for vcall_offset. */
27427 /* Need a free register for GOT references. */
27428 if (flag_pic && !(*targetm.binds_local_p) (function))
27431 /* Otherwise ok. */
27435 /* Output the assembler code for a thunk function. THUNK_DECL is the
27436 declaration for the thunk function itself, FUNCTION is the decl for
27437 the target function. DELTA is an immediate constant offset to be
27438 added to THIS. If VCALL_OFFSET is nonzero, the word at
27439 *(*this + vcall_offset) should be added to THIS. */
27442 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
27443 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
27444 HOST_WIDE_INT vcall_offset, tree function)
27447 rtx this_param = x86_this_parameter (function);
27450 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
27451 pull it in now and let DELTA benefit. */
27452 if (REG_P (this_param))
27453 this_reg = this_param;
27454 else if (vcall_offset)
27456 /* Put the this parameter into %eax. */
27457 xops[0] = this_param;
27458 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
27459 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27462 this_reg = NULL_RTX;
27464 /* Adjust the this parameter by a fixed constant. */
27467 xops[0] = GEN_INT (delta);
27468 xops[1] = this_reg ? this_reg : this_param;
27471 if (!x86_64_general_operand (xops[0], DImode))
27473 tmp = gen_rtx_REG (DImode, R10_REG);
27475 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
27477 xops[1] = this_param;
27479 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
27482 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
27485 /* Adjust the this parameter by a value stored in the vtable. */
27489 tmp = gen_rtx_REG (DImode, R10_REG);
27492 int tmp_regno = CX_REG;
27493 if (lookup_attribute ("fastcall",
27494 TYPE_ATTRIBUTES (TREE_TYPE (function))))
27495 tmp_regno = AX_REG;
27496 tmp = gen_rtx_REG (SImode, tmp_regno);
27499 xops[0] = gen_rtx_MEM (Pmode, this_reg);
27501 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27503 /* Adjust the this parameter. */
27504 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
27505 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
27507 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
27508 xops[0] = GEN_INT (vcall_offset);
27510 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
27511 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
27513 xops[1] = this_reg;
27514 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
27517 /* If necessary, drop THIS back to its stack slot. */
27518 if (this_reg && this_reg != this_param)
27520 xops[0] = this_reg;
27521 xops[1] = this_param;
27522 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
27525 xops[0] = XEXP (DECL_RTL (function), 0);
27528 if (!flag_pic || (*targetm.binds_local_p) (function))
27529 output_asm_insn ("jmp\t%P0", xops);
27530 /* All thunks should be in the same object as their target,
27531 and thus binds_local_p should be true. */
27532 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
27533 gcc_unreachable ();
27536 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
27537 tmp = gen_rtx_CONST (Pmode, tmp);
27538 tmp = gen_rtx_MEM (QImode, tmp);
27540 output_asm_insn ("jmp\t%A0", xops);
27545 if (!flag_pic || (*targetm.binds_local_p) (function))
27546 output_asm_insn ("jmp\t%P0", xops);
27551 rtx sym_ref = XEXP (DECL_RTL (function), 0);
27552 tmp = (gen_rtx_SYMBOL_REF
27554 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
27555 tmp = gen_rtx_MEM (QImode, tmp);
27557 output_asm_insn ("jmp\t%0", xops);
27560 #endif /* TARGET_MACHO */
27562 tmp = gen_rtx_REG (SImode, CX_REG);
27563 output_set_got (tmp, NULL_RTX);
27566 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
27567 output_asm_insn ("jmp\t{*}%1", xops);
27573 x86_file_start (void)
27575 default_file_start ();
27577 darwin_file_start ();
27579 if (X86_FILE_START_VERSION_DIRECTIVE)
27580 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
27581 if (X86_FILE_START_FLTUSED)
27582 fputs ("\t.global\t__fltused\n", asm_out_file);
27583 if (ix86_asm_dialect == ASM_INTEL)
27584 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
27588 x86_field_alignment (tree field, int computed)
27590 enum machine_mode mode;
27591 tree type = TREE_TYPE (field);
27593 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
27595 mode = TYPE_MODE (strip_array_types (type));
27596 if (mode == DFmode || mode == DCmode
27597 || GET_MODE_CLASS (mode) == MODE_INT
27598 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
27599 return MIN (32, computed);
27603 /* Output assembler code to FILE to increment profiler label # LABELNO
27604 for profiling a function entry. */
27606 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
27610 #ifndef NO_PROFILE_COUNTERS
27611 fprintf (file, "\tleaq\t" LPREFIX "P%d@(%%rip),%%r11\n", labelno);
27614 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
27615 fputs ("\tcall\t*" MCOUNT_NAME "@GOTPCREL(%rip)\n", file);
27617 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
27621 #ifndef NO_PROFILE_COUNTERS
27622 fprintf (file, "\tleal\t" LPREFIX "P%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
27625 fputs ("\tcall\t*" MCOUNT_NAME "@GOT(%ebx)\n", file);
27629 #ifndef NO_PROFILE_COUNTERS
27630 fprintf (file, "\tmovl\t$" LPREFIX "P%d,%%" PROFILE_COUNT_REGISTER "\n",
27633 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
27637 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27638 /* We don't have exact information about the insn sizes, but we may assume
27639 quite safely that we are informed about all 1 byte insns and memory
27640 address sizes. This is enough to eliminate unnecessary padding in
27644 min_insn_size (rtx insn)
27648 if (!INSN_P (insn) || !active_insn_p (insn))
27651 /* Discard alignments we've emit and jump instructions. */
27652 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
27653 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
27655 if (JUMP_TABLE_DATA_P (insn))
27658 /* Important case - calls are always 5 bytes.
27659 It is common to have many calls in the row. */
27661 && symbolic_reference_mentioned_p (PATTERN (insn))
27662 && !SIBLING_CALL_P (insn))
27664 len = get_attr_length (insn);
27668 /* For normal instructions we rely on get_attr_length being exact,
27669 with a few exceptions. */
27670 if (!JUMP_P (insn))
27672 enum attr_type type = get_attr_type (insn);
27677 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
27678 || asm_noperands (PATTERN (insn)) >= 0)
27685 /* Otherwise trust get_attr_length. */
27689 l = get_attr_length_address (insn);
27690 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
27699 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
27703 ix86_avoid_jump_mispredicts (void)
27705 rtx insn, start = get_insns ();
27706 int nbytes = 0, njumps = 0;
27709 /* Look for all minimal intervals of instructions containing 4 jumps.
27710 The intervals are bounded by START and INSN. NBYTES is the total
27711 size of instructions in the interval including INSN and not including
27712 START. When the NBYTES is smaller than 16 bytes, it is possible
27713 that the end of START and INSN ends up in the same 16byte page.
27715 The smallest offset in the page INSN can start is the case where START
27716 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
27717 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
27719 for (insn = start; insn; insn = NEXT_INSN (insn))
27723 if (LABEL_P (insn))
27725 int align = label_to_alignment (insn);
27726 int max_skip = label_to_max_skip (insn);
27730 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
27731 already in the current 16 byte page, because otherwise
27732 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
27733 bytes to reach 16 byte boundary. */
27735 || (align <= 3 && max_skip != (1 << align) - 1))
27738 fprintf (dump_file, "Label %i with max_skip %i\n",
27739 INSN_UID (insn), max_skip);
27742 while (nbytes + max_skip >= 16)
27744 start = NEXT_INSN (start);
27745 if ((JUMP_P (start)
27746 && GET_CODE (PATTERN (start)) != ADDR_VEC
27747 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27749 njumps--, isjump = 1;
27752 nbytes -= min_insn_size (start);
27758 min_size = min_insn_size (insn);
27759 nbytes += min_size;
27761 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
27762 INSN_UID (insn), min_size);
27764 && GET_CODE (PATTERN (insn)) != ADDR_VEC
27765 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
27773 start = NEXT_INSN (start);
27774 if ((JUMP_P (start)
27775 && GET_CODE (PATTERN (start)) != ADDR_VEC
27776 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
27778 njumps--, isjump = 1;
27781 nbytes -= min_insn_size (start);
27783 gcc_assert (njumps >= 0);
27785 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
27786 INSN_UID (start), INSN_UID (insn), nbytes);
27788 if (njumps == 3 && isjump && nbytes < 16)
27790 int padsize = 15 - nbytes + min_insn_size (insn);
27793 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
27794 INSN_UID (insn), padsize);
27795 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
27801 /* AMD Athlon works faster
27802 when RET is not destination of conditional jump or directly preceded
27803 by other jump instruction. We avoid the penalty by inserting NOP just
27804 before the RET instructions in such cases. */
27806 ix86_pad_returns (void)
27811 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
27813 basic_block bb = e->src;
27814 rtx ret = BB_END (bb);
27816 bool replace = false;
27818 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
27819 || optimize_bb_for_size_p (bb))
27821 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27822 if (active_insn_p (prev) || LABEL_P (prev))
27824 if (prev && LABEL_P (prev))
27829 FOR_EACH_EDGE (e, ei, bb->preds)
27830 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27831 && !(e->flags & EDGE_FALLTHRU))
27836 prev = prev_active_insn (ret);
27838 && ((JUMP_P (prev) && any_condjump_p (prev))
27841 /* Empty functions get branch mispredict even when the jump destination
27842 is not visible to us. */
27843 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27848 emit_jump_insn_before (gen_return_internal_long (), ret);
27854 /* Implement machine specific optimizations. We implement padding of returns
27855 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27859 if (optimize && optimize_function_for_speed_p (cfun))
27861 if (TARGET_PAD_RETURNS)
27862 ix86_pad_returns ();
27863 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27864 if (TARGET_FOUR_JUMP_LIMIT)
27865 ix86_avoid_jump_mispredicts ();
27870 /* Return nonzero when QImode register that must be represented via REX prefix
27873 x86_extended_QIreg_mentioned_p (rtx insn)
27876 extract_insn_cached (insn);
27877 for (i = 0; i < recog_data.n_operands; i++)
27878 if (REG_P (recog_data.operand[i])
27879 && REGNO (recog_data.operand[i]) > BX_REG)
27884 /* Return nonzero when P points to register encoded via REX prefix.
27885 Called via for_each_rtx. */
27887 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27889 unsigned int regno;
27892 regno = REGNO (*p);
27893 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27896 /* Return true when INSN mentions register that must be encoded using REX
27899 x86_extended_reg_mentioned_p (rtx insn)
27901 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27902 extended_reg_mentioned_1, NULL);
27905 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27906 optabs would emit if we didn't have TFmode patterns. */
27909 x86_emit_floatuns (rtx operands[2])
27911 rtx neglab, donelab, i0, i1, f0, in, out;
27912 enum machine_mode mode, inmode;
27914 inmode = GET_MODE (operands[1]);
27915 gcc_assert (inmode == SImode || inmode == DImode);
27918 in = force_reg (inmode, operands[1]);
27919 mode = GET_MODE (out);
27920 neglab = gen_label_rtx ();
27921 donelab = gen_label_rtx ();
27922 f0 = gen_reg_rtx (mode);
27924 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27926 expand_float (out, in, 0);
27928 emit_jump_insn (gen_jump (donelab));
27931 emit_label (neglab);
27933 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27935 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27937 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27939 expand_float (f0, i0, 0);
27941 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27943 emit_label (donelab);
27946 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27947 with all elements equal to VAR. Return true if successful. */
27950 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27951 rtx target, rtx val)
27953 enum machine_mode hmode, smode, wsmode, wvmode;
27968 val = force_reg (GET_MODE_INNER (mode), val);
27969 x = gen_rtx_VEC_DUPLICATE (mode, val);
27970 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27976 if (TARGET_SSE || TARGET_3DNOW_A)
27978 val = gen_lowpart (SImode, val);
27979 x = gen_rtx_TRUNCATE (HImode, val);
27980 x = gen_rtx_VEC_DUPLICATE (mode, x);
27981 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28003 /* Extend HImode to SImode using a paradoxical SUBREG. */
28004 tmp1 = gen_reg_rtx (SImode);
28005 emit_move_insn (tmp1, gen_lowpart (SImode, val));
28006 /* Insert the SImode value as low element of V4SImode vector. */
28007 tmp2 = gen_reg_rtx (V4SImode);
28008 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
28009 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
28010 CONST0_RTX (V4SImode),
28012 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
28013 /* Cast the V4SImode vector back to a V8HImode vector. */
28014 tmp1 = gen_reg_rtx (V8HImode);
28015 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
28016 /* Duplicate the low short through the whole low SImode word. */
28017 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
28018 /* Cast the V8HImode vector back to a V4SImode vector. */
28019 tmp2 = gen_reg_rtx (V4SImode);
28020 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
28021 /* Replicate the low element of the V4SImode vector. */
28022 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
28023 /* Cast the V2SImode back to V8HImode, and store in target. */
28024 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
28035 /* Extend QImode to SImode using a paradoxical SUBREG. */
28036 tmp1 = gen_reg_rtx (SImode);
28037 emit_move_insn (tmp1, gen_lowpart (SImode, val));
28038 /* Insert the SImode value as low element of V4SImode vector. */
28039 tmp2 = gen_reg_rtx (V4SImode);
28040 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
28041 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
28042 CONST0_RTX (V4SImode),
28044 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
28045 /* Cast the V4SImode vector back to a V16QImode vector. */
28046 tmp1 = gen_reg_rtx (V16QImode);
28047 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
28048 /* Duplicate the low byte through the whole low SImode word. */
28049 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
28050 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
28051 /* Cast the V16QImode vector back to a V4SImode vector. */
28052 tmp2 = gen_reg_rtx (V4SImode);
28053 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
28054 /* Replicate the low element of the V4SImode vector. */
28055 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
28056 /* Cast the V2SImode back to V16QImode, and store in target. */
28057 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
28065 /* Replicate the value once into the next wider mode and recurse. */
28066 val = convert_modes (wsmode, smode, val, true);
28067 x = expand_simple_binop (wsmode, ASHIFT, val,
28068 GEN_INT (GET_MODE_BITSIZE (smode)),
28069 NULL_RTX, 1, OPTAB_LIB_WIDEN);
28070 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
28072 x = gen_reg_rtx (wvmode);
28073 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
28074 gcc_unreachable ();
28075 emit_move_insn (target, gen_lowpart (mode, x));
28098 rtx tmp = gen_reg_rtx (hmode);
28099 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
28100 emit_insn (gen_rtx_SET (VOIDmode, target,
28101 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
28110 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28111 whose ONE_VAR element is VAR, and other elements are zero. Return true
28115 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
28116 rtx target, rtx var, int one_var)
28118 enum machine_mode vsimode;
28121 bool use_vector_set = false;
28126 /* For SSE4.1, we normally use vector set. But if the second
28127 element is zero and inter-unit moves are OK, we use movq
28129 use_vector_set = (TARGET_64BIT
28131 && !(TARGET_INTER_UNIT_MOVES
28137 use_vector_set = TARGET_SSE4_1;
28140 use_vector_set = TARGET_SSE2;
28143 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
28150 use_vector_set = TARGET_AVX;
28153 /* Use ix86_expand_vector_set in 64bit mode only. */
28154 use_vector_set = TARGET_AVX && TARGET_64BIT;
28160 if (use_vector_set)
28162 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
28163 var = force_reg (GET_MODE_INNER (mode), var);
28164 ix86_expand_vector_set (mmx_ok, target, var, one_var);
28180 var = force_reg (GET_MODE_INNER (mode), var);
28181 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
28182 emit_insn (gen_rtx_SET (VOIDmode, target, x));
28187 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
28188 new_target = gen_reg_rtx (mode);
28190 new_target = target;
28191 var = force_reg (GET_MODE_INNER (mode), var);
28192 x = gen_rtx_VEC_DUPLICATE (mode, var);
28193 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
28194 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
28197 /* We need to shuffle the value to the correct position, so
28198 create a new pseudo to store the intermediate result. */
28200 /* With SSE2, we can use the integer shuffle insns. */
28201 if (mode != V4SFmode && TARGET_SSE2)
28203 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
28205 GEN_INT (one_var == 1 ? 0 : 1),
28206 GEN_INT (one_var == 2 ? 0 : 1),
28207 GEN_INT (one_var == 3 ? 0 : 1)));
28208 if (target != new_target)
28209 emit_move_insn (target, new_target);
28213 /* Otherwise convert the intermediate result to V4SFmode and
28214 use the SSE1 shuffle instructions. */
28215 if (mode != V4SFmode)
28217 tmp = gen_reg_rtx (V4SFmode);
28218 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
28223 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
28225 GEN_INT (one_var == 1 ? 0 : 1),
28226 GEN_INT (one_var == 2 ? 0+4 : 1+4),
28227 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
28229 if (mode != V4SFmode)
28230 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
28231 else if (tmp != target)
28232 emit_move_insn (target, tmp);
28234 else if (target != new_target)
28235 emit_move_insn (target, new_target);
28240 vsimode = V4SImode;
28246 vsimode = V2SImode;
28252 /* Zero extend the variable element to SImode and recurse. */
28253 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
28255 x = gen_reg_rtx (vsimode);
28256 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
28258 gcc_unreachable ();
28260 emit_move_insn (target, gen_lowpart (mode, x));
28268 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
28269 consisting of the values in VALS. It is known that all elements
28270 except ONE_VAR are constants. Return true if successful. */
28273 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
28274 rtx target, rtx vals, int one_var)
28276 rtx var = XVECEXP (vals, 0, one_var);
28277 enum machine_mode wmode;
28280 const_vec = copy_rtx (vals);
28281 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
28282 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
28290 /* For the two element vectors, it's just as easy to use
28291 the general case. */
28295 /* Use ix86_expand_vector_set in 64bit mode only. */
28318 /* There's no way to set one QImode entry easily. Combine
28319 the variable value with its adjacent constant value, and
28320 promote to an HImode set. */
28321 x = XVECEXP (vals, 0, one_var ^ 1);
28324 var = convert_modes (HImode, QImode, var, true);
28325 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
28326 NULL_RTX, 1, OPTAB_LIB_WIDEN);
28327 x = GEN_INT (INTVAL (x) & 0xff);
28331 var = convert_modes (HImode, QImode, var, true);
28332 x = gen_int_mode (INTVAL (x) << 8, HImode);
28334 if (x != const0_rtx)
28335 var = expand_simple_binop (HImode, IOR, var, x, var,
28336 1, OPTAB_LIB_WIDEN);
28338 x = gen_reg_rtx (wmode);
28339 emit_move_insn (x, gen_lowpart (wmode, const_vec));
28340 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
28342 emit_move_insn (target, gen_lowpart (mode, x));
28349 emit_move_insn (target, const_vec);
28350 ix86_expand_vector_set (mmx_ok, target, var, one_var);
28354 /* A subroutine of ix86_expand_vector_init_general. Use vector
28355 concatenate to handle the most general case: all values variable,
28356 and none identical. */
28359 ix86_expand_vector_init_concat (enum machine_mode mode,
28360 rtx target, rtx *ops, int n)
28362 enum machine_mode cmode, hmode = VOIDmode;
28363 rtx first[8], second[4];
28403 gcc_unreachable ();
28406 if (!register_operand (ops[1], cmode))
28407 ops[1] = force_reg (cmode, ops[1]);
28408 if (!register_operand (ops[0], cmode))
28409 ops[0] = force_reg (cmode, ops[0]);
28410 emit_insn (gen_rtx_SET (VOIDmode, target,
28411 gen_rtx_VEC_CONCAT (mode, ops[0],
28431 gcc_unreachable ();
28447 gcc_unreachable ();
28452 /* FIXME: We process inputs backward to help RA. PR 36222. */
28455 for (; i > 0; i -= 2, j--)
28457 first[j] = gen_reg_rtx (cmode);
28458 v = gen_rtvec (2, ops[i - 1], ops[i]);
28459 ix86_expand_vector_init (false, first[j],
28460 gen_rtx_PARALLEL (cmode, v));
28466 gcc_assert (hmode != VOIDmode);
28467 for (i = j = 0; i < n; i += 2, j++)
28469 second[j] = gen_reg_rtx (hmode);
28470 ix86_expand_vector_init_concat (hmode, second [j],
28474 ix86_expand_vector_init_concat (mode, target, second, n);
28477 ix86_expand_vector_init_concat (mode, target, first, n);
28481 gcc_unreachable ();
28485 /* A subroutine of ix86_expand_vector_init_general. Use vector
28486 interleave to handle the most general case: all values variable,
28487 and none identical. */
28490 ix86_expand_vector_init_interleave (enum machine_mode mode,
28491 rtx target, rtx *ops, int n)
28493 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
28496 rtx (*gen_load_even) (rtx, rtx, rtx);
28497 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
28498 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
28503 gen_load_even = gen_vec_setv8hi;
28504 gen_interleave_first_low = gen_vec_interleave_lowv4si;
28505 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28506 inner_mode = HImode;
28507 first_imode = V4SImode;
28508 second_imode = V2DImode;
28509 third_imode = VOIDmode;
28512 gen_load_even = gen_vec_setv16qi;
28513 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
28514 gen_interleave_second_low = gen_vec_interleave_lowv4si;
28515 inner_mode = QImode;
28516 first_imode = V8HImode;
28517 second_imode = V4SImode;
28518 third_imode = V2DImode;
28521 gcc_unreachable ();
28524 for (i = 0; i < n; i++)
28526 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
28527 op0 = gen_reg_rtx (SImode);
28528 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
28530 /* Insert the SImode value as low element of V4SImode vector. */
28531 op1 = gen_reg_rtx (V4SImode);
28532 op0 = gen_rtx_VEC_MERGE (V4SImode,
28533 gen_rtx_VEC_DUPLICATE (V4SImode,
28535 CONST0_RTX (V4SImode),
28537 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
28539 /* Cast the V4SImode vector back to a vector in orignal mode. */
28540 op0 = gen_reg_rtx (mode);
28541 emit_move_insn (op0, gen_lowpart (mode, op1));
28543 /* Load even elements into the second positon. */
28544 emit_insn ((*gen_load_even) (op0,
28545 force_reg (inner_mode,
28549 /* Cast vector to FIRST_IMODE vector. */
28550 ops[i] = gen_reg_rtx (first_imode);
28551 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
28554 /* Interleave low FIRST_IMODE vectors. */
28555 for (i = j = 0; i < n; i += 2, j++)
28557 op0 = gen_reg_rtx (first_imode);
28558 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
28560 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
28561 ops[j] = gen_reg_rtx (second_imode);
28562 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
28565 /* Interleave low SECOND_IMODE vectors. */
28566 switch (second_imode)
28569 for (i = j = 0; i < n / 2; i += 2, j++)
28571 op0 = gen_reg_rtx (second_imode);
28572 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
28575 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
28577 ops[j] = gen_reg_rtx (third_imode);
28578 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
28580 second_imode = V2DImode;
28581 gen_interleave_second_low = gen_vec_interleave_lowv2di;
28585 op0 = gen_reg_rtx (second_imode);
28586 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
28589 /* Cast the SECOND_IMODE vector back to a vector on original
28591 emit_insn (gen_rtx_SET (VOIDmode, target,
28592 gen_lowpart (mode, op0)));
28596 gcc_unreachable ();
28600 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
28601 all values variable, and none identical. */
28604 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
28605 rtx target, rtx vals)
28607 rtx ops[32], op0, op1;
28608 enum machine_mode half_mode = VOIDmode;
28615 if (!mmx_ok && !TARGET_SSE)
28627 n = GET_MODE_NUNITS (mode);
28628 for (i = 0; i < n; i++)
28629 ops[i] = XVECEXP (vals, 0, i);
28630 ix86_expand_vector_init_concat (mode, target, ops, n);
28634 half_mode = V16QImode;
28638 half_mode = V8HImode;
28642 n = GET_MODE_NUNITS (mode);
28643 for (i = 0; i < n; i++)
28644 ops[i] = XVECEXP (vals, 0, i);
28645 op0 = gen_reg_rtx (half_mode);
28646 op1 = gen_reg_rtx (half_mode);
28647 ix86_expand_vector_init_interleave (half_mode, op0, ops,
28649 ix86_expand_vector_init_interleave (half_mode, op1,
28650 &ops [n >> 1], n >> 2);
28651 emit_insn (gen_rtx_SET (VOIDmode, target,
28652 gen_rtx_VEC_CONCAT (mode, op0, op1)));
28656 if (!TARGET_SSE4_1)
28664 /* Don't use ix86_expand_vector_init_interleave if we can't
28665 move from GPR to SSE register directly. */
28666 if (!TARGET_INTER_UNIT_MOVES)
28669 n = GET_MODE_NUNITS (mode);
28670 for (i = 0; i < n; i++)
28671 ops[i] = XVECEXP (vals, 0, i);
28672 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
28680 gcc_unreachable ();
28684 int i, j, n_elts, n_words, n_elt_per_word;
28685 enum machine_mode inner_mode;
28686 rtx words[4], shift;
28688 inner_mode = GET_MODE_INNER (mode);
28689 n_elts = GET_MODE_NUNITS (mode);
28690 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
28691 n_elt_per_word = n_elts / n_words;
28692 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
28694 for (i = 0; i < n_words; ++i)
28696 rtx word = NULL_RTX;
28698 for (j = 0; j < n_elt_per_word; ++j)
28700 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
28701 elt = convert_modes (word_mode, inner_mode, elt, true);
28707 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
28708 word, 1, OPTAB_LIB_WIDEN);
28709 word = expand_simple_binop (word_mode, IOR, word, elt,
28710 word, 1, OPTAB_LIB_WIDEN);
28718 emit_move_insn (target, gen_lowpart (mode, words[0]));
28719 else if (n_words == 2)
28721 rtx tmp = gen_reg_rtx (mode);
28722 emit_clobber (tmp);
28723 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
28724 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
28725 emit_move_insn (target, tmp);
28727 else if (n_words == 4)
28729 rtx tmp = gen_reg_rtx (V4SImode);
28730 gcc_assert (word_mode == SImode);
28731 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
28732 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
28733 emit_move_insn (target, gen_lowpart (mode, tmp));
28736 gcc_unreachable ();
28740 /* Initialize vector TARGET via VALS. Suppress the use of MMX
28741 instructions unless MMX_OK is true. */
28744 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
28746 enum machine_mode mode = GET_MODE (target);
28747 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28748 int n_elts = GET_MODE_NUNITS (mode);
28749 int n_var = 0, one_var = -1;
28750 bool all_same = true, all_const_zero = true;
28754 for (i = 0; i < n_elts; ++i)
28756 x = XVECEXP (vals, 0, i);
28757 if (!(CONST_INT_P (x)
28758 || GET_CODE (x) == CONST_DOUBLE
28759 || GET_CODE (x) == CONST_FIXED))
28760 n_var++, one_var = i;
28761 else if (x != CONST0_RTX (inner_mode))
28762 all_const_zero = false;
28763 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
28767 /* Constants are best loaded from the constant pool. */
28770 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
28774 /* If all values are identical, broadcast the value. */
28776 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
28777 XVECEXP (vals, 0, 0)))
28780 /* Values where only one field is non-constant are best loaded from
28781 the pool and overwritten via move later. */
28785 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
28786 XVECEXP (vals, 0, one_var),
28790 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
28794 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
28798 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
28800 enum machine_mode mode = GET_MODE (target);
28801 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28802 enum machine_mode half_mode;
28803 bool use_vec_merge = false;
28805 static rtx (*gen_extract[6][2]) (rtx, rtx)
28807 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
28808 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
28809 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
28810 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
28811 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
28812 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
28814 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
28816 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
28817 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
28818 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
28819 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
28820 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
28821 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28831 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28832 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28834 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28836 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28837 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28843 use_vec_merge = TARGET_SSE4_1;
28851 /* For the two element vectors, we implement a VEC_CONCAT with
28852 the extraction of the other element. */
28854 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28855 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28858 op0 = val, op1 = tmp;
28860 op0 = tmp, op1 = val;
28862 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28863 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28868 use_vec_merge = TARGET_SSE4_1;
28875 use_vec_merge = true;
28879 /* tmp = target = A B C D */
28880 tmp = copy_to_reg (target);
28881 /* target = A A B B */
28882 emit_insn (gen_sse_unpcklps (target, target, target));
28883 /* target = X A B B */
28884 ix86_expand_vector_set (false, target, val, 0);
28885 /* target = A X C D */
28886 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28887 const1_rtx, const0_rtx,
28888 GEN_INT (2+4), GEN_INT (3+4)));
28892 /* tmp = target = A B C D */
28893 tmp = copy_to_reg (target);
28894 /* tmp = X B C D */
28895 ix86_expand_vector_set (false, tmp, val, 0);
28896 /* target = A B X D */
28897 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28898 const0_rtx, const1_rtx,
28899 GEN_INT (0+4), GEN_INT (3+4)));
28903 /* tmp = target = A B C D */
28904 tmp = copy_to_reg (target);
28905 /* tmp = X B C D */
28906 ix86_expand_vector_set (false, tmp, val, 0);
28907 /* target = A B X D */
28908 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28909 const0_rtx, const1_rtx,
28910 GEN_INT (2+4), GEN_INT (0+4)));
28914 gcc_unreachable ();
28919 use_vec_merge = TARGET_SSE4_1;
28923 /* Element 0 handled by vec_merge below. */
28926 use_vec_merge = true;
28932 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28933 store into element 0, then shuffle them back. */
28937 order[0] = GEN_INT (elt);
28938 order[1] = const1_rtx;
28939 order[2] = const2_rtx;
28940 order[3] = GEN_INT (3);
28941 order[elt] = const0_rtx;
28943 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28944 order[1], order[2], order[3]));
28946 ix86_expand_vector_set (false, target, val, 0);
28948 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28949 order[1], order[2], order[3]));
28953 /* For SSE1, we have to reuse the V4SF code. */
28954 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28955 gen_lowpart (SFmode, val), elt);
28960 use_vec_merge = TARGET_SSE2;
28963 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28967 use_vec_merge = TARGET_SSE4_1;
28974 half_mode = V16QImode;
28980 half_mode = V8HImode;
28986 half_mode = V4SImode;
28992 half_mode = V2DImode;
28998 half_mode = V4SFmode;
29004 half_mode = V2DFmode;
29010 /* Compute offset. */
29014 gcc_assert (i <= 1);
29016 /* Extract the half. */
29017 tmp = gen_reg_rtx (half_mode);
29018 emit_insn ((*gen_extract[j][i]) (tmp, target));
29020 /* Put val in tmp at elt. */
29021 ix86_expand_vector_set (false, tmp, val, elt);
29024 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
29033 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
29034 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
29035 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
29039 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
29041 emit_move_insn (mem, target);
29043 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
29044 emit_move_insn (tmp, val);
29046 emit_move_insn (target, mem);
29051 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
29053 enum machine_mode mode = GET_MODE (vec);
29054 enum machine_mode inner_mode = GET_MODE_INNER (mode);
29055 bool use_vec_extr = false;
29068 use_vec_extr = true;
29072 use_vec_extr = TARGET_SSE4_1;
29084 tmp = gen_reg_rtx (mode);
29085 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
29086 GEN_INT (elt), GEN_INT (elt),
29087 GEN_INT (elt+4), GEN_INT (elt+4)));
29091 tmp = gen_reg_rtx (mode);
29092 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
29096 gcc_unreachable ();
29099 use_vec_extr = true;
29104 use_vec_extr = TARGET_SSE4_1;
29118 tmp = gen_reg_rtx (mode);
29119 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
29120 GEN_INT (elt), GEN_INT (elt),
29121 GEN_INT (elt), GEN_INT (elt)));
29125 tmp = gen_reg_rtx (mode);
29126 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
29130 gcc_unreachable ();
29133 use_vec_extr = true;
29138 /* For SSE1, we have to reuse the V4SF code. */
29139 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
29140 gen_lowpart (V4SFmode, vec), elt);
29146 use_vec_extr = TARGET_SSE2;
29149 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
29153 use_vec_extr = TARGET_SSE4_1;
29157 /* ??? Could extract the appropriate HImode element and shift. */
29164 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
29165 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
29167 /* Let the rtl optimizers know about the zero extension performed. */
29168 if (inner_mode == QImode || inner_mode == HImode)
29170 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
29171 target = gen_lowpart (SImode, target);
29174 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
29178 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
29180 emit_move_insn (mem, vec);
29182 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
29183 emit_move_insn (target, tmp);
29187 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
29188 pattern to reduce; DEST is the destination; IN is the input vector. */
29191 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
29193 rtx tmp1, tmp2, tmp3;
29195 tmp1 = gen_reg_rtx (V4SFmode);
29196 tmp2 = gen_reg_rtx (V4SFmode);
29197 tmp3 = gen_reg_rtx (V4SFmode);
29199 emit_insn (gen_sse_movhlps (tmp1, in, in));
29200 emit_insn (fn (tmp2, tmp1, in));
29202 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
29203 const1_rtx, const1_rtx,
29204 GEN_INT (1+4), GEN_INT (1+4)));
29205 emit_insn (fn (dest, tmp2, tmp3));
29208 /* Target hook for scalar_mode_supported_p. */
29210 ix86_scalar_mode_supported_p (enum machine_mode mode)
29212 if (DECIMAL_FLOAT_MODE_P (mode))
29213 return default_decimal_float_supported_p ();
29214 else if (mode == TFmode)
29217 return default_scalar_mode_supported_p (mode);
29220 /* Implements target hook vector_mode_supported_p. */
29222 ix86_vector_mode_supported_p (enum machine_mode mode)
29224 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
29226 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
29228 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
29230 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
29232 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
29237 /* Target hook for c_mode_for_suffix. */
29238 static enum machine_mode
29239 ix86_c_mode_for_suffix (char suffix)
29249 /* Worker function for TARGET_MD_ASM_CLOBBERS.
29251 We do this in the new i386 backend to maintain source compatibility
29252 with the old cc0-based compiler. */
29255 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
29256 tree inputs ATTRIBUTE_UNUSED,
29259 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
29261 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
29266 /* Implements target vector targetm.asm.encode_section_info. This
29267 is not used by netware. */
29269 static void ATTRIBUTE_UNUSED
29270 ix86_encode_section_info (tree decl, rtx rtl, int first)
29272 default_encode_section_info (decl, rtl, first);
29274 if (TREE_CODE (decl) == VAR_DECL
29275 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
29276 && ix86_in_large_data_p (decl))
29277 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
29280 /* Worker function for REVERSE_CONDITION. */
29283 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
29285 return (mode != CCFPmode && mode != CCFPUmode
29286 ? reverse_condition (code)
29287 : reverse_condition_maybe_unordered (code));
29290 /* Output code to perform an x87 FP register move, from OPERANDS[1]
29294 output_387_reg_move (rtx insn, rtx *operands)
29296 if (REG_P (operands[0]))
29298 if (REG_P (operands[1])
29299 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
29301 if (REGNO (operands[0]) == FIRST_STACK_REG)
29302 return output_387_ffreep (operands, 0);
29303 return "fstp\t%y0";
29305 if (STACK_TOP_P (operands[0]))
29306 return "fld%Z1\t%y1";
29309 else if (MEM_P (operands[0]))
29311 gcc_assert (REG_P (operands[1]));
29312 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
29313 return "fstp%Z0\t%y0";
29316 /* There is no non-popping store to memory for XFmode.
29317 So if we need one, follow the store with a load. */
29318 if (GET_MODE (operands[0]) == XFmode)
29319 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
29321 return "fst%Z0\t%y0";
29328 /* Output code to perform a conditional jump to LABEL, if C2 flag in
29329 FP status register is set. */
29332 ix86_emit_fp_unordered_jump (rtx label)
29334 rtx reg = gen_reg_rtx (HImode);
29337 emit_insn (gen_x86_fnstsw_1 (reg));
29339 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
29341 emit_insn (gen_x86_sahf_1 (reg));
29343 temp = gen_rtx_REG (CCmode, FLAGS_REG);
29344 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
29348 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
29350 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
29351 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
29354 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
29355 gen_rtx_LABEL_REF (VOIDmode, label),
29357 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
29359 emit_jump_insn (temp);
29360 predict_jump (REG_BR_PROB_BASE * 10 / 100);
29363 /* Output code to perform a log1p XFmode calculation. */
29365 void ix86_emit_i387_log1p (rtx op0, rtx op1)
29367 rtx label1 = gen_label_rtx ();
29368 rtx label2 = gen_label_rtx ();
29370 rtx tmp = gen_reg_rtx (XFmode);
29371 rtx tmp2 = gen_reg_rtx (XFmode);
29374 emit_insn (gen_absxf2 (tmp, op1));
29375 test = gen_rtx_GE (VOIDmode, tmp,
29376 CONST_DOUBLE_FROM_REAL_VALUE (
29377 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
29379 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
29381 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
29382 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
29383 emit_jump (label2);
29385 emit_label (label1);
29386 emit_move_insn (tmp, CONST1_RTX (XFmode));
29387 emit_insn (gen_addxf3 (tmp, op1, tmp));
29388 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
29389 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
29391 emit_label (label2);
29394 /* Output code to perform a Newton-Rhapson approximation of a single precision
29395 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
29397 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
29399 rtx x0, x1, e0, e1, two;
29401 x0 = gen_reg_rtx (mode);
29402 e0 = gen_reg_rtx (mode);
29403 e1 = gen_reg_rtx (mode);
29404 x1 = gen_reg_rtx (mode);
29406 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
29408 if (VECTOR_MODE_P (mode))
29409 two = ix86_build_const_vector (SFmode, true, two);
29411 two = force_reg (mode, two);
29413 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
29415 /* x0 = rcp(b) estimate */
29416 emit_insn (gen_rtx_SET (VOIDmode, x0,
29417 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
29420 emit_insn (gen_rtx_SET (VOIDmode, e0,
29421 gen_rtx_MULT (mode, x0, a)));
29423 emit_insn (gen_rtx_SET (VOIDmode, e1,
29424 gen_rtx_MULT (mode, x0, b)));
29426 emit_insn (gen_rtx_SET (VOIDmode, x1,
29427 gen_rtx_MINUS (mode, two, e1)));
29428 /* res = e0 * x1 */
29429 emit_insn (gen_rtx_SET (VOIDmode, res,
29430 gen_rtx_MULT (mode, e0, x1)));
29433 /* Output code to perform a Newton-Rhapson approximation of a
29434 single precision floating point [reciprocal] square root. */
29436 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
29439 rtx x0, e0, e1, e2, e3, mthree, mhalf;
29442 x0 = gen_reg_rtx (mode);
29443 e0 = gen_reg_rtx (mode);
29444 e1 = gen_reg_rtx (mode);
29445 e2 = gen_reg_rtx (mode);
29446 e3 = gen_reg_rtx (mode);
29448 real_from_integer (&r, VOIDmode, -3, -1, 0);
29449 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29451 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
29452 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
29454 if (VECTOR_MODE_P (mode))
29456 mthree = ix86_build_const_vector (SFmode, true, mthree);
29457 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
29460 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
29461 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
29463 /* x0 = rsqrt(a) estimate */
29464 emit_insn (gen_rtx_SET (VOIDmode, x0,
29465 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
29468 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
29473 zero = gen_reg_rtx (mode);
29474 mask = gen_reg_rtx (mode);
29476 zero = force_reg (mode, CONST0_RTX(mode));
29477 emit_insn (gen_rtx_SET (VOIDmode, mask,
29478 gen_rtx_NE (mode, zero, a)));
29480 emit_insn (gen_rtx_SET (VOIDmode, x0,
29481 gen_rtx_AND (mode, x0, mask)));
29485 emit_insn (gen_rtx_SET (VOIDmode, e0,
29486 gen_rtx_MULT (mode, x0, a)));
29488 emit_insn (gen_rtx_SET (VOIDmode, e1,
29489 gen_rtx_MULT (mode, e0, x0)));
29492 mthree = force_reg (mode, mthree);
29493 emit_insn (gen_rtx_SET (VOIDmode, e2,
29494 gen_rtx_PLUS (mode, e1, mthree)));
29496 mhalf = force_reg (mode, mhalf);
29498 /* e3 = -.5 * x0 */
29499 emit_insn (gen_rtx_SET (VOIDmode, e3,
29500 gen_rtx_MULT (mode, x0, mhalf)));
29502 /* e3 = -.5 * e0 */
29503 emit_insn (gen_rtx_SET (VOIDmode, e3,
29504 gen_rtx_MULT (mode, e0, mhalf)));
29505 /* ret = e2 * e3 */
29506 emit_insn (gen_rtx_SET (VOIDmode, res,
29507 gen_rtx_MULT (mode, e2, e3)));
29510 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
29512 static void ATTRIBUTE_UNUSED
29513 i386_solaris_elf_named_section (const char *name, unsigned int flags,
29516 /* With Binutils 2.15, the "@unwind" marker must be specified on
29517 every occurrence of the ".eh_frame" section, not just the first
29520 && strcmp (name, ".eh_frame") == 0)
29522 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
29523 flags & SECTION_WRITE ? "aw" : "a");
29526 default_elf_asm_named_section (name, flags, decl);
29529 /* Return the mangling of TYPE if it is an extended fundamental type. */
29531 static const char *
29532 ix86_mangle_type (const_tree type)
29534 type = TYPE_MAIN_VARIANT (type);
29536 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
29537 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
29540 switch (TYPE_MODE (type))
29543 /* __float128 is "g". */
29546 /* "long double" or __float80 is "e". */
29553 /* For 32-bit code we can save PIC register setup by using
29554 __stack_chk_fail_local hidden function instead of calling
29555 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
29556 register, so it is better to call __stack_chk_fail directly. */
29559 ix86_stack_protect_fail (void)
29561 return TARGET_64BIT
29562 ? default_external_stack_protect_fail ()
29563 : default_hidden_stack_protect_fail ();
29566 /* Select a format to encode pointers in exception handling data. CODE
29567 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
29568 true if the symbol may be affected by dynamic relocations.
29570 ??? All x86 object file formats are capable of representing this.
29571 After all, the relocation needed is the same as for the call insn.
29572 Whether or not a particular assembler allows us to enter such, I
29573 guess we'll have to see. */
29575 asm_preferred_eh_data_format (int code, int global)
29579 int type = DW_EH_PE_sdata8;
29581 || ix86_cmodel == CM_SMALL_PIC
29582 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
29583 type = DW_EH_PE_sdata4;
29584 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
29586 if (ix86_cmodel == CM_SMALL
29587 || (ix86_cmodel == CM_MEDIUM && code))
29588 return DW_EH_PE_udata4;
29589 return DW_EH_PE_absptr;
29592 /* Expand copysign from SIGN to the positive value ABS_VALUE
29593 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
29596 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
29598 enum machine_mode mode = GET_MODE (sign);
29599 rtx sgn = gen_reg_rtx (mode);
29600 if (mask == NULL_RTX)
29602 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
29603 if (!VECTOR_MODE_P (mode))
29605 /* We need to generate a scalar mode mask in this case. */
29606 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29607 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29608 mask = gen_reg_rtx (mode);
29609 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29613 mask = gen_rtx_NOT (mode, mask);
29614 emit_insn (gen_rtx_SET (VOIDmode, sgn,
29615 gen_rtx_AND (mode, mask, sign)));
29616 emit_insn (gen_rtx_SET (VOIDmode, result,
29617 gen_rtx_IOR (mode, abs_value, sgn)));
29620 /* Expand fabs (OP0) and return a new rtx that holds the result. The
29621 mask for masking out the sign-bit is stored in *SMASK, if that is
29624 ix86_expand_sse_fabs (rtx op0, rtx *smask)
29626 enum machine_mode mode = GET_MODE (op0);
29629 xa = gen_reg_rtx (mode);
29630 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
29631 if (!VECTOR_MODE_P (mode))
29633 /* We need to generate a scalar mode mask in this case. */
29634 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
29635 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
29636 mask = gen_reg_rtx (mode);
29637 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
29639 emit_insn (gen_rtx_SET (VOIDmode, xa,
29640 gen_rtx_AND (mode, op0, mask)));
29648 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
29649 swapping the operands if SWAP_OPERANDS is true. The expanded
29650 code is a forward jump to a newly created label in case the
29651 comparison is true. The generated label rtx is returned. */
29653 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
29654 bool swap_operands)
29665 label = gen_label_rtx ();
29666 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
29667 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29668 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
29669 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
29670 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
29671 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
29672 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
29673 JUMP_LABEL (tmp) = label;
29678 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
29679 using comparison code CODE. Operands are swapped for the comparison if
29680 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
29682 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
29683 bool swap_operands)
29685 enum machine_mode mode = GET_MODE (op0);
29686 rtx mask = gen_reg_rtx (mode);
29695 if (mode == DFmode)
29696 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
29697 gen_rtx_fmt_ee (code, mode, op0, op1)));
29699 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
29700 gen_rtx_fmt_ee (code, mode, op0, op1)));
29705 /* Generate and return a rtx of mode MODE for 2**n where n is the number
29706 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
29708 ix86_gen_TWO52 (enum machine_mode mode)
29710 REAL_VALUE_TYPE TWO52r;
29713 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
29714 TWO52 = const_double_from_real_value (TWO52r, mode);
29715 TWO52 = force_reg (mode, TWO52);
29720 /* Expand SSE sequence for computing lround from OP1 storing
29723 ix86_expand_lround (rtx op0, rtx op1)
29725 /* C code for the stuff we're doing below:
29726 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
29729 enum machine_mode mode = GET_MODE (op1);
29730 const struct real_format *fmt;
29731 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29734 /* load nextafter (0.5, 0.0) */
29735 fmt = REAL_MODE_FORMAT (mode);
29736 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29737 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29739 /* adj = copysign (0.5, op1) */
29740 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
29741 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
29743 /* adj = op1 + adj */
29744 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
29746 /* op0 = (imode)adj */
29747 expand_fix (op0, adj, 0);
29750 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
29753 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
29755 /* C code for the stuff we're doing below (for do_floor):
29757 xi -= (double)xi > op1 ? 1 : 0;
29760 enum machine_mode fmode = GET_MODE (op1);
29761 enum machine_mode imode = GET_MODE (op0);
29762 rtx ireg, freg, label, tmp;
29764 /* reg = (long)op1 */
29765 ireg = gen_reg_rtx (imode);
29766 expand_fix (ireg, op1, 0);
29768 /* freg = (double)reg */
29769 freg = gen_reg_rtx (fmode);
29770 expand_float (freg, ireg, 0);
29772 /* ireg = (freg > op1) ? ireg - 1 : ireg */
29773 label = ix86_expand_sse_compare_and_jump (UNLE,
29774 freg, op1, !do_floor);
29775 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
29776 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
29777 emit_move_insn (ireg, tmp);
29779 emit_label (label);
29780 LABEL_NUSES (label) = 1;
29782 emit_move_insn (op0, ireg);
29785 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
29786 result in OPERAND0. */
29788 ix86_expand_rint (rtx operand0, rtx operand1)
29790 /* C code for the stuff we're doing below:
29791 xa = fabs (operand1);
29792 if (!isless (xa, 2**52))
29794 xa = xa + 2**52 - 2**52;
29795 return copysign (xa, operand1);
29797 enum machine_mode mode = GET_MODE (operand0);
29798 rtx res, xa, label, TWO52, mask;
29800 res = gen_reg_rtx (mode);
29801 emit_move_insn (res, operand1);
29803 /* xa = abs (operand1) */
29804 xa = ix86_expand_sse_fabs (res, &mask);
29806 /* if (!isless (xa, TWO52)) goto label; */
29807 TWO52 = ix86_gen_TWO52 (mode);
29808 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29810 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29811 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29813 ix86_sse_copysign_to_positive (res, xa, res, mask);
29815 emit_label (label);
29816 LABEL_NUSES (label) = 1;
29818 emit_move_insn (operand0, res);
29821 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29824 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29826 /* C code for the stuff we expand below.
29827 double xa = fabs (x), x2;
29828 if (!isless (xa, TWO52))
29830 xa = xa + TWO52 - TWO52;
29831 x2 = copysign (xa, x);
29840 enum machine_mode mode = GET_MODE (operand0);
29841 rtx xa, TWO52, tmp, label, one, res, mask;
29843 TWO52 = ix86_gen_TWO52 (mode);
29845 /* Temporary for holding the result, initialized to the input
29846 operand to ease control flow. */
29847 res = gen_reg_rtx (mode);
29848 emit_move_insn (res, operand1);
29850 /* xa = abs (operand1) */
29851 xa = ix86_expand_sse_fabs (res, &mask);
29853 /* if (!isless (xa, TWO52)) goto label; */
29854 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29856 /* xa = xa + TWO52 - TWO52; */
29857 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29858 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29860 /* xa = copysign (xa, operand1) */
29861 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29863 /* generate 1.0 or -1.0 */
29864 one = force_reg (mode,
29865 const_double_from_real_value (do_floor
29866 ? dconst1 : dconstm1, mode));
29868 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29869 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29870 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29871 gen_rtx_AND (mode, one, tmp)));
29872 /* We always need to subtract here to preserve signed zero. */
29873 tmp = expand_simple_binop (mode, MINUS,
29874 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29875 emit_move_insn (res, tmp);
29877 emit_label (label);
29878 LABEL_NUSES (label) = 1;
29880 emit_move_insn (operand0, res);
29883 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29886 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29888 /* C code for the stuff we expand below.
29889 double xa = fabs (x), x2;
29890 if (!isless (xa, TWO52))
29892 x2 = (double)(long)x;
29899 if (HONOR_SIGNED_ZEROS (mode))
29900 return copysign (x2, x);
29903 enum machine_mode mode = GET_MODE (operand0);
29904 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29906 TWO52 = ix86_gen_TWO52 (mode);
29908 /* Temporary for holding the result, initialized to the input
29909 operand to ease control flow. */
29910 res = gen_reg_rtx (mode);
29911 emit_move_insn (res, operand1);
29913 /* xa = abs (operand1) */
29914 xa = ix86_expand_sse_fabs (res, &mask);
29916 /* if (!isless (xa, TWO52)) goto label; */
29917 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29919 /* xa = (double)(long)x */
29920 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29921 expand_fix (xi, res, 0);
29922 expand_float (xa, xi, 0);
29925 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29927 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29928 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29929 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29930 gen_rtx_AND (mode, one, tmp)));
29931 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29932 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29933 emit_move_insn (res, tmp);
29935 if (HONOR_SIGNED_ZEROS (mode))
29936 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29938 emit_label (label);
29939 LABEL_NUSES (label) = 1;
29941 emit_move_insn (operand0, res);
29944 /* Expand SSE sequence for computing round from OPERAND1 storing
29945 into OPERAND0. Sequence that works without relying on DImode truncation
29946 via cvttsd2siq that is only available on 64bit targets. */
29948 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29950 /* C code for the stuff we expand below.
29951 double xa = fabs (x), xa2, x2;
29952 if (!isless (xa, TWO52))
29954 Using the absolute value and copying back sign makes
29955 -0.0 -> -0.0 correct.
29956 xa2 = xa + TWO52 - TWO52;
29961 else if (dxa > 0.5)
29963 x2 = copysign (xa2, x);
29966 enum machine_mode mode = GET_MODE (operand0);
29967 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29969 TWO52 = ix86_gen_TWO52 (mode);
29971 /* Temporary for holding the result, initialized to the input
29972 operand to ease control flow. */
29973 res = gen_reg_rtx (mode);
29974 emit_move_insn (res, operand1);
29976 /* xa = abs (operand1) */
29977 xa = ix86_expand_sse_fabs (res, &mask);
29979 /* if (!isless (xa, TWO52)) goto label; */
29980 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29982 /* xa2 = xa + TWO52 - TWO52; */
29983 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29984 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29986 /* dxa = xa2 - xa; */
29987 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29989 /* generate 0.5, 1.0 and -0.5 */
29990 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29991 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29992 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29996 tmp = gen_reg_rtx (mode);
29997 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29998 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29999 emit_insn (gen_rtx_SET (VOIDmode, tmp,
30000 gen_rtx_AND (mode, one, tmp)));
30001 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
30002 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
30003 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
30004 emit_insn (gen_rtx_SET (VOIDmode, tmp,
30005 gen_rtx_AND (mode, one, tmp)));
30006 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
30008 /* res = copysign (xa2, operand1) */
30009 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
30011 emit_label (label);
30012 LABEL_NUSES (label) = 1;
30014 emit_move_insn (operand0, res);
30017 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30020 ix86_expand_trunc (rtx operand0, rtx operand1)
30022 /* C code for SSE variant we expand below.
30023 double xa = fabs (x), x2;
30024 if (!isless (xa, TWO52))
30026 x2 = (double)(long)x;
30027 if (HONOR_SIGNED_ZEROS (mode))
30028 return copysign (x2, x);
30031 enum machine_mode mode = GET_MODE (operand0);
30032 rtx xa, xi, TWO52, label, res, mask;
30034 TWO52 = ix86_gen_TWO52 (mode);
30036 /* Temporary for holding the result, initialized to the input
30037 operand to ease control flow. */
30038 res = gen_reg_rtx (mode);
30039 emit_move_insn (res, operand1);
30041 /* xa = abs (operand1) */
30042 xa = ix86_expand_sse_fabs (res, &mask);
30044 /* if (!isless (xa, TWO52)) goto label; */
30045 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30047 /* x = (double)(long)x */
30048 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
30049 expand_fix (xi, res, 0);
30050 expand_float (res, xi, 0);
30052 if (HONOR_SIGNED_ZEROS (mode))
30053 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
30055 emit_label (label);
30056 LABEL_NUSES (label) = 1;
30058 emit_move_insn (operand0, res);
30061 /* Expand SSE sequence for computing trunc from OPERAND1 storing
30064 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
30066 enum machine_mode mode = GET_MODE (operand0);
30067 rtx xa, mask, TWO52, label, one, res, smask, tmp;
30069 /* C code for SSE variant we expand below.
30070 double xa = fabs (x), x2;
30071 if (!isless (xa, TWO52))
30073 xa2 = xa + TWO52 - TWO52;
30077 x2 = copysign (xa2, x);
30081 TWO52 = ix86_gen_TWO52 (mode);
30083 /* Temporary for holding the result, initialized to the input
30084 operand to ease control flow. */
30085 res = gen_reg_rtx (mode);
30086 emit_move_insn (res, operand1);
30088 /* xa = abs (operand1) */
30089 xa = ix86_expand_sse_fabs (res, &smask);
30091 /* if (!isless (xa, TWO52)) goto label; */
30092 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30094 /* res = xa + TWO52 - TWO52; */
30095 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
30096 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
30097 emit_move_insn (res, tmp);
30100 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
30102 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
30103 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
30104 emit_insn (gen_rtx_SET (VOIDmode, mask,
30105 gen_rtx_AND (mode, mask, one)));
30106 tmp = expand_simple_binop (mode, MINUS,
30107 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
30108 emit_move_insn (res, tmp);
30110 /* res = copysign (res, operand1) */
30111 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
30113 emit_label (label);
30114 LABEL_NUSES (label) = 1;
30116 emit_move_insn (operand0, res);
30119 /* Expand SSE sequence for computing round from OPERAND1 storing
30122 ix86_expand_round (rtx operand0, rtx operand1)
30124 /* C code for the stuff we're doing below:
30125 double xa = fabs (x);
30126 if (!isless (xa, TWO52))
30128 xa = (double)(long)(xa + nextafter (0.5, 0.0));
30129 return copysign (xa, x);
30131 enum machine_mode mode = GET_MODE (operand0);
30132 rtx res, TWO52, xa, label, xi, half, mask;
30133 const struct real_format *fmt;
30134 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
30136 /* Temporary for holding the result, initialized to the input
30137 operand to ease control flow. */
30138 res = gen_reg_rtx (mode);
30139 emit_move_insn (res, operand1);
30141 TWO52 = ix86_gen_TWO52 (mode);
30142 xa = ix86_expand_sse_fabs (res, &mask);
30143 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
30145 /* load nextafter (0.5, 0.0) */
30146 fmt = REAL_MODE_FORMAT (mode);
30147 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
30148 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
30150 /* xa = xa + 0.5 */
30151 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
30152 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
30154 /* xa = (double)(int64_t)xa */
30155 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
30156 expand_fix (xi, xa, 0);
30157 expand_float (xa, xi, 0);
30159 /* res = copysign (xa, operand1) */
30160 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
30162 emit_label (label);
30163 LABEL_NUSES (label) = 1;
30165 emit_move_insn (operand0, res);
30168 /* Validate whether a FMA4 instruction is valid or not.
30169 OPERANDS is the array of operands.
30170 NUM is the number of operands.
30171 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
30172 NUM_MEMORY is the maximum number of memory operands to accept.
30173 NUM_MEMORY less than zero is a special case to allow an operand
30174 of an instruction to be memory operation.
30175 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
30178 ix86_fma4_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
30179 bool uses_oc0, int num_memory, bool commutative)
30185 /* Count the number of memory arguments */
30188 for (i = 0; i < num; i++)
30190 enum machine_mode mode = GET_MODE (operands[i]);
30191 if (register_operand (operands[i], mode))
30194 else if (memory_operand (operands[i], mode))
30196 mem_mask |= (1 << i);
30202 rtx pattern = PATTERN (insn);
30204 /* allow 0 for pcmov */
30205 if (GET_CODE (pattern) != SET
30206 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
30208 || operands[i] != CONST0_RTX (mode))
30213 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
30214 a memory operation. */
30215 if (num_memory < 0)
30217 num_memory = -num_memory;
30218 if ((mem_mask & (1 << (num-1))) != 0)
30220 mem_mask &= ~(1 << (num-1));
30225 /* If there were no memory operations, allow the insn */
30229 /* Do not allow the destination register to be a memory operand. */
30230 else if (mem_mask & (1 << 0))
30233 /* If there are too many memory operations, disallow the instruction. While
30234 the hardware only allows 1 memory reference, before register allocation
30235 for some insns, we allow two memory operations sometimes in order to allow
30236 code like the following to be optimized:
30238 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
30240 or similar cases that are vectorized into using the vfmaddss
30242 else if (mem_count > num_memory)
30245 /* Don't allow more than one memory operation if not optimizing. */
30246 else if (mem_count > 1 && !optimize)
30249 else if (num == 4 && mem_count == 1)
30251 /* formats (destination is the first argument), example vfmaddss:
30252 xmm1, xmm1, xmm2, xmm3/mem
30253 xmm1, xmm1, xmm2/mem, xmm3
30254 xmm1, xmm2, xmm3/mem, xmm1
30255 xmm1, xmm2/mem, xmm3, xmm1 */
30257 return ((mem_mask == (1 << 1))
30258 || (mem_mask == (1 << 2))
30259 || (mem_mask == (1 << 3)));
30261 /* format, example vpmacsdd:
30262 xmm1, xmm2, xmm3/mem, xmm1 */
30264 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
30266 return (mem_mask == (1 << 2));
30269 else if (num == 4 && num_memory == 2)
30271 /* If there are two memory operations, we can load one of the memory ops
30272 into the destination register. This is for optimizing the
30273 multiply/add ops, which the combiner has optimized both the multiply
30274 and the add insns to have a memory operation. We have to be careful
30275 that the destination doesn't overlap with the inputs. */
30276 rtx op0 = operands[0];
30278 if (reg_mentioned_p (op0, operands[1])
30279 || reg_mentioned_p (op0, operands[2])
30280 || reg_mentioned_p (op0, operands[3]))
30283 /* formats (destination is the first argument), example vfmaddss:
30284 xmm1, xmm1, xmm2, xmm3/mem
30285 xmm1, xmm1, xmm2/mem, xmm3
30286 xmm1, xmm2, xmm3/mem, xmm1
30287 xmm1, xmm2/mem, xmm3, xmm1
30289 For the oc0 case, we will load either operands[1] or operands[3] into
30290 operands[0], so any combination of 2 memory operands is ok. */
30294 /* format, example vpmacsdd:
30295 xmm1, xmm2, xmm3/mem, xmm1
30297 For the integer multiply/add instructions be more restrictive and
30298 require operands[2] and operands[3] to be the memory operands. */
30300 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
30302 return (mem_mask == ((1 << 2) | (1 << 3)));
30305 else if (num == 3 && num_memory == 1)
30307 /* formats, example vprotb:
30308 xmm1, xmm2, xmm3/mem
30309 xmm1, xmm2/mem, xmm3 */
30311 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
30313 /* format, example vpcomeq:
30314 xmm1, xmm2, xmm3/mem */
30316 return (mem_mask == (1 << 2));
30320 gcc_unreachable ();
30326 /* Fixup an FMA4 instruction that has 2 memory input references into a form the
30327 hardware will allow by using the destination register to load one of the
30328 memory operations. Presently this is used by the multiply/add routines to
30329 allow 2 memory references. */
30332 ix86_expand_fma4_multiple_memory (rtx operands[],
30334 enum machine_mode mode)
30336 rtx op0 = operands[0];
30338 || memory_operand (op0, mode)
30339 || reg_mentioned_p (op0, operands[1])
30340 || reg_mentioned_p (op0, operands[2])
30341 || reg_mentioned_p (op0, operands[3]))
30342 gcc_unreachable ();
30344 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
30345 the destination register. */
30346 if (memory_operand (operands[1], mode))
30348 emit_move_insn (op0, operands[1]);
30351 else if (memory_operand (operands[3], mode))
30353 emit_move_insn (op0, operands[3]);
30357 gcc_unreachable ();
30362 /* Table of valid machine attributes. */
30363 static const struct attribute_spec ix86_attribute_table[] =
30365 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
30366 /* Stdcall attribute says callee is responsible for popping arguments
30367 if they are not variable. */
30368 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30369 /* Fastcall attribute says callee is responsible for popping arguments
30370 if they are not variable. */
30371 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30372 /* Cdecl attribute says the callee is a normal C declaration */
30373 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30374 /* Regparm attribute specifies how many integer arguments are to be
30375 passed in registers. */
30376 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
30377 /* Sseregparm attribute says we are using x86_64 calling conventions
30378 for FP arguments. */
30379 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
30380 /* force_align_arg_pointer says this function realigns the stack at entry. */
30381 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
30382 false, true, true, ix86_handle_cconv_attribute },
30383 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30384 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
30385 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
30386 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
30388 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
30389 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
30390 #ifdef SUBTARGET_ATTRIBUTE_TABLE
30391 SUBTARGET_ATTRIBUTE_TABLE,
30393 /* ms_abi and sysv_abi calling convention function attributes. */
30394 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
30395 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
30396 { "ms_hook_prologue", 0, 0, true, false, false, ix86_handle_fndecl_attribute },
30398 { NULL, 0, 0, false, false, false, NULL }
30401 /* Implement targetm.vectorize.builtin_vectorization_cost. */
30403 x86_builtin_vectorization_cost (bool runtime_test)
30405 /* If the branch of the runtime test is taken - i.e. - the vectorized
30406 version is skipped - this incurs a misprediction cost (because the
30407 vectorized version is expected to be the fall-through). So we subtract
30408 the latency of a mispredicted branch from the costs that are incured
30409 when the vectorized version is executed.
30411 TODO: The values in individual target tables have to be tuned or new
30412 fields may be needed. For eg. on K8, the default branch path is the
30413 not-taken path. If the taken path is predicted correctly, the minimum
30414 penalty of going down the taken-path is 1 cycle. If the taken-path is
30415 not predicted correctly, then the minimum penalty is 10 cycles. */
30419 return (-(ix86_cost->cond_taken_branch_cost));
30425 /* This function returns the calling abi specific va_list type node.
30426 It returns the FNDECL specific va_list type. */
30429 ix86_fn_abi_va_list (tree fndecl)
30432 return va_list_type_node;
30433 gcc_assert (fndecl != NULL_TREE);
30435 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
30436 return ms_va_list_type_node;
30438 return sysv_va_list_type_node;
30441 /* Returns the canonical va_list type specified by TYPE. If there
30442 is no valid TYPE provided, it return NULL_TREE. */
30445 ix86_canonical_va_list_type (tree type)
30449 /* Resolve references and pointers to va_list type. */
30450 if (INDIRECT_REF_P (type))
30451 type = TREE_TYPE (type);
30452 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
30453 type = TREE_TYPE (type);
30457 wtype = va_list_type_node;
30458 gcc_assert (wtype != NULL_TREE);
30460 if (TREE_CODE (wtype) == ARRAY_TYPE)
30462 /* If va_list is an array type, the argument may have decayed
30463 to a pointer type, e.g. by being passed to another function.
30464 In that case, unwrap both types so that we can compare the
30465 underlying records. */
30466 if (TREE_CODE (htype) == ARRAY_TYPE
30467 || POINTER_TYPE_P (htype))
30469 wtype = TREE_TYPE (wtype);
30470 htype = TREE_TYPE (htype);
30473 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30474 return va_list_type_node;
30475 wtype = sysv_va_list_type_node;
30476 gcc_assert (wtype != NULL_TREE);
30478 if (TREE_CODE (wtype) == ARRAY_TYPE)
30480 /* If va_list is an array type, the argument may have decayed
30481 to a pointer type, e.g. by being passed to another function.
30482 In that case, unwrap both types so that we can compare the
30483 underlying records. */
30484 if (TREE_CODE (htype) == ARRAY_TYPE
30485 || POINTER_TYPE_P (htype))
30487 wtype = TREE_TYPE (wtype);
30488 htype = TREE_TYPE (htype);
30491 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30492 return sysv_va_list_type_node;
30493 wtype = ms_va_list_type_node;
30494 gcc_assert (wtype != NULL_TREE);
30496 if (TREE_CODE (wtype) == ARRAY_TYPE)
30498 /* If va_list is an array type, the argument may have decayed
30499 to a pointer type, e.g. by being passed to another function.
30500 In that case, unwrap both types so that we can compare the
30501 underlying records. */
30502 if (TREE_CODE (htype) == ARRAY_TYPE
30503 || POINTER_TYPE_P (htype))
30505 wtype = TREE_TYPE (wtype);
30506 htype = TREE_TYPE (htype);
30509 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
30510 return ms_va_list_type_node;
30513 return std_canonical_va_list_type (type);
30516 /* Iterate through the target-specific builtin types for va_list.
30517 IDX denotes the iterator, *PTREE is set to the result type of
30518 the va_list builtin, and *PNAME to its internal type.
30519 Returns zero if there is no element for this index, otherwise
30520 IDX should be increased upon the next call.
30521 Note, do not iterate a base builtin's name like __builtin_va_list.
30522 Used from c_common_nodes_and_builtins. */
30525 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
30531 *ptree = ms_va_list_type_node;
30532 *pname = "__builtin_ms_va_list";
30535 *ptree = sysv_va_list_type_node;
30536 *pname = "__builtin_sysv_va_list";
30544 /* Initialize the GCC target structure. */
30545 #undef TARGET_RETURN_IN_MEMORY
30546 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
30548 #undef TARGET_LEGITIMIZE_ADDRESS
30549 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
30551 #undef TARGET_ATTRIBUTE_TABLE
30552 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
30553 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30554 # undef TARGET_MERGE_DECL_ATTRIBUTES
30555 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
30558 #undef TARGET_COMP_TYPE_ATTRIBUTES
30559 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
30561 #undef TARGET_INIT_BUILTINS
30562 #define TARGET_INIT_BUILTINS ix86_init_builtins
30563 #undef TARGET_BUILTIN_DECL
30564 #define TARGET_BUILTIN_DECL ix86_builtin_decl
30565 #undef TARGET_EXPAND_BUILTIN
30566 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
30568 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
30569 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
30570 ix86_builtin_vectorized_function
30572 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
30573 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
30575 #undef TARGET_BUILTIN_RECIPROCAL
30576 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
30578 #undef TARGET_ASM_FUNCTION_EPILOGUE
30579 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
30581 #undef TARGET_ENCODE_SECTION_INFO
30582 #ifndef SUBTARGET_ENCODE_SECTION_INFO
30583 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
30585 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
30588 #undef TARGET_ASM_OPEN_PAREN
30589 #define TARGET_ASM_OPEN_PAREN ""
30590 #undef TARGET_ASM_CLOSE_PAREN
30591 #define TARGET_ASM_CLOSE_PAREN ""
30593 #undef TARGET_ASM_BYTE_OP
30594 #define TARGET_ASM_BYTE_OP ASM_BYTE
30596 #undef TARGET_ASM_ALIGNED_HI_OP
30597 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
30598 #undef TARGET_ASM_ALIGNED_SI_OP
30599 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
30601 #undef TARGET_ASM_ALIGNED_DI_OP
30602 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
30605 #undef TARGET_ASM_UNALIGNED_HI_OP
30606 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
30607 #undef TARGET_ASM_UNALIGNED_SI_OP
30608 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
30609 #undef TARGET_ASM_UNALIGNED_DI_OP
30610 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
30612 #undef TARGET_SCHED_ADJUST_COST
30613 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
30614 #undef TARGET_SCHED_ISSUE_RATE
30615 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
30616 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
30617 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
30618 ia32_multipass_dfa_lookahead
30620 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
30621 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
30624 #undef TARGET_HAVE_TLS
30625 #define TARGET_HAVE_TLS true
30627 #undef TARGET_CANNOT_FORCE_CONST_MEM
30628 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
30629 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
30630 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
30632 #undef TARGET_DELEGITIMIZE_ADDRESS
30633 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
30635 #undef TARGET_MS_BITFIELD_LAYOUT_P
30636 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
30639 #undef TARGET_BINDS_LOCAL_P
30640 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
30642 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
30643 #undef TARGET_BINDS_LOCAL_P
30644 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
30647 #undef TARGET_ASM_OUTPUT_MI_THUNK
30648 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
30649 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
30650 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
30652 #undef TARGET_ASM_FILE_START
30653 #define TARGET_ASM_FILE_START x86_file_start
30655 #undef TARGET_DEFAULT_TARGET_FLAGS
30656 #define TARGET_DEFAULT_TARGET_FLAGS \
30658 | TARGET_SUBTARGET_DEFAULT \
30659 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
30661 #undef TARGET_HANDLE_OPTION
30662 #define TARGET_HANDLE_OPTION ix86_handle_option
30664 #undef TARGET_RTX_COSTS
30665 #define TARGET_RTX_COSTS ix86_rtx_costs
30666 #undef TARGET_ADDRESS_COST
30667 #define TARGET_ADDRESS_COST ix86_address_cost
30669 #undef TARGET_FIXED_CONDITION_CODE_REGS
30670 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
30671 #undef TARGET_CC_MODES_COMPATIBLE
30672 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
30674 #undef TARGET_MACHINE_DEPENDENT_REORG
30675 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
30677 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
30678 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
30680 #undef TARGET_BUILD_BUILTIN_VA_LIST
30681 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
30683 #undef TARGET_FN_ABI_VA_LIST
30684 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
30686 #undef TARGET_CANONICAL_VA_LIST_TYPE
30687 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
30689 #undef TARGET_EXPAND_BUILTIN_VA_START
30690 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
30692 #undef TARGET_MD_ASM_CLOBBERS
30693 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
30695 #undef TARGET_PROMOTE_PROTOTYPES
30696 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
30697 #undef TARGET_STRUCT_VALUE_RTX
30698 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
30699 #undef TARGET_SETUP_INCOMING_VARARGS
30700 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
30701 #undef TARGET_MUST_PASS_IN_STACK
30702 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
30703 #undef TARGET_PASS_BY_REFERENCE
30704 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
30705 #undef TARGET_INTERNAL_ARG_POINTER
30706 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
30707 #undef TARGET_UPDATE_STACK_BOUNDARY
30708 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
30709 #undef TARGET_GET_DRAP_RTX
30710 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
30711 #undef TARGET_STRICT_ARGUMENT_NAMING
30712 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
30713 #undef TARGET_STATIC_CHAIN
30714 #define TARGET_STATIC_CHAIN ix86_static_chain
30715 #undef TARGET_TRAMPOLINE_INIT
30716 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
30718 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
30719 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
30721 #undef TARGET_SCALAR_MODE_SUPPORTED_P
30722 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
30724 #undef TARGET_VECTOR_MODE_SUPPORTED_P
30725 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
30727 #undef TARGET_C_MODE_FOR_SUFFIX
30728 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
30731 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
30732 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
30735 #ifdef SUBTARGET_INSERT_ATTRIBUTES
30736 #undef TARGET_INSERT_ATTRIBUTES
30737 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
30740 #undef TARGET_MANGLE_TYPE
30741 #define TARGET_MANGLE_TYPE ix86_mangle_type
30743 #undef TARGET_STACK_PROTECT_FAIL
30744 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
30746 #undef TARGET_FUNCTION_VALUE
30747 #define TARGET_FUNCTION_VALUE ix86_function_value
30749 #undef TARGET_SECONDARY_RELOAD
30750 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
30752 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
30753 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
30755 #undef TARGET_SET_CURRENT_FUNCTION
30756 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
30758 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
30759 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
30761 #undef TARGET_OPTION_SAVE
30762 #define TARGET_OPTION_SAVE ix86_function_specific_save
30764 #undef TARGET_OPTION_RESTORE
30765 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
30767 #undef TARGET_OPTION_PRINT
30768 #define TARGET_OPTION_PRINT ix86_function_specific_print
30770 #undef TARGET_CAN_INLINE_P
30771 #define TARGET_CAN_INLINE_P ix86_can_inline_p
30773 #undef TARGET_EXPAND_TO_RTL_HOOK
30774 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
30776 #undef TARGET_LEGITIMATE_ADDRESS_P
30777 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
30779 #undef TARGET_IRA_COVER_CLASSES
30780 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
30782 #undef TARGET_FRAME_POINTER_REQUIRED
30783 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
30785 #undef TARGET_CAN_ELIMINATE
30786 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
30788 struct gcc_target targetm = TARGET_INITIALIZER;
30790 #include "gt-i386.h"
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