1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-codes.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
46 #include "target-def.h"
47 #include "langhooks.h"
49 #include "tree-gimple.h"
52 #include "tm-constrs.h"
55 static int x86_builtin_vectorization_cost (bool);
57 #ifndef CHECK_STACK_LIMIT
58 #define CHECK_STACK_LIMIT (-1)
61 /* Return index of given mode in mult and division cost tables. */
62 #define MODE_INDEX(mode) \
63 ((mode) == QImode ? 0 \
64 : (mode) == HImode ? 1 \
65 : (mode) == SImode ? 2 \
66 : (mode) == DImode ? 3 \
69 /* Processor costs (relative to an add) */
70 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
71 #define COSTS_N_BYTES(N) ((N) * 2)
73 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
76 struct processor_costs size_cost = { /* costs for tuning for size */
77 COSTS_N_BYTES (2), /* cost of an add instruction */
78 COSTS_N_BYTES (3), /* cost of a lea instruction */
79 COSTS_N_BYTES (2), /* variable shift costs */
80 COSTS_N_BYTES (3), /* constant shift costs */
81 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
82 COSTS_N_BYTES (3), /* HI */
83 COSTS_N_BYTES (3), /* SI */
84 COSTS_N_BYTES (3), /* DI */
85 COSTS_N_BYTES (5)}, /* other */
86 0, /* cost of multiply per each bit set */
87 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
88 COSTS_N_BYTES (3), /* HI */
89 COSTS_N_BYTES (3), /* SI */
90 COSTS_N_BYTES (3), /* DI */
91 COSTS_N_BYTES (5)}, /* other */
92 COSTS_N_BYTES (3), /* cost of movsx */
93 COSTS_N_BYTES (3), /* cost of movzx */
96 2, /* cost for loading QImode using movzbl */
97 {2, 2, 2}, /* cost of loading integer registers
98 in QImode, HImode and SImode.
99 Relative to reg-reg move (2). */
100 {2, 2, 2}, /* cost of storing integer registers */
101 2, /* cost of reg,reg fld/fst */
102 {2, 2, 2}, /* cost of loading fp registers
103 in SFmode, DFmode and XFmode */
104 {2, 2, 2}, /* cost of storing fp registers
105 in SFmode, DFmode and XFmode */
106 3, /* cost of moving MMX register */
107 {3, 3}, /* cost of loading MMX registers
108 in SImode and DImode */
109 {3, 3}, /* cost of storing MMX registers
110 in SImode and DImode */
111 3, /* cost of moving SSE register */
112 {3, 3, 3}, /* cost of loading SSE registers
113 in SImode, DImode and TImode */
114 {3, 3, 3}, /* cost of storing SSE registers
115 in SImode, DImode and TImode */
116 3, /* MMX or SSE register to integer */
117 0, /* size of l1 cache */
118 0, /* size of l2 cache */
119 0, /* size of prefetch block */
120 0, /* number of parallel prefetches */
122 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
123 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
124 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
125 COSTS_N_BYTES (2), /* cost of FABS instruction. */
126 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
127 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
128 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
129 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
130 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
131 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
132 1, /* scalar_stmt_cost. */
133 1, /* scalar load_cost. */
134 1, /* scalar_store_cost. */
135 1, /* vec_stmt_cost. */
136 1, /* vec_to_scalar_cost. */
137 1, /* scalar_to_vec_cost. */
138 1, /* vec_align_load_cost. */
139 1, /* vec_unalign_load_cost. */
140 1, /* vec_store_cost. */
141 1, /* cond_taken_branch_cost. */
142 1, /* cond_not_taken_branch_cost. */
145 /* Processor costs (relative to an add) */
147 struct processor_costs i386_cost = { /* 386 specific costs */
148 COSTS_N_INSNS (1), /* cost of an add instruction */
149 COSTS_N_INSNS (1), /* cost of a lea instruction */
150 COSTS_N_INSNS (3), /* variable shift costs */
151 COSTS_N_INSNS (2), /* constant shift costs */
152 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
153 COSTS_N_INSNS (6), /* HI */
154 COSTS_N_INSNS (6), /* SI */
155 COSTS_N_INSNS (6), /* DI */
156 COSTS_N_INSNS (6)}, /* other */
157 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
158 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
159 COSTS_N_INSNS (23), /* HI */
160 COSTS_N_INSNS (23), /* SI */
161 COSTS_N_INSNS (23), /* DI */
162 COSTS_N_INSNS (23)}, /* other */
163 COSTS_N_INSNS (3), /* cost of movsx */
164 COSTS_N_INSNS (2), /* cost of movzx */
165 15, /* "large" insn */
167 4, /* cost for loading QImode using movzbl */
168 {2, 4, 2}, /* cost of loading integer registers
169 in QImode, HImode and SImode.
170 Relative to reg-reg move (2). */
171 {2, 4, 2}, /* cost of storing integer registers */
172 2, /* cost of reg,reg fld/fst */
173 {8, 8, 8}, /* cost of loading fp registers
174 in SFmode, DFmode and XFmode */
175 {8, 8, 8}, /* cost of storing fp registers
176 in SFmode, DFmode and XFmode */
177 2, /* cost of moving MMX register */
178 {4, 8}, /* cost of loading MMX registers
179 in SImode and DImode */
180 {4, 8}, /* cost of storing MMX registers
181 in SImode and DImode */
182 2, /* cost of moving SSE register */
183 {4, 8, 16}, /* cost of loading SSE registers
184 in SImode, DImode and TImode */
185 {4, 8, 16}, /* cost of storing SSE registers
186 in SImode, DImode and TImode */
187 3, /* MMX or SSE register to integer */
188 0, /* size of l1 cache */
189 0, /* size of l2 cache */
190 0, /* size of prefetch block */
191 0, /* number of parallel prefetches */
193 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
194 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
195 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
196 COSTS_N_INSNS (22), /* cost of FABS instruction. */
197 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
198 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
199 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
200 DUMMY_STRINGOP_ALGS},
201 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
202 DUMMY_STRINGOP_ALGS},
203 1, /* scalar_stmt_cost. */
204 1, /* scalar load_cost. */
205 1, /* scalar_store_cost. */
206 1, /* vec_stmt_cost. */
207 1, /* vec_to_scalar_cost. */
208 1, /* scalar_to_vec_cost. */
209 1, /* vec_align_load_cost. */
210 2, /* vec_unalign_load_cost. */
211 1, /* vec_store_cost. */
212 3, /* cond_taken_branch_cost. */
213 1, /* cond_not_taken_branch_cost. */
217 struct processor_costs i486_cost = { /* 486 specific costs */
218 COSTS_N_INSNS (1), /* cost of an add instruction */
219 COSTS_N_INSNS (1), /* cost of a lea instruction */
220 COSTS_N_INSNS (3), /* variable shift costs */
221 COSTS_N_INSNS (2), /* constant shift costs */
222 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
223 COSTS_N_INSNS (12), /* HI */
224 COSTS_N_INSNS (12), /* SI */
225 COSTS_N_INSNS (12), /* DI */
226 COSTS_N_INSNS (12)}, /* other */
227 1, /* cost of multiply per each bit set */
228 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
229 COSTS_N_INSNS (40), /* HI */
230 COSTS_N_INSNS (40), /* SI */
231 COSTS_N_INSNS (40), /* DI */
232 COSTS_N_INSNS (40)}, /* other */
233 COSTS_N_INSNS (3), /* cost of movsx */
234 COSTS_N_INSNS (2), /* cost of movzx */
235 15, /* "large" insn */
237 4, /* cost for loading QImode using movzbl */
238 {2, 4, 2}, /* cost of loading integer registers
239 in QImode, HImode and SImode.
240 Relative to reg-reg move (2). */
241 {2, 4, 2}, /* cost of storing integer registers */
242 2, /* cost of reg,reg fld/fst */
243 {8, 8, 8}, /* cost of loading fp registers
244 in SFmode, DFmode and XFmode */
245 {8, 8, 8}, /* cost of storing fp registers
246 in SFmode, DFmode and XFmode */
247 2, /* cost of moving MMX register */
248 {4, 8}, /* cost of loading MMX registers
249 in SImode and DImode */
250 {4, 8}, /* cost of storing MMX registers
251 in SImode and DImode */
252 2, /* cost of moving SSE register */
253 {4, 8, 16}, /* cost of loading SSE registers
254 in SImode, DImode and TImode */
255 {4, 8, 16}, /* cost of storing SSE registers
256 in SImode, DImode and TImode */
257 3, /* MMX or SSE register to integer */
258 4, /* size of l1 cache. 486 has 8kB cache
259 shared for code and data, so 4kB is
260 not really precise. */
261 4, /* size of l2 cache */
262 0, /* size of prefetch block */
263 0, /* number of parallel prefetches */
265 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
266 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
267 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
268 COSTS_N_INSNS (3), /* cost of FABS instruction. */
269 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
270 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
271 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
272 DUMMY_STRINGOP_ALGS},
273 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
274 DUMMY_STRINGOP_ALGS},
275 1, /* scalar_stmt_cost. */
276 1, /* scalar load_cost. */
277 1, /* scalar_store_cost. */
278 1, /* vec_stmt_cost. */
279 1, /* vec_to_scalar_cost. */
280 1, /* scalar_to_vec_cost. */
281 1, /* vec_align_load_cost. */
282 2, /* vec_unalign_load_cost. */
283 1, /* vec_store_cost. */
284 3, /* cond_taken_branch_cost. */
285 1, /* cond_not_taken_branch_cost. */
289 struct processor_costs pentium_cost = {
290 COSTS_N_INSNS (1), /* cost of an add instruction */
291 COSTS_N_INSNS (1), /* cost of a lea instruction */
292 COSTS_N_INSNS (4), /* variable shift costs */
293 COSTS_N_INSNS (1), /* constant shift costs */
294 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
295 COSTS_N_INSNS (11), /* HI */
296 COSTS_N_INSNS (11), /* SI */
297 COSTS_N_INSNS (11), /* DI */
298 COSTS_N_INSNS (11)}, /* other */
299 0, /* cost of multiply per each bit set */
300 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
301 COSTS_N_INSNS (25), /* HI */
302 COSTS_N_INSNS (25), /* SI */
303 COSTS_N_INSNS (25), /* DI */
304 COSTS_N_INSNS (25)}, /* other */
305 COSTS_N_INSNS (3), /* cost of movsx */
306 COSTS_N_INSNS (2), /* cost of movzx */
307 8, /* "large" insn */
309 6, /* cost for loading QImode using movzbl */
310 {2, 4, 2}, /* cost of loading integer registers
311 in QImode, HImode and SImode.
312 Relative to reg-reg move (2). */
313 {2, 4, 2}, /* cost of storing integer registers */
314 2, /* cost of reg,reg fld/fst */
315 {2, 2, 6}, /* cost of loading fp registers
316 in SFmode, DFmode and XFmode */
317 {4, 4, 6}, /* cost of storing fp registers
318 in SFmode, DFmode and XFmode */
319 8, /* cost of moving MMX register */
320 {8, 8}, /* cost of loading MMX registers
321 in SImode and DImode */
322 {8, 8}, /* cost of storing MMX registers
323 in SImode and DImode */
324 2, /* cost of moving SSE register */
325 {4, 8, 16}, /* cost of loading SSE registers
326 in SImode, DImode and TImode */
327 {4, 8, 16}, /* cost of storing SSE registers
328 in SImode, DImode and TImode */
329 3, /* MMX or SSE register to integer */
330 8, /* size of l1 cache. */
331 8, /* size of l2 cache */
332 0, /* size of prefetch block */
333 0, /* number of parallel prefetches */
335 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
336 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
337 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
338 COSTS_N_INSNS (1), /* cost of FABS instruction. */
339 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
340 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
341 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
342 DUMMY_STRINGOP_ALGS},
343 {{libcall, {{-1, rep_prefix_4_byte}}},
344 DUMMY_STRINGOP_ALGS},
345 1, /* scalar_stmt_cost. */
346 1, /* scalar load_cost. */
347 1, /* scalar_store_cost. */
348 1, /* vec_stmt_cost. */
349 1, /* vec_to_scalar_cost. */
350 1, /* scalar_to_vec_cost. */
351 1, /* vec_align_load_cost. */
352 2, /* vec_unalign_load_cost. */
353 1, /* vec_store_cost. */
354 3, /* cond_taken_branch_cost. */
355 1, /* cond_not_taken_branch_cost. */
359 struct processor_costs pentiumpro_cost = {
360 COSTS_N_INSNS (1), /* cost of an add instruction */
361 COSTS_N_INSNS (1), /* cost of a lea instruction */
362 COSTS_N_INSNS (1), /* variable shift costs */
363 COSTS_N_INSNS (1), /* constant shift costs */
364 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
365 COSTS_N_INSNS (4), /* HI */
366 COSTS_N_INSNS (4), /* SI */
367 COSTS_N_INSNS (4), /* DI */
368 COSTS_N_INSNS (4)}, /* other */
369 0, /* cost of multiply per each bit set */
370 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
371 COSTS_N_INSNS (17), /* HI */
372 COSTS_N_INSNS (17), /* SI */
373 COSTS_N_INSNS (17), /* DI */
374 COSTS_N_INSNS (17)}, /* other */
375 COSTS_N_INSNS (1), /* cost of movsx */
376 COSTS_N_INSNS (1), /* cost of movzx */
377 8, /* "large" insn */
379 2, /* cost for loading QImode using movzbl */
380 {4, 4, 4}, /* cost of loading integer registers
381 in QImode, HImode and SImode.
382 Relative to reg-reg move (2). */
383 {2, 2, 2}, /* cost of storing integer registers */
384 2, /* cost of reg,reg fld/fst */
385 {2, 2, 6}, /* cost of loading fp registers
386 in SFmode, DFmode and XFmode */
387 {4, 4, 6}, /* cost of storing fp registers
388 in SFmode, DFmode and XFmode */
389 2, /* cost of moving MMX register */
390 {2, 2}, /* cost of loading MMX registers
391 in SImode and DImode */
392 {2, 2}, /* cost of storing MMX registers
393 in SImode and DImode */
394 2, /* cost of moving SSE register */
395 {2, 2, 8}, /* cost of loading SSE registers
396 in SImode, DImode and TImode */
397 {2, 2, 8}, /* cost of storing SSE registers
398 in SImode, DImode and TImode */
399 3, /* MMX or SSE register to integer */
400 8, /* size of l1 cache. */
401 256, /* size of l2 cache */
402 32, /* size of prefetch block */
403 6, /* number of parallel prefetches */
405 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
406 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
407 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
408 COSTS_N_INSNS (2), /* cost of FABS instruction. */
409 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
410 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
411 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
412 the alignment). For small blocks inline loop is still a noticeable win, for bigger
413 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
414 more expensive startup time in CPU, but after 4K the difference is down in the noise.
416 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
417 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
418 DUMMY_STRINGOP_ALGS},
419 {{rep_prefix_4_byte, {{1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, libcall}}},
421 DUMMY_STRINGOP_ALGS},
422 1, /* scalar_stmt_cost. */
423 1, /* scalar load_cost. */
424 1, /* scalar_store_cost. */
425 1, /* vec_stmt_cost. */
426 1, /* vec_to_scalar_cost. */
427 1, /* scalar_to_vec_cost. */
428 1, /* vec_align_load_cost. */
429 2, /* vec_unalign_load_cost. */
430 1, /* vec_store_cost. */
431 3, /* cond_taken_branch_cost. */
432 1, /* cond_not_taken_branch_cost. */
436 struct processor_costs geode_cost = {
437 COSTS_N_INSNS (1), /* cost of an add instruction */
438 COSTS_N_INSNS (1), /* cost of a lea instruction */
439 COSTS_N_INSNS (2), /* variable shift costs */
440 COSTS_N_INSNS (1), /* constant shift costs */
441 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
442 COSTS_N_INSNS (4), /* HI */
443 COSTS_N_INSNS (7), /* SI */
444 COSTS_N_INSNS (7), /* DI */
445 COSTS_N_INSNS (7)}, /* other */
446 0, /* cost of multiply per each bit set */
447 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
448 COSTS_N_INSNS (23), /* HI */
449 COSTS_N_INSNS (39), /* SI */
450 COSTS_N_INSNS (39), /* DI */
451 COSTS_N_INSNS (39)}, /* other */
452 COSTS_N_INSNS (1), /* cost of movsx */
453 COSTS_N_INSNS (1), /* cost of movzx */
454 8, /* "large" insn */
456 1, /* cost for loading QImode using movzbl */
457 {1, 1, 1}, /* cost of loading integer registers
458 in QImode, HImode and SImode.
459 Relative to reg-reg move (2). */
460 {1, 1, 1}, /* cost of storing integer registers */
461 1, /* cost of reg,reg fld/fst */
462 {1, 1, 1}, /* cost of loading fp registers
463 in SFmode, DFmode and XFmode */
464 {4, 6, 6}, /* cost of storing fp registers
465 in SFmode, DFmode and XFmode */
467 1, /* cost of moving MMX register */
468 {1, 1}, /* cost of loading MMX registers
469 in SImode and DImode */
470 {1, 1}, /* cost of storing MMX registers
471 in SImode and DImode */
472 1, /* cost of moving SSE register */
473 {1, 1, 1}, /* cost of loading SSE registers
474 in SImode, DImode and TImode */
475 {1, 1, 1}, /* cost of storing SSE registers
476 in SImode, DImode and TImode */
477 1, /* MMX or SSE register to integer */
478 64, /* size of l1 cache. */
479 128, /* size of l2 cache. */
480 32, /* size of prefetch block */
481 1, /* number of parallel prefetches */
483 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
484 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
485 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
486 COSTS_N_INSNS (1), /* cost of FABS instruction. */
487 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
488 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
489 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
490 DUMMY_STRINGOP_ALGS},
491 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
492 DUMMY_STRINGOP_ALGS},
493 1, /* scalar_stmt_cost. */
494 1, /* scalar load_cost. */
495 1, /* scalar_store_cost. */
496 1, /* vec_stmt_cost. */
497 1, /* vec_to_scalar_cost. */
498 1, /* scalar_to_vec_cost. */
499 1, /* vec_align_load_cost. */
500 2, /* vec_unalign_load_cost. */
501 1, /* vec_store_cost. */
502 3, /* cond_taken_branch_cost. */
503 1, /* cond_not_taken_branch_cost. */
507 struct processor_costs k6_cost = {
508 COSTS_N_INSNS (1), /* cost of an add instruction */
509 COSTS_N_INSNS (2), /* cost of a lea instruction */
510 COSTS_N_INSNS (1), /* variable shift costs */
511 COSTS_N_INSNS (1), /* constant shift costs */
512 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
513 COSTS_N_INSNS (3), /* HI */
514 COSTS_N_INSNS (3), /* SI */
515 COSTS_N_INSNS (3), /* DI */
516 COSTS_N_INSNS (3)}, /* other */
517 0, /* cost of multiply per each bit set */
518 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
519 COSTS_N_INSNS (18), /* HI */
520 COSTS_N_INSNS (18), /* SI */
521 COSTS_N_INSNS (18), /* DI */
522 COSTS_N_INSNS (18)}, /* other */
523 COSTS_N_INSNS (2), /* cost of movsx */
524 COSTS_N_INSNS (2), /* cost of movzx */
525 8, /* "large" insn */
527 3, /* cost for loading QImode using movzbl */
528 {4, 5, 4}, /* cost of loading integer registers
529 in QImode, HImode and SImode.
530 Relative to reg-reg move (2). */
531 {2, 3, 2}, /* cost of storing integer registers */
532 4, /* cost of reg,reg fld/fst */
533 {6, 6, 6}, /* cost of loading fp registers
534 in SFmode, DFmode and XFmode */
535 {4, 4, 4}, /* cost of storing fp registers
536 in SFmode, DFmode and XFmode */
537 2, /* cost of moving MMX register */
538 {2, 2}, /* cost of loading MMX registers
539 in SImode and DImode */
540 {2, 2}, /* cost of storing MMX registers
541 in SImode and DImode */
542 2, /* cost of moving SSE register */
543 {2, 2, 8}, /* cost of loading SSE registers
544 in SImode, DImode and TImode */
545 {2, 2, 8}, /* cost of storing SSE registers
546 in SImode, DImode and TImode */
547 6, /* MMX or SSE register to integer */
548 32, /* size of l1 cache. */
549 32, /* size of l2 cache. Some models
550 have integrated l2 cache, but
551 optimizing for k6 is not important
552 enough to worry about that. */
553 32, /* size of prefetch block */
554 1, /* number of parallel prefetches */
556 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
557 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
558 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
559 COSTS_N_INSNS (2), /* cost of FABS instruction. */
560 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
561 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
562 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
563 DUMMY_STRINGOP_ALGS},
564 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
565 DUMMY_STRINGOP_ALGS},
566 1, /* scalar_stmt_cost. */
567 1, /* scalar load_cost. */
568 1, /* scalar_store_cost. */
569 1, /* vec_stmt_cost. */
570 1, /* vec_to_scalar_cost. */
571 1, /* scalar_to_vec_cost. */
572 1, /* vec_align_load_cost. */
573 2, /* vec_unalign_load_cost. */
574 1, /* vec_store_cost. */
575 3, /* cond_taken_branch_cost. */
576 1, /* cond_not_taken_branch_cost. */
580 struct processor_costs athlon_cost = {
581 COSTS_N_INSNS (1), /* cost of an add instruction */
582 COSTS_N_INSNS (2), /* cost of a lea instruction */
583 COSTS_N_INSNS (1), /* variable shift costs */
584 COSTS_N_INSNS (1), /* constant shift costs */
585 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
586 COSTS_N_INSNS (5), /* HI */
587 COSTS_N_INSNS (5), /* SI */
588 COSTS_N_INSNS (5), /* DI */
589 COSTS_N_INSNS (5)}, /* other */
590 0, /* cost of multiply per each bit set */
591 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
592 COSTS_N_INSNS (26), /* HI */
593 COSTS_N_INSNS (42), /* SI */
594 COSTS_N_INSNS (74), /* DI */
595 COSTS_N_INSNS (74)}, /* other */
596 COSTS_N_INSNS (1), /* cost of movsx */
597 COSTS_N_INSNS (1), /* cost of movzx */
598 8, /* "large" insn */
600 4, /* cost for loading QImode using movzbl */
601 {3, 4, 3}, /* cost of loading integer registers
602 in QImode, HImode and SImode.
603 Relative to reg-reg move (2). */
604 {3, 4, 3}, /* cost of storing integer registers */
605 4, /* cost of reg,reg fld/fst */
606 {4, 4, 12}, /* cost of loading fp registers
607 in SFmode, DFmode and XFmode */
608 {6, 6, 8}, /* cost of storing fp registers
609 in SFmode, DFmode and XFmode */
610 2, /* cost of moving MMX register */
611 {4, 4}, /* cost of loading MMX registers
612 in SImode and DImode */
613 {4, 4}, /* cost of storing MMX registers
614 in SImode and DImode */
615 2, /* cost of moving SSE register */
616 {4, 4, 6}, /* cost of loading SSE registers
617 in SImode, DImode and TImode */
618 {4, 4, 5}, /* cost of storing SSE registers
619 in SImode, DImode and TImode */
620 5, /* MMX or SSE register to integer */
621 64, /* size of l1 cache. */
622 256, /* size of l2 cache. */
623 64, /* size of prefetch block */
624 6, /* number of parallel prefetches */
626 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
627 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
628 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
629 COSTS_N_INSNS (2), /* cost of FABS instruction. */
630 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
631 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
632 /* For some reason, Athlon deals better with REP prefix (relative to loops)
633 compared to K8. Alignment becomes important after 8 bytes for memcpy and
634 128 bytes for memset. */
635 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
636 DUMMY_STRINGOP_ALGS},
637 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
638 DUMMY_STRINGOP_ALGS},
639 1, /* scalar_stmt_cost. */
640 1, /* scalar load_cost. */
641 1, /* scalar_store_cost. */
642 1, /* vec_stmt_cost. */
643 1, /* vec_to_scalar_cost. */
644 1, /* scalar_to_vec_cost. */
645 1, /* vec_align_load_cost. */
646 2, /* vec_unalign_load_cost. */
647 1, /* vec_store_cost. */
648 3, /* cond_taken_branch_cost. */
649 1, /* cond_not_taken_branch_cost. */
653 struct processor_costs k8_cost = {
654 COSTS_N_INSNS (1), /* cost of an add instruction */
655 COSTS_N_INSNS (2), /* cost of a lea instruction */
656 COSTS_N_INSNS (1), /* variable shift costs */
657 COSTS_N_INSNS (1), /* constant shift costs */
658 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
659 COSTS_N_INSNS (4), /* HI */
660 COSTS_N_INSNS (3), /* SI */
661 COSTS_N_INSNS (4), /* DI */
662 COSTS_N_INSNS (5)}, /* other */
663 0, /* cost of multiply per each bit set */
664 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
665 COSTS_N_INSNS (26), /* HI */
666 COSTS_N_INSNS (42), /* SI */
667 COSTS_N_INSNS (74), /* DI */
668 COSTS_N_INSNS (74)}, /* other */
669 COSTS_N_INSNS (1), /* cost of movsx */
670 COSTS_N_INSNS (1), /* cost of movzx */
671 8, /* "large" insn */
673 4, /* cost for loading QImode using movzbl */
674 {3, 4, 3}, /* cost of loading integer registers
675 in QImode, HImode and SImode.
676 Relative to reg-reg move (2). */
677 {3, 4, 3}, /* cost of storing integer registers */
678 4, /* cost of reg,reg fld/fst */
679 {4, 4, 12}, /* cost of loading fp registers
680 in SFmode, DFmode and XFmode */
681 {6, 6, 8}, /* cost of storing fp registers
682 in SFmode, DFmode and XFmode */
683 2, /* cost of moving MMX register */
684 {3, 3}, /* cost of loading MMX registers
685 in SImode and DImode */
686 {4, 4}, /* cost of storing MMX registers
687 in SImode and DImode */
688 2, /* cost of moving SSE register */
689 {4, 3, 6}, /* cost of loading SSE registers
690 in SImode, DImode and TImode */
691 {4, 4, 5}, /* cost of storing SSE registers
692 in SImode, DImode and TImode */
693 5, /* MMX or SSE register to integer */
694 64, /* size of l1 cache. */
695 512, /* size of l2 cache. */
696 64, /* size of prefetch block */
697 /* New AMD processors never drop prefetches; if they cannot be performed
698 immediately, they are queued. We set number of simultaneous prefetches
699 to a large constant to reflect this (it probably is not a good idea not
700 to limit number of prefetches at all, as their execution also takes some
702 100, /* number of parallel prefetches */
704 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
705 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
706 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
707 COSTS_N_INSNS (2), /* cost of FABS instruction. */
708 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
709 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
710 /* K8 has optimized REP instruction for medium sized blocks, but for very small
711 blocks it is better to use loop. For large blocks, libcall can do
712 nontemporary accesses and beat inline considerably. */
713 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
714 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
715 {{libcall, {{8, loop}, {24, unrolled_loop},
716 {2048, rep_prefix_4_byte}, {-1, libcall}}},
717 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 4, /* scalar_stmt_cost. */
719 2, /* scalar load_cost. */
720 2, /* scalar_store_cost. */
721 5, /* vec_stmt_cost. */
722 0, /* vec_to_scalar_cost. */
723 2, /* scalar_to_vec_cost. */
724 2, /* vec_align_load_cost. */
725 3, /* vec_unalign_load_cost. */
726 3, /* vec_store_cost. */
727 6, /* cond_taken_branch_cost. */
728 1, /* cond_not_taken_branch_cost. */
731 struct processor_costs amdfam10_cost = {
732 COSTS_N_INSNS (1), /* cost of an add instruction */
733 COSTS_N_INSNS (2), /* cost of a lea instruction */
734 COSTS_N_INSNS (1), /* variable shift costs */
735 COSTS_N_INSNS (1), /* constant shift costs */
736 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
737 COSTS_N_INSNS (4), /* HI */
738 COSTS_N_INSNS (3), /* SI */
739 COSTS_N_INSNS (4), /* DI */
740 COSTS_N_INSNS (5)}, /* other */
741 0, /* cost of multiply per each bit set */
742 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
743 COSTS_N_INSNS (35), /* HI */
744 COSTS_N_INSNS (51), /* SI */
745 COSTS_N_INSNS (83), /* DI */
746 COSTS_N_INSNS (83)}, /* other */
747 COSTS_N_INSNS (1), /* cost of movsx */
748 COSTS_N_INSNS (1), /* cost of movzx */
749 8, /* "large" insn */
751 4, /* cost for loading QImode using movzbl */
752 {3, 4, 3}, /* cost of loading integer registers
753 in QImode, HImode and SImode.
754 Relative to reg-reg move (2). */
755 {3, 4, 3}, /* cost of storing integer registers */
756 4, /* cost of reg,reg fld/fst */
757 {4, 4, 12}, /* cost of loading fp registers
758 in SFmode, DFmode and XFmode */
759 {6, 6, 8}, /* cost of storing fp registers
760 in SFmode, DFmode and XFmode */
761 2, /* cost of moving MMX register */
762 {3, 3}, /* cost of loading MMX registers
763 in SImode and DImode */
764 {4, 4}, /* cost of storing MMX registers
765 in SImode and DImode */
766 2, /* cost of moving SSE register */
767 {4, 4, 3}, /* cost of loading SSE registers
768 in SImode, DImode and TImode */
769 {4, 4, 5}, /* cost of storing SSE registers
770 in SImode, DImode and TImode */
771 3, /* MMX or SSE register to integer */
773 MOVD reg64, xmmreg Double FSTORE 4
774 MOVD reg32, xmmreg Double FSTORE 4
776 MOVD reg64, xmmreg Double FADD 3
778 MOVD reg32, xmmreg Double FADD 3
780 64, /* size of l1 cache. */
781 512, /* size of l2 cache. */
782 64, /* size of prefetch block */
783 /* New AMD processors never drop prefetches; if they cannot be performed
784 immediately, they are queued. We set number of simultaneous prefetches
785 to a large constant to reflect this (it probably is not a good idea not
786 to limit number of prefetches at all, as their execution also takes some
788 100, /* number of parallel prefetches */
790 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
791 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
792 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
793 COSTS_N_INSNS (2), /* cost of FABS instruction. */
794 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
795 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
797 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
798 very small blocks it is better to use loop. For large blocks, libcall can
799 do nontemporary accesses and beat inline considerably. */
800 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
801 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
802 {{libcall, {{8, loop}, {24, unrolled_loop},
803 {2048, rep_prefix_4_byte}, {-1, libcall}}},
804 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 4, /* scalar_stmt_cost. */
806 2, /* scalar load_cost. */
807 2, /* scalar_store_cost. */
808 6, /* vec_stmt_cost. */
809 0, /* vec_to_scalar_cost. */
810 2, /* scalar_to_vec_cost. */
811 2, /* vec_align_load_cost. */
812 2, /* vec_unalign_load_cost. */
813 2, /* vec_store_cost. */
814 6, /* cond_taken_branch_cost. */
815 1, /* cond_not_taken_branch_cost. */
819 struct processor_costs pentium4_cost = {
820 COSTS_N_INSNS (1), /* cost of an add instruction */
821 COSTS_N_INSNS (3), /* cost of a lea instruction */
822 COSTS_N_INSNS (4), /* variable shift costs */
823 COSTS_N_INSNS (4), /* constant shift costs */
824 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
825 COSTS_N_INSNS (15), /* HI */
826 COSTS_N_INSNS (15), /* SI */
827 COSTS_N_INSNS (15), /* DI */
828 COSTS_N_INSNS (15)}, /* other */
829 0, /* cost of multiply per each bit set */
830 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
831 COSTS_N_INSNS (56), /* HI */
832 COSTS_N_INSNS (56), /* SI */
833 COSTS_N_INSNS (56), /* DI */
834 COSTS_N_INSNS (56)}, /* other */
835 COSTS_N_INSNS (1), /* cost of movsx */
836 COSTS_N_INSNS (1), /* cost of movzx */
837 16, /* "large" insn */
839 2, /* cost for loading QImode using movzbl */
840 {4, 5, 4}, /* cost of loading integer registers
841 in QImode, HImode and SImode.
842 Relative to reg-reg move (2). */
843 {2, 3, 2}, /* cost of storing integer registers */
844 2, /* cost of reg,reg fld/fst */
845 {2, 2, 6}, /* cost of loading fp registers
846 in SFmode, DFmode and XFmode */
847 {4, 4, 6}, /* cost of storing fp registers
848 in SFmode, DFmode and XFmode */
849 2, /* cost of moving MMX register */
850 {2, 2}, /* cost of loading MMX registers
851 in SImode and DImode */
852 {2, 2}, /* cost of storing MMX registers
853 in SImode and DImode */
854 12, /* cost of moving SSE register */
855 {12, 12, 12}, /* cost of loading SSE registers
856 in SImode, DImode and TImode */
857 {2, 2, 8}, /* cost of storing SSE registers
858 in SImode, DImode and TImode */
859 10, /* MMX or SSE register to integer */
860 8, /* size of l1 cache. */
861 256, /* size of l2 cache. */
862 64, /* size of prefetch block */
863 6, /* number of parallel prefetches */
865 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
866 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
867 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
868 COSTS_N_INSNS (2), /* cost of FABS instruction. */
869 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
870 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
871 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
872 DUMMY_STRINGOP_ALGS},
873 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
875 DUMMY_STRINGOP_ALGS},
876 1, /* scalar_stmt_cost. */
877 1, /* scalar load_cost. */
878 1, /* scalar_store_cost. */
879 1, /* vec_stmt_cost. */
880 1, /* vec_to_scalar_cost. */
881 1, /* scalar_to_vec_cost. */
882 1, /* vec_align_load_cost. */
883 2, /* vec_unalign_load_cost. */
884 1, /* vec_store_cost. */
885 3, /* cond_taken_branch_cost. */
886 1, /* cond_not_taken_branch_cost. */
890 struct processor_costs nocona_cost = {
891 COSTS_N_INSNS (1), /* cost of an add instruction */
892 COSTS_N_INSNS (1), /* cost of a lea instruction */
893 COSTS_N_INSNS (1), /* variable shift costs */
894 COSTS_N_INSNS (1), /* constant shift costs */
895 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
896 COSTS_N_INSNS (10), /* HI */
897 COSTS_N_INSNS (10), /* SI */
898 COSTS_N_INSNS (10), /* DI */
899 COSTS_N_INSNS (10)}, /* other */
900 0, /* cost of multiply per each bit set */
901 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
902 COSTS_N_INSNS (66), /* HI */
903 COSTS_N_INSNS (66), /* SI */
904 COSTS_N_INSNS (66), /* DI */
905 COSTS_N_INSNS (66)}, /* other */
906 COSTS_N_INSNS (1), /* cost of movsx */
907 COSTS_N_INSNS (1), /* cost of movzx */
908 16, /* "large" insn */
910 4, /* cost for loading QImode using movzbl */
911 {4, 4, 4}, /* cost of loading integer registers
912 in QImode, HImode and SImode.
913 Relative to reg-reg move (2). */
914 {4, 4, 4}, /* cost of storing integer registers */
915 3, /* cost of reg,reg fld/fst */
916 {12, 12, 12}, /* cost of loading fp registers
917 in SFmode, DFmode and XFmode */
918 {4, 4, 4}, /* cost of storing fp registers
919 in SFmode, DFmode and XFmode */
920 6, /* cost of moving MMX register */
921 {12, 12}, /* cost of loading MMX registers
922 in SImode and DImode */
923 {12, 12}, /* cost of storing MMX registers
924 in SImode and DImode */
925 6, /* cost of moving SSE register */
926 {12, 12, 12}, /* cost of loading SSE registers
927 in SImode, DImode and TImode */
928 {12, 12, 12}, /* cost of storing SSE registers
929 in SImode, DImode and TImode */
930 8, /* MMX or SSE register to integer */
931 8, /* size of l1 cache. */
932 1024, /* size of l2 cache. */
933 128, /* size of prefetch block */
934 8, /* number of parallel prefetches */
936 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
937 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
938 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
939 COSTS_N_INSNS (3), /* cost of FABS instruction. */
940 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
941 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
942 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
943 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
944 {100000, unrolled_loop}, {-1, libcall}}}},
945 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
947 {libcall, {{24, loop}, {64, unrolled_loop},
948 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
949 1, /* scalar_stmt_cost. */
950 1, /* scalar load_cost. */
951 1, /* scalar_store_cost. */
952 1, /* vec_stmt_cost. */
953 1, /* vec_to_scalar_cost. */
954 1, /* scalar_to_vec_cost. */
955 1, /* vec_align_load_cost. */
956 2, /* vec_unalign_load_cost. */
957 1, /* vec_store_cost. */
958 3, /* cond_taken_branch_cost. */
959 1, /* cond_not_taken_branch_cost. */
963 struct processor_costs core2_cost = {
964 COSTS_N_INSNS (1), /* cost of an add instruction */
965 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
966 COSTS_N_INSNS (1), /* variable shift costs */
967 COSTS_N_INSNS (1), /* constant shift costs */
968 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
969 COSTS_N_INSNS (3), /* HI */
970 COSTS_N_INSNS (3), /* SI */
971 COSTS_N_INSNS (3), /* DI */
972 COSTS_N_INSNS (3)}, /* other */
973 0, /* cost of multiply per each bit set */
974 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
975 COSTS_N_INSNS (22), /* HI */
976 COSTS_N_INSNS (22), /* SI */
977 COSTS_N_INSNS (22), /* DI */
978 COSTS_N_INSNS (22)}, /* other */
979 COSTS_N_INSNS (1), /* cost of movsx */
980 COSTS_N_INSNS (1), /* cost of movzx */
981 8, /* "large" insn */
983 2, /* cost for loading QImode using movzbl */
984 {6, 6, 6}, /* cost of loading integer registers
985 in QImode, HImode and SImode.
986 Relative to reg-reg move (2). */
987 {4, 4, 4}, /* cost of storing integer registers */
988 2, /* cost of reg,reg fld/fst */
989 {6, 6, 6}, /* cost of loading fp registers
990 in SFmode, DFmode and XFmode */
991 {4, 4, 4}, /* cost of loading integer registers */
992 2, /* cost of moving MMX register */
993 {6, 6}, /* cost of loading MMX registers
994 in SImode and DImode */
995 {4, 4}, /* cost of storing MMX registers
996 in SImode and DImode */
997 2, /* cost of moving SSE register */
998 {6, 6, 6}, /* cost of loading SSE registers
999 in SImode, DImode and TImode */
1000 {4, 4, 4}, /* cost of storing SSE registers
1001 in SImode, DImode and TImode */
1002 2, /* MMX or SSE register to integer */
1003 32, /* size of l1 cache. */
1004 2048, /* size of l2 cache. */
1005 128, /* size of prefetch block */
1006 8, /* number of parallel prefetches */
1007 3, /* Branch cost */
1008 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1009 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1010 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1011 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1012 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1013 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1014 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1015 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1016 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1017 {{libcall, {{8, loop}, {15, unrolled_loop},
1018 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1019 {libcall, {{24, loop}, {32, unrolled_loop},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 1, /* scalar_stmt_cost. */
1022 1, /* scalar load_cost. */
1023 1, /* scalar_store_cost. */
1024 1, /* vec_stmt_cost. */
1025 1, /* vec_to_scalar_cost. */
1026 1, /* scalar_to_vec_cost. */
1027 1, /* vec_align_load_cost. */
1028 2, /* vec_unalign_load_cost. */
1029 1, /* vec_store_cost. */
1030 3, /* cond_taken_branch_cost. */
1031 1, /* cond_not_taken_branch_cost. */
1034 /* Generic64 should produce code tuned for Nocona and K8. */
1036 struct processor_costs generic64_cost = {
1037 COSTS_N_INSNS (1), /* cost of an add instruction */
1038 /* On all chips taken into consideration lea is 2 cycles and more. With
1039 this cost however our current implementation of synth_mult results in
1040 use of unnecessary temporary registers causing regression on several
1041 SPECfp benchmarks. */
1042 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1043 COSTS_N_INSNS (1), /* variable shift costs */
1044 COSTS_N_INSNS (1), /* constant shift costs */
1045 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1046 COSTS_N_INSNS (4), /* HI */
1047 COSTS_N_INSNS (3), /* SI */
1048 COSTS_N_INSNS (4), /* DI */
1049 COSTS_N_INSNS (2)}, /* other */
1050 0, /* cost of multiply per each bit set */
1051 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1052 COSTS_N_INSNS (26), /* HI */
1053 COSTS_N_INSNS (42), /* SI */
1054 COSTS_N_INSNS (74), /* DI */
1055 COSTS_N_INSNS (74)}, /* other */
1056 COSTS_N_INSNS (1), /* cost of movsx */
1057 COSTS_N_INSNS (1), /* cost of movzx */
1058 8, /* "large" insn */
1059 17, /* MOVE_RATIO */
1060 4, /* cost for loading QImode using movzbl */
1061 {4, 4, 4}, /* cost of loading integer registers
1062 in QImode, HImode and SImode.
1063 Relative to reg-reg move (2). */
1064 {4, 4, 4}, /* cost of storing integer registers */
1065 4, /* cost of reg,reg fld/fst */
1066 {12, 12, 12}, /* cost of loading fp registers
1067 in SFmode, DFmode and XFmode */
1068 {6, 6, 8}, /* cost of storing fp registers
1069 in SFmode, DFmode and XFmode */
1070 2, /* cost of moving MMX register */
1071 {8, 8}, /* cost of loading MMX registers
1072 in SImode and DImode */
1073 {8, 8}, /* cost of storing MMX registers
1074 in SImode and DImode */
1075 2, /* cost of moving SSE register */
1076 {8, 8, 8}, /* cost of loading SSE registers
1077 in SImode, DImode and TImode */
1078 {8, 8, 8}, /* cost of storing SSE registers
1079 in SImode, DImode and TImode */
1080 5, /* MMX or SSE register to integer */
1081 32, /* size of l1 cache. */
1082 512, /* size of l2 cache. */
1083 64, /* size of prefetch block */
1084 6, /* number of parallel prefetches */
1085 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1086 is increased to perhaps more appropriate value of 5. */
1087 3, /* Branch cost */
1088 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1089 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1090 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1091 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1092 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1093 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1094 {DUMMY_STRINGOP_ALGS,
1095 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1096 {DUMMY_STRINGOP_ALGS,
1097 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1113 struct processor_costs generic32_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1116 COSTS_N_INSNS (1), /* variable shift costs */
1117 COSTS_N_INSNS (1), /* constant shift costs */
1118 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1119 COSTS_N_INSNS (4), /* HI */
1120 COSTS_N_INSNS (3), /* SI */
1121 COSTS_N_INSNS (4), /* DI */
1122 COSTS_N_INSNS (2)}, /* other */
1123 0, /* cost of multiply per each bit set */
1124 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1125 COSTS_N_INSNS (26), /* HI */
1126 COSTS_N_INSNS (42), /* SI */
1127 COSTS_N_INSNS (74), /* DI */
1128 COSTS_N_INSNS (74)}, /* other */
1129 COSTS_N_INSNS (1), /* cost of movsx */
1130 COSTS_N_INSNS (1), /* cost of movzx */
1131 8, /* "large" insn */
1132 17, /* MOVE_RATIO */
1133 4, /* cost for loading QImode using movzbl */
1134 {4, 4, 4}, /* cost of loading integer registers
1135 in QImode, HImode and SImode.
1136 Relative to reg-reg move (2). */
1137 {4, 4, 4}, /* cost of storing integer registers */
1138 4, /* cost of reg,reg fld/fst */
1139 {12, 12, 12}, /* cost of loading fp registers
1140 in SFmode, DFmode and XFmode */
1141 {6, 6, 8}, /* cost of storing fp registers
1142 in SFmode, DFmode and XFmode */
1143 2, /* cost of moving MMX register */
1144 {8, 8}, /* cost of loading MMX registers
1145 in SImode and DImode */
1146 {8, 8}, /* cost of storing MMX registers
1147 in SImode and DImode */
1148 2, /* cost of moving SSE register */
1149 {8, 8, 8}, /* cost of loading SSE registers
1150 in SImode, DImode and TImode */
1151 {8, 8, 8}, /* cost of storing SSE registers
1152 in SImode, DImode and TImode */
1153 5, /* MMX or SSE register to integer */
1154 32, /* size of l1 cache. */
1155 256, /* size of l2 cache. */
1156 64, /* size of prefetch block */
1157 6, /* number of parallel prefetches */
1158 3, /* Branch cost */
1159 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1160 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1161 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1162 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1163 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1164 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1165 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1166 DUMMY_STRINGOP_ALGS},
1167 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1168 DUMMY_STRINGOP_ALGS},
1169 1, /* scalar_stmt_cost. */
1170 1, /* scalar load_cost. */
1171 1, /* scalar_store_cost. */
1172 1, /* vec_stmt_cost. */
1173 1, /* vec_to_scalar_cost. */
1174 1, /* scalar_to_vec_cost. */
1175 1, /* vec_align_load_cost. */
1176 2, /* vec_unalign_load_cost. */
1177 1, /* vec_store_cost. */
1178 3, /* cond_taken_branch_cost. */
1179 1, /* cond_not_taken_branch_cost. */
1182 const struct processor_costs *ix86_cost = &pentium_cost;
1184 /* Processor feature/optimization bitmasks. */
1185 #define m_386 (1<<PROCESSOR_I386)
1186 #define m_486 (1<<PROCESSOR_I486)
1187 #define m_PENT (1<<PROCESSOR_PENTIUM)
1188 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1189 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1190 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1191 #define m_CORE2 (1<<PROCESSOR_CORE2)
1193 #define m_GEODE (1<<PROCESSOR_GEODE)
1194 #define m_K6 (1<<PROCESSOR_K6)
1195 #define m_K6_GEODE (m_K6 | m_GEODE)
1196 #define m_K8 (1<<PROCESSOR_K8)
1197 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1198 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1199 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1200 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1202 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1203 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1205 /* Generic instruction choice should be common subset of supported CPUs
1206 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1207 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1209 /* Feature tests against the various tunings. */
1210 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1211 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1212 negatively, so enabling for Generic64 seems like good code size
1213 tradeoff. We can't enable it for 32bit generic because it does not
1214 work well with PPro base chips. */
1215 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1217 /* X86_TUNE_PUSH_MEMORY */
1218 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1219 | m_NOCONA | m_CORE2 | m_GENERIC,
1221 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1224 /* X86_TUNE_USE_BIT_TEST */
1227 /* X86_TUNE_UNROLL_STRLEN */
1228 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1231 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1233 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1234 on simulation result. But after P4 was made, no performance benefit
1235 was observed with branch hints. It also increases the code size.
1236 As a result, icc never generates branch hints. */
1239 /* X86_TUNE_DOUBLE_WITH_ADD */
1242 /* X86_TUNE_USE_SAHF */
1243 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1244 | m_NOCONA | m_CORE2 | m_GENERIC,
1246 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1247 partial dependencies. */
1248 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1249 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1251 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1252 register stalls on Generic32 compilation setting as well. However
1253 in current implementation the partial register stalls are not eliminated
1254 very well - they can be introduced via subregs synthesized by combine
1255 and can happen in caller/callee saving sequences. Because this option
1256 pays back little on PPro based chips and is in conflict with partial reg
1257 dependencies used by Athlon/P4 based chips, it is better to leave it off
1258 for generic32 for now. */
1261 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1262 m_CORE2 | m_GENERIC,
1264 /* X86_TUNE_USE_HIMODE_FIOP */
1265 m_386 | m_486 | m_K6_GEODE,
1267 /* X86_TUNE_USE_SIMODE_FIOP */
1268 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1270 /* X86_TUNE_USE_MOV0 */
1273 /* X86_TUNE_USE_CLTD */
1274 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1279 /* X86_TUNE_SPLIT_LONG_MOVES */
1282 /* X86_TUNE_READ_MODIFY_WRITE */
1285 /* X86_TUNE_READ_MODIFY */
1288 /* X86_TUNE_PROMOTE_QIMODE */
1289 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1290 | m_GENERIC /* | m_PENT4 ? */,
1292 /* X86_TUNE_FAST_PREFIX */
1293 ~(m_PENT | m_486 | m_386),
1295 /* X86_TUNE_SINGLE_STRINGOP */
1296 m_386 | m_PENT4 | m_NOCONA,
1298 /* X86_TUNE_QIMODE_MATH */
1301 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1302 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1303 might be considered for Generic32 if our scheme for avoiding partial
1304 stalls was more effective. */
1307 /* X86_TUNE_PROMOTE_QI_REGS */
1310 /* X86_TUNE_PROMOTE_HI_REGS */
1313 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1314 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1316 /* X86_TUNE_ADD_ESP_8 */
1317 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1318 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1320 /* X86_TUNE_SUB_ESP_4 */
1321 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1323 /* X86_TUNE_SUB_ESP_8 */
1324 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1325 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1327 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1328 for DFmode copies */
1329 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1330 | m_GENERIC | m_GEODE),
1332 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1333 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1335 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1336 conflict here in between PPro/Pentium4 based chips that thread 128bit
1337 SSE registers as single units versus K8 based chips that divide SSE
1338 registers to two 64bit halves. This knob promotes all store destinations
1339 to be 128bit to allow register renaming on 128bit SSE units, but usually
1340 results in one extra microop on 64bit SSE units. Experimental results
1341 shows that disabling this option on P4 brings over 20% SPECfp regression,
1342 while enabling it on K8 brings roughly 2.4% regression that can be partly
1343 masked by careful scheduling of moves. */
1344 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1346 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1349 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1350 are resolved on SSE register parts instead of whole registers, so we may
1351 maintain just lower part of scalar values in proper format leaving the
1352 upper part undefined. */
1355 /* X86_TUNE_SSE_TYPELESS_STORES */
1358 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1359 m_PPRO | m_PENT4 | m_NOCONA,
1361 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1362 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1364 /* X86_TUNE_PROLOGUE_USING_MOVE */
1365 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1367 /* X86_TUNE_EPILOGUE_USING_MOVE */
1368 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_SHIFT1 */
1373 /* X86_TUNE_USE_FFREEP */
1376 /* X86_TUNE_INTER_UNIT_MOVES */
1377 ~(m_AMD_MULTIPLE | m_GENERIC),
1379 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1382 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1383 than 4 branch instructions in the 16 byte window. */
1384 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1386 /* X86_TUNE_SCHEDULE */
1387 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1389 /* X86_TUNE_USE_BT */
1392 /* X86_TUNE_USE_INCDEC */
1393 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1395 /* X86_TUNE_PAD_RETURNS */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_EXT_80387_CONSTANTS */
1399 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SHORTEN_X87_SSE */
1404 /* X86_TUNE_AVOID_VECTOR_DECODE */
1407 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1408 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1411 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1412 vector path on AMD machines. */
1413 m_K8 | m_GENERIC64 | m_AMDFAM10,
1415 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1417 m_K8 | m_GENERIC64 | m_AMDFAM10,
1419 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1423 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1424 but one byte longer. */
1427 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1428 operand that cannot be represented using a modRM byte. The XOR
1429 replacement is long decoded, so this split helps here as well. */
1432 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1433 from integer to FP. */
1437 /* Feature tests against the various architecture variations. */
1438 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1439 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1440 ~(m_386 | m_486 | m_PENT | m_K6),
1442 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1445 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1448 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1451 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1455 static const unsigned int x86_accumulate_outgoing_args
1456 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1458 static const unsigned int x86_arch_always_fancy_math_387
1459 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1460 | m_NOCONA | m_CORE2 | m_GENERIC;
1462 static enum stringop_alg stringop_alg = no_stringop;
1464 /* In case the average insn count for single function invocation is
1465 lower than this constant, emit fast (but longer) prologue and
1467 #define FAST_PROLOGUE_INSN_COUNT 20
1469 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1470 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1471 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1472 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1474 /* Array of the smallest class containing reg number REGNO, indexed by
1475 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1477 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1479 /* ax, dx, cx, bx */
1480 AREG, DREG, CREG, BREG,
1481 /* si, di, bp, sp */
1482 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1484 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1485 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1488 /* flags, fpsr, fpcr, frame */
1489 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1491 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1494 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1497 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1498 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1499 /* SSE REX registers */
1500 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1504 /* The "default" register map used in 32bit mode. */
1506 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1508 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1509 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1510 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1511 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1512 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1513 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1514 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1517 static int const x86_64_int_parameter_registers[6] =
1519 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1520 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1523 static int const x86_64_ms_abi_int_parameter_registers[4] =
1525 2 /*RCX*/, 1 /*RDX*/,
1526 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1529 static int const x86_64_int_return_registers[4] =
1531 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1534 /* The "default" register map used in 64bit mode. */
1535 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1537 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1538 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1539 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1540 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1541 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1542 8,9,10,11,12,13,14,15, /* extended integer registers */
1543 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1546 /* Define the register numbers to be used in Dwarf debugging information.
1547 The SVR4 reference port C compiler uses the following register numbers
1548 in its Dwarf output code:
1549 0 for %eax (gcc regno = 0)
1550 1 for %ecx (gcc regno = 2)
1551 2 for %edx (gcc regno = 1)
1552 3 for %ebx (gcc regno = 3)
1553 4 for %esp (gcc regno = 7)
1554 5 for %ebp (gcc regno = 6)
1555 6 for %esi (gcc regno = 4)
1556 7 for %edi (gcc regno = 5)
1557 The following three DWARF register numbers are never generated by
1558 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1559 believes these numbers have these meanings.
1560 8 for %eip (no gcc equivalent)
1561 9 for %eflags (gcc regno = 17)
1562 10 for %trapno (no gcc equivalent)
1563 It is not at all clear how we should number the FP stack registers
1564 for the x86 architecture. If the version of SDB on x86/svr4 were
1565 a bit less brain dead with respect to floating-point then we would
1566 have a precedent to follow with respect to DWARF register numbers
1567 for x86 FP registers, but the SDB on x86/svr4 is so completely
1568 broken with respect to FP registers that it is hardly worth thinking
1569 of it as something to strive for compatibility with.
1570 The version of x86/svr4 SDB I have at the moment does (partially)
1571 seem to believe that DWARF register number 11 is associated with
1572 the x86 register %st(0), but that's about all. Higher DWARF
1573 register numbers don't seem to be associated with anything in
1574 particular, and even for DWARF regno 11, SDB only seems to under-
1575 stand that it should say that a variable lives in %st(0) (when
1576 asked via an `=' command) if we said it was in DWARF regno 11,
1577 but SDB still prints garbage when asked for the value of the
1578 variable in question (via a `/' command).
1579 (Also note that the labels SDB prints for various FP stack regs
1580 when doing an `x' command are all wrong.)
1581 Note that these problems generally don't affect the native SVR4
1582 C compiler because it doesn't allow the use of -O with -g and
1583 because when it is *not* optimizing, it allocates a memory
1584 location for each floating-point variable, and the memory
1585 location is what gets described in the DWARF AT_location
1586 attribute for the variable in question.
1587 Regardless of the severe mental illness of the x86/svr4 SDB, we
1588 do something sensible here and we use the following DWARF
1589 register numbers. Note that these are all stack-top-relative
1591 11 for %st(0) (gcc regno = 8)
1592 12 for %st(1) (gcc regno = 9)
1593 13 for %st(2) (gcc regno = 10)
1594 14 for %st(3) (gcc regno = 11)
1595 15 for %st(4) (gcc regno = 12)
1596 16 for %st(5) (gcc regno = 13)
1597 17 for %st(6) (gcc regno = 14)
1598 18 for %st(7) (gcc regno = 15)
1600 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1602 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1603 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1604 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1605 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1606 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1607 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1608 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1611 /* Test and compare insns in i386.md store the information needed to
1612 generate branch and scc insns here. */
1614 rtx ix86_compare_op0 = NULL_RTX;
1615 rtx ix86_compare_op1 = NULL_RTX;
1616 rtx ix86_compare_emitted = NULL_RTX;
1618 /* Size of the register save area. */
1619 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1621 /* Define the structure for the machine field in struct function. */
1623 struct stack_local_entry GTY(())
1625 unsigned short mode;
1628 struct stack_local_entry *next;
1631 /* Structure describing stack frame layout.
1632 Stack grows downward:
1638 saved frame pointer if frame_pointer_needed
1639 <- HARD_FRAME_POINTER
1644 [va_arg registers] (
1645 > to_allocate <- FRAME_POINTER
1655 HOST_WIDE_INT frame;
1657 int outgoing_arguments_size;
1660 HOST_WIDE_INT to_allocate;
1661 /* The offsets relative to ARG_POINTER. */
1662 HOST_WIDE_INT frame_pointer_offset;
1663 HOST_WIDE_INT hard_frame_pointer_offset;
1664 HOST_WIDE_INT stack_pointer_offset;
1666 /* When save_regs_using_mov is set, emit prologue using
1667 move instead of push instructions. */
1668 bool save_regs_using_mov;
1671 /* Code model option. */
1672 enum cmodel ix86_cmodel;
1674 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1676 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1678 /* Which unit we are generating floating point math for. */
1679 enum fpmath_unit ix86_fpmath;
1681 /* Which cpu are we scheduling for. */
1682 enum processor_type ix86_tune;
1684 /* Which instruction set architecture to use. */
1685 enum processor_type ix86_arch;
1687 /* true if sse prefetch instruction is not NOOP. */
1688 int x86_prefetch_sse;
1690 /* ix86_regparm_string as a number */
1691 static int ix86_regparm;
1693 /* -mstackrealign option */
1694 extern int ix86_force_align_arg_pointer;
1695 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1697 /* Preferred alignment for stack boundary in bits. */
1698 unsigned int ix86_preferred_stack_boundary;
1700 /* Values 1-5: see jump.c */
1701 int ix86_branch_cost;
1703 /* Variables which are this size or smaller are put in the data/bss
1704 or ldata/lbss sections. */
1706 int ix86_section_threshold = 65536;
1708 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1709 char internal_label_prefix[16];
1710 int internal_label_prefix_len;
1712 /* Fence to use after loop using movnt. */
1715 /* Register class used for passing given 64bit part of the argument.
1716 These represent classes as documented by the PS ABI, with the exception
1717 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1718 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1720 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1721 whenever possible (upper half does contain padding). */
1722 enum x86_64_reg_class
1725 X86_64_INTEGER_CLASS,
1726 X86_64_INTEGERSI_CLASS,
1733 X86_64_COMPLEX_X87_CLASS,
1736 static const char * const x86_64_reg_class_name[] =
1738 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1739 "sseup", "x87", "x87up", "cplx87", "no"
1742 #define MAX_CLASSES 4
1744 /* Table of constants used by fldpi, fldln2, etc.... */
1745 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1746 static bool ext_80387_constants_init = 0;
1749 static struct machine_function * ix86_init_machine_status (void);
1750 static rtx ix86_function_value (const_tree, const_tree, bool);
1751 static int ix86_function_regparm (const_tree, const_tree);
1752 static void ix86_compute_frame_layout (struct ix86_frame *);
1753 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1757 /* The svr4 ABI for the i386 says that records and unions are returned
1759 #ifndef DEFAULT_PCC_STRUCT_RETURN
1760 #define DEFAULT_PCC_STRUCT_RETURN 1
1763 /* Bit flags that specify the ISA we are compiling for. */
1764 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1766 /* A mask of ix86_isa_flags that includes bit X if X
1767 was set or cleared on the command line. */
1768 static int ix86_isa_flags_explicit;
1770 /* Define a set of ISAs which aren't available for a given ISA. MMX
1771 and SSE ISAs are handled separately. */
1773 #define OPTION_MASK_ISA_MMX_UNSET \
1774 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_UNSET)
1775 #define OPTION_MASK_ISA_3DNOW_UNSET OPTION_MASK_ISA_3DNOW_A
1777 #define OPTION_MASK_ISA_SSE_UNSET \
1778 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE2_UNSET)
1779 #define OPTION_MASK_ISA_SSE2_UNSET \
1780 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE3_UNSET)
1781 #define OPTION_MASK_ISA_SSE3_UNSET \
1782 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSSE3_UNSET)
1783 #define OPTION_MASK_ISA_SSSE3_UNSET \
1784 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_1_UNSET)
1785 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1786 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_2_UNSET)
1787 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4A
1789 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1790 as -msse4.1 -msse4.2. -mno-sse4 should the same as -mno-sse4.1. */
1791 #define OPTION_MASK_ISA_SSE4 \
1792 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2)
1793 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1795 #define OPTION_MASK_ISA_SSE4A_UNSET OPTION_MASK_ISA_SSE4
1797 #define OPTION_MASK_ISA_SSE5_UNSET \
1798 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_UNSET)
1800 /* Vectorization library interface and handlers. */
1801 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1802 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1804 /* Implement TARGET_HANDLE_OPTION. */
1807 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1812 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX;
1815 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1816 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1821 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW;
1824 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1825 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
1833 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE;
1836 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
1837 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
1842 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2;
1845 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
1846 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
1851 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3;
1854 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
1855 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
1860 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3;
1863 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
1864 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
1869 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1;
1872 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
1873 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
1878 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2;
1881 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
1882 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
1887 ix86_isa_flags |= OPTION_MASK_ISA_SSE4;
1888 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4;
1892 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1893 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1897 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A;
1900 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1901 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1906 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5;
1909 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
1910 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
1919 /* Sometimes certain combinations of command options do not make
1920 sense on a particular target machine. You can define a macro
1921 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1922 defined, is executed once just after all the command options have
1925 Don't use this macro to turn on various extra optimizations for
1926 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1929 override_options (void)
1932 int ix86_tune_defaulted = 0;
1933 int ix86_arch_specified = 0;
1934 unsigned int ix86_arch_mask, ix86_tune_mask;
1936 /* Comes from final.c -- no real reason to change it. */
1937 #define MAX_CODE_ALIGN 16
1941 const struct processor_costs *cost; /* Processor costs */
1942 const int align_loop; /* Default alignments. */
1943 const int align_loop_max_skip;
1944 const int align_jump;
1945 const int align_jump_max_skip;
1946 const int align_func;
1948 const processor_target_table[PROCESSOR_max] =
1950 {&i386_cost, 4, 3, 4, 3, 4},
1951 {&i486_cost, 16, 15, 16, 15, 16},
1952 {&pentium_cost, 16, 7, 16, 7, 16},
1953 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1954 {&geode_cost, 0, 0, 0, 0, 0},
1955 {&k6_cost, 32, 7, 32, 7, 32},
1956 {&athlon_cost, 16, 7, 16, 7, 16},
1957 {&pentium4_cost, 0, 0, 0, 0, 0},
1958 {&k8_cost, 16, 7, 16, 7, 16},
1959 {&nocona_cost, 0, 0, 0, 0, 0},
1960 {&core2_cost, 16, 10, 16, 10, 16},
1961 {&generic32_cost, 16, 7, 16, 7, 16},
1962 {&generic64_cost, 16, 10, 16, 10, 16},
1963 {&amdfam10_cost, 32, 24, 32, 7, 32}
1966 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1973 PTA_PREFETCH_SSE = 1 << 4,
1975 PTA_3DNOW_A = 1 << 6,
1979 PTA_POPCNT = 1 << 10,
1981 PTA_SSE4A = 1 << 12,
1982 PTA_NO_SAHF = 1 << 13,
1983 PTA_SSE4_1 = 1 << 14,
1984 PTA_SSE4_2 = 1 << 15,
1990 const char *const name; /* processor name or nickname. */
1991 const enum processor_type processor;
1992 const unsigned /*enum pta_flags*/ flags;
1994 const processor_alias_table[] =
1996 {"i386", PROCESSOR_I386, 0},
1997 {"i486", PROCESSOR_I486, 0},
1998 {"i586", PROCESSOR_PENTIUM, 0},
1999 {"pentium", PROCESSOR_PENTIUM, 0},
2000 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2001 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2002 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2003 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2004 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2005 {"i686", PROCESSOR_PENTIUMPRO, 0},
2006 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2007 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2008 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2009 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2010 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2011 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2012 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2013 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2014 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2015 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2016 | PTA_CX16 | PTA_NO_SAHF)},
2017 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2018 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2021 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2022 |PTA_PREFETCH_SSE)},
2023 {"k6", PROCESSOR_K6, PTA_MMX},
2024 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2025 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2026 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2027 | PTA_PREFETCH_SSE)},
2028 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2029 | PTA_PREFETCH_SSE)},
2030 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2032 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2034 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2036 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2037 | PTA_MMX | PTA_SSE | PTA_SSE2
2039 {"k8", PROCESSOR_K8, (PTA_64BIT
2040 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2041 | PTA_SSE | PTA_SSE2
2043 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2044 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2045 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2047 {"opteron", PROCESSOR_K8, (PTA_64BIT
2048 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2049 | PTA_SSE | PTA_SSE2
2051 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2052 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2053 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2055 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2056 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2057 | PTA_SSE | PTA_SSE2
2059 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2060 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2061 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2063 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2064 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2065 | PTA_SSE | PTA_SSE2
2067 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2068 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2069 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2071 | PTA_CX16 | PTA_ABM)},
2072 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2073 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2074 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2076 | PTA_CX16 | PTA_ABM)},
2077 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2078 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2081 int const pta_size = ARRAY_SIZE (processor_alias_table);
2083 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2084 SUBTARGET_OVERRIDE_OPTIONS;
2087 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2088 SUBSUBTARGET_OVERRIDE_OPTIONS;
2091 /* -fPIC is the default for x86_64. */
2092 if (TARGET_MACHO && TARGET_64BIT)
2095 /* Set the default values for switches whose default depends on TARGET_64BIT
2096 in case they weren't overwritten by command line options. */
2099 /* Mach-O doesn't support omitting the frame pointer for now. */
2100 if (flag_omit_frame_pointer == 2)
2101 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2102 if (flag_asynchronous_unwind_tables == 2)
2103 flag_asynchronous_unwind_tables = 1;
2104 if (flag_pcc_struct_return == 2)
2105 flag_pcc_struct_return = 0;
2109 if (flag_omit_frame_pointer == 2)
2110 flag_omit_frame_pointer = 0;
2111 if (flag_asynchronous_unwind_tables == 2)
2112 flag_asynchronous_unwind_tables = 0;
2113 if (flag_pcc_struct_return == 2)
2114 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2117 /* Need to check -mtune=generic first. */
2118 if (ix86_tune_string)
2120 if (!strcmp (ix86_tune_string, "generic")
2121 || !strcmp (ix86_tune_string, "i686")
2122 /* As special support for cross compilers we read -mtune=native
2123 as -mtune=generic. With native compilers we won't see the
2124 -mtune=native, as it was changed by the driver. */
2125 || !strcmp (ix86_tune_string, "native"))
2128 ix86_tune_string = "generic64";
2130 ix86_tune_string = "generic32";
2132 else if (!strncmp (ix86_tune_string, "generic", 7))
2133 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2137 if (ix86_arch_string)
2138 ix86_tune_string = ix86_arch_string;
2139 if (!ix86_tune_string)
2141 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
2142 ix86_tune_defaulted = 1;
2145 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2146 need to use a sensible tune option. */
2147 if (!strcmp (ix86_tune_string, "generic")
2148 || !strcmp (ix86_tune_string, "x86-64")
2149 || !strcmp (ix86_tune_string, "i686"))
2152 ix86_tune_string = "generic64";
2154 ix86_tune_string = "generic32";
2157 if (ix86_stringop_string)
2159 if (!strcmp (ix86_stringop_string, "rep_byte"))
2160 stringop_alg = rep_prefix_1_byte;
2161 else if (!strcmp (ix86_stringop_string, "libcall"))
2162 stringop_alg = libcall;
2163 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2164 stringop_alg = rep_prefix_4_byte;
2165 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2166 stringop_alg = rep_prefix_8_byte;
2167 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2168 stringop_alg = loop_1_byte;
2169 else if (!strcmp (ix86_stringop_string, "loop"))
2170 stringop_alg = loop;
2171 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2172 stringop_alg = unrolled_loop;
2174 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
2176 if (!strcmp (ix86_tune_string, "x86-64"))
2177 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
2178 "-mtune=generic instead as appropriate.");
2180 if (!ix86_arch_string)
2181 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2183 ix86_arch_specified = 1;
2185 if (!strcmp (ix86_arch_string, "generic"))
2186 error ("generic CPU can be used only for -mtune= switch");
2187 if (!strncmp (ix86_arch_string, "generic", 7))
2188 error ("bad value (%s) for -march= switch", ix86_arch_string);
2190 if (ix86_cmodel_string != 0)
2192 if (!strcmp (ix86_cmodel_string, "small"))
2193 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2194 else if (!strcmp (ix86_cmodel_string, "medium"))
2195 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2196 else if (!strcmp (ix86_cmodel_string, "large"))
2197 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2199 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2200 else if (!strcmp (ix86_cmodel_string, "32"))
2201 ix86_cmodel = CM_32;
2202 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2203 ix86_cmodel = CM_KERNEL;
2205 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
2209 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
2210 use of rip-relative addressing. This eliminates fixups that
2211 would otherwise be needed if this object is to be placed in a
2212 DLL, and is essentially just as efficient as direct addressing. */
2213 if (TARGET_64BIT_MS_ABI)
2214 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2215 else if (TARGET_64BIT)
2216 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2218 ix86_cmodel = CM_32;
2220 if (ix86_asm_string != 0)
2223 && !strcmp (ix86_asm_string, "intel"))
2224 ix86_asm_dialect = ASM_INTEL;
2225 else if (!strcmp (ix86_asm_string, "att"))
2226 ix86_asm_dialect = ASM_ATT;
2228 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2230 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2231 error ("code model %qs not supported in the %s bit mode",
2232 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2233 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2234 sorry ("%i-bit mode not compiled in",
2235 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2237 for (i = 0; i < pta_size; i++)
2238 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2240 ix86_arch = processor_alias_table[i].processor;
2241 /* Default cpu tuning to the architecture. */
2242 ix86_tune = ix86_arch;
2244 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2245 error ("CPU you selected does not support x86-64 "
2248 if (processor_alias_table[i].flags & PTA_MMX
2249 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2250 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2251 if (processor_alias_table[i].flags & PTA_3DNOW
2252 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2253 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2254 if (processor_alias_table[i].flags & PTA_3DNOW_A
2255 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2256 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2257 if (processor_alias_table[i].flags & PTA_SSE
2258 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2259 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2260 if (processor_alias_table[i].flags & PTA_SSE2
2261 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2262 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2263 if (processor_alias_table[i].flags & PTA_SSE3
2264 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2265 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2266 if (processor_alias_table[i].flags & PTA_SSSE3
2267 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2268 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2269 if (processor_alias_table[i].flags & PTA_SSE4_1
2270 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2271 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2272 if (processor_alias_table[i].flags & PTA_SSE4_2
2273 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2274 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2275 if (processor_alias_table[i].flags & PTA_SSE4A
2276 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2277 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2278 if (processor_alias_table[i].flags & PTA_SSE5
2279 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2280 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2282 if (processor_alias_table[i].flags & PTA_ABM)
2284 if (processor_alias_table[i].flags & PTA_CX16)
2285 x86_cmpxchg16b = true;
2286 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
2288 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2289 x86_prefetch_sse = true;
2290 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
2297 error ("bad value (%s) for -march= switch", ix86_arch_string);
2299 ix86_arch_mask = 1u << ix86_arch;
2300 for (i = 0; i < X86_ARCH_LAST; ++i)
2301 ix86_arch_features[i] &= ix86_arch_mask;
2303 for (i = 0; i < pta_size; i++)
2304 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2306 ix86_tune = processor_alias_table[i].processor;
2307 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2309 if (ix86_tune_defaulted)
2311 ix86_tune_string = "x86-64";
2312 for (i = 0; i < pta_size; i++)
2313 if (! strcmp (ix86_tune_string,
2314 processor_alias_table[i].name))
2316 ix86_tune = processor_alias_table[i].processor;
2319 error ("CPU you selected does not support x86-64 "
2322 /* Intel CPUs have always interpreted SSE prefetch instructions as
2323 NOPs; so, we can enable SSE prefetch instructions even when
2324 -mtune (rather than -march) points us to a processor that has them.
2325 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2326 higher processors. */
2328 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2329 x86_prefetch_sse = true;
2333 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2335 ix86_tune_mask = 1u << ix86_tune;
2336 for (i = 0; i < X86_TUNE_LAST; ++i)
2337 ix86_tune_features[i] &= ix86_tune_mask;
2340 ix86_cost = &size_cost;
2342 ix86_cost = processor_target_table[ix86_tune].cost;
2344 /* Arrange to set up i386_stack_locals for all functions. */
2345 init_machine_status = ix86_init_machine_status;
2347 /* Validate -mregparm= value. */
2348 if (ix86_regparm_string)
2351 warning (0, "-mregparm is ignored in 64-bit mode");
2352 i = atoi (ix86_regparm_string);
2353 if (i < 0 || i > REGPARM_MAX)
2354 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2359 ix86_regparm = REGPARM_MAX;
2361 /* If the user has provided any of the -malign-* options,
2362 warn and use that value only if -falign-* is not set.
2363 Remove this code in GCC 3.2 or later. */
2364 if (ix86_align_loops_string)
2366 warning (0, "-malign-loops is obsolete, use -falign-loops");
2367 if (align_loops == 0)
2369 i = atoi (ix86_align_loops_string);
2370 if (i < 0 || i > MAX_CODE_ALIGN)
2371 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2373 align_loops = 1 << i;
2377 if (ix86_align_jumps_string)
2379 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2380 if (align_jumps == 0)
2382 i = atoi (ix86_align_jumps_string);
2383 if (i < 0 || i > MAX_CODE_ALIGN)
2384 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2386 align_jumps = 1 << i;
2390 if (ix86_align_funcs_string)
2392 warning (0, "-malign-functions is obsolete, use -falign-functions");
2393 if (align_functions == 0)
2395 i = atoi (ix86_align_funcs_string);
2396 if (i < 0 || i > MAX_CODE_ALIGN)
2397 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2399 align_functions = 1 << i;
2403 /* Default align_* from the processor table. */
2404 if (align_loops == 0)
2406 align_loops = processor_target_table[ix86_tune].align_loop;
2407 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2409 if (align_jumps == 0)
2411 align_jumps = processor_target_table[ix86_tune].align_jump;
2412 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2414 if (align_functions == 0)
2416 align_functions = processor_target_table[ix86_tune].align_func;
2419 /* Validate -mbranch-cost= value, or provide default. */
2420 ix86_branch_cost = ix86_cost->branch_cost;
2421 if (ix86_branch_cost_string)
2423 i = atoi (ix86_branch_cost_string);
2425 error ("-mbranch-cost=%d is not between 0 and 5", i);
2427 ix86_branch_cost = i;
2429 if (ix86_section_threshold_string)
2431 i = atoi (ix86_section_threshold_string);
2433 error ("-mlarge-data-threshold=%d is negative", i);
2435 ix86_section_threshold = i;
2438 if (ix86_tls_dialect_string)
2440 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2441 ix86_tls_dialect = TLS_DIALECT_GNU;
2442 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2443 ix86_tls_dialect = TLS_DIALECT_GNU2;
2444 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2445 ix86_tls_dialect = TLS_DIALECT_SUN;
2447 error ("bad value (%s) for -mtls-dialect= switch",
2448 ix86_tls_dialect_string);
2451 if (ix87_precision_string)
2453 i = atoi (ix87_precision_string);
2454 if (i != 32 && i != 64 && i != 80)
2455 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2460 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2462 /* Enable by default the SSE and MMX builtins. Do allow the user to
2463 explicitly disable any of these. In particular, disabling SSE and
2464 MMX for kernel code is extremely useful. */
2465 if (!ix86_arch_specified)
2467 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2468 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2471 warning (0, "-mrtd is ignored in 64bit mode");
2475 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2477 if (!ix86_arch_specified)
2479 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2481 /* i386 ABI does not specify red zone. It still makes sense to use it
2482 when programmer takes care to stack from being destroyed. */
2483 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2484 target_flags |= MASK_NO_RED_ZONE;
2487 /* Keep nonleaf frame pointers. */
2488 if (flag_omit_frame_pointer)
2489 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2490 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2491 flag_omit_frame_pointer = 1;
2493 /* If we're doing fast math, we don't care about comparison order
2494 wrt NaNs. This lets us use a shorter comparison sequence. */
2495 if (flag_finite_math_only)
2496 target_flags &= ~MASK_IEEE_FP;
2498 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2499 since the insns won't need emulation. */
2500 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2501 target_flags &= ~MASK_NO_FANCY_MATH_387;
2503 /* Likewise, if the target doesn't have a 387, or we've specified
2504 software floating point, don't use 387 inline intrinsics. */
2506 target_flags |= MASK_NO_FANCY_MATH_387;
2508 /* Turn on SSE4A bultins for -msse5. */
2510 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2512 /* Turn on SSE4.1 builtins for -msse4.2. */
2514 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2516 /* Turn on SSSE3 builtins for -msse4.1. */
2518 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2520 /* Turn on SSE3 builtins for -mssse3. */
2522 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2524 /* Turn on SSE3 builtins for -msse4a. */
2526 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2528 /* Turn on SSE2 builtins for -msse3. */
2530 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2532 /* Turn on SSE builtins for -msse2. */
2534 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2536 /* Turn on MMX builtins for -msse. */
2539 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
2540 x86_prefetch_sse = true;
2543 /* Turn on MMX builtins for 3Dnow. */
2545 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2547 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
2548 if (TARGET_SSE4_2 || TARGET_ABM)
2551 /* Validate -mpreferred-stack-boundary= value, or provide default.
2552 The default of 128 bits is for Pentium III's SSE __m128. We can't
2553 change it because of optimize_size. Otherwise, we can't mix object
2554 files compiled with -Os and -On. */
2555 ix86_preferred_stack_boundary = 128;
2556 if (ix86_preferred_stack_boundary_string)
2558 i = atoi (ix86_preferred_stack_boundary_string);
2559 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2560 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2561 TARGET_64BIT ? 4 : 2);
2563 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2566 /* Accept -msseregparm only if at least SSE support is enabled. */
2567 if (TARGET_SSEREGPARM
2569 error ("-msseregparm used without SSE enabled");
2571 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2572 if (ix86_fpmath_string != 0)
2574 if (! strcmp (ix86_fpmath_string, "387"))
2575 ix86_fpmath = FPMATH_387;
2576 else if (! strcmp (ix86_fpmath_string, "sse"))
2580 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2581 ix86_fpmath = FPMATH_387;
2584 ix86_fpmath = FPMATH_SSE;
2586 else if (! strcmp (ix86_fpmath_string, "387,sse")
2587 || ! strcmp (ix86_fpmath_string, "sse,387"))
2591 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2592 ix86_fpmath = FPMATH_387;
2594 else if (!TARGET_80387)
2596 warning (0, "387 instruction set disabled, using SSE arithmetics");
2597 ix86_fpmath = FPMATH_SSE;
2600 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
2603 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2606 /* If the i387 is disabled, then do not return values in it. */
2608 target_flags &= ~MASK_FLOAT_RETURNS;
2610 /* Use external vectorized library in vectorizing intrinsics. */
2611 if (ix86_veclibabi_string)
2613 if (strcmp (ix86_veclibabi_string, "acml") == 0)
2614 ix86_veclib_handler = ix86_veclibabi_acml;
2616 error ("unknown vectorization library ABI type (%s) for "
2617 "-mveclibabi= switch", ix86_veclibabi_string);
2620 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2621 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2623 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2625 /* ??? Unwind info is not correct around the CFG unless either a frame
2626 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2627 unwind info generation to be aware of the CFG and propagating states
2629 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2630 || flag_exceptions || flag_non_call_exceptions)
2631 && flag_omit_frame_pointer
2632 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2634 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2635 warning (0, "unwind tables currently require either a frame pointer "
2636 "or -maccumulate-outgoing-args for correctness");
2637 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2640 /* For sane SSE instruction set generation we need fcomi instruction.
2641 It is safe to enable all CMOVE instructions. */
2645 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2648 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2649 p = strchr (internal_label_prefix, 'X');
2650 internal_label_prefix_len = p - internal_label_prefix;
2654 /* When scheduling description is not available, disable scheduler pass
2655 so it won't slow down the compilation and make x87 code slower. */
2656 if (!TARGET_SCHEDULE)
2657 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2659 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2660 set_param_value ("simultaneous-prefetches",
2661 ix86_cost->simultaneous_prefetches);
2662 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2663 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2664 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
2665 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
2666 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
2667 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
2670 /* Return true if this goes in large data/bss. */
2673 ix86_in_large_data_p (tree exp)
2675 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2678 /* Functions are never large data. */
2679 if (TREE_CODE (exp) == FUNCTION_DECL)
2682 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2684 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2685 if (strcmp (section, ".ldata") == 0
2686 || strcmp (section, ".lbss") == 0)
2692 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2694 /* If this is an incomplete type with size 0, then we can't put it
2695 in data because it might be too big when completed. */
2696 if (!size || size > ix86_section_threshold)
2703 /* Switch to the appropriate section for output of DECL.
2704 DECL is either a `VAR_DECL' node or a constant of some sort.
2705 RELOC indicates whether forming the initial value of DECL requires
2706 link-time relocations. */
2708 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2712 x86_64_elf_select_section (tree decl, int reloc,
2713 unsigned HOST_WIDE_INT align)
2715 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2716 && ix86_in_large_data_p (decl))
2718 const char *sname = NULL;
2719 unsigned int flags = SECTION_WRITE;
2720 switch (categorize_decl_for_section (decl, reloc))
2725 case SECCAT_DATA_REL:
2726 sname = ".ldata.rel";
2728 case SECCAT_DATA_REL_LOCAL:
2729 sname = ".ldata.rel.local";
2731 case SECCAT_DATA_REL_RO:
2732 sname = ".ldata.rel.ro";
2734 case SECCAT_DATA_REL_RO_LOCAL:
2735 sname = ".ldata.rel.ro.local";
2739 flags |= SECTION_BSS;
2742 case SECCAT_RODATA_MERGE_STR:
2743 case SECCAT_RODATA_MERGE_STR_INIT:
2744 case SECCAT_RODATA_MERGE_CONST:
2748 case SECCAT_SRODATA:
2755 /* We don't split these for medium model. Place them into
2756 default sections and hope for best. */
2761 /* We might get called with string constants, but get_named_section
2762 doesn't like them as they are not DECLs. Also, we need to set
2763 flags in that case. */
2765 return get_section (sname, flags, NULL);
2766 return get_named_section (decl, sname, reloc);
2769 return default_elf_select_section (decl, reloc, align);
2772 /* Build up a unique section name, expressed as a
2773 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2774 RELOC indicates whether the initial value of EXP requires
2775 link-time relocations. */
2777 static void ATTRIBUTE_UNUSED
2778 x86_64_elf_unique_section (tree decl, int reloc)
2780 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2781 && ix86_in_large_data_p (decl))
2783 const char *prefix = NULL;
2784 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2785 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2787 switch (categorize_decl_for_section (decl, reloc))
2790 case SECCAT_DATA_REL:
2791 case SECCAT_DATA_REL_LOCAL:
2792 case SECCAT_DATA_REL_RO:
2793 case SECCAT_DATA_REL_RO_LOCAL:
2794 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2797 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2800 case SECCAT_RODATA_MERGE_STR:
2801 case SECCAT_RODATA_MERGE_STR_INIT:
2802 case SECCAT_RODATA_MERGE_CONST:
2803 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2805 case SECCAT_SRODATA:
2812 /* We don't split these for medium model. Place them into
2813 default sections and hope for best. */
2821 plen = strlen (prefix);
2823 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2824 name = targetm.strip_name_encoding (name);
2825 nlen = strlen (name);
2827 string = (char *) alloca (nlen + plen + 1);
2828 memcpy (string, prefix, plen);
2829 memcpy (string + plen, name, nlen + 1);
2831 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2835 default_unique_section (decl, reloc);
2838 #ifdef COMMON_ASM_OP
2839 /* This says how to output assembler code to declare an
2840 uninitialized external linkage data object.
2842 For medium model x86-64 we need to use .largecomm opcode for
2845 x86_elf_aligned_common (FILE *file,
2846 const char *name, unsigned HOST_WIDE_INT size,
2849 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2850 && size > (unsigned int)ix86_section_threshold)
2851 fprintf (file, ".largecomm\t");
2853 fprintf (file, "%s", COMMON_ASM_OP);
2854 assemble_name (file, name);
2855 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2856 size, align / BITS_PER_UNIT);
2860 /* Utility function for targets to use in implementing
2861 ASM_OUTPUT_ALIGNED_BSS. */
2864 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2865 const char *name, unsigned HOST_WIDE_INT size,
2868 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2869 && size > (unsigned int)ix86_section_threshold)
2870 switch_to_section (get_named_section (decl, ".lbss", 0));
2872 switch_to_section (bss_section);
2873 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2874 #ifdef ASM_DECLARE_OBJECT_NAME
2875 last_assemble_variable_decl = decl;
2876 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2878 /* Standard thing is just output label for the object. */
2879 ASM_OUTPUT_LABEL (file, name);
2880 #endif /* ASM_DECLARE_OBJECT_NAME */
2881 ASM_OUTPUT_SKIP (file, size ? size : 1);
2885 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2887 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2888 make the problem with not enough registers even worse. */
2889 #ifdef INSN_SCHEDULING
2891 flag_schedule_insns = 0;
2895 /* The Darwin libraries never set errno, so we might as well
2896 avoid calling them when that's the only reason we would. */
2897 flag_errno_math = 0;
2899 /* The default values of these switches depend on the TARGET_64BIT
2900 that is not known at this moment. Mark these values with 2 and
2901 let user the to override these. In case there is no command line option
2902 specifying them, we will set the defaults in override_options. */
2904 flag_omit_frame_pointer = 2;
2905 flag_pcc_struct_return = 2;
2906 flag_asynchronous_unwind_tables = 2;
2907 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2908 SUBTARGET_OPTIMIZATION_OPTIONS;
2912 /* Decide whether we can make a sibling call to a function. DECL is the
2913 declaration of the function being targeted by the call and EXP is the
2914 CALL_EXPR representing the call. */
2917 ix86_function_ok_for_sibcall (tree decl, tree exp)
2922 /* If we are generating position-independent code, we cannot sibcall
2923 optimize any indirect call, or a direct call to a global function,
2924 as the PLT requires %ebx be live. */
2925 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
2932 func = TREE_TYPE (CALL_EXPR_FN (exp));
2933 if (POINTER_TYPE_P (func))
2934 func = TREE_TYPE (func);
2937 /* Check that the return value locations are the same. Like
2938 if we are returning floats on the 80387 register stack, we cannot
2939 make a sibcall from a function that doesn't return a float to a
2940 function that does or, conversely, from a function that does return
2941 a float to a function that doesn't; the necessary stack adjustment
2942 would not be executed. This is also the place we notice
2943 differences in the return value ABI. Note that it is ok for one
2944 of the functions to have void return type as long as the return
2945 value of the other is passed in a register. */
2946 a = ix86_function_value (TREE_TYPE (exp), func, false);
2947 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
2949 if (STACK_REG_P (a) || STACK_REG_P (b))
2951 if (!rtx_equal_p (a, b))
2954 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
2956 else if (!rtx_equal_p (a, b))
2959 /* If this call is indirect, we'll need to be able to use a call-clobbered
2960 register for the address of the target function. Make sure that all
2961 such registers are not used for passing parameters. */
2962 if (!decl && !TARGET_64BIT)
2966 /* We're looking at the CALL_EXPR, we need the type of the function. */
2967 type = CALL_EXPR_FN (exp); /* pointer expression */
2968 type = TREE_TYPE (type); /* pointer type */
2969 type = TREE_TYPE (type); /* function type */
2971 if (ix86_function_regparm (type, NULL) >= 3)
2973 /* ??? Need to count the actual number of registers to be used,
2974 not the possible number of registers. Fix later. */
2979 /* Dllimport'd functions are also called indirectly. */
2980 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
2981 && decl && DECL_DLLIMPORT_P (decl)
2982 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
2985 /* If we forced aligned the stack, then sibcalling would unalign the
2986 stack, which may break the called function. */
2987 if (cfun->machine->force_align_arg_pointer)
2990 /* Otherwise okay. That also includes certain types of indirect calls. */
2994 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2995 calling convention attributes;
2996 arguments as in struct attribute_spec.handler. */
2999 ix86_handle_cconv_attribute (tree *node, tree name,
3001 int flags ATTRIBUTE_UNUSED,
3004 if (TREE_CODE (*node) != FUNCTION_TYPE
3005 && TREE_CODE (*node) != METHOD_TYPE
3006 && TREE_CODE (*node) != FIELD_DECL
3007 && TREE_CODE (*node) != TYPE_DECL)
3009 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3010 IDENTIFIER_POINTER (name));
3011 *no_add_attrs = true;
3015 /* Can combine regparm with all attributes but fastcall. */
3016 if (is_attribute_p ("regparm", name))
3020 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3022 error ("fastcall and regparm attributes are not compatible");
3025 cst = TREE_VALUE (args);
3026 if (TREE_CODE (cst) != INTEGER_CST)
3028 warning (OPT_Wattributes,
3029 "%qs attribute requires an integer constant argument",
3030 IDENTIFIER_POINTER (name));
3031 *no_add_attrs = true;
3033 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
3035 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
3036 IDENTIFIER_POINTER (name), REGPARM_MAX);
3037 *no_add_attrs = true;
3041 && lookup_attribute (ix86_force_align_arg_pointer_string,
3042 TYPE_ATTRIBUTES (*node))
3043 && compare_tree_int (cst, REGPARM_MAX-1))
3045 error ("%s functions limited to %d register parameters",
3046 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
3054 /* Do not warn when emulating the MS ABI. */
3055 if (!TARGET_64BIT_MS_ABI)
3056 warning (OPT_Wattributes, "%qs attribute ignored",
3057 IDENTIFIER_POINTER (name));
3058 *no_add_attrs = true;
3062 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
3063 if (is_attribute_p ("fastcall", name))
3065 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3067 error ("fastcall and cdecl attributes are not compatible");
3069 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3071 error ("fastcall and stdcall attributes are not compatible");
3073 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
3075 error ("fastcall and regparm attributes are not compatible");
3079 /* Can combine stdcall with fastcall (redundant), regparm and
3081 else if (is_attribute_p ("stdcall", name))
3083 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3085 error ("stdcall and cdecl attributes are not compatible");
3087 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3089 error ("stdcall and fastcall attributes are not compatible");
3093 /* Can combine cdecl with regparm and sseregparm. */
3094 else if (is_attribute_p ("cdecl", name))
3096 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3098 error ("stdcall and cdecl attributes are not compatible");
3100 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3102 error ("fastcall and cdecl attributes are not compatible");
3106 /* Can combine sseregparm with all attributes. */
3111 /* Return 0 if the attributes for two types are incompatible, 1 if they
3112 are compatible, and 2 if they are nearly compatible (which causes a
3113 warning to be generated). */
3116 ix86_comp_type_attributes (const_tree type1, const_tree type2)
3118 /* Check for mismatch of non-default calling convention. */
3119 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
3121 if (TREE_CODE (type1) != FUNCTION_TYPE
3122 && TREE_CODE (type1) != METHOD_TYPE)
3125 /* Check for mismatched fastcall/regparm types. */
3126 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
3127 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
3128 || (ix86_function_regparm (type1, NULL)
3129 != ix86_function_regparm (type2, NULL)))
3132 /* Check for mismatched sseregparm types. */
3133 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
3134 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
3137 /* Check for mismatched return types (cdecl vs stdcall). */
3138 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
3139 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
3145 /* Return the regparm value for a function with the indicated TYPE and DECL.
3146 DECL may be NULL when calling function indirectly
3147 or considering a libcall. */
3150 ix86_function_regparm (const_tree type, const_tree decl)
3153 int regparm = ix86_regparm;
3158 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
3160 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
3162 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
3165 /* Use register calling convention for local functions when possible. */
3166 if (decl && TREE_CODE (decl) == FUNCTION_DECL
3167 && flag_unit_at_a_time && !profile_flag)
3169 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3170 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3173 int local_regparm, globals = 0, regno;
3176 /* Make sure no regparm register is taken by a
3177 global register variable. */
3178 for (local_regparm = 0; local_regparm < 3; local_regparm++)
3179 if (global_regs[local_regparm])
3182 /* We can't use regparm(3) for nested functions as these use
3183 static chain pointer in third argument. */
3184 if (local_regparm == 3
3185 && (decl_function_context (decl)
3186 || ix86_force_align_arg_pointer)
3187 && !DECL_NO_STATIC_CHAIN (decl))
3190 /* If the function realigns its stackpointer, the prologue will
3191 clobber %ecx. If we've already generated code for the callee,
3192 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
3193 scanning the attributes for the self-realigning property. */
3194 f = DECL_STRUCT_FUNCTION (decl);
3195 if (local_regparm == 3
3196 && (f ? !!f->machine->force_align_arg_pointer
3197 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
3198 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
3201 /* Each global register variable increases register preassure,
3202 so the more global reg vars there are, the smaller regparm
3203 optimization use, unless requested by the user explicitly. */
3204 for (regno = 0; regno < 6; regno++)
3205 if (global_regs[regno])
3208 = globals < local_regparm ? local_regparm - globals : 0;
3210 if (local_regparm > regparm)
3211 regparm = local_regparm;
3218 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
3219 DFmode (2) arguments in SSE registers for a function with the
3220 indicated TYPE and DECL. DECL may be NULL when calling function
3221 indirectly or considering a libcall. Otherwise return 0. */
3224 ix86_function_sseregparm (const_tree type, const_tree decl)
3226 gcc_assert (!TARGET_64BIT);
3228 /* Use SSE registers to pass SFmode and DFmode arguments if requested
3229 by the sseregparm attribute. */
3230 if (TARGET_SSEREGPARM
3231 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
3236 error ("Calling %qD with attribute sseregparm without "
3237 "SSE/SSE2 enabled", decl);
3239 error ("Calling %qT with attribute sseregparm without "
3240 "SSE/SSE2 enabled", type);
3247 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3248 (and DFmode for SSE2) arguments in SSE registers. */
3249 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
3251 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3252 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3254 return TARGET_SSE2 ? 2 : 1;
3260 /* Return true if EAX is live at the start of the function. Used by
3261 ix86_expand_prologue to determine if we need special help before
3262 calling allocate_stack_worker. */
3265 ix86_eax_live_at_start_p (void)
3267 /* Cheat. Don't bother working forward from ix86_function_regparm
3268 to the function type to whether an actual argument is located in
3269 eax. Instead just look at cfg info, which is still close enough
3270 to correct at this point. This gives false positives for broken
3271 functions that might use uninitialized data that happens to be
3272 allocated in eax, but who cares? */
3273 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
3276 /* Value is the number of bytes of arguments automatically
3277 popped when returning from a subroutine call.
3278 FUNDECL is the declaration node of the function (as a tree),
3279 FUNTYPE is the data type of the function (as a tree),
3280 or for a library call it is an identifier node for the subroutine name.
3281 SIZE is the number of bytes of arguments passed on the stack.
3283 On the 80386, the RTD insn may be used to pop them if the number
3284 of args is fixed, but if the number is variable then the caller
3285 must pop them all. RTD can't be used for library calls now
3286 because the library is compiled with the Unix compiler.
3287 Use of RTD is a selectable option, since it is incompatible with
3288 standard Unix calling sequences. If the option is not selected,
3289 the caller must always pop the args.
3291 The attribute stdcall is equivalent to RTD on a per module basis. */
3294 ix86_return_pops_args (tree fundecl, tree funtype, int size)
3298 /* None of the 64-bit ABIs pop arguments. */
3302 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
3304 /* Cdecl functions override -mrtd, and never pop the stack. */
3305 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
3307 /* Stdcall and fastcall functions will pop the stack if not
3309 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
3310 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
3313 if (rtd && ! stdarg_p (funtype))
3317 /* Lose any fake structure return argument if it is passed on the stack. */
3318 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
3319 && !KEEP_AGGREGATE_RETURN_POINTER)
3321 int nregs = ix86_function_regparm (funtype, fundecl);
3323 return GET_MODE_SIZE (Pmode);
3329 /* Argument support functions. */
3331 /* Return true when register may be used to pass function parameters. */
3333 ix86_function_arg_regno_p (int regno)
3336 const int *parm_regs;
3341 return (regno < REGPARM_MAX
3342 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3344 return (regno < REGPARM_MAX
3345 || (TARGET_MMX && MMX_REGNO_P (regno)
3346 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3347 || (TARGET_SSE && SSE_REGNO_P (regno)
3348 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3353 if (SSE_REGNO_P (regno) && TARGET_SSE)
3358 if (TARGET_SSE && SSE_REGNO_P (regno)
3359 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3363 /* RAX is used as hidden argument to va_arg functions. */
3364 if (!TARGET_64BIT_MS_ABI && regno == AX_REG)
3367 if (TARGET_64BIT_MS_ABI)
3368 parm_regs = x86_64_ms_abi_int_parameter_registers;
3370 parm_regs = x86_64_int_parameter_registers;
3371 for (i = 0; i < REGPARM_MAX; i++)
3372 if (regno == parm_regs[i])
3377 /* Return if we do not know how to pass TYPE solely in registers. */
3380 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
3382 if (must_pass_in_stack_var_size_or_pad (mode, type))
3385 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3386 The layout_type routine is crafty and tries to trick us into passing
3387 currently unsupported vector types on the stack by using TImode. */
3388 return (!TARGET_64BIT && mode == TImode
3389 && type && TREE_CODE (type) != VECTOR_TYPE);
3392 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3393 for a call to a function whose data type is FNTYPE.
3394 For a library call, FNTYPE is 0. */
3397 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3398 tree fntype, /* tree ptr for function decl */
3399 rtx libname, /* SYMBOL_REF of library name or 0 */
3402 memset (cum, 0, sizeof (*cum));
3404 /* Set up the number of registers to use for passing arguments. */
3405 cum->nregs = ix86_regparm;
3407 cum->sse_nregs = SSE_REGPARM_MAX;
3409 cum->mmx_nregs = MMX_REGPARM_MAX;
3410 cum->warn_sse = true;
3411 cum->warn_mmx = true;
3412 cum->maybe_vaarg = (fntype
3413 ? (!prototype_p (fntype) || stdarg_p (fntype))
3418 /* If there are variable arguments, then we won't pass anything
3419 in registers in 32-bit mode. */
3420 if (cum->maybe_vaarg)
3430 /* Use ecx and edx registers if function has fastcall attribute,
3431 else look for regparm information. */
3434 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3440 cum->nregs = ix86_function_regparm (fntype, fndecl);
3443 /* Set up the number of SSE registers used for passing SFmode
3444 and DFmode arguments. Warn for mismatching ABI. */
3445 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
3449 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3450 But in the case of vector types, it is some vector mode.
3452 When we have only some of our vector isa extensions enabled, then there
3453 are some modes for which vector_mode_supported_p is false. For these
3454 modes, the generic vector support in gcc will choose some non-vector mode
3455 in order to implement the type. By computing the natural mode, we'll
3456 select the proper ABI location for the operand and not depend on whatever
3457 the middle-end decides to do with these vector types. */
3459 static enum machine_mode
3460 type_natural_mode (const_tree type)
3462 enum machine_mode mode = TYPE_MODE (type);
3464 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3466 HOST_WIDE_INT size = int_size_in_bytes (type);
3467 if ((size == 8 || size == 16)
3468 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3469 && TYPE_VECTOR_SUBPARTS (type) > 1)
3471 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3473 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3474 mode = MIN_MODE_VECTOR_FLOAT;
3476 mode = MIN_MODE_VECTOR_INT;
3478 /* Get the mode which has this inner mode and number of units. */
3479 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3480 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3481 && GET_MODE_INNER (mode) == innermode)
3491 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3492 this may not agree with the mode that the type system has chosen for the
3493 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3494 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3497 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3502 if (orig_mode != BLKmode)
3503 tmp = gen_rtx_REG (orig_mode, regno);
3506 tmp = gen_rtx_REG (mode, regno);
3507 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3508 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3514 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3515 of this code is to classify each 8bytes of incoming argument by the register
3516 class and assign registers accordingly. */
3518 /* Return the union class of CLASS1 and CLASS2.
3519 See the x86-64 PS ABI for details. */
3521 static enum x86_64_reg_class
3522 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3524 /* Rule #1: If both classes are equal, this is the resulting class. */
3525 if (class1 == class2)
3528 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3530 if (class1 == X86_64_NO_CLASS)
3532 if (class2 == X86_64_NO_CLASS)
3535 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3536 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3537 return X86_64_MEMORY_CLASS;
3539 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3540 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3541 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3542 return X86_64_INTEGERSI_CLASS;
3543 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3544 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3545 return X86_64_INTEGER_CLASS;
3547 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3549 if (class1 == X86_64_X87_CLASS
3550 || class1 == X86_64_X87UP_CLASS
3551 || class1 == X86_64_COMPLEX_X87_CLASS
3552 || class2 == X86_64_X87_CLASS
3553 || class2 == X86_64_X87UP_CLASS
3554 || class2 == X86_64_COMPLEX_X87_CLASS)
3555 return X86_64_MEMORY_CLASS;
3557 /* Rule #6: Otherwise class SSE is used. */
3558 return X86_64_SSE_CLASS;
3561 /* Classify the argument of type TYPE and mode MODE.
3562 CLASSES will be filled by the register class used to pass each word
3563 of the operand. The number of words is returned. In case the parameter
3564 should be passed in memory, 0 is returned. As a special case for zero
3565 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3567 BIT_OFFSET is used internally for handling records and specifies offset
3568 of the offset in bits modulo 256 to avoid overflow cases.
3570 See the x86-64 PS ABI for details.
3574 classify_argument (enum machine_mode mode, const_tree type,
3575 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3577 HOST_WIDE_INT bytes =
3578 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3579 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3581 /* Variable sized entities are always passed/returned in memory. */
3585 if (mode != VOIDmode
3586 && targetm.calls.must_pass_in_stack (mode, type))
3589 if (type && AGGREGATE_TYPE_P (type))
3593 enum x86_64_reg_class subclasses[MAX_CLASSES];
3595 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3599 for (i = 0; i < words; i++)
3600 classes[i] = X86_64_NO_CLASS;
3602 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3603 signalize memory class, so handle it as special case. */
3606 classes[0] = X86_64_NO_CLASS;
3610 /* Classify each field of record and merge classes. */
3611 switch (TREE_CODE (type))
3614 /* And now merge the fields of structure. */
3615 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3617 if (TREE_CODE (field) == FIELD_DECL)
3621 if (TREE_TYPE (field) == error_mark_node)
3624 /* Bitfields are always classified as integer. Handle them
3625 early, since later code would consider them to be
3626 misaligned integers. */
3627 if (DECL_BIT_FIELD (field))
3629 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3630 i < ((int_bit_position (field) + (bit_offset % 64))
3631 + tree_low_cst (DECL_SIZE (field), 0)
3634 merge_classes (X86_64_INTEGER_CLASS,
3639 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3640 TREE_TYPE (field), subclasses,
3641 (int_bit_position (field)
3642 + bit_offset) % 256);
3645 for (i = 0; i < num; i++)
3648 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3650 merge_classes (subclasses[i], classes[i + pos]);
3658 /* Arrays are handled as small records. */
3661 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3662 TREE_TYPE (type), subclasses, bit_offset);
3666 /* The partial classes are now full classes. */
3667 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3668 subclasses[0] = X86_64_SSE_CLASS;
3669 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3670 subclasses[0] = X86_64_INTEGER_CLASS;
3672 for (i = 0; i < words; i++)
3673 classes[i] = subclasses[i % num];
3678 case QUAL_UNION_TYPE:
3679 /* Unions are similar to RECORD_TYPE but offset is always 0.
3681 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3683 if (TREE_CODE (field) == FIELD_DECL)
3687 if (TREE_TYPE (field) == error_mark_node)
3690 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3691 TREE_TYPE (field), subclasses,
3695 for (i = 0; i < num; i++)
3696 classes[i] = merge_classes (subclasses[i], classes[i]);
3705 /* Final merger cleanup. */
3706 for (i = 0; i < words; i++)
3708 /* If one class is MEMORY, everything should be passed in
3710 if (classes[i] == X86_64_MEMORY_CLASS)
3713 /* The X86_64_SSEUP_CLASS should be always preceded by
3714 X86_64_SSE_CLASS. */
3715 if (classes[i] == X86_64_SSEUP_CLASS
3716 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3717 classes[i] = X86_64_SSE_CLASS;
3719 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3720 if (classes[i] == X86_64_X87UP_CLASS
3721 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3722 classes[i] = X86_64_SSE_CLASS;
3727 /* Compute alignment needed. We align all types to natural boundaries with
3728 exception of XFmode that is aligned to 64bits. */
3729 if (mode != VOIDmode && mode != BLKmode)
3731 int mode_alignment = GET_MODE_BITSIZE (mode);
3734 mode_alignment = 128;
3735 else if (mode == XCmode)
3736 mode_alignment = 256;
3737 if (COMPLEX_MODE_P (mode))
3738 mode_alignment /= 2;
3739 /* Misaligned fields are always returned in memory. */
3740 if (bit_offset % mode_alignment)
3744 /* for V1xx modes, just use the base mode */
3745 if (VECTOR_MODE_P (mode)
3746 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3747 mode = GET_MODE_INNER (mode);
3749 /* Classification of atomic types. */
3754 classes[0] = X86_64_SSE_CLASS;
3757 classes[0] = X86_64_SSE_CLASS;
3758 classes[1] = X86_64_SSEUP_CLASS;
3767 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3768 classes[0] = X86_64_INTEGERSI_CLASS;
3770 classes[0] = X86_64_INTEGER_CLASS;
3774 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3779 if (!(bit_offset % 64))
3780 classes[0] = X86_64_SSESF_CLASS;
3782 classes[0] = X86_64_SSE_CLASS;
3785 classes[0] = X86_64_SSEDF_CLASS;
3788 classes[0] = X86_64_X87_CLASS;
3789 classes[1] = X86_64_X87UP_CLASS;
3792 classes[0] = X86_64_SSE_CLASS;
3793 classes[1] = X86_64_SSEUP_CLASS;
3796 classes[0] = X86_64_SSE_CLASS;
3799 classes[0] = X86_64_SSEDF_CLASS;
3800 classes[1] = X86_64_SSEDF_CLASS;
3803 classes[0] = X86_64_COMPLEX_X87_CLASS;
3806 /* This modes is larger than 16 bytes. */
3814 classes[0] = X86_64_SSE_CLASS;
3815 classes[1] = X86_64_SSEUP_CLASS;
3821 classes[0] = X86_64_SSE_CLASS;
3827 gcc_assert (VECTOR_MODE_P (mode));
3832 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3834 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3835 classes[0] = X86_64_INTEGERSI_CLASS;
3837 classes[0] = X86_64_INTEGER_CLASS;
3838 classes[1] = X86_64_INTEGER_CLASS;
3839 return 1 + (bytes > 8);
3843 /* Examine the argument and return set number of register required in each
3844 class. Return 0 iff parameter should be passed in memory. */
3846 examine_argument (enum machine_mode mode, const_tree type, int in_return,
3847 int *int_nregs, int *sse_nregs)
3849 enum x86_64_reg_class regclass[MAX_CLASSES];
3850 int n = classify_argument (mode, type, regclass, 0);
3856 for (n--; n >= 0; n--)
3857 switch (regclass[n])
3859 case X86_64_INTEGER_CLASS:
3860 case X86_64_INTEGERSI_CLASS:
3863 case X86_64_SSE_CLASS:
3864 case X86_64_SSESF_CLASS:
3865 case X86_64_SSEDF_CLASS:
3868 case X86_64_NO_CLASS:
3869 case X86_64_SSEUP_CLASS:
3871 case X86_64_X87_CLASS:
3872 case X86_64_X87UP_CLASS:
3876 case X86_64_COMPLEX_X87_CLASS:
3877 return in_return ? 2 : 0;
3878 case X86_64_MEMORY_CLASS:
3884 /* Construct container for the argument used by GCC interface. See
3885 FUNCTION_ARG for the detailed description. */
3888 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3889 const_tree type, int in_return, int nintregs, int nsseregs,
3890 const int *intreg, int sse_regno)
3892 /* The following variables hold the static issued_error state. */
3893 static bool issued_sse_arg_error;
3894 static bool issued_sse_ret_error;
3895 static bool issued_x87_ret_error;
3897 enum machine_mode tmpmode;
3899 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3900 enum x86_64_reg_class regclass[MAX_CLASSES];
3904 int needed_sseregs, needed_intregs;
3905 rtx exp[MAX_CLASSES];
3908 n = classify_argument (mode, type, regclass, 0);
3911 if (!examine_argument (mode, type, in_return, &needed_intregs,
3914 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
3917 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
3918 some less clueful developer tries to use floating-point anyway. */
3919 if (needed_sseregs && !TARGET_SSE)
3923 if (!issued_sse_ret_error)
3925 error ("SSE register return with SSE disabled");
3926 issued_sse_ret_error = true;
3929 else if (!issued_sse_arg_error)
3931 error ("SSE register argument with SSE disabled");
3932 issued_sse_arg_error = true;
3937 /* Likewise, error if the ABI requires us to return values in the
3938 x87 registers and the user specified -mno-80387. */
3939 if (!TARGET_80387 && in_return)
3940 for (i = 0; i < n; i++)
3941 if (regclass[i] == X86_64_X87_CLASS
3942 || regclass[i] == X86_64_X87UP_CLASS
3943 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
3945 if (!issued_x87_ret_error)
3947 error ("x87 register return with x87 disabled");
3948 issued_x87_ret_error = true;
3953 /* First construct simple cases. Avoid SCmode, since we want to use
3954 single register to pass this type. */
3955 if (n == 1 && mode != SCmode)
3956 switch (regclass[0])
3958 case X86_64_INTEGER_CLASS:
3959 case X86_64_INTEGERSI_CLASS:
3960 return gen_rtx_REG (mode, intreg[0]);
3961 case X86_64_SSE_CLASS:
3962 case X86_64_SSESF_CLASS:
3963 case X86_64_SSEDF_CLASS:
3964 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
3965 case X86_64_X87_CLASS:
3966 case X86_64_COMPLEX_X87_CLASS:
3967 return gen_rtx_REG (mode, FIRST_STACK_REG);
3968 case X86_64_NO_CLASS:
3969 /* Zero sized array, struct or class. */
3974 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
3975 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
3976 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
3979 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
3980 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
3981 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
3982 && regclass[1] == X86_64_INTEGER_CLASS
3983 && (mode == CDImode || mode == TImode || mode == TFmode)
3984 && intreg[0] + 1 == intreg[1])
3985 return gen_rtx_REG (mode, intreg[0]);
3987 /* Otherwise figure out the entries of the PARALLEL. */
3988 for (i = 0; i < n; i++)
3990 switch (regclass[i])
3992 case X86_64_NO_CLASS:
3994 case X86_64_INTEGER_CLASS:
3995 case X86_64_INTEGERSI_CLASS:
3996 /* Merge TImodes on aligned occasions here too. */
3997 if (i * 8 + 8 > bytes)
3998 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
3999 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
4003 /* We've requested 24 bytes we don't have mode for. Use DImode. */
4004 if (tmpmode == BLKmode)
4006 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4007 gen_rtx_REG (tmpmode, *intreg),
4011 case X86_64_SSESF_CLASS:
4012 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4013 gen_rtx_REG (SFmode,
4014 SSE_REGNO (sse_regno)),
4018 case X86_64_SSEDF_CLASS:
4019 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4020 gen_rtx_REG (DFmode,
4021 SSE_REGNO (sse_regno)),
4025 case X86_64_SSE_CLASS:
4026 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
4030 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4031 gen_rtx_REG (tmpmode,
4032 SSE_REGNO (sse_regno)),
4034 if (tmpmode == TImode)
4043 /* Empty aligned struct, union or class. */
4047 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
4048 for (i = 0; i < nexps; i++)
4049 XVECEXP (ret, 0, i) = exp [i];
4053 /* Update the data in CUM to advance over an argument of mode MODE
4054 and data type TYPE. (TYPE is null for libcalls where that information
4055 may not be available.) */
4058 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4059 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4075 cum->words += words;
4076 cum->nregs -= words;
4077 cum->regno += words;
4079 if (cum->nregs <= 0)
4087 if (cum->float_in_sse < 2)
4090 if (cum->float_in_sse < 1)
4101 if (!type || !AGGREGATE_TYPE_P (type))
4103 cum->sse_words += words;
4104 cum->sse_nregs -= 1;
4105 cum->sse_regno += 1;
4106 if (cum->sse_nregs <= 0)
4118 if (!type || !AGGREGATE_TYPE_P (type))
4120 cum->mmx_words += words;
4121 cum->mmx_nregs -= 1;
4122 cum->mmx_regno += 1;
4123 if (cum->mmx_nregs <= 0)
4134 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4135 tree type, HOST_WIDE_INT words)
4137 int int_nregs, sse_nregs;
4139 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
4140 cum->words += words;
4141 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
4143 cum->nregs -= int_nregs;
4144 cum->sse_nregs -= sse_nregs;
4145 cum->regno += int_nregs;
4146 cum->sse_regno += sse_nregs;
4149 cum->words += words;
4153 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
4154 HOST_WIDE_INT words)
4156 /* Otherwise, this should be passed indirect. */
4157 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
4159 cum->words += words;
4168 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4169 tree type, int named ATTRIBUTE_UNUSED)
4171 HOST_WIDE_INT bytes, words;
4173 if (mode == BLKmode)
4174 bytes = int_size_in_bytes (type);
4176 bytes = GET_MODE_SIZE (mode);
4177 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4180 mode = type_natural_mode (type);
4182 if (TARGET_64BIT_MS_ABI)
4183 function_arg_advance_ms_64 (cum, bytes, words);
4184 else if (TARGET_64BIT)
4185 function_arg_advance_64 (cum, mode, type, words);
4187 function_arg_advance_32 (cum, mode, type, bytes, words);
4190 /* Define where to put the arguments to a function.
4191 Value is zero to push the argument on the stack,
4192 or a hard register in which to store the argument.
4194 MODE is the argument's machine mode.
4195 TYPE is the data type of the argument (as a tree).
4196 This is null for libcalls where that information may
4198 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4199 the preceding args and about the function being called.
4200 NAMED is nonzero if this argument is a named parameter
4201 (otherwise it is an extra parameter matching an ellipsis). */
4204 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4205 enum machine_mode orig_mode, tree type,
4206 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4208 static bool warnedsse, warnedmmx;
4210 /* Avoid the AL settings for the Unix64 ABI. */
4211 if (mode == VOIDmode)
4227 if (words <= cum->nregs)
4229 int regno = cum->regno;
4231 /* Fastcall allocates the first two DWORD (SImode) or
4232 smaller arguments to ECX and EDX. */
4235 if (mode == BLKmode || mode == DImode)
4238 /* ECX not EAX is the first allocated register. */
4239 if (regno == AX_REG)
4242 return gen_rtx_REG (mode, regno);
4247 if (cum->float_in_sse < 2)
4250 if (cum->float_in_sse < 1)
4260 if (!type || !AGGREGATE_TYPE_P (type))
4262 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
4265 warning (0, "SSE vector argument without SSE enabled "
4269 return gen_reg_or_parallel (mode, orig_mode,
4270 cum->sse_regno + FIRST_SSE_REG);
4278 if (!type || !AGGREGATE_TYPE_P (type))
4280 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
4283 warning (0, "MMX vector argument without MMX enabled "
4287 return gen_reg_or_parallel (mode, orig_mode,
4288 cum->mmx_regno + FIRST_MMX_REG);
4297 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4298 enum machine_mode orig_mode, tree type)
4300 /* Handle a hidden AL argument containing number of registers
4301 for varargs x86-64 functions. */
4302 if (mode == VOIDmode)
4303 return GEN_INT (cum->maybe_vaarg
4304 ? (cum->sse_nregs < 0
4309 return construct_container (mode, orig_mode, type, 0, cum->nregs,
4311 &x86_64_int_parameter_registers [cum->regno],
4316 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4317 enum machine_mode orig_mode, int named)
4321 /* Avoid the AL settings for the Unix64 ABI. */
4322 if (mode == VOIDmode)
4325 /* If we've run out of registers, it goes on the stack. */
4326 if (cum->nregs == 0)
4329 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4331 /* Only floating point modes are passed in anything but integer regs. */
4332 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4335 regno = cum->regno + FIRST_SSE_REG;
4340 /* Unnamed floating parameters are passed in both the
4341 SSE and integer registers. */
4342 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4343 t2 = gen_rtx_REG (mode, regno);
4344 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4345 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4346 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4350 return gen_reg_or_parallel (mode, orig_mode, regno);
4354 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4355 tree type, int named)
4357 enum machine_mode mode = omode;
4358 HOST_WIDE_INT bytes, words;
4360 if (mode == BLKmode)
4361 bytes = int_size_in_bytes (type);
4363 bytes = GET_MODE_SIZE (mode);
4364 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4366 /* To simplify the code below, represent vector types with a vector mode
4367 even if MMX/SSE are not active. */
4368 if (type && TREE_CODE (type) == VECTOR_TYPE)
4369 mode = type_natural_mode (type);
4371 if (TARGET_64BIT_MS_ABI)
4372 return function_arg_ms_64 (cum, mode, omode, named);
4373 else if (TARGET_64BIT)
4374 return function_arg_64 (cum, mode, omode, type);
4376 return function_arg_32 (cum, mode, omode, type, bytes, words);
4379 /* A C expression that indicates when an argument must be passed by
4380 reference. If nonzero for an argument, a copy of that argument is
4381 made in memory and a pointer to the argument is passed instead of
4382 the argument itself. The pointer is passed in whatever way is
4383 appropriate for passing a pointer to that type. */
4386 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4387 enum machine_mode mode ATTRIBUTE_UNUSED,
4388 const_tree type, bool named ATTRIBUTE_UNUSED)
4390 if (TARGET_64BIT_MS_ABI)
4394 /* Arrays are passed by reference. */
4395 if (TREE_CODE (type) == ARRAY_TYPE)
4398 if (AGGREGATE_TYPE_P (type))
4400 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4401 are passed by reference. */
4402 int el2 = exact_log2 (int_size_in_bytes (type));
4403 return !(el2 >= 0 && el2 <= 3);
4407 /* __m128 is passed by reference. */
4408 /* ??? How to handle complex? For now treat them as structs,
4409 and pass them by reference if they're too large. */
4410 if (GET_MODE_SIZE (mode) > 8)
4413 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4419 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4420 ABI. Only called if TARGET_SSE. */
4422 contains_128bit_aligned_vector_p (tree type)
4424 enum machine_mode mode = TYPE_MODE (type);
4425 if (SSE_REG_MODE_P (mode)
4426 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4428 if (TYPE_ALIGN (type) < 128)
4431 if (AGGREGATE_TYPE_P (type))
4433 /* Walk the aggregates recursively. */
4434 switch (TREE_CODE (type))
4438 case QUAL_UNION_TYPE:
4442 /* Walk all the structure fields. */
4443 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4445 if (TREE_CODE (field) == FIELD_DECL
4446 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
4453 /* Just for use if some languages passes arrays by value. */
4454 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
4465 /* Gives the alignment boundary, in bits, of an argument with the
4466 specified mode and type. */
4469 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4473 align = TYPE_ALIGN (type);
4475 align = GET_MODE_ALIGNMENT (mode);
4476 if (align < PARM_BOUNDARY)
4477 align = PARM_BOUNDARY;
4480 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4481 make an exception for SSE modes since these require 128bit
4484 The handling here differs from field_alignment. ICC aligns MMX
4485 arguments to 4 byte boundaries, while structure fields are aligned
4486 to 8 byte boundaries. */
4488 align = PARM_BOUNDARY;
4491 if (!SSE_REG_MODE_P (mode))
4492 align = PARM_BOUNDARY;
4496 if (!contains_128bit_aligned_vector_p (type))
4497 align = PARM_BOUNDARY;
4505 /* Return true if N is a possible register number of function value. */
4508 ix86_function_value_regno_p (int regno)
4515 case FIRST_FLOAT_REG:
4516 if (TARGET_64BIT_MS_ABI)
4518 return TARGET_FLOAT_RETURNS_IN_80387;
4524 if (TARGET_MACHO || TARGET_64BIT)
4532 /* Define how to find the value returned by a function.
4533 VALTYPE is the data type of the value (as a tree).
4534 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4535 otherwise, FUNC is 0. */
4538 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4539 const_tree fntype, const_tree fn)
4543 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4544 we normally prevent this case when mmx is not available. However
4545 some ABIs may require the result to be returned like DImode. */
4546 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4547 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4549 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4550 we prevent this case when sse is not available. However some ABIs
4551 may require the result to be returned like integer TImode. */
4552 else if (mode == TImode
4553 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4554 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4556 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4557 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4558 regno = FIRST_FLOAT_REG;
4560 /* Most things go in %eax. */
4563 /* Override FP return register with %xmm0 for local functions when
4564 SSE math is enabled or for functions with sseregparm attribute. */
4565 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4567 int sse_level = ix86_function_sseregparm (fntype, fn);
4568 if ((sse_level >= 1 && mode == SFmode)
4569 || (sse_level == 2 && mode == DFmode))
4570 regno = FIRST_SSE_REG;
4573 return gen_rtx_REG (orig_mode, regno);
4577 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4582 /* Handle libcalls, which don't provide a type node. */
4583 if (valtype == NULL)
4595 return gen_rtx_REG (mode, FIRST_SSE_REG);
4598 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4602 return gen_rtx_REG (mode, AX_REG);
4606 ret = construct_container (mode, orig_mode, valtype, 1,
4607 REGPARM_MAX, SSE_REGPARM_MAX,
4608 x86_64_int_return_registers, 0);
4610 /* For zero sized structures, construct_container returns NULL, but we
4611 need to keep rest of compiler happy by returning meaningful value. */
4613 ret = gen_rtx_REG (orig_mode, AX_REG);
4619 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4621 unsigned int regno = AX_REG;
4625 if (mode == SFmode || mode == DFmode)
4626 regno = FIRST_SSE_REG;
4627 else if (VECTOR_MODE_P (mode) || GET_MODE_SIZE (mode) == 16)
4628 regno = FIRST_SSE_REG;
4631 return gen_rtx_REG (orig_mode, regno);
4635 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
4636 enum machine_mode orig_mode, enum machine_mode mode)
4638 const_tree fn, fntype;
4641 if (fntype_or_decl && DECL_P (fntype_or_decl))
4642 fn = fntype_or_decl;
4643 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4645 if (TARGET_64BIT_MS_ABI)
4646 return function_value_ms_64 (orig_mode, mode);
4647 else if (TARGET_64BIT)
4648 return function_value_64 (orig_mode, mode, valtype);
4650 return function_value_32 (orig_mode, mode, fntype, fn);
4654 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
4655 bool outgoing ATTRIBUTE_UNUSED)
4657 enum machine_mode mode, orig_mode;
4659 orig_mode = TYPE_MODE (valtype);
4660 mode = type_natural_mode (valtype);
4661 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
4665 ix86_libcall_value (enum machine_mode mode)
4667 return ix86_function_value_1 (NULL, NULL, mode, mode);
4670 /* Return true iff type is returned in memory. */
4673 return_in_memory_32 (const_tree type, enum machine_mode mode)
4677 if (mode == BLKmode)
4680 size = int_size_in_bytes (type);
4682 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4685 if (VECTOR_MODE_P (mode) || mode == TImode)
4687 /* User-created vectors small enough to fit in EAX. */
4691 /* MMX/3dNow values are returned in MM0,
4692 except when it doesn't exits. */
4694 return (TARGET_MMX ? 0 : 1);
4696 /* SSE values are returned in XMM0, except when it doesn't exist. */
4698 return (TARGET_SSE ? 0 : 1);
4713 return_in_memory_64 (const_tree type, enum machine_mode mode)
4715 int needed_intregs, needed_sseregs;
4716 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4720 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
4722 HOST_WIDE_INT size = int_size_in_bytes (type);
4724 /* __m128 and friends are returned in xmm0. */
4725 if (!COMPLEX_MODE_P (mode) && size == 16 && VECTOR_MODE_P (mode))
4728 /* Otherwise, the size must be exactly in [1248]. But not for complex. */
4729 return (size != 1 && size != 2 && size != 4 && size != 8)
4730 || COMPLEX_MODE_P (mode);
4734 ix86_return_in_memory (const_tree type)
4736 const enum machine_mode mode = type_natural_mode (type);
4738 if (TARGET_64BIT_MS_ABI)
4739 return return_in_memory_ms_64 (type, mode);
4740 else if (TARGET_64BIT)
4741 return return_in_memory_64 (type, mode);
4743 return return_in_memory_32 (type, mode);
4746 /* Return false iff TYPE is returned in memory. This version is used
4747 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4748 but differs notably in that when MMX is available, 8-byte vectors
4749 are returned in memory, rather than in MMX registers. */
4752 ix86_sol10_return_in_memory (const_tree type)
4755 enum machine_mode mode = type_natural_mode (type);
4758 return return_in_memory_64 (type, mode);
4760 if (mode == BLKmode)
4763 size = int_size_in_bytes (type);
4765 if (VECTOR_MODE_P (mode))
4767 /* Return in memory only if MMX registers *are* available. This
4768 seems backwards, but it is consistent with the existing
4775 else if (mode == TImode)
4777 else if (mode == XFmode)
4783 /* When returning SSE vector types, we have a choice of either
4784 (1) being abi incompatible with a -march switch, or
4785 (2) generating an error.
4786 Given no good solution, I think the safest thing is one warning.
4787 The user won't be able to use -Werror, but....
4789 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4790 called in response to actually generating a caller or callee that
4791 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4792 via aggregate_value_p for general type probing from tree-ssa. */
4795 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4797 static bool warnedsse, warnedmmx;
4799 if (!TARGET_64BIT && type)
4801 /* Look at the return type of the function, not the function type. */
4802 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4804 if (!TARGET_SSE && !warnedsse)
4807 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4810 warning (0, "SSE vector return without SSE enabled "
4815 if (!TARGET_MMX && !warnedmmx)
4817 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4820 warning (0, "MMX vector return without MMX enabled "
4830 /* Create the va_list data type. */
4833 ix86_build_builtin_va_list (void)
4835 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
4837 /* For i386 we use plain pointer to argument area. */
4838 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4839 return build_pointer_type (char_type_node);
4841 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4842 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4844 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
4845 unsigned_type_node);
4846 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
4847 unsigned_type_node);
4848 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4850 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4853 va_list_gpr_counter_field = f_gpr;
4854 va_list_fpr_counter_field = f_fpr;
4856 DECL_FIELD_CONTEXT (f_gpr) = record;
4857 DECL_FIELD_CONTEXT (f_fpr) = record;
4858 DECL_FIELD_CONTEXT (f_ovf) = record;
4859 DECL_FIELD_CONTEXT (f_sav) = record;
4861 TREE_CHAIN (record) = type_decl;
4862 TYPE_NAME (record) = type_decl;
4863 TYPE_FIELDS (record) = f_gpr;
4864 TREE_CHAIN (f_gpr) = f_fpr;
4865 TREE_CHAIN (f_fpr) = f_ovf;
4866 TREE_CHAIN (f_ovf) = f_sav;
4868 layout_type (record);
4870 /* The correct type is an array type of one element. */
4871 return build_array_type (record, build_index_type (size_zero_node));
4874 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4877 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
4887 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4890 /* Indicate to allocate space on the stack for varargs save area. */
4891 ix86_save_varrargs_registers = 1;
4892 /* We need 16-byte stack alignment to save SSE registers. If user
4893 asked for lower preferred_stack_boundary, lets just hope that he knows
4894 what he is doing and won't varargs SSE values.
4896 We also may end up assuming that only 64bit values are stored in SSE
4897 register let some floating point program work. */
4898 if (ix86_preferred_stack_boundary >= 128)
4899 cfun->stack_alignment_needed = 128;
4901 save_area = frame_pointer_rtx;
4902 set = get_varargs_alias_set ();
4904 for (i = cum->regno;
4906 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
4909 mem = gen_rtx_MEM (Pmode,
4910 plus_constant (save_area, i * UNITS_PER_WORD));
4911 MEM_NOTRAP_P (mem) = 1;
4912 set_mem_alias_set (mem, set);
4913 emit_move_insn (mem, gen_rtx_REG (Pmode,
4914 x86_64_int_parameter_registers[i]));
4917 if (cum->sse_nregs && cfun->va_list_fpr_size)
4919 /* Now emit code to save SSE registers. The AX parameter contains number
4920 of SSE parameter registers used to call this function. We use
4921 sse_prologue_save insn template that produces computed jump across
4922 SSE saves. We need some preparation work to get this working. */
4924 label = gen_label_rtx ();
4925 label_ref = gen_rtx_LABEL_REF (Pmode, label);
4927 /* Compute address to jump to :
4928 label - 5*eax + nnamed_sse_arguments*5 */
4929 tmp_reg = gen_reg_rtx (Pmode);
4930 nsse_reg = gen_reg_rtx (Pmode);
4931 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
4932 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4933 gen_rtx_MULT (Pmode, nsse_reg,
4938 gen_rtx_CONST (DImode,
4939 gen_rtx_PLUS (DImode,
4941 GEN_INT (cum->sse_regno * 4))));
4943 emit_move_insn (nsse_reg, label_ref);
4944 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
4946 /* Compute address of memory block we save into. We always use pointer
4947 pointing 127 bytes after first byte to store - this is needed to keep
4948 instruction size limited by 4 bytes. */
4949 tmp_reg = gen_reg_rtx (Pmode);
4950 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4951 plus_constant (save_area,
4952 8 * REGPARM_MAX + 127)));
4953 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
4954 MEM_NOTRAP_P (mem) = 1;
4955 set_mem_alias_set (mem, set);
4956 set_mem_align (mem, BITS_PER_WORD);
4958 /* And finally do the dirty job! */
4959 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
4960 GEN_INT (cum->sse_regno), label));
4965 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
4967 alias_set_type set = get_varargs_alias_set ();
4970 for (i = cum->regno; i < REGPARM_MAX; i++)
4974 mem = gen_rtx_MEM (Pmode,
4975 plus_constant (virtual_incoming_args_rtx,
4976 i * UNITS_PER_WORD));
4977 MEM_NOTRAP_P (mem) = 1;
4978 set_mem_alias_set (mem, set);
4980 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
4981 emit_move_insn (mem, reg);
4986 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4987 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4990 CUMULATIVE_ARGS next_cum;
4993 /* This argument doesn't appear to be used anymore. Which is good,
4994 because the old code here didn't suppress rtl generation. */
4995 gcc_assert (!no_rtl);
5000 fntype = TREE_TYPE (current_function_decl);
5002 /* For varargs, we do not want to skip the dummy va_dcl argument.
5003 For stdargs, we do want to skip the last named argument. */
5005 if (stdarg_p (fntype))
5006 function_arg_advance (&next_cum, mode, type, 1);
5008 if (TARGET_64BIT_MS_ABI)
5009 setup_incoming_varargs_ms_64 (&next_cum);
5011 setup_incoming_varargs_64 (&next_cum);
5014 /* Implement va_start. */
5017 ix86_va_start (tree valist, rtx nextarg)
5019 HOST_WIDE_INT words, n_gpr, n_fpr;
5020 tree f_gpr, f_fpr, f_ovf, f_sav;
5021 tree gpr, fpr, ovf, sav, t;
5024 /* Only 64bit target needs something special. */
5025 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5027 std_expand_builtin_va_start (valist, nextarg);
5031 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5032 f_fpr = TREE_CHAIN (f_gpr);
5033 f_ovf = TREE_CHAIN (f_fpr);
5034 f_sav = TREE_CHAIN (f_ovf);
5036 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5037 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5038 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5039 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5040 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5042 /* Count number of gp and fp argument registers used. */
5043 words = current_function_args_info.words;
5044 n_gpr = current_function_args_info.regno;
5045 n_fpr = current_function_args_info.sse_regno;
5047 if (cfun->va_list_gpr_size)
5049 type = TREE_TYPE (gpr);
5050 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
5051 build_int_cst (type, n_gpr * 8));
5052 TREE_SIDE_EFFECTS (t) = 1;
5053 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5056 if (cfun->va_list_fpr_size)
5058 type = TREE_TYPE (fpr);
5059 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
5060 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
5061 TREE_SIDE_EFFECTS (t) = 1;
5062 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5065 /* Find the overflow area. */
5066 type = TREE_TYPE (ovf);
5067 t = make_tree (type, virtual_incoming_args_rtx);
5069 t = build2 (POINTER_PLUS_EXPR, type, t,
5070 size_int (words * UNITS_PER_WORD));
5071 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
5072 TREE_SIDE_EFFECTS (t) = 1;
5073 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5075 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
5077 /* Find the register save area.
5078 Prologue of the function save it right above stack frame. */
5079 type = TREE_TYPE (sav);
5080 t = make_tree (type, frame_pointer_rtx);
5081 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
5082 TREE_SIDE_EFFECTS (t) = 1;
5083 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5087 /* Implement va_arg. */
5090 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5092 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
5093 tree f_gpr, f_fpr, f_ovf, f_sav;
5094 tree gpr, fpr, ovf, sav, t;
5096 tree lab_false, lab_over = NULL_TREE;
5101 enum machine_mode nat_mode;
5103 /* Only 64bit target needs something special. */
5104 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5105 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5107 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5108 f_fpr = TREE_CHAIN (f_gpr);
5109 f_ovf = TREE_CHAIN (f_fpr);
5110 f_sav = TREE_CHAIN (f_ovf);
5112 valist = build_va_arg_indirect_ref (valist);
5113 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5114 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5115 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5116 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5118 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5120 type = build_pointer_type (type);
5121 size = int_size_in_bytes (type);
5122 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5124 nat_mode = type_natural_mode (type);
5125 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
5126 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
5128 /* Pull the value out of the saved registers. */
5130 addr = create_tmp_var (ptr_type_node, "addr");
5131 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5135 int needed_intregs, needed_sseregs;
5137 tree int_addr, sse_addr;
5139 lab_false = create_artificial_label ();
5140 lab_over = create_artificial_label ();
5142 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
5144 need_temp = (!REG_P (container)
5145 && ((needed_intregs && TYPE_ALIGN (type) > 64)
5146 || TYPE_ALIGN (type) > 128));
5148 /* In case we are passing structure, verify that it is consecutive block
5149 on the register save area. If not we need to do moves. */
5150 if (!need_temp && !REG_P (container))
5152 /* Verify that all registers are strictly consecutive */
5153 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
5157 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5159 rtx slot = XVECEXP (container, 0, i);
5160 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
5161 || INTVAL (XEXP (slot, 1)) != i * 16)
5169 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5171 rtx slot = XVECEXP (container, 0, i);
5172 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
5173 || INTVAL (XEXP (slot, 1)) != i * 8)
5185 int_addr = create_tmp_var (ptr_type_node, "int_addr");
5186 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
5187 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
5188 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
5191 /* First ensure that we fit completely in registers. */
5194 t = build_int_cst (TREE_TYPE (gpr),
5195 (REGPARM_MAX - needed_intregs + 1) * 8);
5196 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
5197 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5198 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5199 gimplify_and_add (t, pre_p);
5203 t = build_int_cst (TREE_TYPE (fpr),
5204 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
5206 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
5207 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5208 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5209 gimplify_and_add (t, pre_p);
5212 /* Compute index to start of area used for integer regs. */
5215 /* int_addr = gpr + sav; */
5216 t = fold_convert (sizetype, gpr);
5217 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5218 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
5219 gimplify_and_add (t, pre_p);
5223 /* sse_addr = fpr + sav; */
5224 t = fold_convert (sizetype, fpr);
5225 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5226 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
5227 gimplify_and_add (t, pre_p);
5232 tree temp = create_tmp_var (type, "va_arg_tmp");
5235 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
5236 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5237 gimplify_and_add (t, pre_p);
5239 for (i = 0; i < XVECLEN (container, 0); i++)
5241 rtx slot = XVECEXP (container, 0, i);
5242 rtx reg = XEXP (slot, 0);
5243 enum machine_mode mode = GET_MODE (reg);
5244 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
5245 tree addr_type = build_pointer_type (piece_type);
5248 tree dest_addr, dest;
5250 if (SSE_REGNO_P (REGNO (reg)))
5252 src_addr = sse_addr;
5253 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
5257 src_addr = int_addr;
5258 src_offset = REGNO (reg) * 8;
5260 src_addr = fold_convert (addr_type, src_addr);
5261 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
5262 size_int (src_offset));
5263 src = build_va_arg_indirect_ref (src_addr);
5265 dest_addr = fold_convert (addr_type, addr);
5266 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
5267 size_int (INTVAL (XEXP (slot, 1))));
5268 dest = build_va_arg_indirect_ref (dest_addr);
5270 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
5271 gimplify_and_add (t, pre_p);
5277 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
5278 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
5279 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
5280 gimplify_and_add (t, pre_p);
5284 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
5285 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
5286 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
5287 gimplify_and_add (t, pre_p);
5290 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5291 gimplify_and_add (t, pre_p);
5293 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5294 append_to_statement_list (t, pre_p);
5297 /* ... otherwise out of the overflow area. */
5299 /* Care for on-stack alignment if needed. */
5300 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
5301 || integer_zerop (TYPE_SIZE (type)))
5305 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
5306 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
5307 size_int (align - 1));
5308 t = fold_convert (sizetype, t);
5309 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5311 t = fold_convert (TREE_TYPE (ovf), t);
5313 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5315 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5316 gimplify_and_add (t2, pre_p);
5318 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
5319 size_int (rsize * UNITS_PER_WORD));
5320 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
5321 gimplify_and_add (t, pre_p);
5325 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5326 append_to_statement_list (t, pre_p);
5329 ptrtype = build_pointer_type (type);
5330 addr = fold_convert (ptrtype, addr);
5333 addr = build_va_arg_indirect_ref (addr);
5334 return build_va_arg_indirect_ref (addr);
5337 /* Return nonzero if OPNUM's MEM should be matched
5338 in movabs* patterns. */
5341 ix86_check_movabs (rtx insn, int opnum)
5345 set = PATTERN (insn);
5346 if (GET_CODE (set) == PARALLEL)
5347 set = XVECEXP (set, 0, 0);
5348 gcc_assert (GET_CODE (set) == SET);
5349 mem = XEXP (set, opnum);
5350 while (GET_CODE (mem) == SUBREG)
5351 mem = SUBREG_REG (mem);
5352 gcc_assert (MEM_P (mem));
5353 return (volatile_ok || !MEM_VOLATILE_P (mem));
5356 /* Initialize the table of extra 80387 mathematical constants. */
5359 init_ext_80387_constants (void)
5361 static const char * cst[5] =
5363 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5364 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5365 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5366 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5367 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5371 for (i = 0; i < 5; i++)
5373 real_from_string (&ext_80387_constants_table[i], cst[i]);
5374 /* Ensure each constant is rounded to XFmode precision. */
5375 real_convert (&ext_80387_constants_table[i],
5376 XFmode, &ext_80387_constants_table[i]);
5379 ext_80387_constants_init = 1;
5382 /* Return true if the constant is something that can be loaded with
5383 a special instruction. */
5386 standard_80387_constant_p (rtx x)
5388 enum machine_mode mode = GET_MODE (x);
5392 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5395 if (x == CONST0_RTX (mode))
5397 if (x == CONST1_RTX (mode))
5400 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5402 /* For XFmode constants, try to find a special 80387 instruction when
5403 optimizing for size or on those CPUs that benefit from them. */
5405 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5409 if (! ext_80387_constants_init)
5410 init_ext_80387_constants ();
5412 for (i = 0; i < 5; i++)
5413 if (real_identical (&r, &ext_80387_constants_table[i]))
5417 /* Load of the constant -0.0 or -1.0 will be split as
5418 fldz;fchs or fld1;fchs sequence. */
5419 if (real_isnegzero (&r))
5421 if (real_identical (&r, &dconstm1))
5427 /* Return the opcode of the special instruction to be used to load
5431 standard_80387_constant_opcode (rtx x)
5433 switch (standard_80387_constant_p (x))
5457 /* Return the CONST_DOUBLE representing the 80387 constant that is
5458 loaded by the specified special instruction. The argument IDX
5459 matches the return value from standard_80387_constant_p. */
5462 standard_80387_constant_rtx (int idx)
5466 if (! ext_80387_constants_init)
5467 init_ext_80387_constants ();
5483 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5487 /* Return 1 if mode is a valid mode for sse. */
5489 standard_sse_mode_p (enum machine_mode mode)
5506 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5509 standard_sse_constant_p (rtx x)
5511 enum machine_mode mode = GET_MODE (x);
5513 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5515 if (vector_all_ones_operand (x, mode)
5516 && standard_sse_mode_p (mode))
5517 return TARGET_SSE2 ? 2 : -1;
5522 /* Return the opcode of the special instruction to be used to load
5526 standard_sse_constant_opcode (rtx insn, rtx x)
5528 switch (standard_sse_constant_p (x))
5531 if (get_attr_mode (insn) == MODE_V4SF)
5532 return "xorps\t%0, %0";
5533 else if (get_attr_mode (insn) == MODE_V2DF)
5534 return "xorpd\t%0, %0";
5536 return "pxor\t%0, %0";
5538 return "pcmpeqd\t%0, %0";
5543 /* Returns 1 if OP contains a symbol reference */
5546 symbolic_reference_mentioned_p (rtx op)
5551 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5554 fmt = GET_RTX_FORMAT (GET_CODE (op));
5555 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5561 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5562 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5566 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5573 /* Return 1 if it is appropriate to emit `ret' instructions in the
5574 body of a function. Do this only if the epilogue is simple, needing a
5575 couple of insns. Prior to reloading, we can't tell how many registers
5576 must be saved, so return 0 then. Return 0 if there is no frame
5577 marker to de-allocate. */
5580 ix86_can_use_return_insn_p (void)
5582 struct ix86_frame frame;
5584 if (! reload_completed || frame_pointer_needed)
5587 /* Don't allow more than 32 pop, since that's all we can do
5588 with one instruction. */
5589 if (current_function_pops_args
5590 && current_function_args_size >= 32768)
5593 ix86_compute_frame_layout (&frame);
5594 return frame.to_allocate == 0 && frame.nregs == 0;
5597 /* Value should be nonzero if functions must have frame pointers.
5598 Zero means the frame pointer need not be set up (and parms may
5599 be accessed via the stack pointer) in functions that seem suitable. */
5602 ix86_frame_pointer_required (void)
5604 /* If we accessed previous frames, then the generated code expects
5605 to be able to access the saved ebp value in our frame. */
5606 if (cfun->machine->accesses_prev_frame)
5609 /* Several x86 os'es need a frame pointer for other reasons,
5610 usually pertaining to setjmp. */
5611 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5614 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5615 the frame pointer by default. Turn it back on now if we've not
5616 got a leaf function. */
5617 if (TARGET_OMIT_LEAF_FRAME_POINTER
5618 && (!current_function_is_leaf
5619 || ix86_current_function_calls_tls_descriptor))
5622 if (current_function_profile)
5628 /* Record that the current function accesses previous call frames. */
5631 ix86_setup_frame_addresses (void)
5633 cfun->machine->accesses_prev_frame = 1;
5636 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5637 # define USE_HIDDEN_LINKONCE 1
5639 # define USE_HIDDEN_LINKONCE 0
5642 static int pic_labels_used;
5644 /* Fills in the label name that should be used for a pc thunk for
5645 the given register. */
5648 get_pc_thunk_name (char name[32], unsigned int regno)
5650 gcc_assert (!TARGET_64BIT);
5652 if (USE_HIDDEN_LINKONCE)
5653 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5655 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5659 /* This function generates code for -fpic that loads %ebx with
5660 the return address of the caller and then returns. */
5663 ix86_file_end (void)
5668 for (regno = 0; regno < 8; ++regno)
5672 if (! ((pic_labels_used >> regno) & 1))
5675 get_pc_thunk_name (name, regno);
5680 switch_to_section (darwin_sections[text_coal_section]);
5681 fputs ("\t.weak_definition\t", asm_out_file);
5682 assemble_name (asm_out_file, name);
5683 fputs ("\n\t.private_extern\t", asm_out_file);
5684 assemble_name (asm_out_file, name);
5685 fputs ("\n", asm_out_file);
5686 ASM_OUTPUT_LABEL (asm_out_file, name);
5690 if (USE_HIDDEN_LINKONCE)
5694 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5696 TREE_PUBLIC (decl) = 1;
5697 TREE_STATIC (decl) = 1;
5698 DECL_ONE_ONLY (decl) = 1;
5700 (*targetm.asm_out.unique_section) (decl, 0);
5701 switch_to_section (get_named_section (decl, NULL, 0));
5703 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5704 fputs ("\t.hidden\t", asm_out_file);
5705 assemble_name (asm_out_file, name);
5706 fputc ('\n', asm_out_file);
5707 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5711 switch_to_section (text_section);
5712 ASM_OUTPUT_LABEL (asm_out_file, name);
5715 xops[0] = gen_rtx_REG (SImode, regno);
5716 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
5717 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5718 output_asm_insn ("ret", xops);
5721 if (NEED_INDICATE_EXEC_STACK)
5722 file_end_indicate_exec_stack ();
5725 /* Emit code for the SET_GOT patterns. */
5728 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5734 if (TARGET_VXWORKS_RTP && flag_pic)
5736 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5737 xops[2] = gen_rtx_MEM (Pmode,
5738 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
5739 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5741 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5742 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5743 an unadorned address. */
5744 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5745 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
5746 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
5750 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5752 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5754 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5757 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5759 output_asm_insn ("call\t%a2", xops);
5762 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5763 is what will be referenced by the Mach-O PIC subsystem. */
5765 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5768 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5769 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5772 output_asm_insn ("pop{l}\t%0", xops);
5777 get_pc_thunk_name (name, REGNO (dest));
5778 pic_labels_used |= 1 << REGNO (dest);
5780 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5781 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5782 output_asm_insn ("call\t%X2", xops);
5783 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5784 is what will be referenced by the Mach-O PIC subsystem. */
5787 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5789 targetm.asm_out.internal_label (asm_out_file, "L",
5790 CODE_LABEL_NUMBER (label));
5797 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5798 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
5800 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
5805 /* Generate an "push" pattern for input ARG. */
5810 return gen_rtx_SET (VOIDmode,
5812 gen_rtx_PRE_DEC (Pmode,
5813 stack_pointer_rtx)),
5817 /* Return >= 0 if there is an unused call-clobbered register available
5818 for the entire function. */
5821 ix86_select_alt_pic_regnum (void)
5823 if (current_function_is_leaf && !current_function_profile
5824 && !ix86_current_function_calls_tls_descriptor)
5827 for (i = 2; i >= 0; --i)
5828 if (!df_regs_ever_live_p (i))
5832 return INVALID_REGNUM;
5835 /* Return 1 if we need to save REGNO. */
5837 ix86_save_reg (unsigned int regno, int maybe_eh_return)
5839 if (pic_offset_table_rtx
5840 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
5841 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
5842 || current_function_profile
5843 || current_function_calls_eh_return
5844 || current_function_uses_const_pool))
5846 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
5851 if (current_function_calls_eh_return && maybe_eh_return)
5856 unsigned test = EH_RETURN_DATA_REGNO (i);
5857 if (test == INVALID_REGNUM)
5864 if (cfun->machine->force_align_arg_pointer
5865 && regno == REGNO (cfun->machine->force_align_arg_pointer))
5868 return (df_regs_ever_live_p (regno)
5869 && !call_used_regs[regno]
5870 && !fixed_regs[regno]
5871 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
5874 /* Return number of registers to be saved on the stack. */
5877 ix86_nsaved_regs (void)
5882 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
5883 if (ix86_save_reg (regno, true))
5888 /* Return the offset between two registers, one to be eliminated, and the other
5889 its replacement, at the start of a routine. */
5892 ix86_initial_elimination_offset (int from, int to)
5894 struct ix86_frame frame;
5895 ix86_compute_frame_layout (&frame);
5897 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
5898 return frame.hard_frame_pointer_offset;
5899 else if (from == FRAME_POINTER_REGNUM
5900 && to == HARD_FRAME_POINTER_REGNUM)
5901 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
5904 gcc_assert (to == STACK_POINTER_REGNUM);
5906 if (from == ARG_POINTER_REGNUM)
5907 return frame.stack_pointer_offset;
5909 gcc_assert (from == FRAME_POINTER_REGNUM);
5910 return frame.stack_pointer_offset - frame.frame_pointer_offset;
5914 /* Fill structure ix86_frame about frame of currently computed function. */
5917 ix86_compute_frame_layout (struct ix86_frame *frame)
5919 HOST_WIDE_INT total_size;
5920 unsigned int stack_alignment_needed;
5921 HOST_WIDE_INT offset;
5922 unsigned int preferred_alignment;
5923 HOST_WIDE_INT size = get_frame_size ();
5925 frame->nregs = ix86_nsaved_regs ();
5928 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
5929 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
5931 /* During reload iteration the amount of registers saved can change.
5932 Recompute the value as needed. Do not recompute when amount of registers
5933 didn't change as reload does multiple calls to the function and does not
5934 expect the decision to change within single iteration. */
5936 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
5938 int count = frame->nregs;
5940 cfun->machine->use_fast_prologue_epilogue_nregs = count;
5941 /* The fast prologue uses move instead of push to save registers. This
5942 is significantly longer, but also executes faster as modern hardware
5943 can execute the moves in parallel, but can't do that for push/pop.
5945 Be careful about choosing what prologue to emit: When function takes
5946 many instructions to execute we may use slow version as well as in
5947 case function is known to be outside hot spot (this is known with
5948 feedback only). Weight the size of function by number of registers
5949 to save as it is cheap to use one or two push instructions but very
5950 slow to use many of them. */
5952 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
5953 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
5954 || (flag_branch_probabilities
5955 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
5956 cfun->machine->use_fast_prologue_epilogue = false;
5958 cfun->machine->use_fast_prologue_epilogue
5959 = !expensive_function_p (count);
5961 if (TARGET_PROLOGUE_USING_MOVE
5962 && cfun->machine->use_fast_prologue_epilogue)
5963 frame->save_regs_using_mov = true;
5965 frame->save_regs_using_mov = false;
5968 /* Skip return address and saved base pointer. */
5969 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
5971 frame->hard_frame_pointer_offset = offset;
5973 /* Do some sanity checking of stack_alignment_needed and
5974 preferred_alignment, since i386 port is the only using those features
5975 that may break easily. */
5977 gcc_assert (!size || stack_alignment_needed);
5978 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
5979 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5980 gcc_assert (stack_alignment_needed
5981 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5983 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
5984 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
5986 /* Register save area */
5987 offset += frame->nregs * UNITS_PER_WORD;
5990 if (ix86_save_varrargs_registers)
5992 offset += X86_64_VARARGS_SIZE;
5993 frame->va_arg_size = X86_64_VARARGS_SIZE;
5996 frame->va_arg_size = 0;
5998 /* Align start of frame for local function. */
5999 frame->padding1 = ((offset + stack_alignment_needed - 1)
6000 & -stack_alignment_needed) - offset;
6002 offset += frame->padding1;
6004 /* Frame pointer points here. */
6005 frame->frame_pointer_offset = offset;
6009 /* Add outgoing arguments area. Can be skipped if we eliminated
6010 all the function calls as dead code.
6011 Skipping is however impossible when function calls alloca. Alloca
6012 expander assumes that last current_function_outgoing_args_size
6013 of stack frame are unused. */
6014 if (ACCUMULATE_OUTGOING_ARGS
6015 && (!current_function_is_leaf || current_function_calls_alloca
6016 || ix86_current_function_calls_tls_descriptor))
6018 offset += current_function_outgoing_args_size;
6019 frame->outgoing_arguments_size = current_function_outgoing_args_size;
6022 frame->outgoing_arguments_size = 0;
6024 /* Align stack boundary. Only needed if we're calling another function
6026 if (!current_function_is_leaf || current_function_calls_alloca
6027 || ix86_current_function_calls_tls_descriptor)
6028 frame->padding2 = ((offset + preferred_alignment - 1)
6029 & -preferred_alignment) - offset;
6031 frame->padding2 = 0;
6033 offset += frame->padding2;
6035 /* We've reached end of stack frame. */
6036 frame->stack_pointer_offset = offset;
6038 /* Size prologue needs to allocate. */
6039 frame->to_allocate =
6040 (size + frame->padding1 + frame->padding2
6041 + frame->outgoing_arguments_size + frame->va_arg_size);
6043 if ((!frame->to_allocate && frame->nregs <= 1)
6044 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
6045 frame->save_regs_using_mov = false;
6047 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
6048 && current_function_is_leaf
6049 && !ix86_current_function_calls_tls_descriptor)
6051 frame->red_zone_size = frame->to_allocate;
6052 if (frame->save_regs_using_mov)
6053 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
6054 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
6055 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
6058 frame->red_zone_size = 0;
6059 frame->to_allocate -= frame->red_zone_size;
6060 frame->stack_pointer_offset -= frame->red_zone_size;
6062 fprintf (stderr, "\n");
6063 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
6064 fprintf (stderr, "size: %ld\n", (long)size);
6065 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
6066 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
6067 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
6068 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
6069 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
6070 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
6071 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
6072 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
6073 (long)frame->hard_frame_pointer_offset);
6074 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
6075 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
6076 fprintf (stderr, "current_function_calls_alloca: %ld\n", (long)current_function_calls_alloca);
6077 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
6081 /* Emit code to save registers in the prologue. */
6084 ix86_emit_save_regs (void)
6089 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
6090 if (ix86_save_reg (regno, true))
6092 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
6093 RTX_FRAME_RELATED_P (insn) = 1;
6097 /* Emit code to save registers using MOV insns. First register
6098 is restored from POINTER + OFFSET. */
6100 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
6105 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6106 if (ix86_save_reg (regno, true))
6108 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
6110 gen_rtx_REG (Pmode, regno));
6111 RTX_FRAME_RELATED_P (insn) = 1;
6112 offset += UNITS_PER_WORD;
6116 /* Expand prologue or epilogue stack adjustment.
6117 The pattern exist to put a dependency on all ebp-based memory accesses.
6118 STYLE should be negative if instructions should be marked as frame related,
6119 zero if %r11 register is live and cannot be freely used and positive
6123 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
6128 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
6129 else if (x86_64_immediate_operand (offset, DImode))
6130 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
6134 /* r11 is used by indirect sibcall return as well, set before the
6135 epilogue and used after the epilogue. ATM indirect sibcall
6136 shouldn't be used together with huge frame sizes in one
6137 function because of the frame_size check in sibcall.c. */
6139 r11 = gen_rtx_REG (DImode, R11_REG);
6140 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
6142 RTX_FRAME_RELATED_P (insn) = 1;
6143 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
6147 RTX_FRAME_RELATED_P (insn) = 1;
6150 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
6153 ix86_internal_arg_pointer (void)
6155 bool has_force_align_arg_pointer =
6156 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
6157 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
6158 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
6159 && DECL_NAME (current_function_decl)
6160 && MAIN_NAME_P (DECL_NAME (current_function_decl))
6161 && DECL_FILE_SCOPE_P (current_function_decl))
6162 || ix86_force_align_arg_pointer
6163 || has_force_align_arg_pointer)
6165 /* Nested functions can't realign the stack due to a register
6167 if (DECL_CONTEXT (current_function_decl)
6168 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
6170 if (ix86_force_align_arg_pointer)
6171 warning (0, "-mstackrealign ignored for nested functions");
6172 if (has_force_align_arg_pointer)
6173 error ("%s not supported for nested functions",
6174 ix86_force_align_arg_pointer_string);
6175 return virtual_incoming_args_rtx;
6177 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, CX_REG);
6178 return copy_to_reg (cfun->machine->force_align_arg_pointer);
6181 return virtual_incoming_args_rtx;
6184 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
6185 This is called from dwarf2out.c to emit call frame instructions
6186 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
6188 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
6190 rtx unspec = SET_SRC (pattern);
6191 gcc_assert (GET_CODE (unspec) == UNSPEC);
6195 case UNSPEC_REG_SAVE:
6196 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
6197 SET_DEST (pattern));
6199 case UNSPEC_DEF_CFA:
6200 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
6201 INTVAL (XVECEXP (unspec, 0, 0)));
6208 /* Expand the prologue into a bunch of separate insns. */
6211 ix86_expand_prologue (void)
6215 struct ix86_frame frame;
6216 HOST_WIDE_INT allocate;
6218 ix86_compute_frame_layout (&frame);
6220 if (cfun->machine->force_align_arg_pointer)
6224 /* Grab the argument pointer. */
6225 x = plus_constant (stack_pointer_rtx, 4);
6226 y = cfun->machine->force_align_arg_pointer;
6227 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
6228 RTX_FRAME_RELATED_P (insn) = 1;
6230 /* The unwind info consists of two parts: install the fafp as the cfa,
6231 and record the fafp as the "save register" of the stack pointer.
6232 The later is there in order that the unwinder can see where it
6233 should restore the stack pointer across the and insn. */
6234 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
6235 x = gen_rtx_SET (VOIDmode, y, x);
6236 RTX_FRAME_RELATED_P (x) = 1;
6237 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
6239 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
6240 RTX_FRAME_RELATED_P (y) = 1;
6241 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
6242 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6243 REG_NOTES (insn) = x;
6245 /* Align the stack. */
6246 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
6249 /* And here we cheat like madmen with the unwind info. We force the
6250 cfa register back to sp+4, which is exactly what it was at the
6251 start of the function. Re-pushing the return address results in
6252 the return at the same spot relative to the cfa, and thus is
6253 correct wrt the unwind info. */
6254 x = cfun->machine->force_align_arg_pointer;
6255 x = gen_frame_mem (Pmode, plus_constant (x, -4));
6256 insn = emit_insn (gen_push (x));
6257 RTX_FRAME_RELATED_P (insn) = 1;
6260 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
6261 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
6262 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6263 REG_NOTES (insn) = x;
6266 /* Note: AT&T enter does NOT have reversed args. Enter is probably
6267 slower on all targets. Also sdb doesn't like it. */
6269 if (frame_pointer_needed)
6271 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
6272 RTX_FRAME_RELATED_P (insn) = 1;
6274 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6275 RTX_FRAME_RELATED_P (insn) = 1;
6278 allocate = frame.to_allocate;
6280 if (!frame.save_regs_using_mov)
6281 ix86_emit_save_regs ();
6283 allocate += frame.nregs * UNITS_PER_WORD;
6285 /* When using red zone we may start register saving before allocating
6286 the stack frame saving one cycle of the prologue. */
6287 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
6288 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
6289 : stack_pointer_rtx,
6290 -frame.nregs * UNITS_PER_WORD);
6294 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
6295 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6296 GEN_INT (-allocate), -1);
6299 /* Only valid for Win32. */
6300 rtx eax = gen_rtx_REG (Pmode, AX_REG);
6304 gcc_assert (!TARGET_64BIT || TARGET_64BIT_MS_ABI);
6306 if (TARGET_64BIT_MS_ABI)
6309 eax_live = ix86_eax_live_at_start_p ();
6313 emit_insn (gen_push (eax));
6314 allocate -= UNITS_PER_WORD;
6317 emit_move_insn (eax, GEN_INT (allocate));
6320 insn = gen_allocate_stack_worker_64 (eax);
6322 insn = gen_allocate_stack_worker_32 (eax);
6323 insn = emit_insn (insn);
6324 RTX_FRAME_RELATED_P (insn) = 1;
6325 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
6326 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
6327 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6328 t, REG_NOTES (insn));
6332 if (frame_pointer_needed)
6333 t = plus_constant (hard_frame_pointer_rtx,
6336 - frame.nregs * UNITS_PER_WORD);
6338 t = plus_constant (stack_pointer_rtx, allocate);
6339 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6343 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
6345 if (!frame_pointer_needed || !frame.to_allocate)
6346 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6348 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6349 -frame.nregs * UNITS_PER_WORD);
6352 pic_reg_used = false;
6353 if (pic_offset_table_rtx
6354 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6355 || current_function_profile))
6357 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6359 if (alt_pic_reg_used != INVALID_REGNUM)
6360 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
6362 pic_reg_used = true;
6369 if (ix86_cmodel == CM_LARGE_PIC)
6371 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
6372 rtx label = gen_label_rtx ();
6374 LABEL_PRESERVE_P (label) = 1;
6375 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6376 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6377 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6378 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6379 pic_offset_table_rtx, tmp_reg));
6382 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6385 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6388 /* Prevent function calls from being scheduled before the call to mcount.
6389 In the pic_reg_used case, make sure that the got load isn't deleted. */
6390 if (current_function_profile)
6393 emit_insn (gen_prologue_use (pic_offset_table_rtx));
6394 emit_insn (gen_blockage ());
6398 /* Emit code to restore saved registers using MOV insns. First register
6399 is restored from POINTER + OFFSET. */
6401 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6402 int maybe_eh_return)
6405 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6407 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6408 if (ix86_save_reg (regno, maybe_eh_return))
6410 /* Ensure that adjust_address won't be forced to produce pointer
6411 out of range allowed by x86-64 instruction set. */
6412 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6416 r11 = gen_rtx_REG (DImode, R11_REG);
6417 emit_move_insn (r11, GEN_INT (offset));
6418 emit_insn (gen_adddi3 (r11, r11, pointer));
6419 base_address = gen_rtx_MEM (Pmode, r11);
6422 emit_move_insn (gen_rtx_REG (Pmode, regno),
6423 adjust_address (base_address, Pmode, offset));
6424 offset += UNITS_PER_WORD;
6428 /* Restore function stack, frame, and registers. */
6431 ix86_expand_epilogue (int style)
6434 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6435 struct ix86_frame frame;
6436 HOST_WIDE_INT offset;
6438 ix86_compute_frame_layout (&frame);
6440 /* Calculate start of saved registers relative to ebp. Special care
6441 must be taken for the normal return case of a function using
6442 eh_return: the eax and edx registers are marked as saved, but not
6443 restored along this path. */
6444 offset = frame.nregs;
6445 if (current_function_calls_eh_return && style != 2)
6447 offset *= -UNITS_PER_WORD;
6449 /* If we're only restoring one register and sp is not valid then
6450 using a move instruction to restore the register since it's
6451 less work than reloading sp and popping the register.
6453 The default code result in stack adjustment using add/lea instruction,
6454 while this code results in LEAVE instruction (or discrete equivalent),
6455 so it is profitable in some other cases as well. Especially when there
6456 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6457 and there is exactly one register to pop. This heuristic may need some
6458 tuning in future. */
6459 if ((!sp_valid && frame.nregs <= 1)
6460 || (TARGET_EPILOGUE_USING_MOVE
6461 && cfun->machine->use_fast_prologue_epilogue
6462 && (frame.nregs > 1 || frame.to_allocate))
6463 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6464 || (frame_pointer_needed && TARGET_USE_LEAVE
6465 && cfun->machine->use_fast_prologue_epilogue
6466 && frame.nregs == 1)
6467 || current_function_calls_eh_return)
6469 /* Restore registers. We can use ebp or esp to address the memory
6470 locations. If both are available, default to ebp, since offsets
6471 are known to be small. Only exception is esp pointing directly to the
6472 end of block of saved registers, where we may simplify addressing
6475 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6476 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6477 frame.to_allocate, style == 2);
6479 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6480 offset, style == 2);
6482 /* eh_return epilogues need %ecx added to the stack pointer. */
6485 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6487 if (frame_pointer_needed)
6489 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6490 tmp = plus_constant (tmp, UNITS_PER_WORD);
6491 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6493 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6494 emit_move_insn (hard_frame_pointer_rtx, tmp);
6496 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6501 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6502 tmp = plus_constant (tmp, (frame.to_allocate
6503 + frame.nregs * UNITS_PER_WORD));
6504 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6507 else if (!frame_pointer_needed)
6508 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6509 GEN_INT (frame.to_allocate
6510 + frame.nregs * UNITS_PER_WORD),
6512 /* If not an i386, mov & pop is faster than "leave". */
6513 else if (TARGET_USE_LEAVE || optimize_size
6514 || !cfun->machine->use_fast_prologue_epilogue)
6515 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6518 pro_epilogue_adjust_stack (stack_pointer_rtx,
6519 hard_frame_pointer_rtx,
6522 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6524 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6529 /* First step is to deallocate the stack frame so that we can
6530 pop the registers. */
6533 gcc_assert (frame_pointer_needed);
6534 pro_epilogue_adjust_stack (stack_pointer_rtx,
6535 hard_frame_pointer_rtx,
6536 GEN_INT (offset), style);
6538 else if (frame.to_allocate)
6539 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6540 GEN_INT (frame.to_allocate), style);
6542 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6543 if (ix86_save_reg (regno, false))
6546 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
6548 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
6550 if (frame_pointer_needed)
6552 /* Leave results in shorter dependency chains on CPUs that are
6553 able to grok it fast. */
6554 if (TARGET_USE_LEAVE)
6555 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6556 else if (TARGET_64BIT)
6557 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6559 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6563 if (cfun->machine->force_align_arg_pointer)
6565 emit_insn (gen_addsi3 (stack_pointer_rtx,
6566 cfun->machine->force_align_arg_pointer,
6570 /* Sibcall epilogues don't want a return instruction. */
6574 if (current_function_pops_args && current_function_args_size)
6576 rtx popc = GEN_INT (current_function_pops_args);
6578 /* i386 can only pop 64K bytes. If asked to pop more, pop
6579 return address, do explicit add, and jump indirectly to the
6582 if (current_function_pops_args >= 65536)
6584 rtx ecx = gen_rtx_REG (SImode, CX_REG);
6586 /* There is no "pascal" calling convention in any 64bit ABI. */
6587 gcc_assert (!TARGET_64BIT);
6589 emit_insn (gen_popsi1 (ecx));
6590 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6591 emit_jump_insn (gen_return_indirect_internal (ecx));
6594 emit_jump_insn (gen_return_pop_internal (popc));
6597 emit_jump_insn (gen_return_internal ());
6600 /* Reset from the function's potential modifications. */
6603 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6604 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6606 if (pic_offset_table_rtx)
6607 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
6609 /* Mach-O doesn't support labels at the end of objects, so if
6610 it looks like we might want one, insert a NOP. */
6612 rtx insn = get_last_insn ();
6615 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6616 insn = PREV_INSN (insn);
6620 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6621 fputs ("\tnop\n", file);
6627 /* Extract the parts of an RTL expression that is a valid memory address
6628 for an instruction. Return 0 if the structure of the address is
6629 grossly off. Return -1 if the address contains ASHIFT, so it is not
6630 strictly valid, but still used for computing length of lea instruction. */
6633 ix86_decompose_address (rtx addr, struct ix86_address *out)
6635 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6636 rtx base_reg, index_reg;
6637 HOST_WIDE_INT scale = 1;
6638 rtx scale_rtx = NULL_RTX;
6640 enum ix86_address_seg seg = SEG_DEFAULT;
6642 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6644 else if (GET_CODE (addr) == PLUS)
6654 addends[n++] = XEXP (op, 1);
6657 while (GET_CODE (op) == PLUS);
6662 for (i = n; i >= 0; --i)
6665 switch (GET_CODE (op))
6670 index = XEXP (op, 0);
6671 scale_rtx = XEXP (op, 1);
6675 if (XINT (op, 1) == UNSPEC_TP
6676 && TARGET_TLS_DIRECT_SEG_REFS
6677 && seg == SEG_DEFAULT)
6678 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6707 else if (GET_CODE (addr) == MULT)
6709 index = XEXP (addr, 0); /* index*scale */
6710 scale_rtx = XEXP (addr, 1);
6712 else if (GET_CODE (addr) == ASHIFT)
6716 /* We're called for lea too, which implements ashift on occasion. */
6717 index = XEXP (addr, 0);
6718 tmp = XEXP (addr, 1);
6719 if (!CONST_INT_P (tmp))
6721 scale = INTVAL (tmp);
6722 if ((unsigned HOST_WIDE_INT) scale > 3)
6728 disp = addr; /* displacement */
6730 /* Extract the integral value of scale. */
6733 if (!CONST_INT_P (scale_rtx))
6735 scale = INTVAL (scale_rtx);
6738 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6739 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6741 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6742 if (base_reg && index_reg && scale == 1
6743 && (index_reg == arg_pointer_rtx
6744 || index_reg == frame_pointer_rtx
6745 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6748 tmp = base, base = index, index = tmp;
6749 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6752 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6753 if ((base_reg == hard_frame_pointer_rtx
6754 || base_reg == frame_pointer_rtx
6755 || base_reg == arg_pointer_rtx) && !disp)
6758 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6759 Avoid this by transforming to [%esi+0]. */
6760 if (ix86_tune == PROCESSOR_K6 && !optimize_size
6761 && base_reg && !index_reg && !disp
6763 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6766 /* Special case: encode reg+reg instead of reg*2. */
6767 if (!base && index && scale && scale == 2)
6768 base = index, base_reg = index_reg, scale = 1;
6770 /* Special case: scaling cannot be encoded without base or displacement. */
6771 if (!base && !disp && index && scale != 1)
6783 /* Return cost of the memory address x.
6784 For i386, it is better to use a complex address than let gcc copy
6785 the address into a reg and make a new pseudo. But not if the address
6786 requires to two regs - that would mean more pseudos with longer
6789 ix86_address_cost (rtx x)
6791 struct ix86_address parts;
6793 int ok = ix86_decompose_address (x, &parts);
6797 if (parts.base && GET_CODE (parts.base) == SUBREG)
6798 parts.base = SUBREG_REG (parts.base);
6799 if (parts.index && GET_CODE (parts.index) == SUBREG)
6800 parts.index = SUBREG_REG (parts.index);
6802 /* Attempt to minimize number of registers in the address. */
6804 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
6806 && (!REG_P (parts.index)
6807 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
6811 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
6813 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
6814 && parts.base != parts.index)
6817 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6818 since it's predecode logic can't detect the length of instructions
6819 and it degenerates to vector decoded. Increase cost of such
6820 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6821 to split such addresses or even refuse such addresses at all.
6823 Following addressing modes are affected:
6828 The first and last case may be avoidable by explicitly coding the zero in
6829 memory address, but I don't have AMD-K6 machine handy to check this
6833 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
6834 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
6835 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
6841 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6842 this is used for to form addresses to local data when -fPIC is in
6846 darwin_local_data_pic (rtx disp)
6848 if (GET_CODE (disp) == MINUS)
6850 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
6851 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
6852 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
6854 const char *sym_name = XSTR (XEXP (disp, 1), 0);
6855 if (! strcmp (sym_name, "<pic base>"))
6863 /* Determine if a given RTX is a valid constant. We already know this
6864 satisfies CONSTANT_P. */
6867 legitimate_constant_p (rtx x)
6869 switch (GET_CODE (x))
6874 if (GET_CODE (x) == PLUS)
6876 if (!CONST_INT_P (XEXP (x, 1)))
6881 if (TARGET_MACHO && darwin_local_data_pic (x))
6884 /* Only some unspecs are valid as "constants". */
6885 if (GET_CODE (x) == UNSPEC)
6886 switch (XINT (x, 1))
6891 return TARGET_64BIT;
6894 x = XVECEXP (x, 0, 0);
6895 return (GET_CODE (x) == SYMBOL_REF
6896 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
6898 x = XVECEXP (x, 0, 0);
6899 return (GET_CODE (x) == SYMBOL_REF
6900 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
6905 /* We must have drilled down to a symbol. */
6906 if (GET_CODE (x) == LABEL_REF)
6908 if (GET_CODE (x) != SYMBOL_REF)
6913 /* TLS symbols are never valid. */
6914 if (SYMBOL_REF_TLS_MODEL (x))
6917 /* DLLIMPORT symbols are never valid. */
6918 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
6919 && SYMBOL_REF_DLLIMPORT_P (x))
6924 if (GET_MODE (x) == TImode
6925 && x != CONST0_RTX (TImode)
6931 if (x == CONST0_RTX (GET_MODE (x)))
6939 /* Otherwise we handle everything else in the move patterns. */
6943 /* Determine if it's legal to put X into the constant pool. This
6944 is not possible for the address of thread-local symbols, which
6945 is checked above. */
6948 ix86_cannot_force_const_mem (rtx x)
6950 /* We can always put integral constants and vectors in memory. */
6951 switch (GET_CODE (x))
6961 return !legitimate_constant_p (x);
6964 /* Determine if a given RTX is a valid constant address. */
6967 constant_address_p (rtx x)
6969 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
6972 /* Nonzero if the constant value X is a legitimate general operand
6973 when generating PIC code. It is given that flag_pic is on and
6974 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
6977 legitimate_pic_operand_p (rtx x)
6981 switch (GET_CODE (x))
6984 inner = XEXP (x, 0);
6985 if (GET_CODE (inner) == PLUS
6986 && CONST_INT_P (XEXP (inner, 1)))
6987 inner = XEXP (inner, 0);
6989 /* Only some unspecs are valid as "constants". */
6990 if (GET_CODE (inner) == UNSPEC)
6991 switch (XINT (inner, 1))
6996 return TARGET_64BIT;
6998 x = XVECEXP (inner, 0, 0);
6999 return (GET_CODE (x) == SYMBOL_REF
7000 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7008 return legitimate_pic_address_disp_p (x);
7015 /* Determine if a given CONST RTX is a valid memory displacement
7019 legitimate_pic_address_disp_p (rtx disp)
7023 /* In 64bit mode we can allow direct addresses of symbols and labels
7024 when they are not dynamic symbols. */
7027 rtx op0 = disp, op1;
7029 switch (GET_CODE (disp))
7035 if (GET_CODE (XEXP (disp, 0)) != PLUS)
7037 op0 = XEXP (XEXP (disp, 0), 0);
7038 op1 = XEXP (XEXP (disp, 0), 1);
7039 if (!CONST_INT_P (op1)
7040 || INTVAL (op1) >= 16*1024*1024
7041 || INTVAL (op1) < -16*1024*1024)
7043 if (GET_CODE (op0) == LABEL_REF)
7045 if (GET_CODE (op0) != SYMBOL_REF)
7050 /* TLS references should always be enclosed in UNSPEC. */
7051 if (SYMBOL_REF_TLS_MODEL (op0))
7053 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
7054 && ix86_cmodel != CM_LARGE_PIC)
7062 if (GET_CODE (disp) != CONST)
7064 disp = XEXP (disp, 0);
7068 /* We are unsafe to allow PLUS expressions. This limit allowed distance
7069 of GOT tables. We should not need these anyway. */
7070 if (GET_CODE (disp) != UNSPEC
7071 || (XINT (disp, 1) != UNSPEC_GOTPCREL
7072 && XINT (disp, 1) != UNSPEC_GOTOFF
7073 && XINT (disp, 1) != UNSPEC_PLTOFF))
7076 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
7077 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
7083 if (GET_CODE (disp) == PLUS)
7085 if (!CONST_INT_P (XEXP (disp, 1)))
7087 disp = XEXP (disp, 0);
7091 if (TARGET_MACHO && darwin_local_data_pic (disp))
7094 if (GET_CODE (disp) != UNSPEC)
7097 switch (XINT (disp, 1))
7102 /* We need to check for both symbols and labels because VxWorks loads
7103 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
7105 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7106 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
7108 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
7109 While ABI specify also 32bit relocation but we don't produce it in
7110 small PIC model at all. */
7111 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7112 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
7114 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
7116 case UNSPEC_GOTTPOFF:
7117 case UNSPEC_GOTNTPOFF:
7118 case UNSPEC_INDNTPOFF:
7121 disp = XVECEXP (disp, 0, 0);
7122 return (GET_CODE (disp) == SYMBOL_REF
7123 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
7125 disp = XVECEXP (disp, 0, 0);
7126 return (GET_CODE (disp) == SYMBOL_REF
7127 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
7129 disp = XVECEXP (disp, 0, 0);
7130 return (GET_CODE (disp) == SYMBOL_REF
7131 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
7137 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
7138 memory address for an instruction. The MODE argument is the machine mode
7139 for the MEM expression that wants to use this address.
7141 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
7142 convert common non-canonical forms to canonical form so that they will
7146 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
7147 rtx addr, int strict)
7149 struct ix86_address parts;
7150 rtx base, index, disp;
7151 HOST_WIDE_INT scale;
7152 const char *reason = NULL;
7153 rtx reason_rtx = NULL_RTX;
7155 if (ix86_decompose_address (addr, &parts) <= 0)
7157 reason = "decomposition failed";
7162 index = parts.index;
7164 scale = parts.scale;
7166 /* Validate base register.
7168 Don't allow SUBREG's that span more than a word here. It can lead to spill
7169 failures when the base is one word out of a two word structure, which is
7170 represented internally as a DImode int. */
7179 else if (GET_CODE (base) == SUBREG
7180 && REG_P (SUBREG_REG (base))
7181 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
7183 reg = SUBREG_REG (base);
7186 reason = "base is not a register";
7190 if (GET_MODE (base) != Pmode)
7192 reason = "base is not in Pmode";
7196 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
7197 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
7199 reason = "base is not valid";
7204 /* Validate index register.
7206 Don't allow SUBREG's that span more than a word here -- same as above. */
7215 else if (GET_CODE (index) == SUBREG
7216 && REG_P (SUBREG_REG (index))
7217 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
7219 reg = SUBREG_REG (index);
7222 reason = "index is not a register";
7226 if (GET_MODE (index) != Pmode)
7228 reason = "index is not in Pmode";
7232 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
7233 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
7235 reason = "index is not valid";
7240 /* Validate scale factor. */
7243 reason_rtx = GEN_INT (scale);
7246 reason = "scale without index";
7250 if (scale != 2 && scale != 4 && scale != 8)
7252 reason = "scale is not a valid multiplier";
7257 /* Validate displacement. */
7262 if (GET_CODE (disp) == CONST
7263 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
7264 switch (XINT (XEXP (disp, 0), 1))
7266 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
7267 used. While ABI specify also 32bit relocations, we don't produce
7268 them at all and use IP relative instead. */
7271 gcc_assert (flag_pic);
7273 goto is_legitimate_pic;
7274 reason = "64bit address unspec";
7277 case UNSPEC_GOTPCREL:
7278 gcc_assert (flag_pic);
7279 goto is_legitimate_pic;
7281 case UNSPEC_GOTTPOFF:
7282 case UNSPEC_GOTNTPOFF:
7283 case UNSPEC_INDNTPOFF:
7289 reason = "invalid address unspec";
7293 else if (SYMBOLIC_CONST (disp)
7297 && MACHOPIC_INDIRECT
7298 && !machopic_operand_p (disp)
7304 if (TARGET_64BIT && (index || base))
7306 /* foo@dtpoff(%rX) is ok. */
7307 if (GET_CODE (disp) != CONST
7308 || GET_CODE (XEXP (disp, 0)) != PLUS
7309 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
7310 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
7311 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
7312 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
7314 reason = "non-constant pic memory reference";
7318 else if (! legitimate_pic_address_disp_p (disp))
7320 reason = "displacement is an invalid pic construct";
7324 /* This code used to verify that a symbolic pic displacement
7325 includes the pic_offset_table_rtx register.
7327 While this is good idea, unfortunately these constructs may
7328 be created by "adds using lea" optimization for incorrect
7337 This code is nonsensical, but results in addressing
7338 GOT table with pic_offset_table_rtx base. We can't
7339 just refuse it easily, since it gets matched by
7340 "addsi3" pattern, that later gets split to lea in the
7341 case output register differs from input. While this
7342 can be handled by separate addsi pattern for this case
7343 that never results in lea, this seems to be easier and
7344 correct fix for crash to disable this test. */
7346 else if (GET_CODE (disp) != LABEL_REF
7347 && !CONST_INT_P (disp)
7348 && (GET_CODE (disp) != CONST
7349 || !legitimate_constant_p (disp))
7350 && (GET_CODE (disp) != SYMBOL_REF
7351 || !legitimate_constant_p (disp)))
7353 reason = "displacement is not constant";
7356 else if (TARGET_64BIT
7357 && !x86_64_immediate_operand (disp, VOIDmode))
7359 reason = "displacement is out of range";
7364 /* Everything looks valid. */
7371 /* Return a unique alias set for the GOT. */
7373 static alias_set_type
7374 ix86_GOT_alias_set (void)
7376 static alias_set_type set = -1;
7378 set = new_alias_set ();
7382 /* Return a legitimate reference for ORIG (an address) using the
7383 register REG. If REG is 0, a new pseudo is generated.
7385 There are two types of references that must be handled:
7387 1. Global data references must load the address from the GOT, via
7388 the PIC reg. An insn is emitted to do this load, and the reg is
7391 2. Static data references, constant pool addresses, and code labels
7392 compute the address as an offset from the GOT, whose base is in
7393 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7394 differentiate them from global data objects. The returned
7395 address is the PIC reg + an unspec constant.
7397 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7398 reg also appears in the address. */
7401 legitimize_pic_address (rtx orig, rtx reg)
7408 if (TARGET_MACHO && !TARGET_64BIT)
7411 reg = gen_reg_rtx (Pmode);
7412 /* Use the generic Mach-O PIC machinery. */
7413 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7417 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7419 else if (TARGET_64BIT
7420 && ix86_cmodel != CM_SMALL_PIC
7421 && gotoff_operand (addr, Pmode))
7424 /* This symbol may be referenced via a displacement from the PIC
7425 base address (@GOTOFF). */
7427 if (reload_in_progress)
7428 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7429 if (GET_CODE (addr) == CONST)
7430 addr = XEXP (addr, 0);
7431 if (GET_CODE (addr) == PLUS)
7433 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7435 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7438 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7439 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7441 tmpreg = gen_reg_rtx (Pmode);
7444 emit_move_insn (tmpreg, new_rtx);
7448 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7449 tmpreg, 1, OPTAB_DIRECT);
7452 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7454 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7456 /* This symbol may be referenced via a displacement from the PIC
7457 base address (@GOTOFF). */
7459 if (reload_in_progress)
7460 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7461 if (GET_CODE (addr) == CONST)
7462 addr = XEXP (addr, 0);
7463 if (GET_CODE (addr) == PLUS)
7465 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7467 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7470 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7471 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7472 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7476 emit_move_insn (reg, new_rtx);
7480 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7481 /* We can't use @GOTOFF for text labels on VxWorks;
7482 see gotoff_operand. */
7483 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7485 /* Given that we've already handled dllimport variables separately
7486 in legitimize_address, and all other variables should satisfy
7487 legitimate_pic_address_disp_p, we should never arrive here. */
7488 gcc_assert (!TARGET_64BIT_MS_ABI);
7490 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7492 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7493 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7494 new_rtx = gen_const_mem (Pmode, new_rtx);
7495 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7498 reg = gen_reg_rtx (Pmode);
7499 /* Use directly gen_movsi, otherwise the address is loaded
7500 into register for CSE. We don't want to CSE this addresses,
7501 instead we CSE addresses from the GOT table, so skip this. */
7502 emit_insn (gen_movsi (reg, new_rtx));
7507 /* This symbol must be referenced via a load from the
7508 Global Offset Table (@GOT). */
7510 if (reload_in_progress)
7511 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7512 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7513 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7515 new_rtx = force_reg (Pmode, new_rtx);
7516 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7517 new_rtx = gen_const_mem (Pmode, new_rtx);
7518 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7521 reg = gen_reg_rtx (Pmode);
7522 emit_move_insn (reg, new_rtx);
7528 if (CONST_INT_P (addr)
7529 && !x86_64_immediate_operand (addr, VOIDmode))
7533 emit_move_insn (reg, addr);
7537 new_rtx = force_reg (Pmode, addr);
7539 else if (GET_CODE (addr) == CONST)
7541 addr = XEXP (addr, 0);
7543 /* We must match stuff we generate before. Assume the only
7544 unspecs that can get here are ours. Not that we could do
7545 anything with them anyway.... */
7546 if (GET_CODE (addr) == UNSPEC
7547 || (GET_CODE (addr) == PLUS
7548 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7550 gcc_assert (GET_CODE (addr) == PLUS);
7552 if (GET_CODE (addr) == PLUS)
7554 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7556 /* Check first to see if this is a constant offset from a @GOTOFF
7557 symbol reference. */
7558 if (gotoff_operand (op0, Pmode)
7559 && CONST_INT_P (op1))
7563 if (reload_in_progress)
7564 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7565 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7567 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
7568 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7569 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7573 emit_move_insn (reg, new_rtx);
7579 if (INTVAL (op1) < -16*1024*1024
7580 || INTVAL (op1) >= 16*1024*1024)
7582 if (!x86_64_immediate_operand (op1, Pmode))
7583 op1 = force_reg (Pmode, op1);
7584 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7590 base = legitimize_pic_address (XEXP (addr, 0), reg);
7591 new_rtx = legitimize_pic_address (XEXP (addr, 1),
7592 base == reg ? NULL_RTX : reg);
7594 if (CONST_INT_P (new_rtx))
7595 new_rtx = plus_constant (base, INTVAL (new_rtx));
7598 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
7600 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
7601 new_rtx = XEXP (new_rtx, 1);
7603 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
7611 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7614 get_thread_pointer (int to_reg)
7618 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7622 reg = gen_reg_rtx (Pmode);
7623 insn = gen_rtx_SET (VOIDmode, reg, tp);
7624 insn = emit_insn (insn);
7629 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7630 false if we expect this to be used for a memory address and true if
7631 we expect to load the address into a register. */
7634 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7636 rtx dest, base, off, pic, tp;
7641 case TLS_MODEL_GLOBAL_DYNAMIC:
7642 dest = gen_reg_rtx (Pmode);
7643 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7645 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7647 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
7650 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7651 insns = get_insns ();
7654 CONST_OR_PURE_CALL_P (insns) = 1;
7655 emit_libcall_block (insns, dest, rax, x);
7657 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7658 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7660 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7662 if (TARGET_GNU2_TLS)
7664 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7666 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7670 case TLS_MODEL_LOCAL_DYNAMIC:
7671 base = gen_reg_rtx (Pmode);
7672 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7674 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7676 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
7679 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7680 insns = get_insns ();
7683 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7684 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7685 CONST_OR_PURE_CALL_P (insns) = 1;
7686 emit_libcall_block (insns, base, rax, note);
7688 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7689 emit_insn (gen_tls_local_dynamic_base_64 (base));
7691 emit_insn (gen_tls_local_dynamic_base_32 (base));
7693 if (TARGET_GNU2_TLS)
7695 rtx x = ix86_tls_module_base ();
7697 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7698 gen_rtx_MINUS (Pmode, x, tp));
7701 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7702 off = gen_rtx_CONST (Pmode, off);
7704 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7706 if (TARGET_GNU2_TLS)
7708 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7710 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7715 case TLS_MODEL_INITIAL_EXEC:
7719 type = UNSPEC_GOTNTPOFF;
7723 if (reload_in_progress)
7724 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7725 pic = pic_offset_table_rtx;
7726 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7728 else if (!TARGET_ANY_GNU_TLS)
7730 pic = gen_reg_rtx (Pmode);
7731 emit_insn (gen_set_got (pic));
7732 type = UNSPEC_GOTTPOFF;
7737 type = UNSPEC_INDNTPOFF;
7740 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7741 off = gen_rtx_CONST (Pmode, off);
7743 off = gen_rtx_PLUS (Pmode, pic, off);
7744 off = gen_const_mem (Pmode, off);
7745 set_mem_alias_set (off, ix86_GOT_alias_set ());
7747 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7749 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7750 off = force_reg (Pmode, off);
7751 return gen_rtx_PLUS (Pmode, base, off);
7755 base = get_thread_pointer (true);
7756 dest = gen_reg_rtx (Pmode);
7757 emit_insn (gen_subsi3 (dest, base, off));
7761 case TLS_MODEL_LOCAL_EXEC:
7762 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7763 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7764 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7765 off = gen_rtx_CONST (Pmode, off);
7767 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7769 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7770 return gen_rtx_PLUS (Pmode, base, off);
7774 base = get_thread_pointer (true);
7775 dest = gen_reg_rtx (Pmode);
7776 emit_insn (gen_subsi3 (dest, base, off));
7787 /* Create or return the unique __imp_DECL dllimport symbol corresponding
7790 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
7791 htab_t dllimport_map;
7794 get_dllimport_decl (tree decl)
7796 struct tree_map *h, in;
7800 size_t namelen, prefixlen;
7806 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
7808 in.hash = htab_hash_pointer (decl);
7809 in.base.from = decl;
7810 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
7811 h = (struct tree_map *) *loc;
7815 *loc = h = GGC_NEW (struct tree_map);
7817 h->base.from = decl;
7818 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
7819 DECL_ARTIFICIAL (to) = 1;
7820 DECL_IGNORED_P (to) = 1;
7821 DECL_EXTERNAL (to) = 1;
7822 TREE_READONLY (to) = 1;
7824 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
7825 name = targetm.strip_name_encoding (name);
7826 prefix = name[0] == FASTCALL_PREFIX ? "*__imp_": "*__imp__";
7827 namelen = strlen (name);
7828 prefixlen = strlen (prefix);
7829 imp_name = (char *) alloca (namelen + prefixlen + 1);
7830 memcpy (imp_name, prefix, prefixlen);
7831 memcpy (imp_name + prefixlen, name, namelen + 1);
7833 name = ggc_alloc_string (imp_name, namelen + prefixlen);
7834 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
7835 SET_SYMBOL_REF_DECL (rtl, to);
7836 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
7838 rtl = gen_const_mem (Pmode, rtl);
7839 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
7841 SET_DECL_RTL (to, rtl);
7842 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
7847 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
7848 true if we require the result be a register. */
7851 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
7856 gcc_assert (SYMBOL_REF_DECL (symbol));
7857 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
7859 x = DECL_RTL (imp_decl);
7861 x = force_reg (Pmode, x);
7865 /* Try machine-dependent ways of modifying an illegitimate address
7866 to be legitimate. If we find one, return the new, valid address.
7867 This macro is used in only one place: `memory_address' in explow.c.
7869 OLDX is the address as it was before break_out_memory_refs was called.
7870 In some cases it is useful to look at this to decide what needs to be done.
7872 MODE and WIN are passed so that this macro can use
7873 GO_IF_LEGITIMATE_ADDRESS.
7875 It is always safe for this macro to do nothing. It exists to recognize
7876 opportunities to optimize the output.
7878 For the 80386, we handle X+REG by loading X into a register R and
7879 using R+REG. R will go in a general reg and indexing will be used.
7880 However, if REG is a broken-out memory address or multiplication,
7881 nothing needs to be done because REG can certainly go in a general reg.
7883 When -fpic is used, special handling is needed for symbolic references.
7884 See comments by legitimize_pic_address in i386.c for details. */
7887 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
7892 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
7894 return legitimize_tls_address (x, (enum tls_model) log, false);
7895 if (GET_CODE (x) == CONST
7896 && GET_CODE (XEXP (x, 0)) == PLUS
7897 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
7898 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
7900 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
7901 (enum tls_model) log, false);
7902 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
7905 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
7907 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
7908 return legitimize_dllimport_symbol (x, true);
7909 if (GET_CODE (x) == CONST
7910 && GET_CODE (XEXP (x, 0)) == PLUS
7911 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
7912 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
7914 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
7915 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
7919 if (flag_pic && SYMBOLIC_CONST (x))
7920 return legitimize_pic_address (x, 0);
7922 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
7923 if (GET_CODE (x) == ASHIFT
7924 && CONST_INT_P (XEXP (x, 1))
7925 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
7928 log = INTVAL (XEXP (x, 1));
7929 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
7930 GEN_INT (1 << log));
7933 if (GET_CODE (x) == PLUS)
7935 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
7937 if (GET_CODE (XEXP (x, 0)) == ASHIFT
7938 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7939 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
7942 log = INTVAL (XEXP (XEXP (x, 0), 1));
7943 XEXP (x, 0) = gen_rtx_MULT (Pmode,
7944 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
7945 GEN_INT (1 << log));
7948 if (GET_CODE (XEXP (x, 1)) == ASHIFT
7949 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
7950 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
7953 log = INTVAL (XEXP (XEXP (x, 1), 1));
7954 XEXP (x, 1) = gen_rtx_MULT (Pmode,
7955 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
7956 GEN_INT (1 << log));
7959 /* Put multiply first if it isn't already. */
7960 if (GET_CODE (XEXP (x, 1)) == MULT)
7962 rtx tmp = XEXP (x, 0);
7963 XEXP (x, 0) = XEXP (x, 1);
7968 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
7969 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
7970 created by virtual register instantiation, register elimination, and
7971 similar optimizations. */
7972 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
7975 x = gen_rtx_PLUS (Pmode,
7976 gen_rtx_PLUS (Pmode, XEXP (x, 0),
7977 XEXP (XEXP (x, 1), 0)),
7978 XEXP (XEXP (x, 1), 1));
7982 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
7983 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
7984 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
7985 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
7986 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
7987 && CONSTANT_P (XEXP (x, 1)))
7990 rtx other = NULL_RTX;
7992 if (CONST_INT_P (XEXP (x, 1)))
7994 constant = XEXP (x, 1);
7995 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
7997 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
7999 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
8000 other = XEXP (x, 1);
8008 x = gen_rtx_PLUS (Pmode,
8009 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
8010 XEXP (XEXP (XEXP (x, 0), 1), 0)),
8011 plus_constant (other, INTVAL (constant)));
8015 if (changed && legitimate_address_p (mode, x, FALSE))
8018 if (GET_CODE (XEXP (x, 0)) == MULT)
8021 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
8024 if (GET_CODE (XEXP (x, 1)) == MULT)
8027 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
8031 && REG_P (XEXP (x, 1))
8032 && REG_P (XEXP (x, 0)))
8035 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
8038 x = legitimize_pic_address (x, 0);
8041 if (changed && legitimate_address_p (mode, x, FALSE))
8044 if (REG_P (XEXP (x, 0)))
8046 rtx temp = gen_reg_rtx (Pmode);
8047 rtx val = force_operand (XEXP (x, 1), temp);
8049 emit_move_insn (temp, val);
8055 else if (REG_P (XEXP (x, 1)))
8057 rtx temp = gen_reg_rtx (Pmode);
8058 rtx val = force_operand (XEXP (x, 0), temp);
8060 emit_move_insn (temp, val);
8070 /* Print an integer constant expression in assembler syntax. Addition
8071 and subtraction are the only arithmetic that may appear in these
8072 expressions. FILE is the stdio stream to write to, X is the rtx, and
8073 CODE is the operand print code from the output string. */
8076 output_pic_addr_const (FILE *file, rtx x, int code)
8080 switch (GET_CODE (x))
8083 gcc_assert (flag_pic);
8088 if (! TARGET_MACHO || TARGET_64BIT)
8089 output_addr_const (file, x);
8092 const char *name = XSTR (x, 0);
8094 /* Mark the decl as referenced so that cgraph will
8095 output the function. */
8096 if (SYMBOL_REF_DECL (x))
8097 mark_decl_referenced (SYMBOL_REF_DECL (x));
8100 if (MACHOPIC_INDIRECT
8101 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
8102 name = machopic_indirection_name (x, /*stub_p=*/true);
8104 assemble_name (file, name);
8106 if (!TARGET_MACHO && !TARGET_64BIT_MS_ABI
8107 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
8108 fputs ("@PLT", file);
8115 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
8116 assemble_name (asm_out_file, buf);
8120 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8124 /* This used to output parentheses around the expression,
8125 but that does not work on the 386 (either ATT or BSD assembler). */
8126 output_pic_addr_const (file, XEXP (x, 0), code);
8130 if (GET_MODE (x) == VOIDmode)
8132 /* We can use %d if the number is <32 bits and positive. */
8133 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
8134 fprintf (file, "0x%lx%08lx",
8135 (unsigned long) CONST_DOUBLE_HIGH (x),
8136 (unsigned long) CONST_DOUBLE_LOW (x));
8138 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
8141 /* We can't handle floating point constants;
8142 PRINT_OPERAND must handle them. */
8143 output_operand_lossage ("floating constant misused");
8147 /* Some assemblers need integer constants to appear first. */
8148 if (CONST_INT_P (XEXP (x, 0)))
8150 output_pic_addr_const (file, XEXP (x, 0), code);
8152 output_pic_addr_const (file, XEXP (x, 1), code);
8156 gcc_assert (CONST_INT_P (XEXP (x, 1)));
8157 output_pic_addr_const (file, XEXP (x, 1), code);
8159 output_pic_addr_const (file, XEXP (x, 0), code);
8165 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
8166 output_pic_addr_const (file, XEXP (x, 0), code);
8168 output_pic_addr_const (file, XEXP (x, 1), code);
8170 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
8174 gcc_assert (XVECLEN (x, 0) == 1);
8175 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
8176 switch (XINT (x, 1))
8179 fputs ("@GOT", file);
8182 fputs ("@GOTOFF", file);
8185 fputs ("@PLTOFF", file);
8187 case UNSPEC_GOTPCREL:
8188 fputs ("@GOTPCREL(%rip)", file);
8190 case UNSPEC_GOTTPOFF:
8191 /* FIXME: This might be @TPOFF in Sun ld too. */
8192 fputs ("@GOTTPOFF", file);
8195 fputs ("@TPOFF", file);
8199 fputs ("@TPOFF", file);
8201 fputs ("@NTPOFF", file);
8204 fputs ("@DTPOFF", file);
8206 case UNSPEC_GOTNTPOFF:
8208 fputs ("@GOTTPOFF(%rip)", file);
8210 fputs ("@GOTNTPOFF", file);
8212 case UNSPEC_INDNTPOFF:
8213 fputs ("@INDNTPOFF", file);
8216 output_operand_lossage ("invalid UNSPEC as operand");
8222 output_operand_lossage ("invalid expression as operand");
8226 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8227 We need to emit DTP-relative relocations. */
8229 static void ATTRIBUTE_UNUSED
8230 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
8232 fputs (ASM_LONG, file);
8233 output_addr_const (file, x);
8234 fputs ("@DTPOFF", file);
8240 fputs (", 0", file);
8247 /* In the name of slightly smaller debug output, and to cater to
8248 general assembler lossage, recognize PIC+GOTOFF and turn it back
8249 into a direct symbol reference.
8251 On Darwin, this is necessary to avoid a crash, because Darwin
8252 has a different PIC label for each routine but the DWARF debugging
8253 information is not associated with any particular routine, so it's
8254 necessary to remove references to the PIC label from RTL stored by
8255 the DWARF output code. */
8258 ix86_delegitimize_address (rtx orig_x)
8261 /* reg_addend is NULL or a multiple of some register. */
8262 rtx reg_addend = NULL_RTX;
8263 /* const_addend is NULL or a const_int. */
8264 rtx const_addend = NULL_RTX;
8265 /* This is the result, or NULL. */
8266 rtx result = NULL_RTX;
8273 if (GET_CODE (x) != CONST
8274 || GET_CODE (XEXP (x, 0)) != UNSPEC
8275 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
8278 return XVECEXP (XEXP (x, 0), 0, 0);
8281 if (GET_CODE (x) != PLUS
8282 || GET_CODE (XEXP (x, 1)) != CONST)
8285 if (REG_P (XEXP (x, 0))
8286 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
8287 /* %ebx + GOT/GOTOFF */
8289 else if (GET_CODE (XEXP (x, 0)) == PLUS)
8291 /* %ebx + %reg * scale + GOT/GOTOFF */
8292 reg_addend = XEXP (x, 0);
8293 if (REG_P (XEXP (reg_addend, 0))
8294 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
8295 reg_addend = XEXP (reg_addend, 1);
8296 else if (REG_P (XEXP (reg_addend, 1))
8297 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
8298 reg_addend = XEXP (reg_addend, 0);
8301 if (!REG_P (reg_addend)
8302 && GET_CODE (reg_addend) != MULT
8303 && GET_CODE (reg_addend) != ASHIFT)
8309 x = XEXP (XEXP (x, 1), 0);
8310 if (GET_CODE (x) == PLUS
8311 && CONST_INT_P (XEXP (x, 1)))
8313 const_addend = XEXP (x, 1);
8317 if (GET_CODE (x) == UNSPEC
8318 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8319 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8320 result = XVECEXP (x, 0, 0);
8322 if (TARGET_MACHO && darwin_local_data_pic (x)
8324 result = XEXP (x, 0);
8330 result = gen_rtx_PLUS (Pmode, result, const_addend);
8332 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8336 /* If X is a machine specific address (i.e. a symbol or label being
8337 referenced as a displacement from the GOT implemented using an
8338 UNSPEC), then return the base term. Otherwise return X. */
8341 ix86_find_base_term (rtx x)
8347 if (GET_CODE (x) != CONST)
8350 if (GET_CODE (term) == PLUS
8351 && (CONST_INT_P (XEXP (term, 1))
8352 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8353 term = XEXP (term, 0);
8354 if (GET_CODE (term) != UNSPEC
8355 || XINT (term, 1) != UNSPEC_GOTPCREL)
8358 term = XVECEXP (term, 0, 0);
8360 if (GET_CODE (term) != SYMBOL_REF
8361 && GET_CODE (term) != LABEL_REF)
8367 term = ix86_delegitimize_address (x);
8369 if (GET_CODE (term) != SYMBOL_REF
8370 && GET_CODE (term) != LABEL_REF)
8377 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8382 if (mode == CCFPmode || mode == CCFPUmode)
8384 enum rtx_code second_code, bypass_code;
8385 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8386 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8387 code = ix86_fp_compare_code_to_integer (code);
8391 code = reverse_condition (code);
8442 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8446 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8447 Those same assemblers have the same but opposite lossage on cmov. */
8449 suffix = fp ? "nbe" : "a";
8450 else if (mode == CCCmode)
8473 gcc_assert (mode == CCmode || mode == CCCmode);
8495 gcc_assert (mode == CCmode || mode == CCCmode);
8496 suffix = fp ? "nb" : "ae";
8499 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8506 else if (mode == CCCmode)
8507 suffix = fp ? "nb" : "ae";
8512 suffix = fp ? "u" : "p";
8515 suffix = fp ? "nu" : "np";
8520 fputs (suffix, file);
8523 /* Print the name of register X to FILE based on its machine mode and number.
8524 If CODE is 'w', pretend the mode is HImode.
8525 If CODE is 'b', pretend the mode is QImode.
8526 If CODE is 'k', pretend the mode is SImode.
8527 If CODE is 'q', pretend the mode is DImode.
8528 If CODE is 'h', pretend the reg is the 'high' byte register.
8529 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8532 print_reg (rtx x, int code, FILE *file)
8534 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
8535 && REGNO (x) != FRAME_POINTER_REGNUM
8536 && REGNO (x) != FLAGS_REG
8537 && REGNO (x) != FPSR_REG
8538 && REGNO (x) != FPCR_REG);
8540 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
8543 if (code == 'w' || MMX_REG_P (x))
8545 else if (code == 'b')
8547 else if (code == 'k')
8549 else if (code == 'q')
8551 else if (code == 'y')
8553 else if (code == 'h')
8556 code = GET_MODE_SIZE (GET_MODE (x));
8558 /* Irritatingly, AMD extended registers use different naming convention
8559 from the normal registers. */
8560 if (REX_INT_REG_P (x))
8562 gcc_assert (TARGET_64BIT);
8566 error ("extended registers have no high halves");
8569 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8572 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8575 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8578 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8581 error ("unsupported operand size for extended register");
8589 if (STACK_TOP_P (x))
8591 fputs ("st(0)", file);
8598 if (! ANY_FP_REG_P (x))
8599 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8604 fputs (hi_reg_name[REGNO (x)], file);
8607 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8609 fputs (qi_reg_name[REGNO (x)], file);
8612 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8614 fputs (qi_high_reg_name[REGNO (x)], file);
8621 /* Locate some local-dynamic symbol still in use by this function
8622 so that we can print its name in some tls_local_dynamic_base
8626 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8630 if (GET_CODE (x) == SYMBOL_REF
8631 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8633 cfun->machine->some_ld_name = XSTR (x, 0);
8641 get_some_local_dynamic_name (void)
8645 if (cfun->machine->some_ld_name)
8646 return cfun->machine->some_ld_name;
8648 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8650 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8651 return cfun->machine->some_ld_name;
8657 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8658 C -- print opcode suffix for set/cmov insn.
8659 c -- like C, but print reversed condition
8660 F,f -- likewise, but for floating-point.
8661 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8663 R -- print the prefix for register names.
8664 z -- print the opcode suffix for the size of the current operand.
8665 * -- print a star (in certain assembler syntax)
8666 A -- print an absolute memory reference.
8667 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8668 s -- print a shift double count, followed by the assemblers argument
8670 b -- print the QImode name of the register for the indicated operand.
8671 %b0 would print %al if operands[0] is reg 0.
8672 w -- likewise, print the HImode name of the register.
8673 k -- likewise, print the SImode name of the register.
8674 q -- likewise, print the DImode name of the register.
8675 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8676 y -- print "st(0)" instead of "st" as a register.
8677 D -- print condition for SSE cmp instruction.
8678 P -- if PIC, print an @PLT suffix.
8679 X -- don't print any sort of PIC '@' suffix for a symbol.
8680 & -- print some in-use local-dynamic symbol name.
8681 H -- print a memory address offset by 8; used for sse high-parts
8682 Y -- print condition for SSE5 com* instruction.
8683 + -- print a branch hint as 'cs' or 'ds' prefix
8684 ; -- print a semicolon (after prefixes due to bug in older gas).
8688 print_operand (FILE *file, rtx x, int code)
8695 if (ASSEMBLER_DIALECT == ASM_ATT)
8700 assemble_name (file, get_some_local_dynamic_name ());
8704 switch (ASSEMBLER_DIALECT)
8711 /* Intel syntax. For absolute addresses, registers should not
8712 be surrounded by braces. */
8716 PRINT_OPERAND (file, x, 0);
8726 PRINT_OPERAND (file, x, 0);
8731 if (ASSEMBLER_DIALECT == ASM_ATT)
8736 if (ASSEMBLER_DIALECT == ASM_ATT)
8741 if (ASSEMBLER_DIALECT == ASM_ATT)
8746 if (ASSEMBLER_DIALECT == ASM_ATT)
8751 if (ASSEMBLER_DIALECT == ASM_ATT)
8756 if (ASSEMBLER_DIALECT == ASM_ATT)
8761 /* 387 opcodes don't get size suffixes if the operands are
8763 if (STACK_REG_P (x))
8766 /* Likewise if using Intel opcodes. */
8767 if (ASSEMBLER_DIALECT == ASM_INTEL)
8770 /* This is the size of op from size of operand. */
8771 switch (GET_MODE_SIZE (GET_MODE (x)))
8780 #ifdef HAVE_GAS_FILDS_FISTS
8790 if (GET_MODE (x) == SFmode)
8805 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
8807 #ifdef GAS_MNEMONICS
8833 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
8835 PRINT_OPERAND (file, x, 0);
8841 /* Little bit of braindamage here. The SSE compare instructions
8842 does use completely different names for the comparisons that the
8843 fp conditional moves. */
8844 switch (GET_CODE (x))
8859 fputs ("unord", file);
8863 fputs ("neq", file);
8867 fputs ("nlt", file);
8871 fputs ("nle", file);
8874 fputs ("ord", file);
8881 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8882 if (ASSEMBLER_DIALECT == ASM_ATT)
8884 switch (GET_MODE (x))
8886 case HImode: putc ('w', file); break;
8888 case SFmode: putc ('l', file); break;
8890 case DFmode: putc ('q', file); break;
8891 default: gcc_unreachable ();
8898 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
8901 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8902 if (ASSEMBLER_DIALECT == ASM_ATT)
8905 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
8908 /* Like above, but reverse condition */
8910 /* Check to see if argument to %c is really a constant
8911 and not a condition code which needs to be reversed. */
8912 if (!COMPARISON_P (x))
8914 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
8917 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
8920 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8921 if (ASSEMBLER_DIALECT == ASM_ATT)
8924 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
8928 /* It doesn't actually matter what mode we use here, as we're
8929 only going to use this for printing. */
8930 x = adjust_address_nv (x, DImode, 8);
8937 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
8940 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
8943 int pred_val = INTVAL (XEXP (x, 0));
8945 if (pred_val < REG_BR_PROB_BASE * 45 / 100
8946 || pred_val > REG_BR_PROB_BASE * 55 / 100)
8948 int taken = pred_val > REG_BR_PROB_BASE / 2;
8949 int cputaken = final_forward_branch_p (current_output_insn) == 0;
8951 /* Emit hints only in the case default branch prediction
8952 heuristics would fail. */
8953 if (taken != cputaken)
8955 /* We use 3e (DS) prefix for taken branches and
8956 2e (CS) prefix for not taken branches. */
8958 fputs ("ds ; ", file);
8960 fputs ("cs ; ", file);
8968 switch (GET_CODE (x))
8971 fputs ("neq", file);
8978 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
8982 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
8993 fputs ("unord", file);
8996 fputs ("ord", file);
8999 fputs ("ueq", file);
9002 fputs ("nlt", file);
9005 fputs ("nle", file);
9008 fputs ("ule", file);
9011 fputs ("ult", file);
9014 fputs ("une", file);
9023 fputs (" ; ", file);
9030 output_operand_lossage ("invalid operand code '%c'", code);
9035 print_reg (x, code, file);
9039 /* No `byte ptr' prefix for call instructions. */
9040 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
9043 switch (GET_MODE_SIZE (GET_MODE (x)))
9045 case 1: size = "BYTE"; break;
9046 case 2: size = "WORD"; break;
9047 case 4: size = "DWORD"; break;
9048 case 8: size = "QWORD"; break;
9049 case 12: size = "XWORD"; break;
9050 case 16: size = "XMMWORD"; break;
9055 /* Check for explicit size override (codes 'b', 'w' and 'k') */
9058 else if (code == 'w')
9060 else if (code == 'k')
9064 fputs (" PTR ", file);
9068 /* Avoid (%rip) for call operands. */
9069 if (CONSTANT_ADDRESS_P (x) && code == 'P'
9070 && !CONST_INT_P (x))
9071 output_addr_const (file, x);
9072 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
9073 output_operand_lossage ("invalid constraints for operand");
9078 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9083 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9084 REAL_VALUE_TO_TARGET_SINGLE (r, l);
9086 if (ASSEMBLER_DIALECT == ASM_ATT)
9088 fprintf (file, "0x%08lx", l);
9091 /* These float cases don't actually occur as immediate operands. */
9092 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9096 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9097 fprintf (file, "%s", dstr);
9100 else if (GET_CODE (x) == CONST_DOUBLE
9101 && GET_MODE (x) == XFmode)
9105 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9106 fprintf (file, "%s", dstr);
9111 /* We have patterns that allow zero sets of memory, for instance.
9112 In 64-bit mode, we should probably support all 8-byte vectors,
9113 since we can in fact encode that into an immediate. */
9114 if (GET_CODE (x) == CONST_VECTOR)
9116 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
9122 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
9124 if (ASSEMBLER_DIALECT == ASM_ATT)
9127 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
9128 || GET_CODE (x) == LABEL_REF)
9130 if (ASSEMBLER_DIALECT == ASM_ATT)
9133 fputs ("OFFSET FLAT:", file);
9136 if (CONST_INT_P (x))
9137 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9139 output_pic_addr_const (file, x, code);
9141 output_addr_const (file, x);
9145 /* Print a memory operand whose address is ADDR. */
9148 print_operand_address (FILE *file, rtx addr)
9150 struct ix86_address parts;
9151 rtx base, index, disp;
9153 int ok = ix86_decompose_address (addr, &parts);
9158 index = parts.index;
9160 scale = parts.scale;
9168 if (USER_LABEL_PREFIX[0] == 0)
9170 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
9176 if (!base && !index)
9178 /* Displacement only requires special attention. */
9180 if (CONST_INT_P (disp))
9182 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
9184 if (USER_LABEL_PREFIX[0] == 0)
9186 fputs ("ds:", file);
9188 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
9191 output_pic_addr_const (file, disp, 0);
9193 output_addr_const (file, disp);
9195 /* Use one byte shorter RIP relative addressing for 64bit mode. */
9198 if (GET_CODE (disp) == CONST
9199 && GET_CODE (XEXP (disp, 0)) == PLUS
9200 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9201 disp = XEXP (XEXP (disp, 0), 0);
9202 if (GET_CODE (disp) == LABEL_REF
9203 || (GET_CODE (disp) == SYMBOL_REF
9204 && SYMBOL_REF_TLS_MODEL (disp) == 0))
9205 fputs ("(%rip)", file);
9210 if (ASSEMBLER_DIALECT == ASM_ATT)
9215 output_pic_addr_const (file, disp, 0);
9216 else if (GET_CODE (disp) == LABEL_REF)
9217 output_asm_label (disp);
9219 output_addr_const (file, disp);
9224 print_reg (base, 0, file);
9228 print_reg (index, 0, file);
9230 fprintf (file, ",%d", scale);
9236 rtx offset = NULL_RTX;
9240 /* Pull out the offset of a symbol; print any symbol itself. */
9241 if (GET_CODE (disp) == CONST
9242 && GET_CODE (XEXP (disp, 0)) == PLUS
9243 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9245 offset = XEXP (XEXP (disp, 0), 1);
9246 disp = gen_rtx_CONST (VOIDmode,
9247 XEXP (XEXP (disp, 0), 0));
9251 output_pic_addr_const (file, disp, 0);
9252 else if (GET_CODE (disp) == LABEL_REF)
9253 output_asm_label (disp);
9254 else if (CONST_INT_P (disp))
9257 output_addr_const (file, disp);
9263 print_reg (base, 0, file);
9266 if (INTVAL (offset) >= 0)
9268 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9272 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9279 print_reg (index, 0, file);
9281 fprintf (file, "*%d", scale);
9289 output_addr_const_extra (FILE *file, rtx x)
9293 if (GET_CODE (x) != UNSPEC)
9296 op = XVECEXP (x, 0, 0);
9297 switch (XINT (x, 1))
9299 case UNSPEC_GOTTPOFF:
9300 output_addr_const (file, op);
9301 /* FIXME: This might be @TPOFF in Sun ld. */
9302 fputs ("@GOTTPOFF", file);
9305 output_addr_const (file, op);
9306 fputs ("@TPOFF", file);
9309 output_addr_const (file, op);
9311 fputs ("@TPOFF", file);
9313 fputs ("@NTPOFF", file);
9316 output_addr_const (file, op);
9317 fputs ("@DTPOFF", file);
9319 case UNSPEC_GOTNTPOFF:
9320 output_addr_const (file, op);
9322 fputs ("@GOTTPOFF(%rip)", file);
9324 fputs ("@GOTNTPOFF", file);
9326 case UNSPEC_INDNTPOFF:
9327 output_addr_const (file, op);
9328 fputs ("@INDNTPOFF", file);
9338 /* Split one or more DImode RTL references into pairs of SImode
9339 references. The RTL can be REG, offsettable MEM, integer constant, or
9340 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9341 split and "num" is its length. lo_half and hi_half are output arrays
9342 that parallel "operands". */
9345 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9349 rtx op = operands[num];
9351 /* simplify_subreg refuse to split volatile memory addresses,
9352 but we still have to handle it. */
9355 lo_half[num] = adjust_address (op, SImode, 0);
9356 hi_half[num] = adjust_address (op, SImode, 4);
9360 lo_half[num] = simplify_gen_subreg (SImode, op,
9361 GET_MODE (op) == VOIDmode
9362 ? DImode : GET_MODE (op), 0);
9363 hi_half[num] = simplify_gen_subreg (SImode, op,
9364 GET_MODE (op) == VOIDmode
9365 ? DImode : GET_MODE (op), 4);
9369 /* Split one or more TImode RTL references into pairs of DImode
9370 references. The RTL can be REG, offsettable MEM, integer constant, or
9371 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9372 split and "num" is its length. lo_half and hi_half are output arrays
9373 that parallel "operands". */
9376 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9380 rtx op = operands[num];
9382 /* simplify_subreg refuse to split volatile memory addresses, but we
9383 still have to handle it. */
9386 lo_half[num] = adjust_address (op, DImode, 0);
9387 hi_half[num] = adjust_address (op, DImode, 8);
9391 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
9392 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
9397 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
9398 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
9399 is the expression of the binary operation. The output may either be
9400 emitted here, or returned to the caller, like all output_* functions.
9402 There is no guarantee that the operands are the same mode, as they
9403 might be within FLOAT or FLOAT_EXTEND expressions. */
9405 #ifndef SYSV386_COMPAT
9406 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
9407 wants to fix the assemblers because that causes incompatibility
9408 with gcc. No-one wants to fix gcc because that causes
9409 incompatibility with assemblers... You can use the option of
9410 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
9411 #define SYSV386_COMPAT 1
9415 output_387_binary_op (rtx insn, rtx *operands)
9417 static char buf[30];
9420 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
9422 #ifdef ENABLE_CHECKING
9423 /* Even if we do not want to check the inputs, this documents input
9424 constraints. Which helps in understanding the following code. */
9425 if (STACK_REG_P (operands[0])
9426 && ((REG_P (operands[1])
9427 && REGNO (operands[0]) == REGNO (operands[1])
9428 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
9429 || (REG_P (operands[2])
9430 && REGNO (operands[0]) == REGNO (operands[2])
9431 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9432 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9435 gcc_assert (is_sse);
9438 switch (GET_CODE (operands[3]))
9441 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9442 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9450 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9451 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9459 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9460 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9468 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9469 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9483 if (GET_MODE (operands[0]) == SFmode)
9484 strcat (buf, "ss\t{%2, %0|%0, %2}");
9486 strcat (buf, "sd\t{%2, %0|%0, %2}");
9491 switch (GET_CODE (operands[3]))
9495 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9497 rtx temp = operands[2];
9498 operands[2] = operands[1];
9502 /* know operands[0] == operands[1]. */
9504 if (MEM_P (operands[2]))
9510 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9512 if (STACK_TOP_P (operands[0]))
9513 /* How is it that we are storing to a dead operand[2]?
9514 Well, presumably operands[1] is dead too. We can't
9515 store the result to st(0) as st(0) gets popped on this
9516 instruction. Instead store to operands[2] (which I
9517 think has to be st(1)). st(1) will be popped later.
9518 gcc <= 2.8.1 didn't have this check and generated
9519 assembly code that the Unixware assembler rejected. */
9520 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9522 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9526 if (STACK_TOP_P (operands[0]))
9527 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9529 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9534 if (MEM_P (operands[1]))
9540 if (MEM_P (operands[2]))
9546 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9549 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9550 derived assemblers, confusingly reverse the direction of
9551 the operation for fsub{r} and fdiv{r} when the
9552 destination register is not st(0). The Intel assembler
9553 doesn't have this brain damage. Read !SYSV386_COMPAT to
9554 figure out what the hardware really does. */
9555 if (STACK_TOP_P (operands[0]))
9556 p = "{p\t%0, %2|rp\t%2, %0}";
9558 p = "{rp\t%2, %0|p\t%0, %2}";
9560 if (STACK_TOP_P (operands[0]))
9561 /* As above for fmul/fadd, we can't store to st(0). */
9562 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9564 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9569 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9572 if (STACK_TOP_P (operands[0]))
9573 p = "{rp\t%0, %1|p\t%1, %0}";
9575 p = "{p\t%1, %0|rp\t%0, %1}";
9577 if (STACK_TOP_P (operands[0]))
9578 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9580 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9585 if (STACK_TOP_P (operands[0]))
9587 if (STACK_TOP_P (operands[1]))
9588 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9590 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9593 else if (STACK_TOP_P (operands[1]))
9596 p = "{\t%1, %0|r\t%0, %1}";
9598 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9604 p = "{r\t%2, %0|\t%0, %2}";
9606 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9619 /* Return needed mode for entity in optimize_mode_switching pass. */
9622 ix86_mode_needed (int entity, rtx insn)
9624 enum attr_i387_cw mode;
9626 /* The mode UNINITIALIZED is used to store control word after a
9627 function call or ASM pattern. The mode ANY specify that function
9628 has no requirements on the control word and make no changes in the
9629 bits we are interested in. */
9632 || (NONJUMP_INSN_P (insn)
9633 && (asm_noperands (PATTERN (insn)) >= 0
9634 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
9635 return I387_CW_UNINITIALIZED;
9637 if (recog_memoized (insn) < 0)
9640 mode = get_attr_i387_cw (insn);
9645 if (mode == I387_CW_TRUNC)
9650 if (mode == I387_CW_FLOOR)
9655 if (mode == I387_CW_CEIL)
9660 if (mode == I387_CW_MASK_PM)
9671 /* Output code to initialize control word copies used by trunc?f?i and
9672 rounding patterns. CURRENT_MODE is set to current control word,
9673 while NEW_MODE is set to new control word. */
9676 emit_i387_cw_initialization (int mode)
9678 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
9681 enum ix86_stack_slot slot;
9683 rtx reg = gen_reg_rtx (HImode);
9685 emit_insn (gen_x86_fnstcw_1 (stored_mode));
9686 emit_move_insn (reg, copy_rtx (stored_mode));
9688 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
9693 /* round toward zero (truncate) */
9694 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
9695 slot = SLOT_CW_TRUNC;
9699 /* round down toward -oo */
9700 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9701 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
9702 slot = SLOT_CW_FLOOR;
9706 /* round up toward +oo */
9707 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9708 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
9709 slot = SLOT_CW_CEIL;
9712 case I387_CW_MASK_PM:
9713 /* mask precision exception for nearbyint() */
9714 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9715 slot = SLOT_CW_MASK_PM;
9727 /* round toward zero (truncate) */
9728 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
9729 slot = SLOT_CW_TRUNC;
9733 /* round down toward -oo */
9734 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
9735 slot = SLOT_CW_FLOOR;
9739 /* round up toward +oo */
9740 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
9741 slot = SLOT_CW_CEIL;
9744 case I387_CW_MASK_PM:
9745 /* mask precision exception for nearbyint() */
9746 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9747 slot = SLOT_CW_MASK_PM;
9755 gcc_assert (slot < MAX_386_STACK_LOCALS);
9757 new_mode = assign_386_stack_local (HImode, slot);
9758 emit_move_insn (new_mode, reg);
9761 /* Output code for INSN to convert a float to a signed int. OPERANDS
9762 are the insn operands. The output may be [HSD]Imode and the input
9763 operand may be [SDX]Fmode. */
9766 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
9768 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9769 int dimode_p = GET_MODE (operands[0]) == DImode;
9770 int round_mode = get_attr_i387_cw (insn);
9772 /* Jump through a hoop or two for DImode, since the hardware has no
9773 non-popping instruction. We used to do this a different way, but
9774 that was somewhat fragile and broke with post-reload splitters. */
9775 if ((dimode_p || fisttp) && !stack_top_dies)
9776 output_asm_insn ("fld\t%y1", operands);
9778 gcc_assert (STACK_TOP_P (operands[1]));
9779 gcc_assert (MEM_P (operands[0]));
9780 gcc_assert (GET_MODE (operands[1]) != TFmode);
9783 output_asm_insn ("fisttp%z0\t%0", operands);
9786 if (round_mode != I387_CW_ANY)
9787 output_asm_insn ("fldcw\t%3", operands);
9788 if (stack_top_dies || dimode_p)
9789 output_asm_insn ("fistp%z0\t%0", operands);
9791 output_asm_insn ("fist%z0\t%0", operands);
9792 if (round_mode != I387_CW_ANY)
9793 output_asm_insn ("fldcw\t%2", operands);
9799 /* Output code for x87 ffreep insn. The OPNO argument, which may only
9800 have the values zero or one, indicates the ffreep insn's operand
9801 from the OPERANDS array. */
9804 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
9806 if (TARGET_USE_FFREEP)
9807 #if HAVE_AS_IX86_FFREEP
9808 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
9811 static char retval[] = ".word\t0xc_df";
9812 int regno = REGNO (operands[opno]);
9814 gcc_assert (FP_REGNO_P (regno));
9816 retval[9] = '0' + (regno - FIRST_STACK_REG);
9821 return opno ? "fstp\t%y1" : "fstp\t%y0";
9825 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9826 should be used. UNORDERED_P is true when fucom should be used. */
9829 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
9832 rtx cmp_op0, cmp_op1;
9833 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
9837 cmp_op0 = operands[0];
9838 cmp_op1 = operands[1];
9842 cmp_op0 = operands[1];
9843 cmp_op1 = operands[2];
9848 if (GET_MODE (operands[0]) == SFmode)
9850 return "ucomiss\t{%1, %0|%0, %1}";
9852 return "comiss\t{%1, %0|%0, %1}";
9855 return "ucomisd\t{%1, %0|%0, %1}";
9857 return "comisd\t{%1, %0|%0, %1}";
9860 gcc_assert (STACK_TOP_P (cmp_op0));
9862 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9864 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
9868 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
9869 return output_387_ffreep (operands, 1);
9872 return "ftst\n\tfnstsw\t%0";
9875 if (STACK_REG_P (cmp_op1)
9877 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
9878 && REGNO (cmp_op1) != FIRST_STACK_REG)
9880 /* If both the top of the 387 stack dies, and the other operand
9881 is also a stack register that dies, then this must be a
9882 `fcompp' float compare */
9886 /* There is no double popping fcomi variant. Fortunately,
9887 eflags is immune from the fstp's cc clobbering. */
9889 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
9891 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
9892 return output_387_ffreep (operands, 0);
9897 return "fucompp\n\tfnstsw\t%0";
9899 return "fcompp\n\tfnstsw\t%0";
9904 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
9906 static const char * const alt[16] =
9908 "fcom%z2\t%y2\n\tfnstsw\t%0",
9909 "fcomp%z2\t%y2\n\tfnstsw\t%0",
9910 "fucom%z2\t%y2\n\tfnstsw\t%0",
9911 "fucomp%z2\t%y2\n\tfnstsw\t%0",
9913 "ficom%z2\t%y2\n\tfnstsw\t%0",
9914 "ficomp%z2\t%y2\n\tfnstsw\t%0",
9918 "fcomi\t{%y1, %0|%0, %y1}",
9919 "fcomip\t{%y1, %0|%0, %y1}",
9920 "fucomi\t{%y1, %0|%0, %y1}",
9921 "fucomip\t{%y1, %0|%0, %y1}",
9932 mask = eflags_p << 3;
9933 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
9934 mask |= unordered_p << 1;
9935 mask |= stack_top_dies;
9937 gcc_assert (mask < 16);
9946 ix86_output_addr_vec_elt (FILE *file, int value)
9948 const char *directive = ASM_LONG;
9952 directive = ASM_QUAD;
9954 gcc_assert (!TARGET_64BIT);
9957 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
9961 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
9963 const char *directive = ASM_LONG;
9966 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
9967 directive = ASM_QUAD;
9969 gcc_assert (!TARGET_64BIT);
9971 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
9972 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
9973 fprintf (file, "%s%s%d-%s%d\n",
9974 directive, LPREFIX, value, LPREFIX, rel);
9975 else if (HAVE_AS_GOTOFF_IN_DATA)
9976 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
9978 else if (TARGET_MACHO)
9980 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
9981 machopic_output_function_base_name (file);
9982 fprintf(file, "\n");
9986 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
9987 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
9990 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
9994 ix86_expand_clear (rtx dest)
9998 /* We play register width games, which are only valid after reload. */
9999 gcc_assert (reload_completed);
10001 /* Avoid HImode and its attendant prefix byte. */
10002 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
10003 dest = gen_rtx_REG (SImode, REGNO (dest));
10004 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
10006 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
10007 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
10009 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10010 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
10016 /* X is an unchanging MEM. If it is a constant pool reference, return
10017 the constant pool rtx, else NULL. */
10020 maybe_get_pool_constant (rtx x)
10022 x = ix86_delegitimize_address (XEXP (x, 0));
10024 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
10025 return get_pool_constant (x);
10031 ix86_expand_move (enum machine_mode mode, rtx operands[])
10034 enum tls_model model;
10039 if (GET_CODE (op1) == SYMBOL_REF)
10041 model = SYMBOL_REF_TLS_MODEL (op1);
10044 op1 = legitimize_tls_address (op1, model, true);
10045 op1 = force_operand (op1, op0);
10049 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10050 && SYMBOL_REF_DLLIMPORT_P (op1))
10051 op1 = legitimize_dllimport_symbol (op1, false);
10053 else if (GET_CODE (op1) == CONST
10054 && GET_CODE (XEXP (op1, 0)) == PLUS
10055 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
10057 rtx addend = XEXP (XEXP (op1, 0), 1);
10058 rtx symbol = XEXP (XEXP (op1, 0), 0);
10061 model = SYMBOL_REF_TLS_MODEL (symbol);
10063 tmp = legitimize_tls_address (symbol, model, true);
10064 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10065 && SYMBOL_REF_DLLIMPORT_P (symbol))
10066 tmp = legitimize_dllimport_symbol (symbol, true);
10070 tmp = force_operand (tmp, NULL);
10071 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
10072 op0, 1, OPTAB_DIRECT);
10078 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
10080 if (TARGET_MACHO && !TARGET_64BIT)
10085 rtx temp = ((reload_in_progress
10086 || ((op0 && REG_P (op0))
10088 ? op0 : gen_reg_rtx (Pmode));
10089 op1 = machopic_indirect_data_reference (op1, temp);
10090 op1 = machopic_legitimize_pic_address (op1, mode,
10091 temp == op1 ? 0 : temp);
10093 else if (MACHOPIC_INDIRECT)
10094 op1 = machopic_indirect_data_reference (op1, 0);
10102 op1 = force_reg (Pmode, op1);
10103 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
10105 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
10106 op1 = legitimize_pic_address (op1, reg);
10115 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
10116 || !push_operand (op0, mode))
10118 op1 = force_reg (mode, op1);
10120 if (push_operand (op0, mode)
10121 && ! general_no_elim_operand (op1, mode))
10122 op1 = copy_to_mode_reg (mode, op1);
10124 /* Force large constants in 64bit compilation into register
10125 to get them CSEed. */
10126 if (can_create_pseudo_p ()
10127 && (mode == DImode) && TARGET_64BIT
10128 && immediate_operand (op1, mode)
10129 && !x86_64_zext_immediate_operand (op1, VOIDmode)
10130 && !register_operand (op0, mode)
10132 op1 = copy_to_mode_reg (mode, op1);
10134 if (can_create_pseudo_p ()
10135 && FLOAT_MODE_P (mode)
10136 && GET_CODE (op1) == CONST_DOUBLE)
10138 /* If we are loading a floating point constant to a register,
10139 force the value to memory now, since we'll get better code
10140 out the back end. */
10142 op1 = validize_mem (force_const_mem (mode, op1));
10143 if (!register_operand (op0, mode))
10145 rtx temp = gen_reg_rtx (mode);
10146 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
10147 emit_move_insn (op0, temp);
10153 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10157 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
10159 rtx op0 = operands[0], op1 = operands[1];
10160 unsigned int align = GET_MODE_ALIGNMENT (mode);
10162 /* Force constants other than zero into memory. We do not know how
10163 the instructions used to build constants modify the upper 64 bits
10164 of the register, once we have that information we may be able
10165 to handle some of them more efficiently. */
10166 if (can_create_pseudo_p ()
10167 && register_operand (op0, mode)
10168 && (CONSTANT_P (op1)
10169 || (GET_CODE (op1) == SUBREG
10170 && CONSTANT_P (SUBREG_REG (op1))))
10171 && standard_sse_constant_p (op1) <= 0)
10172 op1 = validize_mem (force_const_mem (mode, op1));
10174 /* TDmode values are passed as TImode on the stack. TImode values
10175 are moved via xmm registers, and moving them to stack can result in
10176 unaligned memory access. Use ix86_expand_vector_move_misalign()
10177 if memory operand is not aligned correctly. */
10178 if (can_create_pseudo_p ()
10179 && (mode == TImode) && !TARGET_64BIT
10180 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
10181 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
10185 /* ix86_expand_vector_move_misalign() does not like constants ... */
10186 if (CONSTANT_P (op1)
10187 || (GET_CODE (op1) == SUBREG
10188 && CONSTANT_P (SUBREG_REG (op1))))
10189 op1 = validize_mem (force_const_mem (mode, op1));
10191 /* ... nor both arguments in memory. */
10192 if (!register_operand (op0, mode)
10193 && !register_operand (op1, mode))
10194 op1 = force_reg (mode, op1);
10196 tmp[0] = op0; tmp[1] = op1;
10197 ix86_expand_vector_move_misalign (mode, tmp);
10201 /* Make operand1 a register if it isn't already. */
10202 if (can_create_pseudo_p ()
10203 && !register_operand (op0, mode)
10204 && !register_operand (op1, mode))
10206 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
10210 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10213 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
10214 straight to ix86_expand_vector_move. */
10215 /* Code generation for scalar reg-reg moves of single and double precision data:
10216 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
10220 if (x86_sse_partial_reg_dependency == true)
10225 Code generation for scalar loads of double precision data:
10226 if (x86_sse_split_regs == true)
10227 movlpd mem, reg (gas syntax)
10231 Code generation for unaligned packed loads of single precision data
10232 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
10233 if (x86_sse_unaligned_move_optimal)
10236 if (x86_sse_partial_reg_dependency == true)
10248 Code generation for unaligned packed loads of double precision data
10249 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
10250 if (x86_sse_unaligned_move_optimal)
10253 if (x86_sse_split_regs == true)
10266 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
10275 /* If we're optimizing for size, movups is the smallest. */
10278 op0 = gen_lowpart (V4SFmode, op0);
10279 op1 = gen_lowpart (V4SFmode, op1);
10280 emit_insn (gen_sse_movups (op0, op1));
10284 /* ??? If we have typed data, then it would appear that using
10285 movdqu is the only way to get unaligned data loaded with
10287 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10289 op0 = gen_lowpart (V16QImode, op0);
10290 op1 = gen_lowpart (V16QImode, op1);
10291 emit_insn (gen_sse2_movdqu (op0, op1));
10295 if (TARGET_SSE2 && mode == V2DFmode)
10299 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10301 op0 = gen_lowpart (V2DFmode, op0);
10302 op1 = gen_lowpart (V2DFmode, op1);
10303 emit_insn (gen_sse2_movupd (op0, op1));
10307 /* When SSE registers are split into halves, we can avoid
10308 writing to the top half twice. */
10309 if (TARGET_SSE_SPLIT_REGS)
10311 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10316 /* ??? Not sure about the best option for the Intel chips.
10317 The following would seem to satisfy; the register is
10318 entirely cleared, breaking the dependency chain. We
10319 then store to the upper half, with a dependency depth
10320 of one. A rumor has it that Intel recommends two movsd
10321 followed by an unpacklpd, but this is unconfirmed. And
10322 given that the dependency depth of the unpacklpd would
10323 still be one, I'm not sure why this would be better. */
10324 zero = CONST0_RTX (V2DFmode);
10327 m = adjust_address (op1, DFmode, 0);
10328 emit_insn (gen_sse2_loadlpd (op0, zero, m));
10329 m = adjust_address (op1, DFmode, 8);
10330 emit_insn (gen_sse2_loadhpd (op0, op0, m));
10334 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10336 op0 = gen_lowpart (V4SFmode, op0);
10337 op1 = gen_lowpart (V4SFmode, op1);
10338 emit_insn (gen_sse_movups (op0, op1));
10342 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
10343 emit_move_insn (op0, CONST0_RTX (mode));
10345 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10347 if (mode != V4SFmode)
10348 op0 = gen_lowpart (V4SFmode, op0);
10349 m = adjust_address (op1, V2SFmode, 0);
10350 emit_insn (gen_sse_loadlps (op0, op0, m));
10351 m = adjust_address (op1, V2SFmode, 8);
10352 emit_insn (gen_sse_loadhps (op0, op0, m));
10355 else if (MEM_P (op0))
10357 /* If we're optimizing for size, movups is the smallest. */
10360 op0 = gen_lowpart (V4SFmode, op0);
10361 op1 = gen_lowpart (V4SFmode, op1);
10362 emit_insn (gen_sse_movups (op0, op1));
10366 /* ??? Similar to above, only less clear because of quote
10367 typeless stores unquote. */
10368 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
10369 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10371 op0 = gen_lowpart (V16QImode, op0);
10372 op1 = gen_lowpart (V16QImode, op1);
10373 emit_insn (gen_sse2_movdqu (op0, op1));
10377 if (TARGET_SSE2 && mode == V2DFmode)
10379 m = adjust_address (op0, DFmode, 0);
10380 emit_insn (gen_sse2_storelpd (m, op1));
10381 m = adjust_address (op0, DFmode, 8);
10382 emit_insn (gen_sse2_storehpd (m, op1));
10386 if (mode != V4SFmode)
10387 op1 = gen_lowpart (V4SFmode, op1);
10388 m = adjust_address (op0, V2SFmode, 0);
10389 emit_insn (gen_sse_storelps (m, op1));
10390 m = adjust_address (op0, V2SFmode, 8);
10391 emit_insn (gen_sse_storehps (m, op1));
10395 gcc_unreachable ();
10398 /* Expand a push in MODE. This is some mode for which we do not support
10399 proper push instructions, at least from the registers that we expect
10400 the value to live in. */
10403 ix86_expand_push (enum machine_mode mode, rtx x)
10407 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
10408 GEN_INT (-GET_MODE_SIZE (mode)),
10409 stack_pointer_rtx, 1, OPTAB_DIRECT);
10410 if (tmp != stack_pointer_rtx)
10411 emit_move_insn (stack_pointer_rtx, tmp);
10413 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
10414 emit_move_insn (tmp, x);
10417 /* Helper function of ix86_fixup_binary_operands to canonicalize
10418 operand order. Returns true if the operands should be swapped. */
10421 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
10424 rtx dst = operands[0];
10425 rtx src1 = operands[1];
10426 rtx src2 = operands[2];
10428 /* If the operation is not commutative, we can't do anything. */
10429 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10432 /* Highest priority is that src1 should match dst. */
10433 if (rtx_equal_p (dst, src1))
10435 if (rtx_equal_p (dst, src2))
10438 /* Next highest priority is that immediate constants come second. */
10439 if (immediate_operand (src2, mode))
10441 if (immediate_operand (src1, mode))
10444 /* Lowest priority is that memory references should come second. */
10454 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10455 destination to use for the operation. If different from the true
10456 destination in operands[0], a copy operation will be required. */
10459 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10462 rtx dst = operands[0];
10463 rtx src1 = operands[1];
10464 rtx src2 = operands[2];
10466 /* Canonicalize operand order. */
10467 if (ix86_swap_binary_operands_p (code, mode, operands))
10474 /* Both source operands cannot be in memory. */
10475 if (MEM_P (src1) && MEM_P (src2))
10477 /* Optimization: Only read from memory once. */
10478 if (rtx_equal_p (src1, src2))
10480 src2 = force_reg (mode, src2);
10484 src2 = force_reg (mode, src2);
10487 /* If the destination is memory, and we do not have matching source
10488 operands, do things in registers. */
10489 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10490 dst = gen_reg_rtx (mode);
10492 /* Source 1 cannot be a constant. */
10493 if (CONSTANT_P (src1))
10494 src1 = force_reg (mode, src1);
10496 /* Source 1 cannot be a non-matching memory. */
10497 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10498 src1 = force_reg (mode, src1);
10500 operands[1] = src1;
10501 operands[2] = src2;
10505 /* Similarly, but assume that the destination has already been
10506 set up properly. */
10509 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10510 enum machine_mode mode, rtx operands[])
10512 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10513 gcc_assert (dst == operands[0]);
10516 /* Attempt to expand a binary operator. Make the expansion closer to the
10517 actual machine, then just general_operand, which will allow 3 separate
10518 memory references (one output, two input) in a single insn. */
10521 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10524 rtx src1, src2, dst, op, clob;
10526 dst = ix86_fixup_binary_operands (code, mode, operands);
10527 src1 = operands[1];
10528 src2 = operands[2];
10530 /* Emit the instruction. */
10532 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10533 if (reload_in_progress)
10535 /* Reload doesn't know about the flags register, and doesn't know that
10536 it doesn't want to clobber it. We can only do this with PLUS. */
10537 gcc_assert (code == PLUS);
10542 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10543 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10546 /* Fix up the destination if needed. */
10547 if (dst != operands[0])
10548 emit_move_insn (operands[0], dst);
10551 /* Return TRUE or FALSE depending on whether the binary operator meets the
10552 appropriate constraints. */
10555 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10558 rtx dst = operands[0];
10559 rtx src1 = operands[1];
10560 rtx src2 = operands[2];
10562 /* Both source operands cannot be in memory. */
10563 if (MEM_P (src1) && MEM_P (src2))
10566 /* Canonicalize operand order for commutative operators. */
10567 if (ix86_swap_binary_operands_p (code, mode, operands))
10574 /* If the destination is memory, we must have a matching source operand. */
10575 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10578 /* Source 1 cannot be a constant. */
10579 if (CONSTANT_P (src1))
10582 /* Source 1 cannot be a non-matching memory. */
10583 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10589 /* Attempt to expand a unary operator. Make the expansion closer to the
10590 actual machine, then just general_operand, which will allow 2 separate
10591 memory references (one output, one input) in a single insn. */
10594 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10597 int matching_memory;
10598 rtx src, dst, op, clob;
10603 /* If the destination is memory, and we do not have matching source
10604 operands, do things in registers. */
10605 matching_memory = 0;
10608 if (rtx_equal_p (dst, src))
10609 matching_memory = 1;
10611 dst = gen_reg_rtx (mode);
10614 /* When source operand is memory, destination must match. */
10615 if (MEM_P (src) && !matching_memory)
10616 src = force_reg (mode, src);
10618 /* Emit the instruction. */
10620 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10621 if (reload_in_progress || code == NOT)
10623 /* Reload doesn't know about the flags register, and doesn't know that
10624 it doesn't want to clobber it. */
10625 gcc_assert (code == NOT);
10630 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10631 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10634 /* Fix up the destination if needed. */
10635 if (dst != operands[0])
10636 emit_move_insn (operands[0], dst);
10639 /* Return TRUE or FALSE depending on whether the unary operator meets the
10640 appropriate constraints. */
10643 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
10644 enum machine_mode mode ATTRIBUTE_UNUSED,
10645 rtx operands[2] ATTRIBUTE_UNUSED)
10647 /* If one of operands is memory, source and destination must match. */
10648 if ((MEM_P (operands[0])
10649 || MEM_P (operands[1]))
10650 && ! rtx_equal_p (operands[0], operands[1]))
10655 /* Post-reload splitter for converting an SF or DFmode value in an
10656 SSE register into an unsigned SImode. */
10659 ix86_split_convert_uns_si_sse (rtx operands[])
10661 enum machine_mode vecmode;
10662 rtx value, large, zero_or_two31, input, two31, x;
10664 large = operands[1];
10665 zero_or_two31 = operands[2];
10666 input = operands[3];
10667 two31 = operands[4];
10668 vecmode = GET_MODE (large);
10669 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
10671 /* Load up the value into the low element. We must ensure that the other
10672 elements are valid floats -- zero is the easiest such value. */
10675 if (vecmode == V4SFmode)
10676 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
10678 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
10682 input = gen_rtx_REG (vecmode, REGNO (input));
10683 emit_move_insn (value, CONST0_RTX (vecmode));
10684 if (vecmode == V4SFmode)
10685 emit_insn (gen_sse_movss (value, value, input));
10687 emit_insn (gen_sse2_movsd (value, value, input));
10690 emit_move_insn (large, two31);
10691 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
10693 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
10694 emit_insn (gen_rtx_SET (VOIDmode, large, x));
10696 x = gen_rtx_AND (vecmode, zero_or_two31, large);
10697 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
10699 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
10700 emit_insn (gen_rtx_SET (VOIDmode, value, x));
10702 large = gen_rtx_REG (V4SImode, REGNO (large));
10703 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
10705 x = gen_rtx_REG (V4SImode, REGNO (value));
10706 if (vecmode == V4SFmode)
10707 emit_insn (gen_sse2_cvttps2dq (x, value));
10709 emit_insn (gen_sse2_cvttpd2dq (x, value));
10712 emit_insn (gen_xorv4si3 (value, value, large));
10715 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10716 Expects the 64-bit DImode to be supplied in a pair of integral
10717 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10718 -mfpmath=sse, !optimize_size only. */
10721 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
10723 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
10724 rtx int_xmm, fp_xmm;
10725 rtx biases, exponents;
10728 int_xmm = gen_reg_rtx (V4SImode);
10729 if (TARGET_INTER_UNIT_MOVES)
10730 emit_insn (gen_movdi_to_sse (int_xmm, input));
10731 else if (TARGET_SSE_SPLIT_REGS)
10733 emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
10734 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
10738 x = gen_reg_rtx (V2DImode);
10739 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
10740 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
10743 x = gen_rtx_CONST_VECTOR (V4SImode,
10744 gen_rtvec (4, GEN_INT (0x43300000UL),
10745 GEN_INT (0x45300000UL),
10746 const0_rtx, const0_rtx));
10747 exponents = validize_mem (force_const_mem (V4SImode, x));
10749 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10750 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
10752 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10753 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10754 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10755 (0x1.0p84 + double(fp_value_hi_xmm)).
10756 Note these exponents differ by 32. */
10758 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
10760 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10761 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10762 real_ldexp (&bias_lo_rvt, &dconst1, 52);
10763 real_ldexp (&bias_hi_rvt, &dconst1, 84);
10764 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
10765 x = const_double_from_real_value (bias_hi_rvt, DFmode);
10766 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
10767 biases = validize_mem (force_const_mem (V2DFmode, biases));
10768 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
10770 /* Add the upper and lower DFmode values together. */
10772 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
10775 x = copy_to_mode_reg (V2DFmode, fp_xmm);
10776 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
10777 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
10780 ix86_expand_vector_extract (false, target, fp_xmm, 0);
10783 /* Convert an unsigned SImode value into a DFmode. Only currently used
10784 for SSE, but applicable anywhere. */
10787 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
10789 REAL_VALUE_TYPE TWO31r;
10792 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
10793 NULL, 1, OPTAB_DIRECT);
10795 fp = gen_reg_rtx (DFmode);
10796 emit_insn (gen_floatsidf2 (fp, x));
10798 real_ldexp (&TWO31r, &dconst1, 31);
10799 x = const_double_from_real_value (TWO31r, DFmode);
10801 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
10803 emit_move_insn (target, x);
10806 /* Convert a signed DImode value into a DFmode. Only used for SSE in
10807 32-bit mode; otherwise we have a direct convert instruction. */
10810 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
10812 REAL_VALUE_TYPE TWO32r;
10813 rtx fp_lo, fp_hi, x;
10815 fp_lo = gen_reg_rtx (DFmode);
10816 fp_hi = gen_reg_rtx (DFmode);
10818 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
10820 real_ldexp (&TWO32r, &dconst1, 32);
10821 x = const_double_from_real_value (TWO32r, DFmode);
10822 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
10824 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
10826 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
10829 emit_move_insn (target, x);
10832 /* Convert an unsigned SImode value into a SFmode, using only SSE.
10833 For x86_32, -mfpmath=sse, !optimize_size only. */
10835 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
10837 REAL_VALUE_TYPE ONE16r;
10838 rtx fp_hi, fp_lo, int_hi, int_lo, x;
10840 real_ldexp (&ONE16r, &dconst1, 16);
10841 x = const_double_from_real_value (ONE16r, SFmode);
10842 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
10843 NULL, 0, OPTAB_DIRECT);
10844 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
10845 NULL, 0, OPTAB_DIRECT);
10846 fp_hi = gen_reg_rtx (SFmode);
10847 fp_lo = gen_reg_rtx (SFmode);
10848 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
10849 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
10850 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
10852 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
10854 if (!rtx_equal_p (target, fp_hi))
10855 emit_move_insn (target, fp_hi);
10858 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
10859 then replicate the value for all elements of the vector
10863 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
10870 v = gen_rtvec (4, value, value, value, value);
10871 return gen_rtx_CONST_VECTOR (V4SImode, v);
10875 v = gen_rtvec (2, value, value);
10876 return gen_rtx_CONST_VECTOR (V2DImode, v);
10880 v = gen_rtvec (4, value, value, value, value);
10882 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
10883 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
10884 return gen_rtx_CONST_VECTOR (V4SFmode, v);
10888 v = gen_rtvec (2, value, value);
10890 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
10891 return gen_rtx_CONST_VECTOR (V2DFmode, v);
10894 gcc_unreachable ();
10898 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
10899 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
10900 for an SSE register. If VECT is true, then replicate the mask for
10901 all elements of the vector register. If INVERT is true, then create
10902 a mask excluding the sign bit. */
10905 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
10907 enum machine_mode vec_mode, imode;
10908 HOST_WIDE_INT hi, lo;
10913 /* Find the sign bit, sign extended to 2*HWI. */
10919 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
10920 lo = 0x80000000, hi = lo < 0;
10926 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
10927 if (HOST_BITS_PER_WIDE_INT >= 64)
10928 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
10930 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
10936 vec_mode = VOIDmode;
10937 gcc_assert (HOST_BITS_PER_WIDE_INT >= 64);
10938 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
10942 gcc_unreachable ();
10946 lo = ~lo, hi = ~hi;
10948 /* Force this value into the low part of a fp vector constant. */
10949 mask = immed_double_const (lo, hi, imode);
10950 mask = gen_lowpart (mode, mask);
10952 if (vec_mode == VOIDmode)
10953 return force_reg (mode, mask);
10955 v = ix86_build_const_vector (mode, vect, mask);
10956 return force_reg (vec_mode, v);
10959 /* Generate code for floating point ABS or NEG. */
10962 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
10965 rtx mask, set, use, clob, dst, src;
10966 bool matching_memory;
10967 bool use_sse = false;
10968 bool vector_mode = VECTOR_MODE_P (mode);
10969 enum machine_mode elt_mode = mode;
10973 elt_mode = GET_MODE_INNER (mode);
10976 else if (mode == TFmode)
10978 else if (TARGET_SSE_MATH)
10979 use_sse = SSE_FLOAT_MODE_P (mode);
10981 /* NEG and ABS performed with SSE use bitwise mask operations.
10982 Create the appropriate mask now. */
10984 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
10991 /* If the destination is memory, and we don't have matching source
10992 operands or we're using the x87, do things in registers. */
10993 matching_memory = false;
10996 if (use_sse && rtx_equal_p (dst, src))
10997 matching_memory = true;
10999 dst = gen_reg_rtx (mode);
11001 if (MEM_P (src) && !matching_memory)
11002 src = force_reg (mode, src);
11006 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
11007 set = gen_rtx_SET (VOIDmode, dst, set);
11012 set = gen_rtx_fmt_e (code, mode, src);
11013 set = gen_rtx_SET (VOIDmode, dst, set);
11016 use = gen_rtx_USE (VOIDmode, mask);
11017 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11018 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11019 gen_rtvec (3, set, use, clob)));
11025 if (dst != operands[0])
11026 emit_move_insn (operands[0], dst);
11029 /* Expand a copysign operation. Special case operand 0 being a constant. */
11032 ix86_expand_copysign (rtx operands[])
11034 enum machine_mode mode, vmode;
11035 rtx dest, op0, op1, mask, nmask;
11037 dest = operands[0];
11041 mode = GET_MODE (dest);
11042 vmode = mode == SFmode ? V4SFmode : V2DFmode;
11044 if (GET_CODE (op0) == CONST_DOUBLE)
11046 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
11048 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
11049 op0 = simplify_unary_operation (ABS, mode, op0, mode);
11051 if (mode == SFmode || mode == DFmode)
11053 if (op0 == CONST0_RTX (mode))
11054 op0 = CONST0_RTX (vmode);
11059 if (mode == SFmode)
11060 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
11061 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11063 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
11064 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
11068 mask = ix86_build_signbit_mask (mode, 0, 0);
11070 if (mode == SFmode)
11071 copysign_insn = gen_copysignsf3_const;
11072 else if (mode == DFmode)
11073 copysign_insn = gen_copysigndf3_const;
11075 copysign_insn = gen_copysigntf3_const;
11077 emit_insn (copysign_insn (dest, op0, op1, mask));
11081 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
11083 nmask = ix86_build_signbit_mask (mode, 0, 1);
11084 mask = ix86_build_signbit_mask (mode, 0, 0);
11086 if (mode == SFmode)
11087 copysign_insn = gen_copysignsf3_var;
11088 else if (mode == DFmode)
11089 copysign_insn = gen_copysigndf3_var;
11091 copysign_insn = gen_copysigntf3_var;
11093 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
11097 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
11098 be a constant, and so has already been expanded into a vector constant. */
11101 ix86_split_copysign_const (rtx operands[])
11103 enum machine_mode mode, vmode;
11104 rtx dest, op0, op1, mask, x;
11106 dest = operands[0];
11109 mask = operands[3];
11111 mode = GET_MODE (dest);
11112 vmode = GET_MODE (mask);
11114 dest = simplify_gen_subreg (vmode, dest, mode, 0);
11115 x = gen_rtx_AND (vmode, dest, mask);
11116 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11118 if (op0 != CONST0_RTX (vmode))
11120 x = gen_rtx_IOR (vmode, dest, op0);
11121 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11125 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
11126 so we have to do two masks. */
11129 ix86_split_copysign_var (rtx operands[])
11131 enum machine_mode mode, vmode;
11132 rtx dest, scratch, op0, op1, mask, nmask, x;
11134 dest = operands[0];
11135 scratch = operands[1];
11138 nmask = operands[4];
11139 mask = operands[5];
11141 mode = GET_MODE (dest);
11142 vmode = GET_MODE (mask);
11144 if (rtx_equal_p (op0, op1))
11146 /* Shouldn't happen often (it's useless, obviously), but when it does
11147 we'd generate incorrect code if we continue below. */
11148 emit_move_insn (dest, op0);
11152 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
11154 gcc_assert (REGNO (op1) == REGNO (scratch));
11156 x = gen_rtx_AND (vmode, scratch, mask);
11157 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11160 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11161 x = gen_rtx_NOT (vmode, dest);
11162 x = gen_rtx_AND (vmode, x, op0);
11163 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11167 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
11169 x = gen_rtx_AND (vmode, scratch, mask);
11171 else /* alternative 2,4 */
11173 gcc_assert (REGNO (mask) == REGNO (scratch));
11174 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
11175 x = gen_rtx_AND (vmode, scratch, op1);
11177 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11179 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
11181 dest = simplify_gen_subreg (vmode, op0, mode, 0);
11182 x = gen_rtx_AND (vmode, dest, nmask);
11184 else /* alternative 3,4 */
11186 gcc_assert (REGNO (nmask) == REGNO (dest));
11188 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11189 x = gen_rtx_AND (vmode, dest, op0);
11191 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11194 x = gen_rtx_IOR (vmode, dest, scratch);
11195 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11198 /* Return TRUE or FALSE depending on whether the first SET in INSN
11199 has source and destination with matching CC modes, and that the
11200 CC mode is at least as constrained as REQ_MODE. */
11203 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
11206 enum machine_mode set_mode;
11208 set = PATTERN (insn);
11209 if (GET_CODE (set) == PARALLEL)
11210 set = XVECEXP (set, 0, 0);
11211 gcc_assert (GET_CODE (set) == SET);
11212 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
11214 set_mode = GET_MODE (SET_DEST (set));
11218 if (req_mode != CCNOmode
11219 && (req_mode != CCmode
11220 || XEXP (SET_SRC (set), 1) != const0_rtx))
11224 if (req_mode == CCGCmode)
11228 if (req_mode == CCGOCmode || req_mode == CCNOmode)
11232 if (req_mode == CCZmode)
11239 gcc_unreachable ();
11242 return (GET_MODE (SET_SRC (set)) == set_mode);
11245 /* Generate insn patterns to do an integer compare of OPERANDS. */
11248 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
11250 enum machine_mode cmpmode;
11253 cmpmode = SELECT_CC_MODE (code, op0, op1);
11254 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
11256 /* This is very simple, but making the interface the same as in the
11257 FP case makes the rest of the code easier. */
11258 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
11259 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
11261 /* Return the test that should be put into the flags user, i.e.
11262 the bcc, scc, or cmov instruction. */
11263 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
11266 /* Figure out whether to use ordered or unordered fp comparisons.
11267 Return the appropriate mode to use. */
11270 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
11272 /* ??? In order to make all comparisons reversible, we do all comparisons
11273 non-trapping when compiling for IEEE. Once gcc is able to distinguish
11274 all forms trapping and nontrapping comparisons, we can make inequality
11275 comparisons trapping again, since it results in better code when using
11276 FCOM based compares. */
11277 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
11281 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
11283 enum machine_mode mode = GET_MODE (op0);
11285 if (SCALAR_FLOAT_MODE_P (mode))
11287 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11288 return ix86_fp_compare_mode (code);
11293 /* Only zero flag is needed. */
11294 case EQ: /* ZF=0 */
11295 case NE: /* ZF!=0 */
11297 /* Codes needing carry flag. */
11298 case GEU: /* CF=0 */
11299 case LTU: /* CF=1 */
11300 /* Detect overflow checks. They need just the carry flag. */
11301 if (GET_CODE (op0) == PLUS
11302 && rtx_equal_p (op1, XEXP (op0, 0)))
11306 case GTU: /* CF=0 & ZF=0 */
11307 case LEU: /* CF=1 | ZF=1 */
11308 /* Detect overflow checks. They need just the carry flag. */
11309 if (GET_CODE (op0) == MINUS
11310 && rtx_equal_p (op1, XEXP (op0, 0)))
11314 /* Codes possibly doable only with sign flag when
11315 comparing against zero. */
11316 case GE: /* SF=OF or SF=0 */
11317 case LT: /* SF<>OF or SF=1 */
11318 if (op1 == const0_rtx)
11321 /* For other cases Carry flag is not required. */
11323 /* Codes doable only with sign flag when comparing
11324 against zero, but we miss jump instruction for it
11325 so we need to use relational tests against overflow
11326 that thus needs to be zero. */
11327 case GT: /* ZF=0 & SF=OF */
11328 case LE: /* ZF=1 | SF<>OF */
11329 if (op1 == const0_rtx)
11333 /* strcmp pattern do (use flags) and combine may ask us for proper
11338 gcc_unreachable ();
11342 /* Return the fixed registers used for condition codes. */
11345 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
11352 /* If two condition code modes are compatible, return a condition code
11353 mode which is compatible with both. Otherwise, return
11356 static enum machine_mode
11357 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
11362 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
11365 if ((m1 == CCGCmode && m2 == CCGOCmode)
11366 || (m1 == CCGOCmode && m2 == CCGCmode))
11372 gcc_unreachable ();
11402 /* These are only compatible with themselves, which we already
11408 /* Split comparison code CODE into comparisons we can do using branch
11409 instructions. BYPASS_CODE is comparison code for branch that will
11410 branch around FIRST_CODE and SECOND_CODE. If some of branches
11411 is not required, set value to UNKNOWN.
11412 We never require more than two branches. */
11415 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
11416 enum rtx_code *first_code,
11417 enum rtx_code *second_code)
11419 *first_code = code;
11420 *bypass_code = UNKNOWN;
11421 *second_code = UNKNOWN;
11423 /* The fcomi comparison sets flags as follows:
11433 case GT: /* GTU - CF=0 & ZF=0 */
11434 case GE: /* GEU - CF=0 */
11435 case ORDERED: /* PF=0 */
11436 case UNORDERED: /* PF=1 */
11437 case UNEQ: /* EQ - ZF=1 */
11438 case UNLT: /* LTU - CF=1 */
11439 case UNLE: /* LEU - CF=1 | ZF=1 */
11440 case LTGT: /* EQ - ZF=0 */
11442 case LT: /* LTU - CF=1 - fails on unordered */
11443 *first_code = UNLT;
11444 *bypass_code = UNORDERED;
11446 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
11447 *first_code = UNLE;
11448 *bypass_code = UNORDERED;
11450 case EQ: /* EQ - ZF=1 - fails on unordered */
11451 *first_code = UNEQ;
11452 *bypass_code = UNORDERED;
11454 case NE: /* NE - ZF=0 - fails on unordered */
11455 *first_code = LTGT;
11456 *second_code = UNORDERED;
11458 case UNGE: /* GEU - CF=0 - fails on unordered */
11460 *second_code = UNORDERED;
11462 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
11464 *second_code = UNORDERED;
11467 gcc_unreachable ();
11469 if (!TARGET_IEEE_FP)
11471 *second_code = UNKNOWN;
11472 *bypass_code = UNKNOWN;
11476 /* Return cost of comparison done fcom + arithmetics operations on AX.
11477 All following functions do use number of instructions as a cost metrics.
11478 In future this should be tweaked to compute bytes for optimize_size and
11479 take into account performance of various instructions on various CPUs. */
11481 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
11483 if (!TARGET_IEEE_FP)
11485 /* The cost of code output by ix86_expand_fp_compare. */
11509 gcc_unreachable ();
11513 /* Return cost of comparison done using fcomi operation.
11514 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11516 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11518 enum rtx_code bypass_code, first_code, second_code;
11519 /* Return arbitrarily high cost when instruction is not supported - this
11520 prevents gcc from using it. */
11523 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11524 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11527 /* Return cost of comparison done using sahf operation.
11528 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11530 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11532 enum rtx_code bypass_code, first_code, second_code;
11533 /* Return arbitrarily high cost when instruction is not preferred - this
11534 avoids gcc from using it. */
11535 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11537 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11538 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11541 /* Compute cost of the comparison done using any method.
11542 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11544 ix86_fp_comparison_cost (enum rtx_code code)
11546 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11549 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11550 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11552 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11553 if (min > sahf_cost)
11555 if (min > fcomi_cost)
11560 /* Return true if we should use an FCOMI instruction for this
11564 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11566 enum rtx_code swapped_code = swap_condition (code);
11568 return ((ix86_fp_comparison_cost (code)
11569 == ix86_fp_comparison_fcomi_cost (code))
11570 || (ix86_fp_comparison_cost (swapped_code)
11571 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11574 /* Swap, force into registers, or otherwise massage the two operands
11575 to a fp comparison. The operands are updated in place; the new
11576 comparison code is returned. */
11578 static enum rtx_code
11579 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11581 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11582 rtx op0 = *pop0, op1 = *pop1;
11583 enum machine_mode op_mode = GET_MODE (op0);
11584 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11586 /* All of the unordered compare instructions only work on registers.
11587 The same is true of the fcomi compare instructions. The XFmode
11588 compare instructions require registers except when comparing
11589 against zero or when converting operand 1 from fixed point to
11593 && (fpcmp_mode == CCFPUmode
11594 || (op_mode == XFmode
11595 && ! (standard_80387_constant_p (op0) == 1
11596 || standard_80387_constant_p (op1) == 1)
11597 && GET_CODE (op1) != FLOAT)
11598 || ix86_use_fcomi_compare (code)))
11600 op0 = force_reg (op_mode, op0);
11601 op1 = force_reg (op_mode, op1);
11605 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11606 things around if they appear profitable, otherwise force op0
11607 into a register. */
11609 if (standard_80387_constant_p (op0) == 0
11611 && ! (standard_80387_constant_p (op1) == 0
11615 tmp = op0, op0 = op1, op1 = tmp;
11616 code = swap_condition (code);
11620 op0 = force_reg (op_mode, op0);
11622 if (CONSTANT_P (op1))
11624 int tmp = standard_80387_constant_p (op1);
11626 op1 = validize_mem (force_const_mem (op_mode, op1));
11630 op1 = force_reg (op_mode, op1);
11633 op1 = force_reg (op_mode, op1);
11637 /* Try to rearrange the comparison to make it cheaper. */
11638 if (ix86_fp_comparison_cost (code)
11639 > ix86_fp_comparison_cost (swap_condition (code))
11640 && (REG_P (op1) || can_create_pseudo_p ()))
11643 tmp = op0, op0 = op1, op1 = tmp;
11644 code = swap_condition (code);
11646 op0 = force_reg (op_mode, op0);
11654 /* Convert comparison codes we use to represent FP comparison to integer
11655 code that will result in proper branch. Return UNKNOWN if no such code
11659 ix86_fp_compare_code_to_integer (enum rtx_code code)
11688 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11691 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
11692 rtx *second_test, rtx *bypass_test)
11694 enum machine_mode fpcmp_mode, intcmp_mode;
11696 int cost = ix86_fp_comparison_cost (code);
11697 enum rtx_code bypass_code, first_code, second_code;
11699 fpcmp_mode = ix86_fp_compare_mode (code);
11700 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
11703 *second_test = NULL_RTX;
11705 *bypass_test = NULL_RTX;
11707 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11709 /* Do fcomi/sahf based test when profitable. */
11710 if (ix86_fp_comparison_arithmetics_cost (code) > cost
11711 && (bypass_code == UNKNOWN || bypass_test)
11712 && (second_code == UNKNOWN || second_test))
11714 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11715 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
11721 gcc_assert (TARGET_SAHF);
11724 scratch = gen_reg_rtx (HImode);
11725 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
11727 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
11730 /* The FP codes work out to act like unsigned. */
11731 intcmp_mode = fpcmp_mode;
11733 if (bypass_code != UNKNOWN)
11734 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
11735 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11737 if (second_code != UNKNOWN)
11738 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
11739 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11744 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11745 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11746 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11748 scratch = gen_reg_rtx (HImode);
11749 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11751 /* In the unordered case, we have to check C2 for NaN's, which
11752 doesn't happen to work out to anything nice combination-wise.
11753 So do some bit twiddling on the value we've got in AH to come
11754 up with an appropriate set of condition codes. */
11756 intcmp_mode = CCNOmode;
11761 if (code == GT || !TARGET_IEEE_FP)
11763 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11768 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11769 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11770 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
11771 intcmp_mode = CCmode;
11777 if (code == LT && TARGET_IEEE_FP)
11779 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11780 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
11781 intcmp_mode = CCmode;
11786 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
11792 if (code == GE || !TARGET_IEEE_FP)
11794 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
11799 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11800 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11807 if (code == LE && TARGET_IEEE_FP)
11809 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11810 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11811 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11812 intcmp_mode = CCmode;
11817 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11823 if (code == EQ && TARGET_IEEE_FP)
11825 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11826 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11827 intcmp_mode = CCmode;
11832 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11839 if (code == NE && TARGET_IEEE_FP)
11841 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11842 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11848 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11854 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11858 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11863 gcc_unreachable ();
11867 /* Return the test that should be put into the flags user, i.e.
11868 the bcc, scc, or cmov instruction. */
11869 return gen_rtx_fmt_ee (code, VOIDmode,
11870 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11875 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
11878 op0 = ix86_compare_op0;
11879 op1 = ix86_compare_op1;
11882 *second_test = NULL_RTX;
11884 *bypass_test = NULL_RTX;
11886 if (ix86_compare_emitted)
11888 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
11889 ix86_compare_emitted = NULL_RTX;
11891 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
11893 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
11894 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
11895 second_test, bypass_test);
11898 ret = ix86_expand_int_compare (code, op0, op1);
11903 /* Return true if the CODE will result in nontrivial jump sequence. */
11905 ix86_fp_jump_nontrivial_p (enum rtx_code code)
11907 enum rtx_code bypass_code, first_code, second_code;
11910 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11911 return bypass_code != UNKNOWN || second_code != UNKNOWN;
11915 ix86_expand_branch (enum rtx_code code, rtx label)
11919 /* If we have emitted a compare insn, go straight to simple.
11920 ix86_expand_compare won't emit anything if ix86_compare_emitted
11922 if (ix86_compare_emitted)
11925 switch (GET_MODE (ix86_compare_op0))
11931 tmp = ix86_expand_compare (code, NULL, NULL);
11932 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11933 gen_rtx_LABEL_REF (VOIDmode, label),
11935 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11944 enum rtx_code bypass_code, first_code, second_code;
11946 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
11947 &ix86_compare_op1);
11949 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11951 /* Check whether we will use the natural sequence with one jump. If
11952 so, we can expand jump early. Otherwise delay expansion by
11953 creating compound insn to not confuse optimizers. */
11954 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
11956 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
11957 gen_rtx_LABEL_REF (VOIDmode, label),
11958 pc_rtx, NULL_RTX, NULL_RTX);
11962 tmp = gen_rtx_fmt_ee (code, VOIDmode,
11963 ix86_compare_op0, ix86_compare_op1);
11964 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11965 gen_rtx_LABEL_REF (VOIDmode, label),
11967 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
11969 use_fcomi = ix86_use_fcomi_compare (code);
11970 vec = rtvec_alloc (3 + !use_fcomi);
11971 RTVEC_ELT (vec, 0) = tmp;
11973 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
11975 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
11978 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
11980 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
11989 /* Expand DImode branch into multiple compare+branch. */
11991 rtx lo[2], hi[2], label2;
11992 enum rtx_code code1, code2, code3;
11993 enum machine_mode submode;
11995 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
11997 tmp = ix86_compare_op0;
11998 ix86_compare_op0 = ix86_compare_op1;
11999 ix86_compare_op1 = tmp;
12000 code = swap_condition (code);
12002 if (GET_MODE (ix86_compare_op0) == DImode)
12004 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
12005 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
12010 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
12011 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
12015 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
12016 avoid two branches. This costs one extra insn, so disable when
12017 optimizing for size. */
12019 if ((code == EQ || code == NE)
12021 || hi[1] == const0_rtx || lo[1] == const0_rtx))
12026 if (hi[1] != const0_rtx)
12027 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
12028 NULL_RTX, 0, OPTAB_WIDEN);
12031 if (lo[1] != const0_rtx)
12032 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
12033 NULL_RTX, 0, OPTAB_WIDEN);
12035 tmp = expand_binop (submode, ior_optab, xor1, xor0,
12036 NULL_RTX, 0, OPTAB_WIDEN);
12038 ix86_compare_op0 = tmp;
12039 ix86_compare_op1 = const0_rtx;
12040 ix86_expand_branch (code, label);
12044 /* Otherwise, if we are doing less-than or greater-or-equal-than,
12045 op1 is a constant and the low word is zero, then we can just
12046 examine the high word. */
12048 if (CONST_INT_P (hi[1]) && lo[1] == const0_rtx)
12051 case LT: case LTU: case GE: case GEU:
12052 ix86_compare_op0 = hi[0];
12053 ix86_compare_op1 = hi[1];
12054 ix86_expand_branch (code, label);
12060 /* Otherwise, we need two or three jumps. */
12062 label2 = gen_label_rtx ();
12065 code2 = swap_condition (code);
12066 code3 = unsigned_condition (code);
12070 case LT: case GT: case LTU: case GTU:
12073 case LE: code1 = LT; code2 = GT; break;
12074 case GE: code1 = GT; code2 = LT; break;
12075 case LEU: code1 = LTU; code2 = GTU; break;
12076 case GEU: code1 = GTU; code2 = LTU; break;
12078 case EQ: code1 = UNKNOWN; code2 = NE; break;
12079 case NE: code2 = UNKNOWN; break;
12082 gcc_unreachable ();
12087 * if (hi(a) < hi(b)) goto true;
12088 * if (hi(a) > hi(b)) goto false;
12089 * if (lo(a) < lo(b)) goto true;
12093 ix86_compare_op0 = hi[0];
12094 ix86_compare_op1 = hi[1];
12096 if (code1 != UNKNOWN)
12097 ix86_expand_branch (code1, label);
12098 if (code2 != UNKNOWN)
12099 ix86_expand_branch (code2, label2);
12101 ix86_compare_op0 = lo[0];
12102 ix86_compare_op1 = lo[1];
12103 ix86_expand_branch (code3, label);
12105 if (code2 != UNKNOWN)
12106 emit_label (label2);
12111 gcc_unreachable ();
12115 /* Split branch based on floating point condition. */
12117 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
12118 rtx target1, rtx target2, rtx tmp, rtx pushed)
12120 rtx second, bypass;
12121 rtx label = NULL_RTX;
12123 int bypass_probability = -1, second_probability = -1, probability = -1;
12126 if (target2 != pc_rtx)
12129 code = reverse_condition_maybe_unordered (code);
12134 condition = ix86_expand_fp_compare (code, op1, op2,
12135 tmp, &second, &bypass);
12137 /* Remove pushed operand from stack. */
12139 ix86_free_from_memory (GET_MODE (pushed));
12141 if (split_branch_probability >= 0)
12143 /* Distribute the probabilities across the jumps.
12144 Assume the BYPASS and SECOND to be always test
12146 probability = split_branch_probability;
12148 /* Value of 1 is low enough to make no need for probability
12149 to be updated. Later we may run some experiments and see
12150 if unordered values are more frequent in practice. */
12152 bypass_probability = 1;
12154 second_probability = 1;
12156 if (bypass != NULL_RTX)
12158 label = gen_label_rtx ();
12159 i = emit_jump_insn (gen_rtx_SET
12161 gen_rtx_IF_THEN_ELSE (VOIDmode,
12163 gen_rtx_LABEL_REF (VOIDmode,
12166 if (bypass_probability >= 0)
12168 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12169 GEN_INT (bypass_probability),
12172 i = emit_jump_insn (gen_rtx_SET
12174 gen_rtx_IF_THEN_ELSE (VOIDmode,
12175 condition, target1, target2)));
12176 if (probability >= 0)
12178 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12179 GEN_INT (probability),
12181 if (second != NULL_RTX)
12183 i = emit_jump_insn (gen_rtx_SET
12185 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
12187 if (second_probability >= 0)
12189 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12190 GEN_INT (second_probability),
12193 if (label != NULL_RTX)
12194 emit_label (label);
12198 ix86_expand_setcc (enum rtx_code code, rtx dest)
12200 rtx ret, tmp, tmpreg, equiv;
12201 rtx second_test, bypass_test;
12203 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
12204 return 0; /* FAIL */
12206 gcc_assert (GET_MODE (dest) == QImode);
12208 ret = ix86_expand_compare (code, &second_test, &bypass_test);
12209 PUT_MODE (ret, QImode);
12214 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
12215 if (bypass_test || second_test)
12217 rtx test = second_test;
12219 rtx tmp2 = gen_reg_rtx (QImode);
12222 gcc_assert (!second_test);
12223 test = bypass_test;
12225 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
12227 PUT_MODE (test, QImode);
12228 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
12231 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
12233 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
12236 /* Attach a REG_EQUAL note describing the comparison result. */
12237 if (ix86_compare_op0 && ix86_compare_op1)
12239 equiv = simplify_gen_relational (code, QImode,
12240 GET_MODE (ix86_compare_op0),
12241 ix86_compare_op0, ix86_compare_op1);
12242 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
12245 return 1; /* DONE */
12248 /* Expand comparison setting or clearing carry flag. Return true when
12249 successful and set pop for the operation. */
12251 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
12253 enum machine_mode mode =
12254 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
12256 /* Do not handle DImode compares that go through special path. */
12257 if (mode == (TARGET_64BIT ? TImode : DImode))
12260 if (SCALAR_FLOAT_MODE_P (mode))
12262 rtx second_test = NULL, bypass_test = NULL;
12263 rtx compare_op, compare_seq;
12265 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
12267 /* Shortcut: following common codes never translate
12268 into carry flag compares. */
12269 if (code == EQ || code == NE || code == UNEQ || code == LTGT
12270 || code == ORDERED || code == UNORDERED)
12273 /* These comparisons require zero flag; swap operands so they won't. */
12274 if ((code == GT || code == UNLE || code == LE || code == UNGT)
12275 && !TARGET_IEEE_FP)
12280 code = swap_condition (code);
12283 /* Try to expand the comparison and verify that we end up with
12284 carry flag based comparison. This fails to be true only when
12285 we decide to expand comparison using arithmetic that is not
12286 too common scenario. */
12288 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12289 &second_test, &bypass_test);
12290 compare_seq = get_insns ();
12293 if (second_test || bypass_test)
12296 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12297 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12298 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
12300 code = GET_CODE (compare_op);
12302 if (code != LTU && code != GEU)
12305 emit_insn (compare_seq);
12310 if (!INTEGRAL_MODE_P (mode))
12319 /* Convert a==0 into (unsigned)a<1. */
12322 if (op1 != const0_rtx)
12325 code = (code == EQ ? LTU : GEU);
12328 /* Convert a>b into b<a or a>=b-1. */
12331 if (CONST_INT_P (op1))
12333 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
12334 /* Bail out on overflow. We still can swap operands but that
12335 would force loading of the constant into register. */
12336 if (op1 == const0_rtx
12337 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
12339 code = (code == GTU ? GEU : LTU);
12346 code = (code == GTU ? LTU : GEU);
12350 /* Convert a>=0 into (unsigned)a<0x80000000. */
12353 if (mode == DImode || op1 != const0_rtx)
12355 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12356 code = (code == LT ? GEU : LTU);
12360 if (mode == DImode || op1 != constm1_rtx)
12362 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12363 code = (code == LE ? GEU : LTU);
12369 /* Swapping operands may cause constant to appear as first operand. */
12370 if (!nonimmediate_operand (op0, VOIDmode))
12372 if (!can_create_pseudo_p ())
12374 op0 = force_reg (mode, op0);
12376 ix86_compare_op0 = op0;
12377 ix86_compare_op1 = op1;
12378 *pop = ix86_expand_compare (code, NULL, NULL);
12379 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
12384 ix86_expand_int_movcc (rtx operands[])
12386 enum rtx_code code = GET_CODE (operands[1]), compare_code;
12387 rtx compare_seq, compare_op;
12388 rtx second_test, bypass_test;
12389 enum machine_mode mode = GET_MODE (operands[0]);
12390 bool sign_bit_compare_p = false;;
12393 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12394 compare_seq = get_insns ();
12397 compare_code = GET_CODE (compare_op);
12399 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
12400 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
12401 sign_bit_compare_p = true;
12403 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
12404 HImode insns, we'd be swallowed in word prefix ops. */
12406 if ((mode != HImode || TARGET_FAST_PREFIX)
12407 && (mode != (TARGET_64BIT ? TImode : DImode))
12408 && CONST_INT_P (operands[2])
12409 && CONST_INT_P (operands[3]))
12411 rtx out = operands[0];
12412 HOST_WIDE_INT ct = INTVAL (operands[2]);
12413 HOST_WIDE_INT cf = INTVAL (operands[3]);
12414 HOST_WIDE_INT diff;
12417 /* Sign bit compares are better done using shifts than we do by using
12419 if (sign_bit_compare_p
12420 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12421 ix86_compare_op1, &compare_op))
12423 /* Detect overlap between destination and compare sources. */
12426 if (!sign_bit_compare_p)
12428 bool fpcmp = false;
12430 compare_code = GET_CODE (compare_op);
12432 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12433 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12436 compare_code = ix86_fp_compare_code_to_integer (compare_code);
12439 /* To simplify rest of code, restrict to the GEU case. */
12440 if (compare_code == LTU)
12442 HOST_WIDE_INT tmp = ct;
12445 compare_code = reverse_condition (compare_code);
12446 code = reverse_condition (code);
12451 PUT_CODE (compare_op,
12452 reverse_condition_maybe_unordered
12453 (GET_CODE (compare_op)));
12455 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12459 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
12460 || reg_overlap_mentioned_p (out, ix86_compare_op1))
12461 tmp = gen_reg_rtx (mode);
12463 if (mode == DImode)
12464 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
12466 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
12470 if (code == GT || code == GE)
12471 code = reverse_condition (code);
12474 HOST_WIDE_INT tmp = ct;
12479 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
12480 ix86_compare_op1, VOIDmode, 0, -1);
12493 tmp = expand_simple_binop (mode, PLUS,
12495 copy_rtx (tmp), 1, OPTAB_DIRECT);
12506 tmp = expand_simple_binop (mode, IOR,
12508 copy_rtx (tmp), 1, OPTAB_DIRECT);
12510 else if (diff == -1 && ct)
12520 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12522 tmp = expand_simple_binop (mode, PLUS,
12523 copy_rtx (tmp), GEN_INT (cf),
12524 copy_rtx (tmp), 1, OPTAB_DIRECT);
12532 * andl cf - ct, dest
12542 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12545 tmp = expand_simple_binop (mode, AND,
12547 gen_int_mode (cf - ct, mode),
12548 copy_rtx (tmp), 1, OPTAB_DIRECT);
12550 tmp = expand_simple_binop (mode, PLUS,
12551 copy_rtx (tmp), GEN_INT (ct),
12552 copy_rtx (tmp), 1, OPTAB_DIRECT);
12555 if (!rtx_equal_p (tmp, out))
12556 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12558 return 1; /* DONE */
12563 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12566 tmp = ct, ct = cf, cf = tmp;
12569 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12571 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12573 /* We may be reversing unordered compare to normal compare, that
12574 is not valid in general (we may convert non-trapping condition
12575 to trapping one), however on i386 we currently emit all
12576 comparisons unordered. */
12577 compare_code = reverse_condition_maybe_unordered (compare_code);
12578 code = reverse_condition_maybe_unordered (code);
12582 compare_code = reverse_condition (compare_code);
12583 code = reverse_condition (code);
12587 compare_code = UNKNOWN;
12588 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12589 && CONST_INT_P (ix86_compare_op1))
12591 if (ix86_compare_op1 == const0_rtx
12592 && (code == LT || code == GE))
12593 compare_code = code;
12594 else if (ix86_compare_op1 == constm1_rtx)
12598 else if (code == GT)
12603 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12604 if (compare_code != UNKNOWN
12605 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12606 && (cf == -1 || ct == -1))
12608 /* If lea code below could be used, only optimize
12609 if it results in a 2 insn sequence. */
12611 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12612 || diff == 3 || diff == 5 || diff == 9)
12613 || (compare_code == LT && ct == -1)
12614 || (compare_code == GE && cf == -1))
12617 * notl op1 (if necessary)
12625 code = reverse_condition (code);
12628 out = emit_store_flag (out, code, ix86_compare_op0,
12629 ix86_compare_op1, VOIDmode, 0, -1);
12631 out = expand_simple_binop (mode, IOR,
12633 out, 1, OPTAB_DIRECT);
12634 if (out != operands[0])
12635 emit_move_insn (operands[0], out);
12637 return 1; /* DONE */
12642 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
12643 || diff == 3 || diff == 5 || diff == 9)
12644 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
12646 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
12652 * lea cf(dest*(ct-cf)),dest
12656 * This also catches the degenerate setcc-only case.
12662 out = emit_store_flag (out, code, ix86_compare_op0,
12663 ix86_compare_op1, VOIDmode, 0, 1);
12666 /* On x86_64 the lea instruction operates on Pmode, so we need
12667 to get arithmetics done in proper mode to match. */
12669 tmp = copy_rtx (out);
12673 out1 = copy_rtx (out);
12674 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
12678 tmp = gen_rtx_PLUS (mode, tmp, out1);
12684 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
12687 if (!rtx_equal_p (tmp, out))
12690 out = force_operand (tmp, copy_rtx (out));
12692 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
12694 if (!rtx_equal_p (out, operands[0]))
12695 emit_move_insn (operands[0], copy_rtx (out));
12697 return 1; /* DONE */
12701 * General case: Jumpful:
12702 * xorl dest,dest cmpl op1, op2
12703 * cmpl op1, op2 movl ct, dest
12704 * setcc dest jcc 1f
12705 * decl dest movl cf, dest
12706 * andl (cf-ct),dest 1:
12709 * Size 20. Size 14.
12711 * This is reasonably steep, but branch mispredict costs are
12712 * high on modern cpus, so consider failing only if optimizing
12716 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12717 && BRANCH_COST >= 2)
12721 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12726 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12728 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12730 /* We may be reversing unordered compare to normal compare,
12731 that is not valid in general (we may convert non-trapping
12732 condition to trapping one), however on i386 we currently
12733 emit all comparisons unordered. */
12734 code = reverse_condition_maybe_unordered (code);
12738 code = reverse_condition (code);
12739 if (compare_code != UNKNOWN)
12740 compare_code = reverse_condition (compare_code);
12744 if (compare_code != UNKNOWN)
12746 /* notl op1 (if needed)
12751 For x < 0 (resp. x <= -1) there will be no notl,
12752 so if possible swap the constants to get rid of the
12754 True/false will be -1/0 while code below (store flag
12755 followed by decrement) is 0/-1, so the constants need
12756 to be exchanged once more. */
12758 if (compare_code == GE || !cf)
12760 code = reverse_condition (code);
12765 HOST_WIDE_INT tmp = cf;
12770 out = emit_store_flag (out, code, ix86_compare_op0,
12771 ix86_compare_op1, VOIDmode, 0, -1);
12775 out = emit_store_flag (out, code, ix86_compare_op0,
12776 ix86_compare_op1, VOIDmode, 0, 1);
12778 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
12779 copy_rtx (out), 1, OPTAB_DIRECT);
12782 out = expand_simple_binop (mode, AND, copy_rtx (out),
12783 gen_int_mode (cf - ct, mode),
12784 copy_rtx (out), 1, OPTAB_DIRECT);
12786 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
12787 copy_rtx (out), 1, OPTAB_DIRECT);
12788 if (!rtx_equal_p (out, operands[0]))
12789 emit_move_insn (operands[0], copy_rtx (out));
12791 return 1; /* DONE */
12795 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12797 /* Try a few things more with specific constants and a variable. */
12800 rtx var, orig_out, out, tmp;
12802 if (BRANCH_COST <= 2)
12803 return 0; /* FAIL */
12805 /* If one of the two operands is an interesting constant, load a
12806 constant with the above and mask it in with a logical operation. */
12808 if (CONST_INT_P (operands[2]))
12811 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
12812 operands[3] = constm1_rtx, op = and_optab;
12813 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
12814 operands[3] = const0_rtx, op = ior_optab;
12816 return 0; /* FAIL */
12818 else if (CONST_INT_P (operands[3]))
12821 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
12822 operands[2] = constm1_rtx, op = and_optab;
12823 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
12824 operands[2] = const0_rtx, op = ior_optab;
12826 return 0; /* FAIL */
12829 return 0; /* FAIL */
12831 orig_out = operands[0];
12832 tmp = gen_reg_rtx (mode);
12835 /* Recurse to get the constant loaded. */
12836 if (ix86_expand_int_movcc (operands) == 0)
12837 return 0; /* FAIL */
12839 /* Mask in the interesting variable. */
12840 out = expand_binop (mode, op, var, tmp, orig_out, 0,
12842 if (!rtx_equal_p (out, orig_out))
12843 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
12845 return 1; /* DONE */
12849 * For comparison with above,
12859 if (! nonimmediate_operand (operands[2], mode))
12860 operands[2] = force_reg (mode, operands[2]);
12861 if (! nonimmediate_operand (operands[3], mode))
12862 operands[3] = force_reg (mode, operands[3]);
12864 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
12866 rtx tmp = gen_reg_rtx (mode);
12867 emit_move_insn (tmp, operands[3]);
12870 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
12872 rtx tmp = gen_reg_rtx (mode);
12873 emit_move_insn (tmp, operands[2]);
12877 if (! register_operand (operands[2], VOIDmode)
12879 || ! register_operand (operands[3], VOIDmode)))
12880 operands[2] = force_reg (mode, operands[2]);
12883 && ! register_operand (operands[3], VOIDmode))
12884 operands[3] = force_reg (mode, operands[3]);
12886 emit_insn (compare_seq);
12887 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12888 gen_rtx_IF_THEN_ELSE (mode,
12889 compare_op, operands[2],
12892 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
12893 gen_rtx_IF_THEN_ELSE (mode,
12895 copy_rtx (operands[3]),
12896 copy_rtx (operands[0]))));
12898 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
12899 gen_rtx_IF_THEN_ELSE (mode,
12901 copy_rtx (operands[2]),
12902 copy_rtx (operands[0]))));
12904 return 1; /* DONE */
12907 /* Swap, force into registers, or otherwise massage the two operands
12908 to an sse comparison with a mask result. Thus we differ a bit from
12909 ix86_prepare_fp_compare_args which expects to produce a flags result.
12911 The DEST operand exists to help determine whether to commute commutative
12912 operators. The POP0/POP1 operands are updated in place. The new
12913 comparison code is returned, or UNKNOWN if not implementable. */
12915 static enum rtx_code
12916 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
12917 rtx *pop0, rtx *pop1)
12925 /* We have no LTGT as an operator. We could implement it with
12926 NE & ORDERED, but this requires an extra temporary. It's
12927 not clear that it's worth it. */
12934 /* These are supported directly. */
12941 /* For commutative operators, try to canonicalize the destination
12942 operand to be first in the comparison - this helps reload to
12943 avoid extra moves. */
12944 if (!dest || !rtx_equal_p (dest, *pop1))
12952 /* These are not supported directly. Swap the comparison operands
12953 to transform into something that is supported. */
12957 code = swap_condition (code);
12961 gcc_unreachable ();
12967 /* Detect conditional moves that exactly match min/max operational
12968 semantics. Note that this is IEEE safe, as long as we don't
12969 interchange the operands.
12971 Returns FALSE if this conditional move doesn't match a MIN/MAX,
12972 and TRUE if the operation is successful and instructions are emitted. */
12975 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
12976 rtx cmp_op1, rtx if_true, rtx if_false)
12978 enum machine_mode mode;
12984 else if (code == UNGE)
12987 if_true = if_false;
12993 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
12995 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
13000 mode = GET_MODE (dest);
13002 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
13003 but MODE may be a vector mode and thus not appropriate. */
13004 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
13006 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
13009 if_true = force_reg (mode, if_true);
13010 v = gen_rtvec (2, if_true, if_false);
13011 tmp = gen_rtx_UNSPEC (mode, v, u);
13015 code = is_min ? SMIN : SMAX;
13016 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
13019 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
13023 /* Expand an sse vector comparison. Return the register with the result. */
13026 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
13027 rtx op_true, rtx op_false)
13029 enum machine_mode mode = GET_MODE (dest);
13032 cmp_op0 = force_reg (mode, cmp_op0);
13033 if (!nonimmediate_operand (cmp_op1, mode))
13034 cmp_op1 = force_reg (mode, cmp_op1);
13037 || reg_overlap_mentioned_p (dest, op_true)
13038 || reg_overlap_mentioned_p (dest, op_false))
13039 dest = gen_reg_rtx (mode);
13041 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
13042 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13047 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
13048 operations. This is used for both scalar and vector conditional moves. */
13051 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
13053 enum machine_mode mode = GET_MODE (dest);
13058 rtx pcmov = gen_rtx_SET (mode, dest,
13059 gen_rtx_IF_THEN_ELSE (mode, cmp,
13064 else if (op_false == CONST0_RTX (mode))
13066 op_true = force_reg (mode, op_true);
13067 x = gen_rtx_AND (mode, cmp, op_true);
13068 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13070 else if (op_true == CONST0_RTX (mode))
13072 op_false = force_reg (mode, op_false);
13073 x = gen_rtx_NOT (mode, cmp);
13074 x = gen_rtx_AND (mode, x, op_false);
13075 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13079 op_true = force_reg (mode, op_true);
13080 op_false = force_reg (mode, op_false);
13082 t2 = gen_reg_rtx (mode);
13084 t3 = gen_reg_rtx (mode);
13088 x = gen_rtx_AND (mode, op_true, cmp);
13089 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
13091 x = gen_rtx_NOT (mode, cmp);
13092 x = gen_rtx_AND (mode, x, op_false);
13093 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
13095 x = gen_rtx_IOR (mode, t3, t2);
13096 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13100 /* Expand a floating-point conditional move. Return true if successful. */
13103 ix86_expand_fp_movcc (rtx operands[])
13105 enum machine_mode mode = GET_MODE (operands[0]);
13106 enum rtx_code code = GET_CODE (operands[1]);
13107 rtx tmp, compare_op, second_test, bypass_test;
13109 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
13111 enum machine_mode cmode;
13113 /* Since we've no cmove for sse registers, don't force bad register
13114 allocation just to gain access to it. Deny movcc when the
13115 comparison mode doesn't match the move mode. */
13116 cmode = GET_MODE (ix86_compare_op0);
13117 if (cmode == VOIDmode)
13118 cmode = GET_MODE (ix86_compare_op1);
13122 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13124 &ix86_compare_op1);
13125 if (code == UNKNOWN)
13128 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
13129 ix86_compare_op1, operands[2],
13133 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
13134 ix86_compare_op1, operands[2], operands[3]);
13135 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
13139 /* The floating point conditional move instructions don't directly
13140 support conditions resulting from a signed integer comparison. */
13142 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13144 /* The floating point conditional move instructions don't directly
13145 support signed integer comparisons. */
13147 if (!fcmov_comparison_operator (compare_op, VOIDmode))
13149 gcc_assert (!second_test && !bypass_test);
13150 tmp = gen_reg_rtx (QImode);
13151 ix86_expand_setcc (code, tmp);
13153 ix86_compare_op0 = tmp;
13154 ix86_compare_op1 = const0_rtx;
13155 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13157 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13159 tmp = gen_reg_rtx (mode);
13160 emit_move_insn (tmp, operands[3]);
13163 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13165 tmp = gen_reg_rtx (mode);
13166 emit_move_insn (tmp, operands[2]);
13170 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13171 gen_rtx_IF_THEN_ELSE (mode, compare_op,
13172 operands[2], operands[3])));
13174 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13175 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
13176 operands[3], operands[0])));
13178 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13179 gen_rtx_IF_THEN_ELSE (mode, second_test,
13180 operands[2], operands[0])));
13185 /* Expand a floating-point vector conditional move; a vcond operation
13186 rather than a movcc operation. */
13189 ix86_expand_fp_vcond (rtx operands[])
13191 enum rtx_code code = GET_CODE (operands[3]);
13194 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13195 &operands[4], &operands[5]);
13196 if (code == UNKNOWN)
13199 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
13200 operands[5], operands[1], operands[2]))
13203 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
13204 operands[1], operands[2]);
13205 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
13209 /* Expand a signed/unsigned integral vector conditional move. */
13212 ix86_expand_int_vcond (rtx operands[])
13214 enum machine_mode mode = GET_MODE (operands[0]);
13215 enum rtx_code code = GET_CODE (operands[3]);
13216 bool negate = false;
13219 cop0 = operands[4];
13220 cop1 = operands[5];
13222 /* Canonicalize the comparison to EQ, GT, GTU. */
13233 code = reverse_condition (code);
13239 code = reverse_condition (code);
13245 code = swap_condition (code);
13246 x = cop0, cop0 = cop1, cop1 = x;
13250 gcc_unreachable ();
13253 /* Only SSE4.1/SSE4.2 supports V2DImode. */
13254 if (mode == V2DImode)
13259 /* SSE4.1 supports EQ. */
13260 if (!TARGET_SSE4_1)
13266 /* SSE4.2 supports GT/GTU. */
13267 if (!TARGET_SSE4_2)
13272 gcc_unreachable ();
13276 /* Unsigned parallel compare is not supported by the hardware. Play some
13277 tricks to turn this into a signed comparison against 0. */
13280 cop0 = force_reg (mode, cop0);
13289 /* Perform a parallel modulo subtraction. */
13290 t1 = gen_reg_rtx (mode);
13291 emit_insn ((mode == V4SImode
13293 : gen_subv2di3) (t1, cop0, cop1));
13295 /* Extract the original sign bit of op0. */
13296 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
13298 t2 = gen_reg_rtx (mode);
13299 emit_insn ((mode == V4SImode
13301 : gen_andv2di3) (t2, cop0, mask));
13303 /* XOR it back into the result of the subtraction. This results
13304 in the sign bit set iff we saw unsigned underflow. */
13305 x = gen_reg_rtx (mode);
13306 emit_insn ((mode == V4SImode
13308 : gen_xorv2di3) (x, t1, t2));
13316 /* Perform a parallel unsigned saturating subtraction. */
13317 x = gen_reg_rtx (mode);
13318 emit_insn (gen_rtx_SET (VOIDmode, x,
13319 gen_rtx_US_MINUS (mode, cop0, cop1)));
13326 gcc_unreachable ();
13330 cop1 = CONST0_RTX (mode);
13333 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
13334 operands[1+negate], operands[2-negate]);
13336 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
13337 operands[2-negate]);
13341 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
13342 true if we should do zero extension, else sign extension. HIGH_P is
13343 true if we want the N/2 high elements, else the low elements. */
13346 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13348 enum machine_mode imode = GET_MODE (operands[1]);
13349 rtx (*unpack)(rtx, rtx, rtx);
13356 unpack = gen_vec_interleave_highv16qi;
13358 unpack = gen_vec_interleave_lowv16qi;
13362 unpack = gen_vec_interleave_highv8hi;
13364 unpack = gen_vec_interleave_lowv8hi;
13368 unpack = gen_vec_interleave_highv4si;
13370 unpack = gen_vec_interleave_lowv4si;
13373 gcc_unreachable ();
13376 dest = gen_lowpart (imode, operands[0]);
13379 se = force_reg (imode, CONST0_RTX (imode));
13381 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
13382 operands[1], pc_rtx, pc_rtx);
13384 emit_insn (unpack (dest, operands[1], se));
13387 /* This function performs the same task as ix86_expand_sse_unpack,
13388 but with SSE4.1 instructions. */
13391 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13393 enum machine_mode imode = GET_MODE (operands[1]);
13394 rtx (*unpack)(rtx, rtx);
13401 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
13403 unpack = gen_sse4_1_extendv8qiv8hi2;
13407 unpack = gen_sse4_1_zero_extendv4hiv4si2;
13409 unpack = gen_sse4_1_extendv4hiv4si2;
13413 unpack = gen_sse4_1_zero_extendv2siv2di2;
13415 unpack = gen_sse4_1_extendv2siv2di2;
13418 gcc_unreachable ();
13421 dest = operands[0];
13424 /* Shift higher 8 bytes to lower 8 bytes. */
13425 src = gen_reg_rtx (imode);
13426 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
13427 gen_lowpart (TImode, operands[1]),
13433 emit_insn (unpack (dest, src));
13436 /* This function performs the same task as ix86_expand_sse_unpack,
13437 but with amdfam15 instructions. */
13439 #define PPERM_SRC 0x00 /* copy source */
13440 #define PPERM_INVERT 0x20 /* invert source */
13441 #define PPERM_REVERSE 0x40 /* bit reverse source */
13442 #define PPERM_REV_INV 0x60 /* bit reverse & invert src */
13443 #define PPERM_ZERO 0x80 /* all 0's */
13444 #define PPERM_ONES 0xa0 /* all 1's */
13445 #define PPERM_SIGN 0xc0 /* propagate sign bit */
13446 #define PPERM_INV_SIGN 0xe0 /* invert & propagate sign */
13448 #define PPERM_SRC1 0x00 /* use first source byte */
13449 #define PPERM_SRC2 0x10 /* use second source byte */
13452 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13454 enum machine_mode imode = GET_MODE (operands[1]);
13455 int pperm_bytes[16];
13457 int h = (high_p) ? 8 : 0;
13460 rtvec v = rtvec_alloc (16);
13463 rtx op0 = operands[0], op1 = operands[1];
13468 vs = rtvec_alloc (8);
13469 h2 = (high_p) ? 8 : 0;
13470 for (i = 0; i < 8; i++)
13472 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
13473 pperm_bytes[2*i+1] = ((unsigned_p)
13475 : PPERM_SIGN | PPERM_SRC2 | i | h);
13478 for (i = 0; i < 16; i++)
13479 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13481 for (i = 0; i < 8; i++)
13482 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13484 p = gen_rtx_PARALLEL (VOIDmode, vs);
13485 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13487 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
13489 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
13493 vs = rtvec_alloc (4);
13494 h2 = (high_p) ? 4 : 0;
13495 for (i = 0; i < 4; i++)
13497 sign_extend = ((unsigned_p)
13499 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
13500 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
13501 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
13502 pperm_bytes[4*i+2] = sign_extend;
13503 pperm_bytes[4*i+3] = sign_extend;
13506 for (i = 0; i < 16; i++)
13507 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13509 for (i = 0; i < 4; i++)
13510 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13512 p = gen_rtx_PARALLEL (VOIDmode, vs);
13513 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13515 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
13517 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
13521 vs = rtvec_alloc (2);
13522 h2 = (high_p) ? 2 : 0;
13523 for (i = 0; i < 2; i++)
13525 sign_extend = ((unsigned_p)
13527 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
13528 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
13529 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
13530 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
13531 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
13532 pperm_bytes[8*i+4] = sign_extend;
13533 pperm_bytes[8*i+5] = sign_extend;
13534 pperm_bytes[8*i+6] = sign_extend;
13535 pperm_bytes[8*i+7] = sign_extend;
13538 for (i = 0; i < 16; i++)
13539 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13541 for (i = 0; i < 2; i++)
13542 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13544 p = gen_rtx_PARALLEL (VOIDmode, vs);
13545 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13547 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
13549 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
13553 gcc_unreachable ();
13559 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
13560 next narrower integer vector type */
13562 ix86_expand_sse5_pack (rtx operands[3])
13564 enum machine_mode imode = GET_MODE (operands[0]);
13565 int pperm_bytes[16];
13567 rtvec v = rtvec_alloc (16);
13569 rtx op0 = operands[0];
13570 rtx op1 = operands[1];
13571 rtx op2 = operands[2];
13576 for (i = 0; i < 8; i++)
13578 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
13579 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
13582 for (i = 0; i < 16; i++)
13583 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13585 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13586 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
13590 for (i = 0; i < 4; i++)
13592 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
13593 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
13594 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
13595 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
13598 for (i = 0; i < 16; i++)
13599 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13601 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13602 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
13606 for (i = 0; i < 2; i++)
13608 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
13609 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
13610 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
13611 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
13612 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
13613 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
13614 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
13615 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
13618 for (i = 0; i < 16; i++)
13619 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13621 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13622 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
13626 gcc_unreachable ();
13632 /* Expand conditional increment or decrement using adb/sbb instructions.
13633 The default case using setcc followed by the conditional move can be
13634 done by generic code. */
13636 ix86_expand_int_addcc (rtx operands[])
13638 enum rtx_code code = GET_CODE (operands[1]);
13640 rtx val = const0_rtx;
13641 bool fpcmp = false;
13642 enum machine_mode mode = GET_MODE (operands[0]);
13644 if (operands[3] != const1_rtx
13645 && operands[3] != constm1_rtx)
13647 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
13648 ix86_compare_op1, &compare_op))
13650 code = GET_CODE (compare_op);
13652 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
13653 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
13656 code = ix86_fp_compare_code_to_integer (code);
13663 PUT_CODE (compare_op,
13664 reverse_condition_maybe_unordered
13665 (GET_CODE (compare_op)));
13667 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
13669 PUT_MODE (compare_op, mode);
13671 /* Construct either adc or sbb insn. */
13672 if ((code == LTU) == (operands[3] == constm1_rtx))
13674 switch (GET_MODE (operands[0]))
13677 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
13680 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
13683 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
13686 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13689 gcc_unreachable ();
13694 switch (GET_MODE (operands[0]))
13697 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
13700 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
13703 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
13706 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13709 gcc_unreachable ();
13712 return 1; /* DONE */
13716 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
13717 works for floating pointer parameters and nonoffsetable memories.
13718 For pushes, it returns just stack offsets; the values will be saved
13719 in the right order. Maximally three parts are generated. */
13722 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
13727 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
13729 size = (GET_MODE_SIZE (mode) + 4) / 8;
13731 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
13732 gcc_assert (size >= 2 && size <= 3);
13734 /* Optimize constant pool reference to immediates. This is used by fp
13735 moves, that force all constants to memory to allow combining. */
13736 if (MEM_P (operand) && MEM_READONLY_P (operand))
13738 rtx tmp = maybe_get_pool_constant (operand);
13743 if (MEM_P (operand) && !offsettable_memref_p (operand))
13745 /* The only non-offsetable memories we handle are pushes. */
13746 int ok = push_operand (operand, VOIDmode);
13750 operand = copy_rtx (operand);
13751 PUT_MODE (operand, Pmode);
13752 parts[0] = parts[1] = parts[2] = operand;
13756 if (GET_CODE (operand) == CONST_VECTOR)
13758 enum machine_mode imode = int_mode_for_mode (mode);
13759 /* Caution: if we looked through a constant pool memory above,
13760 the operand may actually have a different mode now. That's
13761 ok, since we want to pun this all the way back to an integer. */
13762 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
13763 gcc_assert (operand != NULL);
13769 if (mode == DImode)
13770 split_di (&operand, 1, &parts[0], &parts[1]);
13773 if (REG_P (operand))
13775 gcc_assert (reload_completed);
13776 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
13777 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
13779 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
13781 else if (offsettable_memref_p (operand))
13783 operand = adjust_address (operand, SImode, 0);
13784 parts[0] = operand;
13785 parts[1] = adjust_address (operand, SImode, 4);
13787 parts[2] = adjust_address (operand, SImode, 8);
13789 else if (GET_CODE (operand) == CONST_DOUBLE)
13794 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13798 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
13799 parts[2] = gen_int_mode (l[2], SImode);
13802 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
13805 gcc_unreachable ();
13807 parts[1] = gen_int_mode (l[1], SImode);
13808 parts[0] = gen_int_mode (l[0], SImode);
13811 gcc_unreachable ();
13816 if (mode == TImode)
13817 split_ti (&operand, 1, &parts[0], &parts[1]);
13818 if (mode == XFmode || mode == TFmode)
13820 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
13821 if (REG_P (operand))
13823 gcc_assert (reload_completed);
13824 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
13825 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
13827 else if (offsettable_memref_p (operand))
13829 operand = adjust_address (operand, DImode, 0);
13830 parts[0] = operand;
13831 parts[1] = adjust_address (operand, upper_mode, 8);
13833 else if (GET_CODE (operand) == CONST_DOUBLE)
13838 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13839 real_to_target (l, &r, mode);
13841 /* Do not use shift by 32 to avoid warning on 32bit systems. */
13842 if (HOST_BITS_PER_WIDE_INT >= 64)
13845 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
13846 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
13849 parts[0] = immed_double_const (l[0], l[1], DImode);
13851 if (upper_mode == SImode)
13852 parts[1] = gen_int_mode (l[2], SImode);
13853 else if (HOST_BITS_PER_WIDE_INT >= 64)
13856 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
13857 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
13860 parts[1] = immed_double_const (l[2], l[3], DImode);
13863 gcc_unreachable ();
13870 /* Emit insns to perform a move or push of DI, DF, and XF values.
13871 Return false when normal moves are needed; true when all required
13872 insns have been emitted. Operands 2-4 contain the input values
13873 int the correct order; operands 5-7 contain the output values. */
13876 ix86_split_long_move (rtx operands[])
13881 int collisions = 0;
13882 enum machine_mode mode = GET_MODE (operands[0]);
13884 /* The DFmode expanders may ask us to move double.
13885 For 64bit target this is single move. By hiding the fact
13886 here we simplify i386.md splitters. */
13887 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
13889 /* Optimize constant pool reference to immediates. This is used by
13890 fp moves, that force all constants to memory to allow combining. */
13892 if (MEM_P (operands[1])
13893 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13894 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
13895 operands[1] = get_pool_constant (XEXP (operands[1], 0));
13896 if (push_operand (operands[0], VOIDmode))
13898 operands[0] = copy_rtx (operands[0]);
13899 PUT_MODE (operands[0], Pmode);
13902 operands[0] = gen_lowpart (DImode, operands[0]);
13903 operands[1] = gen_lowpart (DImode, operands[1]);
13904 emit_move_insn (operands[0], operands[1]);
13908 /* The only non-offsettable memory we handle is push. */
13909 if (push_operand (operands[0], VOIDmode))
13912 gcc_assert (!MEM_P (operands[0])
13913 || offsettable_memref_p (operands[0]));
13915 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
13916 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
13918 /* When emitting push, take care for source operands on the stack. */
13919 if (push && MEM_P (operands[1])
13920 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
13923 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
13924 XEXP (part[1][2], 0));
13925 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
13926 XEXP (part[1][1], 0));
13929 /* We need to do copy in the right order in case an address register
13930 of the source overlaps the destination. */
13931 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
13933 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
13935 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
13938 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
13941 /* Collision in the middle part can be handled by reordering. */
13942 if (collisions == 1 && nparts == 3
13943 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
13946 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
13947 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
13950 /* If there are more collisions, we can't handle it by reordering.
13951 Do an lea to the last part and use only one colliding move. */
13952 else if (collisions > 1)
13958 base = part[0][nparts - 1];
13960 /* Handle the case when the last part isn't valid for lea.
13961 Happens in 64-bit mode storing the 12-byte XFmode. */
13962 if (GET_MODE (base) != Pmode)
13963 base = gen_rtx_REG (Pmode, REGNO (base));
13965 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
13966 part[1][0] = replace_equiv_address (part[1][0], base);
13967 part[1][1] = replace_equiv_address (part[1][1],
13968 plus_constant (base, UNITS_PER_WORD));
13970 part[1][2] = replace_equiv_address (part[1][2],
13971 plus_constant (base, 8));
13981 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
13982 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
13983 emit_move_insn (part[0][2], part[1][2]);
13988 /* In 64bit mode we don't have 32bit push available. In case this is
13989 register, it is OK - we will just use larger counterpart. We also
13990 retype memory - these comes from attempt to avoid REX prefix on
13991 moving of second half of TFmode value. */
13992 if (GET_MODE (part[1][1]) == SImode)
13994 switch (GET_CODE (part[1][1]))
13997 part[1][1] = adjust_address (part[1][1], DImode, 0);
14001 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
14005 gcc_unreachable ();
14008 if (GET_MODE (part[1][0]) == SImode)
14009 part[1][0] = part[1][1];
14012 emit_move_insn (part[0][1], part[1][1]);
14013 emit_move_insn (part[0][0], part[1][0]);
14017 /* Choose correct order to not overwrite the source before it is copied. */
14018 if ((REG_P (part[0][0])
14019 && REG_P (part[1][1])
14020 && (REGNO (part[0][0]) == REGNO (part[1][1])
14022 && REGNO (part[0][0]) == REGNO (part[1][2]))))
14024 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
14028 operands[2] = part[0][2];
14029 operands[3] = part[0][1];
14030 operands[4] = part[0][0];
14031 operands[5] = part[1][2];
14032 operands[6] = part[1][1];
14033 operands[7] = part[1][0];
14037 operands[2] = part[0][1];
14038 operands[3] = part[0][0];
14039 operands[5] = part[1][1];
14040 operands[6] = part[1][0];
14047 operands[2] = part[0][0];
14048 operands[3] = part[0][1];
14049 operands[4] = part[0][2];
14050 operands[5] = part[1][0];
14051 operands[6] = part[1][1];
14052 operands[7] = part[1][2];
14056 operands[2] = part[0][0];
14057 operands[3] = part[0][1];
14058 operands[5] = part[1][0];
14059 operands[6] = part[1][1];
14063 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
14066 if (CONST_INT_P (operands[5])
14067 && operands[5] != const0_rtx
14068 && REG_P (operands[2]))
14070 if (CONST_INT_P (operands[6])
14071 && INTVAL (operands[6]) == INTVAL (operands[5]))
14072 operands[6] = operands[2];
14075 && CONST_INT_P (operands[7])
14076 && INTVAL (operands[7]) == INTVAL (operands[5]))
14077 operands[7] = operands[2];
14081 && CONST_INT_P (operands[6])
14082 && operands[6] != const0_rtx
14083 && REG_P (operands[3])
14084 && CONST_INT_P (operands[7])
14085 && INTVAL (operands[7]) == INTVAL (operands[6]))
14086 operands[7] = operands[3];
14089 emit_move_insn (operands[2], operands[5]);
14090 emit_move_insn (operands[3], operands[6]);
14092 emit_move_insn (operands[4], operands[7]);
14097 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
14098 left shift by a constant, either using a single shift or
14099 a sequence of add instructions. */
14102 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
14106 emit_insn ((mode == DImode
14108 : gen_adddi3) (operand, operand, operand));
14110 else if (!optimize_size
14111 && count * ix86_cost->add <= ix86_cost->shift_const)
14114 for (i=0; i<count; i++)
14116 emit_insn ((mode == DImode
14118 : gen_adddi3) (operand, operand, operand));
14122 emit_insn ((mode == DImode
14124 : gen_ashldi3) (operand, operand, GEN_INT (count)));
14128 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
14130 rtx low[2], high[2];
14132 const int single_width = mode == DImode ? 32 : 64;
14134 if (CONST_INT_P (operands[2]))
14136 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14137 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14139 if (count >= single_width)
14141 emit_move_insn (high[0], low[1]);
14142 emit_move_insn (low[0], const0_rtx);
14144 if (count > single_width)
14145 ix86_expand_ashl_const (high[0], count - single_width, mode);
14149 if (!rtx_equal_p (operands[0], operands[1]))
14150 emit_move_insn (operands[0], operands[1]);
14151 emit_insn ((mode == DImode
14153 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
14154 ix86_expand_ashl_const (low[0], count, mode);
14159 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14161 if (operands[1] == const1_rtx)
14163 /* Assuming we've chosen a QImode capable registers, then 1 << N
14164 can be done with two 32/64-bit shifts, no branches, no cmoves. */
14165 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
14167 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
14169 ix86_expand_clear (low[0]);
14170 ix86_expand_clear (high[0]);
14171 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
14173 d = gen_lowpart (QImode, low[0]);
14174 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14175 s = gen_rtx_EQ (QImode, flags, const0_rtx);
14176 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14178 d = gen_lowpart (QImode, high[0]);
14179 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14180 s = gen_rtx_NE (QImode, flags, const0_rtx);
14181 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14184 /* Otherwise, we can get the same results by manually performing
14185 a bit extract operation on bit 5/6, and then performing the two
14186 shifts. The two methods of getting 0/1 into low/high are exactly
14187 the same size. Avoiding the shift in the bit extract case helps
14188 pentium4 a bit; no one else seems to care much either way. */
14193 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
14194 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
14196 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
14197 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
14199 emit_insn ((mode == DImode
14201 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
14202 emit_insn ((mode == DImode
14204 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
14205 emit_move_insn (low[0], high[0]);
14206 emit_insn ((mode == DImode
14208 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
14211 emit_insn ((mode == DImode
14213 : gen_ashldi3) (low[0], low[0], operands[2]));
14214 emit_insn ((mode == DImode
14216 : gen_ashldi3) (high[0], high[0], operands[2]));
14220 if (operands[1] == constm1_rtx)
14222 /* For -1 << N, we can avoid the shld instruction, because we
14223 know that we're shifting 0...31/63 ones into a -1. */
14224 emit_move_insn (low[0], constm1_rtx);
14226 emit_move_insn (high[0], low[0]);
14228 emit_move_insn (high[0], constm1_rtx);
14232 if (!rtx_equal_p (operands[0], operands[1]))
14233 emit_move_insn (operands[0], operands[1]);
14235 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14236 emit_insn ((mode == DImode
14238 : gen_x86_64_shld) (high[0], low[0], operands[2]));
14241 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
14243 if (TARGET_CMOVE && scratch)
14245 ix86_expand_clear (scratch);
14246 emit_insn ((mode == DImode
14247 ? gen_x86_shift_adj_1
14248 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
14251 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
14255 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
14257 rtx low[2], high[2];
14259 const int single_width = mode == DImode ? 32 : 64;
14261 if (CONST_INT_P (operands[2]))
14263 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14264 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14266 if (count == single_width * 2 - 1)
14268 emit_move_insn (high[0], high[1]);
14269 emit_insn ((mode == DImode
14271 : gen_ashrdi3) (high[0], high[0],
14272 GEN_INT (single_width - 1)));
14273 emit_move_insn (low[0], high[0]);
14276 else if (count >= single_width)
14278 emit_move_insn (low[0], high[1]);
14279 emit_move_insn (high[0], low[0]);
14280 emit_insn ((mode == DImode
14282 : gen_ashrdi3) (high[0], high[0],
14283 GEN_INT (single_width - 1)));
14284 if (count > single_width)
14285 emit_insn ((mode == DImode
14287 : gen_ashrdi3) (low[0], low[0],
14288 GEN_INT (count - single_width)));
14292 if (!rtx_equal_p (operands[0], operands[1]))
14293 emit_move_insn (operands[0], operands[1]);
14294 emit_insn ((mode == DImode
14296 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14297 emit_insn ((mode == DImode
14299 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
14304 if (!rtx_equal_p (operands[0], operands[1]))
14305 emit_move_insn (operands[0], operands[1]);
14307 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14309 emit_insn ((mode == DImode
14311 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14312 emit_insn ((mode == DImode
14314 : gen_ashrdi3) (high[0], high[0], operands[2]));
14316 if (TARGET_CMOVE && scratch)
14318 emit_move_insn (scratch, high[0]);
14319 emit_insn ((mode == DImode
14321 : gen_ashrdi3) (scratch, scratch,
14322 GEN_INT (single_width - 1)));
14323 emit_insn ((mode == DImode
14324 ? gen_x86_shift_adj_1
14325 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14329 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
14334 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
14336 rtx low[2], high[2];
14338 const int single_width = mode == DImode ? 32 : 64;
14340 if (CONST_INT_P (operands[2]))
14342 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14343 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14345 if (count >= single_width)
14347 emit_move_insn (low[0], high[1]);
14348 ix86_expand_clear (high[0]);
14350 if (count > single_width)
14351 emit_insn ((mode == DImode
14353 : gen_lshrdi3) (low[0], low[0],
14354 GEN_INT (count - single_width)));
14358 if (!rtx_equal_p (operands[0], operands[1]))
14359 emit_move_insn (operands[0], operands[1]);
14360 emit_insn ((mode == DImode
14362 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14363 emit_insn ((mode == DImode
14365 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
14370 if (!rtx_equal_p (operands[0], operands[1]))
14371 emit_move_insn (operands[0], operands[1]);
14373 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14375 emit_insn ((mode == DImode
14377 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14378 emit_insn ((mode == DImode
14380 : gen_lshrdi3) (high[0], high[0], operands[2]));
14382 /* Heh. By reversing the arguments, we can reuse this pattern. */
14383 if (TARGET_CMOVE && scratch)
14385 ix86_expand_clear (scratch);
14386 emit_insn ((mode == DImode
14387 ? gen_x86_shift_adj_1
14388 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14392 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
14396 /* Predict just emitted jump instruction to be taken with probability PROB. */
14398 predict_jump (int prob)
14400 rtx insn = get_last_insn ();
14401 gcc_assert (JUMP_P (insn));
14403 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14408 /* Helper function for the string operations below. Dest VARIABLE whether
14409 it is aligned to VALUE bytes. If true, jump to the label. */
14411 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
14413 rtx label = gen_label_rtx ();
14414 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
14415 if (GET_MODE (variable) == DImode)
14416 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
14418 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
14419 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
14422 predict_jump (REG_BR_PROB_BASE * 50 / 100);
14424 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14428 /* Adjust COUNTER by the VALUE. */
14430 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
14432 if (GET_MODE (countreg) == DImode)
14433 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
14435 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
14438 /* Zero extend possibly SImode EXP to Pmode register. */
14440 ix86_zero_extend_to_Pmode (rtx exp)
14443 if (GET_MODE (exp) == VOIDmode)
14444 return force_reg (Pmode, exp);
14445 if (GET_MODE (exp) == Pmode)
14446 return copy_to_mode_reg (Pmode, exp);
14447 r = gen_reg_rtx (Pmode);
14448 emit_insn (gen_zero_extendsidi2 (r, exp));
14452 /* Divide COUNTREG by SCALE. */
14454 scale_counter (rtx countreg, int scale)
14457 rtx piece_size_mask;
14461 if (CONST_INT_P (countreg))
14462 return GEN_INT (INTVAL (countreg) / scale);
14463 gcc_assert (REG_P (countreg));
14465 piece_size_mask = GEN_INT (scale - 1);
14466 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
14467 GEN_INT (exact_log2 (scale)),
14468 NULL, 1, OPTAB_DIRECT);
14472 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
14473 DImode for constant loop counts. */
14475 static enum machine_mode
14476 counter_mode (rtx count_exp)
14478 if (GET_MODE (count_exp) != VOIDmode)
14479 return GET_MODE (count_exp);
14480 if (GET_CODE (count_exp) != CONST_INT)
14482 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
14487 /* When SRCPTR is non-NULL, output simple loop to move memory
14488 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
14489 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
14490 equivalent loop to set memory by VALUE (supposed to be in MODE).
14492 The size is rounded down to whole number of chunk size moved at once.
14493 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
14497 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
14498 rtx destptr, rtx srcptr, rtx value,
14499 rtx count, enum machine_mode mode, int unroll,
14502 rtx out_label, top_label, iter, tmp;
14503 enum machine_mode iter_mode = counter_mode (count);
14504 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
14505 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
14511 top_label = gen_label_rtx ();
14512 out_label = gen_label_rtx ();
14513 iter = gen_reg_rtx (iter_mode);
14515 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
14516 NULL, 1, OPTAB_DIRECT);
14517 /* Those two should combine. */
14518 if (piece_size == const1_rtx)
14520 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
14522 predict_jump (REG_BR_PROB_BASE * 10 / 100);
14524 emit_move_insn (iter, const0_rtx);
14526 emit_label (top_label);
14528 tmp = convert_modes (Pmode, iter_mode, iter, true);
14529 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
14530 destmem = change_address (destmem, mode, x_addr);
14534 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
14535 srcmem = change_address (srcmem, mode, y_addr);
14537 /* When unrolling for chips that reorder memory reads and writes,
14538 we can save registers by using single temporary.
14539 Also using 4 temporaries is overkill in 32bit mode. */
14540 if (!TARGET_64BIT && 0)
14542 for (i = 0; i < unroll; i++)
14547 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14549 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14551 emit_move_insn (destmem, srcmem);
14557 gcc_assert (unroll <= 4);
14558 for (i = 0; i < unroll; i++)
14560 tmpreg[i] = gen_reg_rtx (mode);
14564 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14566 emit_move_insn (tmpreg[i], srcmem);
14568 for (i = 0; i < unroll; i++)
14573 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14575 emit_move_insn (destmem, tmpreg[i]);
14580 for (i = 0; i < unroll; i++)
14584 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14585 emit_move_insn (destmem, value);
14588 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
14589 true, OPTAB_LIB_WIDEN);
14591 emit_move_insn (iter, tmp);
14593 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
14595 if (expected_size != -1)
14597 expected_size /= GET_MODE_SIZE (mode) * unroll;
14598 if (expected_size == 0)
14600 else if (expected_size > REG_BR_PROB_BASE)
14601 predict_jump (REG_BR_PROB_BASE - 1);
14603 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
14606 predict_jump (REG_BR_PROB_BASE * 80 / 100);
14607 iter = ix86_zero_extend_to_Pmode (iter);
14608 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
14609 true, OPTAB_LIB_WIDEN);
14610 if (tmp != destptr)
14611 emit_move_insn (destptr, tmp);
14614 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
14615 true, OPTAB_LIB_WIDEN);
14617 emit_move_insn (srcptr, tmp);
14619 emit_label (out_label);
14622 /* Output "rep; mov" instruction.
14623 Arguments have same meaning as for previous function */
14625 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
14626 rtx destptr, rtx srcptr,
14628 enum machine_mode mode)
14634 /* If the size is known, it is shorter to use rep movs. */
14635 if (mode == QImode && CONST_INT_P (count)
14636 && !(INTVAL (count) & 3))
14639 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14640 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14641 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
14642 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
14643 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14644 if (mode != QImode)
14646 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14647 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14648 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14649 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
14650 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14651 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
14655 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14656 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
14658 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
14662 /* Output "rep; stos" instruction.
14663 Arguments have same meaning as for previous function */
14665 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
14667 enum machine_mode mode)
14672 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14673 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14674 value = force_reg (mode, gen_lowpart (mode, value));
14675 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14676 if (mode != QImode)
14678 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14679 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14680 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14683 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14684 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
14688 emit_strmov (rtx destmem, rtx srcmem,
14689 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
14691 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
14692 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
14693 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14696 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
14698 expand_movmem_epilogue (rtx destmem, rtx srcmem,
14699 rtx destptr, rtx srcptr, rtx count, int max_size)
14702 if (CONST_INT_P (count))
14704 HOST_WIDE_INT countval = INTVAL (count);
14707 if ((countval & 0x10) && max_size > 16)
14711 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14712 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
14715 gcc_unreachable ();
14718 if ((countval & 0x08) && max_size > 8)
14721 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14724 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14725 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
14729 if ((countval & 0x04) && max_size > 4)
14731 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14734 if ((countval & 0x02) && max_size > 2)
14736 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
14739 if ((countval & 0x01) && max_size > 1)
14741 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
14748 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
14749 count, 1, OPTAB_DIRECT);
14750 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
14751 count, QImode, 1, 4);
14755 /* When there are stringops, we can cheaply increase dest and src pointers.
14756 Otherwise we save code size by maintaining offset (zero is readily
14757 available from preceding rep operation) and using x86 addressing modes.
14759 if (TARGET_SINGLE_STRINGOP)
14763 rtx label = ix86_expand_aligntest (count, 4, true);
14764 src = change_address (srcmem, SImode, srcptr);
14765 dest = change_address (destmem, SImode, destptr);
14766 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14767 emit_label (label);
14768 LABEL_NUSES (label) = 1;
14772 rtx label = ix86_expand_aligntest (count, 2, true);
14773 src = change_address (srcmem, HImode, srcptr);
14774 dest = change_address (destmem, HImode, destptr);
14775 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14776 emit_label (label);
14777 LABEL_NUSES (label) = 1;
14781 rtx label = ix86_expand_aligntest (count, 1, true);
14782 src = change_address (srcmem, QImode, srcptr);
14783 dest = change_address (destmem, QImode, destptr);
14784 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14785 emit_label (label);
14786 LABEL_NUSES (label) = 1;
14791 rtx offset = force_reg (Pmode, const0_rtx);
14796 rtx label = ix86_expand_aligntest (count, 4, true);
14797 src = change_address (srcmem, SImode, srcptr);
14798 dest = change_address (destmem, SImode, destptr);
14799 emit_move_insn (dest, src);
14800 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
14801 true, OPTAB_LIB_WIDEN);
14803 emit_move_insn (offset, tmp);
14804 emit_label (label);
14805 LABEL_NUSES (label) = 1;
14809 rtx label = ix86_expand_aligntest (count, 2, true);
14810 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14811 src = change_address (srcmem, HImode, tmp);
14812 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14813 dest = change_address (destmem, HImode, tmp);
14814 emit_move_insn (dest, src);
14815 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
14816 true, OPTAB_LIB_WIDEN);
14818 emit_move_insn (offset, tmp);
14819 emit_label (label);
14820 LABEL_NUSES (label) = 1;
14824 rtx label = ix86_expand_aligntest (count, 1, true);
14825 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14826 src = change_address (srcmem, QImode, tmp);
14827 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14828 dest = change_address (destmem, QImode, tmp);
14829 emit_move_insn (dest, src);
14830 emit_label (label);
14831 LABEL_NUSES (label) = 1;
14836 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14838 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
14839 rtx count, int max_size)
14842 expand_simple_binop (counter_mode (count), AND, count,
14843 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
14844 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
14845 gen_lowpart (QImode, value), count, QImode,
14849 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14851 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
14855 if (CONST_INT_P (count))
14857 HOST_WIDE_INT countval = INTVAL (count);
14860 if ((countval & 0x10) && max_size > 16)
14864 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14865 emit_insn (gen_strset (destptr, dest, value));
14866 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
14867 emit_insn (gen_strset (destptr, dest, value));
14870 gcc_unreachable ();
14873 if ((countval & 0x08) && max_size > 8)
14877 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14878 emit_insn (gen_strset (destptr, dest, value));
14882 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
14883 emit_insn (gen_strset (destptr, dest, value));
14884 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
14885 emit_insn (gen_strset (destptr, dest, value));
14889 if ((countval & 0x04) && max_size > 4)
14891 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
14892 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
14895 if ((countval & 0x02) && max_size > 2)
14897 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
14898 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
14901 if ((countval & 0x01) && max_size > 1)
14903 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
14904 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
14911 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
14916 rtx label = ix86_expand_aligntest (count, 16, true);
14919 dest = change_address (destmem, DImode, destptr);
14920 emit_insn (gen_strset (destptr, dest, value));
14921 emit_insn (gen_strset (destptr, dest, value));
14925 dest = change_address (destmem, SImode, destptr);
14926 emit_insn (gen_strset (destptr, dest, value));
14927 emit_insn (gen_strset (destptr, dest, value));
14928 emit_insn (gen_strset (destptr, dest, value));
14929 emit_insn (gen_strset (destptr, dest, value));
14931 emit_label (label);
14932 LABEL_NUSES (label) = 1;
14936 rtx label = ix86_expand_aligntest (count, 8, true);
14939 dest = change_address (destmem, DImode, destptr);
14940 emit_insn (gen_strset (destptr, dest, value));
14944 dest = change_address (destmem, SImode, destptr);
14945 emit_insn (gen_strset (destptr, dest, value));
14946 emit_insn (gen_strset (destptr, dest, value));
14948 emit_label (label);
14949 LABEL_NUSES (label) = 1;
14953 rtx label = ix86_expand_aligntest (count, 4, true);
14954 dest = change_address (destmem, SImode, destptr);
14955 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
14956 emit_label (label);
14957 LABEL_NUSES (label) = 1;
14961 rtx label = ix86_expand_aligntest (count, 2, true);
14962 dest = change_address (destmem, HImode, destptr);
14963 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
14964 emit_label (label);
14965 LABEL_NUSES (label) = 1;
14969 rtx label = ix86_expand_aligntest (count, 1, true);
14970 dest = change_address (destmem, QImode, destptr);
14971 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
14972 emit_label (label);
14973 LABEL_NUSES (label) = 1;
14977 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
14978 DESIRED_ALIGNMENT. */
14980 expand_movmem_prologue (rtx destmem, rtx srcmem,
14981 rtx destptr, rtx srcptr, rtx count,
14982 int align, int desired_alignment)
14984 if (align <= 1 && desired_alignment > 1)
14986 rtx label = ix86_expand_aligntest (destptr, 1, false);
14987 srcmem = change_address (srcmem, QImode, srcptr);
14988 destmem = change_address (destmem, QImode, destptr);
14989 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
14990 ix86_adjust_counter (count, 1);
14991 emit_label (label);
14992 LABEL_NUSES (label) = 1;
14994 if (align <= 2 && desired_alignment > 2)
14996 rtx label = ix86_expand_aligntest (destptr, 2, false);
14997 srcmem = change_address (srcmem, HImode, srcptr);
14998 destmem = change_address (destmem, HImode, destptr);
14999 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15000 ix86_adjust_counter (count, 2);
15001 emit_label (label);
15002 LABEL_NUSES (label) = 1;
15004 if (align <= 4 && desired_alignment > 4)
15006 rtx label = ix86_expand_aligntest (destptr, 4, false);
15007 srcmem = change_address (srcmem, SImode, srcptr);
15008 destmem = change_address (destmem, SImode, destptr);
15009 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15010 ix86_adjust_counter (count, 4);
15011 emit_label (label);
15012 LABEL_NUSES (label) = 1;
15014 gcc_assert (desired_alignment <= 8);
15017 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
15018 DESIRED_ALIGNMENT. */
15020 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
15021 int align, int desired_alignment)
15023 if (align <= 1 && desired_alignment > 1)
15025 rtx label = ix86_expand_aligntest (destptr, 1, false);
15026 destmem = change_address (destmem, QImode, destptr);
15027 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
15028 ix86_adjust_counter (count, 1);
15029 emit_label (label);
15030 LABEL_NUSES (label) = 1;
15032 if (align <= 2 && desired_alignment > 2)
15034 rtx label = ix86_expand_aligntest (destptr, 2, false);
15035 destmem = change_address (destmem, HImode, destptr);
15036 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
15037 ix86_adjust_counter (count, 2);
15038 emit_label (label);
15039 LABEL_NUSES (label) = 1;
15041 if (align <= 4 && desired_alignment > 4)
15043 rtx label = ix86_expand_aligntest (destptr, 4, false);
15044 destmem = change_address (destmem, SImode, destptr);
15045 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
15046 ix86_adjust_counter (count, 4);
15047 emit_label (label);
15048 LABEL_NUSES (label) = 1;
15050 gcc_assert (desired_alignment <= 8);
15053 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
15054 static enum stringop_alg
15055 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
15056 int *dynamic_check)
15058 const struct stringop_algs * algs;
15059 /* Algorithms using the rep prefix want at least edi and ecx;
15060 additionally, memset wants eax and memcpy wants esi. Don't
15061 consider such algorithms if the user has appropriated those
15062 registers for their own purposes. */
15063 bool rep_prefix_usable = !(global_regs[CX_REG] || global_regs[DI_REG]
15064 || (memset ? global_regs[AX_REG] : global_regs[SI_REG]));
15066 #define ALG_USABLE_P(alg) (rep_prefix_usable \
15067 || (alg != rep_prefix_1_byte \
15068 && alg != rep_prefix_4_byte \
15069 && alg != rep_prefix_8_byte))
15071 *dynamic_check = -1;
15073 algs = &ix86_cost->memset[TARGET_64BIT != 0];
15075 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
15076 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
15077 return stringop_alg;
15078 /* rep; movq or rep; movl is the smallest variant. */
15079 else if (optimize_size)
15081 if (!count || (count & 3))
15082 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
15084 return rep_prefix_usable ? rep_prefix_4_byte : loop;
15086 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
15088 else if (expected_size != -1 && expected_size < 4)
15089 return loop_1_byte;
15090 else if (expected_size != -1)
15093 enum stringop_alg alg = libcall;
15094 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15096 /* We get here if the algorithms that were not libcall-based
15097 were rep-prefix based and we are unable to use rep prefixes
15098 based on global register usage. Break out of the loop and
15099 use the heuristic below. */
15100 if (algs->size[i].max == 0)
15102 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
15104 enum stringop_alg candidate = algs->size[i].alg;
15106 if (candidate != libcall && ALG_USABLE_P (candidate))
15108 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
15109 last non-libcall inline algorithm. */
15110 if (TARGET_INLINE_ALL_STRINGOPS)
15112 /* When the current size is best to be copied by a libcall,
15113 but we are still forced to inline, run the heuristic below
15114 that will pick code for medium sized blocks. */
15115 if (alg != libcall)
15119 else if (ALG_USABLE_P (candidate))
15123 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
15125 /* When asked to inline the call anyway, try to pick meaningful choice.
15126 We look for maximal size of block that is faster to copy by hand and
15127 take blocks of at most of that size guessing that average size will
15128 be roughly half of the block.
15130 If this turns out to be bad, we might simply specify the preferred
15131 choice in ix86_costs. */
15132 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15133 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
15136 enum stringop_alg alg;
15138 bool any_alg_usable_p = true;
15140 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15142 enum stringop_alg candidate = algs->size[i].alg;
15143 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
15145 if (candidate != libcall && candidate
15146 && ALG_USABLE_P (candidate))
15147 max = algs->size[i].max;
15149 /* If there aren't any usable algorithms, then recursing on
15150 smaller sizes isn't going to find anything. Just return the
15151 simple byte-at-a-time copy loop. */
15152 if (!any_alg_usable_p)
15154 /* Pick something reasonable. */
15155 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15156 *dynamic_check = 128;
15157 return loop_1_byte;
15161 alg = decide_alg (count, max / 2, memset, dynamic_check);
15162 gcc_assert (*dynamic_check == -1);
15163 gcc_assert (alg != libcall);
15164 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15165 *dynamic_check = max;
15168 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
15169 #undef ALG_USABLE_P
15172 /* Decide on alignment. We know that the operand is already aligned to ALIGN
15173 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
15175 decide_alignment (int align,
15176 enum stringop_alg alg,
15179 int desired_align = 0;
15183 gcc_unreachable ();
15185 case unrolled_loop:
15186 desired_align = GET_MODE_SIZE (Pmode);
15188 case rep_prefix_8_byte:
15191 case rep_prefix_4_byte:
15192 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15193 copying whole cacheline at once. */
15194 if (TARGET_PENTIUMPRO)
15199 case rep_prefix_1_byte:
15200 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15201 copying whole cacheline at once. */
15202 if (TARGET_PENTIUMPRO)
15216 if (desired_align < align)
15217 desired_align = align;
15218 if (expected_size != -1 && expected_size < 4)
15219 desired_align = align;
15220 return desired_align;
15223 /* Return the smallest power of 2 greater than VAL. */
15225 smallest_pow2_greater_than (int val)
15233 /* Expand string move (memcpy) operation. Use i386 string operations when
15234 profitable. expand_clrmem contains similar code. The code depends upon
15235 architecture, block size and alignment, but always has the same
15238 1) Prologue guard: Conditional that jumps up to epilogues for small
15239 blocks that can be handled by epilogue alone. This is faster but
15240 also needed for correctness, since prologue assume the block is larger
15241 than the desired alignment.
15243 Optional dynamic check for size and libcall for large
15244 blocks is emitted here too, with -minline-stringops-dynamically.
15246 2) Prologue: copy first few bytes in order to get destination aligned
15247 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
15248 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
15249 We emit either a jump tree on power of two sized blocks, or a byte loop.
15251 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
15252 with specified algorithm.
15254 4) Epilogue: code copying tail of the block that is too small to be
15255 handled by main body (or up to size guarded by prologue guard). */
15258 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
15259 rtx expected_align_exp, rtx expected_size_exp)
15265 rtx jump_around_label = NULL;
15266 HOST_WIDE_INT align = 1;
15267 unsigned HOST_WIDE_INT count = 0;
15268 HOST_WIDE_INT expected_size = -1;
15269 int size_needed = 0, epilogue_size_needed;
15270 int desired_align = 0;
15271 enum stringop_alg alg;
15274 if (CONST_INT_P (align_exp))
15275 align = INTVAL (align_exp);
15276 /* i386 can do misaligned access on reasonably increased cost. */
15277 if (CONST_INT_P (expected_align_exp)
15278 && INTVAL (expected_align_exp) > align)
15279 align = INTVAL (expected_align_exp);
15280 if (CONST_INT_P (count_exp))
15281 count = expected_size = INTVAL (count_exp);
15282 if (CONST_INT_P (expected_size_exp) && count == 0)
15283 expected_size = INTVAL (expected_size_exp);
15285 /* Step 0: Decide on preferred algorithm, desired alignment and
15286 size of chunks to be copied by main loop. */
15288 alg = decide_alg (count, expected_size, false, &dynamic_check);
15289 desired_align = decide_alignment (align, alg, expected_size);
15291 if (!TARGET_ALIGN_STRINGOPS)
15292 align = desired_align;
15294 if (alg == libcall)
15296 gcc_assert (alg != no_stringop);
15298 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
15299 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15300 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
15305 gcc_unreachable ();
15307 size_needed = GET_MODE_SIZE (Pmode);
15309 case unrolled_loop:
15310 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
15312 case rep_prefix_8_byte:
15315 case rep_prefix_4_byte:
15318 case rep_prefix_1_byte:
15324 epilogue_size_needed = size_needed;
15326 /* Step 1: Prologue guard. */
15328 /* Alignment code needs count to be in register. */
15329 if (CONST_INT_P (count_exp) && desired_align > align)
15331 enum machine_mode mode = SImode;
15332 if (TARGET_64BIT && (count & ~0xffffffff))
15334 count_exp = force_reg (mode, count_exp);
15336 gcc_assert (desired_align >= 1 && align >= 1);
15338 /* Ensure that alignment prologue won't copy past end of block. */
15339 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15341 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15342 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15343 Make sure it is power of 2. */
15344 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15346 label = gen_label_rtx ();
15347 emit_cmp_and_jump_insns (count_exp,
15348 GEN_INT (epilogue_size_needed),
15349 LTU, 0, counter_mode (count_exp), 1, label);
15350 if (GET_CODE (count_exp) == CONST_INT)
15352 else if (expected_size == -1 || expected_size < epilogue_size_needed)
15353 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15355 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15357 /* Emit code to decide on runtime whether library call or inline should be
15359 if (dynamic_check != -1)
15361 rtx hot_label = gen_label_rtx ();
15362 jump_around_label = gen_label_rtx ();
15363 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15364 LEU, 0, GET_MODE (count_exp), 1, hot_label);
15365 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15366 emit_block_move_via_libcall (dst, src, count_exp, false);
15367 emit_jump (jump_around_label);
15368 emit_label (hot_label);
15371 /* Step 2: Alignment prologue. */
15373 if (desired_align > align)
15375 /* Except for the first move in epilogue, we no longer know
15376 constant offset in aliasing info. It don't seems to worth
15377 the pain to maintain it for the first move, so throw away
15379 src = change_address (src, BLKmode, srcreg);
15380 dst = change_address (dst, BLKmode, destreg);
15381 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
15384 if (label && size_needed == 1)
15386 emit_label (label);
15387 LABEL_NUSES (label) = 1;
15391 /* Step 3: Main loop. */
15397 gcc_unreachable ();
15399 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15400 count_exp, QImode, 1, expected_size);
15403 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15404 count_exp, Pmode, 1, expected_size);
15406 case unrolled_loop:
15407 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
15408 registers for 4 temporaries anyway. */
15409 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15410 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
15413 case rep_prefix_8_byte:
15414 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15417 case rep_prefix_4_byte:
15418 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15421 case rep_prefix_1_byte:
15422 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15426 /* Adjust properly the offset of src and dest memory for aliasing. */
15427 if (CONST_INT_P (count_exp))
15429 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
15430 (count / size_needed) * size_needed);
15431 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15432 (count / size_needed) * size_needed);
15436 src = change_address (src, BLKmode, srcreg);
15437 dst = change_address (dst, BLKmode, destreg);
15440 /* Step 4: Epilogue to copy the remaining bytes. */
15444 /* When the main loop is done, COUNT_EXP might hold original count,
15445 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15446 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15447 bytes. Compensate if needed. */
15449 if (size_needed < epilogue_size_needed)
15452 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15453 GEN_INT (size_needed - 1), count_exp, 1,
15455 if (tmp != count_exp)
15456 emit_move_insn (count_exp, tmp);
15458 emit_label (label);
15459 LABEL_NUSES (label) = 1;
15462 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15463 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
15464 epilogue_size_needed);
15465 if (jump_around_label)
15466 emit_label (jump_around_label);
15470 /* Helper function for memcpy. For QImode value 0xXY produce
15471 0xXYXYXYXY of wide specified by MODE. This is essentially
15472 a * 0x10101010, but we can do slightly better than
15473 synth_mult by unwinding the sequence by hand on CPUs with
15476 promote_duplicated_reg (enum machine_mode mode, rtx val)
15478 enum machine_mode valmode = GET_MODE (val);
15480 int nops = mode == DImode ? 3 : 2;
15482 gcc_assert (mode == SImode || mode == DImode);
15483 if (val == const0_rtx)
15484 return copy_to_mode_reg (mode, const0_rtx);
15485 if (CONST_INT_P (val))
15487 HOST_WIDE_INT v = INTVAL (val) & 255;
15491 if (mode == DImode)
15492 v |= (v << 16) << 16;
15493 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
15496 if (valmode == VOIDmode)
15498 if (valmode != QImode)
15499 val = gen_lowpart (QImode, val);
15500 if (mode == QImode)
15502 if (!TARGET_PARTIAL_REG_STALL)
15504 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
15505 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
15506 <= (ix86_cost->shift_const + ix86_cost->add) * nops
15507 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
15509 rtx reg = convert_modes (mode, QImode, val, true);
15510 tmp = promote_duplicated_reg (mode, const1_rtx);
15511 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
15516 rtx reg = convert_modes (mode, QImode, val, true);
15518 if (!TARGET_PARTIAL_REG_STALL)
15519 if (mode == SImode)
15520 emit_insn (gen_movsi_insv_1 (reg, reg));
15522 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
15525 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
15526 NULL, 1, OPTAB_DIRECT);
15528 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15530 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
15531 NULL, 1, OPTAB_DIRECT);
15532 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15533 if (mode == SImode)
15535 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
15536 NULL, 1, OPTAB_DIRECT);
15537 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15542 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
15543 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
15544 alignment from ALIGN to DESIRED_ALIGN. */
15546 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
15551 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
15552 promoted_val = promote_duplicated_reg (DImode, val);
15553 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
15554 promoted_val = promote_duplicated_reg (SImode, val);
15555 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
15556 promoted_val = promote_duplicated_reg (HImode, val);
15558 promoted_val = val;
15560 return promoted_val;
15563 /* Expand string clear operation (bzero). Use i386 string operations when
15564 profitable. See expand_movmem comment for explanation of individual
15565 steps performed. */
15567 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
15568 rtx expected_align_exp, rtx expected_size_exp)
15573 rtx jump_around_label = NULL;
15574 HOST_WIDE_INT align = 1;
15575 unsigned HOST_WIDE_INT count = 0;
15576 HOST_WIDE_INT expected_size = -1;
15577 int size_needed = 0, epilogue_size_needed;
15578 int desired_align = 0;
15579 enum stringop_alg alg;
15580 rtx promoted_val = NULL;
15581 bool force_loopy_epilogue = false;
15584 if (CONST_INT_P (align_exp))
15585 align = INTVAL (align_exp);
15586 /* i386 can do misaligned access on reasonably increased cost. */
15587 if (CONST_INT_P (expected_align_exp)
15588 && INTVAL (expected_align_exp) > align)
15589 align = INTVAL (expected_align_exp);
15590 if (CONST_INT_P (count_exp))
15591 count = expected_size = INTVAL (count_exp);
15592 if (CONST_INT_P (expected_size_exp) && count == 0)
15593 expected_size = INTVAL (expected_size_exp);
15595 /* Step 0: Decide on preferred algorithm, desired alignment and
15596 size of chunks to be copied by main loop. */
15598 alg = decide_alg (count, expected_size, true, &dynamic_check);
15599 desired_align = decide_alignment (align, alg, expected_size);
15601 if (!TARGET_ALIGN_STRINGOPS)
15602 align = desired_align;
15604 if (alg == libcall)
15606 gcc_assert (alg != no_stringop);
15608 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
15609 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15614 gcc_unreachable ();
15616 size_needed = GET_MODE_SIZE (Pmode);
15618 case unrolled_loop:
15619 size_needed = GET_MODE_SIZE (Pmode) * 4;
15621 case rep_prefix_8_byte:
15624 case rep_prefix_4_byte:
15627 case rep_prefix_1_byte:
15632 epilogue_size_needed = size_needed;
15634 /* Step 1: Prologue guard. */
15636 /* Alignment code needs count to be in register. */
15637 if (CONST_INT_P (count_exp) && desired_align > align)
15639 enum machine_mode mode = SImode;
15640 if (TARGET_64BIT && (count & ~0xffffffff))
15642 count_exp = force_reg (mode, count_exp);
15644 /* Do the cheap promotion to allow better CSE across the
15645 main loop and epilogue (ie one load of the big constant in the
15646 front of all code. */
15647 if (CONST_INT_P (val_exp))
15648 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15649 desired_align, align);
15650 /* Ensure that alignment prologue won't copy past end of block. */
15651 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15653 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15654 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15655 Make sure it is power of 2. */
15656 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15658 /* To improve performance of small blocks, we jump around the VAL
15659 promoting mode. This mean that if the promoted VAL is not constant,
15660 we might not use it in the epilogue and have to use byte
15662 if (epilogue_size_needed > 2 && !promoted_val)
15663 force_loopy_epilogue = true;
15664 label = gen_label_rtx ();
15665 emit_cmp_and_jump_insns (count_exp,
15666 GEN_INT (epilogue_size_needed),
15667 LTU, 0, counter_mode (count_exp), 1, label);
15668 if (GET_CODE (count_exp) == CONST_INT)
15670 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
15671 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15673 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15675 if (dynamic_check != -1)
15677 rtx hot_label = gen_label_rtx ();
15678 jump_around_label = gen_label_rtx ();
15679 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15680 LEU, 0, counter_mode (count_exp), 1, hot_label);
15681 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15682 set_storage_via_libcall (dst, count_exp, val_exp, false);
15683 emit_jump (jump_around_label);
15684 emit_label (hot_label);
15687 /* Step 2: Alignment prologue. */
15689 /* Do the expensive promotion once we branched off the small blocks. */
15691 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15692 desired_align, align);
15693 gcc_assert (desired_align >= 1 && align >= 1);
15695 if (desired_align > align)
15697 /* Except for the first move in epilogue, we no longer know
15698 constant offset in aliasing info. It don't seems to worth
15699 the pain to maintain it for the first move, so throw away
15701 dst = change_address (dst, BLKmode, destreg);
15702 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
15705 if (label && size_needed == 1)
15707 emit_label (label);
15708 LABEL_NUSES (label) = 1;
15712 /* Step 3: Main loop. */
15718 gcc_unreachable ();
15720 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15721 count_exp, QImode, 1, expected_size);
15724 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15725 count_exp, Pmode, 1, expected_size);
15727 case unrolled_loop:
15728 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15729 count_exp, Pmode, 4, expected_size);
15731 case rep_prefix_8_byte:
15732 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15735 case rep_prefix_4_byte:
15736 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15739 case rep_prefix_1_byte:
15740 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15744 /* Adjust properly the offset of src and dest memory for aliasing. */
15745 if (CONST_INT_P (count_exp))
15746 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15747 (count / size_needed) * size_needed);
15749 dst = change_address (dst, BLKmode, destreg);
15751 /* Step 4: Epilogue to copy the remaining bytes. */
15755 /* When the main loop is done, COUNT_EXP might hold original count,
15756 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15757 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15758 bytes. Compensate if needed. */
15760 if (size_needed < desired_align - align)
15763 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15764 GEN_INT (size_needed - 1), count_exp, 1,
15766 size_needed = desired_align - align + 1;
15767 if (tmp != count_exp)
15768 emit_move_insn (count_exp, tmp);
15770 emit_label (label);
15771 LABEL_NUSES (label) = 1;
15773 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15775 if (force_loopy_epilogue)
15776 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
15779 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
15782 if (jump_around_label)
15783 emit_label (jump_around_label);
15787 /* Expand the appropriate insns for doing strlen if not just doing
15790 out = result, initialized with the start address
15791 align_rtx = alignment of the address.
15792 scratch = scratch register, initialized with the startaddress when
15793 not aligned, otherwise undefined
15795 This is just the body. It needs the initializations mentioned above and
15796 some address computing at the end. These things are done in i386.md. */
15799 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
15803 rtx align_2_label = NULL_RTX;
15804 rtx align_3_label = NULL_RTX;
15805 rtx align_4_label = gen_label_rtx ();
15806 rtx end_0_label = gen_label_rtx ();
15808 rtx tmpreg = gen_reg_rtx (SImode);
15809 rtx scratch = gen_reg_rtx (SImode);
15813 if (CONST_INT_P (align_rtx))
15814 align = INTVAL (align_rtx);
15816 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
15818 /* Is there a known alignment and is it less than 4? */
15821 rtx scratch1 = gen_reg_rtx (Pmode);
15822 emit_move_insn (scratch1, out);
15823 /* Is there a known alignment and is it not 2? */
15826 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
15827 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
15829 /* Leave just the 3 lower bits. */
15830 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
15831 NULL_RTX, 0, OPTAB_WIDEN);
15833 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15834 Pmode, 1, align_4_label);
15835 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
15836 Pmode, 1, align_2_label);
15837 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
15838 Pmode, 1, align_3_label);
15842 /* Since the alignment is 2, we have to check 2 or 0 bytes;
15843 check if is aligned to 4 - byte. */
15845 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
15846 NULL_RTX, 0, OPTAB_WIDEN);
15848 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15849 Pmode, 1, align_4_label);
15852 mem = change_address (src, QImode, out);
15854 /* Now compare the bytes. */
15856 /* Compare the first n unaligned byte on a byte per byte basis. */
15857 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
15858 QImode, 1, end_0_label);
15860 /* Increment the address. */
15862 emit_insn (gen_adddi3 (out, out, const1_rtx));
15864 emit_insn (gen_addsi3 (out, out, const1_rtx));
15866 /* Not needed with an alignment of 2 */
15869 emit_label (align_2_label);
15871 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
15875 emit_insn (gen_adddi3 (out, out, const1_rtx));
15877 emit_insn (gen_addsi3 (out, out, const1_rtx));
15879 emit_label (align_3_label);
15882 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
15886 emit_insn (gen_adddi3 (out, out, const1_rtx));
15888 emit_insn (gen_addsi3 (out, out, const1_rtx));
15891 /* Generate loop to check 4 bytes at a time. It is not a good idea to
15892 align this loop. It gives only huge programs, but does not help to
15894 emit_label (align_4_label);
15896 mem = change_address (src, SImode, out);
15897 emit_move_insn (scratch, mem);
15899 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
15901 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
15903 /* This formula yields a nonzero result iff one of the bytes is zero.
15904 This saves three branches inside loop and many cycles. */
15906 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
15907 emit_insn (gen_one_cmplsi2 (scratch, scratch));
15908 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
15909 emit_insn (gen_andsi3 (tmpreg, tmpreg,
15910 gen_int_mode (0x80808080, SImode)));
15911 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
15916 rtx reg = gen_reg_rtx (SImode);
15917 rtx reg2 = gen_reg_rtx (Pmode);
15918 emit_move_insn (reg, tmpreg);
15919 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
15921 /* If zero is not in the first two bytes, move two bytes forward. */
15922 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
15923 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15924 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
15925 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
15926 gen_rtx_IF_THEN_ELSE (SImode, tmp,
15929 /* Emit lea manually to avoid clobbering of flags. */
15930 emit_insn (gen_rtx_SET (SImode, reg2,
15931 gen_rtx_PLUS (Pmode, out, const2_rtx)));
15933 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15934 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
15935 emit_insn (gen_rtx_SET (VOIDmode, out,
15936 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
15943 rtx end_2_label = gen_label_rtx ();
15944 /* Is zero in the first two bytes? */
15946 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
15947 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15948 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
15949 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15950 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
15952 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
15953 JUMP_LABEL (tmp) = end_2_label;
15955 /* Not in the first two. Move two bytes forward. */
15956 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
15958 emit_insn (gen_adddi3 (out, out, const2_rtx));
15960 emit_insn (gen_addsi3 (out, out, const2_rtx));
15962 emit_label (end_2_label);
15966 /* Avoid branch in fixing the byte. */
15967 tmpreg = gen_lowpart (QImode, tmpreg);
15968 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
15969 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
15971 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
15973 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
15975 emit_label (end_0_label);
15978 /* Expand strlen. */
15981 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
15983 rtx addr, scratch1, scratch2, scratch3, scratch4;
15985 /* The generic case of strlen expander is long. Avoid it's
15986 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
15988 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
15989 && !TARGET_INLINE_ALL_STRINGOPS
15991 && (!CONST_INT_P (align) || INTVAL (align) < 4))
15994 addr = force_reg (Pmode, XEXP (src, 0));
15995 scratch1 = gen_reg_rtx (Pmode);
15997 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16000 /* Well it seems that some optimizer does not combine a call like
16001 foo(strlen(bar), strlen(bar));
16002 when the move and the subtraction is done here. It does calculate
16003 the length just once when these instructions are done inside of
16004 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
16005 often used and I use one fewer register for the lifetime of
16006 output_strlen_unroll() this is better. */
16008 emit_move_insn (out, addr);
16010 ix86_expand_strlensi_unroll_1 (out, src, align);
16012 /* strlensi_unroll_1 returns the address of the zero at the end of
16013 the string, like memchr(), so compute the length by subtracting
16014 the start address. */
16016 emit_insn (gen_subdi3 (out, out, addr));
16018 emit_insn (gen_subsi3 (out, out, addr));
16024 /* Can't use this if the user has appropriated eax, ecx, or edi. */
16025 if (global_regs[AX_REG] || global_regs[CX_REG] || global_regs[DI_REG])
16028 scratch2 = gen_reg_rtx (Pmode);
16029 scratch3 = gen_reg_rtx (Pmode);
16030 scratch4 = force_reg (Pmode, constm1_rtx);
16032 emit_move_insn (scratch3, addr);
16033 eoschar = force_reg (QImode, eoschar);
16035 src = replace_equiv_address_nv (src, scratch3);
16037 /* If .md starts supporting :P, this can be done in .md. */
16038 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
16039 scratch4), UNSPEC_SCAS);
16040 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
16043 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
16044 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
16048 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
16049 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
16055 /* For given symbol (function) construct code to compute address of it's PLT
16056 entry in large x86-64 PIC model. */
16058 construct_plt_address (rtx symbol)
16060 rtx tmp = gen_reg_rtx (Pmode);
16061 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
16063 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16064 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
16066 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
16067 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
16072 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
16073 rtx callarg2 ATTRIBUTE_UNUSED,
16074 rtx pop, int sibcall)
16076 rtx use = NULL, call;
16078 if (pop == const0_rtx)
16080 gcc_assert (!TARGET_64BIT || !pop);
16082 if (TARGET_MACHO && !TARGET_64BIT)
16085 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
16086 fnaddr = machopic_indirect_call_target (fnaddr);
16091 /* Static functions and indirect calls don't need the pic register. */
16092 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
16093 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16094 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
16095 use_reg (&use, pic_offset_table_rtx);
16098 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
16100 rtx al = gen_rtx_REG (QImode, AX_REG);
16101 emit_move_insn (al, callarg2);
16102 use_reg (&use, al);
16105 if (ix86_cmodel == CM_LARGE_PIC
16106 && GET_CODE (fnaddr) == MEM
16107 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16108 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
16109 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
16110 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
16112 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16113 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16115 if (sibcall && TARGET_64BIT
16116 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
16119 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16120 fnaddr = gen_rtx_REG (Pmode, R11_REG);
16121 emit_move_insn (fnaddr, addr);
16122 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16125 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
16127 call = gen_rtx_SET (VOIDmode, retval, call);
16130 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
16131 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
16132 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
16135 call = emit_call_insn (call);
16137 CALL_INSN_FUNCTION_USAGE (call) = use;
16141 /* Clear stack slot assignments remembered from previous functions.
16142 This is called from INIT_EXPANDERS once before RTL is emitted for each
16145 static struct machine_function *
16146 ix86_init_machine_status (void)
16148 struct machine_function *f;
16150 f = GGC_CNEW (struct machine_function);
16151 f->use_fast_prologue_epilogue_nregs = -1;
16152 f->tls_descriptor_call_expanded_p = 0;
16157 /* Return a MEM corresponding to a stack slot with mode MODE.
16158 Allocate a new slot if necessary.
16160 The RTL for a function can have several slots available: N is
16161 which slot to use. */
16164 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
16166 struct stack_local_entry *s;
16168 gcc_assert (n < MAX_386_STACK_LOCALS);
16170 /* Virtual slot is valid only before vregs are instantiated. */
16171 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
16173 for (s = ix86_stack_locals; s; s = s->next)
16174 if (s->mode == mode && s->n == n)
16175 return copy_rtx (s->rtl);
16177 s = (struct stack_local_entry *)
16178 ggc_alloc (sizeof (struct stack_local_entry));
16181 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
16183 s->next = ix86_stack_locals;
16184 ix86_stack_locals = s;
16188 /* Construct the SYMBOL_REF for the tls_get_addr function. */
16190 static GTY(()) rtx ix86_tls_symbol;
16192 ix86_tls_get_addr (void)
16195 if (!ix86_tls_symbol)
16197 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
16198 (TARGET_ANY_GNU_TLS
16200 ? "___tls_get_addr"
16201 : "__tls_get_addr");
16204 return ix86_tls_symbol;
16207 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
16209 static GTY(()) rtx ix86_tls_module_base_symbol;
16211 ix86_tls_module_base (void)
16214 if (!ix86_tls_module_base_symbol)
16216 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
16217 "_TLS_MODULE_BASE_");
16218 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
16219 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
16222 return ix86_tls_module_base_symbol;
16225 /* Calculate the length of the memory address in the instruction
16226 encoding. Does not include the one-byte modrm, opcode, or prefix. */
16229 memory_address_length (rtx addr)
16231 struct ix86_address parts;
16232 rtx base, index, disp;
16236 if (GET_CODE (addr) == PRE_DEC
16237 || GET_CODE (addr) == POST_INC
16238 || GET_CODE (addr) == PRE_MODIFY
16239 || GET_CODE (addr) == POST_MODIFY)
16242 ok = ix86_decompose_address (addr, &parts);
16245 if (parts.base && GET_CODE (parts.base) == SUBREG)
16246 parts.base = SUBREG_REG (parts.base);
16247 if (parts.index && GET_CODE (parts.index) == SUBREG)
16248 parts.index = SUBREG_REG (parts.index);
16251 index = parts.index;
16256 - esp as the base always wants an index,
16257 - ebp as the base always wants a displacement. */
16259 /* Register Indirect. */
16260 if (base && !index && !disp)
16262 /* esp (for its index) and ebp (for its displacement) need
16263 the two-byte modrm form. */
16264 if (addr == stack_pointer_rtx
16265 || addr == arg_pointer_rtx
16266 || addr == frame_pointer_rtx
16267 || addr == hard_frame_pointer_rtx)
16271 /* Direct Addressing. */
16272 else if (disp && !base && !index)
16277 /* Find the length of the displacement constant. */
16280 if (base && satisfies_constraint_K (disp))
16285 /* ebp always wants a displacement. */
16286 else if (base == hard_frame_pointer_rtx)
16289 /* An index requires the two-byte modrm form.... */
16291 /* ...like esp, which always wants an index. */
16292 || base == stack_pointer_rtx
16293 || base == arg_pointer_rtx
16294 || base == frame_pointer_rtx)
16301 /* Compute default value for "length_immediate" attribute. When SHORTFORM
16302 is set, expect that insn have 8bit immediate alternative. */
16304 ix86_attr_length_immediate_default (rtx insn, int shortform)
16308 extract_insn_cached (insn);
16309 for (i = recog_data.n_operands - 1; i >= 0; --i)
16310 if (CONSTANT_P (recog_data.operand[i]))
16313 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
16317 switch (get_attr_mode (insn))
16328 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
16333 fatal_insn ("unknown insn mode", insn);
16339 /* Compute default value for "length_address" attribute. */
16341 ix86_attr_length_address_default (rtx insn)
16345 if (get_attr_type (insn) == TYPE_LEA)
16347 rtx set = PATTERN (insn);
16349 if (GET_CODE (set) == PARALLEL)
16350 set = XVECEXP (set, 0, 0);
16352 gcc_assert (GET_CODE (set) == SET);
16354 return memory_address_length (SET_SRC (set));
16357 extract_insn_cached (insn);
16358 for (i = recog_data.n_operands - 1; i >= 0; --i)
16359 if (MEM_P (recog_data.operand[i]))
16361 return memory_address_length (XEXP (recog_data.operand[i], 0));
16367 /* Return the maximum number of instructions a cpu can issue. */
16370 ix86_issue_rate (void)
16374 case PROCESSOR_PENTIUM:
16378 case PROCESSOR_PENTIUMPRO:
16379 case PROCESSOR_PENTIUM4:
16380 case PROCESSOR_ATHLON:
16382 case PROCESSOR_AMDFAM10:
16383 case PROCESSOR_NOCONA:
16384 case PROCESSOR_GENERIC32:
16385 case PROCESSOR_GENERIC64:
16388 case PROCESSOR_CORE2:
16396 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
16397 by DEP_INSN and nothing set by DEP_INSN. */
16400 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16404 /* Simplify the test for uninteresting insns. */
16405 if (insn_type != TYPE_SETCC
16406 && insn_type != TYPE_ICMOV
16407 && insn_type != TYPE_FCMOV
16408 && insn_type != TYPE_IBR)
16411 if ((set = single_set (dep_insn)) != 0)
16413 set = SET_DEST (set);
16416 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
16417 && XVECLEN (PATTERN (dep_insn), 0) == 2
16418 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
16419 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
16421 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16422 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16427 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
16430 /* This test is true if the dependent insn reads the flags but
16431 not any other potentially set register. */
16432 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
16435 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
16441 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
16442 address with operands set by DEP_INSN. */
16445 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16449 if (insn_type == TYPE_LEA
16452 addr = PATTERN (insn);
16454 if (GET_CODE (addr) == PARALLEL)
16455 addr = XVECEXP (addr, 0, 0);
16457 gcc_assert (GET_CODE (addr) == SET);
16459 addr = SET_SRC (addr);
16464 extract_insn_cached (insn);
16465 for (i = recog_data.n_operands - 1; i >= 0; --i)
16466 if (MEM_P (recog_data.operand[i]))
16468 addr = XEXP (recog_data.operand[i], 0);
16475 return modified_in_p (addr, dep_insn);
16479 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16481 enum attr_type insn_type, dep_insn_type;
16482 enum attr_memory memory;
16484 int dep_insn_code_number;
16486 /* Anti and output dependencies have zero cost on all CPUs. */
16487 if (REG_NOTE_KIND (link) != 0)
16490 dep_insn_code_number = recog_memoized (dep_insn);
16492 /* If we can't recognize the insns, we can't really do anything. */
16493 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
16496 insn_type = get_attr_type (insn);
16497 dep_insn_type = get_attr_type (dep_insn);
16501 case PROCESSOR_PENTIUM:
16502 /* Address Generation Interlock adds a cycle of latency. */
16503 if (ix86_agi_dependent (insn, dep_insn, insn_type))
16506 /* ??? Compares pair with jump/setcc. */
16507 if (ix86_flags_dependent (insn, dep_insn, insn_type))
16510 /* Floating point stores require value to be ready one cycle earlier. */
16511 if (insn_type == TYPE_FMOV
16512 && get_attr_memory (insn) == MEMORY_STORE
16513 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16517 case PROCESSOR_PENTIUMPRO:
16518 memory = get_attr_memory (insn);
16520 /* INT->FP conversion is expensive. */
16521 if (get_attr_fp_int_src (dep_insn))
16524 /* There is one cycle extra latency between an FP op and a store. */
16525 if (insn_type == TYPE_FMOV
16526 && (set = single_set (dep_insn)) != NULL_RTX
16527 && (set2 = single_set (insn)) != NULL_RTX
16528 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
16529 && MEM_P (SET_DEST (set2)))
16532 /* Show ability of reorder buffer to hide latency of load by executing
16533 in parallel with previous instruction in case
16534 previous instruction is not needed to compute the address. */
16535 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16536 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16538 /* Claim moves to take one cycle, as core can issue one load
16539 at time and the next load can start cycle later. */
16540 if (dep_insn_type == TYPE_IMOV
16541 || dep_insn_type == TYPE_FMOV)
16549 memory = get_attr_memory (insn);
16551 /* The esp dependency is resolved before the instruction is really
16553 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
16554 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
16557 /* INT->FP conversion is expensive. */
16558 if (get_attr_fp_int_src (dep_insn))
16561 /* Show ability of reorder buffer to hide latency of load by executing
16562 in parallel with previous instruction in case
16563 previous instruction is not needed to compute the address. */
16564 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16565 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16567 /* Claim moves to take one cycle, as core can issue one load
16568 at time and the next load can start cycle later. */
16569 if (dep_insn_type == TYPE_IMOV
16570 || dep_insn_type == TYPE_FMOV)
16579 case PROCESSOR_ATHLON:
16581 case PROCESSOR_AMDFAM10:
16582 case PROCESSOR_GENERIC32:
16583 case PROCESSOR_GENERIC64:
16584 memory = get_attr_memory (insn);
16586 /* Show ability of reorder buffer to hide latency of load by executing
16587 in parallel with previous instruction in case
16588 previous instruction is not needed to compute the address. */
16589 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16590 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16592 enum attr_unit unit = get_attr_unit (insn);
16595 /* Because of the difference between the length of integer and
16596 floating unit pipeline preparation stages, the memory operands
16597 for floating point are cheaper.
16599 ??? For Athlon it the difference is most probably 2. */
16600 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
16603 loadcost = TARGET_ATHLON ? 2 : 0;
16605 if (cost >= loadcost)
16618 /* How many alternative schedules to try. This should be as wide as the
16619 scheduling freedom in the DFA, but no wider. Making this value too
16620 large results extra work for the scheduler. */
16623 ia32_multipass_dfa_lookahead (void)
16625 if (ix86_tune == PROCESSOR_PENTIUM)
16628 if (ix86_tune == PROCESSOR_PENTIUMPRO
16629 || ix86_tune == PROCESSOR_K6)
16637 /* Compute the alignment given to a constant that is being placed in memory.
16638 EXP is the constant and ALIGN is the alignment that the object would
16640 The value of this function is used instead of that alignment to align
16644 ix86_constant_alignment (tree exp, int align)
16646 if (TREE_CODE (exp) == REAL_CST)
16648 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
16650 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
16653 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
16654 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
16655 return BITS_PER_WORD;
16660 /* Compute the alignment for a static variable.
16661 TYPE is the data type, and ALIGN is the alignment that
16662 the object would ordinarily have. The value of this function is used
16663 instead of that alignment to align the object. */
16666 ix86_data_alignment (tree type, int align)
16668 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
16670 if (AGGREGATE_TYPE_P (type)
16671 && TYPE_SIZE (type)
16672 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16673 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
16674 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
16675 && align < max_align)
16678 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16679 to 16byte boundary. */
16682 if (AGGREGATE_TYPE_P (type)
16683 && TYPE_SIZE (type)
16684 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16685 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
16686 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16690 if (TREE_CODE (type) == ARRAY_TYPE)
16692 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16694 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16697 else if (TREE_CODE (type) == COMPLEX_TYPE)
16700 if (TYPE_MODE (type) == DCmode && align < 64)
16702 if (TYPE_MODE (type) == XCmode && align < 128)
16705 else if ((TREE_CODE (type) == RECORD_TYPE
16706 || TREE_CODE (type) == UNION_TYPE
16707 || TREE_CODE (type) == QUAL_UNION_TYPE)
16708 && TYPE_FIELDS (type))
16710 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16712 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16715 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16716 || TREE_CODE (type) == INTEGER_TYPE)
16718 if (TYPE_MODE (type) == DFmode && align < 64)
16720 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16727 /* Compute the alignment for a local variable.
16728 TYPE is the data type, and ALIGN is the alignment that
16729 the object would ordinarily have. The value of this macro is used
16730 instead of that alignment to align the object. */
16733 ix86_local_alignment (tree type, int align)
16735 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16736 to 16byte boundary. */
16739 if (AGGREGATE_TYPE_P (type)
16740 && TYPE_SIZE (type)
16741 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16742 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
16743 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16746 if (TREE_CODE (type) == ARRAY_TYPE)
16748 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16750 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16753 else if (TREE_CODE (type) == COMPLEX_TYPE)
16755 if (TYPE_MODE (type) == DCmode && align < 64)
16757 if (TYPE_MODE (type) == XCmode && align < 128)
16760 else if ((TREE_CODE (type) == RECORD_TYPE
16761 || TREE_CODE (type) == UNION_TYPE
16762 || TREE_CODE (type) == QUAL_UNION_TYPE)
16763 && TYPE_FIELDS (type))
16765 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16767 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16770 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16771 || TREE_CODE (type) == INTEGER_TYPE)
16774 if (TYPE_MODE (type) == DFmode && align < 64)
16776 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16782 /* Emit RTL insns to initialize the variable parts of a trampoline.
16783 FNADDR is an RTX for the address of the function's pure code.
16784 CXT is an RTX for the static chain value for the function. */
16786 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
16790 /* Compute offset from the end of the jmp to the target function. */
16791 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
16792 plus_constant (tramp, 10),
16793 NULL_RTX, 1, OPTAB_DIRECT);
16794 emit_move_insn (gen_rtx_MEM (QImode, tramp),
16795 gen_int_mode (0xb9, QImode));
16796 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
16797 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
16798 gen_int_mode (0xe9, QImode));
16799 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
16804 /* Try to load address using shorter movl instead of movabs.
16805 We may want to support movq for kernel mode, but kernel does not use
16806 trampolines at the moment. */
16807 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
16809 fnaddr = copy_to_mode_reg (DImode, fnaddr);
16810 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16811 gen_int_mode (0xbb41, HImode));
16812 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
16813 gen_lowpart (SImode, fnaddr));
16818 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16819 gen_int_mode (0xbb49, HImode));
16820 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16824 /* Load static chain using movabs to r10. */
16825 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16826 gen_int_mode (0xba49, HImode));
16827 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16830 /* Jump to the r11 */
16831 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16832 gen_int_mode (0xff49, HImode));
16833 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
16834 gen_int_mode (0xe3, QImode));
16836 gcc_assert (offset <= TRAMPOLINE_SIZE);
16839 #ifdef ENABLE_EXECUTE_STACK
16840 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
16841 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
16845 /* Codes for all the SSE/MMX builtins. */
16848 IX86_BUILTIN_ADDPS,
16849 IX86_BUILTIN_ADDSS,
16850 IX86_BUILTIN_DIVPS,
16851 IX86_BUILTIN_DIVSS,
16852 IX86_BUILTIN_MULPS,
16853 IX86_BUILTIN_MULSS,
16854 IX86_BUILTIN_SUBPS,
16855 IX86_BUILTIN_SUBSS,
16857 IX86_BUILTIN_CMPEQPS,
16858 IX86_BUILTIN_CMPLTPS,
16859 IX86_BUILTIN_CMPLEPS,
16860 IX86_BUILTIN_CMPGTPS,
16861 IX86_BUILTIN_CMPGEPS,
16862 IX86_BUILTIN_CMPNEQPS,
16863 IX86_BUILTIN_CMPNLTPS,
16864 IX86_BUILTIN_CMPNLEPS,
16865 IX86_BUILTIN_CMPNGTPS,
16866 IX86_BUILTIN_CMPNGEPS,
16867 IX86_BUILTIN_CMPORDPS,
16868 IX86_BUILTIN_CMPUNORDPS,
16869 IX86_BUILTIN_CMPEQSS,
16870 IX86_BUILTIN_CMPLTSS,
16871 IX86_BUILTIN_CMPLESS,
16872 IX86_BUILTIN_CMPNEQSS,
16873 IX86_BUILTIN_CMPNLTSS,
16874 IX86_BUILTIN_CMPNLESS,
16875 IX86_BUILTIN_CMPNGTSS,
16876 IX86_BUILTIN_CMPNGESS,
16877 IX86_BUILTIN_CMPORDSS,
16878 IX86_BUILTIN_CMPUNORDSS,
16880 IX86_BUILTIN_COMIEQSS,
16881 IX86_BUILTIN_COMILTSS,
16882 IX86_BUILTIN_COMILESS,
16883 IX86_BUILTIN_COMIGTSS,
16884 IX86_BUILTIN_COMIGESS,
16885 IX86_BUILTIN_COMINEQSS,
16886 IX86_BUILTIN_UCOMIEQSS,
16887 IX86_BUILTIN_UCOMILTSS,
16888 IX86_BUILTIN_UCOMILESS,
16889 IX86_BUILTIN_UCOMIGTSS,
16890 IX86_BUILTIN_UCOMIGESS,
16891 IX86_BUILTIN_UCOMINEQSS,
16893 IX86_BUILTIN_CVTPI2PS,
16894 IX86_BUILTIN_CVTPS2PI,
16895 IX86_BUILTIN_CVTSI2SS,
16896 IX86_BUILTIN_CVTSI642SS,
16897 IX86_BUILTIN_CVTSS2SI,
16898 IX86_BUILTIN_CVTSS2SI64,
16899 IX86_BUILTIN_CVTTPS2PI,
16900 IX86_BUILTIN_CVTTSS2SI,
16901 IX86_BUILTIN_CVTTSS2SI64,
16903 IX86_BUILTIN_MAXPS,
16904 IX86_BUILTIN_MAXSS,
16905 IX86_BUILTIN_MINPS,
16906 IX86_BUILTIN_MINSS,
16908 IX86_BUILTIN_LOADUPS,
16909 IX86_BUILTIN_STOREUPS,
16910 IX86_BUILTIN_MOVSS,
16912 IX86_BUILTIN_MOVHLPS,
16913 IX86_BUILTIN_MOVLHPS,
16914 IX86_BUILTIN_LOADHPS,
16915 IX86_BUILTIN_LOADLPS,
16916 IX86_BUILTIN_STOREHPS,
16917 IX86_BUILTIN_STORELPS,
16919 IX86_BUILTIN_MASKMOVQ,
16920 IX86_BUILTIN_MOVMSKPS,
16921 IX86_BUILTIN_PMOVMSKB,
16923 IX86_BUILTIN_MOVNTPS,
16924 IX86_BUILTIN_MOVNTQ,
16926 IX86_BUILTIN_LOADDQU,
16927 IX86_BUILTIN_STOREDQU,
16929 IX86_BUILTIN_PACKSSWB,
16930 IX86_BUILTIN_PACKSSDW,
16931 IX86_BUILTIN_PACKUSWB,
16933 IX86_BUILTIN_PADDB,
16934 IX86_BUILTIN_PADDW,
16935 IX86_BUILTIN_PADDD,
16936 IX86_BUILTIN_PADDQ,
16937 IX86_BUILTIN_PADDSB,
16938 IX86_BUILTIN_PADDSW,
16939 IX86_BUILTIN_PADDUSB,
16940 IX86_BUILTIN_PADDUSW,
16941 IX86_BUILTIN_PSUBB,
16942 IX86_BUILTIN_PSUBW,
16943 IX86_BUILTIN_PSUBD,
16944 IX86_BUILTIN_PSUBQ,
16945 IX86_BUILTIN_PSUBSB,
16946 IX86_BUILTIN_PSUBSW,
16947 IX86_BUILTIN_PSUBUSB,
16948 IX86_BUILTIN_PSUBUSW,
16951 IX86_BUILTIN_PANDN,
16955 IX86_BUILTIN_PAVGB,
16956 IX86_BUILTIN_PAVGW,
16958 IX86_BUILTIN_PCMPEQB,
16959 IX86_BUILTIN_PCMPEQW,
16960 IX86_BUILTIN_PCMPEQD,
16961 IX86_BUILTIN_PCMPGTB,
16962 IX86_BUILTIN_PCMPGTW,
16963 IX86_BUILTIN_PCMPGTD,
16965 IX86_BUILTIN_PMADDWD,
16967 IX86_BUILTIN_PMAXSW,
16968 IX86_BUILTIN_PMAXUB,
16969 IX86_BUILTIN_PMINSW,
16970 IX86_BUILTIN_PMINUB,
16972 IX86_BUILTIN_PMULHUW,
16973 IX86_BUILTIN_PMULHW,
16974 IX86_BUILTIN_PMULLW,
16976 IX86_BUILTIN_PSADBW,
16977 IX86_BUILTIN_PSHUFW,
16979 IX86_BUILTIN_PSLLW,
16980 IX86_BUILTIN_PSLLD,
16981 IX86_BUILTIN_PSLLQ,
16982 IX86_BUILTIN_PSRAW,
16983 IX86_BUILTIN_PSRAD,
16984 IX86_BUILTIN_PSRLW,
16985 IX86_BUILTIN_PSRLD,
16986 IX86_BUILTIN_PSRLQ,
16987 IX86_BUILTIN_PSLLWI,
16988 IX86_BUILTIN_PSLLDI,
16989 IX86_BUILTIN_PSLLQI,
16990 IX86_BUILTIN_PSRAWI,
16991 IX86_BUILTIN_PSRADI,
16992 IX86_BUILTIN_PSRLWI,
16993 IX86_BUILTIN_PSRLDI,
16994 IX86_BUILTIN_PSRLQI,
16996 IX86_BUILTIN_PUNPCKHBW,
16997 IX86_BUILTIN_PUNPCKHWD,
16998 IX86_BUILTIN_PUNPCKHDQ,
16999 IX86_BUILTIN_PUNPCKLBW,
17000 IX86_BUILTIN_PUNPCKLWD,
17001 IX86_BUILTIN_PUNPCKLDQ,
17003 IX86_BUILTIN_SHUFPS,
17005 IX86_BUILTIN_RCPPS,
17006 IX86_BUILTIN_RCPSS,
17007 IX86_BUILTIN_RSQRTPS,
17008 IX86_BUILTIN_RSQRTSS,
17009 IX86_BUILTIN_RSQRTF,
17010 IX86_BUILTIN_SQRTPS,
17011 IX86_BUILTIN_SQRTSS,
17013 IX86_BUILTIN_UNPCKHPS,
17014 IX86_BUILTIN_UNPCKLPS,
17016 IX86_BUILTIN_ANDPS,
17017 IX86_BUILTIN_ANDNPS,
17019 IX86_BUILTIN_XORPS,
17022 IX86_BUILTIN_LDMXCSR,
17023 IX86_BUILTIN_STMXCSR,
17024 IX86_BUILTIN_SFENCE,
17026 /* 3DNow! Original */
17027 IX86_BUILTIN_FEMMS,
17028 IX86_BUILTIN_PAVGUSB,
17029 IX86_BUILTIN_PF2ID,
17030 IX86_BUILTIN_PFACC,
17031 IX86_BUILTIN_PFADD,
17032 IX86_BUILTIN_PFCMPEQ,
17033 IX86_BUILTIN_PFCMPGE,
17034 IX86_BUILTIN_PFCMPGT,
17035 IX86_BUILTIN_PFMAX,
17036 IX86_BUILTIN_PFMIN,
17037 IX86_BUILTIN_PFMUL,
17038 IX86_BUILTIN_PFRCP,
17039 IX86_BUILTIN_PFRCPIT1,
17040 IX86_BUILTIN_PFRCPIT2,
17041 IX86_BUILTIN_PFRSQIT1,
17042 IX86_BUILTIN_PFRSQRT,
17043 IX86_BUILTIN_PFSUB,
17044 IX86_BUILTIN_PFSUBR,
17045 IX86_BUILTIN_PI2FD,
17046 IX86_BUILTIN_PMULHRW,
17048 /* 3DNow! Athlon Extensions */
17049 IX86_BUILTIN_PF2IW,
17050 IX86_BUILTIN_PFNACC,
17051 IX86_BUILTIN_PFPNACC,
17052 IX86_BUILTIN_PI2FW,
17053 IX86_BUILTIN_PSWAPDSI,
17054 IX86_BUILTIN_PSWAPDSF,
17057 IX86_BUILTIN_ADDPD,
17058 IX86_BUILTIN_ADDSD,
17059 IX86_BUILTIN_DIVPD,
17060 IX86_BUILTIN_DIVSD,
17061 IX86_BUILTIN_MULPD,
17062 IX86_BUILTIN_MULSD,
17063 IX86_BUILTIN_SUBPD,
17064 IX86_BUILTIN_SUBSD,
17066 IX86_BUILTIN_CMPEQPD,
17067 IX86_BUILTIN_CMPLTPD,
17068 IX86_BUILTIN_CMPLEPD,
17069 IX86_BUILTIN_CMPGTPD,
17070 IX86_BUILTIN_CMPGEPD,
17071 IX86_BUILTIN_CMPNEQPD,
17072 IX86_BUILTIN_CMPNLTPD,
17073 IX86_BUILTIN_CMPNLEPD,
17074 IX86_BUILTIN_CMPNGTPD,
17075 IX86_BUILTIN_CMPNGEPD,
17076 IX86_BUILTIN_CMPORDPD,
17077 IX86_BUILTIN_CMPUNORDPD,
17078 IX86_BUILTIN_CMPEQSD,
17079 IX86_BUILTIN_CMPLTSD,
17080 IX86_BUILTIN_CMPLESD,
17081 IX86_BUILTIN_CMPNEQSD,
17082 IX86_BUILTIN_CMPNLTSD,
17083 IX86_BUILTIN_CMPNLESD,
17084 IX86_BUILTIN_CMPORDSD,
17085 IX86_BUILTIN_CMPUNORDSD,
17087 IX86_BUILTIN_COMIEQSD,
17088 IX86_BUILTIN_COMILTSD,
17089 IX86_BUILTIN_COMILESD,
17090 IX86_BUILTIN_COMIGTSD,
17091 IX86_BUILTIN_COMIGESD,
17092 IX86_BUILTIN_COMINEQSD,
17093 IX86_BUILTIN_UCOMIEQSD,
17094 IX86_BUILTIN_UCOMILTSD,
17095 IX86_BUILTIN_UCOMILESD,
17096 IX86_BUILTIN_UCOMIGTSD,
17097 IX86_BUILTIN_UCOMIGESD,
17098 IX86_BUILTIN_UCOMINEQSD,
17100 IX86_BUILTIN_MAXPD,
17101 IX86_BUILTIN_MAXSD,
17102 IX86_BUILTIN_MINPD,
17103 IX86_BUILTIN_MINSD,
17105 IX86_BUILTIN_ANDPD,
17106 IX86_BUILTIN_ANDNPD,
17108 IX86_BUILTIN_XORPD,
17110 IX86_BUILTIN_SQRTPD,
17111 IX86_BUILTIN_SQRTSD,
17113 IX86_BUILTIN_UNPCKHPD,
17114 IX86_BUILTIN_UNPCKLPD,
17116 IX86_BUILTIN_SHUFPD,
17118 IX86_BUILTIN_LOADUPD,
17119 IX86_BUILTIN_STOREUPD,
17120 IX86_BUILTIN_MOVSD,
17122 IX86_BUILTIN_LOADHPD,
17123 IX86_BUILTIN_LOADLPD,
17125 IX86_BUILTIN_CVTDQ2PD,
17126 IX86_BUILTIN_CVTDQ2PS,
17128 IX86_BUILTIN_CVTPD2DQ,
17129 IX86_BUILTIN_CVTPD2PI,
17130 IX86_BUILTIN_CVTPD2PS,
17131 IX86_BUILTIN_CVTTPD2DQ,
17132 IX86_BUILTIN_CVTTPD2PI,
17134 IX86_BUILTIN_CVTPI2PD,
17135 IX86_BUILTIN_CVTSI2SD,
17136 IX86_BUILTIN_CVTSI642SD,
17138 IX86_BUILTIN_CVTSD2SI,
17139 IX86_BUILTIN_CVTSD2SI64,
17140 IX86_BUILTIN_CVTSD2SS,
17141 IX86_BUILTIN_CVTSS2SD,
17142 IX86_BUILTIN_CVTTSD2SI,
17143 IX86_BUILTIN_CVTTSD2SI64,
17145 IX86_BUILTIN_CVTPS2DQ,
17146 IX86_BUILTIN_CVTPS2PD,
17147 IX86_BUILTIN_CVTTPS2DQ,
17149 IX86_BUILTIN_MOVNTI,
17150 IX86_BUILTIN_MOVNTPD,
17151 IX86_BUILTIN_MOVNTDQ,
17154 IX86_BUILTIN_MASKMOVDQU,
17155 IX86_BUILTIN_MOVMSKPD,
17156 IX86_BUILTIN_PMOVMSKB128,
17158 IX86_BUILTIN_PACKSSWB128,
17159 IX86_BUILTIN_PACKSSDW128,
17160 IX86_BUILTIN_PACKUSWB128,
17162 IX86_BUILTIN_PADDB128,
17163 IX86_BUILTIN_PADDW128,
17164 IX86_BUILTIN_PADDD128,
17165 IX86_BUILTIN_PADDQ128,
17166 IX86_BUILTIN_PADDSB128,
17167 IX86_BUILTIN_PADDSW128,
17168 IX86_BUILTIN_PADDUSB128,
17169 IX86_BUILTIN_PADDUSW128,
17170 IX86_BUILTIN_PSUBB128,
17171 IX86_BUILTIN_PSUBW128,
17172 IX86_BUILTIN_PSUBD128,
17173 IX86_BUILTIN_PSUBQ128,
17174 IX86_BUILTIN_PSUBSB128,
17175 IX86_BUILTIN_PSUBSW128,
17176 IX86_BUILTIN_PSUBUSB128,
17177 IX86_BUILTIN_PSUBUSW128,
17179 IX86_BUILTIN_PAND128,
17180 IX86_BUILTIN_PANDN128,
17181 IX86_BUILTIN_POR128,
17182 IX86_BUILTIN_PXOR128,
17184 IX86_BUILTIN_PAVGB128,
17185 IX86_BUILTIN_PAVGW128,
17187 IX86_BUILTIN_PCMPEQB128,
17188 IX86_BUILTIN_PCMPEQW128,
17189 IX86_BUILTIN_PCMPEQD128,
17190 IX86_BUILTIN_PCMPGTB128,
17191 IX86_BUILTIN_PCMPGTW128,
17192 IX86_BUILTIN_PCMPGTD128,
17194 IX86_BUILTIN_PMADDWD128,
17196 IX86_BUILTIN_PMAXSW128,
17197 IX86_BUILTIN_PMAXUB128,
17198 IX86_BUILTIN_PMINSW128,
17199 IX86_BUILTIN_PMINUB128,
17201 IX86_BUILTIN_PMULUDQ,
17202 IX86_BUILTIN_PMULUDQ128,
17203 IX86_BUILTIN_PMULHUW128,
17204 IX86_BUILTIN_PMULHW128,
17205 IX86_BUILTIN_PMULLW128,
17207 IX86_BUILTIN_PSADBW128,
17208 IX86_BUILTIN_PSHUFHW,
17209 IX86_BUILTIN_PSHUFLW,
17210 IX86_BUILTIN_PSHUFD,
17212 IX86_BUILTIN_PSLLDQI128,
17213 IX86_BUILTIN_PSLLWI128,
17214 IX86_BUILTIN_PSLLDI128,
17215 IX86_BUILTIN_PSLLQI128,
17216 IX86_BUILTIN_PSRAWI128,
17217 IX86_BUILTIN_PSRADI128,
17218 IX86_BUILTIN_PSRLDQI128,
17219 IX86_BUILTIN_PSRLWI128,
17220 IX86_BUILTIN_PSRLDI128,
17221 IX86_BUILTIN_PSRLQI128,
17223 IX86_BUILTIN_PSLLDQ128,
17224 IX86_BUILTIN_PSLLW128,
17225 IX86_BUILTIN_PSLLD128,
17226 IX86_BUILTIN_PSLLQ128,
17227 IX86_BUILTIN_PSRAW128,
17228 IX86_BUILTIN_PSRAD128,
17229 IX86_BUILTIN_PSRLW128,
17230 IX86_BUILTIN_PSRLD128,
17231 IX86_BUILTIN_PSRLQ128,
17233 IX86_BUILTIN_PUNPCKHBW128,
17234 IX86_BUILTIN_PUNPCKHWD128,
17235 IX86_BUILTIN_PUNPCKHDQ128,
17236 IX86_BUILTIN_PUNPCKHQDQ128,
17237 IX86_BUILTIN_PUNPCKLBW128,
17238 IX86_BUILTIN_PUNPCKLWD128,
17239 IX86_BUILTIN_PUNPCKLDQ128,
17240 IX86_BUILTIN_PUNPCKLQDQ128,
17242 IX86_BUILTIN_CLFLUSH,
17243 IX86_BUILTIN_MFENCE,
17244 IX86_BUILTIN_LFENCE,
17246 /* Prescott New Instructions. */
17247 IX86_BUILTIN_ADDSUBPS,
17248 IX86_BUILTIN_HADDPS,
17249 IX86_BUILTIN_HSUBPS,
17250 IX86_BUILTIN_MOVSHDUP,
17251 IX86_BUILTIN_MOVSLDUP,
17252 IX86_BUILTIN_ADDSUBPD,
17253 IX86_BUILTIN_HADDPD,
17254 IX86_BUILTIN_HSUBPD,
17255 IX86_BUILTIN_LDDQU,
17257 IX86_BUILTIN_MONITOR,
17258 IX86_BUILTIN_MWAIT,
17261 IX86_BUILTIN_PHADDW,
17262 IX86_BUILTIN_PHADDD,
17263 IX86_BUILTIN_PHADDSW,
17264 IX86_BUILTIN_PHSUBW,
17265 IX86_BUILTIN_PHSUBD,
17266 IX86_BUILTIN_PHSUBSW,
17267 IX86_BUILTIN_PMADDUBSW,
17268 IX86_BUILTIN_PMULHRSW,
17269 IX86_BUILTIN_PSHUFB,
17270 IX86_BUILTIN_PSIGNB,
17271 IX86_BUILTIN_PSIGNW,
17272 IX86_BUILTIN_PSIGND,
17273 IX86_BUILTIN_PALIGNR,
17274 IX86_BUILTIN_PABSB,
17275 IX86_BUILTIN_PABSW,
17276 IX86_BUILTIN_PABSD,
17278 IX86_BUILTIN_PHADDW128,
17279 IX86_BUILTIN_PHADDD128,
17280 IX86_BUILTIN_PHADDSW128,
17281 IX86_BUILTIN_PHSUBW128,
17282 IX86_BUILTIN_PHSUBD128,
17283 IX86_BUILTIN_PHSUBSW128,
17284 IX86_BUILTIN_PMADDUBSW128,
17285 IX86_BUILTIN_PMULHRSW128,
17286 IX86_BUILTIN_PSHUFB128,
17287 IX86_BUILTIN_PSIGNB128,
17288 IX86_BUILTIN_PSIGNW128,
17289 IX86_BUILTIN_PSIGND128,
17290 IX86_BUILTIN_PALIGNR128,
17291 IX86_BUILTIN_PABSB128,
17292 IX86_BUILTIN_PABSW128,
17293 IX86_BUILTIN_PABSD128,
17295 /* AMDFAM10 - SSE4A New Instructions. */
17296 IX86_BUILTIN_MOVNTSD,
17297 IX86_BUILTIN_MOVNTSS,
17298 IX86_BUILTIN_EXTRQI,
17299 IX86_BUILTIN_EXTRQ,
17300 IX86_BUILTIN_INSERTQI,
17301 IX86_BUILTIN_INSERTQ,
17304 IX86_BUILTIN_BLENDPD,
17305 IX86_BUILTIN_BLENDPS,
17306 IX86_BUILTIN_BLENDVPD,
17307 IX86_BUILTIN_BLENDVPS,
17308 IX86_BUILTIN_PBLENDVB128,
17309 IX86_BUILTIN_PBLENDW128,
17314 IX86_BUILTIN_INSERTPS128,
17316 IX86_BUILTIN_MOVNTDQA,
17317 IX86_BUILTIN_MPSADBW128,
17318 IX86_BUILTIN_PACKUSDW128,
17319 IX86_BUILTIN_PCMPEQQ,
17320 IX86_BUILTIN_PHMINPOSUW128,
17322 IX86_BUILTIN_PMAXSB128,
17323 IX86_BUILTIN_PMAXSD128,
17324 IX86_BUILTIN_PMAXUD128,
17325 IX86_BUILTIN_PMAXUW128,
17327 IX86_BUILTIN_PMINSB128,
17328 IX86_BUILTIN_PMINSD128,
17329 IX86_BUILTIN_PMINUD128,
17330 IX86_BUILTIN_PMINUW128,
17332 IX86_BUILTIN_PMOVSXBW128,
17333 IX86_BUILTIN_PMOVSXBD128,
17334 IX86_BUILTIN_PMOVSXBQ128,
17335 IX86_BUILTIN_PMOVSXWD128,
17336 IX86_BUILTIN_PMOVSXWQ128,
17337 IX86_BUILTIN_PMOVSXDQ128,
17339 IX86_BUILTIN_PMOVZXBW128,
17340 IX86_BUILTIN_PMOVZXBD128,
17341 IX86_BUILTIN_PMOVZXBQ128,
17342 IX86_BUILTIN_PMOVZXWD128,
17343 IX86_BUILTIN_PMOVZXWQ128,
17344 IX86_BUILTIN_PMOVZXDQ128,
17346 IX86_BUILTIN_PMULDQ128,
17347 IX86_BUILTIN_PMULLD128,
17349 IX86_BUILTIN_ROUNDPD,
17350 IX86_BUILTIN_ROUNDPS,
17351 IX86_BUILTIN_ROUNDSD,
17352 IX86_BUILTIN_ROUNDSS,
17354 IX86_BUILTIN_PTESTZ,
17355 IX86_BUILTIN_PTESTC,
17356 IX86_BUILTIN_PTESTNZC,
17358 IX86_BUILTIN_VEC_INIT_V2SI,
17359 IX86_BUILTIN_VEC_INIT_V4HI,
17360 IX86_BUILTIN_VEC_INIT_V8QI,
17361 IX86_BUILTIN_VEC_EXT_V2DF,
17362 IX86_BUILTIN_VEC_EXT_V2DI,
17363 IX86_BUILTIN_VEC_EXT_V4SF,
17364 IX86_BUILTIN_VEC_EXT_V4SI,
17365 IX86_BUILTIN_VEC_EXT_V8HI,
17366 IX86_BUILTIN_VEC_EXT_V2SI,
17367 IX86_BUILTIN_VEC_EXT_V4HI,
17368 IX86_BUILTIN_VEC_EXT_V16QI,
17369 IX86_BUILTIN_VEC_SET_V2DI,
17370 IX86_BUILTIN_VEC_SET_V4SF,
17371 IX86_BUILTIN_VEC_SET_V4SI,
17372 IX86_BUILTIN_VEC_SET_V8HI,
17373 IX86_BUILTIN_VEC_SET_V4HI,
17374 IX86_BUILTIN_VEC_SET_V16QI,
17376 IX86_BUILTIN_VEC_PACK_SFIX,
17379 IX86_BUILTIN_CRC32QI,
17380 IX86_BUILTIN_CRC32HI,
17381 IX86_BUILTIN_CRC32SI,
17382 IX86_BUILTIN_CRC32DI,
17384 IX86_BUILTIN_PCMPESTRI128,
17385 IX86_BUILTIN_PCMPESTRM128,
17386 IX86_BUILTIN_PCMPESTRA128,
17387 IX86_BUILTIN_PCMPESTRC128,
17388 IX86_BUILTIN_PCMPESTRO128,
17389 IX86_BUILTIN_PCMPESTRS128,
17390 IX86_BUILTIN_PCMPESTRZ128,
17391 IX86_BUILTIN_PCMPISTRI128,
17392 IX86_BUILTIN_PCMPISTRM128,
17393 IX86_BUILTIN_PCMPISTRA128,
17394 IX86_BUILTIN_PCMPISTRC128,
17395 IX86_BUILTIN_PCMPISTRO128,
17396 IX86_BUILTIN_PCMPISTRS128,
17397 IX86_BUILTIN_PCMPISTRZ128,
17399 IX86_BUILTIN_PCMPGTQ,
17401 /* TFmode support builtins. */
17403 IX86_BUILTIN_FABSQ,
17404 IX86_BUILTIN_COPYSIGNQ,
17406 /* SSE5 instructions */
17407 IX86_BUILTIN_FMADDSS,
17408 IX86_BUILTIN_FMADDSD,
17409 IX86_BUILTIN_FMADDPS,
17410 IX86_BUILTIN_FMADDPD,
17411 IX86_BUILTIN_FMSUBSS,
17412 IX86_BUILTIN_FMSUBSD,
17413 IX86_BUILTIN_FMSUBPS,
17414 IX86_BUILTIN_FMSUBPD,
17415 IX86_BUILTIN_FNMADDSS,
17416 IX86_BUILTIN_FNMADDSD,
17417 IX86_BUILTIN_FNMADDPS,
17418 IX86_BUILTIN_FNMADDPD,
17419 IX86_BUILTIN_FNMSUBSS,
17420 IX86_BUILTIN_FNMSUBSD,
17421 IX86_BUILTIN_FNMSUBPS,
17422 IX86_BUILTIN_FNMSUBPD,
17423 IX86_BUILTIN_PCMOV_V2DI,
17424 IX86_BUILTIN_PCMOV_V4SI,
17425 IX86_BUILTIN_PCMOV_V8HI,
17426 IX86_BUILTIN_PCMOV_V16QI,
17427 IX86_BUILTIN_PCMOV_V4SF,
17428 IX86_BUILTIN_PCMOV_V2DF,
17429 IX86_BUILTIN_PPERM,
17430 IX86_BUILTIN_PERMPS,
17431 IX86_BUILTIN_PERMPD,
17432 IX86_BUILTIN_PMACSSWW,
17433 IX86_BUILTIN_PMACSWW,
17434 IX86_BUILTIN_PMACSSWD,
17435 IX86_BUILTIN_PMACSWD,
17436 IX86_BUILTIN_PMACSSDD,
17437 IX86_BUILTIN_PMACSDD,
17438 IX86_BUILTIN_PMACSSDQL,
17439 IX86_BUILTIN_PMACSSDQH,
17440 IX86_BUILTIN_PMACSDQL,
17441 IX86_BUILTIN_PMACSDQH,
17442 IX86_BUILTIN_PMADCSSWD,
17443 IX86_BUILTIN_PMADCSWD,
17444 IX86_BUILTIN_PHADDBW,
17445 IX86_BUILTIN_PHADDBD,
17446 IX86_BUILTIN_PHADDBQ,
17447 IX86_BUILTIN_PHADDWD,
17448 IX86_BUILTIN_PHADDWQ,
17449 IX86_BUILTIN_PHADDDQ,
17450 IX86_BUILTIN_PHADDUBW,
17451 IX86_BUILTIN_PHADDUBD,
17452 IX86_BUILTIN_PHADDUBQ,
17453 IX86_BUILTIN_PHADDUWD,
17454 IX86_BUILTIN_PHADDUWQ,
17455 IX86_BUILTIN_PHADDUDQ,
17456 IX86_BUILTIN_PHSUBBW,
17457 IX86_BUILTIN_PHSUBWD,
17458 IX86_BUILTIN_PHSUBDQ,
17459 IX86_BUILTIN_PROTB,
17460 IX86_BUILTIN_PROTW,
17461 IX86_BUILTIN_PROTD,
17462 IX86_BUILTIN_PROTQ,
17463 IX86_BUILTIN_PROTB_IMM,
17464 IX86_BUILTIN_PROTW_IMM,
17465 IX86_BUILTIN_PROTD_IMM,
17466 IX86_BUILTIN_PROTQ_IMM,
17467 IX86_BUILTIN_PSHLB,
17468 IX86_BUILTIN_PSHLW,
17469 IX86_BUILTIN_PSHLD,
17470 IX86_BUILTIN_PSHLQ,
17471 IX86_BUILTIN_PSHAB,
17472 IX86_BUILTIN_PSHAW,
17473 IX86_BUILTIN_PSHAD,
17474 IX86_BUILTIN_PSHAQ,
17475 IX86_BUILTIN_FRCZSS,
17476 IX86_BUILTIN_FRCZSD,
17477 IX86_BUILTIN_FRCZPS,
17478 IX86_BUILTIN_FRCZPD,
17479 IX86_BUILTIN_CVTPH2PS,
17480 IX86_BUILTIN_CVTPS2PH,
17482 IX86_BUILTIN_COMEQSS,
17483 IX86_BUILTIN_COMNESS,
17484 IX86_BUILTIN_COMLTSS,
17485 IX86_BUILTIN_COMLESS,
17486 IX86_BUILTIN_COMGTSS,
17487 IX86_BUILTIN_COMGESS,
17488 IX86_BUILTIN_COMUEQSS,
17489 IX86_BUILTIN_COMUNESS,
17490 IX86_BUILTIN_COMULTSS,
17491 IX86_BUILTIN_COMULESS,
17492 IX86_BUILTIN_COMUGTSS,
17493 IX86_BUILTIN_COMUGESS,
17494 IX86_BUILTIN_COMORDSS,
17495 IX86_BUILTIN_COMUNORDSS,
17496 IX86_BUILTIN_COMFALSESS,
17497 IX86_BUILTIN_COMTRUESS,
17499 IX86_BUILTIN_COMEQSD,
17500 IX86_BUILTIN_COMNESD,
17501 IX86_BUILTIN_COMLTSD,
17502 IX86_BUILTIN_COMLESD,
17503 IX86_BUILTIN_COMGTSD,
17504 IX86_BUILTIN_COMGESD,
17505 IX86_BUILTIN_COMUEQSD,
17506 IX86_BUILTIN_COMUNESD,
17507 IX86_BUILTIN_COMULTSD,
17508 IX86_BUILTIN_COMULESD,
17509 IX86_BUILTIN_COMUGTSD,
17510 IX86_BUILTIN_COMUGESD,
17511 IX86_BUILTIN_COMORDSD,
17512 IX86_BUILTIN_COMUNORDSD,
17513 IX86_BUILTIN_COMFALSESD,
17514 IX86_BUILTIN_COMTRUESD,
17516 IX86_BUILTIN_COMEQPS,
17517 IX86_BUILTIN_COMNEPS,
17518 IX86_BUILTIN_COMLTPS,
17519 IX86_BUILTIN_COMLEPS,
17520 IX86_BUILTIN_COMGTPS,
17521 IX86_BUILTIN_COMGEPS,
17522 IX86_BUILTIN_COMUEQPS,
17523 IX86_BUILTIN_COMUNEPS,
17524 IX86_BUILTIN_COMULTPS,
17525 IX86_BUILTIN_COMULEPS,
17526 IX86_BUILTIN_COMUGTPS,
17527 IX86_BUILTIN_COMUGEPS,
17528 IX86_BUILTIN_COMORDPS,
17529 IX86_BUILTIN_COMUNORDPS,
17530 IX86_BUILTIN_COMFALSEPS,
17531 IX86_BUILTIN_COMTRUEPS,
17533 IX86_BUILTIN_COMEQPD,
17534 IX86_BUILTIN_COMNEPD,
17535 IX86_BUILTIN_COMLTPD,
17536 IX86_BUILTIN_COMLEPD,
17537 IX86_BUILTIN_COMGTPD,
17538 IX86_BUILTIN_COMGEPD,
17539 IX86_BUILTIN_COMUEQPD,
17540 IX86_BUILTIN_COMUNEPD,
17541 IX86_BUILTIN_COMULTPD,
17542 IX86_BUILTIN_COMULEPD,
17543 IX86_BUILTIN_COMUGTPD,
17544 IX86_BUILTIN_COMUGEPD,
17545 IX86_BUILTIN_COMORDPD,
17546 IX86_BUILTIN_COMUNORDPD,
17547 IX86_BUILTIN_COMFALSEPD,
17548 IX86_BUILTIN_COMTRUEPD,
17550 IX86_BUILTIN_PCOMEQUB,
17551 IX86_BUILTIN_PCOMNEUB,
17552 IX86_BUILTIN_PCOMLTUB,
17553 IX86_BUILTIN_PCOMLEUB,
17554 IX86_BUILTIN_PCOMGTUB,
17555 IX86_BUILTIN_PCOMGEUB,
17556 IX86_BUILTIN_PCOMFALSEUB,
17557 IX86_BUILTIN_PCOMTRUEUB,
17558 IX86_BUILTIN_PCOMEQUW,
17559 IX86_BUILTIN_PCOMNEUW,
17560 IX86_BUILTIN_PCOMLTUW,
17561 IX86_BUILTIN_PCOMLEUW,
17562 IX86_BUILTIN_PCOMGTUW,
17563 IX86_BUILTIN_PCOMGEUW,
17564 IX86_BUILTIN_PCOMFALSEUW,
17565 IX86_BUILTIN_PCOMTRUEUW,
17566 IX86_BUILTIN_PCOMEQUD,
17567 IX86_BUILTIN_PCOMNEUD,
17568 IX86_BUILTIN_PCOMLTUD,
17569 IX86_BUILTIN_PCOMLEUD,
17570 IX86_BUILTIN_PCOMGTUD,
17571 IX86_BUILTIN_PCOMGEUD,
17572 IX86_BUILTIN_PCOMFALSEUD,
17573 IX86_BUILTIN_PCOMTRUEUD,
17574 IX86_BUILTIN_PCOMEQUQ,
17575 IX86_BUILTIN_PCOMNEUQ,
17576 IX86_BUILTIN_PCOMLTUQ,
17577 IX86_BUILTIN_PCOMLEUQ,
17578 IX86_BUILTIN_PCOMGTUQ,
17579 IX86_BUILTIN_PCOMGEUQ,
17580 IX86_BUILTIN_PCOMFALSEUQ,
17581 IX86_BUILTIN_PCOMTRUEUQ,
17583 IX86_BUILTIN_PCOMEQB,
17584 IX86_BUILTIN_PCOMNEB,
17585 IX86_BUILTIN_PCOMLTB,
17586 IX86_BUILTIN_PCOMLEB,
17587 IX86_BUILTIN_PCOMGTB,
17588 IX86_BUILTIN_PCOMGEB,
17589 IX86_BUILTIN_PCOMFALSEB,
17590 IX86_BUILTIN_PCOMTRUEB,
17591 IX86_BUILTIN_PCOMEQW,
17592 IX86_BUILTIN_PCOMNEW,
17593 IX86_BUILTIN_PCOMLTW,
17594 IX86_BUILTIN_PCOMLEW,
17595 IX86_BUILTIN_PCOMGTW,
17596 IX86_BUILTIN_PCOMGEW,
17597 IX86_BUILTIN_PCOMFALSEW,
17598 IX86_BUILTIN_PCOMTRUEW,
17599 IX86_BUILTIN_PCOMEQD,
17600 IX86_BUILTIN_PCOMNED,
17601 IX86_BUILTIN_PCOMLTD,
17602 IX86_BUILTIN_PCOMLED,
17603 IX86_BUILTIN_PCOMGTD,
17604 IX86_BUILTIN_PCOMGED,
17605 IX86_BUILTIN_PCOMFALSED,
17606 IX86_BUILTIN_PCOMTRUED,
17607 IX86_BUILTIN_PCOMEQQ,
17608 IX86_BUILTIN_PCOMNEQ,
17609 IX86_BUILTIN_PCOMLTQ,
17610 IX86_BUILTIN_PCOMLEQ,
17611 IX86_BUILTIN_PCOMGTQ,
17612 IX86_BUILTIN_PCOMGEQ,
17613 IX86_BUILTIN_PCOMFALSEQ,
17614 IX86_BUILTIN_PCOMTRUEQ,
17619 /* Table for the ix86 builtin decls. */
17620 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
17622 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
17623 * if the target_flags include one of MASK. Stores the function decl
17624 * in the ix86_builtins array.
17625 * Returns the function decl or NULL_TREE, if the builtin was not added. */
17628 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
17630 tree decl = NULL_TREE;
17632 if (mask & ix86_isa_flags
17633 && (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT))
17635 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
17637 ix86_builtins[(int) code] = decl;
17643 /* Like def_builtin, but also marks the function decl "const". */
17646 def_builtin_const (int mask, const char *name, tree type,
17647 enum ix86_builtins code)
17649 tree decl = def_builtin (mask, name, type, code);
17651 TREE_READONLY (decl) = 1;
17655 /* Bits for builtin_description.flag. */
17657 /* Set when we don't support the comparison natively, and should
17658 swap_comparison in order to support it. */
17659 #define BUILTIN_DESC_SWAP_OPERANDS 1
17661 struct builtin_description
17663 const unsigned int mask;
17664 const enum insn_code icode;
17665 const char *const name;
17666 const enum ix86_builtins code;
17667 const enum rtx_code comparison;
17671 static const struct builtin_description bdesc_comi[] =
17673 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
17674 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
17675 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
17676 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
17677 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
17678 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
17679 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
17680 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
17681 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
17682 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
17683 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
17684 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
17685 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
17686 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
17687 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
17688 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
17689 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
17690 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
17691 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
17692 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
17693 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
17694 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
17695 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
17696 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
17699 static const struct builtin_description bdesc_ptest[] =
17702 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, 0 },
17703 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, 0 },
17704 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, 0 },
17707 static const struct builtin_description bdesc_pcmpestr[] =
17710 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
17711 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
17712 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
17713 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
17714 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
17715 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
17716 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
17719 static const struct builtin_description bdesc_pcmpistr[] =
17722 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
17723 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
17724 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
17725 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
17726 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
17727 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
17728 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
17731 static const struct builtin_description bdesc_crc32[] =
17734 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32qi, 0, IX86_BUILTIN_CRC32QI, UNKNOWN, 0 },
17735 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, 0, IX86_BUILTIN_CRC32HI, UNKNOWN, 0 },
17736 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, 0, IX86_BUILTIN_CRC32SI, UNKNOWN, 0 },
17737 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32di, 0, IX86_BUILTIN_CRC32DI, UNKNOWN, 0 },
17740 /* SSE builtins with 3 arguments and the last argument must be an immediate or xmm0. */
17741 static const struct builtin_description bdesc_sse_3arg[] =
17744 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, 0 },
17745 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, 0 },
17746 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, 0 },
17747 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, 0 },
17748 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, 0 },
17749 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, 0 },
17750 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, 0 },
17751 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, 0 },
17752 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, 0 },
17753 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, 0 },
17754 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, 0, IX86_BUILTIN_ROUNDSD, UNKNOWN, 0 },
17755 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, 0, IX86_BUILTIN_ROUNDSS, UNKNOWN, 0 },
17758 static const struct builtin_description bdesc_2arg[] =
17761 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, 0 },
17762 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, 0 },
17763 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, 0 },
17764 { OPTION_MASK_ISA_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, 0 },
17765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, 0 },
17766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, 0 },
17767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, 0 },
17768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, 0 },
17770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
17771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
17772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
17773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, BUILTIN_DESC_SWAP_OPERANDS },
17774 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, BUILTIN_DESC_SWAP_OPERANDS },
17775 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
17776 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
17777 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
17778 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
17779 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17780 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17781 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
17782 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
17783 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
17784 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
17785 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
17786 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
17787 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
17788 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
17789 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17790 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17791 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 },
17793 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, 0 },
17794 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, 0 },
17795 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, 0 },
17796 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, 0 },
17798 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, 0 },
17799 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, 0 },
17800 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, 0 },
17801 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, 0 },
17803 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, 0 },
17804 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, 0 },
17805 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, 0 },
17806 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, 0 },
17807 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, 0 },
17810 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, 0 },
17811 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, 0 },
17812 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, 0 },
17813 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, 0 },
17814 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, 0 },
17815 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, 0 },
17816 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, 0 },
17817 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, 0 },
17819 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, 0 },
17820 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, 0 },
17821 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, 0 },
17822 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, 0 },
17823 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, 0 },
17824 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, 0 },
17825 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, 0 },
17826 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, 0 },
17828 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, 0 },
17829 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, 0 },
17830 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, 0 },
17832 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, 0 },
17833 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, 0 },
17834 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, 0 },
17835 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, 0 },
17837 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, 0 },
17838 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, 0 },
17840 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, 0 },
17841 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, 0 },
17842 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, 0 },
17843 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, 0 },
17844 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, 0 },
17845 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, 0 },
17847 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, 0 },
17848 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, 0 },
17849 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, 0 },
17850 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, 0 },
17852 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, 0 },
17853 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, 0 },
17854 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, 0 },
17855 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, 0 },
17856 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, 0 },
17857 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, 0 },
17860 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, UNKNOWN, 0 },
17861 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, UNKNOWN, 0 },
17862 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, UNKNOWN, 0 },
17864 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, UNKNOWN, 0 },
17865 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, UNKNOWN, 0 },
17866 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, UNKNOWN, 0 },
17868 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, UNKNOWN, 0 },
17869 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, UNKNOWN, 0 },
17870 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, UNKNOWN, 0 },
17871 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, UNKNOWN, 0 },
17872 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, UNKNOWN, 0 },
17873 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, UNKNOWN, 0 },
17875 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, UNKNOWN, 0 },
17876 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, UNKNOWN, 0 },
17877 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, UNKNOWN, 0 },
17878 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, UNKNOWN, 0 },
17879 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, UNKNOWN, 0 },
17880 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, UNKNOWN, 0 },
17882 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, UNKNOWN, 0 },
17883 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, UNKNOWN, 0 },
17884 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, UNKNOWN, 0 },
17885 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, UNKNOWN, 0 },
17887 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, UNKNOWN, 0 },
17888 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, UNKNOWN, 0 },
17891 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, 0 },
17892 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, 0 },
17893 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, 0 },
17894 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, 0 },
17895 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, 0 },
17896 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, 0 },
17897 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, 0 },
17898 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, 0 },
17900 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
17901 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
17902 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
17903 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, BUILTIN_DESC_SWAP_OPERANDS },
17904 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, BUILTIN_DESC_SWAP_OPERANDS },
17905 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
17906 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
17907 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
17908 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
17909 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
17910 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
17911 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
17912 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
17913 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
17914 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
17915 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
17916 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
17917 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
17918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
17919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
17921 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, 0 },
17922 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, 0 },
17923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, 0 },
17924 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, 0 },
17926 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, 0 },
17927 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, 0 },
17928 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, 0 },
17929 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, 0 },
17931 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, 0 },
17932 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, 0 },
17933 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, 0 },
17935 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, 0 },
17938 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, 0 },
17939 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, 0 },
17940 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, 0 },
17941 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, 0 },
17942 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, 0 },
17943 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, 0 },
17944 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, 0 },
17945 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, 0 },
17947 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, 0 },
17948 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, 0 },
17949 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, 0 },
17950 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, 0 },
17951 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, 0 },
17952 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, 0 },
17953 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, 0 },
17954 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, 0 },
17956 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, 0 },
17957 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN, 0 },
17959 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, 0 },
17960 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, 0 },
17961 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, 0 },
17962 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, 0 },
17964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, 0 },
17965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, 0 },
17967 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, 0 },
17968 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, 0 },
17969 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, 0 },
17970 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, 0 },
17971 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, 0 },
17972 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, 0 },
17974 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, 0 },
17975 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, 0 },
17976 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, 0 },
17977 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, 0 },
17979 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, 0 },
17980 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, 0 },
17981 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, 0 },
17982 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, 0 },
17983 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, 0 },
17984 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, 0 },
17985 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, 0 },
17986 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, 0 },
17988 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, 0 },
17989 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, 0 },
17990 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, 0 },
17992 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, 0 },
17993 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, UNKNOWN, 0 },
17995 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, UNKNOWN, 0 },
17996 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, UNKNOWN, 0 },
17998 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, UNKNOWN, 0 },
17999 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, UNKNOWN, 0 },
18000 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, UNKNOWN, 0 },
18002 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, UNKNOWN, 0 },
18003 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, UNKNOWN, 0 },
18004 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, UNKNOWN, 0 },
18006 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, UNKNOWN, 0 },
18007 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, UNKNOWN, 0 },
18009 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, UNKNOWN, 0 },
18011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, UNKNOWN, 0 },
18012 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, UNKNOWN, 0 },
18013 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, UNKNOWN, 0 },
18014 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, UNKNOWN, 0 },
18017 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, 0 },
18018 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, 0 },
18019 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, 0 },
18020 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, 0 },
18021 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, 0 },
18022 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, 0 },
18025 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, 0 },
18026 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, 0 },
18027 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, 0 },
18028 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, 0 },
18029 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, 0 },
18030 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, 0 },
18031 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, 0 },
18032 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, 0 },
18033 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, 0 },
18034 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, 0 },
18035 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, 0 },
18036 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, 0 },
18037 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, 0 },
18038 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, 0 },
18039 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, 0 },
18040 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, 0 },
18041 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, 0 },
18042 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, 0 },
18043 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, 0 },
18044 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, 0 },
18045 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, 0 },
18046 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, 0 },
18047 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, 0 },
18048 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, 0 },
18051 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, 0 },
18052 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, 0 },
18053 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, 0 },
18054 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, 0 },
18055 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, 0 },
18056 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, 0 },
18057 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, 0 },
18058 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, 0 },
18059 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, 0 },
18060 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, 0 },
18061 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, 0, IX86_BUILTIN_PMULDQ128, UNKNOWN, 0 },
18062 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, 0 },
18065 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, 0 },
18068 static const struct builtin_description bdesc_1arg[] =
18070 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, UNKNOWN, 0 },
18071 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, UNKNOWN, 0 },
18073 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, UNKNOWN, 0 },
18074 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, UNKNOWN, 0 },
18075 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, UNKNOWN, 0 },
18077 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, UNKNOWN, 0 },
18078 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, UNKNOWN, 0 },
18079 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, UNKNOWN, 0 },
18080 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, UNKNOWN, 0 },
18081 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, UNKNOWN, 0 },
18082 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, 0 },
18084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, UNKNOWN, 0 },
18085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, UNKNOWN, 0 },
18087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, UNKNOWN, 0 },
18089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, UNKNOWN, 0 },
18090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, UNKNOWN, 0 },
18092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, UNKNOWN, 0 },
18093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, UNKNOWN, 0 },
18094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, UNKNOWN, 0 },
18095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, 0 },
18096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, UNKNOWN, 0 },
18098 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, UNKNOWN, 0 },
18100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, UNKNOWN, 0 },
18101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, UNKNOWN, 0 },
18102 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, UNKNOWN, 0 },
18103 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, 0 },
18105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, UNKNOWN, 0 },
18106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, UNKNOWN, 0 },
18107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, 0 },
18110 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, 0 },
18111 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, 0 },
18114 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, 0 },
18115 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, 0 },
18116 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, 0 },
18117 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, 0 },
18118 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, 0 },
18119 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, 0 },
18122 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVSXBW128, UNKNOWN, 0 },
18123 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVSXBD128, UNKNOWN, 0 },
18124 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, 0 },
18125 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVSXWD128, UNKNOWN, 0 },
18126 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, 0 },
18127 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, 0, IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, 0 },
18128 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVZXBW128, UNKNOWN, 0 },
18129 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVZXBD128, UNKNOWN, 0 },
18130 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, 0 },
18131 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVZXWD128, UNKNOWN, 0 },
18132 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, 0 },
18133 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, 0, IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, 0 },
18134 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, 0 },
18136 /* Fake 1 arg builtins with a constant smaller than 8 bits as the 2nd arg. */
18137 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundpd, 0, IX86_BUILTIN_ROUNDPD, UNKNOWN, 0 },
18138 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_roundps, 0, IX86_BUILTIN_ROUNDPS, UNKNOWN, 0 },
18142 enum multi_arg_type {
18152 MULTI_ARG_3_PERMPS,
18153 MULTI_ARG_3_PERMPD,
18160 MULTI_ARG_2_DI_IMM,
18161 MULTI_ARG_2_SI_IMM,
18162 MULTI_ARG_2_HI_IMM,
18163 MULTI_ARG_2_QI_IMM,
18164 MULTI_ARG_2_SF_CMP,
18165 MULTI_ARG_2_DF_CMP,
18166 MULTI_ARG_2_DI_CMP,
18167 MULTI_ARG_2_SI_CMP,
18168 MULTI_ARG_2_HI_CMP,
18169 MULTI_ARG_2_QI_CMP,
18192 static const struct builtin_description bdesc_multi_arg[] =
18194 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
18195 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
18196 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
18197 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
18198 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
18199 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
18200 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
18201 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
18202 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
18203 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
18204 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
18205 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
18206 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
18207 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
18208 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
18209 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
18210 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18211 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18212 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
18213 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
18214 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
18215 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
18216 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
18217 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
18218 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
18219 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
18220 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
18221 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
18222 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18223 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
18224 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
18225 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
18226 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18227 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18228 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18229 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18230 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18231 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
18232 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
18233 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
18234 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
18235 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
18236 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
18237 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
18238 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
18239 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
18240 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
18241 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
18242 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
18243 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
18244 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
18245 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
18246 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
18247 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
18248 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
18249 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
18250 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
18251 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
18252 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
18253 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
18254 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
18255 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
18256 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
18257 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
18258 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
18259 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
18260 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
18261 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
18262 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
18263 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
18264 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
18265 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
18266 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
18267 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
18268 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
18270 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
18271 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18272 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18273 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
18274 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
18275 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
18276 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
18277 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18278 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18279 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18280 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18281 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18282 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18283 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18284 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18285 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18287 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
18288 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18289 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18290 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
18291 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
18292 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
18293 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
18294 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18295 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18296 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18297 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18298 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18299 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18300 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18301 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18302 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18304 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
18305 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18306 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18307 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
18308 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
18309 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
18310 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
18311 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18312 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18313 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18314 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18315 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18316 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18317 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18318 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18319 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18321 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
18322 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18323 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18324 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
18325 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
18326 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
18327 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
18328 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18329 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18330 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18331 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18332 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18333 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18334 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18335 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18336 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18338 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
18339 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18340 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18341 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
18342 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
18343 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
18344 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
18346 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
18347 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18348 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18349 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
18350 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
18351 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
18352 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
18354 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
18355 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18356 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18357 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
18358 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
18359 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
18360 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
18362 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18363 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18364 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18365 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
18366 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
18367 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
18368 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
18370 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
18371 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18372 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18373 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
18374 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
18375 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
18376 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
18378 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
18379 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18380 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18381 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
18382 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
18383 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
18384 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
18386 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
18387 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18388 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18389 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
18390 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
18391 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
18392 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
18394 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18395 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18396 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18397 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
18398 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
18399 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
18400 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
18402 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
18403 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
18404 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
18405 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
18406 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
18407 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
18408 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
18409 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
18411 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18412 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18413 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18414 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18415 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18416 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18417 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18418 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18420 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18421 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18422 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18423 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18424 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18425 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18426 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18427 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18430 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
18431 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
18434 ix86_init_mmx_sse_builtins (void)
18436 const struct builtin_description * d;
18439 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
18440 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
18441 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
18442 tree V2DI_type_node
18443 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
18444 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
18445 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
18446 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
18447 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
18448 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
18449 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
18451 tree pchar_type_node = build_pointer_type (char_type_node);
18452 tree pcchar_type_node = build_pointer_type (
18453 build_type_variant (char_type_node, 1, 0));
18454 tree pfloat_type_node = build_pointer_type (float_type_node);
18455 tree pcfloat_type_node = build_pointer_type (
18456 build_type_variant (float_type_node, 1, 0));
18457 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
18458 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
18459 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
18462 tree int_ftype_v4sf_v4sf
18463 = build_function_type_list (integer_type_node,
18464 V4SF_type_node, V4SF_type_node, NULL_TREE);
18465 tree v4si_ftype_v4sf_v4sf
18466 = build_function_type_list (V4SI_type_node,
18467 V4SF_type_node, V4SF_type_node, NULL_TREE);
18468 /* MMX/SSE/integer conversions. */
18469 tree int_ftype_v4sf
18470 = build_function_type_list (integer_type_node,
18471 V4SF_type_node, NULL_TREE);
18472 tree int64_ftype_v4sf
18473 = build_function_type_list (long_long_integer_type_node,
18474 V4SF_type_node, NULL_TREE);
18475 tree int_ftype_v8qi
18476 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
18477 tree v4sf_ftype_v4sf_int
18478 = build_function_type_list (V4SF_type_node,
18479 V4SF_type_node, integer_type_node, NULL_TREE);
18480 tree v4sf_ftype_v4sf_int64
18481 = build_function_type_list (V4SF_type_node,
18482 V4SF_type_node, long_long_integer_type_node,
18484 tree v4sf_ftype_v4sf_v2si
18485 = build_function_type_list (V4SF_type_node,
18486 V4SF_type_node, V2SI_type_node, NULL_TREE);
18488 /* Miscellaneous. */
18489 tree v8qi_ftype_v4hi_v4hi
18490 = build_function_type_list (V8QI_type_node,
18491 V4HI_type_node, V4HI_type_node, NULL_TREE);
18492 tree v4hi_ftype_v2si_v2si
18493 = build_function_type_list (V4HI_type_node,
18494 V2SI_type_node, V2SI_type_node, NULL_TREE);
18495 tree v4sf_ftype_v4sf_v4sf_int
18496 = build_function_type_list (V4SF_type_node,
18497 V4SF_type_node, V4SF_type_node,
18498 integer_type_node, NULL_TREE);
18499 tree v2si_ftype_v4hi_v4hi
18500 = build_function_type_list (V2SI_type_node,
18501 V4HI_type_node, V4HI_type_node, NULL_TREE);
18502 tree v4hi_ftype_v4hi_int
18503 = build_function_type_list (V4HI_type_node,
18504 V4HI_type_node, integer_type_node, NULL_TREE);
18505 tree v4hi_ftype_v4hi_di
18506 = build_function_type_list (V4HI_type_node,
18507 V4HI_type_node, long_long_unsigned_type_node,
18509 tree v2si_ftype_v2si_di
18510 = build_function_type_list (V2SI_type_node,
18511 V2SI_type_node, long_long_unsigned_type_node,
18513 tree void_ftype_void
18514 = build_function_type (void_type_node, void_list_node);
18515 tree void_ftype_unsigned
18516 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
18517 tree void_ftype_unsigned_unsigned
18518 = build_function_type_list (void_type_node, unsigned_type_node,
18519 unsigned_type_node, NULL_TREE);
18520 tree void_ftype_pcvoid_unsigned_unsigned
18521 = build_function_type_list (void_type_node, const_ptr_type_node,
18522 unsigned_type_node, unsigned_type_node,
18524 tree unsigned_ftype_void
18525 = build_function_type (unsigned_type_node, void_list_node);
18526 tree v2si_ftype_v4sf
18527 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
18528 /* Loads/stores. */
18529 tree void_ftype_v8qi_v8qi_pchar
18530 = build_function_type_list (void_type_node,
18531 V8QI_type_node, V8QI_type_node,
18532 pchar_type_node, NULL_TREE);
18533 tree v4sf_ftype_pcfloat
18534 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
18535 /* @@@ the type is bogus */
18536 tree v4sf_ftype_v4sf_pv2si
18537 = build_function_type_list (V4SF_type_node,
18538 V4SF_type_node, pv2si_type_node, NULL_TREE);
18539 tree void_ftype_pv2si_v4sf
18540 = build_function_type_list (void_type_node,
18541 pv2si_type_node, V4SF_type_node, NULL_TREE);
18542 tree void_ftype_pfloat_v4sf
18543 = build_function_type_list (void_type_node,
18544 pfloat_type_node, V4SF_type_node, NULL_TREE);
18545 tree void_ftype_pdi_di
18546 = build_function_type_list (void_type_node,
18547 pdi_type_node, long_long_unsigned_type_node,
18549 tree void_ftype_pv2di_v2di
18550 = build_function_type_list (void_type_node,
18551 pv2di_type_node, V2DI_type_node, NULL_TREE);
18552 /* Normal vector unops. */
18553 tree v4sf_ftype_v4sf
18554 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
18555 tree v16qi_ftype_v16qi
18556 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
18557 tree v8hi_ftype_v8hi
18558 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
18559 tree v4si_ftype_v4si
18560 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
18561 tree v8qi_ftype_v8qi
18562 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
18563 tree v4hi_ftype_v4hi
18564 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
18566 /* Normal vector binops. */
18567 tree v4sf_ftype_v4sf_v4sf
18568 = build_function_type_list (V4SF_type_node,
18569 V4SF_type_node, V4SF_type_node, NULL_TREE);
18570 tree v8qi_ftype_v8qi_v8qi
18571 = build_function_type_list (V8QI_type_node,
18572 V8QI_type_node, V8QI_type_node, NULL_TREE);
18573 tree v4hi_ftype_v4hi_v4hi
18574 = build_function_type_list (V4HI_type_node,
18575 V4HI_type_node, V4HI_type_node, NULL_TREE);
18576 tree v2si_ftype_v2si_v2si
18577 = build_function_type_list (V2SI_type_node,
18578 V2SI_type_node, V2SI_type_node, NULL_TREE);
18579 tree di_ftype_di_di
18580 = build_function_type_list (long_long_unsigned_type_node,
18581 long_long_unsigned_type_node,
18582 long_long_unsigned_type_node, NULL_TREE);
18584 tree di_ftype_di_di_int
18585 = build_function_type_list (long_long_unsigned_type_node,
18586 long_long_unsigned_type_node,
18587 long_long_unsigned_type_node,
18588 integer_type_node, NULL_TREE);
18590 tree v2si_ftype_v2sf
18591 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
18592 tree v2sf_ftype_v2si
18593 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
18594 tree v2si_ftype_v2si
18595 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
18596 tree v2sf_ftype_v2sf
18597 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
18598 tree v2sf_ftype_v2sf_v2sf
18599 = build_function_type_list (V2SF_type_node,
18600 V2SF_type_node, V2SF_type_node, NULL_TREE);
18601 tree v2si_ftype_v2sf_v2sf
18602 = build_function_type_list (V2SI_type_node,
18603 V2SF_type_node, V2SF_type_node, NULL_TREE);
18604 tree pint_type_node = build_pointer_type (integer_type_node);
18605 tree pdouble_type_node = build_pointer_type (double_type_node);
18606 tree pcdouble_type_node = build_pointer_type (
18607 build_type_variant (double_type_node, 1, 0));
18608 tree int_ftype_v2df_v2df
18609 = build_function_type_list (integer_type_node,
18610 V2DF_type_node, V2DF_type_node, NULL_TREE);
18612 tree void_ftype_pcvoid
18613 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
18614 tree v4sf_ftype_v4si
18615 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
18616 tree v4si_ftype_v4sf
18617 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
18618 tree v2df_ftype_v4si
18619 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
18620 tree v4si_ftype_v2df
18621 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
18622 tree v4si_ftype_v2df_v2df
18623 = build_function_type_list (V4SI_type_node,
18624 V2DF_type_node, V2DF_type_node, NULL_TREE);
18625 tree v2si_ftype_v2df
18626 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
18627 tree v4sf_ftype_v2df
18628 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
18629 tree v2df_ftype_v2si
18630 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
18631 tree v2df_ftype_v4sf
18632 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
18633 tree int_ftype_v2df
18634 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
18635 tree int64_ftype_v2df
18636 = build_function_type_list (long_long_integer_type_node,
18637 V2DF_type_node, NULL_TREE);
18638 tree v2df_ftype_v2df_int
18639 = build_function_type_list (V2DF_type_node,
18640 V2DF_type_node, integer_type_node, NULL_TREE);
18641 tree v2df_ftype_v2df_int64
18642 = build_function_type_list (V2DF_type_node,
18643 V2DF_type_node, long_long_integer_type_node,
18645 tree v4sf_ftype_v4sf_v2df
18646 = build_function_type_list (V4SF_type_node,
18647 V4SF_type_node, V2DF_type_node, NULL_TREE);
18648 tree v2df_ftype_v2df_v4sf
18649 = build_function_type_list (V2DF_type_node,
18650 V2DF_type_node, V4SF_type_node, NULL_TREE);
18651 tree v2df_ftype_v2df_v2df_int
18652 = build_function_type_list (V2DF_type_node,
18653 V2DF_type_node, V2DF_type_node,
18656 tree v2df_ftype_v2df_pcdouble
18657 = build_function_type_list (V2DF_type_node,
18658 V2DF_type_node, pcdouble_type_node, NULL_TREE);
18659 tree void_ftype_pdouble_v2df
18660 = build_function_type_list (void_type_node,
18661 pdouble_type_node, V2DF_type_node, NULL_TREE);
18662 tree void_ftype_pint_int
18663 = build_function_type_list (void_type_node,
18664 pint_type_node, integer_type_node, NULL_TREE);
18665 tree void_ftype_v16qi_v16qi_pchar
18666 = build_function_type_list (void_type_node,
18667 V16QI_type_node, V16QI_type_node,
18668 pchar_type_node, NULL_TREE);
18669 tree v2df_ftype_pcdouble
18670 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
18671 tree v2df_ftype_v2df_v2df
18672 = build_function_type_list (V2DF_type_node,
18673 V2DF_type_node, V2DF_type_node, NULL_TREE);
18674 tree v16qi_ftype_v16qi_v16qi
18675 = build_function_type_list (V16QI_type_node,
18676 V16QI_type_node, V16QI_type_node, NULL_TREE);
18677 tree v8hi_ftype_v8hi_v8hi
18678 = build_function_type_list (V8HI_type_node,
18679 V8HI_type_node, V8HI_type_node, NULL_TREE);
18680 tree v4si_ftype_v4si_v4si
18681 = build_function_type_list (V4SI_type_node,
18682 V4SI_type_node, V4SI_type_node, NULL_TREE);
18683 tree v2di_ftype_v2di_v2di
18684 = build_function_type_list (V2DI_type_node,
18685 V2DI_type_node, V2DI_type_node, NULL_TREE);
18686 tree v2di_ftype_v2df_v2df
18687 = build_function_type_list (V2DI_type_node,
18688 V2DF_type_node, V2DF_type_node, NULL_TREE);
18689 tree v2df_ftype_v2df
18690 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
18691 tree v2di_ftype_v2di_int
18692 = build_function_type_list (V2DI_type_node,
18693 V2DI_type_node, integer_type_node, NULL_TREE);
18694 tree v2di_ftype_v2di_v2di_int
18695 = build_function_type_list (V2DI_type_node, V2DI_type_node,
18696 V2DI_type_node, integer_type_node, NULL_TREE);
18697 tree v4si_ftype_v4si_int
18698 = build_function_type_list (V4SI_type_node,
18699 V4SI_type_node, integer_type_node, NULL_TREE);
18700 tree v8hi_ftype_v8hi_int
18701 = build_function_type_list (V8HI_type_node,
18702 V8HI_type_node, integer_type_node, NULL_TREE);
18703 tree v4si_ftype_v8hi_v8hi
18704 = build_function_type_list (V4SI_type_node,
18705 V8HI_type_node, V8HI_type_node, NULL_TREE);
18706 tree di_ftype_v8qi_v8qi
18707 = build_function_type_list (long_long_unsigned_type_node,
18708 V8QI_type_node, V8QI_type_node, NULL_TREE);
18709 tree di_ftype_v2si_v2si
18710 = build_function_type_list (long_long_unsigned_type_node,
18711 V2SI_type_node, V2SI_type_node, NULL_TREE);
18712 tree v2di_ftype_v16qi_v16qi
18713 = build_function_type_list (V2DI_type_node,
18714 V16QI_type_node, V16QI_type_node, NULL_TREE);
18715 tree v2di_ftype_v4si_v4si
18716 = build_function_type_list (V2DI_type_node,
18717 V4SI_type_node, V4SI_type_node, NULL_TREE);
18718 tree int_ftype_v16qi
18719 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
18720 tree v16qi_ftype_pcchar
18721 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
18722 tree void_ftype_pchar_v16qi
18723 = build_function_type_list (void_type_node,
18724 pchar_type_node, V16QI_type_node, NULL_TREE);
18726 tree v2di_ftype_v2di_unsigned_unsigned
18727 = build_function_type_list (V2DI_type_node, V2DI_type_node,
18728 unsigned_type_node, unsigned_type_node,
18730 tree v2di_ftype_v2di_v2di_unsigned_unsigned
18731 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
18732 unsigned_type_node, unsigned_type_node,
18734 tree v2di_ftype_v2di_v16qi
18735 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
18737 tree v2df_ftype_v2df_v2df_v2df
18738 = build_function_type_list (V2DF_type_node,
18739 V2DF_type_node, V2DF_type_node,
18740 V2DF_type_node, NULL_TREE);
18741 tree v4sf_ftype_v4sf_v4sf_v4sf
18742 = build_function_type_list (V4SF_type_node,
18743 V4SF_type_node, V4SF_type_node,
18744 V4SF_type_node, NULL_TREE);
18745 tree v8hi_ftype_v16qi
18746 = build_function_type_list (V8HI_type_node, V16QI_type_node,
18748 tree v4si_ftype_v16qi
18749 = build_function_type_list (V4SI_type_node, V16QI_type_node,
18751 tree v2di_ftype_v16qi
18752 = build_function_type_list (V2DI_type_node, V16QI_type_node,
18754 tree v4si_ftype_v8hi
18755 = build_function_type_list (V4SI_type_node, V8HI_type_node,
18757 tree v2di_ftype_v8hi
18758 = build_function_type_list (V2DI_type_node, V8HI_type_node,
18760 tree v2di_ftype_v4si
18761 = build_function_type_list (V2DI_type_node, V4SI_type_node,
18763 tree v2di_ftype_pv2di
18764 = build_function_type_list (V2DI_type_node, pv2di_type_node,
18766 tree v16qi_ftype_v16qi_v16qi_int
18767 = build_function_type_list (V16QI_type_node, V16QI_type_node,
18768 V16QI_type_node, integer_type_node,
18770 tree v16qi_ftype_v16qi_v16qi_v16qi
18771 = build_function_type_list (V16QI_type_node, V16QI_type_node,
18772 V16QI_type_node, V16QI_type_node,
18774 tree v8hi_ftype_v8hi_v8hi_int
18775 = build_function_type_list (V8HI_type_node, V8HI_type_node,
18776 V8HI_type_node, integer_type_node,
18778 tree v4si_ftype_v4si_v4si_int
18779 = build_function_type_list (V4SI_type_node, V4SI_type_node,
18780 V4SI_type_node, integer_type_node,
18782 tree int_ftype_v2di_v2di
18783 = build_function_type_list (integer_type_node,
18784 V2DI_type_node, V2DI_type_node,
18786 tree int_ftype_v16qi_int_v16qi_int_int
18787 = build_function_type_list (integer_type_node,
18794 tree v16qi_ftype_v16qi_int_v16qi_int_int
18795 = build_function_type_list (V16QI_type_node,
18802 tree int_ftype_v16qi_v16qi_int
18803 = build_function_type_list (integer_type_node,
18809 /* SSE5 instructions */
18810 tree v2di_ftype_v2di_v2di_v2di
18811 = build_function_type_list (V2DI_type_node,
18817 tree v4si_ftype_v4si_v4si_v4si
18818 = build_function_type_list (V4SI_type_node,
18824 tree v4si_ftype_v4si_v4si_v2di
18825 = build_function_type_list (V4SI_type_node,
18831 tree v8hi_ftype_v8hi_v8hi_v8hi
18832 = build_function_type_list (V8HI_type_node,
18838 tree v8hi_ftype_v8hi_v8hi_v4si
18839 = build_function_type_list (V8HI_type_node,
18845 tree v2df_ftype_v2df_v2df_v16qi
18846 = build_function_type_list (V2DF_type_node,
18852 tree v4sf_ftype_v4sf_v4sf_v16qi
18853 = build_function_type_list (V4SF_type_node,
18859 tree v2di_ftype_v2di_si
18860 = build_function_type_list (V2DI_type_node,
18865 tree v4si_ftype_v4si_si
18866 = build_function_type_list (V4SI_type_node,
18871 tree v8hi_ftype_v8hi_si
18872 = build_function_type_list (V8HI_type_node,
18877 tree v16qi_ftype_v16qi_si
18878 = build_function_type_list (V16QI_type_node,
18882 tree v4sf_ftype_v4hi
18883 = build_function_type_list (V4SF_type_node,
18887 tree v4hi_ftype_v4sf
18888 = build_function_type_list (V4HI_type_node,
18892 tree v2di_ftype_v2di
18893 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
18897 /* The __float80 type. */
18898 if (TYPE_MODE (long_double_type_node) == XFmode)
18899 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
18903 /* The __float80 type. */
18904 tree float80_type_node = make_node (REAL_TYPE);
18906 TYPE_PRECISION (float80_type_node) = 80;
18907 layout_type (float80_type_node);
18908 (*lang_hooks.types.register_builtin_type) (float80_type_node,
18914 tree float128_type_node = make_node (REAL_TYPE);
18916 TYPE_PRECISION (float128_type_node) = 128;
18917 layout_type (float128_type_node);
18918 (*lang_hooks.types.register_builtin_type) (float128_type_node,
18921 /* TFmode support builtins. */
18922 ftype = build_function_type (float128_type_node,
18924 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_infq", ftype, IX86_BUILTIN_INFQ);
18926 ftype = build_function_type_list (float128_type_node,
18927 float128_type_node,
18929 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_fabsq", ftype, IX86_BUILTIN_FABSQ);
18931 ftype = build_function_type_list (float128_type_node,
18932 float128_type_node,
18933 float128_type_node,
18935 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_copysignq", ftype, IX86_BUILTIN_COPYSIGNQ);
18938 /* Add all SSE builtins that are more or less simple operations on
18940 for (i = 0, d = bdesc_sse_3arg;
18941 i < ARRAY_SIZE (bdesc_sse_3arg);
18944 /* Use one of the operands; the target can have a different mode for
18945 mask-generating compares. */
18946 enum machine_mode mode;
18951 mode = insn_data[d->icode].operand[1].mode;
18956 type = v16qi_ftype_v16qi_v16qi_int;
18959 type = v8hi_ftype_v8hi_v8hi_int;
18962 type = v4si_ftype_v4si_v4si_int;
18965 type = v2di_ftype_v2di_v2di_int;
18968 type = v2df_ftype_v2df_v2df_int;
18971 type = v4sf_ftype_v4sf_v4sf_int;
18974 gcc_unreachable ();
18977 /* Override for variable blends. */
18980 case CODE_FOR_sse4_1_blendvpd:
18981 type = v2df_ftype_v2df_v2df_v2df;
18983 case CODE_FOR_sse4_1_blendvps:
18984 type = v4sf_ftype_v4sf_v4sf_v4sf;
18986 case CODE_FOR_sse4_1_pblendvb:
18987 type = v16qi_ftype_v16qi_v16qi_v16qi;
18993 def_builtin_const (d->mask, d->name, type, d->code);
18996 /* Add all builtins that are more or less simple operations on two
18998 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
19000 /* Use one of the operands; the target can have a different mode for
19001 mask-generating compares. */
19002 enum machine_mode mode;
19007 mode = insn_data[d->icode].operand[1].mode;
19012 type = v16qi_ftype_v16qi_v16qi;
19015 type = v8hi_ftype_v8hi_v8hi;
19018 type = v4si_ftype_v4si_v4si;
19021 type = v2di_ftype_v2di_v2di;
19024 type = v2df_ftype_v2df_v2df;
19027 type = v4sf_ftype_v4sf_v4sf;
19030 type = v8qi_ftype_v8qi_v8qi;
19033 type = v4hi_ftype_v4hi_v4hi;
19036 type = v2si_ftype_v2si_v2si;
19039 type = di_ftype_di_di;
19043 gcc_unreachable ();
19046 /* Override for comparisons. */
19047 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
19048 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
19049 type = v4si_ftype_v4sf_v4sf;
19051 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
19052 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
19053 type = v2di_ftype_v2df_v2df;
19055 if (d->icode == CODE_FOR_vec_pack_sfix_v2df)
19056 type = v4si_ftype_v2df_v2df;
19058 def_builtin_const (d->mask, d->name, type, d->code);
19061 /* Add all builtins that are more or less simple operations on 1 operand. */
19062 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
19064 enum machine_mode mode;
19069 mode = insn_data[d->icode].operand[1].mode;
19074 type = v16qi_ftype_v16qi;
19077 type = v8hi_ftype_v8hi;
19080 type = v4si_ftype_v4si;
19083 type = v2df_ftype_v2df;
19086 type = v4sf_ftype_v4sf;
19089 type = v8qi_ftype_v8qi;
19092 type = v4hi_ftype_v4hi;
19095 type = v2si_ftype_v2si;
19102 def_builtin_const (d->mask, d->name, type, d->code);
19105 /* pcmpestr[im] insns. */
19106 for (i = 0, d = bdesc_pcmpestr;
19107 i < ARRAY_SIZE (bdesc_pcmpestr);
19110 if (d->code == IX86_BUILTIN_PCMPESTRM128)
19111 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
19113 ftype = int_ftype_v16qi_int_v16qi_int_int;
19114 def_builtin_const (d->mask, d->name, ftype, d->code);
19117 /* pcmpistr[im] insns. */
19118 for (i = 0, d = bdesc_pcmpistr;
19119 i < ARRAY_SIZE (bdesc_pcmpistr);
19122 if (d->code == IX86_BUILTIN_PCMPISTRM128)
19123 ftype = v16qi_ftype_v16qi_v16qi_int;
19125 ftype = int_ftype_v16qi_v16qi_int;
19126 def_builtin_const (d->mask, d->name, ftype, d->code);
19129 /* Add the remaining MMX insns with somewhat more complicated types. */
19130 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
19131 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
19132 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
19133 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
19135 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
19136 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
19137 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
19139 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
19140 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
19142 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
19143 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
19145 /* comi/ucomi insns. */
19146 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
19147 if (d->mask == OPTION_MASK_ISA_SSE2)
19148 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
19150 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
19153 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
19154 def_builtin_const (d->mask, d->name, int_ftype_v2di_v2di, d->code);
19156 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
19157 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
19158 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
19160 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
19161 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
19162 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
19163 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
19164 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
19165 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
19166 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
19167 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
19168 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
19169 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
19170 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
19172 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
19174 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
19175 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
19177 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
19178 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
19179 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
19180 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
19182 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
19183 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
19184 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
19185 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
19187 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
19189 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
19191 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
19192 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
19193 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
19194 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
19195 ftype = build_function_type_list (float_type_node,
19198 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtf", ftype, IX86_BUILTIN_RSQRTF);
19199 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
19200 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
19202 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
19204 /* Original 3DNow! */
19205 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
19206 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
19207 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
19208 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
19209 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
19210 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
19211 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
19212 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
19213 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
19214 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
19215 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
19216 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
19217 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
19218 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
19219 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
19220 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
19221 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
19222 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
19223 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
19224 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
19226 /* 3DNow! extension as used in the Athlon CPU. */
19227 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
19228 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
19229 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
19230 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
19231 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
19232 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
19235 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
19237 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
19238 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
19240 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
19241 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
19243 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
19244 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
19245 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
19246 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
19247 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
19249 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
19250 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
19251 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
19252 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
19254 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
19255 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
19257 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
19259 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
19260 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
19262 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
19263 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
19264 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
19265 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
19266 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
19268 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
19270 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
19271 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
19272 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
19273 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
19275 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
19276 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
19277 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
19279 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
19280 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
19281 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
19282 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
19284 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
19285 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
19286 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
19288 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
19289 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
19291 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
19292 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
19294 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
19295 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
19296 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
19297 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
19298 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128);
19299 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128);
19300 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
19302 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
19303 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
19304 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
19305 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
19306 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128);
19307 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128);
19308 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
19310 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
19311 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
19312 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128);
19313 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128);
19315 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
19317 /* Prescott New Instructions. */
19318 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
19319 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
19320 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
19323 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
19324 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int, IX86_BUILTIN_PALIGNR);
19327 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_movntdqa", v2di_ftype_pv2di, IX86_BUILTIN_MOVNTDQA);
19328 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVSXBW128);
19329 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVSXBD128);
19330 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVSXBQ128);
19331 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVSXWD128);
19332 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVSXWQ128);
19333 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovsxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVSXDQ128);
19334 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbw128", v8hi_ftype_v16qi, IX86_BUILTIN_PMOVZXBW128);
19335 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbd128", v4si_ftype_v16qi, IX86_BUILTIN_PMOVZXBD128);
19336 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxbq128", v2di_ftype_v16qi, IX86_BUILTIN_PMOVZXBQ128);
19337 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwd128", v4si_ftype_v8hi, IX86_BUILTIN_PMOVZXWD128);
19338 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxwq128", v2di_ftype_v8hi, IX86_BUILTIN_PMOVZXWQ128);
19339 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmovzxdq128", v2di_ftype_v4si, IX86_BUILTIN_PMOVZXDQ128);
19340 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmuldq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULDQ128);
19342 /* SSE4.1 and SSE5 */
19343 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundpd", v2df_ftype_v2df_int, IX86_BUILTIN_ROUNDPD);
19344 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundps", v4sf_ftype_v4sf_int, IX86_BUILTIN_ROUNDPS);
19345 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundsd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_ROUNDSD);
19346 def_builtin_const (OPTION_MASK_ISA_ROUND, "__builtin_ia32_roundss", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_ROUNDSS);
19349 ftype = build_function_type_list (unsigned_type_node,
19350 unsigned_type_node,
19351 unsigned_char_type_node,
19353 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32qi", ftype, IX86_BUILTIN_CRC32QI);
19354 ftype = build_function_type_list (unsigned_type_node,
19355 unsigned_type_node,
19356 short_unsigned_type_node,
19358 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32hi", ftype, IX86_BUILTIN_CRC32HI);
19359 ftype = build_function_type_list (unsigned_type_node,
19360 unsigned_type_node,
19361 unsigned_type_node,
19363 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32si", ftype, IX86_BUILTIN_CRC32SI);
19364 ftype = build_function_type_list (long_long_unsigned_type_node,
19365 long_long_unsigned_type_node,
19366 long_long_unsigned_type_node,
19368 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32di", ftype, IX86_BUILTIN_CRC32DI);
19370 /* AMDFAM10 SSE4A New built-ins */
19371 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntsd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTSD);
19372 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntss", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTSS);
19373 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrqi", v2di_ftype_v2di_unsigned_unsigned, IX86_BUILTIN_EXTRQI);
19374 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrq", v2di_ftype_v2di_v16qi, IX86_BUILTIN_EXTRQ);
19375 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertqi", v2di_ftype_v2di_v2di_unsigned_unsigned, IX86_BUILTIN_INSERTQI);
19376 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertq", v2di_ftype_v2di_v2di, IX86_BUILTIN_INSERTQ);
19378 /* Access to the vec_init patterns. */
19379 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
19380 integer_type_node, NULL_TREE);
19381 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
19383 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
19384 short_integer_type_node,
19385 short_integer_type_node,
19386 short_integer_type_node, NULL_TREE);
19387 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
19389 ftype = build_function_type_list (V8QI_type_node, char_type_node,
19390 char_type_node, char_type_node,
19391 char_type_node, char_type_node,
19392 char_type_node, char_type_node,
19393 char_type_node, NULL_TREE);
19394 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
19396 /* Access to the vec_extract patterns. */
19397 ftype = build_function_type_list (double_type_node, V2DF_type_node,
19398 integer_type_node, NULL_TREE);
19399 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
19401 ftype = build_function_type_list (long_long_integer_type_node,
19402 V2DI_type_node, integer_type_node,
19404 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
19406 ftype = build_function_type_list (float_type_node, V4SF_type_node,
19407 integer_type_node, NULL_TREE);
19408 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
19410 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
19411 integer_type_node, NULL_TREE);
19412 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
19414 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
19415 integer_type_node, NULL_TREE);
19416 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
19418 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
19419 integer_type_node, NULL_TREE);
19420 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
19422 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
19423 integer_type_node, NULL_TREE);
19424 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
19426 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
19427 integer_type_node, NULL_TREE);
19428 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
19430 /* Access to the vec_set patterns. */
19431 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
19433 integer_type_node, NULL_TREE);
19434 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
19436 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
19438 integer_type_node, NULL_TREE);
19439 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
19441 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
19443 integer_type_node, NULL_TREE);
19444 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
19446 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
19448 integer_type_node, NULL_TREE);
19449 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
19451 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
19453 integer_type_node, NULL_TREE);
19454 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
19456 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
19458 integer_type_node, NULL_TREE);
19459 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
19461 /* Add SSE5 multi-arg argument instructions */
19462 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
19464 tree mtype = NULL_TREE;
19469 switch ((enum multi_arg_type)d->flag)
19471 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
19472 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
19473 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
19474 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
19475 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
19476 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
19477 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
19478 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
19479 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
19480 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
19481 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
19482 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
19483 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
19484 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
19485 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
19486 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
19487 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
19488 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
19489 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
19490 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
19491 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
19492 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
19493 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
19494 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
19495 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
19496 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
19497 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
19498 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
19499 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
19500 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
19501 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
19502 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
19503 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
19504 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
19505 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
19506 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
19507 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
19508 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
19509 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
19510 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
19511 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
19512 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
19513 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
19514 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
19515 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
19516 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
19517 case MULTI_ARG_UNKNOWN:
19519 gcc_unreachable ();
19523 def_builtin_const (d->mask, d->name, mtype, d->code);
19528 ix86_init_builtins (void)
19531 ix86_init_mmx_sse_builtins ();
19534 /* Errors in the source file can cause expand_expr to return const0_rtx
19535 where we expect a vector. To avoid crashing, use one of the vector
19536 clear instructions. */
19538 safe_vector_operand (rtx x, enum machine_mode mode)
19540 if (x == const0_rtx)
19541 x = CONST0_RTX (mode);
19545 /* Subroutine of ix86_expand_builtin to take care of SSE insns with
19546 4 operands. The third argument must be a constant smaller than 8
19550 ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp,
19554 tree arg0 = CALL_EXPR_ARG (exp, 0);
19555 tree arg1 = CALL_EXPR_ARG (exp, 1);
19556 tree arg2 = CALL_EXPR_ARG (exp, 2);
19557 rtx op0 = expand_normal (arg0);
19558 rtx op1 = expand_normal (arg1);
19559 rtx op2 = expand_normal (arg2);
19560 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19561 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
19562 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
19563 enum machine_mode mode3 = insn_data[icode].operand[3].mode;
19565 if (VECTOR_MODE_P (mode1))
19566 op0 = safe_vector_operand (op0, mode1);
19567 if (VECTOR_MODE_P (mode2))
19568 op1 = safe_vector_operand (op1, mode2);
19569 if (VECTOR_MODE_P (mode3))
19570 op2 = safe_vector_operand (op2, mode3);
19574 || GET_MODE (target) != tmode
19575 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19576 target = gen_reg_rtx (tmode);
19578 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19579 op0 = copy_to_mode_reg (mode1, op0);
19580 if ((optimize && !register_operand (op1, mode2))
19581 || !(*insn_data[icode].operand[2].predicate) (op1, mode2))
19582 op1 = copy_to_mode_reg (mode2, op1);
19584 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19587 case CODE_FOR_sse4_1_blendvpd:
19588 case CODE_FOR_sse4_1_blendvps:
19589 case CODE_FOR_sse4_1_pblendvb:
19590 op2 = copy_to_mode_reg (mode3, op2);
19593 case CODE_FOR_sse4_1_roundsd:
19594 case CODE_FOR_sse4_1_roundss:
19595 error ("the third argument must be a 4-bit immediate");
19599 error ("the third argument must be an 8-bit immediate");
19603 pat = GEN_FCN (icode) (target, op0, op1, op2);
19610 /* Subroutine of ix86_expand_builtin to take care of crc32 insns. */
19613 ix86_expand_crc32 (enum insn_code icode, tree exp, rtx target)
19616 tree arg0 = CALL_EXPR_ARG (exp, 0);
19617 tree arg1 = CALL_EXPR_ARG (exp, 1);
19618 rtx op0 = expand_normal (arg0);
19619 rtx op1 = expand_normal (arg1);
19620 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19621 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19622 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19626 || GET_MODE (target) != tmode
19627 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19628 target = gen_reg_rtx (tmode);
19630 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
19631 op0 = copy_to_mode_reg (mode0, op0);
19632 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
19634 op1 = copy_to_reg (op1);
19635 op1 = simplify_gen_subreg (mode1, op1, GET_MODE (op1), 0);
19638 pat = GEN_FCN (icode) (target, op0, op1);
19645 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
19648 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
19651 tree arg0 = CALL_EXPR_ARG (exp, 0);
19652 tree arg1 = CALL_EXPR_ARG (exp, 1);
19653 rtx op0 = expand_normal (arg0);
19654 rtx op1 = expand_normal (arg1);
19655 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19656 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19657 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19659 if (VECTOR_MODE_P (mode0))
19660 op0 = safe_vector_operand (op0, mode0);
19661 if (VECTOR_MODE_P (mode1))
19662 op1 = safe_vector_operand (op1, mode1);
19664 if (optimize || !target
19665 || GET_MODE (target) != tmode
19666 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19667 target = gen_reg_rtx (tmode);
19669 if (GET_MODE (op1) == SImode && mode1 == TImode)
19671 rtx x = gen_reg_rtx (V4SImode);
19672 emit_insn (gen_sse2_loadd (x, op1));
19673 op1 = gen_lowpart (TImode, x);
19676 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
19677 op0 = copy_to_mode_reg (mode0, op0);
19678 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
19679 op1 = copy_to_mode_reg (mode1, op1);
19681 /* ??? Using ix86_fixup_binary_operands is problematic when
19682 we've got mismatched modes. Fake it. */
19688 if (tmode == mode0 && tmode == mode1)
19690 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
19694 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
19696 op0 = force_reg (mode0, op0);
19697 op1 = force_reg (mode1, op1);
19698 target = gen_reg_rtx (tmode);
19701 pat = GEN_FCN (icode) (target, op0, op1);
19708 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
19711 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
19712 enum multi_arg_type m_type,
19713 enum insn_code sub_code)
19718 bool comparison_p = false;
19720 bool last_arg_constant = false;
19721 int num_memory = 0;
19724 enum machine_mode mode;
19727 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19731 case MULTI_ARG_3_SF:
19732 case MULTI_ARG_3_DF:
19733 case MULTI_ARG_3_DI:
19734 case MULTI_ARG_3_SI:
19735 case MULTI_ARG_3_SI_DI:
19736 case MULTI_ARG_3_HI:
19737 case MULTI_ARG_3_HI_SI:
19738 case MULTI_ARG_3_QI:
19739 case MULTI_ARG_3_PERMPS:
19740 case MULTI_ARG_3_PERMPD:
19744 case MULTI_ARG_2_SF:
19745 case MULTI_ARG_2_DF:
19746 case MULTI_ARG_2_DI:
19747 case MULTI_ARG_2_SI:
19748 case MULTI_ARG_2_HI:
19749 case MULTI_ARG_2_QI:
19753 case MULTI_ARG_2_DI_IMM:
19754 case MULTI_ARG_2_SI_IMM:
19755 case MULTI_ARG_2_HI_IMM:
19756 case MULTI_ARG_2_QI_IMM:
19758 last_arg_constant = true;
19761 case MULTI_ARG_1_SF:
19762 case MULTI_ARG_1_DF:
19763 case MULTI_ARG_1_DI:
19764 case MULTI_ARG_1_SI:
19765 case MULTI_ARG_1_HI:
19766 case MULTI_ARG_1_QI:
19767 case MULTI_ARG_1_SI_DI:
19768 case MULTI_ARG_1_HI_DI:
19769 case MULTI_ARG_1_HI_SI:
19770 case MULTI_ARG_1_QI_DI:
19771 case MULTI_ARG_1_QI_SI:
19772 case MULTI_ARG_1_QI_HI:
19773 case MULTI_ARG_1_PH2PS:
19774 case MULTI_ARG_1_PS2PH:
19778 case MULTI_ARG_2_SF_CMP:
19779 case MULTI_ARG_2_DF_CMP:
19780 case MULTI_ARG_2_DI_CMP:
19781 case MULTI_ARG_2_SI_CMP:
19782 case MULTI_ARG_2_HI_CMP:
19783 case MULTI_ARG_2_QI_CMP:
19785 comparison_p = true;
19788 case MULTI_ARG_2_SF_TF:
19789 case MULTI_ARG_2_DF_TF:
19790 case MULTI_ARG_2_DI_TF:
19791 case MULTI_ARG_2_SI_TF:
19792 case MULTI_ARG_2_HI_TF:
19793 case MULTI_ARG_2_QI_TF:
19798 case MULTI_ARG_UNKNOWN:
19800 gcc_unreachable ();
19803 if (optimize || !target
19804 || GET_MODE (target) != tmode
19805 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19806 target = gen_reg_rtx (tmode);
19808 gcc_assert (nargs <= 4);
19810 for (i = 0; i < nargs; i++)
19812 tree arg = CALL_EXPR_ARG (exp, i);
19813 rtx op = expand_normal (arg);
19814 int adjust = (comparison_p) ? 1 : 0;
19815 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
19817 if (last_arg_constant && i == nargs-1)
19819 if (GET_CODE (op) != CONST_INT)
19821 error ("last argument must be an immediate");
19822 return gen_reg_rtx (tmode);
19827 if (VECTOR_MODE_P (mode))
19828 op = safe_vector_operand (op, mode);
19830 /* If we aren't optimizing, only allow one memory operand to be
19832 if (memory_operand (op, mode))
19835 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
19838 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
19840 op = force_reg (mode, op);
19844 args[i].mode = mode;
19850 pat = GEN_FCN (icode) (target, args[0].op);
19855 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
19856 GEN_INT ((int)sub_code));
19857 else if (! comparison_p)
19858 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
19861 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
19865 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
19870 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
19874 gcc_unreachable ();
19884 /* Subroutine of ix86_expand_builtin to take care of stores. */
19887 ix86_expand_store_builtin (enum insn_code icode, tree exp)
19890 tree arg0 = CALL_EXPR_ARG (exp, 0);
19891 tree arg1 = CALL_EXPR_ARG (exp, 1);
19892 rtx op0 = expand_normal (arg0);
19893 rtx op1 = expand_normal (arg1);
19894 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
19895 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
19897 if (VECTOR_MODE_P (mode1))
19898 op1 = safe_vector_operand (op1, mode1);
19900 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
19901 op1 = copy_to_mode_reg (mode1, op1);
19903 pat = GEN_FCN (icode) (op0, op1);
19909 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
19912 ix86_expand_unop_builtin (enum insn_code icode, tree exp,
19913 rtx target, int do_load)
19916 tree arg0 = CALL_EXPR_ARG (exp, 0);
19917 rtx op0 = expand_normal (arg0);
19918 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19919 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19921 if (optimize || !target
19922 || GET_MODE (target) != tmode
19923 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19924 target = gen_reg_rtx (tmode);
19926 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
19929 if (VECTOR_MODE_P (mode0))
19930 op0 = safe_vector_operand (op0, mode0);
19932 if ((optimize && !register_operand (op0, mode0))
19933 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
19934 op0 = copy_to_mode_reg (mode0, op0);
19939 case CODE_FOR_sse4_1_roundpd:
19940 case CODE_FOR_sse4_1_roundps:
19942 tree arg1 = CALL_EXPR_ARG (exp, 1);
19943 rtx op1 = expand_normal (arg1);
19944 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
19946 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
19948 error ("the second argument must be a 4-bit immediate");
19951 pat = GEN_FCN (icode) (target, op0, op1);
19955 pat = GEN_FCN (icode) (target, op0);
19965 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
19966 sqrtss, rsqrtss, rcpss. */
19969 ix86_expand_unop1_builtin (enum insn_code icode, tree exp, rtx target)
19972 tree arg0 = CALL_EXPR_ARG (exp, 0);
19973 rtx op1, op0 = expand_normal (arg0);
19974 enum machine_mode tmode = insn_data[icode].operand[0].mode;
19975 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
19977 if (optimize || !target
19978 || GET_MODE (target) != tmode
19979 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19980 target = gen_reg_rtx (tmode);
19982 if (VECTOR_MODE_P (mode0))
19983 op0 = safe_vector_operand (op0, mode0);
19985 if ((optimize && !register_operand (op0, mode0))
19986 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
19987 op0 = copy_to_mode_reg (mode0, op0);
19990 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
19991 op1 = copy_to_mode_reg (mode0, op1);
19993 pat = GEN_FCN (icode) (target, op0, op1);
20000 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
20003 ix86_expand_sse_compare (const struct builtin_description *d, tree exp,
20007 tree arg0 = CALL_EXPR_ARG (exp, 0);
20008 tree arg1 = CALL_EXPR_ARG (exp, 1);
20009 rtx op0 = expand_normal (arg0);
20010 rtx op1 = expand_normal (arg1);
20012 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
20013 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
20014 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
20015 enum rtx_code comparison = d->comparison;
20017 if (VECTOR_MODE_P (mode0))
20018 op0 = safe_vector_operand (op0, mode0);
20019 if (VECTOR_MODE_P (mode1))
20020 op1 = safe_vector_operand (op1, mode1);
20022 /* Swap operands if we have a comparison that isn't available in
20024 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20026 rtx tmp = gen_reg_rtx (mode1);
20027 emit_move_insn (tmp, op1);
20032 if (optimize || !target
20033 || GET_MODE (target) != tmode
20034 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
20035 target = gen_reg_rtx (tmode);
20037 if ((optimize && !register_operand (op0, mode0))
20038 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
20039 op0 = copy_to_mode_reg (mode0, op0);
20040 if ((optimize && !register_operand (op1, mode1))
20041 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
20042 op1 = copy_to_mode_reg (mode1, op1);
20044 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
20045 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
20052 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
20055 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
20059 tree arg0 = CALL_EXPR_ARG (exp, 0);
20060 tree arg1 = CALL_EXPR_ARG (exp, 1);
20061 rtx op0 = expand_normal (arg0);
20062 rtx op1 = expand_normal (arg1);
20063 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20064 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20065 enum rtx_code comparison = d->comparison;
20067 if (VECTOR_MODE_P (mode0))
20068 op0 = safe_vector_operand (op0, mode0);
20069 if (VECTOR_MODE_P (mode1))
20070 op1 = safe_vector_operand (op1, mode1);
20072 /* Swap operands if we have a comparison that isn't available in
20074 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20081 target = gen_reg_rtx (SImode);
20082 emit_move_insn (target, const0_rtx);
20083 target = gen_rtx_SUBREG (QImode, target, 0);
20085 if ((optimize && !register_operand (op0, mode0))
20086 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20087 op0 = copy_to_mode_reg (mode0, op0);
20088 if ((optimize && !register_operand (op1, mode1))
20089 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20090 op1 = copy_to_mode_reg (mode1, op1);
20092 pat = GEN_FCN (d->icode) (op0, op1);
20096 emit_insn (gen_rtx_SET (VOIDmode,
20097 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20098 gen_rtx_fmt_ee (comparison, QImode,
20102 return SUBREG_REG (target);
20105 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
20108 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
20112 tree arg0 = CALL_EXPR_ARG (exp, 0);
20113 tree arg1 = CALL_EXPR_ARG (exp, 1);
20114 rtx op0 = expand_normal (arg0);
20115 rtx op1 = expand_normal (arg1);
20116 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20117 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20118 enum rtx_code comparison = d->comparison;
20120 if (VECTOR_MODE_P (mode0))
20121 op0 = safe_vector_operand (op0, mode0);
20122 if (VECTOR_MODE_P (mode1))
20123 op1 = safe_vector_operand (op1, mode1);
20125 target = gen_reg_rtx (SImode);
20126 emit_move_insn (target, const0_rtx);
20127 target = gen_rtx_SUBREG (QImode, target, 0);
20129 if ((optimize && !register_operand (op0, mode0))
20130 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20131 op0 = copy_to_mode_reg (mode0, op0);
20132 if ((optimize && !register_operand (op1, mode1))
20133 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20134 op1 = copy_to_mode_reg (mode1, op1);
20136 pat = GEN_FCN (d->icode) (op0, op1);
20140 emit_insn (gen_rtx_SET (VOIDmode,
20141 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20142 gen_rtx_fmt_ee (comparison, QImode,
20146 return SUBREG_REG (target);
20149 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
20152 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
20153 tree exp, rtx target)
20156 tree arg0 = CALL_EXPR_ARG (exp, 0);
20157 tree arg1 = CALL_EXPR_ARG (exp, 1);
20158 tree arg2 = CALL_EXPR_ARG (exp, 2);
20159 tree arg3 = CALL_EXPR_ARG (exp, 3);
20160 tree arg4 = CALL_EXPR_ARG (exp, 4);
20161 rtx scratch0, scratch1;
20162 rtx op0 = expand_normal (arg0);
20163 rtx op1 = expand_normal (arg1);
20164 rtx op2 = expand_normal (arg2);
20165 rtx op3 = expand_normal (arg3);
20166 rtx op4 = expand_normal (arg4);
20167 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
20169 tmode0 = insn_data[d->icode].operand[0].mode;
20170 tmode1 = insn_data[d->icode].operand[1].mode;
20171 modev2 = insn_data[d->icode].operand[2].mode;
20172 modei3 = insn_data[d->icode].operand[3].mode;
20173 modev4 = insn_data[d->icode].operand[4].mode;
20174 modei5 = insn_data[d->icode].operand[5].mode;
20175 modeimm = insn_data[d->icode].operand[6].mode;
20177 if (VECTOR_MODE_P (modev2))
20178 op0 = safe_vector_operand (op0, modev2);
20179 if (VECTOR_MODE_P (modev4))
20180 op2 = safe_vector_operand (op2, modev4);
20182 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20183 op0 = copy_to_mode_reg (modev2, op0);
20184 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
20185 op1 = copy_to_mode_reg (modei3, op1);
20186 if ((optimize && !register_operand (op2, modev4))
20187 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
20188 op2 = copy_to_mode_reg (modev4, op2);
20189 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
20190 op3 = copy_to_mode_reg (modei5, op3);
20192 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
20194 error ("the fifth argument must be a 8-bit immediate");
20198 if (d->code == IX86_BUILTIN_PCMPESTRI128)
20200 if (optimize || !target
20201 || GET_MODE (target) != tmode0
20202 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20203 target = gen_reg_rtx (tmode0);
20205 scratch1 = gen_reg_rtx (tmode1);
20207 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
20209 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
20211 if (optimize || !target
20212 || GET_MODE (target) != tmode1
20213 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20214 target = gen_reg_rtx (tmode1);
20216 scratch0 = gen_reg_rtx (tmode0);
20218 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
20222 gcc_assert (d->flag);
20224 scratch0 = gen_reg_rtx (tmode0);
20225 scratch1 = gen_reg_rtx (tmode1);
20227 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
20237 target = gen_reg_rtx (SImode);
20238 emit_move_insn (target, const0_rtx);
20239 target = gen_rtx_SUBREG (QImode, target, 0);
20242 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20243 gen_rtx_fmt_ee (EQ, QImode,
20244 gen_rtx_REG ((enum machine_mode) d->flag,
20247 return SUBREG_REG (target);
20254 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
20257 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
20258 tree exp, rtx target)
20261 tree arg0 = CALL_EXPR_ARG (exp, 0);
20262 tree arg1 = CALL_EXPR_ARG (exp, 1);
20263 tree arg2 = CALL_EXPR_ARG (exp, 2);
20264 rtx scratch0, scratch1;
20265 rtx op0 = expand_normal (arg0);
20266 rtx op1 = expand_normal (arg1);
20267 rtx op2 = expand_normal (arg2);
20268 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
20270 tmode0 = insn_data[d->icode].operand[0].mode;
20271 tmode1 = insn_data[d->icode].operand[1].mode;
20272 modev2 = insn_data[d->icode].operand[2].mode;
20273 modev3 = insn_data[d->icode].operand[3].mode;
20274 modeimm = insn_data[d->icode].operand[4].mode;
20276 if (VECTOR_MODE_P (modev2))
20277 op0 = safe_vector_operand (op0, modev2);
20278 if (VECTOR_MODE_P (modev3))
20279 op1 = safe_vector_operand (op1, modev3);
20281 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20282 op0 = copy_to_mode_reg (modev2, op0);
20283 if ((optimize && !register_operand (op1, modev3))
20284 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
20285 op1 = copy_to_mode_reg (modev3, op1);
20287 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
20289 error ("the third argument must be a 8-bit immediate");
20293 if (d->code == IX86_BUILTIN_PCMPISTRI128)
20295 if (optimize || !target
20296 || GET_MODE (target) != tmode0
20297 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20298 target = gen_reg_rtx (tmode0);
20300 scratch1 = gen_reg_rtx (tmode1);
20302 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
20304 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
20306 if (optimize || !target
20307 || GET_MODE (target) != tmode1
20308 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20309 target = gen_reg_rtx (tmode1);
20311 scratch0 = gen_reg_rtx (tmode0);
20313 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
20317 gcc_assert (d->flag);
20319 scratch0 = gen_reg_rtx (tmode0);
20320 scratch1 = gen_reg_rtx (tmode1);
20322 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
20332 target = gen_reg_rtx (SImode);
20333 emit_move_insn (target, const0_rtx);
20334 target = gen_rtx_SUBREG (QImode, target, 0);
20337 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20338 gen_rtx_fmt_ee (EQ, QImode,
20339 gen_rtx_REG ((enum machine_mode) d->flag,
20342 return SUBREG_REG (target);
20348 /* Return the integer constant in ARG. Constrain it to be in the range
20349 of the subparts of VEC_TYPE; issue an error if not. */
20352 get_element_number (tree vec_type, tree arg)
20354 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
20356 if (!host_integerp (arg, 1)
20357 || (elt = tree_low_cst (arg, 1), elt > max))
20359 error ("selector must be an integer constant in the range 0..%wi", max);
20366 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20367 ix86_expand_vector_init. We DO have language-level syntax for this, in
20368 the form of (type){ init-list }. Except that since we can't place emms
20369 instructions from inside the compiler, we can't allow the use of MMX
20370 registers unless the user explicitly asks for it. So we do *not* define
20371 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
20372 we have builtins invoked by mmintrin.h that gives us license to emit
20373 these sorts of instructions. */
20376 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
20378 enum machine_mode tmode = TYPE_MODE (type);
20379 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
20380 int i, n_elt = GET_MODE_NUNITS (tmode);
20381 rtvec v = rtvec_alloc (n_elt);
20383 gcc_assert (VECTOR_MODE_P (tmode));
20384 gcc_assert (call_expr_nargs (exp) == n_elt);
20386 for (i = 0; i < n_elt; ++i)
20388 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
20389 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
20392 if (!target || !register_operand (target, tmode))
20393 target = gen_reg_rtx (tmode);
20395 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
20399 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20400 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
20401 had a language-level syntax for referencing vector elements. */
20404 ix86_expand_vec_ext_builtin (tree exp, rtx target)
20406 enum machine_mode tmode, mode0;
20411 arg0 = CALL_EXPR_ARG (exp, 0);
20412 arg1 = CALL_EXPR_ARG (exp, 1);
20414 op0 = expand_normal (arg0);
20415 elt = get_element_number (TREE_TYPE (arg0), arg1);
20417 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20418 mode0 = TYPE_MODE (TREE_TYPE (arg0));
20419 gcc_assert (VECTOR_MODE_P (mode0));
20421 op0 = force_reg (mode0, op0);
20423 if (optimize || !target || !register_operand (target, tmode))
20424 target = gen_reg_rtx (tmode);
20426 ix86_expand_vector_extract (true, target, op0, elt);
20431 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20432 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
20433 a language-level syntax for referencing vector elements. */
20436 ix86_expand_vec_set_builtin (tree exp)
20438 enum machine_mode tmode, mode1;
20439 tree arg0, arg1, arg2;
20441 rtx op0, op1, target;
20443 arg0 = CALL_EXPR_ARG (exp, 0);
20444 arg1 = CALL_EXPR_ARG (exp, 1);
20445 arg2 = CALL_EXPR_ARG (exp, 2);
20447 tmode = TYPE_MODE (TREE_TYPE (arg0));
20448 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20449 gcc_assert (VECTOR_MODE_P (tmode));
20451 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
20452 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
20453 elt = get_element_number (TREE_TYPE (arg0), arg2);
20455 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
20456 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
20458 op0 = force_reg (tmode, op0);
20459 op1 = force_reg (mode1, op1);
20461 /* OP0 is the source of these builtin functions and shouldn't be
20462 modified. Create a copy, use it and return it as target. */
20463 target = gen_reg_rtx (tmode);
20464 emit_move_insn (target, op0);
20465 ix86_expand_vector_set (true, target, op1, elt);
20470 /* Expand an expression EXP that calls a built-in function,
20471 with result going to TARGET if that's convenient
20472 (and in mode MODE if that's convenient).
20473 SUBTARGET may be used as the target for computing one of EXP's operands.
20474 IGNORE is nonzero if the value is to be ignored. */
20477 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
20478 enum machine_mode mode ATTRIBUTE_UNUSED,
20479 int ignore ATTRIBUTE_UNUSED)
20481 const struct builtin_description *d;
20483 enum insn_code icode;
20484 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
20485 tree arg0, arg1, arg2, arg3;
20486 rtx op0, op1, op2, op3, pat;
20487 enum machine_mode tmode, mode0, mode1, mode2, mode3, mode4;
20488 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
20492 case IX86_BUILTIN_EMMS:
20493 emit_insn (gen_mmx_emms ());
20496 case IX86_BUILTIN_SFENCE:
20497 emit_insn (gen_sse_sfence ());
20500 case IX86_BUILTIN_MASKMOVQ:
20501 case IX86_BUILTIN_MASKMOVDQU:
20502 icode = (fcode == IX86_BUILTIN_MASKMOVQ
20503 ? CODE_FOR_mmx_maskmovq
20504 : CODE_FOR_sse2_maskmovdqu);
20505 /* Note the arg order is different from the operand order. */
20506 arg1 = CALL_EXPR_ARG (exp, 0);
20507 arg2 = CALL_EXPR_ARG (exp, 1);
20508 arg0 = CALL_EXPR_ARG (exp, 2);
20509 op0 = expand_normal (arg0);
20510 op1 = expand_normal (arg1);
20511 op2 = expand_normal (arg2);
20512 mode0 = insn_data[icode].operand[0].mode;
20513 mode1 = insn_data[icode].operand[1].mode;
20514 mode2 = insn_data[icode].operand[2].mode;
20516 op0 = force_reg (Pmode, op0);
20517 op0 = gen_rtx_MEM (mode1, op0);
20519 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
20520 op0 = copy_to_mode_reg (mode0, op0);
20521 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
20522 op1 = copy_to_mode_reg (mode1, op1);
20523 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
20524 op2 = copy_to_mode_reg (mode2, op2);
20525 pat = GEN_FCN (icode) (op0, op1, op2);
20531 case IX86_BUILTIN_RSQRTF:
20532 return ix86_expand_unop1_builtin (CODE_FOR_rsqrtsf2, exp, target);
20534 case IX86_BUILTIN_SQRTSS:
20535 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, exp, target);
20536 case IX86_BUILTIN_RSQRTSS:
20537 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, exp, target);
20538 case IX86_BUILTIN_RCPSS:
20539 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, exp, target);
20541 case IX86_BUILTIN_LOADUPS:
20542 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, exp, target, 1);
20544 case IX86_BUILTIN_STOREUPS:
20545 return ix86_expand_store_builtin (CODE_FOR_sse_movups, exp);
20547 case IX86_BUILTIN_LOADHPS:
20548 case IX86_BUILTIN_LOADLPS:
20549 case IX86_BUILTIN_LOADHPD:
20550 case IX86_BUILTIN_LOADLPD:
20551 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
20552 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
20553 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
20554 : CODE_FOR_sse2_loadlpd);
20555 arg0 = CALL_EXPR_ARG (exp, 0);
20556 arg1 = CALL_EXPR_ARG (exp, 1);
20557 op0 = expand_normal (arg0);
20558 op1 = expand_normal (arg1);
20559 tmode = insn_data[icode].operand[0].mode;
20560 mode0 = insn_data[icode].operand[1].mode;
20561 mode1 = insn_data[icode].operand[2].mode;
20563 op0 = force_reg (mode0, op0);
20564 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
20565 if (optimize || target == 0
20566 || GET_MODE (target) != tmode
20567 || !register_operand (target, tmode))
20568 target = gen_reg_rtx (tmode);
20569 pat = GEN_FCN (icode) (target, op0, op1);
20575 case IX86_BUILTIN_STOREHPS:
20576 case IX86_BUILTIN_STORELPS:
20577 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
20578 : CODE_FOR_sse_storelps);
20579 arg0 = CALL_EXPR_ARG (exp, 0);
20580 arg1 = CALL_EXPR_ARG (exp, 1);
20581 op0 = expand_normal (arg0);
20582 op1 = expand_normal (arg1);
20583 mode0 = insn_data[icode].operand[0].mode;
20584 mode1 = insn_data[icode].operand[1].mode;
20586 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20587 op1 = force_reg (mode1, op1);
20589 pat = GEN_FCN (icode) (op0, op1);
20595 case IX86_BUILTIN_MOVNTPS:
20596 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, exp);
20597 case IX86_BUILTIN_MOVNTQ:
20598 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, exp);
20600 case IX86_BUILTIN_LDMXCSR:
20601 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
20602 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
20603 emit_move_insn (target, op0);
20604 emit_insn (gen_sse_ldmxcsr (target));
20607 case IX86_BUILTIN_STMXCSR:
20608 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
20609 emit_insn (gen_sse_stmxcsr (target));
20610 return copy_to_mode_reg (SImode, target);
20612 case IX86_BUILTIN_SHUFPS:
20613 case IX86_BUILTIN_SHUFPD:
20614 icode = (fcode == IX86_BUILTIN_SHUFPS
20615 ? CODE_FOR_sse_shufps
20616 : CODE_FOR_sse2_shufpd);
20617 arg0 = CALL_EXPR_ARG (exp, 0);
20618 arg1 = CALL_EXPR_ARG (exp, 1);
20619 arg2 = CALL_EXPR_ARG (exp, 2);
20620 op0 = expand_normal (arg0);
20621 op1 = expand_normal (arg1);
20622 op2 = expand_normal (arg2);
20623 tmode = insn_data[icode].operand[0].mode;
20624 mode0 = insn_data[icode].operand[1].mode;
20625 mode1 = insn_data[icode].operand[2].mode;
20626 mode2 = insn_data[icode].operand[3].mode;
20628 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20629 op0 = copy_to_mode_reg (mode0, op0);
20630 if ((optimize && !register_operand (op1, mode1))
20631 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
20632 op1 = copy_to_mode_reg (mode1, op1);
20633 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
20635 /* @@@ better error message */
20636 error ("mask must be an immediate");
20637 return gen_reg_rtx (tmode);
20639 if (optimize || target == 0
20640 || GET_MODE (target) != tmode
20641 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20642 target = gen_reg_rtx (tmode);
20643 pat = GEN_FCN (icode) (target, op0, op1, op2);
20649 case IX86_BUILTIN_PSHUFW:
20650 case IX86_BUILTIN_PSHUFD:
20651 case IX86_BUILTIN_PSHUFHW:
20652 case IX86_BUILTIN_PSHUFLW:
20653 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
20654 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
20655 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
20656 : CODE_FOR_mmx_pshufw);
20657 arg0 = CALL_EXPR_ARG (exp, 0);
20658 arg1 = CALL_EXPR_ARG (exp, 1);
20659 op0 = expand_normal (arg0);
20660 op1 = expand_normal (arg1);
20661 tmode = insn_data[icode].operand[0].mode;
20662 mode1 = insn_data[icode].operand[1].mode;
20663 mode2 = insn_data[icode].operand[2].mode;
20665 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20666 op0 = copy_to_mode_reg (mode1, op0);
20667 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20669 /* @@@ better error message */
20670 error ("mask must be an immediate");
20674 || GET_MODE (target) != tmode
20675 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20676 target = gen_reg_rtx (tmode);
20677 pat = GEN_FCN (icode) (target, op0, op1);
20683 case IX86_BUILTIN_PSLLW128:
20684 case IX86_BUILTIN_PSLLWI128:
20685 icode = CODE_FOR_ashlv8hi3;
20687 case IX86_BUILTIN_PSLLD128:
20688 case IX86_BUILTIN_PSLLDI128:
20689 icode = CODE_FOR_ashlv4si3;
20691 case IX86_BUILTIN_PSLLQ128:
20692 case IX86_BUILTIN_PSLLQI128:
20693 icode = CODE_FOR_ashlv2di3;
20695 case IX86_BUILTIN_PSRAW128:
20696 case IX86_BUILTIN_PSRAWI128:
20697 icode = CODE_FOR_ashrv8hi3;
20699 case IX86_BUILTIN_PSRAD128:
20700 case IX86_BUILTIN_PSRADI128:
20701 icode = CODE_FOR_ashrv4si3;
20703 case IX86_BUILTIN_PSRLW128:
20704 case IX86_BUILTIN_PSRLWI128:
20705 icode = CODE_FOR_lshrv8hi3;
20707 case IX86_BUILTIN_PSRLD128:
20708 case IX86_BUILTIN_PSRLDI128:
20709 icode = CODE_FOR_lshrv4si3;
20711 case IX86_BUILTIN_PSRLQ128:
20712 case IX86_BUILTIN_PSRLQI128:
20713 icode = CODE_FOR_lshrv2di3;
20716 arg0 = CALL_EXPR_ARG (exp, 0);
20717 arg1 = CALL_EXPR_ARG (exp, 1);
20718 op0 = expand_normal (arg0);
20719 op1 = expand_normal (arg1);
20721 tmode = insn_data[icode].operand[0].mode;
20722 mode1 = insn_data[icode].operand[1].mode;
20724 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20725 op0 = copy_to_reg (op0);
20727 if (!CONST_INT_P (op1))
20728 op1 = simplify_gen_subreg (SImode, op1, GET_MODE (op1), 0);
20730 if (! (*insn_data[icode].operand[2].predicate) (op1, SImode))
20731 op1 = copy_to_reg (op1);
20733 target = gen_reg_rtx (tmode);
20734 pat = GEN_FCN (icode) (target, op0, op1);
20740 case IX86_BUILTIN_PSLLDQI128:
20741 case IX86_BUILTIN_PSRLDQI128:
20742 icode = (fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
20743 : CODE_FOR_sse2_lshrti3);
20744 arg0 = CALL_EXPR_ARG (exp, 0);
20745 arg1 = CALL_EXPR_ARG (exp, 1);
20746 op0 = expand_normal (arg0);
20747 op1 = expand_normal (arg1);
20748 tmode = insn_data[icode].operand[0].mode;
20749 mode1 = insn_data[icode].operand[1].mode;
20750 mode2 = insn_data[icode].operand[2].mode;
20752 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20754 op0 = copy_to_reg (op0);
20755 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
20757 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20759 error ("shift must be an immediate");
20762 target = gen_reg_rtx (V2DImode);
20763 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0),
20770 case IX86_BUILTIN_FEMMS:
20771 emit_insn (gen_mmx_femms ());
20774 case IX86_BUILTIN_PAVGUSB:
20775 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, exp, target);
20777 case IX86_BUILTIN_PF2ID:
20778 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, exp, target, 0);
20780 case IX86_BUILTIN_PFACC:
20781 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, exp, target);
20783 case IX86_BUILTIN_PFADD:
20784 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, exp, target);
20786 case IX86_BUILTIN_PFCMPEQ:
20787 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, exp, target);
20789 case IX86_BUILTIN_PFCMPGE:
20790 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, exp, target);
20792 case IX86_BUILTIN_PFCMPGT:
20793 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, exp, target);
20795 case IX86_BUILTIN_PFMAX:
20796 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, exp, target);
20798 case IX86_BUILTIN_PFMIN:
20799 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, exp, target);
20801 case IX86_BUILTIN_PFMUL:
20802 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, exp, target);
20804 case IX86_BUILTIN_PFRCP:
20805 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, exp, target, 0);
20807 case IX86_BUILTIN_PFRCPIT1:
20808 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, exp, target);
20810 case IX86_BUILTIN_PFRCPIT2:
20811 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, exp, target);
20813 case IX86_BUILTIN_PFRSQIT1:
20814 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, exp, target);
20816 case IX86_BUILTIN_PFRSQRT:
20817 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, exp, target, 0);
20819 case IX86_BUILTIN_PFSUB:
20820 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, exp, target);
20822 case IX86_BUILTIN_PFSUBR:
20823 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, exp, target);
20825 case IX86_BUILTIN_PI2FD:
20826 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, exp, target, 0);
20828 case IX86_BUILTIN_PMULHRW:
20829 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, exp, target);
20831 case IX86_BUILTIN_PF2IW:
20832 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, exp, target, 0);
20834 case IX86_BUILTIN_PFNACC:
20835 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, exp, target);
20837 case IX86_BUILTIN_PFPNACC:
20838 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, exp, target);
20840 case IX86_BUILTIN_PI2FW:
20841 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, exp, target, 0);
20843 case IX86_BUILTIN_PSWAPDSI:
20844 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, exp, target, 0);
20846 case IX86_BUILTIN_PSWAPDSF:
20847 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, exp, target, 0);
20849 case IX86_BUILTIN_SQRTSD:
20850 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, exp, target);
20851 case IX86_BUILTIN_LOADUPD:
20852 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, exp, target, 1);
20853 case IX86_BUILTIN_STOREUPD:
20854 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, exp);
20856 case IX86_BUILTIN_MFENCE:
20857 emit_insn (gen_sse2_mfence ());
20859 case IX86_BUILTIN_LFENCE:
20860 emit_insn (gen_sse2_lfence ());
20863 case IX86_BUILTIN_CLFLUSH:
20864 arg0 = CALL_EXPR_ARG (exp, 0);
20865 op0 = expand_normal (arg0);
20866 icode = CODE_FOR_sse2_clflush;
20867 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
20868 op0 = copy_to_mode_reg (Pmode, op0);
20870 emit_insn (gen_sse2_clflush (op0));
20873 case IX86_BUILTIN_MOVNTPD:
20874 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, exp);
20875 case IX86_BUILTIN_MOVNTDQ:
20876 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, exp);
20877 case IX86_BUILTIN_MOVNTI:
20878 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, exp);
20880 case IX86_BUILTIN_LOADDQU:
20881 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, exp, target, 1);
20882 case IX86_BUILTIN_STOREDQU:
20883 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, exp);
20885 case IX86_BUILTIN_MONITOR:
20886 arg0 = CALL_EXPR_ARG (exp, 0);
20887 arg1 = CALL_EXPR_ARG (exp, 1);
20888 arg2 = CALL_EXPR_ARG (exp, 2);
20889 op0 = expand_normal (arg0);
20890 op1 = expand_normal (arg1);
20891 op2 = expand_normal (arg2);
20893 op0 = copy_to_mode_reg (Pmode, op0);
20895 op1 = copy_to_mode_reg (SImode, op1);
20897 op2 = copy_to_mode_reg (SImode, op2);
20899 emit_insn (gen_sse3_monitor (op0, op1, op2));
20901 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
20904 case IX86_BUILTIN_MWAIT:
20905 arg0 = CALL_EXPR_ARG (exp, 0);
20906 arg1 = CALL_EXPR_ARG (exp, 1);
20907 op0 = expand_normal (arg0);
20908 op1 = expand_normal (arg1);
20910 op0 = copy_to_mode_reg (SImode, op0);
20912 op1 = copy_to_mode_reg (SImode, op1);
20913 emit_insn (gen_sse3_mwait (op0, op1));
20916 case IX86_BUILTIN_LDDQU:
20917 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, exp,
20920 case IX86_BUILTIN_PALIGNR:
20921 case IX86_BUILTIN_PALIGNR128:
20922 if (fcode == IX86_BUILTIN_PALIGNR)
20924 icode = CODE_FOR_ssse3_palignrdi;
20929 icode = CODE_FOR_ssse3_palignrti;
20932 arg0 = CALL_EXPR_ARG (exp, 0);
20933 arg1 = CALL_EXPR_ARG (exp, 1);
20934 arg2 = CALL_EXPR_ARG (exp, 2);
20935 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
20936 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
20937 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
20938 tmode = insn_data[icode].operand[0].mode;
20939 mode1 = insn_data[icode].operand[1].mode;
20940 mode2 = insn_data[icode].operand[2].mode;
20941 mode3 = insn_data[icode].operand[3].mode;
20943 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20945 op0 = copy_to_reg (op0);
20946 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
20948 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20950 op1 = copy_to_reg (op1);
20951 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
20953 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
20955 error ("shift must be an immediate");
20958 target = gen_reg_rtx (mode);
20959 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
20966 case IX86_BUILTIN_MOVNTDQA:
20967 return ix86_expand_unop_builtin (CODE_FOR_sse4_1_movntdqa, exp,
20970 case IX86_BUILTIN_MOVNTSD:
20971 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv2df, exp);
20973 case IX86_BUILTIN_MOVNTSS:
20974 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv4sf, exp);
20976 case IX86_BUILTIN_INSERTQ:
20977 case IX86_BUILTIN_EXTRQ:
20978 icode = (fcode == IX86_BUILTIN_EXTRQ
20979 ? CODE_FOR_sse4a_extrq
20980 : CODE_FOR_sse4a_insertq);
20981 arg0 = CALL_EXPR_ARG (exp, 0);
20982 arg1 = CALL_EXPR_ARG (exp, 1);
20983 op0 = expand_normal (arg0);
20984 op1 = expand_normal (arg1);
20985 tmode = insn_data[icode].operand[0].mode;
20986 mode1 = insn_data[icode].operand[1].mode;
20987 mode2 = insn_data[icode].operand[2].mode;
20988 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20989 op0 = copy_to_mode_reg (mode1, op0);
20990 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
20991 op1 = copy_to_mode_reg (mode2, op1);
20992 if (optimize || target == 0
20993 || GET_MODE (target) != tmode
20994 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20995 target = gen_reg_rtx (tmode);
20996 pat = GEN_FCN (icode) (target, op0, op1);
21002 case IX86_BUILTIN_EXTRQI:
21003 icode = CODE_FOR_sse4a_extrqi;
21004 arg0 = CALL_EXPR_ARG (exp, 0);
21005 arg1 = CALL_EXPR_ARG (exp, 1);
21006 arg2 = CALL_EXPR_ARG (exp, 2);
21007 op0 = expand_normal (arg0);
21008 op1 = expand_normal (arg1);
21009 op2 = expand_normal (arg2);
21010 tmode = insn_data[icode].operand[0].mode;
21011 mode1 = insn_data[icode].operand[1].mode;
21012 mode2 = insn_data[icode].operand[2].mode;
21013 mode3 = insn_data[icode].operand[3].mode;
21014 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21015 op0 = copy_to_mode_reg (mode1, op0);
21016 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21018 error ("index mask must be an immediate");
21019 return gen_reg_rtx (tmode);
21021 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21023 error ("length mask must be an immediate");
21024 return gen_reg_rtx (tmode);
21026 if (optimize || target == 0
21027 || GET_MODE (target) != tmode
21028 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21029 target = gen_reg_rtx (tmode);
21030 pat = GEN_FCN (icode) (target, op0, op1, op2);
21036 case IX86_BUILTIN_INSERTQI:
21037 icode = CODE_FOR_sse4a_insertqi;
21038 arg0 = CALL_EXPR_ARG (exp, 0);
21039 arg1 = CALL_EXPR_ARG (exp, 1);
21040 arg2 = CALL_EXPR_ARG (exp, 2);
21041 arg3 = CALL_EXPR_ARG (exp, 3);
21042 op0 = expand_normal (arg0);
21043 op1 = expand_normal (arg1);
21044 op2 = expand_normal (arg2);
21045 op3 = expand_normal (arg3);
21046 tmode = insn_data[icode].operand[0].mode;
21047 mode1 = insn_data[icode].operand[1].mode;
21048 mode2 = insn_data[icode].operand[2].mode;
21049 mode3 = insn_data[icode].operand[3].mode;
21050 mode4 = insn_data[icode].operand[4].mode;
21052 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21053 op0 = copy_to_mode_reg (mode1, op0);
21055 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21056 op1 = copy_to_mode_reg (mode2, op1);
21058 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21060 error ("index mask must be an immediate");
21061 return gen_reg_rtx (tmode);
21063 if (! (*insn_data[icode].operand[4].predicate) (op3, mode4))
21065 error ("length mask must be an immediate");
21066 return gen_reg_rtx (tmode);
21068 if (optimize || target == 0
21069 || GET_MODE (target) != tmode
21070 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21071 target = gen_reg_rtx (tmode);
21072 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
21078 case IX86_BUILTIN_VEC_INIT_V2SI:
21079 case IX86_BUILTIN_VEC_INIT_V4HI:
21080 case IX86_BUILTIN_VEC_INIT_V8QI:
21081 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
21083 case IX86_BUILTIN_VEC_EXT_V2DF:
21084 case IX86_BUILTIN_VEC_EXT_V2DI:
21085 case IX86_BUILTIN_VEC_EXT_V4SF:
21086 case IX86_BUILTIN_VEC_EXT_V4SI:
21087 case IX86_BUILTIN_VEC_EXT_V8HI:
21088 case IX86_BUILTIN_VEC_EXT_V2SI:
21089 case IX86_BUILTIN_VEC_EXT_V4HI:
21090 case IX86_BUILTIN_VEC_EXT_V16QI:
21091 return ix86_expand_vec_ext_builtin (exp, target);
21093 case IX86_BUILTIN_VEC_SET_V2DI:
21094 case IX86_BUILTIN_VEC_SET_V4SF:
21095 case IX86_BUILTIN_VEC_SET_V4SI:
21096 case IX86_BUILTIN_VEC_SET_V8HI:
21097 case IX86_BUILTIN_VEC_SET_V4HI:
21098 case IX86_BUILTIN_VEC_SET_V16QI:
21099 return ix86_expand_vec_set_builtin (exp);
21101 case IX86_BUILTIN_INFQ:
21103 REAL_VALUE_TYPE inf;
21107 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
21109 tmp = validize_mem (force_const_mem (mode, tmp));
21112 target = gen_reg_rtx (mode);
21114 emit_move_insn (target, tmp);
21118 case IX86_BUILTIN_FABSQ:
21119 return ix86_expand_unop_builtin (CODE_FOR_abstf2, exp, target, 0);
21121 case IX86_BUILTIN_COPYSIGNQ:
21122 return ix86_expand_binop_builtin (CODE_FOR_copysigntf3, exp, target);
21128 for (i = 0, d = bdesc_sse_3arg;
21129 i < ARRAY_SIZE (bdesc_sse_3arg);
21131 if (d->code == fcode)
21132 return ix86_expand_sse_4_operands_builtin (d->icode, exp,
21135 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
21136 if (d->code == fcode)
21138 /* Compares are treated specially. */
21139 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
21140 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
21141 || d->icode == CODE_FOR_sse2_maskcmpv2df3
21142 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
21143 return ix86_expand_sse_compare (d, exp, target);
21145 return ix86_expand_binop_builtin (d->icode, exp, target);
21148 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
21149 if (d->code == fcode)
21150 return ix86_expand_unop_builtin (d->icode, exp, target, 0);
21152 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
21153 if (d->code == fcode)
21154 return ix86_expand_sse_comi (d, exp, target);
21156 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
21157 if (d->code == fcode)
21158 return ix86_expand_sse_ptest (d, exp, target);
21160 for (i = 0, d = bdesc_crc32; i < ARRAY_SIZE (bdesc_crc32); i++, d++)
21161 if (d->code == fcode)
21162 return ix86_expand_crc32 (d->icode, exp, target);
21164 for (i = 0, d = bdesc_pcmpestr;
21165 i < ARRAY_SIZE (bdesc_pcmpestr);
21167 if (d->code == fcode)
21168 return ix86_expand_sse_pcmpestr (d, exp, target);
21170 for (i = 0, d = bdesc_pcmpistr;
21171 i < ARRAY_SIZE (bdesc_pcmpistr);
21173 if (d->code == fcode)
21174 return ix86_expand_sse_pcmpistr (d, exp, target);
21176 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
21177 if (d->code == fcode)
21178 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
21179 (enum multi_arg_type)d->flag,
21182 gcc_unreachable ();
21185 /* Returns a function decl for a vectorized version of the builtin function
21186 with builtin function code FN and the result vector type TYPE, or NULL_TREE
21187 if it is not available. */
21190 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
21193 enum machine_mode in_mode, out_mode;
21196 if (TREE_CODE (type_out) != VECTOR_TYPE
21197 || TREE_CODE (type_in) != VECTOR_TYPE)
21200 out_mode = TYPE_MODE (TREE_TYPE (type_out));
21201 out_n = TYPE_VECTOR_SUBPARTS (type_out);
21202 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21203 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21207 case BUILT_IN_SQRT:
21208 if (out_mode == DFmode && out_n == 2
21209 && in_mode == DFmode && in_n == 2)
21210 return ix86_builtins[IX86_BUILTIN_SQRTPD];
21213 case BUILT_IN_SQRTF:
21214 if (out_mode == SFmode && out_n == 4
21215 && in_mode == SFmode && in_n == 4)
21216 return ix86_builtins[IX86_BUILTIN_SQRTPS];
21219 case BUILT_IN_LRINT:
21220 if (out_mode == SImode && out_n == 4
21221 && in_mode == DFmode && in_n == 2)
21222 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
21225 case BUILT_IN_LRINTF:
21226 if (out_mode == SImode && out_n == 4
21227 && in_mode == SFmode && in_n == 4)
21228 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
21235 /* Dispatch to a handler for a vectorization library. */
21236 if (ix86_veclib_handler)
21237 return (*ix86_veclib_handler)(fn, type_out, type_in);
21242 /* Handler for an ACML-style interface to a library with vectorized
21246 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
21248 char name[20] = "__vr.._";
21249 tree fntype, new_fndecl, args;
21252 enum machine_mode el_mode, in_mode;
21255 /* The ACML is 64bits only and suitable for unsafe math only as
21256 it does not correctly support parts of IEEE with the required
21257 precision such as denormals. */
21259 || !flag_unsafe_math_optimizations)
21262 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21263 n = TYPE_VECTOR_SUBPARTS (type_out);
21264 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21265 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21266 if (el_mode != in_mode
21276 case BUILT_IN_LOG2:
21277 case BUILT_IN_LOG10:
21280 if (el_mode != DFmode
21285 case BUILT_IN_SINF:
21286 case BUILT_IN_COSF:
21287 case BUILT_IN_EXPF:
21288 case BUILT_IN_POWF:
21289 case BUILT_IN_LOGF:
21290 case BUILT_IN_LOG2F:
21291 case BUILT_IN_LOG10F:
21294 if (el_mode != SFmode
21303 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21304 sprintf (name + 7, "%s", bname+10);
21307 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21308 args = TREE_CHAIN (args))
21312 fntype = build_function_type_list (type_out, type_in, NULL);
21314 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21316 /* Build a function declaration for the vectorized function. */
21317 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21318 TREE_PUBLIC (new_fndecl) = 1;
21319 DECL_EXTERNAL (new_fndecl) = 1;
21320 DECL_IS_NOVOPS (new_fndecl) = 1;
21321 TREE_READONLY (new_fndecl) = 1;
21327 /* Returns a decl of a function that implements conversion of the
21328 input vector of type TYPE, or NULL_TREE if it is not available. */
21331 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
21333 if (TREE_CODE (type) != VECTOR_TYPE)
21339 switch (TYPE_MODE (type))
21342 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
21347 case FIX_TRUNC_EXPR:
21348 switch (TYPE_MODE (type))
21351 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
21361 /* Returns a code for a target-specific builtin that implements
21362 reciprocal of the function, or NULL_TREE if not available. */
21365 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
21366 bool sqrt ATTRIBUTE_UNUSED)
21368 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
21369 && flag_finite_math_only && !flag_trapping_math
21370 && flag_unsafe_math_optimizations))
21374 /* Machine dependent builtins. */
21377 /* Vectorized version of sqrt to rsqrt conversion. */
21378 case IX86_BUILTIN_SQRTPS:
21379 return ix86_builtins[IX86_BUILTIN_RSQRTPS];
21385 /* Normal builtins. */
21388 /* Sqrt to rsqrt conversion. */
21389 case BUILT_IN_SQRTF:
21390 return ix86_builtins[IX86_BUILTIN_RSQRTF];
21397 /* Store OPERAND to the memory after reload is completed. This means
21398 that we can't easily use assign_stack_local. */
21400 ix86_force_to_memory (enum machine_mode mode, rtx operand)
21404 gcc_assert (reload_completed);
21405 if (TARGET_RED_ZONE)
21407 result = gen_rtx_MEM (mode,
21408 gen_rtx_PLUS (Pmode,
21410 GEN_INT (-RED_ZONE_SIZE)));
21411 emit_move_insn (result, operand);
21413 else if (!TARGET_RED_ZONE && TARGET_64BIT)
21419 operand = gen_lowpart (DImode, operand);
21423 gen_rtx_SET (VOIDmode,
21424 gen_rtx_MEM (DImode,
21425 gen_rtx_PRE_DEC (DImode,
21426 stack_pointer_rtx)),
21430 gcc_unreachable ();
21432 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21441 split_di (&operand, 1, operands, operands + 1);
21443 gen_rtx_SET (VOIDmode,
21444 gen_rtx_MEM (SImode,
21445 gen_rtx_PRE_DEC (Pmode,
21446 stack_pointer_rtx)),
21449 gen_rtx_SET (VOIDmode,
21450 gen_rtx_MEM (SImode,
21451 gen_rtx_PRE_DEC (Pmode,
21452 stack_pointer_rtx)),
21457 /* Store HImodes as SImodes. */
21458 operand = gen_lowpart (SImode, operand);
21462 gen_rtx_SET (VOIDmode,
21463 gen_rtx_MEM (GET_MODE (operand),
21464 gen_rtx_PRE_DEC (SImode,
21465 stack_pointer_rtx)),
21469 gcc_unreachable ();
21471 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21476 /* Free operand from the memory. */
21478 ix86_free_from_memory (enum machine_mode mode)
21480 if (!TARGET_RED_ZONE)
21484 if (mode == DImode || TARGET_64BIT)
21488 /* Use LEA to deallocate stack space. In peephole2 it will be converted
21489 to pop or add instruction if registers are available. */
21490 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
21491 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
21496 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
21497 QImode must go into class Q_REGS.
21498 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
21499 movdf to do mem-to-mem moves through integer regs. */
21501 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
21503 enum machine_mode mode = GET_MODE (x);
21505 /* We're only allowed to return a subclass of CLASS. Many of the
21506 following checks fail for NO_REGS, so eliminate that early. */
21507 if (regclass == NO_REGS)
21510 /* All classes can load zeros. */
21511 if (x == CONST0_RTX (mode))
21514 /* Force constants into memory if we are loading a (nonzero) constant into
21515 an MMX or SSE register. This is because there are no MMX/SSE instructions
21516 to load from a constant. */
21518 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
21521 /* Prefer SSE regs only, if we can use them for math. */
21522 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
21523 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
21525 /* Floating-point constants need more complex checks. */
21526 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
21528 /* General regs can load everything. */
21529 if (reg_class_subset_p (regclass, GENERAL_REGS))
21532 /* Floats can load 0 and 1 plus some others. Note that we eliminated
21533 zero above. We only want to wind up preferring 80387 registers if
21534 we plan on doing computation with them. */
21536 && standard_80387_constant_p (x))
21538 /* Limit class to non-sse. */
21539 if (regclass == FLOAT_SSE_REGS)
21541 if (regclass == FP_TOP_SSE_REGS)
21543 if (regclass == FP_SECOND_SSE_REGS)
21544 return FP_SECOND_REG;
21545 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
21552 /* Generally when we see PLUS here, it's the function invariant
21553 (plus soft-fp const_int). Which can only be computed into general
21555 if (GET_CODE (x) == PLUS)
21556 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
21558 /* QImode constants are easy to load, but non-constant QImode data
21559 must go into Q_REGS. */
21560 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
21562 if (reg_class_subset_p (regclass, Q_REGS))
21564 if (reg_class_subset_p (Q_REGS, regclass))
21572 /* Discourage putting floating-point values in SSE registers unless
21573 SSE math is being used, and likewise for the 387 registers. */
21575 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
21577 enum machine_mode mode = GET_MODE (x);
21579 /* Restrict the output reload class to the register bank that we are doing
21580 math on. If we would like not to return a subset of CLASS, reject this
21581 alternative: if reload cannot do this, it will still use its choice. */
21582 mode = GET_MODE (x);
21583 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
21584 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
21586 if (X87_FLOAT_MODE_P (mode))
21588 if (regclass == FP_TOP_SSE_REGS)
21590 else if (regclass == FP_SECOND_SSE_REGS)
21591 return FP_SECOND_REG;
21593 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
21599 /* If we are copying between general and FP registers, we need a memory
21600 location. The same is true for SSE and MMX registers.
21602 To optimize register_move_cost performance, allow inline variant.
21604 The macro can't work reliably when one of the CLASSES is class containing
21605 registers from multiple units (SSE, MMX, integer). We avoid this by never
21606 combining those units in single alternative in the machine description.
21607 Ensure that this constraint holds to avoid unexpected surprises.
21609 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
21610 enforce these sanity checks. */
21613 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
21614 enum machine_mode mode, int strict)
21616 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
21617 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
21618 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
21619 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
21620 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
21621 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
21623 gcc_assert (!strict);
21627 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
21630 /* ??? This is a lie. We do have moves between mmx/general, and for
21631 mmx/sse2. But by saying we need secondary memory we discourage the
21632 register allocator from using the mmx registers unless needed. */
21633 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
21636 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
21638 /* SSE1 doesn't have any direct moves from other classes. */
21642 /* If the target says that inter-unit moves are more expensive
21643 than moving through memory, then don't generate them. */
21644 if (!TARGET_INTER_UNIT_MOVES)
21647 /* Between SSE and general, we have moves no larger than word size. */
21648 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
21656 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
21657 enum machine_mode mode, int strict)
21659 return inline_secondary_memory_needed (class1, class2, mode, strict);
21662 /* Return true if the registers in CLASS cannot represent the change from
21663 modes FROM to TO. */
21666 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
21667 enum reg_class regclass)
21672 /* x87 registers can't do subreg at all, as all values are reformatted
21673 to extended precision. */
21674 if (MAYBE_FLOAT_CLASS_P (regclass))
21677 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
21679 /* Vector registers do not support QI or HImode loads. If we don't
21680 disallow a change to these modes, reload will assume it's ok to
21681 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
21682 the vec_dupv4hi pattern. */
21683 if (GET_MODE_SIZE (from) < 4)
21686 /* Vector registers do not support subreg with nonzero offsets, which
21687 are otherwise valid for integer registers. Since we can't see
21688 whether we have a nonzero offset from here, prohibit all
21689 nonparadoxical subregs changing size. */
21690 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
21697 /* Return the cost of moving data of mode M between a
21698 register and memory. A value of 2 is the default; this cost is
21699 relative to those in `REGISTER_MOVE_COST'.
21701 This function is used extensively by register_move_cost that is used to
21702 build tables at startup. Make it inline in this case.
21703 When IN is 2, return maximum of in and out move cost.
21705 If moving between registers and memory is more expensive than
21706 between two registers, you should define this macro to express the
21709 Model also increased moving costs of QImode registers in non
21713 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
21717 if (FLOAT_CLASS_P (regclass))
21735 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
21736 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
21738 if (SSE_CLASS_P (regclass))
21741 switch (GET_MODE_SIZE (mode))
21756 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
21757 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
21759 if (MMX_CLASS_P (regclass))
21762 switch (GET_MODE_SIZE (mode))
21774 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
21775 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
21777 switch (GET_MODE_SIZE (mode))
21780 if (Q_CLASS_P (regclass) || TARGET_64BIT)
21783 return ix86_cost->int_store[0];
21784 if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
21785 cost = ix86_cost->movzbl_load;
21787 cost = ix86_cost->int_load[0];
21789 return MAX (cost, ix86_cost->int_store[0]);
21795 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
21797 return ix86_cost->movzbl_load;
21799 return ix86_cost->int_store[0] + 4;
21804 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
21805 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
21807 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
21808 if (mode == TFmode)
21811 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
21813 cost = ix86_cost->int_load[2];
21815 cost = ix86_cost->int_store[2];
21816 return (cost * (((int) GET_MODE_SIZE (mode)
21817 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
21822 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
21824 return inline_memory_move_cost (mode, regclass, in);
21828 /* Return the cost of moving data from a register in class CLASS1 to
21829 one in class CLASS2.
21831 It is not required that the cost always equal 2 when FROM is the same as TO;
21832 on some machines it is expensive to move between registers if they are not
21833 general registers. */
21836 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
21837 enum reg_class class2)
21839 /* In case we require secondary memory, compute cost of the store followed
21840 by load. In order to avoid bad register allocation choices, we need
21841 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
21843 if (inline_secondary_memory_needed (class1, class2, mode, 0))
21847 cost += inline_memory_move_cost (mode, class1, 2);
21848 cost += inline_memory_move_cost (mode, class2, 2);
21850 /* In case of copying from general_purpose_register we may emit multiple
21851 stores followed by single load causing memory size mismatch stall.
21852 Count this as arbitrarily high cost of 20. */
21853 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
21856 /* In the case of FP/MMX moves, the registers actually overlap, and we
21857 have to switch modes in order to treat them differently. */
21858 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
21859 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
21865 /* Moves between SSE/MMX and integer unit are expensive. */
21866 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
21867 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
21869 /* ??? By keeping returned value relatively high, we limit the number
21870 of moves between integer and MMX/SSE registers for all targets.
21871 Additionally, high value prevents problem with x86_modes_tieable_p(),
21872 where integer modes in MMX/SSE registers are not tieable
21873 because of missing QImode and HImode moves to, from or between
21874 MMX/SSE registers. */
21875 return MAX (ix86_cost->mmxsse_to_integer, 8);
21877 if (MAYBE_FLOAT_CLASS_P (class1))
21878 return ix86_cost->fp_move;
21879 if (MAYBE_SSE_CLASS_P (class1))
21880 return ix86_cost->sse_move;
21881 if (MAYBE_MMX_CLASS_P (class1))
21882 return ix86_cost->mmx_move;
21886 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
21889 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
21891 /* Flags and only flags can only hold CCmode values. */
21892 if (CC_REGNO_P (regno))
21893 return GET_MODE_CLASS (mode) == MODE_CC;
21894 if (GET_MODE_CLASS (mode) == MODE_CC
21895 || GET_MODE_CLASS (mode) == MODE_RANDOM
21896 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
21898 if (FP_REGNO_P (regno))
21899 return VALID_FP_MODE_P (mode);
21900 if (SSE_REGNO_P (regno))
21902 /* We implement the move patterns for all vector modes into and
21903 out of SSE registers, even when no operation instructions
21905 return (VALID_SSE_REG_MODE (mode)
21906 || VALID_SSE2_REG_MODE (mode)
21907 || VALID_MMX_REG_MODE (mode)
21908 || VALID_MMX_REG_MODE_3DNOW (mode));
21910 if (MMX_REGNO_P (regno))
21912 /* We implement the move patterns for 3DNOW modes even in MMX mode,
21913 so if the register is available at all, then we can move data of
21914 the given mode into or out of it. */
21915 return (VALID_MMX_REG_MODE (mode)
21916 || VALID_MMX_REG_MODE_3DNOW (mode));
21919 if (mode == QImode)
21921 /* Take care for QImode values - they can be in non-QI regs,
21922 but then they do cause partial register stalls. */
21923 if (regno < 4 || TARGET_64BIT)
21925 if (!TARGET_PARTIAL_REG_STALL)
21927 return reload_in_progress || reload_completed;
21929 /* We handle both integer and floats in the general purpose registers. */
21930 else if (VALID_INT_MODE_P (mode))
21932 else if (VALID_FP_MODE_P (mode))
21934 else if (VALID_DFP_MODE_P (mode))
21936 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
21937 on to use that value in smaller contexts, this can easily force a
21938 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
21939 supporting DImode, allow it. */
21940 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
21946 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
21947 tieable integer mode. */
21950 ix86_tieable_integer_mode_p (enum machine_mode mode)
21959 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
21962 return TARGET_64BIT;
21969 /* Return true if MODE1 is accessible in a register that can hold MODE2
21970 without copying. That is, all register classes that can hold MODE2
21971 can also hold MODE1. */
21974 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
21976 if (mode1 == mode2)
21979 if (ix86_tieable_integer_mode_p (mode1)
21980 && ix86_tieable_integer_mode_p (mode2))
21983 /* MODE2 being XFmode implies fp stack or general regs, which means we
21984 can tie any smaller floating point modes to it. Note that we do not
21985 tie this with TFmode. */
21986 if (mode2 == XFmode)
21987 return mode1 == SFmode || mode1 == DFmode;
21989 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
21990 that we can tie it with SFmode. */
21991 if (mode2 == DFmode)
21992 return mode1 == SFmode;
21994 /* If MODE2 is only appropriate for an SSE register, then tie with
21995 any other mode acceptable to SSE registers. */
21996 if (GET_MODE_SIZE (mode2) == 16
21997 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
21998 return (GET_MODE_SIZE (mode1) == 16
21999 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
22001 /* If MODE2 is appropriate for an MMX register, then tie
22002 with any other mode acceptable to MMX registers. */
22003 if (GET_MODE_SIZE (mode2) == 8
22004 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
22005 return (GET_MODE_SIZE (mode1) == 8
22006 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
22011 /* Compute a (partial) cost for rtx X. Return true if the complete
22012 cost has been computed, and false if subexpressions should be
22013 scanned. In either case, *TOTAL contains the cost result. */
22016 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
22018 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
22019 enum machine_mode mode = GET_MODE (x);
22027 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
22029 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
22031 else if (flag_pic && SYMBOLIC_CONST (x)
22033 || (!GET_CODE (x) != LABEL_REF
22034 && (GET_CODE (x) != SYMBOL_REF
22035 || !SYMBOL_REF_LOCAL_P (x)))))
22042 if (mode == VOIDmode)
22045 switch (standard_80387_constant_p (x))
22050 default: /* Other constants */
22055 /* Start with (MEM (SYMBOL_REF)), since that's where
22056 it'll probably end up. Add a penalty for size. */
22057 *total = (COSTS_N_INSNS (1)
22058 + (flag_pic != 0 && !TARGET_64BIT)
22059 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
22065 /* The zero extensions is often completely free on x86_64, so make
22066 it as cheap as possible. */
22067 if (TARGET_64BIT && mode == DImode
22068 && GET_MODE (XEXP (x, 0)) == SImode)
22070 else if (TARGET_ZERO_EXTEND_WITH_AND)
22071 *total = ix86_cost->add;
22073 *total = ix86_cost->movzx;
22077 *total = ix86_cost->movsx;
22081 if (CONST_INT_P (XEXP (x, 1))
22082 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
22084 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22087 *total = ix86_cost->add;
22090 if ((value == 2 || value == 3)
22091 && ix86_cost->lea <= ix86_cost->shift_const)
22093 *total = ix86_cost->lea;
22103 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
22105 if (CONST_INT_P (XEXP (x, 1)))
22107 if (INTVAL (XEXP (x, 1)) > 32)
22108 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
22110 *total = ix86_cost->shift_const * 2;
22114 if (GET_CODE (XEXP (x, 1)) == AND)
22115 *total = ix86_cost->shift_var * 2;
22117 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
22122 if (CONST_INT_P (XEXP (x, 1)))
22123 *total = ix86_cost->shift_const;
22125 *total = ix86_cost->shift_var;
22130 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22132 /* ??? SSE scalar cost should be used here. */
22133 *total = ix86_cost->fmul;
22136 else if (X87_FLOAT_MODE_P (mode))
22138 *total = ix86_cost->fmul;
22141 else if (FLOAT_MODE_P (mode))
22143 /* ??? SSE vector cost should be used here. */
22144 *total = ix86_cost->fmul;
22149 rtx op0 = XEXP (x, 0);
22150 rtx op1 = XEXP (x, 1);
22152 if (CONST_INT_P (XEXP (x, 1)))
22154 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22155 for (nbits = 0; value != 0; value &= value - 1)
22159 /* This is arbitrary. */
22162 /* Compute costs correctly for widening multiplication. */
22163 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
22164 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
22165 == GET_MODE_SIZE (mode))
22167 int is_mulwiden = 0;
22168 enum machine_mode inner_mode = GET_MODE (op0);
22170 if (GET_CODE (op0) == GET_CODE (op1))
22171 is_mulwiden = 1, op1 = XEXP (op1, 0);
22172 else if (CONST_INT_P (op1))
22174 if (GET_CODE (op0) == SIGN_EXTEND)
22175 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
22178 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
22182 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
22185 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
22186 + nbits * ix86_cost->mult_bit
22187 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
22196 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22197 /* ??? SSE cost should be used here. */
22198 *total = ix86_cost->fdiv;
22199 else if (X87_FLOAT_MODE_P (mode))
22200 *total = ix86_cost->fdiv;
22201 else if (FLOAT_MODE_P (mode))
22202 /* ??? SSE vector cost should be used here. */
22203 *total = ix86_cost->fdiv;
22205 *total = ix86_cost->divide[MODE_INDEX (mode)];
22209 if (GET_MODE_CLASS (mode) == MODE_INT
22210 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
22212 if (GET_CODE (XEXP (x, 0)) == PLUS
22213 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
22214 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
22215 && CONSTANT_P (XEXP (x, 1)))
22217 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
22218 if (val == 2 || val == 4 || val == 8)
22220 *total = ix86_cost->lea;
22221 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22222 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
22224 *total += rtx_cost (XEXP (x, 1), outer_code);
22228 else if (GET_CODE (XEXP (x, 0)) == MULT
22229 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
22231 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
22232 if (val == 2 || val == 4 || val == 8)
22234 *total = ix86_cost->lea;
22235 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22236 *total += rtx_cost (XEXP (x, 1), outer_code);
22240 else if (GET_CODE (XEXP (x, 0)) == PLUS)
22242 *total = ix86_cost->lea;
22243 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22244 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22245 *total += rtx_cost (XEXP (x, 1), outer_code);
22252 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22254 /* ??? SSE cost should be used here. */
22255 *total = ix86_cost->fadd;
22258 else if (X87_FLOAT_MODE_P (mode))
22260 *total = ix86_cost->fadd;
22263 else if (FLOAT_MODE_P (mode))
22265 /* ??? SSE vector cost should be used here. */
22266 *total = ix86_cost->fadd;
22274 if (!TARGET_64BIT && mode == DImode)
22276 *total = (ix86_cost->add * 2
22277 + (rtx_cost (XEXP (x, 0), outer_code)
22278 << (GET_MODE (XEXP (x, 0)) != DImode))
22279 + (rtx_cost (XEXP (x, 1), outer_code)
22280 << (GET_MODE (XEXP (x, 1)) != DImode)));
22286 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22288 /* ??? SSE cost should be used here. */
22289 *total = ix86_cost->fchs;
22292 else if (X87_FLOAT_MODE_P (mode))
22294 *total = ix86_cost->fchs;
22297 else if (FLOAT_MODE_P (mode))
22299 /* ??? SSE vector cost should be used here. */
22300 *total = ix86_cost->fchs;
22306 if (!TARGET_64BIT && mode == DImode)
22307 *total = ix86_cost->add * 2;
22309 *total = ix86_cost->add;
22313 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
22314 && XEXP (XEXP (x, 0), 1) == const1_rtx
22315 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
22316 && XEXP (x, 1) == const0_rtx)
22318 /* This kind of construct is implemented using test[bwl].
22319 Treat it as if we had an AND. */
22320 *total = (ix86_cost->add
22321 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
22322 + rtx_cost (const1_rtx, outer_code));
22328 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
22333 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22334 /* ??? SSE cost should be used here. */
22335 *total = ix86_cost->fabs;
22336 else if (X87_FLOAT_MODE_P (mode))
22337 *total = ix86_cost->fabs;
22338 else if (FLOAT_MODE_P (mode))
22339 /* ??? SSE vector cost should be used here. */
22340 *total = ix86_cost->fabs;
22344 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22345 /* ??? SSE cost should be used here. */
22346 *total = ix86_cost->fsqrt;
22347 else if (X87_FLOAT_MODE_P (mode))
22348 *total = ix86_cost->fsqrt;
22349 else if (FLOAT_MODE_P (mode))
22350 /* ??? SSE vector cost should be used here. */
22351 *total = ix86_cost->fsqrt;
22355 if (XINT (x, 1) == UNSPEC_TP)
22366 static int current_machopic_label_num;
22368 /* Given a symbol name and its associated stub, write out the
22369 definition of the stub. */
22372 machopic_output_stub (FILE *file, const char *symb, const char *stub)
22374 unsigned int length;
22375 char *binder_name, *symbol_name, lazy_ptr_name[32];
22376 int label = ++current_machopic_label_num;
22378 /* For 64-bit we shouldn't get here. */
22379 gcc_assert (!TARGET_64BIT);
22381 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
22382 symb = (*targetm.strip_name_encoding) (symb);
22384 length = strlen (stub);
22385 binder_name = alloca (length + 32);
22386 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
22388 length = strlen (symb);
22389 symbol_name = alloca (length + 32);
22390 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
22392 sprintf (lazy_ptr_name, "L%d$lz", label);
22395 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
22397 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
22399 fprintf (file, "%s:\n", stub);
22400 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22404 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
22405 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
22406 fprintf (file, "\tjmp\t*%%edx\n");
22409 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
22411 fprintf (file, "%s:\n", binder_name);
22415 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
22416 fprintf (file, "\tpushl\t%%eax\n");
22419 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
22421 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
22423 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
22424 fprintf (file, "%s:\n", lazy_ptr_name);
22425 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22426 fprintf (file, "\t.long %s\n", binder_name);
22430 darwin_x86_file_end (void)
22432 darwin_file_end ();
22435 #endif /* TARGET_MACHO */
22437 /* Order the registers for register allocator. */
22440 x86_order_regs_for_local_alloc (void)
22445 /* First allocate the local general purpose registers. */
22446 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22447 if (GENERAL_REGNO_P (i) && call_used_regs[i])
22448 reg_alloc_order [pos++] = i;
22450 /* Global general purpose registers. */
22451 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22452 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
22453 reg_alloc_order [pos++] = i;
22455 /* x87 registers come first in case we are doing FP math
22457 if (!TARGET_SSE_MATH)
22458 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22459 reg_alloc_order [pos++] = i;
22461 /* SSE registers. */
22462 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
22463 reg_alloc_order [pos++] = i;
22464 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
22465 reg_alloc_order [pos++] = i;
22467 /* x87 registers. */
22468 if (TARGET_SSE_MATH)
22469 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22470 reg_alloc_order [pos++] = i;
22472 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
22473 reg_alloc_order [pos++] = i;
22475 /* Initialize the rest of array as we do not allocate some registers
22477 while (pos < FIRST_PSEUDO_REGISTER)
22478 reg_alloc_order [pos++] = 0;
22481 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
22482 struct attribute_spec.handler. */
22484 ix86_handle_struct_attribute (tree *node, tree name,
22485 tree args ATTRIBUTE_UNUSED,
22486 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
22489 if (DECL_P (*node))
22491 if (TREE_CODE (*node) == TYPE_DECL)
22492 type = &TREE_TYPE (*node);
22497 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
22498 || TREE_CODE (*type) == UNION_TYPE)))
22500 warning (OPT_Wattributes, "%qs attribute ignored",
22501 IDENTIFIER_POINTER (name));
22502 *no_add_attrs = true;
22505 else if ((is_attribute_p ("ms_struct", name)
22506 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
22507 || ((is_attribute_p ("gcc_struct", name)
22508 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
22510 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
22511 IDENTIFIER_POINTER (name));
22512 *no_add_attrs = true;
22519 ix86_ms_bitfield_layout_p (const_tree record_type)
22521 return (TARGET_MS_BITFIELD_LAYOUT &&
22522 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
22523 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
22526 /* Returns an expression indicating where the this parameter is
22527 located on entry to the FUNCTION. */
22530 x86_this_parameter (tree function)
22532 tree type = TREE_TYPE (function);
22533 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
22537 const int *parm_regs;
22539 if (TARGET_64BIT_MS_ABI)
22540 parm_regs = x86_64_ms_abi_int_parameter_registers;
22542 parm_regs = x86_64_int_parameter_registers;
22543 return gen_rtx_REG (DImode, parm_regs[aggr]);
22546 if (ix86_function_regparm (type, function) > 0 && !stdarg_p (type))
22548 int regno = AX_REG;
22549 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
22551 return gen_rtx_REG (SImode, regno);
22554 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
22557 /* Determine whether x86_output_mi_thunk can succeed. */
22560 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
22561 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
22562 HOST_WIDE_INT vcall_offset, const_tree function)
22564 /* 64-bit can handle anything. */
22568 /* For 32-bit, everything's fine if we have one free register. */
22569 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
22572 /* Need a free register for vcall_offset. */
22576 /* Need a free register for GOT references. */
22577 if (flag_pic && !(*targetm.binds_local_p) (function))
22580 /* Otherwise ok. */
22584 /* Output the assembler code for a thunk function. THUNK_DECL is the
22585 declaration for the thunk function itself, FUNCTION is the decl for
22586 the target function. DELTA is an immediate constant offset to be
22587 added to THIS. If VCALL_OFFSET is nonzero, the word at
22588 *(*this + vcall_offset) should be added to THIS. */
22591 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
22592 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
22593 HOST_WIDE_INT vcall_offset, tree function)
22596 rtx this_param = x86_this_parameter (function);
22599 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
22600 pull it in now and let DELTA benefit. */
22601 if (REG_P (this_param))
22602 this_reg = this_param;
22603 else if (vcall_offset)
22605 /* Put the this parameter into %eax. */
22606 xops[0] = this_param;
22607 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
22608 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22611 this_reg = NULL_RTX;
22613 /* Adjust the this parameter by a fixed constant. */
22616 xops[0] = GEN_INT (delta);
22617 xops[1] = this_reg ? this_reg : this_param;
22620 if (!x86_64_general_operand (xops[0], DImode))
22622 tmp = gen_rtx_REG (DImode, R10_REG);
22624 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
22626 xops[1] = this_param;
22628 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
22631 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
22634 /* Adjust the this parameter by a value stored in the vtable. */
22638 tmp = gen_rtx_REG (DImode, R10_REG);
22641 int tmp_regno = CX_REG;
22642 if (lookup_attribute ("fastcall",
22643 TYPE_ATTRIBUTES (TREE_TYPE (function))))
22644 tmp_regno = AX_REG;
22645 tmp = gen_rtx_REG (SImode, tmp_regno);
22648 xops[0] = gen_rtx_MEM (Pmode, this_reg);
22651 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
22653 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22655 /* Adjust the this parameter. */
22656 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
22657 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
22659 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
22660 xops[0] = GEN_INT (vcall_offset);
22662 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
22663 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
22665 xops[1] = this_reg;
22667 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
22669 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
22672 /* If necessary, drop THIS back to its stack slot. */
22673 if (this_reg && this_reg != this_param)
22675 xops[0] = this_reg;
22676 xops[1] = this_param;
22677 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
22680 xops[0] = XEXP (DECL_RTL (function), 0);
22683 if (!flag_pic || (*targetm.binds_local_p) (function))
22684 output_asm_insn ("jmp\t%P0", xops);
22685 /* All thunks should be in the same object as their target,
22686 and thus binds_local_p should be true. */
22687 else if (TARGET_64BIT_MS_ABI)
22688 gcc_unreachable ();
22691 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
22692 tmp = gen_rtx_CONST (Pmode, tmp);
22693 tmp = gen_rtx_MEM (QImode, tmp);
22695 output_asm_insn ("jmp\t%A0", xops);
22700 if (!flag_pic || (*targetm.binds_local_p) (function))
22701 output_asm_insn ("jmp\t%P0", xops);
22706 rtx sym_ref = XEXP (DECL_RTL (function), 0);
22707 tmp = (gen_rtx_SYMBOL_REF
22709 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
22710 tmp = gen_rtx_MEM (QImode, tmp);
22712 output_asm_insn ("jmp\t%0", xops);
22715 #endif /* TARGET_MACHO */
22717 tmp = gen_rtx_REG (SImode, CX_REG);
22718 output_set_got (tmp, NULL_RTX);
22721 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
22722 output_asm_insn ("jmp\t{*}%1", xops);
22728 x86_file_start (void)
22730 default_file_start ();
22732 darwin_file_start ();
22734 if (X86_FILE_START_VERSION_DIRECTIVE)
22735 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
22736 if (X86_FILE_START_FLTUSED)
22737 fputs ("\t.global\t__fltused\n", asm_out_file);
22738 if (ix86_asm_dialect == ASM_INTEL)
22739 fputs ("\t.intel_syntax\n", asm_out_file);
22743 x86_field_alignment (tree field, int computed)
22745 enum machine_mode mode;
22746 tree type = TREE_TYPE (field);
22748 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
22750 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
22751 ? get_inner_array_type (type) : type);
22752 if (mode == DFmode || mode == DCmode
22753 || GET_MODE_CLASS (mode) == MODE_INT
22754 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
22755 return MIN (32, computed);
22759 /* Output assembler code to FILE to increment profiler label # LABELNO
22760 for profiling a function entry. */
22762 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
22766 #ifndef NO_PROFILE_COUNTERS
22767 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
22770 if (!TARGET_64BIT_MS_ABI && flag_pic)
22771 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
22773 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
22777 #ifndef NO_PROFILE_COUNTERS
22778 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
22779 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
22781 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
22785 #ifndef NO_PROFILE_COUNTERS
22786 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
22787 PROFILE_COUNT_REGISTER);
22789 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
22793 /* We don't have exact information about the insn sizes, but we may assume
22794 quite safely that we are informed about all 1 byte insns and memory
22795 address sizes. This is enough to eliminate unnecessary padding in
22799 min_insn_size (rtx insn)
22803 if (!INSN_P (insn) || !active_insn_p (insn))
22806 /* Discard alignments we've emit and jump instructions. */
22807 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
22808 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
22811 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
22812 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
22815 /* Important case - calls are always 5 bytes.
22816 It is common to have many calls in the row. */
22818 && symbolic_reference_mentioned_p (PATTERN (insn))
22819 && !SIBLING_CALL_P (insn))
22821 if (get_attr_length (insn) <= 1)
22824 /* For normal instructions we may rely on the sizes of addresses
22825 and the presence of symbol to require 4 bytes of encoding.
22826 This is not the case for jumps where references are PC relative. */
22827 if (!JUMP_P (insn))
22829 l = get_attr_length_address (insn);
22830 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
22839 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
22843 ix86_avoid_jump_misspredicts (void)
22845 rtx insn, start = get_insns ();
22846 int nbytes = 0, njumps = 0;
22849 /* Look for all minimal intervals of instructions containing 4 jumps.
22850 The intervals are bounded by START and INSN. NBYTES is the total
22851 size of instructions in the interval including INSN and not including
22852 START. When the NBYTES is smaller than 16 bytes, it is possible
22853 that the end of START and INSN ends up in the same 16byte page.
22855 The smallest offset in the page INSN can start is the case where START
22856 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
22857 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
22859 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
22862 nbytes += min_insn_size (insn);
22864 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
22865 INSN_UID (insn), min_insn_size (insn));
22867 && GET_CODE (PATTERN (insn)) != ADDR_VEC
22868 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
22876 start = NEXT_INSN (start);
22877 if ((JUMP_P (start)
22878 && GET_CODE (PATTERN (start)) != ADDR_VEC
22879 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
22881 njumps--, isjump = 1;
22884 nbytes -= min_insn_size (start);
22886 gcc_assert (njumps >= 0);
22888 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
22889 INSN_UID (start), INSN_UID (insn), nbytes);
22891 if (njumps == 3 && isjump && nbytes < 16)
22893 int padsize = 15 - nbytes + min_insn_size (insn);
22896 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
22897 INSN_UID (insn), padsize);
22898 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
22903 /* AMD Athlon works faster
22904 when RET is not destination of conditional jump or directly preceded
22905 by other jump instruction. We avoid the penalty by inserting NOP just
22906 before the RET instructions in such cases. */
22908 ix86_pad_returns (void)
22913 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
22915 basic_block bb = e->src;
22916 rtx ret = BB_END (bb);
22918 bool replace = false;
22920 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
22921 || !maybe_hot_bb_p (bb))
22923 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
22924 if (active_insn_p (prev) || LABEL_P (prev))
22926 if (prev && LABEL_P (prev))
22931 FOR_EACH_EDGE (e, ei, bb->preds)
22932 if (EDGE_FREQUENCY (e) && e->src->index >= 0
22933 && !(e->flags & EDGE_FALLTHRU))
22938 prev = prev_active_insn (ret);
22940 && ((JUMP_P (prev) && any_condjump_p (prev))
22943 /* Empty functions get branch mispredict even when the jump destination
22944 is not visible to us. */
22945 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
22950 emit_insn_before (gen_return_internal_long (), ret);
22956 /* Implement machine specific optimizations. We implement padding of returns
22957 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
22961 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
22962 ix86_pad_returns ();
22963 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
22964 ix86_avoid_jump_misspredicts ();
22967 /* Return nonzero when QImode register that must be represented via REX prefix
22970 x86_extended_QIreg_mentioned_p (rtx insn)
22973 extract_insn_cached (insn);
22974 for (i = 0; i < recog_data.n_operands; i++)
22975 if (REG_P (recog_data.operand[i])
22976 && REGNO (recog_data.operand[i]) >= 4)
22981 /* Return nonzero when P points to register encoded via REX prefix.
22982 Called via for_each_rtx. */
22984 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
22986 unsigned int regno;
22989 regno = REGNO (*p);
22990 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
22993 /* Return true when INSN mentions register that must be encoded using REX
22996 x86_extended_reg_mentioned_p (rtx insn)
22998 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
23001 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
23002 optabs would emit if we didn't have TFmode patterns. */
23005 x86_emit_floatuns (rtx operands[2])
23007 rtx neglab, donelab, i0, i1, f0, in, out;
23008 enum machine_mode mode, inmode;
23010 inmode = GET_MODE (operands[1]);
23011 gcc_assert (inmode == SImode || inmode == DImode);
23014 in = force_reg (inmode, operands[1]);
23015 mode = GET_MODE (out);
23016 neglab = gen_label_rtx ();
23017 donelab = gen_label_rtx ();
23018 f0 = gen_reg_rtx (mode);
23020 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
23022 expand_float (out, in, 0);
23024 emit_jump_insn (gen_jump (donelab));
23027 emit_label (neglab);
23029 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
23031 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
23033 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
23035 expand_float (f0, i0, 0);
23037 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
23039 emit_label (donelab);
23042 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23043 with all elements equal to VAR. Return true if successful. */
23046 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
23047 rtx target, rtx val)
23049 enum machine_mode smode, wsmode, wvmode;
23064 val = force_reg (GET_MODE_INNER (mode), val);
23065 x = gen_rtx_VEC_DUPLICATE (mode, val);
23066 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23072 if (TARGET_SSE || TARGET_3DNOW_A)
23074 val = gen_lowpart (SImode, val);
23075 x = gen_rtx_TRUNCATE (HImode, val);
23076 x = gen_rtx_VEC_DUPLICATE (mode, x);
23077 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23099 /* Extend HImode to SImode using a paradoxical SUBREG. */
23100 tmp1 = gen_reg_rtx (SImode);
23101 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23102 /* Insert the SImode value as low element of V4SImode vector. */
23103 tmp2 = gen_reg_rtx (V4SImode);
23104 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23105 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23106 CONST0_RTX (V4SImode),
23108 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23109 /* Cast the V4SImode vector back to a V8HImode vector. */
23110 tmp1 = gen_reg_rtx (V8HImode);
23111 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
23112 /* Duplicate the low short through the whole low SImode word. */
23113 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
23114 /* Cast the V8HImode vector back to a V4SImode vector. */
23115 tmp2 = gen_reg_rtx (V4SImode);
23116 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23117 /* Replicate the low element of the V4SImode vector. */
23118 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23119 /* Cast the V2SImode back to V8HImode, and store in target. */
23120 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
23131 /* Extend QImode to SImode using a paradoxical SUBREG. */
23132 tmp1 = gen_reg_rtx (SImode);
23133 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23134 /* Insert the SImode value as low element of V4SImode vector. */
23135 tmp2 = gen_reg_rtx (V4SImode);
23136 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23137 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23138 CONST0_RTX (V4SImode),
23140 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23141 /* Cast the V4SImode vector back to a V16QImode vector. */
23142 tmp1 = gen_reg_rtx (V16QImode);
23143 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
23144 /* Duplicate the low byte through the whole low SImode word. */
23145 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23146 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23147 /* Cast the V16QImode vector back to a V4SImode vector. */
23148 tmp2 = gen_reg_rtx (V4SImode);
23149 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23150 /* Replicate the low element of the V4SImode vector. */
23151 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23152 /* Cast the V2SImode back to V16QImode, and store in target. */
23153 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
23161 /* Replicate the value once into the next wider mode and recurse. */
23162 val = convert_modes (wsmode, smode, val, true);
23163 x = expand_simple_binop (wsmode, ASHIFT, val,
23164 GEN_INT (GET_MODE_BITSIZE (smode)),
23165 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23166 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
23168 x = gen_reg_rtx (wvmode);
23169 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
23170 gcc_unreachable ();
23171 emit_move_insn (target, gen_lowpart (mode, x));
23179 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23180 whose ONE_VAR element is VAR, and other elements are zero. Return true
23184 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
23185 rtx target, rtx var, int one_var)
23187 enum machine_mode vsimode;
23203 var = force_reg (GET_MODE_INNER (mode), var);
23204 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
23205 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23210 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
23211 new_target = gen_reg_rtx (mode);
23213 new_target = target;
23214 var = force_reg (GET_MODE_INNER (mode), var);
23215 x = gen_rtx_VEC_DUPLICATE (mode, var);
23216 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
23217 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
23220 /* We need to shuffle the value to the correct position, so
23221 create a new pseudo to store the intermediate result. */
23223 /* With SSE2, we can use the integer shuffle insns. */
23224 if (mode != V4SFmode && TARGET_SSE2)
23226 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
23228 GEN_INT (one_var == 1 ? 0 : 1),
23229 GEN_INT (one_var == 2 ? 0 : 1),
23230 GEN_INT (one_var == 3 ? 0 : 1)));
23231 if (target != new_target)
23232 emit_move_insn (target, new_target);
23236 /* Otherwise convert the intermediate result to V4SFmode and
23237 use the SSE1 shuffle instructions. */
23238 if (mode != V4SFmode)
23240 tmp = gen_reg_rtx (V4SFmode);
23241 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
23246 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
23248 GEN_INT (one_var == 1 ? 0 : 1),
23249 GEN_INT (one_var == 2 ? 0+4 : 1+4),
23250 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
23252 if (mode != V4SFmode)
23253 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
23254 else if (tmp != target)
23255 emit_move_insn (target, tmp);
23257 else if (target != new_target)
23258 emit_move_insn (target, new_target);
23263 vsimode = V4SImode;
23269 vsimode = V2SImode;
23275 /* Zero extend the variable element to SImode and recurse. */
23276 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
23278 x = gen_reg_rtx (vsimode);
23279 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
23281 gcc_unreachable ();
23283 emit_move_insn (target, gen_lowpart (mode, x));
23291 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23292 consisting of the values in VALS. It is known that all elements
23293 except ONE_VAR are constants. Return true if successful. */
23296 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
23297 rtx target, rtx vals, int one_var)
23299 rtx var = XVECEXP (vals, 0, one_var);
23300 enum machine_mode wmode;
23303 const_vec = copy_rtx (vals);
23304 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
23305 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
23313 /* For the two element vectors, it's just as easy to use
23314 the general case. */
23330 /* There's no way to set one QImode entry easily. Combine
23331 the variable value with its adjacent constant value, and
23332 promote to an HImode set. */
23333 x = XVECEXP (vals, 0, one_var ^ 1);
23336 var = convert_modes (HImode, QImode, var, true);
23337 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
23338 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23339 x = GEN_INT (INTVAL (x) & 0xff);
23343 var = convert_modes (HImode, QImode, var, true);
23344 x = gen_int_mode (INTVAL (x) << 8, HImode);
23346 if (x != const0_rtx)
23347 var = expand_simple_binop (HImode, IOR, var, x, var,
23348 1, OPTAB_LIB_WIDEN);
23350 x = gen_reg_rtx (wmode);
23351 emit_move_insn (x, gen_lowpart (wmode, const_vec));
23352 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
23354 emit_move_insn (target, gen_lowpart (mode, x));
23361 emit_move_insn (target, const_vec);
23362 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23366 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
23367 all values variable, and none identical. */
23370 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
23371 rtx target, rtx vals)
23373 enum machine_mode half_mode = GET_MODE_INNER (mode);
23374 rtx op0 = NULL, op1 = NULL;
23375 bool use_vec_concat = false;
23381 if (!mmx_ok && !TARGET_SSE)
23387 /* For the two element vectors, we always implement VEC_CONCAT. */
23388 op0 = XVECEXP (vals, 0, 0);
23389 op1 = XVECEXP (vals, 0, 1);
23390 use_vec_concat = true;
23394 half_mode = V2SFmode;
23397 half_mode = V2SImode;
23403 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
23404 Recurse to load the two halves. */
23406 op0 = gen_reg_rtx (half_mode);
23407 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
23408 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
23410 op1 = gen_reg_rtx (half_mode);
23411 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
23412 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
23414 use_vec_concat = true;
23425 gcc_unreachable ();
23428 if (use_vec_concat)
23430 if (!register_operand (op0, half_mode))
23431 op0 = force_reg (half_mode, op0);
23432 if (!register_operand (op1, half_mode))
23433 op1 = force_reg (half_mode, op1);
23435 emit_insn (gen_rtx_SET (VOIDmode, target,
23436 gen_rtx_VEC_CONCAT (mode, op0, op1)));
23440 int i, j, n_elts, n_words, n_elt_per_word;
23441 enum machine_mode inner_mode;
23442 rtx words[4], shift;
23444 inner_mode = GET_MODE_INNER (mode);
23445 n_elts = GET_MODE_NUNITS (mode);
23446 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
23447 n_elt_per_word = n_elts / n_words;
23448 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
23450 for (i = 0; i < n_words; ++i)
23452 rtx word = NULL_RTX;
23454 for (j = 0; j < n_elt_per_word; ++j)
23456 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
23457 elt = convert_modes (word_mode, inner_mode, elt, true);
23463 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
23464 word, 1, OPTAB_LIB_WIDEN);
23465 word = expand_simple_binop (word_mode, IOR, word, elt,
23466 word, 1, OPTAB_LIB_WIDEN);
23474 emit_move_insn (target, gen_lowpart (mode, words[0]));
23475 else if (n_words == 2)
23477 rtx tmp = gen_reg_rtx (mode);
23478 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
23479 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
23480 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
23481 emit_move_insn (target, tmp);
23483 else if (n_words == 4)
23485 rtx tmp = gen_reg_rtx (V4SImode);
23486 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
23487 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
23488 emit_move_insn (target, gen_lowpart (mode, tmp));
23491 gcc_unreachable ();
23495 /* Initialize vector TARGET via VALS. Suppress the use of MMX
23496 instructions unless MMX_OK is true. */
23499 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
23501 enum machine_mode mode = GET_MODE (target);
23502 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23503 int n_elts = GET_MODE_NUNITS (mode);
23504 int n_var = 0, one_var = -1;
23505 bool all_same = true, all_const_zero = true;
23509 for (i = 0; i < n_elts; ++i)
23511 x = XVECEXP (vals, 0, i);
23512 if (!CONSTANT_P (x))
23513 n_var++, one_var = i;
23514 else if (x != CONST0_RTX (inner_mode))
23515 all_const_zero = false;
23516 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
23520 /* Constants are best loaded from the constant pool. */
23523 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
23527 /* If all values are identical, broadcast the value. */
23529 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
23530 XVECEXP (vals, 0, 0)))
23533 /* Values where only one field is non-constant are best loaded from
23534 the pool and overwritten via move later. */
23538 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
23539 XVECEXP (vals, 0, one_var),
23543 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
23547 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
23551 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
23553 enum machine_mode mode = GET_MODE (target);
23554 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23555 bool use_vec_merge = false;
23564 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
23565 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
23567 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
23569 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
23570 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23576 use_vec_merge = TARGET_SSE4_1;
23584 /* For the two element vectors, we implement a VEC_CONCAT with
23585 the extraction of the other element. */
23587 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
23588 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
23591 op0 = val, op1 = tmp;
23593 op0 = tmp, op1 = val;
23595 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
23596 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23601 use_vec_merge = TARGET_SSE4_1;
23608 use_vec_merge = true;
23612 /* tmp = target = A B C D */
23613 tmp = copy_to_reg (target);
23614 /* target = A A B B */
23615 emit_insn (gen_sse_unpcklps (target, target, target));
23616 /* target = X A B B */
23617 ix86_expand_vector_set (false, target, val, 0);
23618 /* target = A X C D */
23619 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23620 GEN_INT (1), GEN_INT (0),
23621 GEN_INT (2+4), GEN_INT (3+4)));
23625 /* tmp = target = A B C D */
23626 tmp = copy_to_reg (target);
23627 /* tmp = X B C D */
23628 ix86_expand_vector_set (false, tmp, val, 0);
23629 /* target = A B X D */
23630 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23631 GEN_INT (0), GEN_INT (1),
23632 GEN_INT (0+4), GEN_INT (3+4)));
23636 /* tmp = target = A B C D */
23637 tmp = copy_to_reg (target);
23638 /* tmp = X B C D */
23639 ix86_expand_vector_set (false, tmp, val, 0);
23640 /* target = A B X D */
23641 emit_insn (gen_sse_shufps_1 (target, target, tmp,
23642 GEN_INT (0), GEN_INT (1),
23643 GEN_INT (2+4), GEN_INT (0+4)));
23647 gcc_unreachable ();
23652 use_vec_merge = TARGET_SSE4_1;
23656 /* Element 0 handled by vec_merge below. */
23659 use_vec_merge = true;
23665 /* With SSE2, use integer shuffles to swap element 0 and ELT,
23666 store into element 0, then shuffle them back. */
23670 order[0] = GEN_INT (elt);
23671 order[1] = const1_rtx;
23672 order[2] = const2_rtx;
23673 order[3] = GEN_INT (3);
23674 order[elt] = const0_rtx;
23676 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
23677 order[1], order[2], order[3]));
23679 ix86_expand_vector_set (false, target, val, 0);
23681 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
23682 order[1], order[2], order[3]));
23686 /* For SSE1, we have to reuse the V4SF code. */
23687 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
23688 gen_lowpart (SFmode, val), elt);
23693 use_vec_merge = TARGET_SSE2;
23696 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
23700 use_vec_merge = TARGET_SSE4_1;
23710 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
23711 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
23712 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23716 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
23718 emit_move_insn (mem, target);
23720 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
23721 emit_move_insn (tmp, val);
23723 emit_move_insn (target, mem);
23728 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
23730 enum machine_mode mode = GET_MODE (vec);
23731 enum machine_mode inner_mode = GET_MODE_INNER (mode);
23732 bool use_vec_extr = false;
23745 use_vec_extr = true;
23749 use_vec_extr = TARGET_SSE4_1;
23761 tmp = gen_reg_rtx (mode);
23762 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
23763 GEN_INT (elt), GEN_INT (elt),
23764 GEN_INT (elt+4), GEN_INT (elt+4)));
23768 tmp = gen_reg_rtx (mode);
23769 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
23773 gcc_unreachable ();
23776 use_vec_extr = true;
23781 use_vec_extr = TARGET_SSE4_1;
23795 tmp = gen_reg_rtx (mode);
23796 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
23797 GEN_INT (elt), GEN_INT (elt),
23798 GEN_INT (elt), GEN_INT (elt)));
23802 tmp = gen_reg_rtx (mode);
23803 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
23807 gcc_unreachable ();
23810 use_vec_extr = true;
23815 /* For SSE1, we have to reuse the V4SF code. */
23816 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
23817 gen_lowpart (V4SFmode, vec), elt);
23823 use_vec_extr = TARGET_SSE2;
23826 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
23830 use_vec_extr = TARGET_SSE4_1;
23834 /* ??? Could extract the appropriate HImode element and shift. */
23841 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
23842 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
23844 /* Let the rtl optimizers know about the zero extension performed. */
23845 if (inner_mode == QImode || inner_mode == HImode)
23847 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
23848 target = gen_lowpart (SImode, target);
23851 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
23855 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
23857 emit_move_insn (mem, vec);
23859 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
23860 emit_move_insn (target, tmp);
23864 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
23865 pattern to reduce; DEST is the destination; IN is the input vector. */
23868 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
23870 rtx tmp1, tmp2, tmp3;
23872 tmp1 = gen_reg_rtx (V4SFmode);
23873 tmp2 = gen_reg_rtx (V4SFmode);
23874 tmp3 = gen_reg_rtx (V4SFmode);
23876 emit_insn (gen_sse_movhlps (tmp1, in, in));
23877 emit_insn (fn (tmp2, tmp1, in));
23879 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
23880 GEN_INT (1), GEN_INT (1),
23881 GEN_INT (1+4), GEN_INT (1+4)));
23882 emit_insn (fn (dest, tmp2, tmp3));
23885 /* Target hook for scalar_mode_supported_p. */
23887 ix86_scalar_mode_supported_p (enum machine_mode mode)
23889 if (DECIMAL_FLOAT_MODE_P (mode))
23891 else if (mode == TFmode)
23892 return TARGET_64BIT;
23894 return default_scalar_mode_supported_p (mode);
23897 /* Implements target hook vector_mode_supported_p. */
23899 ix86_vector_mode_supported_p (enum machine_mode mode)
23901 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
23903 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
23905 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
23907 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
23912 /* Target hook for c_mode_for_suffix. */
23913 static enum machine_mode
23914 ix86_c_mode_for_suffix (char suffix)
23916 if (TARGET_64BIT && suffix == 'q')
23918 if (TARGET_MMX && suffix == 'w')
23924 /* Worker function for TARGET_MD_ASM_CLOBBERS.
23926 We do this in the new i386 backend to maintain source compatibility
23927 with the old cc0-based compiler. */
23930 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
23931 tree inputs ATTRIBUTE_UNUSED,
23934 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
23936 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
23941 /* Implements target vector targetm.asm.encode_section_info. This
23942 is not used by netware. */
23944 static void ATTRIBUTE_UNUSED
23945 ix86_encode_section_info (tree decl, rtx rtl, int first)
23947 default_encode_section_info (decl, rtl, first);
23949 if (TREE_CODE (decl) == VAR_DECL
23950 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
23951 && ix86_in_large_data_p (decl))
23952 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
23955 /* Worker function for REVERSE_CONDITION. */
23958 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
23960 return (mode != CCFPmode && mode != CCFPUmode
23961 ? reverse_condition (code)
23962 : reverse_condition_maybe_unordered (code));
23965 /* Output code to perform an x87 FP register move, from OPERANDS[1]
23969 output_387_reg_move (rtx insn, rtx *operands)
23971 if (REG_P (operands[0]))
23973 if (REG_P (operands[1])
23974 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
23976 if (REGNO (operands[0]) == FIRST_STACK_REG)
23977 return output_387_ffreep (operands, 0);
23978 return "fstp\t%y0";
23980 if (STACK_TOP_P (operands[0]))
23981 return "fld%z1\t%y1";
23984 else if (MEM_P (operands[0]))
23986 gcc_assert (REG_P (operands[1]));
23987 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
23988 return "fstp%z0\t%y0";
23991 /* There is no non-popping store to memory for XFmode.
23992 So if we need one, follow the store with a load. */
23993 if (GET_MODE (operands[0]) == XFmode)
23994 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
23996 return "fst%z0\t%y0";
24003 /* Output code to perform a conditional jump to LABEL, if C2 flag in
24004 FP status register is set. */
24007 ix86_emit_fp_unordered_jump (rtx label)
24009 rtx reg = gen_reg_rtx (HImode);
24012 emit_insn (gen_x86_fnstsw_1 (reg));
24014 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
24016 emit_insn (gen_x86_sahf_1 (reg));
24018 temp = gen_rtx_REG (CCmode, FLAGS_REG);
24019 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
24023 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
24025 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
24026 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
24029 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
24030 gen_rtx_LABEL_REF (VOIDmode, label),
24032 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
24034 emit_jump_insn (temp);
24035 predict_jump (REG_BR_PROB_BASE * 10 / 100);
24038 /* Output code to perform a log1p XFmode calculation. */
24040 void ix86_emit_i387_log1p (rtx op0, rtx op1)
24042 rtx label1 = gen_label_rtx ();
24043 rtx label2 = gen_label_rtx ();
24045 rtx tmp = gen_reg_rtx (XFmode);
24046 rtx tmp2 = gen_reg_rtx (XFmode);
24048 emit_insn (gen_absxf2 (tmp, op1));
24049 emit_insn (gen_cmpxf (tmp,
24050 CONST_DOUBLE_FROM_REAL_VALUE (
24051 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
24053 emit_jump_insn (gen_bge (label1));
24055 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24056 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
24057 emit_jump (label2);
24059 emit_label (label1);
24060 emit_move_insn (tmp, CONST1_RTX (XFmode));
24061 emit_insn (gen_addxf3 (tmp, op1, tmp));
24062 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24063 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
24065 emit_label (label2);
24068 /* Output code to perform a Newton-Rhapson approximation of a single precision
24069 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
24071 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
24073 rtx x0, x1, e0, e1, two;
24075 x0 = gen_reg_rtx (mode);
24076 e0 = gen_reg_rtx (mode);
24077 e1 = gen_reg_rtx (mode);
24078 x1 = gen_reg_rtx (mode);
24080 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
24082 if (VECTOR_MODE_P (mode))
24083 two = ix86_build_const_vector (SFmode, true, two);
24085 two = force_reg (mode, two);
24087 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
24089 /* x0 = 1./b estimate */
24090 emit_insn (gen_rtx_SET (VOIDmode, x0,
24091 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
24094 emit_insn (gen_rtx_SET (VOIDmode, e0,
24095 gen_rtx_MULT (mode, x0, b)));
24097 emit_insn (gen_rtx_SET (VOIDmode, e1,
24098 gen_rtx_MINUS (mode, two, e0)));
24100 emit_insn (gen_rtx_SET (VOIDmode, x1,
24101 gen_rtx_MULT (mode, x0, e1)));
24103 emit_insn (gen_rtx_SET (VOIDmode, res,
24104 gen_rtx_MULT (mode, a, x1)));
24107 /* Output code to perform a Newton-Rhapson approximation of a
24108 single precision floating point [reciprocal] square root. */
24110 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
24113 rtx x0, e0, e1, e2, e3, three, half, zero, mask;
24115 x0 = gen_reg_rtx (mode);
24116 e0 = gen_reg_rtx (mode);
24117 e1 = gen_reg_rtx (mode);
24118 e2 = gen_reg_rtx (mode);
24119 e3 = gen_reg_rtx (mode);
24121 three = CONST_DOUBLE_FROM_REAL_VALUE (dconst3, SFmode);
24122 half = CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, SFmode);
24124 mask = gen_reg_rtx (mode);
24126 if (VECTOR_MODE_P (mode))
24128 three = ix86_build_const_vector (SFmode, true, three);
24129 half = ix86_build_const_vector (SFmode, true, half);
24132 three = force_reg (mode, three);
24133 half = force_reg (mode, half);
24135 zero = force_reg (mode, CONST0_RTX(mode));
24137 /* sqrt(a) = 0.5 * a * rsqrtss(a) * (3.0 - a * rsqrtss(a) * rsqrtss(a))
24138 1.0 / sqrt(a) = 0.5 * rsqrtss(a) * (3.0 - a * rsqrtss(a) * rsqrtss(a)) */
24140 /* Compare a to zero. */
24141 emit_insn (gen_rtx_SET (VOIDmode, mask,
24142 gen_rtx_NE (mode, a, zero)));
24144 /* x0 = 1./sqrt(a) estimate */
24145 emit_insn (gen_rtx_SET (VOIDmode, x0,
24146 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
24148 /* Filter out infinity. */
24149 if (VECTOR_MODE_P (mode))
24150 emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (V4SFmode, x0),
24152 gen_lowpart (V4SFmode, x0),
24153 gen_lowpart (V4SFmode, mask))));
24155 emit_insn (gen_rtx_SET (VOIDmode, x0,
24156 gen_rtx_AND (mode, x0, mask)));
24159 emit_insn (gen_rtx_SET (VOIDmode, e0,
24160 gen_rtx_MULT (mode, x0, a)));
24162 emit_insn (gen_rtx_SET (VOIDmode, e1,
24163 gen_rtx_MULT (mode, e0, x0)));
24165 emit_insn (gen_rtx_SET (VOIDmode, e2,
24166 gen_rtx_MINUS (mode, three, e1)));
24169 emit_insn (gen_rtx_SET (VOIDmode, e3,
24170 gen_rtx_MULT (mode, half, x0)));
24173 emit_insn (gen_rtx_SET (VOIDmode, e3,
24174 gen_rtx_MULT (mode, half, e0)));
24175 /* ret = e2 * e3 */
24176 emit_insn (gen_rtx_SET (VOIDmode, res,
24177 gen_rtx_MULT (mode, e2, e3)));
24180 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
24182 static void ATTRIBUTE_UNUSED
24183 i386_solaris_elf_named_section (const char *name, unsigned int flags,
24186 /* With Binutils 2.15, the "@unwind" marker must be specified on
24187 every occurrence of the ".eh_frame" section, not just the first
24190 && strcmp (name, ".eh_frame") == 0)
24192 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
24193 flags & SECTION_WRITE ? "aw" : "a");
24196 default_elf_asm_named_section (name, flags, decl);
24199 /* Return the mangling of TYPE if it is an extended fundamental type. */
24201 static const char *
24202 ix86_mangle_type (const_tree type)
24204 type = TYPE_MAIN_VARIANT (type);
24206 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24207 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24210 switch (TYPE_MODE (type))
24213 /* __float128 is "g". */
24216 /* "long double" or __float80 is "e". */
24223 /* For 32-bit code we can save PIC register setup by using
24224 __stack_chk_fail_local hidden function instead of calling
24225 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
24226 register, so it is better to call __stack_chk_fail directly. */
24229 ix86_stack_protect_fail (void)
24231 return TARGET_64BIT
24232 ? default_external_stack_protect_fail ()
24233 : default_hidden_stack_protect_fail ();
24236 /* Select a format to encode pointers in exception handling data. CODE
24237 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
24238 true if the symbol may be affected by dynamic relocations.
24240 ??? All x86 object file formats are capable of representing this.
24241 After all, the relocation needed is the same as for the call insn.
24242 Whether or not a particular assembler allows us to enter such, I
24243 guess we'll have to see. */
24245 asm_preferred_eh_data_format (int code, int global)
24249 int type = DW_EH_PE_sdata8;
24251 || ix86_cmodel == CM_SMALL_PIC
24252 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
24253 type = DW_EH_PE_sdata4;
24254 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
24256 if (ix86_cmodel == CM_SMALL
24257 || (ix86_cmodel == CM_MEDIUM && code))
24258 return DW_EH_PE_udata4;
24259 return DW_EH_PE_absptr;
24262 /* Expand copysign from SIGN to the positive value ABS_VALUE
24263 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
24266 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
24268 enum machine_mode mode = GET_MODE (sign);
24269 rtx sgn = gen_reg_rtx (mode);
24270 if (mask == NULL_RTX)
24272 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
24273 if (!VECTOR_MODE_P (mode))
24275 /* We need to generate a scalar mode mask in this case. */
24276 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24277 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24278 mask = gen_reg_rtx (mode);
24279 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24283 mask = gen_rtx_NOT (mode, mask);
24284 emit_insn (gen_rtx_SET (VOIDmode, sgn,
24285 gen_rtx_AND (mode, mask, sign)));
24286 emit_insn (gen_rtx_SET (VOIDmode, result,
24287 gen_rtx_IOR (mode, abs_value, sgn)));
24290 /* Expand fabs (OP0) and return a new rtx that holds the result. The
24291 mask for masking out the sign-bit is stored in *SMASK, if that is
24294 ix86_expand_sse_fabs (rtx op0, rtx *smask)
24296 enum machine_mode mode = GET_MODE (op0);
24299 xa = gen_reg_rtx (mode);
24300 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
24301 if (!VECTOR_MODE_P (mode))
24303 /* We need to generate a scalar mode mask in this case. */
24304 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24305 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24306 mask = gen_reg_rtx (mode);
24307 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24309 emit_insn (gen_rtx_SET (VOIDmode, xa,
24310 gen_rtx_AND (mode, op0, mask)));
24318 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
24319 swapping the operands if SWAP_OPERANDS is true. The expanded
24320 code is a forward jump to a newly created label in case the
24321 comparison is true. The generated label rtx is returned. */
24323 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
24324 bool swap_operands)
24335 label = gen_label_rtx ();
24336 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
24337 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24338 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
24339 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
24340 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
24341 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
24342 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
24343 JUMP_LABEL (tmp) = label;
24348 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
24349 using comparison code CODE. Operands are swapped for the comparison if
24350 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
24352 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
24353 bool swap_operands)
24355 enum machine_mode mode = GET_MODE (op0);
24356 rtx mask = gen_reg_rtx (mode);
24365 if (mode == DFmode)
24366 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
24367 gen_rtx_fmt_ee (code, mode, op0, op1)));
24369 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
24370 gen_rtx_fmt_ee (code, mode, op0, op1)));
24375 /* Generate and return a rtx of mode MODE for 2**n where n is the number
24376 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
24378 ix86_gen_TWO52 (enum machine_mode mode)
24380 REAL_VALUE_TYPE TWO52r;
24383 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
24384 TWO52 = const_double_from_real_value (TWO52r, mode);
24385 TWO52 = force_reg (mode, TWO52);
24390 /* Expand SSE sequence for computing lround from OP1 storing
24393 ix86_expand_lround (rtx op0, rtx op1)
24395 /* C code for the stuff we're doing below:
24396 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
24399 enum machine_mode mode = GET_MODE (op1);
24400 const struct real_format *fmt;
24401 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
24404 /* load nextafter (0.5, 0.0) */
24405 fmt = REAL_MODE_FORMAT (mode);
24406 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
24407 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
24409 /* adj = copysign (0.5, op1) */
24410 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
24411 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
24413 /* adj = op1 + adj */
24414 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
24416 /* op0 = (imode)adj */
24417 expand_fix (op0, adj, 0);
24420 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
24423 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
24425 /* C code for the stuff we're doing below (for do_floor):
24427 xi -= (double)xi > op1 ? 1 : 0;
24430 enum machine_mode fmode = GET_MODE (op1);
24431 enum machine_mode imode = GET_MODE (op0);
24432 rtx ireg, freg, label, tmp;
24434 /* reg = (long)op1 */
24435 ireg = gen_reg_rtx (imode);
24436 expand_fix (ireg, op1, 0);
24438 /* freg = (double)reg */
24439 freg = gen_reg_rtx (fmode);
24440 expand_float (freg, ireg, 0);
24442 /* ireg = (freg > op1) ? ireg - 1 : ireg */
24443 label = ix86_expand_sse_compare_and_jump (UNLE,
24444 freg, op1, !do_floor);
24445 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
24446 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
24447 emit_move_insn (ireg, tmp);
24449 emit_label (label);
24450 LABEL_NUSES (label) = 1;
24452 emit_move_insn (op0, ireg);
24455 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
24456 result in OPERAND0. */
24458 ix86_expand_rint (rtx operand0, rtx operand1)
24460 /* C code for the stuff we're doing below:
24461 xa = fabs (operand1);
24462 if (!isless (xa, 2**52))
24464 xa = xa + 2**52 - 2**52;
24465 return copysign (xa, operand1);
24467 enum machine_mode mode = GET_MODE (operand0);
24468 rtx res, xa, label, TWO52, mask;
24470 res = gen_reg_rtx (mode);
24471 emit_move_insn (res, operand1);
24473 /* xa = abs (operand1) */
24474 xa = ix86_expand_sse_fabs (res, &mask);
24476 /* if (!isless (xa, TWO52)) goto label; */
24477 TWO52 = ix86_gen_TWO52 (mode);
24478 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24480 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24481 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
24483 ix86_sse_copysign_to_positive (res, xa, res, mask);
24485 emit_label (label);
24486 LABEL_NUSES (label) = 1;
24488 emit_move_insn (operand0, res);
24491 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
24494 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
24496 /* C code for the stuff we expand below.
24497 double xa = fabs (x), x2;
24498 if (!isless (xa, TWO52))
24500 xa = xa + TWO52 - TWO52;
24501 x2 = copysign (xa, x);
24510 enum machine_mode mode = GET_MODE (operand0);
24511 rtx xa, TWO52, tmp, label, one, res, mask;
24513 TWO52 = ix86_gen_TWO52 (mode);
24515 /* Temporary for holding the result, initialized to the input
24516 operand to ease control flow. */
24517 res = gen_reg_rtx (mode);
24518 emit_move_insn (res, operand1);
24520 /* xa = abs (operand1) */
24521 xa = ix86_expand_sse_fabs (res, &mask);
24523 /* if (!isless (xa, TWO52)) goto label; */
24524 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24526 /* xa = xa + TWO52 - TWO52; */
24527 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24528 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
24530 /* xa = copysign (xa, operand1) */
24531 ix86_sse_copysign_to_positive (xa, xa, res, mask);
24533 /* generate 1.0 or -1.0 */
24534 one = force_reg (mode,
24535 const_double_from_real_value (do_floor
24536 ? dconst1 : dconstm1, mode));
24538 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
24539 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
24540 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24541 gen_rtx_AND (mode, one, tmp)));
24542 /* We always need to subtract here to preserve signed zero. */
24543 tmp = expand_simple_binop (mode, MINUS,
24544 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24545 emit_move_insn (res, tmp);
24547 emit_label (label);
24548 LABEL_NUSES (label) = 1;
24550 emit_move_insn (operand0, res);
24553 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
24556 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
24558 /* C code for the stuff we expand below.
24559 double xa = fabs (x), x2;
24560 if (!isless (xa, TWO52))
24562 x2 = (double)(long)x;
24569 if (HONOR_SIGNED_ZEROS (mode))
24570 return copysign (x2, x);
24573 enum machine_mode mode = GET_MODE (operand0);
24574 rtx xa, xi, TWO52, tmp, label, one, res, mask;
24576 TWO52 = ix86_gen_TWO52 (mode);
24578 /* Temporary for holding the result, initialized to the input
24579 operand to ease control flow. */
24580 res = gen_reg_rtx (mode);
24581 emit_move_insn (res, operand1);
24583 /* xa = abs (operand1) */
24584 xa = ix86_expand_sse_fabs (res, &mask);
24586 /* if (!isless (xa, TWO52)) goto label; */
24587 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24589 /* xa = (double)(long)x */
24590 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
24591 expand_fix (xi, res, 0);
24592 expand_float (xa, xi, 0);
24595 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
24597 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
24598 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
24599 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24600 gen_rtx_AND (mode, one, tmp)));
24601 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
24602 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24603 emit_move_insn (res, tmp);
24605 if (HONOR_SIGNED_ZEROS (mode))
24606 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
24608 emit_label (label);
24609 LABEL_NUSES (label) = 1;
24611 emit_move_insn (operand0, res);
24614 /* Expand SSE sequence for computing round from OPERAND1 storing
24615 into OPERAND0. Sequence that works without relying on DImode truncation
24616 via cvttsd2siq that is only available on 64bit targets. */
24618 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
24620 /* C code for the stuff we expand below.
24621 double xa = fabs (x), xa2, x2;
24622 if (!isless (xa, TWO52))
24624 Using the absolute value and copying back sign makes
24625 -0.0 -> -0.0 correct.
24626 xa2 = xa + TWO52 - TWO52;
24631 else if (dxa > 0.5)
24633 x2 = copysign (xa2, x);
24636 enum machine_mode mode = GET_MODE (operand0);
24637 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
24639 TWO52 = ix86_gen_TWO52 (mode);
24641 /* Temporary for holding the result, initialized to the input
24642 operand to ease control flow. */
24643 res = gen_reg_rtx (mode);
24644 emit_move_insn (res, operand1);
24646 /* xa = abs (operand1) */
24647 xa = ix86_expand_sse_fabs (res, &mask);
24649 /* if (!isless (xa, TWO52)) goto label; */
24650 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24652 /* xa2 = xa + TWO52 - TWO52; */
24653 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24654 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
24656 /* dxa = xa2 - xa; */
24657 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
24659 /* generate 0.5, 1.0 and -0.5 */
24660 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
24661 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
24662 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
24666 tmp = gen_reg_rtx (mode);
24667 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
24668 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
24669 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24670 gen_rtx_AND (mode, one, tmp)));
24671 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24672 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
24673 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
24674 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24675 gen_rtx_AND (mode, one, tmp)));
24676 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
24678 /* res = copysign (xa2, operand1) */
24679 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
24681 emit_label (label);
24682 LABEL_NUSES (label) = 1;
24684 emit_move_insn (operand0, res);
24687 /* Expand SSE sequence for computing trunc from OPERAND1 storing
24690 ix86_expand_trunc (rtx operand0, rtx operand1)
24692 /* C code for SSE variant we expand below.
24693 double xa = fabs (x), x2;
24694 if (!isless (xa, TWO52))
24696 x2 = (double)(long)x;
24697 if (HONOR_SIGNED_ZEROS (mode))
24698 return copysign (x2, x);
24701 enum machine_mode mode = GET_MODE (operand0);
24702 rtx xa, xi, TWO52, label, res, mask;
24704 TWO52 = ix86_gen_TWO52 (mode);
24706 /* Temporary for holding the result, initialized to the input
24707 operand to ease control flow. */
24708 res = gen_reg_rtx (mode);
24709 emit_move_insn (res, operand1);
24711 /* xa = abs (operand1) */
24712 xa = ix86_expand_sse_fabs (res, &mask);
24714 /* if (!isless (xa, TWO52)) goto label; */
24715 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24717 /* x = (double)(long)x */
24718 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
24719 expand_fix (xi, res, 0);
24720 expand_float (res, xi, 0);
24722 if (HONOR_SIGNED_ZEROS (mode))
24723 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
24725 emit_label (label);
24726 LABEL_NUSES (label) = 1;
24728 emit_move_insn (operand0, res);
24731 /* Expand SSE sequence for computing trunc from OPERAND1 storing
24734 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
24736 enum machine_mode mode = GET_MODE (operand0);
24737 rtx xa, mask, TWO52, label, one, res, smask, tmp;
24739 /* C code for SSE variant we expand below.
24740 double xa = fabs (x), x2;
24741 if (!isless (xa, TWO52))
24743 xa2 = xa + TWO52 - TWO52;
24747 x2 = copysign (xa2, x);
24751 TWO52 = ix86_gen_TWO52 (mode);
24753 /* Temporary for holding the result, initialized to the input
24754 operand to ease control flow. */
24755 res = gen_reg_rtx (mode);
24756 emit_move_insn (res, operand1);
24758 /* xa = abs (operand1) */
24759 xa = ix86_expand_sse_fabs (res, &smask);
24761 /* if (!isless (xa, TWO52)) goto label; */
24762 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24764 /* res = xa + TWO52 - TWO52; */
24765 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24766 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
24767 emit_move_insn (res, tmp);
24770 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
24772 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
24773 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
24774 emit_insn (gen_rtx_SET (VOIDmode, mask,
24775 gen_rtx_AND (mode, mask, one)));
24776 tmp = expand_simple_binop (mode, MINUS,
24777 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
24778 emit_move_insn (res, tmp);
24780 /* res = copysign (res, operand1) */
24781 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
24783 emit_label (label);
24784 LABEL_NUSES (label) = 1;
24786 emit_move_insn (operand0, res);
24789 /* Expand SSE sequence for computing round from OPERAND1 storing
24792 ix86_expand_round (rtx operand0, rtx operand1)
24794 /* C code for the stuff we're doing below:
24795 double xa = fabs (x);
24796 if (!isless (xa, TWO52))
24798 xa = (double)(long)(xa + nextafter (0.5, 0.0));
24799 return copysign (xa, x);
24801 enum machine_mode mode = GET_MODE (operand0);
24802 rtx res, TWO52, xa, label, xi, half, mask;
24803 const struct real_format *fmt;
24804 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
24806 /* Temporary for holding the result, initialized to the input
24807 operand to ease control flow. */
24808 res = gen_reg_rtx (mode);
24809 emit_move_insn (res, operand1);
24811 TWO52 = ix86_gen_TWO52 (mode);
24812 xa = ix86_expand_sse_fabs (res, &mask);
24813 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24815 /* load nextafter (0.5, 0.0) */
24816 fmt = REAL_MODE_FORMAT (mode);
24817 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
24818 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
24820 /* xa = xa + 0.5 */
24821 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
24822 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
24824 /* xa = (double)(int64_t)xa */
24825 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
24826 expand_fix (xi, xa, 0);
24827 expand_float (xa, xi, 0);
24829 /* res = copysign (xa, operand1) */
24830 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
24832 emit_label (label);
24833 LABEL_NUSES (label) = 1;
24835 emit_move_insn (operand0, res);
24839 /* Validate whether a SSE5 instruction is valid or not.
24840 OPERANDS is the array of operands.
24841 NUM is the number of operands.
24842 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
24843 NUM_MEMORY is the maximum number of memory operands to accept. */
24844 bool ix86_sse5_valid_op_p (rtx operands[], rtx insn, int num, bool uses_oc0, int num_memory)
24850 /* Count the number of memory arguments */
24853 for (i = 0; i < num; i++)
24855 enum machine_mode mode = GET_MODE (operands[i]);
24856 if (register_operand (operands[i], mode))
24859 else if (memory_operand (operands[i], mode))
24861 mem_mask |= (1 << i);
24867 rtx pattern = PATTERN (insn);
24869 /* allow 0 for pcmov */
24870 if (GET_CODE (pattern) != SET
24871 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
24873 || operands[i] != CONST0_RTX (mode))
24878 /* If there were no memory operations, allow the insn */
24882 /* Do not allow the destination register to be a memory operand. */
24883 else if (mem_mask & (1 << 0))
24886 /* If there are too many memory operations, disallow the instruction. While
24887 the hardware only allows 1 memory reference, before register allocation
24888 for some insns, we allow two memory operations sometimes in order to allow
24889 code like the following to be optimized:
24891 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
24893 or similar cases that are vectorized into using the fmaddss
24895 else if (mem_count > num_memory)
24898 /* Don't allow more than one memory operation if not optimizing. */
24899 else if (mem_count > 1 && !optimize)
24902 else if (num == 4 && mem_count == 1)
24904 /* formats (destination is the first argument), example fmaddss:
24905 xmm1, xmm1, xmm2, xmm3/mem
24906 xmm1, xmm1, xmm2/mem, xmm3
24907 xmm1, xmm2, xmm3/mem, xmm1
24908 xmm1, xmm2/mem, xmm3, xmm1 */
24910 return ((mem_mask == (1 << 1))
24911 || (mem_mask == (1 << 2))
24912 || (mem_mask == (1 << 3)));
24914 /* format, example pmacsdd:
24915 xmm1, xmm2, xmm3/mem, xmm1 */
24917 return (mem_mask == (1 << 2));
24920 else if (num == 4 && num_memory == 2)
24922 /* If there are two memory operations, we can load one of the memory ops
24923 into the destination register. This is for optimizing the
24924 multiply/add ops, which the combiner has optimized both the multiply
24925 and the add insns to have a memory operation. We have to be careful
24926 that the destination doesn't overlap with the inputs. */
24927 rtx op0 = operands[0];
24929 if (reg_mentioned_p (op0, operands[1])
24930 || reg_mentioned_p (op0, operands[2])
24931 || reg_mentioned_p (op0, operands[3]))
24934 /* formats (destination is the first argument), example fmaddss:
24935 xmm1, xmm1, xmm2, xmm3/mem
24936 xmm1, xmm1, xmm2/mem, xmm3
24937 xmm1, xmm2, xmm3/mem, xmm1
24938 xmm1, xmm2/mem, xmm3, xmm1
24940 For the oc0 case, we will load either operands[1] or operands[3] into
24941 operands[0], so any combination of 2 memory operands is ok. */
24945 /* format, example pmacsdd:
24946 xmm1, xmm2, xmm3/mem, xmm1
24948 For the integer multiply/add instructions be more restrictive and
24949 require operands[2] and operands[3] to be the memory operands. */
24951 return (mem_mask == ((1 << 2) | (1 << 3)));
24954 else if (num == 3 && num_memory == 1)
24956 /* formats, example protb:
24957 xmm1, xmm2, xmm3/mem
24958 xmm1, xmm2/mem, xmm3 */
24960 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
24962 /* format, example comeq:
24963 xmm1, xmm2, xmm3/mem */
24965 return (mem_mask == (1 << 2));
24969 gcc_unreachable ();
24975 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
24976 hardware will allow by using the destination register to load one of the
24977 memory operations. Presently this is used by the multiply/add routines to
24978 allow 2 memory references. */
24981 ix86_expand_sse5_multiple_memory (rtx operands[],
24983 enum machine_mode mode)
24985 rtx op0 = operands[0];
24987 || memory_operand (op0, mode)
24988 || reg_mentioned_p (op0, operands[1])
24989 || reg_mentioned_p (op0, operands[2])
24990 || reg_mentioned_p (op0, operands[3]))
24991 gcc_unreachable ();
24993 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
24994 the destination register. */
24995 if (memory_operand (operands[1], mode))
24997 emit_move_insn (op0, operands[1]);
25000 else if (memory_operand (operands[3], mode))
25002 emit_move_insn (op0, operands[3]);
25006 gcc_unreachable ();
25012 /* Table of valid machine attributes. */
25013 static const struct attribute_spec ix86_attribute_table[] =
25015 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
25016 /* Stdcall attribute says callee is responsible for popping arguments
25017 if they are not variable. */
25018 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25019 /* Fastcall attribute says callee is responsible for popping arguments
25020 if they are not variable. */
25021 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25022 /* Cdecl attribute says the callee is a normal C declaration */
25023 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25024 /* Regparm attribute specifies how many integer arguments are to be
25025 passed in registers. */
25026 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
25027 /* Sseregparm attribute says we are using x86_64 calling conventions
25028 for FP arguments. */
25029 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25030 /* force_align_arg_pointer says this function realigns the stack at entry. */
25031 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
25032 false, true, true, ix86_handle_cconv_attribute },
25033 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25034 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
25035 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
25036 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
25038 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25039 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25040 #ifdef SUBTARGET_ATTRIBUTE_TABLE
25041 SUBTARGET_ATTRIBUTE_TABLE,
25043 { NULL, 0, 0, false, false, false, NULL }
25046 /* Implement targetm.vectorize.builtin_vectorization_cost. */
25048 x86_builtin_vectorization_cost (bool runtime_test)
25050 /* If the branch of the runtime test is taken - i.e. - the vectorized
25051 version is skipped - this incurs a misprediction cost (because the
25052 vectorized version is expected to be the fall-through). So we subtract
25053 the latency of a mispredicted branch from the costs that are incured
25054 when the vectorized version is executed.
25056 TODO: The values in individual target tables have to be tuned or new
25057 fields may be needed. For eg. on K8, the default branch path is the
25058 not-taken path. If the taken path is predicted correctly, the minimum
25059 penalty of going down the taken-path is 1 cycle. If the taken-path is
25060 not predicted correctly, then the minimum penalty is 10 cycles. */
25064 return (-(ix86_cost->cond_taken_branch_cost));
25070 /* Initialize the GCC target structure. */
25071 #undef TARGET_ATTRIBUTE_TABLE
25072 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
25073 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25074 # undef TARGET_MERGE_DECL_ATTRIBUTES
25075 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
25078 #undef TARGET_COMP_TYPE_ATTRIBUTES
25079 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
25081 #undef TARGET_INIT_BUILTINS
25082 #define TARGET_INIT_BUILTINS ix86_init_builtins
25083 #undef TARGET_EXPAND_BUILTIN
25084 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
25086 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
25087 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
25088 ix86_builtin_vectorized_function
25090 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
25091 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
25093 #undef TARGET_BUILTIN_RECIPROCAL
25094 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
25096 #undef TARGET_ASM_FUNCTION_EPILOGUE
25097 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
25099 #undef TARGET_ENCODE_SECTION_INFO
25100 #ifndef SUBTARGET_ENCODE_SECTION_INFO
25101 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
25103 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
25106 #undef TARGET_ASM_OPEN_PAREN
25107 #define TARGET_ASM_OPEN_PAREN ""
25108 #undef TARGET_ASM_CLOSE_PAREN
25109 #define TARGET_ASM_CLOSE_PAREN ""
25111 #undef TARGET_ASM_ALIGNED_HI_OP
25112 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
25113 #undef TARGET_ASM_ALIGNED_SI_OP
25114 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
25116 #undef TARGET_ASM_ALIGNED_DI_OP
25117 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
25120 #undef TARGET_ASM_UNALIGNED_HI_OP
25121 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
25122 #undef TARGET_ASM_UNALIGNED_SI_OP
25123 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
25124 #undef TARGET_ASM_UNALIGNED_DI_OP
25125 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
25127 #undef TARGET_SCHED_ADJUST_COST
25128 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
25129 #undef TARGET_SCHED_ISSUE_RATE
25130 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
25131 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
25132 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
25133 ia32_multipass_dfa_lookahead
25135 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
25136 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
25139 #undef TARGET_HAVE_TLS
25140 #define TARGET_HAVE_TLS true
25142 #undef TARGET_CANNOT_FORCE_CONST_MEM
25143 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
25144 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
25145 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
25147 #undef TARGET_DELEGITIMIZE_ADDRESS
25148 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
25150 #undef TARGET_MS_BITFIELD_LAYOUT_P
25151 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
25154 #undef TARGET_BINDS_LOCAL_P
25155 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
25157 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25158 #undef TARGET_BINDS_LOCAL_P
25159 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
25162 #undef TARGET_ASM_OUTPUT_MI_THUNK
25163 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
25164 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
25165 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
25167 #undef TARGET_ASM_FILE_START
25168 #define TARGET_ASM_FILE_START x86_file_start
25170 #undef TARGET_DEFAULT_TARGET_FLAGS
25171 #define TARGET_DEFAULT_TARGET_FLAGS \
25173 | TARGET_SUBTARGET_DEFAULT \
25174 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
25176 #undef TARGET_HANDLE_OPTION
25177 #define TARGET_HANDLE_OPTION ix86_handle_option
25179 #undef TARGET_RTX_COSTS
25180 #define TARGET_RTX_COSTS ix86_rtx_costs
25181 #undef TARGET_ADDRESS_COST
25182 #define TARGET_ADDRESS_COST ix86_address_cost
25184 #undef TARGET_FIXED_CONDITION_CODE_REGS
25185 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
25186 #undef TARGET_CC_MODES_COMPATIBLE
25187 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
25189 #undef TARGET_MACHINE_DEPENDENT_REORG
25190 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
25192 #undef TARGET_BUILD_BUILTIN_VA_LIST
25193 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
25195 #undef TARGET_MD_ASM_CLOBBERS
25196 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
25198 #undef TARGET_PROMOTE_PROTOTYPES
25199 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
25200 #undef TARGET_STRUCT_VALUE_RTX
25201 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
25202 #undef TARGET_SETUP_INCOMING_VARARGS
25203 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
25204 #undef TARGET_MUST_PASS_IN_STACK
25205 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
25206 #undef TARGET_PASS_BY_REFERENCE
25207 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
25208 #undef TARGET_INTERNAL_ARG_POINTER
25209 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
25210 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
25211 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
25212 #undef TARGET_STRICT_ARGUMENT_NAMING
25213 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
25215 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
25216 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
25218 #undef TARGET_SCALAR_MODE_SUPPORTED_P
25219 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
25221 #undef TARGET_VECTOR_MODE_SUPPORTED_P
25222 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
25224 #undef TARGET_C_MODE_FOR_SUFFIX
25225 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
25228 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
25229 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
25232 #ifdef SUBTARGET_INSERT_ATTRIBUTES
25233 #undef TARGET_INSERT_ATTRIBUTES
25234 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
25237 #undef TARGET_MANGLE_TYPE
25238 #define TARGET_MANGLE_TYPE ix86_mangle_type
25240 #undef TARGET_STACK_PROTECT_FAIL
25241 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
25243 #undef TARGET_FUNCTION_VALUE
25244 #define TARGET_FUNCTION_VALUE ix86_function_value
25246 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
25247 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
25249 struct gcc_target targetm = TARGET_INITIALIZER;
25251 #include "gt-i386.h"
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