1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
53 #ifndef CHECK_STACK_LIMIT
54 #define CHECK_STACK_LIMIT (-1)
57 /* Return index of given mode in mult and division cost tables. */
58 #define MODE_INDEX(mode) \
59 ((mode) == QImode ? 0 \
60 : (mode) == HImode ? 1 \
61 : (mode) == SImode ? 2 \
62 : (mode) == DImode ? 3 \
65 /* Processor costs (relative to an add) */
67 struct processor_costs size_cost = { /* costs for tunning for size */
68 2, /* cost of an add instruction */
69 3, /* cost of a lea instruction */
70 2, /* variable shift costs */
71 3, /* constant shift costs */
72 {3, 3, 3, 3, 5}, /* cost of starting a multiply */
73 0, /* cost of multiply per each bit set */
74 {3, 3, 3, 3, 5}, /* cost of a divide/mod */
75 3, /* cost of movsx */
76 3, /* cost of movzx */
79 2, /* cost for loading QImode using movzbl */
80 {2, 2, 2}, /* cost of loading integer registers
81 in QImode, HImode and SImode.
82 Relative to reg-reg move (2). */
83 {2, 2, 2}, /* cost of storing integer registers */
84 2, /* cost of reg,reg fld/fst */
85 {2, 2, 2}, /* cost of loading fp registers
86 in SFmode, DFmode and XFmode */
87 {2, 2, 2}, /* cost of loading integer registers */
88 3, /* cost of moving MMX register */
89 {3, 3}, /* cost of loading MMX registers
90 in SImode and DImode */
91 {3, 3}, /* cost of storing MMX registers
92 in SImode and DImode */
93 3, /* cost of moving SSE register */
94 {3, 3, 3}, /* cost of loading SSE registers
95 in SImode, DImode and TImode */
96 {3, 3, 3}, /* cost of storing SSE registers
97 in SImode, DImode and TImode */
98 3, /* MMX or SSE register to integer */
99 0, /* size of prefetch block */
100 0, /* number of parallel prefetches */
102 2, /* cost of FADD and FSUB insns. */
103 2, /* cost of FMUL instruction. */
104 2, /* cost of FDIV instruction. */
105 2, /* cost of FABS instruction. */
106 2, /* cost of FCHS instruction. */
107 2, /* cost of FSQRT instruction. */
110 /* Processor costs (relative to an add) */
112 struct processor_costs i386_cost = { /* 386 specific costs */
113 1, /* cost of an add instruction */
114 1, /* cost of a lea instruction */
115 3, /* variable shift costs */
116 2, /* constant shift costs */
117 {6, 6, 6, 6, 6}, /* cost of starting a multiply */
118 1, /* cost of multiply per each bit set */
119 {23, 23, 23, 23, 23}, /* cost of a divide/mod */
120 3, /* cost of movsx */
121 2, /* cost of movzx */
122 15, /* "large" insn */
124 4, /* cost for loading QImode using movzbl */
125 {2, 4, 2}, /* cost of loading integer registers
126 in QImode, HImode and SImode.
127 Relative to reg-reg move (2). */
128 {2, 4, 2}, /* cost of storing integer registers */
129 2, /* cost of reg,reg fld/fst */
130 {8, 8, 8}, /* cost of loading fp registers
131 in SFmode, DFmode and XFmode */
132 {8, 8, 8}, /* cost of loading integer registers */
133 2, /* cost of moving MMX register */
134 {4, 8}, /* cost of loading MMX registers
135 in SImode and DImode */
136 {4, 8}, /* cost of storing MMX registers
137 in SImode and DImode */
138 2, /* cost of moving SSE register */
139 {4, 8, 16}, /* cost of loading SSE registers
140 in SImode, DImode and TImode */
141 {4, 8, 16}, /* cost of storing SSE registers
142 in SImode, DImode and TImode */
143 3, /* MMX or SSE register to integer */
144 0, /* size of prefetch block */
145 0, /* number of parallel prefetches */
147 23, /* cost of FADD and FSUB insns. */
148 27, /* cost of FMUL instruction. */
149 88, /* cost of FDIV instruction. */
150 22, /* cost of FABS instruction. */
151 24, /* cost of FCHS instruction. */
152 122, /* cost of FSQRT instruction. */
156 struct processor_costs i486_cost = { /* 486 specific costs */
157 1, /* cost of an add instruction */
158 1, /* cost of a lea instruction */
159 3, /* variable shift costs */
160 2, /* constant shift costs */
161 {12, 12, 12, 12, 12}, /* cost of starting a multiply */
162 1, /* cost of multiply per each bit set */
163 {40, 40, 40, 40, 40}, /* cost of a divide/mod */
164 3, /* cost of movsx */
165 2, /* cost of movzx */
166 15, /* "large" insn */
168 4, /* cost for loading QImode using movzbl */
169 {2, 4, 2}, /* cost of loading integer registers
170 in QImode, HImode and SImode.
171 Relative to reg-reg move (2). */
172 {2, 4, 2}, /* cost of storing integer registers */
173 2, /* cost of reg,reg fld/fst */
174 {8, 8, 8}, /* cost of loading fp registers
175 in SFmode, DFmode and XFmode */
176 {8, 8, 8}, /* cost of loading integer registers */
177 2, /* cost of moving MMX register */
178 {4, 8}, /* cost of loading MMX registers
179 in SImode and DImode */
180 {4, 8}, /* cost of storing MMX registers
181 in SImode and DImode */
182 2, /* cost of moving SSE register */
183 {4, 8, 16}, /* cost of loading SSE registers
184 in SImode, DImode and TImode */
185 {4, 8, 16}, /* cost of storing SSE registers
186 in SImode, DImode and TImode */
187 3, /* MMX or SSE register to integer */
188 0, /* size of prefetch block */
189 0, /* number of parallel prefetches */
191 8, /* cost of FADD and FSUB insns. */
192 16, /* cost of FMUL instruction. */
193 73, /* cost of FDIV instruction. */
194 3, /* cost of FABS instruction. */
195 3, /* cost of FCHS instruction. */
196 83, /* cost of FSQRT instruction. */
200 struct processor_costs pentium_cost = {
201 1, /* cost of an add instruction */
202 1, /* cost of a lea instruction */
203 4, /* variable shift costs */
204 1, /* constant shift costs */
205 {11, 11, 11, 11, 11}, /* cost of starting a multiply */
206 0, /* cost of multiply per each bit set */
207 {25, 25, 25, 25, 25}, /* cost of a divide/mod */
208 3, /* cost of movsx */
209 2, /* cost of movzx */
210 8, /* "large" insn */
212 6, /* cost for loading QImode using movzbl */
213 {2, 4, 2}, /* cost of loading integer registers
214 in QImode, HImode and SImode.
215 Relative to reg-reg move (2). */
216 {2, 4, 2}, /* cost of storing integer registers */
217 2, /* cost of reg,reg fld/fst */
218 {2, 2, 6}, /* cost of loading fp registers
219 in SFmode, DFmode and XFmode */
220 {4, 4, 6}, /* cost of loading integer registers */
221 8, /* cost of moving MMX register */
222 {8, 8}, /* cost of loading MMX registers
223 in SImode and DImode */
224 {8, 8}, /* cost of storing MMX registers
225 in SImode and DImode */
226 2, /* cost of moving SSE register */
227 {4, 8, 16}, /* cost of loading SSE registers
228 in SImode, DImode and TImode */
229 {4, 8, 16}, /* cost of storing SSE registers
230 in SImode, DImode and TImode */
231 3, /* MMX or SSE register to integer */
232 0, /* size of prefetch block */
233 0, /* number of parallel prefetches */
235 3, /* cost of FADD and FSUB insns. */
236 3, /* cost of FMUL instruction. */
237 39, /* cost of FDIV instruction. */
238 1, /* cost of FABS instruction. */
239 1, /* cost of FCHS instruction. */
240 70, /* cost of FSQRT instruction. */
244 struct processor_costs pentiumpro_cost = {
245 1, /* cost of an add instruction */
246 1, /* cost of a lea instruction */
247 1, /* variable shift costs */
248 1, /* constant shift costs */
249 {4, 4, 4, 4, 4}, /* cost of starting a multiply */
250 0, /* cost of multiply per each bit set */
251 {17, 17, 17, 17, 17}, /* cost of a divide/mod */
252 1, /* cost of movsx */
253 1, /* cost of movzx */
254 8, /* "large" insn */
256 2, /* cost for loading QImode using movzbl */
257 {4, 4, 4}, /* cost of loading integer registers
258 in QImode, HImode and SImode.
259 Relative to reg-reg move (2). */
260 {2, 2, 2}, /* cost of storing integer registers */
261 2, /* cost of reg,reg fld/fst */
262 {2, 2, 6}, /* cost of loading fp registers
263 in SFmode, DFmode and XFmode */
264 {4, 4, 6}, /* cost of loading integer registers */
265 2, /* cost of moving MMX register */
266 {2, 2}, /* cost of loading MMX registers
267 in SImode and DImode */
268 {2, 2}, /* cost of storing MMX registers
269 in SImode and DImode */
270 2, /* cost of moving SSE register */
271 {2, 2, 8}, /* cost of loading SSE registers
272 in SImode, DImode and TImode */
273 {2, 2, 8}, /* cost of storing SSE registers
274 in SImode, DImode and TImode */
275 3, /* MMX or SSE register to integer */
276 32, /* size of prefetch block */
277 6, /* number of parallel prefetches */
279 3, /* cost of FADD and FSUB insns. */
280 5, /* cost of FMUL instruction. */
281 56, /* cost of FDIV instruction. */
282 2, /* cost of FABS instruction. */
283 2, /* cost of FCHS instruction. */
284 56, /* cost of FSQRT instruction. */
288 struct processor_costs k6_cost = {
289 1, /* cost of an add instruction */
290 2, /* cost of a lea instruction */
291 1, /* variable shift costs */
292 1, /* constant shift costs */
293 {3, 3, 3, 3, 3}, /* cost of starting a multiply */
294 0, /* cost of multiply per each bit set */
295 {18, 18, 18, 18, 18}, /* cost of a divide/mod */
296 2, /* cost of movsx */
297 2, /* cost of movzx */
298 8, /* "large" insn */
300 3, /* cost for loading QImode using movzbl */
301 {4, 5, 4}, /* cost of loading integer registers
302 in QImode, HImode and SImode.
303 Relative to reg-reg move (2). */
304 {2, 3, 2}, /* cost of storing integer registers */
305 4, /* cost of reg,reg fld/fst */
306 {6, 6, 6}, /* cost of loading fp registers
307 in SFmode, DFmode and XFmode */
308 {4, 4, 4}, /* cost of loading integer registers */
309 2, /* cost of moving MMX register */
310 {2, 2}, /* cost of loading MMX registers
311 in SImode and DImode */
312 {2, 2}, /* cost of storing MMX registers
313 in SImode and DImode */
314 2, /* cost of moving SSE register */
315 {2, 2, 8}, /* cost of loading SSE registers
316 in SImode, DImode and TImode */
317 {2, 2, 8}, /* cost of storing SSE registers
318 in SImode, DImode and TImode */
319 6, /* MMX or SSE register to integer */
320 32, /* size of prefetch block */
321 1, /* number of parallel prefetches */
323 2, /* cost of FADD and FSUB insns. */
324 2, /* cost of FMUL instruction. */
325 56, /* cost of FDIV instruction. */
326 2, /* cost of FABS instruction. */
327 2, /* cost of FCHS instruction. */
328 56, /* cost of FSQRT instruction. */
332 struct processor_costs athlon_cost = {
333 1, /* cost of an add instruction */
334 2, /* cost of a lea instruction */
335 1, /* variable shift costs */
336 1, /* constant shift costs */
337 {5, 5, 5, 5, 5}, /* cost of starting a multiply */
338 0, /* cost of multiply per each bit set */
339 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
340 1, /* cost of movsx */
341 1, /* cost of movzx */
342 8, /* "large" insn */
344 4, /* cost for loading QImode using movzbl */
345 {3, 4, 3}, /* cost of loading integer registers
346 in QImode, HImode and SImode.
347 Relative to reg-reg move (2). */
348 {3, 4, 3}, /* cost of storing integer registers */
349 4, /* cost of reg,reg fld/fst */
350 {4, 4, 12}, /* cost of loading fp registers
351 in SFmode, DFmode and XFmode */
352 {6, 6, 8}, /* cost of loading integer registers */
353 2, /* cost of moving MMX register */
354 {4, 4}, /* cost of loading MMX registers
355 in SImode and DImode */
356 {4, 4}, /* cost of storing MMX registers
357 in SImode and DImode */
358 2, /* cost of moving SSE register */
359 {4, 4, 6}, /* cost of loading SSE registers
360 in SImode, DImode and TImode */
361 {4, 4, 5}, /* cost of storing SSE registers
362 in SImode, DImode and TImode */
363 5, /* MMX or SSE register to integer */
364 64, /* size of prefetch block */
365 6, /* number of parallel prefetches */
367 4, /* cost of FADD and FSUB insns. */
368 4, /* cost of FMUL instruction. */
369 24, /* cost of FDIV instruction. */
370 2, /* cost of FABS instruction. */
371 2, /* cost of FCHS instruction. */
372 35, /* cost of FSQRT instruction. */
376 struct processor_costs k8_cost = {
377 1, /* cost of an add instruction */
378 2, /* cost of a lea instruction */
379 1, /* variable shift costs */
380 1, /* constant shift costs */
381 {3, 4, 3, 4, 5}, /* cost of starting a multiply */
382 0, /* cost of multiply per each bit set */
383 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
384 1, /* cost of movsx */
385 1, /* cost of movzx */
386 8, /* "large" insn */
388 4, /* cost for loading QImode using movzbl */
389 {3, 4, 3}, /* cost of loading integer registers
390 in QImode, HImode and SImode.
391 Relative to reg-reg move (2). */
392 {3, 4, 3}, /* cost of storing integer registers */
393 4, /* cost of reg,reg fld/fst */
394 {4, 4, 12}, /* cost of loading fp registers
395 in SFmode, DFmode and XFmode */
396 {6, 6, 8}, /* cost of loading integer registers */
397 2, /* cost of moving MMX register */
398 {3, 3}, /* cost of loading MMX registers
399 in SImode and DImode */
400 {4, 4}, /* cost of storing MMX registers
401 in SImode and DImode */
402 2, /* cost of moving SSE register */
403 {4, 3, 6}, /* cost of loading SSE registers
404 in SImode, DImode and TImode */
405 {4, 4, 5}, /* cost of storing SSE registers
406 in SImode, DImode and TImode */
407 5, /* MMX or SSE register to integer */
408 64, /* size of prefetch block */
409 6, /* number of parallel prefetches */
411 4, /* cost of FADD and FSUB insns. */
412 4, /* cost of FMUL instruction. */
413 19, /* cost of FDIV instruction. */
414 2, /* cost of FABS instruction. */
415 2, /* cost of FCHS instruction. */
416 35, /* cost of FSQRT instruction. */
420 struct processor_costs pentium4_cost = {
421 1, /* cost of an add instruction */
422 3, /* cost of a lea instruction */
423 4, /* variable shift costs */
424 4, /* constant shift costs */
425 {15, 15, 15, 15, 15}, /* cost of starting a multiply */
426 0, /* cost of multiply per each bit set */
427 {56, 56, 56, 56, 56}, /* cost of a divide/mod */
428 1, /* cost of movsx */
429 1, /* cost of movzx */
430 16, /* "large" insn */
432 2, /* cost for loading QImode using movzbl */
433 {4, 5, 4}, /* cost of loading integer registers
434 in QImode, HImode and SImode.
435 Relative to reg-reg move (2). */
436 {2, 3, 2}, /* cost of storing integer registers */
437 2, /* cost of reg,reg fld/fst */
438 {2, 2, 6}, /* cost of loading fp registers
439 in SFmode, DFmode and XFmode */
440 {4, 4, 6}, /* cost of loading integer registers */
441 2, /* cost of moving MMX register */
442 {2, 2}, /* cost of loading MMX registers
443 in SImode and DImode */
444 {2, 2}, /* cost of storing MMX registers
445 in SImode and DImode */
446 12, /* cost of moving SSE register */
447 {12, 12, 12}, /* cost of loading SSE registers
448 in SImode, DImode and TImode */
449 {2, 2, 8}, /* cost of storing SSE registers
450 in SImode, DImode and TImode */
451 10, /* MMX or SSE register to integer */
452 64, /* size of prefetch block */
453 6, /* number of parallel prefetches */
455 5, /* cost of FADD and FSUB insns. */
456 7, /* cost of FMUL instruction. */
457 43, /* cost of FDIV instruction. */
458 2, /* cost of FABS instruction. */
459 2, /* cost of FCHS instruction. */
460 43, /* cost of FSQRT instruction. */
464 struct processor_costs nocona_cost = {
465 1, /* cost of an add instruction */
466 1, /* cost of a lea instruction */
467 1, /* variable shift costs */
468 1, /* constant shift costs */
469 {10, 10, 10, 10, 10}, /* cost of starting a multiply */
470 0, /* cost of multiply per each bit set */
471 {66, 66, 66, 66, 66}, /* cost of a divide/mod */
472 1, /* cost of movsx */
473 1, /* cost of movzx */
474 16, /* "large" insn */
476 4, /* cost for loading QImode using movzbl */
477 {4, 4, 4}, /* cost of loading integer registers
478 in QImode, HImode and SImode.
479 Relative to reg-reg move (2). */
480 {4, 4, 4}, /* cost of storing integer registers */
481 3, /* cost of reg,reg fld/fst */
482 {12, 12, 12}, /* cost of loading fp registers
483 in SFmode, DFmode and XFmode */
484 {4, 4, 4}, /* cost of loading integer registers */
485 6, /* cost of moving MMX register */
486 {12, 12}, /* cost of loading MMX registers
487 in SImode and DImode */
488 {12, 12}, /* cost of storing MMX registers
489 in SImode and DImode */
490 6, /* cost of moving SSE register */
491 {12, 12, 12}, /* cost of loading SSE registers
492 in SImode, DImode and TImode */
493 {12, 12, 12}, /* cost of storing SSE registers
494 in SImode, DImode and TImode */
495 8, /* MMX or SSE register to integer */
496 128, /* size of prefetch block */
497 8, /* number of parallel prefetches */
499 6, /* cost of FADD and FSUB insns. */
500 8, /* cost of FMUL instruction. */
501 40, /* cost of FDIV instruction. */
502 3, /* cost of FABS instruction. */
503 3, /* cost of FCHS instruction. */
504 44, /* cost of FSQRT instruction. */
507 const struct processor_costs *ix86_cost = &pentium_cost;
509 /* Processor feature/optimization bitmasks. */
510 #define m_386 (1<<PROCESSOR_I386)
511 #define m_486 (1<<PROCESSOR_I486)
512 #define m_PENT (1<<PROCESSOR_PENTIUM)
513 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
514 #define m_K6 (1<<PROCESSOR_K6)
515 #define m_ATHLON (1<<PROCESSOR_ATHLON)
516 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
517 #define m_K8 (1<<PROCESSOR_K8)
518 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
519 #define m_NOCONA (1<<PROCESSOR_NOCONA)
521 const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8;
522 const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
523 const int x86_zero_extend_with_and = m_486 | m_PENT;
524 const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA /* m_386 | m_K6 */;
525 const int x86_double_with_add = ~m_386;
526 const int x86_use_bit_test = m_386;
527 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6;
528 const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
529 const int x86_fisttp = m_NOCONA;
530 const int x86_3dnow_a = m_ATHLON_K8;
531 const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
532 /* Branch hints were put in P4 based on simulation result. But
533 after P4 was made, no performance benefit was observed with
534 branch hints. It also increases the code size. As the result,
535 icc never generates branch hints. */
536 const int x86_branch_hints = 0;
537 const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA;
538 const int x86_partial_reg_stall = m_PPRO;
539 const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
540 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT);
541 const int x86_use_mov0 = m_K6;
542 const int x86_use_cltd = ~(m_PENT | m_K6);
543 const int x86_read_modify_write = ~m_PENT;
544 const int x86_read_modify = ~(m_PENT | m_PPRO);
545 const int x86_split_long_moves = m_PPRO;
546 const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8;
547 const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
548 const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
549 const int x86_qimode_math = ~(0);
550 const int x86_promote_qi_regs = 0;
551 const int x86_himode_math = ~(m_PPRO);
552 const int x86_promote_hi_regs = m_PPRO;
553 const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA;
554 const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA;
555 const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA;
556 const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA;
557 const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO);
558 const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
559 const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
560 const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO;
561 const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO;
562 const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO;
563 const int x86_decompose_lea = m_PENT4 | m_NOCONA;
564 const int x86_shift1 = ~m_486;
565 const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
566 const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO;
567 /* Set for machines where the type and dependencies are resolved on SSE
568 register parts instead of whole registers, so we may maintain just
569 lower part of scalar values in proper format leaving the upper part
571 const int x86_sse_split_regs = m_ATHLON_K8;
572 const int x86_sse_typeless_stores = m_ATHLON_K8;
573 const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
574 const int x86_use_ffreep = m_ATHLON_K8;
575 const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
577 /* ??? Allowing interunit moves makes it all too easy for the compiler to put
578 integer data in xmm registers. Which results in pretty abysmal code. */
579 const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
581 const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO;
582 /* Some CPU cores are not able to predict more than 4 branch instructions in
583 the 16 byte window. */
584 const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
585 const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT;
586 const int x86_use_bt = m_ATHLON_K8;
587 /* Compare and exchange was added for 80486. */
588 const int x86_cmpxchg = ~m_386;
589 /* Exchange and add was added for 80486. */
590 const int x86_xadd = ~m_386;
592 /* In case the average insn count for single function invocation is
593 lower than this constant, emit fast (but longer) prologue and
595 #define FAST_PROLOGUE_INSN_COUNT 20
597 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
598 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
599 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
600 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
602 /* Array of the smallest class containing reg number REGNO, indexed by
603 REGNO. Used by REGNO_REG_CLASS in i386.h. */
605 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
608 AREG, DREG, CREG, BREG,
610 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
612 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
613 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
616 /* flags, fpsr, dirflag, frame */
617 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
618 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
620 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
622 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
623 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
624 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
628 /* The "default" register map used in 32bit mode. */
630 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
632 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
633 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
634 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
635 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
636 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
637 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
638 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
641 static int const x86_64_int_parameter_registers[6] =
643 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
644 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
647 static int const x86_64_int_return_registers[4] =
649 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
652 /* The "default" register map used in 64bit mode. */
653 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
655 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
656 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
657 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
658 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
659 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
660 8,9,10,11,12,13,14,15, /* extended integer registers */
661 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
664 /* Define the register numbers to be used in Dwarf debugging information.
665 The SVR4 reference port C compiler uses the following register numbers
666 in its Dwarf output code:
667 0 for %eax (gcc regno = 0)
668 1 for %ecx (gcc regno = 2)
669 2 for %edx (gcc regno = 1)
670 3 for %ebx (gcc regno = 3)
671 4 for %esp (gcc regno = 7)
672 5 for %ebp (gcc regno = 6)
673 6 for %esi (gcc regno = 4)
674 7 for %edi (gcc regno = 5)
675 The following three DWARF register numbers are never generated by
676 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
677 believes these numbers have these meanings.
678 8 for %eip (no gcc equivalent)
679 9 for %eflags (gcc regno = 17)
680 10 for %trapno (no gcc equivalent)
681 It is not at all clear how we should number the FP stack registers
682 for the x86 architecture. If the version of SDB on x86/svr4 were
683 a bit less brain dead with respect to floating-point then we would
684 have a precedent to follow with respect to DWARF register numbers
685 for x86 FP registers, but the SDB on x86/svr4 is so completely
686 broken with respect to FP registers that it is hardly worth thinking
687 of it as something to strive for compatibility with.
688 The version of x86/svr4 SDB I have at the moment does (partially)
689 seem to believe that DWARF register number 11 is associated with
690 the x86 register %st(0), but that's about all. Higher DWARF
691 register numbers don't seem to be associated with anything in
692 particular, and even for DWARF regno 11, SDB only seems to under-
693 stand that it should say that a variable lives in %st(0) (when
694 asked via an `=' command) if we said it was in DWARF regno 11,
695 but SDB still prints garbage when asked for the value of the
696 variable in question (via a `/' command).
697 (Also note that the labels SDB prints for various FP stack regs
698 when doing an `x' command are all wrong.)
699 Note that these problems generally don't affect the native SVR4
700 C compiler because it doesn't allow the use of -O with -g and
701 because when it is *not* optimizing, it allocates a memory
702 location for each floating-point variable, and the memory
703 location is what gets described in the DWARF AT_location
704 attribute for the variable in question.
705 Regardless of the severe mental illness of the x86/svr4 SDB, we
706 do something sensible here and we use the following DWARF
707 register numbers. Note that these are all stack-top-relative
709 11 for %st(0) (gcc regno = 8)
710 12 for %st(1) (gcc regno = 9)
711 13 for %st(2) (gcc regno = 10)
712 14 for %st(3) (gcc regno = 11)
713 15 for %st(4) (gcc regno = 12)
714 16 for %st(5) (gcc regno = 13)
715 17 for %st(6) (gcc regno = 14)
716 18 for %st(7) (gcc regno = 15)
718 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
720 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
721 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
722 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
723 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
724 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
725 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
726 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
729 /* Test and compare insns in i386.md store the information needed to
730 generate branch and scc insns here. */
732 rtx ix86_compare_op0 = NULL_RTX;
733 rtx ix86_compare_op1 = NULL_RTX;
734 rtx ix86_compare_emitted = NULL_RTX;
736 /* Size of the register save area. */
737 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
739 /* Define the structure for the machine field in struct function. */
741 struct stack_local_entry GTY(())
746 struct stack_local_entry *next;
749 /* Structure describing stack frame layout.
750 Stack grows downward:
756 saved frame pointer if frame_pointer_needed
757 <- HARD_FRAME_POINTER
763 > to_allocate <- FRAME_POINTER
775 int outgoing_arguments_size;
778 HOST_WIDE_INT to_allocate;
779 /* The offsets relative to ARG_POINTER. */
780 HOST_WIDE_INT frame_pointer_offset;
781 HOST_WIDE_INT hard_frame_pointer_offset;
782 HOST_WIDE_INT stack_pointer_offset;
784 /* When save_regs_using_mov is set, emit prologue using
785 move instead of push instructions. */
786 bool save_regs_using_mov;
789 /* Code model option. */
790 enum cmodel ix86_cmodel;
792 enum asm_dialect ix86_asm_dialect = ASM_ATT;
794 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
796 /* Which unit we are generating floating point math for. */
797 enum fpmath_unit ix86_fpmath;
799 /* Which cpu are we scheduling for. */
800 enum processor_type ix86_tune;
801 /* Which instruction set architecture to use. */
802 enum processor_type ix86_arch;
804 /* true if sse prefetch instruction is not NOOP. */
805 int x86_prefetch_sse;
807 /* ix86_regparm_string as a number */
808 static int ix86_regparm;
810 /* Preferred alignment for stack boundary in bits. */
811 unsigned int ix86_preferred_stack_boundary;
813 /* Values 1-5: see jump.c */
814 int ix86_branch_cost;
816 /* Variables which are this size or smaller are put in the data/bss
817 or ldata/lbss sections. */
819 int ix86_section_threshold = 65536;
821 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
822 char internal_label_prefix[16];
823 int internal_label_prefix_len;
825 static bool ix86_handle_option (size_t, const char *, int);
826 static void output_pic_addr_const (FILE *, rtx, int);
827 static void put_condition_code (enum rtx_code, enum machine_mode,
829 static const char *get_some_local_dynamic_name (void);
830 static int get_some_local_dynamic_name_1 (rtx *, void *);
831 static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
832 static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
834 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
835 static enum machine_mode ix86_cc_modes_compatible (enum machine_mode,
837 static rtx get_thread_pointer (int);
838 static rtx legitimize_tls_address (rtx, enum tls_model, int);
839 static void get_pc_thunk_name (char [32], unsigned int);
840 static rtx gen_push (rtx);
841 static int ix86_flags_dependant (rtx, rtx, enum attr_type);
842 static int ix86_agi_dependant (rtx, rtx, enum attr_type);
843 static struct machine_function * ix86_init_machine_status (void);
844 static int ix86_split_to_parts (rtx, rtx *, enum machine_mode);
845 static int ix86_nsaved_regs (void);
846 static void ix86_emit_save_regs (void);
847 static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT);
848 static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int);
849 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT);
850 static HOST_WIDE_INT ix86_GOT_alias_set (void);
851 static void ix86_adjust_counter (rtx, HOST_WIDE_INT);
852 static rtx ix86_expand_aligntest (rtx, int);
853 static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx);
854 static int ix86_issue_rate (void);
855 static int ix86_adjust_cost (rtx, rtx, rtx, int);
856 static int ia32_multipass_dfa_lookahead (void);
857 static void ix86_init_mmx_sse_builtins (void);
858 static rtx x86_this_parameter (tree);
859 static void x86_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
860 HOST_WIDE_INT, tree);
861 static bool x86_can_output_mi_thunk (tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
862 static void x86_file_start (void);
863 static void ix86_reorg (void);
864 static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*);
865 static tree ix86_build_builtin_va_list (void);
866 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
868 static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
869 static bool ix86_vector_mode_supported_p (enum machine_mode);
871 static int ix86_address_cost (rtx);
872 static bool ix86_cannot_force_const_mem (rtx);
873 static rtx ix86_delegitimize_address (rtx);
875 static void i386_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
877 struct builtin_description;
878 static rtx ix86_expand_sse_comi (const struct builtin_description *,
880 static rtx ix86_expand_sse_compare (const struct builtin_description *,
882 static rtx ix86_expand_unop1_builtin (enum insn_code, tree, rtx);
883 static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
884 static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
885 static rtx ix86_expand_store_builtin (enum insn_code, tree);
886 static rtx safe_vector_operand (rtx, enum machine_mode);
887 static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
888 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
889 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
890 static int ix86_fp_comparison_sahf_cost (enum rtx_code code);
891 static int ix86_fp_comparison_cost (enum rtx_code code);
892 static unsigned int ix86_select_alt_pic_regnum (void);
893 static int ix86_save_reg (unsigned int, int);
894 static void ix86_compute_frame_layout (struct ix86_frame *);
895 static int ix86_comp_type_attributes (tree, tree);
896 static int ix86_function_regparm (tree, tree);
897 const struct attribute_spec ix86_attribute_table[];
898 static bool ix86_function_ok_for_sibcall (tree, tree);
899 static tree ix86_handle_cconv_attribute (tree *, tree, tree, int, bool *);
900 static int ix86_value_regno (enum machine_mode, tree, tree);
901 static bool contains_128bit_aligned_vector_p (tree);
902 static rtx ix86_struct_value_rtx (tree, int);
903 static bool ix86_ms_bitfield_layout_p (tree);
904 static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *);
905 static int extended_reg_mentioned_1 (rtx *, void *);
906 static bool ix86_rtx_costs (rtx, int, int, int *);
907 static int min_insn_size (rtx);
908 static tree ix86_md_asm_clobbers (tree outputs, tree inputs, tree clobbers);
909 static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type);
910 static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
912 static void ix86_init_builtins (void);
913 static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
914 static const char *ix86_mangle_fundamental_type (tree);
915 static tree ix86_stack_protect_fail (void);
917 /* This function is only used on Solaris. */
918 static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
921 /* Register class used for passing given 64bit part of the argument.
922 These represent classes as documented by the PS ABI, with the exception
923 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
924 use SF or DFmode move instead of DImode to avoid reformatting penalties.
926 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
927 whenever possible (upper half does contain padding).
929 enum x86_64_reg_class
932 X86_64_INTEGER_CLASS,
933 X86_64_INTEGERSI_CLASS,
940 X86_64_COMPLEX_X87_CLASS,
943 static const char * const x86_64_reg_class_name[] = {
944 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
945 "sseup", "x87", "x87up", "cplx87", "no"
948 #define MAX_CLASSES 4
950 /* Table of constants used by fldpi, fldln2, etc.... */
951 static REAL_VALUE_TYPE ext_80387_constants_table [5];
952 static bool ext_80387_constants_init = 0;
953 static void init_ext_80387_constants (void);
954 static bool ix86_in_large_data_p (tree) ATTRIBUTE_UNUSED;
955 static void ix86_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
956 static void x86_64_elf_unique_section (tree decl, int reloc) ATTRIBUTE_UNUSED;
957 static void x86_64_elf_select_section (tree decl, int reloc,
958 unsigned HOST_WIDE_INT align)
961 /* Initialize the GCC target structure. */
962 #undef TARGET_ATTRIBUTE_TABLE
963 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
964 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
965 # undef TARGET_MERGE_DECL_ATTRIBUTES
966 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
969 #undef TARGET_COMP_TYPE_ATTRIBUTES
970 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
972 #undef TARGET_INIT_BUILTINS
973 #define TARGET_INIT_BUILTINS ix86_init_builtins
974 #undef TARGET_EXPAND_BUILTIN
975 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
977 #undef TARGET_ASM_FUNCTION_EPILOGUE
978 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
980 #undef TARGET_ENCODE_SECTION_INFO
981 #ifndef SUBTARGET_ENCODE_SECTION_INFO
982 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
984 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
987 #undef TARGET_ASM_OPEN_PAREN
988 #define TARGET_ASM_OPEN_PAREN ""
989 #undef TARGET_ASM_CLOSE_PAREN
990 #define TARGET_ASM_CLOSE_PAREN ""
992 #undef TARGET_ASM_ALIGNED_HI_OP
993 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
994 #undef TARGET_ASM_ALIGNED_SI_OP
995 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
997 #undef TARGET_ASM_ALIGNED_DI_OP
998 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1001 #undef TARGET_ASM_UNALIGNED_HI_OP
1002 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1003 #undef TARGET_ASM_UNALIGNED_SI_OP
1004 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1005 #undef TARGET_ASM_UNALIGNED_DI_OP
1006 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1008 #undef TARGET_SCHED_ADJUST_COST
1009 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1010 #undef TARGET_SCHED_ISSUE_RATE
1011 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1012 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1013 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1014 ia32_multipass_dfa_lookahead
1016 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1017 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1020 #undef TARGET_HAVE_TLS
1021 #define TARGET_HAVE_TLS true
1023 #undef TARGET_CANNOT_FORCE_CONST_MEM
1024 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1026 #undef TARGET_DELEGITIMIZE_ADDRESS
1027 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1029 #undef TARGET_MS_BITFIELD_LAYOUT_P
1030 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1033 #undef TARGET_BINDS_LOCAL_P
1034 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1037 #undef TARGET_ASM_OUTPUT_MI_THUNK
1038 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1039 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1040 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1042 #undef TARGET_ASM_FILE_START
1043 #define TARGET_ASM_FILE_START x86_file_start
1045 #undef TARGET_DEFAULT_TARGET_FLAGS
1046 #define TARGET_DEFAULT_TARGET_FLAGS \
1048 | TARGET_64BIT_DEFAULT \
1049 | TARGET_SUBTARGET_DEFAULT \
1050 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1052 #undef TARGET_HANDLE_OPTION
1053 #define TARGET_HANDLE_OPTION ix86_handle_option
1055 #undef TARGET_RTX_COSTS
1056 #define TARGET_RTX_COSTS ix86_rtx_costs
1057 #undef TARGET_ADDRESS_COST
1058 #define TARGET_ADDRESS_COST ix86_address_cost
1060 #undef TARGET_FIXED_CONDITION_CODE_REGS
1061 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1062 #undef TARGET_CC_MODES_COMPATIBLE
1063 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1065 #undef TARGET_MACHINE_DEPENDENT_REORG
1066 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1068 #undef TARGET_BUILD_BUILTIN_VA_LIST
1069 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1071 #undef TARGET_MD_ASM_CLOBBERS
1072 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1074 #undef TARGET_PROMOTE_PROTOTYPES
1075 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1076 #undef TARGET_STRUCT_VALUE_RTX
1077 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1078 #undef TARGET_SETUP_INCOMING_VARARGS
1079 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1080 #undef TARGET_MUST_PASS_IN_STACK
1081 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1082 #undef TARGET_PASS_BY_REFERENCE
1083 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1085 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1086 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1088 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1089 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1092 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1093 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
1096 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1097 #undef TARGET_INSERT_ATTRIBUTES
1098 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1101 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
1102 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
1104 #undef TARGET_STACK_PROTECT_FAIL
1105 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
1107 #undef TARGET_FUNCTION_VALUE
1108 #define TARGET_FUNCTION_VALUE ix86_function_value
1110 struct gcc_target targetm = TARGET_INITIALIZER;
1113 /* The svr4 ABI for the i386 says that records and unions are returned
1115 #ifndef DEFAULT_PCC_STRUCT_RETURN
1116 #define DEFAULT_PCC_STRUCT_RETURN 1
1119 /* Implement TARGET_HANDLE_OPTION. */
1122 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1129 target_flags &= ~MASK_3DNOW_A;
1130 target_flags_explicit |= MASK_3DNOW_A;
1137 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1138 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1145 target_flags &= ~(MASK_SSE2 | MASK_SSE3);
1146 target_flags_explicit |= MASK_SSE2 | MASK_SSE3;
1153 target_flags &= ~MASK_SSE3;
1154 target_flags_explicit |= MASK_SSE3;
1163 /* Sometimes certain combinations of command options do not make
1164 sense on a particular target machine. You can define a macro
1165 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1166 defined, is executed once just after all the command options have
1169 Don't use this macro to turn on various extra optimizations for
1170 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1173 override_options (void)
1176 int ix86_tune_defaulted = 0;
1178 /* Comes from final.c -- no real reason to change it. */
1179 #define MAX_CODE_ALIGN 16
1183 const struct processor_costs *cost; /* Processor costs */
1184 const int target_enable; /* Target flags to enable. */
1185 const int target_disable; /* Target flags to disable. */
1186 const int align_loop; /* Default alignments. */
1187 const int align_loop_max_skip;
1188 const int align_jump;
1189 const int align_jump_max_skip;
1190 const int align_func;
1192 const processor_target_table[PROCESSOR_max] =
1194 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1195 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1196 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1197 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1198 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1199 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1200 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1201 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1202 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0}
1205 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1208 const char *const name; /* processor name or nickname. */
1209 const enum processor_type processor;
1210 const enum pta_flags
1216 PTA_PREFETCH_SSE = 16,
1222 const processor_alias_table[] =
1224 {"i386", PROCESSOR_I386, 0},
1225 {"i486", PROCESSOR_I486, 0},
1226 {"i586", PROCESSOR_PENTIUM, 0},
1227 {"pentium", PROCESSOR_PENTIUM, 0},
1228 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1229 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1230 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1231 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1232 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
1233 {"i686", PROCESSOR_PENTIUMPRO, 0},
1234 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1235 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1236 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1237 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1238 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1239 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1240 | PTA_MMX | PTA_PREFETCH_SSE},
1241 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1242 | PTA_MMX | PTA_PREFETCH_SSE},
1243 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1244 | PTA_MMX | PTA_PREFETCH_SSE},
1245 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1246 | PTA_MMX | PTA_PREFETCH_SSE},
1247 {"k6", PROCESSOR_K6, PTA_MMX},
1248 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1249 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1250 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1252 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1253 | PTA_3DNOW | PTA_3DNOW_A},
1254 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1255 | PTA_3DNOW_A | PTA_SSE},
1256 {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1257 | PTA_3DNOW_A | PTA_SSE},
1258 {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1259 | PTA_3DNOW_A | PTA_SSE},
1260 {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
1261 | PTA_SSE | PTA_SSE2 },
1262 {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1263 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1264 {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1265 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1266 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1267 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1268 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1269 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
1272 int const pta_size = ARRAY_SIZE (processor_alias_table);
1274 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1275 SUBTARGET_OVERRIDE_OPTIONS;
1278 /* Set the default values for switches whose default depends on TARGET_64BIT
1279 in case they weren't overwritten by command line options. */
1282 if (flag_omit_frame_pointer == 2)
1283 flag_omit_frame_pointer = 1;
1284 if (flag_asynchronous_unwind_tables == 2)
1285 flag_asynchronous_unwind_tables = 1;
1286 if (flag_pcc_struct_return == 2)
1287 flag_pcc_struct_return = 0;
1291 if (flag_omit_frame_pointer == 2)
1292 flag_omit_frame_pointer = 0;
1293 if (flag_asynchronous_unwind_tables == 2)
1294 flag_asynchronous_unwind_tables = 0;
1295 if (flag_pcc_struct_return == 2)
1296 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1299 if (!ix86_tune_string && ix86_arch_string)
1300 ix86_tune_string = ix86_arch_string;
1301 if (!ix86_tune_string)
1303 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1304 ix86_tune_defaulted = 1;
1306 if (!ix86_arch_string)
1307 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
1309 if (ix86_cmodel_string != 0)
1311 if (!strcmp (ix86_cmodel_string, "small"))
1312 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1313 else if (!strcmp (ix86_cmodel_string, "medium"))
1314 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
1316 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string);
1317 else if (!strcmp (ix86_cmodel_string, "32"))
1318 ix86_cmodel = CM_32;
1319 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
1320 ix86_cmodel = CM_KERNEL;
1321 else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic)
1322 ix86_cmodel = CM_LARGE;
1324 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
1328 ix86_cmodel = CM_32;
1330 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1332 if (ix86_asm_string != 0)
1334 if (!strcmp (ix86_asm_string, "intel"))
1335 ix86_asm_dialect = ASM_INTEL;
1336 else if (!strcmp (ix86_asm_string, "att"))
1337 ix86_asm_dialect = ASM_ATT;
1339 error ("bad value (%s) for -masm= switch", ix86_asm_string);
1341 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
1342 error ("code model %qs not supported in the %s bit mode",
1343 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
1344 if (ix86_cmodel == CM_LARGE)
1345 sorry ("code model %<large%> not supported yet");
1346 if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
1347 sorry ("%i-bit mode not compiled in",
1348 (target_flags & MASK_64BIT) ? 64 : 32);
1350 for (i = 0; i < pta_size; i++)
1351 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
1353 ix86_arch = processor_alias_table[i].processor;
1354 /* Default cpu tuning to the architecture. */
1355 ix86_tune = ix86_arch;
1356 if (processor_alias_table[i].flags & PTA_MMX
1357 && !(target_flags_explicit & MASK_MMX))
1358 target_flags |= MASK_MMX;
1359 if (processor_alias_table[i].flags & PTA_3DNOW
1360 && !(target_flags_explicit & MASK_3DNOW))
1361 target_flags |= MASK_3DNOW;
1362 if (processor_alias_table[i].flags & PTA_3DNOW_A
1363 && !(target_flags_explicit & MASK_3DNOW_A))
1364 target_flags |= MASK_3DNOW_A;
1365 if (processor_alias_table[i].flags & PTA_SSE
1366 && !(target_flags_explicit & MASK_SSE))
1367 target_flags |= MASK_SSE;
1368 if (processor_alias_table[i].flags & PTA_SSE2
1369 && !(target_flags_explicit & MASK_SSE2))
1370 target_flags |= MASK_SSE2;
1371 if (processor_alias_table[i].flags & PTA_SSE3
1372 && !(target_flags_explicit & MASK_SSE3))
1373 target_flags |= MASK_SSE3;
1374 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1375 x86_prefetch_sse = true;
1376 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1377 error ("CPU you selected does not support x86-64 "
1383 error ("bad value (%s) for -march= switch", ix86_arch_string);
1385 for (i = 0; i < pta_size; i++)
1386 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
1388 ix86_tune = processor_alias_table[i].processor;
1389 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1391 if (ix86_tune_defaulted)
1393 ix86_tune_string = "x86-64";
1394 for (i = 0; i < pta_size; i++)
1395 if (! strcmp (ix86_tune_string,
1396 processor_alias_table[i].name))
1398 ix86_tune = processor_alias_table[i].processor;
1401 error ("CPU you selected does not support x86-64 "
1404 /* Intel CPUs have always interpreted SSE prefetch instructions as
1405 NOPs; so, we can enable SSE prefetch instructions even when
1406 -mtune (rather than -march) points us to a processor that has them.
1407 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
1408 higher processors. */
1409 if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
1410 x86_prefetch_sse = true;
1414 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1417 ix86_cost = &size_cost;
1419 ix86_cost = processor_target_table[ix86_tune].cost;
1420 target_flags |= processor_target_table[ix86_tune].target_enable;
1421 target_flags &= ~processor_target_table[ix86_tune].target_disable;
1423 /* Arrange to set up i386_stack_locals for all functions. */
1424 init_machine_status = ix86_init_machine_status;
1426 /* Validate -mregparm= value. */
1427 if (ix86_regparm_string)
1429 i = atoi (ix86_regparm_string);
1430 if (i < 0 || i > REGPARM_MAX)
1431 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
1437 ix86_regparm = REGPARM_MAX;
1439 /* If the user has provided any of the -malign-* options,
1440 warn and use that value only if -falign-* is not set.
1441 Remove this code in GCC 3.2 or later. */
1442 if (ix86_align_loops_string)
1444 warning (0, "-malign-loops is obsolete, use -falign-loops");
1445 if (align_loops == 0)
1447 i = atoi (ix86_align_loops_string);
1448 if (i < 0 || i > MAX_CODE_ALIGN)
1449 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1451 align_loops = 1 << i;
1455 if (ix86_align_jumps_string)
1457 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
1458 if (align_jumps == 0)
1460 i = atoi (ix86_align_jumps_string);
1461 if (i < 0 || i > MAX_CODE_ALIGN)
1462 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1464 align_jumps = 1 << i;
1468 if (ix86_align_funcs_string)
1470 warning (0, "-malign-functions is obsolete, use -falign-functions");
1471 if (align_functions == 0)
1473 i = atoi (ix86_align_funcs_string);
1474 if (i < 0 || i > MAX_CODE_ALIGN)
1475 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
1477 align_functions = 1 << i;
1481 /* Default align_* from the processor table. */
1482 if (align_loops == 0)
1484 align_loops = processor_target_table[ix86_tune].align_loop;
1485 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
1487 if (align_jumps == 0)
1489 align_jumps = processor_target_table[ix86_tune].align_jump;
1490 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
1492 if (align_functions == 0)
1494 align_functions = processor_target_table[ix86_tune].align_func;
1497 /* Validate -mpreferred-stack-boundary= value, or provide default.
1498 The default of 128 bits is for Pentium III's SSE __m128, but we
1499 don't want additional code to keep the stack aligned when
1500 optimizing for code size. */
1501 ix86_preferred_stack_boundary = (optimize_size
1502 ? TARGET_64BIT ? 128 : 32
1504 if (ix86_preferred_stack_boundary_string)
1506 i = atoi (ix86_preferred_stack_boundary_string);
1507 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
1508 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
1509 TARGET_64BIT ? 4 : 2);
1511 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
1514 /* Validate -mbranch-cost= value, or provide default. */
1515 ix86_branch_cost = processor_target_table[ix86_tune].cost->branch_cost;
1516 if (ix86_branch_cost_string)
1518 i = atoi (ix86_branch_cost_string);
1520 error ("-mbranch-cost=%d is not between 0 and 5", i);
1522 ix86_branch_cost = i;
1524 if (ix86_section_threshold_string)
1526 i = atoi (ix86_section_threshold_string);
1528 error ("-mlarge-data-threshold=%d is negative", i);
1530 ix86_section_threshold = i;
1533 if (ix86_tls_dialect_string)
1535 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
1536 ix86_tls_dialect = TLS_DIALECT_GNU;
1537 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
1538 ix86_tls_dialect = TLS_DIALECT_SUN;
1540 error ("bad value (%s) for -mtls-dialect= switch",
1541 ix86_tls_dialect_string);
1544 /* Keep nonleaf frame pointers. */
1545 if (flag_omit_frame_pointer)
1546 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
1547 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
1548 flag_omit_frame_pointer = 1;
1550 /* If we're doing fast math, we don't care about comparison order
1551 wrt NaNs. This lets us use a shorter comparison sequence. */
1552 if (flag_unsafe_math_optimizations)
1553 target_flags &= ~MASK_IEEE_FP;
1555 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
1556 since the insns won't need emulation. */
1557 if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
1558 target_flags &= ~MASK_NO_FANCY_MATH_387;
1560 /* Likewise, if the target doesn't have a 387, or we've specified
1561 software floating point, don't use 387 inline intrinsics. */
1563 target_flags |= MASK_NO_FANCY_MATH_387;
1565 /* Turn on SSE2 builtins for -msse3. */
1567 target_flags |= MASK_SSE2;
1569 /* Turn on SSE builtins for -msse2. */
1571 target_flags |= MASK_SSE;
1573 /* Turn on MMX builtins for -msse. */
1576 target_flags |= MASK_MMX & ~target_flags_explicit;
1577 x86_prefetch_sse = true;
1580 /* Turn on MMX builtins for 3Dnow. */
1582 target_flags |= MASK_MMX;
1586 if (TARGET_ALIGN_DOUBLE)
1587 error ("-malign-double makes no sense in the 64bit mode");
1589 error ("-mrtd calling convention not supported in the 64bit mode");
1591 /* Enable by default the SSE and MMX builtins. Do allow the user to
1592 explicitly disable any of these. In particular, disabling SSE and
1593 MMX for kernel code is extremely useful. */
1595 |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE)
1596 & ~target_flags_explicit);
1600 /* i386 ABI does not specify red zone. It still makes sense to use it
1601 when programmer takes care to stack from being destroyed. */
1602 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
1603 target_flags |= MASK_NO_RED_ZONE;
1606 /* Accept -msseregparm only if at least SSE support is enabled. */
1607 if (TARGET_SSEREGPARM
1609 error ("-msseregparm used without SSE enabled");
1611 ix86_fpmath = TARGET_FPMATH_DEFAULT;
1613 if (ix86_fpmath_string != 0)
1615 if (! strcmp (ix86_fpmath_string, "387"))
1616 ix86_fpmath = FPMATH_387;
1617 else if (! strcmp (ix86_fpmath_string, "sse"))
1621 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1622 ix86_fpmath = FPMATH_387;
1625 ix86_fpmath = FPMATH_SSE;
1627 else if (! strcmp (ix86_fpmath_string, "387,sse")
1628 || ! strcmp (ix86_fpmath_string, "sse,387"))
1632 warning (0, "SSE instruction set disabled, using 387 arithmetics");
1633 ix86_fpmath = FPMATH_387;
1635 else if (!TARGET_80387)
1637 warning (0, "387 instruction set disabled, using SSE arithmetics");
1638 ix86_fpmath = FPMATH_SSE;
1641 ix86_fpmath = FPMATH_SSE | FPMATH_387;
1644 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
1647 /* If the i387 is disabled, then do not return values in it. */
1649 target_flags &= ~MASK_FLOAT_RETURNS;
1651 if ((x86_accumulate_outgoing_args & TUNEMASK)
1652 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
1654 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
1656 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
1659 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
1660 p = strchr (internal_label_prefix, 'X');
1661 internal_label_prefix_len = p - internal_label_prefix;
1665 /* When scheduling description is not available, disable scheduler pass
1666 so it won't slow down the compilation and make x87 code slower. */
1667 if (!TARGET_SCHEDULE)
1668 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
1671 /* switch to the appropriate section for output of DECL.
1672 DECL is either a `VAR_DECL' node or a constant of some sort.
1673 RELOC indicates whether forming the initial value of DECL requires
1674 link-time relocations. */
1677 x86_64_elf_select_section (tree decl, int reloc,
1678 unsigned HOST_WIDE_INT align)
1680 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1681 && ix86_in_large_data_p (decl))
1683 const char *sname = NULL;
1684 switch (categorize_decl_for_section (decl, reloc, flag_pic))
1689 case SECCAT_DATA_REL:
1690 sname = ".ldata.rel";
1692 case SECCAT_DATA_REL_LOCAL:
1693 sname = ".ldata.rel.local";
1695 case SECCAT_DATA_REL_RO:
1696 sname = ".ldata.rel.ro";
1698 case SECCAT_DATA_REL_RO_LOCAL:
1699 sname = ".ldata.rel.ro.local";
1705 case SECCAT_RODATA_MERGE_STR:
1706 case SECCAT_RODATA_MERGE_STR_INIT:
1707 case SECCAT_RODATA_MERGE_CONST:
1710 case SECCAT_SRODATA:
1717 /* We don't split these for medium model. Place them into
1718 default sections and hope for best. */
1723 named_section (decl, sname, reloc);
1727 default_elf_select_section (decl, reloc, align);
1730 /* Build up a unique section name, expressed as a
1731 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
1732 RELOC indicates whether the initial value of EXP requires
1733 link-time relocations. */
1736 x86_64_elf_unique_section (tree decl, int reloc)
1738 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1739 && ix86_in_large_data_p (decl))
1741 const char *prefix = NULL;
1742 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
1743 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
1745 switch (categorize_decl_for_section (decl, reloc, flag_pic))
1748 case SECCAT_DATA_REL:
1749 case SECCAT_DATA_REL_LOCAL:
1750 case SECCAT_DATA_REL_RO:
1751 case SECCAT_DATA_REL_RO_LOCAL:
1752 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
1755 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
1758 case SECCAT_RODATA_MERGE_STR:
1759 case SECCAT_RODATA_MERGE_STR_INIT:
1760 case SECCAT_RODATA_MERGE_CONST:
1761 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
1763 case SECCAT_SRODATA:
1770 /* We don't split these for medium model. Place them into
1771 default sections and hope for best. */
1779 plen = strlen (prefix);
1781 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
1782 name = targetm.strip_name_encoding (name);
1783 nlen = strlen (name);
1785 string = alloca (nlen + plen + 1);
1786 memcpy (string, prefix, plen);
1787 memcpy (string + plen, name, nlen + 1);
1789 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
1793 default_unique_section (decl, reloc);
1796 #ifdef COMMON_ASM_OP
1797 /* This says how to output assembler code to declare an
1798 uninitialized external linkage data object.
1800 For medium model x86-64 we need to use .largecomm opcode for
1803 x86_elf_aligned_common (FILE *file,
1804 const char *name, unsigned HOST_WIDE_INT size,
1807 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1808 && size > (unsigned int)ix86_section_threshold)
1809 fprintf (file, ".largecomm\t");
1811 fprintf (file, "%s", COMMON_ASM_OP);
1812 assemble_name (file, name);
1813 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
1814 size, align / BITS_PER_UNIT);
1817 /* Utility function for targets to use in implementing
1818 ASM_OUTPUT_ALIGNED_BSS. */
1821 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
1822 const char *name, unsigned HOST_WIDE_INT size,
1825 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
1826 && size > (unsigned int)ix86_section_threshold)
1827 named_section (decl, ".lbss", 0);
1830 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
1831 #ifdef ASM_DECLARE_OBJECT_NAME
1832 last_assemble_variable_decl = decl;
1833 ASM_DECLARE_OBJECT_NAME (file, name, decl);
1835 /* Standard thing is just output label for the object. */
1836 ASM_OUTPUT_LABEL (file, name);
1837 #endif /* ASM_DECLARE_OBJECT_NAME */
1838 ASM_OUTPUT_SKIP (file, size ? size : 1);
1843 optimization_options (int level, int size ATTRIBUTE_UNUSED)
1845 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
1846 make the problem with not enough registers even worse. */
1847 #ifdef INSN_SCHEDULING
1849 flag_schedule_insns = 0;
1853 /* The Darwin libraries never set errno, so we might as well
1854 avoid calling them when that's the only reason we would. */
1855 flag_errno_math = 0;
1857 /* The default values of these switches depend on the TARGET_64BIT
1858 that is not known at this moment. Mark these values with 2 and
1859 let user the to override these. In case there is no command line option
1860 specifying them, we will set the defaults in override_options. */
1862 flag_omit_frame_pointer = 2;
1863 flag_pcc_struct_return = 2;
1864 flag_asynchronous_unwind_tables = 2;
1865 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1866 SUBTARGET_OPTIMIZATION_OPTIONS;
1870 /* Table of valid machine attributes. */
1871 const struct attribute_spec ix86_attribute_table[] =
1873 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1874 /* Stdcall attribute says callee is responsible for popping arguments
1875 if they are not variable. */
1876 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1877 /* Fastcall attribute says callee is responsible for popping arguments
1878 if they are not variable. */
1879 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1880 /* Cdecl attribute says the callee is a normal C declaration */
1881 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1882 /* Regparm attribute specifies how many integer arguments are to be
1883 passed in registers. */
1884 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
1885 /* Sseregparm attribute says we are using x86_64 calling conventions
1886 for FP arguments. */
1887 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
1888 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1889 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
1890 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
1891 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
1893 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
1894 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
1895 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1896 SUBTARGET_ATTRIBUTE_TABLE,
1898 { NULL, 0, 0, false, false, false, NULL }
1901 /* Decide whether we can make a sibling call to a function. DECL is the
1902 declaration of the function being targeted by the call and EXP is the
1903 CALL_EXPR representing the call. */
1906 ix86_function_ok_for_sibcall (tree decl, tree exp)
1911 /* If we are generating position-independent code, we cannot sibcall
1912 optimize any indirect call, or a direct call to a global function,
1913 as the PLT requires %ebx be live. */
1914 if (!TARGET_64BIT && flag_pic && (!decl || TREE_PUBLIC (decl)))
1921 func = TREE_TYPE (TREE_OPERAND (exp, 0));
1922 if (POINTER_TYPE_P (func))
1923 func = TREE_TYPE (func);
1926 /* Check that the return value locations are the same. Like
1927 if we are returning floats on the 80387 register stack, we cannot
1928 make a sibcall from a function that doesn't return a float to a
1929 function that does or, conversely, from a function that does return
1930 a float to a function that doesn't; the necessary stack adjustment
1931 would not be executed. This is also the place we notice
1932 differences in the return value ABI. */
1933 a = ix86_function_value (TREE_TYPE (exp), func, false);
1934 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
1936 if (! rtx_equal_p (a, b))
1939 /* If this call is indirect, we'll need to be able to use a call-clobbered
1940 register for the address of the target function. Make sure that all
1941 such registers are not used for passing parameters. */
1942 if (!decl && !TARGET_64BIT)
1946 /* We're looking at the CALL_EXPR, we need the type of the function. */
1947 type = TREE_OPERAND (exp, 0); /* pointer expression */
1948 type = TREE_TYPE (type); /* pointer type */
1949 type = TREE_TYPE (type); /* function type */
1951 if (ix86_function_regparm (type, NULL) >= 3)
1953 /* ??? Need to count the actual number of registers to be used,
1954 not the possible number of registers. Fix later. */
1959 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1960 /* Dllimport'd functions are also called indirectly. */
1961 if (decl && lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl))
1962 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
1966 /* Otherwise okay. That also includes certain types of indirect calls. */
1970 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
1971 calling convention attributes;
1972 arguments as in struct attribute_spec.handler. */
1975 ix86_handle_cconv_attribute (tree *node, tree name,
1977 int flags ATTRIBUTE_UNUSED,
1980 if (TREE_CODE (*node) != FUNCTION_TYPE
1981 && TREE_CODE (*node) != METHOD_TYPE
1982 && TREE_CODE (*node) != FIELD_DECL
1983 && TREE_CODE (*node) != TYPE_DECL)
1985 warning (OPT_Wattributes, "%qs attribute only applies to functions",
1986 IDENTIFIER_POINTER (name));
1987 *no_add_attrs = true;
1991 /* Can combine regparm with all attributes but fastcall. */
1992 if (is_attribute_p ("regparm", name))
1996 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
1998 error ("fastcall and regparm attributes are not compatible");
2001 cst = TREE_VALUE (args);
2002 if (TREE_CODE (cst) != INTEGER_CST)
2004 warning (OPT_Wattributes,
2005 "%qs attribute requires an integer constant argument",
2006 IDENTIFIER_POINTER (name));
2007 *no_add_attrs = true;
2009 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2011 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2012 IDENTIFIER_POINTER (name), REGPARM_MAX);
2013 *no_add_attrs = true;
2021 warning (OPT_Wattributes, "%qs attribute ignored",
2022 IDENTIFIER_POINTER (name));
2023 *no_add_attrs = true;
2027 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2028 if (is_attribute_p ("fastcall", name))
2030 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2032 error ("fastcall and cdecl attributes are not compatible");
2034 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2036 error ("fastcall and stdcall attributes are not compatible");
2038 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2040 error ("fastcall and regparm attributes are not compatible");
2044 /* Can combine stdcall with fastcall (redundant), regparm and
2046 else if (is_attribute_p ("stdcall", name))
2048 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2050 error ("stdcall and cdecl attributes are not compatible");
2052 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2054 error ("stdcall and fastcall attributes are not compatible");
2058 /* Can combine cdecl with regparm and sseregparm. */
2059 else if (is_attribute_p ("cdecl", name))
2061 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2063 error ("stdcall and cdecl attributes are not compatible");
2065 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2067 error ("fastcall and cdecl attributes are not compatible");
2071 /* Can combine sseregparm with all attributes. */
2076 /* Return 0 if the attributes for two types are incompatible, 1 if they
2077 are compatible, and 2 if they are nearly compatible (which causes a
2078 warning to be generated). */
2081 ix86_comp_type_attributes (tree type1, tree type2)
2083 /* Check for mismatch of non-default calling convention. */
2084 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2086 if (TREE_CODE (type1) != FUNCTION_TYPE)
2089 /* Check for mismatched fastcall/regparm types. */
2090 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2091 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2092 || (ix86_function_regparm (type1, NULL)
2093 != ix86_function_regparm (type2, NULL)))
2096 /* Check for mismatched sseregparm types. */
2097 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2098 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2101 /* Check for mismatched return types (cdecl vs stdcall). */
2102 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2103 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2109 /* Return the regparm value for a function with the indicated TYPE and DECL.
2110 DECL may be NULL when calling function indirectly
2111 or considering a libcall. */
2114 ix86_function_regparm (tree type, tree decl)
2117 int regparm = ix86_regparm;
2118 bool user_convention = false;
2122 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
2125 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
2126 user_convention = true;
2129 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
2132 user_convention = true;
2135 /* Use register calling convention for local functions when possible. */
2136 if (!TARGET_64BIT && !user_convention && decl
2137 && flag_unit_at_a_time && !profile_flag)
2139 struct cgraph_local_info *i = cgraph_local_info (decl);
2142 /* We can't use regparm(3) for nested functions as these use
2143 static chain pointer in third argument. */
2144 if (DECL_CONTEXT (decl) && !DECL_NO_STATIC_CHAIN (decl))
2154 /* Return 1 or 2, if we can pass up to 8 SFmode (1) and DFmode (2) arguments
2155 in SSE registers for a function with the indicated TYPE and DECL.
2156 DECL may be NULL when calling function indirectly
2157 or considering a libcall. Otherwise return 0. */
2160 ix86_function_sseregparm (tree type, tree decl)
2162 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2163 by the sseregparm attribute. */
2164 if (TARGET_SSEREGPARM
2166 && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
2171 error ("Calling %qD with attribute sseregparm without "
2172 "SSE/SSE2 enabled", decl);
2174 error ("Calling %qT with attribute sseregparm without "
2175 "SSE/SSE2 enabled", type);
2182 /* For local functions, pass SFmode (and DFmode for SSE2) arguments
2183 in SSE registers even for 32-bit mode and not just 3, but up to
2184 8 SSE arguments in registers. */
2185 if (!TARGET_64BIT && decl
2186 && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
2188 struct cgraph_local_info *i = cgraph_local_info (decl);
2190 return TARGET_SSE2 ? 2 : 1;
2196 /* Return true if EAX is live at the start of the function. Used by
2197 ix86_expand_prologue to determine if we need special help before
2198 calling allocate_stack_worker. */
2201 ix86_eax_live_at_start_p (void)
2203 /* Cheat. Don't bother working forward from ix86_function_regparm
2204 to the function type to whether an actual argument is located in
2205 eax. Instead just look at cfg info, which is still close enough
2206 to correct at this point. This gives false positives for broken
2207 functions that might use uninitialized data that happens to be
2208 allocated in eax, but who cares? */
2209 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end, 0);
2212 /* Value is the number of bytes of arguments automatically
2213 popped when returning from a subroutine call.
2214 FUNDECL is the declaration node of the function (as a tree),
2215 FUNTYPE is the data type of the function (as a tree),
2216 or for a library call it is an identifier node for the subroutine name.
2217 SIZE is the number of bytes of arguments passed on the stack.
2219 On the 80386, the RTD insn may be used to pop them if the number
2220 of args is fixed, but if the number is variable then the caller
2221 must pop them all. RTD can't be used for library calls now
2222 because the library is compiled with the Unix compiler.
2223 Use of RTD is a selectable option, since it is incompatible with
2224 standard Unix calling sequences. If the option is not selected,
2225 the caller must always pop the args.
2227 The attribute stdcall is equivalent to RTD on a per module basis. */
2230 ix86_return_pops_args (tree fundecl, tree funtype, int size)
2232 int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
2234 /* Cdecl functions override -mrtd, and never pop the stack. */
2235 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {
2237 /* Stdcall and fastcall functions will pop the stack if not
2239 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
2240 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
2244 && (TYPE_ARG_TYPES (funtype) == NULL_TREE
2245 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
2246 == void_type_node)))
2250 /* Lose any fake structure return argument if it is passed on the stack. */
2251 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
2253 && !KEEP_AGGREGATE_RETURN_POINTER)
2255 int nregs = ix86_function_regparm (funtype, fundecl);
2258 return GET_MODE_SIZE (Pmode);
2264 /* Argument support functions. */
2266 /* Return true when register may be used to pass function parameters. */
2268 ix86_function_arg_regno_p (int regno)
2272 return (regno < REGPARM_MAX
2273 || (TARGET_MMX && MMX_REGNO_P (regno)
2274 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
2275 || (TARGET_SSE && SSE_REGNO_P (regno)
2276 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
2278 if (TARGET_SSE && SSE_REGNO_P (regno)
2279 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
2281 /* RAX is used as hidden argument to va_arg functions. */
2284 for (i = 0; i < REGPARM_MAX; i++)
2285 if (regno == x86_64_int_parameter_registers[i])
2290 /* Return if we do not know how to pass TYPE solely in registers. */
2293 ix86_must_pass_in_stack (enum machine_mode mode, tree type)
2295 if (must_pass_in_stack_var_size_or_pad (mode, type))
2298 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
2299 The layout_type routine is crafty and tries to trick us into passing
2300 currently unsupported vector types on the stack by using TImode. */
2301 return (!TARGET_64BIT && mode == TImode
2302 && type && TREE_CODE (type) != VECTOR_TYPE);
2305 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2306 for a call to a function whose data type is FNTYPE.
2307 For a library call, FNTYPE is 0. */
2310 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
2311 tree fntype, /* tree ptr for function decl */
2312 rtx libname, /* SYMBOL_REF of library name or 0 */
2315 static CUMULATIVE_ARGS zero_cum;
2316 tree param, next_param;
2318 if (TARGET_DEBUG_ARG)
2320 fprintf (stderr, "\ninit_cumulative_args (");
2322 fprintf (stderr, "fntype code = %s, ret code = %s",
2323 tree_code_name[(int) TREE_CODE (fntype)],
2324 tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
2326 fprintf (stderr, "no fntype");
2329 fprintf (stderr, ", libname = %s", XSTR (libname, 0));
2334 /* Set up the number of registers to use for passing arguments. */
2335 cum->nregs = ix86_regparm;
2337 cum->sse_nregs = SSE_REGPARM_MAX;
2339 cum->mmx_nregs = MMX_REGPARM_MAX;
2340 cum->warn_sse = true;
2341 cum->warn_mmx = true;
2342 cum->maybe_vaarg = false;
2344 /* Use ecx and edx registers if function has fastcall attribute,
2345 else look for regparm information. */
2346 if (fntype && !TARGET_64BIT)
2348 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
2354 cum->nregs = ix86_function_regparm (fntype, fndecl);
2357 /* Set up the number of SSE registers used for passing SFmode
2358 and DFmode arguments. Warn for mismatching ABI. */
2359 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
2361 /* Determine if this function has variable arguments. This is
2362 indicated by the last argument being 'void_type_mode' if there
2363 are no variable arguments. If there are variable arguments, then
2364 we won't pass anything in registers in 32-bit mode. */
2366 if (cum->nregs || cum->mmx_nregs || cum->sse_nregs)
2368 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
2369 param != 0; param = next_param)
2371 next_param = TREE_CHAIN (param);
2372 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
2382 cum->float_in_sse = 0;
2384 cum->maybe_vaarg = true;
2388 if ((!fntype && !libname)
2389 || (fntype && !TYPE_ARG_TYPES (fntype)))
2390 cum->maybe_vaarg = true;
2392 if (TARGET_DEBUG_ARG)
2393 fprintf (stderr, ", nregs=%d )\n", cum->nregs);
2398 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
2399 But in the case of vector types, it is some vector mode.
2401 When we have only some of our vector isa extensions enabled, then there
2402 are some modes for which vector_mode_supported_p is false. For these
2403 modes, the generic vector support in gcc will choose some non-vector mode
2404 in order to implement the type. By computing the natural mode, we'll
2405 select the proper ABI location for the operand and not depend on whatever
2406 the middle-end decides to do with these vector types. */
2408 static enum machine_mode
2409 type_natural_mode (tree type)
2411 enum machine_mode mode = TYPE_MODE (type);
2413 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
2415 HOST_WIDE_INT size = int_size_in_bytes (type);
2416 if ((size == 8 || size == 16)
2417 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
2418 && TYPE_VECTOR_SUBPARTS (type) > 1)
2420 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
2422 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
2423 mode = MIN_MODE_VECTOR_FLOAT;
2425 mode = MIN_MODE_VECTOR_INT;
2427 /* Get the mode which has this inner mode and number of units. */
2428 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
2429 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
2430 && GET_MODE_INNER (mode) == innermode)
2440 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
2441 this may not agree with the mode that the type system has chosen for the
2442 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
2443 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
2446 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
2451 if (orig_mode != BLKmode)
2452 tmp = gen_rtx_REG (orig_mode, regno);
2455 tmp = gen_rtx_REG (mode, regno);
2456 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
2457 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
2463 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
2464 of this code is to classify each 8bytes of incoming argument by the register
2465 class and assign registers accordingly. */
2467 /* Return the union class of CLASS1 and CLASS2.
2468 See the x86-64 PS ABI for details. */
2470 static enum x86_64_reg_class
2471 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
2473 /* Rule #1: If both classes are equal, this is the resulting class. */
2474 if (class1 == class2)
2477 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
2479 if (class1 == X86_64_NO_CLASS)
2481 if (class2 == X86_64_NO_CLASS)
2484 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
2485 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
2486 return X86_64_MEMORY_CLASS;
2488 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
2489 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
2490 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
2491 return X86_64_INTEGERSI_CLASS;
2492 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
2493 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
2494 return X86_64_INTEGER_CLASS;
2496 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
2498 if (class1 == X86_64_X87_CLASS
2499 || class1 == X86_64_X87UP_CLASS
2500 || class1 == X86_64_COMPLEX_X87_CLASS
2501 || class2 == X86_64_X87_CLASS
2502 || class2 == X86_64_X87UP_CLASS
2503 || class2 == X86_64_COMPLEX_X87_CLASS)
2504 return X86_64_MEMORY_CLASS;
2506 /* Rule #6: Otherwise class SSE is used. */
2507 return X86_64_SSE_CLASS;
2510 /* Classify the argument of type TYPE and mode MODE.
2511 CLASSES will be filled by the register class used to pass each word
2512 of the operand. The number of words is returned. In case the parameter
2513 should be passed in memory, 0 is returned. As a special case for zero
2514 sized containers, classes[0] will be NO_CLASS and 1 is returned.
2516 BIT_OFFSET is used internally for handling records and specifies offset
2517 of the offset in bits modulo 256 to avoid overflow cases.
2519 See the x86-64 PS ABI for details.
2523 classify_argument (enum machine_mode mode, tree type,
2524 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
2526 HOST_WIDE_INT bytes =
2527 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
2528 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2530 /* Variable sized entities are always passed/returned in memory. */
2534 if (mode != VOIDmode
2535 && targetm.calls.must_pass_in_stack (mode, type))
2538 if (type && AGGREGATE_TYPE_P (type))
2542 enum x86_64_reg_class subclasses[MAX_CLASSES];
2544 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
2548 for (i = 0; i < words; i++)
2549 classes[i] = X86_64_NO_CLASS;
2551 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
2552 signalize memory class, so handle it as special case. */
2555 classes[0] = X86_64_NO_CLASS;
2559 /* Classify each field of record and merge classes. */
2560 switch (TREE_CODE (type))
2563 /* For classes first merge in the field of the subclasses. */
2564 if (TYPE_BINFO (type))
2566 tree binfo, base_binfo;
2569 for (binfo = TYPE_BINFO (type), basenum = 0;
2570 BINFO_BASE_ITERATE (binfo, basenum, base_binfo); basenum++)
2573 int offset = tree_low_cst (BINFO_OFFSET (base_binfo), 0) * 8;
2574 tree type = BINFO_TYPE (base_binfo);
2576 num = classify_argument (TYPE_MODE (type),
2578 (offset + bit_offset) % 256);
2581 for (i = 0; i < num; i++)
2583 int pos = (offset + (bit_offset % 64)) / 8 / 8;
2585 merge_classes (subclasses[i], classes[i + pos]);
2589 /* And now merge the fields of structure. */
2590 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2592 if (TREE_CODE (field) == FIELD_DECL)
2596 /* Bitfields are always classified as integer. Handle them
2597 early, since later code would consider them to be
2598 misaligned integers. */
2599 if (DECL_BIT_FIELD (field))
2601 for (i = int_bit_position (field) / 8 / 8;
2602 i < (int_bit_position (field)
2603 + tree_low_cst (DECL_SIZE (field), 0)
2606 merge_classes (X86_64_INTEGER_CLASS,
2611 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
2612 TREE_TYPE (field), subclasses,
2613 (int_bit_position (field)
2614 + bit_offset) % 256);
2617 for (i = 0; i < num; i++)
2620 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
2622 merge_classes (subclasses[i], classes[i + pos]);
2630 /* Arrays are handled as small records. */
2633 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
2634 TREE_TYPE (type), subclasses, bit_offset);
2638 /* The partial classes are now full classes. */
2639 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
2640 subclasses[0] = X86_64_SSE_CLASS;
2641 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
2642 subclasses[0] = X86_64_INTEGER_CLASS;
2644 for (i = 0; i < words; i++)
2645 classes[i] = subclasses[i % num];
2650 case QUAL_UNION_TYPE:
2651 /* Unions are similar to RECORD_TYPE but offset is always 0.
2654 /* Unions are not derived. */
2655 gcc_assert (!TYPE_BINFO (type)
2656 || !BINFO_N_BASE_BINFOS (TYPE_BINFO (type)));
2657 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2659 if (TREE_CODE (field) == FIELD_DECL)
2662 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
2663 TREE_TYPE (field), subclasses,
2667 for (i = 0; i < num; i++)
2668 classes[i] = merge_classes (subclasses[i], classes[i]);
2677 /* Final merger cleanup. */
2678 for (i = 0; i < words; i++)
2680 /* If one class is MEMORY, everything should be passed in
2682 if (classes[i] == X86_64_MEMORY_CLASS)
2685 /* The X86_64_SSEUP_CLASS should be always preceded by
2686 X86_64_SSE_CLASS. */
2687 if (classes[i] == X86_64_SSEUP_CLASS
2688 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
2689 classes[i] = X86_64_SSE_CLASS;
2691 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
2692 if (classes[i] == X86_64_X87UP_CLASS
2693 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
2694 classes[i] = X86_64_SSE_CLASS;
2699 /* Compute alignment needed. We align all types to natural boundaries with
2700 exception of XFmode that is aligned to 64bits. */
2701 if (mode != VOIDmode && mode != BLKmode)
2703 int mode_alignment = GET_MODE_BITSIZE (mode);
2706 mode_alignment = 128;
2707 else if (mode == XCmode)
2708 mode_alignment = 256;
2709 if (COMPLEX_MODE_P (mode))
2710 mode_alignment /= 2;
2711 /* Misaligned fields are always returned in memory. */
2712 if (bit_offset % mode_alignment)
2716 /* for V1xx modes, just use the base mode */
2717 if (VECTOR_MODE_P (mode)
2718 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
2719 mode = GET_MODE_INNER (mode);
2721 /* Classification of atomic types. */
2731 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
2732 classes[0] = X86_64_INTEGERSI_CLASS;
2734 classes[0] = X86_64_INTEGER_CLASS;
2738 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
2743 if (!(bit_offset % 64))
2744 classes[0] = X86_64_SSESF_CLASS;
2746 classes[0] = X86_64_SSE_CLASS;
2749 classes[0] = X86_64_SSEDF_CLASS;
2752 classes[0] = X86_64_X87_CLASS;
2753 classes[1] = X86_64_X87UP_CLASS;
2756 classes[0] = X86_64_SSE_CLASS;
2757 classes[1] = X86_64_SSEUP_CLASS;
2760 classes[0] = X86_64_SSE_CLASS;
2763 classes[0] = X86_64_SSEDF_CLASS;
2764 classes[1] = X86_64_SSEDF_CLASS;
2767 classes[0] = X86_64_COMPLEX_X87_CLASS;
2770 /* This modes is larger than 16 bytes. */
2778 classes[0] = X86_64_SSE_CLASS;
2779 classes[1] = X86_64_SSEUP_CLASS;
2785 classes[0] = X86_64_SSE_CLASS;
2791 gcc_assert (VECTOR_MODE_P (mode));
2796 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
2798 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
2799 classes[0] = X86_64_INTEGERSI_CLASS;
2801 classes[0] = X86_64_INTEGER_CLASS;
2802 classes[1] = X86_64_INTEGER_CLASS;
2803 return 1 + (bytes > 8);
2807 /* Examine the argument and return set number of register required in each
2808 class. Return 0 iff parameter should be passed in memory. */
2810 examine_argument (enum machine_mode mode, tree type, int in_return,
2811 int *int_nregs, int *sse_nregs)
2813 enum x86_64_reg_class class[MAX_CLASSES];
2814 int n = classify_argument (mode, type, class, 0);
2820 for (n--; n >= 0; n--)
2823 case X86_64_INTEGER_CLASS:
2824 case X86_64_INTEGERSI_CLASS:
2827 case X86_64_SSE_CLASS:
2828 case X86_64_SSESF_CLASS:
2829 case X86_64_SSEDF_CLASS:
2832 case X86_64_NO_CLASS:
2833 case X86_64_SSEUP_CLASS:
2835 case X86_64_X87_CLASS:
2836 case X86_64_X87UP_CLASS:
2840 case X86_64_COMPLEX_X87_CLASS:
2841 return in_return ? 2 : 0;
2842 case X86_64_MEMORY_CLASS:
2848 /* Construct container for the argument used by GCC interface. See
2849 FUNCTION_ARG for the detailed description. */
2852 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
2853 tree type, int in_return, int nintregs, int nsseregs,
2854 const int *intreg, int sse_regno)
2856 enum machine_mode tmpmode;
2858 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
2859 enum x86_64_reg_class class[MAX_CLASSES];
2863 int needed_sseregs, needed_intregs;
2864 rtx exp[MAX_CLASSES];
2867 n = classify_argument (mode, type, class, 0);
2868 if (TARGET_DEBUG_ARG)
2871 fprintf (stderr, "Memory class\n");
2874 fprintf (stderr, "Classes:");
2875 for (i = 0; i < n; i++)
2877 fprintf (stderr, " %s", x86_64_reg_class_name[class[i]]);
2879 fprintf (stderr, "\n");
2884 if (!examine_argument (mode, type, in_return, &needed_intregs,
2887 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
2890 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
2891 some less clueful developer tries to use floating-point anyway. */
2892 if (needed_sseregs && !TARGET_SSE)
2894 static bool issued_error;
2897 issued_error = true;
2899 error ("SSE register return with SSE disabled");
2901 error ("SSE register argument with SSE disabled");
2906 /* First construct simple cases. Avoid SCmode, since we want to use
2907 single register to pass this type. */
2908 if (n == 1 && mode != SCmode)
2911 case X86_64_INTEGER_CLASS:
2912 case X86_64_INTEGERSI_CLASS:
2913 return gen_rtx_REG (mode, intreg[0]);
2914 case X86_64_SSE_CLASS:
2915 case X86_64_SSESF_CLASS:
2916 case X86_64_SSEDF_CLASS:
2917 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
2918 case X86_64_X87_CLASS:
2919 case X86_64_COMPLEX_X87_CLASS:
2920 return gen_rtx_REG (mode, FIRST_STACK_REG);
2921 case X86_64_NO_CLASS:
2922 /* Zero sized array, struct or class. */
2927 if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
2929 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
2931 && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
2932 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
2933 if (n == 2 && class[0] == X86_64_INTEGER_CLASS
2934 && class[1] == X86_64_INTEGER_CLASS
2935 && (mode == CDImode || mode == TImode || mode == TFmode)
2936 && intreg[0] + 1 == intreg[1])
2937 return gen_rtx_REG (mode, intreg[0]);
2939 /* Otherwise figure out the entries of the PARALLEL. */
2940 for (i = 0; i < n; i++)
2944 case X86_64_NO_CLASS:
2946 case X86_64_INTEGER_CLASS:
2947 case X86_64_INTEGERSI_CLASS:
2948 /* Merge TImodes on aligned occasions here too. */
2949 if (i * 8 + 8 > bytes)
2950 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
2951 else if (class[i] == X86_64_INTEGERSI_CLASS)
2955 /* We've requested 24 bytes we don't have mode for. Use DImode. */
2956 if (tmpmode == BLKmode)
2958 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
2959 gen_rtx_REG (tmpmode, *intreg),
2963 case X86_64_SSESF_CLASS:
2964 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
2965 gen_rtx_REG (SFmode,
2966 SSE_REGNO (sse_regno)),
2970 case X86_64_SSEDF_CLASS:
2971 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
2972 gen_rtx_REG (DFmode,
2973 SSE_REGNO (sse_regno)),
2977 case X86_64_SSE_CLASS:
2978 if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
2982 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
2983 gen_rtx_REG (tmpmode,
2984 SSE_REGNO (sse_regno)),
2986 if (tmpmode == TImode)
2995 /* Empty aligned struct, union or class. */
2999 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
3000 for (i = 0; i < nexps; i++)
3001 XVECEXP (ret, 0, i) = exp [i];
3005 /* Update the data in CUM to advance over an argument
3006 of mode MODE and data type TYPE.
3007 (TYPE is null for libcalls where that information may not be available.) */
3010 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3011 tree type, int named)
3014 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3015 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3018 mode = type_natural_mode (type);
3020 if (TARGET_DEBUG_ARG)
3021 fprintf (stderr, "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, "
3022 "mode=%s, named=%d)\n\n",
3023 words, cum->words, cum->nregs, cum->sse_nregs,
3024 GET_MODE_NAME (mode), named);
3028 int int_nregs, sse_nregs;
3029 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
3030 cum->words += words;
3031 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
3033 cum->nregs -= int_nregs;
3034 cum->sse_nregs -= sse_nregs;
3035 cum->regno += int_nregs;
3036 cum->sse_regno += sse_nregs;
3039 cum->words += words;
3057 cum->words += words;
3058 cum->nregs -= words;
3059 cum->regno += words;
3061 if (cum->nregs <= 0)
3069 if (cum->float_in_sse < 2)
3072 if (cum->float_in_sse < 1)
3083 if (!type || !AGGREGATE_TYPE_P (type))
3085 cum->sse_words += words;
3086 cum->sse_nregs -= 1;
3087 cum->sse_regno += 1;
3088 if (cum->sse_nregs <= 0)
3100 if (!type || !AGGREGATE_TYPE_P (type))
3102 cum->mmx_words += words;
3103 cum->mmx_nregs -= 1;
3104 cum->mmx_regno += 1;
3105 if (cum->mmx_nregs <= 0)
3116 /* Define where to put the arguments to a function.
3117 Value is zero to push the argument on the stack,
3118 or a hard register in which to store the argument.
3120 MODE is the argument's machine mode.
3121 TYPE is the data type of the argument (as a tree).
3122 This is null for libcalls where that information may
3124 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3125 the preceding args and about the function being called.
3126 NAMED is nonzero if this argument is a named parameter
3127 (otherwise it is an extra parameter matching an ellipsis). */
3130 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode,
3131 tree type, int named)
3133 enum machine_mode mode = orig_mode;
3136 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3137 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3138 static bool warnedsse, warnedmmx;
3140 /* To simplify the code below, represent vector types with a vector mode
3141 even if MMX/SSE are not active. */
3142 if (type && TREE_CODE (type) == VECTOR_TYPE)
3143 mode = type_natural_mode (type);
3145 /* Handle a hidden AL argument containing number of registers for varargs
3146 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
3148 if (mode == VOIDmode)
3151 return GEN_INT (cum->maybe_vaarg
3152 ? (cum->sse_nregs < 0
3160 ret = construct_container (mode, orig_mode, type, 0, cum->nregs,
3162 &x86_64_int_parameter_registers [cum->regno],
3167 /* For now, pass fp/complex values on the stack. */
3179 if (words <= cum->nregs)
3181 int regno = cum->regno;
3183 /* Fastcall allocates the first two DWORD (SImode) or
3184 smaller arguments to ECX and EDX. */
3187 if (mode == BLKmode || mode == DImode)
3190 /* ECX not EAX is the first allocated register. */
3194 ret = gen_rtx_REG (mode, regno);
3198 if (cum->float_in_sse < 2)
3201 if (cum->float_in_sse < 1)
3211 if (!type || !AGGREGATE_TYPE_P (type))
3213 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
3216 warning (0, "SSE vector argument without SSE enabled "
3220 ret = gen_reg_or_parallel (mode, orig_mode,
3221 cum->sse_regno + FIRST_SSE_REG);
3228 if (!type || !AGGREGATE_TYPE_P (type))
3230 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
3233 warning (0, "MMX vector argument without MMX enabled "
3237 ret = gen_reg_or_parallel (mode, orig_mode,
3238 cum->mmx_regno + FIRST_MMX_REG);
3243 if (TARGET_DEBUG_ARG)
3246 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
3247 words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);
3250 print_simple_rtl (stderr, ret);
3252 fprintf (stderr, ", stack");
3254 fprintf (stderr, " )\n");
3260 /* A C expression that indicates when an argument must be passed by
3261 reference. If nonzero for an argument, a copy of that argument is
3262 made in memory and a pointer to the argument is passed instead of
3263 the argument itself. The pointer is passed in whatever way is
3264 appropriate for passing a pointer to that type. */
3267 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3268 enum machine_mode mode ATTRIBUTE_UNUSED,
3269 tree type, bool named ATTRIBUTE_UNUSED)
3274 if (type && int_size_in_bytes (type) == -1)
3276 if (TARGET_DEBUG_ARG)
3277 fprintf (stderr, "function_arg_pass_by_reference\n");
3284 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
3285 ABI. Only called if TARGET_SSE. */
3287 contains_128bit_aligned_vector_p (tree type)
3289 enum machine_mode mode = TYPE_MODE (type);
3290 if (SSE_REG_MODE_P (mode)
3291 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
3293 if (TYPE_ALIGN (type) < 128)
3296 if (AGGREGATE_TYPE_P (type))
3298 /* Walk the aggregates recursively. */
3299 switch (TREE_CODE (type))
3303 case QUAL_UNION_TYPE:
3307 if (TYPE_BINFO (type))
3309 tree binfo, base_binfo;
3312 for (binfo = TYPE_BINFO (type), i = 0;
3313 BINFO_BASE_ITERATE (binfo, i, base_binfo); i++)
3314 if (contains_128bit_aligned_vector_p
3315 (BINFO_TYPE (base_binfo)))
3318 /* And now merge the fields of structure. */
3319 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3321 if (TREE_CODE (field) == FIELD_DECL
3322 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
3329 /* Just for use if some languages passes arrays by value. */
3330 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
3340 /* Gives the alignment boundary, in bits, of an argument with the
3341 specified mode and type. */
3344 ix86_function_arg_boundary (enum machine_mode mode, tree type)
3348 align = TYPE_ALIGN (type);
3350 align = GET_MODE_ALIGNMENT (mode);
3351 if (align < PARM_BOUNDARY)
3352 align = PARM_BOUNDARY;
3355 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
3356 make an exception for SSE modes since these require 128bit
3359 The handling here differs from field_alignment. ICC aligns MMX
3360 arguments to 4 byte boundaries, while structure fields are aligned
3361 to 8 byte boundaries. */
3363 align = PARM_BOUNDARY;
3366 if (!SSE_REG_MODE_P (mode))
3367 align = PARM_BOUNDARY;
3371 if (!contains_128bit_aligned_vector_p (type))
3372 align = PARM_BOUNDARY;
3380 /* Return true if N is a possible register number of function value. */
3382 ix86_function_value_regno_p (int regno)
3385 || (regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)
3386 || (regno == FIRST_SSE_REG && TARGET_SSE))
3390 && (regno == FIRST_MMX_REG && TARGET_MMX))
3396 /* Define how to find the value returned by a function.
3397 VALTYPE is the data type of the value (as a tree).
3398 If the precise function being called is known, FUNC is its FUNCTION_DECL;
3399 otherwise, FUNC is 0. */
3401 ix86_function_value (tree valtype, tree fntype_or_decl,
3402 bool outgoing ATTRIBUTE_UNUSED)
3404 enum machine_mode natmode = type_natural_mode (valtype);
3408 rtx ret = construct_container (natmode, TYPE_MODE (valtype), valtype,
3409 1, REGPARM_MAX, SSE_REGPARM_MAX,
3410 x86_64_int_return_registers, 0);
3411 /* For zero sized structures, construct_container return NULL, but we
3412 need to keep rest of compiler happy by returning meaningful value. */
3414 ret = gen_rtx_REG (TYPE_MODE (valtype), 0);
3419 tree fn = NULL_TREE, fntype;
3421 && DECL_P (fntype_or_decl))
3422 fn = fntype_or_decl;
3423 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
3424 return gen_rtx_REG (TYPE_MODE (valtype),
3425 ix86_value_regno (natmode, fn, fntype));
3429 /* Return false iff type is returned in memory. */
3431 ix86_return_in_memory (tree type)
3433 int needed_intregs, needed_sseregs, size;
3434 enum machine_mode mode = type_natural_mode (type);
3437 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
3439 if (mode == BLKmode)
3442 size = int_size_in_bytes (type);
3444 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
3447 if (VECTOR_MODE_P (mode) || mode == TImode)
3449 /* User-created vectors small enough to fit in EAX. */
3453 /* MMX/3dNow values are returned in MM0,
3454 except when it doesn't exits. */
3456 return (TARGET_MMX ? 0 : 1);
3458 /* SSE values are returned in XMM0, except when it doesn't exist. */
3460 return (TARGET_SSE ? 0 : 1);
3471 /* When returning SSE vector types, we have a choice of either
3472 (1) being abi incompatible with a -march switch, or
3473 (2) generating an error.
3474 Given no good solution, I think the safest thing is one warning.
3475 The user won't be able to use -Werror, but....
3477 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
3478 called in response to actually generating a caller or callee that
3479 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
3480 via aggregate_value_p for general type probing from tree-ssa. */
3483 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
3485 static bool warnedsse, warnedmmx;
3489 /* Look at the return type of the function, not the function type. */
3490 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
3492 if (!TARGET_SSE && !warnedsse)
3495 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3498 warning (0, "SSE vector return without SSE enabled "
3503 if (!TARGET_MMX && !warnedmmx)
3505 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
3508 warning (0, "MMX vector return without MMX enabled "
3517 /* Define how to find the value returned by a library function
3518 assuming the value has mode MODE. */
3520 ix86_libcall_value (enum machine_mode mode)
3531 return gen_rtx_REG (mode, FIRST_SSE_REG);
3534 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
3538 return gen_rtx_REG (mode, 0);
3542 return gen_rtx_REG (mode, ix86_value_regno (mode, NULL, NULL));
3545 /* Given a mode, return the register to use for a return value. */
3548 ix86_value_regno (enum machine_mode mode, tree func, tree fntype)
3550 gcc_assert (!TARGET_64BIT);
3552 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
3553 we prevent this case when mmx is not available. */
3554 if ((VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8))
3555 return FIRST_MMX_REG;
3557 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
3558 we prevent this case when sse is not available. */
3559 if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
3560 return FIRST_SSE_REG;
3562 /* Most things go in %eax, except (unless -mno-fp-ret-in-387) fp values. */
3563 if (GET_MODE_CLASS (mode) != MODE_FLOAT || !TARGET_FLOAT_RETURNS_IN_80387)
3566 /* Floating point return values in %st(0), except for local functions when
3567 SSE math is enabled or for functions with sseregparm attribute. */
3568 if ((func || fntype)
3569 && (mode == SFmode || mode == DFmode))
3571 int sse_level = ix86_function_sseregparm (fntype, func);
3572 if ((sse_level >= 1 && mode == SFmode)
3573 || (sse_level == 2 && mode == DFmode))
3574 return FIRST_SSE_REG;
3577 return FIRST_FLOAT_REG;
3580 /* Create the va_list data type. */
3583 ix86_build_builtin_va_list (void)
3585 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
3587 /* For i386 we use plain pointer to argument area. */
3589 return build_pointer_type (char_type_node);
3591 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3592 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
3594 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
3595 unsigned_type_node);
3596 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
3597 unsigned_type_node);
3598 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
3600 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
3603 va_list_gpr_counter_field = f_gpr;
3604 va_list_fpr_counter_field = f_fpr;
3606 DECL_FIELD_CONTEXT (f_gpr) = record;
3607 DECL_FIELD_CONTEXT (f_fpr) = record;
3608 DECL_FIELD_CONTEXT (f_ovf) = record;
3609 DECL_FIELD_CONTEXT (f_sav) = record;
3611 TREE_CHAIN (record) = type_decl;
3612 TYPE_NAME (record) = type_decl;
3613 TYPE_FIELDS (record) = f_gpr;
3614 TREE_CHAIN (f_gpr) = f_fpr;
3615 TREE_CHAIN (f_fpr) = f_ovf;
3616 TREE_CHAIN (f_ovf) = f_sav;
3618 layout_type (record);
3620 /* The correct type is an array type of one element. */
3621 return build_array_type (record, build_index_type (size_zero_node));
3624 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3627 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3628 tree type, int *pretend_size ATTRIBUTE_UNUSED,
3631 CUMULATIVE_ARGS next_cum;
3632 rtx save_area = NULL_RTX, mem;
3645 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
3648 /* Indicate to allocate space on the stack for varargs save area. */
3649 ix86_save_varrargs_registers = 1;
3651 cfun->stack_alignment_needed = 128;
3653 fntype = TREE_TYPE (current_function_decl);
3654 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
3655 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3656 != void_type_node));
3658 /* For varargs, we do not want to skip the dummy va_dcl argument.
3659 For stdargs, we do want to skip the last named argument. */
3662 function_arg_advance (&next_cum, mode, type, 1);
3665 save_area = frame_pointer_rtx;
3667 set = get_varargs_alias_set ();
3669 for (i = next_cum.regno;
3671 && i < next_cum.regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
3674 mem = gen_rtx_MEM (Pmode,
3675 plus_constant (save_area, i * UNITS_PER_WORD));
3676 set_mem_alias_set (mem, set);
3677 emit_move_insn (mem, gen_rtx_REG (Pmode,
3678 x86_64_int_parameter_registers[i]));
3681 if (next_cum.sse_nregs && cfun->va_list_fpr_size)
3683 /* Now emit code to save SSE registers. The AX parameter contains number
3684 of SSE parameter registers used to call this function. We use
3685 sse_prologue_save insn template that produces computed jump across
3686 SSE saves. We need some preparation work to get this working. */
3688 label = gen_label_rtx ();
3689 label_ref = gen_rtx_LABEL_REF (Pmode, label);
3691 /* Compute address to jump to :
3692 label - 5*eax + nnamed_sse_arguments*5 */
3693 tmp_reg = gen_reg_rtx (Pmode);
3694 nsse_reg = gen_reg_rtx (Pmode);
3695 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
3696 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
3697 gen_rtx_MULT (Pmode, nsse_reg,
3699 if (next_cum.sse_regno)
3702 gen_rtx_CONST (DImode,
3703 gen_rtx_PLUS (DImode,
3705 GEN_INT (next_cum.sse_regno * 4))));
3707 emit_move_insn (nsse_reg, label_ref);
3708 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
3710 /* Compute address of memory block we save into. We always use pointer
3711 pointing 127 bytes after first byte to store - this is needed to keep
3712 instruction size limited by 4 bytes. */
3713 tmp_reg = gen_reg_rtx (Pmode);
3714 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
3715 plus_constant (save_area,
3716 8 * REGPARM_MAX + 127)));
3717 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
3718 set_mem_alias_set (mem, set);
3719 set_mem_align (mem, BITS_PER_WORD);
3721 /* And finally do the dirty job! */
3722 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
3723 GEN_INT (next_cum.sse_regno), label));
3728 /* Implement va_start. */
3731 ix86_va_start (tree valist, rtx nextarg)
3733 HOST_WIDE_INT words, n_gpr, n_fpr;
3734 tree f_gpr, f_fpr, f_ovf, f_sav;
3735 tree gpr, fpr, ovf, sav, t;
3737 /* Only 64bit target needs something special. */
3740 std_expand_builtin_va_start (valist, nextarg);
3744 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
3745 f_fpr = TREE_CHAIN (f_gpr);
3746 f_ovf = TREE_CHAIN (f_fpr);
3747 f_sav = TREE_CHAIN (f_ovf);
3749 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
3750 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
3751 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
3752 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
3753 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
3755 /* Count number of gp and fp argument registers used. */
3756 words = current_function_args_info.words;
3757 n_gpr = current_function_args_info.regno;
3758 n_fpr = current_function_args_info.sse_regno;
3760 if (TARGET_DEBUG_ARG)
3761 fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
3762 (int) words, (int) n_gpr, (int) n_fpr);
3764 if (cfun->va_list_gpr_size)
3766 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
3767 build_int_cst (NULL_TREE, n_gpr * 8));
3768 TREE_SIDE_EFFECTS (t) = 1;
3769 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3772 if (cfun->va_list_fpr_size)
3774 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
3775 build_int_cst (NULL_TREE, n_fpr * 16 + 8*REGPARM_MAX));
3776 TREE_SIDE_EFFECTS (t) = 1;
3777 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3780 /* Find the overflow area. */
3781 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
3783 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
3784 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
3785 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
3786 TREE_SIDE_EFFECTS (t) = 1;
3787 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3789 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
3791 /* Find the register save area.
3792 Prologue of the function save it right above stack frame. */
3793 t = make_tree (TREE_TYPE (sav), frame_pointer_rtx);
3794 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
3795 TREE_SIDE_EFFECTS (t) = 1;
3796 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3800 /* Implement va_arg. */
3803 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
3805 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
3806 tree f_gpr, f_fpr, f_ovf, f_sav;
3807 tree gpr, fpr, ovf, sav, t;
3809 tree lab_false, lab_over = NULL_TREE;
3814 enum machine_mode nat_mode;
3816 /* Only 64bit target needs something special. */
3818 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
3820 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
3821 f_fpr = TREE_CHAIN (f_gpr);
3822 f_ovf = TREE_CHAIN (f_fpr);
3823 f_sav = TREE_CHAIN (f_ovf);
3825 valist = build_va_arg_indirect_ref (valist);
3826 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
3827 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
3828 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
3829 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
3831 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
3833 type = build_pointer_type (type);
3834 size = int_size_in_bytes (type);
3835 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3837 nat_mode = type_natural_mode (type);
3838 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
3839 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
3841 /* Pull the value out of the saved registers. */
3843 addr = create_tmp_var (ptr_type_node, "addr");
3844 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
3848 int needed_intregs, needed_sseregs;
3850 tree int_addr, sse_addr;
3852 lab_false = create_artificial_label ();
3853 lab_over = create_artificial_label ();
3855 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
3857 need_temp = (!REG_P (container)
3858 && ((needed_intregs && TYPE_ALIGN (type) > 64)
3859 || TYPE_ALIGN (type) > 128));
3861 /* In case we are passing structure, verify that it is consecutive block
3862 on the register save area. If not we need to do moves. */
3863 if (!need_temp && !REG_P (container))
3865 /* Verify that all registers are strictly consecutive */
3866 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
3870 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
3872 rtx slot = XVECEXP (container, 0, i);
3873 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
3874 || INTVAL (XEXP (slot, 1)) != i * 16)
3882 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
3884 rtx slot = XVECEXP (container, 0, i);
3885 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
3886 || INTVAL (XEXP (slot, 1)) != i * 8)
3898 int_addr = create_tmp_var (ptr_type_node, "int_addr");
3899 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
3900 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
3901 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
3904 /* First ensure that we fit completely in registers. */
3907 t = build_int_cst (TREE_TYPE (gpr),
3908 (REGPARM_MAX - needed_intregs + 1) * 8);
3909 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
3910 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
3911 t = build (COND_EXPR, void_type_node, t, t2, NULL_TREE);
3912 gimplify_and_add (t, pre_p);
3916 t = build_int_cst (TREE_TYPE (fpr),
3917 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
3919 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
3920 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
3921 t = build (COND_EXPR, void_type_node, t, t2, NULL_TREE);
3922 gimplify_and_add (t, pre_p);
3925 /* Compute index to start of area used for integer regs. */
3928 /* int_addr = gpr + sav; */
3929 t = fold_convert (ptr_type_node, gpr);
3930 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
3931 t = build2 (MODIFY_EXPR, void_type_node, int_addr, t);
3932 gimplify_and_add (t, pre_p);
3936 /* sse_addr = fpr + sav; */
3937 t = fold_convert (ptr_type_node, fpr);
3938 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
3939 t = build2 (MODIFY_EXPR, void_type_node, sse_addr, t);
3940 gimplify_and_add (t, pre_p);
3945 tree temp = create_tmp_var (type, "va_arg_tmp");
3948 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
3949 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
3950 gimplify_and_add (t, pre_p);
3952 for (i = 0; i < XVECLEN (container, 0); i++)
3954 rtx slot = XVECEXP (container, 0, i);
3955 rtx reg = XEXP (slot, 0);
3956 enum machine_mode mode = GET_MODE (reg);
3957 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
3958 tree addr_type = build_pointer_type (piece_type);
3961 tree dest_addr, dest;
3963 if (SSE_REGNO_P (REGNO (reg)))
3965 src_addr = sse_addr;
3966 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
3970 src_addr = int_addr;
3971 src_offset = REGNO (reg) * 8;
3973 src_addr = fold_convert (addr_type, src_addr);
3974 src_addr = fold (build2 (PLUS_EXPR, addr_type, src_addr,
3975 size_int (src_offset)));
3976 src = build_va_arg_indirect_ref (src_addr);
3978 dest_addr = fold_convert (addr_type, addr);
3979 dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr,
3980 size_int (INTVAL (XEXP (slot, 1)))));
3981 dest = build_va_arg_indirect_ref (dest_addr);
3983 t = build2 (MODIFY_EXPR, void_type_node, dest, src);
3984 gimplify_and_add (t, pre_p);
3990 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
3991 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
3992 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
3993 gimplify_and_add (t, pre_p);
3997 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
3998 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
3999 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
4000 gimplify_and_add (t, pre_p);
4003 t = build1 (GOTO_EXPR, void_type_node, lab_over);
4004 gimplify_and_add (t, pre_p);
4006 t = build1 (LABEL_EXPR, void_type_node, lab_false);
4007 append_to_statement_list (t, pre_p);
4010 /* ... otherwise out of the overflow area. */
4012 /* Care for on-stack alignment if needed. */
4013 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64)
4017 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
4018 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf,
4019 build_int_cst (TREE_TYPE (ovf), align - 1));
4020 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4021 build_int_cst (TREE_TYPE (t), -align));
4023 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
4025 t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
4026 gimplify_and_add (t2, pre_p);
4028 t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
4029 build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD));
4030 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4031 gimplify_and_add (t, pre_p);
4035 t = build1 (LABEL_EXPR, void_type_node, lab_over);
4036 append_to_statement_list (t, pre_p);
4039 ptrtype = build_pointer_type (type);
4040 addr = fold_convert (ptrtype, addr);
4043 addr = build_va_arg_indirect_ref (addr);
4044 return build_va_arg_indirect_ref (addr);
4047 /* Return nonzero if OPNUM's MEM should be matched
4048 in movabs* patterns. */
4051 ix86_check_movabs (rtx insn, int opnum)
4055 set = PATTERN (insn);
4056 if (GET_CODE (set) == PARALLEL)
4057 set = XVECEXP (set, 0, 0);
4058 gcc_assert (GET_CODE (set) == SET);
4059 mem = XEXP (set, opnum);
4060 while (GET_CODE (mem) == SUBREG)
4061 mem = SUBREG_REG (mem);
4062 gcc_assert (GET_CODE (mem) == MEM);
4063 return (volatile_ok || !MEM_VOLATILE_P (mem));
4066 /* Initialize the table of extra 80387 mathematical constants. */
4069 init_ext_80387_constants (void)
4071 static const char * cst[5] =
4073 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
4074 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
4075 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
4076 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
4077 "3.1415926535897932385128089594061862044", /* 4: fldpi */
4081 for (i = 0; i < 5; i++)
4083 real_from_string (&ext_80387_constants_table[i], cst[i]);
4084 /* Ensure each constant is rounded to XFmode precision. */
4085 real_convert (&ext_80387_constants_table[i],
4086 XFmode, &ext_80387_constants_table[i]);
4089 ext_80387_constants_init = 1;
4092 /* Return true if the constant is something that can be loaded with
4093 a special instruction. */
4096 standard_80387_constant_p (rtx x)
4098 if (GET_CODE (x) != CONST_DOUBLE || !FLOAT_MODE_P (GET_MODE (x)))
4101 if (x == CONST0_RTX (GET_MODE (x)))
4103 if (x == CONST1_RTX (GET_MODE (x)))
4106 /* For XFmode constants, try to find a special 80387 instruction when
4107 optimizing for size or on those CPUs that benefit from them. */
4108 if (GET_MODE (x) == XFmode
4109 && (optimize_size || x86_ext_80387_constants & TUNEMASK))
4114 if (! ext_80387_constants_init)
4115 init_ext_80387_constants ();
4117 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4118 for (i = 0; i < 5; i++)
4119 if (real_identical (&r, &ext_80387_constants_table[i]))
4126 /* Return the opcode of the special instruction to be used to load
4130 standard_80387_constant_opcode (rtx x)
4132 switch (standard_80387_constant_p (x))
4153 /* Return the CONST_DOUBLE representing the 80387 constant that is
4154 loaded by the specified special instruction. The argument IDX
4155 matches the return value from standard_80387_constant_p. */
4158 standard_80387_constant_rtx (int idx)
4162 if (! ext_80387_constants_init)
4163 init_ext_80387_constants ();
4179 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
4183 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
4186 standard_sse_constant_p (rtx x)
4188 if (x == const0_rtx)
4190 return (x == CONST0_RTX (GET_MODE (x)));
4193 /* Returns 1 if OP contains a symbol reference */
4196 symbolic_reference_mentioned_p (rtx op)
4201 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
4204 fmt = GET_RTX_FORMAT (GET_CODE (op));
4205 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
4211 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
4212 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
4216 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
4223 /* Return 1 if it is appropriate to emit `ret' instructions in the
4224 body of a function. Do this only if the epilogue is simple, needing a
4225 couple of insns. Prior to reloading, we can't tell how many registers
4226 must be saved, so return 0 then. Return 0 if there is no frame
4227 marker to de-allocate. */
4230 ix86_can_use_return_insn_p (void)
4232 struct ix86_frame frame;
4234 if (! reload_completed || frame_pointer_needed)
4237 /* Don't allow more than 32 pop, since that's all we can do
4238 with one instruction. */
4239 if (current_function_pops_args
4240 && current_function_args_size >= 32768)
4243 ix86_compute_frame_layout (&frame);
4244 return frame.to_allocate == 0 && frame.nregs == 0;
4247 /* Value should be nonzero if functions must have frame pointers.
4248 Zero means the frame pointer need not be set up (and parms may
4249 be accessed via the stack pointer) in functions that seem suitable. */
4252 ix86_frame_pointer_required (void)
4254 /* If we accessed previous frames, then the generated code expects
4255 to be able to access the saved ebp value in our frame. */
4256 if (cfun->machine->accesses_prev_frame)
4259 /* Several x86 os'es need a frame pointer for other reasons,
4260 usually pertaining to setjmp. */
4261 if (SUBTARGET_FRAME_POINTER_REQUIRED)
4264 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
4265 the frame pointer by default. Turn it back on now if we've not
4266 got a leaf function. */
4267 if (TARGET_OMIT_LEAF_FRAME_POINTER
4268 && (!current_function_is_leaf))
4271 if (current_function_profile)
4277 /* Record that the current function accesses previous call frames. */
4280 ix86_setup_frame_addresses (void)
4282 cfun->machine->accesses_prev_frame = 1;
4285 #if defined(HAVE_GAS_HIDDEN) && defined(SUPPORTS_ONE_ONLY)
4286 # define USE_HIDDEN_LINKONCE 1
4288 # define USE_HIDDEN_LINKONCE 0
4291 static int pic_labels_used;
4293 /* Fills in the label name that should be used for a pc thunk for
4294 the given register. */
4297 get_pc_thunk_name (char name[32], unsigned int regno)
4299 if (USE_HIDDEN_LINKONCE)
4300 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
4302 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
4306 /* This function generates code for -fpic that loads %ebx with
4307 the return address of the caller and then returns. */
4310 ix86_file_end (void)
4315 for (regno = 0; regno < 8; ++regno)
4319 if (! ((pic_labels_used >> regno) & 1))
4322 get_pc_thunk_name (name, regno);
4324 if (USE_HIDDEN_LINKONCE)
4328 decl = build_decl (FUNCTION_DECL, get_identifier (name),
4330 TREE_PUBLIC (decl) = 1;
4331 TREE_STATIC (decl) = 1;
4332 DECL_ONE_ONLY (decl) = 1;
4334 (*targetm.asm_out.unique_section) (decl, 0);
4335 named_section (decl, NULL, 0);
4337 (*targetm.asm_out.globalize_label) (asm_out_file, name);
4338 fputs ("\t.hidden\t", asm_out_file);
4339 assemble_name (asm_out_file, name);
4340 fputc ('\n', asm_out_file);
4341 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
4346 ASM_OUTPUT_LABEL (asm_out_file, name);
4349 xops[0] = gen_rtx_REG (SImode, regno);
4350 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
4351 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
4352 output_asm_insn ("ret", xops);
4355 if (NEED_INDICATE_EXEC_STACK)
4356 file_end_indicate_exec_stack ();
4359 /* Emit code for the SET_GOT patterns. */
4362 output_set_got (rtx dest)
4367 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
4369 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
4371 xops[2] = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());
4374 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
4376 output_asm_insn ("call\t%a2", xops);
4379 /* Output the "canonical" label name ("Lxx$pb") here too. This
4380 is what will be referred to by the Mach-O PIC subsystem. */
4381 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
4383 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4384 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
4387 output_asm_insn ("pop{l}\t%0", xops);
4392 get_pc_thunk_name (name, REGNO (dest));
4393 pic_labels_used |= 1 << REGNO (dest);
4395 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
4396 xops[2] = gen_rtx_MEM (QImode, xops[2]);
4397 output_asm_insn ("call\t%X2", xops);
4400 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
4401 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
4402 else if (!TARGET_MACHO)
4403 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
4408 /* Generate an "push" pattern for input ARG. */
4413 return gen_rtx_SET (VOIDmode,
4415 gen_rtx_PRE_DEC (Pmode,
4416 stack_pointer_rtx)),
4420 /* Return >= 0 if there is an unused call-clobbered register available
4421 for the entire function. */
4424 ix86_select_alt_pic_regnum (void)
4426 if (current_function_is_leaf && !current_function_profile)
4429 for (i = 2; i >= 0; --i)
4430 if (!regs_ever_live[i])
4434 return INVALID_REGNUM;
4437 /* Return 1 if we need to save REGNO. */
4439 ix86_save_reg (unsigned int regno, int maybe_eh_return)
4441 if (pic_offset_table_rtx
4442 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
4443 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
4444 || current_function_profile
4445 || current_function_calls_eh_return
4446 || current_function_uses_const_pool))
4448 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
4453 if (current_function_calls_eh_return && maybe_eh_return)
4458 unsigned test = EH_RETURN_DATA_REGNO (i);
4459 if (test == INVALID_REGNUM)
4466 return (regs_ever_live[regno]
4467 && !call_used_regs[regno]
4468 && !fixed_regs[regno]
4469 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
4472 /* Return number of registers to be saved on the stack. */
4475 ix86_nsaved_regs (void)
4480 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
4481 if (ix86_save_reg (regno, true))
4486 /* Return the offset between two registers, one to be eliminated, and the other
4487 its replacement, at the start of a routine. */
4490 ix86_initial_elimination_offset (int from, int to)
4492 struct ix86_frame frame;
4493 ix86_compute_frame_layout (&frame);
4495 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
4496 return frame.hard_frame_pointer_offset;
4497 else if (from == FRAME_POINTER_REGNUM
4498 && to == HARD_FRAME_POINTER_REGNUM)
4499 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
4502 gcc_assert (to == STACK_POINTER_REGNUM);
4504 if (from == ARG_POINTER_REGNUM)
4505 return frame.stack_pointer_offset;
4507 gcc_assert (from == FRAME_POINTER_REGNUM);
4508 return frame.stack_pointer_offset - frame.frame_pointer_offset;
4512 /* Fill structure ix86_frame about frame of currently computed function. */
4515 ix86_compute_frame_layout (struct ix86_frame *frame)
4517 HOST_WIDE_INT total_size;
4518 unsigned int stack_alignment_needed;
4519 HOST_WIDE_INT offset;
4520 unsigned int preferred_alignment;
4521 HOST_WIDE_INT size = get_frame_size ();
4523 frame->nregs = ix86_nsaved_regs ();
4526 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
4527 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
4529 /* During reload iteration the amount of registers saved can change.
4530 Recompute the value as needed. Do not recompute when amount of registers
4531 didn't change as reload does multiple calls to the function and does not
4532 expect the decision to change within single iteration. */
4534 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
4536 int count = frame->nregs;
4538 cfun->machine->use_fast_prologue_epilogue_nregs = count;
4539 /* The fast prologue uses move instead of push to save registers. This
4540 is significantly longer, but also executes faster as modern hardware
4541 can execute the moves in parallel, but can't do that for push/pop.
4543 Be careful about choosing what prologue to emit: When function takes
4544 many instructions to execute we may use slow version as well as in
4545 case function is known to be outside hot spot (this is known with
4546 feedback only). Weight the size of function by number of registers
4547 to save as it is cheap to use one or two push instructions but very
4548 slow to use many of them. */
4550 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
4551 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
4552 || (flag_branch_probabilities
4553 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
4554 cfun->machine->use_fast_prologue_epilogue = false;
4556 cfun->machine->use_fast_prologue_epilogue
4557 = !expensive_function_p (count);
4559 if (TARGET_PROLOGUE_USING_MOVE
4560 && cfun->machine->use_fast_prologue_epilogue)
4561 frame->save_regs_using_mov = true;
4563 frame->save_regs_using_mov = false;
4566 /* Skip return address and saved base pointer. */
4567 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
4569 frame->hard_frame_pointer_offset = offset;
4571 /* Do some sanity checking of stack_alignment_needed and
4572 preferred_alignment, since i386 port is the only using those features
4573 that may break easily. */
4575 gcc_assert (!size || stack_alignment_needed);
4576 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
4577 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
4578 gcc_assert (stack_alignment_needed
4579 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
4581 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
4582 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
4584 /* Register save area */
4585 offset += frame->nregs * UNITS_PER_WORD;
4588 if (ix86_save_varrargs_registers)
4590 offset += X86_64_VARARGS_SIZE;
4591 frame->va_arg_size = X86_64_VARARGS_SIZE;
4594 frame->va_arg_size = 0;
4596 /* Align start of frame for local function. */
4597 frame->padding1 = ((offset + stack_alignment_needed - 1)
4598 & -stack_alignment_needed) - offset;
4600 offset += frame->padding1;
4602 /* Frame pointer points here. */
4603 frame->frame_pointer_offset = offset;
4607 /* Add outgoing arguments area. Can be skipped if we eliminated
4608 all the function calls as dead code.
4609 Skipping is however impossible when function calls alloca. Alloca
4610 expander assumes that last current_function_outgoing_args_size
4611 of stack frame are unused. */
4612 if (ACCUMULATE_OUTGOING_ARGS
4613 && (!current_function_is_leaf || current_function_calls_alloca))
4615 offset += current_function_outgoing_args_size;
4616 frame->outgoing_arguments_size = current_function_outgoing_args_size;
4619 frame->outgoing_arguments_size = 0;
4621 /* Align stack boundary. Only needed if we're calling another function
4623 if (!current_function_is_leaf || current_function_calls_alloca)
4624 frame->padding2 = ((offset + preferred_alignment - 1)
4625 & -preferred_alignment) - offset;
4627 frame->padding2 = 0;
4629 offset += frame->padding2;
4631 /* We've reached end of stack frame. */
4632 frame->stack_pointer_offset = offset;
4634 /* Size prologue needs to allocate. */
4635 frame->to_allocate =
4636 (size + frame->padding1 + frame->padding2
4637 + frame->outgoing_arguments_size + frame->va_arg_size);
4639 if ((!frame->to_allocate && frame->nregs <= 1)
4640 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
4641 frame->save_regs_using_mov = false;
4643 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
4644 && current_function_is_leaf)
4646 frame->red_zone_size = frame->to_allocate;
4647 if (frame->save_regs_using_mov)
4648 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
4649 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
4650 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
4653 frame->red_zone_size = 0;
4654 frame->to_allocate -= frame->red_zone_size;
4655 frame->stack_pointer_offset -= frame->red_zone_size;
4657 fprintf (stderr, "nregs: %i\n", frame->nregs);
4658 fprintf (stderr, "size: %i\n", size);
4659 fprintf (stderr, "alignment1: %i\n", stack_alignment_needed);
4660 fprintf (stderr, "padding1: %i\n", frame->padding1);
4661 fprintf (stderr, "va_arg: %i\n", frame->va_arg_size);
4662 fprintf (stderr, "padding2: %i\n", frame->padding2);
4663 fprintf (stderr, "to_allocate: %i\n", frame->to_allocate);
4664 fprintf (stderr, "red_zone_size: %i\n", frame->red_zone_size);
4665 fprintf (stderr, "frame_pointer_offset: %i\n", frame->frame_pointer_offset);
4666 fprintf (stderr, "hard_frame_pointer_offset: %i\n",
4667 frame->hard_frame_pointer_offset);
4668 fprintf (stderr, "stack_pointer_offset: %i\n", frame->stack_pointer_offset);
4672 /* Emit code to save registers in the prologue. */
4675 ix86_emit_save_regs (void)
4680 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
4681 if (ix86_save_reg (regno, true))
4683 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
4684 RTX_FRAME_RELATED_P (insn) = 1;
4688 /* Emit code to save registers using MOV insns. First register
4689 is restored from POINTER + OFFSET. */
4691 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
4696 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4697 if (ix86_save_reg (regno, true))
4699 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
4701 gen_rtx_REG (Pmode, regno));
4702 RTX_FRAME_RELATED_P (insn) = 1;
4703 offset += UNITS_PER_WORD;
4707 /* Expand prologue or epilogue stack adjustment.
4708 The pattern exist to put a dependency on all ebp-based memory accesses.
4709 STYLE should be negative if instructions should be marked as frame related,
4710 zero if %r11 register is live and cannot be freely used and positive
4714 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
4719 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
4720 else if (x86_64_immediate_operand (offset, DImode))
4721 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
4725 /* r11 is used by indirect sibcall return as well, set before the
4726 epilogue and used after the epilogue. ATM indirect sibcall
4727 shouldn't be used together with huge frame sizes in one
4728 function because of the frame_size check in sibcall.c. */
4730 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
4731 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
4733 RTX_FRAME_RELATED_P (insn) = 1;
4734 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
4738 RTX_FRAME_RELATED_P (insn) = 1;
4741 /* Expand the prologue into a bunch of separate insns. */
4744 ix86_expand_prologue (void)
4748 struct ix86_frame frame;
4749 HOST_WIDE_INT allocate;
4751 ix86_compute_frame_layout (&frame);
4753 /* Note: AT&T enter does NOT have reversed args. Enter is probably
4754 slower on all targets. Also sdb doesn't like it. */
4756 if (frame_pointer_needed)
4758 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
4759 RTX_FRAME_RELATED_P (insn) = 1;
4761 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
4762 RTX_FRAME_RELATED_P (insn) = 1;
4765 allocate = frame.to_allocate;
4767 if (!frame.save_regs_using_mov)
4768 ix86_emit_save_regs ();
4770 allocate += frame.nregs * UNITS_PER_WORD;
4772 /* When using red zone we may start register saving before allocating
4773 the stack frame saving one cycle of the prologue. */
4774 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
4775 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
4776 : stack_pointer_rtx,
4777 -frame.nregs * UNITS_PER_WORD);
4781 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
4782 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
4783 GEN_INT (-allocate), -1);
4786 /* Only valid for Win32. */
4787 rtx eax = gen_rtx_REG (SImode, 0);
4788 bool eax_live = ix86_eax_live_at_start_p ();
4791 gcc_assert (!TARGET_64BIT);
4795 emit_insn (gen_push (eax));
4799 emit_move_insn (eax, GEN_INT (allocate));
4801 insn = emit_insn (gen_allocate_stack_worker (eax));
4802 RTX_FRAME_RELATED_P (insn) = 1;
4803 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
4804 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
4805 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4806 t, REG_NOTES (insn));
4810 if (frame_pointer_needed)
4811 t = plus_constant (hard_frame_pointer_rtx,
4814 - frame.nregs * UNITS_PER_WORD);
4816 t = plus_constant (stack_pointer_rtx, allocate);
4817 emit_move_insn (eax, gen_rtx_MEM (SImode, t));
4821 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
4823 if (!frame_pointer_needed || !frame.to_allocate)
4824 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
4826 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
4827 -frame.nregs * UNITS_PER_WORD);
4830 pic_reg_used = false;
4831 if (pic_offset_table_rtx
4832 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
4833 || current_function_profile))
4835 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
4837 if (alt_pic_reg_used != INVALID_REGNUM)
4838 REGNO (pic_offset_table_rtx) = alt_pic_reg_used;
4840 pic_reg_used = true;
4846 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
4848 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
4850 /* Even with accurate pre-reload life analysis, we can wind up
4851 deleting all references to the pic register after reload.
4852 Consider if cross-jumping unifies two sides of a branch
4853 controlled by a comparison vs the only read from a global.
4854 In which case, allow the set_got to be deleted, though we're
4855 too late to do anything about the ebx save in the prologue. */
4856 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
4859 /* Prevent function calls from be scheduled before the call to mcount.
4860 In the pic_reg_used case, make sure that the got load isn't deleted. */
4861 if (current_function_profile)
4862 emit_insn (gen_blockage (pic_reg_used ? pic_offset_table_rtx : const0_rtx));
4865 /* Emit code to restore saved registers using MOV insns. First register
4866 is restored from POINTER + OFFSET. */
4868 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
4869 int maybe_eh_return)
4872 rtx base_address = gen_rtx_MEM (Pmode, pointer);
4874 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4875 if (ix86_save_reg (regno, maybe_eh_return))
4877 /* Ensure that adjust_address won't be forced to produce pointer
4878 out of range allowed by x86-64 instruction set. */
4879 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
4883 r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
4884 emit_move_insn (r11, GEN_INT (offset));
4885 emit_insn (gen_adddi3 (r11, r11, pointer));
4886 base_address = gen_rtx_MEM (Pmode, r11);
4889 emit_move_insn (gen_rtx_REG (Pmode, regno),
4890 adjust_address (base_address, Pmode, offset));
4891 offset += UNITS_PER_WORD;
4895 /* Restore function stack, frame, and registers. */
4898 ix86_expand_epilogue (int style)
4901 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
4902 struct ix86_frame frame;
4903 HOST_WIDE_INT offset;
4905 ix86_compute_frame_layout (&frame);
4907 /* Calculate start of saved registers relative to ebp. Special care
4908 must be taken for the normal return case of a function using
4909 eh_return: the eax and edx registers are marked as saved, but not
4910 restored along this path. */
4911 offset = frame.nregs;
4912 if (current_function_calls_eh_return && style != 2)
4914 offset *= -UNITS_PER_WORD;
4916 /* If we're only restoring one register and sp is not valid then
4917 using a move instruction to restore the register since it's
4918 less work than reloading sp and popping the register.
4920 The default code result in stack adjustment using add/lea instruction,
4921 while this code results in LEAVE instruction (or discrete equivalent),
4922 so it is profitable in some other cases as well. Especially when there
4923 are no registers to restore. We also use this code when TARGET_USE_LEAVE
4924 and there is exactly one register to pop. This heuristic may need some
4925 tuning in future. */
4926 if ((!sp_valid && frame.nregs <= 1)
4927 || (TARGET_EPILOGUE_USING_MOVE
4928 && cfun->machine->use_fast_prologue_epilogue
4929 && (frame.nregs > 1 || frame.to_allocate))
4930 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
4931 || (frame_pointer_needed && TARGET_USE_LEAVE
4932 && cfun->machine->use_fast_prologue_epilogue
4933 && frame.nregs == 1)
4934 || current_function_calls_eh_return)
4936 /* Restore registers. We can use ebp or esp to address the memory
4937 locations. If both are available, default to ebp, since offsets
4938 are known to be small. Only exception is esp pointing directly to the
4939 end of block of saved registers, where we may simplify addressing
4942 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
4943 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
4944 frame.to_allocate, style == 2);
4946 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
4947 offset, style == 2);
4949 /* eh_return epilogues need %ecx added to the stack pointer. */
4952 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
4954 if (frame_pointer_needed)
4956 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
4957 tmp = plus_constant (tmp, UNITS_PER_WORD);
4958 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
4960 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
4961 emit_move_insn (hard_frame_pointer_rtx, tmp);
4963 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
4968 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
4969 tmp = plus_constant (tmp, (frame.to_allocate
4970 + frame.nregs * UNITS_PER_WORD));
4971 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
4974 else if (!frame_pointer_needed)
4975 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
4976 GEN_INT (frame.to_allocate
4977 + frame.nregs * UNITS_PER_WORD),
4979 /* If not an i386, mov & pop is faster than "leave". */
4980 else if (TARGET_USE_LEAVE || optimize_size
4981 || !cfun->machine->use_fast_prologue_epilogue)
4982 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
4985 pro_epilogue_adjust_stack (stack_pointer_rtx,
4986 hard_frame_pointer_rtx,
4989 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
4991 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
4996 /* First step is to deallocate the stack frame so that we can
4997 pop the registers. */
5000 gcc_assert (frame_pointer_needed);
5001 pro_epilogue_adjust_stack (stack_pointer_rtx,
5002 hard_frame_pointer_rtx,
5003 GEN_INT (offset), style);
5005 else if (frame.to_allocate)
5006 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5007 GEN_INT (frame.to_allocate), style);
5009 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5010 if (ix86_save_reg (regno, false))
5013 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
5015 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
5017 if (frame_pointer_needed)
5019 /* Leave results in shorter dependency chains on CPUs that are
5020 able to grok it fast. */
5021 if (TARGET_USE_LEAVE)
5022 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
5023 else if (TARGET_64BIT)
5024 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
5026 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
5030 /* Sibcall epilogues don't want a return instruction. */
5034 if (current_function_pops_args && current_function_args_size)
5036 rtx popc = GEN_INT (current_function_pops_args);
5038 /* i386 can only pop 64K bytes. If asked to pop more, pop
5039 return address, do explicit add, and jump indirectly to the
5042 if (current_function_pops_args >= 65536)
5044 rtx ecx = gen_rtx_REG (SImode, 2);
5046 /* There is no "pascal" calling convention in 64bit ABI. */
5047 gcc_assert (!TARGET_64BIT);
5049 emit_insn (gen_popsi1 (ecx));
5050 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
5051 emit_jump_insn (gen_return_indirect_internal (ecx));
5054 emit_jump_insn (gen_return_pop_internal (popc));
5057 emit_jump_insn (gen_return_internal ());
5060 /* Reset from the function's potential modifications. */
5063 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5064 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5066 if (pic_offset_table_rtx)
5067 REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM;
5070 /* Extract the parts of an RTL expression that is a valid memory address
5071 for an instruction. Return 0 if the structure of the address is
5072 grossly off. Return -1 if the address contains ASHIFT, so it is not
5073 strictly valid, but still used for computing length of lea instruction. */
5076 ix86_decompose_address (rtx addr, struct ix86_address *out)
5078 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
5079 rtx base_reg, index_reg;
5080 HOST_WIDE_INT scale = 1;
5081 rtx scale_rtx = NULL_RTX;
5083 enum ix86_address_seg seg = SEG_DEFAULT;
5085 if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
5087 else if (GET_CODE (addr) == PLUS)
5097 addends[n++] = XEXP (op, 1);
5100 while (GET_CODE (op) == PLUS);
5105 for (i = n; i >= 0; --i)
5108 switch (GET_CODE (op))
5113 index = XEXP (op, 0);
5114 scale_rtx = XEXP (op, 1);
5118 if (XINT (op, 1) == UNSPEC_TP
5119 && TARGET_TLS_DIRECT_SEG_REFS
5120 && seg == SEG_DEFAULT)
5121 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
5150 else if (GET_CODE (addr) == MULT)
5152 index = XEXP (addr, 0); /* index*scale */
5153 scale_rtx = XEXP (addr, 1);
5155 else if (GET_CODE (addr) == ASHIFT)
5159 /* We're called for lea too, which implements ashift on occasion. */
5160 index = XEXP (addr, 0);
5161 tmp = XEXP (addr, 1);
5162 if (GET_CODE (tmp) != CONST_INT)
5164 scale = INTVAL (tmp);
5165 if ((unsigned HOST_WIDE_INT) scale > 3)
5171 disp = addr; /* displacement */
5173 /* Extract the integral value of scale. */
5176 if (GET_CODE (scale_rtx) != CONST_INT)
5178 scale = INTVAL (scale_rtx);
5181 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
5182 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
5184 /* Allow arg pointer and stack pointer as index if there is not scaling. */
5185 if (base_reg && index_reg && scale == 1
5186 && (index_reg == arg_pointer_rtx
5187 || index_reg == frame_pointer_rtx
5188 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
5191 tmp = base, base = index, index = tmp;
5192 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
5195 /* Special case: %ebp cannot be encoded as a base without a displacement. */
5196 if ((base_reg == hard_frame_pointer_rtx
5197 || base_reg == frame_pointer_rtx
5198 || base_reg == arg_pointer_rtx) && !disp)
5201 /* Special case: on K6, [%esi] makes the instruction vector decoded.
5202 Avoid this by transforming to [%esi+0]. */
5203 if (ix86_tune == PROCESSOR_K6 && !optimize_size
5204 && base_reg && !index_reg && !disp
5206 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
5209 /* Special case: encode reg+reg instead of reg*2. */
5210 if (!base && index && scale && scale == 2)
5211 base = index, base_reg = index_reg, scale = 1;
5213 /* Special case: scaling cannot be encoded without base or displacement. */
5214 if (!base && !disp && index && scale != 1)
5226 /* Return cost of the memory address x.
5227 For i386, it is better to use a complex address than let gcc copy
5228 the address into a reg and make a new pseudo. But not if the address
5229 requires to two regs - that would mean more pseudos with longer
5232 ix86_address_cost (rtx x)
5234 struct ix86_address parts;
5236 int ok = ix86_decompose_address (x, &parts);
5240 if (parts.base && GET_CODE (parts.base) == SUBREG)
5241 parts.base = SUBREG_REG (parts.base);
5242 if (parts.index && GET_CODE (parts.index) == SUBREG)
5243 parts.index = SUBREG_REG (parts.index);
5245 /* More complex memory references are better. */
5246 if (parts.disp && parts.disp != const0_rtx)
5248 if (parts.seg != SEG_DEFAULT)
5251 /* Attempt to minimize number of registers in the address. */
5253 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
5255 && (!REG_P (parts.index)
5256 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
5260 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
5262 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
5263 && parts.base != parts.index)
5266 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
5267 since it's predecode logic can't detect the length of instructions
5268 and it degenerates to vector decoded. Increase cost of such
5269 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
5270 to split such addresses or even refuse such addresses at all.
5272 Following addressing modes are affected:
5277 The first and last case may be avoidable by explicitly coding the zero in
5278 memory address, but I don't have AMD-K6 machine handy to check this
5282 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
5283 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
5284 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
5290 /* If X is a machine specific address (i.e. a symbol or label being
5291 referenced as a displacement from the GOT implemented using an
5292 UNSPEC), then return the base term. Otherwise return X. */
5295 ix86_find_base_term (rtx x)
5301 if (GET_CODE (x) != CONST)
5304 if (GET_CODE (term) == PLUS
5305 && (GET_CODE (XEXP (term, 1)) == CONST_INT
5306 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
5307 term = XEXP (term, 0);
5308 if (GET_CODE (term) != UNSPEC
5309 || XINT (term, 1) != UNSPEC_GOTPCREL)
5312 term = XVECEXP (term, 0, 0);
5314 if (GET_CODE (term) != SYMBOL_REF
5315 && GET_CODE (term) != LABEL_REF)
5321 term = ix86_delegitimize_address (x);
5323 if (GET_CODE (term) != SYMBOL_REF
5324 && GET_CODE (term) != LABEL_REF)
5330 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
5331 this is used for to form addresses to local data when -fPIC is in
5335 darwin_local_data_pic (rtx disp)
5337 if (GET_CODE (disp) == MINUS)
5339 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
5340 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
5341 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
5343 const char *sym_name = XSTR (XEXP (disp, 1), 0);
5344 if (! strcmp (sym_name, "<pic base>"))
5352 /* Determine if a given RTX is a valid constant. We already know this
5353 satisfies CONSTANT_P. */
5356 legitimate_constant_p (rtx x)
5358 switch (GET_CODE (x))
5363 if (GET_CODE (x) == PLUS)
5365 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5370 if (TARGET_MACHO && darwin_local_data_pic (x))
5373 /* Only some unspecs are valid as "constants". */
5374 if (GET_CODE (x) == UNSPEC)
5375 switch (XINT (x, 1))
5378 return TARGET_64BIT;
5381 return local_exec_symbolic_operand (XVECEXP (x, 0, 0), Pmode);
5383 return local_dynamic_symbolic_operand (XVECEXP (x, 0, 0), Pmode);
5388 /* We must have drilled down to a symbol. */
5389 if (!symbolic_operand (x, Pmode))
5394 /* TLS symbols are never valid. */
5395 if (tls_symbolic_operand (x, Pmode))
5403 /* Otherwise we handle everything else in the move patterns. */
5407 /* Determine if it's legal to put X into the constant pool. This
5408 is not possible for the address of thread-local symbols, which
5409 is checked above. */
5412 ix86_cannot_force_const_mem (rtx x)
5414 return !legitimate_constant_p (x);
5417 /* Determine if a given RTX is a valid constant address. */
5420 constant_address_p (rtx x)
5422 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
5425 /* Nonzero if the constant value X is a legitimate general operand
5426 when generating PIC code. It is given that flag_pic is on and
5427 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
5430 legitimate_pic_operand_p (rtx x)
5434 switch (GET_CODE (x))
5437 inner = XEXP (x, 0);
5438 if (GET_CODE (inner) == PLUS
5439 && GET_CODE (XEXP (inner, 1)) == CONST_INT)
5440 inner = XEXP (inner, 0);
5442 /* Only some unspecs are valid as "constants". */
5443 if (GET_CODE (inner) == UNSPEC)
5444 switch (XINT (inner, 1))
5447 return TARGET_64BIT;
5449 return local_exec_symbolic_operand (XVECEXP (inner, 0, 0), Pmode);
5457 return legitimate_pic_address_disp_p (x);
5464 /* Determine if a given CONST RTX is a valid memory displacement
5468 legitimate_pic_address_disp_p (rtx disp)
5472 /* In 64bit mode we can allow direct addresses of symbols and labels
5473 when they are not dynamic symbols. */
5476 /* TLS references should always be enclosed in UNSPEC. */
5477 if (tls_symbolic_operand (disp, GET_MODE (disp)))
5479 if (GET_CODE (disp) == SYMBOL_REF
5480 && !SYMBOL_REF_FAR_ADDR_P (disp)
5481 && SYMBOL_REF_LOCAL_P (disp))
5483 if (GET_CODE (disp) == LABEL_REF)
5485 if (GET_CODE (disp) == CONST
5486 && GET_CODE (XEXP (disp, 0)) == PLUS)
5488 rtx op0 = XEXP (XEXP (disp, 0), 0);
5489 rtx op1 = XEXP (XEXP (disp, 0), 1);
5491 /* TLS references should always be enclosed in UNSPEC. */
5492 if (tls_symbolic_operand (op0, GET_MODE (op0)))
5494 if (((GET_CODE (op0) == SYMBOL_REF
5495 && !SYMBOL_REF_FAR_ADDR_P (op0)
5496 && SYMBOL_REF_LOCAL_P (op0))
5497 || GET_CODE (op0) == LABEL_REF)
5498 && GET_CODE (op1) == CONST_INT
5499 && INTVAL (op1) < 16*1024*1024
5500 && INTVAL (op1) >= -16*1024*1024)
5504 if (GET_CODE (disp) != CONST)
5506 disp = XEXP (disp, 0);
5510 /* We are unsafe to allow PLUS expressions. This limit allowed distance
5511 of GOT tables. We should not need these anyway. */
5512 if (GET_CODE (disp) != UNSPEC
5513 || (XINT (disp, 1) != UNSPEC_GOTPCREL
5514 && XINT (disp, 1) != UNSPEC_GOTOFF))
5517 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
5518 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
5524 if (GET_CODE (disp) == PLUS)
5526 if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
5528 disp = XEXP (disp, 0);
5532 if (TARGET_MACHO && darwin_local_data_pic (disp))
5535 if (GET_CODE (disp) != UNSPEC)
5538 switch (XINT (disp, 1))
5543 return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
5545 if (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
5546 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
5547 return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5549 case UNSPEC_GOTTPOFF:
5550 case UNSPEC_GOTNTPOFF:
5551 case UNSPEC_INDNTPOFF:
5554 return initial_exec_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5556 return local_exec_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5558 return local_dynamic_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
5564 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
5565 memory address for an instruction. The MODE argument is the machine mode
5566 for the MEM expression that wants to use this address.
5568 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
5569 convert common non-canonical forms to canonical form so that they will
5573 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
5575 struct ix86_address parts;
5576 rtx base, index, disp;
5577 HOST_WIDE_INT scale;
5578 const char *reason = NULL;
5579 rtx reason_rtx = NULL_RTX;
5581 if (TARGET_DEBUG_ADDR)
5584 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
5585 GET_MODE_NAME (mode), strict);
5589 if (ix86_decompose_address (addr, &parts) <= 0)
5591 reason = "decomposition failed";
5596 index = parts.index;
5598 scale = parts.scale;
5600 /* Validate base register.
5602 Don't allow SUBREG's that span more than a word here. It can lead to spill
5603 failures when the base is one word out of a two word structure, which is
5604 represented internally as a DImode int. */
5613 else if (GET_CODE (base) == SUBREG
5614 && REG_P (SUBREG_REG (base))
5615 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
5617 reg = SUBREG_REG (base);
5620 reason = "base is not a register";
5624 if (GET_MODE (base) != Pmode)
5626 reason = "base is not in Pmode";
5630 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
5631 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
5633 reason = "base is not valid";
5638 /* Validate index register.
5640 Don't allow SUBREG's that span more than a word here -- same as above. */
5649 else if (GET_CODE (index) == SUBREG
5650 && REG_P (SUBREG_REG (index))
5651 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
5653 reg = SUBREG_REG (index);
5656 reason = "index is not a register";
5660 if (GET_MODE (index) != Pmode)
5662 reason = "index is not in Pmode";
5666 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
5667 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
5669 reason = "index is not valid";
5674 /* Validate scale factor. */
5677 reason_rtx = GEN_INT (scale);
5680 reason = "scale without index";
5684 if (scale != 2 && scale != 4 && scale != 8)
5686 reason = "scale is not a valid multiplier";
5691 /* Validate displacement. */
5696 if (GET_CODE (disp) == CONST
5697 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
5698 switch (XINT (XEXP (disp, 0), 1))
5702 case UNSPEC_GOTPCREL:
5703 gcc_assert (flag_pic);
5704 goto is_legitimate_pic;
5706 case UNSPEC_GOTTPOFF:
5707 case UNSPEC_GOTNTPOFF:
5708 case UNSPEC_INDNTPOFF:
5714 reason = "invalid address unspec";
5718 else if (flag_pic && (SYMBOLIC_CONST (disp)
5720 && !machopic_operand_p (disp)
5725 if (TARGET_64BIT && (index || base))
5727 /* foo@dtpoff(%rX) is ok. */
5728 if (GET_CODE (disp) != CONST
5729 || GET_CODE (XEXP (disp, 0)) != PLUS
5730 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
5731 || GET_CODE (XEXP (XEXP (disp, 0), 1)) != CONST_INT
5732 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
5733 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
5735 reason = "non-constant pic memory reference";
5739 else if (! legitimate_pic_address_disp_p (disp))
5741 reason = "displacement is an invalid pic construct";
5745 /* This code used to verify that a symbolic pic displacement
5746 includes the pic_offset_table_rtx register.
5748 While this is good idea, unfortunately these constructs may
5749 be created by "adds using lea" optimization for incorrect
5758 This code is nonsensical, but results in addressing
5759 GOT table with pic_offset_table_rtx base. We can't
5760 just refuse it easily, since it gets matched by
5761 "addsi3" pattern, that later gets split to lea in the
5762 case output register differs from input. While this
5763 can be handled by separate addsi pattern for this case
5764 that never results in lea, this seems to be easier and
5765 correct fix for crash to disable this test. */
5767 else if (GET_CODE (disp) != LABEL_REF
5768 && GET_CODE (disp) != CONST_INT
5769 && (GET_CODE (disp) != CONST
5770 || !legitimate_constant_p (disp))
5771 && (GET_CODE (disp) != SYMBOL_REF
5772 || !legitimate_constant_p (disp)))
5774 reason = "displacement is not constant";
5777 else if (TARGET_64BIT
5778 && !x86_64_immediate_operand (disp, VOIDmode))
5780 reason = "displacement is out of range";
5785 /* Everything looks valid. */
5786 if (TARGET_DEBUG_ADDR)
5787 fprintf (stderr, "Success.\n");
5791 if (TARGET_DEBUG_ADDR)
5793 fprintf (stderr, "Error: %s\n", reason);
5794 debug_rtx (reason_rtx);
5799 /* Return a unique alias set for the GOT. */
5801 static HOST_WIDE_INT
5802 ix86_GOT_alias_set (void)
5804 static HOST_WIDE_INT set = -1;
5806 set = new_alias_set ();
5810 /* Return a legitimate reference for ORIG (an address) using the
5811 register REG. If REG is 0, a new pseudo is generated.
5813 There are two types of references that must be handled:
5815 1. Global data references must load the address from the GOT, via
5816 the PIC reg. An insn is emitted to do this load, and the reg is
5819 2. Static data references, constant pool addresses, and code labels
5820 compute the address as an offset from the GOT, whose base is in
5821 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
5822 differentiate them from global data objects. The returned
5823 address is the PIC reg + an unspec constant.
5825 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
5826 reg also appears in the address. */
5829 legitimize_pic_address (rtx orig, rtx reg)
5837 reg = gen_reg_rtx (Pmode);
5838 /* Use the generic Mach-O PIC machinery. */
5839 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
5842 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
5844 else if (TARGET_64BIT
5845 && ix86_cmodel != CM_SMALL_PIC
5846 && local_symbolic_operand (addr, Pmode))
5849 /* This symbol may be referenced via a displacement from the PIC
5850 base address (@GOTOFF). */
5852 if (reload_in_progress)
5853 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5854 if (GET_CODE (addr) == CONST)
5855 addr = XEXP (addr, 0);
5856 if (GET_CODE (addr) == PLUS)
5858 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
5859 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
5862 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
5863 new = gen_rtx_CONST (Pmode, new);
5865 tmpreg = gen_reg_rtx (Pmode);
5868 emit_move_insn (tmpreg, new);
5872 new = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
5873 tmpreg, 1, OPTAB_DIRECT);
5876 else new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
5878 else if (!TARGET_64BIT && local_symbolic_operand (addr, Pmode))
5880 /* This symbol may be referenced via a displacement from the PIC
5881 base address (@GOTOFF). */
5883 if (reload_in_progress)
5884 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5885 if (GET_CODE (addr) == CONST)
5886 addr = XEXP (addr, 0);
5887 if (GET_CODE (addr) == PLUS)
5889 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
5890 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
5893 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
5894 new = gen_rtx_CONST (Pmode, new);
5895 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
5899 emit_move_insn (reg, new);
5903 else if (GET_CODE (addr) == SYMBOL_REF)
5907 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
5908 new = gen_rtx_CONST (Pmode, new);
5909 new = gen_const_mem (Pmode, new);
5910 set_mem_alias_set (new, ix86_GOT_alias_set ());
5913 reg = gen_reg_rtx (Pmode);
5914 /* Use directly gen_movsi, otherwise the address is loaded
5915 into register for CSE. We don't want to CSE this addresses,
5916 instead we CSE addresses from the GOT table, so skip this. */
5917 emit_insn (gen_movsi (reg, new));
5922 /* This symbol must be referenced via a load from the
5923 Global Offset Table (@GOT). */
5925 if (reload_in_progress)
5926 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5927 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
5928 new = gen_rtx_CONST (Pmode, new);
5929 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
5930 new = gen_const_mem (Pmode, new);
5931 set_mem_alias_set (new, ix86_GOT_alias_set ());
5934 reg = gen_reg_rtx (Pmode);
5935 emit_move_insn (reg, new);
5941 if (GET_CODE (addr) == CONST)
5943 addr = XEXP (addr, 0);
5945 /* We must match stuff we generate before. Assume the only
5946 unspecs that can get here are ours. Not that we could do
5947 anything with them anyway.... */
5948 if (GET_CODE (addr) == UNSPEC
5949 || (GET_CODE (addr) == PLUS
5950 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
5952 gcc_assert (GET_CODE (addr) == PLUS);
5954 if (GET_CODE (addr) == PLUS)
5956 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
5958 /* Check first to see if this is a constant offset from a @GOTOFF
5959 symbol reference. */
5960 if (local_symbolic_operand (op0, Pmode)
5961 && GET_CODE (op1) == CONST_INT)
5965 if (reload_in_progress)
5966 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
5967 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
5969 new = gen_rtx_PLUS (Pmode, new, op1);
5970 new = gen_rtx_CONST (Pmode, new);
5971 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
5975 emit_move_insn (reg, new);
5981 if (INTVAL (op1) < -16*1024*1024
5982 || INTVAL (op1) >= 16*1024*1024)
5983 new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
5988 base = legitimize_pic_address (XEXP (addr, 0), reg);
5989 new = legitimize_pic_address (XEXP (addr, 1),
5990 base == reg ? NULL_RTX : reg);
5992 if (GET_CODE (new) == CONST_INT)
5993 new = plus_constant (base, INTVAL (new));
5996 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
5998 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
5999 new = XEXP (new, 1);
6001 new = gen_rtx_PLUS (Pmode, base, new);
6009 /* Load the thread pointer. If TO_REG is true, force it into a register. */
6012 get_thread_pointer (int to_reg)
6016 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
6020 reg = gen_reg_rtx (Pmode);
6021 insn = gen_rtx_SET (VOIDmode, reg, tp);
6022 insn = emit_insn (insn);
6027 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
6028 false if we expect this to be used for a memory address and true if
6029 we expect to load the address into a register. */
6032 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
6034 rtx dest, base, off, pic;
6039 case TLS_MODEL_GLOBAL_DYNAMIC:
6040 dest = gen_reg_rtx (Pmode);
6043 rtx rax = gen_rtx_REG (Pmode, 0), insns;
6046 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
6047 insns = get_insns ();
6050 emit_libcall_block (insns, dest, rax, x);
6053 emit_insn (gen_tls_global_dynamic_32 (dest, x));
6056 case TLS_MODEL_LOCAL_DYNAMIC:
6057 base = gen_reg_rtx (Pmode);
6060 rtx rax = gen_rtx_REG (Pmode, 0), insns, note;
6063 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
6064 insns = get_insns ();
6067 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
6068 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
6069 emit_libcall_block (insns, base, rax, note);
6072 emit_insn (gen_tls_local_dynamic_base_32 (base));
6074 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
6075 off = gen_rtx_CONST (Pmode, off);
6077 return gen_rtx_PLUS (Pmode, base, off);
6079 case TLS_MODEL_INITIAL_EXEC:
6083 type = UNSPEC_GOTNTPOFF;
6087 if (reload_in_progress)
6088 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
6089 pic = pic_offset_table_rtx;
6090 type = TARGET_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
6092 else if (!TARGET_GNU_TLS)
6094 pic = gen_reg_rtx (Pmode);
6095 emit_insn (gen_set_got (pic));
6096 type = UNSPEC_GOTTPOFF;
6101 type = UNSPEC_INDNTPOFF;
6104 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
6105 off = gen_rtx_CONST (Pmode, off);
6107 off = gen_rtx_PLUS (Pmode, pic, off);
6108 off = gen_const_mem (Pmode, off);
6109 set_mem_alias_set (off, ix86_GOT_alias_set ());
6111 if (TARGET_64BIT || TARGET_GNU_TLS)
6113 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6114 off = force_reg (Pmode, off);
6115 return gen_rtx_PLUS (Pmode, base, off);
6119 base = get_thread_pointer (true);
6120 dest = gen_reg_rtx (Pmode);
6121 emit_insn (gen_subsi3 (dest, base, off));
6125 case TLS_MODEL_LOCAL_EXEC:
6126 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
6127 (TARGET_64BIT || TARGET_GNU_TLS)
6128 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
6129 off = gen_rtx_CONST (Pmode, off);
6131 if (TARGET_64BIT || TARGET_GNU_TLS)
6133 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
6134 return gen_rtx_PLUS (Pmode, base, off);
6138 base = get_thread_pointer (true);
6139 dest = gen_reg_rtx (Pmode);
6140 emit_insn (gen_subsi3 (dest, base, off));
6151 /* Try machine-dependent ways of modifying an illegitimate address
6152 to be legitimate. If we find one, return the new, valid address.
6153 This macro is used in only one place: `memory_address' in explow.c.
6155 OLDX is the address as it was before break_out_memory_refs was called.
6156 In some cases it is useful to look at this to decide what needs to be done.
6158 MODE and WIN are passed so that this macro can use
6159 GO_IF_LEGITIMATE_ADDRESS.
6161 It is always safe for this macro to do nothing. It exists to recognize
6162 opportunities to optimize the output.
6164 For the 80386, we handle X+REG by loading X into a register R and
6165 using R+REG. R will go in a general reg and indexing will be used.
6166 However, if REG is a broken-out memory address or multiplication,
6167 nothing needs to be done because REG can certainly go in a general reg.
6169 When -fpic is used, special handling is needed for symbolic references.
6170 See comments by legitimize_pic_address in i386.c for details. */
6173 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
6178 if (TARGET_DEBUG_ADDR)
6180 fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
6181 GET_MODE_NAME (mode));
6185 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
6187 return legitimize_tls_address (x, log, false);
6188 if (GET_CODE (x) == CONST
6189 && GET_CODE (XEXP (x, 0)) == PLUS
6190 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
6191 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
6193 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
6194 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
6197 if (flag_pic && SYMBOLIC_CONST (x))
6198 return legitimize_pic_address (x, 0);
6200 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
6201 if (GET_CODE (x) == ASHIFT
6202 && GET_CODE (XEXP (x, 1)) == CONST_INT
6203 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
6206 log = INTVAL (XEXP (x, 1));
6207 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
6208 GEN_INT (1 << log));
6211 if (GET_CODE (x) == PLUS)
6213 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
6215 if (GET_CODE (XEXP (x, 0)) == ASHIFT
6216 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6217 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
6220 log = INTVAL (XEXP (XEXP (x, 0), 1));
6221 XEXP (x, 0) = gen_rtx_MULT (Pmode,
6222 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
6223 GEN_INT (1 << log));
6226 if (GET_CODE (XEXP (x, 1)) == ASHIFT
6227 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
6228 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
6231 log = INTVAL (XEXP (XEXP (x, 1), 1));
6232 XEXP (x, 1) = gen_rtx_MULT (Pmode,
6233 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
6234 GEN_INT (1 << log));
6237 /* Put multiply first if it isn't already. */
6238 if (GET_CODE (XEXP (x, 1)) == MULT)
6240 rtx tmp = XEXP (x, 0);
6241 XEXP (x, 0) = XEXP (x, 1);
6246 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
6247 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
6248 created by virtual register instantiation, register elimination, and
6249 similar optimizations. */
6250 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
6253 x = gen_rtx_PLUS (Pmode,
6254 gen_rtx_PLUS (Pmode, XEXP (x, 0),
6255 XEXP (XEXP (x, 1), 0)),
6256 XEXP (XEXP (x, 1), 1));
6260 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
6261 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
6262 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
6263 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
6264 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
6265 && CONSTANT_P (XEXP (x, 1)))
6268 rtx other = NULL_RTX;
6270 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6272 constant = XEXP (x, 1);
6273 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
6275 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
6277 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
6278 other = XEXP (x, 1);
6286 x = gen_rtx_PLUS (Pmode,
6287 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
6288 XEXP (XEXP (XEXP (x, 0), 1), 0)),
6289 plus_constant (other, INTVAL (constant)));
6293 if (changed && legitimate_address_p (mode, x, FALSE))
6296 if (GET_CODE (XEXP (x, 0)) == MULT)
6299 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
6302 if (GET_CODE (XEXP (x, 1)) == MULT)
6305 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
6309 && GET_CODE (XEXP (x, 1)) == REG
6310 && GET_CODE (XEXP (x, 0)) == REG)
6313 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
6316 x = legitimize_pic_address (x, 0);
6319 if (changed && legitimate_address_p (mode, x, FALSE))
6322 if (GET_CODE (XEXP (x, 0)) == REG)
6324 rtx temp = gen_reg_rtx (Pmode);
6325 rtx val = force_operand (XEXP (x, 1), temp);
6327 emit_move_insn (temp, val);
6333 else if (GET_CODE (XEXP (x, 1)) == REG)
6335 rtx temp = gen_reg_rtx (Pmode);
6336 rtx val = force_operand (XEXP (x, 0), temp);
6338 emit_move_insn (temp, val);
6348 /* Print an integer constant expression in assembler syntax. Addition
6349 and subtraction are the only arithmetic that may appear in these
6350 expressions. FILE is the stdio stream to write to, X is the rtx, and
6351 CODE is the operand print code from the output string. */
6354 output_pic_addr_const (FILE *file, rtx x, int code)
6358 switch (GET_CODE (x))
6361 gcc_assert (flag_pic);
6366 assemble_name (file, XSTR (x, 0));
6367 if (!TARGET_MACHO && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
6368 fputs ("@PLT", file);
6375 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
6376 assemble_name (asm_out_file, buf);
6380 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
6384 /* This used to output parentheses around the expression,
6385 but that does not work on the 386 (either ATT or BSD assembler). */
6386 output_pic_addr_const (file, XEXP (x, 0), code);
6390 if (GET_MODE (x) == VOIDmode)
6392 /* We can use %d if the number is <32 bits and positive. */
6393 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
6394 fprintf (file, "0x%lx%08lx",
6395 (unsigned long) CONST_DOUBLE_HIGH (x),
6396 (unsigned long) CONST_DOUBLE_LOW (x));
6398 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
6401 /* We can't handle floating point constants;
6402 PRINT_OPERAND must handle them. */
6403 output_operand_lossage ("floating constant misused");
6407 /* Some assemblers need integer constants to appear first. */
6408 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6410 output_pic_addr_const (file, XEXP (x, 0), code);
6412 output_pic_addr_const (file, XEXP (x, 1), code);
6416 gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT);
6417 output_pic_addr_const (file, XEXP (x, 1), code);
6419 output_pic_addr_const (file, XEXP (x, 0), code);
6425 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
6426 output_pic_addr_const (file, XEXP (x, 0), code);
6428 output_pic_addr_const (file, XEXP (x, 1), code);
6430 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
6434 gcc_assert (XVECLEN (x, 0) == 1);
6435 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
6436 switch (XINT (x, 1))
6439 fputs ("@GOT", file);
6442 fputs ("@GOTOFF", file);
6444 case UNSPEC_GOTPCREL:
6445 fputs ("@GOTPCREL(%rip)", file);
6447 case UNSPEC_GOTTPOFF:
6448 /* FIXME: This might be @TPOFF in Sun ld too. */
6449 fputs ("@GOTTPOFF", file);
6452 fputs ("@TPOFF", file);
6456 fputs ("@TPOFF", file);
6458 fputs ("@NTPOFF", file);
6461 fputs ("@DTPOFF", file);
6463 case UNSPEC_GOTNTPOFF:
6465 fputs ("@GOTTPOFF(%rip)", file);
6467 fputs ("@GOTNTPOFF", file);
6469 case UNSPEC_INDNTPOFF:
6470 fputs ("@INDNTPOFF", file);
6473 output_operand_lossage ("invalid UNSPEC as operand");
6479 output_operand_lossage ("invalid expression as operand");
6483 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6484 We need to emit DTP-relative relocations. */
6487 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
6489 fputs (ASM_LONG, file);
6490 output_addr_const (file, x);
6491 fputs ("@DTPOFF", file);
6497 fputs (", 0", file);
6504 /* In the name of slightly smaller debug output, and to cater to
6505 general assembler lossage, recognize PIC+GOTOFF and turn it back
6506 into a direct symbol reference. */
6509 ix86_delegitimize_address (rtx orig_x)
6513 if (GET_CODE (x) == MEM)
6518 if (GET_CODE (x) != CONST
6519 || GET_CODE (XEXP (x, 0)) != UNSPEC
6520 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
6521 || GET_CODE (orig_x) != MEM)
6523 return XVECEXP (XEXP (x, 0), 0, 0);
6526 if (GET_CODE (x) != PLUS
6527 || GET_CODE (XEXP (x, 1)) != CONST)
6530 if (GET_CODE (XEXP (x, 0)) == REG
6531 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
6532 /* %ebx + GOT/GOTOFF */
6534 else if (GET_CODE (XEXP (x, 0)) == PLUS)
6536 /* %ebx + %reg * scale + GOT/GOTOFF */
6538 if (GET_CODE (XEXP (y, 0)) == REG
6539 && REGNO (XEXP (y, 0)) == PIC_OFFSET_TABLE_REGNUM)
6541 else if (GET_CODE (XEXP (y, 1)) == REG
6542 && REGNO (XEXP (y, 1)) == PIC_OFFSET_TABLE_REGNUM)
6546 if (GET_CODE (y) != REG
6547 && GET_CODE (y) != MULT
6548 && GET_CODE (y) != ASHIFT)
6554 x = XEXP (XEXP (x, 1), 0);
6555 if (GET_CODE (x) == UNSPEC
6556 && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
6557 || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
6560 return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0));
6561 return XVECEXP (x, 0, 0);
6564 if (GET_CODE (x) == PLUS
6565 && GET_CODE (XEXP (x, 0)) == UNSPEC
6566 && GET_CODE (XEXP (x, 1)) == CONST_INT
6567 && ((XINT (XEXP (x, 0), 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
6568 || (XINT (XEXP (x, 0), 1) == UNSPEC_GOTOFF
6569 && GET_CODE (orig_x) != MEM)))
6571 x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
6573 return gen_rtx_PLUS (Pmode, y, x);
6581 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
6586 if (mode == CCFPmode || mode == CCFPUmode)
6588 enum rtx_code second_code, bypass_code;
6589 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
6590 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
6591 code = ix86_fp_compare_code_to_integer (code);
6595 code = reverse_condition (code);
6606 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
6610 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
6611 Those same assemblers have the same but opposite lossage on cmov. */
6612 gcc_assert (mode == CCmode);
6613 suffix = fp ? "nbe" : "a";
6633 gcc_assert (mode == CCmode);
6655 gcc_assert (mode == CCmode);
6656 suffix = fp ? "nb" : "ae";
6659 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
6663 gcc_assert (mode == CCmode);
6667 suffix = fp ? "u" : "p";
6670 suffix = fp ? "nu" : "np";
6675 fputs (suffix, file);
6678 /* Print the name of register X to FILE based on its machine mode and number.
6679 If CODE is 'w', pretend the mode is HImode.
6680 If CODE is 'b', pretend the mode is QImode.
6681 If CODE is 'k', pretend the mode is SImode.
6682 If CODE is 'q', pretend the mode is DImode.
6683 If CODE is 'h', pretend the reg is the 'high' byte register.
6684 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
6687 print_reg (rtx x, int code, FILE *file)
6689 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
6690 && REGNO (x) != FRAME_POINTER_REGNUM
6691 && REGNO (x) != FLAGS_REG
6692 && REGNO (x) != FPSR_REG);
6694 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
6697 if (code == 'w' || MMX_REG_P (x))
6699 else if (code == 'b')
6701 else if (code == 'k')
6703 else if (code == 'q')
6705 else if (code == 'y')
6707 else if (code == 'h')
6710 code = GET_MODE_SIZE (GET_MODE (x));
6712 /* Irritatingly, AMD extended registers use different naming convention
6713 from the normal registers. */
6714 if (REX_INT_REG_P (x))
6716 gcc_assert (TARGET_64BIT);
6720 error ("extended registers have no high halves");
6723 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
6726 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
6729 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
6732 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
6735 error ("unsupported operand size for extended register");
6743 if (STACK_TOP_P (x))
6745 fputs ("st(0)", file);
6752 if (! ANY_FP_REG_P (x))
6753 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
6758 fputs (hi_reg_name[REGNO (x)], file);
6761 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
6763 fputs (qi_reg_name[REGNO (x)], file);
6766 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
6768 fputs (qi_high_reg_name[REGNO (x)], file);
6775 /* Locate some local-dynamic symbol still in use by this function
6776 so that we can print its name in some tls_local_dynamic_base
6780 get_some_local_dynamic_name (void)
6784 if (cfun->machine->some_ld_name)
6785 return cfun->machine->some_ld_name;
6787 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
6789 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
6790 return cfun->machine->some_ld_name;
6796 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
6800 if (GET_CODE (x) == SYMBOL_REF
6801 && local_dynamic_symbolic_operand (x, Pmode))
6803 cfun->machine->some_ld_name = XSTR (x, 0);
6811 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
6812 C -- print opcode suffix for set/cmov insn.
6813 c -- like C, but print reversed condition
6814 F,f -- likewise, but for floating-point.
6815 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
6817 R -- print the prefix for register names.
6818 z -- print the opcode suffix for the size of the current operand.
6819 * -- print a star (in certain assembler syntax)
6820 A -- print an absolute memory reference.
6821 w -- print the operand as if it's a "word" (HImode) even if it isn't.
6822 s -- print a shift double count, followed by the assemblers argument
6824 b -- print the QImode name of the register for the indicated operand.
6825 %b0 would print %al if operands[0] is reg 0.
6826 w -- likewise, print the HImode name of the register.
6827 k -- likewise, print the SImode name of the register.
6828 q -- likewise, print the DImode name of the register.
6829 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
6830 y -- print "st(0)" instead of "st" as a register.
6831 D -- print condition for SSE cmp instruction.
6832 P -- if PIC, print an @PLT suffix.
6833 X -- don't print any sort of PIC '@' suffix for a symbol.
6834 & -- print some in-use local-dynamic symbol name.
6835 H -- print a memory address offset by 8; used for sse high-parts
6839 print_operand (FILE *file, rtx x, int code)
6846 if (ASSEMBLER_DIALECT == ASM_ATT)
6851 assemble_name (file, get_some_local_dynamic_name ());
6855 switch (ASSEMBLER_DIALECT)
6862 /* Intel syntax. For absolute addresses, registers should not
6863 be surrounded by braces. */
6864 if (GET_CODE (x) != REG)
6867 PRINT_OPERAND (file, x, 0);
6877 PRINT_OPERAND (file, x, 0);
6882 if (ASSEMBLER_DIALECT == ASM_ATT)
6887 if (ASSEMBLER_DIALECT == ASM_ATT)
6892 if (ASSEMBLER_DIALECT == ASM_ATT)
6897 if (ASSEMBLER_DIALECT == ASM_ATT)
6902 if (ASSEMBLER_DIALECT == ASM_ATT)
6907 if (ASSEMBLER_DIALECT == ASM_ATT)
6912 /* 387 opcodes don't get size suffixes if the operands are
6914 if (STACK_REG_P (x))
6917 /* Likewise if using Intel opcodes. */
6918 if (ASSEMBLER_DIALECT == ASM_INTEL)
6921 /* This is the size of op from size of operand. */
6922 switch (GET_MODE_SIZE (GET_MODE (x)))
6925 #ifdef HAVE_GAS_FILDS_FISTS
6931 if (GET_MODE (x) == SFmode)
6946 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
6948 #ifdef GAS_MNEMONICS
6974 if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
6976 PRINT_OPERAND (file, x, 0);
6982 /* Little bit of braindamage here. The SSE compare instructions
6983 does use completely different names for the comparisons that the
6984 fp conditional moves. */
6985 switch (GET_CODE (x))
7000 fputs ("unord", file);
7004 fputs ("neq", file);
7008 fputs ("nlt", file);
7012 fputs ("nle", file);
7015 fputs ("ord", file);
7022 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7023 if (ASSEMBLER_DIALECT == ASM_ATT)
7025 switch (GET_MODE (x))
7027 case HImode: putc ('w', file); break;
7029 case SFmode: putc ('l', file); break;
7031 case DFmode: putc ('q', file); break;
7032 default: gcc_unreachable ();
7039 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
7042 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7043 if (ASSEMBLER_DIALECT == ASM_ATT)
7046 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
7049 /* Like above, but reverse condition */
7051 /* Check to see if argument to %c is really a constant
7052 and not a condition code which needs to be reversed. */
7053 if (!COMPARISON_P (x))
7055 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
7058 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
7061 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
7062 if (ASSEMBLER_DIALECT == ASM_ATT)
7065 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
7069 /* It doesn't actually matter what mode we use here, as we're
7070 only going to use this for printing. */
7071 x = adjust_address_nv (x, DImode, 8);
7078 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
7081 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
7084 int pred_val = INTVAL (XEXP (x, 0));
7086 if (pred_val < REG_BR_PROB_BASE * 45 / 100
7087 || pred_val > REG_BR_PROB_BASE * 55 / 100)
7089 int taken = pred_val > REG_BR_PROB_BASE / 2;
7090 int cputaken = final_forward_branch_p (current_output_insn) == 0;
7092 /* Emit hints only in the case default branch prediction
7093 heuristics would fail. */
7094 if (taken != cputaken)
7096 /* We use 3e (DS) prefix for taken branches and
7097 2e (CS) prefix for not taken branches. */
7099 fputs ("ds ; ", file);
7101 fputs ("cs ; ", file);
7108 output_operand_lossage ("invalid operand code '%c'", code);
7112 if (GET_CODE (x) == REG)
7113 print_reg (x, code, file);
7115 else if (GET_CODE (x) == MEM)
7117 /* No `byte ptr' prefix for call instructions. */
7118 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
7121 switch (GET_MODE_SIZE (GET_MODE (x)))
7123 case 1: size = "BYTE"; break;
7124 case 2: size = "WORD"; break;
7125 case 4: size = "DWORD"; break;
7126 case 8: size = "QWORD"; break;
7127 case 12: size = "XWORD"; break;
7128 case 16: size = "XMMWORD"; break;
7133 /* Check for explicit size override (codes 'b', 'w' and 'k') */
7136 else if (code == 'w')
7138 else if (code == 'k')
7142 fputs (" PTR ", file);
7146 /* Avoid (%rip) for call operands. */
7147 if (CONSTANT_ADDRESS_P (x) && code == 'P'
7148 && GET_CODE (x) != CONST_INT)
7149 output_addr_const (file, x);
7150 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
7151 output_operand_lossage ("invalid constraints for operand");
7156 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
7161 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7162 REAL_VALUE_TO_TARGET_SINGLE (r, l);
7164 if (ASSEMBLER_DIALECT == ASM_ATT)
7166 fprintf (file, "0x%08lx", l);
7169 /* These float cases don't actually occur as immediate operands. */
7170 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
7174 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7175 fprintf (file, "%s", dstr);
7178 else if (GET_CODE (x) == CONST_DOUBLE
7179 && GET_MODE (x) == XFmode)
7183 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
7184 fprintf (file, "%s", dstr);
7189 /* We have patterns that allow zero sets of memory, for instance.
7190 In 64-bit mode, we should probably support all 8-byte vectors,
7191 since we can in fact encode that into an immediate. */
7192 if (GET_CODE (x) == CONST_VECTOR)
7194 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
7200 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
7202 if (ASSEMBLER_DIALECT == ASM_ATT)
7205 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
7206 || GET_CODE (x) == LABEL_REF)
7208 if (ASSEMBLER_DIALECT == ASM_ATT)
7211 fputs ("OFFSET FLAT:", file);
7214 if (GET_CODE (x) == CONST_INT)
7215 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7217 output_pic_addr_const (file, x, code);
7219 output_addr_const (file, x);
7223 /* Print a memory operand whose address is ADDR. */
7226 print_operand_address (FILE *file, rtx addr)
7228 struct ix86_address parts;
7229 rtx base, index, disp;
7231 int ok = ix86_decompose_address (addr, &parts);
7236 index = parts.index;
7238 scale = parts.scale;
7246 if (USER_LABEL_PREFIX[0] == 0)
7248 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
7254 if (!base && !index)
7256 /* Displacement only requires special attention. */
7258 if (GET_CODE (disp) == CONST_INT)
7260 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
7262 if (USER_LABEL_PREFIX[0] == 0)
7264 fputs ("ds:", file);
7266 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
7269 output_pic_addr_const (file, disp, 0);
7271 output_addr_const (file, disp);
7273 /* Use one byte shorter RIP relative addressing for 64bit mode. */
7275 && ((GET_CODE (disp) == SYMBOL_REF
7276 && ! tls_symbolic_operand (disp, GET_MODE (disp)))
7277 || GET_CODE (disp) == LABEL_REF
7278 || (GET_CODE (disp) == CONST
7279 && GET_CODE (XEXP (disp, 0)) == PLUS
7280 && (GET_CODE (XEXP (XEXP (disp, 0), 0)) == SYMBOL_REF
7281 || GET_CODE (XEXP (XEXP (disp, 0), 0)) == LABEL_REF)
7282 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)))
7283 fputs ("(%rip)", file);
7287 if (ASSEMBLER_DIALECT == ASM_ATT)
7292 output_pic_addr_const (file, disp, 0);
7293 else if (GET_CODE (disp) == LABEL_REF)
7294 output_asm_label (disp);
7296 output_addr_const (file, disp);
7301 print_reg (base, 0, file);
7305 print_reg (index, 0, file);
7307 fprintf (file, ",%d", scale);
7313 rtx offset = NULL_RTX;
7317 /* Pull out the offset of a symbol; print any symbol itself. */
7318 if (GET_CODE (disp) == CONST
7319 && GET_CODE (XEXP (disp, 0)) == PLUS
7320 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
7322 offset = XEXP (XEXP (disp, 0), 1);
7323 disp = gen_rtx_CONST (VOIDmode,
7324 XEXP (XEXP (disp, 0), 0));
7328 output_pic_addr_const (file, disp, 0);
7329 else if (GET_CODE (disp) == LABEL_REF)
7330 output_asm_label (disp);
7331 else if (GET_CODE (disp) == CONST_INT)
7334 output_addr_const (file, disp);
7340 print_reg (base, 0, file);
7343 if (INTVAL (offset) >= 0)
7345 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
7349 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
7356 print_reg (index, 0, file);
7358 fprintf (file, "*%d", scale);
7366 output_addr_const_extra (FILE *file, rtx x)
7370 if (GET_CODE (x) != UNSPEC)
7373 op = XVECEXP (x, 0, 0);
7374 switch (XINT (x, 1))
7376 case UNSPEC_GOTTPOFF:
7377 output_addr_const (file, op);
7378 /* FIXME: This might be @TPOFF in Sun ld. */
7379 fputs ("@GOTTPOFF", file);
7382 output_addr_const (file, op);
7383 fputs ("@TPOFF", file);
7386 output_addr_const (file, op);
7388 fputs ("@TPOFF", file);
7390 fputs ("@NTPOFF", file);
7393 output_addr_const (file, op);
7394 fputs ("@DTPOFF", file);
7396 case UNSPEC_GOTNTPOFF:
7397 output_addr_const (file, op);
7399 fputs ("@GOTTPOFF(%rip)", file);
7401 fputs ("@GOTNTPOFF", file);
7403 case UNSPEC_INDNTPOFF:
7404 output_addr_const (file, op);
7405 fputs ("@INDNTPOFF", file);
7415 /* Split one or more DImode RTL references into pairs of SImode
7416 references. The RTL can be REG, offsettable MEM, integer constant, or
7417 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
7418 split and "num" is its length. lo_half and hi_half are output arrays
7419 that parallel "operands". */
7422 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
7426 rtx op = operands[num];
7428 /* simplify_subreg refuse to split volatile memory addresses,
7429 but we still have to handle it. */
7430 if (GET_CODE (op) == MEM)
7432 lo_half[num] = adjust_address (op, SImode, 0);
7433 hi_half[num] = adjust_address (op, SImode, 4);
7437 lo_half[num] = simplify_gen_subreg (SImode, op,
7438 GET_MODE (op) == VOIDmode
7439 ? DImode : GET_MODE (op), 0);
7440 hi_half[num] = simplify_gen_subreg (SImode, op,
7441 GET_MODE (op) == VOIDmode
7442 ? DImode : GET_MODE (op), 4);
7446 /* Split one or more TImode RTL references into pairs of DImode
7447 references. The RTL can be REG, offsettable MEM, integer constant, or
7448 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
7449 split and "num" is its length. lo_half and hi_half are output arrays
7450 that parallel "operands". */
7453 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
7457 rtx op = operands[num];
7459 /* simplify_subreg refuse to split volatile memory addresses, but we
7460 still have to handle it. */
7461 if (GET_CODE (op) == MEM)
7463 lo_half[num] = adjust_address (op, DImode, 0);
7464 hi_half[num] = adjust_address (op, DImode, 8);
7468 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
7469 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
7474 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
7475 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
7476 is the expression of the binary operation. The output may either be
7477 emitted here, or returned to the caller, like all output_* functions.
7479 There is no guarantee that the operands are the same mode, as they
7480 might be within FLOAT or FLOAT_EXTEND expressions. */
7482 #ifndef SYSV386_COMPAT
7483 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
7484 wants to fix the assemblers because that causes incompatibility
7485 with gcc. No-one wants to fix gcc because that causes
7486 incompatibility with assemblers... You can use the option of
7487 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
7488 #define SYSV386_COMPAT 1
7492 output_387_binary_op (rtx insn, rtx *operands)
7494 static char buf[30];
7497 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
7499 #ifdef ENABLE_CHECKING
7500 /* Even if we do not want to check the inputs, this documents input
7501 constraints. Which helps in understanding the following code. */
7502 if (STACK_REG_P (operands[0])
7503 && ((REG_P (operands[1])
7504 && REGNO (operands[0]) == REGNO (operands[1])
7505 && (STACK_REG_P (operands[2]) || GET_CODE (operands[2]) == MEM))
7506 || (REG_P (operands[2])
7507 && REGNO (operands[0]) == REGNO (operands[2])
7508 && (STACK_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)))
7509 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
7512 gcc_assert (is_sse);
7515 switch (GET_CODE (operands[3]))
7518 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7519 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7527 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7528 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7536 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7537 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7545 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
7546 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
7560 if (GET_MODE (operands[0]) == SFmode)
7561 strcat (buf, "ss\t{%2, %0|%0, %2}");
7563 strcat (buf, "sd\t{%2, %0|%0, %2}");
7568 switch (GET_CODE (operands[3]))
7572 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
7574 rtx temp = operands[2];
7575 operands[2] = operands[1];
7579 /* know operands[0] == operands[1]. */
7581 if (GET_CODE (operands[2]) == MEM)
7587 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
7589 if (STACK_TOP_P (operands[0]))
7590 /* How is it that we are storing to a dead operand[2]?
7591 Well, presumably operands[1] is dead too. We can't
7592 store the result to st(0) as st(0) gets popped on this
7593 instruction. Instead store to operands[2] (which I
7594 think has to be st(1)). st(1) will be popped later.
7595 gcc <= 2.8.1 didn't have this check and generated
7596 assembly code that the Unixware assembler rejected. */
7597 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7599 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7603 if (STACK_TOP_P (operands[0]))
7604 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7606 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7611 if (GET_CODE (operands[1]) == MEM)
7617 if (GET_CODE (operands[2]) == MEM)
7623 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
7626 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
7627 derived assemblers, confusingly reverse the direction of
7628 the operation for fsub{r} and fdiv{r} when the
7629 destination register is not st(0). The Intel assembler
7630 doesn't have this brain damage. Read !SYSV386_COMPAT to
7631 figure out what the hardware really does. */
7632 if (STACK_TOP_P (operands[0]))
7633 p = "{p\t%0, %2|rp\t%2, %0}";
7635 p = "{rp\t%2, %0|p\t%0, %2}";
7637 if (STACK_TOP_P (operands[0]))
7638 /* As above for fmul/fadd, we can't store to st(0). */
7639 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7641 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7646 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
7649 if (STACK_TOP_P (operands[0]))
7650 p = "{rp\t%0, %1|p\t%1, %0}";
7652 p = "{p\t%1, %0|rp\t%0, %1}";
7654 if (STACK_TOP_P (operands[0]))
7655 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
7657 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
7662 if (STACK_TOP_P (operands[0]))
7664 if (STACK_TOP_P (operands[1]))
7665 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7667 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
7670 else if (STACK_TOP_P (operands[1]))
7673 p = "{\t%1, %0|r\t%0, %1}";
7675 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
7681 p = "{r\t%2, %0|\t%0, %2}";
7683 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7696 /* Return needed mode for entity in optimize_mode_switching pass. */
7699 ix86_mode_needed (int entity, rtx insn)
7701 enum attr_i387_cw mode;
7703 /* The mode UNINITIALIZED is used to store control word after a
7704 function call or ASM pattern. The mode ANY specify that function
7705 has no requirements on the control word and make no changes in the
7706 bits we are interested in. */
7709 || (NONJUMP_INSN_P (insn)
7710 && (asm_noperands (PATTERN (insn)) >= 0
7711 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
7712 return I387_CW_UNINITIALIZED;
7714 if (recog_memoized (insn) < 0)
7717 mode = get_attr_i387_cw (insn);
7722 if (mode == I387_CW_TRUNC)
7727 if (mode == I387_CW_FLOOR)
7732 if (mode == I387_CW_CEIL)
7737 if (mode == I387_CW_MASK_PM)
7748 /* Output code to initialize control word copies used by trunc?f?i and
7749 rounding patterns. CURRENT_MODE is set to current control word,
7750 while NEW_MODE is set to new control word. */
7753 emit_i387_cw_initialization (int mode)
7755 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
7760 rtx reg = gen_reg_rtx (HImode);
7762 emit_insn (gen_x86_fnstcw_1 (stored_mode));
7763 emit_move_insn (reg, stored_mode);
7765 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
7770 /* round toward zero (truncate) */
7771 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
7772 slot = SLOT_CW_TRUNC;
7776 /* round down toward -oo */
7777 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
7778 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
7779 slot = SLOT_CW_FLOOR;
7783 /* round up toward +oo */
7784 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
7785 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
7786 slot = SLOT_CW_CEIL;
7789 case I387_CW_MASK_PM:
7790 /* mask precision exception for nearbyint() */
7791 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
7792 slot = SLOT_CW_MASK_PM;
7804 /* round toward zero (truncate) */
7805 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
7806 slot = SLOT_CW_TRUNC;
7810 /* round down toward -oo */
7811 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
7812 slot = SLOT_CW_FLOOR;
7816 /* round up toward +oo */
7817 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
7818 slot = SLOT_CW_CEIL;
7821 case I387_CW_MASK_PM:
7822 /* mask precision exception for nearbyint() */
7823 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
7824 slot = SLOT_CW_MASK_PM;
7832 gcc_assert (slot < MAX_386_STACK_LOCALS);
7834 new_mode = assign_386_stack_local (HImode, slot);
7835 emit_move_insn (new_mode, reg);
7838 /* Output code for INSN to convert a float to a signed int. OPERANDS
7839 are the insn operands. The output may be [HSD]Imode and the input
7840 operand may be [SDX]Fmode. */
7843 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
7845 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
7846 int dimode_p = GET_MODE (operands[0]) == DImode;
7847 int round_mode = get_attr_i387_cw (insn);
7849 /* Jump through a hoop or two for DImode, since the hardware has no
7850 non-popping instruction. We used to do this a different way, but
7851 that was somewhat fragile and broke with post-reload splitters. */
7852 if ((dimode_p || fisttp) && !stack_top_dies)
7853 output_asm_insn ("fld\t%y1", operands);
7855 gcc_assert (STACK_TOP_P (operands[1]));
7856 gcc_assert (GET_CODE (operands[0]) == MEM);
7859 output_asm_insn ("fisttp%z0\t%0", operands);
7862 if (round_mode != I387_CW_ANY)
7863 output_asm_insn ("fldcw\t%3", operands);
7864 if (stack_top_dies || dimode_p)
7865 output_asm_insn ("fistp%z0\t%0", operands);
7867 output_asm_insn ("fist%z0\t%0", operands);
7868 if (round_mode != I387_CW_ANY)
7869 output_asm_insn ("fldcw\t%2", operands);
7875 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
7876 should be used. UNORDERED_P is true when fucom should be used. */
7879 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
7882 rtx cmp_op0, cmp_op1;
7883 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
7887 cmp_op0 = operands[0];
7888 cmp_op1 = operands[1];
7892 cmp_op0 = operands[1];
7893 cmp_op1 = operands[2];
7898 if (GET_MODE (operands[0]) == SFmode)
7900 return "ucomiss\t{%1, %0|%0, %1}";
7902 return "comiss\t{%1, %0|%0, %1}";
7905 return "ucomisd\t{%1, %0|%0, %1}";
7907 return "comisd\t{%1, %0|%0, %1}";
7910 gcc_assert (STACK_TOP_P (cmp_op0));
7912 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
7914 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
7918 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
7919 return TARGET_USE_FFREEP ? "ffreep\t%y1" : "fstp\t%y1";
7922 return "ftst\n\tfnstsw\t%0";
7925 if (STACK_REG_P (cmp_op1)
7927 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
7928 && REGNO (cmp_op1) != FIRST_STACK_REG)
7930 /* If both the top of the 387 stack dies, and the other operand
7931 is also a stack register that dies, then this must be a
7932 `fcompp' float compare */
7936 /* There is no double popping fcomi variant. Fortunately,
7937 eflags is immune from the fstp's cc clobbering. */
7939 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
7941 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
7942 return TARGET_USE_FFREEP ? "ffreep\t%y0" : "fstp\t%y0";
7947 return "fucompp\n\tfnstsw\t%0";
7949 return "fcompp\n\tfnstsw\t%0";
7954 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
7956 static const char * const alt[16] =
7958 "fcom%z2\t%y2\n\tfnstsw\t%0",
7959 "fcomp%z2\t%y2\n\tfnstsw\t%0",
7960 "fucom%z2\t%y2\n\tfnstsw\t%0",
7961 "fucomp%z2\t%y2\n\tfnstsw\t%0",
7963 "ficom%z2\t%y2\n\tfnstsw\t%0",
7964 "ficomp%z2\t%y2\n\tfnstsw\t%0",
7968 "fcomi\t{%y1, %0|%0, %y1}",
7969 "fcomip\t{%y1, %0|%0, %y1}",
7970 "fucomi\t{%y1, %0|%0, %y1}",
7971 "fucomip\t{%y1, %0|%0, %y1}",
7982 mask = eflags_p << 3;
7983 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
7984 mask |= unordered_p << 1;
7985 mask |= stack_top_dies;
7987 gcc_assert (mask < 16);
7996 ix86_output_addr_vec_elt (FILE *file, int value)
7998 const char *directive = ASM_LONG;
8002 directive = ASM_QUAD;
8004 gcc_assert (!TARGET_64BIT);
8007 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
8011 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
8014 fprintf (file, "%s%s%d-%s%d\n",
8015 ASM_LONG, LPREFIX, value, LPREFIX, rel);
8016 else if (HAVE_AS_GOTOFF_IN_DATA)
8017 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
8019 else if (TARGET_MACHO)
8021 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
8022 machopic_output_function_base_name (file);
8023 fprintf(file, "\n");
8027 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
8028 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
8031 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
8035 ix86_expand_clear (rtx dest)
8039 /* We play register width games, which are only valid after reload. */
8040 gcc_assert (reload_completed);
8042 /* Avoid HImode and its attendant prefix byte. */
8043 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
8044 dest = gen_rtx_REG (SImode, REGNO (dest));
8046 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
8048 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
8049 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
8051 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, 17));
8052 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
8058 /* X is an unchanging MEM. If it is a constant pool reference, return
8059 the constant pool rtx, else NULL. */
8062 maybe_get_pool_constant (rtx x)
8064 x = ix86_delegitimize_address (XEXP (x, 0));
8066 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
8067 return get_pool_constant (x);
8073 ix86_expand_move (enum machine_mode mode, rtx operands[])
8075 int strict = (reload_in_progress || reload_completed);
8077 enum tls_model model;
8082 if (GET_CODE (op1) == SYMBOL_REF)
8084 model = SYMBOL_REF_TLS_MODEL (op1);
8087 op1 = legitimize_tls_address (op1, model, true);
8088 op1 = force_operand (op1, op0);
8093 else if (GET_CODE (op1) == CONST
8094 && GET_CODE (XEXP (op1, 0)) == PLUS
8095 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
8097 model = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (op1, 0), 0));
8100 rtx addend = XEXP (XEXP (op1, 0), 1);
8101 op1 = legitimize_tls_address (XEXP (XEXP (op1, 0), 0), model, true);
8102 op1 = force_operand (op1, NULL);
8103 op1 = expand_simple_binop (Pmode, PLUS, op1, addend,
8104 op0, 1, OPTAB_DIRECT);
8110 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
8115 rtx temp = ((reload_in_progress
8116 || ((op0 && GET_CODE (op0) == REG)
8118 ? op0 : gen_reg_rtx (Pmode));
8119 op1 = machopic_indirect_data_reference (op1, temp);
8120 op1 = machopic_legitimize_pic_address (op1, mode,
8121 temp == op1 ? 0 : temp);
8123 else if (MACHOPIC_INDIRECT)
8124 op1 = machopic_indirect_data_reference (op1, 0);
8128 if (GET_CODE (op0) == MEM)
8129 op1 = force_reg (Pmode, op1);
8131 op1 = legitimize_address (op1, op1, Pmode);
8132 #endif /* TARGET_MACHO */
8136 if (GET_CODE (op0) == MEM
8137 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
8138 || !push_operand (op0, mode))
8139 && GET_CODE (op1) == MEM)
8140 op1 = force_reg (mode, op1);
8142 if (push_operand (op0, mode)
8143 && ! general_no_elim_operand (op1, mode))
8144 op1 = copy_to_mode_reg (mode, op1);
8146 /* Force large constants in 64bit compilation into register
8147 to get them CSEed. */
8148 if (TARGET_64BIT && mode == DImode
8149 && immediate_operand (op1, mode)
8150 && !x86_64_zext_immediate_operand (op1, VOIDmode)
8151 && !register_operand (op0, mode)
8152 && optimize && !reload_completed && !reload_in_progress)
8153 op1 = copy_to_mode_reg (mode, op1);
8155 if (FLOAT_MODE_P (mode))
8157 /* If we are loading a floating point constant to a register,
8158 force the value to memory now, since we'll get better code
8159 out the back end. */
8163 else if (GET_CODE (op1) == CONST_DOUBLE)
8165 op1 = validize_mem (force_const_mem (mode, op1));
8166 if (!register_operand (op0, mode))
8168 rtx temp = gen_reg_rtx (mode);
8169 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
8170 emit_move_insn (op0, temp);
8177 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8181 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
8183 rtx op0 = operands[0], op1 = operands[1];
8185 /* Force constants other than zero into memory. We do not know how
8186 the instructions used to build constants modify the upper 64 bits
8187 of the register, once we have that information we may be able
8188 to handle some of them more efficiently. */
8189 if ((reload_in_progress | reload_completed) == 0
8190 && register_operand (op0, mode)
8191 && CONSTANT_P (op1) && op1 != CONST0_RTX (mode))
8192 op1 = validize_mem (force_const_mem (mode, op1));
8194 /* Make operand1 a register if it isn't already. */
8196 && !register_operand (op0, mode)
8197 && !register_operand (op1, mode))
8199 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
8203 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
8206 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
8207 straight to ix86_expand_vector_move. */
8210 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
8219 /* If we're optimizing for size, movups is the smallest. */
8222 op0 = gen_lowpart (V4SFmode, op0);
8223 op1 = gen_lowpart (V4SFmode, op1);
8224 emit_insn (gen_sse_movups (op0, op1));
8228 /* ??? If we have typed data, then it would appear that using
8229 movdqu is the only way to get unaligned data loaded with
8231 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8233 op0 = gen_lowpart (V16QImode, op0);
8234 op1 = gen_lowpart (V16QImode, op1);
8235 emit_insn (gen_sse2_movdqu (op0, op1));
8239 if (TARGET_SSE2 && mode == V2DFmode)
8243 /* When SSE registers are split into halves, we can avoid
8244 writing to the top half twice. */
8245 if (TARGET_SSE_SPLIT_REGS)
8247 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8252 /* ??? Not sure about the best option for the Intel chips.
8253 The following would seem to satisfy; the register is
8254 entirely cleared, breaking the dependency chain. We
8255 then store to the upper half, with a dependency depth
8256 of one. A rumor has it that Intel recommends two movsd
8257 followed by an unpacklpd, but this is unconfirmed. And
8258 given that the dependency depth of the unpacklpd would
8259 still be one, I'm not sure why this would be better. */
8260 zero = CONST0_RTX (V2DFmode);
8263 m = adjust_address (op1, DFmode, 0);
8264 emit_insn (gen_sse2_loadlpd (op0, zero, m));
8265 m = adjust_address (op1, DFmode, 8);
8266 emit_insn (gen_sse2_loadhpd (op0, op0, m));
8270 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
8271 emit_move_insn (op0, CONST0_RTX (mode));
8273 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
8275 if (mode != V4SFmode)
8276 op0 = gen_lowpart (V4SFmode, op0);
8277 m = adjust_address (op1, V2SFmode, 0);
8278 emit_insn (gen_sse_loadlps (op0, op0, m));
8279 m = adjust_address (op1, V2SFmode, 8);
8280 emit_insn (gen_sse_loadhps (op0, op0, m));
8283 else if (MEM_P (op0))
8285 /* If we're optimizing for size, movups is the smallest. */
8288 op0 = gen_lowpart (V4SFmode, op0);
8289 op1 = gen_lowpart (V4SFmode, op1);
8290 emit_insn (gen_sse_movups (op0, op1));
8294 /* ??? Similar to above, only less clear because of quote
8295 typeless stores unquote. */
8296 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
8297 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
8299 op0 = gen_lowpart (V16QImode, op0);
8300 op1 = gen_lowpart (V16QImode, op1);
8301 emit_insn (gen_sse2_movdqu (op0, op1));
8305 if (TARGET_SSE2 && mode == V2DFmode)
8307 m = adjust_address (op0, DFmode, 0);
8308 emit_insn (gen_sse2_storelpd (m, op1));
8309 m = adjust_address (op0, DFmode, 8);
8310 emit_insn (gen_sse2_storehpd (m, op1));
8314 if (mode != V4SFmode)
8315 op1 = gen_lowpart (V4SFmode, op1);
8316 m = adjust_address (op0, V2SFmode, 0);
8317 emit_insn (gen_sse_storelps (m, op1));
8318 m = adjust_address (op0, V2SFmode, 8);
8319 emit_insn (gen_sse_storehps (m, op1));
8326 /* Expand a push in MODE. This is some mode for which we do not support
8327 proper push instructions, at least from the registers that we expect
8328 the value to live in. */
8331 ix86_expand_push (enum machine_mode mode, rtx x)
8335 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
8336 GEN_INT (-GET_MODE_SIZE (mode)),
8337 stack_pointer_rtx, 1, OPTAB_DIRECT);
8338 if (tmp != stack_pointer_rtx)
8339 emit_move_insn (stack_pointer_rtx, tmp);
8341 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
8342 emit_move_insn (tmp, x);
8345 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
8346 destination to use for the operation. If different from the true
8347 destination in operands[0], a copy operation will be required. */
8350 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
8353 int matching_memory;
8354 rtx src1, src2, dst;
8360 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
8361 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8362 && (rtx_equal_p (dst, src2)
8363 || immediate_operand (src1, mode)))
8370 /* If the destination is memory, and we do not have matching source
8371 operands, do things in registers. */
8372 matching_memory = 0;
8373 if (GET_CODE (dst) == MEM)
8375 if (rtx_equal_p (dst, src1))
8376 matching_memory = 1;
8377 else if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8378 && rtx_equal_p (dst, src2))
8379 matching_memory = 2;
8381 dst = gen_reg_rtx (mode);
8384 /* Both source operands cannot be in memory. */
8385 if (GET_CODE (src1) == MEM && GET_CODE (src2) == MEM)
8387 if (matching_memory != 2)
8388 src2 = force_reg (mode, src2);
8390 src1 = force_reg (mode, src1);
8393 /* If the operation is not commutable, source 1 cannot be a constant
8394 or non-matching memory. */
8395 if ((CONSTANT_P (src1)
8396 || (!matching_memory && GET_CODE (src1) == MEM))
8397 && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
8398 src1 = force_reg (mode, src1);
8400 src1 = operands[1] = src1;
8401 src2 = operands[2] = src2;
8405 /* Similarly, but assume that the destination has already been
8409 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
8410 enum machine_mode mode, rtx operands[])
8412 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
8413 gcc_assert (dst == operands[0]);
8416 /* Attempt to expand a binary operator. Make the expansion closer to the
8417 actual machine, then just general_operand, which will allow 3 separate
8418 memory references (one output, two input) in a single insn. */
8421 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
8424 rtx src1, src2, dst, op, clob;
8426 dst = ix86_fixup_binary_operands (code, mode, operands);
8430 /* Emit the instruction. */
8432 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
8433 if (reload_in_progress)
8435 /* Reload doesn't know about the flags register, and doesn't know that
8436 it doesn't want to clobber it. We can only do this with PLUS. */
8437 gcc_assert (code == PLUS);
8442 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8443 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
8446 /* Fix up the destination if needed. */
8447 if (dst != operands[0])
8448 emit_move_insn (operands[0], dst);
8451 /* Return TRUE or FALSE depending on whether the binary operator meets the
8452 appropriate constraints. */
8455 ix86_binary_operator_ok (enum rtx_code code,
8456 enum machine_mode mode ATTRIBUTE_UNUSED,
8459 /* Both source operands cannot be in memory. */
8460 if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM)
8462 /* If the operation is not commutable, source 1 cannot be a constant. */
8463 if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != RTX_COMM_ARITH)
8465 /* If the destination is memory, we must have a matching source operand. */
8466 if (GET_CODE (operands[0]) == MEM
8467 && ! (rtx_equal_p (operands[0], operands[1])
8468 || (GET_RTX_CLASS (code) == RTX_COMM_ARITH
8469 && rtx_equal_p (operands[0], operands[2]))))
8471 /* If the operation is not commutable and the source 1 is memory, we must
8472 have a matching destination. */
8473 if (GET_CODE (operands[1]) == MEM
8474 && GET_RTX_CLASS (code) != RTX_COMM_ARITH
8475 && ! rtx_equal_p (operands[0], operands[1]))
8480 /* Attempt to expand a unary operator. Make the expansion closer to the
8481 actual machine, then just general_operand, which will allow 2 separate
8482 memory references (one output, one input) in a single insn. */
8485 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
8488 int matching_memory;
8489 rtx src, dst, op, clob;
8494 /* If the destination is memory, and we do not have matching source
8495 operands, do things in registers. */
8496 matching_memory = 0;
8499 if (rtx_equal_p (dst, src))
8500 matching_memory = 1;
8502 dst = gen_reg_rtx (mode);
8505 /* When source operand is memory, destination must match. */
8506 if (MEM_P (src) && !matching_memory)
8507 src = force_reg (mode, src);
8509 /* Emit the instruction. */
8511 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
8512 if (reload_in_progress || code == NOT)
8514 /* Reload doesn't know about the flags register, and doesn't know that
8515 it doesn't want to clobber it. */
8516 gcc_assert (code == NOT);
8521 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8522 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
8525 /* Fix up the destination if needed. */
8526 if (dst != operands[0])
8527 emit_move_insn (operands[0], dst);
8530 /* Return TRUE or FALSE depending on whether the unary operator meets the
8531 appropriate constraints. */
8534 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
8535 enum machine_mode mode ATTRIBUTE_UNUSED,
8536 rtx operands[2] ATTRIBUTE_UNUSED)
8538 /* If one of operands is memory, source and destination must match. */
8539 if ((GET_CODE (operands[0]) == MEM
8540 || GET_CODE (operands[1]) == MEM)
8541 && ! rtx_equal_p (operands[0], operands[1]))
8546 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
8547 Create a mask for the sign bit in MODE for an SSE register. If VECT is
8548 true, then replicate the mask for all elements of the vector register.
8549 If INVERT is true, then create a mask excluding the sign bit. */
8552 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
8554 enum machine_mode vec_mode;
8555 HOST_WIDE_INT hi, lo;
8560 /* Find the sign bit, sign extended to 2*HWI. */
8562 lo = 0x80000000, hi = lo < 0;
8563 else if (HOST_BITS_PER_WIDE_INT >= 64)
8564 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
8566 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
8571 /* Force this value into the low part of a fp vector constant. */
8572 mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode);
8573 mask = gen_lowpart (mode, mask);
8578 v = gen_rtvec (4, mask, mask, mask, mask);
8580 v = gen_rtvec (4, mask, CONST0_RTX (SFmode),
8581 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
8582 vec_mode = V4SFmode;
8587 v = gen_rtvec (2, mask, mask);
8589 v = gen_rtvec (2, mask, CONST0_RTX (DFmode));
8590 vec_mode = V2DFmode;
8593 return force_reg (vec_mode, gen_rtx_CONST_VECTOR (vec_mode, v));
8596 /* Generate code for floating point ABS or NEG. */
8599 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
8602 rtx mask, set, use, clob, dst, src;
8603 bool matching_memory;
8604 bool use_sse = false;
8605 bool vector_mode = VECTOR_MODE_P (mode);
8606 enum machine_mode elt_mode = mode;
8610 elt_mode = GET_MODE_INNER (mode);
8613 else if (TARGET_SSE_MATH)
8614 use_sse = SSE_FLOAT_MODE_P (mode);
8616 /* NEG and ABS performed with SSE use bitwise mask operations.
8617 Create the appropriate mask now. */
8619 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
8622 /* When not using SSE, we don't use the mask, but prefer to keep the
8623 same general form of the insn pattern to reduce duplication when
8624 it comes time to split. */
8631 /* If the destination is memory, and we don't have matching source
8632 operands, do things in registers. */
8633 matching_memory = false;
8636 if (rtx_equal_p (dst, src))
8637 matching_memory = true;
8639 dst = gen_reg_rtx (mode);
8641 if (MEM_P (src) && !matching_memory)
8642 src = force_reg (mode, src);
8646 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
8647 set = gen_rtx_SET (VOIDmode, dst, set);
8652 set = gen_rtx_fmt_e (code, mode, src);
8653 set = gen_rtx_SET (VOIDmode, dst, set);
8654 use = gen_rtx_USE (VOIDmode, mask);
8655 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
8656 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, set, use, clob)));
8659 if (dst != operands[0])
8660 emit_move_insn (operands[0], dst);
8663 /* Expand a copysign operation. Special case operand 0 being a constant. */
8666 ix86_expand_copysign (rtx operands[])
8668 enum machine_mode mode, vmode;
8669 rtx dest, op0, op1, mask, nmask;
8675 mode = GET_MODE (dest);
8676 vmode = mode == SFmode ? V4SFmode : V2DFmode;
8678 if (GET_CODE (op0) == CONST_DOUBLE)
8682 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
8683 op0 = simplify_unary_operation (ABS, mode, op0, mode);
8685 if (op0 == CONST0_RTX (mode))
8686 op0 = CONST0_RTX (vmode);
8690 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
8691 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
8693 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
8694 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
8697 mask = ix86_build_signbit_mask (mode, 0, 0);
8700 emit_insn (gen_copysignsf3_const (dest, op0, op1, mask));
8702 emit_insn (gen_copysigndf3_const (dest, op0, op1, mask));
8706 nmask = ix86_build_signbit_mask (mode, 0, 1);
8707 mask = ix86_build_signbit_mask (mode, 0, 0);
8710 emit_insn (gen_copysignsf3_var (dest, NULL, op0, op1, nmask, mask));
8712 emit_insn (gen_copysigndf3_var (dest, NULL, op0, op1, nmask, mask));
8716 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
8717 be a constant, and so has already been expanded into a vector constant. */
8720 ix86_split_copysign_const (rtx operands[])
8722 enum machine_mode mode, vmode;
8723 rtx dest, op0, op1, mask, x;
8730 mode = GET_MODE (dest);
8731 vmode = GET_MODE (mask);
8733 dest = simplify_gen_subreg (vmode, dest, mode, 0);
8734 x = gen_rtx_AND (vmode, dest, mask);
8735 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8737 if (op0 != CONST0_RTX (vmode))
8739 x = gen_rtx_IOR (vmode, dest, op0);
8740 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8744 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
8745 so we have to do two masks. */
8748 ix86_split_copysign_var (rtx operands[])
8750 enum machine_mode mode, vmode;
8751 rtx dest, scratch, op0, op1, mask, nmask, x;
8754 scratch = operands[1];
8757 nmask = operands[4];
8760 mode = GET_MODE (dest);
8761 vmode = GET_MODE (mask);
8763 if (rtx_equal_p (op0, op1))
8765 /* Shouldn't happen often (it's useless, obviously), but when it does
8766 we'd generate incorrect code if we continue below. */
8767 emit_move_insn (dest, op0);
8771 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
8773 gcc_assert (REGNO (op1) == REGNO (scratch));
8775 x = gen_rtx_AND (vmode, scratch, mask);
8776 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
8779 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
8780 x = gen_rtx_NOT (vmode, dest);
8781 x = gen_rtx_AND (vmode, x, op0);
8782 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8786 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
8788 x = gen_rtx_AND (vmode, scratch, mask);
8790 else /* alternative 2,4 */
8792 gcc_assert (REGNO (mask) == REGNO (scratch));
8793 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
8794 x = gen_rtx_AND (vmode, scratch, op1);
8796 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
8798 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
8800 dest = simplify_gen_subreg (vmode, op0, mode, 0);
8801 x = gen_rtx_AND (vmode, dest, nmask);
8803 else /* alternative 3,4 */
8805 gcc_assert (REGNO (nmask) == REGNO (dest));
8807 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
8808 x = gen_rtx_AND (vmode, dest, op0);
8810 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8813 x = gen_rtx_IOR (vmode, dest, scratch);
8814 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
8817 /* Return TRUE or FALSE depending on whether the first SET in INSN
8818 has source and destination with matching CC modes, and that the
8819 CC mode is at least as constrained as REQ_MODE. */
8822 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
8825 enum machine_mode set_mode;
8827 set = PATTERN (insn);
8828 if (GET_CODE (set) == PARALLEL)
8829 set = XVECEXP (set, 0, 0);
8830 gcc_assert (GET_CODE (set) == SET);
8831 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
8833 set_mode = GET_MODE (SET_DEST (set));
8837 if (req_mode != CCNOmode
8838 && (req_mode != CCmode
8839 || XEXP (SET_SRC (set), 1) != const0_rtx))
8843 if (req_mode == CCGCmode)
8847 if (req_mode == CCGOCmode || req_mode == CCNOmode)
8851 if (req_mode == CCZmode)
8861 return (GET_MODE (SET_SRC (set)) == set_mode);
8864 /* Generate insn patterns to do an integer compare of OPERANDS. */
8867 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
8869 enum machine_mode cmpmode;
8872 cmpmode = SELECT_CC_MODE (code, op0, op1);
8873 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
8875 /* This is very simple, but making the interface the same as in the
8876 FP case makes the rest of the code easier. */
8877 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
8878 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
8880 /* Return the test that should be put into the flags user, i.e.
8881 the bcc, scc, or cmov instruction. */
8882 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
8885 /* Figure out whether to use ordered or unordered fp comparisons.
8886 Return the appropriate mode to use. */
8889 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
8891 /* ??? In order to make all comparisons reversible, we do all comparisons
8892 non-trapping when compiling for IEEE. Once gcc is able to distinguish
8893 all forms trapping and nontrapping comparisons, we can make inequality
8894 comparisons trapping again, since it results in better code when using
8895 FCOM based compares. */
8896 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
8900 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
8902 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
8903 return ix86_fp_compare_mode (code);
8906 /* Only zero flag is needed. */
8908 case NE: /* ZF!=0 */
8910 /* Codes needing carry flag. */
8911 case GEU: /* CF=0 */
8912 case GTU: /* CF=0 & ZF=0 */
8913 case LTU: /* CF=1 */
8914 case LEU: /* CF=1 | ZF=1 */
8916 /* Codes possibly doable only with sign flag when
8917 comparing against zero. */
8918 case GE: /* SF=OF or SF=0 */
8919 case LT: /* SF<>OF or SF=1 */
8920 if (op1 == const0_rtx)
8923 /* For other cases Carry flag is not required. */
8925 /* Codes doable only with sign flag when comparing
8926 against zero, but we miss jump instruction for it
8927 so we need to use relational tests against overflow
8928 that thus needs to be zero. */
8929 case GT: /* ZF=0 & SF=OF */
8930 case LE: /* ZF=1 | SF<>OF */
8931 if (op1 == const0_rtx)
8935 /* strcmp pattern do (use flags) and combine may ask us for proper
8944 /* Return the fixed registers used for condition codes. */
8947 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
8954 /* If two condition code modes are compatible, return a condition code
8955 mode which is compatible with both. Otherwise, return
8958 static enum machine_mode
8959 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
8964 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
8967 if ((m1 == CCGCmode && m2 == CCGOCmode)
8968 || (m1 == CCGOCmode && m2 == CCGCmode))
8996 /* These are only compatible with themselves, which we already
9002 /* Return true if we should use an FCOMI instruction for this fp comparison. */
9005 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
9007 enum rtx_code swapped_code = swap_condition (code);
9008 return ((ix86_fp_comparison_cost (code) == ix86_fp_comparison_fcomi_cost (code))
9009 || (ix86_fp_comparison_cost (swapped_code)
9010 == ix86_fp_comparison_fcomi_cost (swapped_code)));
9013 /* Swap, force into registers, or otherwise massage the two operands
9014 to a fp comparison. The operands are updated in place; the new
9015 comparison code is returned. */
9017 static enum rtx_code
9018 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
9020 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
9021 rtx op0 = *pop0, op1 = *pop1;
9022 enum machine_mode op_mode = GET_MODE (op0);
9023 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
9025 /* All of the unordered compare instructions only work on registers.
9026 The same is true of the fcomi compare instructions. The same is
9027 true of the XFmode compare instructions if not comparing with
9028 zero (ftst insn is used in this case). */
9031 && (fpcmp_mode == CCFPUmode
9032 || (op_mode == XFmode
9033 && ! (standard_80387_constant_p (op0) == 1
9034 || standard_80387_constant_p (op1) == 1))
9035 || ix86_use_fcomi_compare (code)))
9037 op0 = force_reg (op_mode, op0);
9038 op1 = force_reg (op_mode, op1);
9042 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
9043 things around if they appear profitable, otherwise force op0
9046 if (standard_80387_constant_p (op0) == 0
9047 || (GET_CODE (op0) == MEM
9048 && ! (standard_80387_constant_p (op1) == 0
9049 || GET_CODE (op1) == MEM)))
9052 tmp = op0, op0 = op1, op1 = tmp;
9053 code = swap_condition (code);
9056 if (GET_CODE (op0) != REG)
9057 op0 = force_reg (op_mode, op0);
9059 if (CONSTANT_P (op1))
9061 int tmp = standard_80387_constant_p (op1);
9063 op1 = validize_mem (force_const_mem (op_mode, op1));
9067 op1 = force_reg (op_mode, op1);
9070 op1 = force_reg (op_mode, op1);
9074 /* Try to rearrange the comparison to make it cheaper. */
9075 if (ix86_fp_comparison_cost (code)
9076 > ix86_fp_comparison_cost (swap_condition (code))
9077 && (GET_CODE (op1) == REG || !no_new_pseudos))
9080 tmp = op0, op0 = op1, op1 = tmp;
9081 code = swap_condition (code);
9082 if (GET_CODE (op0) != REG)
9083 op0 = force_reg (op_mode, op0);
9091 /* Convert comparison codes we use to represent FP comparison to integer
9092 code that will result in proper branch. Return UNKNOWN if no such code
9096 ix86_fp_compare_code_to_integer (enum rtx_code code)
9125 /* Split comparison code CODE into comparisons we can do using branch
9126 instructions. BYPASS_CODE is comparison code for branch that will
9127 branch around FIRST_CODE and SECOND_CODE. If some of branches
9128 is not required, set value to UNKNOWN.
9129 We never require more than two branches. */
9132 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
9133 enum rtx_code *first_code,
9134 enum rtx_code *second_code)
9137 *bypass_code = UNKNOWN;
9138 *second_code = UNKNOWN;
9140 /* The fcomi comparison sets flags as follows:
9150 case GT: /* GTU - CF=0 & ZF=0 */
9151 case GE: /* GEU - CF=0 */
9152 case ORDERED: /* PF=0 */
9153 case UNORDERED: /* PF=1 */
9154 case UNEQ: /* EQ - ZF=1 */
9155 case UNLT: /* LTU - CF=1 */
9156 case UNLE: /* LEU - CF=1 | ZF=1 */
9157 case LTGT: /* EQ - ZF=0 */
9159 case LT: /* LTU - CF=1 - fails on unordered */
9161 *bypass_code = UNORDERED;
9163 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
9165 *bypass_code = UNORDERED;
9167 case EQ: /* EQ - ZF=1 - fails on unordered */
9169 *bypass_code = UNORDERED;
9171 case NE: /* NE - ZF=0 - fails on unordered */
9173 *second_code = UNORDERED;
9175 case UNGE: /* GEU - CF=0 - fails on unordered */
9177 *second_code = UNORDERED;
9179 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
9181 *second_code = UNORDERED;
9186 if (!TARGET_IEEE_FP)
9188 *second_code = UNKNOWN;
9189 *bypass_code = UNKNOWN;
9193 /* Return cost of comparison done fcom + arithmetics operations on AX.
9194 All following functions do use number of instructions as a cost metrics.
9195 In future this should be tweaked to compute bytes for optimize_size and
9196 take into account performance of various instructions on various CPUs. */
9198 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
9200 if (!TARGET_IEEE_FP)
9202 /* The cost of code output by ix86_expand_fp_compare. */
9230 /* Return cost of comparison done using fcomi operation.
9231 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9233 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
9235 enum rtx_code bypass_code, first_code, second_code;
9236 /* Return arbitrarily high cost when instruction is not supported - this
9237 prevents gcc from using it. */
9240 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9241 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
9244 /* Return cost of comparison done using sahf operation.
9245 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9247 ix86_fp_comparison_sahf_cost (enum rtx_code code)
9249 enum rtx_code bypass_code, first_code, second_code;
9250 /* Return arbitrarily high cost when instruction is not preferred - this
9251 avoids gcc from using it. */
9252 if (!TARGET_USE_SAHF && !optimize_size)
9254 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9255 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
9258 /* Compute cost of the comparison done using any method.
9259 See ix86_fp_comparison_arithmetics_cost for the metrics. */
9261 ix86_fp_comparison_cost (enum rtx_code code)
9263 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
9266 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
9267 sahf_cost = ix86_fp_comparison_sahf_cost (code);
9269 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
9270 if (min > sahf_cost)
9272 if (min > fcomi_cost)
9277 /* Generate insn patterns to do a floating point compare of OPERANDS. */
9280 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
9281 rtx *second_test, rtx *bypass_test)
9283 enum machine_mode fpcmp_mode, intcmp_mode;
9285 int cost = ix86_fp_comparison_cost (code);
9286 enum rtx_code bypass_code, first_code, second_code;
9288 fpcmp_mode = ix86_fp_compare_mode (code);
9289 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
9292 *second_test = NULL_RTX;
9294 *bypass_test = NULL_RTX;
9296 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9298 /* Do fcomi/sahf based test when profitable. */
9299 if ((bypass_code == UNKNOWN || bypass_test)
9300 && (second_code == UNKNOWN || second_test)
9301 && ix86_fp_comparison_arithmetics_cost (code) > cost)
9305 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9306 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
9312 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9313 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9315 scratch = gen_reg_rtx (HImode);
9316 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9317 emit_insn (gen_x86_sahf_1 (scratch));
9320 /* The FP codes work out to act like unsigned. */
9321 intcmp_mode = fpcmp_mode;
9323 if (bypass_code != UNKNOWN)
9324 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
9325 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9327 if (second_code != UNKNOWN)
9328 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
9329 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9334 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
9335 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
9336 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
9338 scratch = gen_reg_rtx (HImode);
9339 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
9341 /* In the unordered case, we have to check C2 for NaN's, which
9342 doesn't happen to work out to anything nice combination-wise.
9343 So do some bit twiddling on the value we've got in AH to come
9344 up with an appropriate set of condition codes. */
9346 intcmp_mode = CCNOmode;
9351 if (code == GT || !TARGET_IEEE_FP)
9353 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
9358 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9359 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
9360 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
9361 intcmp_mode = CCmode;
9367 if (code == LT && TARGET_IEEE_FP)
9369 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9370 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
9371 intcmp_mode = CCmode;
9376 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
9382 if (code == GE || !TARGET_IEEE_FP)
9384 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
9389 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9390 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
9397 if (code == LE && TARGET_IEEE_FP)
9399 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9400 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
9401 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
9402 intcmp_mode = CCmode;
9407 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
9413 if (code == EQ && TARGET_IEEE_FP)
9415 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9416 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
9417 intcmp_mode = CCmode;
9422 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
9429 if (code == NE && TARGET_IEEE_FP)
9431 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
9432 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
9438 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
9444 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
9448 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
9457 /* Return the test that should be put into the flags user, i.e.
9458 the bcc, scc, or cmov instruction. */
9459 return gen_rtx_fmt_ee (code, VOIDmode,
9460 gen_rtx_REG (intcmp_mode, FLAGS_REG),
9465 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
9468 op0 = ix86_compare_op0;
9469 op1 = ix86_compare_op1;
9472 *second_test = NULL_RTX;
9474 *bypass_test = NULL_RTX;
9476 if (ix86_compare_emitted)
9478 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
9479 ix86_compare_emitted = NULL_RTX;
9481 else if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
9482 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
9483 second_test, bypass_test);
9485 ret = ix86_expand_int_compare (code, op0, op1);
9490 /* Return true if the CODE will result in nontrivial jump sequence. */
9492 ix86_fp_jump_nontrivial_p (enum rtx_code code)
9494 enum rtx_code bypass_code, first_code, second_code;
9497 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9498 return bypass_code != UNKNOWN || second_code != UNKNOWN;
9502 ix86_expand_branch (enum rtx_code code, rtx label)
9506 switch (GET_MODE (ix86_compare_op0))
9512 tmp = ix86_expand_compare (code, NULL, NULL);
9513 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9514 gen_rtx_LABEL_REF (VOIDmode, label),
9516 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
9525 enum rtx_code bypass_code, first_code, second_code;
9527 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
9530 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
9532 /* Check whether we will use the natural sequence with one jump. If
9533 so, we can expand jump early. Otherwise delay expansion by
9534 creating compound insn to not confuse optimizers. */
9535 if (bypass_code == UNKNOWN && second_code == UNKNOWN
9538 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
9539 gen_rtx_LABEL_REF (VOIDmode, label),
9540 pc_rtx, NULL_RTX, NULL_RTX);
9544 tmp = gen_rtx_fmt_ee (code, VOIDmode,
9545 ix86_compare_op0, ix86_compare_op1);
9546 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
9547 gen_rtx_LABEL_REF (VOIDmode, label),
9549 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
9551 use_fcomi = ix86_use_fcomi_compare (code);
9552 vec = rtvec_alloc (3 + !use_fcomi);
9553 RTVEC_ELT (vec, 0) = tmp;
9555 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 18));
9557 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 17));
9560 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
9562 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
9571 /* Expand DImode branch into multiple compare+branch. */
9573 rtx lo[2], hi[2], label2;
9574 enum rtx_code code1, code2, code3;
9575 enum machine_mode submode;
9577 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
9579 tmp = ix86_compare_op0;
9580 ix86_compare_op0 = ix86_compare_op1;
9581 ix86_compare_op1 = tmp;
9582 code = swap_condition (code);
9584 if (GET_MODE (ix86_compare_op0) == DImode)
9586 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
9587 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
9592 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
9593 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
9597 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
9598 avoid two branches. This costs one extra insn, so disable when
9599 optimizing for size. */
9601 if ((code == EQ || code == NE)
9603 || hi[1] == const0_rtx || lo[1] == const0_rtx))
9608 if (hi[1] != const0_rtx)
9609 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
9610 NULL_RTX, 0, OPTAB_WIDEN);
9613 if (lo[1] != const0_rtx)
9614 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
9615 NULL_RTX, 0, OPTAB_WIDEN);
9617 tmp = expand_binop (submode, ior_optab, xor1, xor0,
9618 NULL_RTX, 0, OPTAB_WIDEN);
9620 ix86_compare_op0 = tmp;
9621 ix86_compare_op1 = const0_rtx;
9622 ix86_expand_branch (code, label);
9626 /* Otherwise, if we are doing less-than or greater-or-equal-than,
9627 op1 is a constant and the low word is zero, then we can just
9628 examine the high word. */
9630 if (GET_CODE (hi[1]) == CONST_INT && lo[1] == const0_rtx)
9633 case LT: case LTU: case GE: case GEU:
9634 ix86_compare_op0 = hi[0];
9635 ix86_compare_op1 = hi[1];
9636 ix86_expand_branch (code, label);
9642 /* Otherwise, we need two or three jumps. */
9644 label2 = gen_label_rtx ();
9647 code2 = swap_condition (code);
9648 code3 = unsigned_condition (code);
9652 case LT: case GT: case LTU: case GTU:
9655 case LE: code1 = LT; code2 = GT; break;
9656 case GE: code1 = GT; code2 = LT; break;
9657 case LEU: code1 = LTU; code2 = GTU; break;
9658 case GEU: code1 = GTU; code2 = LTU; break;
9660 case EQ: code1 = UNKNOWN; code2 = NE; break;
9661 case NE: code2 = UNKNOWN; break;
9669 * if (hi(a) < hi(b)) goto true;
9670 * if (hi(a) > hi(b)) goto false;
9671 * if (lo(a) < lo(b)) goto true;
9675 ix86_compare_op0 = hi[0];
9676 ix86_compare_op1 = hi[1];
9678 if (code1 != UNKNOWN)
9679 ix86_expand_branch (code1, label);
9680 if (code2 != UNKNOWN)
9681 ix86_expand_branch (code2, label2);
9683 ix86_compare_op0 = lo[0];
9684 ix86_compare_op1 = lo[1];
9685 ix86_expand_branch (code3, label);
9687 if (code2 != UNKNOWN)
9688 emit_label (label2);
9697 /* Split branch based on floating point condition. */
9699 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
9700 rtx target1, rtx target2, rtx tmp, rtx pushed)
9703 rtx label = NULL_RTX;
9705 int bypass_probability = -1, second_probability = -1, probability = -1;
9708 if (target2 != pc_rtx)
9711 code = reverse_condition_maybe_unordered (code);
9716 condition = ix86_expand_fp_compare (code, op1, op2,
9717 tmp, &second, &bypass);
9719 /* Remove pushed operand from stack. */
9721 ix86_free_from_memory (GET_MODE (pushed));
9723 if (split_branch_probability >= 0)
9725 /* Distribute the probabilities across the jumps.
9726 Assume the BYPASS and SECOND to be always test
9728 probability = split_branch_probability;
9730 /* Value of 1 is low enough to make no need for probability
9731 to be updated. Later we may run some experiments and see
9732 if unordered values are more frequent in practice. */
9734 bypass_probability = 1;
9736 second_probability = 1;
9738 if (bypass != NULL_RTX)
9740 label = gen_label_rtx ();
9741 i = emit_jump_insn (gen_rtx_SET
9743 gen_rtx_IF_THEN_ELSE (VOIDmode,
9745 gen_rtx_LABEL_REF (VOIDmode,
9748 if (bypass_probability >= 0)
9750 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9751 GEN_INT (bypass_probability),
9754 i = emit_jump_insn (gen_rtx_SET
9756 gen_rtx_IF_THEN_ELSE (VOIDmode,
9757 condition, target1, target2)));
9758 if (probability >= 0)
9760 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9761 GEN_INT (probability),
9763 if (second != NULL_RTX)
9765 i = emit_jump_insn (gen_rtx_SET
9767 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
9769 if (second_probability >= 0)
9771 = gen_rtx_EXPR_LIST (REG_BR_PROB,
9772 GEN_INT (second_probability),
9775 if (label != NULL_RTX)
9780 ix86_expand_setcc (enum rtx_code code, rtx dest)
9782 rtx ret, tmp, tmpreg, equiv;
9783 rtx second_test, bypass_test;
9785 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
9786 return 0; /* FAIL */
9788 gcc_assert (GET_MODE (dest) == QImode);
9790 ret = ix86_expand_compare (code, &second_test, &bypass_test);
9791 PUT_MODE (ret, QImode);
9796 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
9797 if (bypass_test || second_test)
9799 rtx test = second_test;
9801 rtx tmp2 = gen_reg_rtx (QImode);
9804 gcc_assert (!second_test);
9807 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
9809 PUT_MODE (test, QImode);
9810 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
9813 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
9815 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
9818 /* Attach a REG_EQUAL note describing the comparison result. */
9819 if (ix86_compare_op0 && ix86_compare_op1)
9821 equiv = simplify_gen_relational (code, QImode,
9822 GET_MODE (ix86_compare_op0),
9823 ix86_compare_op0, ix86_compare_op1);
9824 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
9827 return 1; /* DONE */
9830 /* Expand comparison setting or clearing carry flag. Return true when
9831 successful and set pop for the operation. */
9833 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
9835 enum machine_mode mode =
9836 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
9838 /* Do not handle DImode compares that go trought special path. Also we can't
9839 deal with FP compares yet. This is possible to add. */
9840 if (mode == (TARGET_64BIT ? TImode : DImode))
9842 if (FLOAT_MODE_P (mode))
9844 rtx second_test = NULL, bypass_test = NULL;
9845 rtx compare_op, compare_seq;
9847 /* Shortcut: following common codes never translate into carry flag compares. */
9848 if (code == EQ || code == NE || code == UNEQ || code == LTGT
9849 || code == ORDERED || code == UNORDERED)
9852 /* These comparisons require zero flag; swap operands so they won't. */
9853 if ((code == GT || code == UNLE || code == LE || code == UNGT)
9859 code = swap_condition (code);
9862 /* Try to expand the comparison and verify that we end up with carry flag
9863 based comparison. This is fails to be true only when we decide to expand
9864 comparison using arithmetic that is not too common scenario. */
9866 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
9867 &second_test, &bypass_test);
9868 compare_seq = get_insns ();
9871 if (second_test || bypass_test)
9873 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
9874 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
9875 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
9877 code = GET_CODE (compare_op);
9878 if (code != LTU && code != GEU)
9880 emit_insn (compare_seq);
9884 if (!INTEGRAL_MODE_P (mode))
9892 /* Convert a==0 into (unsigned)a<1. */
9895 if (op1 != const0_rtx)
9898 code = (code == EQ ? LTU : GEU);
9901 /* Convert a>b into b<a or a>=b-1. */
9904 if (GET_CODE (op1) == CONST_INT)
9906 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
9907 /* Bail out on overflow. We still can swap operands but that
9908 would force loading of the constant into register. */
9909 if (op1 == const0_rtx
9910 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
9912 code = (code == GTU ? GEU : LTU);
9919 code = (code == GTU ? LTU : GEU);
9923 /* Convert a>=0 into (unsigned)a<0x80000000. */
9926 if (mode == DImode || op1 != const0_rtx)
9928 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
9929 code = (code == LT ? GEU : LTU);
9933 if (mode == DImode || op1 != constm1_rtx)
9935 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
9936 code = (code == LE ? GEU : LTU);
9942 /* Swapping operands may cause constant to appear as first operand. */
9943 if (!nonimmediate_operand (op0, VOIDmode))
9947 op0 = force_reg (mode, op0);
9949 ix86_compare_op0 = op0;
9950 ix86_compare_op1 = op1;
9951 *pop = ix86_expand_compare (code, NULL, NULL);
9952 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
9957 ix86_expand_int_movcc (rtx operands[])
9959 enum rtx_code code = GET_CODE (operands[1]), compare_code;
9960 rtx compare_seq, compare_op;
9961 rtx second_test, bypass_test;
9962 enum machine_mode mode = GET_MODE (operands[0]);
9963 bool sign_bit_compare_p = false;;
9966 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
9967 compare_seq = get_insns ();
9970 compare_code = GET_CODE (compare_op);
9972 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
9973 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
9974 sign_bit_compare_p = true;
9976 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
9977 HImode insns, we'd be swallowed in word prefix ops. */
9979 if ((mode != HImode || TARGET_FAST_PREFIX)
9980 && (mode != (TARGET_64BIT ? TImode : DImode))
9981 && GET_CODE (operands[2]) == CONST_INT
9982 && GET_CODE (operands[3]) == CONST_INT)
9984 rtx out = operands[0];
9985 HOST_WIDE_INT ct = INTVAL (operands[2]);
9986 HOST_WIDE_INT cf = INTVAL (operands[3]);
9990 /* Sign bit compares are better done using shifts than we do by using
9992 if (sign_bit_compare_p
9993 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
9994 ix86_compare_op1, &compare_op))
9996 /* Detect overlap between destination and compare sources. */
9999 if (!sign_bit_compare_p)
10001 bool fpcmp = false;
10003 compare_code = GET_CODE (compare_op);
10005 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10006 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10009 compare_code = ix86_fp_compare_code_to_integer (compare_code);
10012 /* To simplify rest of code, restrict to the GEU case. */
10013 if (compare_code == LTU)
10015 HOST_WIDE_INT tmp = ct;
10018 compare_code = reverse_condition (compare_code);
10019 code = reverse_condition (code);
10024 PUT_CODE (compare_op,
10025 reverse_condition_maybe_unordered
10026 (GET_CODE (compare_op)));
10028 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
10032 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
10033 || reg_overlap_mentioned_p (out, ix86_compare_op1))
10034 tmp = gen_reg_rtx (mode);
10036 if (mode == DImode)
10037 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
10039 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
10043 if (code == GT || code == GE)
10044 code = reverse_condition (code);
10047 HOST_WIDE_INT tmp = ct;
10052 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
10053 ix86_compare_op1, VOIDmode, 0, -1);
10066 tmp = expand_simple_binop (mode, PLUS,
10068 copy_rtx (tmp), 1, OPTAB_DIRECT);
10079 tmp = expand_simple_binop (mode, IOR,
10081 copy_rtx (tmp), 1, OPTAB_DIRECT);
10083 else if (diff == -1 && ct)
10093 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10095 tmp = expand_simple_binop (mode, PLUS,
10096 copy_rtx (tmp), GEN_INT (cf),
10097 copy_rtx (tmp), 1, OPTAB_DIRECT);
10105 * andl cf - ct, dest
10115 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
10118 tmp = expand_simple_binop (mode, AND,
10120 gen_int_mode (cf - ct, mode),
10121 copy_rtx (tmp), 1, OPTAB_DIRECT);
10123 tmp = expand_simple_binop (mode, PLUS,
10124 copy_rtx (tmp), GEN_INT (ct),
10125 copy_rtx (tmp), 1, OPTAB_DIRECT);
10128 if (!rtx_equal_p (tmp, out))
10129 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
10131 return 1; /* DONE */
10137 tmp = ct, ct = cf, cf = tmp;
10139 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10141 /* We may be reversing unordered compare to normal compare, that
10142 is not valid in general (we may convert non-trapping condition
10143 to trapping one), however on i386 we currently emit all
10144 comparisons unordered. */
10145 compare_code = reverse_condition_maybe_unordered (compare_code);
10146 code = reverse_condition_maybe_unordered (code);
10150 compare_code = reverse_condition (compare_code);
10151 code = reverse_condition (code);
10155 compare_code = UNKNOWN;
10156 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
10157 && GET_CODE (ix86_compare_op1) == CONST_INT)
10159 if (ix86_compare_op1 == const0_rtx
10160 && (code == LT || code == GE))
10161 compare_code = code;
10162 else if (ix86_compare_op1 == constm1_rtx)
10166 else if (code == GT)
10171 /* Optimize dest = (op0 < 0) ? -1 : cf. */
10172 if (compare_code != UNKNOWN
10173 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
10174 && (cf == -1 || ct == -1))
10176 /* If lea code below could be used, only optimize
10177 if it results in a 2 insn sequence. */
10179 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
10180 || diff == 3 || diff == 5 || diff == 9)
10181 || (compare_code == LT && ct == -1)
10182 || (compare_code == GE && cf == -1))
10185 * notl op1 (if necessary)
10193 code = reverse_condition (code);
10196 out = emit_store_flag (out, code, ix86_compare_op0,
10197 ix86_compare_op1, VOIDmode, 0, -1);
10199 out = expand_simple_binop (mode, IOR,
10201 out, 1, OPTAB_DIRECT);
10202 if (out != operands[0])
10203 emit_move_insn (operands[0], out);
10205 return 1; /* DONE */
10210 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
10211 || diff == 3 || diff == 5 || diff == 9)
10212 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
10214 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
10220 * lea cf(dest*(ct-cf)),dest
10224 * This also catches the degenerate setcc-only case.
10230 out = emit_store_flag (out, code, ix86_compare_op0,
10231 ix86_compare_op1, VOIDmode, 0, 1);
10234 /* On x86_64 the lea instruction operates on Pmode, so we need
10235 to get arithmetics done in proper mode to match. */
10237 tmp = copy_rtx (out);
10241 out1 = copy_rtx (out);
10242 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
10246 tmp = gen_rtx_PLUS (mode, tmp, out1);
10252 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
10255 if (!rtx_equal_p (tmp, out))
10258 out = force_operand (tmp, copy_rtx (out));
10260 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
10262 if (!rtx_equal_p (out, operands[0]))
10263 emit_move_insn (operands[0], copy_rtx (out));
10265 return 1; /* DONE */
10269 * General case: Jumpful:
10270 * xorl dest,dest cmpl op1, op2
10271 * cmpl op1, op2 movl ct, dest
10272 * setcc dest jcc 1f
10273 * decl dest movl cf, dest
10274 * andl (cf-ct),dest 1:
10277 * Size 20. Size 14.
10279 * This is reasonably steep, but branch mispredict costs are
10280 * high on modern cpus, so consider failing only if optimizing
10284 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10285 && BRANCH_COST >= 2)
10291 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0)))
10292 /* We may be reversing unordered compare to normal compare,
10293 that is not valid in general (we may convert non-trapping
10294 condition to trapping one), however on i386 we currently
10295 emit all comparisons unordered. */
10296 code = reverse_condition_maybe_unordered (code);
10299 code = reverse_condition (code);
10300 if (compare_code != UNKNOWN)
10301 compare_code = reverse_condition (compare_code);
10305 if (compare_code != UNKNOWN)
10307 /* notl op1 (if needed)
10312 For x < 0 (resp. x <= -1) there will be no notl,
10313 so if possible swap the constants to get rid of the
10315 True/false will be -1/0 while code below (store flag
10316 followed by decrement) is 0/-1, so the constants need
10317 to be exchanged once more. */
10319 if (compare_code == GE || !cf)
10321 code = reverse_condition (code);
10326 HOST_WIDE_INT tmp = cf;
10331 out = emit_store_flag (out, code, ix86_compare_op0,
10332 ix86_compare_op1, VOIDmode, 0, -1);
10336 out = emit_store_flag (out, code, ix86_compare_op0,
10337 ix86_compare_op1, VOIDmode, 0, 1);
10339 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
10340 copy_rtx (out), 1, OPTAB_DIRECT);
10343 out = expand_simple_binop (mode, AND, copy_rtx (out),
10344 gen_int_mode (cf - ct, mode),
10345 copy_rtx (out), 1, OPTAB_DIRECT);
10347 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
10348 copy_rtx (out), 1, OPTAB_DIRECT);
10349 if (!rtx_equal_p (out, operands[0]))
10350 emit_move_insn (operands[0], copy_rtx (out));
10352 return 1; /* DONE */
10356 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
10358 /* Try a few things more with specific constants and a variable. */
10361 rtx var, orig_out, out, tmp;
10363 if (BRANCH_COST <= 2)
10364 return 0; /* FAIL */
10366 /* If one of the two operands is an interesting constant, load a
10367 constant with the above and mask it in with a logical operation. */
10369 if (GET_CODE (operands[2]) == CONST_INT)
10372 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
10373 operands[3] = constm1_rtx, op = and_optab;
10374 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
10375 operands[3] = const0_rtx, op = ior_optab;
10377 return 0; /* FAIL */
10379 else if (GET_CODE (operands[3]) == CONST_INT)
10382 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
10383 operands[2] = constm1_rtx, op = and_optab;
10384 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
10385 operands[2] = const0_rtx, op = ior_optab;
10387 return 0; /* FAIL */
10390 return 0; /* FAIL */
10392 orig_out = operands[0];
10393 tmp = gen_reg_rtx (mode);
10396 /* Recurse to get the constant loaded. */
10397 if (ix86_expand_int_movcc (operands) == 0)
10398 return 0; /* FAIL */
10400 /* Mask in the interesting variable. */
10401 out = expand_binop (mode, op, var, tmp, orig_out, 0,
10403 if (!rtx_equal_p (out, orig_out))
10404 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
10406 return 1; /* DONE */
10410 * For comparison with above,
10420 if (! nonimmediate_operand (operands[2], mode))
10421 operands[2] = force_reg (mode, operands[2]);
10422 if (! nonimmediate_operand (operands[3], mode))
10423 operands[3] = force_reg (mode, operands[3]);
10425 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
10427 rtx tmp = gen_reg_rtx (mode);
10428 emit_move_insn (tmp, operands[3]);
10431 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
10433 rtx tmp = gen_reg_rtx (mode);
10434 emit_move_insn (tmp, operands[2]);
10438 if (! register_operand (operands[2], VOIDmode)
10440 || ! register_operand (operands[3], VOIDmode)))
10441 operands[2] = force_reg (mode, operands[2]);
10444 && ! register_operand (operands[3], VOIDmode))
10445 operands[3] = force_reg (mode, operands[3]);
10447 emit_insn (compare_seq);
10448 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10449 gen_rtx_IF_THEN_ELSE (mode,
10450 compare_op, operands[2],
10453 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
10454 gen_rtx_IF_THEN_ELSE (mode,
10456 copy_rtx (operands[3]),
10457 copy_rtx (operands[0]))));
10459 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
10460 gen_rtx_IF_THEN_ELSE (mode,
10462 copy_rtx (operands[2]),
10463 copy_rtx (operands[0]))));
10465 return 1; /* DONE */
10468 /* Swap, force into registers, or otherwise massage the two operands
10469 to an sse comparison with a mask result. Thus we differ a bit from
10470 ix86_prepare_fp_compare_args which expects to produce a flags result.
10472 The DEST operand exists to help determine whether to commute commutative
10473 operators. The POP0/POP1 operands are updated in place. The new
10474 comparison code is returned, or UNKNOWN if not implementable. */
10476 static enum rtx_code
10477 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
10478 rtx *pop0, rtx *pop1)
10486 /* We have no LTGT as an operator. We could implement it with
10487 NE & ORDERED, but this requires an extra temporary. It's
10488 not clear that it's worth it. */
10495 /* These are supported directly. */
10502 /* For commutative operators, try to canonicalize the destination
10503 operand to be first in the comparison - this helps reload to
10504 avoid extra moves. */
10505 if (!dest || !rtx_equal_p (dest, *pop1))
10513 /* These are not supported directly. Swap the comparison operands
10514 to transform into something that is supported. */
10518 code = swap_condition (code);
10522 gcc_unreachable ();
10528 /* Detect conditional moves that exactly match min/max operational
10529 semantics. Note that this is IEEE safe, as long as we don't
10530 interchange the operands.
10532 Returns FALSE if this conditional move doesn't match a MIN/MAX,
10533 and TRUE if the operation is successful and instructions are emitted. */
10536 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
10537 rtx cmp_op1, rtx if_true, rtx if_false)
10539 enum machine_mode mode;
10545 else if (code == UNGE)
10548 if_true = if_false;
10554 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
10556 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
10561 mode = GET_MODE (dest);
10563 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
10564 but MODE may be a vector mode and thus not appropriate. */
10565 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
10567 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
10570 if_true = force_reg (mode, if_true);
10571 v = gen_rtvec (2, if_true, if_false);
10572 tmp = gen_rtx_UNSPEC (mode, v, u);
10576 code = is_min ? SMIN : SMAX;
10577 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
10580 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
10584 /* Expand an sse vector comparison. Return the register with the result. */
10587 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
10588 rtx op_true, rtx op_false)
10590 enum machine_mode mode = GET_MODE (dest);
10593 cmp_op0 = force_reg (mode, cmp_op0);
10594 if (!nonimmediate_operand (cmp_op1, mode))
10595 cmp_op1 = force_reg (mode, cmp_op1);
10598 || reg_overlap_mentioned_p (dest, op_true)
10599 || reg_overlap_mentioned_p (dest, op_false))
10600 dest = gen_reg_rtx (mode);
10602 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
10603 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10608 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
10609 operations. This is used for both scalar and vector conditional moves. */
10612 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
10614 enum machine_mode mode = GET_MODE (dest);
10617 if (op_false == CONST0_RTX (mode))
10619 op_true = force_reg (mode, op_true);
10620 x = gen_rtx_AND (mode, cmp, op_true);
10621 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10623 else if (op_true == CONST0_RTX (mode))
10625 op_false = force_reg (mode, op_false);
10626 x = gen_rtx_NOT (mode, cmp);
10627 x = gen_rtx_AND (mode, x, op_false);
10628 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10632 op_true = force_reg (mode, op_true);
10633 op_false = force_reg (mode, op_false);
10635 t2 = gen_reg_rtx (mode);
10637 t3 = gen_reg_rtx (mode);
10641 x = gen_rtx_AND (mode, op_true, cmp);
10642 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
10644 x = gen_rtx_NOT (mode, cmp);
10645 x = gen_rtx_AND (mode, x, op_false);
10646 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
10648 x = gen_rtx_IOR (mode, t3, t2);
10649 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10653 /* Expand a floating-point conditional move. Return true if successful. */
10656 ix86_expand_fp_movcc (rtx operands[])
10658 enum machine_mode mode = GET_MODE (operands[0]);
10659 enum rtx_code code = GET_CODE (operands[1]);
10660 rtx tmp, compare_op, second_test, bypass_test;
10662 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
10664 enum machine_mode cmode;
10666 /* Since we've no cmove for sse registers, don't force bad register
10667 allocation just to gain access to it. Deny movcc when the
10668 comparison mode doesn't match the move mode. */
10669 cmode = GET_MODE (ix86_compare_op0);
10670 if (cmode == VOIDmode)
10671 cmode = GET_MODE (ix86_compare_op1);
10675 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
10677 &ix86_compare_op1);
10678 if (code == UNKNOWN)
10681 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
10682 ix86_compare_op1, operands[2],
10686 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
10687 ix86_compare_op1, operands[2], operands[3]);
10688 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
10692 /* The floating point conditional move instructions don't directly
10693 support conditions resulting from a signed integer comparison. */
10695 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10697 /* The floating point conditional move instructions don't directly
10698 support signed integer comparisons. */
10700 if (!fcmov_comparison_operator (compare_op, VOIDmode))
10702 gcc_assert (!second_test && !bypass_test);
10703 tmp = gen_reg_rtx (QImode);
10704 ix86_expand_setcc (code, tmp);
10706 ix86_compare_op0 = tmp;
10707 ix86_compare_op1 = const0_rtx;
10708 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
10710 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
10712 tmp = gen_reg_rtx (mode);
10713 emit_move_insn (tmp, operands[3]);
10716 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
10718 tmp = gen_reg_rtx (mode);
10719 emit_move_insn (tmp, operands[2]);
10723 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10724 gen_rtx_IF_THEN_ELSE (mode, compare_op,
10725 operands[2], operands[3])));
10727 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10728 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
10729 operands[3], operands[0])));
10731 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10732 gen_rtx_IF_THEN_ELSE (mode, second_test,
10733 operands[2], operands[0])));
10738 /* Expand a floating-point vector conditional move; a vcond operation
10739 rather than a movcc operation. */
10742 ix86_expand_fp_vcond (rtx operands[])
10744 enum rtx_code code = GET_CODE (operands[3]);
10747 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
10748 &operands[4], &operands[5]);
10749 if (code == UNKNOWN)
10752 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
10753 operands[5], operands[1], operands[2]))
10756 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
10757 operands[1], operands[2]);
10758 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
10762 /* Expand a signed integral vector conditional move. */
10765 ix86_expand_int_vcond (rtx operands[])
10767 enum machine_mode mode = GET_MODE (operands[0]);
10768 enum rtx_code code = GET_CODE (operands[3]);
10769 bool negate = false;
10772 cop0 = operands[4];
10773 cop1 = operands[5];
10775 /* Canonicalize the comparison to EQ, GT, GTU. */
10786 code = reverse_condition (code);
10792 code = reverse_condition (code);
10798 code = swap_condition (code);
10799 x = cop0, cop0 = cop1, cop1 = x;
10803 gcc_unreachable ();
10806 /* Unsigned parallel compare is not supported by the hardware. Play some
10807 tricks to turn this into a signed comparison against 0. */
10816 /* Perform a parallel modulo subtraction. */
10817 t1 = gen_reg_rtx (mode);
10818 emit_insn (gen_subv4si3 (t1, cop0, cop1));
10820 /* Extract the original sign bit of op0. */
10821 mask = GEN_INT (-0x80000000);
10822 mask = gen_rtx_CONST_VECTOR (mode,
10823 gen_rtvec (4, mask, mask, mask, mask));
10824 mask = force_reg (mode, mask);
10825 t2 = gen_reg_rtx (mode);
10826 emit_insn (gen_andv4si3 (t2, cop0, mask));
10828 /* XOR it back into the result of the subtraction. This results
10829 in the sign bit set iff we saw unsigned underflow. */
10830 x = gen_reg_rtx (mode);
10831 emit_insn (gen_xorv4si3 (x, t1, t2));
10839 /* Perform a parallel unsigned saturating subtraction. */
10840 x = gen_reg_rtx (mode);
10841 emit_insn (gen_rtx_SET (VOIDmode, x,
10842 gen_rtx_US_MINUS (mode, cop0, cop1)));
10849 gcc_unreachable ();
10853 cop1 = CONST0_RTX (mode);
10856 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
10857 operands[1+negate], operands[2-negate]);
10859 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
10860 operands[2-negate]);
10864 /* Expand conditional increment or decrement using adb/sbb instructions.
10865 The default case using setcc followed by the conditional move can be
10866 done by generic code. */
10868 ix86_expand_int_addcc (rtx operands[])
10870 enum rtx_code code = GET_CODE (operands[1]);
10872 rtx val = const0_rtx;
10873 bool fpcmp = false;
10874 enum machine_mode mode = GET_MODE (operands[0]);
10876 if (operands[3] != const1_rtx
10877 && operands[3] != constm1_rtx)
10879 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
10880 ix86_compare_op1, &compare_op))
10882 code = GET_CODE (compare_op);
10884 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
10885 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
10888 code = ix86_fp_compare_code_to_integer (code);
10895 PUT_CODE (compare_op,
10896 reverse_condition_maybe_unordered
10897 (GET_CODE (compare_op)));
10899 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
10901 PUT_MODE (compare_op, mode);
10903 /* Construct either adc or sbb insn. */
10904 if ((code == LTU) == (operands[3] == constm1_rtx))
10906 switch (GET_MODE (operands[0]))
10909 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
10912 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
10915 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
10918 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
10921 gcc_unreachable ();
10926 switch (GET_MODE (operands[0]))
10929 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
10932 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
10935 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
10938 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
10941 gcc_unreachable ();
10944 return 1; /* DONE */
10948 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
10949 works for floating pointer parameters and nonoffsetable memories.
10950 For pushes, it returns just stack offsets; the values will be saved
10951 in the right order. Maximally three parts are generated. */
10954 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
10959 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
10961 size = (GET_MODE_SIZE (mode) + 4) / 8;
10963 gcc_assert (GET_CODE (operand) != REG || !MMX_REGNO_P (REGNO (operand)));
10964 gcc_assert (size >= 2 && size <= 3);
10966 /* Optimize constant pool reference to immediates. This is used by fp
10967 moves, that force all constants to memory to allow combining. */
10968 if (GET_CODE (operand) == MEM && MEM_READONLY_P (operand))
10970 rtx tmp = maybe_get_pool_constant (operand);
10975 if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand))
10977 /* The only non-offsetable memories we handle are pushes. */
10978 int ok = push_operand (operand, VOIDmode);
10982 operand = copy_rtx (operand);
10983 PUT_MODE (operand, Pmode);
10984 parts[0] = parts[1] = parts[2] = operand;
10988 if (GET_CODE (operand) == CONST_VECTOR)
10990 enum machine_mode imode = int_mode_for_mode (mode);
10991 /* Caution: if we looked through a constant pool memory above,
10992 the operand may actually have a different mode now. That's
10993 ok, since we want to pun this all the way back to an integer. */
10994 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
10995 gcc_assert (operand != NULL);
11001 if (mode == DImode)
11002 split_di (&operand, 1, &parts[0], &parts[1]);
11005 if (REG_P (operand))
11007 gcc_assert (reload_completed);
11008 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
11009 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
11011 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
11013 else if (offsettable_memref_p (operand))
11015 operand = adjust_address (operand, SImode, 0);
11016 parts[0] = operand;
11017 parts[1] = adjust_address (operand, SImode, 4);
11019 parts[2] = adjust_address (operand, SImode, 8);
11021 else if (GET_CODE (operand) == CONST_DOUBLE)
11026 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11030 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
11031 parts[2] = gen_int_mode (l[2], SImode);
11034 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
11037 gcc_unreachable ();
11039 parts[1] = gen_int_mode (l[1], SImode);
11040 parts[0] = gen_int_mode (l[0], SImode);
11043 gcc_unreachable ();
11048 if (mode == TImode)
11049 split_ti (&operand, 1, &parts[0], &parts[1]);
11050 if (mode == XFmode || mode == TFmode)
11052 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
11053 if (REG_P (operand))
11055 gcc_assert (reload_completed);
11056 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
11057 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
11059 else if (offsettable_memref_p (operand))
11061 operand = adjust_address (operand, DImode, 0);
11062 parts[0] = operand;
11063 parts[1] = adjust_address (operand, upper_mode, 8);
11065 else if (GET_CODE (operand) == CONST_DOUBLE)
11070 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
11071 real_to_target (l, &r, mode);
11073 /* Do not use shift by 32 to avoid warning on 32bit systems. */
11074 if (HOST_BITS_PER_WIDE_INT >= 64)
11077 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
11078 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
11081 parts[0] = immed_double_const (l[0], l[1], DImode);
11083 if (upper_mode == SImode)
11084 parts[1] = gen_int_mode (l[2], SImode);
11085 else if (HOST_BITS_PER_WIDE_INT >= 64)
11088 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
11089 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
11092 parts[1] = immed_double_const (l[2], l[3], DImode);
11095 gcc_unreachable ();
11102 /* Emit insns to perform a move or push of DI, DF, and XF values.
11103 Return false when normal moves are needed; true when all required
11104 insns have been emitted. Operands 2-4 contain the input values
11105 int the correct order; operands 5-7 contain the output values. */
11108 ix86_split_long_move (rtx operands[])
11113 int collisions = 0;
11114 enum machine_mode mode = GET_MODE (operands[0]);
11116 /* The DFmode expanders may ask us to move double.
11117 For 64bit target this is single move. By hiding the fact
11118 here we simplify i386.md splitters. */
11119 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
11121 /* Optimize constant pool reference to immediates. This is used by
11122 fp moves, that force all constants to memory to allow combining. */
11124 if (GET_CODE (operands[1]) == MEM
11125 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
11126 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
11127 operands[1] = get_pool_constant (XEXP (operands[1], 0));
11128 if (push_operand (operands[0], VOIDmode))
11130 operands[0] = copy_rtx (operands[0]);
11131 PUT_MODE (operands[0], Pmode);
11134 operands[0] = gen_lowpart (DImode, operands[0]);
11135 operands[1] = gen_lowpart (DImode, operands[1]);
11136 emit_move_insn (operands[0], operands[1]);
11140 /* The only non-offsettable memory we handle is push. */
11141 if (push_operand (operands[0], VOIDmode))
11144 gcc_assert (GET_CODE (operands[0]) != MEM
11145 || offsettable_memref_p (operands[0]));
11147 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
11148 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
11150 /* When emitting push, take care for source operands on the stack. */
11151 if (push && GET_CODE (operands[1]) == MEM
11152 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
11155 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
11156 XEXP (part[1][2], 0));
11157 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
11158 XEXP (part[1][1], 0));
11161 /* We need to do copy in the right order in case an address register
11162 of the source overlaps the destination. */
11163 if (REG_P (part[0][0]) && GET_CODE (part[1][0]) == MEM)
11165 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
11167 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11170 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
11173 /* Collision in the middle part can be handled by reordering. */
11174 if (collisions == 1 && nparts == 3
11175 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
11178 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
11179 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
11182 /* If there are more collisions, we can't handle it by reordering.
11183 Do an lea to the last part and use only one colliding move. */
11184 else if (collisions > 1)
11190 base = part[0][nparts - 1];
11192 /* Handle the case when the last part isn't valid for lea.
11193 Happens in 64-bit mode storing the 12-byte XFmode. */
11194 if (GET_MODE (base) != Pmode)
11195 base = gen_rtx_REG (Pmode, REGNO (base));
11197 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
11198 part[1][0] = replace_equiv_address (part[1][0], base);
11199 part[1][1] = replace_equiv_address (part[1][1],
11200 plus_constant (base, UNITS_PER_WORD));
11202 part[1][2] = replace_equiv_address (part[1][2],
11203 plus_constant (base, 8));
11213 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
11214 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
11215 emit_move_insn (part[0][2], part[1][2]);
11220 /* In 64bit mode we don't have 32bit push available. In case this is
11221 register, it is OK - we will just use larger counterpart. We also
11222 retype memory - these comes from attempt to avoid REX prefix on
11223 moving of second half of TFmode value. */
11224 if (GET_MODE (part[1][1]) == SImode)
11226 switch (GET_CODE (part[1][1]))
11229 part[1][1] = adjust_address (part[1][1], DImode, 0);
11233 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
11237 gcc_unreachable ();
11240 if (GET_MODE (part[1][0]) == SImode)
11241 part[1][0] = part[1][1];
11244 emit_move_insn (part[0][1], part[1][1]);
11245 emit_move_insn (part[0][0], part[1][0]);
11249 /* Choose correct order to not overwrite the source before it is copied. */
11250 if ((REG_P (part[0][0])
11251 && REG_P (part[1][1])
11252 && (REGNO (part[0][0]) == REGNO (part[1][1])
11254 && REGNO (part[0][0]) == REGNO (part[1][2]))))
11256 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
11260 operands[2] = part[0][2];
11261 operands[3] = part[0][1];
11262 operands[4] = part[0][0];
11263 operands[5] = part[1][2];
11264 operands[6] = part[1][1];
11265 operands[7] = part[1][0];
11269 operands[2] = part[0][1];
11270 operands[3] = part[0][0];
11271 operands[5] = part[1][1];
11272 operands[6] = part[1][0];
11279 operands[2] = part[0][0];
11280 operands[3] = part[0][1];
11281 operands[4] = part[0][2];
11282 operands[5] = part[1][0];
11283 operands[6] = part[1][1];
11284 operands[7] = part[1][2];
11288 operands[2] = part[0][0];
11289 operands[3] = part[0][1];
11290 operands[5] = part[1][0];
11291 operands[6] = part[1][1];
11295 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
11298 if (GET_CODE (operands[5]) == CONST_INT
11299 && operands[5] != const0_rtx
11300 && REG_P (operands[2]))
11302 if (GET_CODE (operands[6]) == CONST_INT
11303 && INTVAL (operands[6]) == INTVAL (operands[5]))
11304 operands[6] = operands[2];
11307 && GET_CODE (operands[7]) == CONST_INT
11308 && INTVAL (operands[7]) == INTVAL (operands[5]))
11309 operands[7] = operands[2];
11313 && GET_CODE (operands[6]) == CONST_INT
11314 && operands[6] != const0_rtx
11315 && REG_P (operands[3])
11316 && GET_CODE (operands[7]) == CONST_INT
11317 && INTVAL (operands[7]) == INTVAL (operands[6]))
11318 operands[7] = operands[3];
11321 emit_move_insn (operands[2], operands[5]);
11322 emit_move_insn (operands[3], operands[6]);
11324 emit_move_insn (operands[4], operands[7]);
11329 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
11330 left shift by a constant, either using a single shift or
11331 a sequence of add instructions. */
11334 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
11338 emit_insn ((mode == DImode
11340 : gen_adddi3) (operand, operand, operand));
11342 else if (!optimize_size
11343 && count * ix86_cost->add <= ix86_cost->shift_const)
11346 for (i=0; i<count; i++)
11348 emit_insn ((mode == DImode
11350 : gen_adddi3) (operand, operand, operand));
11354 emit_insn ((mode == DImode
11356 : gen_ashldi3) (operand, operand, GEN_INT (count)));
11360 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
11362 rtx low[2], high[2];
11364 const int single_width = mode == DImode ? 32 : 64;
11366 if (GET_CODE (operands[2]) == CONST_INT)
11368 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11369 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11371 if (count >= single_width)
11373 emit_move_insn (high[0], low[1]);
11374 emit_move_insn (low[0], const0_rtx);
11376 if (count > single_width)
11377 ix86_expand_ashl_const (high[0], count - single_width, mode);
11381 if (!rtx_equal_p (operands[0], operands[1]))
11382 emit_move_insn (operands[0], operands[1]);
11383 emit_insn ((mode == DImode
11385 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
11386 ix86_expand_ashl_const (low[0], count, mode);
11391 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11393 if (operands[1] == const1_rtx)
11395 /* Assuming we've chosen a QImode capable registers, then 1 << N
11396 can be done with two 32/64-bit shifts, no branches, no cmoves. */
11397 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
11399 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
11401 ix86_expand_clear (low[0]);
11402 ix86_expand_clear (high[0]);
11403 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
11405 d = gen_lowpart (QImode, low[0]);
11406 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
11407 s = gen_rtx_EQ (QImode, flags, const0_rtx);
11408 emit_insn (gen_rtx_SET (VOIDmode, d, s));
11410 d = gen_lowpart (QImode, high[0]);
11411 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
11412 s = gen_rtx_NE (QImode, flags, const0_rtx);
11413 emit_insn (gen_rtx_SET (VOIDmode, d, s));
11416 /* Otherwise, we can get the same results by manually performing
11417 a bit extract operation on bit 5/6, and then performing the two
11418 shifts. The two methods of getting 0/1 into low/high are exactly
11419 the same size. Avoiding the shift in the bit extract case helps
11420 pentium4 a bit; no one else seems to care much either way. */
11425 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
11426 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
11428 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
11429 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
11431 emit_insn ((mode == DImode
11433 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
11434 emit_insn ((mode == DImode
11436 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
11437 emit_move_insn (low[0], high[0]);
11438 emit_insn ((mode == DImode
11440 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
11443 emit_insn ((mode == DImode
11445 : gen_ashldi3) (low[0], low[0], operands[2]));
11446 emit_insn ((mode == DImode
11448 : gen_ashldi3) (high[0], high[0], operands[2]));
11452 if (operands[1] == constm1_rtx)
11454 /* For -1 << N, we can avoid the shld instruction, because we
11455 know that we're shifting 0...31/63 ones into a -1. */
11456 emit_move_insn (low[0], constm1_rtx);
11458 emit_move_insn (high[0], low[0]);
11460 emit_move_insn (high[0], constm1_rtx);
11464 if (!rtx_equal_p (operands[0], operands[1]))
11465 emit_move_insn (operands[0], operands[1]);
11467 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11468 emit_insn ((mode == DImode
11470 : gen_x86_64_shld) (high[0], low[0], operands[2]));
11473 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
11475 if (TARGET_CMOVE && scratch)
11477 ix86_expand_clear (scratch);
11478 emit_insn ((mode == DImode
11479 ? gen_x86_shift_adj_1
11480 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
11483 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
11487 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
11489 rtx low[2], high[2];
11491 const int single_width = mode == DImode ? 32 : 64;
11493 if (GET_CODE (operands[2]) == CONST_INT)
11495 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11496 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11498 if (count == single_width * 2 - 1)
11500 emit_move_insn (high[0], high[1]);
11501 emit_insn ((mode == DImode
11503 : gen_ashrdi3) (high[0], high[0],
11504 GEN_INT (single_width - 1)));
11505 emit_move_insn (low[0], high[0]);
11508 else if (count >= single_width)
11510 emit_move_insn (low[0], high[1]);
11511 emit_move_insn (high[0], low[0]);
11512 emit_insn ((mode == DImode
11514 : gen_ashrdi3) (high[0], high[0],
11515 GEN_INT (single_width - 1)));
11516 if (count > single_width)
11517 emit_insn ((mode == DImode
11519 : gen_ashrdi3) (low[0], low[0],
11520 GEN_INT (count - single_width)));
11524 if (!rtx_equal_p (operands[0], operands[1]))
11525 emit_move_insn (operands[0], operands[1]);
11526 emit_insn ((mode == DImode
11528 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
11529 emit_insn ((mode == DImode
11531 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
11536 if (!rtx_equal_p (operands[0], operands[1]))
11537 emit_move_insn (operands[0], operands[1]);
11539 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11541 emit_insn ((mode == DImode
11543 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
11544 emit_insn ((mode == DImode
11546 : gen_ashrdi3) (high[0], high[0], operands[2]));
11548 if (TARGET_CMOVE && scratch)
11550 emit_move_insn (scratch, high[0]);
11551 emit_insn ((mode == DImode
11553 : gen_ashrdi3) (scratch, scratch,
11554 GEN_INT (single_width - 1)));
11555 emit_insn ((mode == DImode
11556 ? gen_x86_shift_adj_1
11557 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
11561 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
11566 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
11568 rtx low[2], high[2];
11570 const int single_width = mode == DImode ? 32 : 64;
11572 if (GET_CODE (operands[2]) == CONST_INT)
11574 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
11575 count = INTVAL (operands[2]) & (single_width * 2 - 1);
11577 if (count >= single_width)
11579 emit_move_insn (low[0], high[1]);
11580 ix86_expand_clear (high[0]);
11582 if (count > single_width)
11583 emit_insn ((mode == DImode
11585 : gen_lshrdi3) (low[0], low[0],
11586 GEN_INT (count - single_width)));
11590 if (!rtx_equal_p (operands[0], operands[1]))
11591 emit_move_insn (operands[0], operands[1]);
11592 emit_insn ((mode == DImode
11594 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
11595 emit_insn ((mode == DImode
11597 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
11602 if (!rtx_equal_p (operands[0], operands[1]))
11603 emit_move_insn (operands[0], operands[1]);
11605 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
11607 emit_insn ((mode == DImode
11609 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
11610 emit_insn ((mode == DImode
11612 : gen_lshrdi3) (high[0], high[0], operands[2]));
11614 /* Heh. By reversing the arguments, we can reuse this pattern. */
11615 if (TARGET_CMOVE && scratch)
11617 ix86_expand_clear (scratch);
11618 emit_insn ((mode == DImode
11619 ? gen_x86_shift_adj_1
11620 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
11624 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
11628 /* Helper function for the string operations below. Dest VARIABLE whether
11629 it is aligned to VALUE bytes. If true, jump to the label. */
11631 ix86_expand_aligntest (rtx variable, int value)
11633 rtx label = gen_label_rtx ();
11634 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
11635 if (GET_MODE (variable) == DImode)
11636 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
11638 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
11639 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
11644 /* Adjust COUNTER by the VALUE. */
11646 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
11648 if (GET_MODE (countreg) == DImode)
11649 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
11651 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
11654 /* Zero extend possibly SImode EXP to Pmode register. */
11656 ix86_zero_extend_to_Pmode (rtx exp)
11659 if (GET_MODE (exp) == VOIDmode)
11660 return force_reg (Pmode, exp);
11661 if (GET_MODE (exp) == Pmode)
11662 return copy_to_mode_reg (Pmode, exp);
11663 r = gen_reg_rtx (Pmode);
11664 emit_insn (gen_zero_extendsidi2 (r, exp));
11668 /* Expand string move (memcpy) operation. Use i386 string operations when
11669 profitable. expand_clrmem contains similar code. */
11671 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
11673 rtx srcreg, destreg, countreg, srcexp, destexp;
11674 enum machine_mode counter_mode;
11675 HOST_WIDE_INT align = 0;
11676 unsigned HOST_WIDE_INT count = 0;
11678 if (GET_CODE (align_exp) == CONST_INT)
11679 align = INTVAL (align_exp);
11681 /* Can't use any of this if the user has appropriated esi or edi. */
11682 if (global_regs[4] || global_regs[5])
11685 /* This simple hack avoids all inlining code and simplifies code below. */
11686 if (!TARGET_ALIGN_STRINGOPS)
11689 if (GET_CODE (count_exp) == CONST_INT)
11691 count = INTVAL (count_exp);
11692 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
11696 /* Figure out proper mode for counter. For 32bits it is always SImode,
11697 for 64bits use SImode when possible, otherwise DImode.
11698 Set count to number of bytes copied when known at compile time. */
11700 || GET_MODE (count_exp) == SImode
11701 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
11702 counter_mode = SImode;
11704 counter_mode = DImode;
11706 gcc_assert (counter_mode == SImode || counter_mode == DImode);
11708 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
11709 if (destreg != XEXP (dst, 0))
11710 dst = replace_equiv_address_nv (dst, destreg);
11711 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
11712 if (srcreg != XEXP (src, 0))
11713 src = replace_equiv_address_nv (src, srcreg);
11715 /* When optimizing for size emit simple rep ; movsb instruction for
11716 counts not divisible by 4, except when (movsl;)*(movsw;)?(movsb;)?
11717 sequence is shorter than mov{b,l} $count, %{ecx,cl}; rep; movsb.
11718 Sice of (movsl;)*(movsw;)?(movsb;)? sequence is
11719 count / 4 + (count & 3), the other sequence is either 4 or 7 bytes,
11720 but we don't know whether upper 24 (resp. 56) bits of %ecx will be
11721 known to be zero or not. The rep; movsb sequence causes higher
11722 register pressure though, so take that into account. */
11724 if ((!optimize || optimize_size)
11729 || (count & 3) + count / 4 > 6))))
11731 emit_insn (gen_cld ());
11732 countreg = ix86_zero_extend_to_Pmode (count_exp);
11733 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
11734 srcexp = gen_rtx_PLUS (Pmode, srcreg, countreg);
11735 emit_insn (gen_rep_mov (destreg, dst, srcreg, src, countreg,
11739 /* For constant aligned (or small unaligned) copies use rep movsl
11740 followed by code copying the rest. For PentiumPro ensure 8 byte
11741 alignment to allow rep movsl acceleration. */
11743 else if (count != 0
11745 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
11746 || optimize_size || count < (unsigned int) 64))
11748 unsigned HOST_WIDE_INT offset = 0;
11749 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
11750 rtx srcmem, dstmem;
11752 emit_insn (gen_cld ());
11753 if (count & ~(size - 1))
11755 if ((TARGET_SINGLE_STRINGOP || optimize_size) && count < 5 * 4)
11757 enum machine_mode movs_mode = size == 4 ? SImode : DImode;
11759 while (offset < (count & ~(size - 1)))
11761 srcmem = adjust_automodify_address_nv (src, movs_mode,
11763 dstmem = adjust_automodify_address_nv (dst, movs_mode,
11765 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11771 countreg = GEN_INT ((count >> (size == 4 ? 2 : 3))
11772 & (TARGET_64BIT ? -1 : 0x3fffffff));
11773 countreg = copy_to_mode_reg (counter_mode, countreg);
11774 countreg = ix86_zero_extend_to_Pmode (countreg);
11776 destexp = gen_rtx_ASHIFT (Pmode, countreg,
11777 GEN_INT (size == 4 ? 2 : 3));
11778 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
11779 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
11781 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
11782 countreg, destexp, srcexp));
11783 offset = count & ~(size - 1);
11786 if (size == 8 && (count & 0x04))
11788 srcmem = adjust_automodify_address_nv (src, SImode, srcreg,
11790 dstmem = adjust_automodify_address_nv (dst, SImode, destreg,
11792 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11797 srcmem = adjust_automodify_address_nv (src, HImode, srcreg,
11799 dstmem = adjust_automodify_address_nv (dst, HImode, destreg,
11801 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11806 srcmem = adjust_automodify_address_nv (src, QImode, srcreg,
11808 dstmem = adjust_automodify_address_nv (dst, QImode, destreg,
11810 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11813 /* The generic code based on the glibc implementation:
11814 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
11815 allowing accelerated copying there)
11816 - copy the data using rep movsl
11817 - copy the rest. */
11822 rtx srcmem, dstmem;
11823 int desired_alignment = (TARGET_PENTIUMPRO
11824 && (count == 0 || count >= (unsigned int) 260)
11825 ? 8 : UNITS_PER_WORD);
11826 /* Get rid of MEM_OFFSETs, they won't be accurate. */
11827 dst = change_address (dst, BLKmode, destreg);
11828 src = change_address (src, BLKmode, srcreg);
11830 /* In case we don't know anything about the alignment, default to
11831 library version, since it is usually equally fast and result in
11834 Also emit call when we know that the count is large and call overhead
11835 will not be important. */
11836 if (!TARGET_INLINE_ALL_STRINGOPS
11837 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
11840 if (TARGET_SINGLE_STRINGOP)
11841 emit_insn (gen_cld ());
11843 countreg2 = gen_reg_rtx (Pmode);
11844 countreg = copy_to_mode_reg (counter_mode, count_exp);
11846 /* We don't use loops to align destination and to copy parts smaller
11847 than 4 bytes, because gcc is able to optimize such code better (in
11848 the case the destination or the count really is aligned, gcc is often
11849 able to predict the branches) and also it is friendlier to the
11850 hardware branch prediction.
11852 Using loops is beneficial for generic case, because we can
11853 handle small counts using the loops. Many CPUs (such as Athlon)
11854 have large REP prefix setup costs.
11856 This is quite costly. Maybe we can revisit this decision later or
11857 add some customizability to this code. */
11859 if (count == 0 && align < desired_alignment)
11861 label = gen_label_rtx ();
11862 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
11863 LEU, 0, counter_mode, 1, label);
11867 rtx label = ix86_expand_aligntest (destreg, 1);
11868 srcmem = change_address (src, QImode, srcreg);
11869 dstmem = change_address (dst, QImode, destreg);
11870 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11871 ix86_adjust_counter (countreg, 1);
11872 emit_label (label);
11873 LABEL_NUSES (label) = 1;
11877 rtx label = ix86_expand_aligntest (destreg, 2);
11878 srcmem = change_address (src, HImode, srcreg);
11879 dstmem = change_address (dst, HImode, destreg);
11880 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11881 ix86_adjust_counter (countreg, 2);
11882 emit_label (label);
11883 LABEL_NUSES (label) = 1;
11885 if (align <= 4 && desired_alignment > 4)
11887 rtx label = ix86_expand_aligntest (destreg, 4);
11888 srcmem = change_address (src, SImode, srcreg);
11889 dstmem = change_address (dst, SImode, destreg);
11890 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11891 ix86_adjust_counter (countreg, 4);
11892 emit_label (label);
11893 LABEL_NUSES (label) = 1;
11896 if (label && desired_alignment > 4 && !TARGET_64BIT)
11898 emit_label (label);
11899 LABEL_NUSES (label) = 1;
11902 if (!TARGET_SINGLE_STRINGOP)
11903 emit_insn (gen_cld ());
11906 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
11908 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
11912 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
11913 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
11915 srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg);
11916 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
11917 emit_insn (gen_rep_mov (destreg, dst, srcreg, src,
11918 countreg2, destexp, srcexp));
11922 emit_label (label);
11923 LABEL_NUSES (label) = 1;
11925 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
11927 srcmem = change_address (src, SImode, srcreg);
11928 dstmem = change_address (dst, SImode, destreg);
11929 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11931 if ((align <= 4 || count == 0) && TARGET_64BIT)
11933 rtx label = ix86_expand_aligntest (countreg, 4);
11934 srcmem = change_address (src, SImode, srcreg);
11935 dstmem = change_address (dst, SImode, destreg);
11936 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11937 emit_label (label);
11938 LABEL_NUSES (label) = 1;
11940 if (align > 2 && count != 0 && (count & 2))
11942 srcmem = change_address (src, HImode, srcreg);
11943 dstmem = change_address (dst, HImode, destreg);
11944 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11946 if (align <= 2 || count == 0)
11948 rtx label = ix86_expand_aligntest (countreg, 2);
11949 srcmem = change_address (src, HImode, srcreg);
11950 dstmem = change_address (dst, HImode, destreg);
11951 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11952 emit_label (label);
11953 LABEL_NUSES (label) = 1;
11955 if (align > 1 && count != 0 && (count & 1))
11957 srcmem = change_address (src, QImode, srcreg);
11958 dstmem = change_address (dst, QImode, destreg);
11959 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11961 if (align <= 1 || count == 0)
11963 rtx label = ix86_expand_aligntest (countreg, 1);
11964 srcmem = change_address (src, QImode, srcreg);
11965 dstmem = change_address (dst, QImode, destreg);
11966 emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem));
11967 emit_label (label);
11968 LABEL_NUSES (label) = 1;
11975 /* Expand string clear operation (bzero). Use i386 string operations when
11976 profitable. expand_movmem contains similar code. */
11978 ix86_expand_clrmem (rtx dst, rtx count_exp, rtx align_exp)
11980 rtx destreg, zeroreg, countreg, destexp;
11981 enum machine_mode counter_mode;
11982 HOST_WIDE_INT align = 0;
11983 unsigned HOST_WIDE_INT count = 0;
11985 if (GET_CODE (align_exp) == CONST_INT)
11986 align = INTVAL (align_exp);
11988 /* Can't use any of this if the user has appropriated esi. */
11989 if (global_regs[4])
11992 /* This simple hack avoids all inlining code and simplifies code below. */
11993 if (!TARGET_ALIGN_STRINGOPS)
11996 if (GET_CODE (count_exp) == CONST_INT)
11998 count = INTVAL (count_exp);
11999 if (!TARGET_INLINE_ALL_STRINGOPS && count > 64)
12002 /* Figure out proper mode for counter. For 32bits it is always SImode,
12003 for 64bits use SImode when possible, otherwise DImode.
12004 Set count to number of bytes copied when known at compile time. */
12006 || GET_MODE (count_exp) == SImode
12007 || x86_64_zext_immediate_operand (count_exp, VOIDmode))
12008 counter_mode = SImode;
12010 counter_mode = DImode;
12012 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
12013 if (destreg != XEXP (dst, 0))
12014 dst = replace_equiv_address_nv (dst, destreg);
12017 /* When optimizing for size emit simple rep ; movsb instruction for
12018 counts not divisible by 4. The movl $N, %ecx; rep; stosb
12019 sequence is 7 bytes long, so if optimizing for size and count is
12020 small enough that some stosl, stosw and stosb instructions without
12021 rep are shorter, fall back into the next if. */
12023 if ((!optimize || optimize_size)
12026 && (!optimize_size || (count & 0x03) + (count >> 2) > 7))))
12028 emit_insn (gen_cld ());
12030 countreg = ix86_zero_extend_to_Pmode (count_exp);
12031 zeroreg = copy_to_mode_reg (QImode, const0_rtx);
12032 destexp = gen_rtx_PLUS (Pmode, destreg, countreg);
12033 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg, destexp));
12035 else if (count != 0
12037 || (!TARGET_PENTIUMPRO && !TARGET_64BIT && align >= 4)
12038 || optimize_size || count < (unsigned int) 64))
12040 int size = TARGET_64BIT && !optimize_size ? 8 : 4;
12041 unsigned HOST_WIDE_INT offset = 0;
12043 emit_insn (gen_cld ());
12045 zeroreg = copy_to_mode_reg (size == 4 ? SImode : DImode, const0_rtx);
12046 if (count & ~(size - 1))
12048 unsigned HOST_WIDE_INT repcount;
12049 unsigned int max_nonrep;
12051 repcount = count >> (size == 4 ? 2 : 3);
12053 repcount &= 0x3fffffff;
12055 /* movl $N, %ecx; rep; stosl is 7 bytes, while N x stosl is N bytes.
12056 movl $N, %ecx; rep; stosq is 8 bytes, while N x stosq is 2xN
12057 bytes. In both cases the latter seems to be faster for small
12059 max_nonrep = size == 4 ? 7 : 4;
12060 if (!optimize_size)
12063 case PROCESSOR_PENTIUM4:
12064 case PROCESSOR_NOCONA:
12071 if (repcount <= max_nonrep)
12072 while (repcount-- > 0)
12074 rtx mem = adjust_automodify_address_nv (dst,
12075 GET_MODE (zeroreg),
12077 emit_insn (gen_strset (destreg, mem, zeroreg));
12082 countreg = copy_to_mode_reg (counter_mode, GEN_INT (repcount));
12083 countreg = ix86_zero_extend_to_Pmode (countreg);
12084 destexp = gen_rtx_ASHIFT (Pmode, countreg,
12085 GEN_INT (size == 4 ? 2 : 3));
12086 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12087 emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg,
12089 offset = count & ~(size - 1);
12092 if (size == 8 && (count & 0x04))
12094 rtx mem = adjust_automodify_address_nv (dst, SImode, destreg,
12096 emit_insn (gen_strset (destreg, mem,
12097 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12102 rtx mem = adjust_automodify_address_nv (dst, HImode, destreg,
12104 emit_insn (gen_strset (destreg, mem,
12105 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12110 rtx mem = adjust_automodify_address_nv (dst, QImode, destreg,
12112 emit_insn (gen_strset (destreg, mem,
12113 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12120 /* Compute desired alignment of the string operation. */
12121 int desired_alignment = (TARGET_PENTIUMPRO
12122 && (count == 0 || count >= (unsigned int) 260)
12123 ? 8 : UNITS_PER_WORD);
12125 /* In case we don't know anything about the alignment, default to
12126 library version, since it is usually equally fast and result in
12129 Also emit call when we know that the count is large and call overhead
12130 will not be important. */
12131 if (!TARGET_INLINE_ALL_STRINGOPS
12132 && (align < UNITS_PER_WORD || !TARGET_REP_MOVL_OPTIMAL))
12135 if (TARGET_SINGLE_STRINGOP)
12136 emit_insn (gen_cld ());
12138 countreg2 = gen_reg_rtx (Pmode);
12139 countreg = copy_to_mode_reg (counter_mode, count_exp);
12140 zeroreg = copy_to_mode_reg (Pmode, const0_rtx);
12141 /* Get rid of MEM_OFFSET, it won't be accurate. */
12142 dst = change_address (dst, BLKmode, destreg);
12144 if (count == 0 && align < desired_alignment)
12146 label = gen_label_rtx ();
12147 emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
12148 LEU, 0, counter_mode, 1, label);
12152 rtx label = ix86_expand_aligntest (destreg, 1);
12153 emit_insn (gen_strset (destreg, dst,
12154 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12155 ix86_adjust_counter (countreg, 1);
12156 emit_label (label);
12157 LABEL_NUSES (label) = 1;
12161 rtx label = ix86_expand_aligntest (destreg, 2);
12162 emit_insn (gen_strset (destreg, dst,
12163 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12164 ix86_adjust_counter (countreg, 2);
12165 emit_label (label);
12166 LABEL_NUSES (label) = 1;
12168 if (align <= 4 && desired_alignment > 4)
12170 rtx label = ix86_expand_aligntest (destreg, 4);
12171 emit_insn (gen_strset (destreg, dst,
12173 ? gen_rtx_SUBREG (SImode, zeroreg, 0)
12175 ix86_adjust_counter (countreg, 4);
12176 emit_label (label);
12177 LABEL_NUSES (label) = 1;
12180 if (label && desired_alignment > 4 && !TARGET_64BIT)
12182 emit_label (label);
12183 LABEL_NUSES (label) = 1;
12187 if (!TARGET_SINGLE_STRINGOP)
12188 emit_insn (gen_cld ());
12191 emit_insn (gen_lshrdi3 (countreg2, ix86_zero_extend_to_Pmode (countreg),
12193 destexp = gen_rtx_ASHIFT (Pmode, countreg2, GEN_INT (3));
12197 emit_insn (gen_lshrsi3 (countreg2, countreg, const2_rtx));
12198 destexp = gen_rtx_ASHIFT (Pmode, countreg2, const2_rtx);
12200 destexp = gen_rtx_PLUS (Pmode, destexp, destreg);
12201 emit_insn (gen_rep_stos (destreg, countreg2, dst, zeroreg, destexp));
12205 emit_label (label);
12206 LABEL_NUSES (label) = 1;
12209 if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
12210 emit_insn (gen_strset (destreg, dst,
12211 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12212 if (TARGET_64BIT && (align <= 4 || count == 0))
12214 rtx label = ix86_expand_aligntest (countreg, 4);
12215 emit_insn (gen_strset (destreg, dst,
12216 gen_rtx_SUBREG (SImode, zeroreg, 0)));
12217 emit_label (label);
12218 LABEL_NUSES (label) = 1;
12220 if (align > 2 && count != 0 && (count & 2))
12221 emit_insn (gen_strset (destreg, dst,
12222 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12223 if (align <= 2 || count == 0)
12225 rtx label = ix86_expand_aligntest (countreg, 2);
12226 emit_insn (gen_strset (destreg, dst,
12227 gen_rtx_SUBREG (HImode, zeroreg, 0)));
12228 emit_label (label);
12229 LABEL_NUSES (label) = 1;
12231 if (align > 1 && count != 0 && (count & 1))
12232 emit_insn (gen_strset (destreg, dst,
12233 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12234 if (align <= 1 || count == 0)
12236 rtx label = ix86_expand_aligntest (countreg, 1);
12237 emit_insn (gen_strset (destreg, dst,
12238 gen_rtx_SUBREG (QImode, zeroreg, 0)));
12239 emit_label (label);
12240 LABEL_NUSES (label) = 1;
12246 /* Expand strlen. */
12248 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
12250 rtx addr, scratch1, scratch2, scratch3, scratch4;
12252 /* The generic case of strlen expander is long. Avoid it's
12253 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
12255 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12256 && !TARGET_INLINE_ALL_STRINGOPS
12258 && (GET_CODE (align) != CONST_INT || INTVAL (align) < 4))
12261 addr = force_reg (Pmode, XEXP (src, 0));
12262 scratch1 = gen_reg_rtx (Pmode);
12264 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
12267 /* Well it seems that some optimizer does not combine a call like
12268 foo(strlen(bar), strlen(bar));
12269 when the move and the subtraction is done here. It does calculate
12270 the length just once when these instructions are done inside of
12271 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
12272 often used and I use one fewer register for the lifetime of
12273 output_strlen_unroll() this is better. */
12275 emit_move_insn (out, addr);
12277 ix86_expand_strlensi_unroll_1 (out, src, align);
12279 /* strlensi_unroll_1 returns the address of the zero at the end of
12280 the string, like memchr(), so compute the length by subtracting
12281 the start address. */
12283 emit_insn (gen_subdi3 (out, out, addr));
12285 emit_insn (gen_subsi3 (out, out, addr));
12290 scratch2 = gen_reg_rtx (Pmode);
12291 scratch3 = gen_reg_rtx (Pmode);
12292 scratch4 = force_reg (Pmode, constm1_rtx);
12294 emit_move_insn (scratch3, addr);
12295 eoschar = force_reg (QImode, eoschar);
12297 emit_insn (gen_cld ());
12298 src = replace_equiv_address_nv (src, scratch3);
12300 /* If .md starts supporting :P, this can be done in .md. */
12301 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
12302 scratch4), UNSPEC_SCAS);
12303 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
12306 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
12307 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
12311 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
12312 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
12318 /* Expand the appropriate insns for doing strlen if not just doing
12321 out = result, initialized with the start address
12322 align_rtx = alignment of the address.
12323 scratch = scratch register, initialized with the startaddress when
12324 not aligned, otherwise undefined
12326 This is just the body. It needs the initializations mentioned above and
12327 some address computing at the end. These things are done in i386.md. */
12330 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
12334 rtx align_2_label = NULL_RTX;
12335 rtx align_3_label = NULL_RTX;
12336 rtx align_4_label = gen_label_rtx ();
12337 rtx end_0_label = gen_label_rtx ();
12339 rtx tmpreg = gen_reg_rtx (SImode);
12340 rtx scratch = gen_reg_rtx (SImode);
12344 if (GET_CODE (align_rtx) == CONST_INT)
12345 align = INTVAL (align_rtx);
12347 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
12349 /* Is there a known alignment and is it less than 4? */
12352 rtx scratch1 = gen_reg_rtx (Pmode);
12353 emit_move_insn (scratch1, out);
12354 /* Is there a known alignment and is it not 2? */
12357 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
12358 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
12360 /* Leave just the 3 lower bits. */
12361 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
12362 NULL_RTX, 0, OPTAB_WIDEN);
12364 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
12365 Pmode, 1, align_4_label);
12366 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
12367 Pmode, 1, align_2_label);
12368 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
12369 Pmode, 1, align_3_label);
12373 /* Since the alignment is 2, we have to check 2 or 0 bytes;
12374 check if is aligned to 4 - byte. */
12376 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
12377 NULL_RTX, 0, OPTAB_WIDEN);
12379 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
12380 Pmode, 1, align_4_label);
12383 mem = change_address (src, QImode, out);
12385 /* Now compare the bytes. */
12387 /* Compare the first n unaligned byte on a byte per byte basis. */
12388 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
12389 QImode, 1, end_0_label);
12391 /* Increment the address. */
12393 emit_insn (gen_adddi3 (out, out, const1_rtx));
12395 emit_insn (gen_addsi3 (out, out, const1_rtx));
12397 /* Not needed with an alignment of 2 */
12400 emit_label (align_2_label);
12402 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
12406 emit_insn (gen_adddi3 (out, out, const1_rtx));
12408 emit_insn (gen_addsi3 (out, out, const1_rtx));
12410 emit_label (align_3_label);
12413 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
12417 emit_insn (gen_adddi3 (out, out, const1_rtx));
12419 emit_insn (gen_addsi3 (out, out, const1_rtx));
12422 /* Generate loop to check 4 bytes at a time. It is not a good idea to
12423 align this loop. It gives only huge programs, but does not help to
12425 emit_label (align_4_label);
12427 mem = change_address (src, SImode, out);
12428 emit_move_insn (scratch, mem);
12430 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
12432 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
12434 /* This formula yields a nonzero result iff one of the bytes is zero.
12435 This saves three branches inside loop and many cycles. */
12437 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
12438 emit_insn (gen_one_cmplsi2 (scratch, scratch));
12439 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
12440 emit_insn (gen_andsi3 (tmpreg, tmpreg,
12441 gen_int_mode (0x80808080, SImode)));
12442 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
12447 rtx reg = gen_reg_rtx (SImode);
12448 rtx reg2 = gen_reg_rtx (Pmode);
12449 emit_move_insn (reg, tmpreg);
12450 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
12452 /* If zero is not in the first two bytes, move two bytes forward. */
12453 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
12454 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12455 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
12456 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
12457 gen_rtx_IF_THEN_ELSE (SImode, tmp,
12460 /* Emit lea manually to avoid clobbering of flags. */
12461 emit_insn (gen_rtx_SET (SImode, reg2,
12462 gen_rtx_PLUS (Pmode, out, const2_rtx)));
12464 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12465 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
12466 emit_insn (gen_rtx_SET (VOIDmode, out,
12467 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
12474 rtx end_2_label = gen_label_rtx ();
12475 /* Is zero in the first two bytes? */
12477 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
12478 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
12479 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
12480 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12481 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
12483 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12484 JUMP_LABEL (tmp) = end_2_label;
12486 /* Not in the first two. Move two bytes forward. */
12487 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
12489 emit_insn (gen_adddi3 (out, out, const2_rtx));
12491 emit_insn (gen_addsi3 (out, out, const2_rtx));
12493 emit_label (end_2_label);
12497 /* Avoid branch in fixing the byte. */
12498 tmpreg = gen_lowpart (QImode, tmpreg);
12499 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
12500 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, 17), const0_rtx);
12502 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
12504 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
12506 emit_label (end_0_label);
12510 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
12511 rtx callarg2 ATTRIBUTE_UNUSED,
12512 rtx pop, int sibcall)
12514 rtx use = NULL, call;
12516 if (pop == const0_rtx)
12518 gcc_assert (!TARGET_64BIT || !pop);
12521 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
12522 fnaddr = machopic_indirect_call_target (fnaddr);
12524 /* Static functions and indirect calls don't need the pic register. */
12525 if (! TARGET_64BIT && flag_pic
12526 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
12527 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
12528 use_reg (&use, pic_offset_table_rtx);
12530 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
12532 rtx al = gen_rtx_REG (QImode, 0);
12533 emit_move_insn (al, callarg2);
12534 use_reg (&use, al);
12536 #endif /* TARGET_MACHO */
12538 if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
12540 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
12541 fnaddr = gen_rtx_MEM (QImode, fnaddr);
12543 if (sibcall && TARGET_64BIT
12544 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
12547 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
12548 fnaddr = gen_rtx_REG (Pmode, FIRST_REX_INT_REG + 3 /* R11 */);
12549 emit_move_insn (fnaddr, addr);
12550 fnaddr = gen_rtx_MEM (QImode, fnaddr);
12553 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
12555 call = gen_rtx_SET (VOIDmode, retval, call);
12558 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
12559 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
12560 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
12563 call = emit_call_insn (call);
12565 CALL_INSN_FUNCTION_USAGE (call) = use;
12569 /* Clear stack slot assignments remembered from previous functions.
12570 This is called from INIT_EXPANDERS once before RTL is emitted for each
12573 static struct machine_function *
12574 ix86_init_machine_status (void)
12576 struct machine_function *f;
12578 f = ggc_alloc_cleared (sizeof (struct machine_function));
12579 f->use_fast_prologue_epilogue_nregs = -1;
12584 /* Return a MEM corresponding to a stack slot with mode MODE.
12585 Allocate a new slot if necessary.
12587 The RTL for a function can have several slots available: N is
12588 which slot to use. */
12591 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
12593 struct stack_local_entry *s;
12595 gcc_assert (n < MAX_386_STACK_LOCALS);
12597 for (s = ix86_stack_locals; s; s = s->next)
12598 if (s->mode == mode && s->n == n)
12601 s = (struct stack_local_entry *)
12602 ggc_alloc (sizeof (struct stack_local_entry));
12605 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
12607 s->next = ix86_stack_locals;
12608 ix86_stack_locals = s;
12612 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12614 static GTY(()) rtx ix86_tls_symbol;
12616 ix86_tls_get_addr (void)
12619 if (!ix86_tls_symbol)
12621 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
12622 (TARGET_GNU_TLS && !TARGET_64BIT)
12623 ? "___tls_get_addr"
12624 : "__tls_get_addr");
12627 return ix86_tls_symbol;
12630 /* Calculate the length of the memory address in the instruction
12631 encoding. Does not include the one-byte modrm, opcode, or prefix. */
12634 memory_address_length (rtx addr)
12636 struct ix86_address parts;
12637 rtx base, index, disp;
12641 if (GET_CODE (addr) == PRE_DEC
12642 || GET_CODE (addr) == POST_INC
12643 || GET_CODE (addr) == PRE_MODIFY
12644 || GET_CODE (addr) == POST_MODIFY)
12647 ok = ix86_decompose_address (addr, &parts);
12650 if (parts.base && GET_CODE (parts.base) == SUBREG)
12651 parts.base = SUBREG_REG (parts.base);
12652 if (parts.index && GET_CODE (parts.index) == SUBREG)
12653 parts.index = SUBREG_REG (parts.index);
12656 index = parts.index;
12661 - esp as the base always wants an index,
12662 - ebp as the base always wants a displacement. */
12664 /* Register Indirect. */
12665 if (base && !index && !disp)
12667 /* esp (for its index) and ebp (for its displacement) need
12668 the two-byte modrm form. */
12669 if (addr == stack_pointer_rtx
12670 || addr == arg_pointer_rtx
12671 || addr == frame_pointer_rtx
12672 || addr == hard_frame_pointer_rtx)
12676 /* Direct Addressing. */
12677 else if (disp && !base && !index)
12682 /* Find the length of the displacement constant. */
12685 if (GET_CODE (disp) == CONST_INT
12686 && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K')
12692 /* ebp always wants a displacement. */
12693 else if (base == hard_frame_pointer_rtx)
12696 /* An index requires the two-byte modrm form.... */
12698 /* ...like esp, which always wants an index. */
12699 || base == stack_pointer_rtx
12700 || base == arg_pointer_rtx
12701 || base == frame_pointer_rtx)
12708 /* Compute default value for "length_immediate" attribute. When SHORTFORM
12709 is set, expect that insn have 8bit immediate alternative. */
12711 ix86_attr_length_immediate_default (rtx insn, int shortform)
12715 extract_insn_cached (insn);
12716 for (i = recog_data.n_operands - 1; i >= 0; --i)
12717 if (CONSTANT_P (recog_data.operand[i]))
12721 && GET_CODE (recog_data.operand[i]) == CONST_INT
12722 && CONST_OK_FOR_LETTER_P (INTVAL (recog_data.operand[i]), 'K'))
12726 switch (get_attr_mode (insn))
12737 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
12742 fatal_insn ("unknown insn mode", insn);
12748 /* Compute default value for "length_address" attribute. */
12750 ix86_attr_length_address_default (rtx insn)
12754 if (get_attr_type (insn) == TYPE_LEA)
12756 rtx set = PATTERN (insn);
12758 if (GET_CODE (set) == PARALLEL)
12759 set = XVECEXP (set, 0, 0);
12761 gcc_assert (GET_CODE (set) == SET);
12763 return memory_address_length (SET_SRC (set));
12766 extract_insn_cached (insn);
12767 for (i = recog_data.n_operands - 1; i >= 0; --i)
12768 if (GET_CODE (recog_data.operand[i]) == MEM)
12770 return memory_address_length (XEXP (recog_data.operand[i], 0));
12776 /* Return the maximum number of instructions a cpu can issue. */
12779 ix86_issue_rate (void)
12783 case PROCESSOR_PENTIUM:
12787 case PROCESSOR_PENTIUMPRO:
12788 case PROCESSOR_PENTIUM4:
12789 case PROCESSOR_ATHLON:
12791 case PROCESSOR_NOCONA:
12799 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
12800 by DEP_INSN and nothing set by DEP_INSN. */
12803 ix86_flags_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type)
12807 /* Simplify the test for uninteresting insns. */
12808 if (insn_type != TYPE_SETCC
12809 && insn_type != TYPE_ICMOV
12810 && insn_type != TYPE_FCMOV
12811 && insn_type != TYPE_IBR)
12814 if ((set = single_set (dep_insn)) != 0)
12816 set = SET_DEST (set);
12819 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
12820 && XVECLEN (PATTERN (dep_insn), 0) == 2
12821 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
12822 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
12824 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
12825 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
12830 if (GET_CODE (set) != REG || REGNO (set) != FLAGS_REG)
12833 /* This test is true if the dependent insn reads the flags but
12834 not any other potentially set register. */
12835 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
12838 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
12844 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
12845 address with operands set by DEP_INSN. */
12848 ix86_agi_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type)
12852 if (insn_type == TYPE_LEA
12855 addr = PATTERN (insn);
12857 if (GET_CODE (addr) == PARALLEL)
12858 addr = XVECEXP (addr, 0, 0);
12860 gcc_assert (GET_CODE (addr) == SET);
12862 addr = SET_SRC (addr);
12867 extract_insn_cached (insn);
12868 for (i = recog_data.n_operands - 1; i >= 0; --i)
12869 if (GET_CODE (recog_data.operand[i]) == MEM)
12871 addr = XEXP (recog_data.operand[i], 0);
12878 return modified_in_p (addr, dep_insn);
12882 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
12884 enum attr_type insn_type, dep_insn_type;
12885 enum attr_memory memory;
12887 int dep_insn_code_number;
12889 /* Anti and output dependencies have zero cost on all CPUs. */
12890 if (REG_NOTE_KIND (link) != 0)
12893 dep_insn_code_number = recog_memoized (dep_insn);
12895 /* If we can't recognize the insns, we can't really do anything. */
12896 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
12899 insn_type = get_attr_type (insn);
12900 dep_insn_type = get_attr_type (dep_insn);
12904 case PROCESSOR_PENTIUM:
12905 /* Address Generation Interlock adds a cycle of latency. */
12906 if (ix86_agi_dependant (insn, dep_insn, insn_type))
12909 /* ??? Compares pair with jump/setcc. */
12910 if (ix86_flags_dependant (insn, dep_insn, insn_type))
12913 /* Floating point stores require value to be ready one cycle earlier. */
12914 if (insn_type == TYPE_FMOV
12915 && get_attr_memory (insn) == MEMORY_STORE
12916 && !ix86_agi_dependant (insn, dep_insn, insn_type))
12920 case PROCESSOR_PENTIUMPRO:
12921 memory = get_attr_memory (insn);
12923 /* INT->FP conversion is expensive. */
12924 if (get_attr_fp_int_src (dep_insn))
12927 /* There is one cycle extra latency between an FP op and a store. */
12928 if (insn_type == TYPE_FMOV
12929 && (set = single_set (dep_insn)) != NULL_RTX
12930 && (set2 = single_set (insn)) != NULL_RTX
12931 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
12932 && GET_CODE (SET_DEST (set2)) == MEM)
12935 /* Show ability of reorder buffer to hide latency of load by executing
12936 in parallel with previous instruction in case
12937 previous instruction is not needed to compute the address. */
12938 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
12939 && !ix86_agi_dependant (insn, dep_insn, insn_type))
12941 /* Claim moves to take one cycle, as core can issue one load
12942 at time and the next load can start cycle later. */
12943 if (dep_insn_type == TYPE_IMOV
12944 || dep_insn_type == TYPE_FMOV)
12952 memory = get_attr_memory (insn);
12954 /* The esp dependency is resolved before the instruction is really
12956 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
12957 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
12960 /* INT->FP conversion is expensive. */
12961 if (get_attr_fp_int_src (dep_insn))
12964 /* Show ability of reorder buffer to hide latency of load by executing
12965 in parallel with previous instruction in case
12966 previous instruction is not needed to compute the address. */
12967 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
12968 && !ix86_agi_dependant (insn, dep_insn, insn_type))
12970 /* Claim moves to take one cycle, as core can issue one load
12971 at time and the next load can start cycle later. */
12972 if (dep_insn_type == TYPE_IMOV
12973 || dep_insn_type == TYPE_FMOV)
12982 case PROCESSOR_ATHLON:
12984 memory = get_attr_memory (insn);
12986 /* Show ability of reorder buffer to hide latency of load by executing
12987 in parallel with previous instruction in case
12988 previous instruction is not needed to compute the address. */
12989 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
12990 && !ix86_agi_dependant (insn, dep_insn, insn_type))
12992 enum attr_unit unit = get_attr_unit (insn);
12995 /* Because of the difference between the length of integer and
12996 floating unit pipeline preparation stages, the memory operands
12997 for floating point are cheaper.
12999 ??? For Athlon it the difference is most probably 2. */
13000 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
13003 loadcost = TARGET_ATHLON ? 2 : 0;
13005 if (cost >= loadcost)
13018 /* How many alternative schedules to try. This should be as wide as the
13019 scheduling freedom in the DFA, but no wider. Making this value too
13020 large results extra work for the scheduler. */
13023 ia32_multipass_dfa_lookahead (void)
13025 if (ix86_tune == PROCESSOR_PENTIUM)
13028 if (ix86_tune == PROCESSOR_PENTIUMPRO
13029 || ix86_tune == PROCESSOR_K6)
13037 /* Compute the alignment given to a constant that is being placed in memory.
13038 EXP is the constant and ALIGN is the alignment that the object would
13040 The value of this function is used instead of that alignment to align
13044 ix86_constant_alignment (tree exp, int align)
13046 if (TREE_CODE (exp) == REAL_CST)
13048 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
13050 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
13053 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
13054 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
13055 return BITS_PER_WORD;
13060 /* Compute the alignment for a static variable.
13061 TYPE is the data type, and ALIGN is the alignment that
13062 the object would ordinarily have. The value of this function is used
13063 instead of that alignment to align the object. */
13066 ix86_data_alignment (tree type, int align)
13068 if (AGGREGATE_TYPE_P (type)
13069 && TYPE_SIZE (type)
13070 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13071 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 256
13072 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 256)
13075 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13076 to 16byte boundary. */
13079 if (AGGREGATE_TYPE_P (type)
13080 && TYPE_SIZE (type)
13081 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13082 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
13083 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13087 if (TREE_CODE (type) == ARRAY_TYPE)
13089 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13091 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13094 else if (TREE_CODE (type) == COMPLEX_TYPE)
13097 if (TYPE_MODE (type) == DCmode && align < 64)
13099 if (TYPE_MODE (type) == XCmode && align < 128)
13102 else if ((TREE_CODE (type) == RECORD_TYPE
13103 || TREE_CODE (type) == UNION_TYPE
13104 || TREE_CODE (type) == QUAL_UNION_TYPE)
13105 && TYPE_FIELDS (type))
13107 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13109 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13112 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13113 || TREE_CODE (type) == INTEGER_TYPE)
13115 if (TYPE_MODE (type) == DFmode && align < 64)
13117 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13124 /* Compute the alignment for a local variable.
13125 TYPE is the data type, and ALIGN is the alignment that
13126 the object would ordinarily have. The value of this macro is used
13127 instead of that alignment to align the object. */
13130 ix86_local_alignment (tree type, int align)
13132 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
13133 to 16byte boundary. */
13136 if (AGGREGATE_TYPE_P (type)
13137 && TYPE_SIZE (type)
13138 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
13139 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
13140 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
13143 if (TREE_CODE (type) == ARRAY_TYPE)
13145 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
13147 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
13150 else if (TREE_CODE (type) == COMPLEX_TYPE)
13152 if (TYPE_MODE (type) == DCmode && align < 64)
13154 if (TYPE_MODE (type) == XCmode && align < 128)
13157 else if ((TREE_CODE (type) == RECORD_TYPE
13158 || TREE_CODE (type) == UNION_TYPE
13159 || TREE_CODE (type) == QUAL_UNION_TYPE)
13160 && TYPE_FIELDS (type))
13162 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
13164 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
13167 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
13168 || TREE_CODE (type) == INTEGER_TYPE)
13171 if (TYPE_MODE (type) == DFmode && align < 64)
13173 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
13179 /* Emit RTL insns to initialize the variable parts of a trampoline.
13180 FNADDR is an RTX for the address of the function's pure code.
13181 CXT is an RTX for the static chain value for the function. */
13183 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
13187 /* Compute offset from the end of the jmp to the target function. */
13188 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
13189 plus_constant (tramp, 10),
13190 NULL_RTX, 1, OPTAB_DIRECT);
13191 emit_move_insn (gen_rtx_MEM (QImode, tramp),
13192 gen_int_mode (0xb9, QImode));
13193 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
13194 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
13195 gen_int_mode (0xe9, QImode));
13196 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
13201 /* Try to load address using shorter movl instead of movabs.
13202 We may want to support movq for kernel mode, but kernel does not use
13203 trampolines at the moment. */
13204 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
13206 fnaddr = copy_to_mode_reg (DImode, fnaddr);
13207 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13208 gen_int_mode (0xbb41, HImode));
13209 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
13210 gen_lowpart (SImode, fnaddr));
13215 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13216 gen_int_mode (0xbb49, HImode));
13217 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13221 /* Load static chain using movabs to r10. */
13222 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13223 gen_int_mode (0xba49, HImode));
13224 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
13227 /* Jump to the r11 */
13228 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
13229 gen_int_mode (0xff49, HImode));
13230 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
13231 gen_int_mode (0xe3, QImode));
13233 gcc_assert (offset <= TRAMPOLINE_SIZE);
13236 #ifdef ENABLE_EXECUTE_STACK
13237 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
13238 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
13242 /* Codes for all the SSE/MMX builtins. */
13245 IX86_BUILTIN_ADDPS,
13246 IX86_BUILTIN_ADDSS,
13247 IX86_BUILTIN_DIVPS,
13248 IX86_BUILTIN_DIVSS,
13249 IX86_BUILTIN_MULPS,
13250 IX86_BUILTIN_MULSS,
13251 IX86_BUILTIN_SUBPS,
13252 IX86_BUILTIN_SUBSS,
13254 IX86_BUILTIN_CMPEQPS,
13255 IX86_BUILTIN_CMPLTPS,
13256 IX86_BUILTIN_CMPLEPS,
13257 IX86_BUILTIN_CMPGTPS,
13258 IX86_BUILTIN_CMPGEPS,
13259 IX86_BUILTIN_CMPNEQPS,
13260 IX86_BUILTIN_CMPNLTPS,
13261 IX86_BUILTIN_CMPNLEPS,
13262 IX86_BUILTIN_CMPNGTPS,
13263 IX86_BUILTIN_CMPNGEPS,
13264 IX86_BUILTIN_CMPORDPS,
13265 IX86_BUILTIN_CMPUNORDPS,
13266 IX86_BUILTIN_CMPNEPS,
13267 IX86_BUILTIN_CMPEQSS,
13268 IX86_BUILTIN_CMPLTSS,
13269 IX86_BUILTIN_CMPLESS,
13270 IX86_BUILTIN_CMPNEQSS,
13271 IX86_BUILTIN_CMPNLTSS,
13272 IX86_BUILTIN_CMPNLESS,
13273 IX86_BUILTIN_CMPNGTSS,
13274 IX86_BUILTIN_CMPNGESS,
13275 IX86_BUILTIN_CMPORDSS,
13276 IX86_BUILTIN_CMPUNORDSS,
13277 IX86_BUILTIN_CMPNESS,
13279 IX86_BUILTIN_COMIEQSS,
13280 IX86_BUILTIN_COMILTSS,
13281 IX86_BUILTIN_COMILESS,
13282 IX86_BUILTIN_COMIGTSS,
13283 IX86_BUILTIN_COMIGESS,
13284 IX86_BUILTIN_COMINEQSS,
13285 IX86_BUILTIN_UCOMIEQSS,
13286 IX86_BUILTIN_UCOMILTSS,
13287 IX86_BUILTIN_UCOMILESS,
13288 IX86_BUILTIN_UCOMIGTSS,
13289 IX86_BUILTIN_UCOMIGESS,
13290 IX86_BUILTIN_UCOMINEQSS,
13292 IX86_BUILTIN_CVTPI2PS,
13293 IX86_BUILTIN_CVTPS2PI,
13294 IX86_BUILTIN_CVTSI2SS,
13295 IX86_BUILTIN_CVTSI642SS,
13296 IX86_BUILTIN_CVTSS2SI,
13297 IX86_BUILTIN_CVTSS2SI64,
13298 IX86_BUILTIN_CVTTPS2PI,
13299 IX86_BUILTIN_CVTTSS2SI,
13300 IX86_BUILTIN_CVTTSS2SI64,
13302 IX86_BUILTIN_MAXPS,
13303 IX86_BUILTIN_MAXSS,
13304 IX86_BUILTIN_MINPS,
13305 IX86_BUILTIN_MINSS,
13307 IX86_BUILTIN_LOADUPS,
13308 IX86_BUILTIN_STOREUPS,
13309 IX86_BUILTIN_MOVSS,
13311 IX86_BUILTIN_MOVHLPS,
13312 IX86_BUILTIN_MOVLHPS,
13313 IX86_BUILTIN_LOADHPS,
13314 IX86_BUILTIN_LOADLPS,
13315 IX86_BUILTIN_STOREHPS,
13316 IX86_BUILTIN_STORELPS,
13318 IX86_BUILTIN_MASKMOVQ,
13319 IX86_BUILTIN_MOVMSKPS,
13320 IX86_BUILTIN_PMOVMSKB,
13322 IX86_BUILTIN_MOVNTPS,
13323 IX86_BUILTIN_MOVNTQ,
13325 IX86_BUILTIN_LOADDQU,
13326 IX86_BUILTIN_STOREDQU,
13328 IX86_BUILTIN_PACKSSWB,
13329 IX86_BUILTIN_PACKSSDW,
13330 IX86_BUILTIN_PACKUSWB,
13332 IX86_BUILTIN_PADDB,
13333 IX86_BUILTIN_PADDW,
13334 IX86_BUILTIN_PADDD,
13335 IX86_BUILTIN_PADDQ,
13336 IX86_BUILTIN_PADDSB,
13337 IX86_BUILTIN_PADDSW,
13338 IX86_BUILTIN_PADDUSB,
13339 IX86_BUILTIN_PADDUSW,
13340 IX86_BUILTIN_PSUBB,
13341 IX86_BUILTIN_PSUBW,
13342 IX86_BUILTIN_PSUBD,
13343 IX86_BUILTIN_PSUBQ,
13344 IX86_BUILTIN_PSUBSB,
13345 IX86_BUILTIN_PSUBSW,
13346 IX86_BUILTIN_PSUBUSB,
13347 IX86_BUILTIN_PSUBUSW,
13350 IX86_BUILTIN_PANDN,
13354 IX86_BUILTIN_PAVGB,
13355 IX86_BUILTIN_PAVGW,
13357 IX86_BUILTIN_PCMPEQB,
13358 IX86_BUILTIN_PCMPEQW,
13359 IX86_BUILTIN_PCMPEQD,
13360 IX86_BUILTIN_PCMPGTB,
13361 IX86_BUILTIN_PCMPGTW,
13362 IX86_BUILTIN_PCMPGTD,
13364 IX86_BUILTIN_PMADDWD,
13366 IX86_BUILTIN_PMAXSW,
13367 IX86_BUILTIN_PMAXUB,
13368 IX86_BUILTIN_PMINSW,
13369 IX86_BUILTIN_PMINUB,
13371 IX86_BUILTIN_PMULHUW,
13372 IX86_BUILTIN_PMULHW,
13373 IX86_BUILTIN_PMULLW,
13375 IX86_BUILTIN_PSADBW,
13376 IX86_BUILTIN_PSHUFW,
13378 IX86_BUILTIN_PSLLW,
13379 IX86_BUILTIN_PSLLD,
13380 IX86_BUILTIN_PSLLQ,
13381 IX86_BUILTIN_PSRAW,
13382 IX86_BUILTIN_PSRAD,
13383 IX86_BUILTIN_PSRLW,
13384 IX86_BUILTIN_PSRLD,
13385 IX86_BUILTIN_PSRLQ,
13386 IX86_BUILTIN_PSLLWI,
13387 IX86_BUILTIN_PSLLDI,
13388 IX86_BUILTIN_PSLLQI,
13389 IX86_BUILTIN_PSRAWI,
13390 IX86_BUILTIN_PSRADI,
13391 IX86_BUILTIN_PSRLWI,
13392 IX86_BUILTIN_PSRLDI,
13393 IX86_BUILTIN_PSRLQI,
13395 IX86_BUILTIN_PUNPCKHBW,
13396 IX86_BUILTIN_PUNPCKHWD,
13397 IX86_BUILTIN_PUNPCKHDQ,
13398 IX86_BUILTIN_PUNPCKLBW,
13399 IX86_BUILTIN_PUNPCKLWD,
13400 IX86_BUILTIN_PUNPCKLDQ,
13402 IX86_BUILTIN_SHUFPS,
13404 IX86_BUILTIN_RCPPS,
13405 IX86_BUILTIN_RCPSS,
13406 IX86_BUILTIN_RSQRTPS,
13407 IX86_BUILTIN_RSQRTSS,
13408 IX86_BUILTIN_SQRTPS,
13409 IX86_BUILTIN_SQRTSS,
13411 IX86_BUILTIN_UNPCKHPS,
13412 IX86_BUILTIN_UNPCKLPS,
13414 IX86_BUILTIN_ANDPS,
13415 IX86_BUILTIN_ANDNPS,
13417 IX86_BUILTIN_XORPS,
13420 IX86_BUILTIN_LDMXCSR,
13421 IX86_BUILTIN_STMXCSR,
13422 IX86_BUILTIN_SFENCE,
13424 /* 3DNow! Original */
13425 IX86_BUILTIN_FEMMS,
13426 IX86_BUILTIN_PAVGUSB,
13427 IX86_BUILTIN_PF2ID,
13428 IX86_BUILTIN_PFACC,
13429 IX86_BUILTIN_PFADD,
13430 IX86_BUILTIN_PFCMPEQ,
13431 IX86_BUILTIN_PFCMPGE,
13432 IX86_BUILTIN_PFCMPGT,
13433 IX86_BUILTIN_PFMAX,
13434 IX86_BUILTIN_PFMIN,
13435 IX86_BUILTIN_PFMUL,
13436 IX86_BUILTIN_PFRCP,
13437 IX86_BUILTIN_PFRCPIT1,
13438 IX86_BUILTIN_PFRCPIT2,
13439 IX86_BUILTIN_PFRSQIT1,
13440 IX86_BUILTIN_PFRSQRT,
13441 IX86_BUILTIN_PFSUB,
13442 IX86_BUILTIN_PFSUBR,
13443 IX86_BUILTIN_PI2FD,
13444 IX86_BUILTIN_PMULHRW,
13446 /* 3DNow! Athlon Extensions */
13447 IX86_BUILTIN_PF2IW,
13448 IX86_BUILTIN_PFNACC,
13449 IX86_BUILTIN_PFPNACC,
13450 IX86_BUILTIN_PI2FW,
13451 IX86_BUILTIN_PSWAPDSI,
13452 IX86_BUILTIN_PSWAPDSF,
13455 IX86_BUILTIN_ADDPD,
13456 IX86_BUILTIN_ADDSD,
13457 IX86_BUILTIN_DIVPD,
13458 IX86_BUILTIN_DIVSD,
13459 IX86_BUILTIN_MULPD,
13460 IX86_BUILTIN_MULSD,
13461 IX86_BUILTIN_SUBPD,
13462 IX86_BUILTIN_SUBSD,
13464 IX86_BUILTIN_CMPEQPD,
13465 IX86_BUILTIN_CMPLTPD,
13466 IX86_BUILTIN_CMPLEPD,
13467 IX86_BUILTIN_CMPGTPD,
13468 IX86_BUILTIN_CMPGEPD,
13469 IX86_BUILTIN_CMPNEQPD,
13470 IX86_BUILTIN_CMPNLTPD,
13471 IX86_BUILTIN_CMPNLEPD,
13472 IX86_BUILTIN_CMPNGTPD,
13473 IX86_BUILTIN_CMPNGEPD,
13474 IX86_BUILTIN_CMPORDPD,
13475 IX86_BUILTIN_CMPUNORDPD,
13476 IX86_BUILTIN_CMPNEPD,
13477 IX86_BUILTIN_CMPEQSD,
13478 IX86_BUILTIN_CMPLTSD,
13479 IX86_BUILTIN_CMPLESD,
13480 IX86_BUILTIN_CMPNEQSD,
13481 IX86_BUILTIN_CMPNLTSD,
13482 IX86_BUILTIN_CMPNLESD,
13483 IX86_BUILTIN_CMPORDSD,
13484 IX86_BUILTIN_CMPUNORDSD,
13485 IX86_BUILTIN_CMPNESD,
13487 IX86_BUILTIN_COMIEQSD,
13488 IX86_BUILTIN_COMILTSD,
13489 IX86_BUILTIN_COMILESD,
13490 IX86_BUILTIN_COMIGTSD,
13491 IX86_BUILTIN_COMIGESD,
13492 IX86_BUILTIN_COMINEQSD,
13493 IX86_BUILTIN_UCOMIEQSD,
13494 IX86_BUILTIN_UCOMILTSD,
13495 IX86_BUILTIN_UCOMILESD,
13496 IX86_BUILTIN_UCOMIGTSD,
13497 IX86_BUILTIN_UCOMIGESD,
13498 IX86_BUILTIN_UCOMINEQSD,
13500 IX86_BUILTIN_MAXPD,
13501 IX86_BUILTIN_MAXSD,
13502 IX86_BUILTIN_MINPD,
13503 IX86_BUILTIN_MINSD,
13505 IX86_BUILTIN_ANDPD,
13506 IX86_BUILTIN_ANDNPD,
13508 IX86_BUILTIN_XORPD,
13510 IX86_BUILTIN_SQRTPD,
13511 IX86_BUILTIN_SQRTSD,
13513 IX86_BUILTIN_UNPCKHPD,
13514 IX86_BUILTIN_UNPCKLPD,
13516 IX86_BUILTIN_SHUFPD,
13518 IX86_BUILTIN_LOADUPD,
13519 IX86_BUILTIN_STOREUPD,
13520 IX86_BUILTIN_MOVSD,
13522 IX86_BUILTIN_LOADHPD,
13523 IX86_BUILTIN_LOADLPD,
13525 IX86_BUILTIN_CVTDQ2PD,
13526 IX86_BUILTIN_CVTDQ2PS,
13528 IX86_BUILTIN_CVTPD2DQ,
13529 IX86_BUILTIN_CVTPD2PI,
13530 IX86_BUILTIN_CVTPD2PS,
13531 IX86_BUILTIN_CVTTPD2DQ,
13532 IX86_BUILTIN_CVTTPD2PI,
13534 IX86_BUILTIN_CVTPI2PD,
13535 IX86_BUILTIN_CVTSI2SD,
13536 IX86_BUILTIN_CVTSI642SD,
13538 IX86_BUILTIN_CVTSD2SI,
13539 IX86_BUILTIN_CVTSD2SI64,
13540 IX86_BUILTIN_CVTSD2SS,
13541 IX86_BUILTIN_CVTSS2SD,
13542 IX86_BUILTIN_CVTTSD2SI,
13543 IX86_BUILTIN_CVTTSD2SI64,
13545 IX86_BUILTIN_CVTPS2DQ,
13546 IX86_BUILTIN_CVTPS2PD,
13547 IX86_BUILTIN_CVTTPS2DQ,
13549 IX86_BUILTIN_MOVNTI,
13550 IX86_BUILTIN_MOVNTPD,
13551 IX86_BUILTIN_MOVNTDQ,
13554 IX86_BUILTIN_MASKMOVDQU,
13555 IX86_BUILTIN_MOVMSKPD,
13556 IX86_BUILTIN_PMOVMSKB128,
13558 IX86_BUILTIN_PACKSSWB128,
13559 IX86_BUILTIN_PACKSSDW128,
13560 IX86_BUILTIN_PACKUSWB128,
13562 IX86_BUILTIN_PADDB128,
13563 IX86_BUILTIN_PADDW128,
13564 IX86_BUILTIN_PADDD128,
13565 IX86_BUILTIN_PADDQ128,
13566 IX86_BUILTIN_PADDSB128,
13567 IX86_BUILTIN_PADDSW128,
13568 IX86_BUILTIN_PADDUSB128,
13569 IX86_BUILTIN_PADDUSW128,
13570 IX86_BUILTIN_PSUBB128,
13571 IX86_BUILTIN_PSUBW128,
13572 IX86_BUILTIN_PSUBD128,
13573 IX86_BUILTIN_PSUBQ128,
13574 IX86_BUILTIN_PSUBSB128,
13575 IX86_BUILTIN_PSUBSW128,
13576 IX86_BUILTIN_PSUBUSB128,
13577 IX86_BUILTIN_PSUBUSW128,
13579 IX86_BUILTIN_PAND128,
13580 IX86_BUILTIN_PANDN128,
13581 IX86_BUILTIN_POR128,
13582 IX86_BUILTIN_PXOR128,
13584 IX86_BUILTIN_PAVGB128,
13585 IX86_BUILTIN_PAVGW128,
13587 IX86_BUILTIN_PCMPEQB128,
13588 IX86_BUILTIN_PCMPEQW128,
13589 IX86_BUILTIN_PCMPEQD128,
13590 IX86_BUILTIN_PCMPGTB128,
13591 IX86_BUILTIN_PCMPGTW128,
13592 IX86_BUILTIN_PCMPGTD128,
13594 IX86_BUILTIN_PMADDWD128,
13596 IX86_BUILTIN_PMAXSW128,
13597 IX86_BUILTIN_PMAXUB128,
13598 IX86_BUILTIN_PMINSW128,
13599 IX86_BUILTIN_PMINUB128,
13601 IX86_BUILTIN_PMULUDQ,
13602 IX86_BUILTIN_PMULUDQ128,
13603 IX86_BUILTIN_PMULHUW128,
13604 IX86_BUILTIN_PMULHW128,
13605 IX86_BUILTIN_PMULLW128,
13607 IX86_BUILTIN_PSADBW128,
13608 IX86_BUILTIN_PSHUFHW,
13609 IX86_BUILTIN_PSHUFLW,
13610 IX86_BUILTIN_PSHUFD,
13612 IX86_BUILTIN_PSLLW128,
13613 IX86_BUILTIN_PSLLD128,
13614 IX86_BUILTIN_PSLLQ128,
13615 IX86_BUILTIN_PSRAW128,
13616 IX86_BUILTIN_PSRAD128,
13617 IX86_BUILTIN_PSRLW128,
13618 IX86_BUILTIN_PSRLD128,
13619 IX86_BUILTIN_PSRLQ128,
13620 IX86_BUILTIN_PSLLDQI128,
13621 IX86_BUILTIN_PSLLWI128,
13622 IX86_BUILTIN_PSLLDI128,
13623 IX86_BUILTIN_PSLLQI128,
13624 IX86_BUILTIN_PSRAWI128,
13625 IX86_BUILTIN_PSRADI128,
13626 IX86_BUILTIN_PSRLDQI128,
13627 IX86_BUILTIN_PSRLWI128,
13628 IX86_BUILTIN_PSRLDI128,
13629 IX86_BUILTIN_PSRLQI128,
13631 IX86_BUILTIN_PUNPCKHBW128,
13632 IX86_BUILTIN_PUNPCKHWD128,
13633 IX86_BUILTIN_PUNPCKHDQ128,
13634 IX86_BUILTIN_PUNPCKHQDQ128,
13635 IX86_BUILTIN_PUNPCKLBW128,
13636 IX86_BUILTIN_PUNPCKLWD128,
13637 IX86_BUILTIN_PUNPCKLDQ128,
13638 IX86_BUILTIN_PUNPCKLQDQ128,
13640 IX86_BUILTIN_CLFLUSH,
13641 IX86_BUILTIN_MFENCE,
13642 IX86_BUILTIN_LFENCE,
13644 /* Prescott New Instructions. */
13645 IX86_BUILTIN_ADDSUBPS,
13646 IX86_BUILTIN_HADDPS,
13647 IX86_BUILTIN_HSUBPS,
13648 IX86_BUILTIN_MOVSHDUP,
13649 IX86_BUILTIN_MOVSLDUP,
13650 IX86_BUILTIN_ADDSUBPD,
13651 IX86_BUILTIN_HADDPD,
13652 IX86_BUILTIN_HSUBPD,
13653 IX86_BUILTIN_LDDQU,
13655 IX86_BUILTIN_MONITOR,
13656 IX86_BUILTIN_MWAIT,
13658 IX86_BUILTIN_VEC_INIT_V2SI,
13659 IX86_BUILTIN_VEC_INIT_V4HI,
13660 IX86_BUILTIN_VEC_INIT_V8QI,
13661 IX86_BUILTIN_VEC_EXT_V2DF,
13662 IX86_BUILTIN_VEC_EXT_V2DI,
13663 IX86_BUILTIN_VEC_EXT_V4SF,
13664 IX86_BUILTIN_VEC_EXT_V4SI,
13665 IX86_BUILTIN_VEC_EXT_V8HI,
13666 IX86_BUILTIN_VEC_EXT_V2SI,
13667 IX86_BUILTIN_VEC_EXT_V4HI,
13668 IX86_BUILTIN_VEC_SET_V8HI,
13669 IX86_BUILTIN_VEC_SET_V4HI,
13674 #define def_builtin(MASK, NAME, TYPE, CODE) \
13676 if ((MASK) & target_flags \
13677 && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \
13678 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
13679 NULL, NULL_TREE); \
13682 /* Bits for builtin_description.flag. */
13684 /* Set when we don't support the comparison natively, and should
13685 swap_comparison in order to support it. */
13686 #define BUILTIN_DESC_SWAP_OPERANDS 1
13688 struct builtin_description
13690 const unsigned int mask;
13691 const enum insn_code icode;
13692 const char *const name;
13693 const enum ix86_builtins code;
13694 const enum rtx_code comparison;
13695 const unsigned int flag;
13698 static const struct builtin_description bdesc_comi[] =
13700 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
13701 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
13702 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
13703 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
13704 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
13705 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
13706 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
13707 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
13708 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
13709 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
13710 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
13711 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
13712 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
13713 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
13714 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
13715 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
13716 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
13717 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
13718 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
13719 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
13720 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
13721 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
13722 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
13723 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
13726 static const struct builtin_description bdesc_2arg[] =
13729 { MASK_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, 0, 0 },
13730 { MASK_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, 0, 0 },
13731 { MASK_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, 0, 0 },
13732 { MASK_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, 0, 0 },
13733 { MASK_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 },
13734 { MASK_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 },
13735 { MASK_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 },
13736 { MASK_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 },
13738 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
13739 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
13740 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
13741 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT,
13742 BUILTIN_DESC_SWAP_OPERANDS },
13743 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE,
13744 BUILTIN_DESC_SWAP_OPERANDS },
13745 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
13746 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
13747 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
13748 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
13749 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
13750 BUILTIN_DESC_SWAP_OPERANDS },
13751 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
13752 BUILTIN_DESC_SWAP_OPERANDS },
13753 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
13754 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
13755 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
13756 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
13757 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
13758 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
13759 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
13760 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
13761 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
13762 BUILTIN_DESC_SWAP_OPERANDS },
13763 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
13764 BUILTIN_DESC_SWAP_OPERANDS },
13765 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 },
13767 { MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 },
13768 { MASK_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, 0, 0 },
13769 { MASK_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 },
13770 { MASK_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 },
13772 { MASK_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 },
13773 { MASK_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, 0, 0 },
13774 { MASK_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 },
13775 { MASK_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 },
13777 { MASK_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, 0, 0 },
13778 { MASK_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, 0, 0 },
13779 { MASK_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, 0, 0 },
13780 { MASK_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, 0, 0 },
13781 { MASK_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, 0, 0 },
13784 { MASK_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 },
13785 { MASK_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 },
13786 { MASK_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 },
13787 { MASK_MMX, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 },
13788 { MASK_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 },
13789 { MASK_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 },
13790 { MASK_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 },
13791 { MASK_MMX, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 },
13793 { MASK_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 },
13794 { MASK_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 },
13795 { MASK_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 },
13796 { MASK_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 },
13797 { MASK_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 },
13798 { MASK_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 },
13799 { MASK_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 },
13800 { MASK_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 },
13802 { MASK_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 },
13803 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
13804 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
13806 { MASK_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 },
13807 { MASK_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 },
13808 { MASK_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 },
13809 { MASK_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 },
13811 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
13812 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
13814 { MASK_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 },
13815 { MASK_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 },
13816 { MASK_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 },
13817 { MASK_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 },
13818 { MASK_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 },
13819 { MASK_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 },
13821 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
13822 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
13823 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
13824 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
13826 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
13827 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
13828 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
13829 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
13830 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
13831 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
13834 { MASK_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, 0, 0 },
13835 { MASK_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, 0, 0 },
13836 { MASK_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, 0, 0 },
13838 { MASK_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 },
13839 { MASK_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 },
13840 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 },
13842 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 },
13843 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 },
13844 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 },
13845 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 },
13846 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, 0, 0 },
13847 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, 0, 0 },
13849 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 },
13850 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 },
13851 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 },
13852 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 },
13853 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, 0, 0 },
13854 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, 0, 0 },
13856 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 },
13857 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 },
13858 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 },
13859 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 },
13861 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, 0, 0 },
13862 { MASK_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, 0, 0 },
13865 { MASK_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, 0, 0 },
13866 { MASK_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, 0, 0 },
13867 { MASK_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, 0, 0 },
13868 { MASK_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, 0, 0 },
13869 { MASK_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 },
13870 { MASK_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 },
13871 { MASK_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 },
13872 { MASK_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 },
13874 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
13875 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
13876 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
13877 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT,
13878 BUILTIN_DESC_SWAP_OPERANDS },
13879 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE,
13880 BUILTIN_DESC_SWAP_OPERANDS },
13881 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
13882 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
13883 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
13884 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
13885 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
13886 BUILTIN_DESC_SWAP_OPERANDS },
13887 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
13888 BUILTIN_DESC_SWAP_OPERANDS },
13889 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
13890 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
13891 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
13892 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
13893 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
13894 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
13895 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
13896 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
13897 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
13899 { MASK_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, 0, 0 },
13900 { MASK_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, 0, 0 },
13901 { MASK_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 },
13902 { MASK_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 },
13904 { MASK_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 },
13905 { MASK_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, 0, 0 },
13906 { MASK_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 },
13907 { MASK_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 },
13909 { MASK_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, 0, 0 },
13910 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
13911 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
13914 { MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
13915 { MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
13916 { MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
13917 { MASK_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
13918 { MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
13919 { MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
13920 { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
13921 { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
13923 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
13924 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
13925 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
13926 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
13927 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
13928 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
13929 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
13930 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
13932 { MASK_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, 0, 0 },
13933 { MASK_SSE2, CODE_FOR_sse2_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
13935 { MASK_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 },
13936 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
13937 { MASK_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 },
13938 { MASK_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 },
13940 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
13941 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
13943 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
13944 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
13945 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
13946 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
13947 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
13948 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
13950 { MASK_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, 0, 0 },
13951 { MASK_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, 0, 0 },
13952 { MASK_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, 0, 0 },
13953 { MASK_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, 0, 0 },
13955 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
13956 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
13957 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
13958 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
13959 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
13960 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
13961 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
13962 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
13964 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
13965 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
13966 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
13968 { MASK_SSE2, CODE_FOR_sse2_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
13969 { MASK_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, 0, 0 },
13971 { MASK_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, 0, 0 },
13972 { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, 0, 0 },
13974 { MASK_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, 0, 0 },
13975 { MASK_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, 0, 0 },
13976 { MASK_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, 0, 0 },
13978 { MASK_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, 0, 0 },
13979 { MASK_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, 0, 0 },
13980 { MASK_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, 0, 0 },
13982 { MASK_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, 0, 0 },
13983 { MASK_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, 0, 0 },
13985 { MASK_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, 0, 0 },
13987 { MASK_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 },
13988 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 },
13989 { MASK_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
13990 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
13993 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
13994 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
13995 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
13996 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
13997 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
13998 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
14001 static const struct builtin_description bdesc_1arg[] =
14003 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
14004 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
14006 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },
14007 { MASK_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 },
14008 { MASK_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 },
14010 { MASK_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 },
14011 { MASK_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 },
14012 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 },
14013 { MASK_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 },
14014 { MASK_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 },
14015 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 },
14017 { MASK_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, 0, 0 },
14018 { MASK_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, 0, 0 },
14020 { MASK_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, 0, 0 },
14022 { MASK_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 },
14023 { MASK_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 },
14025 { MASK_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 },
14026 { MASK_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 },
14027 { MASK_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 },
14028 { MASK_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 },
14029 { MASK_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 },
14031 { MASK_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 },
14033 { MASK_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 },
14034 { MASK_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 },
14035 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 },
14036 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 },
14038 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
14039 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
14040 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
14043 { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
14044 { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
14048 ix86_init_builtins (void)
14051 ix86_init_mmx_sse_builtins ();
14054 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
14055 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
14058 ix86_init_mmx_sse_builtins (void)
14060 const struct builtin_description * d;
14063 tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode);
14064 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
14065 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
14066 tree V2DI_type_node
14067 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
14068 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
14069 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
14070 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
14071 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
14072 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
14073 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
14075 tree pchar_type_node = build_pointer_type (char_type_node);
14076 tree pcchar_type_node = build_pointer_type (
14077 build_type_variant (char_type_node, 1, 0));
14078 tree pfloat_type_node = build_pointer_type (float_type_node);
14079 tree pcfloat_type_node = build_pointer_type (
14080 build_type_variant (float_type_node, 1, 0));
14081 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
14082 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
14083 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
14086 tree int_ftype_v4sf_v4sf
14087 = build_function_type_list (integer_type_node,
14088 V4SF_type_node, V4SF_type_node, NULL_TREE);
14089 tree v4si_ftype_v4sf_v4sf
14090 = build_function_type_list (V4SI_type_node,
14091 V4SF_type_node, V4SF_type_node, NULL_TREE);
14092 /* MMX/SSE/integer conversions. */
14093 tree int_ftype_v4sf
14094 = build_function_type_list (integer_type_node,
14095 V4SF_type_node, NULL_TREE);
14096 tree int64_ftype_v4sf
14097 = build_function_type_list (long_long_integer_type_node,
14098 V4SF_type_node, NULL_TREE);
14099 tree int_ftype_v8qi
14100 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
14101 tree v4sf_ftype_v4sf_int
14102 = build_function_type_list (V4SF_type_node,
14103 V4SF_type_node, integer_type_node, NULL_TREE);
14104 tree v4sf_ftype_v4sf_int64
14105 = build_function_type_list (V4SF_type_node,
14106 V4SF_type_node, long_long_integer_type_node,
14108 tree v4sf_ftype_v4sf_v2si
14109 = build_function_type_list (V4SF_type_node,
14110 V4SF_type_node, V2SI_type_node, NULL_TREE);
14112 /* Miscellaneous. */
14113 tree v8qi_ftype_v4hi_v4hi
14114 = build_function_type_list (V8QI_type_node,
14115 V4HI_type_node, V4HI_type_node, NULL_TREE);
14116 tree v4hi_ftype_v2si_v2si
14117 = build_function_type_list (V4HI_type_node,
14118 V2SI_type_node, V2SI_type_node, NULL_TREE);
14119 tree v4sf_ftype_v4sf_v4sf_int
14120 = build_function_type_list (V4SF_type_node,
14121 V4SF_type_node, V4SF_type_node,
14122 integer_type_node, NULL_TREE);
14123 tree v2si_ftype_v4hi_v4hi
14124 = build_function_type_list (V2SI_type_node,
14125 V4HI_type_node, V4HI_type_node, NULL_TREE);
14126 tree v4hi_ftype_v4hi_int
14127 = build_function_type_list (V4HI_type_node,
14128 V4HI_type_node, integer_type_node, NULL_TREE);
14129 tree v4hi_ftype_v4hi_di
14130 = build_function_type_list (V4HI_type_node,
14131 V4HI_type_node, long_long_unsigned_type_node,
14133 tree v2si_ftype_v2si_di
14134 = build_function_type_list (V2SI_type_node,
14135 V2SI_type_node, long_long_unsigned_type_node,
14137 tree void_ftype_void
14138 = build_function_type (void_type_node, void_list_node);
14139 tree void_ftype_unsigned
14140 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
14141 tree void_ftype_unsigned_unsigned
14142 = build_function_type_list (void_type_node, unsigned_type_node,
14143 unsigned_type_node, NULL_TREE);
14144 tree void_ftype_pcvoid_unsigned_unsigned
14145 = build_function_type_list (void_type_node, const_ptr_type_node,
14146 unsigned_type_node, unsigned_type_node,
14148 tree unsigned_ftype_void
14149 = build_function_type (unsigned_type_node, void_list_node);
14150 tree v2si_ftype_v4sf
14151 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
14152 /* Loads/stores. */
14153 tree void_ftype_v8qi_v8qi_pchar
14154 = build_function_type_list (void_type_node,
14155 V8QI_type_node, V8QI_type_node,
14156 pchar_type_node, NULL_TREE);
14157 tree v4sf_ftype_pcfloat
14158 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
14159 /* @@@ the type is bogus */
14160 tree v4sf_ftype_v4sf_pv2si
14161 = build_function_type_list (V4SF_type_node,
14162 V4SF_type_node, pv2si_type_node, NULL_TREE);
14163 tree void_ftype_pv2si_v4sf
14164 = build_function_type_list (void_type_node,
14165 pv2si_type_node, V4SF_type_node, NULL_TREE);
14166 tree void_ftype_pfloat_v4sf
14167 = build_function_type_list (void_type_node,
14168 pfloat_type_node, V4SF_type_node, NULL_TREE);
14169 tree void_ftype_pdi_di
14170 = build_function_type_list (void_type_node,
14171 pdi_type_node, long_long_unsigned_type_node,
14173 tree void_ftype_pv2di_v2di
14174 = build_function_type_list (void_type_node,
14175 pv2di_type_node, V2DI_type_node, NULL_TREE);
14176 /* Normal vector unops. */
14177 tree v4sf_ftype_v4sf
14178 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
14180 /* Normal vector binops. */
14181 tree v4sf_ftype_v4sf_v4sf
14182 = build_function_type_list (V4SF_type_node,
14183 V4SF_type_node, V4SF_type_node, NULL_TREE);
14184 tree v8qi_ftype_v8qi_v8qi
14185 = build_function_type_list (V8QI_type_node,
14186 V8QI_type_node, V8QI_type_node, NULL_TREE);
14187 tree v4hi_ftype_v4hi_v4hi
14188 = build_function_type_list (V4HI_type_node,
14189 V4HI_type_node, V4HI_type_node, NULL_TREE);
14190 tree v2si_ftype_v2si_v2si
14191 = build_function_type_list (V2SI_type_node,
14192 V2SI_type_node, V2SI_type_node, NULL_TREE);
14193 tree di_ftype_di_di
14194 = build_function_type_list (long_long_unsigned_type_node,
14195 long_long_unsigned_type_node,
14196 long_long_unsigned_type_node, NULL_TREE);
14198 tree v2si_ftype_v2sf
14199 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
14200 tree v2sf_ftype_v2si
14201 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
14202 tree v2si_ftype_v2si
14203 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
14204 tree v2sf_ftype_v2sf
14205 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
14206 tree v2sf_ftype_v2sf_v2sf
14207 = build_function_type_list (V2SF_type_node,
14208 V2SF_type_node, V2SF_type_node, NULL_TREE);
14209 tree v2si_ftype_v2sf_v2sf
14210 = build_function_type_list (V2SI_type_node,
14211 V2SF_type_node, V2SF_type_node, NULL_TREE);
14212 tree pint_type_node = build_pointer_type (integer_type_node);
14213 tree pdouble_type_node = build_pointer_type (double_type_node);
14214 tree pcdouble_type_node = build_pointer_type (
14215 build_type_variant (double_type_node, 1, 0));
14216 tree int_ftype_v2df_v2df
14217 = build_function_type_list (integer_type_node,
14218 V2DF_type_node, V2DF_type_node, NULL_TREE);
14220 tree ti_ftype_ti_ti
14221 = build_function_type_list (intTI_type_node,
14222 intTI_type_node, intTI_type_node, NULL_TREE);
14223 tree void_ftype_pcvoid
14224 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
14225 tree v4sf_ftype_v4si
14226 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
14227 tree v4si_ftype_v4sf
14228 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
14229 tree v2df_ftype_v4si
14230 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
14231 tree v4si_ftype_v2df
14232 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
14233 tree v2si_ftype_v2df
14234 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
14235 tree v4sf_ftype_v2df
14236 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
14237 tree v2df_ftype_v2si
14238 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
14239 tree v2df_ftype_v4sf
14240 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
14241 tree int_ftype_v2df
14242 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
14243 tree int64_ftype_v2df
14244 = build_function_type_list (long_long_integer_type_node,
14245 V2DF_type_node, NULL_TREE);
14246 tree v2df_ftype_v2df_int
14247 = build_function_type_list (V2DF_type_node,
14248 V2DF_type_node, integer_type_node, NULL_TREE);
14249 tree v2df_ftype_v2df_int64
14250 = build_function_type_list (V2DF_type_node,
14251 V2DF_type_node, long_long_integer_type_node,
14253 tree v4sf_ftype_v4sf_v2df
14254 = build_function_type_list (V4SF_type_node,
14255 V4SF_type_node, V2DF_type_node, NULL_TREE);
14256 tree v2df_ftype_v2df_v4sf
14257 = build_function_type_list (V2DF_type_node,
14258 V2DF_type_node, V4SF_type_node, NULL_TREE);
14259 tree v2df_ftype_v2df_v2df_int
14260 = build_function_type_list (V2DF_type_node,
14261 V2DF_type_node, V2DF_type_node,
14264 tree v2df_ftype_v2df_pcdouble
14265 = build_function_type_list (V2DF_type_node,
14266 V2DF_type_node, pcdouble_type_node, NULL_TREE);
14267 tree void_ftype_pdouble_v2df
14268 = build_function_type_list (void_type_node,
14269 pdouble_type_node, V2DF_type_node, NULL_TREE);
14270 tree void_ftype_pint_int
14271 = build_function_type_list (void_type_node,
14272 pint_type_node, integer_type_node, NULL_TREE);
14273 tree void_ftype_v16qi_v16qi_pchar
14274 = build_function_type_list (void_type_node,
14275 V16QI_type_node, V16QI_type_node,
14276 pchar_type_node, NULL_TREE);
14277 tree v2df_ftype_pcdouble
14278 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
14279 tree v2df_ftype_v2df_v2df
14280 = build_function_type_list (V2DF_type_node,
14281 V2DF_type_node, V2DF_type_node, NULL_TREE);
14282 tree v16qi_ftype_v16qi_v16qi
14283 = build_function_type_list (V16QI_type_node,
14284 V16QI_type_node, V16QI_type_node, NULL_TREE);
14285 tree v8hi_ftype_v8hi_v8hi
14286 = build_function_type_list (V8HI_type_node,
14287 V8HI_type_node, V8HI_type_node, NULL_TREE);
14288 tree v4si_ftype_v4si_v4si
14289 = build_function_type_list (V4SI_type_node,
14290 V4SI_type_node, V4SI_type_node, NULL_TREE);
14291 tree v2di_ftype_v2di_v2di
14292 = build_function_type_list (V2DI_type_node,
14293 V2DI_type_node, V2DI_type_node, NULL_TREE);
14294 tree v2di_ftype_v2df_v2df
14295 = build_function_type_list (V2DI_type_node,
14296 V2DF_type_node, V2DF_type_node, NULL_TREE);
14297 tree v2df_ftype_v2df
14298 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
14299 tree v2di_ftype_v2di_int
14300 = build_function_type_list (V2DI_type_node,
14301 V2DI_type_node, integer_type_node, NULL_TREE);
14302 tree v4si_ftype_v4si_int
14303 = build_function_type_list (V4SI_type_node,
14304 V4SI_type_node, integer_type_node, NULL_TREE);
14305 tree v8hi_ftype_v8hi_int
14306 = build_function_type_list (V8HI_type_node,
14307 V8HI_type_node, integer_type_node, NULL_TREE);
14308 tree v8hi_ftype_v8hi_v2di
14309 = build_function_type_list (V8HI_type_node,
14310 V8HI_type_node, V2DI_type_node, NULL_TREE);
14311 tree v4si_ftype_v4si_v2di
14312 = build_function_type_list (V4SI_type_node,
14313 V4SI_type_node, V2DI_type_node, NULL_TREE);
14314 tree v4si_ftype_v8hi_v8hi
14315 = build_function_type_list (V4SI_type_node,
14316 V8HI_type_node, V8HI_type_node, NULL_TREE);
14317 tree di_ftype_v8qi_v8qi
14318 = build_function_type_list (long_long_unsigned_type_node,
14319 V8QI_type_node, V8QI_type_node, NULL_TREE);
14320 tree di_ftype_v2si_v2si
14321 = build_function_type_list (long_long_unsigned_type_node,
14322 V2SI_type_node, V2SI_type_node, NULL_TREE);
14323 tree v2di_ftype_v16qi_v16qi
14324 = build_function_type_list (V2DI_type_node,
14325 V16QI_type_node, V16QI_type_node, NULL_TREE);
14326 tree v2di_ftype_v4si_v4si
14327 = build_function_type_list (V2DI_type_node,
14328 V4SI_type_node, V4SI_type_node, NULL_TREE);
14329 tree int_ftype_v16qi
14330 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
14331 tree v16qi_ftype_pcchar
14332 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
14333 tree void_ftype_pchar_v16qi
14334 = build_function_type_list (void_type_node,
14335 pchar_type_node, V16QI_type_node, NULL_TREE);
14338 tree float128_type;
14341 /* The __float80 type. */
14342 if (TYPE_MODE (long_double_type_node) == XFmode)
14343 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
14347 /* The __float80 type. */
14348 float80_type = make_node (REAL_TYPE);
14349 TYPE_PRECISION (float80_type) = 80;
14350 layout_type (float80_type);
14351 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
14354 float128_type = make_node (REAL_TYPE);
14355 TYPE_PRECISION (float128_type) = 128;
14356 layout_type (float128_type);
14357 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
14359 /* Add all builtins that are more or less simple operations on two
14361 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
14363 /* Use one of the operands; the target can have a different mode for
14364 mask-generating compares. */
14365 enum machine_mode mode;
14370 mode = insn_data[d->icode].operand[1].mode;
14375 type = v16qi_ftype_v16qi_v16qi;
14378 type = v8hi_ftype_v8hi_v8hi;
14381 type = v4si_ftype_v4si_v4si;
14384 type = v2di_ftype_v2di_v2di;
14387 type = v2df_ftype_v2df_v2df;
14390 type = ti_ftype_ti_ti;
14393 type = v4sf_ftype_v4sf_v4sf;
14396 type = v8qi_ftype_v8qi_v8qi;
14399 type = v4hi_ftype_v4hi_v4hi;
14402 type = v2si_ftype_v2si_v2si;
14405 type = di_ftype_di_di;
14409 gcc_unreachable ();
14412 /* Override for comparisons. */
14413 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
14414 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
14415 type = v4si_ftype_v4sf_v4sf;
14417 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
14418 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
14419 type = v2di_ftype_v2df_v2df;
14421 def_builtin (d->mask, d->name, type, d->code);
14424 /* Add the remaining MMX insns with somewhat more complicated types. */
14425 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
14426 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
14427 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
14428 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
14430 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
14431 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
14432 def_builtin (MASK_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
14434 def_builtin (MASK_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
14435 def_builtin (MASK_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
14437 def_builtin (MASK_MMX, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
14438 def_builtin (MASK_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
14440 /* comi/ucomi insns. */
14441 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
14442 if (d->mask == MASK_SSE2)
14443 def_builtin (d->mask, d->name, int_ftype_v2df_v2df, d->code);
14445 def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
14447 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
14448 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
14449 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
14451 def_builtin (MASK_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
14452 def_builtin (MASK_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
14453 def_builtin (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
14454 def_builtin (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
14455 def_builtin (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
14456 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
14457 def_builtin (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
14458 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
14459 def_builtin (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
14460 def_builtin (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
14461 def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
14463 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
14465 def_builtin (MASK_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
14466 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
14468 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
14469 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
14470 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
14471 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
14473 def_builtin (MASK_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
14474 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
14475 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
14476 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
14478 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
14480 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
14482 def_builtin (MASK_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
14483 def_builtin (MASK_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
14484 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
14485 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
14486 def_builtin (MASK_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
14487 def_builtin (MASK_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
14489 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
14491 /* Original 3DNow! */
14492 def_builtin (MASK_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
14493 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
14494 def_builtin (MASK_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
14495 def_builtin (MASK_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
14496 def_builtin (MASK_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
14497 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
14498 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
14499 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
14500 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
14501 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
14502 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
14503 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
14504 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
14505 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
14506 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
14507 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
14508 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
14509 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
14510 def_builtin (MASK_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
14511 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
14513 /* 3DNow! extension as used in the Athlon CPU. */
14514 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
14515 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
14516 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
14517 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
14518 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
14519 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
14522 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
14524 def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
14525 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
14527 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
14528 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
14530 def_builtin (MASK_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
14531 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
14532 def_builtin (MASK_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
14533 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
14534 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
14536 def_builtin (MASK_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
14537 def_builtin (MASK_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
14538 def_builtin (MASK_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
14539 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
14541 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
14542 def_builtin (MASK_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
14544 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
14546 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
14547 def_builtin (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
14549 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
14550 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
14551 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
14552 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
14553 def_builtin (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
14555 def_builtin (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
14557 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
14558 def_builtin (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
14559 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
14560 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
14562 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
14563 def_builtin (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
14564 def_builtin (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
14566 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
14567 def_builtin (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
14568 def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
14569 def_builtin (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
14571 def_builtin (MASK_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
14572 def_builtin (MASK_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
14573 def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
14575 def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
14576 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
14578 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
14579 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
14581 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSLLW128);
14582 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSLLD128);
14583 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
14585 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRLW128);
14586 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRLD128);
14587 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
14589 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRAW128);
14590 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRAD128);
14592 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
14593 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
14594 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
14595 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
14597 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
14598 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
14599 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
14600 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
14602 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
14603 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
14605 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
14607 /* Prescott New Instructions. */
14608 def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
14609 void_ftype_pcvoid_unsigned_unsigned,
14610 IX86_BUILTIN_MONITOR);
14611 def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
14612 void_ftype_unsigned_unsigned,
14613 IX86_BUILTIN_MWAIT);
14614 def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
14616 IX86_BUILTIN_MOVSHDUP);
14617 def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
14619 IX86_BUILTIN_MOVSLDUP);
14620 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
14621 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
14623 /* Access to the vec_init patterns. */
14624 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
14625 integer_type_node, NULL_TREE);
14626 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
14627 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
14629 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
14630 short_integer_type_node,
14631 short_integer_type_node,
14632 short_integer_type_node, NULL_TREE);
14633 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v4hi",
14634 ftype, IX86_BUILTIN_VEC_INIT_V4HI);
14636 ftype = build_function_type_list (V8QI_type_node, char_type_node,
14637 char_type_node, char_type_node,
14638 char_type_node, char_type_node,
14639 char_type_node, char_type_node,
14640 char_type_node, NULL_TREE);
14641 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v8qi",
14642 ftype, IX86_BUILTIN_VEC_INIT_V8QI);
14644 /* Access to the vec_extract patterns. */
14645 ftype = build_function_type_list (double_type_node, V2DF_type_node,
14646 integer_type_node, NULL_TREE);
14647 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2df",
14648 ftype, IX86_BUILTIN_VEC_EXT_V2DF);
14650 ftype = build_function_type_list (long_long_integer_type_node,
14651 V2DI_type_node, integer_type_node,
14653 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2di",
14654 ftype, IX86_BUILTIN_VEC_EXT_V2DI);
14656 ftype = build_function_type_list (float_type_node, V4SF_type_node,
14657 integer_type_node, NULL_TREE);
14658 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf",
14659 ftype, IX86_BUILTIN_VEC_EXT_V4SF);
14661 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
14662 integer_type_node, NULL_TREE);
14663 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si",
14664 ftype, IX86_BUILTIN_VEC_EXT_V4SI);
14666 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
14667 integer_type_node, NULL_TREE);
14668 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi",
14669 ftype, IX86_BUILTIN_VEC_EXT_V8HI);
14671 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
14672 integer_type_node, NULL_TREE);
14673 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_ext_v4hi",
14674 ftype, IX86_BUILTIN_VEC_EXT_V4HI);
14676 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
14677 integer_type_node, NULL_TREE);
14678 def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
14679 ftype, IX86_BUILTIN_VEC_EXT_V2SI);
14681 /* Access to the vec_set patterns. */
14682 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
14684 integer_type_node, NULL_TREE);
14685 def_builtin (MASK_SSE, "__builtin_ia32_vec_set_v8hi",
14686 ftype, IX86_BUILTIN_VEC_SET_V8HI);
14688 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
14690 integer_type_node, NULL_TREE);
14691 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_set_v4hi",
14692 ftype, IX86_BUILTIN_VEC_SET_V4HI);
14695 /* Errors in the source file can cause expand_expr to return const0_rtx
14696 where we expect a vector. To avoid crashing, use one of the vector
14697 clear instructions. */
14699 safe_vector_operand (rtx x, enum machine_mode mode)
14701 if (x == const0_rtx)
14702 x = CONST0_RTX (mode);
14706 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
14709 ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
14712 tree arg0 = TREE_VALUE (arglist);
14713 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14714 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14715 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14716 enum machine_mode tmode = insn_data[icode].operand[0].mode;
14717 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
14718 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
14720 if (VECTOR_MODE_P (mode0))
14721 op0 = safe_vector_operand (op0, mode0);
14722 if (VECTOR_MODE_P (mode1))
14723 op1 = safe_vector_operand (op1, mode1);
14725 if (optimize || !target
14726 || GET_MODE (target) != tmode
14727 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14728 target = gen_reg_rtx (tmode);
14730 if (GET_MODE (op1) == SImode && mode1 == TImode)
14732 rtx x = gen_reg_rtx (V4SImode);
14733 emit_insn (gen_sse2_loadd (x, op1));
14734 op1 = gen_lowpart (TImode, x);
14737 /* The insn must want input operands in the same modes as the
14739 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
14740 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
14742 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
14743 op0 = copy_to_mode_reg (mode0, op0);
14744 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
14745 op1 = copy_to_mode_reg (mode1, op1);
14747 /* ??? Using ix86_fixup_binary_operands is problematic when
14748 we've got mismatched modes. Fake it. */
14754 if (tmode == mode0 && tmode == mode1)
14756 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
14760 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
14762 op0 = force_reg (mode0, op0);
14763 op1 = force_reg (mode1, op1);
14764 target = gen_reg_rtx (tmode);
14767 pat = GEN_FCN (icode) (target, op0, op1);
14774 /* Subroutine of ix86_expand_builtin to take care of stores. */
14777 ix86_expand_store_builtin (enum insn_code icode, tree arglist)
14780 tree arg0 = TREE_VALUE (arglist);
14781 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14782 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14783 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14784 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
14785 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
14787 if (VECTOR_MODE_P (mode1))
14788 op1 = safe_vector_operand (op1, mode1);
14790 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
14791 op1 = copy_to_mode_reg (mode1, op1);
14793 pat = GEN_FCN (icode) (op0, op1);
14799 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
14802 ix86_expand_unop_builtin (enum insn_code icode, tree arglist,
14803 rtx target, int do_load)
14806 tree arg0 = TREE_VALUE (arglist);
14807 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14808 enum machine_mode tmode = insn_data[icode].operand[0].mode;
14809 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
14811 if (optimize || !target
14812 || GET_MODE (target) != tmode
14813 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14814 target = gen_reg_rtx (tmode);
14816 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
14819 if (VECTOR_MODE_P (mode0))
14820 op0 = safe_vector_operand (op0, mode0);
14822 if ((optimize && !register_operand (op0, mode0))
14823 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14824 op0 = copy_to_mode_reg (mode0, op0);
14827 pat = GEN_FCN (icode) (target, op0);
14834 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
14835 sqrtss, rsqrtss, rcpss. */
14838 ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target)
14841 tree arg0 = TREE_VALUE (arglist);
14842 rtx op1, op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14843 enum machine_mode tmode = insn_data[icode].operand[0].mode;
14844 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
14846 if (optimize || !target
14847 || GET_MODE (target) != tmode
14848 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14849 target = gen_reg_rtx (tmode);
14851 if (VECTOR_MODE_P (mode0))
14852 op0 = safe_vector_operand (op0, mode0);
14854 if ((optimize && !register_operand (op0, mode0))
14855 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14856 op0 = copy_to_mode_reg (mode0, op0);
14859 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
14860 op1 = copy_to_mode_reg (mode0, op1);
14862 pat = GEN_FCN (icode) (target, op0, op1);
14869 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
14872 ix86_expand_sse_compare (const struct builtin_description *d, tree arglist,
14876 tree arg0 = TREE_VALUE (arglist);
14877 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14878 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14879 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14881 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
14882 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
14883 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
14884 enum rtx_code comparison = d->comparison;
14886 if (VECTOR_MODE_P (mode0))
14887 op0 = safe_vector_operand (op0, mode0);
14888 if (VECTOR_MODE_P (mode1))
14889 op1 = safe_vector_operand (op1, mode1);
14891 /* Swap operands if we have a comparison that isn't available in
14893 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
14895 rtx tmp = gen_reg_rtx (mode1);
14896 emit_move_insn (tmp, op1);
14901 if (optimize || !target
14902 || GET_MODE (target) != tmode
14903 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
14904 target = gen_reg_rtx (tmode);
14906 if ((optimize && !register_operand (op0, mode0))
14907 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
14908 op0 = copy_to_mode_reg (mode0, op0);
14909 if ((optimize && !register_operand (op1, mode1))
14910 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
14911 op1 = copy_to_mode_reg (mode1, op1);
14913 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
14914 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
14921 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
14924 ix86_expand_sse_comi (const struct builtin_description *d, tree arglist,
14928 tree arg0 = TREE_VALUE (arglist);
14929 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
14930 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
14931 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
14933 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
14934 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
14935 enum rtx_code comparison = d->comparison;
14937 if (VECTOR_MODE_P (mode0))
14938 op0 = safe_vector_operand (op0, mode0);
14939 if (VECTOR_MODE_P (mode1))
14940 op1 = safe_vector_operand (op1, mode1);
14942 /* Swap operands if we have a comparison that isn't available in
14944 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
14951 target = gen_reg_rtx (SImode);
14952 emit_move_insn (target, const0_rtx);
14953 target = gen_rtx_SUBREG (QImode, target, 0);
14955 if ((optimize && !register_operand (op0, mode0))
14956 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14957 op0 = copy_to_mode_reg (mode0, op0);
14958 if ((optimize && !register_operand (op1, mode1))
14959 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14960 op1 = copy_to_mode_reg (mode1, op1);
14962 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
14963 pat = GEN_FCN (d->icode) (op0, op1);
14967 emit_insn (gen_rtx_SET (VOIDmode,
14968 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
14969 gen_rtx_fmt_ee (comparison, QImode,
14973 return SUBREG_REG (target);
14976 /* Return the integer constant in ARG. Constrain it to be in the range
14977 of the subparts of VEC_TYPE; issue an error if not. */
14980 get_element_number (tree vec_type, tree arg)
14982 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14984 if (!host_integerp (arg, 1)
14985 || (elt = tree_low_cst (arg, 1), elt > max))
14987 error ("selector must be an integer constant in the range 0..%wi", max);
14994 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
14995 ix86_expand_vector_init. We DO have language-level syntax for this, in
14996 the form of (type){ init-list }. Except that since we can't place emms
14997 instructions from inside the compiler, we can't allow the use of MMX
14998 registers unless the user explicitly asks for it. So we do *not* define
14999 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
15000 we have builtins invoked by mmintrin.h that gives us license to emit
15001 these sorts of instructions. */
15004 ix86_expand_vec_init_builtin (tree type, tree arglist, rtx target)
15006 enum machine_mode tmode = TYPE_MODE (type);
15007 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
15008 int i, n_elt = GET_MODE_NUNITS (tmode);
15009 rtvec v = rtvec_alloc (n_elt);
15011 gcc_assert (VECTOR_MODE_P (tmode));
15013 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
15015 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
15016 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15019 gcc_assert (arglist == NULL);
15021 if (!target || !register_operand (target, tmode))
15022 target = gen_reg_rtx (tmode);
15024 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
15028 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15029 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
15030 had a language-level syntax for referencing vector elements. */
15033 ix86_expand_vec_ext_builtin (tree arglist, rtx target)
15035 enum machine_mode tmode, mode0;
15040 arg0 = TREE_VALUE (arglist);
15041 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15043 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15044 elt = get_element_number (TREE_TYPE (arg0), arg1);
15046 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15047 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15048 gcc_assert (VECTOR_MODE_P (mode0));
15050 op0 = force_reg (mode0, op0);
15052 if (optimize || !target || !register_operand (target, tmode))
15053 target = gen_reg_rtx (tmode);
15055 ix86_expand_vector_extract (true, target, op0, elt);
15060 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
15061 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
15062 a language-level syntax for referencing vector elements. */
15065 ix86_expand_vec_set_builtin (tree arglist)
15067 enum machine_mode tmode, mode1;
15068 tree arg0, arg1, arg2;
15072 arg0 = TREE_VALUE (arglist);
15073 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15074 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15076 tmode = TYPE_MODE (TREE_TYPE (arg0));
15077 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15078 gcc_assert (VECTOR_MODE_P (tmode));
15080 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
15081 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
15082 elt = get_element_number (TREE_TYPE (arg0), arg2);
15084 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15085 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15087 op0 = force_reg (tmode, op0);
15088 op1 = force_reg (mode1, op1);
15090 ix86_expand_vector_set (true, op0, op1, elt);
15095 /* Expand an expression EXP that calls a built-in function,
15096 with result going to TARGET if that's convenient
15097 (and in mode MODE if that's convenient).
15098 SUBTARGET may be used as the target for computing one of EXP's operands.
15099 IGNORE is nonzero if the value is to be ignored. */
15102 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15103 enum machine_mode mode ATTRIBUTE_UNUSED,
15104 int ignore ATTRIBUTE_UNUSED)
15106 const struct builtin_description *d;
15108 enum insn_code icode;
15109 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
15110 tree arglist = TREE_OPERAND (exp, 1);
15111 tree arg0, arg1, arg2;
15112 rtx op0, op1, op2, pat;
15113 enum machine_mode tmode, mode0, mode1, mode2;
15114 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15118 case IX86_BUILTIN_EMMS:
15119 emit_insn (gen_mmx_emms ());
15122 case IX86_BUILTIN_SFENCE:
15123 emit_insn (gen_sse_sfence ());
15126 case IX86_BUILTIN_MASKMOVQ:
15127 case IX86_BUILTIN_MASKMOVDQU:
15128 icode = (fcode == IX86_BUILTIN_MASKMOVQ
15129 ? CODE_FOR_mmx_maskmovq
15130 : CODE_FOR_sse2_maskmovdqu);
15131 /* Note the arg order is different from the operand order. */
15132 arg1 = TREE_VALUE (arglist);
15133 arg2 = TREE_VALUE (TREE_CHAIN (arglist));
15134 arg0 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15135 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15136 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15137 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15138 mode0 = insn_data[icode].operand[0].mode;
15139 mode1 = insn_data[icode].operand[1].mode;
15140 mode2 = insn_data[icode].operand[2].mode;
15142 op0 = force_reg (Pmode, op0);
15143 op0 = gen_rtx_MEM (mode1, op0);
15145 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15146 op0 = copy_to_mode_reg (mode0, op0);
15147 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15148 op1 = copy_to_mode_reg (mode1, op1);
15149 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
15150 op2 = copy_to_mode_reg (mode2, op2);
15151 pat = GEN_FCN (icode) (op0, op1, op2);
15157 case IX86_BUILTIN_SQRTSS:
15158 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, arglist, target);
15159 case IX86_BUILTIN_RSQRTSS:
15160 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, arglist, target);
15161 case IX86_BUILTIN_RCPSS:
15162 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, arglist, target);
15164 case IX86_BUILTIN_LOADUPS:
15165 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, arglist, target, 1);
15167 case IX86_BUILTIN_STOREUPS:
15168 return ix86_expand_store_builtin (CODE_FOR_sse_movups, arglist);
15170 case IX86_BUILTIN_LOADHPS:
15171 case IX86_BUILTIN_LOADLPS:
15172 case IX86_BUILTIN_LOADHPD:
15173 case IX86_BUILTIN_LOADLPD:
15174 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
15175 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
15176 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
15177 : CODE_FOR_sse2_loadlpd);
15178 arg0 = TREE_VALUE (arglist);
15179 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15180 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15181 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15182 tmode = insn_data[icode].operand[0].mode;
15183 mode0 = insn_data[icode].operand[1].mode;
15184 mode1 = insn_data[icode].operand[2].mode;
15186 op0 = force_reg (mode0, op0);
15187 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
15188 if (optimize || target == 0
15189 || GET_MODE (target) != tmode
15190 || !register_operand (target, tmode))
15191 target = gen_reg_rtx (tmode);
15192 pat = GEN_FCN (icode) (target, op0, op1);
15198 case IX86_BUILTIN_STOREHPS:
15199 case IX86_BUILTIN_STORELPS:
15200 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
15201 : CODE_FOR_sse_storelps);
15202 arg0 = TREE_VALUE (arglist);
15203 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15204 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15205 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15206 mode0 = insn_data[icode].operand[0].mode;
15207 mode1 = insn_data[icode].operand[1].mode;
15209 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15210 op1 = force_reg (mode1, op1);
15212 pat = GEN_FCN (icode) (op0, op1);
15218 case IX86_BUILTIN_MOVNTPS:
15219 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, arglist);
15220 case IX86_BUILTIN_MOVNTQ:
15221 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, arglist);
15223 case IX86_BUILTIN_LDMXCSR:
15224 op0 = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
15225 target = assign_386_stack_local (SImode, SLOT_TEMP);
15226 emit_move_insn (target, op0);
15227 emit_insn (gen_sse_ldmxcsr (target));
15230 case IX86_BUILTIN_STMXCSR:
15231 target = assign_386_stack_local (SImode, SLOT_TEMP);
15232 emit_insn (gen_sse_stmxcsr (target));
15233 return copy_to_mode_reg (SImode, target);
15235 case IX86_BUILTIN_SHUFPS:
15236 case IX86_BUILTIN_SHUFPD:
15237 icode = (fcode == IX86_BUILTIN_SHUFPS
15238 ? CODE_FOR_sse_shufps
15239 : CODE_FOR_sse2_shufpd);
15240 arg0 = TREE_VALUE (arglist);
15241 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15242 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15243 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15244 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15245 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15246 tmode = insn_data[icode].operand[0].mode;
15247 mode0 = insn_data[icode].operand[1].mode;
15248 mode1 = insn_data[icode].operand[2].mode;
15249 mode2 = insn_data[icode].operand[3].mode;
15251 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15252 op0 = copy_to_mode_reg (mode0, op0);
15253 if ((optimize && !register_operand (op1, mode1))
15254 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
15255 op1 = copy_to_mode_reg (mode1, op1);
15256 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15258 /* @@@ better error message */
15259 error ("mask must be an immediate");
15260 return gen_reg_rtx (tmode);
15262 if (optimize || target == 0
15263 || GET_MODE (target) != tmode
15264 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15265 target = gen_reg_rtx (tmode);
15266 pat = GEN_FCN (icode) (target, op0, op1, op2);
15272 case IX86_BUILTIN_PSHUFW:
15273 case IX86_BUILTIN_PSHUFD:
15274 case IX86_BUILTIN_PSHUFHW:
15275 case IX86_BUILTIN_PSHUFLW:
15276 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
15277 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
15278 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
15279 : CODE_FOR_mmx_pshufw);
15280 arg0 = TREE_VALUE (arglist);
15281 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15282 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15283 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15284 tmode = insn_data[icode].operand[0].mode;
15285 mode1 = insn_data[icode].operand[1].mode;
15286 mode2 = insn_data[icode].operand[2].mode;
15288 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15289 op0 = copy_to_mode_reg (mode1, op0);
15290 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15292 /* @@@ better error message */
15293 error ("mask must be an immediate");
15297 || GET_MODE (target) != tmode
15298 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15299 target = gen_reg_rtx (tmode);
15300 pat = GEN_FCN (icode) (target, op0, op1);
15306 case IX86_BUILTIN_PSLLDQI128:
15307 case IX86_BUILTIN_PSRLDQI128:
15308 icode = ( fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
15309 : CODE_FOR_sse2_lshrti3);
15310 arg0 = TREE_VALUE (arglist);
15311 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15312 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15313 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15314 tmode = insn_data[icode].operand[0].mode;
15315 mode1 = insn_data[icode].operand[1].mode;
15316 mode2 = insn_data[icode].operand[2].mode;
15318 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15320 op0 = copy_to_reg (op0);
15321 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
15323 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15325 error ("shift must be an immediate");
15328 target = gen_reg_rtx (V2DImode);
15329 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0), op0, op1);
15335 case IX86_BUILTIN_FEMMS:
15336 emit_insn (gen_mmx_femms ());
15339 case IX86_BUILTIN_PAVGUSB:
15340 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, arglist, target);
15342 case IX86_BUILTIN_PF2ID:
15343 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, arglist, target, 0);
15345 case IX86_BUILTIN_PFACC:
15346 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, arglist, target);
15348 case IX86_BUILTIN_PFADD:
15349 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, arglist, target);
15351 case IX86_BUILTIN_PFCMPEQ:
15352 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, arglist, target);
15354 case IX86_BUILTIN_PFCMPGE:
15355 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, arglist, target);
15357 case IX86_BUILTIN_PFCMPGT:
15358 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, arglist, target);
15360 case IX86_BUILTIN_PFMAX:
15361 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, arglist, target);
15363 case IX86_BUILTIN_PFMIN:
15364 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, arglist, target);
15366 case IX86_BUILTIN_PFMUL:
15367 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, arglist, target);
15369 case IX86_BUILTIN_PFRCP:
15370 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, arglist, target, 0);
15372 case IX86_BUILTIN_PFRCPIT1:
15373 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, arglist, target);
15375 case IX86_BUILTIN_PFRCPIT2:
15376 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, arglist, target);
15378 case IX86_BUILTIN_PFRSQIT1:
15379 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, arglist, target);
15381 case IX86_BUILTIN_PFRSQRT:
15382 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, arglist, target, 0);
15384 case IX86_BUILTIN_PFSUB:
15385 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, arglist, target);
15387 case IX86_BUILTIN_PFSUBR:
15388 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, arglist, target);
15390 case IX86_BUILTIN_PI2FD:
15391 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, arglist, target, 0);
15393 case IX86_BUILTIN_PMULHRW:
15394 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, arglist, target);
15396 case IX86_BUILTIN_PF2IW:
15397 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, arglist, target, 0);
15399 case IX86_BUILTIN_PFNACC:
15400 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, arglist, target);
15402 case IX86_BUILTIN_PFPNACC:
15403 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, arglist, target);
15405 case IX86_BUILTIN_PI2FW:
15406 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, arglist, target, 0);
15408 case IX86_BUILTIN_PSWAPDSI:
15409 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, arglist, target, 0);
15411 case IX86_BUILTIN_PSWAPDSF:
15412 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, arglist, target, 0);
15414 case IX86_BUILTIN_SQRTSD:
15415 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, arglist, target);
15416 case IX86_BUILTIN_LOADUPD:
15417 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, arglist, target, 1);
15418 case IX86_BUILTIN_STOREUPD:
15419 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, arglist);
15421 case IX86_BUILTIN_MFENCE:
15422 emit_insn (gen_sse2_mfence ());
15424 case IX86_BUILTIN_LFENCE:
15425 emit_insn (gen_sse2_lfence ());
15428 case IX86_BUILTIN_CLFLUSH:
15429 arg0 = TREE_VALUE (arglist);
15430 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15431 icode = CODE_FOR_sse2_clflush;
15432 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
15433 op0 = copy_to_mode_reg (Pmode, op0);
15435 emit_insn (gen_sse2_clflush (op0));
15438 case IX86_BUILTIN_MOVNTPD:
15439 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, arglist);
15440 case IX86_BUILTIN_MOVNTDQ:
15441 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, arglist);
15442 case IX86_BUILTIN_MOVNTI:
15443 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, arglist);
15445 case IX86_BUILTIN_LOADDQU:
15446 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, arglist, target, 1);
15447 case IX86_BUILTIN_STOREDQU:
15448 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, arglist);
15450 case IX86_BUILTIN_MONITOR:
15451 arg0 = TREE_VALUE (arglist);
15452 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15453 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
15454 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15455 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15456 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
15458 op0 = copy_to_mode_reg (SImode, op0);
15460 op1 = copy_to_mode_reg (SImode, op1);
15462 op2 = copy_to_mode_reg (SImode, op2);
15463 emit_insn (gen_sse3_monitor (op0, op1, op2));
15466 case IX86_BUILTIN_MWAIT:
15467 arg0 = TREE_VALUE (arglist);
15468 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
15469 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
15470 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
15472 op0 = copy_to_mode_reg (SImode, op0);
15474 op1 = copy_to_mode_reg (SImode, op1);
15475 emit_insn (gen_sse3_mwait (op0, op1));
15478 case IX86_BUILTIN_LDDQU:
15479 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist,
15482 case IX86_BUILTIN_VEC_INIT_V2SI:
15483 case IX86_BUILTIN_VEC_INIT_V4HI:
15484 case IX86_BUILTIN_VEC_INIT_V8QI:
15485 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
15487 case IX86_BUILTIN_VEC_EXT_V2DF:
15488 case IX86_BUILTIN_VEC_EXT_V2DI:
15489 case IX86_BUILTIN_VEC_EXT_V4SF:
15490 case IX86_BUILTIN_VEC_EXT_V4SI:
15491 case IX86_BUILTIN_VEC_EXT_V8HI:
15492 case IX86_BUILTIN_VEC_EXT_V2SI:
15493 case IX86_BUILTIN_VEC_EXT_V4HI:
15494 return ix86_expand_vec_ext_builtin (arglist, target);
15496 case IX86_BUILTIN_VEC_SET_V8HI:
15497 case IX86_BUILTIN_VEC_SET_V4HI:
15498 return ix86_expand_vec_set_builtin (arglist);
15504 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
15505 if (d->code == fcode)
15507 /* Compares are treated specially. */
15508 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
15509 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
15510 || d->icode == CODE_FOR_sse2_maskcmpv2df3
15511 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
15512 return ix86_expand_sse_compare (d, arglist, target);
15514 return ix86_expand_binop_builtin (d->icode, arglist, target);
15517 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
15518 if (d->code == fcode)
15519 return ix86_expand_unop_builtin (d->icode, arglist, target, 0);
15521 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
15522 if (d->code == fcode)
15523 return ix86_expand_sse_comi (d, arglist, target);
15525 gcc_unreachable ();
15528 /* Store OPERAND to the memory after reload is completed. This means
15529 that we can't easily use assign_stack_local. */
15531 ix86_force_to_memory (enum machine_mode mode, rtx operand)
15535 gcc_assert (reload_completed);
15536 if (TARGET_RED_ZONE)
15538 result = gen_rtx_MEM (mode,
15539 gen_rtx_PLUS (Pmode,
15541 GEN_INT (-RED_ZONE_SIZE)));
15542 emit_move_insn (result, operand);
15544 else if (!TARGET_RED_ZONE && TARGET_64BIT)
15550 operand = gen_lowpart (DImode, operand);
15554 gen_rtx_SET (VOIDmode,
15555 gen_rtx_MEM (DImode,
15556 gen_rtx_PRE_DEC (DImode,
15557 stack_pointer_rtx)),
15561 gcc_unreachable ();
15563 result = gen_rtx_MEM (mode, stack_pointer_rtx);
15572 split_di (&operand, 1, operands, operands + 1);
15574 gen_rtx_SET (VOIDmode,
15575 gen_rtx_MEM (SImode,
15576 gen_rtx_PRE_DEC (Pmode,
15577 stack_pointer_rtx)),
15580 gen_rtx_SET (VOIDmode,
15581 gen_rtx_MEM (SImode,
15582 gen_rtx_PRE_DEC (Pmode,
15583 stack_pointer_rtx)),
15588 /* It is better to store HImodes as SImodes. */
15589 if (!TARGET_PARTIAL_REG_STALL)
15590 operand = gen_lowpart (SImode, operand);
15594 gen_rtx_SET (VOIDmode,
15595 gen_rtx_MEM (GET_MODE (operand),
15596 gen_rtx_PRE_DEC (SImode,
15597 stack_pointer_rtx)),
15601 gcc_unreachable ();
15603 result = gen_rtx_MEM (mode, stack_pointer_rtx);
15608 /* Free operand from the memory. */
15610 ix86_free_from_memory (enum machine_mode mode)
15612 if (!TARGET_RED_ZONE)
15616 if (mode == DImode || TARGET_64BIT)
15618 else if (mode == HImode && TARGET_PARTIAL_REG_STALL)
15622 /* Use LEA to deallocate stack space. In peephole2 it will be converted
15623 to pop or add instruction if registers are available. */
15624 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
15625 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
15630 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
15631 QImode must go into class Q_REGS.
15632 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
15633 movdf to do mem-to-mem moves through integer regs. */
15635 ix86_preferred_reload_class (rtx x, enum reg_class class)
15637 /* We're only allowed to return a subclass of CLASS. Many of the
15638 following checks fail for NO_REGS, so eliminate that early. */
15639 if (class == NO_REGS)
15642 /* All classes can load zeros. */
15643 if (x == CONST0_RTX (GET_MODE (x)))
15646 /* Floating-point constants need more complex checks. */
15647 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
15649 /* General regs can load everything. */
15650 if (reg_class_subset_p (class, GENERAL_REGS))
15653 /* Floats can load 0 and 1 plus some others. Note that we eliminated
15654 zero above. We only want to wind up preferring 80387 registers if
15655 we plan on doing computation with them. */
15657 && (TARGET_MIX_SSE_I387
15658 || !(TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (x))))
15659 && standard_80387_constant_p (x))
15661 /* Limit class to non-sse. */
15662 if (class == FLOAT_SSE_REGS)
15664 if (class == FP_TOP_SSE_REGS)
15666 if (class == FP_SECOND_SSE_REGS)
15667 return FP_SECOND_REG;
15668 if (class == FLOAT_INT_REGS || class == FLOAT_REGS)
15674 if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x))
15676 if (MAYBE_SSE_CLASS_P (class) && CONSTANT_P (x))
15679 /* Generally when we see PLUS here, it's the function invariant
15680 (plus soft-fp const_int). Which can only be computed into general
15682 if (GET_CODE (x) == PLUS)
15683 return reg_class_subset_p (class, GENERAL_REGS) ? class : NO_REGS;
15685 /* QImode constants are easy to load, but non-constant QImode data
15686 must go into Q_REGS. */
15687 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
15689 if (reg_class_subset_p (class, Q_REGS))
15691 if (reg_class_subset_p (Q_REGS, class))
15699 /* If we are copying between general and FP registers, we need a memory
15700 location. The same is true for SSE and MMX registers.
15702 The macro can't work reliably when one of the CLASSES is class containing
15703 registers from multiple units (SSE, MMX, integer). We avoid this by never
15704 combining those units in single alternative in the machine description.
15705 Ensure that this constraint holds to avoid unexpected surprises.
15707 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
15708 enforce these sanity checks. */
15711 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
15712 enum machine_mode mode, int strict)
15714 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
15715 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
15716 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
15717 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
15718 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
15719 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
15721 gcc_assert (!strict);
15725 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
15728 /* ??? This is a lie. We do have moves between mmx/general, and for
15729 mmx/sse2. But by saying we need secondary memory we discourage the
15730 register allocator from using the mmx registers unless needed. */
15731 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
15734 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
15736 /* SSE1 doesn't have any direct moves from other classes. */
15740 /* If the target says that inter-unit moves are more expensive
15741 than moving through memory, then don't generate them. */
15742 if (!TARGET_INTER_UNIT_MOVES && !optimize_size)
15745 /* Between SSE and general, we have moves no larger than word size. */
15746 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
15749 /* ??? For the cost of one register reformat penalty, we could use
15750 the same instructions to move SFmode and DFmode data, but the
15751 relevant move patterns don't support those alternatives. */
15752 if (mode == SFmode || mode == DFmode)
15759 /* Return true if the registers in CLASS cannot represent the change from
15760 modes FROM to TO. */
15763 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
15764 enum reg_class class)
15769 /* x87 registers can't do subreg at all, as all values are reformatted
15770 to extended precision. */
15771 if (MAYBE_FLOAT_CLASS_P (class))
15774 if (MAYBE_SSE_CLASS_P (class) || MAYBE_MMX_CLASS_P (class))
15776 /* Vector registers do not support QI or HImode loads. If we don't
15777 disallow a change to these modes, reload will assume it's ok to
15778 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
15779 the vec_dupv4hi pattern. */
15780 if (GET_MODE_SIZE (from) < 4)
15783 /* Vector registers do not support subreg with nonzero offsets, which
15784 are otherwise valid for integer registers. Since we can't see
15785 whether we have a nonzero offset from here, prohibit all
15786 nonparadoxical subregs changing size. */
15787 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
15794 /* Return the cost of moving data from a register in class CLASS1 to
15795 one in class CLASS2.
15797 It is not required that the cost always equal 2 when FROM is the same as TO;
15798 on some machines it is expensive to move between registers if they are not
15799 general registers. */
15802 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
15803 enum reg_class class2)
15805 /* In case we require secondary memory, compute cost of the store followed
15806 by load. In order to avoid bad register allocation choices, we need
15807 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
15809 if (ix86_secondary_memory_needed (class1, class2, mode, 0))
15813 cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
15814 MEMORY_MOVE_COST (mode, class1, 1));
15815 cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
15816 MEMORY_MOVE_COST (mode, class2, 1));
15818 /* In case of copying from general_purpose_register we may emit multiple
15819 stores followed by single load causing memory size mismatch stall.
15820 Count this as arbitrarily high cost of 20. */
15821 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
15824 /* In the case of FP/MMX moves, the registers actually overlap, and we
15825 have to switch modes in order to treat them differently. */
15826 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
15827 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
15833 /* Moves between SSE/MMX and integer unit are expensive. */
15834 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
15835 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
15836 return ix86_cost->mmxsse_to_integer;
15837 if (MAYBE_FLOAT_CLASS_P (class1))
15838 return ix86_cost->fp_move;
15839 if (MAYBE_SSE_CLASS_P (class1))
15840 return ix86_cost->sse_move;
15841 if (MAYBE_MMX_CLASS_P (class1))
15842 return ix86_cost->mmx_move;
15846 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
15849 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
15851 /* Flags and only flags can only hold CCmode values. */
15852 if (CC_REGNO_P (regno))
15853 return GET_MODE_CLASS (mode) == MODE_CC;
15854 if (GET_MODE_CLASS (mode) == MODE_CC
15855 || GET_MODE_CLASS (mode) == MODE_RANDOM
15856 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
15858 if (FP_REGNO_P (regno))
15859 return VALID_FP_MODE_P (mode);
15860 if (SSE_REGNO_P (regno))
15862 /* We implement the move patterns for all vector modes into and
15863 out of SSE registers, even when no operation instructions
15865 return (VALID_SSE_REG_MODE (mode)
15866 || VALID_SSE2_REG_MODE (mode)
15867 || VALID_MMX_REG_MODE (mode)
15868 || VALID_MMX_REG_MODE_3DNOW (mode));
15870 if (MMX_REGNO_P (regno))
15872 /* We implement the move patterns for 3DNOW modes even in MMX mode,
15873 so if the register is available at all, then we can move data of
15874 the given mode into or out of it. */
15875 return (VALID_MMX_REG_MODE (mode)
15876 || VALID_MMX_REG_MODE_3DNOW (mode));
15879 if (mode == QImode)
15881 /* Take care for QImode values - they can be in non-QI regs,
15882 but then they do cause partial register stalls. */
15883 if (regno < 4 || TARGET_64BIT)
15885 if (!TARGET_PARTIAL_REG_STALL)
15887 return reload_in_progress || reload_completed;
15889 /* We handle both integer and floats in the general purpose registers. */
15890 else if (VALID_INT_MODE_P (mode))
15892 else if (VALID_FP_MODE_P (mode))
15894 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
15895 on to use that value in smaller contexts, this can easily force a
15896 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
15897 supporting DImode, allow it. */
15898 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
15904 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
15905 tieable integer mode. */
15908 ix86_tieable_integer_mode_p (enum machine_mode mode)
15917 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
15920 return TARGET_64BIT;
15927 /* Return true if MODE1 is accessible in a register that can hold MODE2
15928 without copying. That is, all register classes that can hold MODE2
15929 can also hold MODE1. */
15932 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
15934 if (mode1 == mode2)
15937 if (ix86_tieable_integer_mode_p (mode1)
15938 && ix86_tieable_integer_mode_p (mode2))
15941 /* MODE2 being XFmode implies fp stack or general regs, which means we
15942 can tie any smaller floating point modes to it. Note that we do not
15943 tie this with TFmode. */
15944 if (mode2 == XFmode)
15945 return mode1 == SFmode || mode1 == DFmode;
15947 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
15948 that we can tie it with SFmode. */
15949 if (mode2 == DFmode)
15950 return mode1 == SFmode;
15952 /* If MODE2 is only appropriate for an SSE register, then tie with
15953 any other mode acceptable to SSE registers. */
15954 if (GET_MODE_SIZE (mode2) >= 8
15955 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
15956 return ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1);
15958 /* If MODE2 is appropriate for an MMX (or SSE) register, then tie
15959 with any other mode acceptable to MMX registers. */
15960 if (GET_MODE_SIZE (mode2) == 8
15961 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
15962 return ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1);
15967 /* Return the cost of moving data of mode M between a
15968 register and memory. A value of 2 is the default; this cost is
15969 relative to those in `REGISTER_MOVE_COST'.
15971 If moving between registers and memory is more expensive than
15972 between two registers, you should define this macro to express the
15975 Model also increased moving costs of QImode registers in non
15979 ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
15981 if (FLOAT_CLASS_P (class))
15998 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
16000 if (SSE_CLASS_P (class))
16003 switch (GET_MODE_SIZE (mode))
16017 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
16019 if (MMX_CLASS_P (class))
16022 switch (GET_MODE_SIZE (mode))
16033 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
16035 switch (GET_MODE_SIZE (mode))
16039 return (Q_CLASS_P (class) ? ix86_cost->int_load[0]
16040 : ix86_cost->movzbl_load);
16042 return (Q_CLASS_P (class) ? ix86_cost->int_store[0]
16043 : ix86_cost->int_store[0] + 4);
16046 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
16048 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
16049 if (mode == TFmode)
16051 return ((in ? ix86_cost->int_load[2] : ix86_cost->int_store[2])
16052 * (((int) GET_MODE_SIZE (mode)
16053 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
16057 /* Compute a (partial) cost for rtx X. Return true if the complete
16058 cost has been computed, and false if subexpressions should be
16059 scanned. In either case, *TOTAL contains the cost result. */
16062 ix86_rtx_costs (rtx x, int code, int outer_code, int *total)
16064 enum machine_mode mode = GET_MODE (x);
16072 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
16074 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
16076 else if (flag_pic && SYMBOLIC_CONST (x)
16078 || (!GET_CODE (x) != LABEL_REF
16079 && (GET_CODE (x) != SYMBOL_REF
16080 || !SYMBOL_REF_LOCAL_P (x)))))
16087 if (mode == VOIDmode)
16090 switch (standard_80387_constant_p (x))
16095 default: /* Other constants */
16100 /* Start with (MEM (SYMBOL_REF)), since that's where
16101 it'll probably end up. Add a penalty for size. */
16102 *total = (COSTS_N_INSNS (1)
16103 + (flag_pic != 0 && !TARGET_64BIT)
16104 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
16110 /* The zero extensions is often completely free on x86_64, so make
16111 it as cheap as possible. */
16112 if (TARGET_64BIT && mode == DImode
16113 && GET_MODE (XEXP (x, 0)) == SImode)
16115 else if (TARGET_ZERO_EXTEND_WITH_AND)
16116 *total = COSTS_N_INSNS (ix86_cost->add);
16118 *total = COSTS_N_INSNS (ix86_cost->movzx);
16122 *total = COSTS_N_INSNS (ix86_cost->movsx);
16126 if (GET_CODE (XEXP (x, 1)) == CONST_INT
16127 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
16129 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16132 *total = COSTS_N_INSNS (ix86_cost->add);
16135 if ((value == 2 || value == 3)
16136 && ix86_cost->lea <= ix86_cost->shift_const)
16138 *total = COSTS_N_INSNS (ix86_cost->lea);
16148 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
16150 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16152 if (INTVAL (XEXP (x, 1)) > 32)
16153 *total = COSTS_N_INSNS(ix86_cost->shift_const + 2);
16155 *total = COSTS_N_INSNS(ix86_cost->shift_const * 2);
16159 if (GET_CODE (XEXP (x, 1)) == AND)
16160 *total = COSTS_N_INSNS(ix86_cost->shift_var * 2);
16162 *total = COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2);
16167 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16168 *total = COSTS_N_INSNS (ix86_cost->shift_const);
16170 *total = COSTS_N_INSNS (ix86_cost->shift_var);
16175 if (FLOAT_MODE_P (mode))
16177 *total = COSTS_N_INSNS (ix86_cost->fmul);
16182 rtx op0 = XEXP (x, 0);
16183 rtx op1 = XEXP (x, 1);
16185 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
16187 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
16188 for (nbits = 0; value != 0; value &= value - 1)
16192 /* This is arbitrary. */
16195 /* Compute costs correctly for widening multiplication. */
16196 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
16197 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
16198 == GET_MODE_SIZE (mode))
16200 int is_mulwiden = 0;
16201 enum machine_mode inner_mode = GET_MODE (op0);
16203 if (GET_CODE (op0) == GET_CODE (op1))
16204 is_mulwiden = 1, op1 = XEXP (op1, 0);
16205 else if (GET_CODE (op1) == CONST_INT)
16207 if (GET_CODE (op0) == SIGN_EXTEND)
16208 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
16211 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
16215 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
16218 *total = COSTS_N_INSNS (ix86_cost->mult_init[MODE_INDEX (mode)]
16219 + nbits * ix86_cost->mult_bit)
16220 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code);
16229 if (FLOAT_MODE_P (mode))
16230 *total = COSTS_N_INSNS (ix86_cost->fdiv);
16232 *total = COSTS_N_INSNS (ix86_cost->divide[MODE_INDEX (mode)]);
16236 if (FLOAT_MODE_P (mode))
16237 *total = COSTS_N_INSNS (ix86_cost->fadd);
16238 else if (GET_MODE_CLASS (mode) == MODE_INT
16239 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
16241 if (GET_CODE (XEXP (x, 0)) == PLUS
16242 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
16243 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
16244 && CONSTANT_P (XEXP (x, 1)))
16246 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
16247 if (val == 2 || val == 4 || val == 8)
16249 *total = COSTS_N_INSNS (ix86_cost->lea);
16250 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
16251 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
16253 *total += rtx_cost (XEXP (x, 1), outer_code);
16257 else if (GET_CODE (XEXP (x, 0)) == MULT
16258 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
16260 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
16261 if (val == 2 || val == 4 || val == 8)
16263 *total = COSTS_N_INSNS (ix86_cost->lea);
16264 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
16265 *total += rtx_cost (XEXP (x, 1), outer_code);
16269 else if (GET_CODE (XEXP (x, 0)) == PLUS)
16271 *total = COSTS_N_INSNS (ix86_cost->lea);
16272 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
16273 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
16274 *total += rtx_cost (XEXP (x, 1), outer_code);
16281 if (FLOAT_MODE_P (mode))
16283 *total = COSTS_N_INSNS (ix86_cost->fadd);
16291 if (!TARGET_64BIT && mode == DImode)
16293 *total = (COSTS_N_INSNS (ix86_cost->add) * 2
16294 + (rtx_cost (XEXP (x, 0), outer_code)
16295 << (GET_MODE (XEXP (x, 0)) != DImode))
16296 + (rtx_cost (XEXP (x, 1), outer_code)
16297 << (GET_MODE (XEXP (x, 1)) != DImode)));
16303 if (FLOAT_MODE_P (mode))
16305 *total = COSTS_N_INSNS (ix86_cost->fchs);
16311 if (!TARGET_64BIT && mode == DImode)
16312 *total = COSTS_N_INSNS (ix86_cost->add * 2);
16314 *total = COSTS_N_INSNS (ix86_cost->add);
16318 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
16319 && XEXP (XEXP (x, 0), 1) == const1_rtx
16320 && GET_CODE (XEXP (XEXP (x, 0), 2)) == CONST_INT
16321 && XEXP (x, 1) == const0_rtx)
16323 /* This kind of construct is implemented using test[bwl].
16324 Treat it as if we had an AND. */
16325 *total = (COSTS_N_INSNS (ix86_cost->add)
16326 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
16327 + rtx_cost (const1_rtx, outer_code));
16333 if (!TARGET_SSE_MATH
16335 || (mode == DFmode && !TARGET_SSE2))
16340 if (FLOAT_MODE_P (mode))
16341 *total = COSTS_N_INSNS (ix86_cost->fabs);
16345 if (FLOAT_MODE_P (mode))
16346 *total = COSTS_N_INSNS (ix86_cost->fsqrt);
16350 if (XINT (x, 1) == UNSPEC_TP)
16361 static int current_machopic_label_num;
16363 /* Given a symbol name and its associated stub, write out the
16364 definition of the stub. */
16367 machopic_output_stub (FILE *file, const char *symb, const char *stub)
16369 unsigned int length;
16370 char *binder_name, *symbol_name, lazy_ptr_name[32];
16371 int label = ++current_machopic_label_num;
16373 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16374 symb = (*targetm.strip_name_encoding) (symb);
16376 length = strlen (stub);
16377 binder_name = alloca (length + 32);
16378 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
16380 length = strlen (symb);
16381 symbol_name = alloca (length + 32);
16382 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16384 sprintf (lazy_ptr_name, "L%d$lz", label);
16387 machopic_picsymbol_stub_section ();
16389 machopic_symbol_stub_section ();
16391 fprintf (file, "%s:\n", stub);
16392 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16396 fprintf (file, "\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n", label, label);
16397 fprintf (file, "\tmovl %s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
16398 fprintf (file, "\tjmp %%edx\n");
16401 fprintf (file, "\tjmp *%s\n", lazy_ptr_name);
16403 fprintf (file, "%s:\n", binder_name);
16407 fprintf (file, "\tlea %s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
16408 fprintf (file, "\tpushl %%eax\n");
16411 fprintf (file, "\t pushl $%s\n", lazy_ptr_name);
16413 fprintf (file, "\tjmp dyld_stub_binding_helper\n");
16415 machopic_lazy_symbol_ptr_section ();
16416 fprintf (file, "%s:\n", lazy_ptr_name);
16417 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16418 fprintf (file, "\t.long %s\n", binder_name);
16420 #endif /* TARGET_MACHO */
16422 /* Order the registers for register allocator. */
16425 x86_order_regs_for_local_alloc (void)
16430 /* First allocate the local general purpose registers. */
16431 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16432 if (GENERAL_REGNO_P (i) && call_used_regs[i])
16433 reg_alloc_order [pos++] = i;
16435 /* Global general purpose registers. */
16436 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16437 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
16438 reg_alloc_order [pos++] = i;
16440 /* x87 registers come first in case we are doing FP math
16442 if (!TARGET_SSE_MATH)
16443 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
16444 reg_alloc_order [pos++] = i;
16446 /* SSE registers. */
16447 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
16448 reg_alloc_order [pos++] = i;
16449 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
16450 reg_alloc_order [pos++] = i;
16452 /* x87 registers. */
16453 if (TARGET_SSE_MATH)
16454 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
16455 reg_alloc_order [pos++] = i;
16457 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
16458 reg_alloc_order [pos++] = i;
16460 /* Initialize the rest of array as we do not allocate some registers
16462 while (pos < FIRST_PSEUDO_REGISTER)
16463 reg_alloc_order [pos++] = 0;
16466 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
16467 struct attribute_spec.handler. */
16469 ix86_handle_struct_attribute (tree *node, tree name,
16470 tree args ATTRIBUTE_UNUSED,
16471 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
16474 if (DECL_P (*node))
16476 if (TREE_CODE (*node) == TYPE_DECL)
16477 type = &TREE_TYPE (*node);
16482 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
16483 || TREE_CODE (*type) == UNION_TYPE)))
16485 warning (OPT_Wattributes, "%qs attribute ignored",
16486 IDENTIFIER_POINTER (name));
16487 *no_add_attrs = true;
16490 else if ((is_attribute_p ("ms_struct", name)
16491 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
16492 || ((is_attribute_p ("gcc_struct", name)
16493 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
16495 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
16496 IDENTIFIER_POINTER (name));
16497 *no_add_attrs = true;
16504 ix86_ms_bitfield_layout_p (tree record_type)
16506 return (TARGET_MS_BITFIELD_LAYOUT &&
16507 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
16508 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
16511 /* Returns an expression indicating where the this parameter is
16512 located on entry to the FUNCTION. */
16515 x86_this_parameter (tree function)
16517 tree type = TREE_TYPE (function);
16521 int n = aggregate_value_p (TREE_TYPE (type), type) != 0;
16522 return gen_rtx_REG (DImode, x86_64_int_parameter_registers[n]);
16525 if (ix86_function_regparm (type, function) > 0)
16529 parm = TYPE_ARG_TYPES (type);
16530 /* Figure out whether or not the function has a variable number of
16532 for (; parm; parm = TREE_CHAIN (parm))
16533 if (TREE_VALUE (parm) == void_type_node)
16535 /* If not, the this parameter is in the first argument. */
16539 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
16541 return gen_rtx_REG (SImode, regno);
16545 if (aggregate_value_p (TREE_TYPE (type), type))
16546 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));
16548 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));
16551 /* Determine whether x86_output_mi_thunk can succeed. */
16554 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
16555 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
16556 HOST_WIDE_INT vcall_offset, tree function)
16558 /* 64-bit can handle anything. */
16562 /* For 32-bit, everything's fine if we have one free register. */
16563 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
16566 /* Need a free register for vcall_offset. */
16570 /* Need a free register for GOT references. */
16571 if (flag_pic && !(*targetm.binds_local_p) (function))
16574 /* Otherwise ok. */
16578 /* Output the assembler code for a thunk function. THUNK_DECL is the
16579 declaration for the thunk function itself, FUNCTION is the decl for
16580 the target function. DELTA is an immediate constant offset to be
16581 added to THIS. If VCALL_OFFSET is nonzero, the word at
16582 *(*this + vcall_offset) should be added to THIS. */
16585 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
16586 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
16587 HOST_WIDE_INT vcall_offset, tree function)
16590 rtx this = x86_this_parameter (function);
16593 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
16594 pull it in now and let DELTA benefit. */
16597 else if (vcall_offset)
16599 /* Put the this parameter into %eax. */
16601 xops[1] = this_reg = gen_rtx_REG (Pmode, 0);
16602 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16605 this_reg = NULL_RTX;
16607 /* Adjust the this parameter by a fixed constant. */
16610 xops[0] = GEN_INT (delta);
16611 xops[1] = this_reg ? this_reg : this;
16614 if (!x86_64_general_operand (xops[0], DImode))
16616 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
16618 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
16622 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
16625 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
16628 /* Adjust the this parameter by a value stored in the vtable. */
16632 tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
16635 int tmp_regno = 2 /* ECX */;
16636 if (lookup_attribute ("fastcall",
16637 TYPE_ATTRIBUTES (TREE_TYPE (function))))
16638 tmp_regno = 0 /* EAX */;
16639 tmp = gen_rtx_REG (SImode, tmp_regno);
16642 xops[0] = gen_rtx_MEM (Pmode, this_reg);
16645 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
16647 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16649 /* Adjust the this parameter. */
16650 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
16651 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
16653 rtx tmp2 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
16654 xops[0] = GEN_INT (vcall_offset);
16656 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
16657 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
16659 xops[1] = this_reg;
16661 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
16663 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
16666 /* If necessary, drop THIS back to its stack slot. */
16667 if (this_reg && this_reg != this)
16669 xops[0] = this_reg;
16671 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
16674 xops[0] = XEXP (DECL_RTL (function), 0);
16677 if (!flag_pic || (*targetm.binds_local_p) (function))
16678 output_asm_insn ("jmp\t%P0", xops);
16681 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
16682 tmp = gen_rtx_CONST (Pmode, tmp);
16683 tmp = gen_rtx_MEM (QImode, tmp);
16685 output_asm_insn ("jmp\t%A0", xops);
16690 if (!flag_pic || (*targetm.binds_local_p) (function))
16691 output_asm_insn ("jmp\t%P0", xops);
16696 rtx sym_ref = XEXP (DECL_RTL (function), 0);
16697 tmp = (gen_rtx_SYMBOL_REF
16699 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
16700 tmp = gen_rtx_MEM (QImode, tmp);
16702 output_asm_insn ("jmp\t%0", xops);
16705 #endif /* TARGET_MACHO */
16707 tmp = gen_rtx_REG (SImode, 2 /* ECX */);
16708 output_set_got (tmp);
16711 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
16712 output_asm_insn ("jmp\t{*}%1", xops);
16718 x86_file_start (void)
16720 default_file_start ();
16721 if (X86_FILE_START_VERSION_DIRECTIVE)
16722 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
16723 if (X86_FILE_START_FLTUSED)
16724 fputs ("\t.global\t__fltused\n", asm_out_file);
16725 if (ix86_asm_dialect == ASM_INTEL)
16726 fputs ("\t.intel_syntax\n", asm_out_file);
16730 x86_field_alignment (tree field, int computed)
16732 enum machine_mode mode;
16733 tree type = TREE_TYPE (field);
16735 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
16737 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
16738 ? get_inner_array_type (type) : type);
16739 if (mode == DFmode || mode == DCmode
16740 || GET_MODE_CLASS (mode) == MODE_INT
16741 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
16742 return MIN (32, computed);
16746 /* Output assembler code to FILE to increment profiler label # LABELNO
16747 for profiling a function entry. */
16749 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
16754 #ifndef NO_PROFILE_COUNTERS
16755 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
16757 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
16761 #ifndef NO_PROFILE_COUNTERS
16762 fprintf (file, "\tmovq\t$%sP%d,%%r11\n", LPREFIX, labelno);
16764 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
16768 #ifndef NO_PROFILE_COUNTERS
16769 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
16770 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
16772 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
16776 #ifndef NO_PROFILE_COUNTERS
16777 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
16778 PROFILE_COUNT_REGISTER);
16780 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
16784 /* We don't have exact information about the insn sizes, but we may assume
16785 quite safely that we are informed about all 1 byte insns and memory
16786 address sizes. This is enough to eliminate unnecessary padding in
16790 min_insn_size (rtx insn)
16794 if (!INSN_P (insn) || !active_insn_p (insn))
16797 /* Discard alignments we've emit and jump instructions. */
16798 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
16799 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
16801 if (GET_CODE (insn) == JUMP_INSN
16802 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
16803 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
16806 /* Important case - calls are always 5 bytes.
16807 It is common to have many calls in the row. */
16808 if (GET_CODE (insn) == CALL_INSN
16809 && symbolic_reference_mentioned_p (PATTERN (insn))
16810 && !SIBLING_CALL_P (insn))
16812 if (get_attr_length (insn) <= 1)
16815 /* For normal instructions we may rely on the sizes of addresses
16816 and the presence of symbol to require 4 bytes of encoding.
16817 This is not the case for jumps where references are PC relative. */
16818 if (GET_CODE (insn) != JUMP_INSN)
16820 l = get_attr_length_address (insn);
16821 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
16830 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
16834 ix86_avoid_jump_misspredicts (void)
16836 rtx insn, start = get_insns ();
16837 int nbytes = 0, njumps = 0;
16840 /* Look for all minimal intervals of instructions containing 4 jumps.
16841 The intervals are bounded by START and INSN. NBYTES is the total
16842 size of instructions in the interval including INSN and not including
16843 START. When the NBYTES is smaller than 16 bytes, it is possible
16844 that the end of START and INSN ends up in the same 16byte page.
16846 The smallest offset in the page INSN can start is the case where START
16847 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
16848 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
16850 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16853 nbytes += min_insn_size (insn);
16855 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
16856 INSN_UID (insn), min_insn_size (insn));
16857 if ((GET_CODE (insn) == JUMP_INSN
16858 && GET_CODE (PATTERN (insn)) != ADDR_VEC
16859 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
16860 || GET_CODE (insn) == CALL_INSN)
16867 start = NEXT_INSN (start);
16868 if ((GET_CODE (start) == JUMP_INSN
16869 && GET_CODE (PATTERN (start)) != ADDR_VEC
16870 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
16871 || GET_CODE (start) == CALL_INSN)
16872 njumps--, isjump = 1;
16875 nbytes -= min_insn_size (start);
16877 gcc_assert (njumps >= 0);
16879 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
16880 INSN_UID (start), INSN_UID (insn), nbytes);
16882 if (njumps == 3 && isjump && nbytes < 16)
16884 int padsize = 15 - nbytes + min_insn_size (insn);
16887 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
16888 INSN_UID (insn), padsize);
16889 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
16894 /* AMD Athlon works faster
16895 when RET is not destination of conditional jump or directly preceded
16896 by other jump instruction. We avoid the penalty by inserting NOP just
16897 before the RET instructions in such cases. */
16899 ix86_pad_returns (void)
16904 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
16906 basic_block bb = e->src;
16907 rtx ret = BB_END (bb);
16909 bool replace = false;
16911 if (GET_CODE (ret) != JUMP_INSN || GET_CODE (PATTERN (ret)) != RETURN
16912 || !maybe_hot_bb_p (bb))
16914 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
16915 if (active_insn_p (prev) || GET_CODE (prev) == CODE_LABEL)
16917 if (prev && GET_CODE (prev) == CODE_LABEL)
16922 FOR_EACH_EDGE (e, ei, bb->preds)
16923 if (EDGE_FREQUENCY (e) && e->src->index >= 0
16924 && !(e->flags & EDGE_FALLTHRU))
16929 prev = prev_active_insn (ret);
16931 && ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev))
16932 || GET_CODE (prev) == CALL_INSN))
16934 /* Empty functions get branch mispredict even when the jump destination
16935 is not visible to us. */
16936 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
16941 emit_insn_before (gen_return_internal_long (), ret);
16947 /* Implement machine specific optimizations. We implement padding of returns
16948 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
16952 if (TARGET_ATHLON_K8 && optimize && !optimize_size)
16953 ix86_pad_returns ();
16954 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
16955 ix86_avoid_jump_misspredicts ();
16958 /* Return nonzero when QImode register that must be represented via REX prefix
16961 x86_extended_QIreg_mentioned_p (rtx insn)
16964 extract_insn_cached (insn);
16965 for (i = 0; i < recog_data.n_operands; i++)
16966 if (REG_P (recog_data.operand[i])
16967 && REGNO (recog_data.operand[i]) >= 4)
16972 /* Return nonzero when P points to register encoded via REX prefix.
16973 Called via for_each_rtx. */
16975 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
16977 unsigned int regno;
16980 regno = REGNO (*p);
16981 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
16984 /* Return true when INSN mentions register that must be encoded using REX
16987 x86_extended_reg_mentioned_p (rtx insn)
16989 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
16992 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
16993 optabs would emit if we didn't have TFmode patterns. */
16996 x86_emit_floatuns (rtx operands[2])
16998 rtx neglab, donelab, i0, i1, f0, in, out;
16999 enum machine_mode mode, inmode;
17001 inmode = GET_MODE (operands[1]);
17002 gcc_assert (inmode == SImode || inmode == DImode);
17005 in = force_reg (inmode, operands[1]);
17006 mode = GET_MODE (out);
17007 neglab = gen_label_rtx ();
17008 donelab = gen_label_rtx ();
17009 i1 = gen_reg_rtx (Pmode);
17010 f0 = gen_reg_rtx (mode);
17012 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, Pmode, 0, neglab);
17014 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
17015 emit_jump_insn (gen_jump (donelab));
17018 emit_label (neglab);
17020 i0 = expand_simple_binop (Pmode, LSHIFTRT, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17021 i1 = expand_simple_binop (Pmode, AND, in, const1_rtx, NULL, 1, OPTAB_DIRECT);
17022 i0 = expand_simple_binop (Pmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
17023 expand_float (f0, i0, 0);
17024 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
17026 emit_label (donelab);
17029 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17030 with all elements equal to VAR. Return true if successful. */
17033 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
17034 rtx target, rtx val)
17036 enum machine_mode smode, wsmode, wvmode;
17043 if (!mmx_ok && !TARGET_SSE)
17051 val = force_reg (GET_MODE_INNER (mode), val);
17052 x = gen_rtx_VEC_DUPLICATE (mode, val);
17053 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17059 if (TARGET_SSE || TARGET_3DNOW_A)
17061 val = gen_lowpart (SImode, val);
17062 x = gen_rtx_TRUNCATE (HImode, val);
17063 x = gen_rtx_VEC_DUPLICATE (mode, x);
17064 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17093 /* Replicate the value once into the next wider mode and recurse. */
17094 val = convert_modes (wsmode, smode, val, true);
17095 x = expand_simple_binop (wsmode, ASHIFT, val,
17096 GEN_INT (GET_MODE_BITSIZE (smode)),
17097 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17098 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
17100 x = gen_reg_rtx (wvmode);
17101 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
17102 gcc_unreachable ();
17103 emit_move_insn (target, gen_lowpart (mode, x));
17111 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17112 whose low element is VAR, and other elements are zero. Return true
17116 ix86_expand_vector_init_low_nonzero (bool mmx_ok, enum machine_mode mode,
17117 rtx target, rtx var)
17119 enum machine_mode vsimode;
17126 if (!mmx_ok && !TARGET_SSE)
17132 var = force_reg (GET_MODE_INNER (mode), var);
17133 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
17134 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17139 var = force_reg (GET_MODE_INNER (mode), var);
17140 x = gen_rtx_VEC_DUPLICATE (mode, var);
17141 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
17142 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17147 vsimode = V4SImode;
17153 vsimode = V2SImode;
17156 /* Zero extend the variable element to SImode and recurse. */
17157 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
17159 x = gen_reg_rtx (vsimode);
17160 if (!ix86_expand_vector_init_low_nonzero (mmx_ok, vsimode, x, var))
17161 gcc_unreachable ();
17163 emit_move_insn (target, gen_lowpart (mode, x));
17171 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
17172 consisting of the values in VALS. It is known that all elements
17173 except ONE_VAR are constants. Return true if successful. */
17176 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
17177 rtx target, rtx vals, int one_var)
17179 rtx var = XVECEXP (vals, 0, one_var);
17180 enum machine_mode wmode;
17183 XVECEXP (vals, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
17184 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
17192 /* For the two element vectors, it's just as easy to use
17193 the general case. */
17209 /* There's no way to set one QImode entry easily. Combine
17210 the variable value with its adjacent constant value, and
17211 promote to an HImode set. */
17212 x = XVECEXP (vals, 0, one_var ^ 1);
17215 var = convert_modes (HImode, QImode, var, true);
17216 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
17217 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17218 x = GEN_INT (INTVAL (x) & 0xff);
17222 var = convert_modes (HImode, QImode, var, true);
17223 x = gen_int_mode (INTVAL (x) << 8, HImode);
17225 if (x != const0_rtx)
17226 var = expand_simple_binop (HImode, IOR, var, x, var,
17227 1, OPTAB_LIB_WIDEN);
17229 x = gen_reg_rtx (wmode);
17230 emit_move_insn (x, gen_lowpart (wmode, const_vec));
17231 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
17233 emit_move_insn (target, gen_lowpart (mode, x));
17240 emit_move_insn (target, const_vec);
17241 ix86_expand_vector_set (mmx_ok, target, var, one_var);
17245 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
17246 all values variable, and none identical. */
17249 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
17250 rtx target, rtx vals)
17252 enum machine_mode half_mode = GET_MODE_INNER (mode);
17253 rtx op0 = NULL, op1 = NULL;
17254 bool use_vec_concat = false;
17260 if (!mmx_ok && !TARGET_SSE)
17266 /* For the two element vectors, we always implement VEC_CONCAT. */
17267 op0 = XVECEXP (vals, 0, 0);
17268 op1 = XVECEXP (vals, 0, 1);
17269 use_vec_concat = true;
17273 half_mode = V2SFmode;
17276 half_mode = V2SImode;
17282 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
17283 Recurse to load the two halves. */
17285 op0 = gen_reg_rtx (half_mode);
17286 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
17287 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
17289 op1 = gen_reg_rtx (half_mode);
17290 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
17291 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
17293 use_vec_concat = true;
17304 gcc_unreachable ();
17307 if (use_vec_concat)
17309 if (!register_operand (op0, half_mode))
17310 op0 = force_reg (half_mode, op0);
17311 if (!register_operand (op1, half_mode))
17312 op1 = force_reg (half_mode, op1);
17314 emit_insn (gen_rtx_SET (VOIDmode, target,
17315 gen_rtx_VEC_CONCAT (mode, op0, op1)));
17319 int i, j, n_elts, n_words, n_elt_per_word;
17320 enum machine_mode inner_mode;
17321 rtx words[4], shift;
17323 inner_mode = GET_MODE_INNER (mode);
17324 n_elts = GET_MODE_NUNITS (mode);
17325 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
17326 n_elt_per_word = n_elts / n_words;
17327 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
17329 for (i = 0; i < n_words; ++i)
17331 rtx word = NULL_RTX;
17333 for (j = 0; j < n_elt_per_word; ++j)
17335 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
17336 elt = convert_modes (word_mode, inner_mode, elt, true);
17342 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
17343 word, 1, OPTAB_LIB_WIDEN);
17344 word = expand_simple_binop (word_mode, IOR, word, elt,
17345 word, 1, OPTAB_LIB_WIDEN);
17353 emit_move_insn (target, gen_lowpart (mode, words[0]));
17354 else if (n_words == 2)
17356 rtx tmp = gen_reg_rtx (mode);
17357 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
17358 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
17359 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
17360 emit_move_insn (target, tmp);
17362 else if (n_words == 4)
17364 rtx tmp = gen_reg_rtx (V4SImode);
17365 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
17366 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
17367 emit_move_insn (target, gen_lowpart (mode, tmp));
17370 gcc_unreachable ();
17374 /* Initialize vector TARGET via VALS. Suppress the use of MMX
17375 instructions unless MMX_OK is true. */
17378 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
17380 enum machine_mode mode = GET_MODE (target);
17381 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17382 int n_elts = GET_MODE_NUNITS (mode);
17383 int n_var = 0, one_var = -1;
17384 bool all_same = true, all_const_zero = true;
17388 for (i = 0; i < n_elts; ++i)
17390 x = XVECEXP (vals, 0, i);
17391 if (!CONSTANT_P (x))
17392 n_var++, one_var = i;
17393 else if (x != CONST0_RTX (inner_mode))
17394 all_const_zero = false;
17395 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17399 /* Constants are best loaded from the constant pool. */
17402 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
17406 /* If all values are identical, broadcast the value. */
17408 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
17409 XVECEXP (vals, 0, 0)))
17412 /* Values where only one field is non-constant are best loaded from
17413 the pool and overwritten via move later. */
17416 if (all_const_zero && one_var == 0
17417 && ix86_expand_vector_init_low_nonzero (mmx_ok, mode, target,
17418 XVECEXP (vals, 0, 0)))
17421 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
17425 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
17429 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
17431 enum machine_mode mode = GET_MODE (target);
17432 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17433 bool use_vec_merge = false;
17442 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
17443 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
17445 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
17447 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
17448 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17458 /* For the two element vectors, we implement a VEC_CONCAT with
17459 the extraction of the other element. */
17461 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
17462 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
17465 op0 = val, op1 = tmp;
17467 op0 = tmp, op1 = val;
17469 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
17470 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17478 use_vec_merge = true;
17482 /* tmp = target = A B C D */
17483 tmp = copy_to_reg (target);
17484 /* target = A A B B */
17485 emit_insn (gen_sse_unpcklps (target, target, target));
17486 /* target = X A B B */
17487 ix86_expand_vector_set (false, target, val, 0);
17488 /* target = A X C D */
17489 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17490 GEN_INT (1), GEN_INT (0),
17491 GEN_INT (2+4), GEN_INT (3+4)));
17495 /* tmp = target = A B C D */
17496 tmp = copy_to_reg (target);
17497 /* tmp = X B C D */
17498 ix86_expand_vector_set (false, tmp, val, 0);
17499 /* target = A B X D */
17500 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17501 GEN_INT (0), GEN_INT (1),
17502 GEN_INT (0+4), GEN_INT (3+4)));
17506 /* tmp = target = A B C D */
17507 tmp = copy_to_reg (target);
17508 /* tmp = X B C D */
17509 ix86_expand_vector_set (false, tmp, val, 0);
17510 /* target = A B X D */
17511 emit_insn (gen_sse_shufps_1 (target, target, tmp,
17512 GEN_INT (0), GEN_INT (1),
17513 GEN_INT (2+4), GEN_INT (0+4)));
17517 gcc_unreachable ();
17522 /* Element 0 handled by vec_merge below. */
17525 use_vec_merge = true;
17531 /* With SSE2, use integer shuffles to swap element 0 and ELT,
17532 store into element 0, then shuffle them back. */
17536 order[0] = GEN_INT (elt);
17537 order[1] = const1_rtx;
17538 order[2] = const2_rtx;
17539 order[3] = GEN_INT (3);
17540 order[elt] = const0_rtx;
17542 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
17543 order[1], order[2], order[3]));
17545 ix86_expand_vector_set (false, target, val, 0);
17547 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
17548 order[1], order[2], order[3]));
17552 /* For SSE1, we have to reuse the V4SF code. */
17553 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
17554 gen_lowpart (SFmode, val), elt);
17559 use_vec_merge = TARGET_SSE2;
17562 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
17573 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
17574 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
17575 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17579 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
17581 emit_move_insn (mem, target);
17583 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
17584 emit_move_insn (tmp, val);
17586 emit_move_insn (target, mem);
17591 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
17593 enum machine_mode mode = GET_MODE (vec);
17594 enum machine_mode inner_mode = GET_MODE_INNER (mode);
17595 bool use_vec_extr = false;
17608 use_vec_extr = true;
17620 tmp = gen_reg_rtx (mode);
17621 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
17622 GEN_INT (elt), GEN_INT (elt),
17623 GEN_INT (elt+4), GEN_INT (elt+4)));
17627 tmp = gen_reg_rtx (mode);
17628 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
17632 gcc_unreachable ();
17635 use_vec_extr = true;
17650 tmp = gen_reg_rtx (mode);
17651 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
17652 GEN_INT (elt), GEN_INT (elt),
17653 GEN_INT (elt), GEN_INT (elt)));
17657 tmp = gen_reg_rtx (mode);
17658 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
17662 gcc_unreachable ();
17665 use_vec_extr = true;
17670 /* For SSE1, we have to reuse the V4SF code. */
17671 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
17672 gen_lowpart (V4SFmode, vec), elt);
17678 use_vec_extr = TARGET_SSE2;
17681 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
17686 /* ??? Could extract the appropriate HImode element and shift. */
17693 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
17694 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
17696 /* Let the rtl optimizers know about the zero extension performed. */
17697 if (inner_mode == HImode)
17699 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
17700 target = gen_lowpart (SImode, target);
17703 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
17707 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
17709 emit_move_insn (mem, vec);
17711 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
17712 emit_move_insn (target, tmp);
17716 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
17717 pattern to reduce; DEST is the destination; IN is the input vector. */
17720 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
17722 rtx tmp1, tmp2, tmp3;
17724 tmp1 = gen_reg_rtx (V4SFmode);
17725 tmp2 = gen_reg_rtx (V4SFmode);
17726 tmp3 = gen_reg_rtx (V4SFmode);
17728 emit_insn (gen_sse_movhlps (tmp1, in, in));
17729 emit_insn (fn (tmp2, tmp1, in));
17731 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
17732 GEN_INT (1), GEN_INT (1),
17733 GEN_INT (1+4), GEN_INT (1+4)));
17734 emit_insn (fn (dest, tmp2, tmp3));
17737 /* Implements target hook vector_mode_supported_p. */
17739 ix86_vector_mode_supported_p (enum machine_mode mode)
17741 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
17743 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
17745 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
17747 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
17752 /* Worker function for TARGET_MD_ASM_CLOBBERS.
17754 We do this in the new i386 backend to maintain source compatibility
17755 with the old cc0-based compiler. */
17758 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
17759 tree inputs ATTRIBUTE_UNUSED,
17762 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
17764 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
17766 clobbers = tree_cons (NULL_TREE, build_string (7, "dirflag"),
17771 /* Return true if this goes in small data/bss. */
17774 ix86_in_large_data_p (tree exp)
17776 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
17779 /* Functions are never large data. */
17780 if (TREE_CODE (exp) == FUNCTION_DECL)
17783 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
17785 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
17786 if (strcmp (section, ".ldata") == 0
17787 || strcmp (section, ".lbss") == 0)
17793 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
17795 /* If this is an incomplete type with size 0, then we can't put it
17796 in data because it might be too big when completed. */
17797 if (!size || size > ix86_section_threshold)
17804 ix86_encode_section_info (tree decl, rtx rtl, int first)
17806 default_encode_section_info (decl, rtl, first);
17808 if (TREE_CODE (decl) == VAR_DECL
17809 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
17810 && ix86_in_large_data_p (decl))
17811 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
17814 /* Worker function for REVERSE_CONDITION. */
17817 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
17819 return (mode != CCFPmode && mode != CCFPUmode
17820 ? reverse_condition (code)
17821 : reverse_condition_maybe_unordered (code));
17824 /* Output code to perform an x87 FP register move, from OPERANDS[1]
17828 output_387_reg_move (rtx insn, rtx *operands)
17830 if (REG_P (operands[1])
17831 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
17833 if (REGNO (operands[0]) == FIRST_STACK_REG
17834 && TARGET_USE_FFREEP)
17835 return "ffreep\t%y0";
17836 return "fstp\t%y0";
17838 if (STACK_TOP_P (operands[0]))
17839 return "fld%z1\t%y1";
17843 /* Output code to perform a conditional jump to LABEL, if C2 flag in
17844 FP status register is set. */
17847 ix86_emit_fp_unordered_jump (rtx label)
17849 rtx reg = gen_reg_rtx (HImode);
17852 emit_insn (gen_x86_fnstsw_1 (reg));
17854 if (TARGET_USE_SAHF)
17856 emit_insn (gen_x86_sahf_1 (reg));
17858 temp = gen_rtx_REG (CCmode, FLAGS_REG);
17859 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
17863 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
17865 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
17866 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
17869 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
17870 gen_rtx_LABEL_REF (VOIDmode, label),
17872 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
17873 emit_jump_insn (temp);
17876 /* Output code to perform a log1p XFmode calculation. */
17878 void ix86_emit_i387_log1p (rtx op0, rtx op1)
17880 rtx label1 = gen_label_rtx ();
17881 rtx label2 = gen_label_rtx ();
17883 rtx tmp = gen_reg_rtx (XFmode);
17884 rtx tmp2 = gen_reg_rtx (XFmode);
17886 emit_insn (gen_absxf2 (tmp, op1));
17887 emit_insn (gen_cmpxf (tmp,
17888 CONST_DOUBLE_FROM_REAL_VALUE (
17889 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
17891 emit_jump_insn (gen_bge (label1));
17893 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
17894 emit_insn (gen_fyl2xp1_xf3 (op0, tmp2, op1));
17895 emit_jump (label2);
17897 emit_label (label1);
17898 emit_move_insn (tmp, CONST1_RTX (XFmode));
17899 emit_insn (gen_addxf3 (tmp, op1, tmp));
17900 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
17901 emit_insn (gen_fyl2x_xf3 (op0, tmp2, tmp));
17903 emit_label (label2);
17906 /* Solaris named-section hook. Parameters are as for
17907 named_section_real. */
17910 i386_solaris_elf_named_section (const char *name, unsigned int flags,
17913 /* With Binutils 2.15, the "@unwind" marker must be specified on
17914 every occurrence of the ".eh_frame" section, not just the first
17917 && strcmp (name, ".eh_frame") == 0)
17919 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
17920 flags & SECTION_WRITE ? "aw" : "a");
17923 default_elf_asm_named_section (name, flags, decl);
17926 /* Return the mangling of TYPE if it is an extended fundamental type. */
17928 static const char *
17929 ix86_mangle_fundamental_type (tree type)
17931 switch (TYPE_MODE (type))
17934 /* __float128 is "g". */
17937 /* "long double" or __float80 is "e". */
17944 /* For 32-bit code we can save PIC register setup by using
17945 __stack_chk_fail_local hidden function instead of calling
17946 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
17947 register, so it is better to call __stack_chk_fail directly. */
17950 ix86_stack_protect_fail (void)
17952 return TARGET_64BIT
17953 ? default_external_stack_protect_fail ()
17954 : default_hidden_stack_protect_fail ();
17957 /* Select a format to encode pointers in exception handling data. CODE
17958 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
17959 true if the symbol may be affected by dynamic relocations.
17961 ??? All x86 object file formats are capable of representing this.
17962 After all, the relocation needed is the same as for the call insn.
17963 Whether or not a particular assembler allows us to enter such, I
17964 guess we'll have to see. */
17966 asm_preferred_eh_data_format (int code, int global)
17970 int type = DW_EH_PE_sdata8;
17972 || ix86_cmodel == CM_SMALL_PIC
17973 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
17974 type = DW_EH_PE_sdata4;
17975 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
17977 if (ix86_cmodel == CM_SMALL
17978 || (ix86_cmodel == CM_MEDIUM && code))
17979 return DW_EH_PE_udata4;
17980 return DW_EH_PE_absptr;
17983 #include "gt-i386.h"