2 * Copyright (C) 2007 Free Software Foundation, Inc.
4 * This file is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2, or (at your option) any
9 * In addition to the permissions in the GNU General Public License, the
10 * Free Software Foundation gives you unlimited permission to link the
11 * compiled version of this file with other programs, and to distribute
12 * those programs without any restriction coming from the use of this
13 * file. (The General Public License restrictions do apply in other
14 * respects; for example, they cover modification of the file, and
15 * distribution when not linked into another program.)
17 * This file is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 51 Franklin Street, Fifth Floor,
25 * Boston, MA 02110-1301, USA.
27 * As a special exception, if you link this library with files
28 * compiled with GCC to produce an executable, this does not cause
29 * the resulting executable to be covered by the GNU General Public License.
30 * This exception does not however invalidate any other reasons why
31 * the executable file might be covered by the GNU General Public License.
35 #define bit_SSE3 (1 << 0)
36 #define bit_SSSE3 (1 << 9)
37 #define bit_CMPXCHG16B (1 << 13)
38 #define bit_SSE4_1 (1 << 19)
39 #define bit_SSE4_2 (1 << 20)
40 #define bit_POPCNT (1 << 23)
43 #define bit_CMPXCHG8B (1 << 8)
44 #define bit_CMOV (1 << 15)
45 #define bit_MMX (1 << 23)
46 #define bit_FXSAVE (1 << 24)
47 #define bit_SSE (1 << 25)
48 #define bit_SSE2 (1 << 26)
50 /* Extended Features */
52 #define bit_LAHF_LM (1 << 0)
53 #define bit_SSE4a (1 << 6)
56 #define bit_LM (1 << 29)
57 #define bit_3DNOWP (1 << 30)
58 #define bit_3DNOW (1 << 31)
61 #if defined(__i386__) && defined(__PIC__)
62 /* %ebx may be the PIC register. */
63 #define __cpuid(level, a, b, c, d) \
64 __asm__ ("xchgl\t%%ebx, %1\n\t" \
66 "xchgl\t%%ebx, %1\n\t" \
67 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
70 #define __cpuid(level, a, b, c, d) \
71 __asm__ ("cpuid\n\t" \
72 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
76 /* Return highest supported input value for cpuid instruction. ext can
77 be either 0x0 or 0x8000000 to return highest supported value for
78 basic or extended cpuid information. Function returns 0 if cpuid
79 is not supported or whatever cpuid returns in eax register. If sig
80 pointer is non-null, then first four bytes of the signature
81 (as found in ebx register) are returned in location pointed by sig. */
83 static __inline unsigned int
84 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
86 unsigned int __eax, __ebx, __ecx, __edx;
89 /* See if we can use cpuid. On AMD64 we always can. */
100 : "=&r" (__eax), "=&r" (__ebx)
103 if (!((__eax ^ __ebx) & 0x00200000))
107 /* Host supports cpuid. Return highest supported cpuid input value. */
108 __cpuid (__ext, __eax, __ebx, __ecx, __edx);
116 /* Return cpuid data for requested cpuid level, as found in returned
117 eax, ebx, ecx and edx registers. The function checks if cpuid is
118 supported and returns 1 for valid cpuid information or 0 for
119 unsupported cpuid level. All pointers are requred to be non-null. */
122 __get_cpuid (unsigned int __level,
123 unsigned int *__eax, unsigned int *__ebx,
124 unsigned int *__ecx, unsigned int *__edx)
126 unsigned int __ext = __level & 0x80000000;
128 if (__get_cpuid_max (__ext, 0) < __level)
131 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);