1 ;;- Machine description for GNU compiler -- System/370 version.
2 ;; Copyright (C) 1989, 1993, 1994, 1995 Free Software Foundation, Inc.
3 ;; Contributed by Jan Stein (jan@cd.chalmers.se).
4 ;; Modified for MVS C/370 by Dave Pitts (dpitts@nyx.cs.du.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
24 ;;- updates for most instructions.
27 ;; Special constraints for 370 machine description:
29 ;; a -- Any address register from 1 to 15.
30 ;; d -- Any register from 0 to 15.
31 ;; I -- An 8-bit constant (0..255).
32 ;; J -- A 12-bit constant (0..4095).
33 ;; K -- A 16-bit constant (-32768..32767).
35 ;; Special formats used for outputting 370 instructions.
37 ;; %B -- Print a constant byte integer.
38 ;; %H -- Print a signed 16-bit constant.
39 ;; %L -- Print least significant word of a CONST_DOUBLE.
40 ;; %M -- Print most significant word of a CONST_DOUBLE.
41 ;; %N -- Print next register (second word of a DImode reg).
42 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
43 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
44 ;; %X -- Print a constant byte integer in hex.
46 ;; We have a special constraint for pattern matching.
48 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
50 ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI
51 ;; or SS type instruction or a register
53 ;; For MVS C/370 we use the following stack locations for:
55 ;; 136 - internal function result buffer
56 ;; 140 - numeric conversion buffer
57 ;; 144 - pointer to internal function result buffer
58 ;; 148 - start of automatic variables and function arguments
60 ;; To support programs larger than a page, 4096 bytes, PAGE_REGISTER points
61 ;; to a page origin table, all internal labels are generated to reload the
62 ;; BASE_REGISTER knowing what page it is on and all branch instructions go
63 ;; directly to the target if it is known that the target is on the current
64 ;; page (essentially backward references). All forward references and off
65 ;; page references are handled by loading the address of target into a
66 ;; register and branching indirectly.
68 ;; Some *di patterns have been commented out per advice from RMS, as gcc
69 ;; will generate the right things to do.
73 ;;- Test instructions.
77 ; tstdi instruction pattern(s).
82 (match_operand:DI 0 "register_operand" "d"))]
87 mvs_check_page (0, 4, 0);
92 ; tstsi instruction pattern(s).
97 (match_operand:SI 0 "register_operand" "d"))]
102 mvs_check_page (0, 2, 0);
103 return \"LTR %0,%0\";
107 ; tsthi instruction pattern(s).
112 (match_operand:HI 0 "register_operand" "d"))]
117 mvs_check_page (0, 4, 2);
118 return \"CH %0,=H'0'\";
122 ; tstqi instruction pattern(s).
127 (match_operand:QI 0 "r_or_s_operand" "dm"))]
128 "unsigned_jump_follows_p (insn)"
132 if (REG_P (operands[0]))
134 mvs_check_page (0, 4, 4);
135 return \"N %0,=X'000000FF'\";
137 mvs_check_page (0, 4, 0);
143 (match_operand:QI 0 "register_operand" "d"))]
148 if (unsigned_jump_follows_p (insn))
150 mvs_check_page (0, 4, 4);
151 return \"N %0,=X'000000FF'\";
153 mvs_check_page (0, 8, 0);
154 return \"SLL %0,24\;SRA %0,24\";
158 ; tstdf instruction pattern(s).
163 (match_operand:DF 0 "general_operand" "f"))]
168 mvs_check_page (0, 2, 0);
169 return \"LTDR %0,%0\";
173 ; tstsf instruction pattern(s).
178 (match_operand:SF 0 "general_operand" "f"))]
183 mvs_check_page (0, 2, 0);
184 return \"LTER %0,%0\";
188 ;;- Compare instructions.
192 ; cmpdi instruction pattern(s).
195 ;(define_insn "cmpdi"
197 ; (compare (match_operand:DI 0 "register_operand" "d")
198 ; (match_operand:DI 1 "general_operand" "")))]
202 ; check_label_emit ();
203 ; if (REG_P (operands[1]))
205 ; mvs_check_page (0, 8, 0);
206 ; if (unsigned_jump_follows_p (insn))
207 ; return \"CLR %0,%1\;BNE *+6\;CLR %N0,%N1\";
208 ; return \"CR %0,%1\;BNE *+6\;CLR %N0,%N1\";
210 ; mvs_check_page (0, 12, 0);
211 ; if (unsigned_jump_follows_p (insn))
212 ; return \"CL %0,%M1\;BNE *+8\;CL %N0,%L1\";
213 ; return \"C %0,%M1\;BNE *+8\;CL %N0,%L1\";
217 ; cmpsi instruction pattern(s).
222 (compare (match_operand:SI 0 "register_operand" "d")
223 (match_operand:SI 1 "general_operand" "md")))]
228 if (REG_P (operands[1]))
230 mvs_check_page (0, 2, 0);
231 if (unsigned_jump_follows_p (insn))
232 return \"CLR %0,%1\";
235 if (GET_CODE (operands[1]) == CONST_INT)
237 mvs_check_page (0, 4, 4);
238 if (unsigned_jump_follows_p (insn))
239 return \"CL %0,=F'%c1'\";
240 return \"C %0,=F'%c1'\";
242 mvs_check_page (0, 4, 0);
243 if (unsigned_jump_follows_p (insn))
249 ; cmphi instruction pattern(s).
254 (compare (match_operand:HI 0 "register_operand" "d")
255 (match_operand:HI 1 "general_operand" "")))]
260 if (REG_P (operands[1]))
262 mvs_check_page (0, 8, 0);
263 if (unsigned_jump_follows_p (insn))
264 return \"STH %1,140(,13)\;CLM %0,3,140(13)\";
265 return \"STH %1,140(,13)\;CH %0,140(,13)\";
267 if (GET_CODE (operands[1]) == CONST_INT)
269 mvs_check_page (0, 4, 0);
270 return \"CH %0,%H1\";
272 mvs_check_page (0, 4, 0);
277 ; cmpqi instruction pattern(s).
282 (compare (match_operand:QI 0 "r_or_s_operand" "g")
283 (match_operand:QI 1 "r_or_s_operand" "g")))]
284 "unsigned_jump_follows_p (insn)"
288 if (REG_P (operands[0]))
290 if (REG_P (operands[1]))
292 mvs_check_page (0, 8, 0);
293 return \"STC %1,140(,13)\;CLM %0,1,140(13)\";
295 if (GET_CODE (operands[1]) == CONST_INT)
297 mvs_check_page (0, 4, 1);
298 return \"CLM %0,1,=FL1'%B1'\";
300 mvs_check_page (0, 4, 0);
301 return \"CLM %0,1,%1\";
303 else if (GET_CODE (operands[0]) == CONST_INT)
305 cc_status.flags |= CC_REVERSED;
306 if (REG_P (operands[1]))
308 mvs_check_page (0, 4, 1);
309 return \"CLM %1,1,=FL1'%B0'\";
311 mvs_check_page (0, 4, 0);
312 return \"CLI %1,%B0\";
314 if (GET_CODE (operands[1]) == CONST_INT)
316 mvs_check_page (0, 4, 0);
317 return \"CLI %0,%B1\";
319 if (GET_CODE (operands[1]) == MEM)
321 mvs_check_page (0, 6, 0);
322 return \"CLC %O0(1,%R0),%1\";
324 cc_status.flags |= CC_REVERSED;
325 mvs_check_page (0, 4, 0);
326 return \"CLM %1,1,%0\";
331 (compare (match_operand:QI 0 "register_operand" "d")
332 (match_operand:QI 1 "general_operand" "di")))]
337 if (unsigned_jump_follows_p (insn))
339 if (REG_P (operands[1]))
341 mvs_check_page (0, 4, 0);
342 return \"CLM %0,1,%1\";
344 if (GET_CODE (operands[1]) == CONST_INT)
346 mvs_check_page (0, 4, 1);
347 return \"CLM %0,1,=FL1'%B1'\";
349 mvs_check_page (0, 8, 0);
350 return \"STC %1,140(,13)\;CLM %0,1,140(13)\";
352 if (REG_P (operands[1]))
354 mvs_check_page (0, 18, 0);
355 return \"SLL %0,24\;SRA %0,24\;SLL %1,24\;SRA %1,24\;CR %0,%1\";
357 mvs_check_page (0, 12, 0);
358 return \"SLL %0,24\;SRA %0,24\;C %0,%1\";
362 ; cmpdf instruction pattern(s).
367 (compare (match_operand:DF 0 "general_operand" "f,mF")
368 (match_operand:DF 1 "general_operand" "fmF,f")))]
373 if (FP_REG_P (operands[0]))
375 if (FP_REG_P (operands[1]))
377 mvs_check_page (0, 2, 0);
378 return \"CDR %0,%1\";
380 mvs_check_page (0, 4, 0);
383 cc_status.flags |= CC_REVERSED;
384 mvs_check_page (0, 4, 0);
389 ; cmpsf instruction pattern(s).
394 (compare (match_operand:SF 0 "general_operand" "f,mF")
395 (match_operand:SF 1 "general_operand" "fmF,f")))]
400 if (FP_REG_P (operands[0]))
402 if (FP_REG_P (operands[1]))
404 mvs_check_page (0, 2, 0);
405 return \"CER %0,%1\";
407 mvs_check_page (0, 4, 0);
410 cc_status.flags |= CC_REVERSED;
411 mvs_check_page (0, 4, 0);
416 ; cmpstrsi instruction pattern(s).
419 (define_expand "cmpstrsi"
420 [(set (match_operand:SI 0 "general_operand" "")
421 (compare (match_operand:BLK 1 "general_operand" "")
422 (match_operand:BLK 2 "general_operand" "")))
423 (use (match_operand:SI 3 "general_operand" ""))
424 (use (match_operand:SI 4 "" ""))]
430 op1 = XEXP (operands[1], 0);
431 if (GET_CODE (op1) == REG
432 || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG
433 && GET_CODE (XEXP (op1, 1)) == CONST_INT
434 && (unsigned) INTVAL (XEXP (op1, 1)) < 4096))
440 op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1));
443 op2 = XEXP (operands[2], 0);
444 if (GET_CODE (op2) == REG
445 || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2, 0)) == REG
446 && GET_CODE (XEXP (op2, 1)) == CONST_INT
447 && (unsigned) INTVAL (XEXP (op2, 1)) < 4096))
453 op2 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op2));
456 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
458 emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
459 gen_rtx (SET, VOIDmode, operands[0],
460 gen_rtx (COMPARE, VOIDmode, op1, op2)),
461 gen_rtx (USE, VOIDmode, operands[3]))));
465 rtx reg1 = gen_reg_rtx (DImode);
466 rtx reg2 = gen_reg_rtx (DImode);
467 rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1);
469 emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[3]));
470 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1),
472 emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5,
473 gen_rtx (SET, VOIDmode, operands[0],
474 gen_rtx (COMPARE, VOIDmode, op1, op2)),
475 gen_rtx (USE, VOIDmode, reg1),
476 gen_rtx (USE, VOIDmode, reg2),
477 gen_rtx (CLOBBER, VOIDmode, reg1),
478 gen_rtx (CLOBBER, VOIDmode, reg2))));
483 ; Compare a block that is less than 256 bytes in length.
486 [(set (match_operand:SI 0 "register_operand" "d")
487 (compare (match_operand:BLK 1 "s_operand" "m")
488 (match_operand:BLK 2 "s_operand" "m")))
489 (use (match_operand:QI 3 "immediate_operand" "I"))]
490 "((unsigned) INTVAL (operands[3]) < 256)"
494 mvs_check_page (0, 22, 0);
495 return \"LA %0,1\;CLC %O1(%c3,%R1),%2\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\";
498 ; Compare a block that is larger than 255 bytes in length.
501 [(set (match_operand:SI 0 "register_operand" "d")
502 (compare (match_operand:BLK 1 "general_operand" "m")
503 (match_operand:BLK 2 "general_operand" "m")))
504 (use (match_operand:DI 3 "register_operand" "d"))
505 (use (match_operand:DI 4 "register_operand" "d"))
506 (clobber (match_dup 3))
507 (clobber (match_dup 4))]
512 mvs_check_page (0, 26, 0);
513 return \"LA %3,%1\;LA %4,%2\;LA %0,1\;CLCL %3,%4\;BH *+12\;BL *+6\;SLR %0,%0\;LNR %0,%0\";
517 ;;- Move instructions.
521 ; movdi instruction pattern(s).
525 [(set (match_operand:DI 0 "r_or_s_operand" "=dm")
526 (match_operand:DI 1 "r_or_s_operand" "dim*fF"))]
527 "TARGET_CHAR_INSTRUCTIONS"
531 if (REG_P (operands[0]))
533 if (FP_REG_P (operands[1]))
535 mvs_check_page (0, 8, 0);
536 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
538 if (REG_P (operands[1]))
540 mvs_check_page (0, 4, 0);
541 return \"LR %0,%1\;LR %N0,%N1\";
543 if (operands[1] == const0_rtx)
546 mvs_check_page (0, 4, 0);
547 return \"SLR %0,%0\;SLR %N0,%N0\";
549 if (GET_CODE (operands[1]) == CONST_INT
550 && (unsigned) INTVAL (operands[1]) < 4096)
553 mvs_check_page (0, 6, 0);
554 return \"SLR %0,%0\;LA %N0,%c1\";
556 if (GET_CODE (operands[1]) == CONST_INT)
558 CC_STATUS_SET (operands[0], operands[1]);
559 mvs_check_page (0, 8, 0);
560 return \"L %0,%1\;SRDA %0,32\";
562 mvs_check_page (0, 4, 0);
563 return \"LM %0,%N0,%1\";
565 else if (FP_REG_P (operands[1]))
567 mvs_check_page (0, 4, 0);
568 return \"STD %1,%0\";
570 else if (REG_P (operands[1]))
572 mvs_check_page (0, 4, 0);
573 return \"STM %1,%N1,%0\";
575 mvs_check_page (0, 6, 0);
576 return \"MVC %O0(8,%R0),%1\";
580 [(set (match_operand:DI 0 "general_operand" "=dm")
581 (match_operand:DI 1 "general_operand" "dim*fF"))]
586 if (REG_P (operands[0]))
588 if (FP_REG_P (operands[1]))
590 mvs_check_page (0, 8, 0);
591 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
593 if (REG_P (operands[1]))
595 mvs_check_page (0, 4, 0);
596 return \"LR %0,%1\;LR %N0,%N1\";
598 if (operands[1] == const0_rtx)
601 mvs_check_page (0, 4, 0);
602 return \"SLR %0,%0\;SLR %N0,%N0\";
604 if (GET_CODE (operands[1]) == CONST_INT
605 && (unsigned) INTVAL (operands[1]) < 4096)
608 mvs_check_page (0, 6, 0);
609 return \"SLR %0,%0\;LA %N0,%c1\";
611 if (GET_CODE (operands[1]) == CONST_INT)
613 CC_STATUS_SET (operands[0], operands[1]);
614 mvs_check_page (0, 8, 0);
615 return \"L %0,%1\;SRDA %0,32\";
617 mvs_check_page (0, 4, 0);
618 return \"LM %0,%N0,%1\";
620 else if (FP_REG_P (operands[1]))
622 mvs_check_page (0, 4, 0);
623 return \"STD %1,%0\";
625 mvs_check_page (0, 4, 0);
626 return \"STM %1,%N1,%0\";
630 ; movsi instruction pattern(s).
634 [(set (match_operand:SI 0 "r_or_s_operand" "=dm,dm")
635 (match_operand:SI 1 "r_or_s_operand" "dim,*fF"))]
636 "TARGET_CHAR_INSTRUCTIONS"
640 if (REG_P (operands[0]))
642 if (FP_REG_P (operands[1]))
644 mvs_check_page (0, 8, 0);
645 return \"STE %1,140(,13)\;L %0,140(,13)\";
647 if (REG_P (operands[1]))
649 mvs_check_page (0, 2, 0);
652 if (operands[1] == const0_rtx)
655 mvs_check_page (0, 2, 0);
656 return \"SLR %0,%0\";
658 if (GET_CODE (operands[1]) == CONST_INT
659 && (unsigned) INTVAL (operands[1]) < 4096)
661 mvs_check_page (0, 4, 0);
662 return \"LA %0,%c1\";
664 mvs_check_page (0, 4, 0);
667 else if (FP_REG_P (operands[1]))
669 mvs_check_page (0, 4, 0);
670 return \"STE %1,%0\";
672 else if (REG_P (operands[1]))
674 mvs_check_page (0, 4, 0);
677 mvs_check_page (0, 6, 0);
678 return \"MVC %O0(4,%R0),%1\";
682 [(set (match_operand:SI 0 "general_operand" "=d,dm")
683 (match_operand:SI 1 "general_operand" "dimF,*fd"))]
688 if (REG_P (operands[0]))
690 if (FP_REG_P (operands[1]))
692 mvs_check_page (0, 8, 0);
693 return \"STE %1,140(,13)\;L %0,140(,13)\";
695 if (REG_P (operands[1]))
697 mvs_check_page (0, 2, 0);
700 if (operands[1] == const0_rtx)
703 mvs_check_page (0, 2, 0);
704 return \"SLR %0,%0\";
706 if (GET_CODE (operands[1]) == CONST_INT
707 && (unsigned) INTVAL (operands[1]) < 4096)
709 mvs_check_page (0, 4, 0);
710 return \"LA %0,%c1\";
712 mvs_check_page (0, 4, 0);
715 else if (FP_REG_P (operands[1]))
717 mvs_check_page (0, 4, 0);
718 return \"STE %1,%0\";
720 mvs_check_page (0, 4, 0);
724 ;(define_expand "movsi"
725 ; [(set (match_operand:SI 0 "general_operand" "=d,dm")
726 ; (match_operand:SI 1 "general_operand" "dimF,*fd"))]
733 ; if (GET_CODE (op0) == CONST
734 ; && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SYMBOL_REF
735 ; && SYMBOL_REF_FLAG (XEXP (XEXP (op0, 0), 0)))
737 ; op0 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op0, 0)));
741 ; if (GET_CODE (op1) == CONST
742 ; && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF
743 ; && SYMBOL_REF_FLAG (XEXP (XEXP (op1, 0), 0)))
745 ; op1 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op1, 0)));
748 ; emit_insn (gen_rtx (SET, VOIDmode, op0, op1));
753 ; movhi instruction pattern(s).
757 [(set (match_operand:HI 0 "r_or_s_operand" "=g")
758 (match_operand:HI 1 "r_or_s_operand" "g"))]
759 "TARGET_CHAR_INSTRUCTIONS"
763 if (REG_P (operands[0]))
765 if (REG_P (operands[1]))
767 mvs_check_page (0, 2, 0);
770 if (operands[1] == const0_rtx)
773 mvs_check_page (0, 2, 0);
774 return \"SLR %0,%0\";
776 if (GET_CODE (operands[1]) == CONST_INT
777 && (unsigned) INTVAL (operands[1]) < 4096)
779 mvs_check_page (0, 4, 0);
780 return \"LA %0,%c1\";
782 if (GET_CODE (operands[1]) == CONST_INT)
784 mvs_check_page (0, 4, 0);
785 return \"LH %0,%H1\";
787 mvs_check_page (0, 4, 0);
790 else if (REG_P (operands[1]))
792 mvs_check_page (0, 4, 0);
793 return \"STH %1,%0\";
795 if (GET_CODE (operands[1]) == CONST_INT)
797 mvs_check_page (0, 6, 0);
798 return \"MVC %O0(2,%R0),%H1\";
800 mvs_check_page (0, 6, 0);
801 return \"MVC %O0(2,%R0),%1\";
805 [(set (match_operand:HI 0 "general_operand" "=d,m")
806 (match_operand:HI 1 "general_operand" "g,d"))]
811 if (REG_P (operands[0]))
813 if (REG_P (operands[1]))
815 mvs_check_page (0, 2, 0);
818 if (operands[1] == const0_rtx)
821 mvs_check_page (0, 2, 0);
822 return \"SLR %0,%0\";
824 if (GET_CODE (operands[1]) == CONST_INT
825 && (unsigned) INTVAL (operands[1]) < 4096)
827 mvs_check_page (0, 4, 0);
828 return \"LA %0,%c1\";
830 if (GET_CODE (operands[1]) == CONST_INT)
832 mvs_check_page (0, 4, 0);
833 return \"LH %0,%H1\";
835 mvs_check_page (0, 4, 0);
838 mvs_check_page (0, 4, 0);
839 return \"STH %1,%0\";
843 ; movqi instruction pattern(s).
847 [(set (match_operand:QI 0 "r_or_s_operand" "=g")
848 (match_operand:QI 1 "r_or_s_operand" "g"))]
849 "TARGET_CHAR_INSTRUCTIONS"
853 if (REG_P (operands[0]))
855 if (REG_P (operands[1]))
857 mvs_check_page (0, 2, 0);
860 if (operands[1] == const0_rtx)
863 mvs_check_page (0, 2, 0);
864 return \"SLR %0,%0\";
866 if (GET_CODE (operands[1]) == CONST_INT)
868 if (INTVAL (operands[1]) >= 0)
870 mvs_check_page (0, 4, 0);
871 return \"LA %0,%c1\";
873 mvs_check_page (0, 4, 0);
874 return \"L %0,=F'%c1'\";
876 mvs_check_page (0, 4, 0);
879 else if (REG_P (operands[1]))
881 mvs_check_page (0, 4, 0);
882 return \"STC %1,%0\";
884 else if (GET_CODE (operands[1]) == CONST_INT)
886 mvs_check_page (0, 4, 0);
887 return \"MVI %0,%B1\";
889 mvs_check_page (0, 6, 0);
890 return \"MVC %O0(1,%R0),%1\";
894 [(set (match_operand:QI 0 "general_operand" "=d,m")
895 (match_operand:QI 1 "general_operand" "g,d"))]
900 if (REG_P (operands[0]))
902 if (REG_P (operands[1]))
904 mvs_check_page (0, 2, 0);
907 if (operands[1] == const0_rtx)
910 mvs_check_page (0, 2, 0);
911 return \"SLR %0,%0\";
913 if (GET_CODE (operands[1]) == CONST_INT)
915 if (INTVAL (operands[1]) >= 0)
917 mvs_check_page (0, 4, 0);
918 return \"LA %0,%c1\";
920 mvs_check_page (0, 4, 0);
921 return \"L %0,=F'%c1'\";
923 mvs_check_page (0, 4, 0);
926 mvs_check_page (0, 4, 0);
927 return \"STC %1,%0\";
931 ; movestrictqi instruction pattern(s).
934 (define_insn "movestrictqi"
935 [(set (strict_low_part (match_operand:QI 0 "general_operand" "=d"))
936 (match_operand:QI 1 "general_operand" "g"))]
941 if (REG_P (operands[1]))
943 mvs_check_page (0, 8, 0);
944 return \"STC %1,140(,13)\;IC %0,140(,13)\";
946 mvs_check_page (0, 4, 0);
951 ; movstricthi instruction pattern(s).
955 [(set (strict_low_part (match_operand:HI 0 "register_operand" "=d"))
956 (match_operand:HI 1 "r_or_s_operand" "g"))]
961 if (REG_P (operands[1]))
963 mvs_check_page (0, 8, 0);
964 return \"STH %1,140(,13)\;ICM %0,3,140(13)\";
966 else if (GET_CODE (operands[1]) == CONST_INT)
968 mvs_check_page (0, 4, 0);
969 return \"ICM %0,3,%H1\";
971 mvs_check_page (0, 4, 0);
972 return \"ICM %0,3,%1\";
975 (define_insn "movestricthi"
976 [(set (strict_low_part (match_operand:HI 0 "general_operand" "=dm"))
977 (match_operand:HI 1 "general_operand" "d"))]
982 if (REG_P (operands[0]))
984 mvs_check_page (0, 8, 0);
985 return \"STH %1,140(,13)\;ICM %0,3,140(13)\";
987 mvs_check_page (0, 4, 0);
988 return \"STH %1,%0\";
992 ; movdf instruction pattern(s).
996 [(set (match_operand:DF 0 "r_or_s_operand" "=fm,fm,*dm")
997 (match_operand:DF 1 "r_or_s_operand" "fmF,*dm,fmF"))]
998 "TARGET_CHAR_INSTRUCTIONS"
1001 check_label_emit ();
1002 if (FP_REG_P (operands[0]))
1004 if (FP_REG_P (operands[1]))
1006 mvs_check_page (0, 2, 0);
1007 return \"LDR %0,%1\";
1009 if (REG_P (operands[1]))
1011 mvs_check_page (0, 8, 0);
1012 return \"STM %1,%N1,140(13)\;LD %0,140(,13)\";
1014 if (operands[1] == const0_rtx)
1016 CC_STATUS_SET (operands[0], operands[1]);
1017 mvs_check_page (0, 2, 0);
1018 return \"SDR %0,%0\";
1020 mvs_check_page (0, 4, 0);
1021 return \"LD %0,%1\";
1023 if (REG_P (operands[0]))
1025 if (FP_REG_P (operands[1]))
1027 mvs_check_page (0, 12, 0);
1028 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
1030 mvs_check_page (0, 4, 0);
1031 return \"LM %0,%N0,%1\";
1033 else if (FP_REG_P (operands[1]))
1035 mvs_check_page (0, 4, 0);
1036 return \"STD %1,%0\";
1038 else if (REG_P (operands[1]))
1040 mvs_check_page (0, 4, 0);
1041 return \"STM %1,%N1,%0\";
1043 mvs_check_page (0, 6, 0);
1044 return \"MVC %O0(8,%R0),%1\";
1047 (define_insn "movdf"
1048 [(set (match_operand:DF 0 "general_operand" "=f,fm,m,*d")
1049 (match_operand:DF 1 "general_operand" "fmF,*d,f,fmF"))]
1053 check_label_emit ();
1054 if (FP_REG_P (operands[0]))
1056 if (FP_REG_P (operands[1]))
1058 mvs_check_page (0, 2, 0);
1059 return \"LDR %0,%1\";
1061 if (REG_P (operands[1]))
1063 mvs_check_page (0, 8, 0);
1064 return \"STM %1,%N1,140(13)\;LD %0,140(,13)\";
1066 if (operands[1] == const0_rtx)
1068 CC_STATUS_SET (operands[0], operands[1]);
1069 mvs_check_page (0, 2, 0);
1070 return \"SDR %0,%0\";
1072 mvs_check_page (0, 4, 0);
1073 return \"LD %0,%1\";
1075 else if (REG_P (operands[0]))
1077 if (FP_REG_P (operands[1]))
1079 mvs_check_page (0, 12, 0);
1080 return \"STD %1,140(,13)\;LM %0,%N0,140(13)\";
1082 mvs_check_page (0, 4, 0);
1083 return \"LM %0,%N0,%1\";
1085 else if (FP_REG_P (operands[1]))
1087 mvs_check_page (0, 4, 0);
1088 return \"STD %1,%0\";
1090 mvs_check_page (0, 4, 0);
1091 return \"STM %1,%N1,%0\";
1095 ; movsf instruction pattern(s).
1099 [(set (match_operand:SF 0 "r_or_s_operand" "=fm,fm,*dm")
1100 (match_operand:SF 1 "r_or_s_operand" "fmF,*dm,fmF"))]
1101 "TARGET_CHAR_INSTRUCTIONS"
1104 check_label_emit ();
1105 if (FP_REG_P (operands[0]))
1107 if (FP_REG_P (operands[1]))
1109 mvs_check_page (0, 2, 0);
1110 return \"LER %0,%1\";
1112 if (REG_P (operands[1]))
1114 mvs_check_page (0, 8, 0);
1115 return \"ST %1,140(,13)\;LE %0,140(,13)\";
1117 if (operands[1] == const0_rtx)
1119 CC_STATUS_SET (operands[0], operands[1]);
1120 mvs_check_page (0, 2, 0);
1121 return \"SER %0,%0\";
1123 mvs_check_page (0, 4, 0);
1124 return \"LE %0,%1\";
1126 else if (REG_P (operands[0]))
1128 if (FP_REG_P (operands[1]))
1130 mvs_check_page (0, 8, 0);
1131 return \"STE %1,140(,13)\;L %0,140(,13)\";
1133 mvs_check_page (0, 4, 0);
1136 else if (FP_REG_P (operands[1]))
1138 mvs_check_page (0, 4, 0);
1139 return \"STE %1,%0\";
1141 else if (REG_P (operands[1]))
1143 mvs_check_page (0, 4, 0);
1144 return \"ST %1,%0\";
1146 mvs_check_page (0, 6, 0);
1147 return \"MVC %O0(4,%R0),%1\";
1150 (define_insn "movsf"
1151 [(set (match_operand:SF 0 "general_operand" "=f,fm,m,*d")
1152 (match_operand:SF 1 "general_operand" "fmF,*d,f,fmF"))]
1156 check_label_emit ();
1157 if (FP_REG_P (operands[0]))
1159 if (FP_REG_P (operands[1]))
1161 mvs_check_page (0, 2, 0);
1162 return \"LER %0,%1\";
1164 if (REG_P (operands[1]))
1166 mvs_check_page (0, 8, 0);
1167 return \"ST %1,140(,13)\;LE %0,140(,13)\";
1169 if (operands[1] == const0_rtx)
1171 CC_STATUS_SET (operands[0], operands[1]);
1172 mvs_check_page (0, 2, 0);
1173 return \"SER %0,%0\";
1175 mvs_check_page (0, 4, 0);
1176 return \"LE %0,%1\";
1178 else if (REG_P (operands[0]))
1180 if (FP_REG_P (operands[1]))
1182 mvs_check_page (0, 8, 0);
1183 return \"STE %1,140(,13)\;L %0,140(,13)\";
1185 mvs_check_page (0, 4, 0);
1188 else if (FP_REG_P (operands[1]))
1190 mvs_check_page (0, 4, 0);
1191 return \"STE %1,%0\";
1193 mvs_check_page (0, 4, 0);
1194 return \"ST %1,%0\";
1198 ; movstrsi instruction pattern(s).
1201 (define_expand "movstrsi"
1202 [(set (match_operand:BLK 0 "general_operand" "")
1203 (match_operand:BLK 1 "general_operand" ""))
1204 (use (match_operand:SI 2 "general_operand" ""))
1205 (match_operand 3 "" "")]
1211 op0 = XEXP (operands[0], 0);
1212 if (GET_CODE (op0) == REG
1213 || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 0)) == REG
1214 && GET_CODE (XEXP (op0, 1)) == CONST_INT
1215 && (unsigned) INTVAL (XEXP (op0, 1)) < 4096))
1221 op0 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op0));
1224 op1 = XEXP (operands[1], 0);
1225 if (GET_CODE (op1) == REG
1226 || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1, 0)) == REG
1227 && GET_CODE (XEXP (op1, 1)) == CONST_INT
1228 && (unsigned) INTVAL (XEXP (op1, 1)) < 4096))
1234 op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1));
1237 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 256)
1239 emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
1240 gen_rtx (SET, VOIDmode, op0, op1),
1241 gen_rtx (USE, VOIDmode, operands[2]))));
1245 rtx reg1 = gen_reg_rtx (DImode);
1246 rtx reg2 = gen_reg_rtx (DImode);
1247 rtx subreg = gen_rtx (SUBREG, SImode, reg1, 1);
1249 emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[2]));
1250 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2, 1),
1252 emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (5,
1253 gen_rtx (SET, VOIDmode, op0, op1),
1254 gen_rtx (USE, VOIDmode, reg1),
1255 gen_rtx (USE, VOIDmode, reg2),
1256 gen_rtx (CLOBBER, VOIDmode, reg1),
1257 gen_rtx (CLOBBER, VOIDmode, reg2))));
1262 ; Move a block that is less than 256 bytes in length.
1265 [(set (match_operand:BLK 0 "s_operand" "=m")
1266 (match_operand:BLK 1 "s_operand" "m"))
1267 (use (match_operand 2 "immediate_operand" "I"))]
1268 "((unsigned) INTVAL (operands[2]) < 256)"
1271 check_label_emit ();
1272 mvs_check_page (0, 6, 0);
1273 return \"MVC %O0(%c2,%R0),%1\";
1276 ; Move a block that is larger than 255 bytes in length.
1279 [(set (match_operand:BLK 0 "general_operand" "=m")
1280 (match_operand:BLK 1 "general_operand" "m"))
1281 (use (match_operand:DI 2 "register_operand" "d"))
1282 (use (match_operand:DI 3 "register_operand" "d"))
1283 (clobber (match_dup 2))
1284 (clobber (match_dup 3))]
1288 check_label_emit ();
1289 mvs_check_page (0, 10, 0);
1290 return \"LA %2,%0\;LA %3,%1\;MVCL %2,%3\";
1294 ;;- Conversion instructions.
1298 ; extendsidi2 instruction pattern(s).
1301 (define_expand "extendsidi2"
1302 [(set (match_operand:DI 0 "general_operand" "")
1303 (sign_extend:DI (match_operand:SI 1 "general_operand" "")))]
1307 if (GET_CODE (operands[1]) != CONST_INT)
1309 emit_insn (gen_rtx (SET, VOIDmode,
1310 operand_subword (operands[0], 0, 1, DImode), operands[1]));
1311 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1312 gen_rtx (ASHIFTRT, DImode, operands[0],
1313 gen_rtx (CONST_INT, SImode, 32))));
1317 if (INTVAL (operands[1]) < 0)
1319 emit_insn (gen_rtx (SET, VOIDmode,
1320 operand_subword (operands[0], 0, 1, DImode),
1321 gen_rtx (CONST_INT, SImode, -1)));
1325 emit_insn (gen_rtx (SET, VOIDmode,
1326 operand_subword (operands[0], 0, 1, DImode),
1327 gen_rtx (CONST_INT, SImode, 0)));
1329 emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (SImode, operands[0]),
1336 ; extendhisi2 instruction pattern(s).
1339 (define_insn "extendhisi2"
1340 [(set (match_operand:SI 0 "general_operand" "=d,m")
1341 (sign_extend:SI (match_operand:HI 1 "general_operand" "g,d")))]
1345 check_label_emit ();
1346 if (REG_P (operands[0]))
1348 if (REG_P (operands[1]))
1349 if (REGNO (operands[0]) != REGNO (operands[1]))
1351 mvs_check_page (0, 2, 0);
1352 return \"LR %0,%1\;SLL %0,16\;SRA %0,16\";
1355 return \"\"; /* Should be empty. 16-bits regs are always 32-bits. */
1356 if (operands[1] == const0_rtx)
1359 mvs_check_page (0, 2, 0);
1360 return \"SLR %0,%0\";
1362 if (GET_CODE (operands[1]) == CONST_INT
1363 && (unsigned) INTVAL (operands[1]) < 4096)
1365 mvs_check_page (0, 4, 0);
1366 return \"LA %0,%c1\";
1368 if (GET_CODE (operands[1]) == CONST_INT)
1370 mvs_check_page (0, 4, 0);
1371 return \"LH %0,%H1\";
1373 mvs_check_page (0, 4, 0);
1374 return \"LH %0,%1\";
1376 mvs_check_page (0, 4, 0);
1377 return \"SLL %1,16\;SRA %1,16\;ST %1,%0\";
1381 ; extendqisi2 instruction pattern(s).
1384 (define_insn "extendqisi2"
1385 [(set (match_operand:SI 0 "general_operand" "=d")
1386 (sign_extend:SI (match_operand:QI 1 "general_operand" "0mi")))]
1390 check_label_emit ();
1391 CC_STATUS_SET (operands[0], operands[1]);
1392 if (REG_P (operands[1]))
1394 mvs_check_page (0, 8, 0);
1395 return \"SLL %0,24\;SRA %0,24\";
1397 if (s_operand (operands[1]))
1399 mvs_check_page (0, 8, 0);
1400 return \"ICM %0,8,%1\;SRA %0,24\";
1402 mvs_check_page (0, 12, 0);
1403 return \"IC %0,%1\;SLL %0,24\;SRA %0,24\";
1407 ; extendqihi2 instruction pattern(s).
1410 (define_insn "extendqihi2"
1411 [(set (match_operand:HI 0 "general_operand" "=d")
1412 (sign_extend:HI (match_operand:QI 1 "general_operand" "0m")))]
1416 check_label_emit ();
1417 CC_STATUS_SET (operands[0], operands[1]);
1418 if (REG_P (operands[1]))
1420 mvs_check_page (0, 8, 0);
1421 return \"SLL %0,24\;SRA %0,24\";
1423 if (s_operand (operands[1]))
1425 mvs_check_page (0, 8, 0);
1426 return \"ICM %0,8,%1\;SRA %0,24\";
1428 mvs_check_page (0, 12, 0);
1429 return \"IC %0,%1\;SLL %0,24\;SRA %0,24\";
1433 ; zero_extendsidi2 instruction pattern(s).
1436 (define_expand "zero_extendsidi2"
1437 [(set (match_operand:DI 0 "general_operand" "")
1438 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1442 emit_insn (gen_rtx (SET, VOIDmode,
1443 operand_subword (operands[0], 0, 1, DImode), operands[1]));
1444 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1445 gen_rtx (LSHIFTRT, DImode, operands[0],
1446 gen_rtx (CONST_INT, SImode, 32))));
1451 ; zero_extendhisi2 instruction pattern(s).
1454 (define_insn "zero_extendhisi2"
1455 [(set (match_operand:SI 0 "general_operand" "=d")
1456 (zero_extend:SI (match_operand:HI 1 "general_operand" "0")))]
1460 check_label_emit ();
1461 CC_STATUS_SET (operands[0], operands[1]);
1462 mvs_check_page (0, 4, 4);
1463 return \"N %1,=X'0000FFFF'\";
1467 ; zero_extendqisi2 instruction pattern(s).
1470 (define_insn "zero_extendqisi2"
1471 [(set (match_operand:SI 0 "general_operand" "=d,&d")
1472 (zero_extend:SI (match_operand:QI 1 "general_operand" "0i,m")))]
1476 check_label_emit ();
1477 if (REG_P (operands[1]))
1479 CC_STATUS_SET (operands[0], operands[1]);
1480 mvs_check_page (0, 4, 4);
1481 return \"N %0,=X'000000FF'\";
1483 if (GET_CODE (operands[1]) == CONST_INT)
1485 mvs_check_page (0, 4, 0);
1486 return \"LA %0,%c1\";
1489 mvs_check_page (0, 8, 0);
1490 return \"SLR %0,%0\;IC %0,%1\";
1494 ; zero_extendqihi2 instruction pattern(s).
1497 (define_insn "zero_extendqihi2"
1498 [(set (match_operand:HI 0 "general_operand" "=d,&d")
1499 (zero_extend:HI (match_operand:QI 1 "general_operand" "0i,m")))]
1503 check_label_emit ();
1504 if (REG_P (operands[1]))
1506 CC_STATUS_SET (operands[0], operands[1]);
1507 mvs_check_page (0, 4, 4);
1508 return \"N %0,=X'000000FF'\";
1510 if (GET_CODE (operands[1]) == CONST_INT)
1512 mvs_check_page (0, 4, 0);
1513 return \"LA %0,%c1\";
1516 mvs_check_page (0, 8, 0);
1517 return \"SLR %0,%0\;IC %0,%1\";
1521 ; truncsihi2 instruction pattern(s).
1524 (define_insn "truncsihi2"
1525 [(set (match_operand:HI 0 "general_operand" "=d,m")
1526 (truncate:HI (match_operand:SI 1 "general_operand" "0,d")))]
1530 check_label_emit ();
1531 if (REG_P (operands[0]))
1533 CC_STATUS_SET (operands[0], operands[1]);
1534 mvs_check_page (0, 8, 0);
1535 return \"SLL %0,16\;SRA %0,16\";
1537 mvs_check_page (0, 4, 0);
1538 return \"STH %1,%0\";
1542 ; fix_truncdfsi2 instruction pattern(s).
1545 (define_insn "fix_truncdfsi2"
1546 [(set (match_operand:SI 0 "general_operand" "=d")
1547 (fix:SI (truncate:DF (match_operand:DF 1 "general_operand" "f"))))
1548 (clobber (reg:DF 16))]
1552 check_label_emit ();
1554 if (REGNO (operands[1]) == 16)
1556 mvs_check_page (0, 12, 8);
1557 return \"AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\";
1559 mvs_check_page (0, 14, 8);
1560 return \"LDR 0,%1\;AD 0,=XL8'4F08000000000000'\;STD 0,140(,13)\;L %0,144(,13)\";
1564 ; floatsidf2 instruction pattern(s).
1566 ; Uses the float field of the TCA.
1569 (define_insn "floatsidf2"
1570 [(set (match_operand:DF 0 "general_operand" "=f")
1571 (float:DF (match_operand:SI 1 "general_operand" "d")))]
1575 check_label_emit ();
1577 mvs_check_page (0, 16, 8);
1578 return \"ST %1,508(,12)\;XI 508(12),128\;LD %0,504(,12)\;SD %0,=XL8'4E00000080000000'\";
1582 ; truncdfsf2 instruction pattern(s).
1585 (define_insn "truncdfsf2"
1586 [(set (match_operand:SF 0 "general_operand" "=f")
1587 (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
1591 check_label_emit ();
1592 mvs_check_page (0, 2, 0);
1593 return \"LRER %0,%1\";
1597 ; extendsfdf2 instruction pattern(s).
1600 (define_insn "extendsfdf2"
1601 [(set (match_operand:DF 0 "general_operand" "=f")
1602 (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
1606 check_label_emit ();
1607 CC_STATUS_SET (0, const0_rtx);
1608 if (FP_REG_P (operands[1]))
1610 if (REGNO (operands[0]) == REGNO (operands[1]))
1612 mvs_check_page (0, 10, 0);
1613 return \"STE %1,140(,13)\;SDR %0,%0\;LE %0,140(,13)\";
1615 mvs_check_page (0, 4, 0);
1616 return \"SDR %0,%0\;LER %0,%1\";
1618 mvs_check_page (0, 6, 0);
1619 return \"SDR %0,%0\;LE %0,%1\";
1623 ;;- Add instructions.
1627 ; adddi3 instruction pattern(s).
1630 (define_expand "adddi3"
1631 [(set (match_operand:DI 0 "general_operand" "")
1632 (plus:DI (match_operand:DI 1 "general_operand" "")
1633 (match_operand:DI 2 "general_operand" "")))]
1637 rtx label = gen_label_rtx ();
1638 rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
1639 rtx op0_low = gen_lowpart (SImode, operands[0]);
1641 emit_insn (gen_rtx (SET, VOIDmode, op0_high,
1642 gen_rtx (PLUS, SImode,
1643 operand_subword (operands[1], 0, 1, DImode),
1644 operand_subword (operands[2], 0, 1, DImode))));
1645 emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
1646 gen_rtx (SET, VOIDmode, op0_low,
1647 gen_rtx (PLUS, SImode, gen_lowpart (SImode, operands[1]),
1648 gen_lowpart (SImode, operands[2]))),
1649 gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, label)))));
1650 emit_insn (gen_rtx (SET, VOIDmode, op0_high,
1651 gen_rtx (PLUS, SImode, op0_high,
1652 gen_rtx (CONST_INT, SImode, 1))));
1658 [(set (match_operand:SI 0 "general_operand" "=d")
1659 (plus:SI (match_operand:SI 1 "general_operand" "%0")
1660 (match_operand:SI 2 "general_operand" "g")))
1661 (use (label_ref (match_operand 3 "" "")))]
1667 check_label_emit ();
1668 onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
1669 if (REG_P (operands[2]))
1673 mvs_check_page (0, 8, 4);
1674 return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1676 if (mvs_check_page (0, 6, 0))
1678 mvs_check_page (0, 2, 4);
1679 return \"ALR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1681 return \"ALR %0,%2\;BC 12,%l3\";
1685 mvs_check_page (0, 10, 4);
1686 return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1688 if (mvs_check_page (0, 8 ,0))
1690 mvs_check_page (0, 2, 4);
1691 return \"AL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1693 return \"AL %0,%2\;BC 12,%l3\";
1697 ; addsi3 instruction pattern(s).
1699 ; The following insn is used when it is known that operand one is an address,
1700 ; frame, stack or argument pointer, and operand two is a constant that is
1701 ; small enough to fit in the displacement field.
1702 ; Notice that we can't allow the frame pointer to used as a normal register
1703 ; because of this insn.
1707 [(set (match_operand:SI 0 "register_operand" "=d")
1708 (plus:SI (match_operand:SI 1 "general_operand" "%a")
1709 (match_operand:SI 2 "immediate_operand" "J")))]
1710 "((REGNO (operands[1]) == FRAME_POINTER_REGNUM || REGNO (operands[1]) == ARG_POINTER_REGNUM || REGNO (operands[1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[2]) < 4096)"
1713 check_label_emit ();
1715 mvs_check_page (0, 4, 0);
1716 return \"LA %0,%c2(,%1)\";
1719 ; This insn handles additions that are relative to the frame pointer.
1722 [(set (match_operand:SI 0 "register_operand" "=d")
1723 (plus:SI (match_operand:SI 1 "register_operand" "%a")
1724 (match_operand:SI 2 "immediate_operand" "i")))]
1725 "REGNO (operands[1]) == FRAME_POINTER_REGNUM"
1728 check_label_emit ();
1729 if ((unsigned) INTVAL (operands[2]) < 4096)
1731 mvs_check_page (0, 4, 0);
1732 return \"LA %0,%c2(,%1)\";
1734 if (REGNO (operands[1]) == REGNO (operands[0]))
1736 mvs_check_page (0, 4, 0);
1739 mvs_check_page (0, 6, 0);
1740 return \"L %0,%2\;AR %0,%1\";
1743 (define_insn "addsi3"
1744 [(set (match_operand:SI 0 "general_operand" "=d")
1745 (plus:SI (match_operand:SI 1 "general_operand" "%0")
1746 (match_operand:SI 2 "general_operand" "g")))]
1750 check_label_emit ();
1751 if (REG_P (operands[2]))
1753 mvs_check_page (0, 2, 0);
1754 return \"AR %0,%2\";
1756 if (GET_CODE (operands[2]) == CONST_INT)
1758 if (INTVAL (operands[2]) == -1)
1761 mvs_check_page (0, 2, 0);
1762 return \"BCTR %0,0\";
1765 mvs_check_page (0, 4, 0);
1770 ; addhi3 instruction pattern(s).
1773 (define_insn "addhi3"
1774 [(set (match_operand:HI 0 "general_operand" "=d")
1775 (plus:HI (match_operand:HI 1 "general_operand" "%0")
1776 (match_operand:HI 2 "general_operand" "dmi")))]
1780 check_label_emit ();
1781 if (REG_P (operands[2]))
1783 mvs_check_page (0, 8, 0);
1784 return \"STH %2,140(,13)\;AH %0,140(,13)\";
1786 if (GET_CODE (operands[2]) == CONST_INT)
1788 if (INTVAL (operands[2]) == -1)
1791 mvs_check_page (0, 2, 0);
1792 return \"BCTR %0,0\";
1794 mvs_check_page (0, 4, 0);
1795 return \"AH %0,%H2\";
1797 mvs_check_page (0, 4, 0);
1798 return \"AH %0,%2\";
1802 ; addqi3 instruction pattern(s).
1805 (define_insn "addqi3"
1806 [(set (match_operand:QI 0 "general_operand" "=d")
1807 (plus:QI (match_operand:QI 1 "general_operand" "%a")
1808 (match_operand:QI 2 "general_operand" "ai")))]
1812 check_label_emit ();
1814 mvs_check_page (0, 4, 0);
1815 if (REG_P (operands[2]))
1816 return \"LA %0,0(%1,%2)\";
1817 return \"LA %0,%B2(,%1)\";
1821 ; adddf3 instruction pattern(s).
1824 (define_insn "adddf3"
1825 [(set (match_operand:DF 0 "general_operand" "=f")
1826 (plus:DF (match_operand:DF 1 "general_operand" "%0")
1827 (match_operand:DF 2 "general_operand" "fmF")))]
1831 check_label_emit ();
1832 if (FP_REG_P (operands[2]))
1834 mvs_check_page (0, 2, 0);
1835 return \"ADR %0,%2\";
1837 mvs_check_page (0, 4, 0);
1838 return \"AD %0,%2\";
1842 ; addsf3 instruction pattern(s).
1845 (define_insn "addsf3"
1846 [(set (match_operand:SF 0 "general_operand" "=f")
1847 (plus:SF (match_operand:SF 1 "general_operand" "%0")
1848 (match_operand:SF 2 "general_operand" "fmF")))]
1852 check_label_emit ();
1853 if (FP_REG_P (operands[2]))
1855 mvs_check_page (0, 2, 0);
1856 return \"AER %0,%2\";
1858 mvs_check_page (0, 4, 0);
1859 return \"AE %0,%2\";
1863 ;;- Subtract instructions.
1867 ; subdi3 instruction pattern(s).
1870 (define_expand "subdi3"
1871 [(set (match_operand:DI 0 "general_operand" "")
1872 (minus:DI (match_operand:DI 1 "general_operand" "")
1873 (match_operand:DI 2 "general_operand" "")))]
1877 rtx label = gen_label_rtx ();
1878 rtx op0_high = operand_subword (operands[0], 0, 1, DImode);
1879 rtx op0_low = gen_lowpart (SImode, operands[0]);
1881 emit_insn (gen_rtx (SET, VOIDmode, op0_high,
1882 gen_rtx (MINUS, SImode,
1883 operand_subword (operands[1], 0, 1, DImode),
1884 operand_subword (operands[2], 0, 1, DImode))));
1885 emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
1886 gen_rtx (SET, VOIDmode, op0_low,
1887 gen_rtx (MINUS, SImode,
1888 gen_lowpart (SImode, operands[1]),
1889 gen_lowpart (SImode, operands[2]))),
1890 gen_rtx (USE, VOIDmode,
1891 gen_rtx (LABEL_REF, VOIDmode, label)))));
1892 emit_insn (gen_rtx (SET, VOIDmode, op0_high,
1893 gen_rtx (MINUS, SImode, op0_high,
1894 gen_rtx (CONST_INT, SImode, 1))));
1900 [(set (match_operand:SI 0 "general_operand" "=d")
1901 (minus:SI (match_operand:SI 1 "general_operand" "0")
1902 (match_operand:SI 2 "general_operand" "g")))
1903 (use (label_ref (match_operand 3 "" "")))]
1909 check_label_emit ();
1911 onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[3]));
1912 if (REG_P (operands[2]))
1916 mvs_check_page (0, 8, 4);
1917 return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1919 if (mvs_check_page (0, 6, 0))
1921 mvs_check_page (0, 2, 4);
1922 return \"SLR %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1924 return \"SLR %0,%2\;BC 12,%l3\";
1928 mvs_check_page (0, 10, 4);
1929 return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1931 if (mvs_check_page (0, 8, 0))
1933 mvs_check_page (0, 2, 4);
1934 return \"SL %0,%2\;L 14,=A(%l3)\;BCR 12,14\";
1936 return \"SL %0,%2\;BC 12,%l3\";
1940 ; subsi3 instruction pattern(s).
1943 (define_insn "subsi3"
1944 [(set (match_operand:SI 0 "general_operand" "=d")
1945 (minus:SI (match_operand:SI 1 "general_operand" "0")
1946 (match_operand:SI 2 "general_operand" "g")))]
1950 check_label_emit ();
1951 if (REG_P (operands[2]))
1953 mvs_check_page (0, 2, 0);
1954 return \"SR %0,%2\";
1956 if (operands[2] == const1_rtx)
1959 mvs_check_page (0, 2, 0);
1960 return \"BCTR %0,0\";
1962 mvs_check_page (0, 4, 0);
1967 ; subhi3 instruction pattern(s).
1970 (define_insn "subhi3"
1971 [(set (match_operand:HI 0 "general_operand" "=d")
1972 (minus:HI (match_operand:HI 1 "general_operand" "0")
1973 (match_operand:HI 2 "general_operand" "g")))]
1977 check_label_emit ();
1978 if (REG_P (operands[2]))
1980 mvs_check_page (0, 8, 0);
1981 return \"STH %2,140(,13)\;SH %0,140(,13)\";
1983 if (operands[2] == const1_rtx)
1986 mvs_check_page (0, 2, 0);
1987 return \"BCTR %0,0\";
1989 if (GET_CODE (operands[2]) == CONST_INT)
1991 mvs_check_page (0, 4, 0);
1992 return \"SH %0,%H2\";
1994 mvs_check_page (0, 4, 0);
1995 return \"SH %0,%2\";
1999 ; subqi3 instruction pattern(s).
2002 (define_expand "subqi3"
2003 [(set (match_operand:QI 0 "general_operand" "=d")
2004 (minus:QI (match_operand:QI 1 "general_operand" "0")
2005 (match_operand:QI 2 "general_operand" "di")))]
2009 if (REG_P (operands[2]))
2011 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
2012 gen_rtx (MINUS, QImode, operands[1], operands[2])));
2016 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
2017 gen_rtx (PLUS, QImode, operands[1],
2018 negate_rtx (QImode, operands[2]))));
2024 [(set (match_operand:QI 0 "register_operand" "=d")
2025 (minus:QI (match_operand:QI 1 "register_operand" "0")
2026 (match_operand:QI 2 "register_operand" "d")))]
2030 check_label_emit ();
2032 mvs_check_page (0, 2, 0);
2033 return \"SR %0,%2\";
2037 ; subdf3 instruction pattern(s).
2040 (define_insn "subdf3"
2041 [(set (match_operand:DF 0 "general_operand" "=f")
2042 (minus:DF (match_operand:DF 1 "general_operand" "0")
2043 (match_operand:DF 2 "general_operand" "fmF")))]
2047 check_label_emit ();
2048 if (FP_REG_P (operands[2]))
2050 mvs_check_page (0, 2, 0);
2051 return \"SDR %0,%2\";
2053 mvs_check_page (0, 4, 0);
2054 return \"SD %0,%2\";
2058 ; subsf3 instruction pattern(s).
2061 (define_insn "subsf3"
2062 [(set (match_operand:SF 0 "general_operand" "=f")
2063 (minus:SF (match_operand:SF 1 "general_operand" "0")
2064 (match_operand:SF 2 "general_operand" "fmF")))]
2068 check_label_emit ();
2069 if (FP_REG_P (operands[2]))
2071 mvs_check_page (0, 2, 0);
2072 return \"SER %0,%2\";
2074 mvs_check_page (0, 4, 0);
2075 return \"SE %0,%2\";
2079 ;;- Multiply instructions.
2083 ; mulsi3 instruction pattern(s).
2086 (define_expand "mulsi3"
2087 [(set (match_operand:SI 0 "general_operand" "")
2088 (mult:SI (match_operand:SI 1 "general_operand" "")
2089 (match_operand:SI 2 "general_operand" "")))]
2093 if (GET_CODE (operands[1]) == CONST_INT
2094 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
2096 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
2097 gen_rtx (MULT, SImode, operands[2], operands[1])));
2099 else if (GET_CODE (operands[2]) == CONST_INT
2100 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
2102 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
2103 gen_rtx (MULT, SImode, operands[1], operands[2])));
2107 rtx r = gen_reg_rtx (DImode);
2109 emit_insn (gen_rtx (SET, VOIDmode,
2110 gen_rtx (SUBREG, SImode, r, 1), operands[1]));
2111 emit_insn (gen_rtx (SET, VOIDmode, r,
2112 gen_rtx (MULT, SImode, r, operands[2])));
2113 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
2114 gen_rtx (SUBREG, SImode, r, 1)));
2120 [(set (match_operand:SI 0 "register_operand" "=d")
2121 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2122 (match_operand:SI 2 "immediate_operand" "K")))]
2126 check_label_emit ();
2127 mvs_check_page (0, 4, 0);
2128 return \"MH %0,%H2\";
2132 [(set (match_operand:DI 0 "register_operand" "=d")
2133 (mult:SI (match_operand:DI 1 "general_operand" "%0")
2134 (match_operand:SI 2 "general_operand" "g")))]
2138 check_label_emit ();
2139 if (REG_P (operands[2]))
2141 mvs_check_page (0, 2, 0);
2142 return \"MR %0,%2\";
2144 mvs_check_page (0, 4, 0);
2149 ; muldf3 instruction pattern(s).
2152 (define_insn "muldf3"
2153 [(set (match_operand:DF 0 "general_operand" "=f")
2154 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2155 (match_operand:DF 2 "general_operand" "fmF")))]
2159 check_label_emit ();
2160 if (FP_REG_P (operands[2]))
2162 mvs_check_page (0, 2, 0);
2163 return \"MDR %0,%2\";
2165 mvs_check_page (0, 4, 0);
2166 return \"MD %0,%2\";
2170 ; mulsf3 instruction pattern(s).
2173 (define_insn "mulsf3"
2174 [(set (match_operand:SF 0 "general_operand" "=f")
2175 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2176 (match_operand:SF 2 "general_operand" "fmF")))]
2180 check_label_emit ();
2181 if (FP_REG_P (operands[2]))
2183 mvs_check_page (0, 2, 0);
2184 return \"MER %0,%2\";
2186 mvs_check_page (0, 4, 0);
2187 return \"ME %0,%2\";
2191 ;;- Divide instructions.
2195 ; divsi3 instruction pattern(s).
2198 (define_expand "divsi3"
2199 [(set (match_operand:SI 0 "general_operand" "")
2200 (div:SI (match_operand:SI 1 "general_operand" "")
2201 (match_operand:SI 2 "general_operand" "")))]
2205 rtx r = gen_reg_rtx (DImode);
2207 emit_insn (gen_extendsidi2 (r, operands[1]));
2208 emit_insn (gen_rtx (SET, VOIDmode, r,
2209 gen_rtx (DIV, SImode, r, operands[2])));
2210 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
2211 gen_rtx (SUBREG, SImode, r, 1)));
2217 ; udivsi3 instruction pattern(s).
2220 (define_expand "udivsi3"
2221 [(set (match_operand:SI 0 "general_operand" "")
2222 (udiv:SI (match_operand:SI 1 "general_operand" "")
2223 (match_operand:SI 2 "general_operand" "")))]
2227 rtx dr = gen_reg_rtx (DImode);
2228 rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0);
2229 rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1);
2232 if (GET_CODE (operands[2]) == CONST_INT)
2234 if (INTVAL (operands[2]) > 0)
2236 emit_insn (gen_zero_extendsidi2 (dr, operands[1]));
2237 emit_insn (gen_rtx (SET, VOIDmode, dr,
2238 gen_rtx (DIV, SImode, dr, operands[2])));
2242 rtx label1 = gen_label_rtx ();
2244 emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1]));
2245 emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx));
2246 emit_insn (gen_cmpsi (dr_0, operands[2]));
2247 emit_jump_insn (gen_bltu (label1));
2248 emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx));
2249 emit_label (label1);
2254 rtx label1 = gen_label_rtx ();
2255 rtx label2 = gen_label_rtx ();
2256 rtx label3 = gen_label_rtx ();
2257 rtx sr = gen_reg_rtx (SImode);
2259 emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1]));
2260 emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2]));
2261 emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx));
2262 emit_insn (gen_cmpsi (sr, dr_0));
2263 emit_jump_insn (gen_bgtu (label3));
2264 emit_insn (gen_cmpsi (sr, const1_rtx));
2265 emit_jump_insn (gen_blt (label2));
2266 emit_jump_insn (gen_beq (label1));
2267 emit_insn (gen_rtx (SET, VOIDmode, dr,
2268 gen_rtx (LSHIFTRT, DImode, dr,
2269 gen_rtx (CONST_INT, SImode, 32))));
2270 emit_insn (gen_rtx (SET, VOIDmode, dr,
2271 gen_rtx (DIV, SImode, dr, sr)));
2272 emit_jump_insn (gen_jump (label3));
2273 emit_label (label1);
2274 emit_insn (gen_rtx (SET, VOIDmode, dr_1, dr_0));
2275 emit_jump_insn (gen_jump (label3));
2276 emit_label (label2);
2277 emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx));
2278 emit_label (label3);
2280 emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_1));
2285 ; This is used by divsi3 & udivsi3.
2288 [(set (match_operand:DI 0 "register_operand" "=d")
2289 (div:SI (match_operand:DI 1 "register_operand" "0")
2290 (match_operand:SI 2 "general_operand" "")))]
2294 check_label_emit ();
2295 if (REG_P (operands[2]))
2297 mvs_check_page (0, 2, 0);
2298 return \"DR %0,%2\";
2300 mvs_check_page (0, 4, 0);
2305 ; divdf3 instruction pattern(s).
2308 (define_insn "divdf3"
2309 [(set (match_operand:DF 0 "general_operand" "=f")
2310 (div:DF (match_operand:DF 1 "general_operand" "0")
2311 (match_operand:DF 2 "general_operand" "fmF")))]
2315 check_label_emit ();
2316 if (FP_REG_P (operands[2]))
2318 mvs_check_page (0, 2, 0);
2319 return \"DDR %0,%2\";
2321 mvs_check_page (0, 4, 0);
2322 return \"DD %0,%2\";
2326 ; divsf3 instruction pattern(s).
2329 (define_insn "divsf3"
2330 [(set (match_operand:SF 0 "general_operand" "=f")
2331 (div:SF (match_operand:SF 1 "general_operand" "0")
2332 (match_operand:SF 2 "general_operand" "fmF")))]
2336 check_label_emit ();
2337 if (FP_REG_P (operands[2]))
2339 mvs_check_page (0, 2, 0);
2340 return \"DER %0,%2\";
2342 mvs_check_page (0, 4, 0);
2343 return \"DE %0,%2\";
2347 ;;- Modulo instructions.
2351 ; modsi3 instruction pattern(s).
2354 (define_expand "modsi3"
2355 [(set (match_operand:SI 0 "general_operand" "")
2356 (mod:SI (match_operand:SI 1 "general_operand" "")
2357 (match_operand:SI 2 "general_operand" "")))]
2361 rtx r = gen_reg_rtx (DImode);
2363 emit_insn (gen_extendsidi2 (r, operands[1]));
2364 emit_insn (gen_rtx (SET, VOIDmode, r,
2365 gen_rtx (MOD, SImode, r, operands[2])));
2366 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
2367 gen_rtx (SUBREG, SImode, r, 0)));
2372 ; umodsi3 instruction pattern(s).
2375 (define_expand "umodsi3"
2376 [(set (match_operand:SI 0 "general_operand" "")
2377 (umod:SI (match_operand:SI 1 "general_operand" "")
2378 (match_operand:SI 2 "general_operand" "")))]
2382 rtx dr = gen_reg_rtx (DImode);
2383 rtx dr_0 = gen_rtx (SUBREG, SImode, dr, 0);
2384 rtx dr_1 = gen_rtx (SUBREG, SImode, dr, 1);
2386 emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1]));
2388 if (GET_CODE (operands[2]) == CONST_INT)
2390 if (INTVAL (operands[2]) > 0)
2392 emit_insn (gen_rtx (SET, VOIDmode, dr,
2393 gen_rtx (LSHIFTRT, DImode, dr,
2394 gen_rtx (CONST_INT, SImode, 32))));
2395 emit_insn (gen_rtx (SET, VOIDmode, dr,
2396 gen_rtx (MOD, SImode, dr, operands[2])));
2400 rtx label1 = gen_label_rtx ();
2401 rtx sr = gen_reg_rtx (SImode);
2403 emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2]));
2404 emit_insn (gen_cmpsi (dr_0, sr));
2405 emit_jump_insn (gen_bltu (label1));
2406 emit_insn (gen_rtx (SET, VOIDmode, sr, gen_rtx (ABS, SImode, sr)));
2407 emit_insn (gen_rtx (SET, VOIDmode, dr_0,
2408 gen_rtx (PLUS, SImode, dr_0, sr)));
2409 emit_label (label1);
2414 rtx label1 = gen_label_rtx ();
2415 rtx label2 = gen_label_rtx ();
2416 rtx label3 = gen_label_rtx ();
2417 rtx sr = gen_reg_rtx (SImode);
2419 emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[1]));
2420 emit_insn (gen_rtx (SET, VOIDmode, sr, operands[2]));
2421 emit_insn (gen_cmpsi (sr, dr_0));
2422 emit_jump_insn (gen_bgtu (label3));
2423 emit_insn (gen_cmpsi (sr, const1_rtx));
2424 emit_jump_insn (gen_blt (label2));
2425 emit_jump_insn (gen_beq (label1));
2426 emit_insn (gen_rtx (SET, VOIDmode, dr,
2427 gen_rtx (LSHIFTRT, DImode, dr,
2428 gen_rtx (CONST_INT, SImode, 32))));
2429 emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (MOD, SImode, dr, sr)));
2430 emit_jump_insn (gen_jump (label3));
2431 emit_label (label1);
2432 emit_insn (gen_rtx (SET, VOIDmode, dr_0, const0_rtx));
2433 emit_jump_insn (gen_jump (label3));
2434 emit_label (label2);
2435 emit_insn (gen_rtx (SET, VOIDmode, dr_0,
2436 gen_rtx (MINUS, SImode, dr_0, sr)));
2437 emit_label (label3);
2440 emit_insn (gen_rtx (SET, VOIDmode, operands[0], dr_0));
2445 ; This is used by modsi3 & umodsi3.
2448 [(set (match_operand:DI 0 "register_operand" "=d")
2449 (mod:SI (match_operand:DI 1 "register_operand" "0")
2450 (match_operand:SI 2 "general_operand" "")))]
2454 check_label_emit ();
2455 if (REG_P (operands[2]))
2457 mvs_check_page (0, 2, 0);
2458 return \"DR %0,%2\";
2460 mvs_check_page (0, 4, 0);
2465 ;;- And instructions.
2469 ; anddi3 instruction pattern(s).
2472 ;(define_expand "anddi3"
2473 ; [(set (match_operand:DI 0 "general_operand" "")
2474 ; (and:DI (match_operand:DI 1 "general_operand" "")
2475 ; (match_operand:DI 2 "general_operand" "")))]
2481 ; emit_insn (gen_andsi3 (operand_subword (operands[0], 0, 1, DImode),
2482 ; operand_subword (operands[1], 0, 1, DImode),
2483 ; operand_subword (operands[2], 0, 1, DImode)));
2484 ; emit_insn (gen_andsi3 (gen_lowpart (SImode, operands[0]),
2485 ; gen_lowpart (SImode, operands[1]),
2486 ; gen_lowpart (SImode, operands[2])));
2491 ; andsi3 instruction pattern(s).
2495 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
2496 (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
2497 (match_operand:SI 2 "r_or_s_operand" "g,mi")))]
2498 "TARGET_CHAR_INSTRUCTIONS"
2501 check_label_emit ();
2502 if (REG_P (operands[2]))
2504 mvs_check_page (0, 2, 0);
2505 return \"NR %0,%2\";
2507 if (REG_P (operands[0]))
2509 mvs_check_page (0, 4, 0);
2513 mvs_check_page (0, 6, 0);
2514 return \"NC %O0(4,%R0),%2\";
2517 (define_insn "andsi3"
2518 [(set (match_operand:SI 0 "general_operand" "=d")
2519 (and:SI (match_operand:SI 1 "general_operand" "%0")
2520 (match_operand:SI 2 "general_operand" "g")))]
2524 check_label_emit ();
2525 if (REG_P (operands[2]))
2527 mvs_check_page (0, 2, 0);
2528 return \"NR %0,%2\";
2530 mvs_check_page (0, 4, 0);
2535 ; andhi3 instruction pattern(s).
2539 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
2540 (and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
2541 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
2542 "TARGET_CHAR_INSTRUCTIONS"
2545 check_label_emit ();
2546 if (REG_P (operands[2]))
2548 mvs_check_page (0, 2, 0);
2549 return \"NR %0,%2\";
2551 if (REG_P (operands[0]))
2553 mvs_check_page (0, 4, 0);
2557 if (GET_CODE (operands[2]) == CONST_INT)
2559 mvs_check_page (0, 6, 0);
2560 return \"NC %O0(2,%R0),%H2\";
2562 mvs_check_page (0, 6, 0);
2563 return \"NC %O0(2,%R0),%2\";
2566 (define_insn "andhi3"
2567 [(set (match_operand:HI 0 "general_operand" "=d")
2568 (and:HI (match_operand:HI 1 "general_operand" "%0")
2569 (match_operand:HI 2 "general_operand" "di")))]
2573 check_label_emit ();
2574 if (GET_CODE (operands[2]) == CONST_INT)
2576 mvs_check_page (0, 4, 0);
2579 mvs_check_page (0, 2, 0);
2580 return \"NR %0,%2\";
2584 ; andqi3 instruction pattern(s).
2588 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
2589 (and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
2590 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
2591 "TARGET_CHAR_INSTRUCTIONS"
2594 check_label_emit ();
2596 if (REG_P (operands[2]))
2598 mvs_check_page (0, 2, 0);
2599 return \"NR %0,%2\";
2601 if (REG_P (operands[0]))
2603 mvs_check_page (0, 4, 0);
2606 if (GET_CODE (operands[2]) == CONST_INT)
2608 mvs_check_page (0, 4, 0);
2609 return \"NI %0,%B2\";
2611 mvs_check_page (0, 6, 0);
2612 return \"NC %O0(1,%R0),%2\";
2615 (define_insn "andqi3"
2616 [(set (match_operand:QI 0 "general_operand" "=d")
2617 (and:QI (match_operand:QI 1 "general_operand" "%0")
2618 (match_operand:QI 2 "general_operand" "di")))]
2622 check_label_emit ();
2624 if (GET_CODE (operands[2]) == CONST_INT)
2626 mvs_check_page (0, 4, 0);
2629 mvs_check_page (0, 2, 0);
2630 return \"NR %0,%2\";
2634 ;;- Bit set (inclusive or) instructions.
2638 ; iordi3 instruction pattern(s).
2641 ;(define_expand "iordi3"
2642 ; [(set (match_operand:DI 0 "general_operand" "")
2643 ; (ior:DI (match_operand:DI 1 "general_operand" "")
2644 ; (match_operand:DI 2 "general_operand" "")))]
2650 ; emit_insn (gen_iorsi3 (operand_subword (operands[0], 0, 1, DImode),
2651 ; operand_subword (operands[1], 0, 1, DImode),
2652 ; operand_subword (operands[2], 0, 1, DImode)));
2653 ; emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]),
2654 ; gen_lowpart (SImode, operands[1]),
2655 ; gen_lowpart (SImode, operands[2])));
2660 ; iorsi3 instruction pattern(s).
2664 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
2665 (ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
2666 (match_operand:SI 2 "r_or_s_operand" "g,mi")))]
2667 "TARGET_CHAR_INSTRUCTIONS"
2670 check_label_emit ();
2671 if (REG_P (operands[2]))
2673 mvs_check_page (0, 2, 0);
2674 return \"OR %0,%2\";
2676 if (REG_P (operands[0]))
2678 mvs_check_page (0, 4, 0);
2682 mvs_check_page (0, 6, 0);
2683 return \"OC %O0(4,%R0),%2\";
2686 (define_insn "iorsi3"
2687 [(set (match_operand:SI 0 "general_operand" "=d")
2688 (ior:SI (match_operand:SI 1 "general_operand" "%0")
2689 (match_operand:SI 2 "general_operand" "g")))]
2693 check_label_emit ();
2694 if (REG_P (operands[2]))
2696 mvs_check_page (0, 2, 0);
2697 return \"OR %0,%2\";
2699 mvs_check_page (0, 4, 0);
2704 ; iorhi3 instruction pattern(s).
2708 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
2709 (ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
2710 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
2711 "TARGET_CHAR_INSTRUCTIONS"
2714 check_label_emit ();
2715 if (REG_P (operands[2]))
2717 mvs_check_page (0, 2, 0);
2718 return \"OR %0,%2\";
2720 if (REG_P (operands[0]))
2722 mvs_check_page (0, 4, 0);
2726 if (GET_CODE (operands[2]) == CONST_INT)
2728 mvs_check_page (0, 6, 0);
2729 return \"OC %O0(2,%R0),%H2\";
2731 mvs_check_page (0, 6, 0);
2732 return \"OC %O0(2,%R0),%2\";
2735 (define_insn "iorhi3"
2736 [(set (match_operand:HI 0 "general_operand" "=d")
2737 (ior:HI (match_operand:HI 1 "general_operand" "%0")
2738 (match_operand:HI 2 "general_operand" "di")))]
2742 check_label_emit ();
2743 if (GET_CODE (operands[2]) == CONST_INT)
2745 mvs_check_page (0, 4, 0);
2748 mvs_check_page (0, 2, 0);
2749 return \"OR %0,%2\";
2753 ; iorqi3 instruction pattern(s).
2757 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
2758 (ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
2759 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
2760 "TARGET_CHAR_INSTRUCTIONS"
2763 check_label_emit ();
2765 if (REG_P (operands[2]))
2767 mvs_check_page (0, 2, 0);
2768 return \"OR %0,%2\";
2770 if (REG_P (operands[0]))
2772 mvs_check_page (0, 4, 0);
2776 if (GET_CODE (operands[2]) == CONST_INT)
2778 mvs_check_page (0, 4, 0);
2779 return \"OI %0,%B2\";
2781 mvs_check_page (0, 6, 0);
2782 return \"OC %O0(1,%R0),%2\";
2785 (define_insn "iorqi3"
2786 [(set (match_operand:QI 0 "general_operand" "=d")
2787 (ior:QI (match_operand:QI 1 "general_operand" "%0")
2788 (match_operand:QI 2 "general_operand" "di")))]
2792 check_label_emit ();
2794 if (GET_CODE (operands[2]) == CONST_INT)
2796 mvs_check_page (0, 4, 0);
2799 mvs_check_page (0, 2, 0);
2800 return \"OR %0,%2\";
2804 ;;- Xor instructions.
2808 ; xordi3 instruction pattern(s).
2811 ;(define_expand "xordi3"
2812 ; [(set (match_operand:DI 0 "general_operand" "")
2813 ; (xor:DI (match_operand:DI 1 "general_operand" "")
2814 ; (match_operand:DI 2 "general_operand" "")))]
2820 ; emit_insn (gen_xorsi3 (operand_subword (operands[0], 0, 1, DImode),
2821 ; operand_subword (operands[1], 0, 1, DImode),
2822 ; operand_subword (operands[2], 0, 1, DImode)));
2823 ; emit_insn (gen_xorsi3 (gen_lowpart (SImode, operands[0]),
2824 ; gen_lowpart (SImode, operands[1]),
2825 ; gen_lowpart (SImode, operands[2])));
2830 ; xorsi3 instruction pattern(s).
2834 [(set (match_operand:SI 0 "r_or_s_operand" "=d,m")
2835 (xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0")
2836 (match_operand:SI 2 "r_or_s_operand" "g,mi")))]
2837 "TARGET_CHAR_INSTRUCTIONS"
2840 check_label_emit ();
2841 if (REG_P (operands[2]))
2843 mvs_check_page (0, 2, 0);
2844 return \"XR %0,%2\";
2846 if (REG_P (operands[0]))
2848 mvs_check_page (0, 4, 0);
2852 mvs_check_page (0, 6, 0);
2853 return \"XC %O0(4,%R0),%2\";
2856 (define_insn "xorsi3"
2857 [(set (match_operand:SI 0 "general_operand" "=d")
2858 (xor:SI (match_operand:SI 1 "general_operand" "%0")
2859 (match_operand:SI 2 "general_operand" "g")))]
2863 check_label_emit ();
2864 if (REG_P (operands[2]))
2866 mvs_check_page (0, 2, 0);
2867 return \"XR %0,%2\";
2869 mvs_check_page (0, 4, 0);
2874 ; xorhi3 instruction pattern(s).
2878 [(set (match_operand:HI 0 "r_or_s_operand" "=d,m")
2879 (xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
2880 (match_operand:HI 2 "r_or_s_operand" "di,mi")))]
2881 "TARGET_CHAR_INSTRUCTIONS"
2884 check_label_emit ();
2885 if (REG_P (operands[2]))
2887 mvs_check_page (0, 2, 0);
2888 return \"XR %0,%2\";
2890 if (REG_P (operands[0]))
2892 mvs_check_page (0, 4, 0);
2896 if (GET_CODE (operands[2]) == CONST_INT)
2898 mvs_check_page (0, 6, 0);
2899 return \"XC %O0(2,%R0),%H2\";
2901 mvs_check_page (0, 6, 0);
2902 return \"XC %O0(2,%R0),%2\";
2905 (define_insn "xorhi3"
2906 [(set (match_operand:HI 0 "general_operand" "=d")
2907 (xor:HI (match_operand:HI 1 "general_operand" "%0")
2908 (match_operand:HI 2 "general_operand" "di")))]
2912 check_label_emit ();
2913 if (GET_CODE (operands[2]) == CONST_INT)
2915 mvs_check_page (0, 4, 0);
2918 mvs_check_page (0, 2, 0);
2919 return \"XR %0,%2\";
2923 ; xorqi3 instruction pattern(s).
2927 [(set (match_operand:QI 0 "r_or_s_operand" "=d,m")
2928 (xor:QI (match_operand:QI 1 "r_or_s_operand" "%0,0")
2929 (match_operand:QI 2 "r_or_s_operand" "di,mi")))]
2930 "TARGET_CHAR_INSTRUCTIONS"
2933 check_label_emit ();
2935 if (REG_P (operands[2]))
2937 mvs_check_page (0, 2, 0);
2938 return \"XR %0,%2\";
2940 if (REG_P (operands[0]))
2942 mvs_check_page (0, 4, 0);
2945 if (GET_CODE (operands[2]) == CONST_INT)
2947 mvs_check_page (0, 4, 0);
2948 return \"XI %0,%B2\";
2950 mvs_check_page (0, 6, 0);
2951 return \"XC %O0(1,%R0),%2\";
2954 (define_insn "xorqi3"
2955 [(set (match_operand:QI 0 "general_operand" "=d")
2956 (xor:QI (match_operand:QI 1 "general_operand" "%0")
2957 (match_operand:QI 2 "general_operand" "di")))]
2961 check_label_emit ();
2963 if (GET_CODE (operands[2]) == CONST_INT)
2965 mvs_check_page (0, 4, 0);
2968 mvs_check_page (0, 2, 0);
2969 return \"XR %0,%2\";
2973 ;;- Negate instructions.
2977 ; negsi2 instruction pattern(s).
2980 (define_insn "negsi2"
2981 [(set (match_operand:SI 0 "general_operand" "=d")
2982 (neg:SI (match_operand:SI 1 "general_operand" "d")))]
2986 check_label_emit ();
2987 mvs_check_page (0, 2, 0);
2988 return \"LCR %0,%1\";
2992 ; neghi2 instruction pattern(s).
2995 (define_insn "neghi2"
2996 [(set (match_operand:HI 0 "general_operand" "=d")
2997 (neg:HI (match_operand:HI 1 "general_operand" "d")))]
3001 check_label_emit ();
3002 mvs_check_page (0, 10, 0);
3003 return \"SLL %1,16\;SRA %1,16\;LCR %0,%1\";
3007 ; negdf2 instruction pattern(s).
3010 (define_insn "negdf2"
3011 [(set (match_operand:DF 0 "general_operand" "=f")
3012 (neg:DF (match_operand:DF 1 "general_operand" "f")))]
3016 check_label_emit ();
3017 mvs_check_page (0, 2, 0);
3018 return \"LCDR %0,%1\";
3022 ; negsf2 instruction pattern(s).
3025 (define_insn "negsf2"
3026 [(set (match_operand:SF 0 "general_operand" "=f")
3027 (neg:SF (match_operand:SF 1 "general_operand" "f")))]
3031 check_label_emit ();
3032 mvs_check_page (0, 2, 0);
3033 return \"LCER %0,%1\";
3037 ;;- Absolute value instructions.
3041 ; abssi2 instruction pattern(s).
3044 (define_insn "abssi2"
3045 [(set (match_operand:SI 0 "general_operand" "=d")
3046 (abs:SI (match_operand:SI 1 "general_operand" "d")))]
3050 check_label_emit ();
3051 mvs_check_page (0, 2, 0);
3052 return \"LPR %0,%1\";
3056 ; abshi2 instruction pattern(s).
3059 (define_insn "abshi2"
3060 [(set (match_operand:HI 0 "general_operand" "=d")
3061 (abs:HI (match_operand:HI 1 "general_operand" "d")))]
3065 check_label_emit ();
3066 mvs_check_page (0, 10, 0);
3067 return \"SLL %1,16\;SRA %1,16\;LPR %0,%1\";
3071 ; absdf2 instruction pattern(s).
3074 (define_insn "absdf2"
3075 [(set (match_operand:DF 0 "general_operand" "=f")
3076 (abs:DF (match_operand:DF 1 "general_operand" "f")))]
3080 check_label_emit ();
3081 mvs_check_page (0, 2, 0);
3082 return \"LPDR %0,%1\";
3086 ; abssf2 instruction pattern(s).
3089 (define_insn "abssf2"
3090 [(set (match_operand:SF 0 "general_operand" "=f")
3091 (abs:SF (match_operand:SF 1 "general_operand" "f")))]
3095 check_label_emit ();
3096 mvs_check_page (0, 2, 0);
3097 return \"LPER %0,%1\";
3101 ;;- One complement instructions.
3105 ; one_cmpldi2 instruction pattern(s).
3108 ;(define_expand "one_cmpldi2"
3109 ; [(set (match_operand:DI 0 "general_operand" "")
3110 ; (not:DI (match_operand:DI 1 "general_operand" "")))]
3114 ; rtx gen_one_cmplsi2();
3116 ; emit_insn (gen_one_cmplsi2 (operand_subword (operands[0], 0, 1, DImode),
3117 ; operand_subword (operands[1], 0, 1, DImode)));
3118 ; emit_insn (gen_one_cmplsi2 (gen_lowpart (SImode, operands[0]),
3119 ; gen_lowpart (SImode, operands[1])));
3124 ; one_cmplsi2 instruction pattern(s).
3128 [(set (match_operand:SI 0 "r_or_s_operand" "=dm")
3129 (not:SI (match_operand:SI 1 "r_or_s_operand" "0")))]
3130 "TARGET_CHAR_INSTRUCTIONS"
3133 check_label_emit ();
3134 if (REG_P (operands[0]))
3136 mvs_check_page (0, 4, 4);
3137 return \"X %0,=F'-1'\";
3140 mvs_check_page (0, 6, 4);
3141 return \"XC %O0(4,%R0),=F'-1'\";
3144 (define_insn "one_cmplsi2"
3145 [(set (match_operand:SI 0 "general_operand" "=d")
3146 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3150 check_label_emit ();
3151 mvs_check_page (0, 4, 4);
3152 return \"X %0,=F'-1'\";
3156 ; one_cmplhi2 instruction pattern(s).
3160 [(set (match_operand:HI 0 "r_or_s_operand" "=dm")
3161 (not:HI (match_operand:HI 1 "r_or_s_operand" "0")))]
3162 "TARGET_CHAR_INSTRUCTIONS"
3165 check_label_emit ();
3166 if (REG_P (operands[0]))
3168 mvs_check_page (0, 4, 4);
3169 return \"X %0,=F'-1'\";
3172 mvs_check_page (0, 6, 4);
3173 return \"XC %O0(2,%R0),=X'FFFF'\";
3176 (define_insn "one_cmplhi2"
3177 [(set (match_operand:HI 0 "general_operand" "=d")
3178 (not:HI (match_operand:HI 1 "general_operand" "0")))]
3182 check_label_emit ();
3183 mvs_check_page (0, 4, 4);
3184 return \"X %0,=F'-1'\";
3188 ; one_cmplqi2 instruction pattern(s).
3192 [(set (match_operand:QI 0 "r_or_s_operand" "=dm")
3193 (not:QI (match_operand:QI 1 "r_or_s_operand" "0")))]
3194 "TARGET_CHAR_INSTRUCTIONS"
3197 check_label_emit ();
3199 if (REG_P (operands[0]))
3201 mvs_check_page (0, 4, 4);
3202 return \"X %0,=F'-1'\";
3204 mvs_check_page (0, 4, 0);
3205 return \"XI %0,255\";
3208 (define_insn "one_cmplqi2"
3209 [(set (match_operand:QI 0 "general_operand" "=d")
3210 (not:QI (match_operand:QI 1 "general_operand" "0")))]
3214 check_label_emit ();
3216 mvs_check_page (0, 4, 4);
3217 return \"X %0,=F'-1'\";
3221 ;;- Arithmetic shift instructions.
3225 ; ashldi3 instruction pattern(s).
3228 (define_insn "ashldi3"
3229 [(set (match_operand:DI 0 "general_operand" "=d")
3230 (ashift:DI (match_operand:DI 1 "general_operand" "0")
3231 (match_operand:SI 2 "general_operand" "Ja")))]
3235 check_label_emit ();
3237 mvs_check_page (0, 4, 0);
3238 if (REG_P (operands[2]))
3239 return \"SLDA %0,0(%2)\";
3240 return \"SLDA %0,%c2\";
3244 ; ashrdi3 instruction pattern(s).
3247 (define_insn "ashrdi3"
3248 [(set (match_operand:DI 0 "register_operand" "=d")
3249 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
3250 (match_operand:SI 2 "general_operand" "Ja")))]
3254 check_label_emit ();
3255 mvs_check_page (0, 4, 0);
3256 if (REG_P (operands[2]))
3257 return \"SRDA %0,0(%2)\";
3258 return \"SRDA %0,%c2\";
3262 ; ashlsi3 instruction pattern(s).
3265 (define_insn "ashlsi3"
3266 [(set (match_operand:SI 0 "general_operand" "=d")
3267 (ashift:SI (match_operand:SI 1 "general_operand" "0")
3268 (match_operand:SI 2 "general_operand" "Ja")))]
3272 check_label_emit ();
3274 mvs_check_page (0, 4, 0);
3275 if (REG_P (operands[2]))
3276 return \"SLL %0,0(%2)\";
3277 return \"SLL %0,%c2\";
3281 ; ashrsi3 instruction pattern(s).
3284 (define_insn "ashrsi3"
3285 [(set (match_operand:SI 0 "general_operand" "=d")
3286 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
3287 (match_operand:SI 2 "general_operand" "Ja")))]
3291 check_label_emit ();
3292 mvs_check_page (0, 4, 0);
3293 if (REG_P (operands[2]))
3294 return \"SRA %0,0(%2)\";
3295 return \"SRA %0,%c2\";
3299 ; ashlhi3 instruction pattern(s).
3302 (define_insn "ashlhi3"
3303 [(set (match_operand:HI 0 "general_operand" "=d")
3304 (ashift:HI (match_operand:HI 1 "general_operand" "0")
3305 (match_operand:SI 2 "general_operand" "Ja")))]
3309 check_label_emit ();
3310 mvs_check_page (0, 8, 0);
3311 if (REG_P (operands[2]))
3312 return \"SLL %0,16(%2)\;SRA %0,16\";
3313 return \"SLL %0,16+%c2\;SRA %0,16\";
3317 ; ashrhi3 instruction pattern(s).
3320 (define_insn "ashrhi3"
3321 [(set (match_operand:HI 0 "general_operand" "=d")
3322 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
3323 (match_operand:SI 2 "general_operand" "Ja")))]
3327 check_label_emit ();
3328 mvs_check_page (0, 4, 0);
3329 if (REG_P (operands[2]))
3330 return \"SLL %0,16\;SRA %0,16(%2)\";
3331 return \"SLL %0,16\;SRA %0,16+%c2\";
3335 ; ashlqi3 instruction pattern(s).
3338 (define_insn "ashlqi3"
3339 [(set (match_operand:QI 0 "general_operand" "=d")
3340 (ashift:QI (match_operand:QI 1 "general_operand" "0")
3341 (match_operand:SI 2 "general_operand" "Ja")))]
3345 check_label_emit ();
3347 mvs_check_page (0, 4, 0);
3348 if (REG_P (operands[2]))
3349 return \"SLL %0,0(%2)\";
3350 return \"SLL %0,%c2\";
3354 ; ashrqi3 instruction pattern(s).
3357 (define_insn "ashrqi3"
3358 [(set (match_operand:QI 0 "general_operand" "=d")
3359 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
3360 (match_operand:SI 2 "general_operand" "Ja")))]
3364 check_label_emit ();
3365 mvs_check_page (0, 8, 0);
3366 if (REG_P (operands[2]))
3367 return \"SLL %0,24\;SRA %0,24(%2)\";
3368 return \"SLL %0,24\;SRA %0,24+%c2\";
3372 ;;- Logical shift instructions.
3376 ; lshrdi3 instruction pattern(s).
3379 (define_insn "lshrdi3"
3380 [(set (match_operand:DI 0 "general_operand" "=d")
3381 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
3382 (match_operand:SI 2 "general_operand" "Ja")))]
3386 check_label_emit ();
3387 mvs_check_page (0, 4, 0);
3388 if (REG_P (operands[2]))
3389 return \"SRDL %0,0(%2)\";
3390 return \"SRDL %0,%c2\";
3395 ; lshrsi3 instruction pattern(s).
3398 (define_insn "lshrsi3"
3399 [(set (match_operand:SI 0 "general_operand" "=d")
3400 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
3401 (match_operand:SI 2 "general_operand" "Ja")))]
3405 check_label_emit ();
3406 mvs_check_page (0, 4, 0);
3407 if (REG_P (operands[2]))
3408 return \"SRL %0,0(%2)\";
3409 return \"SRL %0,%c2\";
3413 ; lshrhi3 instruction pattern(s).
3416 (define_insn "lshrhi3"
3417 [(set (match_operand:HI 0 "general_operand" "=d")
3418 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
3419 (match_operand:SI 2 "general_operand" "Ja")))]
3423 check_label_emit ();
3425 if (REG_P (operands[2]))
3427 mvs_check_page (0, 8, 4);
3428 return \"N %0,=X'0000FFFF'\;SRL %0,0(%2)\";
3430 mvs_check_page (0, 8, 4);
3431 return \"N %0,=X'0000FFFF'\;SRL %0,%c2\";
3435 ; lshrqi3 instruction pattern(s).
3438 (define_insn "lshrqi3"
3439 [(set (match_operand:QI 0 "general_operand" "=d")
3440 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
3441 (match_operand:SI 2 "general_operand" "Ja")))]
3445 check_label_emit ();
3447 mvs_check_page (0, 8, 4);
3448 if (REG_P (operands[2]))
3449 return \"N %0,=X'000000FF'\;SRL %0,0(%2)\";
3450 return \"N %0,=X'000000FF'\;SRL %0,%c2\";
3454 ;;- Conditional jump instructions.
3458 ; beq instruction pattern(s).
3463 (if_then_else (eq (cc0)
3465 (label_ref (match_operand 0 "" ""))
3470 check_label_emit ();
3471 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3473 mvs_check_page (0, 6, 4);
3474 return \"L 14,=A(%l0)\;BER 14\";
3476 if (mvs_check_page (0, 4, 0))
3478 mvs_check_page (0, 2, 4);
3479 return \"L 14,=A(%l0)\;BER 14\";
3485 ; bne instruction pattern(s).
3490 (if_then_else (ne (cc0)
3492 (label_ref (match_operand 0 "" ""))
3497 check_label_emit ();
3498 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3500 mvs_check_page (0, 6, 4);
3501 return \"L 14,=A(%l0)\;BNER 14\";
3503 if (mvs_check_page (0, 4, 0))
3505 mvs_check_page (0, 2, 4);
3506 return \"L 14,=A(%l0)\;BNER 14\";
3512 ; bgt instruction pattern(s).
3517 (if_then_else (gt (cc0)
3519 (label_ref (match_operand 0 "" ""))
3524 check_label_emit ();
3525 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3527 mvs_check_page (0, 6, 4);
3528 return \"L 14,=A(%l0)\;BHR 14\";
3530 if (mvs_check_page (0, 4, 0))
3532 mvs_check_page (0, 2, 4);
3533 return \"L 14,=A(%l0)\;BHR 14\";
3539 ; bgtu instruction pattern(s).
3544 (if_then_else (gtu (cc0)
3546 (label_ref (match_operand 0 "" ""))
3551 check_label_emit ();
3552 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3554 mvs_check_page (0, 6, 4);
3555 return \"L 14,=A(%l0)\;BHR 14\";
3557 if (mvs_check_page (0, 4, 0))
3559 mvs_check_page (0, 2, 4);
3560 return \"L 14,=A(%l0)\;BHR 14\";
3566 ; blt instruction pattern(s).
3571 (if_then_else (lt (cc0)
3573 (label_ref (match_operand 0 "" ""))
3578 check_label_emit ();
3579 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3581 mvs_check_page (0, 6, 4);
3582 return \"L 14,=A(%l0)\;BLR 14\";
3584 if (mvs_check_page (0, 4, 0))
3586 mvs_check_page (0, 2, 4);
3587 return \"L 14,=A(%l0)\;BLR 14\";
3593 ; bltu instruction pattern(s).
3598 (if_then_else (ltu (cc0)
3600 (label_ref (match_operand 0 "" ""))
3605 check_label_emit ();
3606 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3608 mvs_check_page (0, 6, 4);
3609 return \"L 14,=A(%l0)\;BLR 14\";
3611 if (mvs_check_page (0, 4, 0))
3613 mvs_check_page (0, 2, 4);
3614 return \"L 14,=A(%l0)\;BLR 14\";
3620 ; bge instruction pattern(s).
3625 (if_then_else (ge (cc0)
3627 (label_ref (match_operand 0 "" ""))
3632 check_label_emit ();
3633 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3635 mvs_check_page (0, 6, 4);
3636 return \"L 14,=A(%l0)\;BNLR 14\";
3638 if (mvs_check_page (0, 4, 0))
3640 mvs_check_page (0, 2, 4);
3641 return \"L 14,=A(%l0)\;BNLR 14\";
3647 ; bgeu instruction pattern(s).
3652 (if_then_else (geu (cc0)
3654 (label_ref (match_operand 0 "" ""))
3659 check_label_emit ();
3660 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3662 mvs_check_page (0, 6, 4);
3663 return \"L 14,=A(%l0)\;BNLR 14\";
3665 if (mvs_check_page (0, 4, 0))
3667 mvs_check_page (0, 2, 4);
3668 return \"L 14,=A(%l0)\;BNLR 14\";
3674 ; ble instruction pattern(s).
3679 (if_then_else (le (cc0)
3681 (label_ref (match_operand 0 "" ""))
3686 check_label_emit ();
3687 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3689 mvs_check_page (0, 6, 4);
3690 return \"L 14,=A(%l0)\;BNHR 14\";
3692 if (mvs_check_page (0, 4, 0))
3694 mvs_check_page (0, 2, 4);
3695 return \"L 14,=A(%l0)\;BNHR 14\";
3701 ; bleu instruction pattern(s).
3706 (if_then_else (leu (cc0)
3708 (label_ref (match_operand 0 "" ""))
3713 check_label_emit ();
3714 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3716 mvs_check_page (0, 6, 4);
3717 return \"L 14,=A(%l0)\;BNHR 14\";
3719 if (mvs_check_page (0, 4, 0))
3721 mvs_check_page (0, 2, 4);
3722 return \"L 14,=A(%l0)\;BNHR 14\";
3728 ;;- Negated conditional jump instructions.
3733 (if_then_else (eq (cc0)
3736 (label_ref (match_operand 0 "" ""))))]
3740 check_label_emit ();
3741 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3743 mvs_check_page (0, 6, 4);
3744 return \"L 14,=A(%l0)\;BNER 14\";
3746 if (mvs_check_page (0, 4, 0))
3748 mvs_check_page (0, 2, 4);
3749 return \"L 14,=A(%l0)\;BNER 14\";
3756 (if_then_else (ne (cc0)
3759 (label_ref (match_operand 0 "" ""))))]
3763 check_label_emit ();
3764 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3766 mvs_check_page (0, 6, 4);
3767 return \"L 14,=A(%l0)\;BER 14\";
3769 if (mvs_check_page (0, 4, 0))
3771 mvs_check_page (0, 2, 4);
3772 return \"L 14,=A(%l0)\;BER 14\";
3779 (if_then_else (gt (cc0)
3782 (label_ref (match_operand 0 "" ""))))]
3786 check_label_emit ();
3787 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3789 mvs_check_page (0, 6, 4);
3790 return \"L 14,=A(%l0)\;BNHR 14\";
3792 if (mvs_check_page (0, 4, 0))
3794 mvs_check_page (0, 2, 4);
3795 return \"L 14,=A(%l0)\;BNHR 14\";
3802 (if_then_else (gtu (cc0)
3805 (label_ref (match_operand 0 "" ""))))]
3809 check_label_emit ();
3810 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3812 mvs_check_page (0, 6, 4);
3813 return \"L 14,=A(%l0)\;BNHR 14\";
3815 if (mvs_check_page (0, 4, 0))
3817 mvs_check_page (0, 2, 4);
3818 return \"L 14,=A(%l0)\;BNHR 14\";
3825 (if_then_else (lt (cc0)
3828 (label_ref (match_operand 0 "" ""))))]
3832 check_label_emit ();
3833 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3835 mvs_check_page (0, 6, 4);
3836 return \"L 14,=A(%l0)\;BNLR 14\";
3838 if (mvs_check_page (0, 4, 0))
3840 mvs_check_page (0, 2, 4);
3841 return \"L 14,=A(%l0)\;BNLR 14\";
3848 (if_then_else (ltu (cc0)
3851 (label_ref (match_operand 0 "" ""))))]
3855 check_label_emit ();
3856 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3858 mvs_check_page (0, 6, 4);
3859 return \"L 14,=A(%l0)\;BNLR 14\";
3861 if (mvs_check_page (0, 4, 0))
3863 mvs_check_page (0, 2, 4);
3864 return \"L 14,=A(%l0)\;BNLR 14\";
3871 (if_then_else (ge (cc0)
3874 (label_ref (match_operand 0 "" ""))))]
3878 check_label_emit ();
3879 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3881 mvs_check_page (0, 6, 4);
3882 return \"L 14,=A(%l0)\;BLR 14\";
3884 if (mvs_check_page (0, 4, 0))
3886 mvs_check_page (0, 2, 4);
3887 return \"L 14,=A(%l0)\;BLR 14\";
3894 (if_then_else (geu (cc0)
3897 (label_ref (match_operand 0 "" ""))))]
3901 check_label_emit ();
3902 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3904 mvs_check_page (0, 6, 4);
3905 return \"L 14,=A(%l0)\;BLR 14\";
3907 if (mvs_check_page (0, 4, 0))
3909 mvs_check_page (0, 2, 4);
3910 return \"L 14,=A(%l0)\;BLR 14\";
3917 (if_then_else (le (cc0)
3920 (label_ref (match_operand 0 "" ""))))]
3924 check_label_emit ();
3925 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3927 mvs_check_page (0, 6, 4);
3928 return \"L 14,=A(%l0)\;BHR 14\";
3930 if (mvs_check_page (0, 4, 0))
3932 mvs_check_page (0, 2, 4);
3933 return \"L 14,=A(%l0)\;BHR 14\";
3940 (if_then_else (leu (cc0)
3943 (label_ref (match_operand 0 "" ""))))]
3947 check_label_emit ();
3948 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
3950 mvs_check_page (0, 6, 4);
3951 return \"L 14,=A(%l0)\;BHR 14\";
3953 if (mvs_check_page (0, 4, 0))
3955 mvs_check_page (0, 2, 4);
3956 return \"L 14,=A(%l0)\;BHR 14\";
3962 ;;- Subtract one and jump if not zero.
3968 (ne (plus:SI (match_operand:SI 0 "register_operand" "+d")
3971 (label_ref (match_operand 1 "" ""))
3974 (plus:SI (match_dup 0)
3979 check_label_emit ();
3980 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1])))
3982 mvs_check_page (0, 6, 4);
3983 return \"L 14,=A(%l1)\;BCTR %0,14\";
3985 if (mvs_check_page (0, 4, 0))
3987 mvs_check_page (0, 2, 4);
3988 return \"L 14,=A(%l1)\;BCTR %0,14\";
3990 return \"BCT %0,%l1\";
3996 (eq (plus:SI (match_operand:SI 0 "register_operand" "+d")
4000 (label_ref (match_operand 1 "" ""))))
4002 (plus:SI (match_dup 0)
4007 check_label_emit ();
4008 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[1])))
4010 mvs_check_page (0, 6, 4);
4011 return \"L 14,=A(%l1)\;BCTR %0,14\";
4013 if (mvs_check_page (0, 4, 0))
4015 mvs_check_page (0, 2, 4);
4016 return \"L 14,=A(%l1)\;BCTR %0,14\";
4018 return \"BCT %0,%l1\";
4022 ;;- Unconditional jump instructions.
4026 ; jump instruction pattern(s).
4031 (label_ref (match_operand 0 "" "")))]
4035 check_label_emit ();
4036 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[0])))
4038 mvs_check_page (0, 6, 4);
4039 return \"L 14,=A(%l0)\;BR 14\";
4041 if (mvs_check_page (0, 4, 0))
4043 mvs_check_page (0, 2, 4);
4044 return \"L 14,=A(%l0)\;BR 14\";
4050 ; indirect-jump instruction pattern(s).
4053 (define_insn "indirect_jump"
4054 [(set (pc) (match_operand:SI 0 "general_operand" "r"))]
4055 "(GET_CODE (operands[0]) != MEM )"
4058 check_label_emit ();
4059 mvs_check_page (0, 2, 0);
4064 ; tablejump instruction pattern(s).
4067 (define_insn "tablejump"
4069 (match_operand:SI 0 "general_operand" "am"))
4070 (use (label_ref (match_operand 1 "" "")))]
4074 check_label_emit ();
4075 if (REG_P (operands[0]))
4077 mvs_check_page (0, 6, 0);
4078 return \"BR %0\;DS 0F\";
4080 mvs_check_page (0, 10, 0);
4081 return \"L 14,%0\;BR 14\;DS 0F\";
4085 ;;- Jump to subroutine.
4087 ;; For the C/370 environment the internal functions, ie. sqrt, are called with
4088 ;; a non-standard form. So, we must fix it here. There's no BM like IBM.
4092 ; call instruction pattern(s).
4096 [(call (match_operand:QI 0 "memory_operand" "m")
4097 (match_operand:SI 1 "immediate_operand" "i"))]
4101 static char temp[128];
4102 int i = STACK_POINTER_OFFSET;
4104 check_label_emit ();
4105 if (mvs_function_check (XSTR (operands[0], 0)))
4107 mvs_check_page (0, 22, 4);
4108 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\",
4113 mvs_check_page (0, 10, 4);
4114 sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i );
4120 ; call_value instruction pattern(s).
4123 (define_insn "call_value"
4124 [(set (match_operand 0 "" "rf")
4125 (call (match_operand:QI 1 "memory_operand" "m")
4126 (match_operand:SI 2 "general_operand" "i")))]
4130 static char temp[128];
4131 int i = STACK_POINTER_OFFSET;
4133 check_label_emit ();
4134 if (mvs_function_check (XSTR (operands[1], 0)))
4136 mvs_check_page (0, 22, 4);
4137 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\",
4142 mvs_check_page (0, 10, 4);
4143 sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i );
4149 [(call (mem:QI (match_operand:SI 0 "" "i"))
4150 (match_operand:SI 1 "general_operand" "g"))]
4151 "GET_CODE (operands[0]) == SYMBOL_REF"
4154 static char temp[128];
4155 int i = STACK_POINTER_OFFSET;
4157 check_label_emit ();
4158 if (mvs_function_check (XSTR (operands[0], 0)))
4160 mvs_check_page (0, 22, 4);
4161 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\;LD 0,136(,13)\",
4166 mvs_check_page (0, 10, 4);
4167 sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%0\;BALR 14,15\", i );
4173 [(set (match_operand 0 "" "rf")
4174 (call (mem:QI (match_operand:SI 1 "" "i"))
4175 (match_operand:SI 2 "general_operand" "g")))]
4176 "GET_CODE (operands[1]) == SYMBOL_REF"
4179 static char temp[128];
4180 int i = STACK_POINTER_OFFSET;
4182 check_label_emit ();
4183 if (mvs_function_check (XSTR (operands[1], 0)))
4185 mvs_check_page (0, 22, 4);
4186 sprintf ( temp, \"LA 1,136(,13)\;ST 1,%d(,13)\;LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\;LD 0,136(,13)\",
4191 mvs_check_page (0, 10, 4);
4192 sprintf ( temp, \"LA 1,%d(,13)\;L 15,%%1\;BALR 14,15\", i );
4199 ;;- Miscellaneous instructions.
4203 ; nop instruction pattern(s).
4211 check_label_emit ();
4212 mvs_check_page (0, 2, 0);