1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have an insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
64 ;; ----------------------------------------------------------------------
66 ;; ----------------------------------------------------------------------
68 (define_attr "cpu" "h8300,h8300h"
69 (const (symbol_ref "cpu_type")))
71 (define_attr "type" "branch,arith"
72 (const_string "arith"))
74 ;; The size of instructions in bytes.
76 (define_attr "length" ""
77 (cond [(eq_attr "type" "branch")
78 (if_then_else (and (ge (minus (match_dup 0) (pc))
80 (le (minus (match_dup 0) (pc))
83 (if_then_else (and (eq_attr "cpu" "h8300h")
84 (and (ge (minus (pc) (match_dup 0))
86 (le (minus (pc) (match_dup 0))
92 ;; The necessity of instruction length adjustment.
94 (define_attr "adjust_length" "yes,no"
95 (cond [(eq_attr "type" "branch") (const_string "no")]
96 (const_string "yes")))
98 ;; Condition code settings.
100 ;; none - insn does not affect cc
101 ;; none_0hit - insn does not affect cc but it does modify operand 0
102 ;; This attribute is used to keep track of when operand 0 changes.
103 ;; See the description of NOTICE_UPDATE_CC for more info.
104 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
105 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
106 ;; compare - compare instruction
107 ;; clobber - value of cc is unknown
109 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
110 (const_string "clobber"))
112 ;; ----------------------------------------------------------------------
114 ;; ----------------------------------------------------------------------
118 (define_insn "pushqi1_h8300"
119 [(parallel [(set (reg:HI SP_REG)
120 (plus:HI (reg:HI SP_REG) (const_int -2)))
121 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
122 (match_operand:QI 0 "register_operand" "r"))])]
124 && REGNO (operands[0]) != SP_REG"
126 [(set_attr "length" "2")
127 (set_attr "cc" "clobber")])
129 (define_insn "pushqi1_h8300hs"
130 [(parallel [(set (reg:SI SP_REG)
131 (plus:SI (reg:SI SP_REG) (const_int -4)))
132 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
133 (match_operand:QI 0 "register_operand" "r"))])]
134 "(TARGET_H8300H || TARGET_H8300S)
135 && REGNO (operands[0]) != SP_REG"
137 [(set_attr "length" "4")
138 (set_attr "cc" "clobber")])
140 (define_expand "pushqi1"
141 [(use (match_operand:QI 0 "register_operand" ""))]
146 emit_insn (gen_pushqi1_h8300 (operands[0]));
148 emit_insn (gen_pushqi1_h8300hs (operands[0]));
153 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
154 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
156 && (register_operand (operands[0], QImode)
157 || register_operand (operands[1], QImode))"
165 [(set_attr "length" "2,2,2,2,4,4")
166 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
169 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
170 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
171 "(TARGET_H8300H || TARGET_H8300S)
172 && (register_operand (operands[0], QImode)
173 || register_operand (operands[1], QImode))"
181 [(set_attr "length" "2,2,2,2,8,8")
182 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
184 (define_expand "movqi"
185 [(set (match_operand:QI 0 "general_operand_dst" "")
186 (match_operand:QI 1 "general_operand_src" ""))]
190 /* One of the ops has to be in a register. */
191 if (!register_operand (operand0, QImode)
192 && !register_operand (operand1, QImode))
194 operands[1] = copy_to_mode_reg (QImode, operand1);
198 (define_insn "movstrictqi"
199 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
200 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
207 [(set_attr_alternative "length"
208 [(const_int 2) (const_int 2) (const_int 2)
209 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
210 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
214 (define_expand "pushhi1_h8300"
215 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
216 (match_operand:HI 0 "register_operand" ""))]
218 && REGNO (operands[0]) != SP_REG"
221 (define_insn "pushhi1_h8300hs"
222 [(parallel [(set (reg:SI SP_REG)
223 (plus:SI (reg:SI SP_REG) (const_int -4)))
224 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
225 (match_operand:HI 0 "register_operand" "r"))])]
226 "(TARGET_H8300H || TARGET_H8300S)
227 && REGNO (operands[0]) != SP_REG"
229 [(set_attr "length" "4")
230 (set_attr "cc" "clobber")])
232 (define_expand "pushhi1"
233 [(use (match_operand:HI 0 "register_operand" ""))]
238 emit_insn (gen_pushhi1_h8300 (operands[0]));
240 emit_insn (gen_pushhi1_h8300hs (operands[0]));
245 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
246 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
248 && (register_operand (operands[0], HImode)
249 || register_operand (operands[1], HImode))
250 && !(GET_CODE (operands[0]) == MEM
251 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
252 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
253 && GET_CODE (operands[1]) == REG
254 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
262 [(set_attr "length" "2,2,2,4,4,4")
263 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
266 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
267 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
268 "(TARGET_H8300H || TARGET_H8300S)
269 && (register_operand (operands[0], HImode)
270 || register_operand (operands[1], HImode))"
278 [(set_attr "length" "2,2,2,4,8,8")
279 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
281 (define_expand "movhi"
282 [(set (match_operand:HI 0 "general_operand_dst" "")
283 (match_operand:HI 1 "general_operand_src" ""))]
287 /* One of the ops has to be in a register. */
288 if (!register_operand (operand1, HImode)
289 && !register_operand (operand0, HImode))
291 operands[1] = copy_to_mode_reg (HImode, operand1);
295 (define_insn "movstricthi"
296 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
297 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
304 [(set_attr_alternative "length"
305 [(const_int 2) (const_int 2) (const_int 4)
306 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
307 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
311 (define_expand "movsi"
312 [(set (match_operand:SI 0 "general_operand_dst" "")
313 (match_operand:SI 1 "general_operand_src" ""))]
319 if (do_movsi (operands))
324 /* One of the ops has to be in a register. */
325 if (!register_operand (operand1, SImode)
326 && !register_operand (operand0, SImode))
328 operands[1] = copy_to_mode_reg (SImode, operand1);
333 (define_expand "movsf"
334 [(set (match_operand:SF 0 "general_operand_dst" "")
335 (match_operand:SF 1 "general_operand_src" ""))]
341 if (do_movsi (operands))
346 /* One of the ops has to be in a register. */
347 if (!register_operand (operand1, SFmode)
348 && !register_operand (operand0, SFmode))
350 operands[1] = copy_to_mode_reg (SFmode, operand1);
355 (define_insn "movsi_h8300"
356 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
357 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
359 && (register_operand (operands[0], SImode)
360 || register_operand (operands[1], SImode))"
363 unsigned int rn = -1;
364 switch (which_alternative)
367 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
369 if (REGNO (operands[0]) < REGNO (operands[1]))
370 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
372 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
374 /* Make sure we don't trample the register we index with. */
375 if (GET_CODE (operands[1]) == MEM)
377 rtx inside = XEXP (operands[1], 0);
382 else if (GET_CODE (inside) == PLUS)
384 rtx lhs = XEXP (inside, 0);
385 rtx rhs = XEXP (inside, 1);
386 if (REG_P (lhs)) rn = REGNO (lhs);
387 if (REG_P (rhs)) rn = REGNO (rhs);
390 if (rn == REGNO (operands[0]))
392 /* Move the second word first. */
393 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
397 /* See if either half is zero. If so, use sub.w to clear
399 if (GET_CODE (operands[1]) == CONST_INT)
401 if ((INTVAL (operands[1]) & 0xffff) == 0)
402 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
403 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
404 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
406 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
409 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
411 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
413 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
418 [(set_attr "length" "4,4,8,8,4,4")
419 (set_attr "cc" "clobber")])
421 (define_insn "movsf_h8300"
422 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
423 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
425 && (register_operand (operands[0], SFmode)
426 || register_operand (operands[1], SFmode))"
429 /* Copy of the movsi stuff. */
430 unsigned int rn = -1;
431 switch (which_alternative)
434 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
436 if (REGNO (operands[0]) < REGNO (operands[1]))
437 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
439 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
441 /* Make sure we don't trample the register we index with. */
442 if (GET_CODE (operands[1]) == MEM)
444 rtx inside = XEXP (operands[1], 0);
449 else if (GET_CODE (inside) == PLUS)
451 rtx lhs = XEXP (inside, 0);
452 rtx rhs = XEXP (inside, 1);
453 if (REG_P (lhs)) rn = REGNO (lhs);
454 if (REG_P (rhs)) rn = REGNO (rhs);
457 if (rn == REGNO (operands[0]))
458 /* Move the second word first. */
459 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
461 /* Move the first word first. */
462 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
465 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
467 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
469 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
474 [(set_attr "length" "4,4,8,8,4,4")
475 (set_attr "cc" "clobber")])
477 (define_insn "movsi_h8300hs"
478 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
479 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
480 "(TARGET_H8300S || TARGET_H8300H)
481 && (register_operand (operands[0], SImode)
482 || register_operand (operands[1], SImode))
483 && !(GET_CODE (operands[0]) == MEM
484 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
485 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
486 && GET_CODE (operands[1]) == REG
487 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
490 switch (which_alternative)
493 return \"sub.l %S0,%S0\";
497 return \"clrmac\;ldmac %1,macl\";
499 return \"stmac macl,%0\";
501 if (GET_CODE (operands[1]) == CONST_INT)
503 int val = INTVAL (operands[1]);
505 /* Look for constants which can be made by adding an 8-bit
506 number to zero in one of the two low bytes. */
507 if (val == (val & 0xff))
509 operands[1] = GEN_INT ((char) val & 0xff);
510 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
513 if (val == (val & 0xff00))
515 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
516 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
519 /* Look for constants that can be obtained by subs, inc, and
521 switch (val & 0xffffffff)
524 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
526 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
528 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
531 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
533 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
536 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
538 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
541 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
543 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
547 return \"mov.l %S1,%S0\";
549 [(set_attr "length" "2,2,6,4,4,10,10,2,6,4")
550 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
552 (define_insn "movsf_h8300h"
553 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
554 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
555 "(TARGET_H8300H || TARGET_H8300S)
556 && (register_operand (operands[0], SFmode)
557 || register_operand (operands[1], SFmode))"
565 [(set_attr "length" "2,2,10,10,4,4")
566 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
568 ;; ----------------------------------------------------------------------
570 ;; ----------------------------------------------------------------------
573 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
575 (match_operand 1 "const_int_operand" "n,n")))]
578 [(set_attr "length" "2,4")
579 (set_attr "cc" "set_zn,set_zn")])
582 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
584 (match_operand 1 "const_int_operand" "n")))]
587 [(set_attr "length" "2")
588 (set_attr "cc" "set_zn")])
590 (define_insn "*tst_extzv_bitqi_1_n"
591 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_operand" "r,U")
593 (match_operand 1 "const_int_operand" "n,n")))]
594 "(TARGET_H8300H || TARGET_H8300S)
595 && INTVAL (operands[1]) != 7"
597 [(set_attr "length" "2,8")
598 (set_attr "cc" "set_zn,set_zn")])
600 (define_insn_and_split "*tst_extzv_memqi_1_n"
601 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
603 (match_operand 1 "const_int_operand" "n")))
604 (clobber (match_scratch:QI 2 "=&r"))]
605 "(TARGET_H8300H || TARGET_H8300S)
606 && !EXTRA_CONSTRAINT (operands[0], 'U')
607 && INTVAL (operands[1]) != 7"
609 "&& reload_completed"
612 (set (cc0) (zero_extract:SI (match_dup 2)
618 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
620 (match_operand 1 "const_int_operand" "n")))]
621 "(TARGET_H8300H || TARGET_H8300S)
622 && INTVAL (operands[1]) <= 15"
624 [(set_attr "length" "2")
625 (set_attr "cc" "set_zn")])
629 (and:HI (match_operand:HI 0 "register_operand" "r")
630 (match_operand:HI 1 "single_one_operand" "n")))]
634 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
635 if (INTVAL (operands[1]) > 128)
637 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
638 return \"btst\\t%V1,%t0\";
640 return \"btst\\t%V1,%s0\";
642 [(set_attr "length" "2")
643 (set_attr "cc" "set_zn")])
647 (and:SI (match_operand:SI 0 "register_operand" "r")
648 (match_operand:SI 1 "single_one_operand" "n")))]
649 "(TARGET_H8300H || TARGET_H8300S)
650 && (INTVAL (operands[1]) & 0xffff) != 0"
653 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
654 if (INTVAL (operands[1]) > 128)
656 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
657 return \"btst\\t%V1,%x0\";
659 return \"btst\\t%V1,%w0\";
661 [(set_attr "length" "2")
662 (set_attr "cc" "set_zn")])
665 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
668 [(set_attr "length" "2")
669 (set_attr "cc" "set_znv")])
672 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
675 [(set_attr "length" "2")
676 (set_attr "cc" "set_znv")])
680 (and:HI (match_operand:HI 0 "register_operand" "r")
684 [(set_attr "length" "2")
685 (set_attr "cc" "set_znv")])
688 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
689 "TARGET_H8300H || TARGET_H8300S"
691 [(set_attr "length" "2")
692 (set_attr "cc" "set_znv")])
696 (and:SI (match_operand:SI 0 "register_operand" "r")
697 (const_int -65536)))]
700 [(set_attr "length" "2")
701 (set_attr "cc" "set_znv")])
705 (compare:QI (match_operand:QI 0 "register_operand" "r")
706 (match_operand:QI 1 "nonmemory_operand" "rn")))]
709 [(set_attr "length" "2")
710 (set_attr "cc" "compare")])
712 (define_expand "cmphi"
714 (compare:HI (match_operand:HI 0 "register_operand" "")
715 (match_operand:HI 1 "nonmemory_operand" "")))]
719 /* Force operand1 into a register if we're compiling
721 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
722 operands[1] = force_reg (HImode, operands[1]);
727 (compare:HI (match_operand:HI 0 "register_operand" "r")
728 (match_operand:HI 1 "register_operand" "r")))]
731 [(set_attr "length" "2")
732 (set_attr "cc" "compare")])
736 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
737 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
738 "TARGET_H8300H || TARGET_H8300S"
740 [(set_attr "length" "2,4")
741 (set_attr "cc" "compare,compare")])
745 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
746 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
747 "TARGET_H8300H || TARGET_H8300S"
749 [(set_attr "length" "2,6")
750 (set_attr "cc" "compare,compare")])
752 ;; ----------------------------------------------------------------------
754 ;; ----------------------------------------------------------------------
756 (define_insn "addqi3"
757 [(set (match_operand:QI 0 "register_operand" "=r")
758 (plus:QI (match_operand:QI 1 "register_operand" "%0")
759 (match_operand:QI 2 "nonmemory_operand" "rn")))]
762 [(set_attr "length" "2")
763 (set_attr "cc" "set_zn")])
765 (define_expand "addhi3"
766 [(set (match_operand:HI 0 "register_operand" "")
767 (plus:HI (match_operand:HI 1 "register_operand" "")
768 (match_operand:HI 2 "nonmemory_operand" "")))]
772 (define_insn "*addhi3_h8300"
773 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
774 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
775 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
781 add.b %s2,%s0\;addx %t2,%t0
783 [(set_attr "length" "2,2,2,4,2")
784 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
786 (define_insn "*addhi3_h8300hs"
787 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
788 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
789 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
790 "TARGET_H8300H || TARGET_H8300S"
797 [(set_attr "length" "2,2,2,4,2")
798 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
800 (define_insn "addhi3_incdec"
801 [(set (match_operand:HI 0 "register_operand" "=r,r")
802 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
803 (match_operand:HI 2 "incdec_operand" "M,O")]
805 "TARGET_H8300H || TARGET_H8300S"
809 [(set_attr "length" "2,2")
810 (set_attr "cc" "set_zn,set_zn")])
813 [(set (match_operand:HI 0 "register_operand" "")
814 (plus:HI (match_dup 0)
815 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
818 "split_adds_subs (HImode, operands, 0); DONE;")
820 (define_expand "addsi3"
821 [(set (match_operand:SI 0 "register_operand" "")
822 (plus:SI (match_operand:SI 1 "register_operand" "")
823 (match_operand:SI 2 "nonmemory_operand" "")))]
827 (define_insn "addsi_h8300"
828 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
829 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
830 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
833 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
834 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
835 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
836 [(set_attr "length" "8,6,10")
837 (set_attr "cc" "clobber")])
839 (define_insn "addsi_h8300h"
840 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
841 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
842 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
843 "TARGET_H8300H || TARGET_H8300S"
849 [(set_attr "length" "2,2,6,2")
850 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
852 (define_insn "addsi3_incdec"
853 [(set (match_operand:SI 0 "register_operand" "=r,r")
854 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
855 (match_operand:SI 2 "incdec_operand" "M,O")]
857 "TARGET_H8300H || TARGET_H8300S"
861 [(set_attr "length" "2,2")
862 (set_attr "cc" "set_zn,set_zn")])
865 [(set (match_operand:SI 0 "register_operand" "")
866 (plus:SI (match_dup 0)
867 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
868 "TARGET_H8300H || TARGET_H8300S"
870 "split_adds_subs (SImode, operands, 0); DONE;")
872 ;; ----------------------------------------------------------------------
873 ;; SUBTRACT INSTRUCTIONS
874 ;; ----------------------------------------------------------------------
876 (define_insn "subqi3"
877 [(set (match_operand:QI 0 "register_operand" "=r")
878 (minus:QI (match_operand:QI 1 "register_operand" "0")
879 (match_operand:QI 2 "register_operand" "r")))]
882 [(set_attr "length" "2")
883 (set_attr "cc" "set_zn")])
885 (define_expand "subhi3"
886 [(set (match_operand:HI 0 "register_operand" "")
887 (minus:HI (match_operand:HI 1 "general_operand" "")
888 (match_operand:HI 2 "nonmemory_operand" "")))]
893 [(set (match_operand:HI 0 "register_operand" "=r,&r")
894 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
895 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
899 add.b %E2,%s0\;addx %F2,%t0"
900 [(set_attr "length" "2,4")
901 (set_attr "cc" "set_zn,clobber")])
904 [(set (match_operand:HI 0 "register_operand" "=r,&r")
905 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
906 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
907 "TARGET_H8300H || TARGET_H8300S"
911 [(set_attr "length" "2,4")
912 (set_attr "cc" "set_zn,set_zn")])
914 (define_expand "subsi3"
915 [(set (match_operand:SI 0 "register_operand" "")
916 (minus:SI (match_operand:SI 1 "register_operand" "")
917 (match_operand:SI 2 "nonmemory_operand" "")))]
921 (define_insn "subsi3_h8300"
922 [(set (match_operand:SI 0 "register_operand" "=r")
923 (minus:SI (match_operand:SI 1 "register_operand" "0")
924 (match_operand:SI 2 "register_operand" "r")))]
926 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
927 [(set_attr "length" "6")
928 (set_attr "cc" "clobber")])
930 (define_insn "subsi3_h8300h"
931 [(set (match_operand:SI 0 "register_operand" "=r,r")
932 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
933 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
934 "TARGET_H8300H || TARGET_H8300S"
938 [(set_attr "length" "2,6")
939 (set_attr "cc" "set_zn,set_zn")])
941 ;; ----------------------------------------------------------------------
942 ;; MULTIPLY INSTRUCTIONS
943 ;; ----------------------------------------------------------------------
945 ;; Note that the H8/300 can only handle umulqihi3.
947 (define_insn "mulqihi3"
948 [(set (match_operand:HI 0 "register_operand" "=r")
949 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
950 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
951 "TARGET_H8300H || TARGET_H8300S"
953 [(set_attr "length" "4")
954 (set_attr "cc" "set_zn")])
956 (define_insn "mulhisi3"
957 [(set (match_operand:SI 0 "register_operand" "=r")
958 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
959 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
960 "TARGET_H8300H || TARGET_H8300S"
962 [(set_attr "length" "4")
963 (set_attr "cc" "set_zn")])
965 (define_insn "umulqihi3"
966 [(set (match_operand:HI 0 "register_operand" "=r")
967 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
968 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
971 [(set_attr "length" "2")
972 (set_attr "cc" "none_0hit")])
974 (define_insn "umulhisi3"
975 [(set (match_operand:SI 0 "register_operand" "=r")
976 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
977 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
978 "TARGET_H8300H || TARGET_H8300S"
980 [(set_attr "length" "2")
981 (set_attr "cc" "none_0hit")])
983 ;; This is a "bridge" instruction. Combine can't cram enough insns
984 ;; together to crate a MAC instruction directly, but it can create
985 ;; this instruction, which then allows combine to create the real
988 ;; Unfortunately, if combine doesn't create a MAC instruction, this
989 ;; insn must generate reasonably correct code. Egad.
991 [(set (match_operand:SI 0 "register_operand" "=a")
994 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
996 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
998 "clrmac\;mac @%2+,@%1+"
999 [(set_attr "length" "6")
1000 (set_attr "cc" "none_0hit")])
1003 [(set (match_operand:SI 0 "register_operand" "=a")
1005 (sign_extend:SI (mem:HI
1006 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1007 (sign_extend:SI (mem:HI
1008 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1009 (match_operand:SI 3 "register_operand" "0")))]
1012 [(set_attr "length" "4")
1013 (set_attr "cc" "none_0hit")])
1015 ;; ----------------------------------------------------------------------
1016 ;; DIVIDE/MOD INSTRUCTIONS
1017 ;; ----------------------------------------------------------------------
1019 (define_insn "udivmodqi4"
1020 [(set (match_operand:QI 0 "register_operand" "=r")
1023 (match_operand:HI 1 "register_operand" "0")
1024 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1025 (set (match_operand:QI 3 "register_operand" "=r")
1029 (zero_extend:HI (match_dup 2)))))]
1033 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1034 return \"divxu.b\\t%X2,%T0\";
1036 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1038 [(set_attr "length" "4")
1039 (set_attr "cc" "clobber")])
1041 (define_insn "divmodqi4"
1042 [(set (match_operand:QI 0 "register_operand" "=r")
1045 (match_operand:HI 1 "register_operand" "0")
1046 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1047 (set (match_operand:QI 3 "register_operand" "=r")
1051 (sign_extend:HI (match_dup 2)))))]
1052 "TARGET_H8300H || TARGET_H8300S"
1055 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1056 return \"divxs.b\\t%X2,%T0\";
1058 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1060 [(set_attr "length" "6")
1061 (set_attr "cc" "clobber")])
1063 (define_insn "udivmodhi4"
1064 [(set (match_operand:HI 0 "register_operand" "=r")
1067 (match_operand:SI 1 "register_operand" "0")
1068 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1069 (set (match_operand:HI 3 "register_operand" "=r")
1073 (zero_extend:SI (match_dup 2)))))]
1074 "TARGET_H8300H || TARGET_H8300S"
1077 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1078 return \"divxu.w\\t%T2,%S0\";
1080 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1082 [(set_attr "length" "4")
1083 (set_attr "cc" "clobber")])
1085 (define_insn "divmodhi4"
1086 [(set (match_operand:HI 0 "register_operand" "=r")
1089 (match_operand:SI 1 "register_operand" "0")
1090 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1091 (set (match_operand:HI 3 "register_operand" "=r")
1095 (sign_extend:SI (match_dup 2)))))]
1096 "TARGET_H8300H || TARGET_H8300S"
1099 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1100 return \"divxs.w\\t%T2,%S0\";
1102 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1104 [(set_attr "length" "6")
1105 (set_attr "cc" "clobber")])
1107 ;; ----------------------------------------------------------------------
1109 ;; ----------------------------------------------------------------------
1112 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1113 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1114 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1115 "register_operand (operands[0], QImode)
1116 || single_zero_operand (operands[2], QImode)"
1120 [(set_attr "length" "2,8")
1121 (set_attr "adjust_length" "no")
1122 (set_attr "cc" "set_znv,none_0hit")])
1124 (define_expand "andqi3"
1125 [(set (match_operand:QI 0 "bit_operand" "")
1126 (and:QI (match_operand:QI 1 "bit_operand" "")
1127 (match_operand:QI 2 "nonmemory_operand" "")))]
1131 if (fix_bit_operand (operands, 0, AND))
1135 (define_expand "andhi3"
1136 [(set (match_operand:HI 0 "register_operand" "")
1137 (and:HI (match_operand:HI 1 "register_operand" "")
1138 (match_operand:HI 2 "nonmemory_operand" "")))]
1142 (define_insn "*andorqi3"
1143 [(set (match_operand:QI 0 "register_operand" "=r")
1144 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1145 (match_operand:QI 3 "single_one_operand" "n"))
1146 (match_operand:QI 1 "register_operand" "0")))]
1148 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1149 [(set_attr "length" "6")
1150 (set_attr "cc" "clobber")])
1152 (define_insn "*andorhi3"
1153 [(set (match_operand:HI 0 "register_operand" "=r")
1154 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1155 (match_operand:HI 3 "single_one_operand" "n"))
1156 (match_operand:HI 1 "register_operand" "0")))]
1160 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1161 if (INTVAL (operands[3]) > 128)
1163 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1164 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1166 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1168 [(set_attr "length" "6")
1169 (set_attr "cc" "clobber")])
1171 (define_insn "*andorsi3"
1172 [(set (match_operand:SI 0 "register_operand" "=r")
1173 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1174 (match_operand:SI 3 "single_one_operand" "n"))
1175 (match_operand:SI 1 "register_operand" "0")))]
1176 "(INTVAL (operands[3]) & 0xffff) != 0"
1179 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1180 if (INTVAL (operands[3]) > 128)
1182 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1183 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1185 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1187 [(set_attr "length" "6")
1188 (set_attr "cc" "clobber")])
1190 (define_insn "*andorsi3_shift_8"
1191 [(set (match_operand:SI 0 "register_operand" "=r")
1192 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1195 (match_operand:SI 1 "register_operand" "0")))]
1198 [(set_attr "length" "2")
1199 (set_attr "cc" "clobber")])
1201 (define_expand "andsi3"
1202 [(set (match_operand:SI 0 "register_operand" "")
1203 (and:SI (match_operand:SI 1 "register_operand" "")
1204 (match_operand:SI 2 "nonmemory_operand" "")))]
1208 ;; ----------------------------------------------------------------------
1210 ;; ----------------------------------------------------------------------
1213 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1214 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1215 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1216 "register_operand (operands[0], QImode)
1217 || single_one_operand (operands[2], QImode)"
1221 [(set_attr "length" "2,8")
1222 (set_attr "adjust_length" "no")
1223 (set_attr "cc" "set_znv,none_0hit")])
1225 (define_expand "iorqi3"
1226 [(set (match_operand:QI 0 "bit_operand" "")
1227 (ior:QI (match_operand:QI 1 "bit_operand" "")
1228 (match_operand:QI 2 "nonmemory_operand" "")))]
1232 if (fix_bit_operand (operands, 1, IOR))
1236 (define_expand "iorhi3"
1237 [(set (match_operand:HI 0 "register_operand" "")
1238 (ior:HI (match_operand:HI 1 "register_operand" "")
1239 (match_operand:HI 2 "nonmemory_operand" "")))]
1243 (define_expand "iorsi3"
1244 [(set (match_operand:SI 0 "register_operand" "")
1245 (ior:SI (match_operand:SI 1 "register_operand" "")
1246 (match_operand:SI 2 "nonmemory_operand" "")))]
1250 ;; ----------------------------------------------------------------------
1252 ;; ----------------------------------------------------------------------
1255 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1256 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1257 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1258 "register_operand (operands[0], QImode)
1259 || single_one_operand (operands[2], QImode)"
1263 [(set_attr "length" "2,8")
1264 (set_attr "adjust_length" "no")
1265 (set_attr "cc" "set_znv,none_0hit")])
1267 (define_expand "xorqi3"
1268 [(set (match_operand:QI 0 "bit_operand" "")
1269 (xor:QI (match_operand:QI 1 "bit_operand" "")
1270 (match_operand:QI 2 "nonmemory_operand" "")))]
1274 if (fix_bit_operand (operands, 1, XOR))
1278 (define_expand "xorhi3"
1279 [(set (match_operand:HI 0 "register_operand" "")
1280 (xor:HI (match_operand:HI 1 "register_operand" "")
1281 (match_operand:HI 2 "nonmemory_operand" "")))]
1285 (define_expand "xorsi3"
1286 [(set (match_operand:SI 0 "register_operand" "")
1287 (xor:SI (match_operand:SI 1 "register_operand" "")
1288 (match_operand:SI 2 "nonmemory_operand" "")))]
1292 ;; ----------------------------------------------------------------------
1293 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1294 ;; ----------------------------------------------------------------------
1297 [(set (match_operand:HI 0 "register_operand" "=r")
1298 (match_operator:HI 3 "bit_operator"
1299 [(match_operand:HI 1 "register_operand" "%0")
1300 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1302 "* return output_logical_op (HImode, operands);"
1303 [(set (attr "length")
1304 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1306 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1309 [(set (match_operand:SI 0 "register_operand" "=r")
1310 (match_operator:SI 3 "bit_operator"
1311 [(match_operand:SI 1 "register_operand" "%0")
1312 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1314 "* return output_logical_op (SImode, operands);"
1315 [(set (attr "length")
1316 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1318 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1320 ;; ----------------------------------------------------------------------
1321 ;; NEGATION INSTRUCTIONS
1322 ;; ----------------------------------------------------------------------
1324 (define_insn "negqi2"
1325 [(set (match_operand:QI 0 "register_operand" "=r")
1326 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1329 [(set_attr "length" "2")
1330 (set_attr "cc" "set_zn")])
1332 (define_expand "neghi2"
1333 [(set (match_operand:HI 0 "register_operand" "")
1334 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1340 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1345 (define_expand "neghi2_h8300"
1347 (not:HI (match_operand:HI 1 "register_operand" "")))
1348 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1349 (set (match_operand:HI 0 "register_operand" "")
1352 "operands[2] = gen_reg_rtx (HImode);")
1354 (define_insn "neghi2_h8300h"
1355 [(set (match_operand:HI 0 "register_operand" "=r")
1356 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1357 "TARGET_H8300H || TARGET_H8300S"
1359 [(set_attr "length" "2")
1360 (set_attr "cc" "set_zn")])
1362 (define_expand "negsi2"
1363 [(set (match_operand:SI 0 "register_operand" "")
1364 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1370 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1375 (define_expand "negsi2_h8300"
1377 (not:SI (match_operand:SI 1 "register_operand" "")))
1378 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1379 (set (match_operand:SI 0 "register_operand" "")
1382 "operands[2] = gen_reg_rtx (SImode);")
1384 (define_insn "negsi2_h8300h"
1385 [(set (match_operand:SI 0 "register_operand" "=r")
1386 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1387 "TARGET_H8300H || TARGET_H8300S"
1389 [(set_attr "length" "2")
1390 (set_attr "cc" "set_zn")])
1392 (define_expand "negsf2"
1393 [(set (match_operand:SF 0 "register_operand" "")
1394 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1398 (define_insn "*negsf2_h8300"
1399 [(set (match_operand:SF 0 "register_operand" "=r")
1400 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1403 [(set_attr "cc" "clobber")
1404 (set_attr "length" "2")])
1406 (define_insn "*negsf2_h8300hs"
1407 [(set (match_operand:SF 0 "register_operand" "=r")
1408 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1409 "TARGET_H8300H || TARGET_H8300S"
1411 [(set_attr "cc" "clobber")
1412 (set_attr "length" "4")])
1414 ;; ----------------------------------------------------------------------
1416 ;; ----------------------------------------------------------------------
1418 (define_insn "one_cmplqi2"
1419 [(set (match_operand:QI 0 "register_operand" "=r")
1420 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1423 [(set_attr "length" "2")
1424 (set_attr "cc" "set_znv")])
1426 (define_expand "one_cmplhi2"
1427 [(set (match_operand:HI 0 "register_operand" "=r")
1428 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1433 [(set (match_operand:HI 0 "register_operand" "=r")
1434 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1437 [(set_attr "cc" "clobber")
1438 (set_attr "length" "4")])
1441 [(set (match_operand:HI 0 "register_operand" "=r")
1442 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1443 "TARGET_H8300H || TARGET_H8300S"
1445 [(set_attr "cc" "set_znv")
1446 (set_attr "length" "2")])
1448 (define_expand "one_cmplsi2"
1449 [(set (match_operand:SI 0 "register_operand" "=r")
1450 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1455 [(set (match_operand:SI 0 "register_operand" "=r")
1456 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1458 "not %w0\;not %x0\;not %y0\;not %z0"
1459 [(set_attr "cc" "clobber")
1460 (set_attr "length" "8")])
1463 [(set (match_operand:SI 0 "register_operand" "=r")
1464 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1465 "TARGET_H8300H || TARGET_H8300S"
1467 [(set_attr "cc" "set_znv")
1468 (set_attr "length" "2")])
1470 ;; ----------------------------------------------------------------------
1471 ;; JUMP INSTRUCTIONS
1472 ;; ----------------------------------------------------------------------
1474 ;; Conditional jump instructions
1476 (define_expand "ble"
1478 (if_then_else (le (cc0)
1480 (label_ref (match_operand 0 "" ""))
1485 (define_expand "bleu"
1487 (if_then_else (leu (cc0)
1489 (label_ref (match_operand 0 "" ""))
1494 (define_expand "bge"
1496 (if_then_else (ge (cc0)
1498 (label_ref (match_operand 0 "" ""))
1503 (define_expand "bgeu"
1505 (if_then_else (geu (cc0)
1507 (label_ref (match_operand 0 "" ""))
1512 (define_expand "blt"
1514 (if_then_else (lt (cc0)
1516 (label_ref (match_operand 0 "" ""))
1521 (define_expand "bltu"
1523 (if_then_else (ltu (cc0)
1525 (label_ref (match_operand 0 "" ""))
1530 (define_expand "bgt"
1532 (if_then_else (gt (cc0)
1534 (label_ref (match_operand 0 "" ""))
1539 (define_expand "bgtu"
1541 (if_then_else (gtu (cc0)
1543 (label_ref (match_operand 0 "" ""))
1548 (define_expand "beq"
1550 (if_then_else (eq (cc0)
1552 (label_ref (match_operand 0 "" ""))
1557 (define_expand "bne"
1559 (if_then_else (ne (cc0)
1561 (label_ref (match_operand 0 "" ""))
1566 (define_insn "branch_true"
1568 (if_then_else (match_operator 1 "comparison_operator"
1569 [(cc0) (const_int 0)])
1570 (label_ref (match_operand 0 "" ""))
1575 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1576 && (GET_CODE (operands[1]) == GT
1577 || GET_CODE (operands[1]) == GE
1578 || GET_CODE (operands[1]) == LE
1579 || GET_CODE (operands[1]) == LT))
1581 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1585 if (get_attr_length (insn) == 2)
1586 return \"b%j1 %l0\";
1587 else if (get_attr_length (insn) == 4)
1588 return \"b%j1 %l0:16\";
1590 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1592 [(set_attr "type" "branch")
1593 (set_attr "cc" "none")])
1595 (define_insn "branch_false"
1597 (if_then_else (match_operator 1 "comparison_operator"
1598 [(cc0) (const_int 0)])
1600 (label_ref (match_operand 0 "" ""))))]
1604 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1605 && (GET_CODE (operands[1]) == GT
1606 || GET_CODE (operands[1]) == GE
1607 || GET_CODE (operands[1]) == LE
1608 || GET_CODE (operands[1]) == LT))
1610 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1614 if (get_attr_length (insn) == 2)
1615 return \"b%k1 %l0\";
1616 else if (get_attr_length (insn) == 4)
1617 return \"b%k1 %l0:16\";
1619 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1621 [(set_attr "type" "branch")
1622 (set_attr "cc" "none")])
1624 ;; Unconditional and other jump instructions.
1628 (label_ref (match_operand 0 "" "")))]
1632 if (get_attr_length (insn) == 2)
1634 else if (get_attr_length (insn) == 4)
1635 return \"bra %l0:16\";
1637 return \"jmp @%l0\";
1639 [(set_attr "type" "branch")
1640 (set_attr "cc" "none")])
1642 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1644 (define_expand "tablejump"
1645 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1646 (use (label_ref (match_operand 1 "" "")))])]
1650 (define_insn "tablejump_h8300"
1651 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1652 (use (label_ref (match_operand 1 "" "")))]
1655 [(set_attr "cc" "none")
1656 (set_attr "length" "2")])
1658 (define_insn "tablejump_h8300h"
1659 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1660 (use (label_ref (match_operand 1 "" "")))]
1661 "TARGET_H8300H || TARGET_H8300S"
1663 [(set_attr "cc" "none")
1664 (set_attr "length" "2")])
1666 (define_insn "tablejump_normal_mode"
1667 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1668 (use (label_ref (match_operand 1 "" "")))]
1669 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1671 [(set_attr "cc" "none")
1672 (set_attr "length" "2")])
1674 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1676 (define_expand "indirect_jump"
1677 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1681 (define_insn "indirect_jump_h8300"
1682 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1685 [(set_attr "cc" "none")
1686 (set_attr "length" "2")])
1688 (define_insn "indirect_jump_h8300h"
1689 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1690 "TARGET_H8300H || TARGET_H8300S"
1692 [(set_attr "cc" "none")
1693 (set_attr "length" "2")])
1695 (define_insn "indirect_jump_normal_mode"
1696 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1697 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1699 [(set_attr "cc" "none")
1700 (set_attr "length" "2")])
1702 ;; Call subroutine with no return value.
1704 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1707 [(call (match_operand:QI 0 "call_insn_operand" "or")
1708 (match_operand:HI 1 "general_operand" "g"))]
1712 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1713 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1714 return \"jsr\\t@%0:8\";
1716 return \"jsr\\t%0\";
1718 [(set_attr "cc" "clobber")
1719 (set (attr "length")
1720 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1724 ;; Call subroutine, returning value in operand 0
1725 ;; (which must be a hard register).
1727 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1729 (define_insn "call_value"
1730 [(set (match_operand 0 "" "=r")
1731 (call (match_operand:QI 1 "call_insn_operand" "or")
1732 (match_operand:HI 2 "general_operand" "g")))]
1736 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1737 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1738 return \"jsr\\t@%1:8\";
1740 return \"jsr\\t%1\";
1742 [(set_attr "cc" "clobber")
1743 (set (attr "length")
1744 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1752 [(set_attr "cc" "none")
1753 (set_attr "length" "2")])
1755 ;; ----------------------------------------------------------------------
1756 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1757 ;; ----------------------------------------------------------------------
1759 (define_insn "*stm_h8300s_2"
1761 [(set (reg:SI SP_REG)
1762 (plus:SI (reg:SI SP_REG) (const_int -8)))
1763 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1764 (match_operand:SI 0 "register_operand" ""))
1765 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1766 (match_operand:SI 1 "register_operand" ""))])]
1768 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1769 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1770 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1771 "stm.l\\t%S0-%S1,@-er7"
1772 [(set_attr "cc" "none")
1773 (set_attr "length" "4")])
1775 (define_insn "*stm_h8300s_3"
1777 [(set (reg:SI SP_REG)
1778 (plus:SI (reg:SI SP_REG) (const_int -12)))
1779 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1780 (match_operand:SI 0 "register_operand" ""))
1781 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1782 (match_operand:SI 1 "register_operand" ""))
1783 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1784 (match_operand:SI 2 "register_operand" ""))])]
1786 && ((REGNO (operands[0]) == 0
1787 && REGNO (operands[1]) == 1
1788 && REGNO (operands[2]) == 2)
1789 || (REGNO (operands[0]) == 4
1790 && REGNO (operands[1]) == 5
1791 && REGNO (operands[2]) == 6))"
1792 "stm.l\\t%S0-%S2,@-er7"
1793 [(set_attr "cc" "none")
1794 (set_attr "length" "4")])
1796 (define_insn "*stm_h8300s_4"
1798 [(set (reg:SI SP_REG)
1799 (plus:SI (reg:SI SP_REG) (const_int -16)))
1800 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1801 (match_operand:SI 0 "register_operand" ""))
1802 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1803 (match_operand:SI 1 "register_operand" ""))
1804 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1805 (match_operand:SI 2 "register_operand" ""))
1806 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1807 (match_operand:SI 3 "register_operand" ""))])]
1809 && REGNO (operands[0]) == 0
1810 && REGNO (operands[1]) == 1
1811 && REGNO (operands[2]) == 2
1812 && REGNO (operands[3]) == 3"
1813 "stm.l\\t%S0-%S3,@-er7"
1814 [(set_attr "cc" "none")
1815 (set_attr "length" "4")])
1817 ;; ----------------------------------------------------------------------
1818 ;; EXTEND INSTRUCTIONS
1819 ;; ----------------------------------------------------------------------
1821 (define_expand "zero_extendqihi2"
1822 [(set (match_operand:HI 0 "register_operand" "")
1823 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1827 (define_insn "*zero_extendqihi2_h8300"
1828 [(set (match_operand:HI 0 "register_operand" "=r,r")
1829 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1834 [(set_attr "length" "2,10")
1835 (set_attr "cc" "clobber,clobber")])
1837 (define_insn "*zero_extendqihi2_h8300hs"
1838 [(set (match_operand:HI 0 "register_operand" "=r,r")
1839 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1840 "TARGET_H8300H || TARGET_H8300S"
1844 [(set_attr "length" "2,10")
1845 (set_attr "cc" "set_znv,set_znv")])
1847 ;; Split the zero extension of a general operand (actually a memory
1848 ;; operand) into a load of the operand and the actual zero extension
1849 ;; so that 1) the length will be accurate, and 2) the zero extensions
1850 ;; appearing at the end of basic blocks may be merged.
1853 [(set (match_operand:HI 0 "register_operand" "")
1854 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1859 (zero_extend:HI (match_dup 2)))]
1860 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
1862 ;; The compiler can synthesize a H8/300H variant of this which is
1863 ;; just as efficient as one that we'd create
1864 (define_insn "zero_extendqisi2"
1865 [(set (match_operand:SI 0 "register_operand" "=r,r")
1866 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1869 mov.b #0,%x0\;sub.w %e0,%e0
1870 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1871 [(set_attr "length" "4,8")
1872 (set_attr "cc" "clobber,clobber")])
1874 (define_expand "zero_extendhisi2"
1875 [(set (match_operand:SI 0 "register_operand" "")
1876 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1880 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1882 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1883 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1887 mov.w %f1,%f0\;sub.w %e0,%e0
1888 mov.w %e1,%f0\;sub.w %e0,%e0"
1889 [(set_attr "length" "2,4,4")
1890 (set_attr "cc" "clobber,clobber,clobber")])
1893 [(set (match_operand:SI 0 "register_operand" "=r")
1894 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1895 "TARGET_H8300H || TARGET_H8300S"
1897 [(set_attr "length" "2")
1898 (set_attr "cc" "set_znv")])
1900 (define_expand "extendqihi2"
1901 [(set (match_operand:HI 0 "register_operand" "")
1902 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1907 [(set (match_operand:HI 0 "register_operand" "=r,r")
1908 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1911 bld #7,%s0\;subx %t0,%t0
1912 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1913 [(set_attr "length" "4,8")
1914 (set_attr "cc" "clobber,clobber")])
1917 [(set (match_operand:HI 0 "register_operand" "=r")
1918 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1919 "TARGET_H8300H || TARGET_H8300S"
1921 [(set_attr "length" "2")
1922 (set_attr "cc" "set_znv")])
1924 ;; The compiler can synthesize a H8/300H variant of this which is
1925 ;; just as efficient as one that we'd create
1926 (define_insn "extendqisi2"
1927 [(set (match_operand:SI 0 "register_operand" "=r,r")
1928 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1931 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1932 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1933 [(set_attr "length" "8,10")
1934 (set_attr "cc" "clobber,clobber")])
1936 (define_expand "extendhisi2"
1937 [(set (match_operand:SI 0 "register_operand" "")
1938 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1943 [(set (match_operand:SI 0 "register_operand" "=r,r")
1944 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1947 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1948 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1949 [(set_attr "length" "6,8")
1950 (set_attr "cc" "clobber,clobber")])
1953 [(set (match_operand:SI 0 "register_operand" "=r")
1954 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1955 "TARGET_H8300H || TARGET_H8300S"
1957 [(set_attr "length" "2")
1958 (set_attr "cc" "set_znv")])
1960 ;; ----------------------------------------------------------------------
1962 ;; ----------------------------------------------------------------------
1964 ;; We make some attempt to provide real efficient shifting. One example is
1965 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1966 ;; reg and moving 0 into the former reg.
1968 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1969 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1970 ;; give the optimizer more cracks at the code. However, we wish to do things
1971 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1972 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1973 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1974 ;; to detect cases it can optimize.
1976 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1977 ;; easier "do it at insn emit time" route.
1981 (define_expand "ashlqi3"
1982 [(set (match_operand:QI 0 "register_operand" "")
1983 (ashift:QI (match_operand:QI 1 "register_operand" "")
1984 (match_operand:QI 2 "nonmemory_operand" "")))]
1986 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
1988 (define_expand "ashrqi3"
1989 [(set (match_operand:QI 0 "register_operand" "")
1990 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1991 (match_operand:QI 2 "nonmemory_operand" "")))]
1993 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
1995 (define_expand "lshrqi3"
1996 [(set (match_operand:QI 0 "register_operand" "")
1997 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1998 (match_operand:QI 2 "nonmemory_operand" "")))]
2000 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
2003 [(set (match_operand:QI 0 "register_operand" "=r,r")
2004 (match_operator:QI 3 "nshift_operator"
2005 [ (match_operand:QI 1 "register_operand" "0,0")
2006 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2007 (clobber (match_scratch:QI 4 "=X,&r"))]
2009 "* return output_a_shift (operands);"
2010 [(set (attr "length")
2011 (symbol_ref "compute_a_shift_length (insn, operands)"))
2012 (set_attr "cc" "clobber")])
2016 (define_expand "ashlhi3"
2017 [(set (match_operand:HI 0 "register_operand" "")
2018 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2019 (match_operand:QI 2 "nonmemory_operand" "")))]
2021 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
2023 (define_expand "lshrhi3"
2024 [(set (match_operand:HI 0 "register_operand" "")
2025 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2026 (match_operand:QI 2 "nonmemory_operand" "")))]
2028 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
2030 (define_expand "ashrhi3"
2031 [(set (match_operand:HI 0 "register_operand" "")
2032 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2033 (match_operand:QI 2 "nonmemory_operand" "")))]
2035 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
2038 [(set (match_operand:HI 0 "register_operand" "=r,r")
2039 (match_operator:HI 3 "nshift_operator"
2040 [ (match_operand:HI 1 "register_operand" "0,0")
2041 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2042 (clobber (match_scratch:QI 4 "=X,&r"))]
2044 "* return output_a_shift (operands);"
2045 [(set (attr "length")
2046 (symbol_ref "compute_a_shift_length (insn, operands)"))
2047 (set_attr "cc" "clobber")])
2051 (define_expand "ashlsi3"
2052 [(set (match_operand:SI 0 "register_operand" "")
2053 (ashift:SI (match_operand:SI 1 "general_operand" "")
2054 (match_operand:QI 2 "nonmemory_operand" "")))]
2056 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
2058 (define_expand "lshrsi3"
2059 [(set (match_operand:SI 0 "register_operand" "")
2060 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2061 (match_operand:QI 2 "nonmemory_operand" "")))]
2063 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
2065 (define_expand "ashrsi3"
2066 [(set (match_operand:SI 0 "register_operand" "")
2067 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2068 (match_operand:QI 2 "nonmemory_operand" "")))]
2070 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
2073 [(set (match_operand:SI 0 "register_operand" "=r,r")
2074 (match_operator:SI 3 "nshift_operator"
2075 [ (match_operand:SI 1 "register_operand" "0,0")
2076 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2077 (clobber (match_scratch:QI 4 "=X,&r"))]
2079 "* return output_a_shift (operands);"
2080 [(set (attr "length")
2081 (symbol_ref "compute_a_shift_length (insn, operands)"))
2082 (set_attr "cc" "clobber")])
2084 ;; ----------------------------------------------------------------------
2086 ;; ----------------------------------------------------------------------
2088 (define_expand "rotlqi3"
2089 [(set (match_operand:QI 0 "register_operand" "")
2090 (rotate:QI (match_operand:QI 1 "register_operand" "")
2091 (match_operand:QI 2 "nonmemory_operand" "")))]
2093 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2095 (define_insn "*rotlqi3_1"
2096 [(set (match_operand:QI 0 "register_operand" "=r")
2097 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2098 (match_operand:QI 2 "immediate_operand" "")))]
2100 "* return emit_a_rotate (ROTATE, operands);"
2101 [(set_attr "length" "20")
2102 (set_attr "cc" "clobber")])
2104 (define_expand "rotlhi3"
2105 [(set (match_operand:HI 0 "register_operand" "")
2106 (rotate:HI (match_operand:HI 1 "register_operand" "")
2107 (match_operand:QI 2 "nonmemory_operand" "")))]
2109 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2111 (define_insn "*rotlhi3_1"
2112 [(set (match_operand:HI 0 "register_operand" "=r")
2113 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2114 (match_operand:QI 2 "immediate_operand" "")))]
2116 "* return emit_a_rotate (ROTATE, operands);"
2117 [(set_attr "length" "20")
2118 (set_attr "cc" "clobber")])
2120 (define_expand "rotlsi3"
2121 [(set (match_operand:SI 0 "register_operand" "")
2122 (rotate:SI (match_operand:SI 1 "register_operand" "")
2123 (match_operand:QI 2 "nonmemory_operand" "")))]
2124 "TARGET_H8300H || TARGET_H8300S"
2125 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2127 (define_insn "*rotlsi3_1"
2128 [(set (match_operand:SI 0 "register_operand" "=r")
2129 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2130 (match_operand:QI 2 "immediate_operand" "")))]
2131 "TARGET_H8300H || TARGET_H8300S"
2132 "* return emit_a_rotate (ROTATE, operands);"
2133 [(set_attr "length" "20")
2134 (set_attr "cc" "clobber")])
2136 ;; -----------------------------------------------------------------
2138 ;; -----------------------------------------------------------------
2139 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2140 ;; instructions so let's use them as well as we can.
2142 ;; You'll never believe all these patterns perform one basic action --
2143 ;; load a bit from the source, optionally invert the bit, then store it
2144 ;; in the destination (which is known to be zero).
2146 ;; Combine obviously need some work to better identify this situation and
2147 ;; canonicalize the form better.
2150 ;; Normal loads with a 16bit destination.
2154 [(set (match_operand:HI 0 "register_operand" "=&r")
2155 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2157 (match_operand:HI 2 "immediate_operand" "n")))]
2159 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2160 [(set_attr "cc" "clobber")
2161 (set_attr "length" "6")])
2164 ;; Inverted loads with a 16bit destination.
2168 [(set (match_operand:HI 0 "register_operand" "=&r")
2169 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2170 (match_operand:HI 3 "const_int_operand" "n"))
2172 (match_operand:HI 2 "const_int_operand" "n")))]
2174 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2175 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2176 [(set_attr "cc" "clobber")
2177 (set_attr "length" "8")])
2180 ;; Normal loads with a 32bit destination.
2184 [(set (match_operand:SI 0 "register_operand" "=&r")
2185 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2187 (match_operand 2 "const_int_operand" "n")))]
2189 && INTVAL (operands[2]) < 16"
2190 "* return output_simode_bld (0, operands);"
2191 [(set_attr "cc" "clobber")
2192 (set_attr "length" "6")])
2195 [(set (match_operand:SI 0 "register_operand" "=r")
2196 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2198 (match_operand 2 "const_int_operand" "n")))]
2199 "(TARGET_H8300H || TARGET_H8300S)
2200 && INTVAL (operands[2]) < 16"
2201 "* return output_simode_bld (0, operands);"
2202 [(set_attr "cc" "clobber")
2203 (set_attr "length" "6")])
2206 ;; Inverted loads with a 32bit destination.
2210 [(set (match_operand:SI 0 "register_operand" "=&r")
2211 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2212 (match_operand:HI 3 "const_int_operand" "n"))
2214 (match_operand 2 "const_int_operand" "n")))]
2216 && INTVAL (operands[2]) < 16
2217 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2218 "* return output_simode_bld (1, operands);"
2219 [(set_attr "cc" "clobber")
2220 (set_attr "length" "6")])
2223 [(set (match_operand:SI 0 "register_operand" "=r")
2224 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
2225 (match_operand 3 "const_int_operand" "n"))
2227 (match_operand 2 "const_int_operand" "n")))]
2228 "(TARGET_H8300H || TARGET_H8300S)
2229 && INTVAL (operands[2]) < 16
2230 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2231 "* return output_simode_bld (1, operands);"
2232 [(set_attr "cc" "clobber")
2233 (set_attr "length" "6")])
2235 (define_expand "insv"
2236 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2237 (match_operand:HI 1 "general_operand" "")
2238 (match_operand:HI 2 "general_operand" ""))
2239 (match_operand:HI 3 "general_operand" ""))]
2243 /* We only have single bit bit-field instructions. */
2244 if (INTVAL (operands[1]) != 1)
2247 /* For now, we don't allow memory operands. */
2248 if (GET_CODE (operands[0]) == MEM
2249 || GET_CODE (operands[3]) == MEM)
2254 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2256 (match_operand:HI 1 "immediate_operand" "n"))
2257 (match_operand:HI 2 "register_operand" "r"))]
2259 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2260 [(set_attr "cc" "clobber")
2261 (set_attr "length" "4")])
2263 (define_expand "extzv"
2264 [(set (match_operand:HI 0 "register_operand" "")
2265 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2266 (match_operand:HI 2 "general_operand" "")
2267 (match_operand:HI 3 "general_operand" "")))]
2271 /* We only have single bit bit-field instructions. */
2272 if (INTVAL (operands[2]) != 1)
2275 /* For now, we don't allow memory operands. */
2276 if (GET_CODE (operands[1]) == MEM)
2280 ;; BAND, BOR, and BXOR patterns
2283 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2284 (match_operator:HI 4 "bit_operator"
2285 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2287 (match_operand:HI 2 "immediate_operand" "n"))
2288 (match_operand:HI 3 "bit_operand" "0")]))]
2290 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2291 [(set_attr "cc" "clobber")
2292 (set_attr "length" "6")
2293 (set_attr "adjust_length" "no")])
2296 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2297 (match_operator:HI 5 "bit_operator"
2298 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2300 (match_operand:HI 2 "immediate_operand" "n"))
2301 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2303 (match_operand:HI 4 "immediate_operand" "n"))]))]
2305 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2306 [(set_attr "cc" "clobber")
2307 (set_attr "length" "6")
2308 (set_attr "adjust_length" "no")])
2310 ;; -----------------------------------------------------------------
2312 ;; -----------------------------------------------------------------
2314 (define_insn "*extzv_8_8"
2315 [(set (match_operand:SI 0 "register_operand" "=r")
2316 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2319 "TARGET_H8300H || TARGET_H8300S"
2320 "mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0"
2321 [(set_attr "cc" "set_znv")
2322 (set_attr "length" "6")])
2324 (define_insn "*extzv_8_16"
2325 [(set (match_operand:SI 0 "register_operand" "=r")
2326 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2329 "TARGET_H8300H || TARGET_H8300S"
2330 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2331 [(set_attr "cc" "set_znv")
2332 (set_attr "length" "6")])
2335 [(set (match_operand:HI 0 "register_operand" "=r")
2336 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2337 (match_operand:HI 2 "register_operand" "0")))]
2338 "REG_P (operands[0])
2339 && REG_P (operands[1])
2340 && REGNO (operands[0]) != REGNO (operands[1])"
2342 [(set_attr "cc" "clobber")
2343 (set_attr "length" "2")])
2346 [(set (match_operand:SI 0 "register_operand" "=r")
2347 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2348 (match_operand:SI 2 "register_operand" "0")))]
2349 "(TARGET_H8300H || TARGET_H8300S)
2350 && REG_P (operands[0])
2351 && REG_P (operands[1])
2352 && (REGNO (operands[0]) != REGNO (operands[1]))"
2354 [(set_attr "cc" "clobber")
2355 (set_attr "length" "2")])
2358 [(set (match_operand:SI 0 "register_operand" "=r")
2359 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2360 (match_operand:SI 2 "register_operand" "0")))]
2363 [(set_attr "cc" "clobber")
2364 (set_attr "length" "2")])
2367 [(set (match_operand:HI 0 "register_operand" "=r")
2368 (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2369 (match_operand:HI 2 "register_operand" "0")))]
2370 "REG_P (operands[0])
2371 && REG_P (operands[1])
2372 && REGNO (operands[0]) != REGNO (operands[1])"
2374 [(set_attr "cc" "clobber")
2375 (set_attr "length" "2")])
2378 [(set (match_operand:SI 0 "register_operand" "=r")
2379 (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2380 (match_operand:SI 2 "register_operand" "0")))]
2381 "(TARGET_H8300H || TARGET_H8300S)
2382 && REG_P (operands[0])
2383 && REG_P (operands[1])
2384 && (REGNO (operands[0]) != REGNO (operands[1]))"
2386 [(set_attr "cc" "clobber")
2387 (set_attr "length" "2")])
2390 [(set (match_operand:SI 0 "register_operand" "=r")
2391 (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2392 (match_operand:SI 2 "register_operand" "0")))]
2393 "REG_P (operands[0])
2394 && REG_P (operands[1])
2395 && REGNO (operands[0]) != REGNO (operands[1])"
2397 [(set_attr "cc" "clobber")
2398 (set_attr "length" "2")])
2401 [(set (match_operand:HI 0 "register_operand" "=r")
2402 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2403 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2405 "REG_P (operands[0])
2406 && REG_P (operands[2])
2407 && REGNO (operands[0]) != REGNO (operands[2])"
2409 [(set_attr "cc" "clobber")
2410 (set_attr "length" "2")])
2412 (define_insn "*iorhi_shift_8"
2413 [(set (match_operand:HI 0 "register_operand" "=r")
2414 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
2416 (match_operand:HI 2 "register_operand" "0")))]
2419 [(set_attr "cc" "clobber")
2420 (set_attr "length" "2")])
2423 [(set (match_operand:SI 0 "register_operand" "=r")
2424 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2425 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2427 "TARGET_H8300H || TARGET_H8300S"
2429 [(set_attr "cc" "clobber")
2430 (set_attr "length" "2")])
2433 [(set (match_operand:SI 0 "register_operand" "=r")
2434 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2436 (match_operand:SI 2 "register_operand" "0")))]
2437 "TARGET_H8300H || TARGET_H8300S"
2439 [(set_attr "cc" "clobber")
2440 (set_attr "length" "2")])
2442 ;; Storing a part of HImode to QImode.
2445 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2446 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
2450 [(set_attr "cc" "set_znv")
2451 (set_attr "length" "8")])
2453 ;; Storing a part of SImode to QImode.
2456 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2457 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2461 [(set_attr "cc" "set_znv")
2462 (set_attr "length" "8")])
2465 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2466 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2468 (clobber (match_scratch:SI 2 "=&r"))]
2469 "TARGET_H8300H || TARGET_H8300S"
2470 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
2471 [(set_attr "cc" "set_znv")
2472 (set_attr "length" "10")])
2475 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2476 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2478 (clobber (match_scratch:SI 2 "=&r"))]
2479 "TARGET_H8300H || TARGET_H8300S"
2480 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
2481 [(set_attr "cc" "set_znv")
2482 (set_attr "length" "10")])
2484 (define_insn_and_split ""
2486 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2490 (label_ref (match_operand 1 "" ""))
2498 (if_then_else (ge (cc0)
2500 (label_ref (match_dup 1))
2504 (define_insn_and_split ""
2506 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2510 (label_ref (match_operand 1 "" ""))
2518 (if_then_else (lt (cc0)
2520 (label_ref (match_dup 1))
2524 ;; -----------------------------------------------------------------
2525 ;; PEEPHOLE PATTERNS
2526 ;; -----------------------------------------------------------------
2528 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
2532 [(set (match_operand:HI 0 "register_operand" "")
2533 (lshiftrt:HI (match_dup 0)
2534 (match_operand:HI 1 "const_int_operand" "")))
2535 (clobber (match_operand:HI 2 "" ""))])
2537 (and:HI (match_dup 0)
2538 (match_operand:HI 3 "const_int_operand" "")))]
2539 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
2541 (and:HI (match_dup 0)
2545 (lshiftrt:HI (match_dup 0)
2547 (clobber (match_dup 2))])]
2550 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
2554 [(set (match_operand:HI 0 "register_operand" "")
2555 (ashift:HI (match_dup 0)
2556 (match_operand:HI 1 "const_int_operand" "")))
2557 (clobber (match_operand:HI 2 "" ""))])
2559 (and:HI (match_dup 0)
2560 (match_operand:HI 3 "const_int_operand" "")))]
2561 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
2563 (and:HI (match_dup 0)
2567 (ashift:HI (match_dup 0)
2569 (clobber (match_dup 2))])]
2572 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
2576 [(set (match_operand:SI 0 "register_operand" "")
2577 (lshiftrt:SI (match_dup 0)
2578 (match_operand:SI 1 "const_int_operand" "")))
2579 (clobber (match_operand:SI 2 "" ""))])
2581 (and:SI (match_dup 0)
2582 (match_operand:SI 3 "const_int_operand" "")))]
2583 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
2585 (and:SI (match_dup 0)
2589 (lshiftrt:SI (match_dup 0)
2591 (clobber (match_dup 2))])]
2594 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
2598 [(set (match_operand:SI 0 "register_operand" "")
2599 (ashift:SI (match_dup 0)
2600 (match_operand:SI 1 "const_int_operand" "")))
2601 (clobber (match_operand:SI 2 "" ""))])
2603 (and:SI (match_dup 0)
2604 (match_operand:SI 3 "const_int_operand" "")))]
2605 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
2607 (and:SI (match_dup 0)
2611 (ashift:SI (match_dup 0)
2613 (clobber (match_dup 2))])]
2616 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
2620 [(set (match_operand:SI 0 "register_operand" "")
2621 (lshiftrt:SI (match_dup 0)
2622 (match_operand:SI 1 "const_int_operand" "")))
2623 (clobber (match_operand:SI 2 "" ""))])
2625 (and:SI (match_dup 0)
2626 (match_operand:SI 3 "const_int_operand" "")))]
2627 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
2629 (and:SI (match_dup 0)
2633 (lshiftrt:SI (match_dup 0)
2635 (clobber (match_dup 2))])]
2638 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
2642 [(set (match_operand:SI 0 "register_operand" "")
2643 (ashift:SI (match_dup 0)
2644 (match_operand:SI 1 "const_int_operand" "")))
2645 (clobber (match_operand:SI 2 "" ""))])
2647 (and:SI (match_dup 0)
2648 (match_operand:SI 3 "const_int_operand" "")))]
2649 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
2651 (and:SI (match_dup 0)
2655 (ashift:SI (match_dup 0)
2657 (clobber (match_dup 2))])]
2660 ;; Convert a QImode push into an SImode push so that the
2661 ;; define_peephole2 below can cram multiple pushes into one stm.l.
2664 [(parallel [(set (reg:SI SP_REG)
2665 (plus:SI (reg:SI SP_REG) (const_int -4)))
2666 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
2667 (match_operand:QI 0 "register_operand" ""))])]
2669 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2671 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
2673 ;; Convert a HImode push into an SImode push so that the
2674 ;; define_peephole2 below can cram multiple pushes into one stm.l.
2677 [(parallel [(set (reg:SI SP_REG)
2678 (plus:SI (reg:SI SP_REG) (const_int -4)))
2679 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
2680 (match_operand:HI 0 "register_operand" ""))])]
2682 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2684 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
2686 ;; Cram four pushes into stm.l.
2689 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2690 (match_operand:SI 0 "register_operand" ""))
2691 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2692 (match_operand:SI 1 "register_operand" ""))
2693 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2694 (match_operand:SI 2 "register_operand" ""))
2695 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2696 (match_operand:SI 3 "register_operand" ""))]
2698 && REGNO (operands[0]) == 0
2699 && REGNO (operands[1]) == 1
2700 && REGNO (operands[2]) == 2
2701 && REGNO (operands[3]) == 3"
2702 [(parallel [(set (reg:SI SP_REG)
2703 (plus:SI (reg:SI SP_REG)
2705 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2707 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2709 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2711 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
2715 ;; Cram three pushes into stm.l.
2718 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2719 (match_operand:SI 0 "register_operand" ""))
2720 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2721 (match_operand:SI 1 "register_operand" ""))
2722 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2723 (match_operand:SI 2 "register_operand" ""))]
2725 && ((REGNO (operands[0]) == 0
2726 && REGNO (operands[1]) == 1
2727 && REGNO (operands[2]) == 2)
2728 || (REGNO (operands[0]) == 4
2729 && REGNO (operands[1]) == 5
2730 && REGNO (operands[2]) == 6))"
2731 [(parallel [(set (reg:SI SP_REG)
2732 (plus:SI (reg:SI SP_REG)
2734 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2736 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2738 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2742 ;; Cram two pushes into stm.l.
2745 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2746 (match_operand:SI 0 "register_operand" ""))
2747 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2748 (match_operand:SI 1 "register_operand" ""))]
2750 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2751 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2752 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2753 [(parallel [(set (reg:SI SP_REG)
2754 (plus:SI (reg:SI SP_REG)
2756 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2758 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2765 ;; add.w r7,r0 (6 bytes)
2770 ;; adds #2,r0 (4 bytes)
2773 [(set (match_operand:HI 0 "register_operand" "")
2774 (match_operand:HI 1 "const_int_operand" ""))
2776 (plus:HI (match_dup 0)
2777 (match_operand:HI 2 "register_operand" "")))]
2778 "REG_P (operands[0]) && REG_P (operands[2])
2779 && REGNO (operands[0]) != REGNO (operands[2])
2780 && (CONST_OK_FOR_J (INTVAL (operands[1]))
2781 || CONST_OK_FOR_L (INTVAL (operands[1]))
2782 || CONST_OK_FOR_N (INTVAL (operands[1])))"
2786 (plus:HI (match_dup 0)
2794 ;; add.l er7,er0 (6 bytes)
2799 ;; adds #4,er0 (4 bytes)
2802 [(set (match_operand:SI 0 "register_operand" "")
2803 (match_operand:SI 1 "const_int_operand" ""))
2805 (plus:SI (match_dup 0)
2806 (match_operand:SI 2 "register_operand" "")))]
2807 "(TARGET_H8300H || TARGET_H8300S)
2808 && REG_P (operands[0]) && REG_P (operands[2])
2809 && REGNO (operands[0]) != REGNO (operands[2])
2810 && (CONST_OK_FOR_L (INTVAL (operands[1]))
2811 || CONST_OK_FOR_N (INTVAL (operands[1])))"
2815 (plus:SI (match_dup 0)
2822 ;; add.l #10,er0 (takes 8 bytes)
2828 ;; add.l er7,er0 (takes 6 bytes)
2831 [(set (match_operand:SI 0 "register_operand" "")
2832 (match_operand:SI 1 "register_operand" ""))
2834 (plus:SI (match_dup 0)
2835 (match_operand:SI 2 "const_int_operand" "")))]
2836 "(TARGET_H8300H || TARGET_H8300S)
2837 && REG_P (operands[0]) && REG_P (operands[1])
2838 && REGNO (operands[0]) != REGNO (operands[1])
2839 && !CONST_OK_FOR_L (INTVAL (operands[2]))
2840 && !CONST_OK_FOR_N (INTVAL (operands[2]))
2841 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
2842 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
2843 || INTVAL (operands[2]) == 0xffff
2844 || INTVAL (operands[2]) == 0xfffe)"
2848 (plus:SI (match_dup 0)
2864 [(set (match_operand:HI 0 "register_operand" "")
2865 (plus:HI (match_dup 0)
2866 (match_operand 1 "incdec_operand" "")))
2870 (if_then_else (match_operator 3 "eqne_operator"
2871 [(cc0) (const_int 0)])
2872 (label_ref (match_operand 2 "" ""))
2874 "TARGET_H8300H || TARGET_H8300S"
2875 [(set (match_operand:HI 0 "register_operand" "")
2876 (unspec:HI [(match_dup 0)
2882 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
2883 (label_ref (match_dup 2))
2887 ;; The SImode version of the previous pattern.
2890 [(set (match_operand:SI 0 "register_operand" "")
2891 (plus:SI (match_dup 0)
2892 (match_operand 1 "incdec_operand" "")))
2896 (if_then_else (match_operator 3 "eqne_operator"
2897 [(cc0) (const_int 0)])
2898 (label_ref (match_operand 2 "" ""))
2900 "TARGET_H8300H || TARGET_H8300S"
2901 [(set (match_operand:SI 0 "register_operand" "")
2902 (unspec:SI [(match_dup 0)
2908 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
2909 (label_ref (match_dup 2))
2913 ;; For a small constant, it is cheaper to actually do the subtraction
2914 ;; and then test the register.
2918 (compare:HI (match_operand:HI 0 "register_operand" "")
2919 (match_operand:HI 1 "const_le_2_operand" "")))
2921 (if_then_else (match_operator 3 "eqne_operator"
2922 [(cc0) (const_int 0)])
2923 (label_ref (match_operand 2 "" ""))
2925 "(TARGET_H8300H || TARGET_H8300S)
2926 && find_regno_note (insn, REG_DEAD, REGNO (operands[0]))"
2930 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
2931 (label_ref (match_operand 2 "" ""))
2933 "operands[1] = GEN_INT (- INTVAL (operands[1]));
2934 split_adds_subs (HImode, operands, 1);")
2936 ;; The SImode version of the previous pattern.
2940 (compare:SI (match_operand:SI 0 "register_operand" "")
2941 (match_operand:SI 1 "const_le_6_operand" "")))
2943 (if_then_else (match_operator 3 "eqne_operator"
2944 [(cc0) (const_int 0)])
2945 (label_ref (match_operand 2 "" ""))
2947 "(TARGET_H8300H || TARGET_H8300S)
2948 && find_regno_note (insn, REG_DEAD, REGNO (operands[0]))"
2952 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
2953 (label_ref (match_operand 2 "" ""))
2955 "operands[1] = GEN_INT (- INTVAL (operands[1]));
2956 split_adds_subs (SImode, operands, 1);")