1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have an insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
64 ;; ----------------------------------------------------------------------
66 ;; ----------------------------------------------------------------------
68 (define_attr "cpu" "h8300,h8300h"
69 (const (symbol_ref "cpu_type")))
71 (define_attr "type" "branch,arith"
72 (const_string "arith"))
74 ;; The size of instructions in bytes.
76 (define_attr "length" ""
77 (cond [(eq_attr "type" "branch")
78 (if_then_else (and (ge (minus (match_dup 0) (pc))
80 (le (minus (match_dup 0) (pc))
83 (if_then_else (and (eq_attr "cpu" "h8300h")
84 (and (ge (minus (pc) (match_dup 0))
86 (le (minus (pc) (match_dup 0))
92 ;; The necessity of instruction length adjustment.
94 (define_attr "adjust_length" "yes,no"
95 (cond [(eq_attr "type" "branch") (const_string "no")]
96 (const_string "yes")))
98 ;; Condition code settings.
100 ;; none - insn does not affect cc
101 ;; none_0hit - insn does not affect cc but it does modify operand 0
102 ;; This attribute is used to keep track of when operand 0 changes.
103 ;; See the description of NOTICE_UPDATE_CC for more info.
104 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
105 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
106 ;; compare - compare instruction
107 ;; clobber - value of cc is unknown
109 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
110 (const_string "clobber"))
112 ;; ----------------------------------------------------------------------
114 ;; ----------------------------------------------------------------------
118 (define_insn "pushqi1_h8300"
119 [(parallel [(set (reg:HI SP_REG)
120 (plus:HI (reg:HI SP_REG) (const_int -2)))
121 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
122 (match_operand:QI 0 "register_operand" "r"))])]
124 && REGNO (operands[0]) != SP_REG"
126 [(set_attr "length" "2")
127 (set_attr "cc" "clobber")])
129 (define_insn "pushqi1_h8300hs"
130 [(parallel [(set (reg:SI SP_REG)
131 (plus:SI (reg:SI SP_REG) (const_int -4)))
132 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
133 (match_operand:QI 0 "register_operand" "r"))])]
134 "(TARGET_H8300H || TARGET_H8300S)
135 && REGNO (operands[0]) != SP_REG"
137 [(set_attr "length" "4")
138 (set_attr "cc" "clobber")])
140 (define_expand "pushqi1"
141 [(use (match_operand:QI 0 "register_operand" ""))]
146 emit_insn (gen_pushqi1_h8300 (operands[0]));
148 emit_insn (gen_pushqi1_h8300hs (operands[0]));
153 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
154 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
156 && (register_operand (operands[0], QImode)
157 || register_operand (operands[1], QImode))"
165 [(set_attr "length" "2,2,2,2,4,4")
166 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
169 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
170 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
171 "(TARGET_H8300H || TARGET_H8300S)
172 && (register_operand (operands[0], QImode)
173 || register_operand (operands[1], QImode))"
181 [(set_attr "length" "2,2,2,2,8,8")
182 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
184 (define_expand "movqi"
185 [(set (match_operand:QI 0 "general_operand_dst" "")
186 (match_operand:QI 1 "general_operand_src" ""))]
190 /* One of the ops has to be in a register. */
191 if (!register_operand (operand0, QImode)
192 && !register_operand (operand1, QImode))
194 operands[1] = copy_to_mode_reg (QImode, operand1);
198 (define_insn "movstrictqi"
199 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
200 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
207 [(set_attr_alternative "length"
208 [(const_int 2) (const_int 2) (const_int 2)
209 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
210 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
214 (define_expand "pushhi1_h8300"
215 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
216 (match_operand:HI 0 "register_operand" ""))]
218 && REGNO (operands[0]) != SP_REG"
221 (define_insn "pushhi1_h8300hs"
222 [(parallel [(set (reg:SI SP_REG)
223 (plus:SI (reg:SI SP_REG) (const_int -4)))
224 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
225 (match_operand:HI 0 "register_operand" "r"))])]
226 "(TARGET_H8300H || TARGET_H8300S)
227 && REGNO (operands[0]) != SP_REG"
229 [(set_attr "length" "4")
230 (set_attr "cc" "clobber")])
232 (define_expand "pushhi1"
233 [(use (match_operand:HI 0 "register_operand" ""))]
238 emit_insn (gen_pushhi1_h8300 (operands[0]));
240 emit_insn (gen_pushhi1_h8300hs (operands[0]));
245 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
246 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
248 && (register_operand (operands[0], HImode)
249 || register_operand (operands[1], HImode))
250 && !(GET_CODE (operands[0]) == MEM
251 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
252 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
253 && GET_CODE (operands[1]) == REG
254 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
262 [(set_attr "length" "2,2,2,4,4,4")
263 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
266 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
267 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
268 "(TARGET_H8300H || TARGET_H8300S)
269 && (register_operand (operands[0], HImode)
270 || register_operand (operands[1], HImode))"
278 [(set_attr "length" "2,2,2,4,8,8")
279 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
281 (define_expand "movhi"
282 [(set (match_operand:HI 0 "general_operand_dst" "")
283 (match_operand:HI 1 "general_operand_src" ""))]
287 /* One of the ops has to be in a register. */
288 if (!register_operand (operand1, HImode)
289 && !register_operand (operand0, HImode))
291 operands[1] = copy_to_mode_reg (HImode, operand1);
295 (define_insn "movstricthi"
296 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
297 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
304 [(set_attr_alternative "length"
305 [(const_int 2) (const_int 2) (const_int 4)
306 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
307 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
311 (define_expand "movsi"
312 [(set (match_operand:SI 0 "general_operand_dst" "")
313 (match_operand:SI 1 "general_operand_src" ""))]
319 if (do_movsi (operands))
324 /* One of the ops has to be in a register. */
325 if (!register_operand (operand1, SImode)
326 && !register_operand (operand0, SImode))
328 operands[1] = copy_to_mode_reg (SImode, operand1);
333 (define_expand "movsf"
334 [(set (match_operand:SF 0 "general_operand_dst" "")
335 (match_operand:SF 1 "general_operand_src" ""))]
341 if (do_movsi (operands))
346 /* One of the ops has to be in a register. */
347 if (!register_operand (operand1, SFmode)
348 && !register_operand (operand0, SFmode))
350 operands[1] = copy_to_mode_reg (SFmode, operand1);
355 (define_insn "movsi_h8300"
356 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
357 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
359 && (register_operand (operands[0], SImode)
360 || register_operand (operands[1], SImode))"
363 unsigned int rn = -1;
364 switch (which_alternative)
367 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
369 if (REGNO (operands[0]) < REGNO (operands[1]))
370 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
372 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
374 /* Make sure we don't trample the register we index with. */
375 if (GET_CODE (operands[1]) == MEM)
377 rtx inside = XEXP (operands[1], 0);
382 else if (GET_CODE (inside) == PLUS)
384 rtx lhs = XEXP (inside, 0);
385 rtx rhs = XEXP (inside, 1);
386 if (REG_P (lhs)) rn = REGNO (lhs);
387 if (REG_P (rhs)) rn = REGNO (rhs);
390 if (rn == REGNO (operands[0]))
392 /* Move the second word first. */
393 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
397 /* See if either half is zero. If so, use sub.w to clear
399 if (GET_CODE (operands[1]) == CONST_INT)
401 if ((INTVAL (operands[1]) & 0xffff) == 0)
402 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
403 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
404 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
406 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
409 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
411 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
413 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
418 [(set_attr "length" "4,4,8,8,4,4")
419 (set_attr "cc" "clobber")])
421 (define_insn "movsf_h8300"
422 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
423 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
425 && (register_operand (operands[0], SFmode)
426 || register_operand (operands[1], SFmode))"
429 /* Copy of the movsi stuff. */
430 unsigned int rn = -1;
431 switch (which_alternative)
434 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
436 if (REGNO (operands[0]) < REGNO (operands[1]))
437 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
439 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
441 /* Make sure we don't trample the register we index with. */
442 if (GET_CODE (operands[1]) == MEM)
444 rtx inside = XEXP (operands[1], 0);
449 else if (GET_CODE (inside) == PLUS)
451 rtx lhs = XEXP (inside, 0);
452 rtx rhs = XEXP (inside, 1);
453 if (REG_P (lhs)) rn = REGNO (lhs);
454 if (REG_P (rhs)) rn = REGNO (rhs);
457 if (rn == REGNO (operands[0]))
458 /* Move the second word first. */
459 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
461 /* Move the first word first. */
462 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
465 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
467 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
469 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
474 [(set_attr "length" "4,4,8,8,4,4")
475 (set_attr "cc" "clobber")])
477 (define_insn "movsi_h8300hs"
478 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
479 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
480 "(TARGET_H8300S || TARGET_H8300H)
481 && (register_operand (operands[0], SImode)
482 || register_operand (operands[1], SImode))
483 && !(GET_CODE (operands[0]) == MEM
484 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
485 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
486 && GET_CODE (operands[1]) == REG
487 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
490 switch (which_alternative)
493 return \"sub.l %S0,%S0\";
497 return \"clrmac\;ldmac %1,macl\";
499 return \"stmac macl,%0\";
501 if (GET_CODE (operands[1]) == CONST_INT)
503 int val = INTVAL (operands[1]);
505 /* Look for constants which can be made by adding an 8-bit
506 number to zero in one of the two low bytes. */
507 if (val == (val & 0xff))
509 operands[1] = GEN_INT ((char) val & 0xff);
510 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
513 if (val == (val & 0xff00))
515 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
516 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
519 /* Look for constants that can be obtained by subs, inc, and
521 switch (val & 0xffffffff)
524 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
526 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
528 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
531 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
533 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
536 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
538 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
541 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
543 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
547 return \"mov.l %S1,%S0\";
549 [(set_attr "length" "2,2,6,4,4,10,10,2,6,4")
550 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
552 (define_insn "movsf_h8300h"
553 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
554 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
555 "(TARGET_H8300H || TARGET_H8300S)
556 && (register_operand (operands[0], SFmode)
557 || register_operand (operands[1], SFmode))"
565 [(set_attr "length" "2,2,10,10,4,4")
566 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
568 ;; ----------------------------------------------------------------------
570 ;; ----------------------------------------------------------------------
573 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
575 (match_operand 1 "const_int_operand" "n,n")))]
578 [(set_attr "length" "2,4")
579 (set_attr "cc" "set_zn,set_zn")])
582 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
584 (match_operand 1 "const_int_operand" "n")))]
587 [(set_attr "length" "2")
588 (set_attr "cc" "set_zn")])
590 (define_insn "*tst_extzv_bitqi_1_n"
591 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_operand" "r,U")
593 (match_operand 1 "const_int_operand" "n,n")))]
594 "(TARGET_H8300H || TARGET_H8300S)
595 && INTVAL (operands[1]) != 7"
597 [(set_attr "length" "2,8")
598 (set_attr "cc" "set_zn,set_zn")])
600 (define_insn_and_split "*tst_extzv_memqi_1_n"
601 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
603 (match_operand 1 "const_int_operand" "n")))
604 (clobber (match_scratch:QI 2 "=&r"))]
605 "(TARGET_H8300H || TARGET_H8300S)
606 && !EXTRA_CONSTRAINT (operands[0], 'U')
607 && INTVAL (operands[1]) != 7"
609 "&& reload_completed"
612 (set (cc0) (zero_extract:SI (match_dup 2)
618 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
620 (match_operand 1 "const_int_operand" "n")))]
621 "(TARGET_H8300H || TARGET_H8300S)
622 && INTVAL (operands[1]) <= 15"
624 [(set_attr "length" "2")
625 (set_attr "cc" "set_zn")])
629 (and:HI (match_operand:HI 0 "register_operand" "r")
630 (match_operand:HI 1 "single_one_operand" "n")))]
634 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
635 if (INTVAL (operands[1]) > 128)
637 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
638 return \"btst\\t%V1,%t0\";
640 return \"btst\\t%V1,%s0\";
642 [(set_attr "length" "2")
643 (set_attr "cc" "set_zn")])
647 (and:SI (match_operand:SI 0 "register_operand" "r")
648 (match_operand:SI 1 "single_one_operand" "n")))]
649 "(TARGET_H8300H || TARGET_H8300S)
650 && (INTVAL (operands[1]) & 0xffff) != 0"
653 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
654 if (INTVAL (operands[1]) > 128)
656 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
657 return \"btst\\t%V1,%x0\";
659 return \"btst\\t%V1,%w0\";
661 [(set_attr "length" "2")
662 (set_attr "cc" "set_zn")])
665 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
668 [(set_attr "length" "2")
669 (set_attr "cc" "set_znv")])
672 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
675 [(set_attr "length" "2")
676 (set_attr "cc" "set_znv")])
680 (and:HI (match_operand:HI 0 "register_operand" "r")
684 [(set_attr "length" "2")
685 (set_attr "cc" "set_znv")])
688 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
689 "TARGET_H8300H || TARGET_H8300S"
691 [(set_attr "length" "2")
692 (set_attr "cc" "set_znv")])
696 (and:SI (match_operand:SI 0 "register_operand" "r")
697 (const_int -65536)))]
700 [(set_attr "length" "2")
701 (set_attr "cc" "set_znv")])
705 (compare:QI (match_operand:QI 0 "register_operand" "r")
706 (match_operand:QI 1 "nonmemory_operand" "rn")))]
709 [(set_attr "length" "2")
710 (set_attr "cc" "compare")])
712 (define_expand "cmphi"
714 (compare:HI (match_operand:HI 0 "register_operand" "")
715 (match_operand:HI 1 "nonmemory_operand" "")))]
719 /* Force operand1 into a register if we're compiling
721 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
722 operands[1] = force_reg (HImode, operands[1]);
727 (compare:HI (match_operand:HI 0 "register_operand" "r")
728 (match_operand:HI 1 "register_operand" "r")))]
731 [(set_attr "length" "2")
732 (set_attr "cc" "compare")])
736 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
737 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
738 "TARGET_H8300H || TARGET_H8300S"
740 [(set_attr "length" "2,4")
741 (set_attr "cc" "compare,compare")])
745 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
746 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
747 "TARGET_H8300H || TARGET_H8300S"
749 [(set_attr "length" "2,6")
750 (set_attr "cc" "compare,compare")])
752 ;; ----------------------------------------------------------------------
754 ;; ----------------------------------------------------------------------
756 (define_insn "addqi3"
757 [(set (match_operand:QI 0 "register_operand" "=r")
758 (plus:QI (match_operand:QI 1 "register_operand" "%0")
759 (match_operand:QI 2 "nonmemory_operand" "rn")))]
762 [(set_attr "length" "2")
763 (set_attr "cc" "set_zn")])
765 (define_expand "addhi3"
766 [(set (match_operand:HI 0 "register_operand" "")
767 (plus:HI (match_operand:HI 1 "register_operand" "")
768 (match_operand:HI 2 "nonmemory_operand" "")))]
772 (define_insn "*addhi3_h8300"
773 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
774 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
775 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
781 add.b %s2,%s0\;addx %t2,%t0
783 [(set_attr "length" "2,2,2,4,2")
784 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
786 (define_insn "*addhi3_h8300hs"
787 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
788 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
789 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
790 "TARGET_H8300H || TARGET_H8300S"
797 [(set_attr "length" "2,2,2,4,2")
798 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
800 (define_insn "addhi3_incdec"
801 [(set (match_operand:HI 0 "register_operand" "=r,r")
802 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
803 (match_operand:HI 2 "incdec_operand" "M,O")]
805 "TARGET_H8300H || TARGET_H8300S"
809 [(set_attr "length" "2,2")
810 (set_attr "cc" "set_zn,set_zn")])
813 [(set (match_operand:HI 0 "register_operand" "")
814 (plus:HI (match_dup 0)
815 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
818 "split_adds_subs (HImode, operands, 0); DONE;")
820 (define_expand "addsi3"
821 [(set (match_operand:SI 0 "register_operand" "")
822 (plus:SI (match_operand:SI 1 "register_operand" "")
823 (match_operand:SI 2 "nonmemory_operand" "")))]
827 (define_insn "addsi_h8300"
828 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
829 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
830 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
833 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
834 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
835 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
836 [(set_attr "length" "8,6,10")
837 (set_attr "cc" "clobber")])
839 (define_insn "addsi_h8300h"
840 [(set (match_operand:SI 0 "register_operand" "=r,r")
841 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
842 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
843 "TARGET_H8300H || TARGET_H8300S"
844 "* return output_plussi (operands);"
845 [(set (attr "length")
846 (symbol_ref "compute_plussi_length (operands)"))
848 (symbol_ref "compute_plussi_cc (operands)"))])
850 (define_insn "addsi3_incdec"
851 [(set (match_operand:SI 0 "register_operand" "=r,r")
852 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
853 (match_operand:SI 2 "incdec_operand" "M,O")]
855 "TARGET_H8300H || TARGET_H8300S"
859 [(set_attr "length" "2,2")
860 (set_attr "cc" "set_zn,set_zn")])
863 [(set (match_operand:SI 0 "register_operand" "")
864 (plus:SI (match_dup 0)
865 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
866 "TARGET_H8300H || TARGET_H8300S"
868 "split_adds_subs (SImode, operands, 0); DONE;")
870 ;; ----------------------------------------------------------------------
871 ;; SUBTRACT INSTRUCTIONS
872 ;; ----------------------------------------------------------------------
874 (define_insn "subqi3"
875 [(set (match_operand:QI 0 "register_operand" "=r")
876 (minus:QI (match_operand:QI 1 "register_operand" "0")
877 (match_operand:QI 2 "register_operand" "r")))]
880 [(set_attr "length" "2")
881 (set_attr "cc" "set_zn")])
883 (define_expand "subhi3"
884 [(set (match_operand:HI 0 "register_operand" "")
885 (minus:HI (match_operand:HI 1 "general_operand" "")
886 (match_operand:HI 2 "nonmemory_operand" "")))]
891 [(set (match_operand:HI 0 "register_operand" "=r,&r")
892 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
893 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
897 add.b %E2,%s0\;addx %F2,%t0"
898 [(set_attr "length" "2,4")
899 (set_attr "cc" "set_zn,clobber")])
902 [(set (match_operand:HI 0 "register_operand" "=r,&r")
903 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
904 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
905 "TARGET_H8300H || TARGET_H8300S"
909 [(set_attr "length" "2,4")
910 (set_attr "cc" "set_zn,set_zn")])
912 (define_expand "subsi3"
913 [(set (match_operand:SI 0 "register_operand" "")
914 (minus:SI (match_operand:SI 1 "register_operand" "")
915 (match_operand:SI 2 "nonmemory_operand" "")))]
919 (define_insn "subsi3_h8300"
920 [(set (match_operand:SI 0 "register_operand" "=r")
921 (minus:SI (match_operand:SI 1 "register_operand" "0")
922 (match_operand:SI 2 "register_operand" "r")))]
924 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
925 [(set_attr "length" "6")
926 (set_attr "cc" "clobber")])
928 (define_insn "subsi3_h8300h"
929 [(set (match_operand:SI 0 "register_operand" "=r,r")
930 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
931 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
932 "TARGET_H8300H || TARGET_H8300S"
936 [(set_attr "length" "2,6")
937 (set_attr "cc" "set_zn,set_zn")])
939 ;; ----------------------------------------------------------------------
940 ;; MULTIPLY INSTRUCTIONS
941 ;; ----------------------------------------------------------------------
943 ;; Note that the H8/300 can only handle umulqihi3.
945 (define_insn "mulqihi3"
946 [(set (match_operand:HI 0 "register_operand" "=r")
947 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
948 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
949 "TARGET_H8300H || TARGET_H8300S"
951 [(set_attr "length" "4")
952 (set_attr "cc" "set_zn")])
954 (define_insn "mulhisi3"
955 [(set (match_operand:SI 0 "register_operand" "=r")
956 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
957 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
958 "TARGET_H8300H || TARGET_H8300S"
960 [(set_attr "length" "4")
961 (set_attr "cc" "set_zn")])
963 (define_insn "umulqihi3"
964 [(set (match_operand:HI 0 "register_operand" "=r")
965 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
966 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
969 [(set_attr "length" "2")
970 (set_attr "cc" "none_0hit")])
972 (define_insn "umulhisi3"
973 [(set (match_operand:SI 0 "register_operand" "=r")
974 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
975 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
976 "TARGET_H8300H || TARGET_H8300S"
978 [(set_attr "length" "2")
979 (set_attr "cc" "none_0hit")])
981 ;; This is a "bridge" instruction. Combine can't cram enough insns
982 ;; together to crate a MAC instruction directly, but it can create
983 ;; this instruction, which then allows combine to create the real
986 ;; Unfortunately, if combine doesn't create a MAC instruction, this
987 ;; insn must generate reasonably correct code. Egad.
989 [(set (match_operand:SI 0 "register_operand" "=a")
992 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
994 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
996 "clrmac\;mac @%2+,@%1+"
997 [(set_attr "length" "6")
998 (set_attr "cc" "none_0hit")])
1001 [(set (match_operand:SI 0 "register_operand" "=a")
1003 (sign_extend:SI (mem:HI
1004 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1005 (sign_extend:SI (mem:HI
1006 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1007 (match_operand:SI 3 "register_operand" "0")))]
1010 [(set_attr "length" "4")
1011 (set_attr "cc" "none_0hit")])
1013 ;; ----------------------------------------------------------------------
1014 ;; DIVIDE/MOD INSTRUCTIONS
1015 ;; ----------------------------------------------------------------------
1017 (define_insn "udivmodqi4"
1018 [(set (match_operand:QI 0 "register_operand" "=r")
1021 (match_operand:HI 1 "register_operand" "0")
1022 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1023 (set (match_operand:QI 3 "register_operand" "=r")
1027 (zero_extend:HI (match_dup 2)))))]
1031 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1032 return \"divxu.b\\t%X2,%T0\";
1034 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1036 [(set_attr "length" "4")
1037 (set_attr "cc" "clobber")])
1039 (define_insn "divmodqi4"
1040 [(set (match_operand:QI 0 "register_operand" "=r")
1043 (match_operand:HI 1 "register_operand" "0")
1044 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1045 (set (match_operand:QI 3 "register_operand" "=r")
1049 (sign_extend:HI (match_dup 2)))))]
1050 "TARGET_H8300H || TARGET_H8300S"
1053 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1054 return \"divxs.b\\t%X2,%T0\";
1056 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1058 [(set_attr "length" "6")
1059 (set_attr "cc" "clobber")])
1061 (define_insn "udivmodhi4"
1062 [(set (match_operand:HI 0 "register_operand" "=r")
1065 (match_operand:SI 1 "register_operand" "0")
1066 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1067 (set (match_operand:HI 3 "register_operand" "=r")
1071 (zero_extend:SI (match_dup 2)))))]
1072 "TARGET_H8300H || TARGET_H8300S"
1075 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1076 return \"divxu.w\\t%T2,%S0\";
1078 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1080 [(set_attr "length" "4")
1081 (set_attr "cc" "clobber")])
1083 (define_insn "divmodhi4"
1084 [(set (match_operand:HI 0 "register_operand" "=r")
1087 (match_operand:SI 1 "register_operand" "0")
1088 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1089 (set (match_operand:HI 3 "register_operand" "=r")
1093 (sign_extend:SI (match_dup 2)))))]
1094 "TARGET_H8300H || TARGET_H8300S"
1097 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1098 return \"divxs.w\\t%T2,%S0\";
1100 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1102 [(set_attr "length" "6")
1103 (set_attr "cc" "clobber")])
1105 ;; ----------------------------------------------------------------------
1107 ;; ----------------------------------------------------------------------
1110 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1111 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1112 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1113 "register_operand (operands[0], QImode)
1114 || single_zero_operand (operands[2], QImode)"
1118 [(set_attr "length" "2,8")
1119 (set_attr "adjust_length" "no")
1120 (set_attr "cc" "set_znv,none_0hit")])
1122 (define_expand "andqi3"
1123 [(set (match_operand:QI 0 "bit_operand" "")
1124 (and:QI (match_operand:QI 1 "bit_operand" "")
1125 (match_operand:QI 2 "nonmemory_operand" "")))]
1129 if (fix_bit_operand (operands, 0, AND))
1133 (define_expand "andhi3"
1134 [(set (match_operand:HI 0 "register_operand" "")
1135 (and:HI (match_operand:HI 1 "register_operand" "")
1136 (match_operand:HI 2 "nonmemory_operand" "")))]
1140 (define_insn "*andorqi3"
1141 [(set (match_operand:QI 0 "register_operand" "=r")
1142 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1143 (match_operand:QI 3 "single_one_operand" "n"))
1144 (match_operand:QI 1 "register_operand" "0")))]
1146 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1147 [(set_attr "length" "6")
1148 (set_attr "cc" "clobber")])
1150 (define_insn "*andorhi3"
1151 [(set (match_operand:HI 0 "register_operand" "=r")
1152 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1153 (match_operand:HI 3 "single_one_operand" "n"))
1154 (match_operand:HI 1 "register_operand" "0")))]
1158 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1159 if (INTVAL (operands[3]) > 128)
1161 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1162 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1164 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1166 [(set_attr "length" "6")
1167 (set_attr "cc" "clobber")])
1169 (define_insn "*andorsi3"
1170 [(set (match_operand:SI 0 "register_operand" "=r")
1171 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1172 (match_operand:SI 3 "single_one_operand" "n"))
1173 (match_operand:SI 1 "register_operand" "0")))]
1174 "(INTVAL (operands[3]) & 0xffff) != 0"
1177 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1178 if (INTVAL (operands[3]) > 128)
1180 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1181 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1183 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1185 [(set_attr "length" "6")
1186 (set_attr "cc" "clobber")])
1188 (define_insn "*andorsi3_shift_8"
1189 [(set (match_operand:SI 0 "register_operand" "=r")
1190 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1193 (match_operand:SI 1 "register_operand" "0")))]
1196 [(set_attr "length" "2")
1197 (set_attr "cc" "clobber")])
1199 (define_expand "andsi3"
1200 [(set (match_operand:SI 0 "register_operand" "")
1201 (and:SI (match_operand:SI 1 "register_operand" "")
1202 (match_operand:SI 2 "nonmemory_operand" "")))]
1206 ;; ----------------------------------------------------------------------
1208 ;; ----------------------------------------------------------------------
1211 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1212 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1213 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1214 "register_operand (operands[0], QImode)
1215 || single_one_operand (operands[2], QImode)"
1219 [(set_attr "length" "2,8")
1220 (set_attr "adjust_length" "no")
1221 (set_attr "cc" "set_znv,none_0hit")])
1223 (define_expand "iorqi3"
1224 [(set (match_operand:QI 0 "bit_operand" "")
1225 (ior:QI (match_operand:QI 1 "bit_operand" "")
1226 (match_operand:QI 2 "nonmemory_operand" "")))]
1230 if (fix_bit_operand (operands, 1, IOR))
1234 (define_expand "iorhi3"
1235 [(set (match_operand:HI 0 "register_operand" "")
1236 (ior:HI (match_operand:HI 1 "register_operand" "")
1237 (match_operand:HI 2 "nonmemory_operand" "")))]
1241 (define_expand "iorsi3"
1242 [(set (match_operand:SI 0 "register_operand" "")
1243 (ior:SI (match_operand:SI 1 "register_operand" "")
1244 (match_operand:SI 2 "nonmemory_operand" "")))]
1248 ;; ----------------------------------------------------------------------
1250 ;; ----------------------------------------------------------------------
1253 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1254 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1255 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1256 "register_operand (operands[0], QImode)
1257 || single_one_operand (operands[2], QImode)"
1261 [(set_attr "length" "2,8")
1262 (set_attr "adjust_length" "no")
1263 (set_attr "cc" "set_znv,none_0hit")])
1265 (define_expand "xorqi3"
1266 [(set (match_operand:QI 0 "bit_operand" "")
1267 (xor:QI (match_operand:QI 1 "bit_operand" "")
1268 (match_operand:QI 2 "nonmemory_operand" "")))]
1272 if (fix_bit_operand (operands, 1, XOR))
1276 (define_expand "xorhi3"
1277 [(set (match_operand:HI 0 "register_operand" "")
1278 (xor:HI (match_operand:HI 1 "register_operand" "")
1279 (match_operand:HI 2 "nonmemory_operand" "")))]
1283 (define_expand "xorsi3"
1284 [(set (match_operand:SI 0 "register_operand" "")
1285 (xor:SI (match_operand:SI 1 "register_operand" "")
1286 (match_operand:SI 2 "nonmemory_operand" "")))]
1290 ;; ----------------------------------------------------------------------
1291 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1292 ;; ----------------------------------------------------------------------
1295 [(set (match_operand:HI 0 "register_operand" "=r")
1296 (match_operator:HI 3 "bit_operator"
1297 [(match_operand:HI 1 "register_operand" "%0")
1298 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1300 "* return output_logical_op (HImode, operands);"
1301 [(set (attr "length")
1302 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1304 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1307 [(set (match_operand:SI 0 "register_operand" "=r")
1308 (match_operator:SI 3 "bit_operator"
1309 [(match_operand:SI 1 "register_operand" "%0")
1310 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1312 "* return output_logical_op (SImode, operands);"
1313 [(set (attr "length")
1314 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1316 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1318 ;; ----------------------------------------------------------------------
1319 ;; NEGATION INSTRUCTIONS
1320 ;; ----------------------------------------------------------------------
1322 (define_insn "negqi2"
1323 [(set (match_operand:QI 0 "register_operand" "=r")
1324 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1327 [(set_attr "length" "2")
1328 (set_attr "cc" "set_zn")])
1330 (define_expand "neghi2"
1331 [(set (match_operand:HI 0 "register_operand" "")
1332 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1338 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1343 (define_expand "neghi2_h8300"
1345 (not:HI (match_operand:HI 1 "register_operand" "")))
1346 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1347 (set (match_operand:HI 0 "register_operand" "")
1350 "operands[2] = gen_reg_rtx (HImode);")
1352 (define_insn "neghi2_h8300h"
1353 [(set (match_operand:HI 0 "register_operand" "=r")
1354 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1355 "TARGET_H8300H || TARGET_H8300S"
1357 [(set_attr "length" "2")
1358 (set_attr "cc" "set_zn")])
1360 (define_expand "negsi2"
1361 [(set (match_operand:SI 0 "register_operand" "")
1362 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1368 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1373 (define_expand "negsi2_h8300"
1375 (not:SI (match_operand:SI 1 "register_operand" "")))
1376 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1377 (set (match_operand:SI 0 "register_operand" "")
1380 "operands[2] = gen_reg_rtx (SImode);")
1382 (define_insn "negsi2_h8300h"
1383 [(set (match_operand:SI 0 "register_operand" "=r")
1384 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1385 "TARGET_H8300H || TARGET_H8300S"
1387 [(set_attr "length" "2")
1388 (set_attr "cc" "set_zn")])
1390 (define_expand "negsf2"
1391 [(set (match_operand:SF 0 "register_operand" "")
1392 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1396 (define_insn "*negsf2_h8300"
1397 [(set (match_operand:SF 0 "register_operand" "=r")
1398 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1401 [(set_attr "cc" "clobber")
1402 (set_attr "length" "2")])
1404 (define_insn "*negsf2_h8300hs"
1405 [(set (match_operand:SF 0 "register_operand" "=r")
1406 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1407 "TARGET_H8300H || TARGET_H8300S"
1409 [(set_attr "cc" "clobber")
1410 (set_attr "length" "4")])
1412 ;; ----------------------------------------------------------------------
1414 ;; ----------------------------------------------------------------------
1416 (define_insn "one_cmplqi2"
1417 [(set (match_operand:QI 0 "register_operand" "=r")
1418 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1421 [(set_attr "length" "2")
1422 (set_attr "cc" "set_znv")])
1424 (define_expand "one_cmplhi2"
1425 [(set (match_operand:HI 0 "register_operand" "=r")
1426 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1431 [(set (match_operand:HI 0 "register_operand" "=r")
1432 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1435 [(set_attr "cc" "clobber")
1436 (set_attr "length" "4")])
1439 [(set (match_operand:HI 0 "register_operand" "=r")
1440 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1441 "TARGET_H8300H || TARGET_H8300S"
1443 [(set_attr "cc" "set_znv")
1444 (set_attr "length" "2")])
1446 (define_expand "one_cmplsi2"
1447 [(set (match_operand:SI 0 "register_operand" "=r")
1448 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1453 [(set (match_operand:SI 0 "register_operand" "=r")
1454 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1456 "not %w0\;not %x0\;not %y0\;not %z0"
1457 [(set_attr "cc" "clobber")
1458 (set_attr "length" "8")])
1461 [(set (match_operand:SI 0 "register_operand" "=r")
1462 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1463 "TARGET_H8300H || TARGET_H8300S"
1465 [(set_attr "cc" "set_znv")
1466 (set_attr "length" "2")])
1468 ;; ----------------------------------------------------------------------
1469 ;; JUMP INSTRUCTIONS
1470 ;; ----------------------------------------------------------------------
1472 ;; Conditional jump instructions
1474 (define_expand "ble"
1476 (if_then_else (le (cc0)
1478 (label_ref (match_operand 0 "" ""))
1483 (define_expand "bleu"
1485 (if_then_else (leu (cc0)
1487 (label_ref (match_operand 0 "" ""))
1492 (define_expand "bge"
1494 (if_then_else (ge (cc0)
1496 (label_ref (match_operand 0 "" ""))
1501 (define_expand "bgeu"
1503 (if_then_else (geu (cc0)
1505 (label_ref (match_operand 0 "" ""))
1510 (define_expand "blt"
1512 (if_then_else (lt (cc0)
1514 (label_ref (match_operand 0 "" ""))
1519 (define_expand "bltu"
1521 (if_then_else (ltu (cc0)
1523 (label_ref (match_operand 0 "" ""))
1528 (define_expand "bgt"
1530 (if_then_else (gt (cc0)
1532 (label_ref (match_operand 0 "" ""))
1537 (define_expand "bgtu"
1539 (if_then_else (gtu (cc0)
1541 (label_ref (match_operand 0 "" ""))
1546 (define_expand "beq"
1548 (if_then_else (eq (cc0)
1550 (label_ref (match_operand 0 "" ""))
1555 (define_expand "bne"
1557 (if_then_else (ne (cc0)
1559 (label_ref (match_operand 0 "" ""))
1564 (define_insn "branch_true"
1566 (if_then_else (match_operator 1 "comparison_operator"
1567 [(cc0) (const_int 0)])
1568 (label_ref (match_operand 0 "" ""))
1573 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1574 && (GET_CODE (operands[1]) == GT
1575 || GET_CODE (operands[1]) == GE
1576 || GET_CODE (operands[1]) == LE
1577 || GET_CODE (operands[1]) == LT))
1579 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1583 if (get_attr_length (insn) == 2)
1584 return \"b%j1 %l0\";
1585 else if (get_attr_length (insn) == 4)
1586 return \"b%j1 %l0:16\";
1588 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1590 [(set_attr "type" "branch")
1591 (set_attr "cc" "none")])
1593 (define_insn "branch_false"
1595 (if_then_else (match_operator 1 "comparison_operator"
1596 [(cc0) (const_int 0)])
1598 (label_ref (match_operand 0 "" ""))))]
1602 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1603 && (GET_CODE (operands[1]) == GT
1604 || GET_CODE (operands[1]) == GE
1605 || GET_CODE (operands[1]) == LE
1606 || GET_CODE (operands[1]) == LT))
1608 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1612 if (get_attr_length (insn) == 2)
1613 return \"b%k1 %l0\";
1614 else if (get_attr_length (insn) == 4)
1615 return \"b%k1 %l0:16\";
1617 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1619 [(set_attr "type" "branch")
1620 (set_attr "cc" "none")])
1622 ;; Unconditional and other jump instructions.
1626 (label_ref (match_operand 0 "" "")))]
1630 if (get_attr_length (insn) == 2)
1632 else if (get_attr_length (insn) == 4)
1633 return \"bra %l0:16\";
1635 return \"jmp @%l0\";
1637 [(set_attr "type" "branch")
1638 (set_attr "cc" "none")])
1640 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1642 (define_expand "tablejump"
1643 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1644 (use (label_ref (match_operand 1 "" "")))])]
1648 (define_insn "tablejump_h8300"
1649 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1650 (use (label_ref (match_operand 1 "" "")))]
1653 [(set_attr "cc" "none")
1654 (set_attr "length" "2")])
1656 (define_insn "tablejump_h8300h"
1657 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1658 (use (label_ref (match_operand 1 "" "")))]
1659 "TARGET_H8300H || TARGET_H8300S"
1661 [(set_attr "cc" "none")
1662 (set_attr "length" "2")])
1664 (define_insn "tablejump_normal_mode"
1665 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1666 (use (label_ref (match_operand 1 "" "")))]
1667 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1669 [(set_attr "cc" "none")
1670 (set_attr "length" "2")])
1672 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1674 (define_expand "indirect_jump"
1675 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1679 (define_insn "indirect_jump_h8300"
1680 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1683 [(set_attr "cc" "none")
1684 (set_attr "length" "2")])
1686 (define_insn "indirect_jump_h8300h"
1687 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1688 "TARGET_H8300H || TARGET_H8300S"
1690 [(set_attr "cc" "none")
1691 (set_attr "length" "2")])
1693 (define_insn "indirect_jump_normal_mode"
1694 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1695 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1697 [(set_attr "cc" "none")
1698 (set_attr "length" "2")])
1700 ;; Call subroutine with no return value.
1702 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1705 [(call (match_operand:QI 0 "call_insn_operand" "or")
1706 (match_operand:HI 1 "general_operand" "g"))]
1710 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1711 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1712 return \"jsr\\t@%0:8\";
1714 return \"jsr\\t%0\";
1716 [(set_attr "cc" "clobber")
1717 (set (attr "length")
1718 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1722 ;; Call subroutine, returning value in operand 0
1723 ;; (which must be a hard register).
1725 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1727 (define_insn "call_value"
1728 [(set (match_operand 0 "" "=r")
1729 (call (match_operand:QI 1 "call_insn_operand" "or")
1730 (match_operand:HI 2 "general_operand" "g")))]
1734 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1735 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1736 return \"jsr\\t@%1:8\";
1738 return \"jsr\\t%1\";
1740 [(set_attr "cc" "clobber")
1741 (set (attr "length")
1742 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1750 [(set_attr "cc" "none")
1751 (set_attr "length" "2")])
1753 ;; ----------------------------------------------------------------------
1754 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1755 ;; ----------------------------------------------------------------------
1757 (define_insn "*stm_h8300s_2"
1759 [(set (reg:SI SP_REG)
1760 (plus:SI (reg:SI SP_REG) (const_int -8)))
1761 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1762 (match_operand:SI 0 "register_operand" ""))
1763 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1764 (match_operand:SI 1 "register_operand" ""))])]
1766 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1767 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1768 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1769 "stm.l\\t%S0-%S1,@-er7"
1770 [(set_attr "cc" "none")
1771 (set_attr "length" "4")])
1773 (define_insn "*stm_h8300s_3"
1775 [(set (reg:SI SP_REG)
1776 (plus:SI (reg:SI SP_REG) (const_int -12)))
1777 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1778 (match_operand:SI 0 "register_operand" ""))
1779 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1780 (match_operand:SI 1 "register_operand" ""))
1781 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1782 (match_operand:SI 2 "register_operand" ""))])]
1784 && ((REGNO (operands[0]) == 0
1785 && REGNO (operands[1]) == 1
1786 && REGNO (operands[2]) == 2)
1787 || (REGNO (operands[0]) == 4
1788 && REGNO (operands[1]) == 5
1789 && REGNO (operands[2]) == 6))"
1790 "stm.l\\t%S0-%S2,@-er7"
1791 [(set_attr "cc" "none")
1792 (set_attr "length" "4")])
1794 (define_insn "*stm_h8300s_4"
1796 [(set (reg:SI SP_REG)
1797 (plus:SI (reg:SI SP_REG) (const_int -16)))
1798 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1799 (match_operand:SI 0 "register_operand" ""))
1800 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1801 (match_operand:SI 1 "register_operand" ""))
1802 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1803 (match_operand:SI 2 "register_operand" ""))
1804 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1805 (match_operand:SI 3 "register_operand" ""))])]
1807 && REGNO (operands[0]) == 0
1808 && REGNO (operands[1]) == 1
1809 && REGNO (operands[2]) == 2
1810 && REGNO (operands[3]) == 3"
1811 "stm.l\\t%S0-%S3,@-er7"
1812 [(set_attr "cc" "none")
1813 (set_attr "length" "4")])
1815 ;; ----------------------------------------------------------------------
1816 ;; EXTEND INSTRUCTIONS
1817 ;; ----------------------------------------------------------------------
1819 (define_expand "zero_extendqihi2"
1820 [(set (match_operand:HI 0 "register_operand" "")
1821 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1825 (define_insn "*zero_extendqihi2_h8300"
1826 [(set (match_operand:HI 0 "register_operand" "=r,r")
1827 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1832 [(set_attr "length" "2,10")
1833 (set_attr "cc" "clobber,clobber")])
1835 (define_insn "*zero_extendqihi2_h8300hs"
1836 [(set (match_operand:HI 0 "register_operand" "=r,r")
1837 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1838 "TARGET_H8300H || TARGET_H8300S"
1842 [(set_attr "length" "2,10")
1843 (set_attr "cc" "set_znv,set_znv")])
1845 ;; Split the zero extension of a general operand (actually a memory
1846 ;; operand) into a load of the operand and the actual zero extension
1847 ;; so that 1) the length will be accurate, and 2) the zero extensions
1848 ;; appearing at the end of basic blocks may be merged.
1851 [(set (match_operand:HI 0 "register_operand" "")
1852 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1857 (zero_extend:HI (match_dup 2)))]
1858 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
1860 ;; The compiler can synthesize a H8/300H variant of this which is
1861 ;; just as efficient as one that we'd create
1862 (define_insn "zero_extendqisi2"
1863 [(set (match_operand:SI 0 "register_operand" "=r,r")
1864 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1867 mov.b #0,%x0\;sub.w %e0,%e0
1868 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1869 [(set_attr "length" "4,8")
1870 (set_attr "cc" "clobber,clobber")])
1872 (define_expand "zero_extendhisi2"
1873 [(set (match_operand:SI 0 "register_operand" "")
1874 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1878 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1880 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1881 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1885 mov.w %f1,%f0\;sub.w %e0,%e0
1886 mov.w %e1,%f0\;sub.w %e0,%e0"
1887 [(set_attr "length" "2,4,4")
1888 (set_attr "cc" "clobber,clobber,clobber")])
1891 [(set (match_operand:SI 0 "register_operand" "=r")
1892 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1893 "TARGET_H8300H || TARGET_H8300S"
1895 [(set_attr "length" "2")
1896 (set_attr "cc" "set_znv")])
1898 (define_expand "extendqihi2"
1899 [(set (match_operand:HI 0 "register_operand" "")
1900 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1905 [(set (match_operand:HI 0 "register_operand" "=r,r")
1906 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1909 bld #7,%s0\;subx %t0,%t0
1910 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1911 [(set_attr "length" "4,8")
1912 (set_attr "cc" "clobber,clobber")])
1915 [(set (match_operand:HI 0 "register_operand" "=r")
1916 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1917 "TARGET_H8300H || TARGET_H8300S"
1919 [(set_attr "length" "2")
1920 (set_attr "cc" "set_znv")])
1922 ;; The compiler can synthesize a H8/300H variant of this which is
1923 ;; just as efficient as one that we'd create
1924 (define_insn "extendqisi2"
1925 [(set (match_operand:SI 0 "register_operand" "=r,r")
1926 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1929 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1930 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1931 [(set_attr "length" "8,10")
1932 (set_attr "cc" "clobber,clobber")])
1934 (define_expand "extendhisi2"
1935 [(set (match_operand:SI 0 "register_operand" "")
1936 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1941 [(set (match_operand:SI 0 "register_operand" "=r,r")
1942 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1945 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1946 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1947 [(set_attr "length" "6,8")
1948 (set_attr "cc" "clobber,clobber")])
1951 [(set (match_operand:SI 0 "register_operand" "=r")
1952 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1953 "TARGET_H8300H || TARGET_H8300S"
1955 [(set_attr "length" "2")
1956 (set_attr "cc" "set_znv")])
1958 ;; ----------------------------------------------------------------------
1960 ;; ----------------------------------------------------------------------
1962 ;; We make some attempt to provide real efficient shifting. One example is
1963 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1964 ;; reg and moving 0 into the former reg.
1966 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1967 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1968 ;; give the optimizer more cracks at the code. However, we wish to do things
1969 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1970 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1971 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1972 ;; to detect cases it can optimize.
1974 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1975 ;; easier "do it at insn emit time" route.
1979 (define_expand "ashlqi3"
1980 [(set (match_operand:QI 0 "register_operand" "")
1981 (ashift:QI (match_operand:QI 1 "register_operand" "")
1982 (match_operand:QI 2 "nonmemory_operand" "")))]
1984 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
1986 (define_expand "ashrqi3"
1987 [(set (match_operand:QI 0 "register_operand" "")
1988 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1989 (match_operand:QI 2 "nonmemory_operand" "")))]
1991 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
1993 (define_expand "lshrqi3"
1994 [(set (match_operand:QI 0 "register_operand" "")
1995 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1996 (match_operand:QI 2 "nonmemory_operand" "")))]
1998 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2001 [(set (match_operand:QI 0 "register_operand" "=r,r")
2002 (match_operator:QI 3 "nshift_operator"
2003 [ (match_operand:QI 1 "register_operand" "0,0")
2004 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2005 (clobber (match_scratch:QI 4 "=X,&r"))]
2007 "* return output_a_shift (operands);"
2008 [(set (attr "length")
2009 (symbol_ref "compute_a_shift_length (insn, operands)"))
2010 (set_attr "cc" "clobber")])
2014 (define_expand "ashlhi3"
2015 [(set (match_operand:HI 0 "register_operand" "")
2016 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2017 (match_operand:QI 2 "nonmemory_operand" "")))]
2019 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2021 (define_expand "lshrhi3"
2022 [(set (match_operand:HI 0 "register_operand" "")
2023 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2024 (match_operand:QI 2 "nonmemory_operand" "")))]
2026 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2028 (define_expand "ashrhi3"
2029 [(set (match_operand:HI 0 "register_operand" "")
2030 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2031 (match_operand:QI 2 "nonmemory_operand" "")))]
2033 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2036 [(set (match_operand:HI 0 "register_operand" "=r,r")
2037 (match_operator:HI 3 "nshift_operator"
2038 [ (match_operand:HI 1 "register_operand" "0,0")
2039 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2040 (clobber (match_scratch:QI 4 "=X,&r"))]
2042 "* return output_a_shift (operands);"
2043 [(set (attr "length")
2044 (symbol_ref "compute_a_shift_length (insn, operands)"))
2045 (set_attr "cc" "clobber")])
2049 (define_expand "ashlsi3"
2050 [(set (match_operand:SI 0 "register_operand" "")
2051 (ashift:SI (match_operand:SI 1 "general_operand" "")
2052 (match_operand:QI 2 "nonmemory_operand" "")))]
2054 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2056 (define_expand "lshrsi3"
2057 [(set (match_operand:SI 0 "register_operand" "")
2058 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2059 (match_operand:QI 2 "nonmemory_operand" "")))]
2061 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2063 (define_expand "ashrsi3"
2064 [(set (match_operand:SI 0 "register_operand" "")
2065 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2066 (match_operand:QI 2 "nonmemory_operand" "")))]
2068 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2071 [(set (match_operand:SI 0 "register_operand" "=r,r")
2072 (match_operator:SI 3 "nshift_operator"
2073 [ (match_operand:SI 1 "register_operand" "0,0")
2074 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2075 (clobber (match_scratch:QI 4 "=X,&r"))]
2077 "* return output_a_shift (operands);"
2078 [(set (attr "length")
2079 (symbol_ref "compute_a_shift_length (insn, operands)"))
2080 (set_attr "cc" "clobber")])
2082 ;; ----------------------------------------------------------------------
2084 ;; ----------------------------------------------------------------------
2086 (define_expand "rotlqi3"
2087 [(set (match_operand:QI 0 "register_operand" "")
2088 (rotate:QI (match_operand:QI 1 "register_operand" "")
2089 (match_operand:QI 2 "nonmemory_operand" "")))]
2091 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2093 (define_insn "*rotlqi3_1"
2094 [(set (match_operand:QI 0 "register_operand" "=r")
2095 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2096 (match_operand:QI 2 "immediate_operand" "")))]
2098 "* return emit_a_rotate (ROTATE, operands);"
2099 [(set_attr "length" "20")
2100 (set_attr "cc" "clobber")])
2102 (define_expand "rotlhi3"
2103 [(set (match_operand:HI 0 "register_operand" "")
2104 (rotate:HI (match_operand:HI 1 "register_operand" "")
2105 (match_operand:QI 2 "nonmemory_operand" "")))]
2107 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2109 (define_insn "*rotlhi3_1"
2110 [(set (match_operand:HI 0 "register_operand" "=r")
2111 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2112 (match_operand:QI 2 "immediate_operand" "")))]
2114 "* return emit_a_rotate (ROTATE, operands);"
2115 [(set_attr "length" "20")
2116 (set_attr "cc" "clobber")])
2118 (define_expand "rotlsi3"
2119 [(set (match_operand:SI 0 "register_operand" "")
2120 (rotate:SI (match_operand:SI 1 "register_operand" "")
2121 (match_operand:QI 2 "nonmemory_operand" "")))]
2122 "TARGET_H8300H || TARGET_H8300S"
2123 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2125 (define_insn "*rotlsi3_1"
2126 [(set (match_operand:SI 0 "register_operand" "=r")
2127 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2128 (match_operand:QI 2 "immediate_operand" "")))]
2129 "TARGET_H8300H || TARGET_H8300S"
2130 "* return emit_a_rotate (ROTATE, operands);"
2131 [(set_attr "length" "20")
2132 (set_attr "cc" "clobber")])
2134 ;; -----------------------------------------------------------------
2136 ;; -----------------------------------------------------------------
2137 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2138 ;; instructions so let's use them as well as we can.
2140 ;; You'll never believe all these patterns perform one basic action --
2141 ;; load a bit from the source, optionally invert the bit, then store it
2142 ;; in the destination (which is known to be zero).
2144 ;; Combine obviously need some work to better identify this situation and
2145 ;; canonicalize the form better.
2148 ;; Normal loads with a 16bit destination.
2152 [(set (match_operand:HI 0 "register_operand" "=&r")
2153 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2155 (match_operand:HI 2 "immediate_operand" "n")))]
2157 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2158 [(set_attr "cc" "clobber")
2159 (set_attr "length" "6")])
2162 ;; Inverted loads with a 16bit destination.
2166 [(set (match_operand:HI 0 "register_operand" "=&r")
2167 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2168 (match_operand:HI 3 "const_int_operand" "n"))
2170 (match_operand:HI 2 "const_int_operand" "n")))]
2172 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2173 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2174 [(set_attr "cc" "clobber")
2175 (set_attr "length" "8")])
2178 ;; Normal loads with a 32bit destination.
2182 [(set (match_operand:SI 0 "register_operand" "=&r")
2183 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2185 (match_operand 2 "const_int_operand" "n")))]
2187 && INTVAL (operands[2]) < 16"
2188 "* return output_simode_bld (0, operands);"
2189 [(set_attr "cc" "clobber")
2190 (set_attr "length" "6")])
2193 [(set (match_operand:SI 0 "register_operand" "=r")
2194 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2196 (match_operand 2 "const_int_operand" "n")))]
2197 "(TARGET_H8300H || TARGET_H8300S)
2198 && INTVAL (operands[2]) < 16"
2199 "* return output_simode_bld (0, operands);"
2200 [(set_attr "cc" "clobber")
2201 (set_attr "length" "6")])
2204 ;; Inverted loads with a 32bit destination.
2208 [(set (match_operand:SI 0 "register_operand" "=&r")
2209 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2210 (match_operand:HI 3 "const_int_operand" "n"))
2212 (match_operand 2 "const_int_operand" "n")))]
2214 && INTVAL (operands[2]) < 16
2215 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2216 "* return output_simode_bld (1, operands);"
2217 [(set_attr "cc" "clobber")
2218 (set_attr "length" "6")])
2221 [(set (match_operand:SI 0 "register_operand" "=r")
2222 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
2223 (match_operand 3 "const_int_operand" "n"))
2225 (match_operand 2 "const_int_operand" "n")))]
2226 "(TARGET_H8300H || TARGET_H8300S)
2227 && INTVAL (operands[2]) < 16
2228 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2229 "* return output_simode_bld (1, operands);"
2230 [(set_attr "cc" "clobber")
2231 (set_attr "length" "6")])
2233 (define_expand "insv"
2234 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2235 (match_operand:HI 1 "general_operand" "")
2236 (match_operand:HI 2 "general_operand" ""))
2237 (match_operand:HI 3 "general_operand" ""))]
2241 /* We only have single bit bit-field instructions. */
2242 if (INTVAL (operands[1]) != 1)
2245 /* For now, we don't allow memory operands. */
2246 if (GET_CODE (operands[0]) == MEM
2247 || GET_CODE (operands[3]) == MEM)
2252 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2254 (match_operand:HI 1 "immediate_operand" "n"))
2255 (match_operand:HI 2 "register_operand" "r"))]
2257 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2258 [(set_attr "cc" "clobber")
2259 (set_attr "length" "4")])
2261 (define_expand "extzv"
2262 [(set (match_operand:HI 0 "register_operand" "")
2263 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2264 (match_operand:HI 2 "general_operand" "")
2265 (match_operand:HI 3 "general_operand" "")))]
2269 /* We only have single bit bit-field instructions. */
2270 if (INTVAL (operands[2]) != 1)
2273 /* For now, we don't allow memory operands. */
2274 if (GET_CODE (operands[1]) == MEM)
2278 ;; BAND, BOR, and BXOR patterns
2281 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2282 (match_operator:HI 4 "bit_operator"
2283 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2285 (match_operand:HI 2 "immediate_operand" "n"))
2286 (match_operand:HI 3 "bit_operand" "0")]))]
2288 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2289 [(set_attr "cc" "clobber")
2290 (set_attr "length" "6")
2291 (set_attr "adjust_length" "no")])
2294 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2295 (match_operator:HI 5 "bit_operator"
2296 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2298 (match_operand:HI 2 "immediate_operand" "n"))
2299 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2301 (match_operand:HI 4 "immediate_operand" "n"))]))]
2303 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2304 [(set_attr "cc" "clobber")
2305 (set_attr "length" "6")
2306 (set_attr "adjust_length" "no")])
2308 ;; -----------------------------------------------------------------
2310 ;; -----------------------------------------------------------------
2312 (define_insn "*extzv_8_8"
2313 [(set (match_operand:SI 0 "register_operand" "=r")
2314 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2317 "TARGET_H8300H || TARGET_H8300S"
2318 "mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0"
2319 [(set_attr "cc" "set_znv")
2320 (set_attr "length" "6")])
2322 (define_insn "*extzv_8_16"
2323 [(set (match_operand:SI 0 "register_operand" "=r")
2324 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2327 "TARGET_H8300H || TARGET_H8300S"
2328 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2329 [(set_attr "cc" "set_znv")
2330 (set_attr "length" "6")])
2334 (define_insn "*addsi3_lshiftrt_16_zexthi"
2335 [(set (match_operand:SI 0 "register_operand" "=r")
2336 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2338 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
2339 "TARGET_H8300H || TARGET_H8300S"
2340 "add.w\t%e1,%f0\;xor.w\t%e0,%e0\;rotxl.w\t%e0,%e0"
2341 [(set_attr "cc" "clobber")
2342 (set_attr "length" "6")])
2346 (define_insn "*iorhi3_zext"
2347 [(set (match_operand:HI 0 "register_operand" "=r")
2348 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2349 (match_operand:HI 2 "register_operand" "0")))]
2350 "REG_P (operands[0])
2351 && REG_P (operands[1])
2352 && REGNO (operands[0]) != REGNO (operands[1])"
2354 [(set_attr "cc" "clobber")
2355 (set_attr "length" "2")])
2357 (define_insn "*iorhi3_ashift_8"
2358 [(set (match_operand:HI 0 "register_operand" "=r")
2359 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
2361 (match_operand:HI 2 "register_operand" "0")))]
2364 [(set_attr "cc" "clobber")
2365 (set_attr "length" "2")])
2367 (define_insn "*iorhi3_lshiftrt_8"
2368 [(set (match_operand:HI 0 "register_operand" "=r")
2369 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
2371 (match_operand:HI 2 "register_operand" "0")))]
2374 [(set_attr "cc" "clobber")
2375 (set_attr "length" "2")])
2377 (define_insn "*iorhi3_two_qi"
2378 [(set (match_operand:HI 0 "register_operand" "=r")
2379 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2380 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2382 "REG_P (operands[0])
2383 && REG_P (operands[2])
2384 && REGNO (operands[0]) != REGNO (operands[2])"
2386 [(set_attr "cc" "clobber")
2387 (set_attr "length" "2")])
2391 (define_insn "*iorsi3_zexthi"
2392 [(set (match_operand:SI 0 "register_operand" "=r")
2393 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2394 (match_operand:SI 2 "register_operand" "0")))]
2395 "(TARGET_H8300H || TARGET_H8300S)
2396 && REG_P (operands[0])
2397 && REG_P (operands[1])
2398 && (REGNO (operands[0]) != REGNO (operands[1]))"
2400 [(set_attr "cc" "clobber")
2401 (set_attr "length" "2")])
2403 (define_insn "*iorsi3_zextqi"
2404 [(set (match_operand:SI 0 "register_operand" "=r")
2405 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2406 (match_operand:SI 2 "register_operand" "0")))]
2409 [(set_attr "cc" "clobber")
2410 (set_attr "length" "2")])
2414 (define_insn "*xorhi3_zextqi"
2415 [(set (match_operand:HI 0 "register_operand" "=r")
2416 (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2417 (match_operand:HI 2 "register_operand" "0")))]
2418 "REG_P (operands[0])
2419 && REG_P (operands[1])
2420 && REGNO (operands[0]) != REGNO (operands[1])"
2422 [(set_attr "cc" "clobber")
2423 (set_attr "length" "2")])
2427 (define_insn "*xorsi3_zexthi"
2428 [(set (match_operand:SI 0 "register_operand" "=r")
2429 (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2430 (match_operand:SI 2 "register_operand" "0")))]
2431 "(TARGET_H8300H || TARGET_H8300S)
2432 && REG_P (operands[0])
2433 && REG_P (operands[1])
2434 && (REGNO (operands[0]) != REGNO (operands[1]))"
2436 [(set_attr "cc" "clobber")
2437 (set_attr "length" "2")])
2439 (define_insn "*xorsi3_zextqi"
2440 [(set (match_operand:SI 0 "register_operand" "=r")
2441 (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2442 (match_operand:SI 2 "register_operand" "0")))]
2443 "REG_P (operands[0])
2444 && REG_P (operands[1])
2445 && REGNO (operands[0]) != REGNO (operands[1])"
2447 [(set_attr "cc" "clobber")
2448 (set_attr "length" "2")])
2450 (define_insn "*iorsi3_two_hi"
2451 [(set (match_operand:SI 0 "register_operand" "=r")
2452 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2453 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2455 "TARGET_H8300H || TARGET_H8300S"
2457 [(set_attr "cc" "clobber")
2458 (set_attr "length" "2")])
2460 (define_insn "*iorsi3_ashift_16"
2461 [(set (match_operand:SI 0 "register_operand" "=r")
2462 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2464 (match_operand:SI 2 "register_operand" "0")))]
2465 "TARGET_H8300H || TARGET_H8300S"
2467 [(set_attr "cc" "clobber")
2468 (set_attr "length" "2")])
2470 ;; Storing a part of HImode to QImode.
2473 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2474 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
2478 [(set_attr "cc" "set_znv")
2479 (set_attr "length" "8")])
2481 ;; Storing a part of SImode to QImode.
2484 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2485 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2489 [(set_attr "cc" "set_znv")
2490 (set_attr "length" "8")])
2493 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2494 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2496 (clobber (match_scratch:SI 2 "=&r"))]
2497 "TARGET_H8300H || TARGET_H8300S"
2498 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
2499 [(set_attr "cc" "set_znv")
2500 (set_attr "length" "10")])
2503 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2504 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2506 (clobber (match_scratch:SI 2 "=&r"))]
2507 "TARGET_H8300H || TARGET_H8300S"
2508 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
2509 [(set_attr "cc" "set_znv")
2510 (set_attr "length" "10")])
2512 (define_insn_and_split ""
2514 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2518 (label_ref (match_operand 1 "" ""))
2526 (if_then_else (ge (cc0)
2528 (label_ref (match_dup 1))
2532 (define_insn_and_split ""
2534 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2538 (label_ref (match_operand 1 "" ""))
2546 (if_then_else (lt (cc0)
2548 (label_ref (match_dup 1))
2552 ;; -----------------------------------------------------------------
2553 ;; PEEPHOLE PATTERNS
2554 ;; -----------------------------------------------------------------
2556 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
2560 [(set (match_operand:HI 0 "register_operand" "")
2561 (lshiftrt:HI (match_dup 0)
2562 (match_operand:HI 1 "const_int_operand" "")))
2563 (clobber (match_operand:HI 2 "" ""))])
2565 (and:HI (match_dup 0)
2566 (match_operand:HI 3 "const_int_operand" "")))]
2567 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
2569 (and:HI (match_dup 0)
2573 (lshiftrt:HI (match_dup 0)
2575 (clobber (match_dup 2))])]
2578 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
2582 [(set (match_operand:HI 0 "register_operand" "")
2583 (ashift:HI (match_dup 0)
2584 (match_operand:HI 1 "const_int_operand" "")))
2585 (clobber (match_operand:HI 2 "" ""))])
2587 (and:HI (match_dup 0)
2588 (match_operand:HI 3 "const_int_operand" "")))]
2589 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
2591 (and:HI (match_dup 0)
2595 (ashift:HI (match_dup 0)
2597 (clobber (match_dup 2))])]
2600 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
2604 [(set (match_operand:SI 0 "register_operand" "")
2605 (lshiftrt:SI (match_dup 0)
2606 (match_operand:SI 1 "const_int_operand" "")))
2607 (clobber (match_operand:SI 2 "" ""))])
2609 (and:SI (match_dup 0)
2610 (match_operand:SI 3 "const_int_operand" "")))]
2611 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
2613 (and:SI (match_dup 0)
2617 (lshiftrt:SI (match_dup 0)
2619 (clobber (match_dup 2))])]
2622 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
2626 [(set (match_operand:SI 0 "register_operand" "")
2627 (ashift:SI (match_dup 0)
2628 (match_operand:SI 1 "const_int_operand" "")))
2629 (clobber (match_operand:SI 2 "" ""))])
2631 (and:SI (match_dup 0)
2632 (match_operand:SI 3 "const_int_operand" "")))]
2633 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
2635 (and:SI (match_dup 0)
2639 (ashift:SI (match_dup 0)
2641 (clobber (match_dup 2))])]
2644 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
2648 [(set (match_operand:SI 0 "register_operand" "")
2649 (lshiftrt:SI (match_dup 0)
2650 (match_operand:SI 1 "const_int_operand" "")))
2651 (clobber (match_operand:SI 2 "" ""))])
2653 (and:SI (match_dup 0)
2654 (match_operand:SI 3 "const_int_operand" "")))]
2655 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
2657 (and:SI (match_dup 0)
2661 (lshiftrt:SI (match_dup 0)
2663 (clobber (match_dup 2))])]
2666 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
2670 [(set (match_operand:SI 0 "register_operand" "")
2671 (ashift:SI (match_dup 0)
2672 (match_operand:SI 1 "const_int_operand" "")))
2673 (clobber (match_operand:SI 2 "" ""))])
2675 (and:SI (match_dup 0)
2676 (match_operand:SI 3 "const_int_operand" "")))]
2677 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
2679 (and:SI (match_dup 0)
2683 (ashift:SI (match_dup 0)
2685 (clobber (match_dup 2))])]
2688 ;; Convert a QImode push into an SImode push so that the
2689 ;; define_peephole2 below can cram multiple pushes into one stm.l.
2692 [(parallel [(set (reg:SI SP_REG)
2693 (plus:SI (reg:SI SP_REG) (const_int -4)))
2694 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
2695 (match_operand:QI 0 "register_operand" ""))])]
2697 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2699 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
2701 ;; Convert a HImode push into an SImode push so that the
2702 ;; define_peephole2 below can cram multiple pushes into one stm.l.
2705 [(parallel [(set (reg:SI SP_REG)
2706 (plus:SI (reg:SI SP_REG) (const_int -4)))
2707 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
2708 (match_operand:HI 0 "register_operand" ""))])]
2710 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2712 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
2714 ;; Cram four pushes into stm.l.
2717 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2718 (match_operand:SI 0 "register_operand" ""))
2719 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2720 (match_operand:SI 1 "register_operand" ""))
2721 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2722 (match_operand:SI 2 "register_operand" ""))
2723 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2724 (match_operand:SI 3 "register_operand" ""))]
2726 && REGNO (operands[0]) == 0
2727 && REGNO (operands[1]) == 1
2728 && REGNO (operands[2]) == 2
2729 && REGNO (operands[3]) == 3"
2730 [(parallel [(set (reg:SI SP_REG)
2731 (plus:SI (reg:SI SP_REG)
2733 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2735 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2737 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2739 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
2743 ;; Cram three pushes into stm.l.
2746 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2747 (match_operand:SI 0 "register_operand" ""))
2748 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2749 (match_operand:SI 1 "register_operand" ""))
2750 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2751 (match_operand:SI 2 "register_operand" ""))]
2753 && ((REGNO (operands[0]) == 0
2754 && REGNO (operands[1]) == 1
2755 && REGNO (operands[2]) == 2)
2756 || (REGNO (operands[0]) == 4
2757 && REGNO (operands[1]) == 5
2758 && REGNO (operands[2]) == 6))"
2759 [(parallel [(set (reg:SI SP_REG)
2760 (plus:SI (reg:SI SP_REG)
2762 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2764 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2766 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2770 ;; Cram two pushes into stm.l.
2773 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2774 (match_operand:SI 0 "register_operand" ""))
2775 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2776 (match_operand:SI 1 "register_operand" ""))]
2778 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2779 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2780 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2781 [(parallel [(set (reg:SI SP_REG)
2782 (plus:SI (reg:SI SP_REG)
2784 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2786 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2793 ;; add.w r7,r0 (6 bytes)
2798 ;; adds #2,r0 (4 bytes)
2801 [(set (match_operand:HI 0 "register_operand" "")
2802 (match_operand:HI 1 "const_int_operand" ""))
2804 (plus:HI (match_dup 0)
2805 (match_operand:HI 2 "register_operand" "")))]
2806 "REG_P (operands[0]) && REG_P (operands[2])
2807 && REGNO (operands[0]) != REGNO (operands[2])
2808 && (CONST_OK_FOR_J (INTVAL (operands[1]))
2809 || CONST_OK_FOR_L (INTVAL (operands[1]))
2810 || CONST_OK_FOR_N (INTVAL (operands[1])))"
2814 (plus:HI (match_dup 0)
2822 ;; add.l er7,er0 (6 bytes)
2827 ;; adds #4,er0 (4 bytes)
2830 [(set (match_operand:SI 0 "register_operand" "")
2831 (match_operand:SI 1 "const_int_operand" ""))
2833 (plus:SI (match_dup 0)
2834 (match_operand:SI 2 "register_operand" "")))]
2835 "(TARGET_H8300H || TARGET_H8300S)
2836 && REG_P (operands[0]) && REG_P (operands[2])
2837 && REGNO (operands[0]) != REGNO (operands[2])
2838 && (CONST_OK_FOR_L (INTVAL (operands[1]))
2839 || CONST_OK_FOR_N (INTVAL (operands[1])))"
2843 (plus:SI (match_dup 0)
2850 ;; add.l #10,er0 (takes 8 bytes)
2856 ;; add.l er7,er0 (takes 6 bytes)
2859 [(set (match_operand:SI 0 "register_operand" "")
2860 (match_operand:SI 1 "register_operand" ""))
2862 (plus:SI (match_dup 0)
2863 (match_operand:SI 2 "const_int_operand" "")))]
2864 "(TARGET_H8300H || TARGET_H8300S)
2865 && REG_P (operands[0]) && REG_P (operands[1])
2866 && REGNO (operands[0]) != REGNO (operands[1])
2867 && !CONST_OK_FOR_L (INTVAL (operands[2]))
2868 && !CONST_OK_FOR_N (INTVAL (operands[2]))
2869 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
2870 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
2871 || INTVAL (operands[2]) == 0xffff
2872 || INTVAL (operands[2]) == 0xfffe)"
2876 (plus:SI (match_dup 0)
2892 [(set (match_operand:HI 0 "register_operand" "")
2893 (plus:HI (match_dup 0)
2894 (match_operand 1 "incdec_operand" "")))
2898 (if_then_else (match_operator 3 "eqne_operator"
2899 [(cc0) (const_int 0)])
2900 (label_ref (match_operand 2 "" ""))
2902 "TARGET_H8300H || TARGET_H8300S"
2903 [(set (match_operand:HI 0 "register_operand" "")
2904 (unspec:HI [(match_dup 0)
2910 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
2911 (label_ref (match_dup 2))
2915 ;; The SImode version of the previous pattern.
2918 [(set (match_operand:SI 0 "register_operand" "")
2919 (plus:SI (match_dup 0)
2920 (match_operand 1 "incdec_operand" "")))
2924 (if_then_else (match_operator 3 "eqne_operator"
2925 [(cc0) (const_int 0)])
2926 (label_ref (match_operand 2 "" ""))
2928 "TARGET_H8300H || TARGET_H8300S"
2929 [(set (match_operand:SI 0 "register_operand" "")
2930 (unspec:SI [(match_dup 0)
2936 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
2937 (label_ref (match_dup 2))
2941 ;; For a small constant, it is cheaper to actually do the subtraction
2942 ;; and then test the register.
2946 (compare:HI (match_operand:HI 0 "register_operand" "")
2947 (match_operand:HI 1 "const_int_le_2_operand" "")))
2949 (if_then_else (match_operator 3 "eqne_operator"
2950 [(cc0) (const_int 0)])
2951 (label_ref (match_operand 2 "" ""))
2953 "(TARGET_H8300H || TARGET_H8300S)
2954 && find_regno_note (insn, REG_DEAD, REGNO (operands[0]))"
2958 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
2959 (label_ref (match_dup 2))
2961 "operands[1] = GEN_INT (- INTVAL (operands[1]));
2962 split_adds_subs (HImode, operands, 1);")
2964 ;; The SImode version of the previous pattern.
2968 (compare:SI (match_operand:SI 0 "register_operand" "")
2969 (match_operand:SI 1 "const_int_le_6_operand" "")))
2971 (if_then_else (match_operator 3 "eqne_operator"
2972 [(cc0) (const_int 0)])
2973 (label_ref (match_operand 2 "" ""))
2975 "(TARGET_H8300H || TARGET_H8300S)
2976 && find_regno_note (insn, REG_DEAD, REGNO (operands[0]))"
2980 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
2981 (label_ref (match_dup 2))
2983 "operands[1] = GEN_INT (- INTVAL (operands[1]));
2984 split_adds_subs (SImode, operands, 1);")
2986 ;; Narrow the mode of testing if possible.
2989 [(set (match_operand:HI 0 "register_operand" "")
2990 (and:HI (match_dup 0)
2991 (match_operand:HI 1 "const_int_qi_operand" "")))
2995 (if_then_else (match_operator 3 "eqne_operator"
2996 [(cc0) (const_int 0)])
2997 (label_ref (match_operand 2 "" ""))
2999 "find_regno_note (next_nonnote_insn (insn), REG_DEAD, REGNO (operands[0]))"
3001 (and:QI (match_dup 4)
3006 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3007 (label_ref (match_dup 2))
3009 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
3010 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));")
3013 [(set (match_operand:SI 0 "register_operand" "")
3014 (and:SI (match_dup 0)
3015 (match_operand:SI 1 "const_int_qi_operand" "")))
3019 (if_then_else (match_operator 3 "eqne_operator"
3020 [(cc0) (const_int 0)])
3021 (label_ref (match_operand 2 "" ""))
3023 "find_regno_note (next_nonnote_insn (insn), REG_DEAD, REGNO (operands[0]))"
3025 (and:QI (match_dup 4)
3030 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3031 (label_ref (match_dup 2))
3033 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
3034 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), QImode));")
3037 [(set (match_operand:SI 0 "register_operand" "")
3038 (and:SI (match_dup 0)
3039 (match_operand:SI 1 "const_int_hi_operand" "")))
3043 (if_then_else (match_operator 3 "eqne_operator"
3044 [(cc0) (const_int 0)])
3045 (label_ref (match_operand 2 "" ""))
3047 "find_regno_note (next_nonnote_insn (insn), REG_DEAD, REGNO (operands[0]))"
3049 (and:HI (match_dup 4)
3054 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
3055 (label_ref (match_dup 2))
3057 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
3058 operands[5] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), HImode));")