1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have an insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
61 ;; ----------------------------------------------------------------------
63 ;; ----------------------------------------------------------------------
65 (define_attr "cpu" "h8300,h8300h"
66 (const (symbol_ref "cpu_type")))
68 (define_attr "type" "branch,arith"
69 (const_string "arith"))
71 ;; The size of instructions in bytes.
73 (define_attr "length" ""
74 (cond [(eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
77 (le (minus (match_dup 0) (pc))
80 (if_then_else (and (eq_attr "cpu" "h8300h")
81 (and (ge (minus (pc) (match_dup 0))
83 (le (minus (pc) (match_dup 0))
89 ;; The necessity of instruction length adjustment.
91 (define_attr "adjust_length" "yes,no"
92 (cond [(eq_attr "type" "branch") (const_string "no")]
93 (const_string "yes")))
95 ;; Condition code settings.
97 ;; none - insn does not affect cc
98 ;; none_0hit - insn does not affect cc but it does modify operand 0
99 ;; This attribute is used to keep track of when operand 0 changes.
100 ;; See the description of NOTICE_UPDATE_CC for more info.
101 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
102 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
103 ;; compare - compare instruction
104 ;; clobber - value of cc is unknown
106 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
107 (const_string "clobber"))
109 ;; ----------------------------------------------------------------------
111 ;; ----------------------------------------------------------------------
115 (define_insn "pushqi1_h8300"
116 [(parallel [(set (reg:HI SP_REG)
117 (plus:HI (reg:HI SP_REG) (const_int -2)))
118 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
119 (match_operand:QI 0 "register_operand" "r"))])]
122 [(set_attr "length" "2")
123 (set_attr "cc" "clobber")])
125 (define_insn "pushqi1_h8300hs"
126 [(parallel [(set (reg:SI SP_REG)
127 (plus:SI (reg:SI SP_REG) (const_int -4)))
128 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
129 (match_operand:QI 0 "register_operand" "r"))])]
130 "TARGET_H8300H || TARGET_H8300S"
132 [(set_attr "length" "4")
133 (set_attr "cc" "clobber")])
135 (define_expand "pushqi1"
136 [(use (match_operand:QI 0 "register_operand" ""))]
141 emit_insn (gen_pushqi1_h8300 (operands[0]));
143 emit_insn (gen_pushqi1_h8300hs (operands[0]));
148 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
149 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
151 && (register_operand (operands[0], QImode)
152 || register_operand (operands[1], QImode))"
160 [(set_attr "length" "2,2,2,2,4,4")
161 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
164 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
165 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
166 "(TARGET_H8300H || TARGET_H8300S)
167 && (register_operand (operands[0], QImode)
168 || register_operand (operands[1], QImode))"
176 [(set_attr "length" "2,2,2,2,8,8")
177 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
179 (define_expand "movqi"
180 [(set (match_operand:QI 0 "general_operand_dst" "")
181 (match_operand:QI 1 "general_operand_src" ""))]
185 /* One of the ops has to be in a register. */
186 if (!register_operand (operand0, QImode)
187 && !register_operand (operand1, QImode))
189 operands[1] = copy_to_mode_reg (QImode, operand1);
193 (define_insn "movstrictqi"
194 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
195 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
202 [(set_attr_alternative "length"
203 [(const_int 2) (const_int 2) (const_int 2)
204 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
205 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
209 (define_expand "pushhi1_h8300"
210 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
211 (match_operand:HI 0 "register_operand" ""))]
215 (define_insn "pushhi1_h8300hs"
216 [(parallel [(set (reg:SI SP_REG)
217 (plus:SI (reg:SI SP_REG) (const_int -4)))
218 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
219 (match_operand:HI 0 "register_operand" "r"))])]
220 "TARGET_H8300H || TARGET_H8300S"
222 [(set_attr "length" "4")
223 (set_attr "cc" "clobber")])
225 (define_expand "pushhi1"
226 [(use (match_operand:HI 0 "register_operand" ""))]
231 emit_insn (gen_pushhi1_h8300 (operands[0]));
233 emit_insn (gen_pushhi1_h8300hs (operands[0]));
238 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
239 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
241 && (register_operand (operands[0], HImode)
242 || register_operand (operands[1], HImode))
243 && !(GET_CODE (operands[0]) == MEM
244 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
245 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
246 && GET_CODE (operands[1]) == REG
247 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
255 [(set_attr "length" "2,2,2,4,4,4")
256 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
259 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
260 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
261 "(TARGET_H8300H || TARGET_H8300S)
262 && (register_operand (operands[0], HImode)
263 || register_operand (operands[1], HImode))"
271 [(set_attr "length" "2,2,2,4,8,8")
272 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
274 (define_expand "movhi"
275 [(set (match_operand:HI 0 "general_operand_dst" "")
276 (match_operand:HI 1 "general_operand_src" ""))]
280 /* One of the ops has to be in a register. */
281 if (!register_operand (operand1, HImode)
282 && !register_operand (operand0, HImode))
284 operands[1] = copy_to_mode_reg (HImode, operand1);
288 (define_insn "movstricthi"
289 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
290 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
297 [(set_attr_alternative "length"
298 [(const_int 2) (const_int 2) (const_int 4)
299 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
300 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
304 (define_expand "movsi"
305 [(set (match_operand:SI 0 "general_operand_dst" "")
306 (match_operand:SI 1 "general_operand_src" ""))]
312 if (do_movsi (operands))
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, SImode)
319 && !register_operand (operand0, SImode))
321 operands[1] = copy_to_mode_reg (SImode, operand1);
326 (define_expand "movsf"
327 [(set (match_operand:SF 0 "general_operand_dst" "")
328 (match_operand:SF 1 "general_operand_src" ""))]
334 if (do_movsi (operands))
339 /* One of the ops has to be in a register. */
340 if (!register_operand (operand1, SFmode)
341 && !register_operand (operand0, SFmode))
343 operands[1] = copy_to_mode_reg (SFmode, operand1);
348 (define_insn "movsi_h8300"
349 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
350 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
352 && (register_operand (operands[0], SImode)
353 || register_operand (operands[1], SImode))"
357 switch (which_alternative)
360 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
362 if (REGNO (operands[0]) < REGNO (operands[1]))
363 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
365 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
367 /* Make sure we don't trample the register we index with. */
368 if (GET_CODE (operands[1]) == MEM)
370 rtx inside = XEXP (operands[1], 0);
375 else if (GET_CODE (inside) == PLUS)
377 rtx lhs = XEXP (inside, 0);
378 rtx rhs = XEXP (inside, 1);
379 if (REG_P (lhs)) rn = REGNO (lhs);
380 if (REG_P (rhs)) rn = REGNO (rhs);
383 if (rn == REGNO (operands[0]))
385 /* Move the second word first. */
386 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
390 /* See if either half is zero. If so, use sub.w to clear
392 if (GET_CODE (operands[1]) == CONST_INT)
394 if ((INTVAL (operands[1]) & 0xffff) == 0)
395 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
396 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
397 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
399 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
402 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
404 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
406 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
411 [(set_attr "length" "4,4,8,8,4,4")
412 (set_attr "cc" "clobber")])
414 (define_insn "movsf_h8300"
415 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
416 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
418 && (register_operand (operands[0], SFmode)
419 || register_operand (operands[1], SFmode))"
422 /* Copy of the movsi stuff. */
424 switch (which_alternative)
427 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
429 if (REGNO (operands[0]) < REGNO (operands[1]))
430 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
432 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
434 /* Make sure we don't trample the register we index with. */
435 if (GET_CODE (operands[1]) == MEM)
437 rtx inside = XEXP (operands[1], 0);
442 else if (GET_CODE (inside) == PLUS)
444 rtx lhs = XEXP (inside, 0);
445 rtx rhs = XEXP (inside, 1);
446 if (REG_P (lhs)) rn = REGNO (lhs);
447 if (REG_P (rhs)) rn = REGNO (rhs);
450 if (rn == REGNO (operands[0]))
451 /* Move the second word first. */
452 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
454 /* Move the first word first. */
455 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
458 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
460 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
462 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
467 [(set_attr "length" "4,4,8,8,4,4")
468 (set_attr "cc" "clobber")])
470 (define_insn "movsi_h8300hs"
471 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
472 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
473 "(TARGET_H8300S || TARGET_H8300H)
474 && (register_operand (operands[0], SImode)
475 || register_operand (operands[1], SImode))
476 && !(GET_CODE (operands[0]) == MEM
477 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
478 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
479 && GET_CODE (operands[1]) == REG
480 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
483 switch (which_alternative)
486 return \"sub.l %S0,%S0\";
490 return \"clrmac\;ldmac %1,macl\";
492 return \"stmac macl,%0\";
494 if (GET_CODE (operands[1]) == CONST_INT)
496 int val = INTVAL (operands[1]);
498 /* Look for constants which can be made by adding an 8-bit
499 number to zero in one of the two low bytes. */
500 if (val == (val & 0xff))
502 operands[1] = GEN_INT ((char) val & 0xff);
503 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
506 if (val == (val & 0xff00))
508 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
509 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
512 /* Look for constants that can be obtained by subs, inc, and
514 switch (val & 0xffffffff)
517 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
519 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
521 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
524 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
526 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
529 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
531 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
534 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
536 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
540 return \"mov.l %S1,%S0\";
542 [(set_attr "length" "2,2,6,4,4,10,10,2,6,4")
543 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
545 (define_insn "movsf_h8300h"
546 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
547 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
548 "(TARGET_H8300H || TARGET_H8300S)
549 && (register_operand (operands[0], SFmode)
550 || register_operand (operands[1], SFmode))"
558 [(set_attr "length" "2,2,10,10,4,4")
559 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
561 ;; ----------------------------------------------------------------------
563 ;; ----------------------------------------------------------------------
566 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
568 (match_operand 1 "const_int_operand" "n,n")))]
571 [(set_attr "length" "2,4")
572 (set_attr "cc" "set_zn,set_zn")])
575 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
577 (match_operand 1 "const_int_operand" "n")))]
580 [(set_attr "length" "2")
581 (set_attr "cc" "set_zn")])
583 (define_insn "*tst_extzv_bitqi_1_n"
584 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_operand" "r,U")
586 (match_operand 1 "const_int_operand" "n,n")))]
587 "(TARGET_H8300H || TARGET_H8300S)
588 && INTVAL (operands[1]) != 7"
590 [(set_attr "length" "2,8")
591 (set_attr "cc" "set_zn,set_zn")])
593 (define_insn_and_split "*tst_extzv_memqi_1_n"
594 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
596 (match_operand 1 "const_int_operand" "n")))
597 (clobber (match_scratch:QI 2 "=&r"))]
598 "(TARGET_H8300H || TARGET_H8300S)
599 && !EXTRA_CONSTRAINT (operands[0], 'U')
600 && INTVAL (operands[1]) != 7"
602 "&& reload_completed"
605 (set (cc0) (zero_extract:SI (match_dup 2)
611 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
613 (match_operand 1 "const_int_operand" "n")))]
614 "(TARGET_H8300H || TARGET_H8300S)
615 && INTVAL (operands[1]) <= 15"
617 [(set_attr "length" "2")
618 (set_attr "cc" "set_zn")])
622 (and:HI (match_operand:HI 0 "register_operand" "r")
623 (match_operand:HI 1 "single_one_operand" "n")))]
627 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
628 if (INTVAL (operands[1]) > 128)
630 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
631 return \"btst\\t%V1,%t0\";
633 return \"btst\\t%V1,%s0\";
635 [(set_attr "length" "2")
636 (set_attr "cc" "set_zn")])
640 (and:SI (match_operand:SI 0 "register_operand" "r")
641 (match_operand:SI 1 "single_one_operand" "n")))]
642 "(TARGET_H8300H || TARGET_H8300S)
643 && (INTVAL (operands[1]) & 0xffff) != 0"
646 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
647 if (INTVAL (operands[1]) > 128)
649 operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
650 return \"btst\\t%V1,%x0\";
652 return \"btst\\t%V1,%w0\";
654 [(set_attr "length" "2")
655 (set_attr "cc" "set_zn")])
658 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
661 [(set_attr "length" "2")
662 (set_attr "cc" "set_znv")])
665 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
668 [(set_attr "length" "2")
669 (set_attr "cc" "set_znv")])
673 (and:HI (match_operand:HI 0 "register_operand" "r")
677 [(set_attr "length" "2")
678 (set_attr "cc" "set_znv")])
681 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
682 "TARGET_H8300H || TARGET_H8300S"
684 [(set_attr "length" "2")
685 (set_attr "cc" "set_znv")])
689 (and:SI (match_operand:SI 0 "register_operand" "r")
690 (const_int -65536)))]
693 [(set_attr "length" "2")
694 (set_attr "cc" "set_znv")])
698 (compare:QI (match_operand:QI 0 "register_operand" "r")
699 (match_operand:QI 1 "nonmemory_operand" "rn")))]
702 [(set_attr "length" "2")
703 (set_attr "cc" "compare")])
705 (define_expand "cmphi"
707 (compare:HI (match_operand:HI 0 "register_operand" "")
708 (match_operand:HI 1 "nonmemory_operand" "")))]
712 /* Force operand1 into a register if we're compiling
714 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
715 operands[1] = force_reg (HImode, operands[1]);
720 (compare:HI (match_operand:HI 0 "register_operand" "r")
721 (match_operand:HI 1 "register_operand" "r")))]
724 [(set_attr "length" "2")
725 (set_attr "cc" "compare")])
729 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
730 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
731 "TARGET_H8300H || TARGET_H8300S"
733 [(set_attr "length" "2,4")
734 (set_attr "cc" "compare,compare")])
738 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
739 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
740 "TARGET_H8300H || TARGET_H8300S"
742 [(set_attr "length" "2,6")
743 (set_attr "cc" "compare,compare")])
745 ;; ----------------------------------------------------------------------
747 ;; ----------------------------------------------------------------------
749 (define_insn "addqi3"
750 [(set (match_operand:QI 0 "register_operand" "=r")
751 (plus:QI (match_operand:QI 1 "register_operand" "%0")
752 (match_operand:QI 2 "nonmemory_operand" "rn")))]
755 [(set_attr "length" "2")
756 (set_attr "cc" "set_zn")])
758 (define_expand "addhi3"
759 [(set (match_operand:HI 0 "register_operand" "")
760 (plus:HI (match_operand:HI 1 "register_operand" "")
761 (match_operand:HI 2 "nonmemory_operand" "")))]
766 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
767 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
768 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
773 add.b %s2,%s0\;addx %t2,%t0
775 mov.w %T1,%T0\;add.w %T2,%T0"
776 [(set_attr "length" "2,2,4,2,6")
777 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
780 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
781 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
782 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
783 "TARGET_H8300H || TARGET_H8300S"
789 [(set_attr "length" "2,2,4,2")
790 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
793 [(set (match_operand:HI 0 "register_operand" "")
794 (plus:HI (match_dup 0)
795 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
798 "split_adds_subs (HImode, operands); DONE;")
800 (define_expand "addsi3"
801 [(set (match_operand:SI 0 "register_operand" "")
802 (plus:SI (match_operand:SI 1 "register_operand" "")
803 (match_operand:SI 2 "nonmemory_operand" "")))]
807 (define_insn "addsi_h8300"
808 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
809 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
810 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
813 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
814 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
815 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
816 [(set_attr "length" "8,6,10")
817 (set_attr "cc" "clobber")])
819 (define_insn "addsi_h8300h"
820 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
821 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
822 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
823 "TARGET_H8300H || TARGET_H8300S"
829 [(set_attr "length" "2,2,6,2")
830 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
833 [(set (match_operand:SI 0 "register_operand" "")
834 (plus:SI (match_dup 0)
835 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
836 "TARGET_H8300H || TARGET_H8300S"
838 "split_adds_subs (SImode, operands); DONE;")
840 ;; ----------------------------------------------------------------------
841 ;; SUBTRACT INSTRUCTIONS
842 ;; ----------------------------------------------------------------------
844 (define_insn "subqi3"
845 [(set (match_operand:QI 0 "register_operand" "=r")
846 (minus:QI (match_operand:QI 1 "register_operand" "0")
847 (match_operand:QI 2 "register_operand" "r")))]
850 [(set_attr "length" "2")
851 (set_attr "cc" "set_zn")])
853 (define_expand "subhi3"
854 [(set (match_operand:HI 0 "register_operand" "")
855 (minus:HI (match_operand:HI 1 "general_operand" "")
856 (match_operand:HI 2 "nonmemory_operand" "")))]
861 [(set (match_operand:HI 0 "register_operand" "=r,&r")
862 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
863 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
867 add.b %E2,%s0\;addx %F2,%t0"
868 [(set_attr "length" "2,4")
869 (set_attr "cc" "set_zn,clobber")])
872 [(set (match_operand:HI 0 "register_operand" "=r,&r")
873 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
874 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
875 "TARGET_H8300H || TARGET_H8300S"
879 [(set_attr "length" "2,4")
880 (set_attr "cc" "set_zn,set_zn")])
882 (define_expand "subsi3"
883 [(set (match_operand:SI 0 "register_operand" "")
884 (minus:SI (match_operand:SI 1 "register_operand" "")
885 (match_operand:SI 2 "nonmemory_operand" "")))]
889 (define_insn "subsi3_h8300"
890 [(set (match_operand:SI 0 "register_operand" "=r")
891 (minus:SI (match_operand:SI 1 "register_operand" "0")
892 (match_operand:SI 2 "register_operand" "r")))]
894 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
895 [(set_attr "length" "6")
896 (set_attr "cc" "clobber")])
898 (define_insn "subsi3_h8300h"
899 [(set (match_operand:SI 0 "register_operand" "=r,r")
900 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
901 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
902 "TARGET_H8300H || TARGET_H8300S"
906 [(set_attr "length" "2,6")
907 (set_attr "cc" "set_zn,set_zn")])
909 ;; ----------------------------------------------------------------------
910 ;; MULTIPLY INSTRUCTIONS
911 ;; ----------------------------------------------------------------------
913 ;; Note that the H8/300 can only handle umulqihi3.
915 (define_insn "mulqihi3"
916 [(set (match_operand:HI 0 "register_operand" "=r")
917 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
918 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
919 "TARGET_H8300H || TARGET_H8300S"
921 [(set_attr "length" "4")
922 (set_attr "cc" "set_zn")])
924 (define_insn "mulhisi3"
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
927 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
928 "TARGET_H8300H || TARGET_H8300S"
930 [(set_attr "length" "4")
931 (set_attr "cc" "set_zn")])
933 (define_insn "umulqihi3"
934 [(set (match_operand:HI 0 "register_operand" "=r")
935 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
936 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
939 [(set_attr "length" "2")
940 (set_attr "cc" "none_0hit")])
942 (define_insn "umulhisi3"
943 [(set (match_operand:SI 0 "register_operand" "=r")
944 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
945 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
946 "TARGET_H8300H || TARGET_H8300S"
948 [(set_attr "length" "2")
949 (set_attr "cc" "none_0hit")])
951 ;; This is a "bridge" instruction. Combine can't cram enough insns
952 ;; together to crate a MAC instruction directly, but it can create
953 ;; this instruction, which then allows combine to create the real
956 ;; Unfortunately, if combine doesn't create a MAC instruction, this
957 ;; insn must generate reasonably correct code. Egad.
959 [(set (match_operand:SI 0 "register_operand" "=a")
962 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
964 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
966 "clrmac\;mac @%2+,@%1+"
967 [(set_attr "length" "6")
968 (set_attr "cc" "none_0hit")])
971 [(set (match_operand:SI 0 "register_operand" "=a")
973 (sign_extend:SI (mem:HI
974 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
975 (sign_extend:SI (mem:HI
976 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
977 (match_operand:SI 3 "register_operand" "0")))]
980 [(set_attr "length" "4")
981 (set_attr "cc" "none_0hit")])
983 ;; ----------------------------------------------------------------------
984 ;; DIVIDE/MOD INSTRUCTIONS
985 ;; ----------------------------------------------------------------------
987 (define_insn "udivmodqi4"
988 [(set (match_operand:QI 0 "register_operand" "=r")
991 (match_operand:HI 1 "register_operand" "0")
992 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
993 (set (match_operand:QI 3 "register_operand" "=r")
997 (zero_extend:HI (match_dup 2)))))]
1001 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1002 return \"divxu.b\\t%X2,%T0\";
1004 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1006 [(set_attr "length" "4")
1007 (set_attr "cc" "clobber")])
1009 (define_insn "divmodqi4"
1010 [(set (match_operand:QI 0 "register_operand" "=r")
1013 (match_operand:HI 1 "register_operand" "0")
1014 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1015 (set (match_operand:QI 3 "register_operand" "=r")
1019 (sign_extend:HI (match_dup 2)))))]
1020 "TARGET_H8300H || TARGET_H8300S"
1023 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1024 return \"divxs.b\\t%X2,%T0\";
1026 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1028 [(set_attr "length" "6")
1029 (set_attr "cc" "clobber")])
1031 (define_insn "udivmodhi4"
1032 [(set (match_operand:HI 0 "register_operand" "=r")
1035 (match_operand:SI 1 "register_operand" "0")
1036 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1037 (set (match_operand:HI 3 "register_operand" "=r")
1041 (zero_extend:SI (match_dup 2)))))]
1042 "TARGET_H8300H || TARGET_H8300S"
1045 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1046 return \"divxu.w\\t%T2,%S0\";
1048 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1050 [(set_attr "length" "4")
1051 (set_attr "cc" "clobber")])
1053 (define_insn "divmodhi4"
1054 [(set (match_operand:HI 0 "register_operand" "=r")
1057 (match_operand:SI 1 "register_operand" "0")
1058 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1059 (set (match_operand:HI 3 "register_operand" "=r")
1063 (sign_extend:SI (match_dup 2)))))]
1064 "TARGET_H8300H || TARGET_H8300S"
1067 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1068 return \"divxs.w\\t%T2,%S0\";
1070 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1072 [(set_attr "length" "6")
1073 (set_attr "cc" "clobber")])
1075 ;; ----------------------------------------------------------------------
1077 ;; ----------------------------------------------------------------------
1080 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1081 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1082 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1083 "register_operand (operands[0], QImode)
1084 || single_zero_operand (operands[2], QImode)"
1088 [(set_attr "length" "2,8")
1089 (set_attr "adjust_length" "no")
1090 (set_attr "cc" "set_znv,none_0hit")])
1092 (define_expand "andqi3"
1093 [(set (match_operand:QI 0 "bit_operand" "")
1094 (and:QI (match_operand:QI 1 "bit_operand" "")
1095 (match_operand:QI 2 "nonmemory_operand" "")))]
1099 if (fix_bit_operand (operands, 0, AND))
1103 (define_expand "andhi3"
1104 [(set (match_operand:HI 0 "register_operand" "")
1105 (and:HI (match_operand:HI 1 "register_operand" "")
1106 (match_operand:HI 2 "nonmemory_operand" "")))]
1110 (define_insn "*andorqi3"
1111 [(set (match_operand:QI 0 "register_operand" "=r")
1112 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1113 (match_operand:QI 3 "single_one_operand" "n"))
1114 (match_operand:QI 1 "register_operand" "0")))]
1116 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1117 [(set_attr "length" "6")
1118 (set_attr "cc" "clobber")])
1120 (define_insn "*andorhi3"
1121 [(set (match_operand:HI 0 "register_operand" "=r")
1122 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1123 (match_operand:HI 3 "single_one_operand" "n"))
1124 (match_operand:HI 1 "register_operand" "0")))]
1128 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1129 if (INTVAL (operands[3]) > 128)
1131 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1132 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1134 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1136 [(set_attr "length" "6")
1137 (set_attr "cc" "clobber")])
1139 (define_insn "*andorsi3"
1140 [(set (match_operand:SI 0 "register_operand" "=r")
1141 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1142 (match_operand:SI 3 "single_one_operand" "n"))
1143 (match_operand:SI 1 "register_operand" "0")))]
1144 "(INTVAL (operands[3]) & 0xffff) != 0"
1147 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1148 if (INTVAL (operands[3]) > 128)
1150 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1151 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1153 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1155 [(set_attr "length" "6")
1156 (set_attr "cc" "clobber")])
1158 (define_insn "*andorsi3_shift_8"
1159 [(set (match_operand:SI 0 "register_operand" "=r")
1160 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1163 (match_operand:SI 1 "register_operand" "0")))]
1166 [(set_attr "length" "2")
1167 (set_attr "cc" "clobber")])
1169 (define_expand "andsi3"
1170 [(set (match_operand:SI 0 "register_operand" "")
1171 (and:SI (match_operand:SI 1 "register_operand" "")
1172 (match_operand:SI 2 "nonmemory_operand" "")))]
1176 ;; ----------------------------------------------------------------------
1178 ;; ----------------------------------------------------------------------
1181 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1182 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1183 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1184 "register_operand (operands[0], QImode)
1185 || single_one_operand (operands[2], QImode)"
1189 [(set_attr "length" "2,8")
1190 (set_attr "adjust_length" "no")
1191 (set_attr "cc" "set_znv,none_0hit")])
1193 (define_expand "iorqi3"
1194 [(set (match_operand:QI 0 "bit_operand" "")
1195 (ior:QI (match_operand:QI 1 "bit_operand" "")
1196 (match_operand:QI 2 "nonmemory_operand" "")))]
1200 if (fix_bit_operand (operands, 1, IOR))
1204 (define_expand "iorhi3"
1205 [(set (match_operand:HI 0 "register_operand" "")
1206 (ior:HI (match_operand:HI 1 "register_operand" "")
1207 (match_operand:HI 2 "nonmemory_operand" "")))]
1211 (define_expand "iorsi3"
1212 [(set (match_operand:SI 0 "register_operand" "")
1213 (ior:SI (match_operand:SI 1 "register_operand" "")
1214 (match_operand:SI 2 "nonmemory_operand" "")))]
1218 ;; ----------------------------------------------------------------------
1220 ;; ----------------------------------------------------------------------
1223 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1224 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1225 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1226 "register_operand (operands[0], QImode)
1227 || single_one_operand (operands[2], QImode)"
1231 [(set_attr "length" "2,8")
1232 (set_attr "adjust_length" "no")
1233 (set_attr "cc" "set_znv,none_0hit")])
1235 (define_expand "xorqi3"
1236 [(set (match_operand:QI 0 "bit_operand" "")
1237 (xor:QI (match_operand:QI 1 "bit_operand" "")
1238 (match_operand:QI 2 "nonmemory_operand" "")))]
1242 if (fix_bit_operand (operands, 1, XOR))
1246 (define_expand "xorhi3"
1247 [(set (match_operand:HI 0 "register_operand" "")
1248 (xor:HI (match_operand:HI 1 "register_operand" "")
1249 (match_operand:HI 2 "nonmemory_operand" "")))]
1253 (define_expand "xorsi3"
1254 [(set (match_operand:SI 0 "register_operand" "")
1255 (xor:SI (match_operand:SI 1 "register_operand" "")
1256 (match_operand:SI 2 "nonmemory_operand" "")))]
1260 ;; ----------------------------------------------------------------------
1261 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1262 ;; ----------------------------------------------------------------------
1265 [(set (match_operand:HI 0 "register_operand" "=r")
1266 (match_operator:HI 3 "bit_operator"
1267 [(match_operand:HI 1 "register_operand" "%0")
1268 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1270 "* return output_logical_op (HImode, operands);"
1271 [(set (attr "length")
1272 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1274 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1277 [(set (match_operand:SI 0 "register_operand" "=r")
1278 (match_operator:SI 3 "bit_operator"
1279 [(match_operand:SI 1 "register_operand" "%0")
1280 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1282 "* return output_logical_op (SImode, operands);"
1283 [(set (attr "length")
1284 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1286 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1288 ;; ----------------------------------------------------------------------
1289 ;; NEGATION INSTRUCTIONS
1290 ;; ----------------------------------------------------------------------
1292 (define_insn "negqi2"
1293 [(set (match_operand:QI 0 "register_operand" "=r")
1294 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1297 [(set_attr "length" "2")
1298 (set_attr "cc" "set_zn")])
1300 (define_expand "neghi2"
1301 [(set (match_operand:HI 0 "register_operand" "")
1302 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1308 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1313 (define_expand "neghi2_h8300"
1315 (not:HI (match_operand:HI 1 "register_operand" "")))
1316 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1317 (set (match_operand:HI 0 "register_operand" "")
1320 "operands[2] = gen_reg_rtx (HImode);")
1322 (define_insn "neghi2_h8300h"
1323 [(set (match_operand:HI 0 "register_operand" "=r")
1324 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1325 "TARGET_H8300H || TARGET_H8300S"
1327 [(set_attr "length" "2")
1328 (set_attr "cc" "set_zn")])
1330 (define_expand "negsi2"
1331 [(set (match_operand:SI 0 "register_operand" "")
1332 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1338 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1343 (define_expand "negsi2_h8300"
1345 (not:SI (match_operand:SI 1 "register_operand" "")))
1346 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1347 (set (match_operand:SI 0 "register_operand" "")
1350 "operands[2] = gen_reg_rtx (SImode);")
1352 (define_insn "negsi2_h8300h"
1353 [(set (match_operand:SI 0 "register_operand" "=r")
1354 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1355 "TARGET_H8300H || TARGET_H8300S"
1357 [(set_attr "length" "2")
1358 (set_attr "cc" "set_zn")])
1360 ;; ----------------------------------------------------------------------
1362 ;; ----------------------------------------------------------------------
1364 (define_insn "one_cmplqi2"
1365 [(set (match_operand:QI 0 "register_operand" "=r")
1366 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1369 [(set_attr "length" "2")
1370 (set_attr "cc" "set_znv")])
1372 (define_expand "one_cmplhi2"
1373 [(set (match_operand:HI 0 "register_operand" "=r")
1374 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1379 [(set (match_operand:HI 0 "register_operand" "=r")
1380 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1383 [(set_attr "cc" "clobber")
1384 (set_attr "length" "4")])
1387 [(set (match_operand:HI 0 "register_operand" "=r")
1388 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1389 "TARGET_H8300H || TARGET_H8300S"
1391 [(set_attr "cc" "set_znv")
1392 (set_attr "length" "2")])
1394 (define_expand "one_cmplsi2"
1395 [(set (match_operand:SI 0 "register_operand" "=r")
1396 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1401 [(set (match_operand:SI 0 "register_operand" "=r")
1402 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1404 "not %w0\;not %x0\;not %y0\;not %z0"
1405 [(set_attr "cc" "clobber")
1406 (set_attr "length" "8")])
1409 [(set (match_operand:SI 0 "register_operand" "=r")
1410 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1411 "TARGET_H8300H || TARGET_H8300S"
1413 [(set_attr "cc" "set_znv")
1414 (set_attr "length" "2")])
1416 ;; ----------------------------------------------------------------------
1417 ;; JUMP INSTRUCTIONS
1418 ;; ----------------------------------------------------------------------
1420 ;; Conditional jump instructions
1422 (define_expand "ble"
1424 (if_then_else (le (cc0)
1426 (label_ref (match_operand 0 "" ""))
1431 (define_expand "bleu"
1433 (if_then_else (leu (cc0)
1435 (label_ref (match_operand 0 "" ""))
1440 (define_expand "bge"
1442 (if_then_else (ge (cc0)
1444 (label_ref (match_operand 0 "" ""))
1449 (define_expand "bgeu"
1451 (if_then_else (geu (cc0)
1453 (label_ref (match_operand 0 "" ""))
1458 (define_expand "blt"
1460 (if_then_else (lt (cc0)
1462 (label_ref (match_operand 0 "" ""))
1467 (define_expand "bltu"
1469 (if_then_else (ltu (cc0)
1471 (label_ref (match_operand 0 "" ""))
1476 (define_expand "bgt"
1478 (if_then_else (gt (cc0)
1480 (label_ref (match_operand 0 "" ""))
1485 (define_expand "bgtu"
1487 (if_then_else (gtu (cc0)
1489 (label_ref (match_operand 0 "" ""))
1494 (define_expand "beq"
1496 (if_then_else (eq (cc0)
1498 (label_ref (match_operand 0 "" ""))
1503 (define_expand "bne"
1505 (if_then_else (ne (cc0)
1507 (label_ref (match_operand 0 "" ""))
1512 (define_insn "branch_true"
1514 (if_then_else (match_operator 1 "comparison_operator"
1515 [(cc0) (const_int 0)])
1516 (label_ref (match_operand 0 "" ""))
1521 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1522 && (GET_CODE (operands[1]) == GT
1523 || GET_CODE (operands[1]) == GE
1524 || GET_CODE (operands[1]) == LE
1525 || GET_CODE (operands[1]) == LT))
1527 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1531 if (get_attr_length (insn) == 2)
1532 return \"b%j1 %l0\";
1533 else if (get_attr_length (insn) == 4)
1534 return \"b%j1 %l0:16\";
1536 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1538 [(set_attr "type" "branch")
1539 (set_attr "cc" "none")])
1541 (define_insn "branch_false"
1543 (if_then_else (match_operator 1 "comparison_operator"
1544 [(cc0) (const_int 0)])
1546 (label_ref (match_operand 0 "" ""))))]
1550 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1551 && (GET_CODE (operands[1]) == GT
1552 || GET_CODE (operands[1]) == GE
1553 || GET_CODE (operands[1]) == LE
1554 || GET_CODE (operands[1]) == LT))
1556 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1560 if (get_attr_length (insn) == 2)
1561 return \"b%k1 %l0\";
1562 else if (get_attr_length (insn) == 4)
1563 return \"b%k1 %l0:16\";
1565 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1567 [(set_attr "type" "branch")
1568 (set_attr "cc" "none")])
1570 ;; Unconditional and other jump instructions.
1574 (label_ref (match_operand 0 "" "")))]
1578 if (get_attr_length (insn) == 2)
1580 else if (get_attr_length (insn) == 4)
1581 return \"bra %l0:16\";
1583 return \"jmp @%l0\";
1585 [(set_attr "type" "branch")
1586 (set_attr "cc" "none")])
1588 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1590 (define_expand "tablejump"
1591 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1592 (use (label_ref (match_operand 1 "" "")))])]
1596 (define_insn "tablejump_h8300"
1597 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1598 (use (label_ref (match_operand 1 "" "")))]
1601 [(set_attr "cc" "none")
1602 (set_attr "length" "2")])
1604 (define_insn "tablejump_h8300h"
1605 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1606 (use (label_ref (match_operand 1 "" "")))]
1607 "TARGET_H8300H || TARGET_H8300S"
1609 [(set_attr "cc" "none")
1610 (set_attr "length" "2")])
1612 (define_insn "tablejump_normal_mode"
1613 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1614 (use (label_ref (match_operand 1 "" "")))]
1615 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1617 [(set_attr "cc" "none")
1618 (set_attr "length" "2")])
1620 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1622 (define_expand "indirect_jump"
1623 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1627 (define_insn "indirect_jump_h8300"
1628 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1631 [(set_attr "cc" "none")
1632 (set_attr "length" "2")])
1634 (define_insn "indirect_jump_h8300h"
1635 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1636 "TARGET_H8300H || TARGET_H8300S"
1638 [(set_attr "cc" "none")
1639 (set_attr "length" "2")])
1641 (define_insn "indirect_jump_normal_mode"
1642 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1643 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1645 [(set_attr "cc" "none")
1646 (set_attr "length" "2")])
1648 ;; Call subroutine with no return value.
1650 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1653 [(call (match_operand:QI 0 "call_insn_operand" "or")
1654 (match_operand:HI 1 "general_operand" "g"))]
1658 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1659 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1660 return \"jsr\\t@%0:8\";
1662 return \"jsr\\t%0\";
1664 [(set_attr "cc" "clobber")
1665 (set (attr "length")
1666 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1670 ;; Call subroutine, returning value in operand 0
1671 ;; (which must be a hard register).
1673 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1675 (define_insn "call_value"
1676 [(set (match_operand 0 "" "=r")
1677 (call (match_operand:QI 1 "call_insn_operand" "or")
1678 (match_operand:HI 2 "general_operand" "g")))]
1682 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1683 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1684 return \"jsr\\t@%1:8\";
1686 return \"jsr\\t%1\";
1688 [(set_attr "cc" "clobber")
1689 (set (attr "length")
1690 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1698 [(set_attr "cc" "none")
1699 (set_attr "length" "2")])
1701 ;; ----------------------------------------------------------------------
1702 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1703 ;; ----------------------------------------------------------------------
1705 (define_insn "*stm_h8300s_2"
1707 [(set (reg:SI SP_REG)
1708 (plus:SI (reg:SI SP_REG) (const_int -8)))
1709 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1710 (match_operand:SI 0 "register_operand" ""))
1711 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1712 (match_operand:SI 1 "register_operand" ""))])]
1714 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1715 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1716 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1717 "stm.l\\t%S0-%S1,@-er7"
1718 [(set_attr "cc" "none")
1719 (set_attr "length" "4")])
1721 (define_insn "*stm_h8300s_3"
1723 [(set (reg:SI SP_REG)
1724 (plus:SI (reg:SI SP_REG) (const_int -12)))
1725 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1726 (match_operand:SI 0 "register_operand" ""))
1727 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1728 (match_operand:SI 1 "register_operand" ""))
1729 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1730 (match_operand:SI 2 "register_operand" ""))])]
1732 && ((REGNO (operands[0]) == 0
1733 && REGNO (operands[1]) == 1
1734 && REGNO (operands[2]) == 2)
1735 || (REGNO (operands[0]) == 4
1736 && REGNO (operands[1]) == 5
1737 && REGNO (operands[2]) == 6))"
1738 "stm.l\\t%S0-%S2,@-er7"
1739 [(set_attr "cc" "none")
1740 (set_attr "length" "4")])
1742 (define_insn "*stm_h8300s_4"
1744 [(set (reg:SI SP_REG)
1745 (plus:SI (reg:SI SP_REG) (const_int -16)))
1746 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1747 (match_operand:SI 0 "register_operand" ""))
1748 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1749 (match_operand:SI 1 "register_operand" ""))
1750 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1751 (match_operand:SI 2 "register_operand" ""))
1752 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
1753 (match_operand:SI 3 "register_operand" ""))])]
1755 && REGNO (operands[0]) == 0
1756 && REGNO (operands[1]) == 1
1757 && REGNO (operands[2]) == 2
1758 && REGNO (operands[3]) == 3"
1759 "stm.l\\t%S0-%S3,@-er7"
1760 [(set_attr "cc" "none")
1761 (set_attr "length" "4")])
1763 ;; ----------------------------------------------------------------------
1764 ;; EXTEND INSTRUCTIONS
1765 ;; ----------------------------------------------------------------------
1767 (define_expand "zero_extendqihi2"
1768 [(set (match_operand:HI 0 "register_operand" "")
1769 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1774 [(set (match_operand:HI 0 "register_operand" "=r,r")
1775 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1779 mov.b %R1,%s0\;mov.b #0,%t0"
1780 [(set_attr "length" "2,10")
1781 (set_attr "cc" "clobber,clobber")])
1784 [(set (match_operand:HI 0 "register_operand" "=r,r")
1785 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1786 "TARGET_H8300H || TARGET_H8300S"
1789 mov.b %R1,%s0\;extu.w %T0"
1790 [(set_attr "length" "2,10")
1791 (set_attr "cc" "set_znv,set_znv")])
1793 ;; The compiler can synthesize a H8/300H variant of this which is
1794 ;; just as efficient as one that we'd create
1795 (define_insn "zero_extendqisi2"
1796 [(set (match_operand:SI 0 "register_operand" "=r,r")
1797 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1800 mov.b #0,%x0\;sub.w %e0,%e0
1801 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1802 [(set_attr "length" "4,6")
1803 (set_attr "cc" "clobber,clobber")])
1805 (define_expand "zero_extendhisi2"
1806 [(set (match_operand:SI 0 "register_operand" "")
1807 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1811 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1813 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1814 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1818 mov.w %f1,%f0\;sub.w %e0,%e0
1819 mov.w %e1,%f0\;sub.w %e0,%e0"
1820 [(set_attr "length" "2,4,4")
1821 (set_attr "cc" "clobber,clobber,clobber")])
1824 [(set (match_operand:SI 0 "register_operand" "=r")
1825 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1826 "TARGET_H8300H || TARGET_H8300S"
1828 [(set_attr "length" "2")
1829 (set_attr "cc" "set_znv")])
1831 (define_expand "extendqihi2"
1832 [(set (match_operand:HI 0 "register_operand" "")
1833 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1838 [(set (match_operand:HI 0 "register_operand" "=r,r")
1839 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1842 bld #7,%s0\;subx %t0,%t0
1843 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1844 [(set_attr "length" "4,8")
1845 (set_attr "cc" "clobber,clobber")])
1848 [(set (match_operand:HI 0 "register_operand" "=r")
1849 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1850 "TARGET_H8300H || TARGET_H8300S"
1852 [(set_attr "length" "2")
1853 (set_attr "cc" "set_znv")])
1855 ;; The compiler can synthesize a H8/300H variant of this which is
1856 ;; just as efficient as one that we'd create
1857 (define_insn "extendqisi2"
1858 [(set (match_operand:SI 0 "register_operand" "=r,r")
1859 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1862 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1863 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1864 [(set_attr "length" "8,10")
1865 (set_attr "cc" "clobber,clobber")])
1867 (define_expand "extendhisi2"
1868 [(set (match_operand:SI 0 "register_operand" "")
1869 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1874 [(set (match_operand:SI 0 "register_operand" "=r,r")
1875 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1878 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1879 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1880 [(set_attr "length" "6,8")
1881 (set_attr "cc" "clobber,clobber")])
1884 [(set (match_operand:SI 0 "register_operand" "=r")
1885 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1886 "TARGET_H8300H || TARGET_H8300S"
1888 [(set_attr "length" "2")
1889 (set_attr "cc" "set_znv")])
1891 ;; ----------------------------------------------------------------------
1893 ;; ----------------------------------------------------------------------
1895 ;; We make some attempt to provide real efficient shifting. One example is
1896 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1897 ;; reg and moving 0 into the former reg.
1899 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1900 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1901 ;; give the optimizer more cracks at the code. However, we wish to do things
1902 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1903 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1904 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1905 ;; to detect cases it can optimize.
1907 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1908 ;; easier "do it at insn emit time" route.
1912 (define_expand "ashlqi3"
1913 [(set (match_operand:QI 0 "register_operand" "")
1914 (ashift:QI (match_operand:QI 1 "register_operand" "")
1915 (match_operand:QI 2 "nonmemory_operand" "")))]
1917 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
1919 (define_expand "ashrqi3"
1920 [(set (match_operand:QI 0 "register_operand" "")
1921 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1922 (match_operand:QI 2 "nonmemory_operand" "")))]
1924 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
1926 (define_expand "lshrqi3"
1927 [(set (match_operand:QI 0 "register_operand" "")
1928 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1929 (match_operand:QI 2 "nonmemory_operand" "")))]
1931 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
1934 [(set (match_operand:QI 0 "register_operand" "=r,r")
1935 (match_operator:QI 3 "nshift_operator"
1936 [ (match_operand:QI 1 "register_operand" "0,0")
1937 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
1938 (clobber (match_scratch:QI 4 "=X,&r"))]
1940 "* return output_a_shift (operands);"
1941 [(set (attr "length")
1942 (symbol_ref "compute_a_shift_length (insn, operands)"))
1943 (set_attr "cc" "clobber")])
1947 (define_expand "ashlhi3"
1948 [(set (match_operand:HI 0 "register_operand" "")
1949 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1950 (match_operand:QI 2 "nonmemory_operand" "")))]
1952 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
1954 (define_expand "lshrhi3"
1955 [(set (match_operand:HI 0 "register_operand" "")
1956 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1957 (match_operand:QI 2 "nonmemory_operand" "")))]
1959 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
1961 (define_expand "ashrhi3"
1962 [(set (match_operand:HI 0 "register_operand" "")
1963 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1964 (match_operand:QI 2 "nonmemory_operand" "")))]
1966 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
1969 [(set (match_operand:HI 0 "register_operand" "=r,r")
1970 (match_operator:HI 3 "nshift_operator"
1971 [ (match_operand:HI 1 "register_operand" "0,0")
1972 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
1973 (clobber (match_scratch:QI 4 "=X,&r"))]
1975 "* return output_a_shift (operands);"
1976 [(set (attr "length")
1977 (symbol_ref "compute_a_shift_length (insn, operands)"))
1978 (set_attr "cc" "clobber")])
1982 (define_expand "ashlsi3"
1983 [(set (match_operand:SI 0 "register_operand" "")
1984 (ashift:SI (match_operand:SI 1 "general_operand" "")
1985 (match_operand:QI 2 "nonmemory_operand" "")))]
1987 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
1989 (define_expand "lshrsi3"
1990 [(set (match_operand:SI 0 "register_operand" "")
1991 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
1992 (match_operand:QI 2 "nonmemory_operand" "")))]
1994 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
1996 (define_expand "ashrsi3"
1997 [(set (match_operand:SI 0 "register_operand" "")
1998 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
1999 (match_operand:QI 2 "nonmemory_operand" "")))]
2001 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
2004 [(set (match_operand:SI 0 "register_operand" "=r,r")
2005 (match_operator:SI 3 "nshift_operator"
2006 [ (match_operand:SI 1 "register_operand" "0,0")
2007 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2008 (clobber (match_scratch:QI 4 "=X,&r"))]
2010 "* return output_a_shift (operands);"
2011 [(set (attr "length")
2012 (symbol_ref "compute_a_shift_length (insn, operands)"))
2013 (set_attr "cc" "clobber")])
2015 ;; ----------------------------------------------------------------------
2017 ;; ----------------------------------------------------------------------
2019 (define_expand "rotlqi3"
2020 [(set (match_operand:QI 0 "register_operand" "")
2021 (rotate:QI (match_operand:QI 1 "register_operand" "")
2022 (match_operand:QI 2 "nonmemory_operand" "")))]
2024 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2026 (define_insn "*rotlqi3_1"
2027 [(set (match_operand:QI 0 "register_operand" "=r")
2028 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2029 (match_operand:QI 2 "immediate_operand" "")))]
2031 "* return emit_a_rotate (ROTATE, operands);"
2032 [(set_attr "length" "20")
2033 (set_attr "cc" "clobber")])
2035 (define_expand "rotlhi3"
2036 [(set (match_operand:HI 0 "register_operand" "")
2037 (rotate:HI (match_operand:HI 1 "register_operand" "")
2038 (match_operand:QI 2 "nonmemory_operand" "")))]
2040 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2042 (define_insn "*rotlhi3_1"
2043 [(set (match_operand:HI 0 "register_operand" "=r")
2044 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2045 (match_operand:QI 2 "immediate_operand" "")))]
2047 "* return emit_a_rotate (ROTATE, operands);"
2048 [(set_attr "length" "20")
2049 (set_attr "cc" "clobber")])
2051 (define_expand "rotlsi3"
2052 [(set (match_operand:SI 0 "register_operand" "")
2053 (rotate:SI (match_operand:SI 1 "register_operand" "")
2054 (match_operand:QI 2 "nonmemory_operand" "")))]
2055 "TARGET_H8300H || TARGET_H8300S"
2056 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2058 (define_insn "*rotlsi3_1"
2059 [(set (match_operand:SI 0 "register_operand" "=r")
2060 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2061 (match_operand:QI 2 "immediate_operand" "")))]
2062 "TARGET_H8300H || TARGET_H8300S"
2063 "* return emit_a_rotate (ROTATE, operands);"
2064 [(set_attr "length" "20")
2065 (set_attr "cc" "clobber")])
2067 ;; -----------------------------------------------------------------
2069 ;; -----------------------------------------------------------------
2070 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2071 ;; instructions so let's use them as well as we can.
2073 ;; You'll never believe all these patterns perform one basic action --
2074 ;; load a bit from the source, optionally invert the bit, then store it
2075 ;; in the destination (which is known to be zero).
2077 ;; Combine obviously need some work to better identify this situation and
2078 ;; canonicalize the form better.
2081 ;; Normal loads with a 16bit destination.
2085 [(set (match_operand:HI 0 "register_operand" "=&r")
2086 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2088 (match_operand:HI 2 "immediate_operand" "n")))]
2090 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2091 [(set_attr "cc" "clobber")
2092 (set_attr "length" "6")])
2095 ;; Inverted loads with a 16bit destination.
2099 [(set (match_operand:HI 0 "register_operand" "=&r")
2100 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2101 (match_operand:HI 3 "const_int_operand" "n"))
2103 (match_operand:HI 2 "const_int_operand" "n")))]
2105 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2106 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2107 [(set_attr "cc" "clobber")
2108 (set_attr "length" "8")])
2111 ;; Normal loads with a 32bit destination.
2115 [(set (match_operand:SI 0 "register_operand" "=&r")
2116 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2118 (match_operand 2 "const_int_operand" "n")))]
2120 && INTVAL (operands[2]) < 16"
2121 "* return output_simode_bld (0, operands);"
2122 [(set_attr "cc" "clobber")
2123 (set_attr "length" "6")])
2126 [(set (match_operand:SI 0 "register_operand" "=r")
2127 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2129 (match_operand 2 "const_int_operand" "n")))]
2130 "(TARGET_H8300H || TARGET_H8300S)
2131 && INTVAL (operands[2]) < 16"
2132 "* return output_simode_bld (0, operands);"
2133 [(set_attr "cc" "clobber")
2134 (set_attr "length" "6")])
2137 ;; Inverted loads with a 32bit destination.
2141 [(set (match_operand:SI 0 "register_operand" "=&r")
2142 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2143 (match_operand:HI 3 "const_int_operand" "n"))
2145 (match_operand 2 "const_int_operand" "n")))]
2147 && INTVAL (operands[2]) < 16
2148 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2149 "* return output_simode_bld (1, operands);"
2150 [(set_attr "cc" "clobber")
2151 (set_attr "length" "6")])
2154 [(set (match_operand:SI 0 "register_operand" "=r")
2155 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
2156 (match_operand 3 "const_int_operand" "n"))
2158 (match_operand 2 "const_int_operand" "n")))]
2159 "(TARGET_H8300H || TARGET_H8300S)
2160 && INTVAL (operands[2]) < 16
2161 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2162 "* return output_simode_bld (1, operands);"
2163 [(set_attr "cc" "clobber")
2164 (set_attr "length" "6")])
2166 (define_expand "insv"
2167 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2168 (match_operand:HI 1 "general_operand" "")
2169 (match_operand:HI 2 "general_operand" ""))
2170 (match_operand:HI 3 "general_operand" ""))]
2174 /* We only have single bit bit-field instructions. */
2175 if (INTVAL (operands[1]) != 1)
2178 /* For now, we don't allow memory operands. */
2179 if (GET_CODE (operands[0]) == MEM
2180 || GET_CODE (operands[3]) == MEM)
2185 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2187 (match_operand:HI 1 "immediate_operand" "n"))
2188 (match_operand:HI 2 "register_operand" "r"))]
2190 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2191 [(set_attr "cc" "clobber")
2192 (set_attr "length" "4")])
2194 (define_expand "extzv"
2195 [(set (match_operand:HI 0 "register_operand" "")
2196 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2197 (match_operand:HI 2 "general_operand" "")
2198 (match_operand:HI 3 "general_operand" "")))]
2202 /* We only have single bit bit-field instructions. */
2203 if (INTVAL (operands[2]) != 1)
2206 /* For now, we don't allow memory operands. */
2207 if (GET_CODE (operands[1]) == MEM)
2211 ;; BAND, BOR, and BXOR patterns
2214 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2215 (match_operator:HI 4 "bit_operator"
2216 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2218 (match_operand:HI 2 "immediate_operand" "n"))
2219 (match_operand:HI 3 "bit_operand" "0")]))]
2221 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2222 [(set_attr "cc" "clobber")
2223 (set_attr "length" "6")
2224 (set_attr "adjust_length" "no")])
2227 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2228 (match_operator:HI 5 "bit_operator"
2229 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2231 (match_operand:HI 2 "immediate_operand" "n"))
2232 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2234 (match_operand:HI 4 "immediate_operand" "n"))]))]
2236 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2237 [(set_attr "cc" "clobber")
2238 (set_attr "length" "6")
2239 (set_attr "adjust_length" "no")])
2241 ;; -----------------------------------------------------------------
2243 ;; -----------------------------------------------------------------
2245 (define_insn "*extzv_8_8"
2246 [(set (match_operand:SI 0 "register_operand" "=r")
2247 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2250 "TARGET_H8300H || TARGET_H8300S"
2251 "mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0"
2252 [(set_attr "cc" "set_znv")
2253 (set_attr "length" "6")])
2255 (define_insn "*extzv_8_16"
2256 [(set (match_operand:SI 0 "register_operand" "=r")
2257 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2260 "TARGET_H8300H || TARGET_H8300S"
2261 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
2262 [(set_attr "cc" "set_znv")
2263 (set_attr "length" "6")])
2266 [(set (match_operand:HI 0 "register_operand" "=r")
2267 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2268 (match_operand:HI 2 "register_operand" "0")))]
2269 "REG_P (operands[0])
2270 && REG_P (operands[1])
2271 && REGNO (operands[0]) != REGNO (operands[1])"
2273 [(set_attr "cc" "clobber")
2274 (set_attr "length" "2")])
2277 [(set (match_operand:SI 0 "register_operand" "=r")
2278 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2279 (match_operand:SI 2 "register_operand" "0")))]
2280 "(TARGET_H8300H || TARGET_H8300S)
2281 && REG_P (operands[0])
2282 && REG_P (operands[1])
2283 && (REGNO (operands[0]) != REGNO (operands[1]))"
2285 [(set_attr "cc" "clobber")
2286 (set_attr "length" "2")])
2289 [(set (match_operand:SI 0 "register_operand" "=r")
2290 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2291 (match_operand:SI 2 "register_operand" "0")))]
2294 [(set_attr "cc" "clobber")
2295 (set_attr "length" "2")])
2298 [(set (match_operand:HI 0 "register_operand" "=r")
2299 (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2300 (match_operand:HI 2 "register_operand" "0")))]
2301 "REG_P (operands[0])
2302 && REG_P (operands[1])
2303 && REGNO (operands[0]) != REGNO (operands[1])"
2305 [(set_attr "cc" "clobber")
2306 (set_attr "length" "2")])
2309 [(set (match_operand:SI 0 "register_operand" "=r")
2310 (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2311 (match_operand:SI 2 "register_operand" "0")))]
2312 "(TARGET_H8300H || TARGET_H8300S)
2313 && REG_P (operands[0])
2314 && REG_P (operands[1])
2315 && (REGNO (operands[0]) != REGNO (operands[1]))"
2317 [(set_attr "cc" "clobber")
2318 (set_attr "length" "2")])
2321 [(set (match_operand:SI 0 "register_operand" "=r")
2322 (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2323 (match_operand:SI 2 "register_operand" "0")))]
2324 "REG_P (operands[0])
2325 && REG_P (operands[1])
2326 && REGNO (operands[0]) != REGNO (operands[1])"
2328 [(set_attr "cc" "clobber")
2329 (set_attr "length" "2")])
2332 [(set (match_operand:HI 0 "register_operand" "=r")
2333 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2334 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2336 "REG_P (operands[0])
2337 && REG_P (operands[2])
2338 && REGNO (operands[0]) != REGNO (operands[2])"
2340 [(set_attr "cc" "clobber")
2341 (set_attr "length" "2")])
2343 (define_insn "*iorhi_shift_8"
2344 [(set (match_operand:HI 0 "register_operand" "=r")
2345 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
2347 (match_operand:HI 2 "register_operand" "0")))]
2350 [(set_attr "cc" "clobber")
2351 (set_attr "length" "2")])
2354 [(set (match_operand:SI 0 "register_operand" "=r")
2355 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2356 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2358 "TARGET_H8300H || TARGET_H8300S"
2360 [(set_attr "cc" "clobber")
2361 (set_attr "length" "2")])
2364 [(set (match_operand:SI 0 "register_operand" "=r")
2365 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2367 (match_operand:SI 2 "register_operand" "0")))]
2368 "TARGET_H8300H || TARGET_H8300S"
2370 [(set_attr "cc" "clobber")
2371 (set_attr "length" "2")])
2373 ;; Storing a part of HImode to QImode.
2376 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2377 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
2381 [(set_attr "cc" "set_znv")
2382 (set_attr "length" "8")])
2384 ;; Storing a part of SImode to QImode.
2387 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2388 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2392 [(set_attr "cc" "set_znv")
2393 (set_attr "length" "8")])
2396 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2397 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2399 (clobber (match_scratch:SI 2 "=&r"))]
2400 "TARGET_H8300H || TARGET_H8300S"
2401 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
2402 [(set_attr "cc" "set_znv")
2403 (set_attr "length" "10")])
2406 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
2407 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2409 (clobber (match_scratch:SI 2 "=&r"))]
2410 "TARGET_H8300H || TARGET_H8300S"
2411 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
2412 [(set_attr "cc" "set_znv")
2413 (set_attr "length" "10")])
2415 (define_insn_and_split ""
2417 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2421 (label_ref (match_operand 1 "" ""))
2429 (if_then_else (ge (cc0)
2431 (label_ref (match_dup 1))
2435 (define_insn_and_split ""
2437 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2441 (label_ref (match_operand 1 "" ""))
2449 (if_then_else (lt (cc0)
2451 (label_ref (match_dup 1))
2455 ;; -----------------------------------------------------------------
2456 ;; PEEPHOLE PATTERNS
2457 ;; -----------------------------------------------------------------
2459 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
2463 [(set (match_operand:HI 0 "register_operand" "")
2464 (lshiftrt:HI (match_dup 0)
2465 (match_operand:HI 1 "const_int_operand" "")))
2466 (clobber (match_operand:HI 2 "" ""))])
2468 (and:HI (match_dup 0)
2469 (match_operand:HI 3 "const_int_operand" "")))]
2470 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
2472 (and:HI (match_dup 0)
2476 (lshiftrt:HI (match_dup 0)
2478 (clobber (match_dup 2))])]
2481 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
2485 [(set (match_operand:HI 0 "register_operand" "")
2486 (ashift:HI (match_dup 0)
2487 (match_operand:HI 1 "const_int_operand" "")))
2488 (clobber (match_operand:HI 2 "" ""))])
2490 (and:HI (match_dup 0)
2491 (match_operand:HI 3 "const_int_operand" "")))]
2492 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
2494 (and:HI (match_dup 0)
2498 (ashift:HI (match_dup 0)
2500 (clobber (match_dup 2))])]
2503 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
2507 [(set (match_operand:SI 0 "register_operand" "")
2508 (lshiftrt:SI (match_dup 0)
2509 (match_operand:SI 1 "const_int_operand" "")))
2510 (clobber (match_operand:SI 2 "" ""))])
2512 (and:SI (match_dup 0)
2513 (match_operand:SI 3 "const_int_operand" "")))]
2514 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
2516 (and:SI (match_dup 0)
2520 (lshiftrt:SI (match_dup 0)
2522 (clobber (match_dup 2))])]
2525 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
2529 [(set (match_operand:SI 0 "register_operand" "")
2530 (ashift:SI (match_dup 0)
2531 (match_operand:SI 1 "const_int_operand" "")))
2532 (clobber (match_operand:SI 2 "" ""))])
2534 (and:SI (match_dup 0)
2535 (match_operand:SI 3 "const_int_operand" "")))]
2536 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
2538 (and:SI (match_dup 0)
2542 (ashift:SI (match_dup 0)
2544 (clobber (match_dup 2))])]
2547 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
2551 [(set (match_operand:SI 0 "register_operand" "")
2552 (lshiftrt:SI (match_dup 0)
2553 (match_operand:SI 1 "const_int_operand" "")))
2554 (clobber (match_operand:SI 2 "" ""))])
2556 (and:SI (match_dup 0)
2557 (match_operand:SI 3 "const_int_operand" "")))]
2558 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
2560 (and:SI (match_dup 0)
2564 (lshiftrt:SI (match_dup 0)
2566 (clobber (match_dup 2))])]
2569 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
2573 [(set (match_operand:SI 0 "register_operand" "")
2574 (ashift:SI (match_dup 0)
2575 (match_operand:SI 1 "const_int_operand" "")))
2576 (clobber (match_operand:SI 2 "" ""))])
2578 (and:SI (match_dup 0)
2579 (match_operand:SI 3 "const_int_operand" "")))]
2580 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
2582 (and:SI (match_dup 0)
2586 (ashift:SI (match_dup 0)
2588 (clobber (match_dup 2))])]
2591 ;; Convert a QImode push into an SImode push so that the
2592 ;; define_peephole2 below can cram multiple pushes into one stm.l.
2595 [(parallel [(set (reg:SI SP_REG)
2596 (plus:SI (reg:SI SP_REG) (const_int -4)))
2597 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
2598 (match_operand:QI 0 "register_operand" ""))])]
2600 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2602 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
2604 ;; Convert a HImode push into an SImode push so that the
2605 ;; define_peephole2 below can cram multiple pushes into one stm.l.
2608 [(parallel [(set (reg:SI SP_REG)
2609 (plus:SI (reg:SI SP_REG) (const_int -4)))
2610 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
2611 (match_operand:HI 0 "register_operand" ""))])]
2613 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2615 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
2617 ;; Cram four pushes into stm.l.
2620 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2621 (match_operand:SI 0 "register_operand" ""))
2622 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2623 (match_operand:SI 1 "register_operand" ""))
2624 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2625 (match_operand:SI 2 "register_operand" ""))
2626 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2627 (match_operand:SI 3 "register_operand" ""))]
2629 && REGNO (operands[0]) == 0
2630 && REGNO (operands[1]) == 1
2631 && REGNO (operands[2]) == 2
2632 && REGNO (operands[3]) == 3"
2633 [(parallel [(set (reg:SI SP_REG)
2634 (plus:SI (reg:SI SP_REG)
2636 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2638 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2640 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2642 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
2646 ;; Cram three pushes into stm.l.
2649 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2650 (match_operand:SI 0 "register_operand" ""))
2651 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2652 (match_operand:SI 1 "register_operand" ""))
2653 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2654 (match_operand:SI 2 "register_operand" ""))]
2656 && ((REGNO (operands[0]) == 0
2657 && REGNO (operands[1]) == 1
2658 && REGNO (operands[2]) == 2)
2659 || (REGNO (operands[0]) == 4
2660 && REGNO (operands[1]) == 5
2661 && REGNO (operands[2]) == 6))"
2662 [(parallel [(set (reg:SI SP_REG)
2663 (plus:SI (reg:SI SP_REG)
2665 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2667 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2669 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2673 ;; Cram two pushes into stm.l.
2676 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2677 (match_operand:SI 0 "register_operand" ""))
2678 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2679 (match_operand:SI 1 "register_operand" ""))]
2681 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2682 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2683 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2684 [(parallel [(set (reg:SI SP_REG)
2685 (plus:SI (reg:SI SP_REG)
2687 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2689 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))