1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (define_attr "cpu" "h8300,h8300h"
30 (const (symbol_ref "cpu_type")))
32 ;; ??? If we can remove the operand type on all the insns, do it.
33 ;; ??? Otherwise, try to have the operand type on all the insns.
35 (define_attr "type" "branch,return,call,arith,move,float,multi"
36 (const_string "arith"))
38 ;; The size of instructions in bytes.
40 (define_attr "length" ""
41 (cond [(eq_attr "type" "branch")
42 (if_then_else (and (ge (minus (pc) (match_dup 0))
44 (le (minus (pc) (match_dup 0))
47 (if_then_else (and (eq_attr "cpu" "h8300h")
48 (and (ge (minus (pc) (match_dup 0))
50 (le (minus (pc) (match_dup 0))
54 (eq_attr "type" "move") (const_int 4)
55 (eq_attr "type" "return") (const_int 2)
56 (eq_attr "type" "float") (const_int 12)
57 (eq_attr "type" "call") (const_int 4)]
60 ;; Condition code settings.
61 ;; none - insn does not affect cc
62 ;; none_0hit - insn does not affect cc but it does modify operand 0
63 ;; This attribute is used to keep track of when operand 0 changes.
64 ;; See the description of NOTICE_UPDATE_CC for more info.
65 ;; set - insn sets flags z,n. v,c are set to 0.
66 ;; (c may not really be set to 0 but that's ok, we don't need it anyway).
67 ;; set_zn_c0 - insn sets z,n to usable values. v is unknown. c may or may not
68 ;; be known (if it isn't that's ok, we don't need it anyway).
69 ;; compare - compare instruction
70 ;; clobber - value of cc is unknown
71 (define_attr "cc" "none,none_0hit,set,set_zn_c0,compare,clobber"
72 (const_string "clobber"))
74 ;; ----------------------------------------------------------------------
76 ;; ----------------------------------------------------------------------
80 (define_insn "movqi_push"
81 [(set (match_operand:QI 0 "push_operand" "=<")
82 (match_operand:QI 1 "register_operand" "r"))]
87 return \"push.w %T1\";
89 return \"push.l %S1\";
91 [(set_attr "type" "move")
92 (set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
93 (set_attr "cc" "set")])
95 ;; ??? Use of the `c' constraint doesn't seem right.
96 (define_insn "movqi_internal"
97 [(set (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<,r")
98 (match_operand:QI 1 "general_operand_src" "I,r>,io,r,r,c"))]
99 "register_operand (operands[0],QImode)
100 || register_operand (operands[1], QImode)"
107 xor %X0,%X0\;bst #0,%X0"
108 [(set_attr "type" "move")
109 (set_attr_alternative "length"
110 [(const_int 2) (const_int 2)
111 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
112 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
113 (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))
115 (set_attr "cc" "set_zn_c0,set,set,set,set,clobber")])
117 (define_expand "movqi"
118 [(set (match_operand:QI 0 "general_operand_dst" "")
119 (match_operand:QI 1 "general_operand_src" ""))]
123 /* One of the ops has to be in a register */
124 if (!register_operand(operand0, QImode)
125 && !register_operand(operand1, QImode))
127 operands[1] = copy_to_mode_reg(QImode, operand1);
131 (define_insn "movstrictqi"
132 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "=r,r,r,o,<"))
133 (match_operand:QI 1 "general_operand_src" "I,r,io,r,r"))]
141 [(set_attr "type" "move")
142 (set_attr_alternative "length"
143 [(const_int 2) (const_int 2)
144 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
145 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
146 (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
147 (set_attr "cc" "set_zn_c0,set,set,set,set")])
151 (define_insn "movhi_push"
152 [(set (match_operand:HI 0 "push_operand" "=<")
153 (match_operand:HI 1 "register_operand" "ra"))]
158 return \"push.w %T1\";
160 return \"push.l %S1\";
162 [(set_attr "type" "move")
163 (set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
164 (set_attr "cc" "set")])
166 (define_insn "movhi_internal"
167 [(set (match_operand:HI 0 "general_operand_dst" "=ra,ra,ra,o,<")
168 (match_operand:HI 1 "general_operand_src" "I,ra>,ion,ra,ra"))]
176 [(set_attr "type" "move")
177 (set_attr_alternative "length"
178 [(const_int 2) (const_int 2)
179 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
180 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
181 (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
182 (set_attr "cc" "set_zn_c0,set,set,set,set")])
184 (define_expand "movhi"
185 [(set (match_operand:HI 0 "general_operand_dst" "")
186 (match_operand:HI 1 "general_operand_src" ""))]
190 /* One of the ops has to be in a register */
191 if (!register_operand(operand1, HImode)
192 && !register_operand(operand0, HImode))
194 operands[1] = copy_to_mode_reg(HImode, operand1);
198 (define_insn "movstricthi"
199 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "=r,r,r,o,<"))
200 (match_operand:HI 1 "general_operand_src" "I,r,io,r,r"))]
208 [(set_attr "type" "move")
209 (set_attr_alternative "length"
210 [(const_int 2) (const_int 2)
211 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
212 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
213 (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4))])
214 (set_attr "cc" "set_zn_c0,set,set,set,set")])
218 (define_expand "movsi"
219 [(set (match_operand:SI 0 "general_operand_dst" "")
220 (match_operand:SI 1 "general_operand_src" ""))]
226 if (do_movsi (operands))
229 else /* TARGET_H8300H */
231 /* One of the ops has to be in a register. */
232 if (!register_operand (operand1, SImode)
233 && !register_operand (operand0, SImode))
235 operands[1] = copy_to_mode_reg (SImode, operand1);
240 (define_expand "movsf"
241 [(set (match_operand:SF 0 "general_operand_dst" "")
242 (match_operand:SF 1 "general_operand_src" ""))]
248 if (do_movsi (operands))
251 else /* TARGET_H8300H */
253 /* One of the ops has to be in a register. */
254 if (!register_operand (operand1, SFmode)
255 && !register_operand (operand0, SFmode))
257 operands[1] = copy_to_mode_reg (SFmode, operand1);
262 (define_insn "movsi_h8300"
263 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
264 (match_operand:SI 1 "general_operand_src" "I,r,ion,r,r,>"))]
266 && (register_operand (operands[0], SImode)
267 || register_operand (operands[1], SImode))"
271 switch (which_alternative)
274 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
276 if (REGNO(operands[0]) < REGNO(operands[1]))
277 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
279 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
281 /* Make sure we don't trample the register we index with. */
283 if (GET_CODE(operands[1]) == MEM)
285 rtx inside = XEXP (operands[1],0);
290 else if (GET_CODE (inside) == PLUS)
292 rtx lhs = XEXP (inside,0);
293 rtx rhs = XEXP (inside,1);
294 if (REG_P (lhs)) rn = REGNO (lhs);
295 if (REG_P (rhs)) rn = REGNO (rhs);
298 if (rn == REGNO (operands[0]))
300 /* Move the second word first. */
301 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
305 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
309 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
311 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
313 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
316 [(set_attr "type" "move")
317 (set_attr "length" "4,4,8,8,4,4")
318 (set_attr "cc" "clobber")])
320 (define_insn "movsf_h8300"
321 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
322 (match_operand:SF 1 "general_operand_src" "I,r,ion,r,r,>"))]
324 && (register_operand (operands[0], SFmode)
325 || register_operand (operands[1], SFmode))"
328 /* Copy of the movsi stuff */
330 switch (which_alternative)
333 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
335 if (REGNO(operands[0]) < REGNO(operands[1]))
336 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
338 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
340 /* Make sure we don't trample the register we index with. */
342 if (GET_CODE (operands[1]) == MEM)
344 rtx inside = XEXP (operands[1],0);
349 else if (GET_CODE (inside) == PLUS)
351 rtx lhs = XEXP (inside,0);
352 rtx rhs = XEXP (inside,1);
353 if (REG_P (lhs)) rn = REGNO (lhs);
354 if (REG_P (rhs)) rn = REGNO (rhs);
357 if (rn == REGNO (operands[0]))
359 /* move the second word first */
360 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
364 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
368 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
370 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
372 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
376 [(set_attr "type" "move")
377 (set_attr "length" "4,4,8,8,4,4")
378 (set_attr "cc" "clobber")])
380 (define_insn "movsi_h8300h"
381 [(set (match_operand:SI 0 "general_operand_dst" "=ra,ra,ra,o,<,ra")
382 (match_operand:SI 1 "general_operand_src" "I,ra,ion,ra,ra,>"))]
384 && (register_operand (operands[0], SImode)
385 || register_operand (operands[1], SImode))"
393 [(set_attr "type" "move")
394 (set_attr "length" "2,2,8,8,4,4")
395 (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
397 (define_insn "movsf_h8300h"
398 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
399 (match_operand:SF 1 "general_operand_src" "I,r,ion,r,r,>"))]
401 && (register_operand (operands[0], SFmode)
402 || register_operand (operands[1], SFmode))"
410 [(set_attr "type" "move")
411 (set_attr "length" "2,2,8,8,4,4")
412 (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
414 ;; ----------------------------------------------------------------------
416 ;; ----------------------------------------------------------------------
419 [(set (cc0) (match_operand:QI 0 "register_operand" "ra"))]
422 [(set_attr "type" "arith")
423 (set_attr "length" "2")
424 (set_attr "cc" "set")])
427 [(set (cc0) (match_operand:HI 0 "general_operand" "ra"))]
430 [(set_attr "type" "arith")
431 (set_attr "length" "2")
432 (set_attr "cc" "set")])
435 [(set (cc0) (match_operand:SI 0 "general_operand" "ra"))]
438 [(set_attr "type" "arith")
439 (set_attr "length" "2")
440 (set_attr "cc" "set")])
444 (compare:QI (match_operand:QI 0 "register_operand" "ra")
445 (match_operand:QI 1 "nonmemory_operand" "rai")))]
448 [(set_attr "type" "arith")
449 (set_attr "length" "2")
450 (set_attr "cc" "compare")])
452 ;; ??? 300h can have an immediate operand here.
456 (compare:HI (match_operand:HI 0 "register_operand" "ra")
457 (match_operand:HI 1 "register_operand" "ra")))]
460 [(set_attr "type" "arith")
461 (set_attr "length" "2")
462 (set_attr "cc" "compare")])
464 ;; ??? 300h can have an immediate operand here.
468 (compare:SI (match_operand:SI 0 "register_operand" "ra")
469 (match_operand:SI 1 "register_operand" "ra")))]
472 [(set_attr "type" "arith")
473 (set_attr "length" "2")
474 (set_attr "cc" "compare")])
476 ;; ----------------------------------------------------------------------
478 ;; ----------------------------------------------------------------------
480 (define_insn "addqi3"
481 [(set (match_operand:QI 0 "register_operand" "=r")
482 (plus:QI (match_operand:QI 1 "register_operand" "%0")
483 (match_operand:QI 2 "nonmemory_operand" "ri")))]
486 [(set_attr "type" "arith")
487 (set_attr "length" "2")
488 (set_attr "cc" "set_zn_c0")])
490 ;; h8300h: adds operates on the 32bit register. We can use it because we don't
491 ;; use the e0-7 registers.
492 ;; ??? 4 can be handled in one insn on the 300h.
494 (define_insn "addhi3"
495 [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,ra,r,ra")
496 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
497 (match_operand:HI 2 "nonmemory_operand" "K,M,L,N,n,ra")))]
501 adds #2,%A0\;adds %C2,%A0
503 subs #2,%A0\;subs %M2,%A0
504 add.b %s2,%s0\;addx %t2,%t0
506 [(set_attr "type" "arith,multi,arith,multi,multi,arith")
507 (set_attr "length" "2,4,2,4,4,2")
508 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,clobber,set_zn_c0")])
510 (define_expand "addsi3"
511 [(set (match_operand:SI 0 "register_operand" "")
512 (plus:SI (match_operand:SI 1 "register_operand" "")
513 (match_operand:SI 2 "nonmemory_operand" "")))]
517 (define_insn "addsi_h8300"
518 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
519 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
520 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
523 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
524 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
525 mov %f1,%f0\;mov %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
526 [(set_attr "type" "arith")
527 (set_attr "length" "8,6,20")
528 (set_attr "cc" "clobber")])
530 ;; ??? 4 can be handled in one insn on the 300h.
531 ;; ??? Should the 'n' constraint be 'i' here?
532 ;; ??? We don't handle (reg + symbol_ref) which the 300h can handle.
534 (define_insn "addsi_h8300h"
535 [(set (match_operand:SI 0 "register_operand" "=ra,ra,ra,ra,r,ra")
536 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
537 (match_operand:SI 2 "nonmemory_operand" "K,M,L,N,n,ra")))]
541 adds #2,%S0\;adds %C2,%S0
543 subs #2,%S0\;subs %M2,%S0
546 [(set_attr "type" "multi,multi,multi,multi,arith,arith")
547 (set_attr "length" "2,4,2,4,6,2")
548 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,set_zn_c0,set_zn_c0")])
550 ;; ----------------------------------------------------------------------
551 ;; SUBTRACT INSTRUCTIONS
552 ;; ----------------------------------------------------------------------
554 (define_insn "subqi3"
555 [(set (match_operand:QI 0 "register_operand" "=r,r")
556 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
557 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
562 [(set_attr "type" "arith")
563 (set_attr "length" "2")
564 (set_attr "cc" "set_zn_c0")])
566 ;; h8300h: subs operates on the 32bit register. We can use it because we don't
567 ;; use the e0-7 registers.
568 ;; ??? 4 can be handled in one insn on the 300h.
569 ;; ??? The fourth alternative can use sub.w on the 300h.
570 ;; ??? Should the 'n' constraint be an 'i' here?
572 (define_insn "subhi3"
573 [(set (match_operand:HI 0 "register_operand" "=ra,ra,ra,r")
574 (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
575 (match_operand:HI 2 "nonmemory_operand" "K,M,ra,n")))]
579 subs #2,%T0\;subs %M2,%T0
581 add.b %E2,%s0\;addx %F2,%t0 ; -%0"
582 [(set_attr "type" "multi")
583 (set_attr "length" "2,4,2,4")
584 (set_attr "cc" "none_0hit,none_0hit,set_zn_c0,clobber")])
586 (define_expand "subsi3"
587 [(set (match_operand:SI 0 "register_operand" "")
588 (minus:SI (match_operand:SI 1 "register_operand" "")
589 (match_operand:SI 2 "nonmemory_operand" "")))]
593 (define_insn "subsi3_h8300"
594 [(set (match_operand:SI 0 "register_operand" "=r")
595 (minus:SI (match_operand:SI 1 "register_operand" "0")
596 (match_operand:SI 2 "register_operand" "r")))]
598 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
599 [(set_attr "type" "arith")
600 (set_attr "length" "6")
601 (set_attr "cc" "clobber")])
603 ;; ??? 4 can be handled in one insn on the 300h.
605 (define_insn "subsi3_h8300h"
606 [(set (match_operand:SI 0 "register_operand" "=ra,ra,ra,r")
607 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
608 (match_operand:SI 2 "nonmemory_operand" "K,M,ra,n")))]
612 subs #2,%T0\;subs %E2,%T0
615 [(set_attr "type" "multi")
616 (set_attr "length" "2,4,2,6")
617 (set_attr "cc" "none_0hit,none_0hit,set_zn_c0,set_zn_c0")])
619 ;; ----------------------------------------------------------------------
620 ;; MULTIPLY INSTRUCTIONS
621 ;; ----------------------------------------------------------------------
623 ;; Note that the h8/300 can only handle umulqihi3.
625 (define_insn "mulqihi3"
626 [(set (match_operand:HI 0 "register_operand" "=r")
627 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
628 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
631 [(set_attr "type" "multi")
632 (set_attr "length" "4")
633 (set_attr "cc" "set_zn_c0")])
635 (define_insn "mulhisi3"
636 [(set (match_operand:SI 0 "register_operand" "=r")
637 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
638 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
641 [(set_attr "type" "multi")
642 (set_attr "length" "4")
643 (set_attr "cc" "set_zn_c0")])
645 (define_insn "umulqihi3"
646 [(set (match_operand:HI 0 "register_operand" "=r")
647 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
648 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
651 [(set_attr "type" "multi")
652 (set_attr "length" "2")
653 (set_attr "cc" "none_0hit")])
655 (define_insn "umulhisi3"
656 [(set (match_operand:SI 0 "register_operand" "=r")
657 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
658 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
661 [(set_attr "type" "multi")
662 (set_attr "length" "2")
663 (set_attr "cc" "none_0hit")])
665 ;; ----------------------------------------------------------------------
666 ;; DIVIDE INSTRUCTIONS
667 ;; ----------------------------------------------------------------------
669 (define_insn "udivqi3"
670 [(set (match_operand:QI 0 "register_operand" "=r")
671 (udiv:QI (match_operand:HI 1 "general_operand" "0")
672 (match_operand:QI 2 "register_operand" "r")))]
675 [(set_attr "type" "multi")
676 (set_attr "length" "2")
677 (set_attr "cc" "clobber")])
679 ;; ??? Will divxu always work here?
681 (define_insn "divqi3"
682 [(set (match_operand:QI 0 "register_operand" "=r")
683 (div:QI (match_operand:HI 1 "general_operand" "0")
684 (match_operand:QI 2 "register_operand" "r")))]
687 [(set_attr "type" "multi")
688 (set_attr "length" "2")
689 (set_attr "cc" "clobber")])
691 (define_insn "udivhi3"
692 [(set (match_operand:HI 0 "register_operand" "=r")
693 (udiv:HI (match_operand:SI 1 "general_operand" "0")
694 (match_operand:HI 2 "register_operand" "r")))]
697 [(set_attr "type" "multi")
698 (set_attr "length" "2")
699 (set_attr "cc" "clobber")])
701 (define_insn "divhi3"
702 [(set (match_operand:HI 0 "register_operand" "=r")
703 (div:HI (match_operand:SI 1 "general_operand" "0")
704 (match_operand:HI 2 "register_operand" "r")))]
707 [(set_attr "type" "multi")
708 (set_attr "length" "4")
709 (set_attr "cc" "clobber")])
711 ;; ----------------------------------------------------------------------
713 ;; ----------------------------------------------------------------------
715 (define_insn "umodqi3"
716 [(set (match_operand:QI 0 "register_operand" "=r")
717 (umod:QI (match_operand:HI 1 "general_operand" "0")
718 (match_operand:QI 2 "register_operand" "r")))]
720 "divxu %X2,%T0\;mov %t0,%s0"
721 [(set_attr "type" "multi")
722 (set_attr "length" "4")
723 (set_attr "cc" "clobber")])
725 (define_insn "modqi3"
726 [(set (match_operand:QI 0 "register_operand" "=r")
727 (mod:QI (match_operand:HI 1 "general_operand" "0")
728 (match_operand:QI 2 "register_operand" "r")))]
730 "divxs.b %X2,%T0\;mov %t0,%s0"
731 [(set_attr "type" "multi")
732 (set_attr "length" "6")
733 (set_attr "cc" "clobber")])
735 (define_insn "umodhi3"
736 [(set (match_operand:HI 0 "register_operand" "=r")
737 (umod:HI (match_operand:SI 1 "general_operand" "0")
738 (match_operand:HI 2 "register_operand" "r")))]
740 "divxu.w %T2,%S0\;mov %e0,%f0"
741 [(set_attr "type" "multi")
742 (set_attr "length" "4")
743 (set_attr "cc" "clobber")])
745 (define_insn "modhi3"
746 [(set (match_operand:HI 0 "register_operand" "=r")
747 (mod:HI (match_operand:SI 1 "general_operand" "0")
748 (match_operand:HI 2 "register_operand" "r")))]
750 "divxs.w %T2,%S0\;mov %e0,%f0"
751 [(set_attr "type" "multi")
752 (set_attr "length" "6")
753 (set_attr "cc" "clobber")])
755 ;; ----------------------------------------------------------------------
757 ;; ----------------------------------------------------------------------
759 (define_insn "andqi3_internal"
760 [(set (match_operand:QI 0 "bit_operand" "=r,U")
761 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
762 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
763 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
767 [(set_attr "type" "arith")
768 (set_attr "length" "2,4")
769 (set_attr "cc" "set,none_0hit")])
771 (define_expand "andqi3"
772 [(set (match_operand:QI 0 "bit_operand" "=r,U")
773 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
774 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
778 if (fix_bit_operand (operands, 'O', AND))
782 ;; ??? Should have a bclr case here also.
783 ;; ??? This should be symmetric with iorhi3.
785 (define_insn "andhi3"
786 [(set (match_operand:HI 0 "register_operand" "=r")
787 (and:HI (match_operand:HI 1 "register_operand" "%0")
788 (match_operand:HI 2 "nonmemory_operand" "rn")))]
792 if (GET_CODE (operands[2]) == CONST_INT)
794 int i = INTVAL (operands[2]);
795 if ((i & 0x00ff) != 0x00ff)
796 output_asm_insn (\"and %s2,%s0\", operands);
797 if ((i & 0xff00) != 0xff00)
798 output_asm_insn (\"and %t2,%t0\", operands);
801 return \"and %s2,%s0\;and %t2,%t0;\";
803 [(set_attr "type" "multi")
804 (set_attr "length" "4")
805 (set_attr "cc" "clobber")])
807 ;; ??? There is an iorsi3 for TARGET_H8300. Should we have andsi3?
809 (define_insn "andsi3"
810 [(set (match_operand:SI 0 "register_operand" "=r,r")
811 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
812 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
817 [(set_attr "type" "arith")
818 (set_attr "length" "4,6")
819 (set_attr "cc" "set")])
821 ;; ----------------------------------------------------------------------
823 ;; ----------------------------------------------------------------------
825 (define_insn "iorqi3_internal"
826 [(set (match_operand:QI 0 "bit_operand" "=U,r")
827 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
828 (match_operand:QI 2 "nonmemory_operand" "P,rn")))]
829 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
833 [(set_attr "type" "arith")
834 (set_attr "length" "4,2")
835 (set_attr "cc" "none_0hit,set")])
837 (define_expand "iorqi3"
838 [(set (match_operand:QI 0 "bit_operand" "=r,U")
839 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
840 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
844 if (fix_bit_operand (operands, 'P', IOR))
848 ;; ??? Should have a bset case here also.
849 ;; ??? This should be symmetric with andhi3.
851 (define_insn "iorhi3"
852 [(set (match_operand:HI 0 "general_operand" "=r,r")
853 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
854 (match_operand:HI 2 "general_operand" "J,rn")))]
860 if (GET_CODE (operands[2]) == CONST_INT)
862 int i = INTVAL (operands[2]);
863 if ((i & 0x00ff) != 0)
864 output_asm_insn (\"or %s2,%s0\", operands);
865 if ((i & 0xff00) != 0)
866 output_asm_insn (\"or %t2,%t0\", operands);
869 return \"or %s2,%s0\;or %t2,%t0; %2 or2\";
873 return \"or %S2,%S0\";
876 [(set_attr "type" "multi")
877 (set_attr "length" "2,4")
878 (set_attr "cc" "clobber,clobber")])
880 (define_insn "iorsi3"
881 [(set (match_operand:SI 0 "register_operand" "=r")
882 (ior:SI (match_operand:SI 1 "register_operand" "%0")
883 (match_operand:SI 2 "nonmemory_operand" "ri")))]
889 if (GET_CODE (operands[2]) == CONST_INT)
891 int i = INTVAL (operands[2]);
892 if ((i & 0x000000ff) != 0)
893 output_asm_insn (\"or %w2,%w0\", operands);
894 if ((i & 0x0000ff00) != 0)
895 output_asm_insn (\"or %x2,%x0\", operands);
896 if ((i & 0x00ff0000) != 0)
897 output_asm_insn (\"or %y2,%y0\", operands);
898 if ((i & 0xff000000) != 0)
899 output_asm_insn (\"or %z2,%z0\", operands);
902 return \"or %w2,%w0\;or %x2,%x0\;or %y2,%y0\;or %z2,%z0\;\";
906 return \"or %S2,%S0\";
909 [(set_attr "type" "multi")
910 (set_attr "length" "8")
911 (set_attr "cc" "clobber")])
913 ;; ----------------------------------------------------------------------
915 ;; ----------------------------------------------------------------------
917 (define_insn "xorqi3_internal"
918 [(set (match_operand:QI 0 "bit_operand" "=r,U")
919 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
920 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
921 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
925 [(set_attr "type" "arith")
926 (set_attr "length" "2,4")
927 (set_attr "cc" "set,none_0hit")])
929 (define_expand "xorqi3"
930 [(set (match_operand:QI 0 "bit_operand" "=r,U")
931 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
932 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
936 if (fix_bit_operand (operands, 'O', XOR))
940 ;; ??? This should be symmetric with andhi3.
942 (define_insn "xorhi3"
943 [(set (match_operand:HI 0 "register_operand" "=r")
944 (xor:HI (match_operand:HI 1 "general_operand" "%0")
945 (match_operand:HI 2 "nonmemory_operand" "rn")))]
950 return \"xor %s2,%s0\;xor %t2,%t0\";
952 return \"xor %S2,%S0\";
954 [(set_attr "type" "multi")
955 (set_attr "length" "4")
956 (set_attr "cc" "clobber")])
958 ;; ??? There is an iorsi3 for TARGET_H8300. Should we have xorsi3?
960 (define_insn "xorsi3"
961 [(set (match_operand:SI 0 "register_operand" "=r,r")
962 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
963 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
968 [(set_attr "type" "arith")
969 (set_attr "length" "4,6")
970 (set_attr "cc" "set")])
972 ;; ----------------------------------------------------------------------
973 ;; NEGATION INSTRUCTIONS
974 ;; ----------------------------------------------------------------------
976 (define_insn "negqi2"
977 [(set (match_operand:QI 0 "register_operand" "=r")
978 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
981 [(set_attr "type" "arith")
982 (set_attr "length" "2")
983 (set_attr "cc" "set_zn_c0")])
985 (define_expand "neghi2"
986 [(set (match_operand:HI 0 "register_operand" "=r")
987 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
993 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
998 (define_expand "neghi2_h8300"
1000 (not:HI (match_operand:HI 1 "register_operand" "r")))
1001 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1002 (set (match_operand:HI 0 "register_operand" "=r")
1005 "{ operands[2] = gen_reg_rtx (HImode); }")
1007 (define_insn "neghi2_h8300h"
1008 [(set (match_operand:HI 0 "register_operand" "=r")
1009 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1012 [(set_attr "type" "arith")
1013 (set_attr "length" "2")
1014 (set_attr "cc" "set_zn_c0")])
1016 (define_expand "negsi2"
1017 [(set (match_operand:SI 0 "register_operand" "=r")
1018 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1024 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1029 (define_expand "negsi2_h8300"
1031 (not:SI (match_operand:SI 1 "register_operand" "r")))
1032 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1033 (set (match_operand:SI 0 "register_operand" "=r")
1036 "{ operands[2] = gen_reg_rtx(SImode); }")
1038 (define_insn "negsi2_h8300h"
1039 [(set (match_operand:SI 0 "register_operand" "=r")
1040 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1043 [(set_attr "type" "arith")
1044 (set_attr "length" "2")
1045 (set_attr "cc" "set_zn_c0")])
1047 ;; ----------------------------------------------------------------------
1049 ;; ----------------------------------------------------------------------
1051 (define_insn "one_cmplqi2"
1052 [(set (match_operand:QI 0 "register_operand" "=r")
1053 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1056 [(set_attr "type" "arith")
1057 (set_attr "length" "2")
1058 (set_attr "cc" "set")])
1060 (define_insn "one_cmplhi2"
1061 [(set (match_operand:HI 0 "register_operand" "=r")
1062 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1067 return \"not %s0\;not %t0\";
1071 [(set_attr "type" "arith")
1072 (set_attr "length" "4")
1073 (set_attr "cc" "clobber")])
1075 (define_insn "one_cmplsi2"
1076 [(set (match_operand:SI 0 "register_operand" "=r")
1077 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1082 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1086 [(set_attr "type" "arith")
1087 ;; ??? length is wrong for 300h
1088 (set_attr "length" "8")
1089 (set_attr "cc" "clobber")])
1091 ;; ----------------------------------------------------------------------
1092 ;; JUMP INSTRUCTIONS
1093 ;; ----------------------------------------------------------------------
1095 ;; Conditional jump instructions
1097 (define_expand "ble"
1099 (if_then_else (le (cc0)
1101 (label_ref (match_operand 0 "" ""))
1106 (define_expand "bleu"
1108 (if_then_else (leu (cc0)
1110 (label_ref (match_operand 0 "" ""))
1115 (define_expand "bge"
1117 (if_then_else (ge (cc0)
1119 (label_ref (match_operand 0 "" ""))
1124 (define_expand "bgeu"
1126 (if_then_else (geu (cc0)
1128 (label_ref (match_operand 0 "" ""))
1133 (define_expand "blt"
1135 (if_then_else (lt (cc0)
1137 (label_ref (match_operand 0 "" ""))
1142 (define_expand "bltu"
1144 (if_then_else (ltu (cc0)
1146 (label_ref (match_operand 0 "" ""))
1151 (define_expand "bgt"
1153 (if_then_else (gt (cc0)
1155 (label_ref (match_operand 0 "" ""))
1160 (define_expand "bgtu"
1162 (if_then_else (gtu (cc0)
1164 (label_ref (match_operand 0 "" ""))
1169 (define_expand "beq"
1171 (if_then_else (eq (cc0)
1173 (label_ref (match_operand 0 "" ""))
1178 (define_expand "bne"
1180 (if_then_else (ne (cc0)
1182 (label_ref (match_operand 0 "" ""))
1187 (define_insn "branch_true"
1189 (if_then_else (match_operator 1 "comparison_operator"
1190 [(cc0) (const_int 0)])
1191 (label_ref (match_operand 0 "" ""))
1196 /* If we erroneously deleted a compare insn (which can happen if we need
1197 CC bits set that aren't), emit the compare. */
1198 if (restore_compare_p (operands[1]))
1201 if (get_attr_length (insn) == 2)
1202 return \"b%j1 %l0\";
1203 else if (get_attr_length (insn) == 4)
1204 return \"b%j1 %l0:16\";
1206 return \"b%k1 %L0\;jmp @%l0\;%L0:\";
1208 [(set_attr "type" "branch")
1209 (set_attr "cc" "none")])
1211 (define_insn "branch_false"
1213 (if_then_else (match_operator 1 "comparison_operator"
1214 [(cc0) (const_int 0)])
1216 (label_ref (match_operand 0 "" ""))))]
1218 ;; ??? We don't take advantage of 16 bit relative jumps in the 300h.
1221 /* If we erroneously deleted a compare insn (which can happen if we need
1222 CC bits set that aren't), emit the compare. */
1223 if (restore_compare_p (operands[1]))
1226 if (get_attr_length (insn) == 2)
1227 return \"b%k1 %l0\";
1228 else if (get_attr_length (insn) == 4)
1229 return \"b%k1 %l0:16\";
1231 return \"b%j1 %L0\;jmp @%l0\;%L0:\";
1233 [(set_attr "type" "branch")
1234 (set_attr "cc" "none")])
1236 ;; Unconditional and other jump instructions.
1240 (label_ref (match_operand 0 "" "")))]
1244 if (get_attr_length (insn) == 2)
1246 else if (get_attr_length (insn) == 4)
1247 return \"bra %l0:16\";
1249 return \"jmp @%l0\";
1251 [(set_attr "type" "branch")
1252 (set_attr "cc" "none")])
1254 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1256 (define_expand "tablejump"
1257 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1258 (use (label_ref (match_operand 1 "" "")))])]
1262 (define_insn "tablejump_h8300"
1263 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1264 (use (label_ref (match_operand 1 "" "")))]
1267 [(set_attr "type" "branch")
1268 (set_attr "cc" "none")
1269 (set_attr "length" "2")])
1271 (define_insn "tablejump_h8300h"
1272 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1273 (use (label_ref (match_operand 1 "" "")))]
1276 [(set_attr "type" "branch")
1277 (set_attr "cc" "none")
1278 (set_attr "length" "2")])
1280 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1282 (define_expand "indirect_jump"
1283 [(set (pc) (match_operand 0 "jump_address_operand" "Vr"))]
1287 (define_insn "indirect_jump_h8300"
1288 [(set (pc) (match_operand:HI 0 "jump_address_operand" "V,r"))]
1293 [(set_attr "type" "branch")
1294 (set_attr "cc" "none")
1295 (set_attr "length" "2")])
1297 (define_insn "indirect_jump_h8300h"
1298 [(set (pc) (match_operand:SI 0 "jump_address_operand" "V,r"))]
1303 [(set_attr "type" "branch")
1304 (set_attr "cc" "none")
1305 (set_attr "length" "2")])
1307 ;; Call subroutine with no return value.
1309 ;; ??? Even though we use HImode here, this works for the 300h.
1312 [(call (match_operand:QI 0 "call_insn_operand" "or")
1313 (match_operand:HI 1 "general_operand" "g"))]
1316 [(set_attr "type" "call")
1317 (set_attr "cc" "clobber")
1318 (set_attr "length" "4")])
1320 ;; Call subroutine, returning value in operand 0
1321 ;; (which must be a hard register).
1323 ;; ??? Even though we use HImode here, this works on the 300h.
1325 (define_insn "call_value"
1326 [(set (match_operand 0 "" "=r")
1327 (call (match_operand:QI 1 "call_insn_operand" "or")
1328 (match_operand:HI 2 "general_operand" "g")))]
1331 [(set_attr "type" "call")
1332 (set_attr "cc" "clobber")
1333 (set_attr "length" "4")])
1339 [(set_attr "type" "multi")
1340 (set_attr "cc" "none")
1341 (set_attr "length" "2")])
1343 ;; ----------------------------------------------------------------------
1344 ;; EXTEND INSTRUCTIONS
1345 ;; ----------------------------------------------------------------------
1347 (define_insn "zero_extendqihi2"
1348 [(set (match_operand:HI 0 "register_operand" "=r,r")
1349 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,g")))]
1353 if (which_alternative==0)
1354 return \"mov.b #0,%t0\";
1357 return \"mov.b %X1,%s0\;mov.b #0,%t0\";
1360 /* ??? See how often this gets optimized. */
1361 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1362 return \"extu.w %T0\";
1364 return \"mov.b %X1,%s0\;extu.w %T0\";
1367 [(set_attr "type" "multi")
1368 ;; ??? This length is wrong for one case.
1369 (set_attr "length" "4")
1370 (set_attr "cc" "clobber")])
1372 (define_insn "zero_extendhisi2"
1373 [(set (match_operand:SI 0 "register_operand" "=r")
1374 (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
1378 /* ??? See how often this gets optimized. */
1379 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1380 return \"extu.l %S0\";
1382 return \"mov.w %T1,%T0\;extu.l %S0\";
1384 [(set_attr "type" "multi")
1385 ;; ??? This length is wrong for one case.
1386 (set_attr "length" "4")
1387 (set_attr "cc" "clobber")])
1389 (define_insn "extendqihi2"
1390 [(set (match_operand:HI 0 "register_operand" "=r")
1391 (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
1397 /* ??? See how often this gets optimized. */
1398 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1399 return \"bld #7,%s0\;subx %t0,%t0\";
1401 return \"mov.b %X1,%s0\;bld #7,%s0\;subx %t0,%t0\";
1405 /* ??? See how often this gets optimized. */
1406 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1407 return \"exts.w %T0\";
1409 return \"mov.b %X1,%s0\;exts.w %T0\";
1412 [(set_attr "type" "multi")
1413 ;; ??? Length is wrong in some cases.
1414 (set_attr "length" "6")
1415 (set_attr "cc" "clobber")])
1417 (define_expand "extendhisi2"
1418 [(set (match_operand:SI 0 "register_operand" "")
1419 (sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
1424 emit_insn (gen_extendhisi2_h8300 (operands[0], operands[1]));
1426 emit_insn (gen_extendhisi2_h8300h (operands[0], operands[1]));
1430 (define_expand "extendhisi2_h8300"
1431 [(set (reg:HI 1) (match_operand:HI 1 "general_operand" ""))
1432 (set (reg:SI 0) (sign_extend:SI (reg:HI 1)))
1433 (set (match_operand:SI 0 "general_operand" "" ) (reg:SI 0))]
1437 (define_expand "extendhisi2_h8300h"
1438 [(set (match_operand:SI 0 "register_operand" "")
1439 (sign_extend:SI (match_operand:HI 1 "general_operand" "")))]
1443 (define_insn "extendhisi2_h8300_internal"
1444 [(set (match_operand:SI 0 "register_operand" "=r")
1445 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1447 "mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1448 [(set_attr "length" "10")
1449 (set_attr "cc" "clobber")])
1451 (define_insn "extendhisi2_h8300h_internal"
1452 [(set (match_operand:SI 0 "register_operand" "=r")
1453 (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
1457 /* ??? See how often this gets optimized. */
1458 if (REG_P (operands[1]) && (REGNO (operands[1]) == REGNO (operands[0])))
1459 return \"exts.l %S0\";
1461 return \"mov.w %T1,%T0\;exts.l %S0\";
1463 [(set_attr "length" "10")
1464 (set_attr "cc" "clobber")])
1466 ;; ----------------------------------------------------------------------
1468 ;; ----------------------------------------------------------------------
1470 ;; We make some attempt to provide real efficient shifting. One example is
1471 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1472 ;; reg and moving 0 into the former reg.
1474 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1475 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1476 ;; give the optimizer more cracks at the code. However, we wish to do things
1477 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1478 ;; There is rtl to handle this (rotate + and), but the h8/300 doesn't handle
1479 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1480 ;; to detect cases it can optimize.
1482 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1483 ;; easier "do it at insn emit time" route.
1487 (define_expand "ashlqi3"
1488 [(set (match_operand:QI 0 "register_operand" "")
1489 (ashift:QI (match_operand:QI 1 "register_operand" "")
1490 (match_operand:QI 2 "nonmemory_operand" "")))]
1492 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
1494 (define_expand "ashrqi3"
1495 [(set (match_operand:QI 0 "register_operand" "")
1496 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1497 (match_operand:QI 2 "nonmemory_operand" "")))]
1499 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
1501 (define_expand "lshrqi3"
1502 [(set (match_operand:QI 0 "register_operand" "")
1503 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1504 (match_operand:QI 2 "nonmemory_operand" "")))]
1506 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
1508 ;; WARNING: The constraints on the scratch register say one is not needed
1509 ;; for constant shifts of 1,2,3,4. Emit_a_shift() must know this.
1511 (define_insn "shiftbyn_QI"
1512 [(set (match_operand:QI 0 "register_operand" "=r,r")
1513 (match_operator:QI 3 "nshift_operator"
1514 [ (match_operand:QI 1 "register_operand" "0,0")
1515 (match_operand:QI 2 "nonmemory_operand" "IKM,rn")]))
1516 (clobber (match_scratch:QI 4 "=X,&r"))]
1518 "* return emit_a_shift (insn, operands);"
1519 [(set_attr "type" "arith")
1520 (set_attr "length" "20")
1521 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1522 ;; However, for cases that loop or are done in pieces, cc does not contain
1523 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1524 (set_attr "cc" "clobber")])
1528 (define_expand "ashlhi3"
1529 [(set (match_operand:HI 0 "register_operand" "")
1530 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1531 (match_operand:QI 2 "nonmemory_operand" "")))]
1533 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
1535 (define_expand "lshrhi3"
1536 [(set (match_operand:HI 0 "register_operand" "")
1537 (lshiftrt:HI (match_operand:HI 1 "general_operand_src" "")
1538 (match_operand:QI 2 "nonmemory_operand" "")))]
1540 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
1542 (define_expand "ashrhi3"
1543 [(set (match_operand:HI 0 "register_operand" "")
1544 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1545 (match_operand:QI 2 "nonmemory_operand" "")))]
1547 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
1549 ;; WARNING: The constraints on the scratch register say one is not needed
1550 ;; for constant shifts of 1,2,3,4. Emit_a_shift() must know this.
1552 (define_insn "shiftbyn_HI"
1553 [(set (match_operand:HI 0 "register_operand" "=r,r")
1554 (match_operator:HI 3 "nshift_operator"
1555 [ (match_operand:HI 1 "register_operand" "0,0")
1556 (match_operand:QI 2 "nonmemory_operand" "IKM,rn")]))
1557 (clobber (match_scratch:QI 4 "=X,&r"))]
1559 "* return emit_a_shift (insn, operands);"
1560 [(set_attr "type" "arith")
1561 (set_attr "length" "20")
1562 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1563 ;; However, for cases that loop or are done in pieces, cc does not contain
1564 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1565 (set_attr "cc" "clobber")])
1569 (define_expand "ashlsi3"
1570 [(set (match_operand:SI 0 "register_operand" "")
1572 (match_operand:SI 1 "general_operand_src" "")
1573 (match_operand:QI 2 "nonmemory_operand" "")))]
1575 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
1577 (define_expand "lshrsi3"
1578 [(set (match_operand:SI 0 "register_operand" "")
1580 (match_operand:SI 1 "general_operand_src" "")
1581 (match_operand:QI 2 "nonmemory_operand" "")))]
1583 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
1585 (define_expand "ashrsi3"
1586 [(set (match_operand:SI 0 "register_operand" "")
1588 (match_operand:SI 1 "general_operand_src" "")
1589 (match_operand:QI 2 "nonmemory_operand" "")))]
1591 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
1593 ;; WARNING: The constraints on the scratch register say one is not needed
1594 ;; for constant shifts of 1,2. Emit_a_shift() must know this.
1596 (define_insn "shiftbyn_SI"
1597 [(set (match_operand:SI 0 "register_operand" "=r,r")
1598 (match_operator:SI 3 "nshift_operator"
1599 [ (match_operand:SI 1 "register_operand" "0,0")
1600 (match_operand:QI 2 "nonmemory_operand" "IK,rn")]))
1601 (clobber (match_scratch:QI 4 "=X,&r"))]
1603 "* return emit_a_shift (insn, operands);"
1604 [(set_attr "type" "arith")
1605 (set_attr "length" "20")
1606 ;; ??? We'd like to indicate that cc is set here, and it is for simple shifts.
1607 ;; However, for cases that loop or are done in pieces, cc does not contain
1608 ;; what we want. Emit_a_shift is free to tweak cc_status as desired.
1609 (set_attr "cc" "clobber")])
1611 ;; -----------------------------------------------------------------
1613 ;; -----------------------------------------------------------------
1614 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1615 ;; instructions so let's use them as well as we can.
1617 ;; BCC and BCS patterns.
1619 (define_insn "bcs_qiqi"
1622 (match_operator 1 "eq_operator"
1623 [(zero_extract:QI (match_operand:QI 2 "bit_operand" "Ur")
1625 (match_operand:HI 3 "immediate_operand" "i"))
1627 (label_ref (match_operand 0 "" ""))
1632 output_asm_insn(\"bld %Z3,%Y2\", operands);
1633 if (get_attr_length (insn) == 2)
1634 return \"b%d1 %l0\";
1635 else if (get_attr_length (insn) == 4)
1636 return \"b%d1 %l0:16\";
1638 return \"b%g1 %L0\;jmp @%l0\;%L0:\";
1640 [(set_attr "type" "branch")
1641 (set_attr "cc" "clobber")])
1643 (define_insn "bcs_hihi"
1646 (match_operator 1 "eq_operator"
1647 [(zero_extract:HI (match_operand:HI 2 "bit_operand" "Ur")
1649 (match_operand:HI 3 "immediate_operand" "i"))
1651 (label_ref (match_operand 0 "" ""))
1656 output_asm_insn(\"bld %Z3,%Y2\", operands);
1657 if (get_attr_length (insn) == 2)
1659 else if (get_attr_length (insn) == 4)
1660 return \"%d1 %l0:16\";
1662 return \"%g1 %L0\;jmp @%l0\;%L0:\";
1664 [(set_attr "type" "branch")
1665 (set_attr "cc" "clobber")])
1667 (define_insn "bcs_hiqi"
1670 (match_operator 1 "eq_operator"
1671 [(zero_extract:HI (match_operand:QI 2 "bit_operand" "Ur")
1673 (match_operand:HI 3 "immediate_operand" "i"))
1675 (label_ref (match_operand 0 "" ""))
1680 output_asm_insn(\"bld %Z3,%Y2\", operands);
1681 if (get_attr_length (insn) == 2)
1683 else if (get_attr_length (insn) == 4)
1684 return \"%d1 %l0:16\";
1686 return \"%g1 %L0\;jmp @%l0\;%L0:\";
1688 [(set_attr "type" "branch")
1689 (set_attr "cc" "clobber")])
1691 ;; BLD and BST patterns
1693 (define_insn "extract_1"
1694 [(set (match_operand:HI 0 "register_operand" "=&r")
1695 (zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur")
1697 (match_operand:HI 2 "immediate_operand" "i")))]
1699 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0")
1701 (define_insn "extract_1_hi"
1702 [(set (match_operand:HI 0 "register_operand" "=&r")
1703 (zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur")
1705 (match_operand:HI 2 "immediate_operand" "i")))]
1707 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0")
1709 (define_insn "insert_1"
1710 [(set (zero_extract:HI (match_operand:QI 0 "bit_operand" "+Ur")
1712 (match_operand:HI 1 "immediate_operand" "i"))
1713 (zero_extract:HI (match_operand:QI 2 "bit_operand" "Ur")
1717 "bld #0,%X2\;bst %Z1,%Y0 ; i1")
1719 ;; This is how combine canonicalizes this pattern. This is perhaps a bug
1720 ;; in combine.c, but there is no problem with writing it this way so we do.
1721 (define_insn "extract_insert_1"
1722 [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "+Ur")
1724 (match_operand:HI 1 "immediate_operand" "i"))
1725 (lshiftrt:QI (match_operand:QI 2 "bit_operand" "Ur")
1726 (match_operand:HI 3 "immediate_operand" "i")))]
1728 "bld %Z3,%Y2\;bst %Z1,%Y0; ei1")
1730 ;; BAND, BOR, and BXOR patterns
1732 (define_insn "bitlogical_1"
1733 [(set (match_operand:HI 0 "bit_operand" "=Ur")
1734 (match_operator:HI 4 "bit_operator"
1735 [(zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur")
1737 (match_operand:HI 2 "immediate_operand" "i"))
1738 (match_operand:HI 3 "bit_operand" "0")]))]
1740 "bld %Z2,%Y1\;%b4 #0,%X0\;bst #0,%X0; bl1")
1742 (define_insn "bitlogical_1_hi"
1743 [(set (match_operand:HI 0 "bit_operand" "=Ur")
1744 (match_operator:HI 4 "bit_operator"
1745 [(zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur")
1747 (match_operand:HI 2 "immediate_operand" "i"))
1748 (match_operand:HI 3 "bit_operand" "0")]))]
1750 "bld %Z2,%Y1\;%b4 #0,%X0\;bst #0,%X0; bl2")
1752 (define_insn "bitlogical_2"
1753 [(set (match_operand:HI 0 "bit_operand" "=Ur")
1754 (match_operator:HI 5 "bit_operator"
1755 [(zero_extract:HI (match_operand:QI 1 "bit_operand" "Ur")
1757 (match_operand:HI 2 "immediate_operand" "i"))
1758 (zero_extract:HI (match_operand:QI 3 "bit_operand" "Ur")
1760 (match_operand:HI 4 "immediate_operand" "i"))]))]
1762 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%X0; bl3")
1764 (define_insn "bitlogical_2_hi"
1765 [(set (match_operand:HI 0 "bit_operand" "=Ur")
1766 (match_operator:HI 5 "bit_operator"
1767 [(zero_extract:HI (match_operand:HI 1 "bit_operand" "Ur")
1769 (match_operand:HI 2 "immediate_operand" "i"))
1770 (zero_extract:HI (match_operand:HI 3 "bit_operand" "Ur")
1772 (match_operand:HI 4 "immediate_operand" "i"))]))]
1774 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%X0; bl3")
1776 ;; This is how combine canonicalizes this pattern. This is perhaps a bug
1777 ;; in combine.c, but there is no problem with writing it this way so we do.
1778 (define_insn "bitlogical_3"
1779 [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "+Ur")
1781 (match_operand:HI 1 "immediate_operand" "i"))
1782 (match_operator:QI 6 "bit_operator"
1783 [(lshiftrt:QI (match_operand:QI 2 "bit_operand" "Ur")
1784 (match_operand:HI 3 "immediate_operand" "i"))
1785 (lshiftrt:QI (match_operand:QI 4 "bit_operand" "Ur")
1786 (match_operand:HI 5 "immediate_operand" "i"))]))]
1788 "bld %Z3,%Y2\;%b6 %Z5,%Y4\;bst %Z1,%Y0; bl5")
1790 ;; This is how combine canonicalizes this pattern. This is perhaps a bug
1791 ;; in combine.c, but there is no problem with writing it this way so we do.
1792 (define_insn "bitnot_1"
1793 [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "=Ur")
1795 (match_operand:HI 1 "immediate_operand" "i"))
1796 (lshiftrt:QI (xor:QI (match_operand:QI 2 "bit_operand" "0")
1797 (match_operand:HI 3 "immediate_operand" "i"))
1798 (match_operand:HI 4 "immediate_operand" "1")))]
1799 "GET_CODE (operands[3]) == CONST_INT && GET_CODE (operands[1]) == CONST_INT
1800 && exact_log2 (INTVAL (operands[3])) == INTVAL (operands[1])"
1803 ;; ??? Implement BIAND, BIOR, BIXOR
1805 ;; ??? Implement BILD, BIST
1807 ;; ??? Apparently general_operand for the 1st and 2nd operands is useful,
1808 ;; but I don't know why. --Jim
1810 (define_expand "insv"
1811 [(set (zero_extract:HI (match_operand:QI 0 "bit_operand" "Ur")
1812 (match_operand:HI 1 "general_operand" "g")
1813 (match_operand:HI 2 "general_operand" "g"))
1814 (zero_extract:HI (match_operand:QI 3 "bit_operand" "Ur")
1817 ;; ??? This should have word mode which is SImode for the h8/300h.
1821 if (INTVAL (operands[1]) != 1)
1825 This INSV pattern is wrong. It should use HImode for operand 3.
1826 Also, the zero_extract around operand 3 is superfluous and should be
1827 deleted. Fixing this is more work than we care to do for the moment,
1828 because it means most of the above patterns would need to be rewritten,
1829 and we also need more combine.c patches to make this work.
1831 So, for now, we work around this bug by simply not accepting any bitfield
1832 inserts that have a position greater than fits in QImode. */
1834 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 8)
1837 /* The bit_operand predicate accepts any memory during RTL generation, but
1838 only 'U' memory afterwards, so if this is a MEM operand, we must force
1839 it to be valid for 'U' by reloading the address. */
1841 if (GET_CODE (operands[0]) == MEM && ! EXTRA_CONSTRAINT (operands[0], 'U'))
1844 mem = gen_rtx (MEM, GET_MODE (operands[0]),
1845 copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
1846 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[0]);
1847 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[0]);
1848 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[0]);
1852 /* Likewise for operands[3]. */
1854 if (GET_CODE (operands[3]) == MEM && ! EXTRA_CONSTRAINT (operands[3], 'U'))
1857 mem = gen_rtx (MEM, GET_MODE (operands[3]),
1858 copy_to_mode_reg (Pmode, XEXP (operands[3], 0)));
1859 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[3]);
1860 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[3]);
1861 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[3]);
1866 ;; ??? Apparently general_operand for the 2nd and 3rd operands is useful,
1867 ;; but I don't know why. --Jim
1869 (define_expand "extzv"
1870 [(set (match_operand:HI 0 "register_operand" "")
1871 (zero_extract:HI (match_operand:QI 1 "bit_operand" "")
1872 (match_operand:HI 2 "general_operand" "g")
1873 (match_operand:HI 3 "general_operand" "g")))]
1874 ;; ??? This should have word mode which is SImode for the h8/300h.
1878 if (INTVAL (operands[2]) != 1)
1881 /* The bit_operand predicate accepts any memory during RTL generation, but
1882 only 'U' memory afterwards, so if this is a MEM operand, we must force
1883 it to be valid for 'U' by reloading the address. */
1885 if (GET_CODE (operands[1]) == MEM && ! EXTRA_CONSTRAINT (operands[1], 'U'))
1888 mem = gen_rtx (MEM, GET_MODE (operands[1]),
1889 copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
1890 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[1]);
1891 MEM_IN_STRUCT_P (mem) = MEM_IN_STRUCT_P (operands[1]);
1892 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (operands[1]);
1897 ;; -----------------------------------------------------------------
1898 ;; STACK POINTER MANIPULATIONS
1899 ;; -----------------------------------------------------------------
1901 ;; This pattern is needed because there is no way on the H8/300
1902 ;; to add a 16 bit immediate value to the stack pointer in one
1903 ;; instruction, which could leave an invalid instruction if interrupted
1904 ;; half way through. Here we add to the stack pointer from a
1907 (define_insn "stack_pointer_manip"
1908 [(set (match_operand:HI 0 "register_operand" "=&ra")
1909 (plus:HI (match_operand:HI 1 "general_operand_src" "g")
1910 (match_operand:HI 2 "register_operand" "ra")))]
1912 "mov.w %T1,%T0\;add.w %T2,%T0"
1913 [(set_attr "type" "arith")
1914 (set_attr "length" "6")
1915 (set_attr "cc" "set_zn_c0")])
1918 ;; -------------------------------------------
1920 ;; -------------------------------------------
1922 (define_expand "movstrhi"
1923 [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
1924 (mem:BLK (match_operand:BLK 1 "general_operand" "")))
1925 (use (match_operand:HI 2 "general_operand" ""))
1926 (use (match_operand:HI 3 "immediate_operand" ""))
1927 (clobber (match_dup 3))
1932 rtx src_ptr = copy_to_mode_reg (Pmode, XEXP(operands[1], 0));
1933 rtx dst_ptr = copy_to_mode_reg (Pmode, XEXP(operands[0], 0));
1935 int max = GET_CODE (operands[2]) == CONST_INT
1936 ? MIN (INTVAL (operands[2]), INTVAL (operands[3])) : 1;
1937 enum machine_mode mode = max >= 2 ? HImode : QImode;
1938 rtx tmpreg = gen_reg_rtx (mode);
1939 rtx increment = mode == QImode ? const1_rtx : const2_rtx;
1940 rtx length = operands[2];
1941 rtx label = gen_label_rtx ();
1942 rtx end_src_ptr = gen_reg_rtx (Pmode);
1944 /* emit_move_insn (length, gen_rtx(MINUS, HImode, length, increment));*/
1946 if (Pmode == HImode)
1947 emit_insn (gen_addhi3 (end_src_ptr, src_ptr, length));
1949 emit_insn (gen_addsi3 (end_src_ptr, src_ptr, length));
1952 emit_move_insn (tmpreg, gen_rtx (MEM, mode, src_ptr));
1953 emit_move_insn (gen_rtx (MEM, mode, dst_ptr), tmpreg);
1954 emit_insn (gen_rtx (SET, VOIDmode, src_ptr,
1955 gen_rtx (PLUS, Pmode, src_ptr, increment)));
1956 emit_insn (gen_rtx (SET, VOIDmode, dst_ptr,
1957 gen_rtx (PLUS, Pmode, dst_ptr, increment)));
1959 emit_insn (gen_rtx (SET, VOIDmode, cc0_rtx,
1960 gen_rtx (COMPARE, Pmode, src_ptr, end_src_ptr)));
1961 emit_jump_insn (gen_bne (label));
1966 ;; ----------------------------------------------
1967 ;; Peepholes go at the end.
1968 ;; ----------------------------------------------
1970 ;; Notice when two byte moves in a row could be a word move.
1973 [(set (match_operand:QI 0 "register_operand" "=r")
1974 (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra")
1975 (match_operand:HI 2 "immediate_operand" "n"))))
1976 (set (match_operand:QI 3 "register_operand" "=r")
1977 (mem:QI (plus:HI (match_dup 1)
1978 (match_operand:HI 4 "immediate_operand" "n"))))]
1979 "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
1980 "mov.w @(%u4,%T1),%T0"
1981 [(set_attr "length" "6")
1982 (set_attr "cc" "set")])
1985 [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "ra")
1986 (match_operand:HI 2 "immediate_operand" "n")))
1987 (match_operand:QI 0 "register_operand" "r"))
1988 (set (mem:QI (plus:HI (match_dup 1)
1989 (match_operand:HI 4 "immediate_operand" "n")))
1990 (match_operand:QI 3 "register_operand" "r"))]
1991 "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
1992 "mov.w %T0,@(%u4,%T1)"
1993 [(set_attr "length" "6")
1994 (set_attr "cc" "set")])
1996 ;; Notice a move which could be post incremented.
1999 [(set (match_operand:QI 0 "register_operand" "")
2000 (mem:QI (match_operand:HI 1 "register_operand" "")))
2001 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 1)))]
2002 "REGNO(operands[1]) != REGNO(operands[0])"
2004 [(set_attr "length" "2")
2005 (set_attr "cc" "set")])
2008 [(set (match_operand:HI 0 "register_operand" "")
2009 (mem:HI (match_operand:HI 1 "register_operand" "")))
2010 (set (match_dup 1) (plus:HI (match_dup 1) (const_int 2)))]
2011 "REGNO(operands[1]) != REGNO(operands[0])"
2013 [(set_attr "length" "2")
2014 (set_attr "cc" "set")])
2016 ;; Notice a move which could be predecremented.
2019 [(set (match_operand:HI 1 "register_operand" "")
2020 (plus:HI (match_dup 1) (const_int -1)))
2021 (set (mem:QI (match_dup 1))
2022 (match_operand:QI 0 "register_operand" ""))]
2023 "REGNO(operands[1]) != REGNO(operands[0])"
2025 [(set_attr "length" "2")
2026 (set_attr "cc" "set")])
2029 [(set (match_operand:HI 1 "register_operand" "")
2030 (plus:HI (match_dup 1) (const_int -1)))
2031 (set (mem:HI (match_dup 1))
2032 (match_operand:HI 0 "register_operand" ""))]
2033 "REGNO(operands[1]) != REGNO(operands[0])"
2035 [(set_attr "length" "2")
2036 (set_attr "cc" "set")])
2039 ; [(set (match_operand:HI 0 "register_operand" "=r")
2040 ; (MEM:HI (match_operand:HI 1 "register_operand" "r")))
2041 ; (set (match_operand:HI 3 "register_operand" "=r")
2042 ; (zero_extract:HI (match_dup 0)
2044 ; (match_operand:HI 2 "general_operand" "g")))
2045 ; (set (MEM:HI (match_dup 1) (match_dup 3)))]
2047 ; "bld #0,%3l\;bst %Z2,%0%Y1"
2048 ; [(set_attr "type" "multi")
2049 ; (set_attr "length" "4")
2050 ; (set_attr "cc" "clobber")])
2052 (define_insn "fancybset1"
2053 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2055 (ashift:HI (const_int 1)
2056 (subreg:QI (match_operand:HI 1 "register_operand" "ri") 0)) 0)
2061 (define_insn "fancybset"
2062 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2064 (ashift:HI (const_int 1)
2065 (match_operand:HI 1 "nonmemory_operand" "ri") ) 0)
2066 (match_operand:QI 2 "general_operand" "Ur")))]
2068 "mov.b %X2,%X0\;bset %X1,%X0")
2070 (define_insn "fancybclr4"
2071 [(set (match_operand:QI 0 "general_operand" "=Ur,Ur")
2074 (rotate:HI (const_int -2)
2075 (match_operand:HI 2 "nonmemory_operand" "ri,ri") ) 0)
2076 (match_operand:QI 1 "general_operand" "0,Ur")))
2077 (clobber (match_scratch:HI 3 "=X,&r"))]
2081 mov.b %X1,%X3\;mov.b %3,%0\;bclr %X2,%X0; l3")
2083 (define_insn "fancybclr5"
2084 [(set (match_operand:QI 0 "general_operand" "=Ur,Ur")
2087 (rotate:HI (const_int -2)
2088 (match_operand:QI 2 "nonmemory_operand" "ri,ri")) 0)
2089 (match_operand:QI 1 "general_operand" "0,Ur")))
2090 (clobber (match_scratch:HI 3 "=X,&r"))]
2094 mov.b %X1,%X3\;mov.b %3,%0\;bclr %X2,%X0;l2")
2096 (define_insn "fancybclr2"
2097 [(set (match_operand:QI 0 "general_operand" "=U,r")
2100 (rotate:HI (const_int -2)
2101 (match_operand:HI 2 "nonmemory_operand" "ri,ri") ) 0)
2102 (match_operand:QI 1 "general_operand" "0,0")))]
2106 (define_insn "fancybclr3"
2107 [(set (match_operand:QI 0 "general_operand" "=U,r")
2110 (rotate:HI (const_int -2)
2111 (match_operand:QI 2 "nonmemory_operand" "ri,ri")) 0)
2112 (match_operand:QI 1 "general_operand" "0,0")))]
2116 (define_insn "fancybclr"
2117 [(set (match_operand:QI 0 "general_operand" "=r")
2118 (and:QI (not:QI (match_operand:QI 1 "general_operand" "0"))
2119 (match_operand:QI 2 "general_operand" "r")))]
2121 "not %X0\;and %X2,%X0")
2123 (define_insn "fancybsetp3"
2124 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2125 (ior:QI (subreg:QI (ashift:HI (const_int 1)
2126 (match_operand:QI 1 "register_operand" "r")) 0)
2127 (match_operand:QI 2 "bit_operand" "0")))]
2131 (define_insn "fancybsetp2"
2132 [(set (match_operand:QI 0 "general_operand" "=r,U")
2133 (ior:QI (subreg:QI (ashift:HI (const_int 1)
2134 (match_operand:QI 1 "register_operand" "r,r")) 0)
2135 (match_operand:QI 2 "general_operand" "U,r")))]
2137 "mov.b %X2,%X0\;bset %X1,%X0")
2139 (define_insn "fancybnot"
2140 [(set (match_operand:QI 0 "bit_operand" "=Ur")
2141 (xor:QI (subreg:QI (ashift:HI (const_int 1)
2142 (match_operand:QI 1 "register_operand" "r")) 0)
2143 (match_operand:QI 2 "bit_operand" "0")))]
2148 (define_insn "fancy_btst"
2150 (if_then_else (eq (zero_extract:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "Ur"))
2152 (match_operand:HI 2 "nonmemory_operand" "rn"))
2154 (label_ref (match_operand 0 "" ""))
2159 if (get_attr_length (insn) == 2)
2160 return \"btst %X2,%X1\;beq %l0\";
2161 else if (get_attr_length (insn) == 4)
2162 return \"btst %X2,%X1\;beq %l0:16\";
2164 return \"btst %X2,%X1\;bne %L1\;jmp @%l0\;%L1:\";
2166 [(set_attr "type" "branch")
2167 (set_attr "cc" "clobber")])
2169 (define_insn "fancy_btst1"
2171 (if_then_else (ne (zero_extract:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "Ur"))
2173 (match_operand:HI 2 "nonmemory_operand" "rn"))
2175 (label_ref (match_operand 0 "" ""))
2180 if (get_attr_length (insn) == 2)
2181 return \"btst %X2,%X1\;bne %l0\";
2182 else if (get_attr_length (insn) == 4)
2183 return \"btst %X2,%X1\;bne %l0:16\";
2185 return \"btst %X2,%X1\;beq %L1\;jmp @%l0\;%L1:\";
2187 [(set_attr "type" "branch")
2188 (set_attr "cc" "clobber")])
2191 [(set (zero_extract:QI (match_operand:QI 0 "bit_operand" "=r,U")
2193 (match_operand 1 "immediate_operand" "n,n"))
2194 (and:QI (not:QI (match_operand:QI 2 "bit_operand" "r,U"))
2197 "bld #0,%X2\;bist %1,%0"
2198 [(set_attr "type" "arith")
2199 (set_attr "length" "4")
2200 (set_attr "cc" "clobber")])