1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 (define_attr "cpu" "h8300,h8300h"
31 (const (symbol_ref "cpu_type")))
33 ;; Many logical operations should have "bit" variants if only one
34 ;; bit is going to be operated on.
36 ;; (and (logical op) (const_int X))
37 ;; If const_int only specifies a few bits (like a single byte in a 4 byte
38 ;; operation, then it's more efficient to only apply the and and logical_op
39 ;; to the bits we care about.
41 ;; Some of the extend instructions accept a general_operand_src, which
42 ;; allows all the normal memory addressing modes. The length computations
43 ;; don't take this into account. The lengths in the MD file should be
44 ;; "worst case" and then be adjusted to their correct values by
45 ;; h8300_adjust_insn_length.
47 ;; On the h8300h, adds/subs operate on the 32bit "er" registers. Right
48 ;; now GCC doesn't expose the "e" half to the compiler, so using add/subs
49 ;; for addhi and subhi is safe.
50 ;; Long term, we want to expose the "e" half to the compiler (gives us
51 ;; 8 more 16bit registers). At that point addhi and subhi can't use adds/subs.
53 ;; There's currently no way to have a insv/extzv expander for the H8/300H
54 ;; because word_mode is different for the H8/300 and H8/300H.
56 ;; Shifts/rotates by small constants should be handled by special
57 ;; patterns so we get the length and cc status correct.
59 ;; Bitfield operations no longer accept memory operands. We need
60 ;; to add variants which operate on memory back to the MD.
62 ;; ??? Implement remaining bit ops available on the h8300
64 (define_attr "type" "branch,arith"
65 (const_string "arith"))
67 ;; The size of instructions in bytes.
69 (define_attr "length" ""
70 (cond [(eq_attr "type" "branch")
71 (if_then_else (and (ge (minus (pc) (match_dup 0))
73 (le (minus (pc) (match_dup 0))
76 (if_then_else (and (eq_attr "cpu" "h8300h")
77 (and (ge (minus (pc) (match_dup 0))
79 (le (minus (pc) (match_dup 0))
85 ;; The necessity of instruction length adjustment.
87 (define_attr "adjust_length" "yes,no"
88 (cond [(eq_attr "type" "branch") (const_string "no")]
89 (const_string "yes")))
91 ;; Condition code settings.
92 ;; none - insn does not affect cc
93 ;; none_0hit - insn does not affect cc but it does modify operand 0
94 ;; This attribute is used to keep track of when operand 0 changes.
95 ;; See the description of NOTICE_UPDATE_CC for more info.
96 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
97 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
98 ;; compare - compare instruction
99 ;; clobber - value of cc is unknown
100 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
101 (const_string "clobber"))
103 ;; ----------------------------------------------------------------------
105 ;; ----------------------------------------------------------------------
109 (define_insn "pushqi1_h8300"
110 [(parallel [(set (reg:HI 7)
111 (plus:HI (reg:HI 7) (const_int -2)))
112 (set (mem:QI (plus:HI (reg:HI 7) (const_int -1)))
113 (match_operand:QI 0 "register_operand" "r"))])]
116 [(set_attr "length" "2")
117 (set_attr "cc" "clobber")])
119 (define_insn "pushqi1_h8300hs"
120 [(parallel [(set (reg:SI 7)
121 (plus:SI (reg:SI 7) (const_int -4)))
122 (set (mem:QI (plus:SI (reg:SI 7) (const_int -3)))
123 (match_operand:QI 0 "register_operand" "r"))])]
124 "TARGET_H8300H || TARGET_H8300S"
126 [(set_attr "length" "4")
127 (set_attr "cc" "clobber")])
129 (define_expand "pushqi1"
130 [(use (match_operand:QI 0 "register_operand" "r"))]
135 emit_insn (gen_pushqi1_h8300 (operands[0]));
137 emit_insn (gen_pushqi1_h8300hs (operands[0]));
142 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
143 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
145 && (register_operand (operands[0],QImode)
146 || register_operand (operands[1], QImode))"
154 [(set_attr "length" "2,2,2,2,4,4")
155 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
158 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
159 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
160 "(TARGET_H8300H || TARGET_H8300S)
161 && (register_operand (operands[0],QImode)
162 || register_operand (operands[1], QImode))"
170 [(set_attr "length" "2,2,2,2,8,8")
171 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
173 (define_expand "movqi"
174 [(set (match_operand:QI 0 "general_operand_dst" "")
175 (match_operand:QI 1 "general_operand_src" ""))]
179 /* One of the ops has to be in a register. */
180 if (!register_operand (operand0, QImode)
181 && !register_operand (operand1, QImode))
183 operands[1] = copy_to_mode_reg (QImode, operand1);
187 (define_insn "movstrictqi"
188 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
189 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
196 [(set_attr_alternative "length"
197 [(const_int 2) (const_int 2) (const_int 2)
198 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
199 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
203 (define_expand "pushhi1_h8300"
204 [(set (mem:QI (pre_dec:HI (reg:HI 7)))
205 (match_operand:QI 0 "register_operand" "r"))]
209 (define_insn "pushhi1_h8300hs"
210 [(parallel [(set (reg:SI 7)
211 (plus:SI (reg:SI 7) (const_int -4)))
212 (set (mem:HI (plus:SI (reg:SI 7) (const_int -2)))
213 (match_operand:HI 0 "register_operand" "r"))])]
214 "TARGET_H8300H || TARGET_H8300S"
216 [(set_attr "length" "4")
217 (set_attr "cc" "clobber")])
219 (define_expand "pushhi1"
220 [(use (match_operand:QI 0 "register_operand" "r"))]
225 emit_insn (gen_pushhi1_h8300 (operands[0]));
227 emit_insn (gen_pushhi1_h8300hs (operands[0]));
232 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
233 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
235 && (register_operand (operands[0],HImode)
236 || register_operand (operands[1], HImode))
237 && !(GET_CODE (operands[0]) == MEM
238 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
239 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
240 && GET_CODE (operands[1]) == REG
241 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
249 [(set_attr "length" "2,2,2,4,4,4")
250 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
253 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
254 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
255 "(TARGET_H8300H || TARGET_H8300S)
256 && (register_operand (operands[0],HImode)
257 || register_operand (operands[1], HImode))"
265 [(set_attr "length" "2,2,2,4,8,8")
266 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
268 (define_expand "movhi"
269 [(set (match_operand:HI 0 "general_operand_dst" "")
270 (match_operand:HI 1 "general_operand_src" ""))]
274 /* One of the ops has to be in a register. */
275 if (!register_operand (operand1, HImode)
276 && !register_operand (operand0, HImode))
278 operands[1] = copy_to_mode_reg (HImode, operand1);
282 (define_insn "movstricthi"
283 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
284 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
291 [(set_attr_alternative "length"
292 [(const_int 2) (const_int 2) (const_int 4)
293 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
294 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
298 (define_expand "movsi"
299 [(set (match_operand:SI 0 "general_operand_dst" "")
300 (match_operand:SI 1 "general_operand_src" ""))]
306 if (do_movsi (operands))
311 /* One of the ops has to be in a register. */
312 if (!register_operand (operand1, SImode)
313 && !register_operand (operand0, SImode))
315 operands[1] = copy_to_mode_reg (SImode, operand1);
320 (define_expand "movsf"
321 [(set (match_operand:SF 0 "general_operand_dst" "")
322 (match_operand:SF 1 "general_operand_src" ""))]
328 if (do_movsi (operands))
333 /* One of the ops has to be in a register. */
334 if (!register_operand (operand1, SFmode)
335 && !register_operand (operand0, SFmode))
337 operands[1] = copy_to_mode_reg (SFmode, operand1);
342 (define_insn "movsi_h8300"
343 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
344 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
346 && (register_operand (operands[0], SImode)
347 || register_operand (operands[1], SImode))"
351 switch (which_alternative)
354 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
356 if (REGNO (operands[0]) < REGNO (operands[1]))
357 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
359 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
361 /* Make sure we don't trample the register we index with. */
362 if (GET_CODE (operands[1]) == MEM)
364 rtx inside = XEXP (operands[1],0);
369 else if (GET_CODE (inside) == PLUS)
371 rtx lhs = XEXP (inside,0);
372 rtx rhs = XEXP (inside,1);
373 if (REG_P (lhs)) rn = REGNO (lhs);
374 if (REG_P (rhs)) rn = REGNO (rhs);
377 if (rn == REGNO (operands[0]))
379 /* Move the second word first. */
380 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
384 /* See if either half is zero. If so, use sub.w to clear
386 if (GET_CODE (operands[1]) == CONST_INT)
388 if ((INTVAL (operands[1]) & 0xffff) == 0)
389 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
390 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
391 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
393 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
396 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
398 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
400 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
405 [(set_attr "length" "4,4,8,8,4,4")
406 (set_attr "cc" "clobber")])
408 (define_insn "movsf_h8300"
409 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
410 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
412 && (register_operand (operands[0], SFmode)
413 || register_operand (operands[1], SFmode))"
416 /* Copy of the movsi stuff. */
418 switch (which_alternative)
421 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
423 if (REGNO (operands[0]) < REGNO (operands[1]))
424 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
426 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
428 /* Make sure we don't trample the register we index with. */
429 if (GET_CODE (operands[1]) == MEM)
431 rtx inside = XEXP (operands[1],0);
436 else if (GET_CODE (inside) == PLUS)
438 rtx lhs = XEXP (inside,0);
439 rtx rhs = XEXP (inside,1);
440 if (REG_P (lhs)) rn = REGNO (lhs);
441 if (REG_P (rhs)) rn = REGNO (rhs);
444 if (rn == REGNO (operands[0]))
445 /* Move the second word first. */
446 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
448 /* Move the first word first. */
449 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
452 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
454 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
456 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
461 [(set_attr "length" "4,4,8,8,4,4")
462 (set_attr "cc" "clobber")])
464 (define_insn "movsi_h8300hs"
465 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
466 (match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
467 "(TARGET_H8300S || TARGET_H8300H)
468 && (register_operand (operands[0], SImode)
469 || register_operand (operands[1], SImode))
470 && !(GET_CODE (operands[0]) == MEM
471 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
472 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
473 && GET_CODE (operands[1]) == REG
474 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
477 switch (which_alternative)
480 return \"sub.l %S0,%S0\";
484 return \"clrmac\;ldmac %1,macl\";
486 return \"stmac macl,%0\";
488 if (GET_CODE (operands[1]) == CONST_INT)
490 int val = INTVAL (operands[1]);
492 /* Look for constants which can be made by adding an 8-bit
493 number to zero in one of the two low bytes. */
494 if (val == (val & 0xff))
496 operands[1] = GEN_INT ((char) val & 0xff);
497 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
500 if (val == (val & 0xff00))
502 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
503 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
506 /* Look for constants that can be obtained by subs, inc, and
508 switch (val & 0xffffffff)
511 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
513 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
515 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
518 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
520 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
523 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
525 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
528 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
530 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
534 return \"mov.l %S1,%S0\";
536 [(set_attr "length" "2,2,10,10,10,4,4,2,6,4")
537 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
539 (define_insn "movsf_h8300h"
540 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
541 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
542 "(TARGET_H8300H || TARGET_H8300S)
543 && (register_operand (operands[0], SFmode)
544 || register_operand (operands[1], SFmode))"
552 [(set_attr "length" "2,2,10,10,4,4")
553 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
555 ;; ----------------------------------------------------------------------
557 ;; ----------------------------------------------------------------------
560 [(set (cc0) (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "rU")
562 (match_operand:QI 1 "const_int_operand" "n")))]
565 [(set_attr "length" "2")
566 (set_attr "cc" "set_zn")])
569 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
571 (match_operand:QI 1 "const_int_operand" "n")))]
574 [(set_attr "length" "2")
575 (set_attr "cc" "set_zn")])
578 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
580 (match_operand:QI 1 "const_int_operand" "n")))]
583 [(set_attr "length" "2")
584 (set_attr "cc" "set_zn")])
587 [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
589 (match_operand:HI 1 "const_int_operand" "n")))]
592 [(set_attr "length" "2")
593 (set_attr "cc" "set_zn")])
596 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
598 (match_operand:HI 1 "const_int_operand" "n")))]
601 [(set_attr "length" "2")
602 (set_attr "cc" "set_zn")])
605 [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
607 (match_operand:HI 1 "const_int_operand" "n")))]
610 [(set_attr "length" "2")
611 (set_attr "cc" "set_zn")])
614 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
617 [(set_attr "length" "2")
618 (set_attr "cc" "set_znv")])
621 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
624 [(set_attr "length" "2")
625 (set_attr "cc" "set_znv")])
628 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
629 "TARGET_H8300H || TARGET_H8300S"
631 [(set_attr "length" "2")
632 (set_attr "cc" "set_znv")])
636 (compare:QI (match_operand:QI 0 "register_operand" "r")
637 (match_operand:QI 1 "nonmemory_operand" "rn")))]
640 [(set_attr "length" "2")
641 (set_attr "cc" "compare")])
643 (define_expand "cmphi"
645 (compare:HI (match_operand:HI 0 "register_operand" "")
646 (match_operand:HI 1 "nonmemory_operand" "")))]
650 /* Force operand1 into a register if we're compiling
652 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
653 operands[1] = force_reg (HImode, operands[1]);
658 (compare:HI (match_operand:HI 0 "register_operand" "r")
659 (match_operand:HI 1 "register_operand" "r")))]
662 [(set_attr "length" "2")
663 (set_attr "cc" "compare")])
667 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
668 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
669 "TARGET_H8300H || TARGET_H8300S"
671 [(set_attr "length" "2,4")
672 (set_attr "cc" "compare,compare")])
676 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
677 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
678 "TARGET_H8300H || TARGET_H8300S"
680 [(set_attr "length" "2,6")
681 (set_attr "cc" "compare,compare")])
683 ;; ----------------------------------------------------------------------
685 ;; ----------------------------------------------------------------------
687 (define_insn "addqi3"
688 [(set (match_operand:QI 0 "register_operand" "=r")
689 (plus:QI (match_operand:QI 1 "register_operand" "%0")
690 (match_operand:QI 2 "nonmemory_operand" "rn")))]
693 [(set_attr "length" "2")
694 (set_attr "cc" "set_zn")])
696 (define_expand "addhi3"
697 [(set (match_operand:HI 0 "register_operand" "")
698 (plus:HI (match_operand:HI 1 "register_operand" "")
699 (match_operand:HI 2 "nonmemory_operand" "")))]
704 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
705 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
706 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
711 add.b %s2,%s0\;addx %t2,%t0
713 mov.w %T1,%T0\;add.w %T2,%T0"
714 [(set_attr "length" "2,2,4,2,6")
715 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
718 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
719 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
720 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
721 "TARGET_H8300H || TARGET_H8300S"
727 [(set_attr "length" "2,2,4,2")
728 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
731 [(set (match_operand:HI 0 "register_operand" "")
732 (plus:HI (match_dup 0)
733 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
736 "split_adds_subs (HImode, operands); DONE;")
738 (define_expand "addsi3"
739 [(set (match_operand:SI 0 "register_operand" "")
740 (plus:SI (match_operand:SI 1 "register_operand" "")
741 (match_operand:SI 2 "nonmemory_operand" "")))]
745 (define_insn "addsi_h8300"
746 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
747 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
748 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
751 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
752 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
753 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
754 [(set_attr "length" "8,6,10")
755 (set_attr "cc" "clobber")])
757 (define_insn "addsi_h8300h"
758 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
759 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
760 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
761 "TARGET_H8300H || TARGET_H8300S"
767 [(set_attr "length" "2,2,6,2")
768 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
771 [(set (match_operand:SI 0 "register_operand" "")
772 (plus:SI (match_dup 0)
773 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
774 "TARGET_H8300H || TARGET_H8300S"
776 "split_adds_subs (SImode, operands); DONE;")
778 ;; ----------------------------------------------------------------------
779 ;; SUBTRACT INSTRUCTIONS
780 ;; ----------------------------------------------------------------------
782 (define_insn "subqi3"
783 [(set (match_operand:QI 0 "register_operand" "=r,r")
784 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
785 (match_operand:QI 2 "nonmemory_operand" "r,n")))]
790 [(set_attr "length" "2")
791 (set_attr "cc" "set_zn")])
793 (define_expand "subhi3"
794 [(set (match_operand:HI 0 "register_operand" "")
795 (minus:HI (match_operand:HI 1 "general_operand" "")
796 (match_operand:HI 2 "nonmemory_operand" "")))]
801 [(set (match_operand:HI 0 "register_operand" "=r,&r")
802 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
803 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
807 add.b %E2,%s0\;addx %F2,%t0"
808 [(set_attr "length" "2,4")
809 (set_attr "cc" "set_zn,clobber")])
812 [(set (match_operand:HI 0 "register_operand" "=r,&r")
813 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
814 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
815 "TARGET_H8300H || TARGET_H8300S"
819 [(set_attr "length" "2,4")
820 (set_attr "cc" "set_zn,set_zn")])
822 (define_expand "subsi3"
823 [(set (match_operand:SI 0 "register_operand" "")
824 (minus:SI (match_operand:SI 1 "register_operand" "")
825 (match_operand:SI 2 "nonmemory_operand" "")))]
829 (define_insn "subsi3_h8300"
830 [(set (match_operand:SI 0 "register_operand" "=r")
831 (minus:SI (match_operand:SI 1 "register_operand" "0")
832 (match_operand:SI 2 "register_operand" "r")))]
834 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
835 [(set_attr "length" "6")
836 (set_attr "cc" "clobber")])
838 (define_insn "subsi3_h8300h"
839 [(set (match_operand:SI 0 "register_operand" "=r,r")
840 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
841 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
842 "TARGET_H8300H || TARGET_H8300S"
846 [(set_attr "length" "2,6")
847 (set_attr "cc" "set_zn,set_zn")])
849 ;; ----------------------------------------------------------------------
850 ;; MULTIPLY INSTRUCTIONS
851 ;; ----------------------------------------------------------------------
853 ;; Note that the H8/300 can only handle umulqihi3.
855 (define_insn "mulqihi3"
856 [(set (match_operand:HI 0 "register_operand" "=r")
857 (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
858 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
859 "TARGET_H8300H || TARGET_H8300S"
861 [(set_attr "length" "4")
862 (set_attr "cc" "set_zn")])
864 (define_insn "mulhisi3"
865 [(set (match_operand:SI 0 "register_operand" "=r")
866 (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
867 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
868 "TARGET_H8300H || TARGET_H8300S"
870 [(set_attr "length" "4")
871 (set_attr "cc" "set_zn")])
873 (define_insn "umulqihi3"
874 [(set (match_operand:HI 0 "register_operand" "=r")
875 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
876 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
879 [(set_attr "length" "2")
880 (set_attr "cc" "none_0hit")])
882 (define_insn "umulhisi3"
883 [(set (match_operand:SI 0 "register_operand" "=r")
884 (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
885 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
886 "TARGET_H8300H || TARGET_H8300S"
888 [(set_attr "length" "2")
889 (set_attr "cc" "none_0hit")])
891 ;; This is a "bridge" instruction. Combine can't cram enough insns
892 ;; together to crate a MAC instruction directly, but it can create
893 ;; this instruction, which then allows combine to create the real
896 ;; Unfortunately, if combine doesn't create a MAC instruction, this
897 ;; insn must generate reasonably correct code. Egad.
899 [(set (match_operand:SI 0 "register_operand" "=a")
902 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
904 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
906 "clrmac\;mac @%2+,@%1+"
907 [(set_attr "length" "6")
908 (set_attr "cc" "none_0hit")])
911 [(set (match_operand:SI 0 "register_operand" "=a")
913 (sign_extend:SI (mem:HI
914 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
915 (sign_extend:SI (mem:HI
916 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
917 (match_operand:SI 3 "register_operand" "0")))]
920 [(set_attr "length" "4")
921 (set_attr "cc" "none_0hit")])
923 ;; ----------------------------------------------------------------------
924 ;; DIVIDE INSTRUCTIONS
925 ;; ----------------------------------------------------------------------
927 (define_insn "udivqi3"
928 [(set (match_operand:QI 0 "register_operand" "=r")
931 (match_operand:HI 1 "general_operand" "0")
932 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
935 [(set_attr "length" "2")
936 (set_attr "cc" "clobber")])
938 ;; ??? Will divxu always work here?
940 (define_insn "divqi3"
941 [(set (match_operand:QI 0 "register_operand" "=r")
944 (match_operand:HI 1 "general_operand" "0")
945 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
948 [(set_attr "length" "2")
949 (set_attr "cc" "clobber")])
951 (define_insn "udivhi3"
952 [(set (match_operand:HI 0 "register_operand" "=r")
955 (match_operand:SI 1 "general_operand" "0")
956 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
957 "TARGET_H8300H || TARGET_H8300S"
959 [(set_attr "length" "2")
960 (set_attr "cc" "clobber")])
962 (define_insn "divhi3"
963 [(set (match_operand:HI 0 "register_operand" "=r")
966 (match_operand:SI 1 "general_operand" "0")
967 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
968 "TARGET_H8300H || TARGET_H8300S"
970 [(set_attr "length" "4")
971 (set_attr "cc" "clobber")])
973 ;; ----------------------------------------------------------------------
975 ;; ----------------------------------------------------------------------
977 (define_insn "umodqi3"
978 [(set (match_operand:QI 0 "register_operand" "=r")
981 (match_operand:HI 1 "general_operand" "0")
982 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
984 "divxu %X2,%T0\;mov %t0,%s0"
985 [(set_attr "length" "4")
986 (set_attr "cc" "clobber")])
988 (define_insn "modqi3"
989 [(set (match_operand:QI 0 "register_operand" "=r")
992 (match_operand:HI 1 "general_operand" "0")
993 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))]
994 "TARGET_H8300H || TARGET_H8300S"
995 "divxs.b %X2,%T0\;mov %t0,%s0"
996 [(set_attr "length" "6")
997 (set_attr "cc" "clobber")])
999 (define_insn "umodhi3"
1000 [(set (match_operand:HI 0 "register_operand" "=r")
1003 (match_operand:SI 1 "general_operand" "0")
1004 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
1005 "TARGET_H8300H || TARGET_H8300S"
1006 "divxu.w %T2,%S0\;mov %e0,%f0"
1007 [(set_attr "length" "4")
1008 (set_attr "cc" "clobber")])
1010 (define_insn "modhi3"
1011 [(set (match_operand:HI 0 "register_operand" "=r")
1014 (match_operand:SI 1 "general_operand" "0")
1015 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))]
1016 "TARGET_H8300H || TARGET_H8300S"
1017 "divxs.w %T2,%S0\;mov %e0,%f0"
1018 [(set_attr "length" "6")
1019 (set_attr "cc" "clobber")])
1021 ;; ----------------------------------------------------------------------
1023 ;; ----------------------------------------------------------------------
1026 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1027 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1028 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1029 "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
1033 [(set_attr "length" "2,4")
1034 (set_attr "adjust_length" "no")
1035 (set_attr "cc" "set_znv,none_0hit")])
1037 (define_expand "andqi3"
1038 [(set (match_operand:QI 0 "bit_operand" "")
1039 (and:QI (match_operand:QI 1 "bit_operand" "")
1040 (match_operand:QI 2 "nonmemory_operand" "")))]
1044 if (fix_bit_operand (operands, 'O', AND))
1048 (define_expand "andhi3"
1049 [(set (match_operand:HI 0 "register_operand" "")
1050 (and:HI (match_operand:HI 1 "register_operand" "")
1051 (match_operand:HI 2 "nonmemory_operand" "")))]
1056 [(set (match_operand:HI 0 "register_operand" "=r")
1057 (and:HI (match_operand:HI 1 "register_operand" "%0")
1058 (match_operand:HI 2 "nonmemory_operand" "rn")))]
1060 "* return output_logical_op (HImode, AND, operands);"
1061 [(set_attr "length" "4")
1062 (set_attr "cc" "clobber")])
1065 [(set (match_operand:HI 0 "register_operand" "=r,r")
1066 (and:HI (match_operand:HI 1 "register_operand" "%0,0")
1067 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
1068 "TARGET_H8300H || TARGET_H8300S"
1069 "* return output_logical_op (HImode, AND, operands);"
1070 [(set_attr "length" "2,4")
1071 (set_attr "cc" "set_znv,clobber")])
1073 (define_insn "*andorhi3"
1074 [(set (match_operand:HI 0 "register_operand" "=r")
1075 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1076 (match_operand:HI 3 "p_operand" "P"))
1077 (match_operand:HI 1 "register_operand" "0")))]
1081 if (INTVAL (operands[3]) > 128)
1083 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1084 return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
1086 return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
1088 [(set_attr "length" "4")
1089 (set_attr "cc" "clobber")])
1091 (define_expand "andsi3"
1092 [(set (match_operand:SI 0 "register_operand" "")
1093 (and:SI (match_operand:SI 1 "register_operand" "")
1094 (match_operand:SI 2 "nonmemory_operand" "")))]
1099 [(set (match_operand:SI 0 "register_operand" "=r")
1100 (and:SI (match_operand:SI 1 "register_operand" "%0")
1101 (match_operand:SI 2 "nonmemory_operand" "rn")))]
1103 "* return output_logical_op (SImode, AND, operands);"
1104 [(set_attr "length" "8")
1105 (set_attr "cc" "clobber")])
1108 [(set (match_operand:SI 0 "register_operand" "=r,r")
1109 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
1110 (match_operand:SI 2 "nonmemory_operand" "r,n")))]
1111 "TARGET_H8300H || TARGET_H8300S"
1112 "* return output_logical_op (SImode, AND, operands);"
1113 [(set_attr "length" "4,6")
1114 (set_attr "cc" "set_znv,clobber")])
1116 ;; ----------------------------------------------------------------------
1118 ;; ----------------------------------------------------------------------
1121 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1122 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1123 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1124 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1128 [(set_attr "length" "2,4")
1129 (set_attr "adjust_length" "no")
1130 (set_attr "cc" "set_znv,none_0hit")])
1132 (define_expand "iorqi3"
1133 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1134 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1135 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1139 if (fix_bit_operand (operands, 'P', IOR))
1143 (define_expand "iorhi3"
1144 [(set (match_operand:HI 0 "general_operand" "=r,r")
1145 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1146 (match_operand:HI 2 "general_operand" "J,rn")))]
1151 [(set (match_operand:HI 0 "general_operand" "=r,r")
1152 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1153 (match_operand:HI 2 "general_operand" "J,rn")))]
1155 "* return output_logical_op (HImode, IOR, operands);"
1156 [(set_attr "length" "2,4")
1157 (set_attr "cc" "clobber,clobber")])
1160 [(set (match_operand:HI 0 "general_operand" "=r,r,r")
1161 (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0")
1162 (match_operand:HI 2 "general_operand" "J,r,n")))]
1163 "TARGET_H8300H || TARGET_H8300S"
1164 "* return output_logical_op (HImode, IOR, operands);"
1165 [(set_attr "length" "2,2,4")
1166 (set_attr "cc" "clobber,set_znv,clobber")])
1168 (define_expand "iorsi3"
1169 [(set (match_operand:SI 0 "register_operand" "")
1170 (ior:SI (match_operand:SI 1 "register_operand" "")
1171 (match_operand:SI 2 "nonmemory_operand" "")))]
1176 [(set (match_operand:SI 0 "register_operand" "=r,r")
1177 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
1178 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1180 "* return output_logical_op (SImode, IOR, operands);"
1181 [(set_attr "length" "2,8")
1182 (set_attr "cc" "clobber,clobber")])
1185 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1186 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0")
1187 (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
1188 "TARGET_H8300H || TARGET_H8300S"
1189 "* return output_logical_op (SImode, IOR, operands);"
1190 [(set_attr "length" "2,4,6")
1191 (set_attr "cc" "clobber,set_znv,clobber")])
1193 ;; ----------------------------------------------------------------------
1195 ;; ----------------------------------------------------------------------
1198 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1199 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1200 (match_operand:QI 2 "nonmemory_operand" "rn,P")))]
1201 "register_operand (operands[0], QImode) || p_operand (operands[2], QImode)"
1205 [(set_attr "length" "2,4")
1206 (set_attr "adjust_length" "no")
1207 (set_attr "cc" "set_znv,none_0hit")])
1209 (define_expand "xorqi3"
1210 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1211 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1212 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1216 if (fix_bit_operand (operands, 'O', XOR))
1220 (define_expand "xorhi3"
1221 [(set (match_operand:HI 0 "register_operand" "")
1222 (xor:HI (match_operand:HI 1 "general_operand" "")
1223 (match_operand:HI 2 "nonmemory_operand" "")))]
1228 [(set (match_operand:HI 0 "register_operand" "=r,r")
1229 (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1230 (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
1232 "* return output_logical_op (HImode, XOR, operands);"
1233 [(set_attr "length" "2,4")
1234 (set_attr "cc" "clobber,clobber")])
1237 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1238 (xor:HI (match_operand:HI 1 "general_operand" "%0,0,0")
1239 (match_operand:HI 2 "nonmemory_operand" "J,r,n")))]
1240 "TARGET_H8300H || TARGET_H8300S"
1241 "* return output_logical_op (HImode, XOR, operands);"
1242 [(set_attr "length" "2,2,4")
1243 (set_attr "cc" "clobber,set_znv,clobber")])
1245 (define_expand "xorsi3"
1246 [(set (match_operand:SI 0 "register_operand" "")
1247 (xor:SI (match_operand:SI 1 "register_operand" "")
1248 (match_operand:SI 2 "nonmemory_operand" "")))]
1253 [(set (match_operand:SI 0 "register_operand" "=r,r")
1254 (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
1255 (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
1257 "* return output_logical_op (SImode, XOR, operands);"
1258 [(set_attr "length" "2,8")
1259 (set_attr "cc" "clobber,clobber")])
1262 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1263 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0")
1264 (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
1265 "TARGET_H8300H || TARGET_H8300S"
1266 "* return output_logical_op (SImode, XOR, operands);"
1267 [(set_attr "length" "2,4,6")
1268 (set_attr "cc" "clobber,set_znv,clobber")])
1270 ;; ----------------------------------------------------------------------
1271 ;; NEGATION INSTRUCTIONS
1272 ;; ----------------------------------------------------------------------
1274 (define_insn "negqi2"
1275 [(set (match_operand:QI 0 "register_operand" "=r")
1276 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1279 [(set_attr "length" "2")
1280 (set_attr "cc" "set_zn")])
1282 (define_expand "neghi2"
1283 [(set (match_operand:HI 0 "register_operand" "=r")
1284 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1290 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1295 (define_expand "neghi2_h8300"
1297 (not:HI (match_operand:HI 1 "register_operand" "r")))
1298 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1299 (set (match_operand:HI 0 "register_operand" "=r")
1302 "{ operands[2] = gen_reg_rtx (HImode); }")
1304 (define_insn "neghi2_h8300h"
1305 [(set (match_operand:HI 0 "register_operand" "=r")
1306 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1307 "TARGET_H8300H || TARGET_H8300S"
1309 [(set_attr "length" "2")
1310 (set_attr "cc" "set_zn")])
1312 (define_expand "negsi2"
1313 [(set (match_operand:SI 0 "register_operand" "=r")
1314 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1320 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1325 (define_expand "negsi2_h8300"
1327 (not:SI (match_operand:SI 1 "register_operand" "r")))
1328 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1329 (set (match_operand:SI 0 "register_operand" "=r")
1332 "{ operands[2] = gen_reg_rtx(SImode); }")
1334 (define_insn "negsi2_h8300h"
1335 [(set (match_operand:SI 0 "register_operand" "=r")
1336 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1337 "TARGET_H8300H || TARGET_H8300S"
1339 [(set_attr "length" "2")
1340 (set_attr "cc" "set_zn")])
1342 ;; ----------------------------------------------------------------------
1344 ;; ----------------------------------------------------------------------
1346 (define_insn "one_cmplqi2"
1347 [(set (match_operand:QI 0 "register_operand" "=r")
1348 (not:QI (match_operand:QI 1 "general_operand" "0")))]
1351 [(set_attr "length" "2")
1352 (set_attr "cc" "set_znv")])
1354 (define_insn "one_cmplhi2"
1355 [(set (match_operand:HI 0 "register_operand" "=r")
1356 (not:HI (match_operand:HI 1 "general_operand" "0")))]
1361 return \"not %s0\;not %t0\";
1365 [(set_attr "cc" "clobber")
1366 (set (attr "length")
1367 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1372 (define_insn "one_cmplsi2"
1373 [(set (match_operand:SI 0 "register_operand" "=r")
1374 (not:SI (match_operand:SI 1 "general_operand" "0")))]
1379 return \"not %w0\;not %x0\;not %y0\;not %z0\";
1383 [(set_attr "cc" "clobber")
1384 (set (attr "length")
1385 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
1390 ;; ----------------------------------------------------------------------
1391 ;; JUMP INSTRUCTIONS
1392 ;; ----------------------------------------------------------------------
1394 ;; Conditional jump instructions
1396 (define_expand "ble"
1398 (if_then_else (le (cc0)
1400 (label_ref (match_operand 0 "" ""))
1405 (define_expand "bleu"
1407 (if_then_else (leu (cc0)
1409 (label_ref (match_operand 0 "" ""))
1414 (define_expand "bge"
1416 (if_then_else (ge (cc0)
1418 (label_ref (match_operand 0 "" ""))
1423 (define_expand "bgeu"
1425 (if_then_else (geu (cc0)
1427 (label_ref (match_operand 0 "" ""))
1432 (define_expand "blt"
1434 (if_then_else (lt (cc0)
1436 (label_ref (match_operand 0 "" ""))
1441 (define_expand "bltu"
1443 (if_then_else (ltu (cc0)
1445 (label_ref (match_operand 0 "" ""))
1450 (define_expand "bgt"
1452 (if_then_else (gt (cc0)
1454 (label_ref (match_operand 0 "" ""))
1459 (define_expand "bgtu"
1461 (if_then_else (gtu (cc0)
1463 (label_ref (match_operand 0 "" ""))
1468 (define_expand "beq"
1470 (if_then_else (eq (cc0)
1472 (label_ref (match_operand 0 "" ""))
1477 (define_expand "bne"
1479 (if_then_else (ne (cc0)
1481 (label_ref (match_operand 0 "" ""))
1486 (define_insn "branch_true"
1488 (if_then_else (match_operator 1 "comparison_operator"
1489 [(cc0) (const_int 0)])
1490 (label_ref (match_operand 0 "" ""))
1495 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1496 && (GET_CODE (operands[1]) == GT
1497 || GET_CODE (operands[1]) == GE
1498 || GET_CODE (operands[1]) == LE
1499 || GET_CODE (operands[1]) == LT))
1501 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1505 if (get_attr_length (insn) == 2)
1506 return \"b%j1 %l0\";
1507 else if (get_attr_length (insn) == 4)
1508 return \"b%j1 %l0:16\";
1510 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1512 [(set_attr "type" "branch")
1513 (set_attr "cc" "none")])
1515 (define_insn "branch_false"
1517 (if_then_else (match_operator 1 "comparison_operator"
1518 [(cc0) (const_int 0)])
1520 (label_ref (match_operand 0 "" ""))))]
1524 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1525 && (GET_CODE (operands[1]) == GT
1526 || GET_CODE (operands[1]) == GE
1527 || GET_CODE (operands[1]) == LE
1528 || GET_CODE (operands[1]) == LT))
1530 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1534 if (get_attr_length (insn) == 2)
1535 return \"b%k1 %l0\";
1536 else if (get_attr_length (insn) == 4)
1537 return \"b%k1 %l0:16\";
1539 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1541 [(set_attr "type" "branch")
1542 (set_attr "cc" "none")])
1544 ;; Unconditional and other jump instructions.
1548 (label_ref (match_operand 0 "" "")))]
1552 if (get_attr_length (insn) == 2)
1554 else if (get_attr_length (insn) == 4)
1555 return \"bra %l0:16\";
1557 return \"jmp @%l0\";
1559 [(set_attr "type" "branch")
1560 (set_attr "cc" "none")])
1562 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1564 (define_expand "tablejump"
1565 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1566 (use (label_ref (match_operand 1 "" "")))])]
1570 (define_insn "tablejump_h8300"
1571 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1572 (use (label_ref (match_operand 1 "" "")))]
1575 [(set_attr "cc" "none")
1576 (set_attr "length" "2")])
1578 (define_insn "tablejump_h8300h"
1579 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1580 (use (label_ref (match_operand 1 "" "")))]
1581 "TARGET_H8300H || TARGET_H8300S"
1583 [(set_attr "cc" "none")
1584 (set_attr "length" "2")])
1586 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1588 (define_expand "indirect_jump"
1589 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1593 (define_insn "indirect_jump_h8300"
1594 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1597 [(set_attr "cc" "none")
1598 (set_attr "length" "2")])
1600 (define_insn "indirect_jump_h8300h"
1601 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1602 "TARGET_H8300H || TARGET_H8300S"
1604 [(set_attr "cc" "none")
1605 (set_attr "length" "2")])
1607 ;; Call subroutine with no return value.
1609 ;; ??? Even though we use HImode here, this works for the 300h.
1612 [(call (match_operand:QI 0 "call_insn_operand" "or")
1613 (match_operand:HI 1 "general_operand" "g"))]
1617 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1618 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1619 return \"jsr\\t\@%0:8\";
1621 return \"jsr\\t%0\";
1623 [(set_attr "cc" "clobber")
1624 (set (attr "length")
1625 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1629 ;; Call subroutine, returning value in operand 0
1630 ;; (which must be a hard register).
1632 ;; ??? Even though we use HImode here, this works on the 300h.
1634 (define_insn "call_value"
1635 [(set (match_operand 0 "" "=r")
1636 (call (match_operand:QI 1 "call_insn_operand" "or")
1637 (match_operand:HI 2 "general_operand" "g")))]
1641 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1642 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1643 return \"jsr\\t\@%1:8\";
1645 return \"jsr\\t%1\";
1647 [(set_attr "cc" "clobber")
1648 (set (attr "length")
1649 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1657 [(set_attr "cc" "none")
1658 (set_attr "length" "2")])
1660 ;; ----------------------------------------------------------------------
1661 ;; EXTEND INSTRUCTIONS
1662 ;; ----------------------------------------------------------------------
1664 (define_expand "zero_extendqihi2"
1665 [(set (match_operand:HI 0 "register_operand" "")
1666 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1671 [(set (match_operand:HI 0 "register_operand" "=r,r")
1672 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1676 mov.b %R1,%s0\;mov.b #0,%t0"
1677 [(set_attr "length" "2,10")
1678 (set_attr "cc" "clobber,clobber")])
1681 [(set (match_operand:HI 0 "register_operand" "=r,r")
1682 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1683 "TARGET_H8300H || TARGET_H8300S"
1686 mov.b %R1,%s0\;extu.w %T0"
1687 [(set_attr "length" "2,10")
1688 (set_attr "cc" "set_znv,set_znv")])
1690 ;; The compiler can synthesize a 300H variant of this which is
1691 ;; just as efficient as one that we'd create
1692 (define_insn "zero_extendqisi2"
1693 [(set (match_operand:SI 0 "register_operand" "=r,r")
1694 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1697 mov.b #0,%x0\;sub.w %e0,%e0
1698 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1699 [(set_attr "length" "4,6")
1700 (set_attr "cc" "clobber,clobber")])
1702 (define_expand "zero_extendhisi2"
1703 [(set (match_operand:SI 0 "register_operand" "")
1704 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1708 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1710 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1711 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1715 mov.w %f1,%f0\;sub.w %e0,%e0
1716 mov.w %e1,%f0\;sub.w %e0,%e0"
1717 [(set_attr "length" "2,4,4")
1718 (set_attr "cc" "clobber,clobber,clobber")])
1721 [(set (match_operand:SI 0 "register_operand" "=r")
1722 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1723 "TARGET_H8300H || TARGET_H8300S"
1725 [(set_attr "length" "2")
1726 (set_attr "cc" "set_znv")])
1728 (define_expand "extendqihi2"
1729 [(set (match_operand:HI 0 "register_operand" "")
1730 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1735 [(set (match_operand:HI 0 "register_operand" "=r,r")
1736 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1739 bld #7,%s0\;subx %t0,%t0
1740 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1741 [(set_attr "length" "4,6")
1742 (set_attr "cc" "clobber,clobber")])
1745 [(set (match_operand:HI 0 "register_operand" "=r")
1746 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1747 "TARGET_H8300H || TARGET_H8300S"
1749 [(set_attr "length" "2")
1750 (set_attr "cc" "set_znv")])
1752 ;; The compiler can synthesize a 300H variant of this which is
1753 ;; just as efficient as one that we'd create
1754 (define_insn "extendqisi2"
1755 [(set (match_operand:SI 0 "register_operand" "=r,r")
1756 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1759 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1760 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1761 [(set_attr "length" "8,10")
1762 (set_attr "cc" "clobber,clobber")])
1764 (define_expand "extendhisi2"
1765 [(set (match_operand:SI 0 "register_operand" "")
1766 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1771 [(set (match_operand:SI 0 "register_operand" "=r,r")
1772 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1775 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1776 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1777 [(set_attr "length" "6,8")
1778 (set_attr "cc" "clobber,clobber")])
1781 [(set (match_operand:SI 0 "register_operand" "=r")
1782 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1783 "TARGET_H8300H || TARGET_H8300S"
1785 [(set_attr "length" "2")
1786 (set_attr "cc" "set_znv")])
1788 ;; ----------------------------------------------------------------------
1790 ;; ----------------------------------------------------------------------
1792 ;; We make some attempt to provide real efficient shifting. One example is
1793 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1794 ;; reg and moving 0 into the former reg.
1796 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1797 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1798 ;; give the optimizer more cracks at the code. However, we wish to do things
1799 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1800 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1801 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1802 ;; to detect cases it can optimize.
1804 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1805 ;; easier "do it at insn emit time" route.
1809 (define_expand "ashlqi3"
1810 [(set (match_operand:QI 0 "register_operand" "")
1811 (ashift:QI (match_operand:QI 1 "register_operand" "")
1812 (match_operand:QI 2 "nonmemory_operand" "")))]
1814 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE;else FAIL;")
1816 (define_expand "ashrqi3"
1817 [(set (match_operand:QI 0 "register_operand" "")
1818 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1819 (match_operand:QI 2 "nonmemory_operand" "")))]
1821 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE;else FAIL;")
1823 (define_expand "lshrqi3"
1824 [(set (match_operand:QI 0 "register_operand" "")
1825 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1826 (match_operand:QI 2 "nonmemory_operand" "")))]
1828 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE;else FAIL;")
1831 [(set (match_operand:QI 0 "register_operand" "=r,r")
1832 (match_operator:QI 3 "nshift_operator"
1833 [ (match_operand:QI 1 "register_operand" "0,0")
1834 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1835 (clobber (match_scratch:QI 4 "=X,&r"))]
1837 "* return emit_a_shift (insn, operands);"
1838 [(set_attr "length" "20")
1839 (set_attr "cc" "clobber")])
1843 (define_expand "ashlhi3"
1844 [(set (match_operand:HI 0 "register_operand" "")
1845 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1846 (match_operand:QI 2 "nonmemory_operand" "")))]
1848 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE;else FAIL;")
1850 (define_expand "lshrhi3"
1851 [(set (match_operand:HI 0 "register_operand" "")
1852 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1853 (match_operand:QI 2 "nonmemory_operand" "")))]
1855 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE;else FAIL;")
1857 (define_expand "ashrhi3"
1858 [(set (match_operand:HI 0 "register_operand" "")
1859 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1860 (match_operand:QI 2 "nonmemory_operand" "")))]
1862 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE;else FAIL;")
1865 [(set (match_operand:HI 0 "register_operand" "=r,r")
1866 (match_operator:HI 3 "nshift_operator"
1867 [ (match_operand:HI 1 "register_operand" "0,0")
1868 (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
1869 (clobber (match_scratch:QI 4 "=X,&r"))]
1871 "* return emit_a_shift (insn, operands);"
1872 [(set_attr "length" "20")
1873 (set_attr "cc" "clobber")])
1877 (define_expand "ashlsi3"
1878 [(set (match_operand:SI 0 "register_operand" "")
1880 (match_operand:SI 1 "general_operand" "")
1881 (match_operand:QI 2 "nonmemory_operand" "")))]
1883 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE;else FAIL;")
1885 (define_expand "lshrsi3"
1886 [(set (match_operand:SI 0 "register_operand" "")
1888 (match_operand:SI 1 "general_operand" "")
1889 (match_operand:QI 2 "nonmemory_operand" "")))]
1891 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE;else FAIL;")
1893 (define_expand "ashrsi3"
1894 [(set (match_operand:SI 0 "register_operand" "")
1896 (match_operand:SI 1 "general_operand" "")
1897 (match_operand:QI 2 "nonmemory_operand" "")))]
1899 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE;else FAIL;")
1902 [(set (match_operand:SI 0 "register_operand" "=r,r")
1903 (match_operator:SI 3 "nshift_operator"
1904 [ (match_operand:SI 1 "register_operand" "0,0")
1905 (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
1906 (clobber (match_scratch:QI 4 "=X,&r"))]
1908 "* return emit_a_shift (insn, operands);"
1909 [(set_attr "length" "20")
1910 (set_attr "cc" "clobber")])
1912 ;; ----------------------------------------------------------------------
1914 ;; ----------------------------------------------------------------------
1916 (define_expand "rotlqi3"
1917 [(set (match_operand:QI 0 "register_operand" "")
1918 (rotate:QI (match_operand:QI 1 "register_operand" "")
1919 (match_operand:QI 2 "nonmemory_operand" "")))]
1921 "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
1923 (define_insn "*rotlqi3_1"
1924 [(set (match_operand:QI 0 "register_operand" "=r")
1925 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1926 (match_operand:QI 2 "immediate_operand" "")))]
1928 "* return emit_a_rotate (ROTATE, operands);"
1929 [(set_attr "length" "20")
1930 (set_attr "cc" "clobber")])
1932 (define_expand "rotlhi3"
1933 [(set (match_operand:HI 0 "register_operand" "")
1934 (rotate:HI (match_operand:HI 1 "register_operand" "")
1935 (match_operand:QI 2 "nonmemory_operand" "")))]
1937 "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
1939 (define_insn "*rotlhi3_1"
1940 [(set (match_operand:HI 0 "register_operand" "=r")
1941 (rotate:HI (match_operand:HI 1 "register_operand" "0")
1942 (match_operand:QI 2 "immediate_operand" "")))]
1944 "* return emit_a_rotate (ROTATE, operands);"
1945 [(set_attr "length" "20")
1946 (set_attr "cc" "clobber")])
1948 (define_expand "rotlsi3"
1949 [(set (match_operand:SI 0 "register_operand" "")
1950 (rotate:SI (match_operand:SI 1 "register_operand" "")
1951 (match_operand:QI 2 "nonmemory_operand" "")))]
1952 "TARGET_H8300H || TARGET_H8300S"
1953 "if (expand_a_rotate (ROTATE, operands)) DONE;else FAIL;")
1955 (define_insn "*rotlsi3_1"
1956 [(set (match_operand:SI 0 "register_operand" "=r")
1957 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1958 (match_operand:QI 2 "immediate_operand" "")))]
1959 "TARGET_H8300H || TARGET_H8300S"
1960 "* return emit_a_rotate (ROTATE, operands);"
1961 [(set_attr "length" "20")
1962 (set_attr "cc" "clobber")])
1964 ;; -----------------------------------------------------------------
1966 ;; -----------------------------------------------------------------
1967 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1968 ;; instructions so let's use them as well as we can.
1970 ;; You'll never believe all these patterns perform one basic action --
1971 ;; load a bit from the source, optionally invert the bit, then store it
1972 ;; in the destination (which is known to be zero).
1974 ;; Combine obviously need some work to better identify this situation and
1975 ;; canonicalize the form better.
1978 ;; Normal loads with a 16bit destination.
1980 ;; Yes, both cases are needed.
1983 [(set (match_operand:HI 0 "register_operand" "=&r")
1984 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1986 (match_operand:HI 2 "immediate_operand" "n")))]
1988 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1989 [(set_attr "cc" "clobber")
1990 (set_attr "length" "6")])
1993 [(set (match_operand:HI 0 "register_operand" "=&r")
1994 (subreg:HI (zero_extract:SI
1995 (match_operand:HI 1 "register_operand" "r")
1997 (match_operand:HI 2 "immediate_operand" "n")) 2))]
1999 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2000 [(set_attr "cc" "clobber")
2001 (set_attr "length" "6")])
2004 ;; Inverted loads with a 16bit destination.
2006 ;; Yes, all four cases are needed.
2010 [(set (match_operand:HI 0 "register_operand" "=&r")
2011 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2012 (match_operand:HI 3 "p_operand" "P"))
2014 (match_operand:HI 2 "const_int_operand" "n")))]
2015 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2016 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2017 [(set_attr "cc" "clobber")
2018 (set_attr "length" "8")])
2021 [(set (match_operand:HI 0 "register_operand" "=&r")
2024 (match_operand:HI 1 "bit_operand" "Ur")
2025 (match_operand:HI 2 "const_int_operand" "n")))
2028 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2029 [(set_attr "cc" "clobber")
2030 (set_attr "length" "8")])
2033 [(set (match_operand:HI 0 "register_operand" "=&r")
2037 (match_operand:SI 1 "register_operand" "Ur")
2038 (match_operand:SI 2 "const_int_operand" "n")) 2))
2040 "INTVAL (operands[2]) < 16"
2041 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2042 [(set_attr "cc" "clobber")
2043 (set_attr "length" "8")])
2046 [(set (match_operand:HI 0 "register_operand" "=&r")
2050 (match_operand:SI 1 "bit_operand" "Ur")
2051 (match_operand:SI 2 "const_int_operand" "n")) 0))
2053 "(TARGET_H8300H || TARGET_H8300S)
2054 && INTVAL (operands[2]) < 16"
2055 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2056 [(set_attr "cc" "clobber")
2057 (set_attr "length" "8")])
2060 ;; Normal loads with a 32bit destination.
2062 ;; Yes, all three cases are needed.
2065 [(set (match_operand:SI 0 "register_operand" "=&r")
2066 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2068 (match_operand:HI 2 "const_int_operand" "n")))]
2070 "* return output_simode_bld (0, 0, operands);"
2071 [(set_attr "cc" "clobber")
2072 (set (attr "length")
2073 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2079 [(set (match_operand:SI 0 "register_operand" "=&r")
2080 (and:SI (zero_extend:SI
2082 (match_operand:QI 1 "bit_operand" "Ur")
2083 (match_operand:QI 2 "const_int_operand" "n")))
2086 "* return output_simode_bld (0, 0, operands);"
2087 [(set_attr "cc" "clobber")
2088 (set (attr "length")
2089 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2095 [(set (match_operand:SI 0 "register_operand" "=&r")
2096 (and:SI (zero_extend:SI
2098 (match_operand:HI 1 "bit_operand" "Ur")
2099 (match_operand:HI 2 "const_int_operand" "n")))
2102 "* return output_simode_bld (0, 0, operands);"
2103 [(set_attr "cc" "clobber")
2104 (set (attr "length")
2105 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2111 ;; Inverted loads with a 32bit destination.
2113 ;; Yes, all seven cases are needed.
2116 [(set (match_operand:SI 0 "register_operand" "=&r")
2118 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
2119 (match_operand:SI 2 "p_operand" "P")))]
2121 "* return output_simode_bld (1, 1, operands);"
2122 [(set_attr "cc" "clobber")
2123 (set (attr "length")
2124 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2129 [(set (match_operand:SI 0 "register_operand" "=&r")
2132 (lshiftrt:HI (match_operand:HI 1 "bit_operand" "Ur")
2133 (match_operand:HI 2 "const_int_operand" "n"))))
2136 "* return output_simode_bld (1, 0, operands);"
2137 [(set_attr "cc" "clobber")
2138 (set (attr "length")
2139 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2145 [(set (match_operand:SI 0 "register_operand" "=&r")
2147 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
2148 (match_operand:SI 2 "p_operand" "P")))]
2150 "* return output_simode_bld (1, 1, operands);"
2151 [(set_attr "cc" "clobber")
2152 (set (attr "length")
2153 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2158 [(set (match_operand:SI 0 "register_operand" "=&r")
2161 (lshiftrt:QI (match_operand:QI 1 "bit_operand" "Ur")
2162 (match_operand:QI 2 "const_int_operand" "n"))))
2165 "* return output_simode_bld (1, 0, operands);"
2166 [(set_attr "cc" "clobber")
2167 (set (attr "length")
2168 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2174 [(set (match_operand:SI 0 "register_operand" "=&r")
2178 (match_operand:HI 1 "bit_operand" "Ur")
2179 (match_operand:HI 2 "const_int_operand" "n")) 0))
2182 "* return output_simode_bld (1, 0, operands);"
2183 [(set_attr "cc" "clobber")
2184 (set (attr "length")
2185 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2191 [(set (match_operand:SI 0 "register_operand" "=&r")
2195 (match_operand:QI 1 "bit_operand" "Ur")
2196 (match_operand:QI 2 "const_int_operand" "n")) 0))
2199 "* return output_simode_bld (1, 0, operands);"
2200 [(set_attr "cc" "clobber")
2201 (set (attr "length")
2202 (if_then_else (eq (symbol_ref "TARGET_H8300H || TARGET_H8300S")
2208 [(set (match_operand:SI 0 "register_operand" "=&r")
2209 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2210 (match_operand:HI 3 "p_operand" "P"))
2212 (match_operand:HI 2 "const_int_operand" "n")))]
2213 "(1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2214 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2215 [(set_attr "cc" "clobber")
2216 (set_attr "length" "8")])
2218 (define_expand "insv"
2219 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2220 (match_operand:HI 1 "general_operand" "")
2221 (match_operand:HI 2 "general_operand" ""))
2222 (match_operand:HI 3 "general_operand" ""))]
2226 /* We only have single bit bitfield instructions. */
2227 if (INTVAL (operands[1]) != 1)
2230 /* For now, we don't allow memory operands. */
2231 if (GET_CODE (operands[0]) == MEM
2232 || GET_CODE (operands[3]) == MEM)
2237 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2239 (match_operand:HI 1 "immediate_operand" "n"))
2240 (match_operand:HI 2 "register_operand" "r"))]
2242 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2243 [(set_attr "cc" "clobber")
2244 (set_attr "length" "4")])
2246 (define_expand "extzv"
2247 [(set (match_operand:HI 0 "register_operand" "")
2248 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2249 (match_operand:HI 2 "general_operand" "")
2250 (match_operand:HI 3 "general_operand" "")))]
2254 /* We only have single bit bitfield instructions. */
2255 if (INTVAL (operands[2]) != 1)
2258 /* For now, we don't allow memory operands. */
2259 if (GET_CODE (operands[1]) == MEM)
2263 ;; BAND, BOR, and BXOR patterns
2266 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2267 (match_operator:HI 4 "bit_operator"
2268 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2270 (match_operand:HI 2 "immediate_operand" "n"))
2271 (match_operand:HI 3 "bit_operand" "0")]))]
2273 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2274 [(set_attr "cc" "clobber")
2275 (set_attr "length" "6")
2276 (set_attr "adjust_length" "no")])
2279 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2280 (match_operator:HI 5 "bit_operator"
2281 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2283 (match_operand:HI 2 "immediate_operand" "n"))
2284 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2286 (match_operand:HI 4 "immediate_operand" "n"))]))]
2288 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2289 [(set_attr "cc" "clobber")
2290 (set_attr "length" "6")
2291 (set_attr "adjust_length" "no")])