1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc.
6 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
7 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 3, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING3. If not see
23 ;; <http://www.gnu.org/licenses/>.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
72 ;; ----------------------------------------------------------------------
74 ;; ----------------------------------------------------------------------
76 (define_attr "cpu" "h8300,h8300h"
77 (const (symbol_ref "cpu_type")))
79 (define_attr "type" "branch,arith,bitbranch,call"
80 (const_string "arith"))
82 (define_attr "length_table" "none,addb,addw,addl,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
83 (const_string "none"))
85 ;; The size of instructions in bytes.
87 (define_attr "length" ""
88 (cond [(eq_attr "type" "branch")
89 ;; In a forward delayed branch, (pc) represents the end of the
90 ;; delay sequence, not the end of the branch itself.
91 (if_then_else (and (ge (minus (match_dup 0) (pc))
93 (le (plus (minus (match_dup 0) (pc))
94 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
97 (if_then_else (and (eq_attr "cpu" "h8300h")
98 (and (ge (minus (pc) (match_dup 0))
100 (le (minus (pc) (match_dup 0))
104 (eq_attr "type" "bitbranch")
106 (and (ge (minus (match_dup 0) (pc))
108 (le (minus (match_dup 0) (pc))
111 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
114 (and (eq_attr "cpu" "h8300h")
115 (and (ge (minus (pc) (match_dup 0))
117 (le (minus (pc) (match_dup 0))
120 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
123 (symbol_ref "h8300_insn_length_from_table (insn, operands)")
125 (eq_attr "length_table" "!none")
126 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
129 ;; Condition code settings.
131 ;; none - insn does not affect cc
132 ;; none_0hit - insn does not affect cc but it does modify operand 0
133 ;; This attribute is used to keep track of when operand 0 changes.
134 ;; See the description of NOTICE_UPDATE_CC for more info.
135 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
136 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
137 ;; compare - compare instruction
138 ;; clobber - value of cc is unknown
140 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
141 (const_string "clobber"))
143 ;; Type of delay slot. NONE means the instruction has no delay slot.
144 ;; JUMP means it is an unconditional jump that (if short enough)
145 ;; could be implemented using bra/s.
146 (define_attr "delay_slot" "none,jump"
147 (const_string "none"))
149 ;; "yes" if the instruction can be put into a delay slot. It's not
150 ;; entirely clear that jsr is not valid in delay slots, but it
151 ;; definitely doesn't have the effect of causing the called function
152 ;; to return to the target of the delayed branch.
153 (define_attr "can_delay" "no,yes"
154 (cond [(eq_attr "type" "branch,bitbranch,call")
156 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
158 (const_string "yes")))
160 ;; Only allow jumps to have a delay slot if we think they might
161 ;; be short enough. This is just an optimization: we don't know
162 ;; for certain whether they will be or not.
163 (define_delay (and (eq_attr "delay_slot" "jump")
164 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
165 [(eq_attr "can_delay" "yes")
169 ;; Provide the maximum length of an assembly instruction in an asm
170 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
172 (define_asm_attributes
173 [(set (attr "length")
174 (cond [(match_test "TARGET_H8300") (const_int 4)
175 (match_test "TARGET_H8300H") (const_int 10)
176 (match_test "TARGET_H8300S") (const_int 10)]
179 (include "predicates.md")
180 (include "constraints.md")
182 ;; ----------------------------------------------------------------------
184 ;; ----------------------------------------------------------------------
186 ;; This mode iterator allows :P to be used for patterns that operate on
187 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
188 (define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")])
191 ;; ----------------------------------------------------------------------
193 ;; ----------------------------------------------------------------------
197 (define_insn "*movqi_h8300"
198 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
199 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
201 && h8300_move_ok (operands[0], operands[1])"
209 [(set_attr "length" "2,2,2,2,4,4")
210 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
212 (define_insn "*movqi_h8300hs"
213 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
214 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
215 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
216 && h8300_move_ok (operands[0], operands[1])"
224 [(set (attr "length")
225 (symbol_ref "compute_mov_length (operands)"))
226 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
228 (define_insn "*movqi_h8sx"
229 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
230 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
235 [(set_attr "length_table" "mov_imm4,movb")
236 (set_attr "cc" "set_znv")])
238 (define_expand "movqi"
239 [(set (match_operand:QI 0 "general_operand_dst" "")
240 (match_operand:QI 1 "general_operand_src" ""))]
243 /* One of the ops has to be in a register. */
244 if (!TARGET_H8300SX && !h8300_move_ok (operands[0], operands[1]))
245 operands[1] = copy_to_mode_reg (QImode, operands[1]);
248 (define_insn "movstrictqi"
249 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
250 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
255 [(set_attr "length" "2,*")
256 (set_attr "length_table" "*,movb")
257 (set_attr "cc" "set_zn,set_znv")])
261 (define_insn "*movhi_h8300"
262 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
263 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
265 && h8300_move_ok (operands[0], operands[1])"
273 [(set (attr "length")
274 (symbol_ref "compute_mov_length (operands)"))
275 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
277 (define_insn "*movhi_h8300hs"
278 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
279 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
280 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
281 && h8300_move_ok (operands[0], operands[1])"
289 [(set (attr "length")
290 (symbol_ref "compute_mov_length (operands)"))
291 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
293 (define_insn "*movhi_h8sx"
294 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
295 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
303 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
304 (set_attr "length" "2,2,*,*,*")
305 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
307 (define_expand "movhi"
308 [(set (match_operand:HI 0 "general_operand_dst" "")
309 (match_operand:HI 1 "general_operand_src" ""))]
312 /* One of the ops has to be in a register. */
313 if (!h8300_move_ok (operands[0], operands[1]))
314 operands[1] = copy_to_mode_reg (HImode, operand1);
317 (define_insn "movstricthi"
318 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
319 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
325 [(set_attr "length" "2,2,*")
326 (set_attr "length_table" "*,*,movw")
327 (set_attr "cc" "set_zn,set_znv,set_znv")])
331 (define_expand "movsi"
332 [(set (match_operand:SI 0 "general_operand_dst" "")
333 (match_operand:SI 1 "general_operand_src" ""))]
338 if (h8300_expand_movsi (operands))
341 else if (!TARGET_H8300SX)
343 /* One of the ops has to be in a register. */
344 if (! h8300_move_ok (operands[0], operands[1]))
345 operands[1] = copy_to_mode_reg (SImode, operand1);
349 (define_insn "*movsi_h8300"
350 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
351 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
353 && h8300_move_ok (operands[0], operands[1])"
355 unsigned int rn = -1;
356 switch (which_alternative)
359 return "sub.w %e0,%e0\;sub.w %f0,%f0";
361 if (REGNO (operands[0]) < REGNO (operands[1]))
362 return "mov.w %e1,%e0\;mov.w %f1,%f0";
364 return "mov.w %f1,%f0\;mov.w %e1,%e0";
366 /* Make sure we don't trample the register we index with. */
367 if (GET_CODE (operands[1]) == MEM)
369 rtx inside = XEXP (operands[1], 0);
374 else if (GET_CODE (inside) == PLUS)
376 rtx lhs = XEXP (inside, 0);
377 rtx rhs = XEXP (inside, 1);
378 if (REG_P (lhs)) rn = REGNO (lhs);
379 if (REG_P (rhs)) rn = REGNO (rhs);
382 if (rn == REGNO (operands[0]))
384 /* Move the second word first. */
385 return "mov.w %f1,%f0\;mov.w %e1,%e0";
389 if (GET_CODE (operands[1]) == CONST_INT)
391 /* If either half is zero, use sub.w to clear that
393 if ((INTVAL (operands[1]) & 0xffff) == 0)
394 return "mov.w %e1,%e0\;sub.w %f0,%f0";
395 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
396 return "sub.w %e0,%e0\;mov.w %f1,%f0";
397 /* If the upper half and the lower half are the same,
398 copy one half to the other. */
399 if ((INTVAL (operands[1]) & 0xffff)
400 == ((INTVAL (operands[1]) >> 16) & 0xffff))
401 return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0";
403 return "mov.w %e1,%e0\;mov.w %f1,%f0";
406 return "mov.w %e1,%e0\;mov.w %f1,%f0";
408 return "mov.w %f1,%T0\;mov.w %e1,%T0";
410 return "mov.w %T1,%e0\;mov.w %T1,%f0";
415 [(set (attr "length")
416 (symbol_ref "compute_mov_length (operands)"))])
418 (define_insn "*movsi_h8300hs"
419 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
420 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
421 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
422 && h8300_move_ok (operands[0], operands[1])"
424 switch (which_alternative)
427 return "sub.l %S0,%S0";
431 return "clrmac\;ldmac %1,macl";
433 return "stmac macl,%0";
435 if (GET_CODE (operands[1]) == CONST_INT)
437 int val = INTVAL (operands[1]);
439 /* Look for constants which can be made by adding an 8-bit
440 number to zero in one of the two low bytes. */
441 if (val == (val & 0xff))
443 operands[1] = GEN_INT ((char) val & 0xff);
444 return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0";
447 if (val == (val & 0xff00))
449 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
450 return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0";
453 /* Look for constants that can be obtained by subs, inc, and
455 switch (val & 0xffffffff)
458 return "sub.l\\t%S0,%S0\;subs\\t#1,%S0";
460 return "sub.l\\t%S0,%S0\;subs\\t#2,%S0";
462 return "sub.l\\t%S0,%S0\;subs\\t#4,%S0";
465 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0";
467 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0";
470 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0";
472 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0";
475 return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0";
477 return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0";
481 return "mov.l %S1,%S0";
483 [(set (attr "length")
484 (symbol_ref "compute_mov_length (operands)"))
485 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
487 (define_insn "*movsi_h8sx"
488 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
489 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
497 clrmac\;ldmac %1,macl
499 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
500 (set_attr "length" "2,2,*,*,2,6,4")
501 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
503 (define_insn "*movsf_h8sx"
504 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
505 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
510 [(set_attr "length" "2,*")
511 (set_attr "length_table" "*,movl")
512 (set_attr "cc" "set_zn,set_znv")])
514 ;; Implement block moves using movmd. Defining movmemsi allows the full
515 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
516 ;; See h8sx_emit_movmd for details.
518 (define_expand "movmemsi"
519 [(use (match_operand:BLK 0 "memory_operand" ""))
520 (use (match_operand:BLK 1 "memory_operand" ""))
521 (use (match_operand:SI 2 "" ""))
522 (use (match_operand:SI 3 "const_int_operand" ""))]
525 if (h8sx_emit_movmd (operands[0], operands[1], operands[2], INTVAL (operands[3])))
531 ;; Expander for generating movmd insns. Operand 0 is the destination
532 ;; memory region, operand 1 is the source, operand 2 is the counter
533 ;; register and operand 3 is the chunk size (1, 2 or 4).
535 (define_expand "movmd"
537 [(set (match_operand:BLK 0 "memory_operand" "")
538 (match_operand:BLK 1 "memory_operand" ""))
539 (unspec [(match_operand:HI 2 "register_operand" "")
540 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
541 (clobber (match_dup 4))
542 (clobber (match_dup 5))
547 operands[4] = copy_rtx (XEXP (operands[0], 0));
548 operands[5] = copy_rtx (XEXP (operands[1], 0));
551 ;; This is a difficult instruction to reload since operand 0 must be the
552 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
554 (define_insn "movmd_internal_normal"
555 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
556 (mem:BLK (match_operand:HI 4 "register_operand" "1,1")))
557 (unspec [(match_operand:HI 5 "register_operand" "2,2")
558 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
559 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
560 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
561 (set (match_operand:HI 2 "register_operand" "=c,c")
563 "TARGET_H8300SX && TARGET_NORMAL_MODE"
567 [(set_attr "length" "2,14")
568 (set_attr "can_delay" "no")
569 (set_attr "cc" "none,clobber")])
571 (define_insn "movmd_internal"
572 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
573 (mem:BLK (match_operand:SI 4 "register_operand" "1,1")))
574 (unspec [(match_operand:HI 5 "register_operand" "2,2")
575 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
576 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
577 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
578 (set (match_operand:HI 2 "register_operand" "=c,c")
580 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
584 [(set_attr "length" "2,14")
585 (set_attr "can_delay" "no")
586 (set_attr "cc" "none,clobber")])
588 ;; Split the above instruction if the destination register isn't er6.
589 ;; We need a sequence like:
597 ;; where <dest> is the current destination register (operand 4).
598 ;; The fourth instruction will be deleted if <dest> dies here.
601 [(set (match_operand:BLK 0 "memory_operand" "")
602 (match_operand:BLK 1 "memory_operand" ""))
603 (unspec [(match_operand:HI 2 "register_operand" "")
604 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
605 (clobber (match_operand:HI 4 "register_operand" ""))
606 (clobber (match_operand:HI 5 "register_operand" ""))
609 "TARGET_H8300SX && TARGET_NORMAL_MODE && reload_completed
610 && REGNO (operands[4]) != DESTINATION_REG"
615 h8300_swap_into_er6 (XEXP (operands[0], 0));
616 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
617 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
618 if (REGNO (operands[4]) != DESTINATION_REG)
619 h8300_swap_out_of_er6 (operands[4]);
624 [(set (match_operand:BLK 0 "memory_operand" "")
625 (match_operand:BLK 1 "memory_operand" ""))
626 (unspec [(match_operand:HI 2 "register_operand" "")
627 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
628 (clobber (match_operand:SI 4 "register_operand" ""))
629 (clobber (match_operand:SI 5 "register_operand" ""))
632 "TARGET_H8300SX && !TARGET_NORMAL_MODE && reload_completed
633 && REGNO (operands[4]) != DESTINATION_REG"
638 h8300_swap_into_er6 (XEXP (operands[0], 0));
639 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
640 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
641 if (REGNO (operands[4]) != DESTINATION_REG)
642 h8300_swap_out_of_er6 (operands[4]);
646 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
647 ;; the final character, but movsd leaves it pointing to the character
650 (define_expand "movstr"
651 [(use (match_operand 0 "register_operand" ""))
652 (use (match_operand:BLK 1 "memory_operand" ""))
653 (use (match_operand:BLK 2 "memory_operand" ""))]
656 operands[1] = replace_equiv_address
657 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
658 operands[2] = replace_equiv_address
659 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
660 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
661 emit_insn (gen_add3_insn (operands[0], XEXP (operands[1], 0), constm1_rtx));
665 ;; Expander for generating a movsd instruction. Operand 0 is the
666 ;; destination string, operand 1 is the source string and operand 2
667 ;; is a scratch register.
669 (define_expand "movsd"
671 [(set (match_operand:BLK 0 "memory_operand" "")
672 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
674 (clobber (match_dup 3))
675 (clobber (match_dup 4))
676 (clobber (match_operand 2 "register_operand" ""))])]
679 operands[3] = copy_rtx (XEXP (operands[0], 0));
680 operands[4] = copy_rtx (XEXP (operands[1], 0));
683 ;; See comments above memcpy_internal().
685 (define_insn "stpcpy_internal_normal"
686 [(set (mem:BLK (match_operand:HI 3 "register_operand" "0,r"))
687 (unspec:BLK [(mem:BLK (match_operand:HI 4 "register_operand" "1,1"))]
689 (clobber (match_operand:HI 0 "register_operand" "=d,??D"))
690 (clobber (match_operand:HI 1 "register_operand" "=f,f"))
691 (clobber (match_operand:HI 2 "register_operand" "=c,c"))]
692 "TARGET_H8300SX && TARGET_NORMAL_MODE"
694 \n1:\tmovsd\t2f\;bra\t1b\n2:
696 [(set_attr "length" "6,18")
697 (set_attr "cc" "none,clobber")])
699 (define_insn "stpcpy_internal"
700 [(set (mem:BLK (match_operand:SI 3 "register_operand" "0,r"))
701 (unspec:BLK [(mem:BLK (match_operand:SI 4 "register_operand" "1,1"))]
703 (clobber (match_operand:SI 0 "register_operand" "=d,??D"))
704 (clobber (match_operand:SI 1 "register_operand" "=f,f"))
705 (clobber (match_operand:SI 2 "register_operand" "=c,c"))]
706 "TARGET_H8300SX && !TARGET_NORMAL_MODE"
708 \n1:\tmovsd\t2f\;bra\t1b\n2:
710 [(set_attr "length" "6,18")
711 (set_attr "cc" "none,clobber")])
713 ;; Split the above instruction if the destination isn't er6. This works
714 ;; in the same way as the movmd splitter.
717 [(set (match_operand:BLK 0 "memory_operand" "")
718 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
719 (clobber (match_operand:HI 2 "register_operand" ""))
720 (clobber (match_operand:HI 3 "register_operand" ""))
721 (clobber (match_operand:HI 4 "register_operand" ""))]
722 "TARGET_H8300SX && TARGET_NORMAL_MODE && reload_completed
723 && REGNO (operands[2]) != DESTINATION_REG"
728 h8300_swap_into_er6 (XEXP (operands[0], 0));
729 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
730 emit_insn (gen_movsd (dest, operands[1], operands[4]));
731 h8300_swap_out_of_er6 (operands[2]);
736 [(set (match_operand:BLK 0 "memory_operand" "")
737 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
738 (clobber (match_operand:SI 2 "register_operand" ""))
739 (clobber (match_operand:SI 3 "register_operand" ""))
740 (clobber (match_operand:SI 4 "register_operand" ""))]
741 "TARGET_H8300SX && !TARGET_NORMAL_MODE && reload_completed
742 && REGNO (operands[2]) != DESTINATION_REG"
747 h8300_swap_into_er6 (XEXP (operands[0], 0));
748 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
749 emit_insn (gen_movsd (dest, operands[1], operands[4]));
750 h8300_swap_out_of_er6 (operands[2]);
756 (define_expand "movsf"
757 [(set (match_operand:SF 0 "general_operand_dst" "")
758 (match_operand:SF 1 "general_operand_src" ""))]
763 if (h8300_expand_movsi (operands))
766 else if (!TARGET_H8300SX)
768 /* One of the ops has to be in a register. */
769 if (!register_operand (operand1, SFmode)
770 && !register_operand (operand0, SFmode))
772 operands[1] = copy_to_mode_reg (SFmode, operand1);
777 (define_insn "*movsf_h8300"
778 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
779 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
781 && (register_operand (operands[0], SFmode)
782 || register_operand (operands[1], SFmode))"
784 /* Copy of the movsi stuff. */
785 unsigned int rn = -1;
786 switch (which_alternative)
789 return "sub.w %e0,%e0\;sub.w %f0,%f0";
791 if (REGNO (operands[0]) < REGNO (operands[1]))
792 return "mov.w %e1,%e0\;mov.w %f1,%f0";
794 return "mov.w %f1,%f0\;mov.w %e1,%e0";
796 /* Make sure we don't trample the register we index with. */
797 if (GET_CODE (operands[1]) == MEM)
799 rtx inside = XEXP (operands[1], 0);
804 else if (GET_CODE (inside) == PLUS)
806 rtx lhs = XEXP (inside, 0);
807 rtx rhs = XEXP (inside, 1);
808 if (REG_P (lhs)) rn = REGNO (lhs);
809 if (REG_P (rhs)) rn = REGNO (rhs);
812 if (rn == REGNO (operands[0]))
813 /* Move the second word first. */
814 return "mov.w %f1,%f0\;mov.w %e1,%e0";
816 /* Move the first word first. */
817 return "mov.w %e1,%e0\;mov.w %f1,%f0";
820 return "mov.w %e1,%e0\;mov.w %f1,%f0";
822 return "mov.w %f1,%T0\;mov.w %e1,%T0";
824 return "mov.w %T1,%e0\;mov.w %T1,%f0";
829 [(set (attr "length")
830 (symbol_ref "compute_mov_length (operands)"))])
832 (define_insn "*movsf_h8300hs"
833 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
834 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
835 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
836 && (register_operand (operands[0], SFmode)
837 || register_operand (operands[1], SFmode))"
845 [(set (attr "length")
846 (symbol_ref "compute_mov_length (operands)"))
847 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
849 ;; ----------------------------------------------------------------------
851 ;; ----------------------------------------------------------------------
853 (define_insn "*pushqi1_h8300"
857 (plus:HI (reg:HI SP_REG) (const_int -2))))
858 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
861 [(set_attr "length" "2")])
863 (define_insn "*pushqi1_h8300hs_<mode>"
867 (plus:P (reg:P SP_REG) (const_int -4))))
868 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
869 "TARGET_H8300H || TARGET_H8300S"
871 [(set_attr "length" "4")])
873 (define_insn "*pushhi1_h8300hs_<mode>"
877 (plus:P (reg:P SP_REG) (const_int -4))))
878 (match_operand:HI 0 "register_no_sp_elim_operand" "r"))]
879 "TARGET_H8300H || TARGET_H8300S"
881 [(set_attr "length" "4")])
883 ;; ----------------------------------------------------------------------
885 ;; ----------------------------------------------------------------------
889 (compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
891 (match_operand 1 "const_int_operand" "n,n"))
895 [(set_attr "length" "2,4")
896 (set_attr "cc" "set_zn,set_zn")])
900 (compare (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
902 (match_operand 1 "const_int_operand" "n"))
906 [(set_attr "length" "2")
907 (set_attr "cc" "set_zn")])
909 (define_insn_and_split "*tst_extzv_1_n"
911 (compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
913 (match_operand 1 "const_int_operand" "n,n,n"))
915 (clobber (match_scratch:QI 2 "=X,X,&r"))]
916 "TARGET_H8300H || TARGET_H8300S"
922 && !satisfies_constraint_U (operands[0])"
925 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2)
929 (clobber (scratch:QI))])]
931 [(set_attr "length" "2,8,10")
932 (set_attr "cc" "set_zn,set_zn,set_zn")])
936 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
938 (match_operand 1 "const_int_operand" "n"))
940 "(TARGET_H8300H || TARGET_H8300S)
941 && INTVAL (operands[1]) <= 15"
943 [(set_attr "length" "2")
944 (set_attr "cc" "set_zn")])
946 (define_insn_and_split "*tstsi_upper_bit"
948 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
950 (match_operand 1 "const_int_operand" "n"))
952 (clobber (match_scratch:SI 2 "=&r"))]
953 "(TARGET_H8300H || TARGET_H8300S)
954 && INTVAL (operands[1]) >= 16"
956 "&& reload_completed"
958 (ior:SI (and:SI (match_dup 2)
960 (lshiftrt:SI (match_dup 0)
963 (compare (zero_extract:SI (match_dup 2)
968 operands[3] = GEN_INT (INTVAL (operands[1]) - 16);
971 (define_insn "*tstsi_variable_bit"
973 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
975 (and:SI (match_operand:SI 1 "register_operand" "r")
978 "TARGET_H8300H || TARGET_H8300S"
980 [(set_attr "length" "2")
981 (set_attr "cc" "set_zn")])
983 (define_insn_and_split "*tstsi_variable_bit_qi"
985 (compare (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
987 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
990 (clobber (match_scratch:QI 2 "=X,X,&r"))]
991 "TARGET_H8300H || TARGET_H8300S"
997 && !satisfies_constraint_U (operands[0])"
1000 (parallel [(set (cc0)
1001 (compare (zero_extract:SI (zero_extend:SI (match_dup 2))
1003 (and:SI (match_dup 1)
1006 (clobber (scratch:QI))])]
1008 [(set_attr "length" "2,8,10")
1009 (set_attr "cc" "set_zn,set_zn,set_zn")])
1011 (define_insn "*tstqi"
1013 (compare (match_operand:QI 0 "register_operand" "r")
1017 [(set_attr "length" "2")
1018 (set_attr "cc" "set_znv")])
1020 (define_insn "*tsthi"
1022 (compare (match_operand:HI 0 "register_operand" "r")
1026 [(set_attr "length" "2")
1027 (set_attr "cc" "set_znv")])
1029 (define_insn "*tsthi_upper"
1031 (compare (and:HI (match_operand:HI 0 "register_operand" "r")
1036 [(set_attr "length" "2")
1037 (set_attr "cc" "set_znv")])
1039 (define_insn "*tstsi"
1041 (compare (match_operand:SI 0 "register_operand" "r")
1043 "TARGET_H8300H || TARGET_H8300S"
1045 [(set_attr "length" "2")
1046 (set_attr "cc" "set_znv")])
1048 (define_insn "*tstsi_upper"
1050 (compare (and:SI (match_operand:SI 0 "register_operand" "r")
1055 [(set_attr "length" "2")
1056 (set_attr "cc" "set_znv")])
1058 (define_insn "*cmpqi"
1060 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
1061 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
1064 [(set_attr "length_table" "addb")
1065 (set_attr "cc" "compare")])
1067 (define_insn "*cmphi_h8300_znvc"
1069 (compare (match_operand:HI 0 "register_operand" "r")
1070 (match_operand:HI 1 "register_operand" "r")))]
1073 [(set_attr "length" "2")
1074 (set_attr "cc" "compare")])
1076 (define_insn "*cmphi_h8300hs_znvc"
1078 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
1079 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
1080 "TARGET_H8300H || TARGET_H8300S"
1082 switch (which_alternative)
1085 if (!TARGET_H8300SX)
1086 return "cmp.w %T1,%T0";
1088 return "cmp.w %T1:3,%T0";
1090 return "cmp.w %T1,%T0";
1095 [(set_attr "length_table" "short_immediate,addw")
1096 (set_attr "cc" "compare,compare")])
1098 (define_insn "cmpsi"
1100 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
1101 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
1102 "TARGET_H8300H || TARGET_H8300S"
1104 switch (which_alternative)
1107 if (!TARGET_H8300SX)
1108 return "cmp.l %S1,%S0";
1110 return "cmp.l %S1:3,%S0";
1112 return "cmp.l %S1,%S0";
1117 [(set_attr "length" "2,*")
1118 (set_attr "length_table" "*,addl")
1119 (set_attr "cc" "compare,compare")])
1121 ;; ----------------------------------------------------------------------
1123 ;; ----------------------------------------------------------------------
1125 (define_expand "addqi3"
1126 [(set (match_operand:QI 0 "register_operand" "")
1127 (plus:QI (match_operand:QI 1 "register_operand" "")
1128 (match_operand:QI 2 "h8300_src_operand" "")))]
1132 (define_insn "*addqi3"
1133 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1134 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
1135 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
1136 "h8300_operands_match_p (operands)"
1138 [(set_attr "length_table" "addb")
1139 (set_attr "cc" "set_zn")])
1141 (define_expand "addhi3"
1142 [(set (match_operand:HI 0 "register_operand" "")
1143 (plus:HI (match_operand:HI 1 "register_operand" "")
1144 (match_operand:HI 2 "h8300_src_operand" "")))]
1148 (define_insn "*addhi3_h8300"
1149 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1150 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1151 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1157 add.b %s2,%s0\;addx %t2,%t0
1159 [(set_attr "length" "2,2,2,4,2")
1160 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1162 ;; This splitter is very important to make the stack adjustment
1163 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1165 ;; We apply this split after the peephole2 pass so that we won't end
1166 ;; up creating too many adds/subs when a scratch register is
1167 ;; available, which is actually a common case because stack unrolling
1168 ;; tends to happen immediately after a function call.
1171 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1172 (plus:HI (match_dup 0)
1173 (match_operand 1 "const_int_gt_2_operand" "")))]
1174 "TARGET_H8300 && epilogue_completed"
1177 split_adds_subs (HImode, operands);
1182 [(match_scratch:HI 2 "r")
1183 (set (match_operand:HI 0 "stack_pointer_operand" "")
1184 (plus:HI (match_dup 0)
1185 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1190 (plus:HI (match_dup 0)
1194 (define_insn "*addhi3_h8300hs"
1195 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1196 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1197 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1198 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1205 [(set_attr "length" "2,2,2,4,2")
1206 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1208 (define_insn "*addhi3_incdec"
1209 [(set (match_operand:HI 0 "register_operand" "=r,r")
1210 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
1211 (match_operand:HI 2 "incdec_operand" "M,O")]
1213 "TARGET_H8300H || TARGET_H8300S"
1217 [(set_attr "length" "2,2")
1218 (set_attr "cc" "set_zn,set_zn")])
1220 (define_insn "*addhi3_h8sx"
1221 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1222 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1223 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1224 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1230 [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
1231 (set_attr "length" "*,*,2,*")
1232 (set_attr "cc" "set_zn")])
1235 [(set (match_operand:HI 0 "register_operand" "")
1236 (plus:HI (match_dup 0)
1237 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1241 split_adds_subs (HImode, operands);
1245 (define_expand "addsi3"
1246 [(set (match_operand:SI 0 "register_operand" "")
1247 (plus:SI (match_operand:SI 1 "register_operand" "")
1248 (match_operand:SI 2 "h8300_src_operand" "")))]
1252 (define_insn "*addsi_h8300"
1253 [(set (match_operand:SI 0 "register_operand" "=r,r")
1254 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1255 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1258 return output_plussi (operands);
1260 [(set (attr "length")
1261 (symbol_ref "compute_plussi_length (operands)"))
1263 (symbol_ref "compute_plussi_cc (operands)"))])
1265 (define_insn "*addsi_h8300hs"
1266 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1267 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1268 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1269 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1271 return output_plussi (operands);
1273 [(set (attr "length")
1274 (symbol_ref "compute_plussi_length (operands)"))
1276 (symbol_ref "compute_plussi_cc (operands)"))])
1278 (define_insn "*addsi3_incdec"
1279 [(set (match_operand:SI 0 "register_operand" "=r,r")
1280 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
1281 (match_operand:SI 2 "incdec_operand" "M,O")]
1283 "TARGET_H8300H || TARGET_H8300S"
1287 [(set_attr "length" "2,2")
1288 (set_attr "cc" "set_zn,set_zn")])
1291 [(set (match_operand:SI 0 "register_operand" "")
1292 (plus:SI (match_dup 0)
1293 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1294 "TARGET_H8300H || TARGET_H8300S"
1297 split_adds_subs (SImode, operands);
1301 ;; ----------------------------------------------------------------------
1302 ;; SUBTRACT INSTRUCTIONS
1303 ;; ----------------------------------------------------------------------
1305 (define_expand "subqi3"
1306 [(set (match_operand:QI 0 "register_operand" "")
1307 (minus:QI (match_operand:QI 1 "register_operand" "")
1308 (match_operand:QI 2 "h8300_src_operand" "")))]
1312 (define_insn "*subqi3"
1313 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1314 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1315 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1316 "h8300_operands_match_p (operands)"
1318 [(set_attr "length_table" "addb")
1319 (set_attr "cc" "set_zn")])
1321 (define_expand "subhi3"
1322 [(set (match_operand:HI 0 "register_operand" "")
1323 (minus:HI (match_operand:HI 1 "register_operand" "")
1324 (match_operand:HI 2 "h8300_src_operand" "")))]
1328 (define_insn "*subhi3_h8300"
1329 [(set (match_operand:HI 0 "register_operand" "=r,r")
1330 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1331 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1335 add.b %E2,%s0\;addx %F2,%t0"
1336 [(set_attr "length" "2,4")
1337 (set_attr "cc" "set_zn,clobber")])
1339 (define_insn "*subhi3_h8300hs"
1340 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
1341 (minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
1342 (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
1343 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1347 [(set_attr "length_table" "addw")
1348 (set_attr "cc" "set_zn")])
1350 (define_expand "subsi3"
1351 [(set (match_operand:SI 0 "register_operand" "")
1352 (minus:SI (match_operand:SI 1 "register_operand" "")
1353 (match_operand:SI 2 "h8300_src_operand" "")))]
1357 operands[2] = force_reg (SImode, operands[2]);
1360 (define_insn "*subsi3_h8300"
1361 [(set (match_operand:SI 0 "register_operand" "=r")
1362 (minus:SI (match_operand:SI 1 "register_operand" "0")
1363 (match_operand:SI 2 "register_operand" "r")))]
1365 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1366 [(set_attr "length" "6")])
1368 (define_insn "*subsi3_h8300hs"
1369 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1370 (minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
1371 (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
1372 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1376 [(set_attr "length_table" "addl")
1377 (set_attr "cc" "set_zn")])
1379 ;; ----------------------------------------------------------------------
1380 ;; MULTIPLY INSTRUCTIONS
1381 ;; ----------------------------------------------------------------------
1383 ;; Note that the H8/300 can only handle umulqihi3.
1385 (define_expand "mulqihi3"
1386 [(set (match_operand:HI 0 "register_operand" "")
1387 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1388 ;; intentionally-mismatched modes
1389 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1390 "TARGET_H8300H || TARGET_H8300S"
1392 if (GET_MODE (operands[2]) != VOIDmode)
1393 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1396 (define_insn "*mulqihi3_const"
1397 [(set (match_operand:HI 0 "register_operand" "=r")
1398 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1399 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1402 [(set_attr "length" "4")
1403 (set_attr "cc" "set_zn")])
1405 (define_insn "*mulqihi3"
1406 [(set (match_operand:HI 0 "register_operand" "=r")
1407 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1408 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1409 "TARGET_H8300H || TARGET_H8300S"
1411 [(set_attr "length" "4")
1412 (set_attr "cc" "set_zn")])
1414 (define_expand "mulhisi3"
1415 [(set (match_operand:SI 0 "register_operand" "")
1416 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1417 ;; intentionally-mismatched modes
1418 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1419 "TARGET_H8300H || TARGET_H8300S"
1421 if (GET_MODE (operands[2]) != VOIDmode)
1422 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1425 (define_insn "*mulhisi3_const"
1426 [(set (match_operand:SI 0 "register_operand" "=r")
1427 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1428 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1431 [(set_attr "length" "4")
1432 (set_attr "cc" "set_zn")])
1434 (define_insn "*mulhisi3"
1435 [(set (match_operand:SI 0 "register_operand" "=r")
1436 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1437 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1438 "TARGET_H8300H || TARGET_H8300S"
1440 [(set_attr "length" "4")
1441 (set_attr "cc" "set_zn")])
1443 (define_expand "umulqihi3"
1444 [(set (match_operand:HI 0 "register_operand" "")
1445 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1446 ;; intentionally-mismatched modes
1447 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1448 "TARGET_H8300H || TARGET_H8300S"
1450 if (GET_MODE (operands[2]) != VOIDmode)
1451 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1454 (define_insn "*umulqihi3_const"
1455 [(set (match_operand:HI 0 "register_operand" "=r")
1456 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1457 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1460 [(set_attr "length" "4")
1461 (set_attr "cc" "set_zn")])
1463 (define_insn "*umulqihi3"
1464 [(set (match_operand:HI 0 "register_operand" "=r")
1465 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1466 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1469 [(set_attr "length" "2")
1470 (set_attr "cc" "none_0hit")])
1472 (define_expand "umulhisi3"
1473 [(set (match_operand:SI 0 "register_operand" "")
1474 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1475 ;; intentionally-mismatched modes
1476 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1477 "TARGET_H8300H || TARGET_H8300S"
1479 if (GET_MODE (operands[2]) != VOIDmode)
1480 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1483 (define_insn "*umulhisi3_const"
1484 [(set (match_operand:SI 0 "register_operand" "=r")
1485 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1486 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1489 [(set_attr "length" "4")
1490 (set_attr "cc" "set_zn")])
1492 (define_insn "*umulhisi3"
1493 [(set (match_operand:SI 0 "register_operand" "=r")
1494 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1495 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1496 "TARGET_H8300H || TARGET_H8300S"
1498 [(set_attr "length" "2")
1499 (set_attr "cc" "none_0hit")])
1501 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1502 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1503 ;; on all H8SX variants.
1505 (define_insn "mulhi3"
1506 [(set (match_operand:HI 0 "register_operand" "=r")
1507 (mult:HI (match_operand:HI 1 "register_operand" "%0")
1508 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1511 [(set_attr "length" "2")
1512 (set_attr "cc" "set_zn")])
1514 (define_insn "mulsi3"
1515 [(set (match_operand:SI 0 "register_operand" "=r")
1516 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1517 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1520 [(set_attr "length" "2")
1521 (set_attr "cc" "set_zn")])
1523 (define_insn "smulsi3_highpart"
1524 [(set (match_operand:SI 0 "register_operand" "=r")
1528 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1529 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1532 "muls/u.l\\t%S2,%S0"
1533 [(set_attr "length" "2")
1534 (set_attr "cc" "set_zn")])
1536 (define_insn "umulsi3_highpart"
1537 [(set (match_operand:SI 0 "register_operand" "=r")
1541 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1542 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1545 "mulu/u.l\\t%S2,%S0"
1546 [(set_attr "length" "2")
1547 (set_attr "cc" "none_0hit")])
1549 ;; This is a "bridge" instruction. Combine can't cram enough insns
1550 ;; together to crate a MAC instruction directly, but it can create
1551 ;; this instruction, which then allows combine to create the real
1554 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1555 ;; insn must generate reasonably correct code. Egad.
1558 [(set (match_operand:SI 0 "register_operand" "=a")
1561 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1563 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1565 "clrmac\;mac @%2+,@%1+"
1566 [(set_attr "length" "6")
1567 (set_attr "cc" "none_0hit")])
1570 [(set (match_operand:SI 0 "register_operand" "=a")
1572 (sign_extend:SI (mem:HI
1573 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1574 (sign_extend:SI (mem:HI
1575 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1576 (match_operand:SI 3 "register_operand" "0")))]
1579 [(set_attr "length" "4")
1580 (set_attr "cc" "none_0hit")])
1582 ;; ----------------------------------------------------------------------
1583 ;; DIVIDE/MOD INSTRUCTIONS
1584 ;; ----------------------------------------------------------------------
1586 (define_insn "udivhi3"
1587 [(set (match_operand:HI 0 "register_operand" "=r")
1588 (udiv:HI (match_operand:HI 1 "register_operand" "0")
1589 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1592 [(set_attr "length" "2")])
1594 (define_insn "divhi3"
1595 [(set (match_operand:HI 0 "register_operand" "=r")
1596 (div:HI (match_operand:HI 1 "register_operand" "0")
1597 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
1600 [(set_attr "length" "2")])
1602 (define_insn "udivsi3"
1603 [(set (match_operand:SI 0 "register_operand" "=r")
1604 (udiv:SI (match_operand:SI 1 "register_operand" "0")
1605 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1608 [(set_attr "length" "2")])
1610 (define_insn "divsi3"
1611 [(set (match_operand:SI 0 "register_operand" "=r")
1612 (div:SI (match_operand:SI 1 "register_operand" "0")
1613 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
1616 [(set_attr "length" "2")])
1618 (define_insn "udivmodqi4"
1619 [(set (match_operand:QI 0 "register_operand" "=r")
1622 (match_operand:HI 1 "register_operand" "0")
1623 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1624 (set (match_operand:QI 3 "register_operand" "=r")
1628 (zero_extend:HI (match_dup 2)))))]
1631 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1632 return "divxu.b\\t%X2,%T0";
1634 return "divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1636 [(set_attr "length" "4")])
1638 (define_insn "divmodqi4"
1639 [(set (match_operand:QI 0 "register_operand" "=r")
1642 (match_operand:HI 1 "register_operand" "0")
1643 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1644 (set (match_operand:QI 3 "register_operand" "=r")
1648 (sign_extend:HI (match_dup 2)))))]
1649 "TARGET_H8300H || TARGET_H8300S"
1651 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1652 return "divxs.b\\t%X2,%T0";
1654 return "divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1656 [(set_attr "length" "6")])
1658 (define_insn "udivmodhi4"
1659 [(set (match_operand:HI 0 "register_operand" "=r")
1662 (match_operand:SI 1 "register_operand" "0")
1663 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1664 (set (match_operand:HI 3 "register_operand" "=r")
1668 (zero_extend:SI (match_dup 2)))))]
1669 "TARGET_H8300H || TARGET_H8300S"
1671 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1672 return "divxu.w\\t%T2,%S0";
1674 return "divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1676 [(set_attr "length" "4")])
1678 (define_insn "divmodhi4"
1679 [(set (match_operand:HI 0 "register_operand" "=r")
1682 (match_operand:SI 1 "register_operand" "0")
1683 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1684 (set (match_operand:HI 3 "register_operand" "=r")
1688 (sign_extend:SI (match_dup 2)))))]
1689 "TARGET_H8300H || TARGET_H8300S"
1691 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1692 return "divxs.w\\t%T2,%S0";
1694 return "divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1696 [(set_attr "length" "6")])
1698 ;; ----------------------------------------------------------------------
1700 ;; ----------------------------------------------------------------------
1702 (define_insn "bclrqi_msx"
1703 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1704 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1705 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1706 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1708 [(set_attr "length" "8")])
1711 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1712 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1713 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1716 (and:QI (match_dup 1)
1719 if (abs (INTVAL (operands[2])) > 0xFF)
1721 operands[0] = adjust_address (operands[0], QImode, 0);
1722 operands[1] = adjust_address (operands[1], QImode, 0);
1723 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1727 operands[0] = adjust_address (operands[0], QImode, 1);
1728 operands[1] = adjust_address (operands[1], QImode, 1);
1732 (define_insn "bclrhi_msx"
1733 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1734 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1735 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1738 [(set_attr "length" "8")])
1740 (define_insn "*andqi3_2"
1741 [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
1742 (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
1743 (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
1749 [(set_attr "length" "8,*,8")
1750 (set_attr "length_table" "*,logicb,*")
1751 (set_attr "cc" "none_0hit,set_znv,none_0hit")])
1753 (define_insn "andqi3_1"
1754 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1755 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1756 (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
1757 "register_operand (operands[0], QImode)
1758 || single_zero_operand (operands[2], QImode)"
1762 [(set_attr "length" "2,8")
1763 (set_attr "cc" "none_0hit,set_znv")])
1765 (define_expand "andqi3"
1766 [(set (match_operand:QI 0 "register_operand" "")
1767 (and:QI (match_operand:QI 1 "register_operand" "")
1768 (match_operand:QI 2 "h8300_src_operand" "")))]
1772 (define_expand "andhi3"
1773 [(set (match_operand:HI 0 "register_operand" "")
1774 (and:HI (match_operand:HI 1 "register_operand" "")
1775 (match_operand:HI 2 "h8300_src_operand" "")))]
1779 (define_insn "*andorqi3"
1780 [(set (match_operand:QI 0 "register_operand" "=r")
1781 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1782 (match_operand:QI 3 "single_one_operand" "n"))
1783 (match_operand:QI 1 "register_operand" "0")))]
1785 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1786 [(set_attr "length" "6")])
1788 (define_insn "*andorhi3"
1789 [(set (match_operand:HI 0 "register_operand" "=r")
1790 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1791 (match_operand:HI 3 "single_one_operand" "n"))
1792 (match_operand:HI 1 "register_operand" "0")))]
1795 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1796 if (INTVAL (operands[3]) > 128)
1798 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1799 return "bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0";
1801 return "bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0";
1803 [(set_attr "length" "6")])
1805 (define_insn "*andorsi3"
1806 [(set (match_operand:SI 0 "register_operand" "=r")
1807 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1808 (match_operand:SI 3 "single_one_operand" "n"))
1809 (match_operand:SI 1 "register_operand" "0")))]
1810 "(INTVAL (operands[3]) & 0xffff) != 0"
1812 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1813 if (INTVAL (operands[3]) > 128)
1815 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1816 return "bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0";
1818 return "bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0";
1820 [(set_attr "length" "6")])
1822 (define_insn "*andorsi3_shift_8"
1823 [(set (match_operand:SI 0 "register_operand" "=r")
1824 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1827 (match_operand:SI 1 "register_operand" "0")))]
1830 [(set_attr "length" "2")])
1832 (define_expand "andsi3"
1833 [(set (match_operand:SI 0 "register_operand" "")
1834 (and:SI (match_operand:SI 1 "register_operand" "")
1835 (match_operand:SI 2 "h8300_src_operand" "")))]
1839 ;; ----------------------------------------------------------------------
1841 ;; ----------------------------------------------------------------------
1843 (define_insn "bsetqi_msx"
1844 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1845 (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1846 (match_operand:QI 2 "single_one_operand" "Y2")))]
1847 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1849 [(set_attr "length" "8")])
1852 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1853 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1854 (match_operand:HI 2 "single_one_operand" "Y2")))]
1857 (ior:QI (match_dup 1)
1860 if (abs (INTVAL (operands[2])) > 0xFF)
1862 operands[0] = adjust_address (operands[0], QImode, 0);
1863 operands[1] = adjust_address (operands[1], QImode, 0);
1864 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1868 operands[0] = adjust_address (operands[0], QImode, 1);
1869 operands[1] = adjust_address (operands[1], QImode, 1);
1873 (define_insn "bsethi_msx"
1874 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1875 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1876 (match_operand:HI 2 "single_one_operand" "Y2")))]
1879 [(set_attr "length" "8")])
1881 (define_insn "iorqi3_1"
1882 [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
1883 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1884 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1885 "TARGET_H8300SX || register_operand (operands[0], QImode)
1886 || single_one_operand (operands[2], QImode)"
1890 [(set_attr "length" "8,*")
1891 (set_attr "length_table" "*,logicb")
1892 (set_attr "cc" "none_0hit,set_znv")])
1895 (define_expand "iorqi3"
1896 [(set (match_operand:QI 0 "register_operand" "")
1897 (ior:QI (match_operand:QI 1 "register_operand" "")
1898 (match_operand:QI 2 "h8300_src_operand" "")))]
1902 (define_expand "iorhi3"
1903 [(set (match_operand:HI 0 "register_operand" "")
1904 (ior:HI (match_operand:HI 1 "register_operand" "")
1905 (match_operand:HI 2 "h8300_src_operand" "")))]
1909 (define_expand "iorsi3"
1910 [(set (match_operand:SI 0 "register_operand" "")
1911 (ior:SI (match_operand:SI 1 "register_operand" "")
1912 (match_operand:SI 2 "h8300_src_operand" "")))]
1916 ;; ----------------------------------------------------------------------
1918 ;; ----------------------------------------------------------------------
1920 (define_insn "bnotqi_msx"
1921 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1922 (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1923 (match_operand:QI 2 "single_one_operand" "Y2")))]
1925 && rtx_equal_p (operands[0], operands[1])"
1927 [(set_attr "length" "8")])
1930 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=U")
1931 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1932 (match_operand:HI 2 "single_one_operand" "Y2")))]
1935 (xor:QI (match_dup 1)
1938 if (abs (INTVAL (operands[2])) > 0xFF)
1940 operands[0] = adjust_address (operands[0], QImode, 0);
1941 operands[1] = adjust_address (operands[1], QImode, 0);
1942 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1946 operands[0] = adjust_address (operands[0], QImode, 1);
1947 operands[1] = adjust_address (operands[1], QImode, 1);
1951 (define_insn "bnothi_msx"
1952 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1953 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1954 (match_operand:HI 2 "single_one_operand" "Y2")))]
1957 [(set_attr "length" "8")])
1959 (define_insn "xorqi3_1"
1960 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1961 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1962 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1963 "TARGET_H8300SX || register_operand (operands[0], QImode)
1964 || single_one_operand (operands[2], QImode)"
1968 [(set_attr "length" "8,*")
1969 (set_attr "length_table" "*,logicb")
1970 (set_attr "cc" "none_0hit,set_znv")])
1972 (define_expand "xorqi3"
1973 [(set (match_operand:QI 0 "register_operand" "")
1974 (xor:QI (match_operand:QI 1 "register_operand" "")
1975 (match_operand:QI 2 "h8300_src_operand" "")))]
1979 (define_expand "xorhi3"
1980 [(set (match_operand:HI 0 "register_operand" "")
1981 (xor:HI (match_operand:HI 1 "register_operand" "")
1982 (match_operand:HI 2 "h8300_src_operand" "")))]
1986 (define_expand "xorsi3"
1987 [(set (match_operand:SI 0 "register_operand" "")
1988 (xor:SI (match_operand:SI 1 "register_operand" "")
1989 (match_operand:SI 2 "h8300_src_operand" "")))]
1993 ;; ----------------------------------------------------------------------
1994 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1995 ;; ----------------------------------------------------------------------
1997 ;; We need a separate pattern here because machines other than the
1998 ;; original H8300 don't have to split the 16-bit operand into a pair
1999 ;; of high/low instructions, so we can accept literal addresses, that
2000 ;; have to be loaded into a register on H8300.
2002 (define_insn "*logicalhi3_sn"
2003 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2004 (match_operator:HI 3 "bit_operator"
2005 [(match_operand:HI 1 "h8300_dst_operand" "%0")
2006 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
2007 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
2009 return output_logical_op (HImode, operands);
2011 [(set (attr "length")
2012 (symbol_ref "compute_logical_op_length (HImode, operands)"))
2014 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2016 (define_insn "*logicalsi3_sn"
2017 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2018 (match_operator:SI 3 "bit_operator"
2019 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2020 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2021 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
2023 return output_logical_op (SImode, operands);
2025 [(set (attr "length")
2026 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2028 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2030 (define_insn "*logicalhi3"
2031 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2032 (match_operator:HI 3 "bit_operator"
2033 [(match_operand:HI 1 "h8300_dst_operand" "%0")
2034 (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
2035 "h8300_operands_match_p (operands)"
2037 return output_logical_op (HImode, operands);
2039 [(set (attr "length")
2040 (symbol_ref "compute_logical_op_length (HImode, operands)"))
2042 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
2044 (define_insn "*logicalsi3"
2045 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2046 (match_operator:SI 3 "bit_operator"
2047 [(match_operand:SI 1 "h8300_dst_operand" "%0")
2048 (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
2049 "h8300_operands_match_p (operands)"
2051 return output_logical_op (SImode, operands);
2053 [(set (attr "length")
2054 (symbol_ref "compute_logical_op_length (SImode, operands)"))
2056 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
2058 ;; ----------------------------------------------------------------------
2059 ;; NEGATION INSTRUCTIONS
2060 ;; ----------------------------------------------------------------------
2062 (define_expand "negqi2"
2063 [(set (match_operand:QI 0 "register_operand" "")
2064 (neg:QI (match_operand:QI 1 "register_operand" "")))]
2068 (define_insn "*negqi2"
2069 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2070 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2073 [(set_attr "length_table" "unary")
2074 (set_attr "cc" "set_zn")])
2076 (define_expand "neghi2"
2077 [(set (match_operand:HI 0 "register_operand" "")
2078 (neg:HI (match_operand:HI 1 "register_operand" "")))]
2083 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
2088 (define_expand "neghi2_h8300"
2090 (not:HI (match_operand:HI 1 "register_operand" "")))
2091 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
2092 (set (match_operand:HI 0 "register_operand" "")
2096 operands[2] = gen_reg_rtx (HImode);
2099 (define_insn "*neghi2_h8300hs"
2100 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2101 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2102 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2104 [(set_attr "length_table" "unary")
2105 (set_attr "cc" "set_zn")])
2107 (define_expand "negsi2"
2108 [(set (match_operand:SI 0 "register_operand" "")
2109 (neg:SI (match_operand:SI 1 "register_operand" "")))]
2114 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
2119 (define_expand "negsi2_h8300"
2121 (not:SI (match_operand:SI 1 "register_operand" "")))
2122 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
2123 (set (match_operand:SI 0 "register_operand" "")
2127 operands[2] = gen_reg_rtx (SImode);
2130 (define_insn "*negsi2_h8300hs"
2131 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2132 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2133 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2135 [(set_attr "length_table" "unary")
2136 (set_attr "cc" "set_zn")])
2138 (define_expand "negsf2"
2139 [(set (match_operand:SF 0 "register_operand" "")
2140 (neg:SF (match_operand:SF 1 "register_operand" "")))]
2144 (define_insn "*negsf2_h8300"
2145 [(set (match_operand:SF 0 "register_operand" "=r")
2146 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2149 [(set_attr "length" "2")])
2151 (define_insn "*negsf2_h8300hs"
2152 [(set (match_operand:SF 0 "register_operand" "=r")
2153 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
2154 "TARGET_H8300H || TARGET_H8300S"
2155 "xor.w\\t#32768,%e0"
2156 [(set_attr "length" "4")])
2158 ;; ----------------------------------------------------------------------
2159 ;; ABSOLUTE VALUE INSTRUCTIONS
2160 ;; ----------------------------------------------------------------------
2162 (define_expand "abssf2"
2163 [(set (match_operand:SF 0 "register_operand" "")
2164 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2168 (define_insn "*abssf2_h8300"
2169 [(set (match_operand:SF 0 "register_operand" "=r")
2170 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2173 [(set_attr "length" "2")])
2175 (define_insn "*abssf2_h8300hs"
2176 [(set (match_operand:SF 0 "register_operand" "=r")
2177 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2178 "TARGET_H8300H || TARGET_H8300S"
2179 "and.w\\t#32767,%e0"
2180 [(set_attr "length" "4")])
2182 ;; ----------------------------------------------------------------------
2184 ;; ----------------------------------------------------------------------
2186 (define_expand "one_cmplqi2"
2187 [(set (match_operand:QI 0 "register_operand" "")
2188 (not:QI (match_operand:QI 1 "register_operand" "")))]
2192 (define_insn "*one_cmplqi2"
2193 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2194 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
2197 [(set_attr "length_table" "unary")
2198 (set_attr "cc" "set_znv")])
2200 (define_expand "one_cmplhi2"
2201 [(set (match_operand:HI 0 "register_operand" "")
2202 (not:HI (match_operand:HI 1 "register_operand" "")))]
2206 (define_insn "*one_cmplhi2_h8300"
2207 [(set (match_operand:HI 0 "register_operand" "=r")
2208 (not:HI (match_operand:HI 1 "register_operand" "0")))]
2211 [(set_attr "length" "4")])
2213 (define_insn "*one_cmplhi2_h8300hs"
2214 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2215 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
2216 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2218 [(set_attr "cc" "set_znv")
2219 (set_attr "length_table" "unary")])
2221 (define_expand "one_cmplsi2"
2222 [(set (match_operand:SI 0 "register_operand" "")
2223 (not:SI (match_operand:SI 1 "register_operand" "")))]
2227 (define_insn "*one_cmplsi2_h8300"
2228 [(set (match_operand:SI 0 "register_operand" "=r")
2229 (not:SI (match_operand:SI 1 "register_operand" "0")))]
2231 "not %w0\;not %x0\;not %y0\;not %z0"
2232 [(set_attr "length" "8")])
2234 (define_insn "*one_cmplsi2_h8300hs"
2235 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2236 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
2237 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
2239 [(set_attr "cc" "set_znv")
2240 (set_attr "length_table" "unary")])
2242 ;; ----------------------------------------------------------------------
2243 ;; JUMP INSTRUCTIONS
2244 ;; ----------------------------------------------------------------------
2246 ;; Conditional jump instructions
2248 (define_expand "cbranchqi4"
2249 [(use (match_operator 0 "ordered_comparison_operator"
2250 [(match_operand:QI 1 "h8300_dst_operand" "")
2251 (match_operand:QI 2 "h8300_src_operand" "")]))
2252 (use (match_operand 3 ""))]
2255 h8300_expand_branch (operands);
2259 (define_expand "cbranchhi4"
2260 [(use (match_operator 0 "ordered_comparison_operator"
2261 [(match_operand:HI 1 "h8300_dst_operand" "")
2262 (match_operand:HI 2 "h8300_src_operand" "")]))
2263 (use (match_operand 3 ""))]
2266 /* Force operand1 into a register if we're compiling
2268 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
2270 operands[2] = force_reg (HImode, operands[2]);
2271 h8300_expand_branch (operands);
2275 (define_expand "cbranchsi4"
2276 [(use (match_operator 0 "ordered_comparison_operator"
2277 [(match_operand:SI 1 "h8300_dst_operand" "")
2278 (match_operand:SI 2 "h8300_src_operand" "")]))
2279 (use (match_operand 3 ""))]
2280 "TARGET_H8300H || TARGET_H8300S"
2282 h8300_expand_branch (operands);
2286 (define_insn "branch_true"
2288 (if_then_else (match_operator 1 "comparison_operator"
2289 [(cc0) (const_int 0)])
2290 (label_ref (match_operand 0 "" ""))
2294 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2295 && (GET_CODE (operands[1]) == GT
2296 || GET_CODE (operands[1]) == GE
2297 || GET_CODE (operands[1]) == LE
2298 || GET_CODE (operands[1]) == LT))
2300 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2304 if (get_attr_length (insn) == 2)
2306 else if (get_attr_length (insn) == 4)
2307 return "b%j1 %l0:16";
2309 return "b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2311 [(set_attr "type" "branch")
2312 (set_attr "cc" "none")])
2314 (define_insn "branch_false"
2316 (if_then_else (match_operator 1 "comparison_operator"
2317 [(cc0) (const_int 0)])
2319 (label_ref (match_operand 0 "" ""))))]
2322 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
2323 && (GET_CODE (operands[1]) == GT
2324 || GET_CODE (operands[1]) == GE
2325 || GET_CODE (operands[1]) == LE
2326 || GET_CODE (operands[1]) == LT))
2328 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
2332 if (get_attr_length (insn) == 2)
2334 else if (get_attr_length (insn) == 4)
2335 return "b%k1 %l0:16";
2337 return "b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2339 [(set_attr "type" "branch")
2340 (set_attr "cc" "none")])
2342 (define_insn "*brabc"
2344 (if_then_else (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2346 (match_operand:QI 2 "immediate_operand" "n"))
2348 (label_ref (match_operand 0 "" ""))
2352 switch (get_attr_length (insn)
2353 - h8300_insn_length_from_table (insn, operands))
2356 return "bra/bc %2,%R1,%l0";
2358 return "bra/bc %2,%R1,%l0:16";
2360 return "bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2363 [(set_attr "type" "bitbranch")
2364 (set_attr "length_table" "bitbranch")
2365 (set_attr "cc" "none")])
2367 (define_insn "*brabs"
2369 (if_then_else (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2371 (match_operand:QI 2 "immediate_operand" "n"))
2373 (label_ref (match_operand 0 "" ""))
2377 switch (get_attr_length (insn)
2378 - h8300_insn_length_from_table (insn, operands))
2381 return "bra/bs %2,%R1,%l0";
2383 return "bra/bs %2,%R1,%l0:16";
2385 return "bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2388 [(set_attr "type" "bitbranch")
2389 (set_attr "length_table" "bitbranch")
2390 (set_attr "cc" "none")])
2392 ;; Unconditional and other jump instructions.
2396 (label_ref (match_operand 0 "" "")))]
2399 if (final_sequence != 0)
2401 if (get_attr_length (insn) == 2)
2405 /* The branch isn't short enough to use bra/s. Output the
2406 branch and delay slot in their normal order.
2408 If this is a backward branch, it will now be branching two
2409 bytes further than previously thought. The length-based
2410 test for bra vs. jump is very conservative though, so the
2411 branch will still be within range. */
2415 vec = XVEC (final_sequence, 0);
2417 final_scan_insn (RTVEC_ELT (vec, 1), asm_out_file, optimize, 1, & seen);
2418 final_scan_insn (RTVEC_ELT (vec, 0), asm_out_file, optimize, 1, & seen);
2419 INSN_DELETED_P (RTVEC_ELT (vec, 1)) = 1;
2423 else if (get_attr_length (insn) == 2)
2425 else if (get_attr_length (insn) == 4)
2426 return "bra %l0:16";
2430 [(set_attr "type" "branch")
2431 (set (attr "delay_slot")
2432 (if_then_else (match_test "TARGET_H8300SX")
2433 (const_string "jump")
2434 (const_string "none")))
2435 (set_attr "cc" "none")])
2437 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2439 (define_expand "tablejump"
2440 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2441 (use (label_ref (match_operand 1 "" "")))])]
2445 (define_insn "*tablejump_h8300"
2446 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2447 (use (label_ref (match_operand 1 "" "")))]
2450 [(set_attr "cc" "none")
2451 (set_attr "length" "2")])
2453 (define_insn "*tablejump_h8300hs_advanced"
2454 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2455 (use (label_ref (match_operand 1 "" "")))]
2456 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2458 [(set_attr "cc" "none")
2459 (set_attr "length" "2")])
2461 (define_insn "*tablejump_h8300hs_normal"
2462 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2463 (use (label_ref (match_operand 1 "" "")))]
2464 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2466 [(set_attr "cc" "none")
2467 (set_attr "length" "2")])
2469 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2471 (define_expand "indirect_jump"
2472 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2476 (define_insn "*indirect_jump_h8300"
2477 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2480 [(set_attr "cc" "none")
2481 (set_attr "length" "2")])
2483 (define_insn "*indirect_jump_h8300hs_advanced"
2484 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2485 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2487 [(set_attr "cc" "none")
2488 (set_attr "length" "2")])
2490 (define_insn "*indirect_jump_h8300hs_normal"
2491 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2492 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2494 [(set_attr "cc" "none")
2495 (set_attr "length" "2")])
2497 ;; Call subroutine with no return value.
2499 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2502 [(call (match_operand:QI 0 "call_insn_operand" "or")
2503 (match_operand:HI 1 "general_operand" "g"))]
2506 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2507 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
2508 return "jsr\\t@%0:8";
2512 [(set_attr "type" "call")
2513 (set (attr "length")
2514 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2518 ;; Call subroutine, returning value in operand 0
2519 ;; (which must be a hard register).
2521 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2523 (define_insn "call_value"
2524 [(set (match_operand 0 "" "=r")
2525 (call (match_operand:QI 1 "call_insn_operand" "or")
2526 (match_operand:HI 2 "general_operand" "g")))]
2529 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2530 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
2531 return "jsr\\t@%1:8";
2535 [(set_attr "type" "call")
2536 (set (attr "length")
2537 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2545 [(set_attr "cc" "none")
2546 (set_attr "length" "2")])
2548 ;; ----------------------------------------------------------------------
2549 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2550 ;; ----------------------------------------------------------------------
2552 (define_expand "push_h8300"
2553 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2554 (match_operand:HI 0 "register_operand" ""))]
2558 (define_expand "push_h8300hs_advanced"
2559 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2560 (match_operand:SI 0 "register_operand" ""))]
2561 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2564 (define_expand "push_h8300hs_normal"
2565 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2566 (match_operand:SI 0 "register_operand" ""))]
2567 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2570 (define_expand "pop_h8300"
2571 [(set (match_operand:HI 0 "register_operand" "")
2572 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2576 (define_expand "pop_h8300hs_advanced"
2577 [(set (match_operand:SI 0 "register_operand" "")
2578 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2579 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2582 (define_expand "pop_h8300hs_normal"
2583 [(set (match_operand:SI 0 "register_operand" "")
2584 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2585 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2588 (define_insn "ldm_h8300sx"
2589 [(match_parallel 0 "h8300_ldm_parallel"
2590 [(set (match_operand:SI 1 "register_operand" "")
2591 (match_operand:SI 2 "memory_operand" ""))])]
2594 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2595 XVECLEN (operands[0], 0) - 2));
2596 return "ldm.l\t@er7+,%S1-%S3";
2598 [(set_attr "cc" "none")
2599 (set_attr "length" "4")])
2601 (define_insn "stm_h8300sx"
2602 [(match_parallel 0 "h8300_stm_parallel"
2603 [(set (match_operand:SI 1 "memory_operand" "")
2604 (match_operand:SI 2 "register_operand" ""))])]
2607 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2608 XVECLEN (operands[0], 0) - 2));
2609 return "stm.l\t%S2-%S3,@-er7";
2611 [(set_attr "cc" "none")
2612 (set_attr "length" "4")])
2614 (define_insn "return_h8sx"
2615 [(match_parallel 0 "h8300_return_parallel"
2617 (set (match_operand:SI 1 "register_operand" "")
2618 (match_operand:SI 2 "memory_operand" ""))])]
2621 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2622 XVECLEN (operands[0], 0) - 2));
2623 if (h8300_current_function_interrupt_function_p ()
2624 || h8300_current_function_monitor_function_p ())
2625 return "rte/l\t%S1-%S3";
2627 return "rts/l\t%S1-%S3";
2629 [(set_attr "cc" "none")
2630 (set_attr "can_delay" "no")
2631 (set_attr "length" "2")])
2633 (define_expand "return"
2635 "h8300_can_use_return_insn_p ()"
2638 (define_insn "*return_1"
2642 if (h8300_current_function_interrupt_function_p ()
2643 || h8300_current_function_monitor_function_p ())
2648 [(set_attr "cc" "none")
2649 (set_attr "can_delay" "no")
2650 (set_attr "length" "2")])
2652 (define_expand "prologue"
2656 h8300_expand_prologue ();
2660 (define_expand "epilogue"
2664 h8300_expand_epilogue ();
2668 (define_insn "monitor_prologue"
2669 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2673 return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr";
2674 else if (TARGET_H8300H && TARGET_NORMAL_MODE)
2675 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2676 else if (TARGET_H8300H)
2677 return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2678 else if (TARGET_H8300S && TARGET_NORMAL_MODE)
2679 return "subs\\t#2,er7\;stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2680 else if (TARGET_H8300S)
2681 return "stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2684 [(set_attr "length" "20")])
2686 ;; ----------------------------------------------------------------------
2687 ;; EXTEND INSTRUCTIONS
2688 ;; ----------------------------------------------------------------------
2690 (define_expand "zero_extendqihi2"
2691 [(set (match_operand:HI 0 "register_operand" "")
2692 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2696 (define_insn "*zero_extendqihi2_h8300"
2697 [(set (match_operand:HI 0 "register_operand" "=r,r")
2698 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2703 [(set_attr "length" "2,10")])
2705 (define_insn "*zero_extendqihi2_h8300hs"
2706 [(set (match_operand:HI 0 "register_operand" "=r,r")
2707 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2708 "TARGET_H8300H || TARGET_H8300S"
2712 [(set_attr "length" "2,10")
2713 (set_attr "cc" "set_znv,set_znv")])
2715 ;; Split the zero extension of a general operand (actually a memory
2716 ;; operand) into a load of the operand and the actual zero extension
2717 ;; so that 1) the length will be accurate, and 2) the zero extensions
2718 ;; appearing at the end of basic blocks may be merged.
2721 [(set (match_operand:HI 0 "register_operand" "")
2722 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2727 (zero_extend:HI (match_dup 2)))]
2729 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2732 (define_expand "zero_extendqisi2"
2733 [(set (match_operand:SI 0 "register_operand" "")
2734 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2738 operands[1] = force_reg (QImode, operands[1]);
2741 (define_insn "*zero_extendqisi2_h8300"
2742 [(set (match_operand:SI 0 "register_operand" "=r,r")
2743 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2746 mov.b #0,%x0\;sub.w %e0,%e0
2747 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2748 [(set_attr "length" "4,8")])
2750 (define_insn "*zero_extendqisi2_h8300hs"
2751 [(set (match_operand:SI 0 "register_operand" "=r,r")
2752 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2753 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2757 [(set (match_operand:SI 0 "register_operand" "")
2758 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2759 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2760 && reg_overlap_mentioned_p (operands[0], operands[1])
2761 && reload_completed"
2765 (zero_extend:HI (match_dup 2)))
2767 (zero_extend:SI (match_dup 3)))]
2769 operands[2] = gen_lowpart (QImode, operands[0]);
2770 operands[3] = gen_lowpart (HImode, operands[0]);
2774 [(set (match_operand:SI 0 "register_operand" "")
2775 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2776 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2777 && !reg_overlap_mentioned_p (operands[0], operands[1])
2778 && reload_completed"
2781 (set (strict_low_part (match_dup 2))
2784 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2787 (define_insn "*zero_extendqisi2_h8sx"
2788 [(set (match_operand:SI 0 "register_operand" "=r")
2789 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2792 [(set_attr "length" "2")
2793 (set_attr "cc" "set_znv")])
2795 (define_expand "zero_extendhisi2"
2796 [(set (match_operand:SI 0 "register_operand" "")
2797 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2801 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2802 (define_insn "*zero_extendhisi2_h8300"
2803 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2804 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2808 mov.w %f1,%f0\;sub.w %e0,%e0
2809 mov.w %e1,%f0\;sub.w %e0,%e0"
2810 [(set_attr "length" "2,4,6")])
2812 (define_insn "*zero_extendhisi2_h8300hs"
2813 [(set (match_operand:SI 0 "register_operand" "=r")
2814 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2815 "TARGET_H8300H || TARGET_H8300S"
2817 [(set_attr "length" "2")
2818 (set_attr "cc" "set_znv")])
2820 (define_expand "extendqihi2"
2821 [(set (match_operand:HI 0 "register_operand" "")
2822 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2826 (define_insn "*extendqihi2_h8300"
2827 [(set (match_operand:HI 0 "register_operand" "=r,r")
2828 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2831 bld #7,%s0\;subx %t0,%t0
2832 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2833 [(set_attr "length" "4,8")])
2835 (define_insn "*extendqihi2_h8300hs"
2836 [(set (match_operand:HI 0 "register_operand" "=r")
2837 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2838 "TARGET_H8300H || TARGET_H8300S"
2840 [(set_attr "length" "2")
2841 (set_attr "cc" "set_znv")])
2843 (define_expand "extendqisi2"
2844 [(set (match_operand:SI 0 "register_operand" "")
2845 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2849 (define_insn "*extendqisi2_h8300"
2850 [(set (match_operand:SI 0 "register_operand" "=r,r")
2851 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2854 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2855 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2856 [(set_attr "length" "8,12")])
2858 ;; The following pattern is needed because without the pattern, the
2859 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2860 ;; shifts, one ashift and one ashiftrt.
2862 (define_insn_and_split "*extendqisi2_h8300hs"
2863 [(set (match_operand:SI 0 "register_operand" "=r")
2864 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2865 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2867 "&& reload_completed"
2869 (sign_extend:HI (match_dup 1)))
2871 (sign_extend:SI (match_dup 2)))]
2873 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
2876 (define_insn "*extendqisi2_h8sx"
2877 [(set (match_operand:SI 0 "register_operand" "=r")
2878 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2881 [(set_attr "length" "2")
2882 (set_attr "cc" "set_znv")])
2884 (define_expand "extendhisi2"
2885 [(set (match_operand:SI 0 "register_operand" "")
2886 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2890 (define_insn "*extendhisi2_h8300"
2891 [(set (match_operand:SI 0 "register_operand" "=r,r")
2892 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2895 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2896 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2897 [(set_attr "length" "6,10")])
2899 (define_insn "*extendhisi2_h8300hs"
2900 [(set (match_operand:SI 0 "register_operand" "=r")
2901 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2902 "TARGET_H8300H || TARGET_H8300S"
2904 [(set_attr "length" "2")
2905 (set_attr "cc" "set_znv")])
2907 ;; ----------------------------------------------------------------------
2909 ;; ----------------------------------------------------------------------
2911 ;; We make some attempt to provide real efficient shifting. One example is
2912 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2913 ;; reg and moving 0 into the former reg.
2915 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2916 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2917 ;; give the optimizer more cracks at the code. However, we wish to do things
2918 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2919 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2920 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2921 ;; to detect cases it can optimize.
2923 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2924 ;; easier "do it at insn emit time" route.
2928 (define_expand "ashlqi3"
2929 [(set (match_operand:QI 0 "register_operand" "")
2930 (ashift:QI (match_operand:QI 1 "register_operand" "")
2931 (match_operand:QI 2 "nonmemory_operand" "")))]
2934 if (expand_a_shift (QImode, ASHIFT, operands))
2938 (define_expand "ashrqi3"
2939 [(set (match_operand:QI 0 "register_operand" "")
2940 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2941 (match_operand:QI 2 "nonmemory_operand" "")))]
2944 if (expand_a_shift (QImode, ASHIFTRT, operands))
2948 (define_expand "lshrqi3"
2949 [(set (match_operand:QI 0 "register_operand" "")
2950 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2951 (match_operand:QI 2 "nonmemory_operand" "")))]
2954 if (expand_a_shift (QImode, LSHIFTRT, operands))
2959 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2960 (match_operator:QI 3 "h8sx_unary_shift_operator"
2961 [(match_operand:QI 1 "h8300_dst_operand" "0")
2962 (match_operand:QI 2 "const_int_operand" "")]))]
2963 "h8300_operands_match_p (operands)"
2965 return output_h8sx_shift (operands, 'b', 'X');
2967 [(set_attr "length_table" "unary")
2968 (set_attr "cc" "set_znv")])
2971 [(set (match_operand:QI 0 "register_operand" "=r")
2972 (match_operator:QI 3 "h8sx_binary_shift_operator"
2973 [(match_operand:QI 1 "register_operand" "0")
2974 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2977 return output_h8sx_shift (operands, 'b', 'X');
2979 [(set_attr "length" "4")
2980 (set_attr "cc" "set_znv")])
2982 (define_insn "*shiftqi"
2983 [(set (match_operand:QI 0 "register_operand" "=r,r")
2984 (match_operator:QI 3 "nshift_operator"
2985 [(match_operand:QI 1 "register_operand" "0,0")
2986 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2987 (clobber (match_scratch:QI 4 "=X,&r"))]
2990 return output_a_shift (operands);
2992 [(set (attr "length")
2993 (symbol_ref "compute_a_shift_length (insn, operands)"))
2995 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2999 (define_expand "ashlhi3"
3000 [(set (match_operand:HI 0 "register_operand" "")
3001 (ashift:HI (match_operand:HI 1 "register_operand" "")
3002 (match_operand:QI 2 "nonmemory_operand" "")))]
3005 if (expand_a_shift (HImode, ASHIFT, operands))
3009 (define_expand "lshrhi3"
3010 [(set (match_operand:HI 0 "register_operand" "")
3011 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
3012 (match_operand:QI 2 "nonmemory_operand" "")))]
3015 if (expand_a_shift (HImode, LSHIFTRT, operands))
3019 (define_expand "ashrhi3"
3020 [(set (match_operand:HI 0 "register_operand" "")
3021 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
3022 (match_operand:QI 2 "nonmemory_operand" "")))]
3025 if (expand_a_shift (HImode, ASHIFTRT, operands))
3030 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
3031 (match_operator:HI 3 "h8sx_unary_shift_operator"
3032 [(match_operand:HI 1 "h8300_dst_operand" "0")
3033 (match_operand:QI 2 "const_int_operand" "")]))]
3034 "h8300_operands_match_p (operands)"
3036 return output_h8sx_shift (operands, 'w', 'T');
3038 [(set_attr "length_table" "unary")
3039 (set_attr "cc" "set_znv")])
3042 [(set (match_operand:HI 0 "register_operand" "=r")
3043 (match_operator:HI 3 "h8sx_binary_shift_operator"
3044 [(match_operand:HI 1 "register_operand" "0")
3045 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
3048 return output_h8sx_shift (operands, 'w', 'T');
3050 [(set_attr "length" "4")
3051 (set_attr "cc" "set_znv")])
3053 (define_insn "*shifthi"
3054 [(set (match_operand:HI 0 "register_operand" "=r,r")
3055 (match_operator:HI 3 "nshift_operator"
3056 [(match_operand:HI 1 "register_operand" "0,0")
3057 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
3058 (clobber (match_scratch:QI 4 "=X,&r"))]
3061 return output_a_shift (operands);
3063 [(set (attr "length")
3064 (symbol_ref "compute_a_shift_length (insn, operands)"))
3066 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3070 (define_expand "ashlsi3"
3071 [(set (match_operand:SI 0 "register_operand" "")
3072 (ashift:SI (match_operand:SI 1 "register_operand" "")
3073 (match_operand:QI 2 "nonmemory_operand" "")))]
3076 if (expand_a_shift (SImode, ASHIFT, operands))
3080 (define_expand "lshrsi3"
3081 [(set (match_operand:SI 0 "register_operand" "")
3082 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
3083 (match_operand:QI 2 "nonmemory_operand" "")))]
3086 if (expand_a_shift (SImode, LSHIFTRT, operands))
3090 (define_expand "ashrsi3"
3091 [(set (match_operand:SI 0 "register_operand" "")
3092 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
3093 (match_operand:QI 2 "nonmemory_operand" "")))]
3096 if (expand_a_shift (SImode, ASHIFTRT, operands))
3101 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
3102 (match_operator:SI 3 "h8sx_unary_shift_operator"
3103 [(match_operand:SI 1 "h8300_dst_operand" "0")
3104 (match_operand:QI 2 "const_int_operand" "")]))]
3105 "h8300_operands_match_p (operands)"
3107 return output_h8sx_shift (operands, 'l', 'S');
3109 [(set_attr "length_table" "unary")
3110 (set_attr "cc" "set_znv")])
3113 [(set (match_operand:SI 0 "register_operand" "=r")
3114 (match_operator:SI 3 "h8sx_binary_shift_operator"
3115 [(match_operand:SI 1 "register_operand" "0")
3116 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
3119 return output_h8sx_shift (operands, 'l', 'S');
3121 [(set_attr "length" "4")
3122 (set_attr "cc" "set_znv")])
3124 (define_insn "*shiftsi"
3125 [(set (match_operand:SI 0 "register_operand" "=r,r")
3126 (match_operator:SI 3 "nshift_operator"
3127 [(match_operand:SI 1 "register_operand" "0,0")
3128 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
3129 (clobber (match_scratch:QI 4 "=X,&r"))]
3132 return output_a_shift (operands);
3134 [(set (attr "length")
3135 (symbol_ref "compute_a_shift_length (insn, operands)"))
3137 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
3139 ;; Split a variable shift into a loop. If the register containing
3140 ;; the shift count dies, then we just use that register.
3143 [(set (match_operand 0 "register_operand" "")
3144 (match_operator 2 "nshift_operator"
3146 (match_operand:QI 1 "register_operand" "")]))
3147 (clobber (match_operand:QI 3 "register_operand" ""))]
3149 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3150 [(set (cc0) (compare (match_dup 1) (const_int 0)))
3152 (if_then_else (le (cc0) (const_int 0))
3153 (label_ref (match_dup 5))
3158 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3159 (clobber (scratch:QI))])
3160 (set (match_dup 1) (plus:QI (match_dup 1) (const_int -1)))
3161 (set (cc0) (compare (match_dup 1) (const_int 0)))
3163 (if_then_else (ne (cc0) (const_int 0))
3164 (label_ref (match_dup 4))
3168 operands[4] = gen_label_rtx ();
3169 operands[5] = gen_label_rtx ();
3173 [(set (match_operand 0 "register_operand" "")
3174 (match_operator 2 "nshift_operator"
3176 (match_operand:QI 1 "register_operand" "")]))
3177 (clobber (match_operand:QI 3 "register_operand" ""))]
3179 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
3182 (set (cc0) (compare (match_dup 3) (const_int 0)))
3184 (if_then_else (le (cc0) (const_int 0))
3185 (label_ref (match_dup 5))
3190 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
3191 (clobber (scratch:QI))])
3192 (set (match_dup 3) (plus:QI (match_dup 3) (const_int -1)))
3193 (set (cc0) (compare (match_dup 3) (const_int 0)))
3195 (if_then_else (ne (cc0) (const_int 0))
3196 (label_ref (match_dup 4))
3200 operands[4] = gen_label_rtx ();
3201 operands[5] = gen_label_rtx ();
3204 ;; ----------------------------------------------------------------------
3206 ;; ----------------------------------------------------------------------
3208 (define_expand "rotlqi3"
3209 [(set (match_operand:QI 0 "register_operand" "")
3210 (rotate:QI (match_operand:QI 1 "register_operand" "")
3211 (match_operand:QI 2 "nonmemory_operand" "")))]
3214 if (expand_a_rotate (operands))
3218 (define_insn "rotlqi3_1"
3219 [(set (match_operand:QI 0 "register_operand" "=r")
3220 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3221 (match_operand:QI 2 "immediate_operand" "")))]
3224 return output_a_rotate (ROTATE, operands);
3226 [(set (attr "length")
3227 (symbol_ref "compute_a_rotate_length (operands)"))])
3229 (define_expand "rotlhi3"
3230 [(set (match_operand:HI 0 "register_operand" "")
3231 (rotate:HI (match_operand:HI 1 "register_operand" "")
3232 (match_operand:QI 2 "nonmemory_operand" "")))]
3235 if (expand_a_rotate (operands))
3239 (define_insn "rotlhi3_1"
3240 [(set (match_operand:HI 0 "register_operand" "=r")
3241 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3242 (match_operand:QI 2 "immediate_operand" "")))]
3245 return output_a_rotate (ROTATE, operands);
3247 [(set (attr "length")
3248 (symbol_ref "compute_a_rotate_length (operands)"))])
3250 (define_expand "rotlsi3"
3251 [(set (match_operand:SI 0 "register_operand" "")
3252 (rotate:SI (match_operand:SI 1 "register_operand" "")
3253 (match_operand:QI 2 "nonmemory_operand" "")))]
3254 "TARGET_H8300H || TARGET_H8300S"
3256 if (expand_a_rotate (operands))
3260 (define_insn "rotlsi3_1"
3261 [(set (match_operand:SI 0 "register_operand" "=r")
3262 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3263 (match_operand:QI 2 "immediate_operand" "")))]
3264 "TARGET_H8300H || TARGET_H8300S"
3266 return output_a_rotate (ROTATE, operands);
3268 [(set (attr "length")
3269 (symbol_ref "compute_a_rotate_length (operands)"))])
3271 ;; -----------------------------------------------------------------
3273 ;; -----------------------------------------------------------------
3274 ;; The H8/300 has given 1/8th of its opcode space to bitfield
3275 ;; instructions so let's use them as well as we can.
3277 ;; You'll never believe all these patterns perform one basic action --
3278 ;; load a bit from the source, optionally invert the bit, then store it
3279 ;; in the destination (which is known to be zero).
3281 ;; Combine obviously need some work to better identify this situation and
3282 ;; canonicalize the form better.
3285 ;; Normal loads with a 16bit destination.
3289 [(set (match_operand:HI 0 "register_operand" "=&r")
3290 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3292 (match_operand:HI 2 "immediate_operand" "n")))]
3294 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
3295 [(set_attr "length" "6")])
3298 ;; Inverted loads with a 16bit destination.
3302 [(set (match_operand:HI 0 "register_operand" "=&r")
3303 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
3304 (match_operand:HI 3 "const_int_operand" "n"))
3306 (match_operand:HI 2 "const_int_operand" "n")))]
3307 "(TARGET_H8300 || TARGET_H8300SX)
3308 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3309 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
3310 [(set_attr "length" "8")])
3313 ;; Normal loads with a 32bit destination.
3316 (define_insn "*extzv_1_r_h8300"
3317 [(set (match_operand:SI 0 "register_operand" "=&r")
3318 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
3320 (match_operand 2 "const_int_operand" "n")))]
3321 "TARGET_H8300 && INTVAL (operands[2]) < 16"
3323 return output_simode_bld (0, operands);
3325 [(set_attr "length" "8")])
3327 (define_insn "*extzv_1_r_h8300hs"
3328 [(set (match_operand:SI 0 "register_operand" "=r,r")
3329 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3331 (match_operand 2 "const_int_operand" "n,n")))]
3332 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
3334 return output_simode_bld (0, operands);
3336 [(set_attr "cc" "set_znv,set_znv")
3337 (set_attr "length" "8,6")])
3340 ;; Inverted loads with a 32bit destination.
3343 (define_insn "*extzv_1_r_inv_h8300"
3344 [(set (match_operand:SI 0 "register_operand" "=&r")
3345 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
3346 (match_operand:HI 3 "const_int_operand" "n"))
3348 (match_operand 2 "const_int_operand" "n")))]
3349 "TARGET_H8300 && INTVAL (operands[2]) < 16
3350 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3352 return output_simode_bld (1, operands);
3354 [(set_attr "length" "8")])
3356 (define_insn "*extzv_1_r_inv_h8300hs"
3357 [(set (match_operand:SI 0 "register_operand" "=r,r")
3358 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
3359 (match_operand 3 "const_int_operand" "n,n"))
3361 (match_operand 2 "const_int_operand" "n,n")))]
3362 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16
3363 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3365 return output_simode_bld (1, operands);
3367 [(set_attr "cc" "set_znv,set_znv")
3368 (set_attr "length" "8,6")])
3370 (define_expand "insv"
3371 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3372 (match_operand:HI 1 "general_operand" "")
3373 (match_operand:HI 2 "general_operand" ""))
3374 (match_operand:HI 3 "register_operand" ""))]
3375 "TARGET_H8300 || TARGET_H8300SX"
3379 if (GET_CODE (operands[1]) == CONST_INT
3380 && GET_CODE (operands[2]) == CONST_INT
3381 && INTVAL (operands[1]) <= 8
3382 && INTVAL (operands[2]) >= 0
3383 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3384 && memory_operand (operands[0], GET_MODE (operands[0])))
3386 /* If the source operand is zero, it's better to use AND rather
3387 than BFST. Likewise OR if the operand is all ones. */
3388 if (GET_CODE (operands[3]) == CONST_INT)
3390 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3391 if ((INTVAL (operands[3]) & mask) == 0)
3393 if ((INTVAL (operands[3]) & mask) == mask)
3396 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3398 if (!can_create_pseudo_p ())
3400 operands[0] = replace_equiv_address (operands[0], force_reg (Pmode,
3401 XEXP (operands[0], 0)));
3403 operands[3] = gen_lowpart (QImode, operands[3]);
3406 if (! register_operand (operands[3], QImode))
3408 if (!can_create_pseudo_p ())
3410 operands[3] = force_reg (QImode, operands[3]);
3412 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3413 operands[3], operands[1], operands[2]));
3419 /* We only have single bit bit-field instructions. */
3420 if (INTVAL (operands[1]) != 1)
3423 /* For now, we don't allow memory operands. */
3424 if (GET_CODE (operands[0]) == MEM
3425 || GET_CODE (operands[3]) == MEM)
3428 if (GET_CODE (operands[3]) != REG)
3429 operands[3] = force_reg (HImode, operands[3]);
3433 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3435 (match_operand:HI 1 "immediate_operand" "n"))
3436 (match_operand:HI 2 "register_operand" "r"))]
3438 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3439 [(set_attr "length" "4")])
3441 (define_expand "extzv"
3442 [(set (match_operand:HI 0 "register_operand" "")
3443 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3444 (match_operand:HI 2 "general_operand" "")
3445 (match_operand:HI 3 "general_operand" "")))]
3446 "TARGET_H8300 || TARGET_H8300SX"
3450 if (GET_CODE (operands[2]) == CONST_INT
3451 && GET_CODE (operands[3]) == CONST_INT
3452 && INTVAL (operands[2]) <= 8
3453 && INTVAL (operands[3]) >= 0
3454 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3455 && memory_operand (operands[1], QImode))
3459 /* Optimize the case where we're extracting into a paradoxical
3460 subreg. It's only necessary to extend to the inner reg. */
3461 if (GET_CODE (operands[0]) == SUBREG
3462 && subreg_lowpart_p (operands[0])
3463 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3464 < GET_MODE_SIZE (GET_MODE (operands[0])))
3465 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3467 operands[0] = SUBREG_REG (operands[0]);
3469 if (!can_create_pseudo_p ())
3470 temp = gen_lowpart (QImode, operands[0]);
3472 temp = gen_reg_rtx (QImode);
3475 if (! bit_memory_operand (operands[1], QImode))
3477 if (!can_create_pseudo_p ())
3479 operands[1] = replace_equiv_address (operands[1],
3480 force_reg (Pmode, XEXP (operands[1], 0)));
3482 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3483 convert_move (operands[0], temp, 1);
3489 /* We only have single bit bit-field instructions. */
3490 if (INTVAL (operands[2]) != 1)
3493 /* For now, we don't allow memory operands. */
3494 if (GET_CODE (operands[1]) == MEM)
3498 ;; BAND, BOR, and BXOR patterns
3501 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3502 (match_operator:HI 4 "bit_operator"
3503 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3505 (match_operand:HI 2 "immediate_operand" "n"))
3506 (match_operand:HI 3 "bit_operand" "0")]))]
3508 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3509 [(set_attr "length" "6")])
3512 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3513 (match_operator:HI 5 "bit_operator"
3514 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3516 (match_operand:HI 2 "immediate_operand" "n"))
3517 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3519 (match_operand:HI 4 "immediate_operand" "n"))]))]
3521 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3522 [(set_attr "length" "6")])
3525 [(set (match_operand:QI 0 "register_operand" "=r")
3526 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3527 (match_operand:QI 2 "immediate_operand" "n")
3528 (match_operand:QI 3 "immediate_operand" "n")))]
3529 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3531 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3532 - (1 << INTVAL (operands[3])));
3533 return "bfld %2,%1,%R0";
3535 [(set_attr "cc" "none_0hit")
3536 (set_attr "length_table" "bitfield")])
3539 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3540 (match_operand:QI 2 "immediate_operand" "n")
3541 (match_operand:QI 3 "immediate_operand" "n"))
3542 (match_operand:QI 1 "register_operand" "r"))]
3543 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3545 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3546 - (1 << INTVAL (operands[3])));
3547 return "bfst %R1,%2,%0";
3549 [(set_attr "cc" "none_0hit")
3550 (set_attr "length_table" "bitfield")])
3552 (define_expand "cstoreqi4"
3553 [(use (match_operator 1 "eqne_operator"
3554 [(match_operand:QI 2 "h8300_dst_operand" "")
3555 (match_operand:QI 3 "h8300_src_operand" "")]))
3556 (clobber (match_operand:HI 0 "register_operand"))]
3559 h8300_expand_store (operands);
3563 (define_expand "cstorehi4"
3564 [(use (match_operator 1 "eqne_operator"
3565 [(match_operand:HI 2 "h8300_dst_operand" "")
3566 (match_operand:HI 3 "h8300_src_operand" "")]))
3567 (clobber (match_operand:HI 0 "register_operand"))]
3570 h8300_expand_store (operands);
3574 (define_expand "cstoresi4"
3575 [(use (match_operator 1 "eqne_operator"
3576 [(match_operand:SI 2 "h8300_dst_operand" "")
3577 (match_operand:SI 3 "h8300_src_operand" "")]))
3578 (clobber (match_operand:HI 0 "register_operand"))]
3581 h8300_expand_store (operands);
3585 (define_insn "*bstzhireg"
3586 [(set (match_operand:HI 0 "register_operand" "=r")
3587 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3589 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3590 [(set_attr "cc" "clobber")])
3592 (define_insn_and_split "*cmpstz"
3593 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
3595 (match_operand:QI 1 "immediate_operand" "n,n"))
3596 (match_operator:QI 2 "eqne_operator"
3597 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3598 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3600 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3601 || GET_CODE (operands[4]) == CONST_INT)
3602 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3603 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3606 [(set (cc0) (match_dup 5))
3607 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3608 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3610 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);
3612 [(set_attr "cc" "set_znv,compare")])
3614 (define_insn "*bstz"
3615 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3617 (match_operand:QI 1 "immediate_operand" "n"))
3618 (eq:QI (cc0) (const_int 0)))]
3619 "TARGET_H8300SX && reload_completed"
3621 [(set_attr "cc" "none_0hit")
3622 (set_attr "length_table" "unary")])
3624 (define_insn "*bistz"
3625 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3627 (match_operand:QI 1 "immediate_operand" "n"))
3628 (ne:QI (cc0) (const_int 0)))]
3629 "TARGET_H8300SX && reload_completed"
3631 [(set_attr "cc" "none_0hit")
3632 (set_attr "length_table" "unary")])
3634 (define_insn_and_split "*cmpcondbset"
3635 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3636 (if_then_else:QI (match_operator 1 "eqne_operator"
3637 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3638 (match_operand 3 "h8300_src_operand" "I,rQi")])
3639 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3640 (match_operand:QI 5 "single_one_operand" "n,n"))
3645 [(set (cc0) (match_dup 6))
3647 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3648 (ior:QI (match_dup 4) (match_dup 5))
3651 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3653 [(set_attr "cc" "set_znv,compare")])
3655 (define_insn "*condbset"
3656 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3657 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3658 [(cc0) (const_int 0)])
3659 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3660 (match_operand:QI 1 "single_one_operand" "n"))
3662 "TARGET_H8300SX && reload_completed"
3664 [(set_attr "cc" "none_0hit")
3665 (set_attr "length_table" "logicb")])
3667 (define_insn_and_split "*cmpcondbclr"
3668 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3669 (if_then_else:QI (match_operator 1 "eqne_operator"
3670 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3671 (match_operand 3 "h8300_src_operand" "I,rQi")])
3672 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3673 (match_operand:QI 5 "single_zero_operand" "n,n"))
3678 [(set (cc0) (match_dup 6))
3680 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3681 (and:QI (match_dup 4) (match_dup 5))
3684 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3686 [(set_attr "cc" "set_znv,compare")])
3688 (define_insn "*condbclr"
3689 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3690 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3691 [(cc0) (const_int 0)])
3692 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3693 (match_operand:QI 1 "single_zero_operand" "n"))
3695 "TARGET_H8300SX && reload_completed"
3697 [(set_attr "cc" "none_0hit")
3698 (set_attr "length_table" "logicb")])
3700 (define_insn_and_split "*cmpcondbsetreg"
3701 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3702 (if_then_else:QI (match_operator 1 "eqne_operator"
3703 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3704 (match_operand 3 "h8300_src_operand" "I,rQi")])
3705 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3706 (ashift:QI (const_int 1)
3707 (match_operand:QI 5 "register_operand" "r,r")))
3712 [(set (cc0) (match_dup 6))
3714 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3715 (ior:QI (match_dup 4)
3716 (ashift:QI (const_int 1)
3717 (match_operand:QI 5 "register_operand" "r,r")))
3720 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3722 [(set_attr "cc" "set_znv,compare")])
3724 (define_insn "*condbsetreg"
3725 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3726 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3727 [(cc0) (const_int 0)])
3728 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3729 (ashift:QI (const_int 1)
3730 (match_operand:QI 1 "register_operand" "r")))
3732 "TARGET_H8300SX && reload_completed"
3734 [(set_attr "cc" "none_0hit")
3735 (set_attr "length_table" "logicb")])
3737 (define_insn_and_split "*cmpcondbclrreg"
3738 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3739 (if_then_else:QI (match_operator 1 "eqne_operator"
3740 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3741 (match_operand 3 "h8300_src_operand" "I,rQi")])
3742 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3743 (ashift:QI (const_int 1)
3744 (match_operand:QI 5 "register_operand" "r,r")))
3749 [(set (cc0) (match_dup 6))
3751 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3752 (and:QI (match_dup 4)
3753 (ashift:QI (const_int 1)
3754 (match_operand:QI 5 "register_operand" "r,r")))
3757 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3759 [(set_attr "cc" "set_znv,compare")])
3761 (define_insn "*condbclrreg"
3762 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3763 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3764 [(cc0) (const_int 0)])
3765 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3766 (ashift:QI (const_int 1)
3767 (match_operand:QI 1 "register_operand" "r")))
3769 "TARGET_H8300SX && reload_completed"
3771 [(set_attr "cc" "none_0hit")
3772 (set_attr "length_table" "logicb")])
3775 ;; -----------------------------------------------------------------
3777 ;; -----------------------------------------------------------------
3781 (define_insn "*insv_si_1_n"
3782 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3784 (match_operand:SI 1 "const_int_operand" "n"))
3785 (match_operand:SI 2 "register_operand" "r"))]
3786 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3787 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3788 [(set_attr "length" "4")])
3790 (define_insn "*insv_si_1_n_lshiftrt"
3791 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3793 (match_operand:SI 1 "const_int_operand" "n"))
3794 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3795 (match_operand:SI 3 "const_int_operand" "n")))]
3796 "(TARGET_H8300H || TARGET_H8300S)
3797 && INTVAL (operands[1]) < 16
3798 && INTVAL (operands[3]) < 16"
3799 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3800 [(set_attr "length" "4")])
3802 (define_insn "*insv_si_1_n_lshiftrt_16"
3803 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3805 (match_operand:SI 1 "const_int_operand" "n"))
3806 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3808 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3809 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3810 [(set_attr "length" "6")])
3812 (define_insn "*insv_si_8_8"
3813 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3816 (match_operand:SI 1 "register_operand" "r"))]
3817 "TARGET_H8300H || TARGET_H8300S"
3819 [(set_attr "length" "2")])
3821 (define_insn "*insv_si_8_8_lshiftrt_8"
3822 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3825 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3827 "TARGET_H8300H || TARGET_H8300S"
3829 [(set_attr "length" "2")])
3833 (define_insn "*extzv_8_8"
3834 [(set (match_operand:SI 0 "register_operand" "=r,r")
3835 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3838 "TARGET_H8300H || TARGET_H8300S"
3840 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3841 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3842 [(set_attr "cc" "set_znv,clobber")
3843 (set_attr "length" "6,4")])
3845 (define_insn "*extzv_8_16"
3846 [(set (match_operand:SI 0 "register_operand" "=r")
3847 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3850 "TARGET_H8300H || TARGET_H8300S"
3851 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3852 [(set_attr "cc" "set_znv")
3853 (set_attr "length" "6")])
3855 (define_insn "*extzv_16_8"
3856 [(set (match_operand:SI 0 "register_operand" "=r")
3857 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3860 (clobber (match_scratch:SI 2 "=&r"))]
3862 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3863 [(set_attr "length" "8")
3864 (set_attr "cc" "set_znv")])
3866 ;; Extract the exponent of a float.
3868 (define_insn_and_split "*extzv_8_23"
3869 [(set (match_operand:SI 0 "register_operand" "=r")
3870 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3873 "(TARGET_H8300H || TARGET_H8300S)"
3875 "&& reload_completed"
3876 [(parallel [(set (match_dup 0)
3877 (ashift:SI (match_dup 0)
3879 (clobber (scratch:QI))])
3880 (parallel [(set (match_dup 0)
3881 (lshiftrt:SI (match_dup 0)
3883 (clobber (scratch:QI))])]
3888 ;; ((SImode) HImode) << 15
3890 (define_insn_and_split "*twoshifts_l16_r1"
3891 [(set (match_operand:SI 0 "register_operand" "=r")
3892 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3894 (const_int 2147450880)))]
3895 "(TARGET_H8300H || TARGET_H8300S)"
3897 "&& reload_completed"
3898 [(parallel [(set (match_dup 0)
3899 (ashift:SI (match_dup 0)
3901 (clobber (scratch:QI))])
3902 (parallel [(set (match_dup 0)
3903 (lshiftrt:SI (match_dup 0)
3905 (clobber (scratch:QI))])]
3908 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3910 (define_insn_and_split "*andsi3_ashift_n_lower"
3911 [(set (match_operand:SI 0 "register_operand" "=r,r")
3912 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3913 (match_operand:QI 2 "const_int_operand" "S,n"))
3914 (match_operand:SI 3 "const_int_operand" "n,n")))
3915 (clobber (match_scratch:QI 4 "=X,&r"))]
3916 "(TARGET_H8300H || TARGET_H8300S)
3917 && INTVAL (operands[2]) <= 15
3918 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3920 "&& reload_completed"
3921 [(parallel [(set (match_dup 5)
3922 (ashift:HI (match_dup 5)
3924 (clobber (match_dup 4))])
3926 (zero_extend:SI (match_dup 5)))]
3928 operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));
3931 ;; Accept (A >> 30) & 2 and the like.
3933 (define_insn "*andsi3_lshiftrt_n_sb"
3934 [(set (match_operand:SI 0 "register_operand" "=r")
3935 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3936 (match_operand:SI 2 "const_int_operand" "n"))
3937 (match_operand:SI 3 "single_one_operand" "n")))]
3938 "(TARGET_H8300H || TARGET_H8300S)
3939 && exact_log2 (INTVAL (operands[3])) < 16
3940 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3942 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3943 return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0";
3945 [(set_attr "length" "8")])
3947 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3948 [(set (match_operand:SI 0 "register_operand" "=r")
3949 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3951 (const_int 4194304)))]
3952 "TARGET_H8300H || TARGET_H8300S"
3954 "&& reload_completed"
3956 (and:SI (lshiftrt:SI (match_dup 0)
3959 (parallel [(set (match_dup 0)
3960 (ashift:SI (match_dup 0)
3962 (clobber (scratch:QI))])]
3967 (define_insn "*addsi3_upper"
3968 [(set (match_operand:SI 0 "register_operand" "=r")
3969 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3971 (match_operand:SI 2 "register_operand" "0")))]
3972 "TARGET_H8300H || TARGET_H8300S"
3974 [(set_attr "length" "2")])
3976 (define_insn "*addsi3_lshiftrt_16_zexthi"
3977 [(set (match_operand:SI 0 "register_operand" "=r")
3978 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3980 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3981 "TARGET_H8300H || TARGET_H8300S"
3982 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3983 [(set_attr "length" "6")])
3985 (define_insn_and_split "*addsi3_and_r_1"
3986 [(set (match_operand:SI 0 "register_operand" "=r")
3987 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3989 (match_operand:SI 2 "register_operand" "0")))]
3990 "TARGET_H8300H || TARGET_H8300S"
3992 "&& reload_completed"
3993 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3998 (if_then_else (eq (cc0)
4000 (label_ref (match_dup 3))
4003 (plus:SI (match_dup 2)
4007 operands[3] = gen_label_rtx ();
4010 (define_insn_and_split "*addsi3_and_not_r_1"
4011 [(set (match_operand:SI 0 "register_operand" "=r")
4012 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4014 (match_operand:SI 2 "register_operand" "0")))]
4015 "TARGET_H8300H || TARGET_H8300S"
4017 "&& reload_completed"
4018 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
4023 (if_then_else (ne (cc0)
4025 (label_ref (match_dup 3))
4028 (plus:SI (match_dup 2)
4032 operands[3] = gen_label_rtx ();
4037 (define_insn "*ixorhi3_zext"
4038 [(set (match_operand:HI 0 "register_operand" "=r")
4039 (match_operator:HI 1 "iorxor_operator"
4040 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
4041 (match_operand:HI 3 "register_operand" "0")]))]
4044 [(set_attr "length" "2")])
4048 (define_insn "*ixorsi3_zext_qi"
4049 [(set (match_operand:SI 0 "register_operand" "=r")
4050 (match_operator:SI 1 "iorxor_operator"
4051 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
4052 (match_operand:SI 3 "register_operand" "0")]))]
4055 [(set_attr "length" "2")])
4057 (define_insn "*ixorsi3_zext_hi"
4058 [(set (match_operand:SI 0 "register_operand" "=r")
4059 (match_operator:SI 1 "iorxor_operator"
4060 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
4061 (match_operand:SI 3 "register_operand" "0")]))]
4062 "TARGET_H8300H || TARGET_H8300S"
4064 [(set_attr "length" "2")])
4066 (define_insn "*ixorsi3_ashift_16"
4067 [(set (match_operand:SI 0 "register_operand" "=r")
4068 (match_operator:SI 1 "iorxor_operator"
4069 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
4071 (match_operand:SI 3 "register_operand" "0")]))]
4072 "TARGET_H8300H || TARGET_H8300S"
4074 [(set_attr "length" "2")])
4076 (define_insn "*ixorsi3_lshiftrt_16"
4077 [(set (match_operand:SI 0 "register_operand" "=r")
4078 (match_operator:SI 1 "iorxor_operator"
4079 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4081 (match_operand:SI 3 "register_operand" "0")]))]
4082 "TARGET_H8300H || TARGET_H8300S"
4084 [(set_attr "length" "2")])
4088 (define_insn "*iorhi3_ashift_8"
4089 [(set (match_operand:HI 0 "register_operand" "=r")
4090 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
4092 (match_operand:HI 2 "register_operand" "0")))]
4095 [(set_attr "length" "2")])
4097 (define_insn "*iorhi3_lshiftrt_8"
4098 [(set (match_operand:HI 0 "register_operand" "=r")
4099 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4101 (match_operand:HI 2 "register_operand" "0")))]
4104 [(set_attr "length" "2")])
4106 (define_insn "*iorhi3_two_qi"
4107 [(set (match_operand:HI 0 "register_operand" "=r")
4108 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
4109 (ashift:HI (match_operand:HI 2 "register_operand" "r")
4113 [(set_attr "length" "2")])
4115 (define_insn "*iorhi3_two_qi_mem"
4116 [(set (match_operand:HI 0 "register_operand" "=&r")
4117 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
4118 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
4121 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
4122 [(set_attr "length" "16")])
4125 [(set (match_operand:HI 0 "register_operand" "")
4126 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
4127 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
4129 "(TARGET_H8300H || TARGET_H8300S)
4131 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
4135 operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));
4140 (define_insn "*iorsi3_two_hi"
4141 [(set (match_operand:SI 0 "register_operand" "=r")
4142 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
4143 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4145 "TARGET_H8300H || TARGET_H8300S"
4147 [(set_attr "length" "2")])
4149 (define_insn_and_split "*iorsi3_two_qi_zext"
4150 [(set (match_operand:SI 0 "register_operand" "=&r")
4151 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
4152 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4154 (const_int 65280))))]
4155 "TARGET_H8300H || TARGET_H8300S"
4157 "&& reload_completed"
4159 (ior:HI (zero_extend:HI (match_dup 1))
4160 (ashift:HI (subreg:HI (match_dup 2) 0)
4163 (zero_extend:SI (match_dup 3)))]
4165 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4168 (define_insn "*iorsi3_e2f"
4169 [(set (match_operand:SI 0 "register_operand" "=r")
4170 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4172 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4174 "TARGET_H8300H || TARGET_H8300S"
4176 [(set_attr "length" "2")])
4178 (define_insn_and_split "*iorsi3_two_qi_sext"
4179 [(set (match_operand:SI 0 "register_operand" "=r")
4180 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
4181 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
4183 "TARGET_H8300H || TARGET_H8300S"
4185 "&& reload_completed"
4187 (ior:HI (zero_extend:HI (match_dup 1))
4188 (ashift:HI (match_dup 4)
4191 (sign_extend:SI (match_dup 3)))]
4193 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4194 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
4197 (define_insn "*iorsi3_w"
4198 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4199 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
4201 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
4202 "TARGET_H8300H || TARGET_H8300S"
4204 [(set_attr "length" "2,8")])
4206 (define_insn "*iorsi3_ashift_31"
4207 [(set (match_operand:SI 0 "register_operand" "=&r")
4208 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4210 (match_operand:SI 2 "register_operand" "0")))]
4211 "TARGET_H8300H || TARGET_H8300S"
4212 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
4213 [(set_attr "length" "6")
4214 (set_attr "cc" "set_znv")])
4216 (define_insn "*iorsi3_and_ashift"
4217 [(set (match_operand:SI 0 "register_operand" "=r")
4218 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4219 (match_operand:SI 2 "const_int_operand" "n"))
4220 (match_operand:SI 3 "single_one_operand" "n"))
4221 (match_operand:SI 4 "register_operand" "0")))]
4222 "(TARGET_H8300H || TARGET_H8300S)
4223 && (INTVAL (operands[3]) & ~0xffff) == 0"
4225 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4226 - INTVAL (operands[2]));
4227 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4228 operands[2] = srcpos;
4229 operands[3] = dstpos;
4230 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
4232 [(set_attr "length" "6")])
4234 (define_insn "*iorsi3_and_lshiftrt"
4235 [(set (match_operand:SI 0 "register_operand" "=r")
4236 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4237 (match_operand:SI 2 "const_int_operand" "n"))
4238 (match_operand:SI 3 "single_one_operand" "n"))
4239 (match_operand:SI 4 "register_operand" "0")))]
4240 "(TARGET_H8300H || TARGET_H8300S)
4241 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
4243 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
4244 + INTVAL (operands[2]));
4245 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
4246 operands[2] = srcpos;
4247 operands[3] = dstpos;
4248 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
4250 [(set_attr "length" "6")])
4252 (define_insn "*iorsi3_zero_extract"
4253 [(set (match_operand:SI 0 "register_operand" "=r")
4254 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
4256 (match_operand:SI 2 "const_int_operand" "n"))
4257 (match_operand:SI 3 "register_operand" "0")))]
4258 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
4259 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
4260 [(set_attr "length" "6")])
4262 (define_insn "*iorsi3_and_lshiftrt_n_sb"
4263 [(set (match_operand:SI 0 "register_operand" "=r")
4264 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4267 (match_operand:SI 2 "register_operand" "0")))]
4268 "TARGET_H8300H || TARGET_H8300S"
4269 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
4270 [(set_attr "length" "8")])
4272 (define_insn "*iorsi3_and_lshiftrt_9_sb"
4273 [(set (match_operand:SI 0 "register_operand" "=r")
4274 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4276 (const_int 4194304))
4277 (match_operand:SI 2 "register_operand" "0")))
4278 (clobber (match_scratch:HI 3 "=&r"))]
4279 "TARGET_H8300H || TARGET_H8300S"
4281 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4282 return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
4284 return "rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
4286 [(set_attr "length" "10")])
4288 ;; Used to OR the exponent of a float.
4290 (define_insn "*iorsi3_shift"
4291 [(set (match_operand:SI 0 "register_operand" "=r")
4292 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4294 (match_operand:SI 2 "register_operand" "0")))
4295 (clobber (match_scratch:SI 3 "=&r"))]
4296 "TARGET_H8300H || TARGET_H8300S"
4300 [(set (match_operand:SI 0 "register_operand" "")
4301 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4304 (clobber (match_operand:SI 2 "register_operand" ""))]
4305 "(TARGET_H8300H || TARGET_H8300S)
4306 && epilogue_completed
4307 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4308 && REGNO (operands[0]) != REGNO (operands[1])"
4309 [(parallel [(set (match_dup 3)
4310 (ashift:HI (match_dup 3)
4312 (clobber (scratch:QI))])
4314 (ior:SI (ashift:SI (match_dup 1)
4318 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
4322 [(set (match_operand:SI 0 "register_operand" "")
4323 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4326 (clobber (match_operand:SI 2 "register_operand" ""))]
4327 "(TARGET_H8300H || TARGET_H8300S)
4328 && epilogue_completed
4329 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4330 && REGNO (operands[0]) != REGNO (operands[1]))"
4333 (parallel [(set (match_dup 3)
4334 (ashift:HI (match_dup 3)
4336 (clobber (scratch:QI))])
4338 (ior:SI (ashift:SI (match_dup 2)
4342 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
4345 (define_insn "*iorsi2_and_1_lshiftrt_1"
4346 [(set (match_operand:SI 0 "register_operand" "=r")
4347 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
4349 (lshiftrt:SI (match_dup 1)
4351 "TARGET_H8300H || TARGET_H8300S"
4352 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
4353 [(set_attr "length" "6")])
4355 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
4356 [(set (match_operand:SI 0 "register_operand" "=r")
4357 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4359 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4361 "TARGET_H8300H || TARGET_H8300S"
4363 "&& reload_completed"
4365 (ior:HI (ashift:HI (match_dup 4)
4368 (parallel [(set (match_dup 0)
4369 (ashift:SI (match_dup 0)
4371 (clobber (scratch:QI))])]
4373 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4374 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
4377 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4378 [(set (match_operand:SI 0 "register_operand" "=&r")
4379 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4381 (const_int 16711680))
4382 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4384 "TARGET_H8300H || TARGET_H8300S"
4386 "&& reload_completed"
4388 (ior:HI (zero_extend:HI (match_dup 1))
4389 (ashift:HI (subreg:HI (match_dup 2) 0)
4391 (parallel [(set (match_dup 0)
4392 (ashift:SI (match_dup 0)
4394 (clobber (scratch:QI))])]
4396 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4399 ;; Used to add the exponent of a float.
4401 (define_insn "*addsi3_shift"
4402 [(set (match_operand:SI 0 "register_operand" "=r")
4403 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4404 (const_int 8388608))
4405 (match_operand:SI 2 "register_operand" "0")))
4406 (clobber (match_scratch:SI 3 "=&r"))]
4407 "TARGET_H8300H || TARGET_H8300S"
4411 [(set (match_operand:SI 0 "register_operand" "")
4412 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4413 (const_int 8388608))
4415 (clobber (match_operand:SI 2 "register_operand" ""))]
4416 "(TARGET_H8300H || TARGET_H8300S)
4417 && epilogue_completed
4418 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4419 && REGNO (operands[0]) != REGNO (operands[1])"
4420 [(parallel [(set (match_dup 3)
4421 (ashift:HI (match_dup 3)
4423 (clobber (scratch:QI))])
4425 (plus:SI (mult:SI (match_dup 1)
4429 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
4433 [(set (match_operand:SI 0 "register_operand" "")
4434 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4435 (const_int 8388608))
4437 (clobber (match_operand:SI 2 "register_operand" ""))]
4438 "(TARGET_H8300H || TARGET_H8300S)
4439 && epilogue_completed
4440 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4441 && REGNO (operands[0]) != REGNO (operands[1]))"
4444 (parallel [(set (match_dup 3)
4445 (ashift:HI (match_dup 3)
4447 (clobber (scratch:QI))])
4449 (plus:SI (mult:SI (match_dup 2)
4453 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
4458 (define_insn_and_split "*ashiftsi_sextqi_7"
4459 [(set (match_operand:SI 0 "register_operand" "=r")
4460 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4462 "TARGET_H8300H || TARGET_H8300S"
4464 "&& reload_completed"
4465 [(parallel [(set (match_dup 2)
4466 (ashift:HI (match_dup 2)
4468 (clobber (scratch:QI))])
4470 (sign_extend:SI (match_dup 2)))
4471 (parallel [(set (match_dup 0)
4472 (ashiftrt:SI (match_dup 0)
4474 (clobber (scratch:QI))])]
4476 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
4479 ;; Storing a part of HImode to QImode.
4482 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4483 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4487 [(set_attr "cc" "set_znv")
4488 (set_attr "length" "8")])
4490 ;; Storing a part of SImode to QImode.
4493 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4494 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4498 [(set_attr "cc" "set_znv")
4499 (set_attr "length" "8")])
4502 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4503 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4505 (clobber (match_scratch:SI 2 "=&r"))]
4506 "TARGET_H8300H || TARGET_H8300S"
4507 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4508 [(set_attr "cc" "set_znv")
4509 (set_attr "length" "10")])
4512 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4513 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4515 (clobber (match_scratch:SI 2 "=&r"))]
4516 "TARGET_H8300H || TARGET_H8300S"
4517 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4518 [(set_attr "cc" "set_znv")
4519 (set_attr "length" "10")])
4521 (define_insn_and_split ""
4523 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4527 (label_ref (match_operand 1 "" ""))
4532 [(set (cc0) (compare (match_dup 0)
4535 (if_then_else (ge (cc0)
4537 (label_ref (match_dup 1))
4541 (define_insn_and_split ""
4543 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4547 (label_ref (match_operand 1 "" ""))
4552 [(set (cc0) (compare (match_dup 0)
4555 (if_then_else (lt (cc0)
4557 (label_ref (match_dup 1))
4561 ;; -----------------------------------------------------------------
4562 ;; PEEPHOLE PATTERNS
4563 ;; -----------------------------------------------------------------
4565 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4568 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4569 (lshiftrt:HI (match_dup 0)
4570 (match_operand:HI 1 "const_int_operand" "")))
4571 (clobber (match_operand:HI 2 "" ""))])
4573 (and:HI (match_dup 0)
4574 (match_operand:HI 3 "const_int_operand" "")))]
4575 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4577 (and:HI (match_dup 0)
4579 (parallel [(set (match_dup 0)
4580 (lshiftrt:HI (match_dup 0) (match_dup 1)))
4581 (clobber (match_dup 2))])]
4584 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4587 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4588 (ashift:HI (match_dup 0)
4589 (match_operand:HI 1 "const_int_operand" "")))
4590 (clobber (match_operand:HI 2 "" ""))])
4592 (and:HI (match_dup 0)
4593 (match_operand:HI 3 "const_int_operand" "")))]
4594 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4596 (and:HI (match_dup 0)
4598 (parallel [(set (match_dup 0)
4599 (ashift:HI (match_dup 0) (match_dup 1)))
4600 (clobber (match_dup 2))])]
4603 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4606 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4607 (lshiftrt:SI (match_dup 0)
4608 (match_operand:SI 1 "const_int_operand" "")))
4609 (clobber (match_operand:SI 2 "" ""))])
4611 (and:SI (match_dup 0)
4612 (match_operand:SI 3 "const_int_operand" "")))]
4613 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4615 (and:SI (match_dup 0)
4617 (parallel [(set (match_dup 0)
4618 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4619 (clobber (match_dup 2))])]
4622 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4625 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4626 (ashift:SI (match_dup 0)
4627 (match_operand:SI 1 "const_int_operand" "")))
4628 (clobber (match_operand:SI 2 "" ""))])
4630 (and:SI (match_dup 0)
4631 (match_operand:SI 3 "const_int_operand" "")))]
4632 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4634 (and:SI (match_dup 0)
4636 (parallel [(set (match_dup 0)
4637 (ashift:SI (match_dup 0) (match_dup 1)))
4638 (clobber (match_dup 2))])]
4641 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4644 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4645 (lshiftrt:SI (match_dup 0)
4646 (match_operand:SI 1 "const_int_operand" "")))
4647 (clobber (match_operand:SI 2 "" ""))])
4649 (and:SI (match_dup 0)
4650 (match_operand:SI 3 "const_int_operand" "")))]
4651 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4653 (and:SI (match_dup 0)
4655 (parallel [(set (match_dup 0)
4656 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4657 (clobber (match_dup 2))])]
4660 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4663 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4664 (ashift:SI (match_dup 0)
4665 (match_operand:SI 1 "const_int_operand" "")))
4666 (clobber (match_operand:SI 2 "" ""))])
4668 (and:SI (match_dup 0)
4669 (match_operand:SI 3 "const_int_operand" "")))]
4670 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4672 (and:SI (match_dup 0)
4674 (parallel [(set (match_dup 0)
4675 (ashift:SI (match_dup 0) (match_dup 1)))
4676 (clobber (match_dup 2))])]
4679 ;; Convert a QImode push into an SImode push so that the
4680 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4683 [(parallel [(set (reg:SI SP_REG)
4684 (plus:SI (reg:SI SP_REG) (const_int -4)))
4685 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4686 (match_operand:QI 0 "register_operand" ""))])]
4687 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4688 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4691 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4695 [(parallel [(set (reg:HI SP_REG)
4696 (plus:HI (reg:HI SP_REG) (const_int -4)))
4697 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4698 (match_operand:QI 0 "register_operand" ""))])]
4699 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4700 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4703 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4706 ;; Convert a HImode push into an SImode push so that the
4707 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4710 [(parallel [(set (reg:SI SP_REG)
4711 (plus:SI (reg:SI SP_REG) (const_int -4)))
4712 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4713 (match_operand:HI 0 "register_operand" ""))])]
4714 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4715 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4718 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4722 [(parallel [(set (reg:HI SP_REG)
4723 (plus:HI (reg:HI SP_REG) (const_int -4)))
4724 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4725 (match_operand:HI 0 "register_operand" ""))])]
4726 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4727 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4730 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4733 ;; Cram four pushes into stm.l.
4736 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4737 (match_operand:SI 0 "register_operand" ""))
4738 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4739 (match_operand:SI 1 "register_operand" ""))
4740 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4741 (match_operand:SI 2 "register_operand" ""))
4742 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4743 (match_operand:SI 3 "register_operand" ""))]
4744 "TARGET_H8300S && !TARGET_NORMAL_MODE
4745 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4746 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4747 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4748 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4749 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4750 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4752 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4754 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4756 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4758 (set (reg:SI SP_REG)
4759 (plus:SI (reg:SI SP_REG)
4760 (const_int -16)))])]
4764 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4765 (match_operand:SI 0 "register_operand" ""))
4766 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4767 (match_operand:SI 1 "register_operand" ""))
4768 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4769 (match_operand:SI 2 "register_operand" ""))
4770 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4771 (match_operand:SI 3 "register_operand" ""))]
4772 "TARGET_H8300S && TARGET_NORMAL_MODE
4773 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4774 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4775 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4776 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4777 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4778 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4780 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4782 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4784 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4786 (set (reg:HI SP_REG)
4787 (plus:HI (reg:HI SP_REG)
4788 (const_int -16)))])]
4791 ;; Cram three pushes into stm.l.
4794 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4795 (match_operand:SI 0 "register_operand" ""))
4796 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4797 (match_operand:SI 1 "register_operand" ""))
4798 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4799 (match_operand:SI 2 "register_operand" ""))]
4800 "TARGET_H8300S && !TARGET_NORMAL_MODE
4801 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4802 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4803 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4804 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4805 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4807 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4809 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4811 (set (reg:SI SP_REG)
4812 (plus:SI (reg:SI SP_REG)
4813 (const_int -12)))])]
4817 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4818 (match_operand:SI 0 "register_operand" ""))
4819 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4820 (match_operand:SI 1 "register_operand" ""))
4821 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4822 (match_operand:SI 2 "register_operand" ""))]
4823 "TARGET_H8300S && TARGET_NORMAL_MODE
4824 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4825 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4826 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4827 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4828 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4830 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4832 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4834 (set (reg:HI SP_REG)
4835 (plus:HI (reg:HI SP_REG)
4836 (const_int -12)))])]
4839 ;; Cram two pushes into stm.l.
4842 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4843 (match_operand:SI 0 "register_operand" ""))
4844 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4845 (match_operand:SI 1 "register_operand" ""))]
4846 "TARGET_H8300S && !TARGET_NORMAL_MODE
4847 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4848 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4849 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4850 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4852 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4854 (set (reg:SI SP_REG)
4855 (plus:SI (reg:SI SP_REG)
4860 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4861 (match_operand:SI 0 "register_operand" ""))
4862 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4863 (match_operand:SI 1 "register_operand" ""))]
4864 "TARGET_H8300S && TARGET_NORMAL_MODE
4865 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4866 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4867 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4868 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4870 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4872 (set (reg:HI SP_REG)
4873 (plus:HI (reg:HI SP_REG)
4880 ;; add.w r7,r0 (6 bytes)
4885 ;; adds #2,r0 (4 bytes)
4888 [(set (match_operand:HI 0 "register_operand" "")
4889 (match_operand:HI 1 "const_int_operand" ""))
4891 (plus:HI (match_dup 0)
4892 (match_operand:HI 2 "register_operand" "")))]
4893 "REG_P (operands[0]) && REG_P (operands[2])
4894 && REGNO (operands[0]) != REGNO (operands[2])
4895 && (satisfies_constraint_J (operands[1])
4896 || satisfies_constraint_L (operands[1])
4897 || satisfies_constraint_N (operands[1]))"
4901 (plus:HI (match_dup 0)
4909 ;; add.l er7,er0 (6 bytes)
4914 ;; adds #4,er0 (4 bytes)
4917 [(set (match_operand:SI 0 "register_operand" "")
4918 (match_operand:SI 1 "const_int_operand" ""))
4920 (plus:SI (match_dup 0)
4921 (match_operand:SI 2 "register_operand" "")))]
4922 "(TARGET_H8300H || TARGET_H8300S)
4923 && REG_P (operands[0]) && REG_P (operands[2])
4924 && REGNO (operands[0]) != REGNO (operands[2])
4925 && (satisfies_constraint_L (operands[1])
4926 || satisfies_constraint_N (operands[1]))"
4930 (plus:SI (match_dup 0)
4937 ;; add.l #10,er0 (takes 8 bytes)
4943 ;; add.l er7,er0 (takes 6 bytes)
4946 [(set (match_operand:SI 0 "register_operand" "")
4947 (match_operand:SI 1 "register_operand" ""))
4949 (plus:SI (match_dup 0)
4950 (match_operand:SI 2 "const_int_operand" "")))]
4951 "(TARGET_H8300H || TARGET_H8300S)
4952 && REG_P (operands[0]) && REG_P (operands[1])
4953 && REGNO (operands[0]) != REGNO (operands[1])
4954 && !satisfies_constraint_L (operands[2])
4955 && !satisfies_constraint_N (operands[2])
4956 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4957 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4958 || INTVAL (operands[2]) == 0xffff
4959 || INTVAL (operands[2]) == 0xfffe)"
4963 (plus:SI (match_dup 0)
4979 [(set (match_operand:HI 0 "register_operand" "")
4980 (plus:HI (match_dup 0)
4981 (match_operand 1 "incdec_operand" "")))
4982 (set (cc0) (compare (match_dup 0)
4985 (if_then_else (match_operator 3 "eqne_operator"
4986 [(cc0) (const_int 0)])
4987 (label_ref (match_operand 2 "" ""))
4989 "TARGET_H8300H || TARGET_H8300S"
4990 [(set (match_operand:HI 0 "register_operand" "")
4991 (unspec:HI [(match_dup 0)
4994 (set (cc0) (compare (match_dup 0)
4997 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4998 (label_ref (match_dup 2))
5002 ;; The SImode version of the previous pattern.
5005 [(set (match_operand:SI 0 "register_operand" "")
5006 (plus:SI (match_dup 0)
5007 (match_operand 1 "incdec_operand" "")))
5008 (set (cc0) (compare (match_dup 0)
5011 (if_then_else (match_operator 3 "eqne_operator"
5012 [(cc0) (const_int 0)])
5013 (label_ref (match_operand 2 "" ""))
5015 "TARGET_H8300H || TARGET_H8300S"
5016 [(set (match_operand:SI 0 "register_operand" "")
5017 (unspec:SI [(match_dup 0)
5020 (set (cc0) (compare (match_dup 0)
5023 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5024 (label_ref (match_dup 2))
5029 [(parallel [(set (cc0)
5030 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
5034 (clobber (scratch:QI))])
5036 (if_then_else (match_operator 1 "eqne_operator"
5037 [(cc0) (const_int 0)])
5038 (label_ref (match_operand 2 "" ""))
5040 "TARGET_H8300H || TARGET_H8300S"
5041 [(set (cc0) (compare (match_dup 0)
5044 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5045 (label_ref (match_dup 2))
5048 operands[3] = ((GET_CODE (operands[1]) == EQ)
5049 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
5050 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));
5053 ;; The next three peephole2's will try to transform
5055 ;; mov.b A,r0l (or mov.l A,er0)
5062 ;; and.b #CST,r0l (if CST is not 255)
5065 [(set (match_operand:QI 0 "register_operand" "")
5066 (match_operand:QI 1 "general_operand" ""))
5067 (set (match_operand:SI 2 "register_operand" "")
5068 (and:SI (match_dup 2)
5070 "(TARGET_H8300H || TARGET_H8300S)
5071 && !reg_overlap_mentioned_p (operands[2], operands[1])
5072 && REGNO (operands[0]) == REGNO (operands[2])"
5075 (set (strict_low_part (match_dup 0))
5080 [(set (match_operand:SI 0 "register_operand" "")
5081 (match_operand:SI 1 "general_operand" ""))
5083 (and:SI (match_dup 0)
5085 "(TARGET_H8300H || TARGET_H8300S)
5086 && !reg_overlap_mentioned_p (operands[0], operands[1])
5087 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
5088 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
5091 (set (strict_low_part (match_dup 2))
5094 operands[2] = gen_lowpart (QImode, operands[0]);
5095 operands[3] = gen_lowpart (QImode, operands[1]);
5099 [(set (match_operand 0 "register_operand" "")
5100 (match_operand 1 "register_operand" ""))
5101 (set (match_operand:SI 2 "register_operand" "")
5102 (and:SI (match_dup 2)
5103 (match_operand:SI 3 "const_int_qi_operand" "")))]
5104 "(TARGET_H8300H || TARGET_H8300S)
5105 && (GET_MODE (operands[0]) == QImode
5106 || GET_MODE (operands[0]) == HImode
5107 || GET_MODE (operands[0]) == SImode)
5108 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5109 && REGNO (operands[0]) == REGNO (operands[2])
5110 && !reg_overlap_mentioned_p (operands[2], operands[1])
5111 && !(GET_CODE (operands[1]) == MEM
5112 && !offsettable_memref_p (operands[1]))
5113 && !(GET_CODE (operands[1]) == MEM
5114 && MEM_VOLATILE_P (operands[1]))"
5117 (set (strict_low_part (match_dup 4))
5120 (and:SI (match_dup 2)
5123 operands[4] = gen_lowpart (QImode, operands[0]);
5124 operands[5] = gen_lowpart (QImode, operands[1]);
5125 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));
5129 [(set (match_operand:SI 0 "register_operand" "")
5130 (match_operand:SI 1 "register_operand" ""))
5132 (and:SI (match_dup 0)
5133 (const_int 65280)))]
5134 "(TARGET_H8300H || TARGET_H8300S)
5135 && !reg_overlap_mentioned_p (operands[0], operands[1])"
5138 (set (zero_extract:SI (match_dup 0)
5141 (lshiftrt:SI (match_dup 1)
5145 ;; If a load of mem:SI is followed by an AND that turns off the upper
5146 ;; half, then we can load mem:HI instead.
5149 [(set (match_operand:SI 0 "register_operand" "")
5150 (match_operand:SI 1 "memory_operand" ""))
5152 (and:SI (match_dup 0)
5153 (match_operand:SI 2 "const_int_operand" "")))]
5154 "(TARGET_H8300H || TARGET_H8300S)
5155 && !MEM_VOLATILE_P (operands[1])
5156 && offsettable_memref_p (operands[1])
5157 && (INTVAL (operands[2]) & ~0xffff) == 0
5158 && INTVAL (operands[2]) != 255"
5162 (and:SI (match_dup 0)
5165 operands[3] = gen_lowpart (HImode, operands[0]);
5166 operands[4] = gen_lowpart (HImode, operands[1]);
5169 ;; Convert a memory comparison to a move if there is a scratch register.
5172 [(match_scratch:QI 1 "r")
5174 (compare (match_operand:QI 0 "memory_operand" "")
5179 (set (cc0) (compare (match_dup 1)
5184 [(match_scratch:HI 1 "r")
5186 (compare (match_operand:HI 0 "memory_operand" "")
5188 "TARGET_H8300H || TARGET_H8300S"
5191 (set (cc0) (compare (match_dup 1)
5196 [(match_scratch:SI 1 "r")
5198 (compare (match_operand:SI 0 "memory_operand" "")
5200 "TARGET_H8300H || TARGET_H8300S"
5203 (set (cc0) (compare (match_dup 1)
5208 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
5209 ;; the equivalent with shorter sequences. Here is the summary. Cases
5210 ;; are grouped for each define_peephole2.
5212 ;; reg const_int use insn
5213 ;; --------------------------------------------------------
5214 ;; dead -2 eq/ne inc.l
5215 ;; dead -1 eq/ne inc.l
5216 ;; dead 1 eq/ne dec.l
5217 ;; dead 2 eq/ne dec.l
5219 ;; dead 1 ge/lt shar.l
5220 ;; dead 3 (H8S) ge/lt shar.l
5222 ;; dead 1 geu/ltu shar.l
5223 ;; dead 3 (H8S) geu/ltu shar.l
5225 ;; ---- 255 ge/lt mov.b
5227 ;; ---- 255 geu/ltu mov.b
5241 (compare (match_operand:HI 0 "register_operand" "")
5242 (match_operand:HI 1 "incdec_operand" "")))
5244 (if_then_else (match_operator 3 "eqne_operator"
5245 [(cc0) (const_int 0)])
5246 (label_ref (match_operand 2 "" ""))
5248 "(TARGET_H8300H || TARGET_H8300S)
5249 && INTVAL (operands[1]) != 0
5250 && peep2_reg_dead_p (1, operands[0])"
5252 (unspec:HI [(match_dup 0)
5255 (set (cc0) (compare (match_dup 0)
5258 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5259 (label_ref (match_dup 2))
5262 operands[4] = GEN_INT (- INTVAL (operands[1]));
5277 (compare (match_operand:HI 0 "register_operand" "")
5278 (match_operand:HI 1 "const_int_operand" "")))
5280 (if_then_else (match_operator 2 "gtle_operator"
5281 [(cc0) (const_int 0)])
5282 (label_ref (match_operand 3 "" ""))
5284 "(TARGET_H8300H || TARGET_H8300S)
5285 && peep2_reg_dead_p (1, operands[0])
5286 && (INTVAL (operands[1]) == 1
5287 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5288 [(parallel [(set (match_dup 0)
5289 (ashiftrt:HI (match_dup 0)
5291 (clobber (scratch:QI))])
5292 (set (cc0) (compare (match_dup 0)
5295 (if_then_else (match_dup 2)
5296 (label_ref (match_dup 3))
5299 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5314 (compare (match_operand:HI 0 "register_operand" "")
5315 (match_operand:HI 1 "const_int_operand" "")))
5317 (if_then_else (match_operator 2 "gtuleu_operator"
5318 [(cc0) (const_int 0)])
5319 (label_ref (match_operand 3 "" ""))
5321 "(TARGET_H8300H || TARGET_H8300S)
5322 && peep2_reg_dead_p (1, operands[0])
5323 && (INTVAL (operands[1]) == 1
5324 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5325 [(parallel [(set (match_dup 0)
5326 (ashiftrt:HI (match_dup 0)
5328 (clobber (scratch:QI))])
5329 (set (cc0) (compare (match_dup 0)
5332 (if_then_else (match_dup 5)
5333 (label_ref (match_dup 3))
5336 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5337 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5338 VOIDmode, cc0_rtx, const0_rtx);
5353 (compare (match_operand:HI 0 "register_operand" "")
5356 (if_then_else (match_operator 1 "gtle_operator"
5357 [(cc0) (const_int 0)])
5358 (label_ref (match_operand 2 "" ""))
5360 "TARGET_H8300H || TARGET_H8300S"
5361 [(set (cc0) (compare (and:HI (match_dup 0)
5365 (if_then_else (match_dup 1)
5366 (label_ref (match_dup 2))
5382 (compare (match_operand:HI 0 "register_operand" "")
5385 (if_then_else (match_operator 1 "gtuleu_operator"
5386 [(cc0) (const_int 0)])
5387 (label_ref (match_operand 2 "" ""))
5389 "TARGET_H8300H || TARGET_H8300S"
5390 [(set (cc0) (compare (and:HI (match_dup 0)
5394 (if_then_else (match_dup 3)
5395 (label_ref (match_dup 2))
5398 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5399 VOIDmode, cc0_rtx, const0_rtx);
5402 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5403 ;; the equivalent with shorter sequences. Here is the summary. Cases
5404 ;; are grouped for each define_peephole2.
5406 ;; reg const_int use insn
5407 ;; --------------------------------------------------------
5408 ;; live -2 eq/ne copy and inc.l
5409 ;; live -1 eq/ne copy and inc.l
5410 ;; live 1 eq/ne copy and dec.l
5411 ;; live 2 eq/ne copy and dec.l
5413 ;; dead -2 eq/ne inc.l
5414 ;; dead -1 eq/ne inc.l
5415 ;; dead 1 eq/ne dec.l
5416 ;; dead 2 eq/ne dec.l
5418 ;; dead -131072 eq/ne inc.w and test
5419 ;; dead -65536 eq/ne inc.w and test
5420 ;; dead 65536 eq/ne dec.w and test
5421 ;; dead 131072 eq/ne dec.w and test
5423 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5424 ;; dead 0x0000??00 eq/ne xor.b and test
5425 ;; dead 0x0000ffff eq/ne not.w and test
5427 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5428 ;; dead 0xffff??ff eq/ne xor.b and not.l
5429 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5430 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5432 ;; live 1 ge/lt copy and shar.l
5433 ;; live 3 (H8S) ge/lt copy and shar.l
5435 ;; live 1 geu/ltu copy and shar.l
5436 ;; live 3 (H8S) geu/ltu copy and shar.l
5438 ;; dead 1 ge/lt shar.l
5439 ;; dead 3 (H8S) ge/lt shar.l
5441 ;; dead 1 geu/ltu shar.l
5442 ;; dead 3 (H8S) geu/ltu shar.l
5444 ;; dead 3 (H8/300H) ge/lt and.b and test
5445 ;; dead 7 ge/lt and.b and test
5446 ;; dead 15 ge/lt and.b and test
5447 ;; dead 31 ge/lt and.b and test
5448 ;; dead 63 ge/lt and.b and test
5449 ;; dead 127 ge/lt and.b and test
5450 ;; dead 255 ge/lt and.b and test
5452 ;; dead 3 (H8/300H) geu/ltu and.b and test
5453 ;; dead 7 geu/ltu and.b and test
5454 ;; dead 15 geu/ltu and.b and test
5455 ;; dead 31 geu/ltu and.b and test
5456 ;; dead 63 geu/ltu and.b and test
5457 ;; dead 127 geu/ltu and.b and test
5458 ;; dead 255 geu/ltu and.b and test
5460 ;; ---- 65535 ge/lt mov.w
5462 ;; ---- 65535 geu/ltu mov.w
5476 (compare (match_operand:SI 0 "register_operand" "")
5477 (match_operand:SI 1 "incdec_operand" "")))
5479 (if_then_else (match_operator 3 "eqne_operator"
5480 [(cc0) (const_int 0)])
5481 (label_ref (match_operand 2 "" ""))
5483 "(TARGET_H8300H || TARGET_H8300S)
5484 && INTVAL (operands[1]) != 0
5485 && peep2_reg_dead_p (1, operands[0])"
5487 (unspec:SI [(match_dup 0)
5490 (set (cc0) (compare (match_dup 0)
5493 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5494 (label_ref (match_dup 2))
5497 operands[4] = GEN_INT (- INTVAL (operands[1]));
5512 (compare (match_operand:SI 0 "register_operand" "")
5513 (match_operand:SI 1 "const_int_operand" "")))
5515 (if_then_else (match_operator 3 "eqne_operator"
5516 [(cc0) (const_int 0)])
5517 (label_ref (match_operand 2 "" ""))
5519 "(TARGET_H8300H || TARGET_H8300S)
5520 && peep2_reg_dead_p (1, operands[0])
5521 && (INTVAL (operands[1]) == -131072
5522 || INTVAL (operands[1]) == -65536
5523 || INTVAL (operands[1]) == 65536
5524 || INTVAL (operands[1]) == 131072)"
5526 (plus:SI (match_dup 0)
5528 (set (cc0) (compare (match_dup 0)
5531 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5532 (label_ref (match_dup 2))
5535 operands[4] = GEN_INT (- INTVAL (operands[1]));
5551 (compare (match_operand:SI 0 "register_operand" "")
5552 (match_operand:SI 1 "const_int_operand" "")))
5554 (if_then_else (match_operator 3 "eqne_operator"
5555 [(cc0) (const_int 0)])
5556 (label_ref (match_operand 2 "" ""))
5558 "(TARGET_H8300H || TARGET_H8300S)
5559 && peep2_reg_dead_p (1, operands[0])
5560 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5561 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5562 || INTVAL (operands[1]) == 0x0000ffff)
5563 && INTVAL (operands[1]) != 0
5564 && INTVAL (operands[1]) != 1
5565 && INTVAL (operands[1]) != 2"
5567 (xor:SI (match_dup 0)
5569 (set (cc0) (compare (match_dup 0)
5572 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5573 (label_ref (match_dup 2))
5590 (compare (match_operand:SI 0 "register_operand" "")
5591 (match_operand:SI 1 "const_int_operand" "")))
5593 (if_then_else (match_operator 3 "eqne_operator"
5594 [(cc0) (const_int 0)])
5595 (label_ref (match_operand 2 "" ""))
5597 "(TARGET_H8300H || TARGET_H8300S)
5598 && peep2_reg_dead_p (1, operands[0])
5599 && ((INTVAL (operands[1]) | 0x00ff) == -1
5600 || (INTVAL (operands[1]) | 0xff00) == -1)
5601 && INTVAL (operands[1]) != -1
5602 && INTVAL (operands[1]) != -2"
5604 (xor:SI (match_dup 0)
5607 (not:SI (match_dup 0)))
5608 (set (cc0) (compare (match_dup 0)
5611 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5612 (label_ref (match_dup 2))
5615 operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);
5620 ;; cmp.l #-2147483648,er0
5631 (compare (match_operand:SI 0 "register_operand" "")
5632 (match_operand:SI 1 "const_int_operand" "")))
5634 (if_then_else (match_operator 3 "eqne_operator"
5635 [(cc0) (const_int 0)])
5636 (label_ref (match_operand 2 "" ""))
5638 "(TARGET_H8300H || TARGET_H8300S)
5639 && peep2_reg_dead_p (1, operands[0])
5640 && (INTVAL (operands[1]) == -2147483647 - 1
5641 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5643 (rotate:SI (match_dup 0)
5646 (unspec:SI [(match_dup 0)
5649 (set (cc0) (compare (match_dup 0)
5652 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5653 (label_ref (match_dup 2))
5656 operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);
5670 ;; We avoid this transformation if we see more than one copy of the
5671 ;; same compare insn immediately before this one.
5674 [(match_scratch:SI 4 "r")
5676 (compare (match_operand:SI 0 "register_operand" "")
5677 (match_operand:SI 1 "const_int_operand" "")))
5679 (if_then_else (match_operator 2 "gtle_operator"
5680 [(cc0) (const_int 0)])
5681 (label_ref (match_operand 3 "" ""))
5683 "(TARGET_H8300H || TARGET_H8300S)
5684 && !peep2_reg_dead_p (1, operands[0])
5685 && (INTVAL (operands[1]) == 1
5686 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5687 && !same_cmp_preceding_p (insn)"
5690 (parallel [(set (match_dup 4)
5691 (ashiftrt:SI (match_dup 4)
5693 (clobber (scratch:QI))])
5694 (set (cc0) (compare (match_dup 4)
5697 (if_then_else (match_dup 2)
5698 (label_ref (match_dup 3))
5701 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5715 ;; We avoid this transformation if we see more than one copy of the
5716 ;; same compare insn immediately before this one.
5719 [(match_scratch:SI 4 "r")
5721 (compare (match_operand:SI 0 "register_operand" "")
5722 (match_operand:SI 1 "const_int_operand" "")))
5724 (if_then_else (match_operator 2 "gtuleu_operator"
5725 [(cc0) (const_int 0)])
5726 (label_ref (match_operand 3 "" ""))
5728 "(TARGET_H8300H || TARGET_H8300S)
5729 && !peep2_reg_dead_p (1, operands[0])
5730 && (INTVAL (operands[1]) == 1
5731 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5732 && !same_cmp_preceding_p (insn)"
5735 (parallel [(set (match_dup 4)
5736 (ashiftrt:SI (match_dup 4)
5738 (clobber (scratch:QI))])
5739 (set (cc0) (compare (match_dup 4)
5742 (if_then_else (match_dup 6)
5743 (label_ref (match_dup 3))
5746 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5747 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5748 VOIDmode, cc0_rtx, const0_rtx);
5763 (compare (match_operand:SI 0 "register_operand" "")
5764 (match_operand:SI 1 "const_int_operand" "")))
5766 (if_then_else (match_operator 2 "gtle_operator"
5767 [(cc0) (const_int 0)])
5768 (label_ref (match_operand 3 "" ""))
5770 "(TARGET_H8300H || TARGET_H8300S)
5771 && peep2_reg_dead_p (1, operands[0])
5772 && (INTVAL (operands[1]) == 1
5773 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5774 [(parallel [(set (match_dup 0)
5775 (ashiftrt:SI (match_dup 0)
5777 (clobber (scratch:QI))])
5778 (set (cc0) (compare (match_dup 0)
5781 (if_then_else (match_dup 2)
5782 (label_ref (match_dup 3))
5785 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5800 (compare (match_operand:SI 0 "register_operand" "")
5801 (match_operand:SI 1 "const_int_operand" "")))
5803 (if_then_else (match_operator 2 "gtuleu_operator"
5804 [(cc0) (const_int 0)])
5805 (label_ref (match_operand 3 "" ""))
5807 "(TARGET_H8300H || TARGET_H8300S)
5808 && peep2_reg_dead_p (1, operands[0])
5809 && (INTVAL (operands[1]) == 1
5810 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5811 [(parallel [(set (match_dup 0)
5812 (ashiftrt:SI (match_dup 0)
5814 (clobber (scratch:QI))])
5815 (set (cc0) (compare (match_dup 0)
5818 (if_then_else (match_dup 5)
5819 (label_ref (match_dup 3))
5822 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5823 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5824 VOIDmode, cc0_rtx, const0_rtx);
5840 (compare (match_operand:SI 0 "register_operand" "")
5841 (match_operand:SI 1 "const_int_operand" "")))
5843 (if_then_else (match_operator 2 "gtle_operator"
5844 [(cc0) (const_int 0)])
5845 (label_ref (match_operand 3 "" ""))
5847 "(TARGET_H8300H || TARGET_H8300S)
5848 && peep2_reg_dead_p (1, operands[0])
5849 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5850 || INTVAL (operands[1]) == 7
5851 || INTVAL (operands[1]) == 15
5852 || INTVAL (operands[1]) == 31
5853 || INTVAL (operands[1]) == 63
5854 || INTVAL (operands[1]) == 127
5855 || INTVAL (operands[1]) == 255)"
5857 (and:SI (match_dup 0)
5859 (set (cc0) (compare (match_dup 0)
5862 (if_then_else (match_dup 2)
5863 (label_ref (match_dup 3))
5866 operands[4] = GEN_INT (~INTVAL (operands[1]));
5882 (compare (match_operand:SI 0 "register_operand" "")
5883 (match_operand:SI 1 "const_int_operand" "")))
5885 (if_then_else (match_operator 2 "gtuleu_operator"
5886 [(cc0) (const_int 0)])
5887 (label_ref (match_operand 3 "" ""))
5889 "(TARGET_H8300H || TARGET_H8300S)
5890 && peep2_reg_dead_p (1, operands[0])
5891 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5892 || INTVAL (operands[1]) == 7
5893 || INTVAL (operands[1]) == 15
5894 || INTVAL (operands[1]) == 31
5895 || INTVAL (operands[1]) == 63
5896 || INTVAL (operands[1]) == 127
5897 || INTVAL (operands[1]) == 255)"
5899 (and:SI (match_dup 0)
5901 (set (cc0) (compare (match_dup 0)
5904 (if_then_else (match_dup 5)
5905 (label_ref (match_dup 3))
5908 operands[4] = GEN_INT (~INTVAL (operands[1]));
5909 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5910 VOIDmode, cc0_rtx, const0_rtx);
5925 (compare (match_operand:SI 0 "register_operand" "")
5928 (if_then_else (match_operator 1 "gtle_operator"
5929 [(cc0) (const_int 0)])
5930 (label_ref (match_operand 2 "" ""))
5932 "TARGET_H8300H || TARGET_H8300S"
5933 [(set (cc0) (compare (and:SI (match_dup 0)
5937 (if_then_else (match_dup 1)
5938 (label_ref (match_dup 2))
5954 (compare (match_operand:SI 0 "register_operand" "")
5957 (if_then_else (match_operator 1 "gtuleu_operator"
5958 [(cc0) (const_int 0)])
5959 (label_ref (match_operand 2 "" ""))
5961 "TARGET_H8300H || TARGET_H8300S"
5962 [(set (cc0) (compare (and:SI (match_dup 0)
5966 (if_then_else (match_dup 3)
5967 (label_ref (match_dup 2))
5970 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5971 VOIDmode, cc0_rtx, const0_rtx);
5985 ;; We avoid this transformation if we see more than one copy of the
5986 ;; same compare insn.
5989 [(match_scratch:SI 4 "r")
5991 (compare (match_operand:SI 0 "register_operand" "")
5992 (match_operand:SI 1 "incdec_operand" "")))
5994 (if_then_else (match_operator 3 "eqne_operator"
5995 [(cc0) (const_int 0)])
5996 (label_ref (match_operand 2 "" ""))
5998 "(TARGET_H8300H || TARGET_H8300S)
5999 && INTVAL (operands[1]) != 0
6000 && !peep2_reg_dead_p (1, operands[0])
6001 && !same_cmp_following_p (insn)"
6005 (unspec:SI [(match_dup 4)
6008 (set (cc0) (compare (match_dup 4)
6011 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6012 (label_ref (match_dup 2))
6015 operands[5] = GEN_INT (- INTVAL (operands[1]));
6017 ;; Narrow the mode of testing if possible.
6020 [(set (match_operand:HI 0 "register_operand" "")
6021 (and:HI (match_dup 0)
6022 (match_operand:HI 1 "const_int_qi_operand" "")))
6023 (set (cc0) (compare (match_dup 0)
6026 (if_then_else (match_operator 3 "eqne_operator"
6027 [(cc0) (const_int 0)])
6028 (label_ref (match_operand 2 "" ""))
6030 "peep2_reg_dead_p (2, operands[0])"
6032 (and:QI (match_dup 4)
6034 (set (cc0) (compare (match_dup 4)
6037 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6038 (label_ref (match_dup 2))
6041 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
6042 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
6046 [(set (match_operand:SI 0 "register_operand" "")
6047 (and:SI (match_dup 0)
6048 (match_operand:SI 1 "const_int_qi_operand" "")))
6049 (set (cc0) (compare (match_dup 0)
6052 (if_then_else (match_operator 3 "eqne_operator"
6053 [(cc0) (const_int 0)])
6054 (label_ref (match_operand 2 "" ""))
6056 "peep2_reg_dead_p (2, operands[0])"
6058 (and:QI (match_dup 4)
6060 (set (cc0) (compare (match_dup 4)
6063 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6064 (label_ref (match_dup 2))
6067 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
6068 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
6072 [(set (match_operand:SI 0 "register_operand" "")
6073 (and:SI (match_dup 0)
6074 (match_operand:SI 1 "const_int_hi_operand" "")))
6075 (set (cc0) (compare (match_dup 0)
6078 (if_then_else (match_operator 3 "eqne_operator"
6079 [(cc0) (const_int 0)])
6080 (label_ref (match_operand 2 "" ""))
6082 "peep2_reg_dead_p (2, operands[0])"
6084 (and:HI (match_dup 4)
6086 (set (cc0) (compare (match_dup 4)
6089 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
6090 (label_ref (match_dup 2))
6093 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
6094 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);
6098 [(set (match_operand:SI 0 "register_operand" "")
6099 (and:SI (match_dup 0)
6100 (match_operand:SI 1 "const_int_qi_operand" "")))
6102 (xor:SI (match_dup 0)
6103 (match_operand:SI 2 "const_int_qi_operand" "")))
6104 (set (cc0) (compare (match_dup 0)
6107 (if_then_else (match_operator 4 "eqne_operator"
6108 [(cc0) (const_int 0)])
6109 (label_ref (match_operand 3 "" ""))
6111 "peep2_reg_dead_p (3, operands[0])
6112 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
6114 (and:QI (match_dup 5)
6117 (xor:QI (match_dup 5)
6119 (set (cc0) (compare (match_dup 5)
6122 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
6123 (label_ref (match_dup 3))
6126 operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
6127 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
6128 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);
6131 ;; These triggers right at the end of allocation of locals in the
6132 ;; prologue (and possibly at other places).
6134 ;; stack adjustment of -4, generate one push
6136 ;; before : 6 bytes, 10 clocks
6137 ;; after : 4 bytes, 10 clocks
6140 [(set (reg:SI SP_REG)
6141 (plus:SI (reg:SI SP_REG)
6143 (set (mem:SI (reg:SI SP_REG))
6144 (match_operand:SI 0 "register_operand" ""))]
6145 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6146 && REGNO (operands[0]) != SP_REG"
6147 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6151 ;; stack adjustment of -12, generate one push
6153 ;; before : 10 bytes, 14 clocks
6154 ;; after : 8 bytes, 14 clocks
6157 [(set (reg:SI SP_REG)
6158 (plus:SI (reg:SI SP_REG)
6160 (set (mem:SI (reg:SI SP_REG))
6161 (match_operand:SI 0 "register_operand" ""))]
6162 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
6163 && REGNO (operands[0]) != SP_REG"
6164 [(set (reg:SI SP_REG)
6165 (plus:SI (reg:SI SP_REG)
6167 (set (reg:SI SP_REG)
6168 (plus:SI (reg:SI SP_REG)
6170 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
6184 ;; if "reg" dies at the end of the sequence.
6187 [(set (match_operand 0 "register_operand" "")
6188 (match_operand 1 "memory_operand" ""))
6190 (match_operator 2 "h8sx_binary_memory_operator"
6192 (match_operand 3 "h8300_src_operand" "")]))
6193 (set (match_operand 4 "memory_operand" "")
6195 "0 /* Disable because it breaks compiling fp-bit.c. */
6197 && peep2_reg_dead_p (3, operands[0])
6198 && !reg_overlap_mentioned_p (operands[0], operands[3])
6199 && !reg_overlap_mentioned_p (operands[0], operands[4])
6200 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
6204 operands[5] = shallow_copy_rtx (operands[2]);
6205 XEXP (operands[5], 0) = operands[1];
6217 ;; if "reg" dies in the second insn.
6220 [(set (match_operand 0 "register_operand" "")
6221 (match_operand 1 "h8300_src_operand" ""))
6222 (set (match_operand 2 "h8300_dst_operand" "")
6223 (match_operator 3 "h8sx_binary_memory_operator"
6224 [(match_operand 4 "h8300_dst_operand" "")
6226 "0 /* Disable because it breaks compiling fp-bit.c. */
6228 && peep2_reg_dead_p (2, operands[0])
6229 && !reg_overlap_mentioned_p (operands[0], operands[4])"
6233 operands[5] = shallow_copy_rtx (operands[3]);
6234 XEXP (operands[5], 1) = operands[1];
6247 ;; if "reg" dies at the end of the sequence.
6250 [(set (match_operand 0 "register_operand" "")
6251 (match_operand 1 "memory_operand" ""))
6253 (match_operator 2 "h8sx_unary_memory_operator"
6255 (set (match_operand 3 "memory_operand" "")
6258 && peep2_reg_dead_p (3, operands[0])
6259 && !reg_overlap_mentioned_p (operands[0], operands[3])
6260 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
6264 operands[4] = shallow_copy_rtx (operands[2]);
6265 XEXP (operands[4], 0) = operands[1];
6277 ;; if "reg" dies in the comparison.
6280 [(set (match_operand 0 "register_operand" "")
6281 (match_operand 1 "h8300_dst_operand" ""))
6283 (compare (match_dup 0)
6284 (match_operand 2 "h8300_src_operand" "")))]
6286 && peep2_reg_dead_p (2, operands[0])
6287 && !reg_overlap_mentioned_p (operands[0], operands[2])
6288 && operands[2] != const0_rtx"
6290 (compare (match_dup 1)
6293 ;; Likewise for the second operand.
6296 [(set (match_operand 0 "register_operand" "")
6297 (match_operand 1 "h8300_src_operand" ""))
6299 (compare (match_operand 2 "h8300_dst_operand" "")
6302 && peep2_reg_dead_p (2, operands[0])
6303 && !reg_overlap_mentioned_p (operands[0], operands[2])"
6305 (compare (match_dup 2)
6308 ;; Combine two moves.
6311 [(set (match_operand 0 "register_operand" "")
6312 (match_operand 1 "h8300_src_operand" ""))
6313 (set (match_operand 2 "h8300_dst_operand" "")
6316 && peep2_reg_dead_p (2, operands[0])
6317 && !reg_overlap_mentioned_p (operands[0], operands[2])"