1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 93, 94, 95, 96, 97, 1998, 1999 Free Software
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 /* Forward declarations. */
43 void print_operand_address ();
45 static int h8300_interrupt_function_p PROTO ((tree));
46 static int h8300_monitor_function_p PROTO ((tree));
47 static int h8300_os_task_function_p PROTO ((tree));
49 /* CPU_TYPE, says what cpu we're compiling for. */
52 /* True if the current function is an interrupt handler
53 (either via #pragma or an attribute specification). */
54 int interrupt_handler;
56 /* True if the current function is an OS Task
57 (via an attribute specification). */
60 /* True if the current function is a monitor
61 (via an attribute specification). */
64 /* True if a #pragma saveall has been seen for the current function. */
67 static char *names_big[] =
68 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"};
70 static char *names_extended[] =
71 {"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"};
73 static char *names_upper_extended[] =
74 {"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"};
76 /* Points to one of the above. */
77 /* ??? The above could be put in an array indexed by CPU_TYPE. */
80 /* Various operations needed by the following, indexed by CPU_TYPE. */
82 static char *h8_push_ops[2] =
84 static char *h8_pop_ops[2] =
86 static char *h8_mov_ops[2] =
89 char *h8_push_op, *h8_pop_op, *h8_mov_op;
91 /* Initialize various cpu specific globals at start up. */
98 cpu_type = (int) CPU_H8300;
99 h8_reg_names = names_big;
103 /* For this we treat the H8/300 and H8/S the same. */
104 cpu_type = (int) CPU_H8300H;
105 h8_reg_names = names_extended;
107 h8_push_op = h8_push_ops[cpu_type];
108 h8_pop_op = h8_pop_ops[cpu_type];
109 h8_mov_op = h8_mov_ops[cpu_type];
117 static char *names_small[] =
118 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
119 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
121 return names_small[REGNO (x) * 2 + b];
124 /* REGNO must be saved/restored across calls if this macro is true. */
126 #define WORD_REG_USED(regno) \
130 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
131 || (regs_ever_live[regno] && !call_used_regs[regno])))
133 /* Output assembly language to FILE for the operation OP with operand size
134 SIZE to adjust the stack pointer. */
137 dosize (file, op, size)
142 /* On the h8300h and h8300s, for sizes <= 8 bytes it is as good or
143 better to use adds/subs insns rather than add.l/sub.l
144 with an immediate value. */
145 if (size > 4 && size <= 8 && (TARGET_H8300H || TARGET_H8300S))
147 /* Crank the size down to <= 4 */
148 fprintf (file, "\t%ss\t#%d,sp\n", op, 4);
155 if (TARGET_H8300H || TARGET_H8300S)
157 fprintf (file, "\t%ss\t#%d,sp\n", op, 4);
162 fprintf (file, "\t%ss\t#%d,sp\n", op, 2);
164 /* Fall through... */
167 fprintf (file, "\t%ss\t#%d,sp\n", op, size);
175 if (current_function_needs_context
176 && strcmp (op, "sub") == 0)
178 /* Egad. We don't have a temporary to hold the
179 size of the frame in the prologue! Just inline
180 the bastard since this shouldn't happen often. */
183 fprintf (file, "\tsubs\t#2,sp\n");
188 fprintf (file, "\tsubs\t#1,sp\n");
193 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
196 fprintf (file, "\t%s\t#%d,sp\n", op, size);
202 /* Output assembly language code for the function prologue. */
203 static int push_order[FIRST_PSEUDO_REGISTER] =
204 {0, 1, 2, 3, 4, 5, 6, -1, -1, -1};
205 static int pop_order[FIRST_PSEUDO_REGISTER] =
206 {6, 5, 4, 3, 2, 1, 0, -1, -1, -1};
208 /* This is what the stack looks like after the prolog of
209 a function with a frame has been set up:
215 <saved registers> <- sp
217 This is what the stack looks like after the prolog of
218 a function which doesn't have a frame:
223 <saved registers> <- sp
227 function_prologue (file, size)
231 register int mask = 0;
232 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
235 /* Note a function with the interrupt attribute and set interrupt_handler
237 if (h8300_interrupt_function_p (current_function_decl))
238 interrupt_handler = 1;
240 /* If the current function has the OS_Task attribute set, then
241 we have a naked prologue. */
242 if (h8300_os_task_function_p (current_function_decl))
244 fprintf (file, ";OS_Task prologue\n");
249 if (h8300_monitor_function_p (current_function_decl))
251 /* My understanding of monitor functions is they act just
252 like interrupt functions, except the prologue must
254 fprintf (file, ";monitor prologue\n");
255 interrupt_handler = 1;
259 fprintf (file, "\tsubs\t#2,sp\n");
260 fprintf (file, "\tpush\tr0\n");
261 fprintf (file, "\tstc\tccr,r0l\n");
262 fprintf (file, "\torc\t#128,ccr\n");
263 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
267 fprintf (file, "\tpush\ter0\n");
268 fprintf (file, "\tstc\tccr,r0l\n");
269 fprintf (file, "\torc\t#128,ccr\n");
270 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
274 if (frame_pointer_needed)
277 fprintf (file, "\t%s\t%s\n", h8_push_op,
278 h8_reg_names[FRAME_POINTER_REGNUM]);
279 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
280 h8_reg_names[STACK_POINTER_REGNUM],
281 h8_reg_names[FRAME_POINTER_REGNUM]);
284 /* leave room for locals */
285 dosize (file, "sub", fsize);
287 /* Push the rest of the registers */
288 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
290 int regno = push_order[idx];
293 && WORD_REG_USED (regno)
294 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
298 /* Try to push multiple registers. */
299 if (regno == 0 || regno == 4)
301 int second_regno = push_order[idx + 1];
302 int third_regno = push_order[idx + 2];
303 int fourth_regno = push_order[idx + 3];
305 if (fourth_regno >= 0
306 && WORD_REG_USED (fourth_regno)
307 && (!frame_pointer_needed
308 || fourth_regno != FRAME_POINTER_REGNUM)
310 && WORD_REG_USED (third_regno)
311 && (!frame_pointer_needed
312 || third_regno != FRAME_POINTER_REGNUM)
314 && WORD_REG_USED (second_regno)
315 && (!frame_pointer_needed
316 || second_regno != FRAME_POINTER_REGNUM))
318 fprintf (file, "\tstm.l %s-%s,@-sp\n",
320 h8_reg_names[fourth_regno]);
325 if (regno == 0 || regno == 4)
327 int second_regno = push_order[idx + 1];
328 int third_regno = push_order[idx + 2];
331 && WORD_REG_USED (third_regno)
332 && (!frame_pointer_needed
333 || third_regno != FRAME_POINTER_REGNUM)
335 && WORD_REG_USED (second_regno)
336 && (!frame_pointer_needed
337 || second_regno != FRAME_POINTER_REGNUM))
339 fprintf (file, "\tstm.l %s-%s,@-sp\n",
341 h8_reg_names[third_regno]);
346 if (regno == 0 || regno == 2 || regno == 4 || regno == 6)
348 int second_regno = push_order[idx + 1];
350 if (second_regno >= 0
351 && WORD_REG_USED (second_regno)
352 && (!frame_pointer_needed
353 || second_regno != FRAME_POINTER_REGNUM))
355 fprintf (file, "\tstm.l %s-%s,@-sp\n",
357 h8_reg_names[second_regno]);
363 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]);
368 /* Output assembly language code for the function epilogue. */
371 function_epilogue (file, size)
376 register int mask = 0;
377 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
379 rtx insn = get_last_insn ();
383 /* OS_Task epilogues are nearly naked -- they just have an
385 fprintf (file, ";OS_task epilogue\n");
386 fprintf (file, "\trts\n");
390 /* monitor epilogues are the same as interrupt function epilogues.
391 Just make a note that we're in an monitor epilogue. */
393 fprintf(file, ";monitor epilogue\n");
395 /* If the last insn was a BARRIER, we don't have to write any code. */
396 if (GET_CODE (insn) == NOTE)
397 insn = prev_nonnote_insn (insn);
398 if (insn && GET_CODE (insn) == BARRIER)
401 /* Pop the saved registers. */
402 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
404 int regno = pop_order[idx];
407 && WORD_REG_USED (regno)
408 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
412 /* Try to pop multiple registers. */
413 if (regno == 7 || regno == 3)
415 int second_regno = pop_order[idx + 1];
416 int third_regno = pop_order[idx + 2];
417 int fourth_regno = pop_order[idx + 3];
419 if (fourth_regno >= 0
420 && WORD_REG_USED (fourth_regno)
421 && (!frame_pointer_needed
422 || fourth_regno != FRAME_POINTER_REGNUM)
424 && WORD_REG_USED (third_regno)
425 && (!frame_pointer_needed
426 || third_regno != FRAME_POINTER_REGNUM)
428 && WORD_REG_USED (second_regno)
429 && (!frame_pointer_needed
430 || second_regno != FRAME_POINTER_REGNUM))
432 fprintf (file, "\tldm.l @sp+,%s-%s\n",
433 h8_reg_names[fourth_regno],
434 h8_reg_names[regno]);
439 if (regno == 6 || regno == 2)
441 int second_regno = pop_order[idx + 1];
442 int third_regno = pop_order[idx + 2];
445 && WORD_REG_USED (third_regno)
446 && (!frame_pointer_needed
447 || third_regno != FRAME_POINTER_REGNUM)
449 && WORD_REG_USED (second_regno)
450 && (!frame_pointer_needed
451 || second_regno != FRAME_POINTER_REGNUM))
453 fprintf (file, "\tldm.l @sp+,%s-%s\n",
454 h8_reg_names[third_regno],
455 h8_reg_names[regno]);
460 if (regno == 7 || regno == 5 || regno == 3 || regno == 1)
462 int second_regno = pop_order[idx + 1];
464 if (second_regno >= 0
465 && WORD_REG_USED (second_regno)
466 && (!frame_pointer_needed
467 || second_regno != FRAME_POINTER_REGNUM))
469 fprintf (file, "\tldm.l @sp+,%s-%s\n",
470 h8_reg_names[second_regno],
471 h8_reg_names[regno]);
477 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]);
481 /* deallocate locals */
482 dosize (file, "add", fsize);
484 /* pop frame pointer if we had one. */
485 if (frame_pointer_needed)
486 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]);
488 /* If this is a monitor function, there is one register still left on
491 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[0]);
493 if (interrupt_handler)
494 fprintf (file, "\trte\n");
496 fprintf (file, "\trts\n");
499 interrupt_handler = 0;
505 /* Output assembly code for the start of the file. */
507 asm_file_start (file)
510 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
511 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
512 fprintf (file, ";\trelease F-1\n");
514 fprintf (file, "; -O%d\n", optimize);
516 fprintf (file, "\n\t.h8300h\n");
517 else if (TARGET_H8300S)
518 fprintf (file, "\n\t.h8300s\n");
520 fprintf (file, "\n\n");
521 output_file_directive (file, main_input_filename);
524 /* Output assembly language code for the end of file. */
530 fprintf (file, "\t.end\n");
533 /* Return true if VALUE is a valid constant for constraint 'P'.
534 IE: VALUE is a power of two <= 2**15. */
537 small_power_of_two (value)
563 /* Return true if VALUE is a valid constant for constraint 'O', which
564 means that the constant would be ok to use as a bit for a bclr
571 return small_power_of_two ((~value) & 0xff);
574 /* Return true is OP is a valid source operand for an integer move
578 general_operand_src (op, mode)
580 enum machine_mode mode;
582 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
584 return general_operand (op, mode);
587 /* Return true if OP is a valid destination operand for an integer move
591 general_operand_dst (op, mode)
593 enum machine_mode mode;
595 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
597 return general_operand (op, mode);
600 /* Return true if OP is a const valid for a bit clear instruction. */
603 o_operand (operand, mode)
605 enum machine_mode mode;
607 return (GET_CODE (operand) == CONST_INT
608 && CONST_OK_FOR_O (INTVAL (operand)));
611 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
614 p_operand (operand, mode)
616 enum machine_mode mode;
618 return (GET_CODE (operand) == CONST_INT
619 && CONST_OK_FOR_P (INTVAL (operand)));
622 /* Return true if OP is a valid call operand. */
625 call_insn_operand (op, mode)
627 enum machine_mode mode;
629 if (GET_CODE (op) == MEM)
631 rtx inside = XEXP (op, 0);
632 if (register_operand (inside, Pmode))
634 if (CONSTANT_ADDRESS_P (inside))
641 adds_subs_operand (op, mode)
643 enum machine_mode mode;
645 if (GET_CODE (op) == CONST_INT)
647 if (INTVAL (op) <= 4 && INTVAL (op) >= 0)
649 if (INTVAL (op) >= -4 && INTVAL (op) <= 0)
651 if ((TARGET_H8300H || TARGET_H8300S)
653 && (INTVAL (op) <= 8 && INTVAL (op) >= 0))
655 if ((TARGET_H8300H || TARGET_H8300S)
657 && (INTVAL (op) >= -8 && INTVAL (op) <= 0))
663 /* Return nonzero if op is an adds/subs operand which only requires
664 one insn to implement. It is assumed that OP is already an adds/subs
667 one_insn_adds_subs_operand (op, mode)
669 enum machine_mode mode;
671 int val = INTVAL (op);
673 if (val == 1 || val == -1
674 || val == 2 || val == -2
675 || ((TARGET_H8300H || TARGET_H8300S)
676 && (val == 4 || val == -4)))
682 output_adds_subs (operands)
685 int val = INTVAL (operands[2]);
687 /* First get the value into the range -4..4 inclusive.
689 The only way it can be out of this range is when TARGET_H8300H
690 or TARGET_H8300S is true, thus it is safe to use adds #4 and subs #4. */
693 output_asm_insn ("adds #4,%A0", operands);
699 output_asm_insn ("subs #4,%A0", operands);
703 /* Handle case were val == 4 or val == -4 and we're compiling
704 for TARGET_H8300H or TARGET_H8300S. */
705 if ((TARGET_H8300H || TARGET_H8300S)
707 return "adds #4,%A0";
709 if ((TARGET_H8300H || TARGET_H8300S)
711 return "subs #4,%A0";
715 output_asm_insn ("adds #2,%A0", operands);
721 output_asm_insn ("subs #2,%A0", operands);
725 /* val should be one or two now. */
727 return "adds #2,%A0";
730 return "subs #2,%A0";
732 /* val should be one now. */
734 return "adds #1,%A0";
737 return "subs #1,%A0";
739 /* If not optimizing, we might be asked to add 0. */
743 /* In theory, this can't happen. */
747 /* Return true if OP is a valid call operand, and OP represents
748 an operand for a small call (4 bytes instead of 6 bytes). */
751 small_call_insn_operand (op, mode)
753 enum machine_mode mode;
755 if (GET_CODE (op) == MEM)
757 rtx inside = XEXP (op, 0);
759 /* Register indirect is a small call. */
760 if (register_operand (inside, Pmode))
763 /* A call through the function vector is a small
765 if (GET_CODE (inside) == SYMBOL_REF
766 && SYMBOL_REF_FLAG (inside))
769 /* Otherwise it's a large call. */
773 /* Return true if OP is a valid jump operand. */
776 jump_address_operand (op, mode)
778 enum machine_mode mode;
780 if (GET_CODE (op) == REG)
781 return mode == Pmode;
783 if (GET_CODE (op) == MEM)
785 rtx inside = XEXP (op, 0);
786 if (register_operand (inside, Pmode))
788 if (CONSTANT_ADDRESS_P (inside))
794 /* Recognize valid operands for bitfield instructions. */
796 extern int rtx_equal_function_value_matters;
799 bit_operand (op, mode)
801 enum machine_mode mode;
803 /* We can except any general operand, expept that MEM operands must
804 be limited to those that use addresses valid for the 'U' constraint. */
805 if (!general_operand (op, mode))
808 /* Accept any mem during RTL generation. Otherwise, the code that does
809 insv and extzv will think that we can not handle memory. However,
810 to avoid reload problems, we only accept 'U' MEM operands after RTL
811 generation. This means that any named pattern which uses this predicate
812 must force its operands to match 'U' before emitting RTL. */
814 if (GET_CODE (op) == REG)
816 if (GET_CODE (op) == SUBREG)
818 if (!rtx_equal_function_value_matters)
820 /* We're building rtl */
821 return GET_CODE (op) == MEM;
825 return (GET_CODE (op) == MEM
826 && EXTRA_CONSTRAINT (op, 'U'));
831 bit_memory_operand (op, mode)
833 enum machine_mode mode;
835 return (GET_CODE (op) == MEM
836 && EXTRA_CONSTRAINT (op, 'U'));
839 /* Recognize valid operators for bit test. */
842 eq_operator (x, mode)
844 enum machine_mode mode;
846 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
849 /* Handle machine specific pragmas for compatibility with existing
850 compilers for the H8/300.
852 pragma saveall generates prolog/epilog code which saves and
853 restores all the registers on function entry.
855 pragma interrupt saves and restores all registers, and exits with
856 an rte instruction rather than an rts. A pointer to a function
857 with this attribute may be safely used in an interrupt vector. */
860 handle_pragma (p_getc, p_ungetc, pname)
861 int (* p_getc) PROTO ((void));
862 void (* p_ungetc) PROTO ((int));
867 if (strcmp (pname, "interrupt") == 0)
868 interrupt_handler = retval = 1;
869 else if (strcmp (pname, "saveall") == 0)
870 pragma_saveall = retval = 1;
875 /* If the next arg with MODE and TYPE is to be passed in a register, return
876 the rtx to represent where it is passed. CUM represents the state after
877 the last argument. NAMED is not used. */
879 static char *hand_list[] =
899 /* Return an RTX to represent where a value with mode MODE will be returned
900 from a function. If the result is 0, the argument is pushed. */
903 function_arg (cum, mode, type, named)
904 CUMULATIVE_ARGS *cum;
905 enum machine_mode mode;
913 /* Never pass unnamed arguments in registers. */
917 /* Pass 3 regs worth of data in regs when user asked on the command line. */
918 if (TARGET_QUICKCALL)
921 /* If calling hand written assembler, use 4 regs of args. */
927 fname = XSTR (cum->libcall, 0);
929 /* See if this libcall is one of the hand coded ones. */
931 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
943 size = int_size_in_bytes (type);
945 size = GET_MODE_SIZE (mode);
947 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
953 switch (cum->nbytes / UNITS_PER_WORD)
956 result = gen_rtx_REG (mode, 0);
959 result = gen_rtx_REG (mode, 1);
962 result = gen_rtx_REG (mode, 2);
965 result = gen_rtx_REG (mode, 3);
976 /* Return the cost of the rtx R with code CODE. */
996 if (TARGET_H8300H || TARGET_H8300S)
1017 /* Documentation for the machine specific operand escapes:
1019 'A' print rn in h8/300 mode, erN in H8/300H mode
1020 'C' print (operand - 2).
1021 'E' like s but negative.
1022 'F' like t but negative.
1023 'G' constant just the negative
1024 'M' turn a 'M' constant into its negative mod 2.
1025 'P' if operand is incing/decing sp, print .w, otherwise .b.
1026 'R' print operand as a byte:8 address if appropriate, else fall back to
1028 'S' print operand as a long word
1029 'T' print operand as a word
1030 'U' if operand is incing/decing sp, print l, otherwise nothing.
1031 'V' find the set bit, and print its number.
1032 'W' find the clear bit, and print its number.
1033 'X' print operand as a byte
1034 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1035 If this operand isn't a register, fall back to 'R' handling.
1037 'b' print the bit opcode
1038 'c' print the ibit opcode
1039 'd' bcc if EQ, bcs if NE
1040 'e' first word of 32 bit value - if reg, then least reg. if mem
1041 then least. if const then most sig word
1042 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1043 then +2. if const then least sig word
1044 'g' bcs if EQ, bcc if NE
1045 'j' print operand as condition code.
1046 'k' print operand as reverse condition code.
1047 's' print as low byte of 16 bit value
1048 't' print as high byte of 16 bit value
1049 'w' print as low byte of 32 bit value
1050 'x' print as 2nd byte of 32 bit value
1051 'y' print as 3rd byte of 32 bit value
1052 'z' print as msb of 32 bit value
1055 /* Return assembly language string which identifies a comparison type. */
1088 /* Print operand X using operand code CODE to assembly language output file
1092 print_operand (file, x, code)
1097 /* This is used for communication between the 'P' and 'U' codes. */
1098 static char *last_p;
1100 /* This is used for communication between codes V,W,Z and Y. */
1106 if (GET_CODE (x) == REG)
1107 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1112 fprintf (file, "#%d", INTVAL (x) - 2);
1115 switch (GET_CODE (x))
1118 fprintf (file, "%sl", names_big[REGNO (x)]);
1121 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1128 switch (GET_CODE (x))
1131 fprintf (file, "%sh", names_big[REGNO (x)]);
1134 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1141 if (GET_CODE (x) != CONST_INT)
1143 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1146 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1153 fprintf (file, "#2");
1159 fprintf (file, "#1");
1166 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1169 fprintf (file, ".w");
1174 fprintf (file, ".b");
1178 if (GET_CODE (x) == REG)
1179 fprintf (file, "%s", names_extended[REGNO (x)]);
1184 if (GET_CODE (x) == REG)
1185 fprintf (file, "%s", names_big[REGNO (x)]);
1190 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1193 bitint = exact_log2 (INTVAL (x));
1196 fprintf (file, "#%d", bitint & 7);
1199 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1202 fprintf (file, "#%d", bitint & 7);
1206 if (GET_CODE (x) == REG)
1207 fprintf (file, "%s", byte_reg (x, 0));
1214 if (GET_CODE (x) == REG)
1215 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1217 print_operand (file, x, 'R');
1221 bitint = INTVAL (x);
1222 fprintf (file, "#%d", bitint & 7);
1225 switch (GET_CODE (x))
1228 fprintf (file, "bor");
1231 fprintf (file, "bxor");
1234 fprintf (file, "band");
1239 switch (GET_CODE (x))
1242 fprintf (file, "bior");
1245 fprintf (file, "bixor");
1248 fprintf (file, "biand");
1253 switch (GET_CODE (x))
1256 fprintf (file, "bcc");
1259 fprintf (file, "bcs");
1266 switch (GET_CODE (x))
1270 fprintf (file, "%s", names_big[REGNO (x)]);
1272 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1275 x = adj_offsettable_operand (x, 0);
1276 print_operand (file, x, 0);
1279 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1285 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1286 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1287 fprintf (file, "#%d", ((val >> 16) & 0xffff));
1296 switch (GET_CODE (x))
1300 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1302 fprintf (file, "%s", names_big[REGNO (x)]);
1305 x = adj_offsettable_operand (x, 2);
1306 print_operand (file, x, 0);
1309 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1315 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1316 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1317 fprintf (file, "#%d", (val & 0xffff));
1325 switch (GET_CODE (x))
1328 fprintf (file, "bcc");
1331 fprintf (file, "bcs");
1338 asm_fprintf (file, cond_string (GET_CODE (x)));
1341 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1344 if (GET_CODE (x) == CONST_INT)
1345 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1347 fprintf (file, "%s", byte_reg (x, 0));
1350 if (GET_CODE (x) == CONST_INT)
1351 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1353 fprintf (file, "%s", byte_reg (x, 1));
1356 if (GET_CODE (x) != CONST_INT)
1358 fprintf (file, "%d", INTVAL (x));
1361 if (GET_CODE (x) == CONST_INT)
1362 fprintf (file, "#%d", INTVAL (x) & 0xff);
1364 fprintf (file, "%s",
1365 byte_reg (x, TARGET_H8300 ? 2 : 0));
1368 if (GET_CODE (x) == CONST_INT)
1369 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1371 fprintf (file, "%s",
1372 byte_reg (x, TARGET_H8300 ? 3 : 1));
1375 if (GET_CODE (x) == CONST_INT)
1376 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1378 fprintf (file, "%s", byte_reg (x, 0));
1381 if (GET_CODE (x) == CONST_INT)
1382 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1384 fprintf (file, "%s", byte_reg (x, 1));
1389 switch (GET_CODE (x))
1392 switch (GET_MODE (x))
1395 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1396 fprintf (file, "%s", byte_reg (x, 0));
1397 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1398 fprintf (file, "%s", names_big[REGNO (x)]);
1402 fprintf (file, "%s", names_big[REGNO (x)]);
1406 fprintf (file, "%s", names_extended[REGNO (x)]);
1414 fprintf (file, "@");
1415 output_address (XEXP (x, 0));
1417 /* If this is an 'R' operand (reference into the 8-bit
1418 area), then specify a symbolic address as "foo:8",
1419 otherwise if operand is still in eight bit section, use
1421 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1422 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1423 fprintf (file, (code == 'R' ? ":8" : ":16"));
1424 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1425 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1426 fprintf (file, ":16");
1433 fprintf (file, "#");
1434 print_operand_address (file, x);
1440 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1441 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1442 fprintf (file, "#%d", val);
1449 /* Output assembly language output for the address ADDR to FILE. */
1452 print_operand_address (file, addr)
1456 switch (GET_CODE (addr))
1459 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1463 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1467 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1471 fprintf (file, "(");
1472 if (GET_CODE (XEXP (addr, 0)) == REG)
1475 print_operand_address (file, XEXP (addr, 1));
1476 fprintf (file, ",");
1477 print_operand_address (file, XEXP (addr, 0));
1482 print_operand_address (file, XEXP (addr, 0));
1483 fprintf (file, "+");
1484 print_operand_address (file, XEXP (addr, 1));
1486 fprintf (file, ")");
1491 /* Since the h8/300 only has 16 bit pointers, negative values are also
1492 those >= 32768. This happens for example with pointer minus a
1493 constant. We don't want to turn (char *p - 2) into
1494 (char *p + 65534) because loop unrolling can build upon this
1495 (IE: char *p + 131068). */
1496 int n = INTVAL (addr);
1498 n = (int) (short) n;
1500 /* ??? Why the special case for -ve values? */
1501 fprintf (file, "-%d", -n);
1503 fprintf (file, "%d", n);
1508 output_addr_const (file, addr);
1513 /* Output all insn addresses and their sizes into the assembly language
1514 output file. This is helpful for debugging whether the length attributes
1515 in the md file are correct. This is not meant to be a user selectable
1519 final_prescan_insn (insn, operand, num_operands)
1523 /* This holds the last insn address. */
1524 static int last_insn_address = 0;
1526 int uid = INSN_UID (insn);
1528 if (TARGET_RTL_DUMP)
1530 fprintf (asm_out_file, "\n****************");
1531 print_rtl (asm_out_file, PATTERN (insn));
1532 fprintf (asm_out_file, "\n");
1535 if (TARGET_ADDRESSES)
1537 fprintf (asm_out_file, "; 0x%x %d\n", insn_addresses[uid],
1538 insn_addresses[uid] - last_insn_address);
1539 last_insn_address = insn_addresses[uid];
1543 /* Prepare for an SI sized move. */
1549 rtx src = operands[1];
1550 rtx dst = operands[0];
1551 if (!reload_in_progress && !reload_completed)
1553 if (!register_operand (dst, GET_MODE (dst)))
1555 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1556 emit_move_insn (tmp, src);
1563 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1564 Define the offset between two registers, one to be eliminated, and the other
1565 its replacement, at the start of a routine. */
1568 initial_offset (from, to)
1572 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1573 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1578 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1579 if (WORD_REG_USED (regno))
1580 offset += UNITS_PER_WORD;
1582 /* See the comments for get_frame_size. We need to round it up to
1585 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1586 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1588 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1589 offset += UNITS_PER_WORD; /* Skip saved PC */
1594 /* Update the condition code from the insn. */
1597 notice_update_cc (body, insn)
1601 switch (get_attr_cc (insn))
1604 /* Insn does not affect CC at all. */
1608 /* Insn does not change CC, but the 0'th operand has been changed. */
1609 if (cc_status.value1 != 0
1610 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1611 cc_status.value1 = 0;
1615 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1616 The V flag is unusable. The C flag may or may not be known but
1617 that's ok because alter_cond will change tests to use EQ/NE. */
1619 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1620 cc_status.value1 = recog_data.operand[0];
1624 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1625 The C flag may or may not be known but that's ok because
1626 alter_cond will change tests to use EQ/NE. */
1628 cc_status.flags |= CC_NO_CARRY;
1629 cc_status.value1 = recog_data.operand[0];
1633 /* The insn is a compare instruction. */
1635 cc_status.value1 = SET_SRC (body);
1639 /* Insn doesn't leave CC in a usable state. */
1645 /* Recognize valid operators for bit instructions */
1648 bit_operator (x, mode)
1650 enum machine_mode mode;
1652 enum rtx_code code = GET_CODE (x);
1661 We devote a fair bit of code to getting efficient shifts since we can only
1662 shift one bit at a time on the H8/300 and H8/300H and only one or two
1663 bits at a time on the H8/S.
1665 The basic shift methods:
1667 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1668 this is the default. SHIFT_LOOP
1670 * inlined shifts -- emit straight line code for the shift; this is
1671 used when a straight line shift is about the same size or smaller
1672 than a loop. We allow the inline version to be slightly longer in
1673 some cases as it saves a register. SHIFT_INLINE
1675 * rotate + and -- rotate the value the opposite direction, then
1676 mask off the values we don't need. This is used when only a few
1677 of the bits in the original value will survive in the shifted value.
1678 Again, this is used when it's about the same size or smaller than
1679 a loop. We allow this version to be slightly longer as it is usually
1680 much faster than a loop. SHIFT_ROT_AND
1682 * swap (+ shifts) -- often it's possible to swap bytes/words to
1683 simulate a shift by 8/16. Once swapped a few inline shifts can be
1684 added if the shift count is slightly more than 8 or 16. This is used
1685 when it's about the same size or smaller than a loop. We allow this
1686 version to be slightly longer as it is usually much faster than a loop.
1689 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1692 Here are some thoughts on what the absolutely positively best code is.
1693 "Best" here means some rational trade-off between code size and speed,
1694 where speed is more preferred but not at the expense of generating 20 insns.
1696 A trailing '*' after the shift count indicates the "best" mode isn't
1699 H8/300 QImode shifts
1700 1-4 - do them inline
1701 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1703 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1704 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1706 H8/300 HImode shifts
1707 1-4 - do them inline
1709 7 - shift 2nd half other way into carry.
1710 copy 1st half into 2nd half
1711 rotate 2nd half other way with carry
1712 rotate 1st half other way (no carry)
1713 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1714 sign extend 1st half (ASHIFTRT)
1715 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1716 9-12 - do shift by 8, inline remaining shifts
1717 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1719 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1720 - ASHIFTRT: shll, subx, set other byte
1722 H8/300 SImode shifts
1723 1-2 - do them inline
1725 7* - shift other way once, move bytes into place,
1726 move carry into place (possibly with sign extension)
1727 8 - move bytes into place, zero or sign extend other
1729 15* - shift other way once, move word into place, move carry into place
1730 16 - move word, zero or sign extend other
1732 24* - move bytes into place, zero or sign extend other
1734 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1737 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1739 ASHIFTRT: shll top byte, subx, copy to other bytes
1741 H8/300H QImode shifts (same as H8/300 QImode shifts)
1742 1-4 - do them inline
1743 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1745 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1746 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1749 H8/300H HImode shifts
1750 1-4 - do them inline
1752 7 - shift 2nd half other way into carry.
1753 copy 1st half into 2nd half
1754 rotate entire word other way using carry
1755 mask off remaining bits (ASHIFT | LSHIFTRT)
1756 sign extend remaining bits (ASHIFTRT)
1757 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1758 9-12 - do shift by 8, inline remaining shifts
1759 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1761 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1762 - ASHIFTRT: shll, subx, set other byte
1764 H8/300H SImode shifts
1765 (These are complicated by the fact that we don't have byte level access to
1767 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1768 1-4 - do them inline
1770 15* - shift other way once, move word into place, move carry into place
1771 (with sign extension for ASHIFTRT)
1772 16 - move word into place, zero or sign extend other
1773 17-20 - do 16bit shift, then inline remaining shifts
1775 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1776 move word 0 to word 1, zero word 0
1777 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1778 zero word 1, zero byte 1
1779 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1780 sign extend byte 0, sign extend word 0
1781 25-27* - either loop, or
1782 do 24 bit shift, inline rest
1783 28-30 - ASHIFT: rotate 4/3/2, mask
1784 LSHIFTRT: rotate 4/3/2, mask
1786 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1789 1-6 - do them inline
1790 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1791 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1794 1-7 - do them inline
1795 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1796 9-12 - do shift by 8, inline remaining shifts
1797 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1799 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1800 - ASHIFTRT: shll, subx, set other byte
1803 (These are complicated by the fact that we don't have byte level access to
1805 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1806 1-10 - do them inline
1808 15* - shift other way once, move word into place, move carry into place
1809 (with sign extension for ASHIFTRT)
1810 16 - move word into place, zero or sign extend other
1811 17-20 - do 16bit shift, then inline remaining shifts
1813 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1814 move word 0 to word 1, zero word 0
1815 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1816 zero word 1, zero byte 1
1817 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1818 sign extend byte 0, sign extend word 0
1819 25-27* - either loop, or
1820 do 24 bit shift, inline rest
1821 28-30 - ASHIFT: rotate 4/3/2, mask
1822 LSHIFTRT: rotate 4/3/2, mask
1824 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1829 nshift_operator (x, mode)
1831 enum machine_mode mode;
1833 switch (GET_CODE (x))
1845 /* Called from the .md file to emit code to do shifts.
1846 Returns a boolean indicating success
1847 (currently this is always TRUE). */
1850 expand_a_shift (mode, code, operands)
1851 enum machine_mode mode;
1855 emit_move_insn (operands[0], operands[1]);
1857 /* need a loop to get all the bits we want - we generate the
1858 code at emit time, but need to allocate a scratch reg now */
1860 emit_insn (gen_rtx_PARALLEL
1863 gen_rtx_SET (VOIDmode, operands[0],
1864 gen_rtx (code, mode, operands[0],
1866 gen_rtx_CLOBBER (VOIDmode,
1867 gen_rtx_SCRATCH (QImode)))));
1872 /* Shift algorithm determination.
1874 There are various ways of doing a shift:
1875 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1877 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1878 necessary bits into position and then set the rest to zero.
1879 SHIFT_SPECIAL: Hand crafted assembler.
1880 SHIFT_LOOP: If the above methods fail, just loop. */
1891 /* Symbols of the various shifts which can be used as indices. */
1895 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1898 /* Symbols of the various modes which can be used as indices. */
1902 QIshift, HIshift, SIshift
1905 /* For single bit shift insns, record assembler and what bits of the
1906 condition code are valid afterwards (represented as various CC_FOO
1907 bits, 0 means CC isn't left in a usable state). */
1915 /* Assembler instruction shift table.
1917 These tables are used to look up the basic shifts.
1918 They are indexed by cpu, shift_type, and mode.
1921 static const struct shift_insn shift_one[2][3][3] =
1927 { "shll\t%X0", CC_NO_CARRY },
1928 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1929 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
1931 /* SHIFT_LSHIFTRT */
1933 { "shlr\t%X0", CC_NO_CARRY },
1934 { "shlr\t%t0\n\trotxr\t%s0", 0 },
1935 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1937 /* SHIFT_ASHIFTRT */
1939 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1940 { "shar\t%t0\n\trotxr\t%s0", 0 },
1941 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1948 { "shll.b\t%X0", CC_NO_CARRY },
1949 { "shll.w\t%T0", CC_NO_CARRY },
1950 { "shll.l\t%S0", CC_NO_CARRY }
1952 /* SHIFT_LSHIFTRT */
1954 { "shlr.b\t%X0", CC_NO_CARRY },
1955 { "shlr.w\t%T0", CC_NO_CARRY },
1956 { "shlr.l\t%S0", CC_NO_CARRY }
1958 /* SHIFT_ASHIFTRT */
1960 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1961 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1962 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1967 static const struct shift_insn shift_two[3][3] =
1971 { "shll.b\t#2,%X0", CC_NO_CARRY },
1972 { "shll.w\t#2,%T0", CC_NO_CARRY },
1973 { "shll.l\t#2,%S0", CC_NO_CARRY }
1975 /* SHIFT_LSHIFTRT */
1977 { "shlr.b\t#2,%X0", CC_NO_CARRY },
1978 { "shlr.w\t#2,%T0", CC_NO_CARRY },
1979 { "shlr.l\t#2,%S0", CC_NO_CARRY }
1981 /* SHIFT_ASHIFTRT */
1983 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1984 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1985 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1989 /* Rotates are organized by which shift they'll be used in implementing.
1990 There's no need to record whether the cc is valid afterwards because
1991 it is the AND insn that will decide this. */
1993 static const char *const rotate_one[2][3][3] =
2000 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2003 /* SHIFT_LSHIFTRT */
2006 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2009 /* SHIFT_ASHIFTRT */
2012 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2024 /* SHIFT_LSHIFTRT */
2030 /* SHIFT_ASHIFTRT */
2039 static const char *const rotate_two[3][3] =
2047 /* SHIFT_LSHIFTRT */
2053 /* SHIFT_ASHIFTRT */
2061 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
2062 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
2063 We don't achieve maximum efficiency in all cases, but the hooks are here
2066 For now we just use lots of switch statements. Since we don't even come
2067 close to supporting all the cases, this is simplest. If this function ever
2068 gets too big, perhaps resort to a more table based lookup. Of course,
2069 at this point you may just wish to do it all in rtl.
2071 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2072 1,2,3,4 will be inlined (1,2 for SI). */
2074 static enum shift_alg
2075 get_shift_alg (cpu, shift_type, mode, count, assembler_p,
2076 assembler2_p, cc_valid_p)
2078 enum shift_type shift_type;
2079 enum machine_mode mode;
2081 const char **assembler_p;
2082 const char **assembler2_p;
2085 /* The default is to loop. */
2086 enum shift_alg alg = SHIFT_LOOP;
2087 enum shift_mode shift_mode;
2089 /* We don't handle negative shifts or shifts greater than the word size,
2090 they should have been handled already. */
2092 if (count < 0 || count > GET_MODE_BITSIZE (mode))
2098 shift_mode = QIshift;
2101 shift_mode = HIshift;
2104 shift_mode = SIshift;
2110 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
2111 It is up to the caller to know that looping clobbers cc. */
2112 *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler;
2114 *assembler2_p = shift_two[shift_type][shift_mode].assembler;
2116 *assembler2_p = NULL;
2117 *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid;
2119 /* Now look for cases we want to optimize. */
2125 return SHIFT_INLINE;
2128 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
2129 fast as SHIFT_ROT_AND, plus CC is valid. */
2130 if (TARGET_H8300S && count <= 6)
2131 return SHIFT_INLINE;
2133 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2134 through the entire value. */
2135 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2137 *assembler_p = "shll\t%X0\n\tsubx\t%X0,%X0";
2139 return SHIFT_SPECIAL;
2142 /* Other ASHIFTRTs are too much of a pain. */
2143 if (shift_type == SHIFT_ASHIFTRT)
2146 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */
2147 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2149 *assembler2_p = rotate_two[shift_type][shift_mode];
2151 return SHIFT_ROT_AND;
2156 return SHIFT_INLINE;
2157 else if (TARGET_H8300S && count <= 7)
2158 return SHIFT_INLINE;
2159 else if (count == 7)
2161 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2163 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2165 return SHIFT_SPECIAL;
2168 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2170 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2172 return SHIFT_SPECIAL;
2175 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2177 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2179 return SHIFT_SPECIAL;
2182 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2184 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2186 return SHIFT_SPECIAL;
2189 if (shift_type == SHIFT_ASHIFTRT)
2191 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2193 return SHIFT_SPECIAL;
2196 else if (count == 8)
2201 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2203 return SHIFT_SPECIAL;
2204 case SHIFT_LSHIFTRT:
2205 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2207 return SHIFT_SPECIAL;
2208 case SHIFT_ASHIFTRT:
2210 *assembler_p = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0\t";
2212 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2214 return SHIFT_SPECIAL;
2217 else if (count == 9)
2222 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
2224 return SHIFT_SPECIAL;
2225 case SHIFT_LSHIFTRT:
2226 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
2228 return SHIFT_SPECIAL;
2229 case SHIFT_ASHIFTRT:
2231 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
2233 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
2235 return SHIFT_SPECIAL;
2238 else if (count == 10)
2244 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\t";
2246 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2248 return SHIFT_SPECIAL;
2249 case SHIFT_LSHIFTRT:
2251 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
2253 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2255 return SHIFT_SPECIAL;
2256 case SHIFT_ASHIFTRT:
2258 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2259 else if (TARGET_H8300H)
2260 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2261 else if (TARGET_H8300S)
2262 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
2264 return SHIFT_SPECIAL;
2267 else if (count == 11)
2273 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
2275 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2277 return SHIFT_SPECIAL;
2278 case SHIFT_LSHIFTRT:
2280 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
2282 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2284 return SHIFT_SPECIAL;
2285 case SHIFT_ASHIFTRT:
2287 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2288 else if (TARGET_H8300H)
2289 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2290 else if (TARGET_H8300S)
2291 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
2293 return SHIFT_SPECIAL;
2296 else if (count == 12)
2302 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
2304 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2306 return SHIFT_SPECIAL;
2307 case SHIFT_LSHIFTRT:
2309 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
2311 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2313 return SHIFT_SPECIAL;
2314 case SHIFT_ASHIFTRT:
2316 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2317 else if (TARGET_H8300H)
2318 *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2319 else if (TARGET_H8300S)
2320 *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
2322 return SHIFT_SPECIAL;
2325 else if (!TARGET_H8300 && (count == 13 || count == 14)
2328 if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2330 *assembler_p = "shll\t%t0,%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2332 return SHIFT_SPECIAL;
2334 else if (shift_type != SHIFT_ASHIFTRT)
2336 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2338 *assembler2_p = rotate_two[shift_type][shift_mode];
2340 *assembler2_p = NULL;
2342 return SHIFT_ROT_AND;
2348 if (count <= (TARGET_H8300 ? 2 : 4))
2349 return SHIFT_INLINE;
2350 else if (TARGET_H8300S && count <= 10)
2351 return SHIFT_INLINE;
2352 else if (count == 8 && TARGET_H8300)
2357 *assembler_p = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2359 return SHIFT_SPECIAL;
2360 case SHIFT_LSHIFTRT:
2361 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2363 return SHIFT_SPECIAL;
2364 case SHIFT_ASHIFTRT:
2365 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2367 return SHIFT_SPECIAL;
2370 else if (count == 8 && !TARGET_H8300)
2375 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2377 return SHIFT_SPECIAL;
2378 case SHIFT_LSHIFTRT:
2379 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2381 return SHIFT_SPECIAL;
2382 case SHIFT_ASHIFTRT:
2383 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2385 return SHIFT_SPECIAL;
2388 else if (count == 16)
2393 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2395 return SHIFT_SPECIAL;
2396 case SHIFT_LSHIFTRT:
2397 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2399 return SHIFT_SPECIAL;
2400 case SHIFT_ASHIFTRT:
2402 *assembler_p = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2404 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2406 return SHIFT_SPECIAL;
2409 else if (count == 17 && !TARGET_H8300)
2414 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
2416 return SHIFT_SPECIAL;
2417 case SHIFT_LSHIFTRT:
2418 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
2420 return SHIFT_SPECIAL;
2421 case SHIFT_ASHIFTRT:
2422 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
2424 return SHIFT_SPECIAL;
2427 else if (count == 18 && !TARGET_H8300)
2433 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
2435 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2437 return SHIFT_SPECIAL;
2438 case SHIFT_LSHIFTRT:
2440 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
2442 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2444 return SHIFT_SPECIAL;
2445 case SHIFT_ASHIFTRT:
2447 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
2449 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2451 return SHIFT_SPECIAL;
2454 else if (count == 19 && !TARGET_H8300)
2460 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
2462 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2464 return SHIFT_SPECIAL;
2465 case SHIFT_LSHIFTRT:
2467 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
2469 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2471 return SHIFT_SPECIAL;
2472 case SHIFT_ASHIFTRT:
2474 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
2476 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2478 return SHIFT_SPECIAL;
2481 else if (count == 20 && TARGET_H8300S)
2486 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
2488 return SHIFT_SPECIAL;
2489 case SHIFT_LSHIFTRT:
2490 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
2492 return SHIFT_SPECIAL;
2493 case SHIFT_ASHIFTRT:
2494 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
2496 return SHIFT_SPECIAL;
2499 else if (count == 24 && !TARGET_H8300)
2504 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2506 return SHIFT_SPECIAL;
2507 case SHIFT_LSHIFTRT:
2508 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2510 return SHIFT_SPECIAL;
2511 case SHIFT_ASHIFTRT:
2512 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2514 return SHIFT_SPECIAL;
2517 else if (count >= 28 && count <= 30 && !TARGET_H8300)
2519 if (shift_type == SHIFT_ASHIFTRT)
2525 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2527 *assembler2_p = rotate_two[shift_type][shift_mode];
2529 *assembler2_p = NULL;
2531 return SHIFT_ROT_AND;
2534 else if (count == 31)
2536 if (shift_type == SHIFT_ASHIFTRT)
2539 *assembler_p = "shll\t%z0\n\tsubx %w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2541 *assembler_p = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2543 return SHIFT_SPECIAL;
2549 if (shift_type == SHIFT_ASHIFT)
2550 *assembler_p = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2552 *assembler_p = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2554 return SHIFT_SPECIAL;
2558 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2560 *assembler2_p = rotate_two[shift_type][shift_mode];
2562 *assembler2_p = NULL;
2564 return SHIFT_ROT_AND;
2577 /* Emit the assembler code for doing shifts. */
2580 emit_a_shift (insn, operands)
2584 static int loopend_lab;
2588 rtx inside = PATTERN (insn);
2589 rtx shift = operands[3];
2590 enum machine_mode mode = GET_MODE (shift);
2591 enum rtx_code code = GET_CODE (shift);
2592 enum shift_type shift_type;
2593 enum shift_mode shift_mode;
2600 shift_mode = QIshift;
2603 shift_mode = HIshift;
2606 shift_mode = SIshift;
2615 shift_type = SHIFT_ASHIFTRT;
2618 shift_type = SHIFT_LSHIFTRT;
2621 shift_type = SHIFT_ASHIFT;
2627 if (GET_CODE (operands[2]) != CONST_INT)
2629 /* Indexing by reg, so have to loop and test at top */
2630 output_asm_insn ("mov.b %X2,%X4", operands);
2631 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2633 /* Get the assembler code to do one shift. */
2634 get_shift_alg (cpu_type, shift_type, mode, 1, &assembler,
2635 &assembler2, &cc_valid);
2639 int n = INTVAL (operands[2]);
2642 /* If the count is negative, make it 0. */
2645 /* If the count is too big, truncate it.
2646 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2647 do the intuitive thing. */
2648 else if (n > GET_MODE_BITSIZE (mode))
2649 n = GET_MODE_BITSIZE (mode);
2651 alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler,
2652 &assembler2, &cc_valid);
2657 /* Emit two bit shifts first. */
2658 while (n > 1 && assembler2 != NULL)
2660 output_asm_insn (assembler2, operands);
2664 /* Now emit one bit shifts for any residual. */
2667 output_asm_insn (assembler, operands);
2671 /* Keep track of CC. */
2674 cc_status.value1 = operands[0];
2675 cc_status.flags |= cc_valid;
2681 int m = GET_MODE_BITSIZE (mode) - n;
2682 int mask = (shift_type == SHIFT_ASHIFT
2683 ? ((1 << GET_MODE_BITSIZE (mode) - n) - 1) << n
2684 : (1 << GET_MODE_BITSIZE (mode) - n) - 1);
2686 /* Not all possibilities of rotate are supported. They shouldn't
2687 be generated, but let's watch for 'em. */
2691 /* Emit two bit rotates first. */
2692 while (m > 1 && assembler2 != NULL)
2694 output_asm_insn (assembler2, operands);
2698 /* Now single bit rotates for any residual. */
2701 output_asm_insn (assembler, operands);
2705 /* Now mask off the high bits. */
2711 sprintf (insn_buf, "and #%d,%%X0",
2713 cc_status.value1 = operands[0];
2714 cc_status.flags |= CC_NO_CARRY;
2717 sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0",
2718 mask & 255, mask >> 8, n);
2726 sprintf (insn_buf, "and.%c #%d,%%%c0",
2727 "bwl"[shift_mode], mask,
2728 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2729 cc_status.value1 = operands[0];
2730 cc_status.flags |= CC_NO_CARRY;
2732 output_asm_insn (insn_buf, operands);
2736 output_asm_insn (assembler, operands);
2740 /* A loop to shift by a "large" constant value.
2741 If we have shift-by-2 insns, use them. */
2742 if (assembler2 != NULL)
2744 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2745 names_big[REGNO (operands[4])]);
2746 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2747 output_asm_insn (assembler2, operands);
2748 output_asm_insn ("add #0xff,%X4", operands);
2749 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2751 output_asm_insn (assembler, operands);
2756 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2757 names_big[REGNO (operands[4])]);
2758 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2759 output_asm_insn (assembler, operands);
2760 output_asm_insn ("add #0xff,%X4", operands);
2761 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2766 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2767 output_asm_insn (assembler, operands);
2768 output_asm_insn ("add #0xff,%X4", operands);
2769 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2770 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2775 /* Fix the operands of a gen_xxx so that it could become a bit
2779 fix_bit_operand (operands, what, type)
2784 /* The bit_operand predicate accepts any memory during RTL generation, but
2785 only 'U' memory afterwards, so if this is a MEM operand, we must force
2786 it to be valid for 'U' by reloading the address. */
2788 if (GET_CODE (operands[2]) == CONST_INT)
2790 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
2792 /* Ok to have a memory dest. */
2793 if (GET_CODE (operands[0]) == MEM && !EXTRA_CONSTRAINT (operands[0], 'U'))
2795 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
2796 copy_to_mode_reg (Pmode,
2797 XEXP (operands[0], 0)));
2798 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[0]);
2799 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2803 if (GET_CODE (operands[1]) == MEM && !EXTRA_CONSTRAINT (operands[1], 'U'))
2805 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
2806 copy_to_mode_reg (Pmode,
2807 XEXP (operands[1], 0)));
2808 RTX_UNCHANGING_P (mem) = RTX_UNCHANGING_P (operands[1]);
2809 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2816 /* Dest and src op must be register. */
2818 operands[1] = force_reg (QImode, operands[1]);
2820 rtx res = gen_reg_rtx (QImode);
2821 emit_insn (gen_rtx_SET (VOIDmode, res,
2822 gen_rtx (type, QImode, operands[1], operands[2])));
2823 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
2828 /* Return nonzero if FUNC is an interrupt function as specified
2829 by the "interrupt" attribute. */
2832 h8300_interrupt_function_p (func)
2837 if (TREE_CODE (func) != FUNCTION_DECL)
2840 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
2841 return a != NULL_TREE;
2844 /* Return nonzero if FUNC is an OS_Task function as specified
2845 by the "OS_Task" attribute. */
2848 h8300_os_task_function_p (func)
2853 if (TREE_CODE (func) != FUNCTION_DECL)
2856 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
2857 return a != NULL_TREE;
2860 /* Return nonzero if FUNC is a monitor function as specified
2861 by the "monitor" attribute. */
2864 h8300_monitor_function_p (func)
2869 if (TREE_CODE (func) != FUNCTION_DECL)
2872 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
2873 return a != NULL_TREE;
2876 /* Return nonzero if FUNC is a function that should be called
2877 through the function vector. */
2880 h8300_funcvec_function_p (func)
2885 if (TREE_CODE (func) != FUNCTION_DECL)
2888 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
2889 return a != NULL_TREE;
2892 /* Return nonzero if DECL is a variable that's in the eight bit
2896 h8300_eightbit_data_p (decl)
2901 if (TREE_CODE (decl) != VAR_DECL)
2904 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
2905 return a != NULL_TREE;
2908 /* Return nonzero if DECL is a variable that's in the tiny
2912 h8300_tiny_data_p (decl)
2917 if (TREE_CODE (decl) != VAR_DECL)
2920 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
2921 return a != NULL_TREE;
2924 /* Return nonzero if ATTR is a valid attribute for DECL.
2925 ATTRIBUTES are any existing attributes and ARGS are the arguments
2928 Supported attributes:
2930 interrupt_handler: output a prologue and epilogue suitable for an
2933 function_vector: This function should be called through the
2936 eightbit_data: This variable lives in the 8-bit data area and can
2937 be referenced with 8-bit absolute memory addresses.
2939 tiny_data: This variable lives in the tiny data area and can be
2940 referenced with 16-bit absolute memory references. */
2943 h8300_valid_machine_decl_attribute (decl, attributes, attr, args)
2949 if (args != NULL_TREE)
2952 if (is_attribute_p ("interrupt_handler", attr)
2953 || is_attribute_p ("OS_Task", attr)
2954 || is_attribute_p ("monitor", attr)
2955 || is_attribute_p ("function_vector", attr))
2956 return TREE_CODE (decl) == FUNCTION_DECL;
2958 if (is_attribute_p ("eightbit_data", attr)
2959 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
2961 if (DECL_INITIAL (decl) == NULL_TREE)
2963 warning ("Only initialized variables can be placed into the 8-bit area.");
2966 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
2970 if (is_attribute_p ("tiny_data", attr)
2971 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
2973 if (DECL_INITIAL (decl) == NULL_TREE)
2975 warning ("Only initialized variables can be placed into the 8-bit area.");
2978 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
2985 extern struct obstack *saveable_obstack;
2987 h8300_encode_label (decl)
2990 char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2991 int len = strlen (str);
2994 newstr = obstack_alloc (saveable_obstack, len + 2);
2996 strcpy (newstr + 1, str);
2998 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3002 output_simode_bld (bild, log2, operands)
3007 /* Clear the destination register. */
3008 if (TARGET_H8300H || TARGET_H8300S)
3009 output_asm_insn ("sub.l\t%S0,%S0", operands);
3011 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3013 /* Get the bit number we want to load. */
3015 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3017 /* Now output the bit load or bit inverse load, and store it in
3020 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3022 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3028 /* Given INSN and its current length LENGTH, return the adjustment
3029 (in bytes) to correctly compute INSN's length.
3031 We use this to get the lengths of various memory references correct. */
3033 h8300_adjust_insn_length (insn, length)
3039 /* We must filter these ou before calling get_attr_adjust_length. */
3040 if (GET_CODE (PATTERN (insn)) == USE
3041 || GET_CODE (PATTERN (insn)) == CLOBBER
3042 || GET_CODE (PATTERN (insn)) == SEQUENCE
3043 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3044 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3047 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3050 pat = PATTERN (insn);
3052 /* Adjust length for reg->mem and mem->reg copies. */
3053 if (GET_CODE (pat) == SET
3054 && (GET_CODE (SET_SRC (pat)) == MEM
3055 || GET_CODE (SET_DEST (pat)) == MEM))
3057 /* This insn might need a length adjustment. */
3060 if (GET_CODE (SET_SRC (pat)) == MEM)
3061 addr = XEXP (SET_SRC (pat), 0);
3063 addr = XEXP (SET_DEST (pat), 0);
3065 /* On the H8/300, only one adjustment is necessary; if the
3066 address mode is register indirect, then this insn is two
3067 bytes shorter than indicated in the machine description. */
3068 if (TARGET_H8300 && GET_CODE (addr) == REG)
3071 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3072 indicated in the machine description. */
3073 if ((TARGET_H8300H || TARGET_H8300S)
3074 && GET_CODE (addr) == REG)
3077 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3078 bytes shorter than indicated in the machine description. */
3079 if ((TARGET_H8300H || TARGET_H8300S)
3080 && GET_CODE (addr) == PLUS
3081 && GET_CODE (XEXP (addr, 0)) == REG
3082 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3083 && INTVAL (XEXP (addr, 1)) > -32768
3084 && INTVAL (XEXP (addr, 1)) < 32767)
3087 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3088 more general abs:24. */
3089 if ((TARGET_H8300H || TARGET_H8300S)
3090 && GET_CODE (addr) == SYMBOL_REF
3091 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3095 /* Loading some constants needs adjustment. */
3096 if (GET_CODE (pat) == SET
3097 && GET_CODE (SET_SRC (pat)) == CONST_INT
3098 && GET_MODE (SET_DEST (pat)) == SImode
3099 && INTVAL (SET_SRC (pat)) != 0)
3102 && ((INTVAL (SET_SRC (pat)) & 0xffff) == 0
3103 || ((INTVAL (SET_SRC (pat)) >> 16) & 0xffff) == 0))
3106 if (TARGET_H8300H || TARGET_H8300S)
3108 int val = INTVAL (SET_SRC (pat));
3110 if (val == (val & 0xff)
3111 || val == (val & 0xff00))
3114 if (val == -4 || val == -2 || val == -1)
3119 /* Shifts need various adjustments. */
3120 if (GET_CODE (pat) == PARALLEL
3121 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3122 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3123 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3124 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3126 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3127 enum machine_mode mode = GET_MODE (src);
3130 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3133 shift = INTVAL (XEXP (src, 1));
3134 /* According to ANSI, negative shift is undefined. It is
3135 considered to be zero in this case (see function
3136 emit_a_shift above). */
3140 /* QImode shifts by small constants take one insn
3141 per shift. So the adjustment is 20 (md length) -
3143 if (mode == QImode && shift <= 4)
3144 return -(20 - shift * 2);
3146 /* Similarly for HImode and SImode shifts by
3147 small constants on the H8/300H and H8/300S. */
3148 if ((TARGET_H8300H || TARGET_H8300S)
3149 && (mode == HImode || mode == SImode) && shift <= 4)
3150 return -(20 - shift * 2);
3152 /* HImode shifts by small constants for the H8/300. */
3153 if (mode == HImode && shift <= 4)
3154 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3156 /* SImode shifts by small constants for the H8/300. */
3157 if (mode == SImode && shift <= 2)
3158 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3160 /* XXX ??? Could check for more shift/rotate cases here. */