1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Forward declarations. */
50 static const char *byte_reg (rtx, int);
51 static int h8300_interrupt_function_p (tree);
52 static int h8300_saveall_function_p (tree);
53 static int h8300_monitor_function_p (tree);
54 static int h8300_os_task_function_p (tree);
55 static void h8300_emit_stack_adjustment (int, unsigned int);
56 static int round_frame_size (int);
57 static unsigned int compute_saved_regs (void);
58 static void push (int);
59 static void pop (int);
60 static const char *cond_string (enum rtx_code);
61 static unsigned int h8300_asm_insn_count (const char *);
62 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
65 #ifndef OBJECT_FORMAT_ELF
66 static void h8300_asm_named_section (const char *, unsigned int);
68 static int h8300_and_costs (rtx);
69 static int h8300_shift_costs (rtx);
71 /* CPU_TYPE, says what cpu we're compiling for. */
74 /* True if a #pragma interrupt has been seen for the current function. */
75 static int pragma_interrupt;
77 /* True if a #pragma saveall has been seen for the current function. */
78 static int pragma_saveall;
80 static const char *const names_big[] =
81 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
83 static const char *const names_extended[] =
84 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
86 static const char *const names_upper_extended[] =
87 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
89 /* Points to one of the above. */
90 /* ??? The above could be put in an array indexed by CPU_TYPE. */
91 const char * const *h8_reg_names;
93 /* Various operations needed by the following, indexed by CPU_TYPE. */
95 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
97 /* Machine-specific symbol_ref flags. */
98 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
102 /* See below where shifts are handled for explanation of this enum. */
112 /* Symbols of the various shifts which can be used as indices. */
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
119 /* Macros to keep the shift algorithm tables small. */
120 #define INL SHIFT_INLINE
121 #define ROT SHIFT_ROT_AND
122 #define LOP SHIFT_LOOP
123 #define SPC SHIFT_SPECIAL
125 /* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
128 by, in the order of indices, machine, shift type, and shift count. */
130 static enum shift_alg shift_alg_qi[3][3][8] = {
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
154 static enum shift_alg shift_alg_hi[3][3][16] = {
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
190 static enum shift_alg shift_alg_si[3][3][32] = {
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
262 /* Initialize various cpu specific globals at start up. */
265 h8300_init_once (void)
267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
278 /* For this we treat the H8/300H and H8S the same. */
279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
286 if (!TARGET_H8300S && TARGET_MAC)
288 error ("-ms2600 is used without -ms");
289 target_flags |= MASK_H8300S;
292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
294 error ("-mn is used without -mh or -ms");
295 target_flags ^= MASK_NORMAL_MODE;
298 /* Some of the shifts are optimized for speed by default.
299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
300 If optimizing for size, change shift_alg for those shift to
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
334 byte_reg (rtx x, int b)
336 static const char *const names_small[] = {
337 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
338 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
341 return names_small[REGNO (x) * 2 + b];
344 /* REGNO must be saved/restored across calls if this macro is true. */
346 #define WORD_REG_USED(regno) \
348 /* No need to save registers if this function will not return. */ \
349 && ! TREE_THIS_VOLATILE (current_function_decl) \
350 && (h8300_saveall_function_p (current_function_decl) \
351 /* Save any call saved register that was used. */ \
352 || (regs_ever_live[regno] && !call_used_regs[regno]) \
353 /* Save the frame pointer if it was used. */ \
354 || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
355 /* Save any register used in an interrupt handler. */ \
356 || (h8300_current_function_interrupt_function_p () \
357 && regs_ever_live[regno]) \
358 /* Save call clobbered registers in non-leaf interrupt \
360 || (h8300_current_function_interrupt_function_p () \
361 && call_used_regs[regno] \
362 && !current_function_is_leaf)))
364 /* Output assembly language to FILE for the operation OP with operand size
365 SIZE to adjust the stack pointer. */
368 h8300_emit_stack_adjustment (int sign, unsigned int size)
370 /* H8/300 cannot add/subtract a large constant with a single
371 instruction. If a temporary register is available, load the
372 constant to it and then do the addition. */
375 && !h8300_current_function_interrupt_function_p ()
376 && !(current_function_needs_context && sign < 0))
379 rtx r3 = gen_rtx_REG (Pmode, 3);
380 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
381 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
382 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
386 /* The stack adjustment made here is further optimized by the
387 splitter. In case of H8/300, the splitter always splits the
388 addition emitted here to make the adjustment
390 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
391 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
395 /* Round up frame size SIZE. */
398 round_frame_size (int size)
400 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
401 & -STACK_BOUNDARY / BITS_PER_UNIT);
404 /* Compute which registers to push/pop.
405 Return a bit vector of registers. */
408 compute_saved_regs (void)
410 unsigned int saved_regs = 0;
413 /* Construct a bit vector of registers to be pushed/popped. */
414 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
416 if (WORD_REG_USED (regno))
417 saved_regs |= 1 << regno;
420 /* Don't push/pop the frame pointer as it is treated separately. */
421 if (frame_pointer_needed)
422 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
427 /* Emit an insn to push register RN. */
432 rtx reg = gen_rtx_REG (word_mode, rn);
436 x = gen_push_h8300 (reg);
437 else if (!TARGET_NORMAL_MODE)
438 x = gen_push_h8300hs_advanced (reg);
440 x = gen_push_h8300hs_normal (reg);
442 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
445 /* Emit an insn to pop register RN. */
450 rtx reg = gen_rtx_REG (word_mode, rn);
454 x = gen_pop_h8300 (reg);
455 else if (!TARGET_NORMAL_MODE)
456 x = gen_pop_h8300hs_advanced (reg);
458 x = gen_pop_h8300hs_normal (reg);
460 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
463 /* This is what the stack looks like after the prolog of
464 a function with a frame has been set up:
470 <saved registers> <- sp
472 This is what the stack looks like after the prolog of
473 a function which doesn't have a frame:
478 <saved registers> <- sp
481 /* Generate RTL code for the function prologue. */
484 h8300_expand_prologue (void)
490 /* If the current function has the OS_Task attribute set, then
491 we have a naked prologue. */
492 if (h8300_os_task_function_p (current_function_decl))
495 if (h8300_monitor_function_p (current_function_decl))
496 /* My understanding of monitor functions is they act just like
497 interrupt functions, except the prologue must mask
499 emit_insn (gen_monitor_prologue ());
501 if (frame_pointer_needed)
504 push (HARD_FRAME_POINTER_REGNUM);
505 emit_insn (gen_rtx_SET (Pmode, hard_frame_pointer_rtx,
509 /* Push the rest of the registers in ascending order. */
510 saved_regs = compute_saved_regs ();
511 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
514 if (saved_regs & (1 << regno))
518 /* See how many registers we can push at the same time. */
519 if ((regno == 0 || regno == 4)
520 && ((saved_regs >> regno) & 0x0f) == 0x0f)
523 else if ((regno == 0 || regno == 4)
524 && ((saved_regs >> regno) & 0x07) == 0x07)
527 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
528 && ((saved_regs >> regno) & 0x03) == 0x03)
538 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
539 gen_rtx_REG (SImode, regno + 1)));
542 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
543 gen_rtx_REG (SImode, regno + 1),
544 gen_rtx_REG (SImode, regno + 2)));
547 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
548 gen_rtx_REG (SImode, regno + 1),
549 gen_rtx_REG (SImode, regno + 2),
550 gen_rtx_REG (SImode, regno + 3)));
558 /* Leave room for locals. */
559 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
563 h8300_can_use_return_insn_p (void)
565 return (reload_completed
566 && !frame_pointer_needed
567 && get_frame_size () == 0
568 && compute_saved_regs () == 0);
571 /* Generate RTL code for the function epilogue. */
574 h8300_expand_epilogue (void)
580 if (h8300_os_task_function_p (current_function_decl))
581 /* OS_Task epilogues are nearly naked -- they just have an
585 /* Deallocate locals. */
586 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
588 /* Pop the saved registers in descending order. */
589 saved_regs = compute_saved_regs ();
590 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
593 if (saved_regs & (1 << regno))
597 /* See how many registers we can pop at the same time. */
598 if ((regno == 7 || regno == 3)
599 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
602 else if ((regno == 6 || regno == 2)
603 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
606 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
607 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
617 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
618 gen_rtx_REG (SImode, regno)));
621 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
622 gen_rtx_REG (SImode, regno - 1),
623 gen_rtx_REG (SImode, regno)));
626 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
627 gen_rtx_REG (SImode, regno - 2),
628 gen_rtx_REG (SImode, regno - 1),
629 gen_rtx_REG (SImode, regno)));
637 /* Pop frame pointer if we had one. */
638 if (frame_pointer_needed)
639 pop (HARD_FRAME_POINTER_REGNUM);
642 /* Return nonzero if the current function is an interrupt
646 h8300_current_function_interrupt_function_p (void)
648 return (h8300_interrupt_function_p (current_function_decl)
649 || h8300_monitor_function_p (current_function_decl));
652 /* Output assembly code for the start of the file. */
655 h8300_file_start (void)
657 default_file_start ();
660 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
661 else if (TARGET_H8300S)
662 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
665 /* Output assembly language code for the end of file. */
668 h8300_file_end (void)
670 fputs ("\t.end\n", asm_out_file);
673 /* Return true if OP is a valid source operand for an integer move
677 general_operand_src (rtx op, enum machine_mode mode)
679 if (GET_MODE (op) == mode
680 && GET_CODE (op) == MEM
681 && GET_CODE (XEXP (op, 0)) == POST_INC)
683 return general_operand (op, mode);
686 /* Return true if OP is a valid destination operand for an integer move
690 general_operand_dst (rtx op, enum machine_mode mode)
692 if (GET_MODE (op) == mode
693 && GET_CODE (op) == MEM
694 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
696 return general_operand (op, mode);
699 /* Return true if OP is a constant that contains only one 1 in its
700 binary representation. */
703 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
705 if (GET_CODE (operand) == CONST_INT)
707 /* We really need to do this masking because 0x80 in QImode is
708 represented as -128 for example. */
709 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
716 /* Return true if OP is a constant that contains only one 0 in its
717 binary representation. */
720 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
722 if (GET_CODE (operand) == CONST_INT)
724 /* We really need to do this masking because 0x80 in QImode is
725 represented as -128 for example. */
726 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
733 /* Return true if OP is a valid call operand. */
736 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
738 if (GET_CODE (op) == MEM)
740 rtx inside = XEXP (op, 0);
741 if (register_operand (inside, Pmode))
743 if (CONSTANT_ADDRESS_P (inside))
749 /* Return 1 if an addition/subtraction of a constant integer can be
750 transformed into two consecutive adds/subs that are faster than the
751 straightforward way. Otherwise, return 0. */
754 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
756 if (GET_CODE (op) == CONST_INT)
758 HOST_WIDE_INT value = INTVAL (op);
760 /* Force VALUE to be positive so that we do not have to consider
761 the negative case. */
764 if (TARGET_H8300H || TARGET_H8300S)
766 /* A constant addition/subtraction takes 2 states in QImode,
767 4 states in HImode, and 6 states in SImode. Thus, the
768 only case we can win is when SImode is used, in which
769 case, two adds/subs are used, taking 4 states. */
779 /* We do not profit directly by splitting addition or
780 subtraction of 3 and 4. However, since these are
781 implemented as a sequence of adds or subs, they do not
782 clobber (cc0) unlike a sequence of add.b and add.x. */
793 /* Split an add of a small constant into two adds/subs insns.
795 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
796 instead of adds/subs. */
799 split_adds_subs (enum machine_mode mode, rtx *operands)
801 HOST_WIDE_INT val = INTVAL (operands[1]);
802 rtx reg = operands[0];
803 HOST_WIDE_INT sign = 1;
804 HOST_WIDE_INT amount;
805 rtx (*gen_add) (rtx, rtx, rtx);
807 /* Force VAL to be positive so that we do not have to consider the
818 gen_add = gen_addhi3;
822 gen_add = gen_addsi3;
829 /* Try different amounts in descending order. */
830 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
834 for (; val >= amount; val -= amount)
835 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
841 /* Return true if OP is a valid call operand, and OP represents
842 an operand for a small call (4 bytes instead of 6 bytes). */
845 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
847 if (GET_CODE (op) == MEM)
849 rtx inside = XEXP (op, 0);
851 /* Register indirect is a small call. */
852 if (register_operand (inside, Pmode))
855 /* A call through the function vector is a small call too. */
856 if (GET_CODE (inside) == SYMBOL_REF
857 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
860 /* Otherwise it's a large call. */
864 /* Return true if OP is a valid jump operand. */
867 jump_address_operand (rtx op, enum machine_mode mode)
869 if (GET_CODE (op) == REG)
870 return mode == Pmode;
872 if (GET_CODE (op) == MEM)
874 rtx inside = XEXP (op, 0);
875 if (register_operand (inside, Pmode))
877 if (CONSTANT_ADDRESS_P (inside))
883 /* Recognize valid operands for bit-field instructions. */
885 extern int rtx_equal_function_value_matters;
888 bit_operand (rtx op, enum machine_mode mode)
890 /* We can accept any general operand, except that MEM operands must
891 be limited to those that use addresses valid for the 'U' constraint. */
892 if (!general_operand (op, mode))
895 /* Accept any mem during RTL generation. Otherwise, the code that does
896 insv and extzv will think that we can not handle memory. However,
897 to avoid reload problems, we only accept 'U' MEM operands after RTL
898 generation. This means that any named pattern which uses this predicate
899 must force its operands to match 'U' before emitting RTL. */
901 if (GET_CODE (op) == REG)
903 if (GET_CODE (op) == SUBREG)
905 return (GET_CODE (op) == MEM
906 && EXTRA_CONSTRAINT (op, 'U'));
910 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
912 return (GET_CODE (op) == MEM
913 && EXTRA_CONSTRAINT (op, 'U'));
916 /* Handle machine specific pragmas for compatibility with existing
917 compilers for the H8/300.
919 pragma saveall generates prologue/epilogue code which saves and
920 restores all the registers on function entry.
922 pragma interrupt saves and restores all registers, and exits with
923 an rte instruction rather than an rts. A pointer to a function
924 with this attribute may be safely used in an interrupt vector. */
927 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
929 pragma_interrupt = 1;
933 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
938 /* If the next function argument with MODE and TYPE is to be passed in
939 a register, return a reg RTX for the hard register in which to pass
940 the argument. CUM represents the state after the last argument.
941 If the argument is to be pushed, NULL_RTX is returned. */
944 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
945 tree type, int named)
947 static const char *const hand_list[] = {
966 rtx result = NULL_RTX;
970 /* Never pass unnamed arguments in registers. */
974 /* Pass 3 regs worth of data in regs when user asked on the command line. */
975 if (TARGET_QUICKCALL)
978 /* If calling hand written assembler, use 4 regs of args. */
981 const char * const *p;
983 fname = XSTR (cum->libcall, 0);
985 /* See if this libcall is one of the hand coded ones. */
986 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
998 size = int_size_in_bytes (type);
1000 size = GET_MODE_SIZE (mode);
1002 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1003 && cum->nbytes / UNITS_PER_WORD <= 3)
1004 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1011 h8300_and_costs (rtx x)
1015 if (GET_MODE (x) == QImode)
1018 if (GET_MODE (x) != HImode
1019 && GET_MODE (x) != SImode)
1024 operands[2] = XEXP (x, 1);
1026 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1030 h8300_shift_costs (rtx x)
1034 if (GET_MODE (x) != QImode
1035 && GET_MODE (x) != HImode
1036 && GET_MODE (x) != SImode)
1041 operands[2] = XEXP (x, 1);
1043 return compute_a_shift_length (NULL, operands) / 2;
1047 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1053 HOST_WIDE_INT n = INTVAL (x);
1055 if (-4 <= n || n <= 4)
1066 *total = 0 + (outer_code == SET);
1070 if (TARGET_H8300H || TARGET_H8300S)
1071 *total = 0 + (outer_code == SET);
1092 *total = COSTS_N_INSNS (h8300_and_costs (x));
1095 /* We say that MOD and DIV are so expensive because otherwise we'll
1096 generate some really horrible code for division of a power of two. */
1109 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1114 if (GET_MODE (x) == HImode)
1126 /* Documentation for the machine specific operand escapes:
1128 'E' like s but negative.
1129 'F' like t but negative.
1130 'G' constant just the negative
1131 'R' print operand as a byte:8 address if appropriate, else fall back to
1133 'S' print operand as a long word
1134 'T' print operand as a word
1135 'V' find the set bit, and print its number.
1136 'W' find the clear bit, and print its number.
1137 'X' print operand as a byte
1138 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1139 If this operand isn't a register, fall back to 'R' handling.
1141 'c' print the opcode corresponding to rtl
1142 'e' first word of 32 bit value - if reg, then least reg. if mem
1143 then least. if const then most sig word
1144 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1145 then +2. if const then least sig word
1146 'j' print operand as condition code.
1147 'k' print operand as reverse condition code.
1148 's' print as low byte of 16 bit value
1149 't' print as high byte of 16 bit value
1150 'w' print as low byte of 32 bit value
1151 'x' print as 2nd byte of 32 bit value
1152 'y' print as 3rd byte of 32 bit value
1153 'z' print as msb of 32 bit value
1156 /* Return assembly language string which identifies a comparison type. */
1159 cond_string (enum rtx_code code)
1188 /* Print operand X using operand code CODE to assembly language output file
1192 print_operand (FILE *file, rtx x, int code)
1194 /* This is used for communication between codes V,W,Z and Y. */
1200 switch (GET_CODE (x))
1203 fprintf (file, "%sl", names_big[REGNO (x)]);
1206 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1213 switch (GET_CODE (x))
1216 fprintf (file, "%sh", names_big[REGNO (x)]);
1219 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1226 if (GET_CODE (x) != CONST_INT)
1228 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1231 if (GET_CODE (x) == REG)
1232 fprintf (file, "%s", names_extended[REGNO (x)]);
1237 if (GET_CODE (x) == REG)
1238 fprintf (file, "%s", names_big[REGNO (x)]);
1243 bitint = exact_log2 (INTVAL (x) & 0xff);
1246 fprintf (file, "#%d", bitint);
1249 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1252 fprintf (file, "#%d", bitint);
1256 if (GET_CODE (x) == REG)
1257 fprintf (file, "%s", byte_reg (x, 0));
1264 if (GET_CODE (x) == REG)
1265 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1267 print_operand (file, x, 'R');
1271 bitint = INTVAL (x);
1272 fprintf (file, "#%d", bitint & 7);
1275 switch (GET_CODE (x))
1278 fprintf (file, "or");
1281 fprintf (file, "xor");
1284 fprintf (file, "and");
1291 switch (GET_CODE (x))
1295 fprintf (file, "%s", names_big[REGNO (x)]);
1297 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1300 print_operand (file, x, 0);
1303 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1309 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1310 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1311 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1320 switch (GET_CODE (x))
1324 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1326 fprintf (file, "%s", names_big[REGNO (x)]);
1329 x = adjust_address (x, HImode, 2);
1330 print_operand (file, x, 0);
1333 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1339 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1340 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1341 fprintf (file, "#%ld", (val & 0xffff));
1349 fputs (cond_string (GET_CODE (x)), file);
1352 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1355 if (GET_CODE (x) == CONST_INT)
1356 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1358 fprintf (file, "%s", byte_reg (x, 0));
1361 if (GET_CODE (x) == CONST_INT)
1362 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1364 fprintf (file, "%s", byte_reg (x, 1));
1367 if (GET_CODE (x) == CONST_INT)
1368 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1370 fprintf (file, "%s",
1371 byte_reg (x, TARGET_H8300 ? 2 : 0));
1374 if (GET_CODE (x) == CONST_INT)
1375 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1377 fprintf (file, "%s",
1378 byte_reg (x, TARGET_H8300 ? 3 : 1));
1381 if (GET_CODE (x) == CONST_INT)
1382 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1384 fprintf (file, "%s", byte_reg (x, 0));
1387 if (GET_CODE (x) == CONST_INT)
1388 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1390 fprintf (file, "%s", byte_reg (x, 1));
1395 switch (GET_CODE (x))
1398 switch (GET_MODE (x))
1401 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1402 fprintf (file, "%s", byte_reg (x, 0));
1403 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1404 fprintf (file, "%s", names_big[REGNO (x)]);
1408 fprintf (file, "%s", names_big[REGNO (x)]);
1412 fprintf (file, "%s", names_extended[REGNO (x)]);
1421 rtx addr = XEXP (x, 0);
1423 fprintf (file, "@");
1424 output_address (addr);
1426 /* We fall back from smaller addressing to larger
1427 addressing in various ways depending on CODE. */
1431 /* Used for mov.b and bit operations. */
1432 if (h8300_eightbit_constant_address_p (addr))
1434 fprintf (file, ":8");
1438 /* Fall through. We should not get here if we are
1439 processing bit operations on H8/300 or H8/300H
1440 because 'U' constraint does not allow bit
1441 operations on the tiny area on these machines. */
1445 /* Used for mov.w and mov.l. */
1446 if (h8300_tiny_constant_address_p (addr))
1447 fprintf (file, ":16");
1459 fprintf (file, "#");
1460 print_operand_address (file, x);
1466 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1467 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1468 fprintf (file, "#%ld", val);
1477 /* Output assembly language output for the address ADDR to FILE. */
1480 print_operand_address (FILE *file, rtx addr)
1482 switch (GET_CODE (addr))
1485 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1489 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1493 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1497 fprintf (file, "(");
1498 if (GET_CODE (XEXP (addr, 0)) == REG)
1501 print_operand_address (file, XEXP (addr, 1));
1502 fprintf (file, ",");
1503 print_operand_address (file, XEXP (addr, 0));
1508 print_operand_address (file, XEXP (addr, 0));
1509 fprintf (file, "+");
1510 print_operand_address (file, XEXP (addr, 1));
1512 fprintf (file, ")");
1517 /* Since the H8/300 only has 16 bit pointers, negative values are also
1518 those >= 32768. This happens for example with pointer minus a
1519 constant. We don't want to turn (char *p - 2) into
1520 (char *p + 65534) because loop unrolling can build upon this
1521 (IE: char *p + 131068). */
1522 int n = INTVAL (addr);
1524 n = (int) (short) n;
1525 fprintf (file, "%d", n);
1530 output_addr_const (file, addr);
1535 /* Output all insn addresses and their sizes into the assembly language
1536 output file. This is helpful for debugging whether the length attributes
1537 in the md file are correct. This is not meant to be a user selectable
1541 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1542 int num_operands ATTRIBUTE_UNUSED)
1544 /* This holds the last insn address. */
1545 static int last_insn_address = 0;
1547 const int uid = INSN_UID (insn);
1549 if (TARGET_ADDRESSES)
1551 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1552 INSN_ADDRESSES (uid) - last_insn_address);
1553 last_insn_address = INSN_ADDRESSES (uid);
1557 /* Prepare for an SI sized move. */
1560 h8300_expand_movsi (rtx operands[])
1562 rtx src = operands[1];
1563 rtx dst = operands[0];
1564 if (!reload_in_progress && !reload_completed)
1566 if (!register_operand (dst, GET_MODE (dst)))
1568 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1569 emit_move_insn (tmp, src);
1576 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1577 Define the offset between two registers, one to be eliminated, and
1578 the other its replacement, at the start of a routine. */
1581 h8300_initial_elimination_offset (int from, int to)
1583 /* The number of bytes that the return address takes on the stack. */
1584 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1586 /* The number of bytes that the saved frame pointer takes on the stack. */
1587 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1589 /* The number of bytes that the saved registers, excluding the frame
1590 pointer, take on the stack. */
1591 int saved_regs_size = 0;
1593 /* The number of bytes that the locals takes on the stack. */
1594 int frame_size = round_frame_size (get_frame_size ());
1598 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1599 if (WORD_REG_USED (regno))
1600 saved_regs_size += UNITS_PER_WORD;
1602 /* Adjust saved_regs_size because the above loop took the frame
1603 pointer int account. */
1604 saved_regs_size -= fp_size;
1606 if (to == HARD_FRAME_POINTER_REGNUM)
1610 case ARG_POINTER_REGNUM:
1611 return pc_size + fp_size;
1612 case RETURN_ADDRESS_POINTER_REGNUM:
1614 case FRAME_POINTER_REGNUM:
1615 return -saved_regs_size;
1620 else if (to == STACK_POINTER_REGNUM)
1624 case ARG_POINTER_REGNUM:
1625 return pc_size + saved_regs_size + frame_size;
1626 case RETURN_ADDRESS_POINTER_REGNUM:
1627 return saved_regs_size + frame_size;
1628 case FRAME_POINTER_REGNUM:
1639 h8300_return_addr_rtx (int count, rtx frame)
1644 ret = gen_rtx_MEM (Pmode,
1645 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1646 else if (flag_omit_frame_pointer)
1649 ret = gen_rtx_MEM (Pmode,
1650 memory_address (Pmode,
1651 plus_constant (frame, UNITS_PER_WORD)));
1652 set_mem_alias_set (ret, get_frame_alias_set ());
1656 /* Update the condition code from the insn. */
1659 notice_update_cc (rtx body, rtx insn)
1663 switch (get_attr_cc (insn))
1666 /* Insn does not affect CC at all. */
1670 /* Insn does not change CC, but the 0'th operand has been changed. */
1671 if (cc_status.value1 != 0
1672 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1673 cc_status.value1 = 0;
1674 if (cc_status.value2 != 0
1675 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1676 cc_status.value2 = 0;
1680 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1681 The V flag is unusable. The C flag may or may not be known but
1682 that's ok because alter_cond will change tests to use EQ/NE. */
1684 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1685 set = single_set (insn);
1686 cc_status.value1 = SET_SRC (set);
1687 if (SET_DEST (set) != cc0_rtx)
1688 cc_status.value2 = SET_DEST (set);
1692 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1693 The C flag may or may not be known but that's ok because
1694 alter_cond will change tests to use EQ/NE. */
1696 cc_status.flags |= CC_NO_CARRY;
1697 set = single_set (insn);
1698 cc_status.value1 = SET_SRC (set);
1699 if (SET_DEST (set) != cc0_rtx)
1701 /* If the destination is STRICT_LOW_PART, strip off
1703 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1704 cc_status.value2 = XEXP (SET_DEST (set), 0);
1706 cc_status.value2 = SET_DEST (set);
1711 /* The insn is a compare instruction. */
1713 cc_status.value1 = SET_SRC (body);
1717 /* Insn doesn't leave CC in a usable state. */
1723 /* Return nonzero if X is a stack pointer. */
1726 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1728 return x == stack_pointer_rtx;
1731 /* Return nonzero if X is a constant whose absolute value is greater
1735 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1737 return (GET_CODE (x) == CONST_INT
1738 && abs (INTVAL (x)) > 2);
1741 /* Return nonzero if X is a constant whose absolute value is no
1745 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1747 return (GET_CODE (x) == CONST_INT
1748 && abs (INTVAL (x)) >= 8);
1751 /* Return nonzero if X is a constant expressible in QImode. */
1754 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1756 return (GET_CODE (x) == CONST_INT
1757 && (INTVAL (x) & 0xff) == INTVAL (x));
1760 /* Return nonzero if X is a constant expressible in HImode. */
1763 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1765 return (GET_CODE (x) == CONST_INT
1766 && (INTVAL (x) & 0xffff) == INTVAL (x));
1769 /* Return nonzero if X is a constant suitable for inc/dec. */
1772 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1774 return (GET_CODE (x) == CONST_INT
1775 && (CONST_OK_FOR_M (INTVAL (x))
1776 || CONST_OK_FOR_O (INTVAL (x))));
1779 /* Return nonzero if X is either EQ or NE. */
1782 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1784 enum rtx_code code = GET_CODE (x);
1786 return (code == EQ || code == NE);
1789 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1792 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1794 enum rtx_code code = GET_CODE (x);
1796 return (code == GT || code == LE || code == GTU || code == LEU);
1799 /* Return nonzero if X is either GTU or LEU. */
1802 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1804 enum rtx_code code = GET_CODE (x);
1806 return (code == GTU || code == LEU);
1809 /* Return nonzero if X is either IOR or XOR. */
1812 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1814 enum rtx_code code = GET_CODE (x);
1816 return (code == IOR || code == XOR);
1819 /* Recognize valid operators for bit instructions. */
1822 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1824 enum rtx_code code = GET_CODE (x);
1831 /* Return the length of mov instruction. */
1834 compute_mov_length (rtx *operands)
1836 /* If the mov instruction involves a memory operand, we compute the
1837 length, assuming the largest addressing mode is used, and then
1838 adjust later in the function. Otherwise, we compute and return
1839 the exact length in one step. */
1840 enum machine_mode mode = GET_MODE (operands[0]);
1841 rtx dest = operands[0];
1842 rtx src = operands[1];
1845 if (GET_CODE (src) == MEM)
1846 addr = XEXP (src, 0);
1847 else if (GET_CODE (dest) == MEM)
1848 addr = XEXP (dest, 0);
1854 unsigned int base_length;
1859 if (addr == NULL_RTX)
1862 /* The eightbit addressing is available only in QImode, so
1863 go ahead and take care of it. */
1864 if (h8300_eightbit_constant_address_p (addr))
1871 if (addr == NULL_RTX)
1876 if (src == const0_rtx)
1886 if (addr == NULL_RTX)
1891 if (GET_CODE (src) == CONST_INT)
1893 if (src == const0_rtx)
1896 if ((INTVAL (src) & 0xffff) == 0)
1899 if ((INTVAL (src) & 0xffff) == 0)
1902 if ((INTVAL (src) & 0xffff)
1903 == ((INTVAL (src) >> 16) & 0xffff))
1913 if (addr == NULL_RTX)
1918 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1931 /* Adjust the length based on the addressing mode used.
1932 Specifically, we subtract the difference between the actual
1933 length and the longest one, which is @(d:16,Rs). For SImode
1934 and SFmode, we double the adjustment because two mov.w are
1935 used to do the job. */
1937 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1938 if (GET_CODE (addr) == PRE_DEC
1939 || GET_CODE (addr) == POST_INC)
1941 if (mode == QImode || mode == HImode)
1942 return base_length - 2;
1944 /* In SImode and SFmode, we use two mov.w instructions, so
1945 double the adjustment. */
1946 return base_length - 4;
1949 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1950 in SImode and SFmode, the second mov.w involves an address
1951 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1953 if (GET_CODE (addr) == REG)
1954 return base_length - 2;
1960 unsigned int base_length;
1965 if (addr == NULL_RTX)
1968 /* The eightbit addressing is available only in QImode, so
1969 go ahead and take care of it. */
1970 if (h8300_eightbit_constant_address_p (addr))
1977 if (addr == NULL_RTX)
1982 if (src == const0_rtx)
1992 if (addr == NULL_RTX)
1996 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2002 if (GET_CODE (src) == CONST_INT)
2004 int val = INTVAL (src);
2009 if (val == (val & 0x00ff) || val == (val & 0xff00))
2012 switch (val & 0xffffffff)
2033 if (addr == NULL_RTX)
2038 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2051 /* Adjust the length based on the addressing mode used.
2052 Specifically, we subtract the difference between the actual
2053 length and the longest one, which is @(d:24,ERs). */
2055 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2056 if (GET_CODE (addr) == PRE_DEC
2057 || GET_CODE (addr) == POST_INC)
2058 return base_length - 6;
2060 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2061 if (GET_CODE (addr) == REG)
2062 return base_length - 6;
2064 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2066 if (GET_CODE (addr) == PLUS
2067 && GET_CODE (XEXP (addr, 0)) == REG
2068 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2069 && INTVAL (XEXP (addr, 1)) > -32768
2070 && INTVAL (XEXP (addr, 1)) < 32767)
2071 return base_length - 4;
2073 /* @aa:16 is 4 bytes shorter than the longest. */
2074 if (h8300_tiny_constant_address_p (addr))
2075 return base_length - 4;
2077 /* @aa:24 is 2 bytes shorter than the longest. */
2078 if (CONSTANT_P (addr))
2079 return base_length - 2;
2086 output_plussi (rtx *operands)
2088 enum machine_mode mode = GET_MODE (operands[0]);
2095 if (GET_CODE (operands[2]) == REG)
2096 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2098 if (GET_CODE (operands[2]) == CONST_INT)
2100 HOST_WIDE_INT n = INTVAL (operands[2]);
2102 if ((n & 0xffffff) == 0)
2103 return "add\t%z2,%z0";
2104 if ((n & 0xffff) == 0)
2105 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2106 if ((n & 0xff) == 0)
2107 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2110 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2114 if (GET_CODE (operands[2]) == REG)
2115 return "add.l\t%S2,%S0";
2117 if (GET_CODE (operands[2]) == CONST_INT)
2119 HOST_WIDE_INT intval = INTVAL (operands[2]);
2121 /* See if we can finish with 2 bytes. */
2123 switch ((unsigned int) intval & 0xffffffff)
2128 return "adds\t%2,%S0";
2133 return "subs\t%G2,%S0";
2137 operands[2] = GEN_INT (intval >> 16);
2138 return "inc.w\t%2,%e0";
2142 operands[2] = GEN_INT (intval >> 16);
2143 return "dec.w\t%G2,%e0";
2146 /* See if we can finish with 4 bytes. */
2147 if ((intval & 0xffff) == 0)
2149 operands[2] = GEN_INT (intval >> 16);
2150 return "add.w\t%2,%e0";
2154 return "add.l\t%S2,%S0";
2159 compute_plussi_length (rtx *operands)
2161 enum machine_mode mode = GET_MODE (operands[0]);
2168 if (GET_CODE (operands[2]) == REG)
2171 if (GET_CODE (operands[2]) == CONST_INT)
2173 HOST_WIDE_INT n = INTVAL (operands[2]);
2175 if ((n & 0xffffff) == 0)
2177 if ((n & 0xffff) == 0)
2179 if ((n & 0xff) == 0)
2187 if (GET_CODE (operands[2]) == REG)
2190 if (GET_CODE (operands[2]) == CONST_INT)
2192 HOST_WIDE_INT intval = INTVAL (operands[2]);
2194 /* See if we can finish with 2 bytes. */
2196 switch ((unsigned int) intval & 0xffffffff)
2217 /* See if we can finish with 4 bytes. */
2218 if ((intval & 0xffff) == 0)
2227 compute_plussi_cc (rtx *operands)
2229 enum machine_mode mode = GET_MODE (operands[0]);
2240 if (GET_CODE (operands[2]) == REG)
2243 if (GET_CODE (operands[2]) == CONST_INT)
2245 HOST_WIDE_INT intval = INTVAL (operands[2]);
2247 /* See if we can finish with 2 bytes. */
2249 switch ((unsigned int) intval & 0xffffffff)
2254 return CC_NONE_0HIT;
2259 return CC_NONE_0HIT;
2270 /* See if we can finish with 4 bytes. */
2271 if ((intval & 0xffff) == 0)
2280 output_logical_op (enum machine_mode mode, rtx *operands)
2282 /* Figure out the logical op that we need to perform. */
2283 enum rtx_code code = GET_CODE (operands[3]);
2284 /* Pretend that every byte is affected if both operands are registers. */
2285 const unsigned HOST_WIDE_INT intval =
2286 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2287 ? INTVAL (operands[2]) : 0x55555555);
2288 /* The determinant of the algorithm. If we perform an AND, 0
2289 affects a bit. Otherwise, 1 affects a bit. */
2290 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2291 /* Break up DET into pieces. */
2292 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2293 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2294 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2295 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2296 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2297 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2298 int lower_half_easy_p = 0;
2299 int upper_half_easy_p = 0;
2300 /* The name of an insn. */
2322 /* First, see if we can finish with one insn. */
2323 if ((TARGET_H8300H || TARGET_H8300S)
2327 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2328 output_asm_insn (insn_buf, operands);
2332 /* Take care of the lower byte. */
2335 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2336 output_asm_insn (insn_buf, operands);
2338 /* Take care of the upper byte. */
2341 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2342 output_asm_insn (insn_buf, operands);
2347 if (TARGET_H8300H || TARGET_H8300S)
2349 /* Determine if the lower half can be taken care of in no more
2351 lower_half_easy_p = (b0 == 0
2353 || (code != IOR && w0 == 0xffff));
2355 /* Determine if the upper half can be taken care of in no more
2357 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2358 || (code == AND && w1 == 0xff00));
2361 /* Check if doing everything with one insn is no worse than
2362 using multiple insns. */
2363 if ((TARGET_H8300H || TARGET_H8300S)
2364 && w0 != 0 && w1 != 0
2365 && !(lower_half_easy_p && upper_half_easy_p)
2366 && !(code == IOR && w1 == 0xffff
2367 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2369 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2370 output_asm_insn (insn_buf, operands);
2374 /* Take care of the lower and upper words individually. For
2375 each word, we try different methods in the order of
2377 1) the special insn (in case of AND or XOR),
2378 2) the word-wise insn, and
2379 3) The byte-wise insn. */
2381 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2382 output_asm_insn ((code == AND)
2383 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2385 else if ((TARGET_H8300H || TARGET_H8300S)
2389 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2390 output_asm_insn (insn_buf, operands);
2396 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2397 output_asm_insn (insn_buf, operands);
2401 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2402 output_asm_insn (insn_buf, operands);
2407 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2408 output_asm_insn ((code == AND)
2409 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2411 else if ((TARGET_H8300H || TARGET_H8300S)
2414 && (w0 & 0x8000) != 0)
2416 output_asm_insn ("exts.l\t%S0", operands);
2418 else if ((TARGET_H8300H || TARGET_H8300S)
2422 output_asm_insn ("extu.w\t%e0", operands);
2424 else if (TARGET_H8300H || TARGET_H8300S)
2428 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2429 output_asm_insn (insn_buf, operands);
2436 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2437 output_asm_insn (insn_buf, operands);
2441 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2442 output_asm_insn (insn_buf, operands);
2454 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2456 /* Figure out the logical op that we need to perform. */
2457 enum rtx_code code = GET_CODE (operands[3]);
2458 /* Pretend that every byte is affected if both operands are registers. */
2459 const unsigned HOST_WIDE_INT intval =
2460 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2461 ? INTVAL (operands[2]) : 0x55555555);
2462 /* The determinant of the algorithm. If we perform an AND, 0
2463 affects a bit. Otherwise, 1 affects a bit. */
2464 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2465 /* Break up DET into pieces. */
2466 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2467 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2468 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2469 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2470 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2471 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2472 int lower_half_easy_p = 0;
2473 int upper_half_easy_p = 0;
2475 unsigned int length = 0;
2480 /* First, see if we can finish with one insn. */
2481 if ((TARGET_H8300H || TARGET_H8300S)
2485 if (REG_P (operands[2]))
2492 /* Take care of the lower byte. */
2496 /* Take care of the upper byte. */
2502 if (TARGET_H8300H || TARGET_H8300S)
2504 /* Determine if the lower half can be taken care of in no more
2506 lower_half_easy_p = (b0 == 0
2508 || (code != IOR && w0 == 0xffff));
2510 /* Determine if the upper half can be taken care of in no more
2512 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2513 || (code == AND && w1 == 0xff00));
2516 /* Check if doing everything with one insn is no worse than
2517 using multiple insns. */
2518 if ((TARGET_H8300H || TARGET_H8300S)
2519 && w0 != 0 && w1 != 0
2520 && !(lower_half_easy_p && upper_half_easy_p)
2521 && !(code == IOR && w1 == 0xffff
2522 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2524 if (REG_P (operands[2]))
2531 /* Take care of the lower and upper words individually. For
2532 each word, we try different methods in the order of
2534 1) the special insn (in case of AND or XOR),
2535 2) the word-wise insn, and
2536 3) The byte-wise insn. */
2538 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2542 else if ((TARGET_H8300H || TARGET_H8300S)
2558 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2562 else if ((TARGET_H8300H || TARGET_H8300S)
2565 && (w0 & 0x8000) != 0)
2569 else if ((TARGET_H8300H || TARGET_H8300S)
2575 else if (TARGET_H8300H || TARGET_H8300S)
2597 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2599 /* Figure out the logical op that we need to perform. */
2600 enum rtx_code code = GET_CODE (operands[3]);
2601 /* Pretend that every byte is affected if both operands are registers. */
2602 const unsigned HOST_WIDE_INT intval =
2603 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2604 ? INTVAL (operands[2]) : 0x55555555);
2605 /* The determinant of the algorithm. If we perform an AND, 0
2606 affects a bit. Otherwise, 1 affects a bit. */
2607 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2608 /* Break up DET into pieces. */
2609 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2610 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2611 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2612 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2613 int lower_half_easy_p = 0;
2614 int upper_half_easy_p = 0;
2615 /* Condition code. */
2616 enum attr_cc cc = CC_CLOBBER;
2621 /* First, see if we can finish with one insn. */
2622 if ((TARGET_H8300H || TARGET_H8300S)
2630 if (TARGET_H8300H || TARGET_H8300S)
2632 /* Determine if the lower half can be taken care of in no more
2634 lower_half_easy_p = (b0 == 0
2636 || (code != IOR && w0 == 0xffff));
2638 /* Determine if the upper half can be taken care of in no more
2640 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2641 || (code == AND && w1 == 0xff00));
2644 /* Check if doing everything with one insn is no worse than
2645 using multiple insns. */
2646 if ((TARGET_H8300H || TARGET_H8300S)
2647 && w0 != 0 && w1 != 0
2648 && !(lower_half_easy_p && upper_half_easy_p)
2649 && !(code == IOR && w1 == 0xffff
2650 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2656 if ((TARGET_H8300H || TARGET_H8300S)
2659 && (w0 & 0x8000) != 0)
2673 We devote a fair bit of code to getting efficient shifts since we
2674 can only shift one bit at a time on the H8/300 and H8/300H and only
2675 one or two bits at a time on the H8S.
2677 All shift code falls into one of the following ways of
2680 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2681 when a straight line shift is about the same size or smaller than
2684 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2685 off the bits we don't need. This is used when only a few of the
2686 bits in the original value will survive in the shifted value.
2688 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2689 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2690 shifts can be added if the shift count is slightly more than 8 or
2691 16. This case also includes other oddballs that are not worth
2694 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2696 For each shift count, we try to use code that has no trade-off
2697 between code size and speed whenever possible.
2699 If the trade-off is unavoidable, we try to be reasonable.
2700 Specifically, the fastest version is one instruction longer than
2701 the shortest version, we take the fastest version. We also provide
2702 the use a way to switch back to the shortest version with -Os.
2704 For the details of the shift algorithms for various shift counts,
2705 refer to shift_alg_[qhs]i. */
2708 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2710 switch (GET_CODE (x))
2722 /* Emit code to do shifts. */
2725 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2727 emit_move_insn (operands[0], operands[1]);
2729 /* Need a loop to get all the bits we want - we generate the
2730 code at emit time, but need to allocate a scratch reg now. */
2732 emit_insn (gen_rtx_PARALLEL
2735 gen_rtx_SET (VOIDmode, operands[0],
2736 gen_rtx_fmt_ee (code, mode,
2737 operands[0], operands[2])),
2738 gen_rtx_CLOBBER (VOIDmode,
2739 gen_rtx_SCRATCH (QImode)))));
2742 /* Symbols of the various modes which can be used as indices. */
2746 QIshift, HIshift, SIshift
2749 /* For single bit shift insns, record assembler and what bits of the
2750 condition code are valid afterwards (represented as various CC_FOO
2751 bits, 0 means CC isn't left in a usable state). */
2755 const char *const assembler;
2759 /* Assembler instruction shift table.
2761 These tables are used to look up the basic shifts.
2762 They are indexed by cpu, shift_type, and mode. */
2764 static const struct shift_insn shift_one[2][3][3] =
2770 { "shll\t%X0", CC_SET_ZNV },
2771 { "add.w\t%T0,%T0", CC_SET_ZN },
2772 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2774 /* SHIFT_LSHIFTRT */
2776 { "shlr\t%X0", CC_SET_ZNV },
2777 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2778 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2780 /* SHIFT_ASHIFTRT */
2782 { "shar\t%X0", CC_SET_ZNV },
2783 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2784 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2791 { "shll.b\t%X0", CC_SET_ZNV },
2792 { "shll.w\t%T0", CC_SET_ZNV },
2793 { "shll.l\t%S0", CC_SET_ZNV }
2795 /* SHIFT_LSHIFTRT */
2797 { "shlr.b\t%X0", CC_SET_ZNV },
2798 { "shlr.w\t%T0", CC_SET_ZNV },
2799 { "shlr.l\t%S0", CC_SET_ZNV }
2801 /* SHIFT_ASHIFTRT */
2803 { "shar.b\t%X0", CC_SET_ZNV },
2804 { "shar.w\t%T0", CC_SET_ZNV },
2805 { "shar.l\t%S0", CC_SET_ZNV }
2810 static const struct shift_insn shift_two[3][3] =
2814 { "shll.b\t#2,%X0", CC_SET_ZNV },
2815 { "shll.w\t#2,%T0", CC_SET_ZNV },
2816 { "shll.l\t#2,%S0", CC_SET_ZNV }
2818 /* SHIFT_LSHIFTRT */
2820 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2821 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2822 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2824 /* SHIFT_ASHIFTRT */
2826 { "shar.b\t#2,%X0", CC_SET_ZNV },
2827 { "shar.w\t#2,%T0", CC_SET_ZNV },
2828 { "shar.l\t#2,%S0", CC_SET_ZNV }
2832 /* Rotates are organized by which shift they'll be used in implementing.
2833 There's no need to record whether the cc is valid afterwards because
2834 it is the AND insn that will decide this. */
2836 static const char *const rotate_one[2][3][3] =
2843 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2846 /* SHIFT_LSHIFTRT */
2849 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2852 /* SHIFT_ASHIFTRT */
2855 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2867 /* SHIFT_LSHIFTRT */
2873 /* SHIFT_ASHIFTRT */
2882 static const char *const rotate_two[3][3] =
2890 /* SHIFT_LSHIFTRT */
2896 /* SHIFT_ASHIFTRT */
2905 /* Shift algorithm. */
2908 /* The number of bits to be shifted by shift1 and shift2. Valid
2909 when ALG is SHIFT_SPECIAL. */
2910 unsigned int remainder;
2912 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2913 const char *special;
2915 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2916 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2919 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2920 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2923 /* CC status for SHIFT_INLINE. */
2926 /* CC status for SHIFT_SPECIAL. */
2930 static void get_shift_alg (enum shift_type,
2931 enum shift_mode, unsigned int,
2932 struct shift_info *);
2934 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2935 best algorithm for doing the shift. The assembler code is stored
2936 in the pointers in INFO. We achieve the maximum efficiency in most
2937 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2938 SImode in particular have a lot of room to optimize.
2940 We first determine the strategy of the shift algorithm by a table
2941 lookup. If that tells us to use a hand crafted assembly code, we
2942 go into the big switch statement to find what that is. Otherwise,
2943 we resort to a generic way, such as inlining. In either case, the
2944 result is returned through INFO. */
2947 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2948 unsigned int count, struct shift_info *info)
2952 /* Find the target CPU. */
2955 else if (TARGET_H8300H)
2960 /* Find the shift algorithm. */
2961 info->alg = SHIFT_LOOP;
2965 if (count < GET_MODE_BITSIZE (QImode))
2966 info->alg = shift_alg_qi[cpu][shift_type][count];
2970 if (count < GET_MODE_BITSIZE (HImode))
2971 info->alg = shift_alg_hi[cpu][shift_type][count];
2975 if (count < GET_MODE_BITSIZE (SImode))
2976 info->alg = shift_alg_si[cpu][shift_type][count];
2983 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2987 info->remainder = count;
2991 /* It is up to the caller to know that looping clobbers cc. */
2992 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2993 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2994 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2998 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2999 info->shift2 = rotate_two[shift_type][shift_mode];
3000 info->cc_inline = CC_CLOBBER;
3004 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3005 info->remainder = 0;
3006 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3007 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3008 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3009 info->cc_special = CC_CLOBBER;
3013 /* Here we only deal with SHIFT_SPECIAL. */
3017 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3018 through the entire value. */
3019 if (shift_type == SHIFT_ASHIFTRT && count == 7)
3021 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3033 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3035 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3037 case SHIFT_LSHIFTRT:
3039 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3041 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3043 case SHIFT_ASHIFTRT:
3044 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3048 else if ((8 <= count && count <= 13)
3049 || (TARGET_H8300S && count == 14))
3051 info->remainder = count - 8;
3056 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3058 case SHIFT_LSHIFTRT:
3061 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3062 info->shift1 = "shlr.b\t%s0";
3063 info->cc_inline = CC_SET_ZNV;
3067 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3068 info->cc_special = CC_SET_ZNV;
3071 case SHIFT_ASHIFTRT:
3074 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3075 info->shift1 = "shar.b\t%s0";
3079 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3080 info->cc_special = CC_SET_ZNV;
3085 else if (count == 14)
3091 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3093 case SHIFT_LSHIFTRT:
3095 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3097 case SHIFT_ASHIFTRT:
3099 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3100 else if (TARGET_H8300H)
3102 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3103 info->cc_special = CC_SET_ZNV;
3105 else /* TARGET_H8300S */
3110 else if (count == 15)
3115 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3117 case SHIFT_LSHIFTRT:
3118 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3120 case SHIFT_ASHIFTRT:
3121 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3128 if (TARGET_H8300 && 8 <= count && count <= 9)
3130 info->remainder = count - 8;
3135 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3137 case SHIFT_LSHIFTRT:
3138 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3139 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3141 case SHIFT_ASHIFTRT:
3142 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3146 else if (count == 8 && !TARGET_H8300)
3151 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3153 case SHIFT_LSHIFTRT:
3154 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3156 case SHIFT_ASHIFTRT:
3157 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3161 else if (count == 15 && TARGET_H8300)
3167 case SHIFT_LSHIFTRT:
3168 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3170 case SHIFT_ASHIFTRT:
3171 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3175 else if (count == 15 && !TARGET_H8300)
3180 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3181 info->cc_special = CC_SET_ZNV;
3183 case SHIFT_LSHIFTRT:
3184 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3185 info->cc_special = CC_SET_ZNV;
3187 case SHIFT_ASHIFTRT:
3191 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3192 || (TARGET_H8300H && 16 <= count && count <= 19)
3193 || (TARGET_H8300S && 16 <= count && count <= 21))
3195 info->remainder = count - 16;
3200 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3202 info->shift1 = "add.w\t%e0,%e0";
3204 case SHIFT_LSHIFTRT:
3207 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3208 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3212 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3213 info->cc_special = CC_SET_ZNV;
3216 case SHIFT_ASHIFTRT:
3219 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3220 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3224 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3225 info->cc_special = CC_SET_ZNV;
3230 else if (TARGET_H8300 && 24 <= count && count <= 28)
3232 info->remainder = count - 24;
3237 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3238 info->shift1 = "shll.b\t%z0";
3239 info->cc_inline = CC_SET_ZNV;
3241 case SHIFT_LSHIFTRT:
3242 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3243 info->shift1 = "shlr.b\t%w0";
3244 info->cc_inline = CC_SET_ZNV;
3246 case SHIFT_ASHIFTRT:
3247 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3248 info->shift1 = "shar.b\t%w0";
3249 info->cc_inline = CC_SET_ZNV;
3253 else if ((TARGET_H8300H && count == 24)
3254 || (TARGET_H8300S && 24 <= count && count <= 25))
3256 info->remainder = count - 24;
3261 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3263 case SHIFT_LSHIFTRT:
3264 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3265 info->cc_special = CC_SET_ZNV;
3267 case SHIFT_ASHIFTRT:
3268 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3269 info->cc_special = CC_SET_ZNV;
3273 else if (!TARGET_H8300 && count == 28)
3279 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3281 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3283 case SHIFT_LSHIFTRT:
3286 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3287 info->cc_special = CC_SET_ZNV;
3290 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3292 case SHIFT_ASHIFTRT:
3296 else if (!TARGET_H8300 && count == 29)
3302 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3304 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3306 case SHIFT_LSHIFTRT:
3309 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3310 info->cc_special = CC_SET_ZNV;
3314 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3315 info->cc_special = CC_SET_ZNV;
3318 case SHIFT_ASHIFTRT:
3322 else if (!TARGET_H8300 && count == 30)
3328 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3330 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3332 case SHIFT_LSHIFTRT:
3334 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3336 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3338 case SHIFT_ASHIFTRT:
3342 else if (count == 31)
3349 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3351 case SHIFT_LSHIFTRT:
3352 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3354 case SHIFT_ASHIFTRT:
3355 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3364 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3365 info->cc_special = CC_SET_ZNV;
3367 case SHIFT_LSHIFTRT:
3368 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3369 info->cc_special = CC_SET_ZNV;
3371 case SHIFT_ASHIFTRT:
3372 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3373 info->cc_special = CC_SET_ZNV;
3386 info->shift2 = NULL;
3389 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3390 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3393 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3398 if (GET_MODE_BITSIZE (mode) <= count)
3401 /* Find out the target CPU. */
3404 else if (TARGET_H8300H)
3409 /* Find the shift algorithm. */
3413 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3414 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3415 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3419 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3420 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3421 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3425 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3426 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3427 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3434 /* On H8/300H, count == 8 uses a scratch register. */
3435 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3436 || (TARGET_H8300H && mode == SImode && count == 8));
3439 /* Emit the assembler code for doing shifts. */
3442 output_a_shift (rtx *operands)
3444 static int loopend_lab;
3445 rtx shift = operands[3];
3446 enum machine_mode mode = GET_MODE (shift);
3447 enum rtx_code code = GET_CODE (shift);
3448 enum shift_type shift_type;
3449 enum shift_mode shift_mode;
3450 struct shift_info info;
3457 shift_mode = QIshift;
3460 shift_mode = HIshift;
3463 shift_mode = SIshift;
3472 shift_type = SHIFT_ASHIFTRT;
3475 shift_type = SHIFT_LSHIFTRT;
3478 shift_type = SHIFT_ASHIFT;
3484 if (GET_CODE (operands[2]) != CONST_INT)
3486 /* This case must be taken care of by one of the two splitters
3487 that convert a variable shift into a loop. */
3492 int n = INTVAL (operands[2]);
3494 /* If the count is negative, make it 0. */
3497 /* If the count is too big, truncate it.
3498 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3499 do the intuitive thing. */
3500 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3501 n = GET_MODE_BITSIZE (mode);
3503 get_shift_alg (shift_type, shift_mode, n, &info);
3508 output_asm_insn (info.special, operands);
3514 /* Emit two bit shifts first. */
3515 if (info.shift2 != NULL)
3517 for (; n > 1; n -= 2)
3518 output_asm_insn (info.shift2, operands);
3521 /* Now emit one bit shifts for any residual. */
3523 output_asm_insn (info.shift1, operands);
3528 int m = GET_MODE_BITSIZE (mode) - n;
3529 const int mask = (shift_type == SHIFT_ASHIFT
3530 ? ((1 << m) - 1) << n
3534 /* Not all possibilities of rotate are supported. They shouldn't
3535 be generated, but let's watch for 'em. */
3536 if (info.shift1 == 0)
3539 /* Emit two bit rotates first. */
3540 if (info.shift2 != NULL)
3542 for (; m > 1; m -= 2)
3543 output_asm_insn (info.shift2, operands);
3546 /* Now single bit rotates for any residual. */
3548 output_asm_insn (info.shift1, operands);
3550 /* Now mask off the high bits. */
3552 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3553 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3554 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3558 output_asm_insn (insn_buf, operands);
3563 /* A loop to shift by a "large" constant value.
3564 If we have shift-by-2 insns, use them. */
3565 if (info.shift2 != NULL)
3567 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3568 names_big[REGNO (operands[4])]);
3569 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3570 output_asm_insn (info.shift2, operands);
3571 output_asm_insn ("add #0xff,%X4", operands);
3572 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3574 output_asm_insn (info.shift1, operands);
3578 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3579 names_big[REGNO (operands[4])]);
3580 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3581 output_asm_insn (info.shift1, operands);
3582 output_asm_insn ("add #0xff,%X4", operands);
3583 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3594 h8300_asm_insn_count (const char *template)
3596 unsigned int count = 1;
3598 for (; *template; template++)
3599 if (*template == '\n')
3606 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3608 rtx shift = operands[3];
3609 enum machine_mode mode = GET_MODE (shift);
3610 enum rtx_code code = GET_CODE (shift);
3611 enum shift_type shift_type;
3612 enum shift_mode shift_mode;
3613 struct shift_info info;
3614 unsigned int wlength = 0;
3619 shift_mode = QIshift;
3622 shift_mode = HIshift;
3625 shift_mode = SIshift;
3634 shift_type = SHIFT_ASHIFTRT;
3637 shift_type = SHIFT_LSHIFTRT;
3640 shift_type = SHIFT_ASHIFT;
3646 if (GET_CODE (operands[2]) != CONST_INT)
3648 /* Get the assembler code to do one shift. */
3649 get_shift_alg (shift_type, shift_mode, 1, &info);
3651 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3655 int n = INTVAL (operands[2]);
3657 /* If the count is negative, make it 0. */
3660 /* If the count is too big, truncate it.
3661 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3662 do the intuitive thing. */
3663 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3664 n = GET_MODE_BITSIZE (mode);
3666 get_shift_alg (shift_type, shift_mode, n, &info);
3671 wlength += h8300_asm_insn_count (info.special);
3673 /* Every assembly instruction used in SHIFT_SPECIAL case
3674 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3675 see xor.l, we just pretend that xor.l counts as two insns
3676 so that the insn length will be computed correctly. */
3677 if (strstr (info.special, "xor.l") != NULL)
3685 if (info.shift2 != NULL)
3687 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3691 wlength += h8300_asm_insn_count (info.shift1) * n;
3697 int m = GET_MODE_BITSIZE (mode) - n;
3699 /* Not all possibilities of rotate are supported. They shouldn't
3700 be generated, but let's watch for 'em. */
3701 if (info.shift1 == 0)
3704 if (info.shift2 != NULL)
3706 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3710 wlength += h8300_asm_insn_count (info.shift1) * m;
3712 /* Now mask off the high bits. */
3733 /* A loop to shift by a "large" constant value.
3734 If we have shift-by-2 insns, use them. */
3735 if (info.shift2 != NULL)
3737 wlength += 3 + h8300_asm_insn_count (info.shift2);
3739 wlength += h8300_asm_insn_count (info.shift1);
3743 wlength += 3 + h8300_asm_insn_count (info.shift1);
3754 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3756 rtx shift = operands[3];
3757 enum machine_mode mode = GET_MODE (shift);
3758 enum rtx_code code = GET_CODE (shift);
3759 enum shift_type shift_type;
3760 enum shift_mode shift_mode;
3761 struct shift_info info;
3766 shift_mode = QIshift;
3769 shift_mode = HIshift;
3772 shift_mode = SIshift;
3781 shift_type = SHIFT_ASHIFTRT;
3784 shift_type = SHIFT_LSHIFTRT;
3787 shift_type = SHIFT_ASHIFT;
3793 if (GET_CODE (operands[2]) != CONST_INT)
3795 /* This case must be taken care of by one of the two splitters
3796 that convert a variable shift into a loop. */
3801 int n = INTVAL (operands[2]);
3803 /* If the count is negative, make it 0. */
3806 /* If the count is too big, truncate it.
3807 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3808 do the intuitive thing. */
3809 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3810 n = GET_MODE_BITSIZE (mode);
3812 get_shift_alg (shift_type, shift_mode, n, &info);
3817 if (info.remainder == 0)
3818 return info.cc_special;
3823 return info.cc_inline;
3826 /* This case always ends with an and instruction. */
3830 /* A loop to shift by a "large" constant value.
3831 If we have shift-by-2 insns, use them. */
3832 if (info.shift2 != NULL)
3835 return info.cc_inline;
3845 /* A rotation by a non-constant will cause a loop to be generated, in
3846 which a rotation by one bit is used. A rotation by a constant,
3847 including the one in the loop, will be taken care of by
3848 output_a_rotate () at the insn emit time. */
3851 expand_a_rotate (enum rtx_code code, rtx operands[])
3853 rtx dst = operands[0];
3854 rtx src = operands[1];
3855 rtx rotate_amount = operands[2];
3856 enum machine_mode mode = GET_MODE (dst);
3859 /* We rotate in place. */
3860 emit_move_insn (dst, src);
3862 if (GET_CODE (rotate_amount) != CONST_INT)
3864 rtx counter = gen_reg_rtx (QImode);
3865 rtx start_label = gen_label_rtx ();
3866 rtx end_label = gen_label_rtx ();
3868 /* If the rotate amount is less than or equal to 0,
3869 we go out of the loop. */
3870 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3871 QImode, 0, end_label);
3873 /* Initialize the loop counter. */
3874 emit_move_insn (counter, rotate_amount);
3876 emit_label (start_label);
3878 /* Rotate by one bit. */
3879 tmp = gen_rtx_fmt_ee (code, mode, dst, GEN_INT (1));
3880 emit_insn (gen_rtx_SET (mode, dst, tmp));
3882 /* Decrement the counter by 1. */
3883 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3884 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3886 /* If the loop counter is nonzero, we go back to the beginning
3888 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3891 emit_label (end_label);
3895 /* Rotate by AMOUNT bits. */
3896 tmp = gen_rtx_fmt_ee (code, mode, dst, rotate_amount);
3897 emit_insn (gen_rtx_SET (mode, dst, tmp));
3903 /* Output rotate insns. */
3906 output_a_rotate (enum rtx_code code, rtx *operands)
3908 rtx dst = operands[0];
3909 rtx rotate_amount = operands[2];
3910 enum shift_mode rotate_mode;
3911 enum shift_type rotate_type;
3912 const char *insn_buf;
3915 enum machine_mode mode = GET_MODE (dst);
3917 if (GET_CODE (rotate_amount) != CONST_INT)
3923 rotate_mode = QIshift;
3926 rotate_mode = HIshift;
3929 rotate_mode = SIshift;
3938 rotate_type = SHIFT_ASHIFT;
3941 rotate_type = SHIFT_LSHIFTRT;
3947 amount = INTVAL (rotate_amount);
3949 /* Clean up AMOUNT. */
3952 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3953 amount = GET_MODE_BITSIZE (mode);
3955 /* Determine the faster direction. After this phase, amount will be
3956 at most a half of GET_MODE_BITSIZE (mode). */
3957 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3959 /* Flip the direction. */
3960 amount = GET_MODE_BITSIZE (mode) - amount;
3962 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3965 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3966 boost up the rotation. */
3967 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3968 || (mode == HImode && TARGET_H8300H && amount >= 6)
3969 || (mode == HImode && TARGET_H8300S && amount == 8)
3970 || (mode == SImode && TARGET_H8300H && amount >= 10)
3971 || (mode == SImode && TARGET_H8300S && amount >= 13))
3976 /* This code works on any family. */
3977 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3978 output_asm_insn (insn_buf, operands);
3982 /* This code works on the H8/300H and H8S. */
3983 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3984 output_asm_insn (insn_buf, operands);
3991 /* Adjust AMOUNT and flip the direction. */
3992 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3994 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3997 /* Emit rotate insns. */
3998 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4001 insn_buf = rotate_two[rotate_type][rotate_mode];
4003 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
4005 for (; amount >= bits; amount -= bits)
4006 output_asm_insn (insn_buf, operands);
4013 compute_a_rotate_length (rtx *operands)
4015 rtx src = operands[1];
4016 rtx amount_rtx = operands[2];
4017 enum machine_mode mode = GET_MODE (src);
4019 unsigned int length = 0;
4021 if (GET_CODE (amount_rtx) != CONST_INT)
4024 amount = INTVAL (amount_rtx);
4026 /* Clean up AMOUNT. */
4029 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4030 amount = GET_MODE_BITSIZE (mode);
4032 /* Determine the faster direction. After this phase, amount
4033 will be at most a half of GET_MODE_BITSIZE (mode). */
4034 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4035 /* Flip the direction. */
4036 amount = GET_MODE_BITSIZE (mode) - amount;
4038 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4039 boost up the rotation. */
4040 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4041 || (mode == HImode && TARGET_H8300H && amount >= 6)
4042 || (mode == HImode && TARGET_H8300S && amount == 8)
4043 || (mode == SImode && TARGET_H8300H && amount >= 10)
4044 || (mode == SImode && TARGET_H8300S && amount >= 13))
4046 /* Adjust AMOUNT and flip the direction. */
4047 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4051 /* We use 2-bit rotations on the H8S. */
4053 amount = amount / 2 + amount % 2;
4055 /* The H8/300 uses three insns to rotate one bit, taking 6
4057 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4062 /* Fix the operands of a gen_xxx so that it could become a bit
4066 fix_bit_operand (rtx *operands, int what, enum rtx_code type)
4068 /* The bit_operand predicate accepts any memory during RTL generation, but
4069 only 'U' memory afterwards, so if this is a MEM operand, we must force
4070 it to be valid for 'U' by reloading the address. */
4072 if ((what == 0 && single_zero_operand (operands[2], QImode))
4073 || (what == 1 && single_one_operand (operands[2], QImode)))
4075 /* OK to have a memory dest. */
4076 if (GET_CODE (operands[0]) == MEM
4077 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4079 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4080 copy_to_mode_reg (Pmode,
4081 XEXP (operands[0], 0)));
4082 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4086 if (GET_CODE (operands[1]) == MEM
4087 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4089 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4090 copy_to_mode_reg (Pmode,
4091 XEXP (operands[1], 0)));
4092 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4098 /* Dest and src op must be register. */
4100 operands[1] = force_reg (QImode, operands[1]);
4102 rtx res = gen_reg_rtx (QImode);
4103 emit_insn (gen_rtx_SET (VOIDmode, res,
4104 gen_rtx_fmt_ee (type, QImode,
4105 operands[1], operands[2])));
4106 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
4111 /* Return nonzero if FUNC is an interrupt function as specified
4112 by the "interrupt" attribute. */
4115 h8300_interrupt_function_p (tree func)
4119 if (TREE_CODE (func) != FUNCTION_DECL)
4122 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4123 return a != NULL_TREE;
4126 /* Return nonzero if FUNC is a saveall function as specified by the
4127 "saveall" attribute. */
4130 h8300_saveall_function_p (tree func)
4134 if (TREE_CODE (func) != FUNCTION_DECL)
4137 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4138 return a != NULL_TREE;
4141 /* Return nonzero if FUNC is an OS_Task function as specified
4142 by the "OS_Task" attribute. */
4145 h8300_os_task_function_p (tree func)
4149 if (TREE_CODE (func) != FUNCTION_DECL)
4152 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4153 return a != NULL_TREE;
4156 /* Return nonzero if FUNC is a monitor function as specified
4157 by the "monitor" attribute. */
4160 h8300_monitor_function_p (tree func)
4164 if (TREE_CODE (func) != FUNCTION_DECL)
4167 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4168 return a != NULL_TREE;
4171 /* Return nonzero if FUNC is a function that should be called
4172 through the function vector. */
4175 h8300_funcvec_function_p (tree func)
4179 if (TREE_CODE (func) != FUNCTION_DECL)
4182 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4183 return a != NULL_TREE;
4186 /* Return nonzero if DECL is a variable that's in the eight bit
4190 h8300_eightbit_data_p (tree decl)
4194 if (TREE_CODE (decl) != VAR_DECL)
4197 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4198 return a != NULL_TREE;
4201 /* Return nonzero if DECL is a variable that's in the tiny
4205 h8300_tiny_data_p (tree decl)
4209 if (TREE_CODE (decl) != VAR_DECL)
4212 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4213 return a != NULL_TREE;
4216 /* Generate an 'interrupt_handler' attribute for decls. We convert
4217 all the pragmas to corresponding attributes. */
4220 h8300_insert_attributes (tree node, tree *attributes)
4222 if (TREE_CODE (node) == FUNCTION_DECL)
4224 if (pragma_interrupt)
4226 pragma_interrupt = 0;
4228 /* Add an 'interrupt_handler' attribute. */
4229 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4237 /* Add an 'saveall' attribute. */
4238 *attributes = tree_cons (get_identifier ("saveall"),
4244 /* Supported attributes:
4246 interrupt_handler: output a prologue and epilogue suitable for an
4249 saveall: output a prologue and epilogue that saves and restores
4250 all registers except the stack pointer.
4252 function_vector: This function should be called through the
4255 eightbit_data: This variable lives in the 8-bit data area and can
4256 be referenced with 8-bit absolute memory addresses.
4258 tiny_data: This variable lives in the tiny data area and can be
4259 referenced with 16-bit absolute memory references. */
4261 const struct attribute_spec h8300_attribute_table[] =
4263 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4264 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4265 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4266 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4267 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4268 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4269 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4270 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4271 { NULL, 0, 0, false, false, false, NULL }
4275 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4276 struct attribute_spec.handler. */
4278 h8300_handle_fndecl_attribute (tree *node, tree name,
4279 tree args ATTRIBUTE_UNUSED,
4280 int flags ATTRIBUTE_UNUSED,
4283 if (TREE_CODE (*node) != FUNCTION_DECL)
4285 warning ("`%s' attribute only applies to functions",
4286 IDENTIFIER_POINTER (name));
4287 *no_add_attrs = true;
4293 /* Handle an "eightbit_data" attribute; arguments as in
4294 struct attribute_spec.handler. */
4296 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4297 tree args ATTRIBUTE_UNUSED,
4298 int flags ATTRIBUTE_UNUSED,
4303 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4305 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4309 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4310 *no_add_attrs = true;
4316 /* Handle an "tiny_data" attribute; arguments as in
4317 struct attribute_spec.handler. */
4319 h8300_handle_tiny_data_attribute (tree *node, tree name,
4320 tree args ATTRIBUTE_UNUSED,
4321 int flags ATTRIBUTE_UNUSED,
4326 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4328 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4332 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4333 *no_add_attrs = true;
4339 /* Mark function vectors, and various small data objects. */
4342 h8300_encode_section_info (tree decl, rtx rtl, int first)
4344 int extra_flags = 0;
4346 default_encode_section_info (decl, rtl, first);
4348 if (TREE_CODE (decl) == FUNCTION_DECL
4349 && h8300_funcvec_function_p (decl))
4350 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4351 else if (TREE_CODE (decl) == VAR_DECL
4352 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4354 if (h8300_eightbit_data_p (decl))
4355 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4356 else if (first && h8300_tiny_data_p (decl))
4357 extra_flags = SYMBOL_FLAG_TINY_DATA;
4361 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4365 output_simode_bld (int bild, rtx operands[])
4369 /* Clear the destination register. */
4370 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4372 /* Now output the bit load or bit inverse load, and store it in
4375 output_asm_insn ("bild\t%Z2,%Y1", operands);
4377 output_asm_insn ("bld\t%Z2,%Y1", operands);
4379 output_asm_insn ("bst\t#0,%w0", operands);
4383 /* Determine if we can clear the destination first. */
4384 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4385 && REGNO (operands[0]) != REGNO (operands[1]));
4388 output_asm_insn ("sub.l\t%S0,%S0", operands);
4390 /* Output the bit load or bit inverse load. */
4392 output_asm_insn ("bild\t%Z2,%Y1", operands);
4394 output_asm_insn ("bld\t%Z2,%Y1", operands);
4397 output_asm_insn ("xor.l\t%S0,%S0", operands);
4399 /* Perform the bit store. */
4400 output_asm_insn ("rotxl.l\t%S0", operands);
4407 #ifndef OBJECT_FORMAT_ELF
4409 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4411 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4412 fprintf (asm_out_file, "\t.section %s\n", name);
4414 #endif /* ! OBJECT_FORMAT_ELF */
4416 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4417 which is a special case of the 'R' operand. */
4420 h8300_eightbit_constant_address_p (rtx x)
4422 /* The ranges of the 8-bit area. */
4423 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4424 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4425 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4426 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4427 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4428 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4430 unsigned HOST_WIDE_INT addr;
4432 /* We accept symbols declared with eightbit_data. */
4433 if (GET_CODE (x) == SYMBOL_REF)
4434 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4436 if (GET_CODE (x) != CONST_INT)
4442 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4443 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4444 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4447 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4448 on H8/300H and H8S. */
4451 h8300_tiny_constant_address_p (rtx x)
4453 /* The ranges of the 16-bit area. */
4454 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4455 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4456 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4457 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4458 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4459 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4460 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4461 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4463 unsigned HOST_WIDE_INT addr;
4465 switch (GET_CODE (x))
4468 /* In the normal mode, any symbol fits in the 16-bit absolute
4469 address range. We also accept symbols declared with
4471 return (TARGET_NORMAL_MODE
4472 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
4476 return (TARGET_NORMAL_MODE
4478 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4480 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4483 return TARGET_NORMAL_MODE;
4492 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4494 HOST_WIDE_INT offset1, offset2;
4502 else if (GET_CODE (addr1) == PLUS
4503 && REG_P (XEXP (addr1, 0))
4504 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4506 reg1 = XEXP (addr1, 0);
4507 offset1 = INTVAL (XEXP (addr1, 1));
4517 else if (GET_CODE (addr2) == PLUS
4518 && REG_P (XEXP (addr2, 0))
4519 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4521 reg2 = XEXP (addr2, 0);
4522 offset2 = INTVAL (XEXP (addr2, 1));
4527 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4528 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4530 && offset1 + 1 == offset2)
4536 /* Return nonzero if we have the same comparison insn as I3 two insns
4537 before I3. I3 is assumed to be a comparison insn. */
4540 same_cmp_preceding_p (rtx i3)
4544 /* Make sure we have a sequence of three insns. */
4545 i2 = prev_nonnote_insn (i3);
4548 i1 = prev_nonnote_insn (i2);
4552 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4553 && any_condjump_p (i2) && onlyjump_p (i2));
4556 /* Return nonzero if we have the same comparison insn as I1 two insns
4557 after I1. I1 is assumed to be a comparison insn. */
4560 same_cmp_following_p (rtx i1)
4564 /* Make sure we have a sequence of three insns. */
4565 i2 = next_nonnote_insn (i1);
4568 i3 = next_nonnote_insn (i2);
4572 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4573 && any_condjump_p (i2) && onlyjump_p (i2));
4576 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4579 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4580 unsigned int new_reg)
4582 /* Interrupt functions can only use registers that have already been
4583 saved by the prologue, even if they would normally be
4586 if (h8300_current_function_interrupt_function_p ()
4587 && !regs_ever_live[new_reg])
4593 /* Return nonzero if X is a legitimate constant. */
4596 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
4601 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
4604 h8300_rtx_ok_for_base_p (rtx x, int strict)
4606 /* Strip off SUBREG if any. */
4607 if (GET_CODE (x) == SUBREG)
4612 ? REG_OK_FOR_BASE_STRICT_P (x)
4613 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
4616 /* Return nozero if X is a legitimate address. On the H8/300, a
4617 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
4618 CONSTANT_ADDRESS. */
4621 h8300_legitimate_address_p (rtx x, int strict)
4623 /* The register indirect addresses like @er0 is always valid. */
4624 if (h8300_rtx_ok_for_base_p (x, strict))
4627 if (CONSTANT_ADDRESS_P (x))
4630 if (GET_CODE (x) == PLUS
4631 && CONSTANT_ADDRESS_P (XEXP (x, 1))
4632 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
4638 /* Perform target dependent optabs initialization. */
4640 h8300_init_libfuncs (void)
4642 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4643 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4644 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4645 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4646 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4650 h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4652 return (TYPE_MODE (type) == BLKmode
4653 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
4656 /* Initialize the GCC target structure. */
4657 #undef TARGET_ATTRIBUTE_TABLE
4658 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4660 #undef TARGET_ASM_ALIGNED_HI_OP
4661 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4663 #undef TARGET_ASM_FILE_START
4664 #define TARGET_ASM_FILE_START h8300_file_start
4665 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4666 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4668 #undef TARGET_ASM_FILE_END
4669 #define TARGET_ASM_FILE_END h8300_file_end
4671 #undef TARGET_ENCODE_SECTION_INFO
4672 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4674 #undef TARGET_INSERT_ATTRIBUTES
4675 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4677 #undef TARGET_RTX_COSTS
4678 #define TARGET_RTX_COSTS h8300_rtx_costs
4680 #undef TARGET_INIT_LIBFUNCS
4681 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4683 #undef TARGET_STRUCT_VALUE_RTX
4684 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
4685 #undef TARGET_RETURN_IN_MEMORY
4686 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
4688 struct gcc_target targetm = TARGET_INITIALIZER;