1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg PARAMS ((rtx, int));
50 static int h8300_interrupt_function_p PARAMS ((tree));
51 static int h8300_monitor_function_p PARAMS ((tree));
52 static int h8300_os_task_function_p PARAMS ((tree));
53 static void dosize PARAMS ((int, unsigned int));
54 static int round_frame_size PARAMS ((int));
55 static unsigned int compute_saved_regs PARAMS ((void));
56 static void push PARAMS ((int));
57 static void pop PARAMS ((int));
58 static const char *cond_string PARAMS ((enum rtx_code));
59 static unsigned int h8300_asm_insn_count PARAMS ((const char *));
60 const struct attribute_spec h8300_attribute_table[];
61 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
62 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
63 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
64 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
65 static void h8300_insert_attributes PARAMS ((tree, tree *));
66 #ifndef OBJECT_FORMAT_ELF
67 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
69 static void h8300_encode_label PARAMS ((tree));
70 static void h8300_encode_section_info PARAMS ((tree, int));
71 static const char *h8300_strip_name_encoding PARAMS ((const char *));
73 /* CPU_TYPE, says what cpu we're compiling for. */
76 /* True if a #pragma interrupt has been seen for the current function. */
77 static int pragma_interrupt;
79 /* True if a #pragma saveall has been seen for the current function. */
80 static int pragma_saveall;
82 static const char *const names_big[] =
83 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
85 static const char *const names_extended[] =
86 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
88 static const char *const names_upper_extended[] =
89 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
91 /* Points to one of the above. */
92 /* ??? The above could be put in an array indexed by CPU_TYPE. */
93 const char * const *h8_reg_names;
95 /* Various operations needed by the following, indexed by CPU_TYPE. */
97 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
99 /* Initialize the GCC target structure. */
100 #undef TARGET_ATTRIBUTE_TABLE
101 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
103 #undef TARGET_ASM_ALIGNED_HI_OP
104 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
106 #undef TARGET_ASM_FUNCTION_EPILOGUE
107 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
108 #undef TARGET_ENCODE_SECTION_INFO
109 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
110 #undef TARGET_STRIP_NAME_ENCODING
111 #define TARGET_STRIP_NAME_ENCODING h8300_strip_name_encoding
113 #undef TARGET_INSERT_ATTRIBUTES
114 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
116 struct gcc_target targetm = TARGET_INITIALIZER;
118 /* See below where shifts are handled for explanation of this enum. */
128 /* Symbols of the various shifts which can be used as indices. */
132 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
135 /* Macros to keep the shift algorithm tables small. */
136 #define INL SHIFT_INLINE
137 #define ROT SHIFT_ROT_AND
138 #define LOP SHIFT_LOOP
139 #define SPC SHIFT_SPECIAL
141 /* The shift algorithms for each machine, mode, shift type, and shift
142 count are defined below. The three tables below correspond to
143 QImode, HImode, and SImode, respectively. Each table is organized
144 by, in the order of indices, machine, shift type, and shift count. */
146 static enum shift_alg shift_alg_qi[3][3][8] = {
149 /* 0 1 2 3 4 5 6 7 */
150 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
151 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
152 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
156 /* 0 1 2 3 4 5 6 7 */
157 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
158 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
159 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
163 /* 0 1 2 3 4 5 6 7 */
164 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
165 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
166 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
170 static enum shift_alg shift_alg_hi[3][3][16] = {
173 /* 0 1 2 3 4 5 6 7 */
174 /* 8 9 10 11 12 13 14 15 */
175 { INL, INL, INL, INL, INL, INL, INL, SPC,
176 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
177 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
178 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
179 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
180 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
184 /* 0 1 2 3 4 5 6 7 */
185 /* 8 9 10 11 12 13 14 15 */
186 { INL, INL, INL, INL, INL, INL, INL, SPC,
187 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
188 { INL, INL, INL, INL, INL, INL, INL, SPC,
189 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
190 { INL, INL, INL, INL, INL, INL, INL, SPC,
191 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
195 /* 0 1 2 3 4 5 6 7 */
196 /* 8 9 10 11 12 13 14 15 */
197 { INL, INL, INL, INL, INL, INL, INL, INL,
198 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
199 { INL, INL, INL, INL, INL, INL, INL, INL,
200 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
201 { INL, INL, INL, INL, INL, INL, INL, INL,
202 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
206 static enum shift_alg shift_alg_si[3][3][32] = {
209 /* 0 1 2 3 4 5 6 7 */
210 /* 8 9 10 11 12 13 14 15 */
211 /* 16 17 18 19 20 21 22 23 */
212 /* 24 25 26 27 28 29 30 31 */
213 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
214 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
215 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
216 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
217 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
218 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
219 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
220 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
221 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
222 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
223 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
224 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
228 /* 0 1 2 3 4 5 6 7 */
229 /* 8 9 10 11 12 13 14 15 */
230 /* 16 17 18 19 20 21 22 23 */
231 /* 24 25 26 27 28 29 30 31 */
232 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
233 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
234 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
235 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
236 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
237 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
238 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
239 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
240 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
241 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
242 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
243 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
247 /* 0 1 2 3 4 5 6 7 */
248 /* 8 9 10 11 12 13 14 15 */
249 /* 16 17 18 19 20 21 22 23 */
250 /* 24 25 26 27 28 29 30 31 */
251 { INL, INL, INL, INL, INL, INL, INL, INL,
252 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
253 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
254 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
255 { INL, INL, INL, INL, INL, INL, INL, INL,
256 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
257 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
258 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
259 { INL, INL, INL, INL, INL, INL, INL, INL,
260 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
261 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
262 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
278 /* Initialize various cpu specific globals at start up. */
283 static const char *const h8_push_ops[2] = { "push" , "push.l" };
284 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
285 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
289 cpu_type = (int) CPU_H8300;
290 h8_reg_names = names_big;
294 /* For this we treat the H8/300H and H8S the same. */
295 cpu_type = (int) CPU_H8300H;
296 h8_reg_names = names_extended;
298 h8_push_op = h8_push_ops[cpu_type];
299 h8_pop_op = h8_pop_ops[cpu_type];
300 h8_mov_op = h8_mov_ops[cpu_type];
302 if (!TARGET_H8300S && TARGET_MAC)
304 error ("-ms2600 is used without -ms");
305 target_flags |= MASK_H8300S;
308 if (TARGET_H8300 && TARGET_NORMAL_MODE)
310 error ("-mn is used without -mh or -ms");
311 target_flags ^= MASK_NORMAL_MODE;
314 /* Some of the shifts are optimized for speed by default.
315 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
316 If optimizing for size, change shift_alg for those shift to
321 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
322 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
324 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
326 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
327 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
329 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
330 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
333 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
334 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
336 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
337 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
339 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
340 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
341 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
342 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
345 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
354 static const char *const names_small[] = {
355 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
356 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
359 return names_small[REGNO (x) * 2 + b];
362 /* REGNO must be saved/restored across calls if this macro is true. */
364 #define WORD_REG_USED(regno) \
366 /* No need to save registers if this function will not return. */ \
367 && ! TREE_THIS_VOLATILE (current_function_decl) \
369 /* Save any call saved register that was used. */ \
370 || (regs_ever_live[regno] && !call_used_regs[regno]) \
371 /* Save the frame pointer if it was used. */ \
372 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
373 /* Save any register used in an interrupt handler. */ \
374 || (h8300_current_function_interrupt_function_p () \
375 && regs_ever_live[regno]) \
376 /* Save call clobbered registers in non-leaf interrupt \
378 || (h8300_current_function_interrupt_function_p () \
379 && call_used_regs[regno] \
380 && !current_function_is_leaf)))
382 /* Output assembly language to FILE for the operation OP with operand size
383 SIZE to adjust the stack pointer. */
390 /* H8/300 cannot add/subtract a large constant with a single
391 instruction. If a temporary register is available, load the
392 constant to it and then do the addition. */
395 && !h8300_current_function_interrupt_function_p ()
396 && !(current_function_needs_context && sign < 0))
399 rtx r3 = gen_rtx_REG (Pmode, 3);
400 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
401 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
402 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
406 /* The stack adjustment made here is further optimized by the
407 splitter. In case of H8/300, the splitter always splits the
408 addition emitted here to make the adjustment
410 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
411 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
415 /* Round up frame size SIZE. */
418 round_frame_size (size)
421 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
422 & -STACK_BOUNDARY / BITS_PER_UNIT);
425 /* Compute which registers to push/pop.
426 Return a bit vector of registers. */
429 compute_saved_regs ()
431 unsigned int saved_regs = 0;
434 /* Construct a bit vector of registers to be pushed/popped. */
435 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
437 if (WORD_REG_USED (regno))
438 saved_regs |= 1 << regno;
441 /* Don't push/pop the frame pointer as it is treated separately. */
442 if (frame_pointer_needed)
443 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
448 /* Emit an insn to push register RN. */
454 rtx reg = gen_rtx_REG (word_mode, rn);
458 x = gen_push_h8300 (reg);
460 x = gen_push_h8300hs (reg);
462 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
465 /* Emit an insn to pop register RN. */
471 rtx reg = gen_rtx_REG (word_mode, rn);
475 x = gen_pop_h8300 (reg);
477 x = gen_pop_h8300hs (reg);
479 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
482 /* This is what the stack looks like after the prolog of
483 a function with a frame has been set up:
489 <saved registers> <- sp
491 This is what the stack looks like after the prolog of
492 a function which doesn't have a frame:
497 <saved registers> <- sp
500 /* Generate RTL code for the function prologue. */
503 h8300_expand_prologue ()
509 /* If the current function has the OS_Task attribute set, then
510 we have a naked prologue. */
511 if (h8300_os_task_function_p (current_function_decl))
514 if (h8300_monitor_function_p (current_function_decl))
515 /* My understanding of monitor functions is they act just like
516 interrupt functions, except the prologue must mask
518 emit_insn (gen_monitor_prologue ());
520 if (frame_pointer_needed)
523 push (FRAME_POINTER_REGNUM);
524 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
527 /* Leave room for locals. */
528 dosize (-1, round_frame_size (get_frame_size ()));
530 /* Push the rest of the registers in ascending order. */
531 saved_regs = compute_saved_regs ();
532 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
535 if (saved_regs & (1 << regno))
539 /* See how many registers we can push at the same time. */
540 if ((regno == 0 || regno == 4)
541 && ((saved_regs >> regno) & 0x0f) == 0x0f)
544 else if ((regno == 0 || regno == 4)
545 && ((saved_regs >> regno) & 0x07) == 0x07)
548 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
549 && ((saved_regs >> regno) & 0x03) == 0x03)
559 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
560 gen_rtx_REG (SImode, regno + 1)));
563 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
564 gen_rtx_REG (SImode, regno + 1),
565 gen_rtx_REG (SImode, regno + 2)));
568 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
569 gen_rtx_REG (SImode, regno + 1),
570 gen_rtx_REG (SImode, regno + 2),
571 gen_rtx_REG (SImode, regno + 3)));
581 h8300_can_use_return_insn_p ()
583 return (reload_completed
584 && !frame_pointer_needed
585 && get_frame_size () == 0
586 && compute_saved_regs () == 0);
589 /* Generate RTL code for the function epilogue. */
592 h8300_expand_epilogue ()
598 if (h8300_os_task_function_p (current_function_decl))
599 /* OS_Task epilogues are nearly naked -- they just have an
603 /* Pop the saved registers in descending order. */
604 saved_regs = compute_saved_regs ();
605 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
608 if (saved_regs & (1 << regno))
612 /* See how many registers we can pop at the same time. */
613 if ((regno == 7 || regno == 3)
614 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
617 else if ((regno == 6 || regno == 2)
618 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
621 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
622 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
632 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
633 gen_rtx_REG (SImode, regno)));
636 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
637 gen_rtx_REG (SImode, regno - 1),
638 gen_rtx_REG (SImode, regno)));
641 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
642 gen_rtx_REG (SImode, regno - 2),
643 gen_rtx_REG (SImode, regno - 1),
644 gen_rtx_REG (SImode, regno)));
652 /* Deallocate locals. */
653 dosize (1, round_frame_size (get_frame_size ()));
655 /* Pop frame pointer if we had one. */
656 if (frame_pointer_needed)
657 pop (FRAME_POINTER_REGNUM);
660 /* Output assembly language code for the function epilogue. */
663 h8300_output_function_epilogue (file, size)
664 FILE *file ATTRIBUTE_UNUSED;
665 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
670 /* Return nonzero if the current function is an interrupt
674 h8300_current_function_interrupt_function_p ()
676 return (h8300_interrupt_function_p (current_function_decl)
677 || h8300_monitor_function_p (current_function_decl));
680 /* Output assembly code for the start of the file. */
683 asm_file_start (file)
686 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
687 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
690 fprintf (file, "; -Os\n");
692 fprintf (file, "; -O%d\n", optimize);
694 fprintf (file, "\n\t.h8300h\n");
695 else if (TARGET_H8300S)
696 fprintf (file, "\n\t.h8300s\n");
698 fprintf (file, "\n\n");
699 output_file_directive (file, main_input_filename);
702 /* Output assembly language code for the end of file. */
708 fprintf (file, "\t.end\n");
711 /* Return true if OP is a valid source operand for an integer move
715 general_operand_src (op, mode)
717 enum machine_mode mode;
719 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
721 return general_operand (op, mode);
724 /* Return true if OP is a valid destination operand for an integer move
728 general_operand_dst (op, mode)
730 enum machine_mode mode;
732 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
734 return general_operand (op, mode);
737 /* Return true if OP is a constant that contains only one 1 in its
738 binary representation. */
741 single_one_operand (operand, mode)
743 enum machine_mode mode ATTRIBUTE_UNUSED;
745 if (GET_CODE (operand) == CONST_INT)
747 /* We really need to do this masking because 0x80 in QImode is
748 represented as -128 for example. */
749 unsigned HOST_WIDE_INT mask =
750 (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
751 ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
752 : ~(unsigned HOST_WIDE_INT) 0;
753 unsigned HOST_WIDE_INT value = INTVAL (operand);
755 if (exact_log2 (value & mask) >= 0)
762 /* Return true if OP is a constant that contains only one 0 in its
763 binary representation. */
766 single_zero_operand (operand, mode)
768 enum machine_mode mode ATTRIBUTE_UNUSED;
770 if (GET_CODE (operand) == CONST_INT)
772 /* We really need to do this masking because 0x80 in QImode is
773 represented as -128 for example. */
774 unsigned HOST_WIDE_INT mask =
775 (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
776 ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
777 : ~(unsigned HOST_WIDE_INT) 0;
778 unsigned HOST_WIDE_INT value = INTVAL (operand);
780 if (exact_log2 (~value & mask) >= 0)
787 /* Return true if OP is a valid call operand. */
790 call_insn_operand (op, mode)
792 enum machine_mode mode ATTRIBUTE_UNUSED;
794 if (GET_CODE (op) == MEM)
796 rtx inside = XEXP (op, 0);
797 if (register_operand (inside, Pmode))
799 if (CONSTANT_ADDRESS_P (inside))
805 /* Return 1 if an addition/subtraction of a constant integer can be
806 transformed into two consecutive adds/subs that are faster than the
807 straightforward way. Otherwise, return 0. */
810 two_insn_adds_subs_operand (op, mode)
812 enum machine_mode mode;
814 if (GET_CODE (op) == CONST_INT)
816 HOST_WIDE_INT value = INTVAL (op);
818 /* Force VALUE to be positive so that we do not have to consider
819 the negative case. */
822 if (TARGET_H8300H || TARGET_H8300S)
824 /* A constant addition/subtraction takes 2 states in QImode,
825 4 states in HImode, and 6 states in SImode. Thus, the
826 only case we can win is when SImode is used, in which
827 case, two adds/subs are used, taking 4 states. */
837 /* We do not profit directly by splitting addition or
838 subtraction of 3 and 4. However, since these are
839 implemented as a sequence of adds or subs, they do not
840 clobber (cc0) unlike a sequence of add.b and add.x. */
851 /* Split an add of a small constant into two adds/subs insns.
853 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
854 instead of adds/subs. */
857 split_adds_subs (mode, operands, use_incdec_p)
858 enum machine_mode mode;
862 HOST_WIDE_INT val = INTVAL (operands[1]);
863 rtx reg = operands[0];
864 HOST_WIDE_INT sign = 1;
865 HOST_WIDE_INT amount;
866 rtx (*gen_last) (rtx, rtx, rtx);
867 rtx (*gen_normal) (rtx, rtx, rtx);
869 /* Force VAL to be positive so that we do not have to consider the
880 gen_normal = gen_addhi3;
881 gen_last = gen_addhi3_incdec;
885 gen_normal = gen_addsi3;
886 gen_last = gen_addsi3_incdec;
893 /* Try different amounts in descending order. */
894 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
898 for (; val >= amount; val -= amount)
900 /* If requested, generate the last insn using inc/dec. */
901 if (use_incdec_p && amount <= 2 && val == amount)
902 emit_insn (gen_last (reg, reg, GEN_INT (sign * amount)));
904 emit_insn (gen_normal (reg, reg, GEN_INT (sign * amount)));
911 /* Return true if OP is a valid call operand, and OP represents
912 an operand for a small call (4 bytes instead of 6 bytes). */
915 small_call_insn_operand (op, mode)
917 enum machine_mode mode ATTRIBUTE_UNUSED;
919 if (GET_CODE (op) == MEM)
921 rtx inside = XEXP (op, 0);
923 /* Register indirect is a small call. */
924 if (register_operand (inside, Pmode))
927 /* A call through the function vector is a small
929 if (GET_CODE (inside) == SYMBOL_REF
930 && SYMBOL_REF_FLAG (inside))
933 /* Otherwise it's a large call. */
937 /* Return true if OP is a valid jump operand. */
940 jump_address_operand (op, mode)
942 enum machine_mode mode;
944 if (GET_CODE (op) == REG)
945 return mode == Pmode;
947 if (GET_CODE (op) == MEM)
949 rtx inside = XEXP (op, 0);
950 if (register_operand (inside, Pmode))
952 if (CONSTANT_ADDRESS_P (inside))
958 /* Recognize valid operands for bit-field instructions. */
960 extern int rtx_equal_function_value_matters;
963 bit_operand (op, mode)
965 enum machine_mode mode;
967 /* We can accept any general operand, except that MEM operands must
968 be limited to those that use addresses valid for the 'U' constraint. */
969 if (!general_operand (op, mode))
972 /* Accept any mem during RTL generation. Otherwise, the code that does
973 insv and extzv will think that we can not handle memory. However,
974 to avoid reload problems, we only accept 'U' MEM operands after RTL
975 generation. This means that any named pattern which uses this predicate
976 must force its operands to match 'U' before emitting RTL. */
978 if (GET_CODE (op) == REG)
980 if (GET_CODE (op) == SUBREG)
982 if (!rtx_equal_function_value_matters)
983 /* We're building rtl. */
984 return GET_CODE (op) == MEM;
986 return (GET_CODE (op) == MEM
987 && EXTRA_CONSTRAINT (op, 'U'));
991 bit_memory_operand (op, mode)
993 enum machine_mode mode ATTRIBUTE_UNUSED;
995 return (GET_CODE (op) == MEM
996 && EXTRA_CONSTRAINT (op, 'U'));
999 /* Handle machine specific pragmas for compatibility with existing
1000 compilers for the H8/300.
1002 pragma saveall generates prologue/epilogue code which saves and
1003 restores all the registers on function entry.
1005 pragma interrupt saves and restores all registers, and exits with
1006 an rte instruction rather than an rts. A pointer to a function
1007 with this attribute may be safely used in an interrupt vector. */
1010 h8300_pr_interrupt (pfile)
1011 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1013 pragma_interrupt = 1;
1017 h8300_pr_saveall (pfile)
1018 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1023 /* If the next function argument with MODE and TYPE is to be passed in
1024 a register, return a reg RTX for the hard register in which to pass
1025 the argument. CUM represents the state after the last argument.
1026 If the argument is to be pushed, NULL_RTX is returned. */
1029 function_arg (cum, mode, type, named)
1030 CUMULATIVE_ARGS *cum;
1031 enum machine_mode mode;
1035 static const char *const hand_list[] = {
1054 rtx result = NULL_RTX;
1058 /* Never pass unnamed arguments in registers. */
1062 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1063 if (TARGET_QUICKCALL)
1066 /* If calling hand written assembler, use 4 regs of args. */
1069 const char * const *p;
1071 fname = XSTR (cum->libcall, 0);
1073 /* See if this libcall is one of the hand coded ones. */
1074 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1085 if (mode == BLKmode)
1086 size = int_size_in_bytes (type);
1088 size = GET_MODE_SIZE (mode);
1090 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1091 && cum->nbytes / UNITS_PER_WORD <= 3)
1092 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1098 /* Return the cost of the rtx R with code CODE. */
1101 const_costs (r, c, outer_code)
1104 enum rtx_code outer_code;
1117 return 0 + (outer_code == SET);
1120 if (TARGET_H8300H || TARGET_H8300S)
1121 return 0 + (outer_code == SET);
1147 if (GET_MODE (x) == QImode)
1150 if (GET_MODE (x) != HImode
1151 && GET_MODE (x) != SImode)
1156 operands[2] = XEXP (x, 1);
1158 return compute_logical_op_length (GET_MODE (x), operands);
1162 h8300_shift_costs (x)
1167 if (GET_MODE (x) != QImode
1168 && GET_MODE (x) != HImode
1169 && GET_MODE (x) != SImode)
1174 operands[2] = XEXP (x, 1);
1176 return compute_a_shift_length (NULL, operands);
1179 /* Documentation for the machine specific operand escapes:
1181 'E' like s but negative.
1182 'F' like t but negative.
1183 'G' constant just the negative
1184 'R' print operand as a byte:8 address if appropriate, else fall back to
1186 'S' print operand as a long word
1187 'T' print operand as a word
1188 'V' find the set bit, and print its number.
1189 'W' find the clear bit, and print its number.
1190 'X' print operand as a byte
1191 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1192 If this operand isn't a register, fall back to 'R' handling.
1194 'b' print the bit opcode
1195 'e' first word of 32 bit value - if reg, then least reg. if mem
1196 then least. if const then most sig word
1197 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1198 then +2. if const then least sig word
1199 'j' print operand as condition code.
1200 'k' print operand as reverse condition code.
1201 's' print as low byte of 16 bit value
1202 't' print as high byte of 16 bit value
1203 'w' print as low byte of 32 bit value
1204 'x' print as 2nd byte of 32 bit value
1205 'y' print as 3rd byte of 32 bit value
1206 'z' print as msb of 32 bit value
1209 /* Return assembly language string which identifies a comparison type. */
1242 /* Print operand X using operand code CODE to assembly language output file
1246 print_operand (file, x, code)
1251 /* This is used for communication between codes V,W,Z and Y. */
1257 switch (GET_CODE (x))
1260 fprintf (file, "%sl", names_big[REGNO (x)]);
1263 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1270 switch (GET_CODE (x))
1273 fprintf (file, "%sh", names_big[REGNO (x)]);
1276 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1283 if (GET_CODE (x) != CONST_INT)
1285 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1288 if (GET_CODE (x) == REG)
1289 fprintf (file, "%s", names_extended[REGNO (x)]);
1294 if (GET_CODE (x) == REG)
1295 fprintf (file, "%s", names_big[REGNO (x)]);
1300 bitint = exact_log2 (INTVAL (x) & 0xff);
1303 fprintf (file, "#%d", bitint);
1306 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1309 fprintf (file, "#%d", bitint);
1313 if (GET_CODE (x) == REG)
1314 fprintf (file, "%s", byte_reg (x, 0));
1321 if (GET_CODE (x) == REG)
1322 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1324 print_operand (file, x, 'R');
1328 bitint = INTVAL (x);
1329 fprintf (file, "#%d", bitint & 7);
1332 switch (GET_CODE (x))
1335 fprintf (file, "bor");
1338 fprintf (file, "bxor");
1341 fprintf (file, "band");
1348 switch (GET_CODE (x))
1352 fprintf (file, "%s", names_big[REGNO (x)]);
1354 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1357 print_operand (file, x, 0);
1360 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1366 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1367 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1368 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1377 switch (GET_CODE (x))
1381 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1383 fprintf (file, "%s", names_big[REGNO (x)]);
1386 x = adjust_address (x, HImode, 2);
1387 print_operand (file, x, 0);
1390 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1396 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1397 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1398 fprintf (file, "#%ld", (val & 0xffff));
1406 fputs (cond_string (GET_CODE (x)), file);
1409 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1412 if (GET_CODE (x) == CONST_INT)
1413 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1415 fprintf (file, "%s", byte_reg (x, 0));
1418 if (GET_CODE (x) == CONST_INT)
1419 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1421 fprintf (file, "%s", byte_reg (x, 1));
1424 if (GET_CODE (x) != CONST_INT)
1426 fprintf (file, "%ld", INTVAL (x));
1429 if (GET_CODE (x) == CONST_INT)
1430 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1432 fprintf (file, "%s",
1433 byte_reg (x, TARGET_H8300 ? 2 : 0));
1436 if (GET_CODE (x) == CONST_INT)
1437 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1439 fprintf (file, "%s",
1440 byte_reg (x, TARGET_H8300 ? 3 : 1));
1443 if (GET_CODE (x) == CONST_INT)
1444 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1446 fprintf (file, "%s", byte_reg (x, 0));
1449 if (GET_CODE (x) == CONST_INT)
1450 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1452 fprintf (file, "%s", byte_reg (x, 1));
1457 switch (GET_CODE (x))
1460 switch (GET_MODE (x))
1463 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1464 fprintf (file, "%s", byte_reg (x, 0));
1465 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1466 fprintf (file, "%s", names_big[REGNO (x)]);
1470 fprintf (file, "%s", names_big[REGNO (x)]);
1474 fprintf (file, "%s", names_extended[REGNO (x)]);
1483 rtx addr = XEXP (x, 0);
1485 fprintf (file, "@");
1486 output_address (addr);
1488 /* We fall back from smaller addressing to larger
1489 addressing in various ways depending on CODE. */
1493 /* Used for mov.b and bit operations. */
1494 if (h8300_eightbit_constant_address_p (addr))
1496 fprintf (file, ":8");
1500 /* Fall through. We should not get here if we are
1501 processing bit operations on H8/300 or H8/300H
1502 because 'U' constraint does not allow bit
1503 operations on the tiny area on these machines. */
1507 /* Used for mov.w and mov.l. */
1508 if (h8300_tiny_constant_address_p (addr))
1509 fprintf (file, ":16");
1521 fprintf (file, "#");
1522 print_operand_address (file, x);
1528 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1529 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1530 fprintf (file, "#%ld", val);
1539 /* Output assembly language output for the address ADDR to FILE. */
1542 print_operand_address (file, addr)
1546 switch (GET_CODE (addr))
1549 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1553 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1557 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1561 fprintf (file, "(");
1562 if (GET_CODE (XEXP (addr, 0)) == REG)
1565 print_operand_address (file, XEXP (addr, 1));
1566 fprintf (file, ",");
1567 print_operand_address (file, XEXP (addr, 0));
1572 print_operand_address (file, XEXP (addr, 0));
1573 fprintf (file, "+");
1574 print_operand_address (file, XEXP (addr, 1));
1576 fprintf (file, ")");
1581 /* Since the H8/300 only has 16 bit pointers, negative values are also
1582 those >= 32768. This happens for example with pointer minus a
1583 constant. We don't want to turn (char *p - 2) into
1584 (char *p + 65534) because loop unrolling can build upon this
1585 (IE: char *p + 131068). */
1586 int n = INTVAL (addr);
1588 n = (int) (short) n;
1589 fprintf (file, "%d", n);
1594 output_addr_const (file, addr);
1599 /* Output all insn addresses and their sizes into the assembly language
1600 output file. This is helpful for debugging whether the length attributes
1601 in the md file are correct. This is not meant to be a user selectable
1605 final_prescan_insn (insn, operand, num_operands)
1606 rtx insn, *operand ATTRIBUTE_UNUSED;
1607 int num_operands ATTRIBUTE_UNUSED;
1609 /* This holds the last insn address. */
1610 static int last_insn_address = 0;
1612 const int uid = INSN_UID (insn);
1614 if (TARGET_RTL_DUMP)
1616 fprintf (asm_out_file, "\n****************");
1617 print_rtl (asm_out_file, PATTERN (insn));
1618 fprintf (asm_out_file, "\n");
1621 if (TARGET_ADDRESSES)
1623 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1624 INSN_ADDRESSES (uid) - last_insn_address);
1625 last_insn_address = INSN_ADDRESSES (uid);
1629 /* Prepare for an SI sized move. */
1635 rtx src = operands[1];
1636 rtx dst = operands[0];
1637 if (!reload_in_progress && !reload_completed)
1639 if (!register_operand (dst, GET_MODE (dst)))
1641 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1642 emit_move_insn (tmp, src);
1649 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1650 Define the offset between two registers, one to be eliminated, and
1651 the other its replacement, at the start of a routine. */
1654 h8300_initial_elimination_offset (from, to)
1659 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1660 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1661 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1662 offset = frame_pointer_needed * UNITS_PER_WORD;
1667 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1668 if (WORD_REG_USED (regno))
1669 offset += UNITS_PER_WORD;
1671 /* See the comments for get_frame_size. We need to round it up to
1674 offset += round_frame_size (get_frame_size ());
1676 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1677 offset += UNITS_PER_WORD; /* Skip saved PC */
1680 if ((TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE)
1687 h8300_return_addr_rtx (count, frame)
1694 ret = gen_rtx_MEM (Pmode,
1695 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1696 else if (flag_omit_frame_pointer)
1699 ret = gen_rtx_MEM (Pmode,
1700 memory_address (Pmode,
1701 plus_constant (frame, UNITS_PER_WORD)));
1702 set_mem_alias_set (ret, get_frame_alias_set ());
1706 /* Update the condition code from the insn. */
1709 notice_update_cc (body, insn)
1713 switch (get_attr_cc (insn))
1716 /* Insn does not affect CC at all. */
1720 /* Insn does not change CC, but the 0'th operand has been changed. */
1721 if (cc_status.value1 != 0
1722 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1723 cc_status.value1 = 0;
1724 if (cc_status.value2 != 0
1725 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1726 cc_status.value2 = 0;
1730 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1731 The V flag is unusable. The C flag may or may not be known but
1732 that's ok because alter_cond will change tests to use EQ/NE. */
1734 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1735 cc_status.value1 = recog_data.operand[0];
1739 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1740 The C flag may or may not be known but that's ok because
1741 alter_cond will change tests to use EQ/NE. */
1743 cc_status.flags |= CC_NO_CARRY;
1744 cc_status.value1 = recog_data.operand[0];
1745 if (GET_CODE (body) == SET && REG_P (SET_SRC (body)))
1746 cc_status.value2 = SET_SRC (body);
1750 /* The insn is a compare instruction. */
1752 cc_status.value1 = SET_SRC (body);
1756 /* Insn doesn't leave CC in a usable state. */
1762 /* Return nonzero if X is a stack pointer. */
1765 stack_pointer_operand (x, mode)
1767 enum machine_mode mode ATTRIBUTE_UNUSED;
1769 return x == stack_pointer_rtx;
1772 /* Return nonzero if X is a constant whose absolute value is no
1776 const_int_le_2_operand (x, mode)
1778 enum machine_mode mode ATTRIBUTE_UNUSED;
1780 return (GET_CODE (x) == CONST_INT
1781 && abs (INTVAL (x)) <= 2);
1784 /* Return nonzero if X is a constant whose absolute value is no
1788 const_int_le_6_operand (x, mode)
1790 enum machine_mode mode ATTRIBUTE_UNUSED;
1792 return (GET_CODE (x) == CONST_INT
1793 && abs (INTVAL (x)) <= 6);
1796 /* Return nonzero if X is a constant whose absolute value is greater
1800 const_int_gt_2_operand (x, mode)
1802 enum machine_mode mode ATTRIBUTE_UNUSED;
1804 return (GET_CODE (x) == CONST_INT
1805 && abs (INTVAL (x)) > 2);
1808 /* Return nonzero if X is a constant whose absolute value is no
1812 const_int_ge_8_operand (x, mode)
1814 enum machine_mode mode ATTRIBUTE_UNUSED;
1816 return (GET_CODE (x) == CONST_INT
1817 && abs (INTVAL (x)) >= 8);
1820 /* Return nonzero if X is a constant expressible in QImode. */
1823 const_int_qi_operand (x, mode)
1825 enum machine_mode mode ATTRIBUTE_UNUSED;
1827 return (GET_CODE (x) == CONST_INT
1828 && (INTVAL (x) & 0xff) == INTVAL (x));
1831 /* Return nonzero if X is a constant expressible in HImode. */
1834 const_int_hi_operand (x, mode)
1836 enum machine_mode mode ATTRIBUTE_UNUSED;
1838 return (GET_CODE (x) == CONST_INT
1839 && (INTVAL (x) & 0xffff) == INTVAL (x));
1842 /* Return nonzero if X is a constant suitable for inc/dec. */
1845 incdec_operand (x, mode)
1847 enum machine_mode mode ATTRIBUTE_UNUSED;
1849 return (GET_CODE (x) == CONST_INT
1850 && (CONST_OK_FOR_M (INTVAL (x))
1851 || CONST_OK_FOR_O (INTVAL (x))));
1854 /* Return nonzero if X is either EQ or NE. */
1857 eqne_operator (x, mode)
1859 enum machine_mode mode ATTRIBUTE_UNUSED;
1861 enum rtx_code code = GET_CODE (x);
1863 return (code == EQ || code == NE);
1866 /* Recognize valid operators for bit instructions. */
1869 bit_operator (x, mode)
1871 enum machine_mode mode ATTRIBUTE_UNUSED;
1873 enum rtx_code code = GET_CODE (x);
1881 output_plussi (operands)
1884 enum machine_mode mode = GET_MODE (operands[0]);
1891 /* Currently we do not support H8/300 here yet. */
1896 if (GET_CODE (operands[2]) == REG)
1897 return "add.l\t%S2,%S0";
1899 if (GET_CODE (operands[2]) == CONST_INT)
1901 HOST_WIDE_INT intval = INTVAL (operands[2]);
1903 /* See if we can finish with 2 bytes. */
1905 switch (intval & 0xffffffff)
1910 return "adds\t%2,%S0";
1915 return "subs\t%G2,%S0";
1919 operands[2] = GEN_INT (intval >> 16);
1920 return "inc.w\t%2,%e0";
1924 operands[2] = GEN_INT (intval >> 16);
1925 return "dec.w\t%G2,%e0";
1928 /* See if we can finish with 4 bytes. */
1929 if ((intval & 0xffff) == 0)
1931 operands[2] = GEN_INT (intval >> 16);
1932 return "add.w\t%2,%e0";
1936 return "add.l\t%S2,%S0";
1941 compute_plussi_length (operands)
1944 enum machine_mode mode = GET_MODE (operands[0]);
1951 /* Currently we do not support H8/300 here yet. */
1956 if (GET_CODE (operands[2]) == REG)
1959 if (GET_CODE (operands[2]) == CONST_INT)
1961 HOST_WIDE_INT intval = INTVAL (operands[2]);
1963 /* See if we can finish with 2 bytes. */
1965 switch (intval & 0xffffffff)
1986 /* See if we can finish with 4 bytes. */
1987 if ((intval & 0xffff) == 0)
1996 compute_plussi_cc (operands)
1999 enum machine_mode mode = GET_MODE (operands[0]);
2006 /* Currently we do not support H8/300 here yet. */
2011 if (GET_CODE (operands[2]) == REG)
2014 if (GET_CODE (operands[2]) == CONST_INT)
2016 HOST_WIDE_INT intval = INTVAL (operands[2]);
2018 /* See if we can finish with 2 bytes. */
2020 switch (intval & 0xffffffff)
2025 return CC_NONE_0HIT;
2030 return CC_NONE_0HIT;
2041 /* See if we can finish with 4 bytes. */
2042 if ((intval & 0xffff) == 0)
2051 output_logical_op (mode, operands)
2052 enum machine_mode mode;
2055 /* Figure out the logical op that we need to perform. */
2056 enum rtx_code code = GET_CODE (operands[3]);
2057 /* Pretend that every byte is affected if both operands are registers. */
2058 const unsigned HOST_WIDE_INT intval =
2059 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2060 ? INTVAL (operands[2]) : 0x55555555);
2061 /* The determinant of the algorithm. If we perform an AND, 0
2062 affects a bit. Otherwise, 1 affects a bit. */
2063 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2064 /* Break up DET into pieces. */
2065 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2066 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2067 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2068 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2069 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2070 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2071 int lower_half_easy_p = 0;
2072 int upper_half_easy_p = 0;
2073 /* The name of an insn. */
2095 /* First, see if we can finish with one insn. */
2096 if ((TARGET_H8300H || TARGET_H8300S)
2100 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2101 output_asm_insn (insn_buf, operands);
2105 /* Take care of the lower byte. */
2108 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2109 output_asm_insn (insn_buf, operands);
2111 /* Take care of the upper byte. */
2114 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2115 output_asm_insn (insn_buf, operands);
2120 if (TARGET_H8300H || TARGET_H8300S)
2122 /* Determine if the lower half can be taken care of in no more
2124 lower_half_easy_p = (b0 == 0
2126 || (code != IOR && w0 == 0xffff));
2128 /* Determine if the upper half can be taken care of in no more
2130 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2131 || (code == AND && w1 == 0xff00));
2134 /* Check if doing everything with one insn is no worse than
2135 using multiple insns. */
2136 if ((TARGET_H8300H || TARGET_H8300S)
2137 && w0 != 0 && w1 != 0
2138 && !(lower_half_easy_p && upper_half_easy_p))
2140 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2141 output_asm_insn (insn_buf, operands);
2145 /* Take care of the lower and upper words individually. For
2146 each word, we try different methods in the order of
2148 1) the special insn (in case of AND or XOR),
2149 2) the word-wise insn, and
2150 3) The byte-wise insn. */
2152 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2153 output_asm_insn ((code == AND)
2154 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2156 else if ((TARGET_H8300H || TARGET_H8300S)
2160 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2161 output_asm_insn (insn_buf, operands);
2167 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2168 output_asm_insn (insn_buf, operands);
2172 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2173 output_asm_insn (insn_buf, operands);
2178 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2179 output_asm_insn ((code == AND)
2180 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2182 else if ((TARGET_H8300H || TARGET_H8300S)
2186 output_asm_insn ("extu.w\t%e0", operands);
2188 else if (TARGET_H8300H || TARGET_H8300S)
2192 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2193 output_asm_insn (insn_buf, operands);
2200 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2201 output_asm_insn (insn_buf, operands);
2205 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2206 output_asm_insn (insn_buf, operands);
2218 compute_logical_op_length (mode, operands)
2219 enum machine_mode mode;
2222 /* Figure out the logical op that we need to perform. */
2223 enum rtx_code code = GET_CODE (operands[3]);
2224 /* Pretend that every byte is affected if both operands are registers. */
2225 const unsigned HOST_WIDE_INT intval =
2226 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2227 ? INTVAL (operands[2]) : 0x55555555);
2228 /* The determinant of the algorithm. If we perform an AND, 0
2229 affects a bit. Otherwise, 1 affects a bit. */
2230 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2231 /* Break up DET into pieces. */
2232 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2233 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2234 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2235 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2236 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2237 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2238 int lower_half_easy_p = 0;
2239 int upper_half_easy_p = 0;
2241 unsigned int length = 0;
2246 /* First, see if we can finish with one insn. */
2247 if ((TARGET_H8300H || TARGET_H8300S)
2251 if (REG_P (operands[2]))
2258 /* Take care of the lower byte. */
2262 /* Take care of the upper byte. */
2268 if (TARGET_H8300H || TARGET_H8300S)
2270 /* Determine if the lower half can be taken care of in no more
2272 lower_half_easy_p = (b0 == 0
2274 || (code != IOR && w0 == 0xffff));
2276 /* Determine if the upper half can be taken care of in no more
2278 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2279 || (code == AND && w1 == 0xff00));
2282 /* Check if doing everything with one insn is no worse than
2283 using multiple insns. */
2284 if ((TARGET_H8300H || TARGET_H8300S)
2285 && w0 != 0 && w1 != 0
2286 && !(lower_half_easy_p && upper_half_easy_p))
2288 if (REG_P (operands[2]))
2295 /* Take care of the lower and upper words individually. For
2296 each word, we try different methods in the order of
2298 1) the special insn (in case of AND or XOR),
2299 2) the word-wise insn, and
2300 3) The byte-wise insn. */
2302 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2306 else if ((TARGET_H8300H || TARGET_H8300S)
2322 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2326 else if ((TARGET_H8300H || TARGET_H8300S)
2332 else if (TARGET_H8300H || TARGET_H8300S)
2354 compute_logical_op_cc (mode, operands)
2355 enum machine_mode mode;
2358 /* Figure out the logical op that we need to perform. */
2359 enum rtx_code code = GET_CODE (operands[3]);
2360 /* Pretend that every byte is affected if both operands are registers. */
2361 const unsigned HOST_WIDE_INT intval =
2362 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2363 ? INTVAL (operands[2]) : 0x55555555);
2364 /* The determinant of the algorithm. If we perform an AND, 0
2365 affects a bit. Otherwise, 1 affects a bit. */
2366 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2367 /* Break up DET into pieces. */
2368 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2369 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2370 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2371 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2372 int lower_half_easy_p = 0;
2373 int upper_half_easy_p = 0;
2374 /* Condition code. */
2375 enum attr_cc cc = CC_CLOBBER;
2380 /* First, see if we can finish with one insn. */
2381 if ((TARGET_H8300H || TARGET_H8300S)
2389 if (TARGET_H8300H || TARGET_H8300S)
2391 /* Determine if the lower half can be taken care of in no more
2393 lower_half_easy_p = (b0 == 0
2395 || (code != IOR && w0 == 0xffff));
2397 /* Determine if the upper half can be taken care of in no more
2399 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2400 || (code == AND && w1 == 0xff00));
2403 /* Check if doing everything with one insn is no worse than
2404 using multiple insns. */
2405 if ((TARGET_H8300H || TARGET_H8300S)
2406 && w0 != 0 && w1 != 0
2407 && !(lower_half_easy_p && upper_half_easy_p))
2420 We devote a fair bit of code to getting efficient shifts since we
2421 can only shift one bit at a time on the H8/300 and H8/300H and only
2422 one or two bits at a time on the H8S.
2424 All shift code falls into one of the following ways of
2427 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2428 when a straight line shift is about the same size or smaller than
2431 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2432 off the bits we don't need. This is used when only a few of the
2433 bits in the original value will survive in the shifted value.
2435 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2436 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2437 shifts can be added if the shift count is slightly more than 8 or
2438 16. This case also includes other oddballs that are not worth
2441 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2443 For each shift count, we try to use code that has no trade-off
2444 between code size and speed whenever possible.
2446 If the trade-off is unavoidable, we try to be reasonable.
2447 Specifically, the fastest version is one instruction longer than
2448 the shortest version, we take the fastest version. We also provide
2449 the use a way to switch back to the shortest version with -Os.
2451 For the details of the shift algorithms for various shift counts,
2452 refer to shift_alg_[qhs]i. */
2455 nshift_operator (x, mode)
2457 enum machine_mode mode ATTRIBUTE_UNUSED;
2459 switch (GET_CODE (x))
2471 /* Emit code to do shifts. */
2474 expand_a_shift (mode, code, operands)
2475 enum machine_mode mode;
2479 emit_move_insn (operands[0], operands[1]);
2481 /* Need a loop to get all the bits we want - we generate the
2482 code at emit time, but need to allocate a scratch reg now. */
2484 emit_insn (gen_rtx_PARALLEL
2487 gen_rtx_SET (VOIDmode, operands[0],
2488 gen_rtx (code, mode, operands[0],
2490 gen_rtx_CLOBBER (VOIDmode,
2491 gen_rtx_SCRATCH (QImode)))));
2494 /* Symbols of the various modes which can be used as indices. */
2498 QIshift, HIshift, SIshift
2501 /* For single bit shift insns, record assembler and what bits of the
2502 condition code are valid afterwards (represented as various CC_FOO
2503 bits, 0 means CC isn't left in a usable state). */
2507 const char *const assembler;
2511 /* Assembler instruction shift table.
2513 These tables are used to look up the basic shifts.
2514 They are indexed by cpu, shift_type, and mode. */
2516 static const struct shift_insn shift_one[2][3][3] =
2522 { "shll\t%X0", CC_NO_CARRY },
2523 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2524 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
2526 /* SHIFT_LSHIFTRT */
2528 { "shlr\t%X0", CC_NO_CARRY },
2529 { "shlr\t%t0\n\trotxr\t%s0", 0 },
2530 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2532 /* SHIFT_ASHIFTRT */
2534 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2535 { "shar\t%t0\n\trotxr\t%s0", 0 },
2536 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2543 { "shll.b\t%X0", CC_NO_CARRY },
2544 { "shll.w\t%T0", CC_NO_CARRY },
2545 { "shll.l\t%S0", CC_NO_CARRY }
2547 /* SHIFT_LSHIFTRT */
2549 { "shlr.b\t%X0", CC_NO_CARRY },
2550 { "shlr.w\t%T0", CC_NO_CARRY },
2551 { "shlr.l\t%S0", CC_NO_CARRY }
2553 /* SHIFT_ASHIFTRT */
2555 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2556 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2557 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2562 static const struct shift_insn shift_two[3][3] =
2566 { "shll.b\t#2,%X0", CC_NO_CARRY },
2567 { "shll.w\t#2,%T0", CC_NO_CARRY },
2568 { "shll.l\t#2,%S0", CC_NO_CARRY }
2570 /* SHIFT_LSHIFTRT */
2572 { "shlr.b\t#2,%X0", CC_NO_CARRY },
2573 { "shlr.w\t#2,%T0", CC_NO_CARRY },
2574 { "shlr.l\t#2,%S0", CC_NO_CARRY }
2576 /* SHIFT_ASHIFTRT */
2578 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2579 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2580 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2584 /* Rotates are organized by which shift they'll be used in implementing.
2585 There's no need to record whether the cc is valid afterwards because
2586 it is the AND insn that will decide this. */
2588 static const char *const rotate_one[2][3][3] =
2595 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2598 /* SHIFT_LSHIFTRT */
2601 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2604 /* SHIFT_ASHIFTRT */
2607 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2619 /* SHIFT_LSHIFTRT */
2625 /* SHIFT_ASHIFTRT */
2634 static const char *const rotate_two[3][3] =
2642 /* SHIFT_LSHIFTRT */
2648 /* SHIFT_ASHIFTRT */
2657 /* Shift algorithm. */
2660 /* The number of bits to be shifted by shift1 and shift2. Valid
2661 when ALG is SHIFT_SPECIAL. */
2662 unsigned int remainder;
2664 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2665 const char *special;
2667 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2668 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2671 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2672 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2675 /* Valid CC flags. */
2679 static void get_shift_alg PARAMS ((enum shift_type,
2680 enum shift_mode, unsigned int,
2681 struct shift_info *));
2683 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2684 best algorithm for doing the shift. The assembler code is stored
2685 in the pointers in INFO. We achieve the maximum efficiency in most
2686 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2687 SImode in particular have a lot of room to optimize.
2689 We first determine the strategy of the shift algorithm by a table
2690 lookup. If that tells us to use a hand crafted assembly code, we
2691 go into the big switch statement to find what that is. Otherwise,
2692 we resort to a generic way, such as inlining. In either case, the
2693 result is returned through INFO. */
2696 get_shift_alg (shift_type, shift_mode, count, info)
2697 enum shift_type shift_type;
2698 enum shift_mode shift_mode;
2700 struct shift_info *info;
2704 /* Find the target CPU. */
2707 else if (TARGET_H8300H)
2712 /* Find the shift algorithm. */
2713 info->alg = SHIFT_LOOP;
2717 if (count < GET_MODE_BITSIZE (QImode))
2718 info->alg = shift_alg_qi[cpu][shift_type][count];
2722 if (count < GET_MODE_BITSIZE (HImode))
2723 info->alg = shift_alg_hi[cpu][shift_type][count];
2727 if (count < GET_MODE_BITSIZE (SImode))
2728 info->alg = shift_alg_si[cpu][shift_type][count];
2735 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2739 info->remainder = count;
2743 /* It is up to the caller to know that looping clobbers cc. */
2744 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2745 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2746 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2750 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2751 info->shift2 = rotate_two[shift_type][shift_mode];
2752 info->cc_valid_p = 0;
2756 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2757 info->remainder = 0;
2758 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2759 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2760 info->cc_valid_p = 0;
2764 /* Here we only deal with SHIFT_SPECIAL. */
2768 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2769 through the entire value. */
2770 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2772 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2784 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2786 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2788 case SHIFT_LSHIFTRT:
2790 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2792 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2794 case SHIFT_ASHIFTRT:
2795 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2799 else if (8 <= count && count <= 13)
2801 info->remainder = count - 8;
2806 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2808 case SHIFT_LSHIFTRT:
2811 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2812 info->shift1 = "shlr.b\t%s0";
2816 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
2819 case SHIFT_ASHIFTRT:
2822 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2823 info->shift1 = "shar.b\t%s0";
2824 info->shift2 = "shar.b\t#2,%s0";
2828 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2833 else if (count == 14)
2839 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2841 case SHIFT_LSHIFTRT:
2843 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2845 case SHIFT_ASHIFTRT:
2847 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2848 else if (TARGET_H8300H)
2849 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2850 else /* TARGET_H8300S */
2851 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.w\t#2,%T0\n\tshar.w\t#2,%T0\n\tshar.w\t#2,%T0";
2855 else if (count == 15)
2860 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
2862 case SHIFT_LSHIFTRT:
2863 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
2865 case SHIFT_ASHIFTRT:
2866 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2873 if (TARGET_H8300 && 8 <= count && count <= 9)
2875 info->remainder = count - 8;
2880 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2882 case SHIFT_LSHIFTRT:
2883 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2884 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
2886 case SHIFT_ASHIFTRT:
2887 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2891 else if (count == 8 && !TARGET_H8300)
2896 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2898 case SHIFT_LSHIFTRT:
2899 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2901 case SHIFT_ASHIFTRT:
2902 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2906 else if (count == 15 && TARGET_H8300)
2912 case SHIFT_LSHIFTRT:
2913 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\trotxl\t%y0,%y0";
2915 case SHIFT_ASHIFTRT:
2916 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
2920 else if (count == 15 && !TARGET_H8300)
2925 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
2927 case SHIFT_LSHIFTRT:
2928 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
2930 case SHIFT_ASHIFTRT:
2934 else if ((TARGET_H8300 && 16 <= count && count <= 20)
2935 || (TARGET_H8300H && 16 <= count && count <= 19)
2936 || (TARGET_H8300S && 16 <= count && count <= 21))
2938 info->remainder = count - 16;
2943 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2946 info->shift1 = "add.w\t%e0,%e0";
2950 info->shift1 = "shll.l\t%S0";
2951 info->shift2 = "shll.l\t#2,%S0";
2954 case SHIFT_LSHIFTRT:
2957 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2958 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
2962 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
2965 case SHIFT_ASHIFTRT:
2968 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2969 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
2973 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2978 else if (TARGET_H8300 && 24 <= count && count <= 28)
2980 info->remainder = count - 24;
2985 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
2986 info->shift1 = "shll.b\t%z0";
2988 case SHIFT_LSHIFTRT:
2989 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
2990 info->shift1 = "shlr.b\t%w0";
2992 case SHIFT_ASHIFTRT:
2993 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
2994 info->shift1 = "shar.b\t%w0";
2998 else if ((TARGET_H8300H && count == 24)
2999 || (TARGET_H8300S && 24 <= count && count <= 25))
3001 info->remainder = count - 24;
3006 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3007 info->shift1 = "shll.l\t%S0";
3008 info->shift2 = "shll.l\t#2,%S0";
3010 case SHIFT_LSHIFTRT:
3011 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3012 info->shift1 = "shlr.l\t%S0";
3013 info->shift2 = "shlr.l\t#2,%S0";
3015 case SHIFT_ASHIFTRT:
3016 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3017 info->shift1 = "shar.l\t%S0";
3018 info->shift2 = "shar.l\t#2,%S0";
3022 else if (!TARGET_H8300 && count == 28)
3028 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3030 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3034 case SHIFT_LSHIFTRT:
3036 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3038 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3042 case SHIFT_ASHIFTRT:
3046 else if (!TARGET_H8300 && count == 29)
3052 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3054 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3058 case SHIFT_LSHIFTRT:
3060 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3062 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3066 case SHIFT_ASHIFTRT:
3070 else if (!TARGET_H8300 && count == 30)
3076 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3078 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3082 case SHIFT_LSHIFTRT:
3084 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3086 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3090 case SHIFT_ASHIFTRT:
3094 else if (count == 31)
3101 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3103 case SHIFT_LSHIFTRT:
3104 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3106 case SHIFT_ASHIFTRT:
3107 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3116 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3118 case SHIFT_LSHIFTRT:
3119 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3121 case SHIFT_ASHIFTRT:
3122 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3135 info->shift2 = NULL;
3138 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3139 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3142 h8300_shift_needs_scratch_p (count, mode)
3144 enum machine_mode mode;
3149 if (GET_MODE_BITSIZE (mode) <= count)
3152 /* Find out the target CPU. */
3155 else if (TARGET_H8300H)
3160 /* Find the shift algorithm. */
3164 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3165 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3166 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3170 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3171 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3172 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3176 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3177 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3178 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3185 /* On H8/300H and H8S, count == 8 uses the scratch register. */
3186 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3187 || (!TARGET_H8300 && mode == SImode && count == 8));
3190 /* Emit the assembler code for doing shifts. */
3193 output_a_shift (operands)
3196 static int loopend_lab;
3197 rtx shift = operands[3];
3198 enum machine_mode mode = GET_MODE (shift);
3199 enum rtx_code code = GET_CODE (shift);
3200 enum shift_type shift_type;
3201 enum shift_mode shift_mode;
3202 struct shift_info info;
3209 shift_mode = QIshift;
3212 shift_mode = HIshift;
3215 shift_mode = SIshift;
3224 shift_type = SHIFT_ASHIFTRT;
3227 shift_type = SHIFT_LSHIFTRT;
3230 shift_type = SHIFT_ASHIFT;
3236 if (GET_CODE (operands[2]) != CONST_INT)
3238 /* This case must be taken care of by one of the two splitters
3239 that convert a variable shift into a loop. */
3244 int n = INTVAL (operands[2]);
3246 /* If the count is negative, make it 0. */
3249 /* If the count is too big, truncate it.
3250 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3251 do the intuitive thing. */
3252 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3253 n = GET_MODE_BITSIZE (mode);
3255 get_shift_alg (shift_type, shift_mode, n, &info);
3260 output_asm_insn (info.special, operands);
3266 /* Emit two bit shifts first. */
3267 if (info.shift2 != NULL)
3269 for (; n > 1; n -= 2)
3270 output_asm_insn (info.shift2, operands);
3273 /* Now emit one bit shifts for any residual. */
3275 output_asm_insn (info.shift1, operands);
3277 /* Keep track of CC. */
3278 if (info.cc_valid_p)
3280 cc_status.value1 = operands[0];
3281 cc_status.flags |= info.cc_valid_p;
3287 int m = GET_MODE_BITSIZE (mode) - n;
3288 const int mask = (shift_type == SHIFT_ASHIFT
3289 ? ((1 << m) - 1) << n
3293 /* Not all possibilities of rotate are supported. They shouldn't
3294 be generated, but let's watch for 'em. */
3295 if (info.shift1 == 0)
3298 /* Emit two bit rotates first. */
3299 if (info.shift2 != NULL)
3301 for (; m > 1; m -= 2)
3302 output_asm_insn (info.shift2, operands);
3305 /* Now single bit rotates for any residual. */
3307 output_asm_insn (info.shift1, operands);
3309 /* Now mask off the high bits. */
3311 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3312 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3313 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3317 cc_status.value1 = operands[0];
3318 cc_status.flags |= CC_NO_CARRY;
3319 output_asm_insn (insn_buf, operands);
3324 /* A loop to shift by a "large" constant value.
3325 If we have shift-by-2 insns, use them. */
3326 if (info.shift2 != NULL)
3328 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3329 names_big[REGNO (operands[4])]);
3330 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3331 output_asm_insn (info.shift2, operands);
3332 output_asm_insn ("add #0xff,%X4", operands);
3333 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3335 output_asm_insn (info.shift1, operands);
3339 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3340 names_big[REGNO (operands[4])]);
3341 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3342 output_asm_insn (info.shift1, operands);
3343 output_asm_insn ("add #0xff,%X4", operands);
3344 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3355 h8300_asm_insn_count (template)
3356 const char *template;
3358 unsigned int count = 1;
3360 for (; *template; template++)
3361 if (*template == '\n')
3368 compute_a_shift_length (insn, operands)
3369 rtx insn ATTRIBUTE_UNUSED;
3372 rtx shift = operands[3];
3373 enum machine_mode mode = GET_MODE (shift);
3374 enum rtx_code code = GET_CODE (shift);
3375 enum shift_type shift_type;
3376 enum shift_mode shift_mode;
3377 struct shift_info info;
3378 unsigned int wlength = 0;
3383 shift_mode = QIshift;
3386 shift_mode = HIshift;
3389 shift_mode = SIshift;
3398 shift_type = SHIFT_ASHIFTRT;
3401 shift_type = SHIFT_LSHIFTRT;
3404 shift_type = SHIFT_ASHIFT;
3410 if (GET_CODE (operands[2]) != CONST_INT)
3412 /* Get the assembler code to do one shift. */
3413 get_shift_alg (shift_type, shift_mode, 1, &info);
3415 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3419 int n = INTVAL (operands[2]);
3421 /* If the count is negative, make it 0. */
3424 /* If the count is too big, truncate it.
3425 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3426 do the intuitive thing. */
3427 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3428 n = GET_MODE_BITSIZE (mode);
3430 get_shift_alg (shift_type, shift_mode, n, &info);
3435 wlength += h8300_asm_insn_count (info.special);
3437 /* Every assembly instruction used in SHIFT_SPECIAL case
3438 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3439 see xor.l, we just pretend that xor.l counts as two insns
3440 so that the insn length will be computed correctly. */
3441 if (strstr (info.special, "xor.l") != NULL)
3449 if (info.shift2 != NULL)
3451 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3455 wlength += h8300_asm_insn_count (info.shift1) * n;
3461 int m = GET_MODE_BITSIZE (mode) - n;
3463 /* Not all possibilities of rotate are supported. They shouldn't
3464 be generated, but let's watch for 'em. */
3465 if (info.shift1 == 0)
3468 if (info.shift2 != NULL)
3470 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3474 wlength += h8300_asm_insn_count (info.shift1) * m;
3476 /* Now mask off the high bits. */
3497 /* A loop to shift by a "large" constant value.
3498 If we have shift-by-2 insns, use them. */
3499 if (info.shift2 != NULL)
3501 wlength += 3 + h8300_asm_insn_count (info.shift2);
3503 wlength += h8300_asm_insn_count (info.shift1);
3507 wlength += 3 + h8300_asm_insn_count (info.shift1);
3517 /* A rotation by a non-constant will cause a loop to be generated, in
3518 which a rotation by one bit is used. A rotation by a constant,
3519 including the one in the loop, will be taken care of by
3520 emit_a_rotate () at the insn emit time. */
3523 expand_a_rotate (code, operands)
3527 rtx dst = operands[0];
3528 rtx src = operands[1];
3529 rtx rotate_amount = operands[2];
3530 enum machine_mode mode = GET_MODE (dst);
3533 /* We rotate in place. */
3534 emit_move_insn (dst, src);
3536 if (GET_CODE (rotate_amount) != CONST_INT)
3538 rtx counter = gen_reg_rtx (QImode);
3539 rtx start_label = gen_label_rtx ();
3540 rtx end_label = gen_label_rtx ();
3542 /* If the rotate amount is less than or equal to 0,
3543 we go out of the loop. */
3544 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3545 QImode, 0, end_label);
3547 /* Initialize the loop counter. */
3548 emit_move_insn (counter, rotate_amount);
3550 emit_label (start_label);
3552 /* Rotate by one bit. */
3553 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3554 emit_insn (gen_rtx_SET (mode, dst, tmp));
3556 /* Decrement the counter by 1. */
3557 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3558 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3560 /* If the loop counter is nonzero, we go back to the beginning
3562 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3565 emit_label (end_label);
3569 /* Rotate by AMOUNT bits. */
3570 tmp = gen_rtx (code, mode, dst, rotate_amount);
3571 emit_insn (gen_rtx_SET (mode, dst, tmp));
3577 /* Emit rotate insns. */
3580 emit_a_rotate (code, operands)
3584 rtx dst = operands[0];
3585 rtx rotate_amount = operands[2];
3586 enum shift_mode rotate_mode;
3587 enum shift_type rotate_type;
3588 const char *insn_buf;
3591 enum machine_mode mode = GET_MODE (dst);
3593 if (GET_CODE (rotate_amount) != CONST_INT)
3599 rotate_mode = QIshift;
3602 rotate_mode = HIshift;
3605 rotate_mode = SIshift;
3614 rotate_type = SHIFT_ASHIFT;
3617 rotate_type = SHIFT_LSHIFTRT;
3623 amount = INTVAL (rotate_amount);
3625 /* Clean up AMOUNT. */
3628 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3629 amount = GET_MODE_BITSIZE (mode);
3631 /* Determine the faster direction. After this phase, amount will be
3632 at most a half of GET_MODE_BITSIZE (mode). */
3633 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3635 /* Flip the direction. */
3636 amount = GET_MODE_BITSIZE (mode) - amount;
3638 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3641 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3642 boost up the rotation. */
3643 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3644 || (mode == HImode && TARGET_H8300H && amount >= 6)
3645 || (mode == HImode && TARGET_H8300S && amount == 8)
3646 || (mode == SImode && TARGET_H8300H && amount >= 10)
3647 || (mode == SImode && TARGET_H8300S && amount >= 13))
3652 /* This code works on any family. */
3653 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3654 output_asm_insn (insn_buf, operands);
3658 /* This code works on the H8/300H and H8S. */
3659 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3660 output_asm_insn (insn_buf, operands);
3667 /* Adjust AMOUNT and flip the direction. */
3668 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3670 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3673 /* Emit rotate insns. */
3674 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3677 insn_buf = rotate_two[rotate_type][rotate_mode];
3679 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3681 for (; amount >= bits; amount -= bits)
3682 output_asm_insn (insn_buf, operands);
3688 /* Fix the operands of a gen_xxx so that it could become a bit
3692 fix_bit_operand (operands, what, type)
3697 /* The bit_operand predicate accepts any memory during RTL generation, but
3698 only 'U' memory afterwards, so if this is a MEM operand, we must force
3699 it to be valid for 'U' by reloading the address. */
3701 if ((what == 0 && single_zero_operand (operands[2], QImode))
3702 || (what == 1 && single_one_operand (operands[2], QImode)))
3704 /* OK to have a memory dest. */
3705 if (GET_CODE (operands[0]) == MEM
3706 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3708 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3709 copy_to_mode_reg (Pmode,
3710 XEXP (operands[0], 0)));
3711 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3715 if (GET_CODE (operands[1]) == MEM
3716 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3718 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3719 copy_to_mode_reg (Pmode,
3720 XEXP (operands[1], 0)));
3721 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3727 /* Dest and src op must be register. */
3729 operands[1] = force_reg (QImode, operands[1]);
3731 rtx res = gen_reg_rtx (QImode);
3732 emit_insn (gen_rtx_SET (VOIDmode, res,
3733 gen_rtx (type, QImode, operands[1], operands[2])));
3734 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3739 /* Return nonzero if FUNC is an interrupt function as specified
3740 by the "interrupt" attribute. */
3743 h8300_interrupt_function_p (func)
3748 if (TREE_CODE (func) != FUNCTION_DECL)
3751 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3752 return a != NULL_TREE;
3755 /* Return nonzero if FUNC is an OS_Task function as specified
3756 by the "OS_Task" attribute. */
3759 h8300_os_task_function_p (func)
3764 if (TREE_CODE (func) != FUNCTION_DECL)
3767 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3768 return a != NULL_TREE;
3771 /* Return nonzero if FUNC is a monitor function as specified
3772 by the "monitor" attribute. */
3775 h8300_monitor_function_p (func)
3780 if (TREE_CODE (func) != FUNCTION_DECL)
3783 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
3784 return a != NULL_TREE;
3787 /* Return nonzero if FUNC is a function that should be called
3788 through the function vector. */
3791 h8300_funcvec_function_p (func)
3796 if (TREE_CODE (func) != FUNCTION_DECL)
3799 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
3800 return a != NULL_TREE;
3803 /* Return nonzero if DECL is a variable that's in the eight bit
3807 h8300_eightbit_data_p (decl)
3812 if (TREE_CODE (decl) != VAR_DECL)
3815 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
3816 return a != NULL_TREE;
3819 /* Return nonzero if DECL is a variable that's in the tiny
3823 h8300_tiny_data_p (decl)
3828 if (TREE_CODE (decl) != VAR_DECL)
3831 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
3832 return a != NULL_TREE;
3835 /* Generate an 'interrupt_handler' attribute for decls. */
3838 h8300_insert_attributes (node, attributes)
3842 if (!pragma_interrupt
3843 || TREE_CODE (node) != FUNCTION_DECL)
3846 pragma_interrupt = 0;
3848 /* Add an 'interrupt_handler' attribute. */
3849 *attributes = tree_cons (get_identifier ("interrupt_handler"),
3853 /* Supported attributes:
3855 interrupt_handler: output a prologue and epilogue suitable for an
3858 function_vector: This function should be called through the
3861 eightbit_data: This variable lives in the 8-bit data area and can
3862 be referenced with 8-bit absolute memory addresses.
3864 tiny_data: This variable lives in the tiny data area and can be
3865 referenced with 16-bit absolute memory references. */
3867 const struct attribute_spec h8300_attribute_table[] =
3869 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3870 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3871 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3872 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3873 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3874 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
3875 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
3876 { NULL, 0, 0, false, false, false, NULL }
3880 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
3881 struct attribute_spec.handler. */
3883 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
3886 tree args ATTRIBUTE_UNUSED;
3887 int flags ATTRIBUTE_UNUSED;
3890 if (TREE_CODE (*node) != FUNCTION_DECL)
3892 warning ("`%s' attribute only applies to functions",
3893 IDENTIFIER_POINTER (name));
3894 *no_add_attrs = true;
3900 /* Handle an "eightbit_data" attribute; arguments as in
3901 struct attribute_spec.handler. */
3903 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
3906 tree args ATTRIBUTE_UNUSED;
3907 int flags ATTRIBUTE_UNUSED;
3912 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3914 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3918 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3919 *no_add_attrs = true;
3925 /* Handle an "tiny_data" attribute; arguments as in
3926 struct attribute_spec.handler. */
3928 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
3931 tree args ATTRIBUTE_UNUSED;
3932 int flags ATTRIBUTE_UNUSED;
3937 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3939 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3943 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3944 *no_add_attrs = true;
3951 h8300_encode_label (decl)
3954 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3955 const int len = strlen (str);
3956 char *newstr = alloca (len + 2);
3959 strcpy (&newstr[1], str);
3961 XSTR (XEXP (DECL_RTL (decl), 0), 0) =
3962 ggc_alloc_string (newstr, len + 1);
3965 /* If we are referencing a function that is supposed to be called
3966 through the function vector, the SYMBOL_REF_FLAG in the rtl
3967 so the call patterns can generate the correct code. */
3970 h8300_encode_section_info (decl, first)
3974 if (TREE_CODE (decl) == FUNCTION_DECL
3975 && h8300_funcvec_function_p (decl))
3976 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
3977 else if (TREE_CODE (decl) == VAR_DECL
3978 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3980 if (h8300_eightbit_data_p (decl))
3981 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
3982 else if (first && h8300_tiny_data_p (decl))
3983 h8300_encode_label (decl);
3987 /* Undo the effects of the above. */
3990 h8300_strip_name_encoding (str)
3993 return str + (*str == '*' || *str == '@' || *str == '&');
3997 output_simode_bld (bild, operands)
4003 /* Clear the destination register. */
4004 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4006 /* Now output the bit load or bit inverse load, and store it in
4009 output_asm_insn ("bild\t%Z2,%Y1", operands);
4011 output_asm_insn ("bld\t%Z2,%Y1", operands);
4013 output_asm_insn ("bst\t#0,%w0", operands);
4017 /* Output the bit load or bit inverse load. */
4019 output_asm_insn ("bild\t%Z2,%Y1", operands);
4021 output_asm_insn ("bld\t%Z2,%Y1", operands);
4023 /* Clear the destination register and perform the bit store. */
4024 output_asm_insn ("xor.l\t%S0,%S0\n\tbst\t#0,%w0", operands);
4031 /* Given INSN and its current length LENGTH, return the adjustment
4032 (in bytes) to correctly compute INSN's length.
4034 We use this to get the lengths of various memory references correct. */
4037 h8300_adjust_insn_length (insn, length)
4039 int length ATTRIBUTE_UNUSED;
4041 rtx pat = PATTERN (insn);
4043 /* We must filter these out before calling get_attr_adjust_length. */
4044 if (GET_CODE (pat) == USE
4045 || GET_CODE (pat) == CLOBBER
4046 || GET_CODE (pat) == SEQUENCE
4047 || GET_CODE (pat) == ADDR_VEC
4048 || GET_CODE (pat) == ADDR_DIFF_VEC)
4051 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
4054 /* Adjust length for reg->mem and mem->reg copies. */
4055 if (GET_CODE (pat) == SET
4056 && (GET_CODE (SET_SRC (pat)) == MEM
4057 || GET_CODE (SET_DEST (pat)) == MEM))
4059 /* This insn might need a length adjustment. */
4062 if (GET_CODE (SET_SRC (pat)) == MEM)
4063 addr = XEXP (SET_SRC (pat), 0);
4065 addr = XEXP (SET_DEST (pat), 0);
4069 /* On the H8/300, we subtract the difference between the
4070 actual length and the longest one, which is @(d:16,ERs). */
4072 /* @Rs is 2 bytes shorter than the longest. */
4073 if (GET_CODE (addr) == REG)
4076 /* @aa:8 is 2 bytes shorter than the longest. */
4077 if (GET_MODE (SET_SRC (pat)) == QImode
4078 && h8300_eightbit_constant_address_p (addr))
4083 /* On the H8/300H and H8S, we subtract the difference
4084 between the actual length and the longest one, which is
4087 /* @ERs is 6 bytes shorter than the longest. */
4088 if (GET_CODE (addr) == REG)
4091 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4092 if (GET_CODE (addr) == PLUS
4093 && GET_CODE (XEXP (addr, 0)) == REG
4094 && GET_CODE (XEXP (addr, 1)) == CONST_INT
4095 && INTVAL (XEXP (addr, 1)) > -32768
4096 && INTVAL (XEXP (addr, 1)) < 32767)
4099 /* @aa:8 is 6 bytes shorter than the longest. */
4100 if (GET_MODE (SET_SRC (pat)) == QImode
4101 && h8300_eightbit_constant_address_p (addr))
4104 /* @aa:16 is 4 bytes shorter than the longest. */
4105 if (h8300_tiny_constant_address_p (addr))
4108 /* @aa:24 is 2 bytes shorter than the longest. */
4109 if (GET_CODE (addr) == CONST_INT)
4114 /* Loading some constants needs adjustment. */
4115 if (GET_CODE (pat) == SET
4116 && GET_CODE (SET_SRC (pat)) == CONST_INT
4117 && GET_MODE (SET_DEST (pat)) == SImode
4118 && INTVAL (SET_SRC (pat)) != 0)
4120 int val = INTVAL (SET_SRC (pat));
4123 && ((val & 0xffff) == 0
4124 || ((val >> 16) & 0xffff) == 0))
4127 if (TARGET_H8300H || TARGET_H8300S)
4129 if (val == (val & 0xff)
4130 || val == (val & 0xff00))
4133 switch (val & 0xffffffff)
4149 /* Rotations need various adjustments. */
4150 if (GET_CODE (pat) == SET
4151 && (GET_CODE (SET_SRC (pat)) == ROTATE
4152 || GET_CODE (SET_SRC (pat)) == ROTATERT))
4154 rtx src = SET_SRC (pat);
4155 enum machine_mode mode = GET_MODE (src);
4159 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
4162 amount = INTVAL (XEXP (src, 1));
4164 /* Clean up AMOUNT. */
4167 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4168 amount = GET_MODE_BITSIZE (mode);
4170 /* Determine the faster direction. After this phase, amount
4171 will be at most a half of GET_MODE_BITSIZE (mode). */
4172 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4173 /* Flip the direction. */
4174 amount = GET_MODE_BITSIZE (mode) - amount;
4176 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4177 boost up the rotation. */
4178 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4179 || (mode == HImode && TARGET_H8300H && amount >= 6)
4180 || (mode == HImode && TARGET_H8300S && amount == 8)
4181 || (mode == SImode && TARGET_H8300H && amount >= 10)
4182 || (mode == SImode && TARGET_H8300S && amount >= 13))
4184 /* Adjust AMOUNT and flip the direction. */
4185 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4189 /* We use 2-bit rotations on the H8S. */
4191 amount = amount / 2 + amount % 2;
4193 /* The H8/300 uses three insns to rotate one bit, taking 6
4195 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4197 return -(20 - states);
4203 #ifndef OBJECT_FORMAT_ELF
4205 h8300_asm_named_section (name, flags)
4207 unsigned int flags ATTRIBUTE_UNUSED;
4209 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4210 fprintf (asm_out_file, "\t.section %s\n", name);
4212 #endif /* ! OBJECT_FORMAT_ELF */
4214 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4215 which is a special case of the 'R' operand. */
4218 h8300_eightbit_constant_address_p (x)
4221 /* The ranges of the 8-bit area. */
4222 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4223 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4224 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4225 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4226 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4227 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4229 unsigned HOST_WIDE_INT addr;
4231 /* We accept symbols declared with eightbit_data. */
4232 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_FLAG (x))
4235 if (GET_CODE (x) != CONST_INT)
4241 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4242 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4243 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4246 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4247 on H8/300H and H8S. */
4250 h8300_tiny_constant_address_p (x)
4253 /* The ranges of the 16-bit area. */
4254 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4255 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4256 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4257 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4258 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4259 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4260 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4261 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4263 unsigned HOST_WIDE_INT addr;
4265 /* We accept symbols declared with tiny_data. */
4266 if (GET_CODE (x) == SYMBOL_REF && TINY_DATA_NAME_P (XSTR (x, 0)))
4269 if (GET_CODE (x) != CONST_INT)
4275 || ((TARGET_H8300H && !TARGET_NORMAL_MODE)
4276 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4277 || ((TARGET_H8300S && !TARGET_NORMAL_MODE)
4278 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));