1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
44 /* Forward declarations. */
45 static int h8300_interrupt_function_p PARAMS ((tree));
46 static int h8300_monitor_function_p PARAMS ((tree));
47 static int h8300_os_task_function_p PARAMS ((tree));
48 static void dosize PARAMS ((FILE *, const char *, unsigned int));
49 static const char *cond_string PARAMS ((enum rtx_code));
51 /* CPU_TYPE, says what cpu we're compiling for. */
54 /* True if the current function is an interrupt handler
55 (either via #pragma or an attribute specification). */
56 int interrupt_handler;
58 /* True if the current function is an OS Task
59 (via an attribute specification). */
62 /* True if the current function is a monitor
63 (via an attribute specification). */
66 /* True if a #pragma saveall has been seen for the current function. */
69 static const char *const names_big[] =
70 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
72 static const char *const names_extended[] =
73 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
75 static const char *const names_upper_extended[] =
76 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
78 /* Points to one of the above. */
79 /* ??? The above could be put in an array indexed by CPU_TYPE. */
80 const char * const *h8_reg_names;
82 /* Various operations needed by the following, indexed by CPU_TYPE. */
84 static const char *const h8_push_ops[2] = { "push", "push.l" };
85 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
86 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
88 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
90 /* Initialize various cpu specific globals at start up. */
97 cpu_type = (int) CPU_H8300;
98 h8_reg_names = names_big;
102 /* For this we treat the H8/300 and H8/S the same. */
103 cpu_type = (int) CPU_H8300H;
104 h8_reg_names = names_extended;
106 h8_push_op = h8_push_ops[cpu_type];
107 h8_pop_op = h8_pop_ops[cpu_type];
108 h8_mov_op = h8_mov_ops[cpu_type];
116 static const char *const names_small[] =
117 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
118 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
120 return names_small[REGNO (x) * 2 + b];
123 /* REGNO must be saved/restored across calls if this macro is true. */
125 #define WORD_REG_USED(regno) \
127 /* No need to save registers if this function will not return. */\
128 && ! TREE_THIS_VOLATILE (current_function_decl) \
130 /* Save any call saved register that was used. */ \
131 || (regs_ever_live[regno] && !call_used_regs[regno]) \
132 /* Save the frame pointer if it was used. */ \
133 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
134 /* Save any register used in an interrupt handler. */ \
135 || (interrupt_handler && regs_ever_live[regno]) \
136 /* Save call clobbered registers in non-leaf interrupt \
138 || (interrupt_handler \
139 && call_used_regs[regno] \
140 && !current_function_is_leaf)))
142 /* Output assembly language to FILE for the operation OP with operand size
143 SIZE to adjust the stack pointer. */
146 dosize (file, op, size)
151 /* On the H8/300H and H8/S, for sizes <= 8 bytes, it is as good or
152 better to use adds/subs insns rather than add.l/sub.l with an
155 Also, on the H8/300, if we don't have a temporary to hold the
156 size of the frame in the prologue, we simply emit a sequence of
157 subs since this shouldn't happen often. */
158 if ((TARGET_H8300 && size <= 4)
159 || ((TARGET_H8300H || TARGET_H8300S) && size <= 8)
160 || (TARGET_H8300 && current_function_needs_context
161 && strcmp (op, "sub")))
163 HOST_WIDE_INT amount;
165 /* Try different amounts in descending order. */
166 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
170 for(; size >= amount; size -= amount)
171 fprintf (file, "\t%ss\t#%d,sp\n", op, amount);
177 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
179 fprintf (file, "\t%s.l\t#%d,sp\n", op, size);
183 /* Output assembly language code for the function prologue. */
184 static int push_order[FIRST_PSEUDO_REGISTER] =
185 { 0, 1, 2, 3, 4, 5, 6, -1, -1, -1 };
186 static int pop_order[FIRST_PSEUDO_REGISTER] =
187 { 6, 5, 4, 3, 2, 1, 0, -1, -1, -1 };
189 /* This is what the stack looks like after the prolog of
190 a function with a frame has been set up:
196 <saved registers> <- sp
198 This is what the stack looks like after the prolog of
199 a function which doesn't have a frame:
204 <saved registers> <- sp
208 function_prologue (file, size)
212 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
214 int push_regs[FIRST_PSEUDO_REGISTER];
217 /* Note a function with the interrupt attribute and set interrupt_handler
219 if (h8300_interrupt_function_p (current_function_decl))
220 interrupt_handler = 1;
222 /* If the current function has the OS_Task attribute set, then
223 we have a naked prologue. */
224 if (h8300_os_task_function_p (current_function_decl))
226 fprintf (file, ";OS_Task prologue\n");
231 if (h8300_monitor_function_p (current_function_decl))
233 /* My understanding of monitor functions is they act just
234 like interrupt functions, except the prologue must
236 fprintf (file, ";monitor prologue\n");
237 interrupt_handler = 1;
241 fprintf (file, "\tsubs\t#2,sp\n");
242 fprintf (file, "\tpush\tr0\n");
243 fprintf (file, "\tstc\tccr,r0l\n");
244 fprintf (file, "\torc\t#128,ccr\n");
245 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
249 fprintf (file, "\tpush\ter0\n");
250 fprintf (file, "\tstc\tccr,r0l\n");
251 fprintf (file, "\torc\t#128,ccr\n");
252 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
256 if (frame_pointer_needed)
259 fprintf (file, "\t%s\t%s\n", h8_push_op,
260 h8_reg_names[FRAME_POINTER_REGNUM]);
261 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
262 h8_reg_names[STACK_POINTER_REGNUM],
263 h8_reg_names[FRAME_POINTER_REGNUM]);
266 /* Leave room for locals. */
267 dosize (file, "sub", fsize);
269 /* Compute which registers to push. */
270 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
272 int regno = push_order[idx];
275 && WORD_REG_USED (regno)
276 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
277 push_regs[idx] = regno;
282 /* Push the rest of the registers. */
283 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
285 int regno = push_regs[idx];
292 /* See how many registers we can push at the same time. */
293 if ((regno == 0 || regno == 4)
294 && push_regs[idx + 1] >= 0
295 && push_regs[idx + 2] >= 0
296 && push_regs[idx + 3] >= 0)
299 else if ((regno == 0 || regno == 4)
300 && push_regs[idx + 1] >= 0
301 && push_regs[idx + 2] >= 0)
304 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
305 && push_regs[idx + 1] >= 0)
310 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]);
312 fprintf (file, "\tstm.l\t%s-%s,@-sp\n",
314 h8_reg_names[regno + (n_regs - 1)]);
319 /* Output assembly language code for the function epilogue. */
322 function_epilogue (file, size)
326 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
328 rtx insn = get_last_insn ();
329 int pop_regs[FIRST_PSEUDO_REGISTER];
334 /* OS_Task epilogues are nearly naked -- they just have an
336 fprintf (file, ";OS_task epilogue\n");
337 fprintf (file, "\trts\n");
341 /* Monitor epilogues are the same as interrupt function epilogues.
342 Just make a note that we're in an monitor epilogue. */
344 fprintf (file, ";monitor epilogue\n");
346 /* If the last insn was a BARRIER, we don't have to write any code. */
347 if (GET_CODE (insn) == NOTE)
348 insn = prev_nonnote_insn (insn);
349 if (insn && GET_CODE (insn) == BARRIER)
352 /* Compute which registers to pop. */
353 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
355 int regno = pop_order[idx];
358 && WORD_REG_USED (regno)
359 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
360 pop_regs[idx] = regno;
365 /* Pop the saved registers. */
366 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
368 int regno = pop_regs[idx];
375 /* See how many registers we can pop at the same time. */
376 if ((regno == 7 || regno == 3)
377 && pop_regs[idx + 1] >= 0
378 && pop_regs[idx + 2] >= 0
379 && pop_regs[idx + 3] >= 0)
382 else if ((regno == 6 || regno == 2)
383 && pop_regs[idx + 1] >= 0
384 && pop_regs[idx + 2] >= 0)
387 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
388 && pop_regs[idx + 1] >= 0)
393 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]);
395 fprintf (file, "\tldm.l\t@sp+,%s-%s\n",
396 h8_reg_names[regno - (n_regs - 1)],
397 h8_reg_names[regno]);
401 /* Deallocate locals. */
402 dosize (file, "add", fsize);
404 /* Pop frame pointer if we had one. */
405 if (frame_pointer_needed)
406 fprintf (file, "\t%s\t%s\n",
407 h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]);
409 /* If this is a monitor function, there is one register still left on
412 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[0]);
414 if (interrupt_handler)
415 fprintf (file, "\trte\n");
417 fprintf (file, "\trts\n");
420 interrupt_handler = 0;
426 /* Output assembly code for the start of the file. */
429 asm_file_start (file)
432 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
433 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
434 fprintf (file, ";\trelease F-1\n");
436 fprintf (file, "; -O%d\n", optimize);
438 fprintf (file, "\n\t.h8300h\n");
439 else if (TARGET_H8300S)
440 fprintf (file, "\n\t.h8300s\n");
442 fprintf (file, "\n\n");
443 output_file_directive (file, main_input_filename);
446 /* Output assembly language code for the end of file. */
452 fprintf (file, "\t.end\n");
455 /* Return true if VALUE is a valid constant for constraint 'P'.
456 IE: VALUE is a power of two <= 2**15. */
459 small_power_of_two (value)
462 int power = exact_log2 (value);
463 return power >= 0 && power <= 15;
466 /* Return true if VALUE is a valid constant for constraint 'O', which
467 means that the constant would be ok to use as a bit for a bclr
474 return small_power_of_two ((~value) & 0xff);
477 /* Return true is OP is a valid source operand for an integer move
481 general_operand_src (op, mode)
483 enum machine_mode mode;
485 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
487 return general_operand (op, mode);
490 /* Return true if OP is a valid destination operand for an integer move
494 general_operand_dst (op, mode)
496 enum machine_mode mode;
498 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
500 return general_operand (op, mode);
503 /* Return true if OP is a const valid for a bit clear instruction. */
506 o_operand (operand, mode)
508 enum machine_mode mode ATTRIBUTE_UNUSED;
510 return (GET_CODE (operand) == CONST_INT
511 && CONST_OK_FOR_O (INTVAL (operand)));
514 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
517 p_operand (operand, mode)
519 enum machine_mode mode ATTRIBUTE_UNUSED;
521 return (GET_CODE (operand) == CONST_INT
522 && CONST_OK_FOR_P (INTVAL (operand)));
525 /* Return true if OP is a valid call operand. */
528 call_insn_operand (op, mode)
530 enum machine_mode mode ATTRIBUTE_UNUSED;
532 if (GET_CODE (op) == MEM)
534 rtx inside = XEXP (op, 0);
535 if (register_operand (inside, Pmode))
537 if (CONSTANT_ADDRESS_P (inside))
543 /* Return 1 if an addition/subtraction of a constant integer can be
544 transformed into two consecutive adds/subs that are faster than the
545 straightforward way. Otherwise, return 0. */
548 two_insn_adds_subs_operand (op, mode)
550 enum machine_mode mode;
552 if (GET_CODE (op) == CONST_INT)
554 HOST_WIDE_INT value = INTVAL (op);
556 /* Force VALUE to be positive so that we do not have to consider
557 the negative case. */
560 if (TARGET_H8300H || TARGET_H8300S)
562 /* A constant addition/subtraction takes 2 states in QImode,
563 4 states in HImode, and 6 states in SImode. Thus, the
564 only case we can win is when SImode is used, in which
565 case, two adds/subs are used, taking 4 states. */
575 /* A constant addition/subtraction takes 2 states in
576 QImode. It takes 6 states in HImode, requiring the
577 constant to be loaded to a register first, and a lot more
578 in SImode. Thus the only case we can win is when either
579 HImode or SImode is used. */
590 /* Split an add of a small constant into two adds/subs insns. */
593 split_adds_subs (mode, operands)
594 enum machine_mode mode;
597 HOST_WIDE_INT val = INTVAL (operands[1]);
598 rtx reg = operands[0];
599 HOST_WIDE_INT sign = 1;
600 HOST_WIDE_INT amount;
602 /* Force VAL to be positive so that we do not have to consider the
610 /* Try different amounts in descending order. */
611 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
615 for(; val >= amount; val -= amount)
617 rtx tmp = gen_rtx_PLUS (mode, reg, GEN_INT (sign * amount));
618 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
625 /* Return true if OP is a valid call operand, and OP represents
626 an operand for a small call (4 bytes instead of 6 bytes). */
629 small_call_insn_operand (op, mode)
631 enum machine_mode mode ATTRIBUTE_UNUSED;
633 if (GET_CODE (op) == MEM)
635 rtx inside = XEXP (op, 0);
637 /* Register indirect is a small call. */
638 if (register_operand (inside, Pmode))
641 /* A call through the function vector is a small
643 if (GET_CODE (inside) == SYMBOL_REF
644 && SYMBOL_REF_FLAG (inside))
647 /* Otherwise it's a large call. */
651 /* Return true if OP is a valid jump operand. */
654 jump_address_operand (op, mode)
656 enum machine_mode mode;
658 if (GET_CODE (op) == REG)
659 return mode == Pmode;
661 if (GET_CODE (op) == MEM)
663 rtx inside = XEXP (op, 0);
664 if (register_operand (inside, Pmode))
666 if (CONSTANT_ADDRESS_P (inside))
672 /* Recognize valid operands for bitfield instructions. */
674 extern int rtx_equal_function_value_matters;
677 bit_operand (op, mode)
679 enum machine_mode mode;
681 /* We can except any general operand, expept that MEM operands must
682 be limited to those that use addresses valid for the 'U' constraint. */
683 if (!general_operand (op, mode))
686 /* Accept any mem during RTL generation. Otherwise, the code that does
687 insv and extzv will think that we can not handle memory. However,
688 to avoid reload problems, we only accept 'U' MEM operands after RTL
689 generation. This means that any named pattern which uses this predicate
690 must force its operands to match 'U' before emitting RTL. */
692 if (GET_CODE (op) == REG)
694 if (GET_CODE (op) == SUBREG)
696 if (!rtx_equal_function_value_matters)
697 /* We're building rtl. */
698 return GET_CODE (op) == MEM;
700 return (GET_CODE (op) == MEM
701 && EXTRA_CONSTRAINT (op, 'U'));
705 bit_memory_operand (op, mode)
707 enum machine_mode mode ATTRIBUTE_UNUSED;
709 return (GET_CODE (op) == MEM
710 && EXTRA_CONSTRAINT (op, 'U'));
713 /* Recognize valid operators for bit test. */
716 eq_operator (x, mode)
718 enum machine_mode mode ATTRIBUTE_UNUSED;
720 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
723 /* Handle machine specific pragmas for compatibility with existing
724 compilers for the H8/300.
726 pragma saveall generates prolog/epilog code which saves and
727 restores all the registers on function entry.
729 pragma interrupt saves and restores all registers, and exits with
730 an rte instruction rather than an rts. A pointer to a function
731 with this attribute may be safely used in an interrupt vector. */
734 handle_pragma (p_getc, p_ungetc, pname)
735 int (* ATTRIBUTE_UNUSED p_getc) PARAMS ((void));
736 void (* ATTRIBUTE_UNUSED p_ungetc) PARAMS ((int));
741 if (strcmp (pname, "interrupt") == 0)
742 interrupt_handler = retval = 1;
743 else if (strcmp (pname, "saveall") == 0)
744 pragma_saveall = retval = 1;
749 /* If the next arg with MODE and TYPE is to be passed in a register, return
750 the rtx to represent where it is passed. CUM represents the state after
751 the last argument. NAMED is not used. */
753 static const char *const hand_list[] =
773 /* Return an RTX to represent where a value with mode MODE will be returned
774 from a function. If the result is 0, the argument is pushed. */
777 function_arg (cum, mode, type, named)
778 CUMULATIVE_ARGS *cum;
779 enum machine_mode mode;
787 /* Never pass unnamed arguments in registers. */
791 /* Pass 3 regs worth of data in regs when user asked on the command line. */
792 if (TARGET_QUICKCALL)
795 /* If calling hand written assembler, use 4 regs of args. */
799 const char * const *p;
801 fname = XSTR (cum->libcall, 0);
803 /* See if this libcall is one of the hand coded ones. */
805 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
817 size = int_size_in_bytes (type);
819 size = GET_MODE_SIZE (mode);
821 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
827 switch (cum->nbytes / UNITS_PER_WORD)
830 result = gen_rtx_REG (mode, 0);
833 result = gen_rtx_REG (mode, 1);
836 result = gen_rtx_REG (mode, 2);
839 result = gen_rtx_REG (mode, 3);
850 /* Return the cost of the rtx R with code CODE. */
870 if (TARGET_H8300H || TARGET_H8300S)
891 /* Documentation for the machine specific operand escapes:
893 'A' print rn in H8/300 mode, erN in H8/300H mode
894 'C' print (operand - 2).
895 'E' like s but negative.
896 'F' like t but negative.
897 'G' constant just the negative
898 'M' turn a 'M' constant into its negative mod 2.
899 'P' if operand is incing/decing sp, print .w, otherwise .b.
900 'R' print operand as a byte:8 address if appropriate, else fall back to
902 'S' print operand as a long word
903 'T' print operand as a word
904 'U' if operand is incing/decing sp, print l, otherwise nothing.
905 'V' find the set bit, and print its number.
906 'W' find the clear bit, and print its number.
907 'X' print operand as a byte
908 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
909 If this operand isn't a register, fall back to 'R' handling.
911 'b' print the bit opcode
912 'c' print the ibit opcode
913 'd' bcc if EQ, bcs if NE
914 'e' first word of 32 bit value - if reg, then least reg. if mem
915 then least. if const then most sig word
916 'f' second word of 32 bit value - if reg, then biggest reg. if mem
917 then +2. if const then least sig word
918 'g' bcs if EQ, bcc if NE
919 'j' print operand as condition code.
920 'k' print operand as reverse condition code.
921 's' print as low byte of 16 bit value
922 't' print as high byte of 16 bit value
923 'w' print as low byte of 32 bit value
924 'x' print as 2nd byte of 32 bit value
925 'y' print as 3rd byte of 32 bit value
926 'z' print as msb of 32 bit value
929 /* Return assembly language string which identifies a comparison type. */
962 /* Print operand X using operand code CODE to assembly language output file
966 print_operand (file, x, code)
971 /* This is used for communication between the 'P' and 'U' codes. */
972 static const char *last_p;
974 /* This is used for communication between codes V,W,Z and Y. */
980 if (GET_CODE (x) == REG)
981 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
986 fprintf (file, "#%d", INTVAL (x) - 2);
989 switch (GET_CODE (x))
992 fprintf (file, "%sl", names_big[REGNO (x)]);
995 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1002 switch (GET_CODE (x))
1005 fprintf (file, "%sh", names_big[REGNO (x)]);
1008 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1015 if (GET_CODE (x) != CONST_INT)
1017 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1020 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1027 fprintf (file, "#2");
1033 fprintf (file, "#1");
1040 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1043 fprintf (file, ".w");
1048 fprintf (file, ".b");
1052 if (GET_CODE (x) == REG)
1053 fprintf (file, "%s", names_extended[REGNO (x)]);
1058 if (GET_CODE (x) == REG)
1059 fprintf (file, "%s", names_big[REGNO (x)]);
1064 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1067 bitint = exact_log2 (INTVAL (x));
1070 fprintf (file, "#%d", bitint & 7);
1073 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1076 fprintf (file, "#%d", bitint & 7);
1080 if (GET_CODE (x) == REG)
1081 fprintf (file, "%s", byte_reg (x, 0));
1088 if (GET_CODE (x) == REG)
1089 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1091 print_operand (file, x, 'R');
1095 bitint = INTVAL (x);
1096 fprintf (file, "#%d", bitint & 7);
1099 switch (GET_CODE (x))
1102 fprintf (file, "bor");
1105 fprintf (file, "bxor");
1108 fprintf (file, "band");
1115 switch (GET_CODE (x))
1118 fprintf (file, "bior");
1121 fprintf (file, "bixor");
1124 fprintf (file, "biand");
1131 switch (GET_CODE (x))
1134 fprintf (file, "bcc");
1137 fprintf (file, "bcs");
1144 switch (GET_CODE (x))
1148 fprintf (file, "%s", names_big[REGNO (x)]);
1150 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1153 x = adj_offsettable_operand (x, 0);
1154 print_operand (file, x, 0);
1157 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1163 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1164 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1165 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1174 switch (GET_CODE (x))
1178 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1180 fprintf (file, "%s", names_big[REGNO (x)]);
1183 x = adj_offsettable_operand (x, 2);
1184 print_operand (file, x, 0);
1187 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1193 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1194 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1195 fprintf (file, "#%ld", (val & 0xffff));
1203 switch (GET_CODE (x))
1206 fprintf (file, "bcc");
1209 fprintf (file, "bcs");
1216 asm_fprintf (file, cond_string (GET_CODE (x)));
1219 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1222 if (GET_CODE (x) == CONST_INT)
1223 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1225 fprintf (file, "%s", byte_reg (x, 0));
1228 if (GET_CODE (x) == CONST_INT)
1229 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1231 fprintf (file, "%s", byte_reg (x, 1));
1234 if (GET_CODE (x) != CONST_INT)
1236 fprintf (file, "%d", INTVAL (x));
1239 if (GET_CODE (x) == CONST_INT)
1240 fprintf (file, "#%d", INTVAL (x) & 0xff);
1242 fprintf (file, "%s",
1243 byte_reg (x, TARGET_H8300 ? 2 : 0));
1246 if (GET_CODE (x) == CONST_INT)
1247 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1249 fprintf (file, "%s",
1250 byte_reg (x, TARGET_H8300 ? 3 : 1));
1253 if (GET_CODE (x) == CONST_INT)
1254 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1256 fprintf (file, "%s", byte_reg (x, 0));
1259 if (GET_CODE (x) == CONST_INT)
1260 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1262 fprintf (file, "%s", byte_reg (x, 1));
1267 switch (GET_CODE (x))
1270 switch (GET_MODE (x))
1273 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1274 fprintf (file, "%s", byte_reg (x, 0));
1275 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1276 fprintf (file, "%s", names_big[REGNO (x)]);
1280 fprintf (file, "%s", names_big[REGNO (x)]);
1284 fprintf (file, "%s", names_extended[REGNO (x)]);
1292 fprintf (file, "@");
1293 output_address (XEXP (x, 0));
1295 /* If this is an 'R' operand (reference into the 8-bit
1296 area), then specify a symbolic address as "foo:8",
1297 otherwise if operand is still in eight bit section, use
1299 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1300 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1301 fprintf (file, (code == 'R' ? ":8" : ":16"));
1302 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1303 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1304 fprintf (file, ":16");
1305 else if ((code == 'R')
1306 && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0)))
1307 fprintf (file, ":8");
1314 fprintf (file, "#");
1315 print_operand_address (file, x);
1321 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1322 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1323 fprintf (file, "#%ld", val);
1332 /* Output assembly language output for the address ADDR to FILE. */
1335 print_operand_address (file, addr)
1339 switch (GET_CODE (addr))
1342 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1346 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1350 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1354 fprintf (file, "(");
1355 if (GET_CODE (XEXP (addr, 0)) == REG)
1358 print_operand_address (file, XEXP (addr, 1));
1359 fprintf (file, ",");
1360 print_operand_address (file, XEXP (addr, 0));
1365 print_operand_address (file, XEXP (addr, 0));
1366 fprintf (file, "+");
1367 print_operand_address (file, XEXP (addr, 1));
1369 fprintf (file, ")");
1374 /* Since the h8/300 only has 16 bit pointers, negative values are also
1375 those >= 32768. This happens for example with pointer minus a
1376 constant. We don't want to turn (char *p - 2) into
1377 (char *p + 65534) because loop unrolling can build upon this
1378 (IE: char *p + 131068). */
1379 int n = INTVAL (addr);
1381 n = (int) (short) n;
1383 /* ??? Why the special case for -ve values? */
1384 fprintf (file, "-%d", -n);
1386 fprintf (file, "%d", n);
1391 output_addr_const (file, addr);
1396 /* Output all insn addresses and their sizes into the assembly language
1397 output file. This is helpful for debugging whether the length attributes
1398 in the md file are correct. This is not meant to be a user selectable
1402 final_prescan_insn (insn, operand, num_operands)
1403 rtx insn, *operand ATTRIBUTE_UNUSED;
1404 int num_operands ATTRIBUTE_UNUSED;
1406 /* This holds the last insn address. */
1407 static int last_insn_address = 0;
1409 int uid = INSN_UID (insn);
1411 if (TARGET_RTL_DUMP)
1413 fprintf (asm_out_file, "\n****************");
1414 print_rtl (asm_out_file, PATTERN (insn));
1415 fprintf (asm_out_file, "\n");
1418 if (TARGET_ADDRESSES)
1420 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1421 INSN_ADDRESSES (uid) - last_insn_address);
1422 last_insn_address = INSN_ADDRESSES (uid);
1426 /* Prepare for an SI sized move. */
1432 rtx src = operands[1];
1433 rtx dst = operands[0];
1434 if (!reload_in_progress && !reload_completed)
1436 if (!register_operand (dst, GET_MODE (dst)))
1438 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1439 emit_move_insn (tmp, src);
1446 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1447 Define the offset between two registers, one to be eliminated, and
1448 the other its replacement, at the start of a routine. */
1451 initial_offset (from, to)
1456 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1457 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1462 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1463 if (WORD_REG_USED (regno))
1464 offset += UNITS_PER_WORD;
1466 /* See the comments for get_frame_size. We need to round it up to
1469 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1470 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1472 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1473 offset += UNITS_PER_WORD; /* Skip saved PC */
1478 /* Update the condition code from the insn. */
1481 notice_update_cc (body, insn)
1485 switch (get_attr_cc (insn))
1488 /* Insn does not affect CC at all. */
1492 /* Insn does not change CC, but the 0'th operand has been changed. */
1493 if (cc_status.value1 != 0
1494 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1495 cc_status.value1 = 0;
1499 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1500 The V flag is unusable. The C flag may or may not be known but
1501 that's ok because alter_cond will change tests to use EQ/NE. */
1503 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1504 cc_status.value1 = recog_data.operand[0];
1508 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1509 The C flag may or may not be known but that's ok because
1510 alter_cond will change tests to use EQ/NE. */
1512 cc_status.flags |= CC_NO_CARRY;
1513 cc_status.value1 = recog_data.operand[0];
1517 /* The insn is a compare instruction. */
1519 cc_status.value1 = SET_SRC (body);
1523 /* Insn doesn't leave CC in a usable state. */
1529 /* Recognize valid operators for bit instructions. */
1532 bit_operator (x, mode)
1534 enum machine_mode mode ATTRIBUTE_UNUSED;
1536 enum rtx_code code = GET_CODE (x);
1545 We devote a fair bit of code to getting efficient shifts since we can only
1546 shift one bit at a time on the H8/300 and H8/300H and only one or two
1547 bits at a time on the H8/S.
1549 The basic shift methods:
1551 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1552 this is the default. SHIFT_LOOP
1554 * inlined shifts -- emit straight line code for the shift; this is
1555 used when a straight line shift is about the same size or smaller
1556 than a loop. We allow the inline version to be slightly longer in
1557 some cases as it saves a register. SHIFT_INLINE
1559 * rotate + and -- rotate the value the opposite direction, then
1560 mask off the values we don't need. This is used when only a few
1561 of the bits in the original value will survive in the shifted value.
1562 Again, this is used when it's about the same size or smaller than
1563 a loop. We allow this version to be slightly longer as it is usually
1564 much faster than a loop. SHIFT_ROT_AND
1566 * swap (+ shifts) -- often it's possible to swap bytes/words to
1567 simulate a shift by 8/16. Once swapped a few inline shifts can be
1568 added if the shift count is slightly more than 8 or 16. This is used
1569 when it's about the same size or smaller than a loop. We allow this
1570 version to be slightly longer as it is usually much faster than a loop.
1573 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1575 Here are some thoughts on what the absolutely positively best code is.
1576 "Best" here means some rational trade-off between code size and speed,
1577 where speed is more preferred but not at the expense of generating 20 insns.
1579 A trailing '*' after the shift count indicates the "best" mode isn't
1582 H8/300 QImode shifts
1583 1-4 - do them inline
1584 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1586 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1587 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1589 H8/300 HImode shifts
1590 1-4 - do them inline
1592 7 - shift 2nd half other way into carry.
1593 copy 1st half into 2nd half
1594 rotate 2nd half other way with carry
1595 rotate 1st half other way (no carry)
1596 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1597 sign extend 1st half (ASHIFTRT)
1598 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1599 9-12 - do shift by 8, inline remaining shifts
1600 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1602 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1603 - ASHIFTRT: shll, subx, set other byte
1605 H8/300 SImode shifts
1606 1-2 - do them inline
1608 7* - shift other way once, move bytes into place,
1609 move carry into place (possibly with sign extension)
1610 8 - move bytes into place, zero or sign extend other
1612 15* - shift other way once, move word into place, move carry into place
1613 16 - move word, zero or sign extend other
1615 24* - move bytes into place, zero or sign extend other
1617 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1620 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1622 ASHIFTRT: shll top byte, subx, copy to other bytes
1624 H8/300H QImode shifts (same as H8/300 QImode shifts)
1625 1-4 - do them inline
1626 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1628 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1629 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1631 H8/300H HImode shifts
1632 1-4 - do them inline
1634 7 - shift 2nd half other way into carry.
1635 copy 1st half into 2nd half
1636 rotate entire word other way using carry
1637 mask off remaining bits (ASHIFT | LSHIFTRT)
1638 sign extend remaining bits (ASHIFTRT)
1639 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1640 9-12 - do shift by 8, inline remaining shifts
1641 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1643 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1644 - ASHIFTRT: shll, subx, set other byte
1646 H8/300H SImode shifts
1647 (These are complicated by the fact that we don't have byte level access to
1649 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1650 1-4 - do them inline
1652 15* - shift other way once, move word into place, move carry into place
1653 (with sign extension for ASHIFTRT)
1654 16 - move word into place, zero or sign extend other
1655 17-20 - do 16bit shift, then inline remaining shifts
1657 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1658 move word 0 to word 1, zero word 0
1659 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1660 zero word 1, zero byte 1
1661 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1662 sign extend byte 0, sign extend word 0
1663 25-27* - either loop, or
1664 do 24 bit shift, inline rest
1665 28-30 - ASHIFT: rotate 4/3/2, mask
1666 LSHIFTRT: rotate 4/3/2, mask
1668 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1671 1-6 - do them inline
1672 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1673 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1676 1-7 - do them inline
1677 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1678 9-12 - do shift by 8, inline remaining shifts
1679 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1681 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1682 - ASHIFTRT: shll, subx, set other byte
1685 (These are complicated by the fact that we don't have byte level access to
1687 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1688 1-10 - do them inline
1690 15* - shift other way once, move word into place, move carry into place
1691 (with sign extension for ASHIFTRT)
1692 16 - move word into place, zero or sign extend other
1693 17-20 - do 16bit shift, then inline remaining shifts
1695 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1696 move word 0 to word 1, zero word 0
1697 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1698 zero word 1, zero byte 1
1699 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1700 sign extend byte 0, sign extend word 0
1701 25-27* - either loop, or
1702 do 24 bit shift, inline rest
1703 28-30 - ASHIFT: rotate 4/3/2, mask
1704 LSHIFTRT: rotate 4/3/2, mask
1706 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1711 nshift_operator (x, mode)
1713 enum machine_mode mode ATTRIBUTE_UNUSED;
1715 switch (GET_CODE (x))
1727 /* Called from the .md file to emit code to do shifts.
1728 Returns a boolean indicating success
1729 (currently this is always TRUE). */
1732 expand_a_shift (mode, code, operands)
1733 enum machine_mode mode;
1737 emit_move_insn (operands[0], operands[1]);
1739 /* Need a loop to get all the bits we want - we generate the
1740 code at emit time, but need to allocate a scratch reg now. */
1742 emit_insn (gen_rtx_PARALLEL
1745 gen_rtx_SET (VOIDmode, operands[0],
1746 gen_rtx (code, mode, operands[0],
1748 gen_rtx_CLOBBER (VOIDmode,
1749 gen_rtx_SCRATCH (QImode)))));
1754 /* Shift algorithm determination.
1756 There are various ways of doing a shift:
1757 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1759 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1760 necessary bits into position and then set the rest to zero.
1761 SHIFT_SPECIAL: Hand crafted assembler.
1762 SHIFT_LOOP: If the above methods fail, just loop. */
1773 /* Symbols of the various shifts which can be used as indices. */
1777 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1780 /* Symbols of the various modes which can be used as indices. */
1784 QIshift, HIshift, SIshift
1787 /* For single bit shift insns, record assembler and what bits of the
1788 condition code are valid afterwards (represented as various CC_FOO
1789 bits, 0 means CC isn't left in a usable state). */
1793 const char *assembler;
1797 /* Assembler instruction shift table.
1799 These tables are used to look up the basic shifts.
1800 They are indexed by cpu, shift_type, and mode. */
1802 static const struct shift_insn shift_one[2][3][3] =
1808 { "shll\t%X0", CC_NO_CARRY },
1809 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1810 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
1812 /* SHIFT_LSHIFTRT */
1814 { "shlr\t%X0", CC_NO_CARRY },
1815 { "shlr\t%t0\n\trotxr\t%s0", 0 },
1816 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1818 /* SHIFT_ASHIFTRT */
1820 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1821 { "shar\t%t0\n\trotxr\t%s0", 0 },
1822 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1829 { "shll.b\t%X0", CC_NO_CARRY },
1830 { "shll.w\t%T0", CC_NO_CARRY },
1831 { "shll.l\t%S0", CC_NO_CARRY }
1833 /* SHIFT_LSHIFTRT */
1835 { "shlr.b\t%X0", CC_NO_CARRY },
1836 { "shlr.w\t%T0", CC_NO_CARRY },
1837 { "shlr.l\t%S0", CC_NO_CARRY }
1839 /* SHIFT_ASHIFTRT */
1841 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1842 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1843 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1848 static const struct shift_insn shift_two[3][3] =
1852 { "shll.b\t#2,%X0", CC_NO_CARRY },
1853 { "shll.w\t#2,%T0", CC_NO_CARRY },
1854 { "shll.l\t#2,%S0", CC_NO_CARRY }
1856 /* SHIFT_LSHIFTRT */
1858 { "shlr.b\t#2,%X0", CC_NO_CARRY },
1859 { "shlr.w\t#2,%T0", CC_NO_CARRY },
1860 { "shlr.l\t#2,%S0", CC_NO_CARRY }
1862 /* SHIFT_ASHIFTRT */
1864 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1865 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1866 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1870 /* Rotates are organized by which shift they'll be used in implementing.
1871 There's no need to record whether the cc is valid afterwards because
1872 it is the AND insn that will decide this. */
1874 static const char *const rotate_one[2][3][3] =
1881 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
1884 /* SHIFT_LSHIFTRT */
1887 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
1890 /* SHIFT_ASHIFTRT */
1893 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
1905 /* SHIFT_LSHIFTRT */
1911 /* SHIFT_ASHIFTRT */
1920 static const char *const rotate_two[3][3] =
1928 /* SHIFT_LSHIFTRT */
1934 /* SHIFT_ASHIFTRT */
1942 static enum shift_alg get_shift_alg PARAMS ((enum attr_cpu, enum shift_type,
1943 enum machine_mode, int,
1944 const char **, const char **,
1947 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
1948 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
1949 We don't achieve maximum efficiency in all cases, but the hooks are here
1952 For now we just use lots of switch statements. Since we don't even come
1953 close to supporting all the cases, this is simplest. If this function ever
1954 gets too big, perhaps resort to a more table based lookup. Of course,
1955 at this point you may just wish to do it all in rtl.
1957 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
1958 1,2,3,4 will be inlined (1,2 for SI). */
1960 static enum shift_alg
1961 get_shift_alg (cpu, shift_type, mode, count, assembler_p,
1962 assembler2_p, cc_valid_p)
1964 enum shift_type shift_type;
1965 enum machine_mode mode;
1967 const char **assembler_p;
1968 const char **assembler2_p;
1971 enum shift_mode shift_mode;
1973 /* We don't handle negative shifts or shifts greater than the word size,
1974 they should have been handled already. */
1976 if (count < 0 || count > GET_MODE_BITSIZE (mode))
1982 shift_mode = QIshift;
1985 shift_mode = HIshift;
1988 shift_mode = SIshift;
1994 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
1995 It is up to the caller to know that looping clobbers cc. */
1996 *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler;
1998 *assembler2_p = shift_two[shift_type][shift_mode].assembler;
2000 *assembler2_p = NULL;
2001 *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid;
2003 /* Now look for cases we want to optimize. */
2009 return SHIFT_INLINE;
2012 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
2013 fast as SHIFT_ROT_AND, plus CC is valid. */
2014 if (TARGET_H8300S && count <= 6)
2015 return SHIFT_INLINE;
2017 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2018 through the entire value. */
2019 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2021 *assembler_p = "shll\t%X0\n\tsubx\t%X0,%X0";
2023 return SHIFT_SPECIAL;
2026 /* Other ASHIFTRTs are too much of a pain. */
2027 if (shift_type == SHIFT_ASHIFTRT)
2030 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */
2031 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2033 *assembler2_p = rotate_two[shift_type][shift_mode];
2035 return SHIFT_ROT_AND;
2040 return SHIFT_INLINE;
2041 else if (TARGET_H8300S && count <= 7)
2042 return SHIFT_INLINE;
2043 else if (count == 7)
2045 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2047 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2049 return SHIFT_SPECIAL;
2052 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2054 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2056 return SHIFT_SPECIAL;
2059 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2061 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2063 return SHIFT_SPECIAL;
2066 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2068 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2070 return SHIFT_SPECIAL;
2073 if (shift_type == SHIFT_ASHIFTRT)
2075 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2077 return SHIFT_SPECIAL;
2080 else if (count == 8)
2085 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2087 return SHIFT_SPECIAL;
2088 case SHIFT_LSHIFTRT:
2089 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2091 return SHIFT_SPECIAL;
2092 case SHIFT_ASHIFTRT:
2094 *assembler_p = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0\t";
2096 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2098 return SHIFT_SPECIAL;
2101 else if (count == 9)
2106 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
2108 return SHIFT_SPECIAL;
2109 case SHIFT_LSHIFTRT:
2110 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
2112 return SHIFT_SPECIAL;
2113 case SHIFT_ASHIFTRT:
2115 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
2117 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
2119 return SHIFT_SPECIAL;
2122 else if (count == 10)
2128 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\t";
2130 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2132 return SHIFT_SPECIAL;
2133 case SHIFT_LSHIFTRT:
2135 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
2137 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2139 return SHIFT_SPECIAL;
2140 case SHIFT_ASHIFTRT:
2142 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2143 else if (TARGET_H8300H)
2144 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2145 else if (TARGET_H8300S)
2146 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
2148 return SHIFT_SPECIAL;
2151 else if (count == 11)
2157 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
2159 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2161 return SHIFT_SPECIAL;
2162 case SHIFT_LSHIFTRT:
2164 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
2166 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2168 return SHIFT_SPECIAL;
2169 case SHIFT_ASHIFTRT:
2171 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2172 else if (TARGET_H8300H)
2173 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2174 else if (TARGET_H8300S)
2175 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
2177 return SHIFT_SPECIAL;
2180 else if (count == 12)
2186 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
2188 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2190 return SHIFT_SPECIAL;
2191 case SHIFT_LSHIFTRT:
2193 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
2195 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2197 return SHIFT_SPECIAL;
2198 case SHIFT_ASHIFTRT:
2200 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2201 else if (TARGET_H8300H)
2202 *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2203 else if (TARGET_H8300S)
2204 *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
2206 return SHIFT_SPECIAL;
2209 else if ((!TARGET_H8300 && (count == 13 || count == 14))
2212 if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2214 *assembler_p = "shll\t%t0,%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2216 return SHIFT_SPECIAL;
2218 else if (shift_type != SHIFT_ASHIFTRT)
2220 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2222 *assembler2_p = rotate_two[shift_type][shift_mode];
2224 *assembler2_p = NULL;
2226 return SHIFT_ROT_AND;
2232 if (count <= (TARGET_H8300 ? 2 : 4))
2233 return SHIFT_INLINE;
2234 else if (TARGET_H8300S && count <= 10)
2235 return SHIFT_INLINE;
2236 else if (count == 8 && TARGET_H8300)
2241 *assembler_p = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2243 return SHIFT_SPECIAL;
2244 case SHIFT_LSHIFTRT:
2245 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2247 return SHIFT_SPECIAL;
2248 case SHIFT_ASHIFTRT:
2249 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2251 return SHIFT_SPECIAL;
2254 else if (count == 8 && !TARGET_H8300)
2259 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2261 return SHIFT_SPECIAL;
2262 case SHIFT_LSHIFTRT:
2263 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2265 return SHIFT_SPECIAL;
2266 case SHIFT_ASHIFTRT:
2267 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2269 return SHIFT_SPECIAL;
2272 else if (count == 16)
2277 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2279 return SHIFT_SPECIAL;
2280 case SHIFT_LSHIFTRT:
2281 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2283 return SHIFT_SPECIAL;
2284 case SHIFT_ASHIFTRT:
2286 *assembler_p = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2288 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2290 return SHIFT_SPECIAL;
2293 else if (count == 17 && !TARGET_H8300)
2298 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
2300 return SHIFT_SPECIAL;
2301 case SHIFT_LSHIFTRT:
2302 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
2304 return SHIFT_SPECIAL;
2305 case SHIFT_ASHIFTRT:
2306 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
2308 return SHIFT_SPECIAL;
2311 else if (count == 18 && !TARGET_H8300)
2317 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
2319 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2321 return SHIFT_SPECIAL;
2322 case SHIFT_LSHIFTRT:
2324 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
2326 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2328 return SHIFT_SPECIAL;
2329 case SHIFT_ASHIFTRT:
2331 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
2333 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2335 return SHIFT_SPECIAL;
2338 else if (count == 19 && !TARGET_H8300)
2344 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
2346 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2348 return SHIFT_SPECIAL;
2349 case SHIFT_LSHIFTRT:
2351 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
2353 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2355 return SHIFT_SPECIAL;
2356 case SHIFT_ASHIFTRT:
2358 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
2360 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2362 return SHIFT_SPECIAL;
2365 else if (count == 20 && TARGET_H8300S)
2370 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
2372 return SHIFT_SPECIAL;
2373 case SHIFT_LSHIFTRT:
2374 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
2376 return SHIFT_SPECIAL;
2377 case SHIFT_ASHIFTRT:
2378 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
2380 return SHIFT_SPECIAL;
2383 else if (count == 24 && !TARGET_H8300)
2388 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2390 return SHIFT_SPECIAL;
2391 case SHIFT_LSHIFTRT:
2392 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2394 return SHIFT_SPECIAL;
2395 case SHIFT_ASHIFTRT:
2396 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2398 return SHIFT_SPECIAL;
2401 else if (count >= 28 && count <= 30 && !TARGET_H8300)
2403 if (shift_type == SHIFT_ASHIFTRT)
2409 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2411 *assembler2_p = rotate_two[shift_type][shift_mode];
2413 *assembler2_p = NULL;
2415 return SHIFT_ROT_AND;
2418 else if (count == 31)
2420 if (shift_type == SHIFT_ASHIFTRT)
2423 *assembler_p = "shll\t%z0\n\tsubx %w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2425 *assembler_p = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2427 return SHIFT_SPECIAL;
2433 if (shift_type == SHIFT_ASHIFT)
2434 *assembler_p = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2436 *assembler_p = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2438 return SHIFT_SPECIAL;
2442 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2444 *assembler2_p = rotate_two[shift_type][shift_mode];
2446 *assembler2_p = NULL;
2448 return SHIFT_ROT_AND;
2458 /* No fancy method is available. Just loop. */
2462 /* Emit the assembler code for doing shifts. */
2465 emit_a_shift (insn, operands)
2466 rtx insn ATTRIBUTE_UNUSED;
2469 static int loopend_lab;
2470 const char *assembler;
2471 const char *assembler2;
2473 rtx shift = operands[3];
2474 enum machine_mode mode = GET_MODE (shift);
2475 enum rtx_code code = GET_CODE (shift);
2476 enum shift_type shift_type;
2477 enum shift_mode shift_mode;
2484 shift_mode = QIshift;
2487 shift_mode = HIshift;
2490 shift_mode = SIshift;
2499 shift_type = SHIFT_ASHIFTRT;
2502 shift_type = SHIFT_LSHIFTRT;
2505 shift_type = SHIFT_ASHIFT;
2511 if (GET_CODE (operands[2]) != CONST_INT)
2513 /* Indexing by reg, so have to loop and test at top. */
2514 output_asm_insn ("mov.b %X2,%X4", operands);
2515 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2517 /* Get the assembler code to do one shift. */
2518 get_shift_alg (cpu_type, shift_type, mode, 1, &assembler,
2519 &assembler2, &cc_valid);
2521 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2522 output_asm_insn (assembler, operands);
2523 output_asm_insn ("add #0xff,%X4", operands);
2524 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2525 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2531 int n = INTVAL (operands[2]);
2534 /* If the count is negative, make it 0. */
2537 /* If the count is too big, truncate it.
2538 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2539 do the intuitive thing. */
2540 else if (n > GET_MODE_BITSIZE (mode))
2541 n = GET_MODE_BITSIZE (mode);
2543 alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler,
2544 &assembler2, &cc_valid);
2549 /* Emit two bit shifts first. */
2550 while (n > 1 && assembler2 != NULL)
2552 output_asm_insn (assembler2, operands);
2556 /* Now emit one bit shifts for any residual. */
2559 output_asm_insn (assembler, operands);
2563 /* Keep track of CC. */
2566 cc_status.value1 = operands[0];
2567 cc_status.flags |= cc_valid;
2573 int m = GET_MODE_BITSIZE (mode) - n;
2574 int mask = (shift_type == SHIFT_ASHIFT
2575 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2576 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2579 /* Not all possibilities of rotate are supported. They shouldn't
2580 be generated, but let's watch for 'em. */
2584 /* Emit two bit rotates first. */
2585 while (m > 1 && assembler2 != NULL)
2587 output_asm_insn (assembler2, operands);
2591 /* Now single bit rotates for any residual. */
2594 output_asm_insn (assembler, operands);
2598 /* Now mask off the high bits. */
2604 sprintf (insn_buf, "and #%d,%%X0", mask);
2605 cc_status.value1 = operands[0];
2606 cc_status.flags |= CC_NO_CARRY;
2609 sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0",
2610 mask & 255, mask >> 8);
2620 sprintf (insn_buf, "and.%c #%d,%%%c0",
2621 "bwl"[shift_mode], mask,
2622 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2623 cc_status.value1 = operands[0];
2624 cc_status.flags |= CC_NO_CARRY;
2626 output_asm_insn (insn_buf, operands);
2631 output_asm_insn (assembler, operands);
2635 /* A loop to shift by a "large" constant value.
2636 If we have shift-by-2 insns, use them. */
2637 if (assembler2 != NULL)
2639 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2640 names_big[REGNO (operands[4])]);
2641 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2642 output_asm_insn (assembler2, operands);
2643 output_asm_insn ("add #0xff,%X4", operands);
2644 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2646 output_asm_insn (assembler, operands);
2650 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2651 names_big[REGNO (operands[4])]);
2652 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2653 output_asm_insn (assembler, operands);
2654 output_asm_insn ("add #0xff,%X4", operands);
2655 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2665 /* Fix the operands of a gen_xxx so that it could become a bit
2669 fix_bit_operand (operands, what, type)
2674 /* The bit_operand predicate accepts any memory during RTL generation, but
2675 only 'U' memory afterwards, so if this is a MEM operand, we must force
2676 it to be valid for 'U' by reloading the address. */
2678 if (GET_CODE (operands[2]) == CONST_INT)
2680 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
2682 /* Ok to have a memory dest. */
2683 if (GET_CODE (operands[0]) == MEM && !EXTRA_CONSTRAINT (operands[0], 'U'))
2685 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
2686 copy_to_mode_reg (Pmode,
2687 XEXP (operands[0], 0)));
2688 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2692 if (GET_CODE (operands[1]) == MEM && !EXTRA_CONSTRAINT (operands[1], 'U'))
2694 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
2695 copy_to_mode_reg (Pmode,
2696 XEXP (operands[1], 0)));
2697 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2704 /* Dest and src op must be register. */
2706 operands[1] = force_reg (QImode, operands[1]);
2708 rtx res = gen_reg_rtx (QImode);
2709 emit_insn (gen_rtx_SET (VOIDmode, res,
2710 gen_rtx (type, QImode, operands[1], operands[2])));
2711 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
2716 /* Return nonzero if FUNC is an interrupt function as specified
2717 by the "interrupt" attribute. */
2720 h8300_interrupt_function_p (func)
2725 if (TREE_CODE (func) != FUNCTION_DECL)
2728 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
2729 return a != NULL_TREE;
2732 /* Return nonzero if FUNC is an OS_Task function as specified
2733 by the "OS_Task" attribute. */
2736 h8300_os_task_function_p (func)
2741 if (TREE_CODE (func) != FUNCTION_DECL)
2744 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
2745 return a != NULL_TREE;
2748 /* Return nonzero if FUNC is a monitor function as specified
2749 by the "monitor" attribute. */
2752 h8300_monitor_function_p (func)
2757 if (TREE_CODE (func) != FUNCTION_DECL)
2760 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
2761 return a != NULL_TREE;
2764 /* Return nonzero if FUNC is a function that should be called
2765 through the function vector. */
2768 h8300_funcvec_function_p (func)
2773 if (TREE_CODE (func) != FUNCTION_DECL)
2776 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
2777 return a != NULL_TREE;
2780 /* Return nonzero if DECL is a variable that's in the eight bit
2784 h8300_eightbit_data_p (decl)
2789 if (TREE_CODE (decl) != VAR_DECL)
2792 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
2793 return a != NULL_TREE;
2796 /* Return nonzero if DECL is a variable that's in the tiny
2800 h8300_tiny_data_p (decl)
2805 if (TREE_CODE (decl) != VAR_DECL)
2808 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
2809 return a != NULL_TREE;
2812 /* Return nonzero if ATTR is a valid attribute for DECL.
2813 ATTRIBUTES are any existing attributes and ARGS are the arguments
2816 Supported attributes:
2818 interrupt_handler: output a prologue and epilogue suitable for an
2821 function_vector: This function should be called through the
2824 eightbit_data: This variable lives in the 8-bit data area and can
2825 be referenced with 8-bit absolute memory addresses.
2827 tiny_data: This variable lives in the tiny data area and can be
2828 referenced with 16-bit absolute memory references. */
2831 h8300_valid_machine_decl_attribute (decl, attributes, attr, args)
2833 tree attributes ATTRIBUTE_UNUSED;
2837 if (args != NULL_TREE)
2840 if (is_attribute_p ("interrupt_handler", attr)
2841 || is_attribute_p ("OS_Task", attr)
2842 || is_attribute_p ("monitor", attr)
2843 || is_attribute_p ("function_vector", attr))
2844 return TREE_CODE (decl) == FUNCTION_DECL;
2846 if (is_attribute_p ("eightbit_data", attr)
2847 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
2849 if (DECL_INITIAL (decl) == NULL_TREE)
2851 warning ("Only initialized variables can be placed into the 8-bit area.");
2854 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
2858 if (is_attribute_p ("tiny_data", attr)
2859 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
2861 if (DECL_INITIAL (decl) == NULL_TREE)
2863 warning ("Only initialized variables can be placed into the 8-bit area.");
2866 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
2873 extern struct obstack *saveable_obstack;
2876 h8300_encode_label (decl)
2879 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2880 int len = strlen (str);
2883 newstr = obstack_alloc (saveable_obstack, len + 2);
2885 strcpy (newstr + 1, str);
2887 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2891 output_simode_bld (bild, log2, operands)
2896 /* Clear the destination register. */
2897 if (TARGET_H8300H || TARGET_H8300S)
2898 output_asm_insn ("sub.l\t%S0,%S0", operands);
2900 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
2902 /* Get the bit number we want to load. */
2904 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
2906 /* Now output the bit load or bit inverse load, and store it in
2909 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
2911 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
2917 /* Given INSN and its current length LENGTH, return the adjustment
2918 (in bytes) to correctly compute INSN's length.
2920 We use this to get the lengths of various memory references correct. */
2923 h8300_adjust_insn_length (insn, length)
2925 int length ATTRIBUTE_UNUSED;
2929 /* We must filter these ou before calling get_attr_adjust_length. */
2930 if (GET_CODE (PATTERN (insn)) == USE
2931 || GET_CODE (PATTERN (insn)) == CLOBBER
2932 || GET_CODE (PATTERN (insn)) == SEQUENCE
2933 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2934 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
2937 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
2940 pat = PATTERN (insn);
2942 /* Adjust length for reg->mem and mem->reg copies. */
2943 if (GET_CODE (pat) == SET
2944 && (GET_CODE (SET_SRC (pat)) == MEM
2945 || GET_CODE (SET_DEST (pat)) == MEM))
2947 /* This insn might need a length adjustment. */
2950 if (GET_CODE (SET_SRC (pat)) == MEM)
2951 addr = XEXP (SET_SRC (pat), 0);
2953 addr = XEXP (SET_DEST (pat), 0);
2955 /* On the H8/300, only one adjustment is necessary; if the
2956 address mode is register indirect, then this insn is two
2957 bytes shorter than indicated in the machine description. */
2958 if (TARGET_H8300 && GET_CODE (addr) == REG)
2961 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
2962 indicated in the machine description. */
2963 if ((TARGET_H8300H || TARGET_H8300S)
2964 && GET_CODE (addr) == REG)
2967 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
2968 bytes shorter than indicated in the machine description. */
2969 if ((TARGET_H8300H || TARGET_H8300S)
2970 && GET_CODE (addr) == PLUS
2971 && GET_CODE (XEXP (addr, 0)) == REG
2972 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2973 && INTVAL (XEXP (addr, 1)) > -32768
2974 && INTVAL (XEXP (addr, 1)) < 32767)
2977 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
2978 more general abs:24. */
2979 if ((TARGET_H8300H || TARGET_H8300S)
2980 && GET_CODE (addr) == SYMBOL_REF
2981 && TINY_DATA_NAME_P (XSTR (addr, 0)))
2985 /* Loading some constants needs adjustment. */
2986 if (GET_CODE (pat) == SET
2987 && GET_CODE (SET_SRC (pat)) == CONST_INT
2988 && GET_MODE (SET_DEST (pat)) == SImode
2989 && INTVAL (SET_SRC (pat)) != 0)
2992 && ((INTVAL (SET_SRC (pat)) & 0xffff) == 0
2993 || ((INTVAL (SET_SRC (pat)) >> 16) & 0xffff) == 0))
2996 if (TARGET_H8300H || TARGET_H8300S)
2998 int val = INTVAL (SET_SRC (pat));
3000 if (val == (val & 0xff)
3001 || val == (val & 0xff00))
3004 if (val == -4 || val == -2 || val == -1)
3009 /* Shifts need various adjustments. */
3010 if (GET_CODE (pat) == PARALLEL
3011 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3012 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3013 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3014 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3016 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3017 enum machine_mode mode = GET_MODE (src);
3020 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3023 shift = INTVAL (XEXP (src, 1));
3024 /* According to ANSI, negative shift is undefined. It is
3025 considered to be zero in this case (see function
3026 emit_a_shift above). */
3030 /* QImode shifts by small constants take one insn
3031 per shift. So the adjustment is 20 (md length) -
3033 if (mode == QImode && shift <= 4)
3034 return -(20 - shift * 2);
3036 /* Similarly for HImode and SImode shifts by
3037 small constants on the H8/300H and H8/300S. */
3038 if ((TARGET_H8300H || TARGET_H8300S)
3039 && (mode == HImode || mode == SImode) && shift <= 4)
3040 return -(20 - shift * 2);
3042 /* HImode shifts by small constants for the H8/300. */
3043 if (mode == HImode && shift <= 4)
3044 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3046 /* SImode shifts by small constants for the H8/300. */
3047 if (mode == SImode && shift <= 2)
3048 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3050 /* XXX ??? Could check for more shift/rotate cases here. */