1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Forward declarations. */
50 static const char *byte_reg (rtx, int);
51 static int h8300_interrupt_function_p (tree);
52 static int h8300_monitor_function_p (tree);
53 static int h8300_os_task_function_p (tree);
54 static void dosize (int, unsigned int);
55 static int round_frame_size (int);
56 static unsigned int compute_saved_regs (void);
57 static void push (int);
58 static void pop (int);
59 static const char *cond_string (enum rtx_code);
60 static unsigned int h8300_asm_insn_count (const char *);
61 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
62 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
63 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
64 #ifndef OBJECT_FORMAT_ELF
65 static void h8300_asm_named_section (const char *, unsigned int);
67 static int h8300_and_costs (rtx);
68 static int h8300_shift_costs (rtx);
70 /* CPU_TYPE, says what cpu we're compiling for. */
73 /* True if a #pragma interrupt has been seen for the current function. */
74 static int pragma_interrupt;
76 /* True if a #pragma saveall has been seen for the current function. */
77 static int pragma_saveall;
79 static const char *const names_big[] =
80 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
82 static const char *const names_extended[] =
83 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
85 static const char *const names_upper_extended[] =
86 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
88 /* Points to one of the above. */
89 /* ??? The above could be put in an array indexed by CPU_TYPE. */
90 const char * const *h8_reg_names;
92 /* Various operations needed by the following, indexed by CPU_TYPE. */
94 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
96 /* Machine-specific symbol_ref flags. */
97 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
98 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
99 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
101 /* See below where shifts are handled for explanation of this enum. */
111 /* Symbols of the various shifts which can be used as indices. */
115 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
118 /* Macros to keep the shift algorithm tables small. */
119 #define INL SHIFT_INLINE
120 #define ROT SHIFT_ROT_AND
121 #define LOP SHIFT_LOOP
122 #define SPC SHIFT_SPECIAL
124 /* The shift algorithms for each machine, mode, shift type, and shift
125 count are defined below. The three tables below correspond to
126 QImode, HImode, and SImode, respectively. Each table is organized
127 by, in the order of indices, machine, shift type, and shift count. */
129 static enum shift_alg shift_alg_qi[3][3][8] = {
132 /* 0 1 2 3 4 5 6 7 */
133 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
135 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
139 /* 0 1 2 3 4 5 6 7 */
140 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
142 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
146 /* 0 1 2 3 4 5 6 7 */
147 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
149 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
153 static enum shift_alg shift_alg_hi[3][3][16] = {
156 /* 0 1 2 3 4 5 6 7 */
157 /* 8 9 10 11 12 13 14 15 */
158 { INL, INL, INL, INL, INL, INL, INL, SPC,
159 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
160 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
161 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
162 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
163 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
167 /* 0 1 2 3 4 5 6 7 */
168 /* 8 9 10 11 12 13 14 15 */
169 { INL, INL, INL, INL, INL, INL, INL, SPC,
170 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
171 { INL, INL, INL, INL, INL, INL, INL, SPC,
172 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
173 { INL, INL, INL, INL, INL, INL, INL, SPC,
174 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
178 /* 0 1 2 3 4 5 6 7 */
179 /* 8 9 10 11 12 13 14 15 */
180 { INL, INL, INL, INL, INL, INL, INL, INL,
181 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
182 { INL, INL, INL, INL, INL, INL, INL, INL,
183 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
184 { INL, INL, INL, INL, INL, INL, INL, INL,
185 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
189 static enum shift_alg shift_alg_si[3][3][32] = {
192 /* 0 1 2 3 4 5 6 7 */
193 /* 8 9 10 11 12 13 14 15 */
194 /* 16 17 18 19 20 21 22 23 */
195 /* 24 25 26 27 28 29 30 31 */
196 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
197 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
198 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
200 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
201 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
202 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
203 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
204 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
205 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
206 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
207 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
211 /* 0 1 2 3 4 5 6 7 */
212 /* 8 9 10 11 12 13 14 15 */
213 /* 16 17 18 19 20 21 22 23 */
214 /* 24 25 26 27 28 29 30 31 */
215 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
216 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
217 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
218 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
219 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
220 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
221 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
222 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
223 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
224 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
225 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
226 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
230 /* 0 1 2 3 4 5 6 7 */
231 /* 8 9 10 11 12 13 14 15 */
232 /* 16 17 18 19 20 21 22 23 */
233 /* 24 25 26 27 28 29 30 31 */
234 { INL, INL, INL, INL, INL, INL, INL, INL,
235 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
236 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
237 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
238 { INL, INL, INL, INL, INL, INL, INL, INL,
239 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
240 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
241 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
242 { INL, INL, INL, INL, INL, INL, INL, INL,
243 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
244 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
245 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
261 /* Initialize various cpu specific globals at start up. */
264 h8300_init_once (void)
266 static const char *const h8_push_ops[2] = { "push" , "push.l" };
267 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
268 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
272 cpu_type = (int) CPU_H8300;
273 h8_reg_names = names_big;
277 /* For this we treat the H8/300H and H8S the same. */
278 cpu_type = (int) CPU_H8300H;
279 h8_reg_names = names_extended;
281 h8_push_op = h8_push_ops[cpu_type];
282 h8_pop_op = h8_pop_ops[cpu_type];
283 h8_mov_op = h8_mov_ops[cpu_type];
285 if (!TARGET_H8300S && TARGET_MAC)
287 error ("-ms2600 is used without -ms");
288 target_flags |= MASK_H8300S;
291 if (TARGET_H8300 && TARGET_NORMAL_MODE)
293 error ("-mn is used without -mh or -ms");
294 target_flags ^= MASK_NORMAL_MODE;
297 /* Some of the shifts are optimized for speed by default.
298 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
299 If optimizing for size, change shift_alg for those shift to
304 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
309 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
312 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
316 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
319 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
322 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
328 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
333 byte_reg (rtx x, int b)
335 static const char *const names_small[] = {
336 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
337 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
340 return names_small[REGNO (x) * 2 + b];
343 /* REGNO must be saved/restored across calls if this macro is true. */
345 #define WORD_REG_USED(regno) \
347 /* No need to save registers if this function will not return. */ \
348 && ! TREE_THIS_VOLATILE (current_function_decl) \
350 /* Save any call saved register that was used. */ \
351 || (regs_ever_live[regno] && !call_used_regs[regno]) \
352 /* Save the frame pointer if it was used. */ \
353 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
354 /* Save any register used in an interrupt handler. */ \
355 || (h8300_current_function_interrupt_function_p () \
356 && regs_ever_live[regno]) \
357 /* Save call clobbered registers in non-leaf interrupt \
359 || (h8300_current_function_interrupt_function_p () \
360 && call_used_regs[regno] \
361 && !current_function_is_leaf)))
363 /* Output assembly language to FILE for the operation OP with operand size
364 SIZE to adjust the stack pointer. */
371 /* H8/300 cannot add/subtract a large constant with a single
372 instruction. If a temporary register is available, load the
373 constant to it and then do the addition. */
376 && !h8300_current_function_interrupt_function_p ()
377 && !(current_function_needs_context && sign < 0))
380 rtx r3 = gen_rtx_REG (Pmode, 3);
381 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
382 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
383 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
387 /* The stack adjustment made here is further optimized by the
388 splitter. In case of H8/300, the splitter always splits the
389 addition emitted here to make the adjustment
391 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
392 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
396 /* Round up frame size SIZE. */
399 round_frame_size (int size)
401 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
402 & -STACK_BOUNDARY / BITS_PER_UNIT);
405 /* Compute which registers to push/pop.
406 Return a bit vector of registers. */
409 compute_saved_regs (void)
411 unsigned int saved_regs = 0;
414 /* Construct a bit vector of registers to be pushed/popped. */
415 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
417 if (WORD_REG_USED (regno))
418 saved_regs |= 1 << regno;
421 /* Don't push/pop the frame pointer as it is treated separately. */
422 if (frame_pointer_needed)
423 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
428 /* Emit an insn to push register RN. */
433 rtx reg = gen_rtx_REG (word_mode, rn);
437 x = gen_push_h8300 (reg);
439 x = gen_push_h8300hs (reg);
441 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
444 /* Emit an insn to pop register RN. */
449 rtx reg = gen_rtx_REG (word_mode, rn);
453 x = gen_pop_h8300 (reg);
455 x = gen_pop_h8300hs (reg);
457 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
460 /* This is what the stack looks like after the prolog of
461 a function with a frame has been set up:
467 <saved registers> <- sp
469 This is what the stack looks like after the prolog of
470 a function which doesn't have a frame:
475 <saved registers> <- sp
478 /* Generate RTL code for the function prologue. */
481 h8300_expand_prologue (void)
487 /* If the current function has the OS_Task attribute set, then
488 we have a naked prologue. */
489 if (h8300_os_task_function_p (current_function_decl))
492 if (h8300_monitor_function_p (current_function_decl))
493 /* My understanding of monitor functions is they act just like
494 interrupt functions, except the prologue must mask
496 emit_insn (gen_monitor_prologue ());
498 if (frame_pointer_needed)
501 push (FRAME_POINTER_REGNUM);
502 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
505 /* Leave room for locals. */
506 dosize (-1, round_frame_size (get_frame_size ()));
508 /* Push the rest of the registers in ascending order. */
509 saved_regs = compute_saved_regs ();
510 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
513 if (saved_regs & (1 << regno))
517 /* See how many registers we can push at the same time. */
518 if ((regno == 0 || regno == 4)
519 && ((saved_regs >> regno) & 0x0f) == 0x0f)
522 else if ((regno == 0 || regno == 4)
523 && ((saved_regs >> regno) & 0x07) == 0x07)
526 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
527 && ((saved_regs >> regno) & 0x03) == 0x03)
537 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
538 gen_rtx_REG (SImode, regno + 1)));
541 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
542 gen_rtx_REG (SImode, regno + 1),
543 gen_rtx_REG (SImode, regno + 2)));
546 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
547 gen_rtx_REG (SImode, regno + 1),
548 gen_rtx_REG (SImode, regno + 2),
549 gen_rtx_REG (SImode, regno + 3)));
559 h8300_can_use_return_insn_p (void)
561 return (reload_completed
562 && !frame_pointer_needed
563 && get_frame_size () == 0
564 && compute_saved_regs () == 0);
567 /* Generate RTL code for the function epilogue. */
570 h8300_expand_epilogue (void)
576 if (h8300_os_task_function_p (current_function_decl))
577 /* OS_Task epilogues are nearly naked -- they just have an
581 /* Pop the saved registers in descending order. */
582 saved_regs = compute_saved_regs ();
583 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
586 if (saved_regs & (1 << regno))
590 /* See how many registers we can pop at the same time. */
591 if ((regno == 7 || regno == 3)
592 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
595 else if ((regno == 6 || regno == 2)
596 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
599 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
600 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
610 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
611 gen_rtx_REG (SImode, regno)));
614 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
615 gen_rtx_REG (SImode, regno - 1),
616 gen_rtx_REG (SImode, regno)));
619 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
620 gen_rtx_REG (SImode, regno - 2),
621 gen_rtx_REG (SImode, regno - 1),
622 gen_rtx_REG (SImode, regno)));
630 /* Deallocate locals. */
631 dosize (1, round_frame_size (get_frame_size ()));
633 /* Pop frame pointer if we had one. */
634 if (frame_pointer_needed)
635 pop (FRAME_POINTER_REGNUM);
638 /* Output assembly language code for the function epilogue. */
641 h8300_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
642 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
647 /* Return nonzero if the current function is an interrupt
651 h8300_current_function_interrupt_function_p (void)
653 return (h8300_interrupt_function_p (current_function_decl)
654 || h8300_monitor_function_p (current_function_decl));
657 /* Output assembly code for the start of the file. */
660 h8300_file_start (void)
662 default_file_start ();
665 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
666 else if (TARGET_H8300S)
667 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
670 /* Output assembly language code for the end of file. */
673 h8300_file_end (void)
675 fputs ("\t.end\n", asm_out_file);
678 /* Return true if OP is a valid source operand for an integer move
682 general_operand_src (rtx op, enum machine_mode mode)
684 if (GET_MODE (op) == mode
685 && GET_CODE (op) == MEM
686 && GET_CODE (XEXP (op, 0)) == POST_INC)
688 return general_operand (op, mode);
691 /* Return true if OP is a valid destination operand for an integer move
695 general_operand_dst (rtx op, enum machine_mode mode)
697 if (GET_MODE (op) == mode
698 && GET_CODE (op) == MEM
699 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
701 return general_operand (op, mode);
704 /* Return true if OP is a constant that contains only one 1 in its
705 binary representation. */
708 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
710 if (GET_CODE (operand) == CONST_INT)
712 /* We really need to do this masking because 0x80 in QImode is
713 represented as -128 for example. */
714 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
721 /* Return true if OP is a constant that contains only one 0 in its
722 binary representation. */
725 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
727 if (GET_CODE (operand) == CONST_INT)
729 /* We really need to do this masking because 0x80 in QImode is
730 represented as -128 for example. */
731 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
738 /* Return true if OP is a valid call operand. */
741 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
743 if (GET_CODE (op) == MEM)
745 rtx inside = XEXP (op, 0);
746 if (register_operand (inside, Pmode))
748 if (CONSTANT_ADDRESS_P (inside))
754 /* Return 1 if an addition/subtraction of a constant integer can be
755 transformed into two consecutive adds/subs that are faster than the
756 straightforward way. Otherwise, return 0. */
759 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
761 if (GET_CODE (op) == CONST_INT)
763 HOST_WIDE_INT value = INTVAL (op);
765 /* Force VALUE to be positive so that we do not have to consider
766 the negative case. */
769 if (TARGET_H8300H || TARGET_H8300S)
771 /* A constant addition/subtraction takes 2 states in QImode,
772 4 states in HImode, and 6 states in SImode. Thus, the
773 only case we can win is when SImode is used, in which
774 case, two adds/subs are used, taking 4 states. */
784 /* We do not profit directly by splitting addition or
785 subtraction of 3 and 4. However, since these are
786 implemented as a sequence of adds or subs, they do not
787 clobber (cc0) unlike a sequence of add.b and add.x. */
798 /* Split an add of a small constant into two adds/subs insns.
800 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
801 instead of adds/subs. */
804 split_adds_subs (enum machine_mode mode, rtx *operands)
806 HOST_WIDE_INT val = INTVAL (operands[1]);
807 rtx reg = operands[0];
808 HOST_WIDE_INT sign = 1;
809 HOST_WIDE_INT amount;
810 rtx (*gen_add) (rtx, rtx, rtx);
812 /* Force VAL to be positive so that we do not have to consider the
823 gen_add = gen_addhi3;
827 gen_add = gen_addsi3;
834 /* Try different amounts in descending order. */
835 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
839 for (; val >= amount; val -= amount)
840 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
846 /* Return true if OP is a valid call operand, and OP represents
847 an operand for a small call (4 bytes instead of 6 bytes). */
850 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
852 if (GET_CODE (op) == MEM)
854 rtx inside = XEXP (op, 0);
856 /* Register indirect is a small call. */
857 if (register_operand (inside, Pmode))
860 /* A call through the function vector is a small call too. */
861 if (GET_CODE (inside) == SYMBOL_REF
862 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
865 /* Otherwise it's a large call. */
869 /* Return true if OP is a valid jump operand. */
872 jump_address_operand (rtx op, enum machine_mode mode)
874 if (GET_CODE (op) == REG)
875 return mode == Pmode;
877 if (GET_CODE (op) == MEM)
879 rtx inside = XEXP (op, 0);
880 if (register_operand (inside, Pmode))
882 if (CONSTANT_ADDRESS_P (inside))
888 /* Recognize valid operands for bit-field instructions. */
890 extern int rtx_equal_function_value_matters;
893 bit_operand (rtx op, enum machine_mode mode)
895 /* We can accept any general operand, except that MEM operands must
896 be limited to those that use addresses valid for the 'U' constraint. */
897 if (!general_operand (op, mode))
900 /* Accept any mem during RTL generation. Otherwise, the code that does
901 insv and extzv will think that we can not handle memory. However,
902 to avoid reload problems, we only accept 'U' MEM operands after RTL
903 generation. This means that any named pattern which uses this predicate
904 must force its operands to match 'U' before emitting RTL. */
906 if (GET_CODE (op) == REG)
908 if (GET_CODE (op) == SUBREG)
910 return (GET_CODE (op) == MEM
911 && EXTRA_CONSTRAINT (op, 'U'));
915 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
917 return (GET_CODE (op) == MEM
918 && EXTRA_CONSTRAINT (op, 'U'));
921 /* Handle machine specific pragmas for compatibility with existing
922 compilers for the H8/300.
924 pragma saveall generates prologue/epilogue code which saves and
925 restores all the registers on function entry.
927 pragma interrupt saves and restores all registers, and exits with
928 an rte instruction rather than an rts. A pointer to a function
929 with this attribute may be safely used in an interrupt vector. */
932 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
934 pragma_interrupt = 1;
938 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
943 /* If the next function argument with MODE and TYPE is to be passed in
944 a register, return a reg RTX for the hard register in which to pass
945 the argument. CUM represents the state after the last argument.
946 If the argument is to be pushed, NULL_RTX is returned. */
949 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
950 tree type, int named)
952 static const char *const hand_list[] = {
971 rtx result = NULL_RTX;
975 /* Never pass unnamed arguments in registers. */
979 /* Pass 3 regs worth of data in regs when user asked on the command line. */
980 if (TARGET_QUICKCALL)
983 /* If calling hand written assembler, use 4 regs of args. */
986 const char * const *p;
988 fname = XSTR (cum->libcall, 0);
990 /* See if this libcall is one of the hand coded ones. */
991 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1002 if (mode == BLKmode)
1003 size = int_size_in_bytes (type);
1005 size = GET_MODE_SIZE (mode);
1007 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1008 && cum->nbytes / UNITS_PER_WORD <= 3)
1009 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1016 h8300_and_costs (rtx x)
1020 if (GET_MODE (x) == QImode)
1023 if (GET_MODE (x) != HImode
1024 && GET_MODE (x) != SImode)
1029 operands[2] = XEXP (x, 1);
1031 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1035 h8300_shift_costs (rtx x)
1039 if (GET_MODE (x) != QImode
1040 && GET_MODE (x) != HImode
1041 && GET_MODE (x) != SImode)
1046 operands[2] = XEXP (x, 1);
1048 return compute_a_shift_length (NULL, operands) / 2;
1052 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1058 HOST_WIDE_INT n = INTVAL (x);
1060 if (-4 <= n || n <= 4)
1071 *total = 0 + (outer_code == SET);
1075 if (TARGET_H8300H || TARGET_H8300S)
1076 *total = 0 + (outer_code == SET);
1097 *total = COSTS_N_INSNS (h8300_and_costs (x));
1100 /* We say that MOD and DIV are so expensive because otherwise we'll
1101 generate some really horrible code for division of a power of two. */
1114 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1119 if (GET_MODE (x) == HImode)
1131 /* Documentation for the machine specific operand escapes:
1133 'E' like s but negative.
1134 'F' like t but negative.
1135 'G' constant just the negative
1136 'R' print operand as a byte:8 address if appropriate, else fall back to
1138 'S' print operand as a long word
1139 'T' print operand as a word
1140 'V' find the set bit, and print its number.
1141 'W' find the clear bit, and print its number.
1142 'X' print operand as a byte
1143 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1144 If this operand isn't a register, fall back to 'R' handling.
1146 'c' print the opcode corresponding to rtl
1147 'e' first word of 32 bit value - if reg, then least reg. if mem
1148 then least. if const then most sig word
1149 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1150 then +2. if const then least sig word
1151 'j' print operand as condition code.
1152 'k' print operand as reverse condition code.
1153 's' print as low byte of 16 bit value
1154 't' print as high byte of 16 bit value
1155 'w' print as low byte of 32 bit value
1156 'x' print as 2nd byte of 32 bit value
1157 'y' print as 3rd byte of 32 bit value
1158 'z' print as msb of 32 bit value
1161 /* Return assembly language string which identifies a comparison type. */
1164 cond_string (enum rtx_code code)
1193 /* Print operand X using operand code CODE to assembly language output file
1197 print_operand (FILE *file, rtx x, int code)
1199 /* This is used for communication between codes V,W,Z and Y. */
1205 switch (GET_CODE (x))
1208 fprintf (file, "%sl", names_big[REGNO (x)]);
1211 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1218 switch (GET_CODE (x))
1221 fprintf (file, "%sh", names_big[REGNO (x)]);
1224 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1231 if (GET_CODE (x) != CONST_INT)
1233 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1236 if (GET_CODE (x) == REG)
1237 fprintf (file, "%s", names_extended[REGNO (x)]);
1242 if (GET_CODE (x) == REG)
1243 fprintf (file, "%s", names_big[REGNO (x)]);
1248 bitint = exact_log2 (INTVAL (x) & 0xff);
1251 fprintf (file, "#%d", bitint);
1254 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1257 fprintf (file, "#%d", bitint);
1261 if (GET_CODE (x) == REG)
1262 fprintf (file, "%s", byte_reg (x, 0));
1269 if (GET_CODE (x) == REG)
1270 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1272 print_operand (file, x, 'R');
1276 bitint = INTVAL (x);
1277 fprintf (file, "#%d", bitint & 7);
1280 switch (GET_CODE (x))
1283 fprintf (file, "or");
1286 fprintf (file, "xor");
1289 fprintf (file, "and");
1296 switch (GET_CODE (x))
1300 fprintf (file, "%s", names_big[REGNO (x)]);
1302 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1305 print_operand (file, x, 0);
1308 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1314 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1315 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1316 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1325 switch (GET_CODE (x))
1329 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1331 fprintf (file, "%s", names_big[REGNO (x)]);
1334 x = adjust_address (x, HImode, 2);
1335 print_operand (file, x, 0);
1338 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1344 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1345 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1346 fprintf (file, "#%ld", (val & 0xffff));
1354 fputs (cond_string (GET_CODE (x)), file);
1357 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1360 if (GET_CODE (x) == CONST_INT)
1361 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1363 fprintf (file, "%s", byte_reg (x, 0));
1366 if (GET_CODE (x) == CONST_INT)
1367 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1369 fprintf (file, "%s", byte_reg (x, 1));
1372 if (GET_CODE (x) == CONST_INT)
1373 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1375 fprintf (file, "%s",
1376 byte_reg (x, TARGET_H8300 ? 2 : 0));
1379 if (GET_CODE (x) == CONST_INT)
1380 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1382 fprintf (file, "%s",
1383 byte_reg (x, TARGET_H8300 ? 3 : 1));
1386 if (GET_CODE (x) == CONST_INT)
1387 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1389 fprintf (file, "%s", byte_reg (x, 0));
1392 if (GET_CODE (x) == CONST_INT)
1393 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1395 fprintf (file, "%s", byte_reg (x, 1));
1400 switch (GET_CODE (x))
1403 switch (GET_MODE (x))
1406 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1407 fprintf (file, "%s", byte_reg (x, 0));
1408 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1409 fprintf (file, "%s", names_big[REGNO (x)]);
1413 fprintf (file, "%s", names_big[REGNO (x)]);
1417 fprintf (file, "%s", names_extended[REGNO (x)]);
1426 rtx addr = XEXP (x, 0);
1428 fprintf (file, "@");
1429 output_address (addr);
1431 /* We fall back from smaller addressing to larger
1432 addressing in various ways depending on CODE. */
1436 /* Used for mov.b and bit operations. */
1437 if (h8300_eightbit_constant_address_p (addr))
1439 fprintf (file, ":8");
1443 /* Fall through. We should not get here if we are
1444 processing bit operations on H8/300 or H8/300H
1445 because 'U' constraint does not allow bit
1446 operations on the tiny area on these machines. */
1450 /* Used for mov.w and mov.l. */
1451 if (h8300_tiny_constant_address_p (addr))
1452 fprintf (file, ":16");
1464 fprintf (file, "#");
1465 print_operand_address (file, x);
1471 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1472 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1473 fprintf (file, "#%ld", val);
1482 /* Output assembly language output for the address ADDR to FILE. */
1485 print_operand_address (FILE *file, rtx addr)
1487 switch (GET_CODE (addr))
1490 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1494 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1498 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1502 fprintf (file, "(");
1503 if (GET_CODE (XEXP (addr, 0)) == REG)
1506 print_operand_address (file, XEXP (addr, 1));
1507 fprintf (file, ",");
1508 print_operand_address (file, XEXP (addr, 0));
1513 print_operand_address (file, XEXP (addr, 0));
1514 fprintf (file, "+");
1515 print_operand_address (file, XEXP (addr, 1));
1517 fprintf (file, ")");
1522 /* Since the H8/300 only has 16 bit pointers, negative values are also
1523 those >= 32768. This happens for example with pointer minus a
1524 constant. We don't want to turn (char *p - 2) into
1525 (char *p + 65534) because loop unrolling can build upon this
1526 (IE: char *p + 131068). */
1527 int n = INTVAL (addr);
1529 n = (int) (short) n;
1530 fprintf (file, "%d", n);
1535 output_addr_const (file, addr);
1540 /* Output all insn addresses and their sizes into the assembly language
1541 output file. This is helpful for debugging whether the length attributes
1542 in the md file are correct. This is not meant to be a user selectable
1546 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1547 int num_operands ATTRIBUTE_UNUSED)
1549 /* This holds the last insn address. */
1550 static int last_insn_address = 0;
1552 const int uid = INSN_UID (insn);
1554 if (TARGET_ADDRESSES)
1556 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1557 INSN_ADDRESSES (uid) - last_insn_address);
1558 last_insn_address = INSN_ADDRESSES (uid);
1562 /* Prepare for an SI sized move. */
1565 do_movsi (rtx operands[])
1567 rtx src = operands[1];
1568 rtx dst = operands[0];
1569 if (!reload_in_progress && !reload_completed)
1571 if (!register_operand (dst, GET_MODE (dst)))
1573 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1574 emit_move_insn (tmp, src);
1581 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1582 Define the offset between two registers, one to be eliminated, and
1583 the other its replacement, at the start of a routine. */
1586 h8300_initial_elimination_offset (int from, int to)
1589 /* The number of bytes that the return address takes on the stack. */
1590 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1592 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1593 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1594 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1595 offset = frame_pointer_needed * UNITS_PER_WORD;
1600 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1601 if (WORD_REG_USED (regno))
1602 offset += UNITS_PER_WORD;
1604 /* See the comments for get_frame_size. We need to round it up to
1607 offset += round_frame_size (get_frame_size ());
1609 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1610 /* Skip saved PC. */
1618 h8300_return_addr_rtx (int count, rtx frame)
1623 ret = gen_rtx_MEM (Pmode,
1624 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1625 else if (flag_omit_frame_pointer)
1628 ret = gen_rtx_MEM (Pmode,
1629 memory_address (Pmode,
1630 plus_constant (frame, UNITS_PER_WORD)));
1631 set_mem_alias_set (ret, get_frame_alias_set ());
1635 /* Update the condition code from the insn. */
1638 notice_update_cc (rtx body, rtx insn)
1642 switch (get_attr_cc (insn))
1645 /* Insn does not affect CC at all. */
1649 /* Insn does not change CC, but the 0'th operand has been changed. */
1650 if (cc_status.value1 != 0
1651 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1652 cc_status.value1 = 0;
1653 if (cc_status.value2 != 0
1654 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1655 cc_status.value2 = 0;
1659 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1660 The V flag is unusable. The C flag may or may not be known but
1661 that's ok because alter_cond will change tests to use EQ/NE. */
1663 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1664 set = single_set (insn);
1665 cc_status.value1 = SET_SRC (set);
1666 if (SET_DEST (set) != cc0_rtx)
1667 cc_status.value2 = SET_DEST (set);
1671 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1672 The C flag may or may not be known but that's ok because
1673 alter_cond will change tests to use EQ/NE. */
1675 cc_status.flags |= CC_NO_CARRY;
1676 set = single_set (insn);
1677 cc_status.value1 = SET_SRC (set);
1678 if (SET_DEST (set) != cc0_rtx)
1680 /* If the destination is STRICT_LOW_PART, strip off
1682 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1683 cc_status.value2 = XEXP (SET_DEST (set), 0);
1685 cc_status.value2 = SET_DEST (set);
1690 /* The insn is a compare instruction. */
1692 cc_status.value1 = SET_SRC (body);
1696 /* Insn doesn't leave CC in a usable state. */
1702 /* Return nonzero if X is a stack pointer. */
1705 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1707 return x == stack_pointer_rtx;
1710 /* Return nonzero if X is a constant whose absolute value is greater
1714 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1716 return (GET_CODE (x) == CONST_INT
1717 && abs (INTVAL (x)) > 2);
1720 /* Return nonzero if X is a constant whose absolute value is no
1724 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1726 return (GET_CODE (x) == CONST_INT
1727 && abs (INTVAL (x)) >= 8);
1730 /* Return nonzero if X is a constant expressible in QImode. */
1733 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1735 return (GET_CODE (x) == CONST_INT
1736 && (INTVAL (x) & 0xff) == INTVAL (x));
1739 /* Return nonzero if X is a constant expressible in HImode. */
1742 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1744 return (GET_CODE (x) == CONST_INT
1745 && (INTVAL (x) & 0xffff) == INTVAL (x));
1748 /* Return nonzero if X is a constant suitable for inc/dec. */
1751 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1753 return (GET_CODE (x) == CONST_INT
1754 && (CONST_OK_FOR_M (INTVAL (x))
1755 || CONST_OK_FOR_O (INTVAL (x))));
1758 /* Return nonzero if X is either EQ or NE. */
1761 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1763 enum rtx_code code = GET_CODE (x);
1765 return (code == EQ || code == NE);
1768 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1771 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1773 enum rtx_code code = GET_CODE (x);
1775 return (code == GT || code == LE || code == GTU || code == LEU);
1778 /* Return nonzero if X is either GTU or LEU. */
1781 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1783 enum rtx_code code = GET_CODE (x);
1785 return (code == GTU || code == LEU);
1788 /* Return nonzero if X is either IOR or XOR. */
1791 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1793 enum rtx_code code = GET_CODE (x);
1795 return (code == IOR || code == XOR);
1798 /* Recognize valid operators for bit instructions. */
1801 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1803 enum rtx_code code = GET_CODE (x);
1810 /* Return the length of mov instruction. */
1813 compute_mov_length (rtx *operands)
1815 /* If the mov instruction involves a memory operand, we compute the
1816 length, assuming the largest addressing mode is used, and then
1817 adjust later in the function. Otherwise, we compute and return
1818 the exact length in one step. */
1819 enum machine_mode mode = GET_MODE (operands[0]);
1820 rtx dest = operands[0];
1821 rtx src = operands[1];
1824 if (GET_CODE (src) == MEM)
1825 addr = XEXP (src, 0);
1826 else if (GET_CODE (dest) == MEM)
1827 addr = XEXP (dest, 0);
1833 unsigned int base_length;
1838 if (addr == NULL_RTX)
1841 /* The eightbit addressing is available only in QImode, so
1842 go ahead and take care of it. */
1843 if (h8300_eightbit_constant_address_p (addr))
1850 if (addr == NULL_RTX)
1855 if (src == const0_rtx)
1865 if (addr == NULL_RTX)
1870 if (GET_CODE (src) == CONST_INT)
1872 if (src == const0_rtx)
1875 if ((INTVAL (src) & 0xffff) == 0)
1878 if ((INTVAL (src) & 0xffff) == 0)
1881 if ((INTVAL (src) & 0xffff)
1882 == ((INTVAL (src) >> 16) & 0xffff))
1892 if (addr == NULL_RTX)
1897 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1910 /* Adjust the length based on the addressing mode used.
1911 Specifically, we subtract the difference between the actual
1912 length and the longest one, which is @(d:16,Rs). For SImode
1913 and SFmode, we double the adjustment because two mov.w are
1914 used to do the job. */
1916 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1917 if (GET_CODE (addr) == PRE_DEC
1918 || GET_CODE (addr) == POST_INC)
1920 if (mode == QImode || mode == HImode)
1921 return base_length - 2;
1923 /* In SImode and SFmode, we use two mov.w instructions, so
1924 double the adjustment. */
1925 return base_length - 4;
1928 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1929 in SImode and SFmode, the second mov.w involves an address
1930 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1932 if (GET_CODE (addr) == REG)
1933 return base_length - 2;
1939 unsigned int base_length;
1944 if (addr == NULL_RTX)
1947 /* The eightbit addressing is available only in QImode, so
1948 go ahead and take care of it. */
1949 if (h8300_eightbit_constant_address_p (addr))
1956 if (addr == NULL_RTX)
1961 if (src == const0_rtx)
1971 if (addr == NULL_RTX)
1975 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
1981 if (GET_CODE (src) == CONST_INT)
1983 int val = INTVAL (src);
1988 if (val == (val & 0x00ff) || val == (val & 0xff00))
1991 switch (val & 0xffffffff)
2012 if (addr == NULL_RTX)
2017 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2030 /* Adjust the length based on the addressing mode used.
2031 Specifically, we subtract the difference between the actual
2032 length and the longest one, which is @(d:24,ERs). */
2034 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2035 if (GET_CODE (addr) == PRE_DEC
2036 || GET_CODE (addr) == POST_INC)
2037 return base_length - 6;
2039 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2040 if (GET_CODE (addr) == REG)
2041 return base_length - 6;
2043 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2045 if (GET_CODE (addr) == PLUS
2046 && GET_CODE (XEXP (addr, 0)) == REG
2047 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2048 && INTVAL (XEXP (addr, 1)) > -32768
2049 && INTVAL (XEXP (addr, 1)) < 32767)
2050 return base_length - 4;
2052 /* @aa:16 is 4 bytes shorter than the longest. */
2053 if (h8300_tiny_constant_address_p (addr))
2054 return base_length - 4;
2056 /* @aa:24 is 2 bytes shorter than the longest. */
2057 if (CONSTANT_P (addr))
2058 return base_length - 2;
2065 output_plussi (rtx *operands)
2067 enum machine_mode mode = GET_MODE (operands[0]);
2074 if (GET_CODE (operands[2]) == REG)
2075 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2077 if (GET_CODE (operands[2]) == CONST_INT)
2079 HOST_WIDE_INT n = INTVAL (operands[2]);
2081 if ((n & 0xffffff) == 0)
2082 return "add\t%z2,%z0";
2083 if ((n & 0xffff) == 0)
2084 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2085 if ((n & 0xff) == 0)
2086 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2089 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2093 if (GET_CODE (operands[2]) == REG)
2094 return "add.l\t%S2,%S0";
2096 if (GET_CODE (operands[2]) == CONST_INT)
2098 HOST_WIDE_INT intval = INTVAL (operands[2]);
2100 /* See if we can finish with 2 bytes. */
2102 switch ((unsigned int) intval & 0xffffffff)
2107 return "adds\t%2,%S0";
2112 return "subs\t%G2,%S0";
2116 operands[2] = GEN_INT (intval >> 16);
2117 return "inc.w\t%2,%e0";
2121 operands[2] = GEN_INT (intval >> 16);
2122 return "dec.w\t%G2,%e0";
2125 /* See if we can finish with 4 bytes. */
2126 if ((intval & 0xffff) == 0)
2128 operands[2] = GEN_INT (intval >> 16);
2129 return "add.w\t%2,%e0";
2133 return "add.l\t%S2,%S0";
2138 compute_plussi_length (rtx *operands)
2140 enum machine_mode mode = GET_MODE (operands[0]);
2147 if (GET_CODE (operands[2]) == REG)
2150 if (GET_CODE (operands[2]) == CONST_INT)
2152 HOST_WIDE_INT n = INTVAL (operands[2]);
2154 if ((n & 0xffffff) == 0)
2156 if ((n & 0xffff) == 0)
2158 if ((n & 0xff) == 0)
2166 if (GET_CODE (operands[2]) == REG)
2169 if (GET_CODE (operands[2]) == CONST_INT)
2171 HOST_WIDE_INT intval = INTVAL (operands[2]);
2173 /* See if we can finish with 2 bytes. */
2175 switch ((unsigned int) intval & 0xffffffff)
2196 /* See if we can finish with 4 bytes. */
2197 if ((intval & 0xffff) == 0)
2206 compute_plussi_cc (rtx *operands)
2208 enum machine_mode mode = GET_MODE (operands[0]);
2219 if (GET_CODE (operands[2]) == REG)
2222 if (GET_CODE (operands[2]) == CONST_INT)
2224 HOST_WIDE_INT intval = INTVAL (operands[2]);
2226 /* See if we can finish with 2 bytes. */
2228 switch ((unsigned int) intval & 0xffffffff)
2233 return CC_NONE_0HIT;
2238 return CC_NONE_0HIT;
2249 /* See if we can finish with 4 bytes. */
2250 if ((intval & 0xffff) == 0)
2259 output_logical_op (enum machine_mode mode, rtx *operands)
2261 /* Figure out the logical op that we need to perform. */
2262 enum rtx_code code = GET_CODE (operands[3]);
2263 /* Pretend that every byte is affected if both operands are registers. */
2264 const unsigned HOST_WIDE_INT intval =
2265 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2266 ? INTVAL (operands[2]) : 0x55555555);
2267 /* The determinant of the algorithm. If we perform an AND, 0
2268 affects a bit. Otherwise, 1 affects a bit. */
2269 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2270 /* Break up DET into pieces. */
2271 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2272 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2273 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2274 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2275 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2276 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2277 int lower_half_easy_p = 0;
2278 int upper_half_easy_p = 0;
2279 /* The name of an insn. */
2301 /* First, see if we can finish with one insn. */
2302 if ((TARGET_H8300H || TARGET_H8300S)
2306 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2307 output_asm_insn (insn_buf, operands);
2311 /* Take care of the lower byte. */
2314 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2315 output_asm_insn (insn_buf, operands);
2317 /* Take care of the upper byte. */
2320 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2321 output_asm_insn (insn_buf, operands);
2326 if (TARGET_H8300H || TARGET_H8300S)
2328 /* Determine if the lower half can be taken care of in no more
2330 lower_half_easy_p = (b0 == 0
2332 || (code != IOR && w0 == 0xffff));
2334 /* Determine if the upper half can be taken care of in no more
2336 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2337 || (code == AND && w1 == 0xff00));
2340 /* Check if doing everything with one insn is no worse than
2341 using multiple insns. */
2342 if ((TARGET_H8300H || TARGET_H8300S)
2343 && w0 != 0 && w1 != 0
2344 && !(lower_half_easy_p && upper_half_easy_p)
2345 && !(code == IOR && w1 == 0xffff
2346 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2348 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2349 output_asm_insn (insn_buf, operands);
2353 /* Take care of the lower and upper words individually. For
2354 each word, we try different methods in the order of
2356 1) the special insn (in case of AND or XOR),
2357 2) the word-wise insn, and
2358 3) The byte-wise insn. */
2360 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2361 output_asm_insn ((code == AND)
2362 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2364 else if ((TARGET_H8300H || TARGET_H8300S)
2368 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2369 output_asm_insn (insn_buf, operands);
2375 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2376 output_asm_insn (insn_buf, operands);
2380 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2381 output_asm_insn (insn_buf, operands);
2386 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2387 output_asm_insn ((code == AND)
2388 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2390 else if ((TARGET_H8300H || TARGET_H8300S)
2393 && (w0 & 0x8000) != 0)
2395 output_asm_insn ("exts.l\t%S0", operands);
2397 else if ((TARGET_H8300H || TARGET_H8300S)
2401 output_asm_insn ("extu.w\t%e0", operands);
2403 else if (TARGET_H8300H || TARGET_H8300S)
2407 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2408 output_asm_insn (insn_buf, operands);
2415 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2416 output_asm_insn (insn_buf, operands);
2420 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2421 output_asm_insn (insn_buf, operands);
2433 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2435 /* Figure out the logical op that we need to perform. */
2436 enum rtx_code code = GET_CODE (operands[3]);
2437 /* Pretend that every byte is affected if both operands are registers. */
2438 const unsigned HOST_WIDE_INT intval =
2439 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2440 ? INTVAL (operands[2]) : 0x55555555);
2441 /* The determinant of the algorithm. If we perform an AND, 0
2442 affects a bit. Otherwise, 1 affects a bit. */
2443 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2444 /* Break up DET into pieces. */
2445 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2446 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2447 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2448 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2449 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2450 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2451 int lower_half_easy_p = 0;
2452 int upper_half_easy_p = 0;
2454 unsigned int length = 0;
2459 /* First, see if we can finish with one insn. */
2460 if ((TARGET_H8300H || TARGET_H8300S)
2464 if (REG_P (operands[2]))
2471 /* Take care of the lower byte. */
2475 /* Take care of the upper byte. */
2481 if (TARGET_H8300H || TARGET_H8300S)
2483 /* Determine if the lower half can be taken care of in no more
2485 lower_half_easy_p = (b0 == 0
2487 || (code != IOR && w0 == 0xffff));
2489 /* Determine if the upper half can be taken care of in no more
2491 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2492 || (code == AND && w1 == 0xff00));
2495 /* Check if doing everything with one insn is no worse than
2496 using multiple insns. */
2497 if ((TARGET_H8300H || TARGET_H8300S)
2498 && w0 != 0 && w1 != 0
2499 && !(lower_half_easy_p && upper_half_easy_p)
2500 && !(code == IOR && w1 == 0xffff
2501 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2503 if (REG_P (operands[2]))
2510 /* Take care of the lower and upper words individually. For
2511 each word, we try different methods in the order of
2513 1) the special insn (in case of AND or XOR),
2514 2) the word-wise insn, and
2515 3) The byte-wise insn. */
2517 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2521 else if ((TARGET_H8300H || TARGET_H8300S)
2537 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2541 else if ((TARGET_H8300H || TARGET_H8300S)
2544 && (w0 & 0x8000) != 0)
2548 else if ((TARGET_H8300H || TARGET_H8300S)
2554 else if (TARGET_H8300H || TARGET_H8300S)
2576 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2578 /* Figure out the logical op that we need to perform. */
2579 enum rtx_code code = GET_CODE (operands[3]);
2580 /* Pretend that every byte is affected if both operands are registers. */
2581 const unsigned HOST_WIDE_INT intval =
2582 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2583 ? INTVAL (operands[2]) : 0x55555555);
2584 /* The determinant of the algorithm. If we perform an AND, 0
2585 affects a bit. Otherwise, 1 affects a bit. */
2586 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2587 /* Break up DET into pieces. */
2588 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2589 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2590 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2591 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2592 int lower_half_easy_p = 0;
2593 int upper_half_easy_p = 0;
2594 /* Condition code. */
2595 enum attr_cc cc = CC_CLOBBER;
2600 /* First, see if we can finish with one insn. */
2601 if ((TARGET_H8300H || TARGET_H8300S)
2609 if (TARGET_H8300H || TARGET_H8300S)
2611 /* Determine if the lower half can be taken care of in no more
2613 lower_half_easy_p = (b0 == 0
2615 || (code != IOR && w0 == 0xffff));
2617 /* Determine if the upper half can be taken care of in no more
2619 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2620 || (code == AND && w1 == 0xff00));
2623 /* Check if doing everything with one insn is no worse than
2624 using multiple insns. */
2625 if ((TARGET_H8300H || TARGET_H8300S)
2626 && w0 != 0 && w1 != 0
2627 && !(lower_half_easy_p && upper_half_easy_p)
2628 && !(code == IOR && w1 == 0xffff
2629 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2635 if ((TARGET_H8300H || TARGET_H8300S)
2638 && (w0 & 0x8000) != 0)
2652 We devote a fair bit of code to getting efficient shifts since we
2653 can only shift one bit at a time on the H8/300 and H8/300H and only
2654 one or two bits at a time on the H8S.
2656 All shift code falls into one of the following ways of
2659 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2660 when a straight line shift is about the same size or smaller than
2663 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2664 off the bits we don't need. This is used when only a few of the
2665 bits in the original value will survive in the shifted value.
2667 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2668 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2669 shifts can be added if the shift count is slightly more than 8 or
2670 16. This case also includes other oddballs that are not worth
2673 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2675 For each shift count, we try to use code that has no trade-off
2676 between code size and speed whenever possible.
2678 If the trade-off is unavoidable, we try to be reasonable.
2679 Specifically, the fastest version is one instruction longer than
2680 the shortest version, we take the fastest version. We also provide
2681 the use a way to switch back to the shortest version with -Os.
2683 For the details of the shift algorithms for various shift counts,
2684 refer to shift_alg_[qhs]i. */
2687 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2689 switch (GET_CODE (x))
2701 /* Emit code to do shifts. */
2704 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2706 emit_move_insn (operands[0], operands[1]);
2708 /* Need a loop to get all the bits we want - we generate the
2709 code at emit time, but need to allocate a scratch reg now. */
2711 emit_insn (gen_rtx_PARALLEL
2714 gen_rtx_SET (VOIDmode, operands[0],
2715 gen_rtx (code, mode, operands[0],
2717 gen_rtx_CLOBBER (VOIDmode,
2718 gen_rtx_SCRATCH (QImode)))));
2721 /* Symbols of the various modes which can be used as indices. */
2725 QIshift, HIshift, SIshift
2728 /* For single bit shift insns, record assembler and what bits of the
2729 condition code are valid afterwards (represented as various CC_FOO
2730 bits, 0 means CC isn't left in a usable state). */
2734 const char *const assembler;
2738 /* Assembler instruction shift table.
2740 These tables are used to look up the basic shifts.
2741 They are indexed by cpu, shift_type, and mode. */
2743 static const struct shift_insn shift_one[2][3][3] =
2749 { "shll\t%X0", CC_SET_ZNV },
2750 { "add.w\t%T0,%T0", CC_SET_ZN },
2751 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2753 /* SHIFT_LSHIFTRT */
2755 { "shlr\t%X0", CC_SET_ZNV },
2756 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2757 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2759 /* SHIFT_ASHIFTRT */
2761 { "shar\t%X0", CC_SET_ZNV },
2762 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2763 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2770 { "shll.b\t%X0", CC_SET_ZNV },
2771 { "shll.w\t%T0", CC_SET_ZNV },
2772 { "shll.l\t%S0", CC_SET_ZNV }
2774 /* SHIFT_LSHIFTRT */
2776 { "shlr.b\t%X0", CC_SET_ZNV },
2777 { "shlr.w\t%T0", CC_SET_ZNV },
2778 { "shlr.l\t%S0", CC_SET_ZNV }
2780 /* SHIFT_ASHIFTRT */
2782 { "shar.b\t%X0", CC_SET_ZNV },
2783 { "shar.w\t%T0", CC_SET_ZNV },
2784 { "shar.l\t%S0", CC_SET_ZNV }
2789 static const struct shift_insn shift_two[3][3] =
2793 { "shll.b\t#2,%X0", CC_SET_ZNV },
2794 { "shll.w\t#2,%T0", CC_SET_ZNV },
2795 { "shll.l\t#2,%S0", CC_SET_ZNV }
2797 /* SHIFT_LSHIFTRT */
2799 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2800 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2801 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2803 /* SHIFT_ASHIFTRT */
2805 { "shar.b\t#2,%X0", CC_SET_ZNV },
2806 { "shar.w\t#2,%T0", CC_SET_ZNV },
2807 { "shar.l\t#2,%S0", CC_SET_ZNV }
2811 /* Rotates are organized by which shift they'll be used in implementing.
2812 There's no need to record whether the cc is valid afterwards because
2813 it is the AND insn that will decide this. */
2815 static const char *const rotate_one[2][3][3] =
2822 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2825 /* SHIFT_LSHIFTRT */
2828 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2831 /* SHIFT_ASHIFTRT */
2834 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2846 /* SHIFT_LSHIFTRT */
2852 /* SHIFT_ASHIFTRT */
2861 static const char *const rotate_two[3][3] =
2869 /* SHIFT_LSHIFTRT */
2875 /* SHIFT_ASHIFTRT */
2884 /* Shift algorithm. */
2887 /* The number of bits to be shifted by shift1 and shift2. Valid
2888 when ALG is SHIFT_SPECIAL. */
2889 unsigned int remainder;
2891 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2892 const char *special;
2894 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2895 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2898 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2899 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2902 /* CC status for SHIFT_INLINE. */
2905 /* CC status for SHIFT_SPECIAL. */
2909 static void get_shift_alg (enum shift_type,
2910 enum shift_mode, unsigned int,
2911 struct shift_info *);
2913 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2914 best algorithm for doing the shift. The assembler code is stored
2915 in the pointers in INFO. We achieve the maximum efficiency in most
2916 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2917 SImode in particular have a lot of room to optimize.
2919 We first determine the strategy of the shift algorithm by a table
2920 lookup. If that tells us to use a hand crafted assembly code, we
2921 go into the big switch statement to find what that is. Otherwise,
2922 we resort to a generic way, such as inlining. In either case, the
2923 result is returned through INFO. */
2926 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2927 unsigned int count, struct shift_info *info)
2931 /* Find the target CPU. */
2934 else if (TARGET_H8300H)
2939 /* Find the shift algorithm. */
2940 info->alg = SHIFT_LOOP;
2944 if (count < GET_MODE_BITSIZE (QImode))
2945 info->alg = shift_alg_qi[cpu][shift_type][count];
2949 if (count < GET_MODE_BITSIZE (HImode))
2950 info->alg = shift_alg_hi[cpu][shift_type][count];
2954 if (count < GET_MODE_BITSIZE (SImode))
2955 info->alg = shift_alg_si[cpu][shift_type][count];
2962 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2966 info->remainder = count;
2970 /* It is up to the caller to know that looping clobbers cc. */
2971 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2972 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2973 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2977 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2978 info->shift2 = rotate_two[shift_type][shift_mode];
2979 info->cc_inline = CC_CLOBBER;
2983 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2984 info->remainder = 0;
2985 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2986 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2987 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2988 info->cc_special = CC_CLOBBER;
2992 /* Here we only deal with SHIFT_SPECIAL. */
2996 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2997 through the entire value. */
2998 if (shift_type == SHIFT_ASHIFTRT && count == 7)
3000 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3012 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3014 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3016 case SHIFT_LSHIFTRT:
3018 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3020 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3022 case SHIFT_ASHIFTRT:
3023 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3027 else if ((8 <= count && count <= 13)
3028 || (TARGET_H8300S && count == 14))
3030 info->remainder = count - 8;
3035 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3037 case SHIFT_LSHIFTRT:
3040 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3041 info->shift1 = "shlr.b\t%s0";
3042 info->cc_inline = CC_SET_ZNV;
3046 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3047 info->cc_special = CC_SET_ZNV;
3050 case SHIFT_ASHIFTRT:
3053 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3054 info->shift1 = "shar.b\t%s0";
3058 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3059 info->cc_special = CC_SET_ZNV;
3064 else if (count == 14)
3070 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3072 case SHIFT_LSHIFTRT:
3074 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3076 case SHIFT_ASHIFTRT:
3078 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3079 else if (TARGET_H8300H)
3081 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3082 info->cc_special = CC_SET_ZNV;
3084 else /* TARGET_H8300S */
3089 else if (count == 15)
3094 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3096 case SHIFT_LSHIFTRT:
3097 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3099 case SHIFT_ASHIFTRT:
3100 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3107 if (TARGET_H8300 && 8 <= count && count <= 9)
3109 info->remainder = count - 8;
3114 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3116 case SHIFT_LSHIFTRT:
3117 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3118 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3120 case SHIFT_ASHIFTRT:
3121 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3125 else if (count == 8 && !TARGET_H8300)
3130 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3132 case SHIFT_LSHIFTRT:
3133 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3135 case SHIFT_ASHIFTRT:
3136 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3140 else if (count == 15 && TARGET_H8300)
3146 case SHIFT_LSHIFTRT:
3147 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3149 case SHIFT_ASHIFTRT:
3150 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3154 else if (count == 15 && !TARGET_H8300)
3159 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3160 info->cc_special = CC_SET_ZNV;
3162 case SHIFT_LSHIFTRT:
3163 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3164 info->cc_special = CC_SET_ZNV;
3166 case SHIFT_ASHIFTRT:
3170 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3171 || (TARGET_H8300H && 16 <= count && count <= 19)
3172 || (TARGET_H8300S && 16 <= count && count <= 21))
3174 info->remainder = count - 16;
3179 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3181 info->shift1 = "add.w\t%e0,%e0";
3183 case SHIFT_LSHIFTRT:
3186 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3187 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3191 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3192 info->cc_special = CC_SET_ZNV;
3195 case SHIFT_ASHIFTRT:
3198 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3199 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3203 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3204 info->cc_special = CC_SET_ZNV;
3209 else if (TARGET_H8300 && 24 <= count && count <= 28)
3211 info->remainder = count - 24;
3216 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3217 info->shift1 = "shll.b\t%z0";
3218 info->cc_inline = CC_SET_ZNV;
3220 case SHIFT_LSHIFTRT:
3221 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3222 info->shift1 = "shlr.b\t%w0";
3223 info->cc_inline = CC_SET_ZNV;
3225 case SHIFT_ASHIFTRT:
3226 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3227 info->shift1 = "shar.b\t%w0";
3228 info->cc_inline = CC_SET_ZNV;
3232 else if ((TARGET_H8300H && count == 24)
3233 || (TARGET_H8300S && 24 <= count && count <= 25))
3235 info->remainder = count - 24;
3240 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3242 case SHIFT_LSHIFTRT:
3243 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3244 info->cc_special = CC_SET_ZNV;
3246 case SHIFT_ASHIFTRT:
3247 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3248 info->cc_special = CC_SET_ZNV;
3252 else if (!TARGET_H8300 && count == 28)
3258 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3260 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3262 case SHIFT_LSHIFTRT:
3265 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3266 info->cc_special = CC_SET_ZNV;
3269 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3271 case SHIFT_ASHIFTRT:
3275 else if (!TARGET_H8300 && count == 29)
3281 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3283 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3285 case SHIFT_LSHIFTRT:
3288 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3289 info->cc_special = CC_SET_ZNV;
3293 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3294 info->cc_special = CC_SET_ZNV;
3297 case SHIFT_ASHIFTRT:
3301 else if (!TARGET_H8300 && count == 30)
3307 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3309 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3311 case SHIFT_LSHIFTRT:
3313 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3315 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3317 case SHIFT_ASHIFTRT:
3321 else if (count == 31)
3328 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3330 case SHIFT_LSHIFTRT:
3331 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3333 case SHIFT_ASHIFTRT:
3334 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3343 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3344 info->cc_special = CC_SET_ZNV;
3346 case SHIFT_LSHIFTRT:
3347 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3348 info->cc_special = CC_SET_ZNV;
3350 case SHIFT_ASHIFTRT:
3351 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3352 info->cc_special = CC_SET_ZNV;
3365 info->shift2 = NULL;
3368 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3369 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3372 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3377 if (GET_MODE_BITSIZE (mode) <= count)
3380 /* Find out the target CPU. */
3383 else if (TARGET_H8300H)
3388 /* Find the shift algorithm. */
3392 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3393 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3394 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3398 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3399 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3400 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3404 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3405 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3406 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3413 /* On H8/300H, count == 8 uses a scratch register. */
3414 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3415 || (TARGET_H8300H && mode == SImode && count == 8));
3418 /* Emit the assembler code for doing shifts. */
3421 output_a_shift (rtx *operands)
3423 static int loopend_lab;
3424 rtx shift = operands[3];
3425 enum machine_mode mode = GET_MODE (shift);
3426 enum rtx_code code = GET_CODE (shift);
3427 enum shift_type shift_type;
3428 enum shift_mode shift_mode;
3429 struct shift_info info;
3436 shift_mode = QIshift;
3439 shift_mode = HIshift;
3442 shift_mode = SIshift;
3451 shift_type = SHIFT_ASHIFTRT;
3454 shift_type = SHIFT_LSHIFTRT;
3457 shift_type = SHIFT_ASHIFT;
3463 if (GET_CODE (operands[2]) != CONST_INT)
3465 /* This case must be taken care of by one of the two splitters
3466 that convert a variable shift into a loop. */
3471 int n = INTVAL (operands[2]);
3473 /* If the count is negative, make it 0. */
3476 /* If the count is too big, truncate it.
3477 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3478 do the intuitive thing. */
3479 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3480 n = GET_MODE_BITSIZE (mode);
3482 get_shift_alg (shift_type, shift_mode, n, &info);
3487 output_asm_insn (info.special, operands);
3493 /* Emit two bit shifts first. */
3494 if (info.shift2 != NULL)
3496 for (; n > 1; n -= 2)
3497 output_asm_insn (info.shift2, operands);
3500 /* Now emit one bit shifts for any residual. */
3502 output_asm_insn (info.shift1, operands);
3507 int m = GET_MODE_BITSIZE (mode) - n;
3508 const int mask = (shift_type == SHIFT_ASHIFT
3509 ? ((1 << m) - 1) << n
3513 /* Not all possibilities of rotate are supported. They shouldn't
3514 be generated, but let's watch for 'em. */
3515 if (info.shift1 == 0)
3518 /* Emit two bit rotates first. */
3519 if (info.shift2 != NULL)
3521 for (; m > 1; m -= 2)
3522 output_asm_insn (info.shift2, operands);
3525 /* Now single bit rotates for any residual. */
3527 output_asm_insn (info.shift1, operands);
3529 /* Now mask off the high bits. */
3531 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3532 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3533 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3537 output_asm_insn (insn_buf, operands);
3542 /* A loop to shift by a "large" constant value.
3543 If we have shift-by-2 insns, use them. */
3544 if (info.shift2 != NULL)
3546 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3547 names_big[REGNO (operands[4])]);
3548 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3549 output_asm_insn (info.shift2, operands);
3550 output_asm_insn ("add #0xff,%X4", operands);
3551 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3553 output_asm_insn (info.shift1, operands);
3557 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3558 names_big[REGNO (operands[4])]);
3559 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3560 output_asm_insn (info.shift1, operands);
3561 output_asm_insn ("add #0xff,%X4", operands);
3562 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3573 h8300_asm_insn_count (const char *template)
3575 unsigned int count = 1;
3577 for (; *template; template++)
3578 if (*template == '\n')
3585 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3587 rtx shift = operands[3];
3588 enum machine_mode mode = GET_MODE (shift);
3589 enum rtx_code code = GET_CODE (shift);
3590 enum shift_type shift_type;
3591 enum shift_mode shift_mode;
3592 struct shift_info info;
3593 unsigned int wlength = 0;
3598 shift_mode = QIshift;
3601 shift_mode = HIshift;
3604 shift_mode = SIshift;
3613 shift_type = SHIFT_ASHIFTRT;
3616 shift_type = SHIFT_LSHIFTRT;
3619 shift_type = SHIFT_ASHIFT;
3625 if (GET_CODE (operands[2]) != CONST_INT)
3627 /* Get the assembler code to do one shift. */
3628 get_shift_alg (shift_type, shift_mode, 1, &info);
3630 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3634 int n = INTVAL (operands[2]);
3636 /* If the count is negative, make it 0. */
3639 /* If the count is too big, truncate it.
3640 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3641 do the intuitive thing. */
3642 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3643 n = GET_MODE_BITSIZE (mode);
3645 get_shift_alg (shift_type, shift_mode, n, &info);
3650 wlength += h8300_asm_insn_count (info.special);
3652 /* Every assembly instruction used in SHIFT_SPECIAL case
3653 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3654 see xor.l, we just pretend that xor.l counts as two insns
3655 so that the insn length will be computed correctly. */
3656 if (strstr (info.special, "xor.l") != NULL)
3664 if (info.shift2 != NULL)
3666 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3670 wlength += h8300_asm_insn_count (info.shift1) * n;
3676 int m = GET_MODE_BITSIZE (mode) - n;
3678 /* Not all possibilities of rotate are supported. They shouldn't
3679 be generated, but let's watch for 'em. */
3680 if (info.shift1 == 0)
3683 if (info.shift2 != NULL)
3685 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3689 wlength += h8300_asm_insn_count (info.shift1) * m;
3691 /* Now mask off the high bits. */
3712 /* A loop to shift by a "large" constant value.
3713 If we have shift-by-2 insns, use them. */
3714 if (info.shift2 != NULL)
3716 wlength += 3 + h8300_asm_insn_count (info.shift2);
3718 wlength += h8300_asm_insn_count (info.shift1);
3722 wlength += 3 + h8300_asm_insn_count (info.shift1);
3733 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3735 rtx shift = operands[3];
3736 enum machine_mode mode = GET_MODE (shift);
3737 enum rtx_code code = GET_CODE (shift);
3738 enum shift_type shift_type;
3739 enum shift_mode shift_mode;
3740 struct shift_info info;
3745 shift_mode = QIshift;
3748 shift_mode = HIshift;
3751 shift_mode = SIshift;
3760 shift_type = SHIFT_ASHIFTRT;
3763 shift_type = SHIFT_LSHIFTRT;
3766 shift_type = SHIFT_ASHIFT;
3772 if (GET_CODE (operands[2]) != CONST_INT)
3774 /* This case must be taken care of by one of the two splitters
3775 that convert a variable shift into a loop. */
3780 int n = INTVAL (operands[2]);
3782 /* If the count is negative, make it 0. */
3785 /* If the count is too big, truncate it.
3786 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3787 do the intuitive thing. */
3788 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3789 n = GET_MODE_BITSIZE (mode);
3791 get_shift_alg (shift_type, shift_mode, n, &info);
3796 if (info.remainder == 0)
3797 return info.cc_special;
3802 return info.cc_inline;
3805 /* This case always ends with an and instruction. */
3809 /* A loop to shift by a "large" constant value.
3810 If we have shift-by-2 insns, use them. */
3811 if (info.shift2 != NULL)
3814 return info.cc_inline;
3824 /* A rotation by a non-constant will cause a loop to be generated, in
3825 which a rotation by one bit is used. A rotation by a constant,
3826 including the one in the loop, will be taken care of by
3827 output_a_rotate () at the insn emit time. */
3830 expand_a_rotate (enum rtx_code code, rtx operands[])
3832 rtx dst = operands[0];
3833 rtx src = operands[1];
3834 rtx rotate_amount = operands[2];
3835 enum machine_mode mode = GET_MODE (dst);
3838 /* We rotate in place. */
3839 emit_move_insn (dst, src);
3841 if (GET_CODE (rotate_amount) != CONST_INT)
3843 rtx counter = gen_reg_rtx (QImode);
3844 rtx start_label = gen_label_rtx ();
3845 rtx end_label = gen_label_rtx ();
3847 /* If the rotate amount is less than or equal to 0,
3848 we go out of the loop. */
3849 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3850 QImode, 0, end_label);
3852 /* Initialize the loop counter. */
3853 emit_move_insn (counter, rotate_amount);
3855 emit_label (start_label);
3857 /* Rotate by one bit. */
3858 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3859 emit_insn (gen_rtx_SET (mode, dst, tmp));
3861 /* Decrement the counter by 1. */
3862 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3863 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3865 /* If the loop counter is nonzero, we go back to the beginning
3867 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3870 emit_label (end_label);
3874 /* Rotate by AMOUNT bits. */
3875 tmp = gen_rtx (code, mode, dst, rotate_amount);
3876 emit_insn (gen_rtx_SET (mode, dst, tmp));
3882 /* Output rotate insns. */
3885 output_a_rotate (enum rtx_code code, rtx *operands)
3887 rtx dst = operands[0];
3888 rtx rotate_amount = operands[2];
3889 enum shift_mode rotate_mode;
3890 enum shift_type rotate_type;
3891 const char *insn_buf;
3894 enum machine_mode mode = GET_MODE (dst);
3896 if (GET_CODE (rotate_amount) != CONST_INT)
3902 rotate_mode = QIshift;
3905 rotate_mode = HIshift;
3908 rotate_mode = SIshift;
3917 rotate_type = SHIFT_ASHIFT;
3920 rotate_type = SHIFT_LSHIFTRT;
3926 amount = INTVAL (rotate_amount);
3928 /* Clean up AMOUNT. */
3931 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3932 amount = GET_MODE_BITSIZE (mode);
3934 /* Determine the faster direction. After this phase, amount will be
3935 at most a half of GET_MODE_BITSIZE (mode). */
3936 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3938 /* Flip the direction. */
3939 amount = GET_MODE_BITSIZE (mode) - amount;
3941 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3944 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3945 boost up the rotation. */
3946 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3947 || (mode == HImode && TARGET_H8300H && amount >= 6)
3948 || (mode == HImode && TARGET_H8300S && amount == 8)
3949 || (mode == SImode && TARGET_H8300H && amount >= 10)
3950 || (mode == SImode && TARGET_H8300S && amount >= 13))
3955 /* This code works on any family. */
3956 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3957 output_asm_insn (insn_buf, operands);
3961 /* This code works on the H8/300H and H8S. */
3962 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3963 output_asm_insn (insn_buf, operands);
3970 /* Adjust AMOUNT and flip the direction. */
3971 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3973 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3976 /* Emit rotate insns. */
3977 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3980 insn_buf = rotate_two[rotate_type][rotate_mode];
3982 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3984 for (; amount >= bits; amount -= bits)
3985 output_asm_insn (insn_buf, operands);
3992 compute_a_rotate_length (rtx *operands)
3994 rtx src = operands[1];
3995 rtx amount_rtx = operands[2];
3996 enum machine_mode mode = GET_MODE (src);
3998 unsigned int length = 0;
4000 if (GET_CODE (amount_rtx) != CONST_INT)
4003 amount = INTVAL (amount_rtx);
4005 /* Clean up AMOUNT. */
4008 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4009 amount = GET_MODE_BITSIZE (mode);
4011 /* Determine the faster direction. After this phase, amount
4012 will be at most a half of GET_MODE_BITSIZE (mode). */
4013 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4014 /* Flip the direction. */
4015 amount = GET_MODE_BITSIZE (mode) - amount;
4017 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4018 boost up the rotation. */
4019 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4020 || (mode == HImode && TARGET_H8300H && amount >= 6)
4021 || (mode == HImode && TARGET_H8300S && amount == 8)
4022 || (mode == SImode && TARGET_H8300H && amount >= 10)
4023 || (mode == SImode && TARGET_H8300S && amount >= 13))
4025 /* Adjust AMOUNT and flip the direction. */
4026 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4030 /* We use 2-bit rotations on the H8S. */
4032 amount = amount / 2 + amount % 2;
4034 /* The H8/300 uses three insns to rotate one bit, taking 6
4036 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4041 /* Fix the operands of a gen_xxx so that it could become a bit
4045 fix_bit_operand (rtx *operands, int what, enum rtx_code type)
4047 /* The bit_operand predicate accepts any memory during RTL generation, but
4048 only 'U' memory afterwards, so if this is a MEM operand, we must force
4049 it to be valid for 'U' by reloading the address. */
4051 if ((what == 0 && single_zero_operand (operands[2], QImode))
4052 || (what == 1 && single_one_operand (operands[2], QImode)))
4054 /* OK to have a memory dest. */
4055 if (GET_CODE (operands[0]) == MEM
4056 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4058 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4059 copy_to_mode_reg (Pmode,
4060 XEXP (operands[0], 0)));
4061 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4065 if (GET_CODE (operands[1]) == MEM
4066 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4068 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4069 copy_to_mode_reg (Pmode,
4070 XEXP (operands[1], 0)));
4071 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4077 /* Dest and src op must be register. */
4079 operands[1] = force_reg (QImode, operands[1]);
4081 rtx res = gen_reg_rtx (QImode);
4082 emit_insn (gen_rtx_SET (VOIDmode, res,
4083 gen_rtx (type, QImode, operands[1], operands[2])));
4084 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
4089 /* Return nonzero if FUNC is an interrupt function as specified
4090 by the "interrupt" attribute. */
4093 h8300_interrupt_function_p (tree func)
4097 if (TREE_CODE (func) != FUNCTION_DECL)
4100 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4101 return a != NULL_TREE;
4104 /* Return nonzero if FUNC is an OS_Task function as specified
4105 by the "OS_Task" attribute. */
4108 h8300_os_task_function_p (tree func)
4112 if (TREE_CODE (func) != FUNCTION_DECL)
4115 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4116 return a != NULL_TREE;
4119 /* Return nonzero if FUNC is a monitor function as specified
4120 by the "monitor" attribute. */
4123 h8300_monitor_function_p (tree func)
4127 if (TREE_CODE (func) != FUNCTION_DECL)
4130 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4131 return a != NULL_TREE;
4134 /* Return nonzero if FUNC is a function that should be called
4135 through the function vector. */
4138 h8300_funcvec_function_p (tree func)
4142 if (TREE_CODE (func) != FUNCTION_DECL)
4145 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4146 return a != NULL_TREE;
4149 /* Return nonzero if DECL is a variable that's in the eight bit
4153 h8300_eightbit_data_p (tree decl)
4157 if (TREE_CODE (decl) != VAR_DECL)
4160 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4161 return a != NULL_TREE;
4164 /* Return nonzero if DECL is a variable that's in the tiny
4168 h8300_tiny_data_p (tree decl)
4172 if (TREE_CODE (decl) != VAR_DECL)
4175 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4176 return a != NULL_TREE;
4179 /* Generate an 'interrupt_handler' attribute for decls. */
4182 h8300_insert_attributes (tree node, tree *attributes)
4184 if (!pragma_interrupt
4185 || TREE_CODE (node) != FUNCTION_DECL)
4188 pragma_interrupt = 0;
4190 /* Add an 'interrupt_handler' attribute. */
4191 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4195 /* Supported attributes:
4197 interrupt_handler: output a prologue and epilogue suitable for an
4200 function_vector: This function should be called through the
4203 eightbit_data: This variable lives in the 8-bit data area and can
4204 be referenced with 8-bit absolute memory addresses.
4206 tiny_data: This variable lives in the tiny data area and can be
4207 referenced with 16-bit absolute memory references. */
4209 const struct attribute_spec h8300_attribute_table[] =
4211 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4212 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4213 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4214 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4215 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4216 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4217 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4218 { NULL, 0, 0, false, false, false, NULL }
4222 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4223 struct attribute_spec.handler. */
4225 h8300_handle_fndecl_attribute (tree *node, tree name,
4226 tree args ATTRIBUTE_UNUSED,
4227 int flags ATTRIBUTE_UNUSED,
4230 if (TREE_CODE (*node) != FUNCTION_DECL)
4232 warning ("`%s' attribute only applies to functions",
4233 IDENTIFIER_POINTER (name));
4234 *no_add_attrs = true;
4240 /* Handle an "eightbit_data" attribute; arguments as in
4241 struct attribute_spec.handler. */
4243 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4244 tree args ATTRIBUTE_UNUSED,
4245 int flags ATTRIBUTE_UNUSED,
4250 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4252 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4256 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4257 *no_add_attrs = true;
4263 /* Handle an "tiny_data" attribute; arguments as in
4264 struct attribute_spec.handler. */
4266 h8300_handle_tiny_data_attribute (tree *node, tree name,
4267 tree args ATTRIBUTE_UNUSED,
4268 int flags ATTRIBUTE_UNUSED,
4273 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4275 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4279 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4280 *no_add_attrs = true;
4286 /* Mark function vectors, and various small data objects. */
4289 h8300_encode_section_info (tree decl, rtx rtl, int first)
4291 int extra_flags = 0;
4293 default_encode_section_info (decl, rtl, first);
4295 if (TREE_CODE (decl) == FUNCTION_DECL
4296 && h8300_funcvec_function_p (decl))
4297 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4298 else if (TREE_CODE (decl) == VAR_DECL
4299 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4301 if (h8300_eightbit_data_p (decl))
4302 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4303 else if (first && h8300_tiny_data_p (decl))
4304 extra_flags = SYMBOL_FLAG_TINY_DATA;
4308 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4312 output_simode_bld (int bild, rtx operands[])
4316 /* Clear the destination register. */
4317 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4319 /* Now output the bit load or bit inverse load, and store it in
4322 output_asm_insn ("bild\t%Z2,%Y1", operands);
4324 output_asm_insn ("bld\t%Z2,%Y1", operands);
4326 output_asm_insn ("bst\t#0,%w0", operands);
4330 /* Determine if we can clear the destination first. */
4331 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4332 && REGNO (operands[0]) != REGNO (operands[1]));
4335 output_asm_insn ("sub.l\t%S0,%S0", operands);
4337 /* Output the bit load or bit inverse load. */
4339 output_asm_insn ("bild\t%Z2,%Y1", operands);
4341 output_asm_insn ("bld\t%Z2,%Y1", operands);
4344 output_asm_insn ("xor.l\t%S0,%S0", operands);
4346 /* Perform the bit store. */
4347 output_asm_insn ("rotxl.l\t%S0", operands);
4354 #ifndef OBJECT_FORMAT_ELF
4356 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4358 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4359 fprintf (asm_out_file, "\t.section %s\n", name);
4361 #endif /* ! OBJECT_FORMAT_ELF */
4363 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4364 which is a special case of the 'R' operand. */
4367 h8300_eightbit_constant_address_p (rtx x)
4369 /* The ranges of the 8-bit area. */
4370 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4371 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4372 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4373 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4374 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4375 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4377 unsigned HOST_WIDE_INT addr;
4379 /* We accept symbols declared with eightbit_data. */
4380 if (GET_CODE (x) == SYMBOL_REF)
4381 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4383 if (GET_CODE (x) != CONST_INT)
4389 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4390 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4391 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4394 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4395 on H8/300H and H8S. */
4398 h8300_tiny_constant_address_p (rtx x)
4400 /* The ranges of the 16-bit area. */
4401 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4402 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4403 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4404 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4405 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4406 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4407 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4408 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4410 unsigned HOST_WIDE_INT addr;
4412 /* We accept symbols declared with tiny_data. */
4413 if (GET_CODE (x) == SYMBOL_REF)
4414 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
4416 if (GET_CODE (x) != CONST_INT)
4422 || TARGET_NORMAL_MODE
4424 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4426 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4430 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4432 HOST_WIDE_INT offset1, offset2;
4440 else if (GET_CODE (addr1) == PLUS
4441 && REG_P (XEXP (addr1, 0))
4442 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4444 reg1 = XEXP (addr1, 0);
4445 offset1 = INTVAL (XEXP (addr1, 1));
4455 else if (GET_CODE (addr2) == PLUS
4456 && REG_P (XEXP (addr2, 0))
4457 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4459 reg2 = XEXP (addr2, 0);
4460 offset2 = INTVAL (XEXP (addr2, 1));
4465 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4466 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4468 && offset1 + 1 == offset2)
4474 /* Return nonzero if we have the same comparison insn as I3 two insns
4475 before I3. I3 is assumed to be a comparison insn. */
4478 same_cmp_preceding_p (rtx i3)
4482 /* Make sure we have a sequence of three insns. */
4483 i2 = prev_nonnote_insn (i3);
4486 i1 = prev_nonnote_insn (i2);
4490 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4491 && any_condjump_p (i2) && onlyjump_p (i2));
4494 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4497 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4498 unsigned int new_reg)
4500 /* Interrupt functions can only use registers that have already been
4501 saved by the prologue, even if they would normally be
4504 if (h8300_current_function_interrupt_function_p ()
4505 && !regs_ever_live[new_reg])
4511 /* Perform target dependent optabs initialization. */
4513 h8300_init_libfuncs (void)
4515 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4516 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4517 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4518 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4519 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4522 /* Initialize the GCC target structure. */
4523 #undef TARGET_ATTRIBUTE_TABLE
4524 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4526 #undef TARGET_ASM_ALIGNED_HI_OP
4527 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4529 #undef TARGET_ASM_FUNCTION_EPILOGUE
4530 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
4532 #undef TARGET_ASM_FILE_START
4533 #define TARGET_ASM_FILE_START h8300_file_start
4534 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4535 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4537 #undef TARGET_ASM_FILE_END
4538 #define TARGET_ASM_FILE_END h8300_file_end
4540 #undef TARGET_ENCODE_SECTION_INFO
4541 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4543 #undef TARGET_INSERT_ATTRIBUTES
4544 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4546 #undef TARGET_RTX_COSTS
4547 #define TARGET_RTX_COSTS h8300_rtx_costs
4549 #undef TARGET_INIT_LIBFUNCS
4550 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4552 struct gcc_target targetm = TARGET_INITIALIZER;