1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
44 /* Forward declarations. */
45 static int h8300_interrupt_function_p PARAMS ((tree));
46 static int h8300_monitor_function_p PARAMS ((tree));
47 static int h8300_os_task_function_p PARAMS ((tree));
48 static void dosize PARAMS ((FILE *, const char *, unsigned int));
49 static const char *cond_string PARAMS ((enum rtx_code));
51 /* CPU_TYPE, says what cpu we're compiling for. */
54 /* True if the current function is an interrupt handler
55 (either via #pragma or an attribute specification). */
56 int interrupt_handler;
58 /* True if the current function is an OS Task
59 (via an attribute specification). */
62 /* True if the current function is a monitor
63 (via an attribute specification). */
66 /* True if a #pragma saveall has been seen for the current function. */
69 static const char *const names_big[] =
70 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
72 static const char *const names_extended[] =
73 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
75 static const char *const names_upper_extended[] =
76 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
78 /* Points to one of the above. */
79 /* ??? The above could be put in an array indexed by CPU_TYPE. */
80 const char * const *h8_reg_names;
82 /* Various operations needed by the following, indexed by CPU_TYPE. */
84 static const char *const h8_push_ops[2] = { "push", "push.l" };
85 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
86 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
88 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
90 /* Initialize various cpu specific globals at start up. */
97 cpu_type = (int) CPU_H8300;
98 h8_reg_names = names_big;
102 /* For this we treat the H8/300 and H8/S the same. */
103 cpu_type = (int) CPU_H8300H;
104 h8_reg_names = names_extended;
106 h8_push_op = h8_push_ops[cpu_type];
107 h8_pop_op = h8_pop_ops[cpu_type];
108 h8_mov_op = h8_mov_ops[cpu_type];
116 static const char *const names_small[] =
117 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
118 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
120 return names_small[REGNO (x) * 2 + b];
123 /* REGNO must be saved/restored across calls if this macro is true. */
125 #define WORD_REG_USED(regno) \
127 /* No need to save registers if this function will not return. */\
128 && ! TREE_THIS_VOLATILE (current_function_decl) \
130 /* Save any call saved register that was used. */ \
131 || (regs_ever_live[regno] && !call_used_regs[regno]) \
132 /* Save the frame pointer if it was used. */ \
133 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
134 /* Save any register used in an interrupt handler. */ \
135 || (interrupt_handler && regs_ever_live[regno]) \
136 /* Save call clobbered registers in non-leaf interrupt \
138 || (interrupt_handler \
139 && call_used_regs[regno] \
140 && !current_function_is_leaf)))
142 /* Output assembly language to FILE for the operation OP with operand size
143 SIZE to adjust the stack pointer. */
146 dosize (file, op, size)
151 /* On the h8300h and h8300s, for sizes <= 8 bytes it is as good or
152 better to use adds/subs insns rather than add.l/sub.l
153 with an immediate value. */
154 if (size > 4 && size <= 8 && (TARGET_H8300H || TARGET_H8300S))
156 /* Crank the size down to <= 4. */
157 fprintf (file, "\t%ss\t#%d,sp\n", op, 4);
164 if (TARGET_H8300H || TARGET_H8300S)
166 fprintf (file, "\t%ss\t#%d,sp\n", op, 4);
171 fprintf (file, "\t%ss\t#%d,sp\n", op, 2);
173 /* Fall through... */
176 fprintf (file, "\t%ss\t#%d,sp\n", op, size);
184 if (current_function_needs_context
185 && strcmp (op, "sub") == 0)
187 /* Egad. We don't have a temporary to hold the
188 size of the frame in the prologue! Just inline
189 the bastard since this shouldn't happen often. */
192 fprintf (file, "\tsubs\t#2,sp\n");
197 fprintf (file, "\tsubs\t#1,sp\n");
202 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
205 fprintf (file, "\t%s\t#%d,sp\n", op, size);
211 /* Output assembly language code for the function prologue. */
212 static int push_order[FIRST_PSEUDO_REGISTER] =
213 { 0, 1, 2, 3, 4, 5, 6, -1, -1, -1 };
214 static int pop_order[FIRST_PSEUDO_REGISTER] =
215 { 6, 5, 4, 3, 2, 1, 0, -1, -1, -1 };
217 /* This is what the stack looks like after the prolog of
218 a function with a frame has been set up:
224 <saved registers> <- sp
226 This is what the stack looks like after the prolog of
227 a function which doesn't have a frame:
232 <saved registers> <- sp
236 function_prologue (file, size)
240 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
243 /* Note a function with the interrupt attribute and set interrupt_handler
245 if (h8300_interrupt_function_p (current_function_decl))
246 interrupt_handler = 1;
248 /* If the current function has the OS_Task attribute set, then
249 we have a naked prologue. */
250 if (h8300_os_task_function_p (current_function_decl))
252 fprintf (file, ";OS_Task prologue\n");
257 if (h8300_monitor_function_p (current_function_decl))
259 /* My understanding of monitor functions is they act just
260 like interrupt functions, except the prologue must
262 fprintf (file, ";monitor prologue\n");
263 interrupt_handler = 1;
267 fprintf (file, "\tsubs\t#2,sp\n");
268 fprintf (file, "\tpush\tr0\n");
269 fprintf (file, "\tstc\tccr,r0l\n");
270 fprintf (file, "\torc\t#128,ccr\n");
271 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
275 fprintf (file, "\tpush\ter0\n");
276 fprintf (file, "\tstc\tccr,r0l\n");
277 fprintf (file, "\torc\t#128,ccr\n");
278 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
282 if (frame_pointer_needed)
285 fprintf (file, "\t%s\t%s\n", h8_push_op,
286 h8_reg_names[FRAME_POINTER_REGNUM]);
287 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
288 h8_reg_names[STACK_POINTER_REGNUM],
289 h8_reg_names[FRAME_POINTER_REGNUM]);
292 /* Leave room for locals. */
293 dosize (file, "sub", fsize);
295 /* Push the rest of the registers. */
296 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
298 int regno = push_order[idx];
301 && WORD_REG_USED (regno)
302 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
306 /* Try to push multiple registers. */
307 if (regno == 0 || regno == 4)
309 int second_regno = push_order[idx + 1];
310 int third_regno = push_order[idx + 2];
311 int fourth_regno = push_order[idx + 3];
313 if (fourth_regno >= 0
314 && WORD_REG_USED (fourth_regno)
315 && (!frame_pointer_needed
316 || fourth_regno != FRAME_POINTER_REGNUM)
318 && WORD_REG_USED (third_regno)
319 && (!frame_pointer_needed
320 || third_regno != FRAME_POINTER_REGNUM)
322 && WORD_REG_USED (second_regno)
323 && (!frame_pointer_needed
324 || second_regno != FRAME_POINTER_REGNUM))
326 fprintf (file, "\tstm.l %s-%s,@-sp\n",
328 h8_reg_names[fourth_regno]);
333 if (regno == 0 || regno == 4)
335 int second_regno = push_order[idx + 1];
336 int third_regno = push_order[idx + 2];
339 && WORD_REG_USED (third_regno)
340 && (!frame_pointer_needed
341 || third_regno != FRAME_POINTER_REGNUM)
343 && WORD_REG_USED (second_regno)
344 && (!frame_pointer_needed
345 || second_regno != FRAME_POINTER_REGNUM))
347 fprintf (file, "\tstm.l %s-%s,@-sp\n",
349 h8_reg_names[third_regno]);
354 if (regno == 0 || regno == 2 || regno == 4 || regno == 6)
356 int second_regno = push_order[idx + 1];
358 if (second_regno >= 0
359 && WORD_REG_USED (second_regno)
360 && (!frame_pointer_needed
361 || second_regno != FRAME_POINTER_REGNUM))
363 fprintf (file, "\tstm.l %s-%s,@-sp\n",
365 h8_reg_names[second_regno]);
371 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]);
376 /* Output assembly language code for the function epilogue. */
379 function_epilogue (file, size)
383 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
385 rtx insn = get_last_insn ();
389 /* OS_Task epilogues are nearly naked -- they just have an
391 fprintf (file, ";OS_task epilogue\n");
392 fprintf (file, "\trts\n");
396 /* Monitor epilogues are the same as interrupt function epilogues.
397 Just make a note that we're in an monitor epilogue. */
399 fprintf (file, ";monitor epilogue\n");
401 /* If the last insn was a BARRIER, we don't have to write any code. */
402 if (GET_CODE (insn) == NOTE)
403 insn = prev_nonnote_insn (insn);
404 if (insn && GET_CODE (insn) == BARRIER)
407 /* Pop the saved registers. */
408 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
410 int regno = pop_order[idx];
413 && WORD_REG_USED (regno)
414 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
418 /* Try to pop multiple registers. */
419 if (regno == 7 || regno == 3)
421 int second_regno = pop_order[idx + 1];
422 int third_regno = pop_order[idx + 2];
423 int fourth_regno = pop_order[idx + 3];
425 if (fourth_regno >= 0
426 && WORD_REG_USED (fourth_regno)
427 && (!frame_pointer_needed
428 || fourth_regno != FRAME_POINTER_REGNUM)
430 && WORD_REG_USED (third_regno)
431 && (!frame_pointer_needed
432 || third_regno != FRAME_POINTER_REGNUM)
434 && WORD_REG_USED (second_regno)
435 && (!frame_pointer_needed
436 || second_regno != FRAME_POINTER_REGNUM))
438 fprintf (file, "\tldm.l @sp+,%s-%s\n",
439 h8_reg_names[fourth_regno],
440 h8_reg_names[regno]);
445 if (regno == 6 || regno == 2)
447 int second_regno = pop_order[idx + 1];
448 int third_regno = pop_order[idx + 2];
451 && WORD_REG_USED (third_regno)
452 && (!frame_pointer_needed
453 || third_regno != FRAME_POINTER_REGNUM)
455 && WORD_REG_USED (second_regno)
456 && (!frame_pointer_needed
457 || second_regno != FRAME_POINTER_REGNUM))
459 fprintf (file, "\tldm.l @sp+,%s-%s\n",
460 h8_reg_names[third_regno],
461 h8_reg_names[regno]);
466 if (regno == 7 || regno == 5 || regno == 3 || regno == 1)
468 int second_regno = pop_order[idx + 1];
470 if (second_regno >= 0
471 && WORD_REG_USED (second_regno)
472 && (!frame_pointer_needed
473 || second_regno != FRAME_POINTER_REGNUM))
475 fprintf (file, "\tldm.l @sp+,%s-%s\n",
476 h8_reg_names[second_regno],
477 h8_reg_names[regno]);
483 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]);
487 /* Deallocate locals. */
488 dosize (file, "add", fsize);
490 /* Pop frame pointer if we had one. */
491 if (frame_pointer_needed)
492 fprintf (file, "\t%s\t%s\n",
493 h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]);
495 /* If this is a monitor function, there is one register still left on
498 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[0]);
500 if (interrupt_handler)
501 fprintf (file, "\trte\n");
503 fprintf (file, "\trts\n");
506 interrupt_handler = 0;
512 /* Output assembly code for the start of the file. */
515 asm_file_start (file)
518 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
519 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
520 fprintf (file, ";\trelease F-1\n");
522 fprintf (file, "; -O%d\n", optimize);
524 fprintf (file, "\n\t.h8300h\n");
525 else if (TARGET_H8300S)
526 fprintf (file, "\n\t.h8300s\n");
528 fprintf (file, "\n\n");
529 output_file_directive (file, main_input_filename);
532 /* Output assembly language code for the end of file. */
538 fprintf (file, "\t.end\n");
541 /* Return true if VALUE is a valid constant for constraint 'P'.
542 IE: VALUE is a power of two <= 2**15. */
545 small_power_of_two (value)
548 int power = exact_log2 (value);
549 return power >= 0 && power <= 15;
552 /* Return true if VALUE is a valid constant for constraint 'O', which
553 means that the constant would be ok to use as a bit for a bclr
560 return small_power_of_two ((~value) & 0xff);
563 /* Return true is OP is a valid source operand for an integer move
567 general_operand_src (op, mode)
569 enum machine_mode mode;
571 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
573 return general_operand (op, mode);
576 /* Return true if OP is a valid destination operand for an integer move
580 general_operand_dst (op, mode)
582 enum machine_mode mode;
584 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
586 return general_operand (op, mode);
589 /* Return true if OP is a const valid for a bit clear instruction. */
592 o_operand (operand, mode)
594 enum machine_mode mode ATTRIBUTE_UNUSED;
596 return (GET_CODE (operand) == CONST_INT
597 && CONST_OK_FOR_O (INTVAL (operand)));
600 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
603 p_operand (operand, mode)
605 enum machine_mode mode ATTRIBUTE_UNUSED;
607 return (GET_CODE (operand) == CONST_INT
608 && CONST_OK_FOR_P (INTVAL (operand)));
611 /* Return true if OP is a valid call operand. */
614 call_insn_operand (op, mode)
616 enum machine_mode mode ATTRIBUTE_UNUSED;
618 if (GET_CODE (op) == MEM)
620 rtx inside = XEXP (op, 0);
621 if (register_operand (inside, Pmode))
623 if (CONSTANT_ADDRESS_P (inside))
629 /* Return 1 if an addition/subtraction of a constant integer can be
630 transformed into two consecutive adds/subs that are faster than the
631 straightforward way. Otherwise, return 0. */
634 two_insn_adds_subs_operand (op, mode)
636 enum machine_mode mode;
638 if (GET_CODE (op) == CONST_INT)
640 HOST_WIDE_INT value = INTVAL (op);
642 /* Force VALUE to be positive so that we do not have to consider
643 the negative case. */
646 if (TARGET_H8300H || TARGET_H8300S)
648 /* A constant addition/subtraction takes 2 states in QImode,
649 4 states in HImode, and 6 states in SImode. Thus, the
650 only case we can win is when SImode is used, in which
651 case, two adds/subs are used, taking 4 states. */
661 /* A constant addition/subtraction takes 2 states in
662 QImode. It takes 6 states in HImode, requiring the
663 constant to be loaded to a register first, and a lot more
664 in SImode. Thus the only case we can win is when either
665 HImode or SImode is used. */
676 /* Split an add of a small constant into two adds/subs insns. */
679 split_adds_subs (mode, operands)
680 enum machine_mode mode;
683 HOST_WIDE_INT val = INTVAL (operands[1]);
684 rtx reg = operands[0];
687 /* Take care of +/- 4 for H8300H and H8300S. */
688 if (TARGET_H8300H || TARGET_H8300S)
690 /* Get the value in range of +/- 4. */
693 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (4));
694 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
699 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (-4));
700 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
704 if (val == 4 || val == -4)
706 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (val));
707 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
712 /* Get the value in range of +/- 2. */
715 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (2));
716 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
721 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (-2));
722 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
726 /* If not optimizing, we might be asked to add 0. */
730 /* We should have one or two now. */
731 if (val >= -2 && val <= 2)
733 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (val));
734 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
738 /* In theory, this can't happen. */
742 /* Return true if OP is a valid call operand, and OP represents
743 an operand for a small call (4 bytes instead of 6 bytes). */
746 small_call_insn_operand (op, mode)
748 enum machine_mode mode ATTRIBUTE_UNUSED;
750 if (GET_CODE (op) == MEM)
752 rtx inside = XEXP (op, 0);
754 /* Register indirect is a small call. */
755 if (register_operand (inside, Pmode))
758 /* A call through the function vector is a small
760 if (GET_CODE (inside) == SYMBOL_REF
761 && SYMBOL_REF_FLAG (inside))
764 /* Otherwise it's a large call. */
768 /* Return true if OP is a valid jump operand. */
771 jump_address_operand (op, mode)
773 enum machine_mode mode;
775 if (GET_CODE (op) == REG)
776 return mode == Pmode;
778 if (GET_CODE (op) == MEM)
780 rtx inside = XEXP (op, 0);
781 if (register_operand (inside, Pmode))
783 if (CONSTANT_ADDRESS_P (inside))
789 /* Recognize valid operands for bitfield instructions. */
791 extern int rtx_equal_function_value_matters;
794 bit_operand (op, mode)
796 enum machine_mode mode;
798 /* We can except any general operand, expept that MEM operands must
799 be limited to those that use addresses valid for the 'U' constraint. */
800 if (!general_operand (op, mode))
803 /* Accept any mem during RTL generation. Otherwise, the code that does
804 insv and extzv will think that we can not handle memory. However,
805 to avoid reload problems, we only accept 'U' MEM operands after RTL
806 generation. This means that any named pattern which uses this predicate
807 must force its operands to match 'U' before emitting RTL. */
809 if (GET_CODE (op) == REG)
811 if (GET_CODE (op) == SUBREG)
813 if (!rtx_equal_function_value_matters)
814 /* We're building rtl. */
815 return GET_CODE (op) == MEM;
817 return (GET_CODE (op) == MEM
818 && EXTRA_CONSTRAINT (op, 'U'));
822 bit_memory_operand (op, mode)
824 enum machine_mode mode ATTRIBUTE_UNUSED;
826 return (GET_CODE (op) == MEM
827 && EXTRA_CONSTRAINT (op, 'U'));
830 /* Recognize valid operators for bit test. */
833 eq_operator (x, mode)
835 enum machine_mode mode ATTRIBUTE_UNUSED;
837 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
840 /* Handle machine specific pragmas for compatibility with existing
841 compilers for the H8/300.
843 pragma saveall generates prolog/epilog code which saves and
844 restores all the registers on function entry.
846 pragma interrupt saves and restores all registers, and exits with
847 an rte instruction rather than an rts. A pointer to a function
848 with this attribute may be safely used in an interrupt vector. */
851 handle_pragma (p_getc, p_ungetc, pname)
852 int (* ATTRIBUTE_UNUSED p_getc) PARAMS ((void));
853 void (* ATTRIBUTE_UNUSED p_ungetc) PARAMS ((int));
858 if (strcmp (pname, "interrupt") == 0)
859 interrupt_handler = retval = 1;
860 else if (strcmp (pname, "saveall") == 0)
861 pragma_saveall = retval = 1;
866 /* If the next arg with MODE and TYPE is to be passed in a register, return
867 the rtx to represent where it is passed. CUM represents the state after
868 the last argument. NAMED is not used. */
870 static const char *const hand_list[] =
890 /* Return an RTX to represent where a value with mode MODE will be returned
891 from a function. If the result is 0, the argument is pushed. */
894 function_arg (cum, mode, type, named)
895 CUMULATIVE_ARGS *cum;
896 enum machine_mode mode;
904 /* Never pass unnamed arguments in registers. */
908 /* Pass 3 regs worth of data in regs when user asked on the command line. */
909 if (TARGET_QUICKCALL)
912 /* If calling hand written assembler, use 4 regs of args. */
916 const char * const *p;
918 fname = XSTR (cum->libcall, 0);
920 /* See if this libcall is one of the hand coded ones. */
922 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
934 size = int_size_in_bytes (type);
936 size = GET_MODE_SIZE (mode);
938 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
944 switch (cum->nbytes / UNITS_PER_WORD)
947 result = gen_rtx_REG (mode, 0);
950 result = gen_rtx_REG (mode, 1);
953 result = gen_rtx_REG (mode, 2);
956 result = gen_rtx_REG (mode, 3);
967 /* Return the cost of the rtx R with code CODE. */
987 if (TARGET_H8300H || TARGET_H8300S)
1008 /* Documentation for the machine specific operand escapes:
1010 'A' print rn in h8/300 mode, erN in H8/300H mode
1011 'C' print (operand - 2).
1012 'E' like s but negative.
1013 'F' like t but negative.
1014 'G' constant just the negative
1015 'M' turn a 'M' constant into its negative mod 2.
1016 'P' if operand is incing/decing sp, print .w, otherwise .b.
1017 'R' print operand as a byte:8 address if appropriate, else fall back to
1019 'S' print operand as a long word
1020 'T' print operand as a word
1021 'U' if operand is incing/decing sp, print l, otherwise nothing.
1022 'V' find the set bit, and print its number.
1023 'W' find the clear bit, and print its number.
1024 'X' print operand as a byte
1025 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1026 If this operand isn't a register, fall back to 'R' handling.
1028 'b' print the bit opcode
1029 'c' print the ibit opcode
1030 'd' bcc if EQ, bcs if NE
1031 'e' first word of 32 bit value - if reg, then least reg. if mem
1032 then least. if const then most sig word
1033 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1034 then +2. if const then least sig word
1035 'g' bcs if EQ, bcc if NE
1036 'j' print operand as condition code.
1037 'k' print operand as reverse condition code.
1038 's' print as low byte of 16 bit value
1039 't' print as high byte of 16 bit value
1040 'w' print as low byte of 32 bit value
1041 'x' print as 2nd byte of 32 bit value
1042 'y' print as 3rd byte of 32 bit value
1043 'z' print as msb of 32 bit value
1046 /* Return assembly language string which identifies a comparison type. */
1079 /* Print operand X using operand code CODE to assembly language output file
1083 print_operand (file, x, code)
1088 /* This is used for communication between the 'P' and 'U' codes. */
1089 static const char *last_p;
1091 /* This is used for communication between codes V,W,Z and Y. */
1097 if (GET_CODE (x) == REG)
1098 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1103 fprintf (file, "#%d", INTVAL (x) - 2);
1106 switch (GET_CODE (x))
1109 fprintf (file, "%sl", names_big[REGNO (x)]);
1112 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1119 switch (GET_CODE (x))
1122 fprintf (file, "%sh", names_big[REGNO (x)]);
1125 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1132 if (GET_CODE (x) != CONST_INT)
1134 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1137 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1144 fprintf (file, "#2");
1150 fprintf (file, "#1");
1157 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1160 fprintf (file, ".w");
1165 fprintf (file, ".b");
1169 if (GET_CODE (x) == REG)
1170 fprintf (file, "%s", names_extended[REGNO (x)]);
1175 if (GET_CODE (x) == REG)
1176 fprintf (file, "%s", names_big[REGNO (x)]);
1181 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1184 bitint = exact_log2 (INTVAL (x));
1187 fprintf (file, "#%d", bitint & 7);
1190 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1193 fprintf (file, "#%d", bitint & 7);
1197 if (GET_CODE (x) == REG)
1198 fprintf (file, "%s", byte_reg (x, 0));
1205 if (GET_CODE (x) == REG)
1206 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1208 print_operand (file, x, 'R');
1212 bitint = INTVAL (x);
1213 fprintf (file, "#%d", bitint & 7);
1216 switch (GET_CODE (x))
1219 fprintf (file, "bor");
1222 fprintf (file, "bxor");
1225 fprintf (file, "band");
1232 switch (GET_CODE (x))
1235 fprintf (file, "bior");
1238 fprintf (file, "bixor");
1241 fprintf (file, "biand");
1248 switch (GET_CODE (x))
1251 fprintf (file, "bcc");
1254 fprintf (file, "bcs");
1261 switch (GET_CODE (x))
1265 fprintf (file, "%s", names_big[REGNO (x)]);
1267 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1270 x = adj_offsettable_operand (x, 0);
1271 print_operand (file, x, 0);
1274 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1280 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1281 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1282 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1291 switch (GET_CODE (x))
1295 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1297 fprintf (file, "%s", names_big[REGNO (x)]);
1300 x = adj_offsettable_operand (x, 2);
1301 print_operand (file, x, 0);
1304 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1310 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1311 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1312 fprintf (file, "#%ld", (val & 0xffff));
1320 switch (GET_CODE (x))
1323 fprintf (file, "bcc");
1326 fprintf (file, "bcs");
1333 asm_fprintf (file, cond_string (GET_CODE (x)));
1336 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1339 if (GET_CODE (x) == CONST_INT)
1340 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1342 fprintf (file, "%s", byte_reg (x, 0));
1345 if (GET_CODE (x) == CONST_INT)
1346 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1348 fprintf (file, "%s", byte_reg (x, 1));
1351 if (GET_CODE (x) != CONST_INT)
1353 fprintf (file, "%d", INTVAL (x));
1356 if (GET_CODE (x) == CONST_INT)
1357 fprintf (file, "#%d", INTVAL (x) & 0xff);
1359 fprintf (file, "%s",
1360 byte_reg (x, TARGET_H8300 ? 2 : 0));
1363 if (GET_CODE (x) == CONST_INT)
1364 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1366 fprintf (file, "%s",
1367 byte_reg (x, TARGET_H8300 ? 3 : 1));
1370 if (GET_CODE (x) == CONST_INT)
1371 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1373 fprintf (file, "%s", byte_reg (x, 0));
1376 if (GET_CODE (x) == CONST_INT)
1377 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1379 fprintf (file, "%s", byte_reg (x, 1));
1384 switch (GET_CODE (x))
1387 switch (GET_MODE (x))
1390 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1391 fprintf (file, "%s", byte_reg (x, 0));
1392 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1393 fprintf (file, "%s", names_big[REGNO (x)]);
1397 fprintf (file, "%s", names_big[REGNO (x)]);
1401 fprintf (file, "%s", names_extended[REGNO (x)]);
1409 fprintf (file, "@");
1410 output_address (XEXP (x, 0));
1412 /* If this is an 'R' operand (reference into the 8-bit
1413 area), then specify a symbolic address as "foo:8",
1414 otherwise if operand is still in eight bit section, use
1416 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1417 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1418 fprintf (file, (code == 'R' ? ":8" : ":16"));
1419 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1420 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1421 fprintf (file, ":16");
1428 fprintf (file, "#");
1429 print_operand_address (file, x);
1435 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1436 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1437 fprintf (file, "#%ld", val);
1446 /* Output assembly language output for the address ADDR to FILE. */
1449 print_operand_address (file, addr)
1453 switch (GET_CODE (addr))
1456 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1460 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1464 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1468 fprintf (file, "(");
1469 if (GET_CODE (XEXP (addr, 0)) == REG)
1472 print_operand_address (file, XEXP (addr, 1));
1473 fprintf (file, ",");
1474 print_operand_address (file, XEXP (addr, 0));
1479 print_operand_address (file, XEXP (addr, 0));
1480 fprintf (file, "+");
1481 print_operand_address (file, XEXP (addr, 1));
1483 fprintf (file, ")");
1488 /* Since the h8/300 only has 16 bit pointers, negative values are also
1489 those >= 32768. This happens for example with pointer minus a
1490 constant. We don't want to turn (char *p - 2) into
1491 (char *p + 65534) because loop unrolling can build upon this
1492 (IE: char *p + 131068). */
1493 int n = INTVAL (addr);
1495 n = (int) (short) n;
1497 /* ??? Why the special case for -ve values? */
1498 fprintf (file, "-%d", -n);
1500 fprintf (file, "%d", n);
1505 output_addr_const (file, addr);
1510 /* Output all insn addresses and their sizes into the assembly language
1511 output file. This is helpful for debugging whether the length attributes
1512 in the md file are correct. This is not meant to be a user selectable
1516 final_prescan_insn (insn, operand, num_operands)
1517 rtx insn, *operand ATTRIBUTE_UNUSED;
1518 int num_operands ATTRIBUTE_UNUSED;
1520 /* This holds the last insn address. */
1521 static int last_insn_address = 0;
1523 int uid = INSN_UID (insn);
1525 if (TARGET_RTL_DUMP)
1527 fprintf (asm_out_file, "\n****************");
1528 print_rtl (asm_out_file, PATTERN (insn));
1529 fprintf (asm_out_file, "\n");
1532 if (TARGET_ADDRESSES)
1534 fprintf (asm_out_file, "; 0x%x %d\n", insn_addresses[uid],
1535 insn_addresses[uid] - last_insn_address);
1536 last_insn_address = insn_addresses[uid];
1540 /* Prepare for an SI sized move. */
1546 rtx src = operands[1];
1547 rtx dst = operands[0];
1548 if (!reload_in_progress && !reload_completed)
1550 if (!register_operand (dst, GET_MODE (dst)))
1552 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1553 emit_move_insn (tmp, src);
1560 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1561 Define the offset between two registers, one to be eliminated, and
1562 the other its replacement, at the start of a routine. */
1565 initial_offset (from, to)
1570 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1571 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1576 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1577 if (WORD_REG_USED (regno))
1578 offset += UNITS_PER_WORD;
1580 /* See the comments for get_frame_size. We need to round it up to
1583 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1584 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1586 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1587 offset += UNITS_PER_WORD; /* Skip saved PC */
1592 /* Update the condition code from the insn. */
1595 notice_update_cc (body, insn)
1599 switch (get_attr_cc (insn))
1602 /* Insn does not affect CC at all. */
1606 /* Insn does not change CC, but the 0'th operand has been changed. */
1607 if (cc_status.value1 != 0
1608 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1609 cc_status.value1 = 0;
1613 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1614 The V flag is unusable. The C flag may or may not be known but
1615 that's ok because alter_cond will change tests to use EQ/NE. */
1617 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1618 cc_status.value1 = recog_data.operand[0];
1622 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1623 The C flag may or may not be known but that's ok because
1624 alter_cond will change tests to use EQ/NE. */
1626 cc_status.flags |= CC_NO_CARRY;
1627 cc_status.value1 = recog_data.operand[0];
1631 /* The insn is a compare instruction. */
1633 cc_status.value1 = SET_SRC (body);
1637 /* Insn doesn't leave CC in a usable state. */
1643 /* Recognize valid operators for bit instructions. */
1646 bit_operator (x, mode)
1648 enum machine_mode mode ATTRIBUTE_UNUSED;
1650 enum rtx_code code = GET_CODE (x);
1659 We devote a fair bit of code to getting efficient shifts since we can only
1660 shift one bit at a time on the H8/300 and H8/300H and only one or two
1661 bits at a time on the H8/S.
1663 The basic shift methods:
1665 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1666 this is the default. SHIFT_LOOP
1668 * inlined shifts -- emit straight line code for the shift; this is
1669 used when a straight line shift is about the same size or smaller
1670 than a loop. We allow the inline version to be slightly longer in
1671 some cases as it saves a register. SHIFT_INLINE
1673 * rotate + and -- rotate the value the opposite direction, then
1674 mask off the values we don't need. This is used when only a few
1675 of the bits in the original value will survive in the shifted value.
1676 Again, this is used when it's about the same size or smaller than
1677 a loop. We allow this version to be slightly longer as it is usually
1678 much faster than a loop. SHIFT_ROT_AND
1680 * swap (+ shifts) -- often it's possible to swap bytes/words to
1681 simulate a shift by 8/16. Once swapped a few inline shifts can be
1682 added if the shift count is slightly more than 8 or 16. This is used
1683 when it's about the same size or smaller than a loop. We allow this
1684 version to be slightly longer as it is usually much faster than a loop.
1687 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1689 Here are some thoughts on what the absolutely positively best code is.
1690 "Best" here means some rational trade-off between code size and speed,
1691 where speed is more preferred but not at the expense of generating 20 insns.
1693 A trailing '*' after the shift count indicates the "best" mode isn't
1696 H8/300 QImode shifts
1697 1-4 - do them inline
1698 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1700 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1701 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1703 H8/300 HImode shifts
1704 1-4 - do them inline
1706 7 - shift 2nd half other way into carry.
1707 copy 1st half into 2nd half
1708 rotate 2nd half other way with carry
1709 rotate 1st half other way (no carry)
1710 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1711 sign extend 1st half (ASHIFTRT)
1712 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1713 9-12 - do shift by 8, inline remaining shifts
1714 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1716 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1717 - ASHIFTRT: shll, subx, set other byte
1719 H8/300 SImode shifts
1720 1-2 - do them inline
1722 7* - shift other way once, move bytes into place,
1723 move carry into place (possibly with sign extension)
1724 8 - move bytes into place, zero or sign extend other
1726 15* - shift other way once, move word into place, move carry into place
1727 16 - move word, zero or sign extend other
1729 24* - move bytes into place, zero or sign extend other
1731 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1734 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1736 ASHIFTRT: shll top byte, subx, copy to other bytes
1738 H8/300H QImode shifts (same as H8/300 QImode shifts)
1739 1-4 - do them inline
1740 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1742 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1743 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1745 H8/300H HImode shifts
1746 1-4 - do them inline
1748 7 - shift 2nd half other way into carry.
1749 copy 1st half into 2nd half
1750 rotate entire word other way using carry
1751 mask off remaining bits (ASHIFT | LSHIFTRT)
1752 sign extend remaining bits (ASHIFTRT)
1753 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1754 9-12 - do shift by 8, inline remaining shifts
1755 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1757 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1758 - ASHIFTRT: shll, subx, set other byte
1760 H8/300H SImode shifts
1761 (These are complicated by the fact that we don't have byte level access to
1763 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1764 1-4 - do them inline
1766 15* - shift other way once, move word into place, move carry into place
1767 (with sign extension for ASHIFTRT)
1768 16 - move word into place, zero or sign extend other
1769 17-20 - do 16bit shift, then inline remaining shifts
1771 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1772 move word 0 to word 1, zero word 0
1773 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1774 zero word 1, zero byte 1
1775 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1776 sign extend byte 0, sign extend word 0
1777 25-27* - either loop, or
1778 do 24 bit shift, inline rest
1779 28-30 - ASHIFT: rotate 4/3/2, mask
1780 LSHIFTRT: rotate 4/3/2, mask
1782 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1785 1-6 - do them inline
1786 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1787 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1790 1-7 - do them inline
1791 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1792 9-12 - do shift by 8, inline remaining shifts
1793 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1795 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1796 - ASHIFTRT: shll, subx, set other byte
1799 (These are complicated by the fact that we don't have byte level access to
1801 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1802 1-10 - do them inline
1804 15* - shift other way once, move word into place, move carry into place
1805 (with sign extension for ASHIFTRT)
1806 16 - move word into place, zero or sign extend other
1807 17-20 - do 16bit shift, then inline remaining shifts
1809 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1810 move word 0 to word 1, zero word 0
1811 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1812 zero word 1, zero byte 1
1813 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1814 sign extend byte 0, sign extend word 0
1815 25-27* - either loop, or
1816 do 24 bit shift, inline rest
1817 28-30 - ASHIFT: rotate 4/3/2, mask
1818 LSHIFTRT: rotate 4/3/2, mask
1820 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1825 nshift_operator (x, mode)
1827 enum machine_mode mode ATTRIBUTE_UNUSED;
1829 switch (GET_CODE (x))
1841 /* Called from the .md file to emit code to do shifts.
1842 Returns a boolean indicating success
1843 (currently this is always TRUE). */
1846 expand_a_shift (mode, code, operands)
1847 enum machine_mode mode;
1851 emit_move_insn (operands[0], operands[1]);
1853 /* Need a loop to get all the bits we want - we generate the
1854 code at emit time, but need to allocate a scratch reg now. */
1856 emit_insn (gen_rtx_PARALLEL
1859 gen_rtx_SET (VOIDmode, operands[0],
1860 gen_rtx (code, mode, operands[0],
1862 gen_rtx_CLOBBER (VOIDmode,
1863 gen_rtx_SCRATCH (QImode)))));
1868 /* Shift algorithm determination.
1870 There are various ways of doing a shift:
1871 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1873 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1874 necessary bits into position and then set the rest to zero.
1875 SHIFT_SPECIAL: Hand crafted assembler.
1876 SHIFT_LOOP: If the above methods fail, just loop. */
1887 /* Symbols of the various shifts which can be used as indices. */
1891 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1894 /* Symbols of the various modes which can be used as indices. */
1898 QIshift, HIshift, SIshift
1901 /* For single bit shift insns, record assembler and what bits of the
1902 condition code are valid afterwards (represented as various CC_FOO
1903 bits, 0 means CC isn't left in a usable state). */
1907 const char *assembler;
1911 /* Assembler instruction shift table.
1913 These tables are used to look up the basic shifts.
1914 They are indexed by cpu, shift_type, and mode. */
1916 static const struct shift_insn shift_one[2][3][3] =
1922 { "shll\t%X0", CC_NO_CARRY },
1923 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1924 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
1926 /* SHIFT_LSHIFTRT */
1928 { "shlr\t%X0", CC_NO_CARRY },
1929 { "shlr\t%t0\n\trotxr\t%s0", 0 },
1930 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1932 /* SHIFT_ASHIFTRT */
1934 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1935 { "shar\t%t0\n\trotxr\t%s0", 0 },
1936 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1943 { "shll.b\t%X0", CC_NO_CARRY },
1944 { "shll.w\t%T0", CC_NO_CARRY },
1945 { "shll.l\t%S0", CC_NO_CARRY }
1947 /* SHIFT_LSHIFTRT */
1949 { "shlr.b\t%X0", CC_NO_CARRY },
1950 { "shlr.w\t%T0", CC_NO_CARRY },
1951 { "shlr.l\t%S0", CC_NO_CARRY }
1953 /* SHIFT_ASHIFTRT */
1955 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1956 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1957 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1962 static const struct shift_insn shift_two[3][3] =
1966 { "shll.b\t#2,%X0", CC_NO_CARRY },
1967 { "shll.w\t#2,%T0", CC_NO_CARRY },
1968 { "shll.l\t#2,%S0", CC_NO_CARRY }
1970 /* SHIFT_LSHIFTRT */
1972 { "shlr.b\t#2,%X0", CC_NO_CARRY },
1973 { "shlr.w\t#2,%T0", CC_NO_CARRY },
1974 { "shlr.l\t#2,%S0", CC_NO_CARRY }
1976 /* SHIFT_ASHIFTRT */
1978 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1979 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1980 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1984 /* Rotates are organized by which shift they'll be used in implementing.
1985 There's no need to record whether the cc is valid afterwards because
1986 it is the AND insn that will decide this. */
1988 static const char *const rotate_one[2][3][3] =
1995 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
1998 /* SHIFT_LSHIFTRT */
2001 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2004 /* SHIFT_ASHIFTRT */
2007 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2019 /* SHIFT_LSHIFTRT */
2025 /* SHIFT_ASHIFTRT */
2034 static const char *const rotate_two[3][3] =
2042 /* SHIFT_LSHIFTRT */
2048 /* SHIFT_ASHIFTRT */
2056 static enum shift_alg get_shift_alg PARAMS ((enum attr_cpu, enum shift_type,
2057 enum machine_mode, int,
2058 const char **, const char **,
2061 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
2062 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
2063 We don't achieve maximum efficiency in all cases, but the hooks are here
2066 For now we just use lots of switch statements. Since we don't even come
2067 close to supporting all the cases, this is simplest. If this function ever
2068 gets too big, perhaps resort to a more table based lookup. Of course,
2069 at this point you may just wish to do it all in rtl.
2071 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2072 1,2,3,4 will be inlined (1,2 for SI). */
2074 static enum shift_alg
2075 get_shift_alg (cpu, shift_type, mode, count, assembler_p,
2076 assembler2_p, cc_valid_p)
2078 enum shift_type shift_type;
2079 enum machine_mode mode;
2081 const char **assembler_p;
2082 const char **assembler2_p;
2085 /* The default is to loop. */
2086 enum shift_alg alg = SHIFT_LOOP;
2087 enum shift_mode shift_mode;
2089 /* We don't handle negative shifts or shifts greater than the word size,
2090 they should have been handled already. */
2092 if (count < 0 || count > GET_MODE_BITSIZE (mode))
2098 shift_mode = QIshift;
2101 shift_mode = HIshift;
2104 shift_mode = SIshift;
2110 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
2111 It is up to the caller to know that looping clobbers cc. */
2112 *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler;
2114 *assembler2_p = shift_two[shift_type][shift_mode].assembler;
2116 *assembler2_p = NULL;
2117 *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid;
2119 /* Now look for cases we want to optimize. */
2125 return SHIFT_INLINE;
2128 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
2129 fast as SHIFT_ROT_AND, plus CC is valid. */
2130 if (TARGET_H8300S && count <= 6)
2131 return SHIFT_INLINE;
2133 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2134 through the entire value. */
2135 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2137 *assembler_p = "shll\t%X0\n\tsubx\t%X0,%X0";
2139 return SHIFT_SPECIAL;
2142 /* Other ASHIFTRTs are too much of a pain. */
2143 if (shift_type == SHIFT_ASHIFTRT)
2146 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */
2147 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2149 *assembler2_p = rotate_two[shift_type][shift_mode];
2151 return SHIFT_ROT_AND;
2156 return SHIFT_INLINE;
2157 else if (TARGET_H8300S && count <= 7)
2158 return SHIFT_INLINE;
2159 else if (count == 7)
2161 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2163 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2165 return SHIFT_SPECIAL;
2168 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2170 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2172 return SHIFT_SPECIAL;
2175 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2177 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2179 return SHIFT_SPECIAL;
2182 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2184 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2186 return SHIFT_SPECIAL;
2189 if (shift_type == SHIFT_ASHIFTRT)
2191 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2193 return SHIFT_SPECIAL;
2196 else if (count == 8)
2201 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2203 return SHIFT_SPECIAL;
2204 case SHIFT_LSHIFTRT:
2205 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2207 return SHIFT_SPECIAL;
2208 case SHIFT_ASHIFTRT:
2210 *assembler_p = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0\t";
2212 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2214 return SHIFT_SPECIAL;
2217 else if (count == 9)
2222 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
2224 return SHIFT_SPECIAL;
2225 case SHIFT_LSHIFTRT:
2226 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
2228 return SHIFT_SPECIAL;
2229 case SHIFT_ASHIFTRT:
2231 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
2233 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
2235 return SHIFT_SPECIAL;
2238 else if (count == 10)
2244 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\t";
2246 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2248 return SHIFT_SPECIAL;
2249 case SHIFT_LSHIFTRT:
2251 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
2253 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2255 return SHIFT_SPECIAL;
2256 case SHIFT_ASHIFTRT:
2258 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2259 else if (TARGET_H8300H)
2260 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2261 else if (TARGET_H8300S)
2262 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
2264 return SHIFT_SPECIAL;
2267 else if (count == 11)
2273 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
2275 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2277 return SHIFT_SPECIAL;
2278 case SHIFT_LSHIFTRT:
2280 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
2282 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2284 return SHIFT_SPECIAL;
2285 case SHIFT_ASHIFTRT:
2287 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2288 else if (TARGET_H8300H)
2289 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2290 else if (TARGET_H8300S)
2291 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
2293 return SHIFT_SPECIAL;
2296 else if (count == 12)
2302 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
2304 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2306 return SHIFT_SPECIAL;
2307 case SHIFT_LSHIFTRT:
2309 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
2311 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2313 return SHIFT_SPECIAL;
2314 case SHIFT_ASHIFTRT:
2316 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2317 else if (TARGET_H8300H)
2318 *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2319 else if (TARGET_H8300S)
2320 *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
2322 return SHIFT_SPECIAL;
2325 else if ((!TARGET_H8300 && (count == 13 || count == 14))
2328 if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2330 *assembler_p = "shll\t%t0,%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2332 return SHIFT_SPECIAL;
2334 else if (shift_type != SHIFT_ASHIFTRT)
2336 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2338 *assembler2_p = rotate_two[shift_type][shift_mode];
2340 *assembler2_p = NULL;
2342 return SHIFT_ROT_AND;
2348 if (count <= (TARGET_H8300 ? 2 : 4))
2349 return SHIFT_INLINE;
2350 else if (TARGET_H8300S && count <= 10)
2351 return SHIFT_INLINE;
2352 else if (count == 8 && TARGET_H8300)
2357 *assembler_p = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2359 return SHIFT_SPECIAL;
2360 case SHIFT_LSHIFTRT:
2361 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2363 return SHIFT_SPECIAL;
2364 case SHIFT_ASHIFTRT:
2365 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2367 return SHIFT_SPECIAL;
2370 else if (count == 8 && !TARGET_H8300)
2375 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2377 return SHIFT_SPECIAL;
2378 case SHIFT_LSHIFTRT:
2379 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2381 return SHIFT_SPECIAL;
2382 case SHIFT_ASHIFTRT:
2383 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2385 return SHIFT_SPECIAL;
2388 else if (count == 16)
2393 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2395 return SHIFT_SPECIAL;
2396 case SHIFT_LSHIFTRT:
2397 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2399 return SHIFT_SPECIAL;
2400 case SHIFT_ASHIFTRT:
2402 *assembler_p = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2404 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2406 return SHIFT_SPECIAL;
2409 else if (count == 17 && !TARGET_H8300)
2414 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
2416 return SHIFT_SPECIAL;
2417 case SHIFT_LSHIFTRT:
2418 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
2420 return SHIFT_SPECIAL;
2421 case SHIFT_ASHIFTRT:
2422 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
2424 return SHIFT_SPECIAL;
2427 else if (count == 18 && !TARGET_H8300)
2433 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
2435 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2437 return SHIFT_SPECIAL;
2438 case SHIFT_LSHIFTRT:
2440 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
2442 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2444 return SHIFT_SPECIAL;
2445 case SHIFT_ASHIFTRT:
2447 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
2449 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2451 return SHIFT_SPECIAL;
2454 else if (count == 19 && !TARGET_H8300)
2460 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
2462 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2464 return SHIFT_SPECIAL;
2465 case SHIFT_LSHIFTRT:
2467 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
2469 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2471 return SHIFT_SPECIAL;
2472 case SHIFT_ASHIFTRT:
2474 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
2476 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2478 return SHIFT_SPECIAL;
2481 else if (count == 20 && TARGET_H8300S)
2486 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
2488 return SHIFT_SPECIAL;
2489 case SHIFT_LSHIFTRT:
2490 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
2492 return SHIFT_SPECIAL;
2493 case SHIFT_ASHIFTRT:
2494 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
2496 return SHIFT_SPECIAL;
2499 else if (count == 24 && !TARGET_H8300)
2504 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2506 return SHIFT_SPECIAL;
2507 case SHIFT_LSHIFTRT:
2508 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2510 return SHIFT_SPECIAL;
2511 case SHIFT_ASHIFTRT:
2512 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2514 return SHIFT_SPECIAL;
2517 else if (count >= 28 && count <= 30 && !TARGET_H8300)
2519 if (shift_type == SHIFT_ASHIFTRT)
2525 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2527 *assembler2_p = rotate_two[shift_type][shift_mode];
2529 *assembler2_p = NULL;
2531 return SHIFT_ROT_AND;
2534 else if (count == 31)
2536 if (shift_type == SHIFT_ASHIFTRT)
2539 *assembler_p = "shll\t%z0\n\tsubx %w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2541 *assembler_p = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2543 return SHIFT_SPECIAL;
2549 if (shift_type == SHIFT_ASHIFT)
2550 *assembler_p = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2552 *assembler_p = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2554 return SHIFT_SPECIAL;
2558 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2560 *assembler2_p = rotate_two[shift_type][shift_mode];
2562 *assembler2_p = NULL;
2564 return SHIFT_ROT_AND;
2577 /* Emit the assembler code for doing shifts. */
2580 emit_a_shift (insn, operands)
2581 rtx insn ATTRIBUTE_UNUSED;
2584 static int loopend_lab;
2585 const char *assembler;
2586 const char *assembler2;
2588 rtx shift = operands[3];
2589 enum machine_mode mode = GET_MODE (shift);
2590 enum rtx_code code = GET_CODE (shift);
2591 enum shift_type shift_type;
2592 enum shift_mode shift_mode;
2599 shift_mode = QIshift;
2602 shift_mode = HIshift;
2605 shift_mode = SIshift;
2614 shift_type = SHIFT_ASHIFTRT;
2617 shift_type = SHIFT_LSHIFTRT;
2620 shift_type = SHIFT_ASHIFT;
2626 if (GET_CODE (operands[2]) != CONST_INT)
2628 /* Indexing by reg, so have to loop and test at top. */
2629 output_asm_insn ("mov.b %X2,%X4", operands);
2630 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2632 /* Get the assembler code to do one shift. */
2633 get_shift_alg (cpu_type, shift_type, mode, 1, &assembler,
2634 &assembler2, &cc_valid);
2638 int n = INTVAL (operands[2]);
2641 /* If the count is negative, make it 0. */
2644 /* If the count is too big, truncate it.
2645 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2646 do the intuitive thing. */
2647 else if (n > GET_MODE_BITSIZE (mode))
2648 n = GET_MODE_BITSIZE (mode);
2650 alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler,
2651 &assembler2, &cc_valid);
2656 /* Emit two bit shifts first. */
2657 while (n > 1 && assembler2 != NULL)
2659 output_asm_insn (assembler2, operands);
2663 /* Now emit one bit shifts for any residual. */
2666 output_asm_insn (assembler, operands);
2670 /* Keep track of CC. */
2673 cc_status.value1 = operands[0];
2674 cc_status.flags |= cc_valid;
2680 int m = GET_MODE_BITSIZE (mode) - n;
2681 int mask = (shift_type == SHIFT_ASHIFT
2682 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2683 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2685 /* Not all possibilities of rotate are supported. They shouldn't
2686 be generated, but let's watch for 'em. */
2690 /* Emit two bit rotates first. */
2691 while (m > 1 && assembler2 != NULL)
2693 output_asm_insn (assembler2, operands);
2697 /* Now single bit rotates for any residual. */
2700 output_asm_insn (assembler, operands);
2704 /* Now mask off the high bits. */
2710 sprintf (insn_buf, "and #%d,%%X0", mask);
2711 cc_status.value1 = operands[0];
2712 cc_status.flags |= CC_NO_CARRY;
2715 sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0",
2716 mask & 255, mask >> 8);
2726 sprintf (insn_buf, "and.%c #%d,%%%c0",
2727 "bwl"[shift_mode], mask,
2728 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2729 cc_status.value1 = operands[0];
2730 cc_status.flags |= CC_NO_CARRY;
2732 output_asm_insn (insn_buf, operands);
2736 output_asm_insn (assembler, operands);
2740 /* A loop to shift by a "large" constant value.
2741 If we have shift-by-2 insns, use them. */
2742 if (assembler2 != NULL)
2744 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2745 names_big[REGNO (operands[4])]);
2746 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2747 output_asm_insn (assembler2, operands);
2748 output_asm_insn ("add #0xff,%X4", operands);
2749 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2751 output_asm_insn (assembler, operands);
2756 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2757 names_big[REGNO (operands[4])]);
2758 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2759 output_asm_insn (assembler, operands);
2760 output_asm_insn ("add #0xff,%X4", operands);
2761 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2766 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2767 output_asm_insn (assembler, operands);
2768 output_asm_insn ("add #0xff,%X4", operands);
2769 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2770 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2775 /* Fix the operands of a gen_xxx so that it could become a bit
2779 fix_bit_operand (operands, what, type)
2784 /* The bit_operand predicate accepts any memory during RTL generation, but
2785 only 'U' memory afterwards, so if this is a MEM operand, we must force
2786 it to be valid for 'U' by reloading the address. */
2788 if (GET_CODE (operands[2]) == CONST_INT)
2790 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
2792 /* Ok to have a memory dest. */
2793 if (GET_CODE (operands[0]) == MEM && !EXTRA_CONSTRAINT (operands[0], 'U'))
2795 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
2796 copy_to_mode_reg (Pmode,
2797 XEXP (operands[0], 0)));
2798 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2802 if (GET_CODE (operands[1]) == MEM && !EXTRA_CONSTRAINT (operands[1], 'U'))
2804 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
2805 copy_to_mode_reg (Pmode,
2806 XEXP (operands[1], 0)));
2807 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2814 /* Dest and src op must be register. */
2816 operands[1] = force_reg (QImode, operands[1]);
2818 rtx res = gen_reg_rtx (QImode);
2819 emit_insn (gen_rtx_SET (VOIDmode, res,
2820 gen_rtx (type, QImode, operands[1], operands[2])));
2821 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
2826 /* Return nonzero if FUNC is an interrupt function as specified
2827 by the "interrupt" attribute. */
2830 h8300_interrupt_function_p (func)
2835 if (TREE_CODE (func) != FUNCTION_DECL)
2838 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
2839 return a != NULL_TREE;
2842 /* Return nonzero if FUNC is an OS_Task function as specified
2843 by the "OS_Task" attribute. */
2846 h8300_os_task_function_p (func)
2851 if (TREE_CODE (func) != FUNCTION_DECL)
2854 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
2855 return a != NULL_TREE;
2858 /* Return nonzero if FUNC is a monitor function as specified
2859 by the "monitor" attribute. */
2862 h8300_monitor_function_p (func)
2867 if (TREE_CODE (func) != FUNCTION_DECL)
2870 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
2871 return a != NULL_TREE;
2874 /* Return nonzero if FUNC is a function that should be called
2875 through the function vector. */
2878 h8300_funcvec_function_p (func)
2883 if (TREE_CODE (func) != FUNCTION_DECL)
2886 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
2887 return a != NULL_TREE;
2890 /* Return nonzero if DECL is a variable that's in the eight bit
2894 h8300_eightbit_data_p (decl)
2899 if (TREE_CODE (decl) != VAR_DECL)
2902 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
2903 return a != NULL_TREE;
2906 /* Return nonzero if DECL is a variable that's in the tiny
2910 h8300_tiny_data_p (decl)
2915 if (TREE_CODE (decl) != VAR_DECL)
2918 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
2919 return a != NULL_TREE;
2922 /* Return nonzero if ATTR is a valid attribute for DECL.
2923 ATTRIBUTES are any existing attributes and ARGS are the arguments
2926 Supported attributes:
2928 interrupt_handler: output a prologue and epilogue suitable for an
2931 function_vector: This function should be called through the
2934 eightbit_data: This variable lives in the 8-bit data area and can
2935 be referenced with 8-bit absolute memory addresses.
2937 tiny_data: This variable lives in the tiny data area and can be
2938 referenced with 16-bit absolute memory references. */
2941 h8300_valid_machine_decl_attribute (decl, attributes, attr, args)
2943 tree attributes ATTRIBUTE_UNUSED;
2947 if (args != NULL_TREE)
2950 if (is_attribute_p ("interrupt_handler", attr)
2951 || is_attribute_p ("OS_Task", attr)
2952 || is_attribute_p ("monitor", attr)
2953 || is_attribute_p ("function_vector", attr))
2954 return TREE_CODE (decl) == FUNCTION_DECL;
2956 if (is_attribute_p ("eightbit_data", attr)
2957 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
2959 if (DECL_INITIAL (decl) == NULL_TREE)
2961 warning ("Only initialized variables can be placed into the 8-bit area.");
2964 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
2968 if (is_attribute_p ("tiny_data", attr)
2969 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
2971 if (DECL_INITIAL (decl) == NULL_TREE)
2973 warning ("Only initialized variables can be placed into the 8-bit area.");
2976 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
2983 extern struct obstack *saveable_obstack;
2986 h8300_encode_label (decl)
2989 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2990 int len = strlen (str);
2993 newstr = obstack_alloc (saveable_obstack, len + 2);
2995 strcpy (newstr + 1, str);
2997 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3001 output_simode_bld (bild, log2, operands)
3006 /* Clear the destination register. */
3007 if (TARGET_H8300H || TARGET_H8300S)
3008 output_asm_insn ("sub.l\t%S0,%S0", operands);
3010 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3012 /* Get the bit number we want to load. */
3014 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3016 /* Now output the bit load or bit inverse load, and store it in
3019 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3021 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3027 /* Given INSN and its current length LENGTH, return the adjustment
3028 (in bytes) to correctly compute INSN's length.
3030 We use this to get the lengths of various memory references correct. */
3033 h8300_adjust_insn_length (insn, length)
3035 int length ATTRIBUTE_UNUSED;
3039 /* We must filter these ou before calling get_attr_adjust_length. */
3040 if (GET_CODE (PATTERN (insn)) == USE
3041 || GET_CODE (PATTERN (insn)) == CLOBBER
3042 || GET_CODE (PATTERN (insn)) == SEQUENCE
3043 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3044 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3047 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3050 pat = PATTERN (insn);
3052 /* Adjust length for reg->mem and mem->reg copies. */
3053 if (GET_CODE (pat) == SET
3054 && (GET_CODE (SET_SRC (pat)) == MEM
3055 || GET_CODE (SET_DEST (pat)) == MEM))
3057 /* This insn might need a length adjustment. */
3060 if (GET_CODE (SET_SRC (pat)) == MEM)
3061 addr = XEXP (SET_SRC (pat), 0);
3063 addr = XEXP (SET_DEST (pat), 0);
3065 /* On the H8/300, only one adjustment is necessary; if the
3066 address mode is register indirect, then this insn is two
3067 bytes shorter than indicated in the machine description. */
3068 if (TARGET_H8300 && GET_CODE (addr) == REG)
3071 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3072 indicated in the machine description. */
3073 if ((TARGET_H8300H || TARGET_H8300S)
3074 && GET_CODE (addr) == REG)
3077 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3078 bytes shorter than indicated in the machine description. */
3079 if ((TARGET_H8300H || TARGET_H8300S)
3080 && GET_CODE (addr) == PLUS
3081 && GET_CODE (XEXP (addr, 0)) == REG
3082 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3083 && INTVAL (XEXP (addr, 1)) > -32768
3084 && INTVAL (XEXP (addr, 1)) < 32767)
3087 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3088 more general abs:24. */
3089 if ((TARGET_H8300H || TARGET_H8300S)
3090 && GET_CODE (addr) == SYMBOL_REF
3091 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3095 /* Loading some constants needs adjustment. */
3096 if (GET_CODE (pat) == SET
3097 && GET_CODE (SET_SRC (pat)) == CONST_INT
3098 && GET_MODE (SET_DEST (pat)) == SImode
3099 && INTVAL (SET_SRC (pat)) != 0)
3102 && ((INTVAL (SET_SRC (pat)) & 0xffff) == 0
3103 || ((INTVAL (SET_SRC (pat)) >> 16) & 0xffff) == 0))
3106 if (TARGET_H8300H || TARGET_H8300S)
3108 int val = INTVAL (SET_SRC (pat));
3110 if (val == (val & 0xff)
3111 || val == (val & 0xff00))
3114 if (val == -4 || val == -2 || val == -1)
3119 /* Shifts need various adjustments. */
3120 if (GET_CODE (pat) == PARALLEL
3121 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3122 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3123 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3124 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3126 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3127 enum machine_mode mode = GET_MODE (src);
3130 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3133 shift = INTVAL (XEXP (src, 1));
3134 /* According to ANSI, negative shift is undefined. It is
3135 considered to be zero in this case (see function
3136 emit_a_shift above). */
3140 /* QImode shifts by small constants take one insn
3141 per shift. So the adjustment is 20 (md length) -
3143 if (mode == QImode && shift <= 4)
3144 return -(20 - shift * 2);
3146 /* Similarly for HImode and SImode shifts by
3147 small constants on the H8/300H and H8/300S. */
3148 if ((TARGET_H8300H || TARGET_H8300S)
3149 && (mode == HImode || mode == SImode) && shift <= 4)
3150 return -(20 - shift * 2);
3152 /* HImode shifts by small constants for the H8/300. */
3153 if (mode == HImode && shift <= 4)
3154 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3156 /* SImode shifts by small constants for the H8/300. */
3157 if (mode == SImode && shift <= 2)
3158 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3160 /* XXX ??? Could check for more shift/rotate cases here. */