1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg PARAMS ((rtx, int));
50 static int h8300_interrupt_function_p PARAMS ((tree));
51 static int h8300_monitor_function_p PARAMS ((tree));
52 static int h8300_os_task_function_p PARAMS ((tree));
53 static void dosize PARAMS ((int, unsigned int));
54 static int round_frame_size PARAMS ((int));
55 static unsigned int compute_saved_regs PARAMS ((void));
56 static void push PARAMS ((int));
57 static void pop PARAMS ((int));
58 static const char *cond_string PARAMS ((enum rtx_code));
59 static unsigned int h8300_asm_insn_count PARAMS ((const char *));
60 const struct attribute_spec h8300_attribute_table[];
61 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
62 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
63 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
64 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
65 static void h8300_insert_attributes PARAMS ((tree, tree *));
66 #ifndef OBJECT_FORMAT_ELF
67 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
69 static void h8300_encode_label PARAMS ((tree));
70 static void h8300_encode_section_info PARAMS ((tree, int));
71 static const char *h8300_strip_name_encoding PARAMS ((const char *));
72 static int const_costs PARAMS ((rtx, enum rtx_code, enum rtx_code));
73 static int h8300_and_costs PARAMS ((rtx));
74 static int h8300_shift_costs PARAMS ((rtx));
75 static bool h8300_rtx_costs PARAMS ((rtx, int, int, int *));
77 /* CPU_TYPE, says what cpu we're compiling for. */
80 /* True if a #pragma interrupt has been seen for the current function. */
81 static int pragma_interrupt;
83 /* True if a #pragma saveall has been seen for the current function. */
84 static int pragma_saveall;
86 static const char *const names_big[] =
87 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
89 static const char *const names_extended[] =
90 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
92 static const char *const names_upper_extended[] =
93 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
95 /* Points to one of the above. */
96 /* ??? The above could be put in an array indexed by CPU_TYPE. */
97 const char * const *h8_reg_names;
99 /* Various operations needed by the following, indexed by CPU_TYPE. */
101 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
103 /* Initialize the GCC target structure. */
104 #undef TARGET_ATTRIBUTE_TABLE
105 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
107 #undef TARGET_ASM_ALIGNED_HI_OP
108 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
110 #undef TARGET_ASM_FUNCTION_EPILOGUE
111 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
112 #undef TARGET_ENCODE_SECTION_INFO
113 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
114 #undef TARGET_STRIP_NAME_ENCODING
115 #define TARGET_STRIP_NAME_ENCODING h8300_strip_name_encoding
117 #undef TARGET_INSERT_ATTRIBUTES
118 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
120 #undef TARGET_RTX_COSTS
121 #define TARGET_RTX_COSTS h8300_rtx_costs
123 struct gcc_target targetm = TARGET_INITIALIZER;
125 /* See below where shifts are handled for explanation of this enum. */
135 /* Symbols of the various shifts which can be used as indices. */
139 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
142 /* Macros to keep the shift algorithm tables small. */
143 #define INL SHIFT_INLINE
144 #define ROT SHIFT_ROT_AND
145 #define LOP SHIFT_LOOP
146 #define SPC SHIFT_SPECIAL
148 /* The shift algorithms for each machine, mode, shift type, and shift
149 count are defined below. The three tables below correspond to
150 QImode, HImode, and SImode, respectively. Each table is organized
151 by, in the order of indices, machine, shift type, and shift count. */
153 static enum shift_alg shift_alg_qi[3][3][8] = {
156 /* 0 1 2 3 4 5 6 7 */
157 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
158 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
159 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
163 /* 0 1 2 3 4 5 6 7 */
164 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
165 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
166 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
170 /* 0 1 2 3 4 5 6 7 */
171 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
173 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
177 static enum shift_alg shift_alg_hi[3][3][16] = {
180 /* 0 1 2 3 4 5 6 7 */
181 /* 8 9 10 11 12 13 14 15 */
182 { INL, INL, INL, INL, INL, INL, INL, SPC,
183 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
184 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
185 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
186 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
187 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
191 /* 0 1 2 3 4 5 6 7 */
192 /* 8 9 10 11 12 13 14 15 */
193 { INL, INL, INL, INL, INL, INL, INL, SPC,
194 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
195 { INL, INL, INL, INL, INL, INL, INL, SPC,
196 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
197 { INL, INL, INL, INL, INL, INL, INL, SPC,
198 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
202 /* 0 1 2 3 4 5 6 7 */
203 /* 8 9 10 11 12 13 14 15 */
204 { INL, INL, INL, INL, INL, INL, INL, INL,
205 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
206 { INL, INL, INL, INL, INL, INL, INL, INL,
207 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
208 { INL, INL, INL, INL, INL, INL, INL, INL,
209 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
213 static enum shift_alg shift_alg_si[3][3][32] = {
216 /* 0 1 2 3 4 5 6 7 */
217 /* 8 9 10 11 12 13 14 15 */
218 /* 16 17 18 19 20 21 22 23 */
219 /* 24 25 26 27 28 29 30 31 */
220 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
222 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
223 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
224 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
225 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
226 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
227 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
228 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
229 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
230 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
231 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
235 /* 0 1 2 3 4 5 6 7 */
236 /* 8 9 10 11 12 13 14 15 */
237 /* 16 17 18 19 20 21 22 23 */
238 /* 24 25 26 27 28 29 30 31 */
239 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
240 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
242 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
243 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
244 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
245 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
246 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
247 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
248 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
249 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
250 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
254 /* 0 1 2 3 4 5 6 7 */
255 /* 8 9 10 11 12 13 14 15 */
256 /* 16 17 18 19 20 21 22 23 */
257 /* 24 25 26 27 28 29 30 31 */
258 { INL, INL, INL, INL, INL, INL, INL, INL,
259 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
260 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
261 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
262 { INL, INL, INL, INL, INL, INL, INL, INL,
263 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
264 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
265 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
266 { INL, INL, INL, INL, INL, INL, INL, INL,
267 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
268 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
269 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
285 /* Initialize various cpu specific globals at start up. */
290 static const char *const h8_push_ops[2] = { "push" , "push.l" };
291 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
292 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
296 cpu_type = (int) CPU_H8300;
297 h8_reg_names = names_big;
301 /* For this we treat the H8/300H and H8S the same. */
302 cpu_type = (int) CPU_H8300H;
303 h8_reg_names = names_extended;
305 h8_push_op = h8_push_ops[cpu_type];
306 h8_pop_op = h8_pop_ops[cpu_type];
307 h8_mov_op = h8_mov_ops[cpu_type];
309 if (!TARGET_H8300S && TARGET_MAC)
311 error ("-ms2600 is used without -ms");
312 target_flags |= MASK_H8300S;
315 if (TARGET_H8300 && TARGET_NORMAL_MODE)
317 error ("-mn is used without -mh or -ms");
318 target_flags ^= MASK_NORMAL_MODE;
321 /* Some of the shifts are optimized for speed by default.
322 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
323 If optimizing for size, change shift_alg for those shift to
328 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
329 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
330 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
331 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
333 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
334 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
336 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
337 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
340 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
341 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
343 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
344 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
346 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
347 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
348 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
349 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
352 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
361 static const char *const names_small[] = {
362 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
363 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
366 return names_small[REGNO (x) * 2 + b];
369 /* REGNO must be saved/restored across calls if this macro is true. */
371 #define WORD_REG_USED(regno) \
373 /* No need to save registers if this function will not return. */ \
374 && ! TREE_THIS_VOLATILE (current_function_decl) \
376 /* Save any call saved register that was used. */ \
377 || (regs_ever_live[regno] && !call_used_regs[regno]) \
378 /* Save the frame pointer if it was used. */ \
379 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
380 /* Save any register used in an interrupt handler. */ \
381 || (h8300_current_function_interrupt_function_p () \
382 && regs_ever_live[regno]) \
383 /* Save call clobbered registers in non-leaf interrupt \
385 || (h8300_current_function_interrupt_function_p () \
386 && call_used_regs[regno] \
387 && !current_function_is_leaf)))
389 /* Output assembly language to FILE for the operation OP with operand size
390 SIZE to adjust the stack pointer. */
397 /* H8/300 cannot add/subtract a large constant with a single
398 instruction. If a temporary register is available, load the
399 constant to it and then do the addition. */
402 && !h8300_current_function_interrupt_function_p ()
403 && !(current_function_needs_context && sign < 0))
406 rtx r3 = gen_rtx_REG (Pmode, 3);
407 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
408 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
409 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
413 /* The stack adjustment made here is further optimized by the
414 splitter. In case of H8/300, the splitter always splits the
415 addition emitted here to make the adjustment
417 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
418 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
422 /* Round up frame size SIZE. */
425 round_frame_size (size)
428 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
429 & -STACK_BOUNDARY / BITS_PER_UNIT);
432 /* Compute which registers to push/pop.
433 Return a bit vector of registers. */
436 compute_saved_regs ()
438 unsigned int saved_regs = 0;
441 /* Construct a bit vector of registers to be pushed/popped. */
442 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
444 if (WORD_REG_USED (regno))
445 saved_regs |= 1 << regno;
448 /* Don't push/pop the frame pointer as it is treated separately. */
449 if (frame_pointer_needed)
450 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
455 /* Emit an insn to push register RN. */
461 rtx reg = gen_rtx_REG (word_mode, rn);
465 x = gen_push_h8300 (reg);
467 x = gen_push_h8300hs (reg);
469 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
472 /* Emit an insn to pop register RN. */
478 rtx reg = gen_rtx_REG (word_mode, rn);
482 x = gen_pop_h8300 (reg);
484 x = gen_pop_h8300hs (reg);
486 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
489 /* This is what the stack looks like after the prolog of
490 a function with a frame has been set up:
496 <saved registers> <- sp
498 This is what the stack looks like after the prolog of
499 a function which doesn't have a frame:
504 <saved registers> <- sp
507 /* Generate RTL code for the function prologue. */
510 h8300_expand_prologue ()
516 /* If the current function has the OS_Task attribute set, then
517 we have a naked prologue. */
518 if (h8300_os_task_function_p (current_function_decl))
521 if (h8300_monitor_function_p (current_function_decl))
522 /* My understanding of monitor functions is they act just like
523 interrupt functions, except the prologue must mask
525 emit_insn (gen_monitor_prologue ());
527 if (frame_pointer_needed)
530 push (FRAME_POINTER_REGNUM);
531 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
534 /* Leave room for locals. */
535 dosize (-1, round_frame_size (get_frame_size ()));
537 /* Push the rest of the registers in ascending order. */
538 saved_regs = compute_saved_regs ();
539 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
542 if (saved_regs & (1 << regno))
546 /* See how many registers we can push at the same time. */
547 if ((regno == 0 || regno == 4)
548 && ((saved_regs >> regno) & 0x0f) == 0x0f)
551 else if ((regno == 0 || regno == 4)
552 && ((saved_regs >> regno) & 0x07) == 0x07)
555 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
556 && ((saved_regs >> regno) & 0x03) == 0x03)
566 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
567 gen_rtx_REG (SImode, regno + 1)));
570 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
571 gen_rtx_REG (SImode, regno + 1),
572 gen_rtx_REG (SImode, regno + 2)));
575 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
576 gen_rtx_REG (SImode, regno + 1),
577 gen_rtx_REG (SImode, regno + 2),
578 gen_rtx_REG (SImode, regno + 3)));
588 h8300_can_use_return_insn_p ()
590 return (reload_completed
591 && !frame_pointer_needed
592 && get_frame_size () == 0
593 && compute_saved_regs () == 0);
596 /* Generate RTL code for the function epilogue. */
599 h8300_expand_epilogue ()
605 if (h8300_os_task_function_p (current_function_decl))
606 /* OS_Task epilogues are nearly naked -- they just have an
610 /* Pop the saved registers in descending order. */
611 saved_regs = compute_saved_regs ();
612 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
615 if (saved_regs & (1 << regno))
619 /* See how many registers we can pop at the same time. */
620 if ((regno == 7 || regno == 3)
621 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
624 else if ((regno == 6 || regno == 2)
625 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
628 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
629 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
639 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
640 gen_rtx_REG (SImode, regno)));
643 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
644 gen_rtx_REG (SImode, regno - 1),
645 gen_rtx_REG (SImode, regno)));
648 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
649 gen_rtx_REG (SImode, regno - 2),
650 gen_rtx_REG (SImode, regno - 1),
651 gen_rtx_REG (SImode, regno)));
659 /* Deallocate locals. */
660 dosize (1, round_frame_size (get_frame_size ()));
662 /* Pop frame pointer if we had one. */
663 if (frame_pointer_needed)
664 pop (FRAME_POINTER_REGNUM);
667 /* Output assembly language code for the function epilogue. */
670 h8300_output_function_epilogue (file, size)
671 FILE *file ATTRIBUTE_UNUSED;
672 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
677 /* Return nonzero if the current function is an interrupt
681 h8300_current_function_interrupt_function_p ()
683 return (h8300_interrupt_function_p (current_function_decl)
684 || h8300_monitor_function_p (current_function_decl));
687 /* Output assembly code for the start of the file. */
690 asm_file_start (file)
693 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
694 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
697 fprintf (file, "; -Os\n");
699 fprintf (file, "; -O%d\n", optimize);
701 fprintf (file, "\n\t.h8300h\n");
702 else if (TARGET_H8300S)
703 fprintf (file, "\n\t.h8300s\n");
705 fprintf (file, "\n\n");
706 output_file_directive (file, main_input_filename);
709 /* Output assembly language code for the end of file. */
715 fprintf (file, "\t.end\n");
718 /* Return true if OP is a valid source operand for an integer move
722 general_operand_src (op, mode)
724 enum machine_mode mode;
726 if (GET_MODE (op) == mode
727 && GET_CODE (op) == MEM
728 && GET_CODE (XEXP (op, 0)) == POST_INC)
730 return general_operand (op, mode);
733 /* Return true if OP is a valid destination operand for an integer move
737 general_operand_dst (op, mode)
739 enum machine_mode mode;
741 if (GET_MODE (op) == mode
742 && GET_CODE (op) == MEM
743 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
745 return general_operand (op, mode);
748 /* Return true if OP is a constant that contains only one 1 in its
749 binary representation. */
752 single_one_operand (operand, mode)
754 enum machine_mode mode ATTRIBUTE_UNUSED;
756 if (GET_CODE (operand) == CONST_INT)
758 /* We really need to do this masking because 0x80 in QImode is
759 represented as -128 for example. */
760 unsigned HOST_WIDE_INT mask =
761 (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
762 ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
763 : ~(unsigned HOST_WIDE_INT) 0;
764 unsigned HOST_WIDE_INT value = INTVAL (operand);
766 if (exact_log2 (value & mask) >= 0)
773 /* Return true if OP is a constant that contains only one 0 in its
774 binary representation. */
777 single_zero_operand (operand, mode)
779 enum machine_mode mode ATTRIBUTE_UNUSED;
781 if (GET_CODE (operand) == CONST_INT)
783 /* We really need to do this masking because 0x80 in QImode is
784 represented as -128 for example. */
785 unsigned HOST_WIDE_INT mask =
786 (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
787 ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
788 : ~(unsigned HOST_WIDE_INT) 0;
789 unsigned HOST_WIDE_INT value = INTVAL (operand);
791 if (exact_log2 (~value & mask) >= 0)
798 /* Return true if OP is a valid call operand. */
801 call_insn_operand (op, mode)
803 enum machine_mode mode ATTRIBUTE_UNUSED;
805 if (GET_CODE (op) == MEM)
807 rtx inside = XEXP (op, 0);
808 if (register_operand (inside, Pmode))
810 if (CONSTANT_ADDRESS_P (inside))
816 /* Return 1 if an addition/subtraction of a constant integer can be
817 transformed into two consecutive adds/subs that are faster than the
818 straightforward way. Otherwise, return 0. */
821 two_insn_adds_subs_operand (op, mode)
823 enum machine_mode mode;
825 if (GET_CODE (op) == CONST_INT)
827 HOST_WIDE_INT value = INTVAL (op);
829 /* Force VALUE to be positive so that we do not have to consider
830 the negative case. */
833 if (TARGET_H8300H || TARGET_H8300S)
835 /* A constant addition/subtraction takes 2 states in QImode,
836 4 states in HImode, and 6 states in SImode. Thus, the
837 only case we can win is when SImode is used, in which
838 case, two adds/subs are used, taking 4 states. */
848 /* We do not profit directly by splitting addition or
849 subtraction of 3 and 4. However, since these are
850 implemented as a sequence of adds or subs, they do not
851 clobber (cc0) unlike a sequence of add.b and add.x. */
862 /* Split an add of a small constant into two adds/subs insns.
864 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
865 instead of adds/subs. */
868 split_adds_subs (mode, operands)
869 enum machine_mode mode;
872 HOST_WIDE_INT val = INTVAL (operands[1]);
873 rtx reg = operands[0];
874 HOST_WIDE_INT sign = 1;
875 HOST_WIDE_INT amount;
876 rtx (*gen_add) (rtx, rtx, rtx);
878 /* Force VAL to be positive so that we do not have to consider the
889 gen_add = gen_addhi3;
893 gen_add = gen_addsi3;
900 /* Try different amounts in descending order. */
901 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
905 for (; val >= amount; val -= amount)
906 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
912 /* Return true if OP is a valid call operand, and OP represents
913 an operand for a small call (4 bytes instead of 6 bytes). */
916 small_call_insn_operand (op, mode)
918 enum machine_mode mode ATTRIBUTE_UNUSED;
920 if (GET_CODE (op) == MEM)
922 rtx inside = XEXP (op, 0);
924 /* Register indirect is a small call. */
925 if (register_operand (inside, Pmode))
928 /* A call through the function vector is a small
930 if (GET_CODE (inside) == SYMBOL_REF
931 && SYMBOL_REF_FLAG (inside))
934 /* Otherwise it's a large call. */
938 /* Return true if OP is a valid jump operand. */
941 jump_address_operand (op, mode)
943 enum machine_mode mode;
945 if (GET_CODE (op) == REG)
946 return mode == Pmode;
948 if (GET_CODE (op) == MEM)
950 rtx inside = XEXP (op, 0);
951 if (register_operand (inside, Pmode))
953 if (CONSTANT_ADDRESS_P (inside))
959 /* Recognize valid operands for bit-field instructions. */
961 extern int rtx_equal_function_value_matters;
964 bit_operand (op, mode)
966 enum machine_mode mode;
968 /* We can accept any general operand, except that MEM operands must
969 be limited to those that use addresses valid for the 'U' constraint. */
970 if (!general_operand (op, mode))
973 /* Accept any mem during RTL generation. Otherwise, the code that does
974 insv and extzv will think that we can not handle memory. However,
975 to avoid reload problems, we only accept 'U' MEM operands after RTL
976 generation. This means that any named pattern which uses this predicate
977 must force its operands to match 'U' before emitting RTL. */
979 if (GET_CODE (op) == REG)
981 if (GET_CODE (op) == SUBREG)
983 if (!rtx_equal_function_value_matters)
984 /* We're building rtl. */
985 return GET_CODE (op) == MEM;
987 return (GET_CODE (op) == MEM
988 && EXTRA_CONSTRAINT (op, 'U'));
992 bit_memory_operand (op, mode)
994 enum machine_mode mode ATTRIBUTE_UNUSED;
996 return (GET_CODE (op) == MEM
997 && EXTRA_CONSTRAINT (op, 'U'));
1000 /* Handle machine specific pragmas for compatibility with existing
1001 compilers for the H8/300.
1003 pragma saveall generates prologue/epilogue code which saves and
1004 restores all the registers on function entry.
1006 pragma interrupt saves and restores all registers, and exits with
1007 an rte instruction rather than an rts. A pointer to a function
1008 with this attribute may be safely used in an interrupt vector. */
1011 h8300_pr_interrupt (pfile)
1012 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1014 pragma_interrupt = 1;
1018 h8300_pr_saveall (pfile)
1019 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1024 /* If the next function argument with MODE and TYPE is to be passed in
1025 a register, return a reg RTX for the hard register in which to pass
1026 the argument. CUM represents the state after the last argument.
1027 If the argument is to be pushed, NULL_RTX is returned. */
1030 function_arg (cum, mode, type, named)
1031 CUMULATIVE_ARGS *cum;
1032 enum machine_mode mode;
1036 static const char *const hand_list[] = {
1055 rtx result = NULL_RTX;
1059 /* Never pass unnamed arguments in registers. */
1063 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1064 if (TARGET_QUICKCALL)
1067 /* If calling hand written assembler, use 4 regs of args. */
1070 const char * const *p;
1072 fname = XSTR (cum->libcall, 0);
1074 /* See if this libcall is one of the hand coded ones. */
1075 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1086 if (mode == BLKmode)
1087 size = int_size_in_bytes (type);
1089 size = GET_MODE_SIZE (mode);
1091 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1092 && cum->nbytes / UNITS_PER_WORD <= 3)
1093 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1099 /* Return the cost of the rtx R with code CODE. */
1102 const_costs (r, c, outer_code)
1105 enum rtx_code outer_code;
1111 HOST_WIDE_INT n = INTVAL (r);
1113 if (-4 <= n || n <= 4)
1123 return 0 + (outer_code == SET);
1126 if (TARGET_H8300H || TARGET_H8300S)
1127 return 0 + (outer_code == SET);
1154 if (GET_MODE (x) == QImode)
1157 if (GET_MODE (x) != HImode
1158 && GET_MODE (x) != SImode)
1163 operands[2] = XEXP (x, 1);
1165 return compute_logical_op_length (GET_MODE (x), operands);
1169 h8300_shift_costs (x)
1174 if (GET_MODE (x) != QImode
1175 && GET_MODE (x) != HImode
1176 && GET_MODE (x) != SImode)
1181 operands[2] = XEXP (x, 1);
1183 return compute_a_shift_length (NULL, operands);
1187 h8300_rtx_costs (x, code, outer_code, total)
1189 int code, outer_code;
1195 *total = COSTS_N_INSNS (h8300_and_costs (x));
1198 /* We say that MOD and DIV are so expensive because otherwise we'll
1199 generate some really horrible code for division of a power of two. */
1212 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1217 if (GET_MODE (x) == HImode)
1224 *total = const_costs (x, code, outer_code);
1229 /* Documentation for the machine specific operand escapes:
1231 'E' like s but negative.
1232 'F' like t but negative.
1233 'G' constant just the negative
1234 'R' print operand as a byte:8 address if appropriate, else fall back to
1236 'S' print operand as a long word
1237 'T' print operand as a word
1238 'V' find the set bit, and print its number.
1239 'W' find the clear bit, and print its number.
1240 'X' print operand as a byte
1241 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1242 If this operand isn't a register, fall back to 'R' handling.
1244 'b' print the bit opcode
1245 'e' first word of 32 bit value - if reg, then least reg. if mem
1246 then least. if const then most sig word
1247 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1248 then +2. if const then least sig word
1249 'j' print operand as condition code.
1250 'k' print operand as reverse condition code.
1251 's' print as low byte of 16 bit value
1252 't' print as high byte of 16 bit value
1253 'w' print as low byte of 32 bit value
1254 'x' print as 2nd byte of 32 bit value
1255 'y' print as 3rd byte of 32 bit value
1256 'z' print as msb of 32 bit value
1259 /* Return assembly language string which identifies a comparison type. */
1292 /* Print operand X using operand code CODE to assembly language output file
1296 print_operand (file, x, code)
1301 /* This is used for communication between codes V,W,Z and Y. */
1307 switch (GET_CODE (x))
1310 fprintf (file, "%sl", names_big[REGNO (x)]);
1313 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1320 switch (GET_CODE (x))
1323 fprintf (file, "%sh", names_big[REGNO (x)]);
1326 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1333 if (GET_CODE (x) != CONST_INT)
1335 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1338 if (GET_CODE (x) == REG)
1339 fprintf (file, "%s", names_extended[REGNO (x)]);
1344 if (GET_CODE (x) == REG)
1345 fprintf (file, "%s", names_big[REGNO (x)]);
1350 bitint = exact_log2 (INTVAL (x) & 0xff);
1353 fprintf (file, "#%d", bitint);
1356 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1359 fprintf (file, "#%d", bitint);
1363 if (GET_CODE (x) == REG)
1364 fprintf (file, "%s", byte_reg (x, 0));
1371 if (GET_CODE (x) == REG)
1372 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1374 print_operand (file, x, 'R');
1378 bitint = INTVAL (x);
1379 fprintf (file, "#%d", bitint & 7);
1382 switch (GET_CODE (x))
1385 fprintf (file, "bor");
1388 fprintf (file, "bxor");
1391 fprintf (file, "band");
1398 switch (GET_CODE (x))
1402 fprintf (file, "%s", names_big[REGNO (x)]);
1404 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1407 print_operand (file, x, 0);
1410 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1416 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1417 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1418 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1427 switch (GET_CODE (x))
1431 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1433 fprintf (file, "%s", names_big[REGNO (x)]);
1436 x = adjust_address (x, HImode, 2);
1437 print_operand (file, x, 0);
1440 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1446 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1447 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1448 fprintf (file, "#%ld", (val & 0xffff));
1456 fputs (cond_string (GET_CODE (x)), file);
1459 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1462 if (GET_CODE (x) == CONST_INT)
1463 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1465 fprintf (file, "%s", byte_reg (x, 0));
1468 if (GET_CODE (x) == CONST_INT)
1469 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1471 fprintf (file, "%s", byte_reg (x, 1));
1474 if (GET_CODE (x) != CONST_INT)
1476 fprintf (file, "%ld", INTVAL (x));
1479 if (GET_CODE (x) == CONST_INT)
1480 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1482 fprintf (file, "%s",
1483 byte_reg (x, TARGET_H8300 ? 2 : 0));
1486 if (GET_CODE (x) == CONST_INT)
1487 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1489 fprintf (file, "%s",
1490 byte_reg (x, TARGET_H8300 ? 3 : 1));
1493 if (GET_CODE (x) == CONST_INT)
1494 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1496 fprintf (file, "%s", byte_reg (x, 0));
1499 if (GET_CODE (x) == CONST_INT)
1500 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1502 fprintf (file, "%s", byte_reg (x, 1));
1507 switch (GET_CODE (x))
1510 switch (GET_MODE (x))
1513 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1514 fprintf (file, "%s", byte_reg (x, 0));
1515 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1516 fprintf (file, "%s", names_big[REGNO (x)]);
1520 fprintf (file, "%s", names_big[REGNO (x)]);
1524 fprintf (file, "%s", names_extended[REGNO (x)]);
1533 rtx addr = XEXP (x, 0);
1535 fprintf (file, "@");
1536 output_address (addr);
1538 /* We fall back from smaller addressing to larger
1539 addressing in various ways depending on CODE. */
1543 /* Used for mov.b and bit operations. */
1544 if (h8300_eightbit_constant_address_p (addr))
1546 fprintf (file, ":8");
1550 /* Fall through. We should not get here if we are
1551 processing bit operations on H8/300 or H8/300H
1552 because 'U' constraint does not allow bit
1553 operations on the tiny area on these machines. */
1557 /* Used for mov.w and mov.l. */
1558 if (h8300_tiny_constant_address_p (addr))
1559 fprintf (file, ":16");
1571 fprintf (file, "#");
1572 print_operand_address (file, x);
1578 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1579 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1580 fprintf (file, "#%ld", val);
1589 /* Output assembly language output for the address ADDR to FILE. */
1592 print_operand_address (file, addr)
1596 switch (GET_CODE (addr))
1599 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1603 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1607 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1611 fprintf (file, "(");
1612 if (GET_CODE (XEXP (addr, 0)) == REG)
1615 print_operand_address (file, XEXP (addr, 1));
1616 fprintf (file, ",");
1617 print_operand_address (file, XEXP (addr, 0));
1622 print_operand_address (file, XEXP (addr, 0));
1623 fprintf (file, "+");
1624 print_operand_address (file, XEXP (addr, 1));
1626 fprintf (file, ")");
1631 /* Since the H8/300 only has 16 bit pointers, negative values are also
1632 those >= 32768. This happens for example with pointer minus a
1633 constant. We don't want to turn (char *p - 2) into
1634 (char *p + 65534) because loop unrolling can build upon this
1635 (IE: char *p + 131068). */
1636 int n = INTVAL (addr);
1638 n = (int) (short) n;
1639 fprintf (file, "%d", n);
1644 output_addr_const (file, addr);
1649 /* Output all insn addresses and their sizes into the assembly language
1650 output file. This is helpful for debugging whether the length attributes
1651 in the md file are correct. This is not meant to be a user selectable
1655 final_prescan_insn (insn, operand, num_operands)
1656 rtx insn, *operand ATTRIBUTE_UNUSED;
1657 int num_operands ATTRIBUTE_UNUSED;
1659 /* This holds the last insn address. */
1660 static int last_insn_address = 0;
1662 const int uid = INSN_UID (insn);
1664 if (TARGET_RTL_DUMP)
1666 fprintf (asm_out_file, "\n****************");
1667 print_rtl (asm_out_file, PATTERN (insn));
1668 fprintf (asm_out_file, "\n");
1671 if (TARGET_ADDRESSES)
1673 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1674 INSN_ADDRESSES (uid) - last_insn_address);
1675 last_insn_address = INSN_ADDRESSES (uid);
1679 /* Prepare for an SI sized move. */
1685 rtx src = operands[1];
1686 rtx dst = operands[0];
1687 if (!reload_in_progress && !reload_completed)
1689 if (!register_operand (dst, GET_MODE (dst)))
1691 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1692 emit_move_insn (tmp, src);
1699 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1700 Define the offset between two registers, one to be eliminated, and
1701 the other its replacement, at the start of a routine. */
1704 h8300_initial_elimination_offset (from, to)
1709 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1710 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1711 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1712 offset = frame_pointer_needed * UNITS_PER_WORD;
1717 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1718 if (WORD_REG_USED (regno))
1719 offset += UNITS_PER_WORD;
1721 /* See the comments for get_frame_size. We need to round it up to
1724 offset += round_frame_size (get_frame_size ());
1726 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1727 offset += UNITS_PER_WORD; /* Skip saved PC */
1730 if ((TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE)
1737 h8300_return_addr_rtx (count, frame)
1744 ret = gen_rtx_MEM (Pmode,
1745 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1746 else if (flag_omit_frame_pointer)
1749 ret = gen_rtx_MEM (Pmode,
1750 memory_address (Pmode,
1751 plus_constant (frame, UNITS_PER_WORD)));
1752 set_mem_alias_set (ret, get_frame_alias_set ());
1756 /* Update the condition code from the insn. */
1759 notice_update_cc (body, insn)
1765 switch (get_attr_cc (insn))
1768 /* Insn does not affect CC at all. */
1772 /* Insn does not change CC, but the 0'th operand has been changed. */
1773 if (cc_status.value1 != 0
1774 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1775 cc_status.value1 = 0;
1776 if (cc_status.value2 != 0
1777 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1778 cc_status.value2 = 0;
1782 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1783 The V flag is unusable. The C flag may or may not be known but
1784 that's ok because alter_cond will change tests to use EQ/NE. */
1786 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1787 set = single_set (insn);
1788 cc_status.value1 = SET_SRC (set);
1789 if (SET_DEST (set) != cc0_rtx)
1790 cc_status.value2 = SET_DEST (set);
1794 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1795 The C flag may or may not be known but that's ok because
1796 alter_cond will change tests to use EQ/NE. */
1798 cc_status.flags |= CC_NO_CARRY;
1799 set = single_set (insn);
1800 cc_status.value1 = SET_SRC (set);
1801 if (SET_DEST (set) != cc0_rtx)
1802 cc_status.value2 = SET_DEST (set);
1806 /* The insn is a compare instruction. */
1808 cc_status.value1 = SET_SRC (body);
1812 /* Insn doesn't leave CC in a usable state. */
1818 /* Return nonzero if X is a stack pointer. */
1821 stack_pointer_operand (x, mode)
1823 enum machine_mode mode ATTRIBUTE_UNUSED;
1825 return x == stack_pointer_rtx;
1828 /* Return nonzero if X is a constant whose absolute value is greater
1832 const_int_gt_2_operand (x, mode)
1834 enum machine_mode mode ATTRIBUTE_UNUSED;
1836 return (GET_CODE (x) == CONST_INT
1837 && abs (INTVAL (x)) > 2);
1840 /* Return nonzero if X is a constant whose absolute value is no
1844 const_int_ge_8_operand (x, mode)
1846 enum machine_mode mode ATTRIBUTE_UNUSED;
1848 return (GET_CODE (x) == CONST_INT
1849 && abs (INTVAL (x)) >= 8);
1852 /* Return nonzero if X is a constant expressible in QImode. */
1855 const_int_qi_operand (x, mode)
1857 enum machine_mode mode ATTRIBUTE_UNUSED;
1859 return (GET_CODE (x) == CONST_INT
1860 && (INTVAL (x) & 0xff) == INTVAL (x));
1863 /* Return nonzero if X is a constant expressible in HImode. */
1866 const_int_hi_operand (x, mode)
1868 enum machine_mode mode ATTRIBUTE_UNUSED;
1870 return (GET_CODE (x) == CONST_INT
1871 && (INTVAL (x) & 0xffff) == INTVAL (x));
1874 /* Return nonzero if X is a constant suitable for inc/dec. */
1877 incdec_operand (x, mode)
1879 enum machine_mode mode ATTRIBUTE_UNUSED;
1881 return (GET_CODE (x) == CONST_INT
1882 && (CONST_OK_FOR_M (INTVAL (x))
1883 || CONST_OK_FOR_O (INTVAL (x))));
1886 /* Return nonzero if X is either EQ or NE. */
1889 eqne_operator (x, mode)
1891 enum machine_mode mode ATTRIBUTE_UNUSED;
1893 enum rtx_code code = GET_CODE (x);
1895 return (code == EQ || code == NE);
1898 /* Return nonzero if X is either GTU or LEU. */
1901 gtuleu_operator (x, mode)
1903 enum machine_mode mode ATTRIBUTE_UNUSED;
1905 enum rtx_code code = GET_CODE (x);
1907 return (code == GTU || code == LEU);
1910 /* Recognize valid operators for bit instructions. */
1913 bit_operator (x, mode)
1915 enum machine_mode mode ATTRIBUTE_UNUSED;
1917 enum rtx_code code = GET_CODE (x);
1925 output_plussi (operands)
1928 enum machine_mode mode = GET_MODE (operands[0]);
1935 if (GET_CODE (operands[2]) == REG)
1936 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1938 if (GET_CODE (operands[2]) == CONST_INT)
1940 HOST_WIDE_INT n = INTVAL (operands[2]);
1942 if ((n & 0xffffff) == 0)
1943 return "add\t%z2,%z0";
1944 if ((n & 0xffff) == 0)
1945 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
1946 if ((n & 0xff) == 0)
1947 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1950 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1954 if (GET_CODE (operands[2]) == REG)
1955 return "add.l\t%S2,%S0";
1957 if (GET_CODE (operands[2]) == CONST_INT)
1959 HOST_WIDE_INT intval = INTVAL (operands[2]);
1961 /* See if we can finish with 2 bytes. */
1963 switch ((unsigned int) intval & 0xffffffff)
1968 return "adds\t%2,%S0";
1973 return "subs\t%G2,%S0";
1977 operands[2] = GEN_INT (intval >> 16);
1978 return "inc.w\t%2,%e0";
1982 operands[2] = GEN_INT (intval >> 16);
1983 return "dec.w\t%G2,%e0";
1986 /* See if we can finish with 4 bytes. */
1987 if ((intval & 0xffff) == 0)
1989 operands[2] = GEN_INT (intval >> 16);
1990 return "add.w\t%2,%e0";
1994 return "add.l\t%S2,%S0";
1999 compute_plussi_length (operands)
2002 enum machine_mode mode = GET_MODE (operands[0]);
2009 if (GET_CODE (operands[2]) == REG)
2012 if (GET_CODE (operands[2]) == CONST_INT)
2014 HOST_WIDE_INT n = INTVAL (operands[2]);
2016 if ((n & 0xffffff) == 0)
2018 if ((n & 0xffff) == 0)
2020 if ((n & 0xff) == 0)
2028 if (GET_CODE (operands[2]) == REG)
2031 if (GET_CODE (operands[2]) == CONST_INT)
2033 HOST_WIDE_INT intval = INTVAL (operands[2]);
2035 /* See if we can finish with 2 bytes. */
2037 switch ((unsigned int) intval & 0xffffffff)
2058 /* See if we can finish with 4 bytes. */
2059 if ((intval & 0xffff) == 0)
2068 compute_plussi_cc (operands)
2071 enum machine_mode mode = GET_MODE (operands[0]);
2082 if (GET_CODE (operands[2]) == REG)
2085 if (GET_CODE (operands[2]) == CONST_INT)
2087 HOST_WIDE_INT intval = INTVAL (operands[2]);
2089 /* See if we can finish with 2 bytes. */
2091 switch ((unsigned int) intval & 0xffffffff)
2096 return CC_NONE_0HIT;
2101 return CC_NONE_0HIT;
2112 /* See if we can finish with 4 bytes. */
2113 if ((intval & 0xffff) == 0)
2122 output_logical_op (mode, operands)
2123 enum machine_mode mode;
2126 /* Figure out the logical op that we need to perform. */
2127 enum rtx_code code = GET_CODE (operands[3]);
2128 /* Pretend that every byte is affected if both operands are registers. */
2129 const unsigned HOST_WIDE_INT intval =
2130 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2131 ? INTVAL (operands[2]) : 0x55555555);
2132 /* The determinant of the algorithm. If we perform an AND, 0
2133 affects a bit. Otherwise, 1 affects a bit. */
2134 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2135 /* Break up DET into pieces. */
2136 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2137 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2138 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2139 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2140 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2141 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2142 int lower_half_easy_p = 0;
2143 int upper_half_easy_p = 0;
2144 /* The name of an insn. */
2166 /* First, see if we can finish with one insn. */
2167 if ((TARGET_H8300H || TARGET_H8300S)
2171 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2172 output_asm_insn (insn_buf, operands);
2176 /* Take care of the lower byte. */
2179 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2180 output_asm_insn (insn_buf, operands);
2182 /* Take care of the upper byte. */
2185 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2186 output_asm_insn (insn_buf, operands);
2191 if (TARGET_H8300H || TARGET_H8300S)
2193 /* Determine if the lower half can be taken care of in no more
2195 lower_half_easy_p = (b0 == 0
2197 || (code != IOR && w0 == 0xffff));
2199 /* Determine if the upper half can be taken care of in no more
2201 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2202 || (code == AND && w1 == 0xff00));
2205 /* Check if doing everything with one insn is no worse than
2206 using multiple insns. */
2207 if ((TARGET_H8300H || TARGET_H8300S)
2208 && w0 != 0 && w1 != 0
2209 && !(lower_half_easy_p && upper_half_easy_p))
2211 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2212 output_asm_insn (insn_buf, operands);
2216 /* Take care of the lower and upper words individually. For
2217 each word, we try different methods in the order of
2219 1) the special insn (in case of AND or XOR),
2220 2) the word-wise insn, and
2221 3) The byte-wise insn. */
2223 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2224 output_asm_insn ((code == AND)
2225 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2227 else if ((TARGET_H8300H || TARGET_H8300S)
2231 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2232 output_asm_insn (insn_buf, operands);
2238 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2239 output_asm_insn (insn_buf, operands);
2243 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2244 output_asm_insn (insn_buf, operands);
2249 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2250 output_asm_insn ((code == AND)
2251 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2253 else if ((TARGET_H8300H || TARGET_H8300S)
2257 output_asm_insn ("extu.w\t%e0", operands);
2259 else if (TARGET_H8300H || TARGET_H8300S)
2263 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2264 output_asm_insn (insn_buf, operands);
2271 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2272 output_asm_insn (insn_buf, operands);
2276 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2277 output_asm_insn (insn_buf, operands);
2289 compute_logical_op_length (mode, operands)
2290 enum machine_mode mode;
2293 /* Figure out the logical op that we need to perform. */
2294 enum rtx_code code = GET_CODE (operands[3]);
2295 /* Pretend that every byte is affected if both operands are registers. */
2296 const unsigned HOST_WIDE_INT intval =
2297 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2298 ? INTVAL (operands[2]) : 0x55555555);
2299 /* The determinant of the algorithm. If we perform an AND, 0
2300 affects a bit. Otherwise, 1 affects a bit. */
2301 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2302 /* Break up DET into pieces. */
2303 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2304 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2305 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2306 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2307 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2308 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2309 int lower_half_easy_p = 0;
2310 int upper_half_easy_p = 0;
2312 unsigned int length = 0;
2317 /* First, see if we can finish with one insn. */
2318 if ((TARGET_H8300H || TARGET_H8300S)
2322 if (REG_P (operands[2]))
2329 /* Take care of the lower byte. */
2333 /* Take care of the upper byte. */
2339 if (TARGET_H8300H || TARGET_H8300S)
2341 /* Determine if the lower half can be taken care of in no more
2343 lower_half_easy_p = (b0 == 0
2345 || (code != IOR && w0 == 0xffff));
2347 /* Determine if the upper half can be taken care of in no more
2349 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2350 || (code == AND && w1 == 0xff00));
2353 /* Check if doing everything with one insn is no worse than
2354 using multiple insns. */
2355 if ((TARGET_H8300H || TARGET_H8300S)
2356 && w0 != 0 && w1 != 0
2357 && !(lower_half_easy_p && upper_half_easy_p))
2359 if (REG_P (operands[2]))
2366 /* Take care of the lower and upper words individually. For
2367 each word, we try different methods in the order of
2369 1) the special insn (in case of AND or XOR),
2370 2) the word-wise insn, and
2371 3) The byte-wise insn. */
2373 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2377 else if ((TARGET_H8300H || TARGET_H8300S)
2393 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2397 else if ((TARGET_H8300H || TARGET_H8300S)
2403 else if (TARGET_H8300H || TARGET_H8300S)
2425 compute_logical_op_cc (mode, operands)
2426 enum machine_mode mode;
2429 /* Figure out the logical op that we need to perform. */
2430 enum rtx_code code = GET_CODE (operands[3]);
2431 /* Pretend that every byte is affected if both operands are registers. */
2432 const unsigned HOST_WIDE_INT intval =
2433 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2434 ? INTVAL (operands[2]) : 0x55555555);
2435 /* The determinant of the algorithm. If we perform an AND, 0
2436 affects a bit. Otherwise, 1 affects a bit. */
2437 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2438 /* Break up DET into pieces. */
2439 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2440 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2441 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2442 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2443 int lower_half_easy_p = 0;
2444 int upper_half_easy_p = 0;
2445 /* Condition code. */
2446 enum attr_cc cc = CC_CLOBBER;
2451 /* First, see if we can finish with one insn. */
2452 if ((TARGET_H8300H || TARGET_H8300S)
2460 if (TARGET_H8300H || TARGET_H8300S)
2462 /* Determine if the lower half can be taken care of in no more
2464 lower_half_easy_p = (b0 == 0
2466 || (code != IOR && w0 == 0xffff));
2468 /* Determine if the upper half can be taken care of in no more
2470 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2471 || (code == AND && w1 == 0xff00));
2474 /* Check if doing everything with one insn is no worse than
2475 using multiple insns. */
2476 if ((TARGET_H8300H || TARGET_H8300S)
2477 && w0 != 0 && w1 != 0
2478 && !(lower_half_easy_p && upper_half_easy_p))
2491 We devote a fair bit of code to getting efficient shifts since we
2492 can only shift one bit at a time on the H8/300 and H8/300H and only
2493 one or two bits at a time on the H8S.
2495 All shift code falls into one of the following ways of
2498 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2499 when a straight line shift is about the same size or smaller than
2502 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2503 off the bits we don't need. This is used when only a few of the
2504 bits in the original value will survive in the shifted value.
2506 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2507 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2508 shifts can be added if the shift count is slightly more than 8 or
2509 16. This case also includes other oddballs that are not worth
2512 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2514 For each shift count, we try to use code that has no trade-off
2515 between code size and speed whenever possible.
2517 If the trade-off is unavoidable, we try to be reasonable.
2518 Specifically, the fastest version is one instruction longer than
2519 the shortest version, we take the fastest version. We also provide
2520 the use a way to switch back to the shortest version with -Os.
2522 For the details of the shift algorithms for various shift counts,
2523 refer to shift_alg_[qhs]i. */
2526 nshift_operator (x, mode)
2528 enum machine_mode mode ATTRIBUTE_UNUSED;
2530 switch (GET_CODE (x))
2542 /* Emit code to do shifts. */
2545 expand_a_shift (mode, code, operands)
2546 enum machine_mode mode;
2550 emit_move_insn (operands[0], operands[1]);
2552 /* Need a loop to get all the bits we want - we generate the
2553 code at emit time, but need to allocate a scratch reg now. */
2555 emit_insn (gen_rtx_PARALLEL
2558 gen_rtx_SET (VOIDmode, operands[0],
2559 gen_rtx (code, mode, operands[0],
2561 gen_rtx_CLOBBER (VOIDmode,
2562 gen_rtx_SCRATCH (QImode)))));
2565 /* Symbols of the various modes which can be used as indices. */
2569 QIshift, HIshift, SIshift
2572 /* For single bit shift insns, record assembler and what bits of the
2573 condition code are valid afterwards (represented as various CC_FOO
2574 bits, 0 means CC isn't left in a usable state). */
2578 const char *const assembler;
2582 /* Assembler instruction shift table.
2584 These tables are used to look up the basic shifts.
2585 They are indexed by cpu, shift_type, and mode. */
2587 static const struct shift_insn shift_one[2][3][3] =
2593 { "shll\t%X0", CC_NO_CARRY },
2594 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2595 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
2597 /* SHIFT_LSHIFTRT */
2599 { "shlr\t%X0", CC_NO_CARRY },
2600 { "shlr\t%t0\n\trotxr\t%s0", 0 },
2601 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2603 /* SHIFT_ASHIFTRT */
2605 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2606 { "shar\t%t0\n\trotxr\t%s0", 0 },
2607 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2614 { "shll.b\t%X0", CC_NO_CARRY },
2615 { "shll.w\t%T0", CC_NO_CARRY },
2616 { "shll.l\t%S0", CC_NO_CARRY }
2618 /* SHIFT_LSHIFTRT */
2620 { "shlr.b\t%X0", CC_NO_CARRY },
2621 { "shlr.w\t%T0", CC_NO_CARRY },
2622 { "shlr.l\t%S0", CC_NO_CARRY }
2624 /* SHIFT_ASHIFTRT */
2626 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2627 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2628 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2633 static const struct shift_insn shift_two[3][3] =
2637 { "shll.b\t#2,%X0", CC_NO_CARRY },
2638 { "shll.w\t#2,%T0", CC_NO_CARRY },
2639 { "shll.l\t#2,%S0", CC_NO_CARRY }
2641 /* SHIFT_LSHIFTRT */
2643 { "shlr.b\t#2,%X0", CC_NO_CARRY },
2644 { "shlr.w\t#2,%T0", CC_NO_CARRY },
2645 { "shlr.l\t#2,%S0", CC_NO_CARRY }
2647 /* SHIFT_ASHIFTRT */
2649 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2650 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2651 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2655 /* Rotates are organized by which shift they'll be used in implementing.
2656 There's no need to record whether the cc is valid afterwards because
2657 it is the AND insn that will decide this. */
2659 static const char *const rotate_one[2][3][3] =
2666 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2669 /* SHIFT_LSHIFTRT */
2672 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2675 /* SHIFT_ASHIFTRT */
2678 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2690 /* SHIFT_LSHIFTRT */
2696 /* SHIFT_ASHIFTRT */
2705 static const char *const rotate_two[3][3] =
2713 /* SHIFT_LSHIFTRT */
2719 /* SHIFT_ASHIFTRT */
2728 /* Shift algorithm. */
2731 /* The number of bits to be shifted by shift1 and shift2. Valid
2732 when ALG is SHIFT_SPECIAL. */
2733 unsigned int remainder;
2735 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2736 const char *special;
2738 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2739 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2742 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2743 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2746 /* Valid CC flags. */
2750 static void get_shift_alg PARAMS ((enum shift_type,
2751 enum shift_mode, unsigned int,
2752 struct shift_info *));
2754 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2755 best algorithm for doing the shift. The assembler code is stored
2756 in the pointers in INFO. We achieve the maximum efficiency in most
2757 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2758 SImode in particular have a lot of room to optimize.
2760 We first determine the strategy of the shift algorithm by a table
2761 lookup. If that tells us to use a hand crafted assembly code, we
2762 go into the big switch statement to find what that is. Otherwise,
2763 we resort to a generic way, such as inlining. In either case, the
2764 result is returned through INFO. */
2767 get_shift_alg (shift_type, shift_mode, count, info)
2768 enum shift_type shift_type;
2769 enum shift_mode shift_mode;
2771 struct shift_info *info;
2775 /* Find the target CPU. */
2778 else if (TARGET_H8300H)
2783 /* Find the shift algorithm. */
2784 info->alg = SHIFT_LOOP;
2788 if (count < GET_MODE_BITSIZE (QImode))
2789 info->alg = shift_alg_qi[cpu][shift_type][count];
2793 if (count < GET_MODE_BITSIZE (HImode))
2794 info->alg = shift_alg_hi[cpu][shift_type][count];
2798 if (count < GET_MODE_BITSIZE (SImode))
2799 info->alg = shift_alg_si[cpu][shift_type][count];
2806 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2810 info->remainder = count;
2814 /* It is up to the caller to know that looping clobbers cc. */
2815 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2816 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2817 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2821 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2822 info->shift2 = rotate_two[shift_type][shift_mode];
2823 info->cc_valid_p = 0;
2827 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2828 info->remainder = 0;
2829 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2830 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2831 info->cc_valid_p = 0;
2835 /* Here we only deal with SHIFT_SPECIAL. */
2839 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2840 through the entire value. */
2841 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2843 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2855 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2857 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2859 case SHIFT_LSHIFTRT:
2861 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2863 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2865 case SHIFT_ASHIFTRT:
2866 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2870 else if ((8 <= count && count <= 13)
2871 || (TARGET_H8300S && count == 14))
2873 info->remainder = count - 8;
2878 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2880 case SHIFT_LSHIFTRT:
2883 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2884 info->shift1 = "shlr.b\t%s0";
2888 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
2891 case SHIFT_ASHIFTRT:
2894 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2895 info->shift1 = "shar.b\t%s0";
2899 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2904 else if (count == 14)
2910 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2912 case SHIFT_LSHIFTRT:
2914 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2916 case SHIFT_ASHIFTRT:
2918 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2919 else if (TARGET_H8300H)
2920 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2921 else /* TARGET_H8300S */
2926 else if (count == 15)
2931 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
2933 case SHIFT_LSHIFTRT:
2934 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
2936 case SHIFT_ASHIFTRT:
2937 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2944 if (TARGET_H8300 && 8 <= count && count <= 9)
2946 info->remainder = count - 8;
2951 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2953 case SHIFT_LSHIFTRT:
2954 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2955 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
2957 case SHIFT_ASHIFTRT:
2958 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2962 else if (count == 8 && !TARGET_H8300)
2967 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2969 case SHIFT_LSHIFTRT:
2970 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2972 case SHIFT_ASHIFTRT:
2973 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2977 else if (count == 15 && TARGET_H8300)
2983 case SHIFT_LSHIFTRT:
2984 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\trotxl\t%y0,%y0";
2986 case SHIFT_ASHIFTRT:
2987 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
2991 else if (count == 15 && !TARGET_H8300)
2996 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
2998 case SHIFT_LSHIFTRT:
2999 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3001 case SHIFT_ASHIFTRT:
3005 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3006 || (TARGET_H8300H && 16 <= count && count <= 19)
3007 || (TARGET_H8300S && 16 <= count && count <= 21))
3009 info->remainder = count - 16;
3014 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3016 info->shift1 = "add.w\t%e0,%e0";
3018 case SHIFT_LSHIFTRT:
3021 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3022 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3026 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3029 case SHIFT_ASHIFTRT:
3032 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3033 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3037 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3042 else if (TARGET_H8300 && 24 <= count && count <= 28)
3044 info->remainder = count - 24;
3049 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3050 info->shift1 = "shll.b\t%z0";
3052 case SHIFT_LSHIFTRT:
3053 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3054 info->shift1 = "shlr.b\t%w0";
3056 case SHIFT_ASHIFTRT:
3057 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3058 info->shift1 = "shar.b\t%w0";
3062 else if ((TARGET_H8300H && count == 24)
3063 || (TARGET_H8300S && 24 <= count && count <= 25))
3065 info->remainder = count - 24;
3070 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3072 case SHIFT_LSHIFTRT:
3073 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3075 case SHIFT_ASHIFTRT:
3076 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3080 else if (!TARGET_H8300 && count == 28)
3086 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3088 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3090 case SHIFT_LSHIFTRT:
3092 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3094 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3096 case SHIFT_ASHIFTRT:
3100 else if (!TARGET_H8300 && count == 29)
3106 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3108 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3110 case SHIFT_LSHIFTRT:
3112 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3114 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3116 case SHIFT_ASHIFTRT:
3120 else if (!TARGET_H8300 && count == 30)
3126 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3128 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3130 case SHIFT_LSHIFTRT:
3132 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3134 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3136 case SHIFT_ASHIFTRT:
3140 else if (count == 31)
3147 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3149 case SHIFT_LSHIFTRT:
3150 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3152 case SHIFT_ASHIFTRT:
3153 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3162 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3164 case SHIFT_LSHIFTRT:
3165 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3167 case SHIFT_ASHIFTRT:
3168 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3181 info->shift2 = NULL;
3184 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3185 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3188 h8300_shift_needs_scratch_p (count, mode)
3190 enum machine_mode mode;
3195 if (GET_MODE_BITSIZE (mode) <= count)
3198 /* Find out the target CPU. */
3201 else if (TARGET_H8300H)
3206 /* Find the shift algorithm. */
3210 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3211 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3212 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3216 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3217 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3218 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3222 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3223 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3224 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3231 /* On H8/300H, count == 8 uses a scratch register. */
3232 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3233 || (TARGET_H8300H && mode == SImode && count == 8));
3236 /* Emit the assembler code for doing shifts. */
3239 output_a_shift (operands)
3242 static int loopend_lab;
3243 rtx shift = operands[3];
3244 enum machine_mode mode = GET_MODE (shift);
3245 enum rtx_code code = GET_CODE (shift);
3246 enum shift_type shift_type;
3247 enum shift_mode shift_mode;
3248 struct shift_info info;
3255 shift_mode = QIshift;
3258 shift_mode = HIshift;
3261 shift_mode = SIshift;
3270 shift_type = SHIFT_ASHIFTRT;
3273 shift_type = SHIFT_LSHIFTRT;
3276 shift_type = SHIFT_ASHIFT;
3282 if (GET_CODE (operands[2]) != CONST_INT)
3284 /* This case must be taken care of by one of the two splitters
3285 that convert a variable shift into a loop. */
3290 int n = INTVAL (operands[2]);
3292 /* If the count is negative, make it 0. */
3295 /* If the count is too big, truncate it.
3296 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3297 do the intuitive thing. */
3298 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3299 n = GET_MODE_BITSIZE (mode);
3301 get_shift_alg (shift_type, shift_mode, n, &info);
3306 output_asm_insn (info.special, operands);
3312 /* Emit two bit shifts first. */
3313 if (info.shift2 != NULL)
3315 for (; n > 1; n -= 2)
3316 output_asm_insn (info.shift2, operands);
3319 /* Now emit one bit shifts for any residual. */
3321 output_asm_insn (info.shift1, operands);
3323 /* Keep track of CC. */
3324 if (info.cc_valid_p)
3326 cc_status.value1 = operands[0];
3327 cc_status.flags |= info.cc_valid_p;
3333 int m = GET_MODE_BITSIZE (mode) - n;
3334 const int mask = (shift_type == SHIFT_ASHIFT
3335 ? ((1 << m) - 1) << n
3339 /* Not all possibilities of rotate are supported. They shouldn't
3340 be generated, but let's watch for 'em. */
3341 if (info.shift1 == 0)
3344 /* Emit two bit rotates first. */
3345 if (info.shift2 != NULL)
3347 for (; m > 1; m -= 2)
3348 output_asm_insn (info.shift2, operands);
3351 /* Now single bit rotates for any residual. */
3353 output_asm_insn (info.shift1, operands);
3355 /* Now mask off the high bits. */
3357 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3358 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3359 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3363 cc_status.value1 = operands[0];
3364 cc_status.flags |= CC_NO_CARRY;
3365 output_asm_insn (insn_buf, operands);
3370 /* A loop to shift by a "large" constant value.
3371 If we have shift-by-2 insns, use them. */
3372 if (info.shift2 != NULL)
3374 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3375 names_big[REGNO (operands[4])]);
3376 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3377 output_asm_insn (info.shift2, operands);
3378 output_asm_insn ("add #0xff,%X4", operands);
3379 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3381 output_asm_insn (info.shift1, operands);
3385 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3386 names_big[REGNO (operands[4])]);
3387 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3388 output_asm_insn (info.shift1, operands);
3389 output_asm_insn ("add #0xff,%X4", operands);
3390 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3401 h8300_asm_insn_count (template)
3402 const char *template;
3404 unsigned int count = 1;
3406 for (; *template; template++)
3407 if (*template == '\n')
3414 compute_a_shift_length (insn, operands)
3415 rtx insn ATTRIBUTE_UNUSED;
3418 rtx shift = operands[3];
3419 enum machine_mode mode = GET_MODE (shift);
3420 enum rtx_code code = GET_CODE (shift);
3421 enum shift_type shift_type;
3422 enum shift_mode shift_mode;
3423 struct shift_info info;
3424 unsigned int wlength = 0;
3429 shift_mode = QIshift;
3432 shift_mode = HIshift;
3435 shift_mode = SIshift;
3444 shift_type = SHIFT_ASHIFTRT;
3447 shift_type = SHIFT_LSHIFTRT;
3450 shift_type = SHIFT_ASHIFT;
3456 if (GET_CODE (operands[2]) != CONST_INT)
3458 /* Get the assembler code to do one shift. */
3459 get_shift_alg (shift_type, shift_mode, 1, &info);
3461 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3465 int n = INTVAL (operands[2]);
3467 /* If the count is negative, make it 0. */
3470 /* If the count is too big, truncate it.
3471 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3472 do the intuitive thing. */
3473 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3474 n = GET_MODE_BITSIZE (mode);
3476 get_shift_alg (shift_type, shift_mode, n, &info);
3481 wlength += h8300_asm_insn_count (info.special);
3483 /* Every assembly instruction used in SHIFT_SPECIAL case
3484 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3485 see xor.l, we just pretend that xor.l counts as two insns
3486 so that the insn length will be computed correctly. */
3487 if (strstr (info.special, "xor.l") != NULL)
3495 if (info.shift2 != NULL)
3497 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3501 wlength += h8300_asm_insn_count (info.shift1) * n;
3507 int m = GET_MODE_BITSIZE (mode) - n;
3509 /* Not all possibilities of rotate are supported. They shouldn't
3510 be generated, but let's watch for 'em. */
3511 if (info.shift1 == 0)
3514 if (info.shift2 != NULL)
3516 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3520 wlength += h8300_asm_insn_count (info.shift1) * m;
3522 /* Now mask off the high bits. */
3543 /* A loop to shift by a "large" constant value.
3544 If we have shift-by-2 insns, use them. */
3545 if (info.shift2 != NULL)
3547 wlength += 3 + h8300_asm_insn_count (info.shift2);
3549 wlength += h8300_asm_insn_count (info.shift1);
3553 wlength += 3 + h8300_asm_insn_count (info.shift1);
3563 /* A rotation by a non-constant will cause a loop to be generated, in
3564 which a rotation by one bit is used. A rotation by a constant,
3565 including the one in the loop, will be taken care of by
3566 emit_a_rotate () at the insn emit time. */
3569 expand_a_rotate (code, operands)
3573 rtx dst = operands[0];
3574 rtx src = operands[1];
3575 rtx rotate_amount = operands[2];
3576 enum machine_mode mode = GET_MODE (dst);
3579 /* We rotate in place. */
3580 emit_move_insn (dst, src);
3582 if (GET_CODE (rotate_amount) != CONST_INT)
3584 rtx counter = gen_reg_rtx (QImode);
3585 rtx start_label = gen_label_rtx ();
3586 rtx end_label = gen_label_rtx ();
3588 /* If the rotate amount is less than or equal to 0,
3589 we go out of the loop. */
3590 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3591 QImode, 0, end_label);
3593 /* Initialize the loop counter. */
3594 emit_move_insn (counter, rotate_amount);
3596 emit_label (start_label);
3598 /* Rotate by one bit. */
3599 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3600 emit_insn (gen_rtx_SET (mode, dst, tmp));
3602 /* Decrement the counter by 1. */
3603 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3604 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3606 /* If the loop counter is nonzero, we go back to the beginning
3608 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3611 emit_label (end_label);
3615 /* Rotate by AMOUNT bits. */
3616 tmp = gen_rtx (code, mode, dst, rotate_amount);
3617 emit_insn (gen_rtx_SET (mode, dst, tmp));
3623 /* Emit rotate insns. */
3626 emit_a_rotate (code, operands)
3630 rtx dst = operands[0];
3631 rtx rotate_amount = operands[2];
3632 enum shift_mode rotate_mode;
3633 enum shift_type rotate_type;
3634 const char *insn_buf;
3637 enum machine_mode mode = GET_MODE (dst);
3639 if (GET_CODE (rotate_amount) != CONST_INT)
3645 rotate_mode = QIshift;
3648 rotate_mode = HIshift;
3651 rotate_mode = SIshift;
3660 rotate_type = SHIFT_ASHIFT;
3663 rotate_type = SHIFT_LSHIFTRT;
3669 amount = INTVAL (rotate_amount);
3671 /* Clean up AMOUNT. */
3674 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3675 amount = GET_MODE_BITSIZE (mode);
3677 /* Determine the faster direction. After this phase, amount will be
3678 at most a half of GET_MODE_BITSIZE (mode). */
3679 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3681 /* Flip the direction. */
3682 amount = GET_MODE_BITSIZE (mode) - amount;
3684 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3687 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3688 boost up the rotation. */
3689 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3690 || (mode == HImode && TARGET_H8300H && amount >= 6)
3691 || (mode == HImode && TARGET_H8300S && amount == 8)
3692 || (mode == SImode && TARGET_H8300H && amount >= 10)
3693 || (mode == SImode && TARGET_H8300S && amount >= 13))
3698 /* This code works on any family. */
3699 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3700 output_asm_insn (insn_buf, operands);
3704 /* This code works on the H8/300H and H8S. */
3705 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3706 output_asm_insn (insn_buf, operands);
3713 /* Adjust AMOUNT and flip the direction. */
3714 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3716 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3719 /* Emit rotate insns. */
3720 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3723 insn_buf = rotate_two[rotate_type][rotate_mode];
3725 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3727 for (; amount >= bits; amount -= bits)
3728 output_asm_insn (insn_buf, operands);
3734 /* Fix the operands of a gen_xxx so that it could become a bit
3738 fix_bit_operand (operands, what, type)
3743 /* The bit_operand predicate accepts any memory during RTL generation, but
3744 only 'U' memory afterwards, so if this is a MEM operand, we must force
3745 it to be valid for 'U' by reloading the address. */
3747 if ((what == 0 && single_zero_operand (operands[2], QImode))
3748 || (what == 1 && single_one_operand (operands[2], QImode)))
3750 /* OK to have a memory dest. */
3751 if (GET_CODE (operands[0]) == MEM
3752 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3754 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3755 copy_to_mode_reg (Pmode,
3756 XEXP (operands[0], 0)));
3757 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3761 if (GET_CODE (operands[1]) == MEM
3762 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3764 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3765 copy_to_mode_reg (Pmode,
3766 XEXP (operands[1], 0)));
3767 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3773 /* Dest and src op must be register. */
3775 operands[1] = force_reg (QImode, operands[1]);
3777 rtx res = gen_reg_rtx (QImode);
3778 emit_insn (gen_rtx_SET (VOIDmode, res,
3779 gen_rtx (type, QImode, operands[1], operands[2])));
3780 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3785 /* Return nonzero if FUNC is an interrupt function as specified
3786 by the "interrupt" attribute. */
3789 h8300_interrupt_function_p (func)
3794 if (TREE_CODE (func) != FUNCTION_DECL)
3797 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3798 return a != NULL_TREE;
3801 /* Return nonzero if FUNC is an OS_Task function as specified
3802 by the "OS_Task" attribute. */
3805 h8300_os_task_function_p (func)
3810 if (TREE_CODE (func) != FUNCTION_DECL)
3813 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3814 return a != NULL_TREE;
3817 /* Return nonzero if FUNC is a monitor function as specified
3818 by the "monitor" attribute. */
3821 h8300_monitor_function_p (func)
3826 if (TREE_CODE (func) != FUNCTION_DECL)
3829 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
3830 return a != NULL_TREE;
3833 /* Return nonzero if FUNC is a function that should be called
3834 through the function vector. */
3837 h8300_funcvec_function_p (func)
3842 if (TREE_CODE (func) != FUNCTION_DECL)
3845 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
3846 return a != NULL_TREE;
3849 /* Return nonzero if DECL is a variable that's in the eight bit
3853 h8300_eightbit_data_p (decl)
3858 if (TREE_CODE (decl) != VAR_DECL)
3861 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
3862 return a != NULL_TREE;
3865 /* Return nonzero if DECL is a variable that's in the tiny
3869 h8300_tiny_data_p (decl)
3874 if (TREE_CODE (decl) != VAR_DECL)
3877 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
3878 return a != NULL_TREE;
3881 /* Generate an 'interrupt_handler' attribute for decls. */
3884 h8300_insert_attributes (node, attributes)
3888 if (!pragma_interrupt
3889 || TREE_CODE (node) != FUNCTION_DECL)
3892 pragma_interrupt = 0;
3894 /* Add an 'interrupt_handler' attribute. */
3895 *attributes = tree_cons (get_identifier ("interrupt_handler"),
3899 /* Supported attributes:
3901 interrupt_handler: output a prologue and epilogue suitable for an
3904 function_vector: This function should be called through the
3907 eightbit_data: This variable lives in the 8-bit data area and can
3908 be referenced with 8-bit absolute memory addresses.
3910 tiny_data: This variable lives in the tiny data area and can be
3911 referenced with 16-bit absolute memory references. */
3913 const struct attribute_spec h8300_attribute_table[] =
3915 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3916 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3917 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3918 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3919 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3920 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
3921 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
3922 { NULL, 0, 0, false, false, false, NULL }
3926 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
3927 struct attribute_spec.handler. */
3929 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
3932 tree args ATTRIBUTE_UNUSED;
3933 int flags ATTRIBUTE_UNUSED;
3936 if (TREE_CODE (*node) != FUNCTION_DECL)
3938 warning ("`%s' attribute only applies to functions",
3939 IDENTIFIER_POINTER (name));
3940 *no_add_attrs = true;
3946 /* Handle an "eightbit_data" attribute; arguments as in
3947 struct attribute_spec.handler. */
3949 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
3952 tree args ATTRIBUTE_UNUSED;
3953 int flags ATTRIBUTE_UNUSED;
3958 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3960 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3964 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3965 *no_add_attrs = true;
3971 /* Handle an "tiny_data" attribute; arguments as in
3972 struct attribute_spec.handler. */
3974 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
3977 tree args ATTRIBUTE_UNUSED;
3978 int flags ATTRIBUTE_UNUSED;
3983 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3985 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3989 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3990 *no_add_attrs = true;
3997 h8300_encode_label (decl)
4000 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
4001 const int len = strlen (str);
4002 char *newstr = alloca (len + 2);
4005 strcpy (&newstr[1], str);
4007 XSTR (XEXP (DECL_RTL (decl), 0), 0) =
4008 ggc_alloc_string (newstr, len + 1);
4011 /* If we are referencing a function that is supposed to be called
4012 through the function vector, the SYMBOL_REF_FLAG in the rtl
4013 so the call patterns can generate the correct code. */
4016 h8300_encode_section_info (decl, first)
4020 if (TREE_CODE (decl) == FUNCTION_DECL
4021 && h8300_funcvec_function_p (decl))
4022 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
4023 else if (TREE_CODE (decl) == VAR_DECL
4024 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4026 if (h8300_eightbit_data_p (decl))
4027 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
4028 else if (first && h8300_tiny_data_p (decl))
4029 h8300_encode_label (decl);
4033 /* Undo the effects of the above. */
4036 h8300_strip_name_encoding (str)
4039 return str + (*str == '*' || *str == '@' || *str == '&');
4043 output_simode_bld (bild, operands)
4049 /* Clear the destination register. */
4050 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4052 /* Now output the bit load or bit inverse load, and store it in
4055 output_asm_insn ("bild\t%Z2,%Y1", operands);
4057 output_asm_insn ("bld\t%Z2,%Y1", operands);
4059 output_asm_insn ("bst\t#0,%w0", operands);
4063 /* Output the bit load or bit inverse load. */
4065 output_asm_insn ("bild\t%Z2,%Y1", operands);
4067 output_asm_insn ("bld\t%Z2,%Y1", operands);
4069 /* Clear the destination register and perform the bit store. */
4070 output_asm_insn ("xor.l\t%S0,%S0\n\tbst\t#0,%w0", operands);
4077 /* Given INSN and its current length LENGTH, return the adjustment
4078 (in bytes) to correctly compute INSN's length.
4080 We use this to get the lengths of various memory references correct. */
4083 h8300_adjust_insn_length (insn, length)
4085 int length ATTRIBUTE_UNUSED;
4087 rtx pat = PATTERN (insn);
4089 /* We must filter these out before calling get_attr_adjust_length. */
4090 if (GET_CODE (pat) == USE
4091 || GET_CODE (pat) == CLOBBER
4092 || GET_CODE (pat) == SEQUENCE
4093 || GET_CODE (pat) == ADDR_VEC
4094 || GET_CODE (pat) == ADDR_DIFF_VEC)
4097 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
4100 /* Adjust length for reg->mem and mem->reg copies. */
4101 if (GET_CODE (pat) == SET
4102 && (GET_CODE (SET_SRC (pat)) == MEM
4103 || GET_CODE (SET_DEST (pat)) == MEM))
4105 /* This insn might need a length adjustment. */
4108 if (GET_CODE (SET_SRC (pat)) == MEM)
4109 addr = XEXP (SET_SRC (pat), 0);
4111 addr = XEXP (SET_DEST (pat), 0);
4115 /* On the H8/300, we subtract the difference between the
4116 actual length and the longest one, which is @(d:16,ERs). */
4118 /* @Rs is 2 bytes shorter than the longest. */
4119 if (GET_CODE (addr) == REG)
4122 /* @aa:8 is 2 bytes shorter than the longest. */
4123 if (GET_MODE (SET_SRC (pat)) == QImode
4124 && h8300_eightbit_constant_address_p (addr))
4129 /* On the H8/300H and H8S, we subtract the difference
4130 between the actual length and the longest one, which is
4133 /* @ERs is 6 bytes shorter than the longest. */
4134 if (GET_CODE (addr) == REG)
4137 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4138 if (GET_CODE (addr) == PLUS
4139 && GET_CODE (XEXP (addr, 0)) == REG
4140 && GET_CODE (XEXP (addr, 1)) == CONST_INT
4141 && INTVAL (XEXP (addr, 1)) > -32768
4142 && INTVAL (XEXP (addr, 1)) < 32767)
4145 /* @aa:8 is 6 bytes shorter than the longest. */
4146 if (GET_MODE (SET_SRC (pat)) == QImode
4147 && h8300_eightbit_constant_address_p (addr))
4150 /* @aa:16 is 4 bytes shorter than the longest. */
4151 if (h8300_tiny_constant_address_p (addr))
4154 /* @aa:24 is 2 bytes shorter than the longest. */
4155 if (GET_CODE (addr) == CONST_INT)
4160 /* Loading some constants needs adjustment. */
4161 if (GET_CODE (pat) == SET
4162 && GET_CODE (SET_SRC (pat)) == CONST_INT
4163 && GET_MODE (SET_DEST (pat)) == SImode
4164 && INTVAL (SET_SRC (pat)) != 0)
4166 int val = INTVAL (SET_SRC (pat));
4169 && ((val & 0xffff) == 0
4170 || ((val >> 16) & 0xffff) == 0))
4173 if (TARGET_H8300H || TARGET_H8300S)
4175 if (val == (val & 0xff)
4176 || val == (val & 0xff00))
4179 switch (val & 0xffffffff)
4195 /* Rotations need various adjustments. */
4196 if (GET_CODE (pat) == SET
4197 && (GET_CODE (SET_SRC (pat)) == ROTATE
4198 || GET_CODE (SET_SRC (pat)) == ROTATERT))
4200 rtx src = SET_SRC (pat);
4201 enum machine_mode mode = GET_MODE (src);
4205 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
4208 amount = INTVAL (XEXP (src, 1));
4210 /* Clean up AMOUNT. */
4213 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4214 amount = GET_MODE_BITSIZE (mode);
4216 /* Determine the faster direction. After this phase, amount
4217 will be at most a half of GET_MODE_BITSIZE (mode). */
4218 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4219 /* Flip the direction. */
4220 amount = GET_MODE_BITSIZE (mode) - amount;
4222 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4223 boost up the rotation. */
4224 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4225 || (mode == HImode && TARGET_H8300H && amount >= 6)
4226 || (mode == HImode && TARGET_H8300S && amount == 8)
4227 || (mode == SImode && TARGET_H8300H && amount >= 10)
4228 || (mode == SImode && TARGET_H8300S && amount >= 13))
4230 /* Adjust AMOUNT and flip the direction. */
4231 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4235 /* We use 2-bit rotations on the H8S. */
4237 amount = amount / 2 + amount % 2;
4239 /* The H8/300 uses three insns to rotate one bit, taking 6
4241 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4243 return -(20 - states);
4249 #ifndef OBJECT_FORMAT_ELF
4251 h8300_asm_named_section (name, flags)
4253 unsigned int flags ATTRIBUTE_UNUSED;
4255 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4256 fprintf (asm_out_file, "\t.section %s\n", name);
4258 #endif /* ! OBJECT_FORMAT_ELF */
4260 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4261 which is a special case of the 'R' operand. */
4264 h8300_eightbit_constant_address_p (x)
4267 /* The ranges of the 8-bit area. */
4268 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4269 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4270 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4271 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4272 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4273 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4275 unsigned HOST_WIDE_INT addr;
4277 /* We accept symbols declared with eightbit_data. */
4278 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_FLAG (x))
4281 if (GET_CODE (x) != CONST_INT)
4287 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4288 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4289 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4292 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4293 on H8/300H and H8S. */
4296 h8300_tiny_constant_address_p (x)
4299 /* The ranges of the 16-bit area. */
4300 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4301 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4302 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4303 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4304 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4305 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4306 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4307 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4309 unsigned HOST_WIDE_INT addr;
4311 /* We accept symbols declared with tiny_data. */
4312 if (GET_CODE (x) == SYMBOL_REF && TINY_DATA_NAME_P (XSTR (x, 0)))
4315 if (GET_CODE (x) != CONST_INT)
4321 || ((TARGET_H8300H && !TARGET_NORMAL_MODE)
4322 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4323 || ((TARGET_H8300S && !TARGET_NORMAL_MODE)
4324 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));