1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg PARAMS ((rtx, int));
50 static int h8300_interrupt_function_p PARAMS ((tree));
51 static int h8300_monitor_function_p PARAMS ((tree));
52 static int h8300_os_task_function_p PARAMS ((tree));
53 static void dosize PARAMS ((int, unsigned int));
54 static int round_frame_size PARAMS ((int));
55 static unsigned int compute_saved_regs PARAMS ((void));
56 static void push PARAMS ((int));
57 static void pop PARAMS ((int));
58 static const char *cond_string PARAMS ((enum rtx_code));
59 static unsigned int h8300_asm_insn_count PARAMS ((const char *));
60 const struct attribute_spec h8300_attribute_table[];
61 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
62 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
63 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
64 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
65 static void h8300_insert_attributes PARAMS ((tree, tree *));
66 #ifndef OBJECT_FORMAT_ELF
67 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
69 static void h8300_encode_label PARAMS ((tree));
70 static void h8300_encode_section_info PARAMS ((tree, int));
71 static const char *h8300_strip_name_encoding PARAMS ((const char *));
73 /* CPU_TYPE, says what cpu we're compiling for. */
76 /* True if a #pragma interrupt has been seen for the current function. */
77 static int pragma_interrupt;
79 /* True if a #pragma saveall has been seen for the current function. */
80 static int pragma_saveall;
82 static const char *const names_big[] =
83 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
85 static const char *const names_extended[] =
86 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
88 static const char *const names_upper_extended[] =
89 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
91 /* Points to one of the above. */
92 /* ??? The above could be put in an array indexed by CPU_TYPE. */
93 const char * const *h8_reg_names;
95 /* Various operations needed by the following, indexed by CPU_TYPE. */
97 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
99 /* Initialize the GCC target structure. */
100 #undef TARGET_ATTRIBUTE_TABLE
101 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
103 #undef TARGET_ASM_ALIGNED_HI_OP
104 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
106 #undef TARGET_ASM_FUNCTION_EPILOGUE
107 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
108 #undef TARGET_ENCODE_SECTION_INFO
109 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
110 #undef TARGET_STRIP_NAME_ENCODING
111 #define TARGET_STRIP_NAME_ENCODING h8300_strip_name_encoding
113 #undef TARGET_INSERT_ATTRIBUTES
114 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
116 struct gcc_target targetm = TARGET_INITIALIZER;
118 /* See below where shifts are handled for explanation of this enum. */
128 /* Symbols of the various shifts which can be used as indices. */
132 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
135 /* Macros to keep the shift algorithm tables small. */
136 #define INL SHIFT_INLINE
137 #define ROT SHIFT_ROT_AND
138 #define LOP SHIFT_LOOP
139 #define SPC SHIFT_SPECIAL
141 /* The shift algorithms for each machine, mode, shift type, and shift
142 count are defined below. The three tables below correspond to
143 QImode, HImode, and SImode, respectively. Each table is organized
144 by, in the order of indices, machine, shift type, and shift count. */
146 static enum shift_alg shift_alg_qi[3][3][8] = {
149 /* 0 1 2 3 4 5 6 7 */
150 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
151 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
152 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
156 /* 0 1 2 3 4 5 6 7 */
157 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
158 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
159 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
163 /* 0 1 2 3 4 5 6 7 */
164 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
165 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
166 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
170 static enum shift_alg shift_alg_hi[3][3][16] = {
173 /* 0 1 2 3 4 5 6 7 */
174 /* 8 9 10 11 12 13 14 15 */
175 { INL, INL, INL, INL, INL, INL, INL, SPC,
176 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
177 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
178 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
179 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
180 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
184 /* 0 1 2 3 4 5 6 7 */
185 /* 8 9 10 11 12 13 14 15 */
186 { INL, INL, INL, INL, INL, INL, INL, SPC,
187 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
188 { INL, INL, INL, INL, INL, INL, INL, SPC,
189 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
190 { INL, INL, INL, INL, INL, INL, INL, SPC,
191 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
195 /* 0 1 2 3 4 5 6 7 */
196 /* 8 9 10 11 12 13 14 15 */
197 { INL, INL, INL, INL, INL, INL, INL, INL,
198 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
199 { INL, INL, INL, INL, INL, INL, INL, INL,
200 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
201 { INL, INL, INL, INL, INL, INL, INL, INL,
202 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
206 static enum shift_alg shift_alg_si[3][3][32] = {
209 /* 0 1 2 3 4 5 6 7 */
210 /* 8 9 10 11 12 13 14 15 */
211 /* 16 17 18 19 20 21 22 23 */
212 /* 24 25 26 27 28 29 30 31 */
213 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
214 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
215 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
216 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
217 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
218 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
219 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
220 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
221 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
222 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
223 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
224 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
228 /* 0 1 2 3 4 5 6 7 */
229 /* 8 9 10 11 12 13 14 15 */
230 /* 16 17 18 19 20 21 22 23 */
231 /* 24 25 26 27 28 29 30 31 */
232 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
233 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
234 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
235 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
236 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
237 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
238 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
239 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
240 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
241 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
242 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
243 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
247 /* 0 1 2 3 4 5 6 7 */
248 /* 8 9 10 11 12 13 14 15 */
249 /* 16 17 18 19 20 21 22 23 */
250 /* 24 25 26 27 28 29 30 31 */
251 { INL, INL, INL, INL, INL, INL, INL, INL,
252 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
253 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
254 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
255 { INL, INL, INL, INL, INL, INL, INL, INL,
256 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
257 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
258 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
259 { INL, INL, INL, INL, INL, INL, INL, INL,
260 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
261 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
262 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
278 /* Initialize various cpu specific globals at start up. */
283 static const char *const h8_push_ops[2] = { "push" , "push.l" };
284 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
285 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
289 cpu_type = (int) CPU_H8300;
290 h8_reg_names = names_big;
294 /* For this we treat the H8/300H and H8S the same. */
295 cpu_type = (int) CPU_H8300H;
296 h8_reg_names = names_extended;
298 h8_push_op = h8_push_ops[cpu_type];
299 h8_pop_op = h8_pop_ops[cpu_type];
300 h8_mov_op = h8_mov_ops[cpu_type];
302 if (!TARGET_H8300S && TARGET_MAC)
304 error ("-ms2600 is used without -ms");
305 target_flags |= MASK_H8300S;
308 if (TARGET_H8300 && TARGET_NORMAL_MODE)
310 error ("-mn is used without -mh or -ms");
311 target_flags ^= MASK_NORMAL_MODE;
314 /* Some of the shifts are optimized for speed by default.
315 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
316 If optimizing for size, change shift_alg for those shift to
321 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
322 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
324 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
326 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
327 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
329 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
330 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
333 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
334 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
336 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
337 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
339 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
340 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
341 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
342 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
345 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
354 static const char *const names_small[] = {
355 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
356 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
359 return names_small[REGNO (x) * 2 + b];
362 /* REGNO must be saved/restored across calls if this macro is true. */
364 #define WORD_REG_USED(regno) \
366 /* No need to save registers if this function will not return. */ \
367 && ! TREE_THIS_VOLATILE (current_function_decl) \
369 /* Save any call saved register that was used. */ \
370 || (regs_ever_live[regno] && !call_used_regs[regno]) \
371 /* Save the frame pointer if it was used. */ \
372 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
373 /* Save any register used in an interrupt handler. */ \
374 || (h8300_current_function_interrupt_function_p () \
375 && regs_ever_live[regno]) \
376 /* Save call clobbered registers in non-leaf interrupt \
378 || (h8300_current_function_interrupt_function_p () \
379 && call_used_regs[regno] \
380 && !current_function_is_leaf)))
382 /* Output assembly language to FILE for the operation OP with operand size
383 SIZE to adjust the stack pointer. */
390 /* H8/300 cannot add/subtract a large constant with a single
391 instruction. If a temporary register is available, load the
392 constant to it and then do the addition. */
395 && !h8300_current_function_interrupt_function_p ()
396 && !(current_function_needs_context && sign < 0))
399 rtx r3 = gen_rtx_REG (Pmode, 3);
400 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
401 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
402 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
406 /* The stack adjustment made here is further optimized by the
407 splitter. In case of H8/300, the splitter always splits the
408 addition emitted here to make the adjustment
410 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
411 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
415 /* Round up frame size SIZE. */
418 round_frame_size (size)
421 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
422 & -STACK_BOUNDARY / BITS_PER_UNIT);
425 /* Compute which registers to push/pop.
426 Return a bit vector of registers. */
429 compute_saved_regs ()
431 unsigned int saved_regs = 0;
434 /* Construct a bit vector of registers to be pushed/popped. */
435 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
437 if (WORD_REG_USED (regno))
438 saved_regs |= 1 << regno;
441 /* Don't push/pop the frame pointer as it is treated separately. */
442 if (frame_pointer_needed)
443 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
448 /* Emit an insn to push register RN. */
454 rtx reg = gen_rtx_REG (word_mode, rn);
458 x = gen_push_h8300 (reg);
460 x = gen_push_h8300hs (reg);
462 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
465 /* Emit an insn to pop register RN. */
471 rtx reg = gen_rtx_REG (word_mode, rn);
475 x = gen_pop_h8300 (reg);
477 x = gen_pop_h8300hs (reg);
479 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
482 /* This is what the stack looks like after the prolog of
483 a function with a frame has been set up:
489 <saved registers> <- sp
491 This is what the stack looks like after the prolog of
492 a function which doesn't have a frame:
497 <saved registers> <- sp
500 /* Generate RTL code for the function prologue. */
503 h8300_expand_prologue ()
509 /* If the current function has the OS_Task attribute set, then
510 we have a naked prologue. */
511 if (h8300_os_task_function_p (current_function_decl))
514 if (h8300_monitor_function_p (current_function_decl))
515 /* My understanding of monitor functions is they act just like
516 interrupt functions, except the prologue must mask
518 emit_insn (gen_monitor_prologue ());
520 if (frame_pointer_needed)
523 push (FRAME_POINTER_REGNUM);
524 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
527 /* Leave room for locals. */
528 dosize (-1, round_frame_size (get_frame_size ()));
530 /* Push the rest of the registers in ascending order. */
531 saved_regs = compute_saved_regs ();
532 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
535 if (saved_regs & (1 << regno))
539 /* See how many registers we can push at the same time. */
540 if ((regno == 0 || regno == 4)
541 && ((saved_regs >> regno) & 0x0f) == 0x0f)
544 else if ((regno == 0 || regno == 4)
545 && ((saved_regs >> regno) & 0x07) == 0x07)
548 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
549 && ((saved_regs >> regno) & 0x03) == 0x03)
559 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
560 gen_rtx_REG (SImode, regno + 1)));
563 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
564 gen_rtx_REG (SImode, regno + 1),
565 gen_rtx_REG (SImode, regno + 2)));
568 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
569 gen_rtx_REG (SImode, regno + 1),
570 gen_rtx_REG (SImode, regno + 2),
571 gen_rtx_REG (SImode, regno + 3)));
581 h8300_can_use_return_insn_p ()
583 return (reload_completed
584 && !frame_pointer_needed
585 && get_frame_size () == 0
586 && compute_saved_regs () == 0);
589 /* Generate RTL code for the function epilogue. */
592 h8300_expand_epilogue ()
598 if (h8300_os_task_function_p (current_function_decl))
599 /* OS_Task epilogues are nearly naked -- they just have an
603 /* Pop the saved registers in descending order. */
604 saved_regs = compute_saved_regs ();
605 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
608 if (saved_regs & (1 << regno))
612 /* See how many registers we can pop at the same time. */
613 if ((regno == 7 || regno == 3)
614 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
617 else if ((regno == 6 || regno == 2)
618 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
621 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
622 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
632 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
633 gen_rtx_REG (SImode, regno)));
636 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
637 gen_rtx_REG (SImode, regno - 1),
638 gen_rtx_REG (SImode, regno)));
641 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
642 gen_rtx_REG (SImode, regno - 2),
643 gen_rtx_REG (SImode, regno - 1),
644 gen_rtx_REG (SImode, regno)));
652 /* Deallocate locals. */
653 dosize (1, round_frame_size (get_frame_size ()));
655 /* Pop frame pointer if we had one. */
656 if (frame_pointer_needed)
657 pop (FRAME_POINTER_REGNUM);
660 /* Output assembly language code for the function epilogue. */
663 h8300_output_function_epilogue (file, size)
664 FILE *file ATTRIBUTE_UNUSED;
665 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
670 /* Return nonzero if the current function is an interrupt
674 h8300_current_function_interrupt_function_p ()
676 return (h8300_interrupt_function_p (current_function_decl)
677 || h8300_monitor_function_p (current_function_decl));
680 /* Output assembly code for the start of the file. */
683 asm_file_start (file)
686 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
687 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
690 fprintf (file, "; -Os\n");
692 fprintf (file, "; -O%d\n", optimize);
694 fprintf (file, "\n\t.h8300h\n");
695 else if (TARGET_H8300S)
696 fprintf (file, "\n\t.h8300s\n");
698 fprintf (file, "\n\n");
699 output_file_directive (file, main_input_filename);
702 /* Output assembly language code for the end of file. */
708 fprintf (file, "\t.end\n");
711 /* Return true if OP is a valid source operand for an integer move
715 general_operand_src (op, mode)
717 enum machine_mode mode;
719 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
721 return general_operand (op, mode);
724 /* Return true if OP is a valid destination operand for an integer move
728 general_operand_dst (op, mode)
730 enum machine_mode mode;
732 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
734 return general_operand (op, mode);
737 /* Return true if OP is a constant that contains only one 1 in its
738 binary representation. */
741 single_one_operand (operand, mode)
743 enum machine_mode mode ATTRIBUTE_UNUSED;
745 if (GET_CODE (operand) == CONST_INT)
747 /* We really need to do this masking because 0x80 in QImode is
748 represented as -128 for example. */
749 unsigned HOST_WIDE_INT mask =
750 (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
751 ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
752 : ~(unsigned HOST_WIDE_INT) 0;
753 unsigned HOST_WIDE_INT value = INTVAL (operand);
755 if (exact_log2 (value & mask) >= 0)
762 /* Return true if OP is a constant that contains only one 0 in its
763 binary representation. */
766 single_zero_operand (operand, mode)
768 enum machine_mode mode ATTRIBUTE_UNUSED;
770 if (GET_CODE (operand) == CONST_INT)
772 /* We really need to do this masking because 0x80 in QImode is
773 represented as -128 for example. */
774 unsigned HOST_WIDE_INT mask =
775 (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
776 ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
777 : ~(unsigned HOST_WIDE_INT) 0;
778 unsigned HOST_WIDE_INT value = INTVAL (operand);
780 if (exact_log2 (~value & mask) >= 0)
787 /* Return true if OP is a valid call operand. */
790 call_insn_operand (op, mode)
792 enum machine_mode mode ATTRIBUTE_UNUSED;
794 if (GET_CODE (op) == MEM)
796 rtx inside = XEXP (op, 0);
797 if (register_operand (inside, Pmode))
799 if (CONSTANT_ADDRESS_P (inside))
805 /* Return 1 if an addition/subtraction of a constant integer can be
806 transformed into two consecutive adds/subs that are faster than the
807 straightforward way. Otherwise, return 0. */
810 two_insn_adds_subs_operand (op, mode)
812 enum machine_mode mode;
814 if (GET_CODE (op) == CONST_INT)
816 HOST_WIDE_INT value = INTVAL (op);
818 /* Force VALUE to be positive so that we do not have to consider
819 the negative case. */
822 if (TARGET_H8300H || TARGET_H8300S)
824 /* A constant addition/subtraction takes 2 states in QImode,
825 4 states in HImode, and 6 states in SImode. Thus, the
826 only case we can win is when SImode is used, in which
827 case, two adds/subs are used, taking 4 states. */
837 /* We do not profit directly by splitting addition or
838 subtraction of 3 and 4. However, since these are
839 implemented as a sequence of adds or subs, they do not
840 clobber (cc0) unlike a sequence of add.b and add.x. */
851 /* Split an add of a small constant into two adds/subs insns.
853 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
854 instead of adds/subs. */
857 split_adds_subs (mode, operands, use_incdec_p)
858 enum machine_mode mode;
862 HOST_WIDE_INT val = INTVAL (operands[1]);
863 rtx reg = operands[0];
864 HOST_WIDE_INT sign = 1;
865 HOST_WIDE_INT amount;
866 rtx (*gen_last) (rtx, rtx, rtx);
867 rtx (*gen_normal) (rtx, rtx, rtx);
869 /* Force VAL to be positive so that we do not have to consider the
880 gen_normal = gen_addhi3;
881 gen_last = gen_addhi3_incdec;
885 gen_normal = gen_addsi3;
886 gen_last = gen_addsi3_incdec;
893 /* Try different amounts in descending order. */
894 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
898 for (; val >= amount; val -= amount)
900 /* If requested, generate the last insn using inc/dec. */
901 if (use_incdec_p && amount <= 2 && val == amount)
902 emit_insn (gen_last (reg, reg, GEN_INT (sign * amount)));
904 emit_insn (gen_normal (reg, reg, GEN_INT (sign * amount)));
911 /* Return true if OP is a valid call operand, and OP represents
912 an operand for a small call (4 bytes instead of 6 bytes). */
915 small_call_insn_operand (op, mode)
917 enum machine_mode mode ATTRIBUTE_UNUSED;
919 if (GET_CODE (op) == MEM)
921 rtx inside = XEXP (op, 0);
923 /* Register indirect is a small call. */
924 if (register_operand (inside, Pmode))
927 /* A call through the function vector is a small
929 if (GET_CODE (inside) == SYMBOL_REF
930 && SYMBOL_REF_FLAG (inside))
933 /* Otherwise it's a large call. */
937 /* Return true if OP is a valid jump operand. */
940 jump_address_operand (op, mode)
942 enum machine_mode mode;
944 if (GET_CODE (op) == REG)
945 return mode == Pmode;
947 if (GET_CODE (op) == MEM)
949 rtx inside = XEXP (op, 0);
950 if (register_operand (inside, Pmode))
952 if (CONSTANT_ADDRESS_P (inside))
958 /* Recognize valid operands for bit-field instructions. */
960 extern int rtx_equal_function_value_matters;
963 bit_operand (op, mode)
965 enum machine_mode mode;
967 /* We can accept any general operand, except that MEM operands must
968 be limited to those that use addresses valid for the 'U' constraint. */
969 if (!general_operand (op, mode))
972 /* Accept any mem during RTL generation. Otherwise, the code that does
973 insv and extzv will think that we can not handle memory. However,
974 to avoid reload problems, we only accept 'U' MEM operands after RTL
975 generation. This means that any named pattern which uses this predicate
976 must force its operands to match 'U' before emitting RTL. */
978 if (GET_CODE (op) == REG)
980 if (GET_CODE (op) == SUBREG)
982 if (!rtx_equal_function_value_matters)
983 /* We're building rtl. */
984 return GET_CODE (op) == MEM;
986 return (GET_CODE (op) == MEM
987 && EXTRA_CONSTRAINT (op, 'U'));
991 bit_memory_operand (op, mode)
993 enum machine_mode mode ATTRIBUTE_UNUSED;
995 return (GET_CODE (op) == MEM
996 && EXTRA_CONSTRAINT (op, 'U'));
999 /* Handle machine specific pragmas for compatibility with existing
1000 compilers for the H8/300.
1002 pragma saveall generates prologue/epilogue code which saves and
1003 restores all the registers on function entry.
1005 pragma interrupt saves and restores all registers, and exits with
1006 an rte instruction rather than an rts. A pointer to a function
1007 with this attribute may be safely used in an interrupt vector. */
1010 h8300_pr_interrupt (pfile)
1011 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1013 pragma_interrupt = 1;
1017 h8300_pr_saveall (pfile)
1018 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1023 /* If the next function argument with MODE and TYPE is to be passed in
1024 a register, return a reg RTX for the hard register in which to pass
1025 the argument. CUM represents the state after the last argument.
1026 If the argument is to be pushed, NULL_RTX is returned. */
1029 function_arg (cum, mode, type, named)
1030 CUMULATIVE_ARGS *cum;
1031 enum machine_mode mode;
1035 static const char *const hand_list[] = {
1054 rtx result = NULL_RTX;
1058 /* Never pass unnamed arguments in registers. */
1062 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1063 if (TARGET_QUICKCALL)
1066 /* If calling hand written assembler, use 4 regs of args. */
1069 const char * const *p;
1071 fname = XSTR (cum->libcall, 0);
1073 /* See if this libcall is one of the hand coded ones. */
1074 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1085 if (mode == BLKmode)
1086 size = int_size_in_bytes (type);
1088 size = GET_MODE_SIZE (mode);
1090 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1091 && cum->nbytes / UNITS_PER_WORD <= 3)
1092 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1098 /* Return the cost of the rtx R with code CODE. */
1101 const_costs (r, c, outer_code)
1104 enum rtx_code outer_code;
1110 HOST_WIDE_INT n = INTVAL (r);
1112 if (-4 <= n || n <= 4)
1122 return 0 + (outer_code == SET);
1125 if (TARGET_H8300H || TARGET_H8300S)
1126 return 0 + (outer_code == SET);
1153 if (GET_MODE (x) == QImode)
1156 if (GET_MODE (x) != HImode
1157 && GET_MODE (x) != SImode)
1162 operands[2] = XEXP (x, 1);
1164 return compute_logical_op_length (GET_MODE (x), operands);
1168 h8300_shift_costs (x)
1173 if (GET_MODE (x) != QImode
1174 && GET_MODE (x) != HImode
1175 && GET_MODE (x) != SImode)
1180 operands[2] = XEXP (x, 1);
1182 return compute_a_shift_length (NULL, operands);
1185 /* Documentation for the machine specific operand escapes:
1187 'E' like s but negative.
1188 'F' like t but negative.
1189 'G' constant just the negative
1190 'R' print operand as a byte:8 address if appropriate, else fall back to
1192 'S' print operand as a long word
1193 'T' print operand as a word
1194 'V' find the set bit, and print its number.
1195 'W' find the clear bit, and print its number.
1196 'X' print operand as a byte
1197 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1198 If this operand isn't a register, fall back to 'R' handling.
1200 'b' print the bit opcode
1201 'e' first word of 32 bit value - if reg, then least reg. if mem
1202 then least. if const then most sig word
1203 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1204 then +2. if const then least sig word
1205 'j' print operand as condition code.
1206 'k' print operand as reverse condition code.
1207 's' print as low byte of 16 bit value
1208 't' print as high byte of 16 bit value
1209 'w' print as low byte of 32 bit value
1210 'x' print as 2nd byte of 32 bit value
1211 'y' print as 3rd byte of 32 bit value
1212 'z' print as msb of 32 bit value
1215 /* Return assembly language string which identifies a comparison type. */
1248 /* Print operand X using operand code CODE to assembly language output file
1252 print_operand (file, x, code)
1257 /* This is used for communication between codes V,W,Z and Y. */
1263 switch (GET_CODE (x))
1266 fprintf (file, "%sl", names_big[REGNO (x)]);
1269 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1276 switch (GET_CODE (x))
1279 fprintf (file, "%sh", names_big[REGNO (x)]);
1282 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1289 if (GET_CODE (x) != CONST_INT)
1291 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1294 if (GET_CODE (x) == REG)
1295 fprintf (file, "%s", names_extended[REGNO (x)]);
1300 if (GET_CODE (x) == REG)
1301 fprintf (file, "%s", names_big[REGNO (x)]);
1306 bitint = exact_log2 (INTVAL (x) & 0xff);
1309 fprintf (file, "#%d", bitint);
1312 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1315 fprintf (file, "#%d", bitint);
1319 if (GET_CODE (x) == REG)
1320 fprintf (file, "%s", byte_reg (x, 0));
1327 if (GET_CODE (x) == REG)
1328 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1330 print_operand (file, x, 'R');
1334 bitint = INTVAL (x);
1335 fprintf (file, "#%d", bitint & 7);
1338 switch (GET_CODE (x))
1341 fprintf (file, "bor");
1344 fprintf (file, "bxor");
1347 fprintf (file, "band");
1354 switch (GET_CODE (x))
1358 fprintf (file, "%s", names_big[REGNO (x)]);
1360 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1363 print_operand (file, x, 0);
1366 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1372 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1373 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1374 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1383 switch (GET_CODE (x))
1387 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1389 fprintf (file, "%s", names_big[REGNO (x)]);
1392 x = adjust_address (x, HImode, 2);
1393 print_operand (file, x, 0);
1396 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1402 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1403 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1404 fprintf (file, "#%ld", (val & 0xffff));
1412 fputs (cond_string (GET_CODE (x)), file);
1415 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1418 if (GET_CODE (x) == CONST_INT)
1419 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1421 fprintf (file, "%s", byte_reg (x, 0));
1424 if (GET_CODE (x) == CONST_INT)
1425 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1427 fprintf (file, "%s", byte_reg (x, 1));
1430 if (GET_CODE (x) != CONST_INT)
1432 fprintf (file, "%ld", INTVAL (x));
1435 if (GET_CODE (x) == CONST_INT)
1436 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1438 fprintf (file, "%s",
1439 byte_reg (x, TARGET_H8300 ? 2 : 0));
1442 if (GET_CODE (x) == CONST_INT)
1443 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1445 fprintf (file, "%s",
1446 byte_reg (x, TARGET_H8300 ? 3 : 1));
1449 if (GET_CODE (x) == CONST_INT)
1450 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1452 fprintf (file, "%s", byte_reg (x, 0));
1455 if (GET_CODE (x) == CONST_INT)
1456 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1458 fprintf (file, "%s", byte_reg (x, 1));
1463 switch (GET_CODE (x))
1466 switch (GET_MODE (x))
1469 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1470 fprintf (file, "%s", byte_reg (x, 0));
1471 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1472 fprintf (file, "%s", names_big[REGNO (x)]);
1476 fprintf (file, "%s", names_big[REGNO (x)]);
1480 fprintf (file, "%s", names_extended[REGNO (x)]);
1489 rtx addr = XEXP (x, 0);
1491 fprintf (file, "@");
1492 output_address (addr);
1494 /* We fall back from smaller addressing to larger
1495 addressing in various ways depending on CODE. */
1499 /* Used for mov.b and bit operations. */
1500 if (h8300_eightbit_constant_address_p (addr))
1502 fprintf (file, ":8");
1506 /* Fall through. We should not get here if we are
1507 processing bit operations on H8/300 or H8/300H
1508 because 'U' constraint does not allow bit
1509 operations on the tiny area on these machines. */
1513 /* Used for mov.w and mov.l. */
1514 if (h8300_tiny_constant_address_p (addr))
1515 fprintf (file, ":16");
1527 fprintf (file, "#");
1528 print_operand_address (file, x);
1534 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1535 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1536 fprintf (file, "#%ld", val);
1545 /* Output assembly language output for the address ADDR to FILE. */
1548 print_operand_address (file, addr)
1552 switch (GET_CODE (addr))
1555 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1559 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1563 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1567 fprintf (file, "(");
1568 if (GET_CODE (XEXP (addr, 0)) == REG)
1571 print_operand_address (file, XEXP (addr, 1));
1572 fprintf (file, ",");
1573 print_operand_address (file, XEXP (addr, 0));
1578 print_operand_address (file, XEXP (addr, 0));
1579 fprintf (file, "+");
1580 print_operand_address (file, XEXP (addr, 1));
1582 fprintf (file, ")");
1587 /* Since the H8/300 only has 16 bit pointers, negative values are also
1588 those >= 32768. This happens for example with pointer minus a
1589 constant. We don't want to turn (char *p - 2) into
1590 (char *p + 65534) because loop unrolling can build upon this
1591 (IE: char *p + 131068). */
1592 int n = INTVAL (addr);
1594 n = (int) (short) n;
1595 fprintf (file, "%d", n);
1600 output_addr_const (file, addr);
1605 /* Output all insn addresses and their sizes into the assembly language
1606 output file. This is helpful for debugging whether the length attributes
1607 in the md file are correct. This is not meant to be a user selectable
1611 final_prescan_insn (insn, operand, num_operands)
1612 rtx insn, *operand ATTRIBUTE_UNUSED;
1613 int num_operands ATTRIBUTE_UNUSED;
1615 /* This holds the last insn address. */
1616 static int last_insn_address = 0;
1618 const int uid = INSN_UID (insn);
1620 if (TARGET_RTL_DUMP)
1622 fprintf (asm_out_file, "\n****************");
1623 print_rtl (asm_out_file, PATTERN (insn));
1624 fprintf (asm_out_file, "\n");
1627 if (TARGET_ADDRESSES)
1629 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1630 INSN_ADDRESSES (uid) - last_insn_address);
1631 last_insn_address = INSN_ADDRESSES (uid);
1635 /* Prepare for an SI sized move. */
1641 rtx src = operands[1];
1642 rtx dst = operands[0];
1643 if (!reload_in_progress && !reload_completed)
1645 if (!register_operand (dst, GET_MODE (dst)))
1647 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1648 emit_move_insn (tmp, src);
1655 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1656 Define the offset between two registers, one to be eliminated, and
1657 the other its replacement, at the start of a routine. */
1660 h8300_initial_elimination_offset (from, to)
1665 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1666 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1667 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1668 offset = frame_pointer_needed * UNITS_PER_WORD;
1673 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1674 if (WORD_REG_USED (regno))
1675 offset += UNITS_PER_WORD;
1677 /* See the comments for get_frame_size. We need to round it up to
1680 offset += round_frame_size (get_frame_size ());
1682 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1683 offset += UNITS_PER_WORD; /* Skip saved PC */
1686 if ((TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE)
1693 h8300_return_addr_rtx (count, frame)
1700 ret = gen_rtx_MEM (Pmode,
1701 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1702 else if (flag_omit_frame_pointer)
1705 ret = gen_rtx_MEM (Pmode,
1706 memory_address (Pmode,
1707 plus_constant (frame, UNITS_PER_WORD)));
1708 set_mem_alias_set (ret, get_frame_alias_set ());
1712 /* Update the condition code from the insn. */
1715 notice_update_cc (body, insn)
1721 switch (get_attr_cc (insn))
1724 /* Insn does not affect CC at all. */
1728 /* Insn does not change CC, but the 0'th operand has been changed. */
1729 if (cc_status.value1 != 0
1730 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1731 cc_status.value1 = 0;
1732 if (cc_status.value2 != 0
1733 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1734 cc_status.value2 = 0;
1738 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1739 The V flag is unusable. The C flag may or may not be known but
1740 that's ok because alter_cond will change tests to use EQ/NE. */
1742 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1743 set = single_set (insn);
1744 cc_status.value1 = SET_SRC (set);
1745 if (SET_DEST (set) != cc0_rtx)
1746 cc_status.value2 = SET_DEST (set);
1750 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1751 The C flag may or may not be known but that's ok because
1752 alter_cond will change tests to use EQ/NE. */
1754 cc_status.flags |= CC_NO_CARRY;
1755 set = single_set (insn);
1756 cc_status.value1 = SET_SRC (set);
1757 if (SET_DEST (set) != cc0_rtx)
1758 cc_status.value2 = SET_DEST (set);
1762 /* The insn is a compare instruction. */
1764 cc_status.value1 = SET_SRC (body);
1768 /* Insn doesn't leave CC in a usable state. */
1774 /* Return nonzero if X is a stack pointer. */
1777 stack_pointer_operand (x, mode)
1779 enum machine_mode mode ATTRIBUTE_UNUSED;
1781 return x == stack_pointer_rtx;
1784 /* Return nonzero if X is a constant whose absolute value is no
1788 const_int_le_2_operand (x, mode)
1790 enum machine_mode mode ATTRIBUTE_UNUSED;
1792 return (GET_CODE (x) == CONST_INT
1793 && abs (INTVAL (x)) <= 2);
1796 /* Return nonzero if X is a constant whose absolute value is no
1800 const_int_le_6_operand (x, mode)
1802 enum machine_mode mode ATTRIBUTE_UNUSED;
1804 return (GET_CODE (x) == CONST_INT
1805 && abs (INTVAL (x)) <= 6);
1808 /* Return nonzero if X is a constant whose absolute value is greater
1812 const_int_gt_2_operand (x, mode)
1814 enum machine_mode mode ATTRIBUTE_UNUSED;
1816 return (GET_CODE (x) == CONST_INT
1817 && abs (INTVAL (x)) > 2);
1820 /* Return nonzero if X is a constant whose absolute value is no
1824 const_int_ge_8_operand (x, mode)
1826 enum machine_mode mode ATTRIBUTE_UNUSED;
1828 return (GET_CODE (x) == CONST_INT
1829 && abs (INTVAL (x)) >= 8);
1832 /* Return nonzero if X is a constant expressible in QImode. */
1835 const_int_qi_operand (x, mode)
1837 enum machine_mode mode ATTRIBUTE_UNUSED;
1839 return (GET_CODE (x) == CONST_INT
1840 && (INTVAL (x) & 0xff) == INTVAL (x));
1843 /* Return nonzero if X is a constant expressible in HImode. */
1846 const_int_hi_operand (x, mode)
1848 enum machine_mode mode ATTRIBUTE_UNUSED;
1850 return (GET_CODE (x) == CONST_INT
1851 && (INTVAL (x) & 0xffff) == INTVAL (x));
1854 /* Return nonzero if X is a constant suitable for inc/dec. */
1857 incdec_operand (x, mode)
1859 enum machine_mode mode ATTRIBUTE_UNUSED;
1861 return (GET_CODE (x) == CONST_INT
1862 && (CONST_OK_FOR_M (INTVAL (x))
1863 || CONST_OK_FOR_O (INTVAL (x))));
1866 /* Return nonzero if X is either EQ or NE. */
1869 eqne_operator (x, mode)
1871 enum machine_mode mode ATTRIBUTE_UNUSED;
1873 enum rtx_code code = GET_CODE (x);
1875 return (code == EQ || code == NE);
1878 /* Recognize valid operators for bit instructions. */
1881 bit_operator (x, mode)
1883 enum machine_mode mode ATTRIBUTE_UNUSED;
1885 enum rtx_code code = GET_CODE (x);
1893 output_plussi (operands)
1896 enum machine_mode mode = GET_MODE (operands[0]);
1903 if (GET_CODE (operands[2]) == REG)
1904 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1906 if (GET_CODE (operands[2]) == CONST_INT)
1908 HOST_WIDE_INT n = INTVAL (operands[2]);
1910 if ((n & 0xffffff) == 0)
1911 return "add\t%z2,%z0";
1912 if ((n & 0xffff) == 0)
1913 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
1914 if ((n & 0xff) == 0)
1915 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1918 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1922 if (GET_CODE (operands[2]) == REG)
1923 return "add.l\t%S2,%S0";
1925 if (GET_CODE (operands[2]) == CONST_INT)
1927 HOST_WIDE_INT intval = INTVAL (operands[2]);
1929 /* See if we can finish with 2 bytes. */
1931 switch ((unsigned int) intval & 0xffffffff)
1936 return "adds\t%2,%S0";
1941 return "subs\t%G2,%S0";
1945 operands[2] = GEN_INT (intval >> 16);
1946 return "inc.w\t%2,%e0";
1950 operands[2] = GEN_INT (intval >> 16);
1951 return "dec.w\t%G2,%e0";
1954 /* See if we can finish with 4 bytes. */
1955 if ((intval & 0xffff) == 0)
1957 operands[2] = GEN_INT (intval >> 16);
1958 return "add.w\t%2,%e0";
1962 return "add.l\t%S2,%S0";
1967 compute_plussi_length (operands)
1970 enum machine_mode mode = GET_MODE (operands[0]);
1977 if (GET_CODE (operands[2]) == REG)
1980 if (GET_CODE (operands[2]) == CONST_INT)
1982 HOST_WIDE_INT n = INTVAL (operands[2]);
1984 if ((n & 0xffffff) == 0)
1986 if ((n & 0xffff) == 0)
1988 if ((n & 0xff) == 0)
1996 if (GET_CODE (operands[2]) == REG)
1999 if (GET_CODE (operands[2]) == CONST_INT)
2001 HOST_WIDE_INT intval = INTVAL (operands[2]);
2003 /* See if we can finish with 2 bytes. */
2005 switch ((unsigned int) intval & 0xffffffff)
2026 /* See if we can finish with 4 bytes. */
2027 if ((intval & 0xffff) == 0)
2036 compute_plussi_cc (operands)
2039 enum machine_mode mode = GET_MODE (operands[0]);
2050 if (GET_CODE (operands[2]) == REG)
2053 if (GET_CODE (operands[2]) == CONST_INT)
2055 HOST_WIDE_INT intval = INTVAL (operands[2]);
2057 /* See if we can finish with 2 bytes. */
2059 switch ((unsigned int) intval & 0xffffffff)
2064 return CC_NONE_0HIT;
2069 return CC_NONE_0HIT;
2080 /* See if we can finish with 4 bytes. */
2081 if ((intval & 0xffff) == 0)
2090 output_logical_op (mode, operands)
2091 enum machine_mode mode;
2094 /* Figure out the logical op that we need to perform. */
2095 enum rtx_code code = GET_CODE (operands[3]);
2096 /* Pretend that every byte is affected if both operands are registers. */
2097 const unsigned HOST_WIDE_INT intval =
2098 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2099 ? INTVAL (operands[2]) : 0x55555555);
2100 /* The determinant of the algorithm. If we perform an AND, 0
2101 affects a bit. Otherwise, 1 affects a bit. */
2102 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2103 /* Break up DET into pieces. */
2104 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2105 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2106 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2107 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2108 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2109 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2110 int lower_half_easy_p = 0;
2111 int upper_half_easy_p = 0;
2112 /* The name of an insn. */
2134 /* First, see if we can finish with one insn. */
2135 if ((TARGET_H8300H || TARGET_H8300S)
2139 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2140 output_asm_insn (insn_buf, operands);
2144 /* Take care of the lower byte. */
2147 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2148 output_asm_insn (insn_buf, operands);
2150 /* Take care of the upper byte. */
2153 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2154 output_asm_insn (insn_buf, operands);
2159 if (TARGET_H8300H || TARGET_H8300S)
2161 /* Determine if the lower half can be taken care of in no more
2163 lower_half_easy_p = (b0 == 0
2165 || (code != IOR && w0 == 0xffff));
2167 /* Determine if the upper half can be taken care of in no more
2169 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2170 || (code == AND && w1 == 0xff00));
2173 /* Check if doing everything with one insn is no worse than
2174 using multiple insns. */
2175 if ((TARGET_H8300H || TARGET_H8300S)
2176 && w0 != 0 && w1 != 0
2177 && !(lower_half_easy_p && upper_half_easy_p))
2179 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2180 output_asm_insn (insn_buf, operands);
2184 /* Take care of the lower and upper words individually. For
2185 each word, we try different methods in the order of
2187 1) the special insn (in case of AND or XOR),
2188 2) the word-wise insn, and
2189 3) The byte-wise insn. */
2191 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2192 output_asm_insn ((code == AND)
2193 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2195 else if ((TARGET_H8300H || TARGET_H8300S)
2199 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2200 output_asm_insn (insn_buf, operands);
2206 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2207 output_asm_insn (insn_buf, operands);
2211 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2212 output_asm_insn (insn_buf, operands);
2217 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2218 output_asm_insn ((code == AND)
2219 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2221 else if ((TARGET_H8300H || TARGET_H8300S)
2225 output_asm_insn ("extu.w\t%e0", operands);
2227 else if (TARGET_H8300H || TARGET_H8300S)
2231 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2232 output_asm_insn (insn_buf, operands);
2239 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2240 output_asm_insn (insn_buf, operands);
2244 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2245 output_asm_insn (insn_buf, operands);
2257 compute_logical_op_length (mode, operands)
2258 enum machine_mode mode;
2261 /* Figure out the logical op that we need to perform. */
2262 enum rtx_code code = GET_CODE (operands[3]);
2263 /* Pretend that every byte is affected if both operands are registers. */
2264 const unsigned HOST_WIDE_INT intval =
2265 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2266 ? INTVAL (operands[2]) : 0x55555555);
2267 /* The determinant of the algorithm. If we perform an AND, 0
2268 affects a bit. Otherwise, 1 affects a bit. */
2269 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2270 /* Break up DET into pieces. */
2271 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2272 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2273 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2274 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2275 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2276 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2277 int lower_half_easy_p = 0;
2278 int upper_half_easy_p = 0;
2280 unsigned int length = 0;
2285 /* First, see if we can finish with one insn. */
2286 if ((TARGET_H8300H || TARGET_H8300S)
2290 if (REG_P (operands[2]))
2297 /* Take care of the lower byte. */
2301 /* Take care of the upper byte. */
2307 if (TARGET_H8300H || TARGET_H8300S)
2309 /* Determine if the lower half can be taken care of in no more
2311 lower_half_easy_p = (b0 == 0
2313 || (code != IOR && w0 == 0xffff));
2315 /* Determine if the upper half can be taken care of in no more
2317 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2318 || (code == AND && w1 == 0xff00));
2321 /* Check if doing everything with one insn is no worse than
2322 using multiple insns. */
2323 if ((TARGET_H8300H || TARGET_H8300S)
2324 && w0 != 0 && w1 != 0
2325 && !(lower_half_easy_p && upper_half_easy_p))
2327 if (REG_P (operands[2]))
2334 /* Take care of the lower and upper words individually. For
2335 each word, we try different methods in the order of
2337 1) the special insn (in case of AND or XOR),
2338 2) the word-wise insn, and
2339 3) The byte-wise insn. */
2341 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2345 else if ((TARGET_H8300H || TARGET_H8300S)
2361 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2365 else if ((TARGET_H8300H || TARGET_H8300S)
2371 else if (TARGET_H8300H || TARGET_H8300S)
2393 compute_logical_op_cc (mode, operands)
2394 enum machine_mode mode;
2397 /* Figure out the logical op that we need to perform. */
2398 enum rtx_code code = GET_CODE (operands[3]);
2399 /* Pretend that every byte is affected if both operands are registers. */
2400 const unsigned HOST_WIDE_INT intval =
2401 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2402 ? INTVAL (operands[2]) : 0x55555555);
2403 /* The determinant of the algorithm. If we perform an AND, 0
2404 affects a bit. Otherwise, 1 affects a bit. */
2405 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2406 /* Break up DET into pieces. */
2407 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2408 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2409 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2410 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2411 int lower_half_easy_p = 0;
2412 int upper_half_easy_p = 0;
2413 /* Condition code. */
2414 enum attr_cc cc = CC_CLOBBER;
2419 /* First, see if we can finish with one insn. */
2420 if ((TARGET_H8300H || TARGET_H8300S)
2428 if (TARGET_H8300H || TARGET_H8300S)
2430 /* Determine if the lower half can be taken care of in no more
2432 lower_half_easy_p = (b0 == 0
2434 || (code != IOR && w0 == 0xffff));
2436 /* Determine if the upper half can be taken care of in no more
2438 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2439 || (code == AND && w1 == 0xff00));
2442 /* Check if doing everything with one insn is no worse than
2443 using multiple insns. */
2444 if ((TARGET_H8300H || TARGET_H8300S)
2445 && w0 != 0 && w1 != 0
2446 && !(lower_half_easy_p && upper_half_easy_p))
2459 We devote a fair bit of code to getting efficient shifts since we
2460 can only shift one bit at a time on the H8/300 and H8/300H and only
2461 one or two bits at a time on the H8S.
2463 All shift code falls into one of the following ways of
2466 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2467 when a straight line shift is about the same size or smaller than
2470 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2471 off the bits we don't need. This is used when only a few of the
2472 bits in the original value will survive in the shifted value.
2474 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2475 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2476 shifts can be added if the shift count is slightly more than 8 or
2477 16. This case also includes other oddballs that are not worth
2480 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2482 For each shift count, we try to use code that has no trade-off
2483 between code size and speed whenever possible.
2485 If the trade-off is unavoidable, we try to be reasonable.
2486 Specifically, the fastest version is one instruction longer than
2487 the shortest version, we take the fastest version. We also provide
2488 the use a way to switch back to the shortest version with -Os.
2490 For the details of the shift algorithms for various shift counts,
2491 refer to shift_alg_[qhs]i. */
2494 nshift_operator (x, mode)
2496 enum machine_mode mode ATTRIBUTE_UNUSED;
2498 switch (GET_CODE (x))
2510 /* Emit code to do shifts. */
2513 expand_a_shift (mode, code, operands)
2514 enum machine_mode mode;
2518 emit_move_insn (operands[0], operands[1]);
2520 /* Need a loop to get all the bits we want - we generate the
2521 code at emit time, but need to allocate a scratch reg now. */
2523 emit_insn (gen_rtx_PARALLEL
2526 gen_rtx_SET (VOIDmode, operands[0],
2527 gen_rtx (code, mode, operands[0],
2529 gen_rtx_CLOBBER (VOIDmode,
2530 gen_rtx_SCRATCH (QImode)))));
2533 /* Symbols of the various modes which can be used as indices. */
2537 QIshift, HIshift, SIshift
2540 /* For single bit shift insns, record assembler and what bits of the
2541 condition code are valid afterwards (represented as various CC_FOO
2542 bits, 0 means CC isn't left in a usable state). */
2546 const char *const assembler;
2550 /* Assembler instruction shift table.
2552 These tables are used to look up the basic shifts.
2553 They are indexed by cpu, shift_type, and mode. */
2555 static const struct shift_insn shift_one[2][3][3] =
2561 { "shll\t%X0", CC_NO_CARRY },
2562 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2563 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
2565 /* SHIFT_LSHIFTRT */
2567 { "shlr\t%X0", CC_NO_CARRY },
2568 { "shlr\t%t0\n\trotxr\t%s0", 0 },
2569 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2571 /* SHIFT_ASHIFTRT */
2573 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2574 { "shar\t%t0\n\trotxr\t%s0", 0 },
2575 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2582 { "shll.b\t%X0", CC_NO_CARRY },
2583 { "shll.w\t%T0", CC_NO_CARRY },
2584 { "shll.l\t%S0", CC_NO_CARRY }
2586 /* SHIFT_LSHIFTRT */
2588 { "shlr.b\t%X0", CC_NO_CARRY },
2589 { "shlr.w\t%T0", CC_NO_CARRY },
2590 { "shlr.l\t%S0", CC_NO_CARRY }
2592 /* SHIFT_ASHIFTRT */
2594 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2595 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2596 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2601 static const struct shift_insn shift_two[3][3] =
2605 { "shll.b\t#2,%X0", CC_NO_CARRY },
2606 { "shll.w\t#2,%T0", CC_NO_CARRY },
2607 { "shll.l\t#2,%S0", CC_NO_CARRY }
2609 /* SHIFT_LSHIFTRT */
2611 { "shlr.b\t#2,%X0", CC_NO_CARRY },
2612 { "shlr.w\t#2,%T0", CC_NO_CARRY },
2613 { "shlr.l\t#2,%S0", CC_NO_CARRY }
2615 /* SHIFT_ASHIFTRT */
2617 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2618 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2619 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2623 /* Rotates are organized by which shift they'll be used in implementing.
2624 There's no need to record whether the cc is valid afterwards because
2625 it is the AND insn that will decide this. */
2627 static const char *const rotate_one[2][3][3] =
2634 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2637 /* SHIFT_LSHIFTRT */
2640 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2643 /* SHIFT_ASHIFTRT */
2646 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2658 /* SHIFT_LSHIFTRT */
2664 /* SHIFT_ASHIFTRT */
2673 static const char *const rotate_two[3][3] =
2681 /* SHIFT_LSHIFTRT */
2687 /* SHIFT_ASHIFTRT */
2696 /* Shift algorithm. */
2699 /* The number of bits to be shifted by shift1 and shift2. Valid
2700 when ALG is SHIFT_SPECIAL. */
2701 unsigned int remainder;
2703 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2704 const char *special;
2706 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2707 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2710 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2711 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2714 /* Valid CC flags. */
2718 static void get_shift_alg PARAMS ((enum shift_type,
2719 enum shift_mode, unsigned int,
2720 struct shift_info *));
2722 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2723 best algorithm for doing the shift. The assembler code is stored
2724 in the pointers in INFO. We achieve the maximum efficiency in most
2725 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2726 SImode in particular have a lot of room to optimize.
2728 We first determine the strategy of the shift algorithm by a table
2729 lookup. If that tells us to use a hand crafted assembly code, we
2730 go into the big switch statement to find what that is. Otherwise,
2731 we resort to a generic way, such as inlining. In either case, the
2732 result is returned through INFO. */
2735 get_shift_alg (shift_type, shift_mode, count, info)
2736 enum shift_type shift_type;
2737 enum shift_mode shift_mode;
2739 struct shift_info *info;
2743 /* Find the target CPU. */
2746 else if (TARGET_H8300H)
2751 /* Find the shift algorithm. */
2752 info->alg = SHIFT_LOOP;
2756 if (count < GET_MODE_BITSIZE (QImode))
2757 info->alg = shift_alg_qi[cpu][shift_type][count];
2761 if (count < GET_MODE_BITSIZE (HImode))
2762 info->alg = shift_alg_hi[cpu][shift_type][count];
2766 if (count < GET_MODE_BITSIZE (SImode))
2767 info->alg = shift_alg_si[cpu][shift_type][count];
2774 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2778 info->remainder = count;
2782 /* It is up to the caller to know that looping clobbers cc. */
2783 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2784 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2785 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2789 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2790 info->shift2 = rotate_two[shift_type][shift_mode];
2791 info->cc_valid_p = 0;
2795 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2796 info->remainder = 0;
2797 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2798 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2799 info->cc_valid_p = 0;
2803 /* Here we only deal with SHIFT_SPECIAL. */
2807 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2808 through the entire value. */
2809 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2811 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2823 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2825 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2827 case SHIFT_LSHIFTRT:
2829 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2831 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2833 case SHIFT_ASHIFTRT:
2834 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2838 else if ((8 <= count && count <= 13)
2839 || (TARGET_H8300S && count == 14))
2841 info->remainder = count - 8;
2846 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2848 case SHIFT_LSHIFTRT:
2851 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2852 info->shift1 = "shlr.b\t%s0";
2856 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
2859 case SHIFT_ASHIFTRT:
2862 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2863 info->shift1 = "shar.b\t%s0";
2867 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2872 else if (count == 14)
2878 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2880 case SHIFT_LSHIFTRT:
2882 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2884 case SHIFT_ASHIFTRT:
2886 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2887 else if (TARGET_H8300H)
2888 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2889 else /* TARGET_H8300S */
2894 else if (count == 15)
2899 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
2901 case SHIFT_LSHIFTRT:
2902 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
2904 case SHIFT_ASHIFTRT:
2905 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2912 if (TARGET_H8300 && 8 <= count && count <= 9)
2914 info->remainder = count - 8;
2919 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2921 case SHIFT_LSHIFTRT:
2922 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2923 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
2925 case SHIFT_ASHIFTRT:
2926 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2930 else if (count == 8 && !TARGET_H8300)
2935 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2937 case SHIFT_LSHIFTRT:
2938 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2940 case SHIFT_ASHIFTRT:
2941 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2945 else if (count == 15 && TARGET_H8300)
2951 case SHIFT_LSHIFTRT:
2952 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\trotxl\t%y0,%y0";
2954 case SHIFT_ASHIFTRT:
2955 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
2959 else if (count == 15 && !TARGET_H8300)
2964 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
2966 case SHIFT_LSHIFTRT:
2967 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
2969 case SHIFT_ASHIFTRT:
2973 else if ((TARGET_H8300 && 16 <= count && count <= 20)
2974 || (TARGET_H8300H && 16 <= count && count <= 19)
2975 || (TARGET_H8300S && 16 <= count && count <= 21))
2977 info->remainder = count - 16;
2982 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2984 info->shift1 = "add.w\t%e0,%e0";
2986 case SHIFT_LSHIFTRT:
2989 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2990 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
2994 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
2997 case SHIFT_ASHIFTRT:
3000 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3001 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3005 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3010 else if (TARGET_H8300 && 24 <= count && count <= 28)
3012 info->remainder = count - 24;
3017 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3018 info->shift1 = "shll.b\t%z0";
3020 case SHIFT_LSHIFTRT:
3021 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3022 info->shift1 = "shlr.b\t%w0";
3024 case SHIFT_ASHIFTRT:
3025 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3026 info->shift1 = "shar.b\t%w0";
3030 else if ((TARGET_H8300H && count == 24)
3031 || (TARGET_H8300S && 24 <= count && count <= 25))
3033 info->remainder = count - 24;
3038 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3040 case SHIFT_LSHIFTRT:
3041 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3043 case SHIFT_ASHIFTRT:
3044 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3048 else if (!TARGET_H8300 && count == 28)
3054 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3056 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3058 case SHIFT_LSHIFTRT:
3060 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3062 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3064 case SHIFT_ASHIFTRT:
3068 else if (!TARGET_H8300 && count == 29)
3074 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3076 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3078 case SHIFT_LSHIFTRT:
3080 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3082 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3084 case SHIFT_ASHIFTRT:
3088 else if (!TARGET_H8300 && count == 30)
3094 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3096 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3098 case SHIFT_LSHIFTRT:
3100 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3102 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3104 case SHIFT_ASHIFTRT:
3108 else if (count == 31)
3115 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3117 case SHIFT_LSHIFTRT:
3118 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3120 case SHIFT_ASHIFTRT:
3121 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3130 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3132 case SHIFT_LSHIFTRT:
3133 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3135 case SHIFT_ASHIFTRT:
3136 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3149 info->shift2 = NULL;
3152 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3153 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3156 h8300_shift_needs_scratch_p (count, mode)
3158 enum machine_mode mode;
3163 if (GET_MODE_BITSIZE (mode) <= count)
3166 /* Find out the target CPU. */
3169 else if (TARGET_H8300H)
3174 /* Find the shift algorithm. */
3178 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3179 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3180 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3184 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3185 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3186 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3190 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3191 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3192 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3199 /* On H8/300H and H8S, count == 8 uses the scratch register. */
3200 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3201 || (TARGET_H8300H && mode == SImode && count == 8));
3204 /* Emit the assembler code for doing shifts. */
3207 output_a_shift (operands)
3210 static int loopend_lab;
3211 rtx shift = operands[3];
3212 enum machine_mode mode = GET_MODE (shift);
3213 enum rtx_code code = GET_CODE (shift);
3214 enum shift_type shift_type;
3215 enum shift_mode shift_mode;
3216 struct shift_info info;
3223 shift_mode = QIshift;
3226 shift_mode = HIshift;
3229 shift_mode = SIshift;
3238 shift_type = SHIFT_ASHIFTRT;
3241 shift_type = SHIFT_LSHIFTRT;
3244 shift_type = SHIFT_ASHIFT;
3250 if (GET_CODE (operands[2]) != CONST_INT)
3252 /* This case must be taken care of by one of the two splitters
3253 that convert a variable shift into a loop. */
3258 int n = INTVAL (operands[2]);
3260 /* If the count is negative, make it 0. */
3263 /* If the count is too big, truncate it.
3264 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3265 do the intuitive thing. */
3266 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3267 n = GET_MODE_BITSIZE (mode);
3269 get_shift_alg (shift_type, shift_mode, n, &info);
3274 output_asm_insn (info.special, operands);
3280 /* Emit two bit shifts first. */
3281 if (info.shift2 != NULL)
3283 for (; n > 1; n -= 2)
3284 output_asm_insn (info.shift2, operands);
3287 /* Now emit one bit shifts for any residual. */
3289 output_asm_insn (info.shift1, operands);
3291 /* Keep track of CC. */
3292 if (info.cc_valid_p)
3294 cc_status.value1 = operands[0];
3295 cc_status.flags |= info.cc_valid_p;
3301 int m = GET_MODE_BITSIZE (mode) - n;
3302 const int mask = (shift_type == SHIFT_ASHIFT
3303 ? ((1 << m) - 1) << n
3307 /* Not all possibilities of rotate are supported. They shouldn't
3308 be generated, but let's watch for 'em. */
3309 if (info.shift1 == 0)
3312 /* Emit two bit rotates first. */
3313 if (info.shift2 != NULL)
3315 for (; m > 1; m -= 2)
3316 output_asm_insn (info.shift2, operands);
3319 /* Now single bit rotates for any residual. */
3321 output_asm_insn (info.shift1, operands);
3323 /* Now mask off the high bits. */
3325 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3326 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3327 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3331 cc_status.value1 = operands[0];
3332 cc_status.flags |= CC_NO_CARRY;
3333 output_asm_insn (insn_buf, operands);
3338 /* A loop to shift by a "large" constant value.
3339 If we have shift-by-2 insns, use them. */
3340 if (info.shift2 != NULL)
3342 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3343 names_big[REGNO (operands[4])]);
3344 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3345 output_asm_insn (info.shift2, operands);
3346 output_asm_insn ("add #0xff,%X4", operands);
3347 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3349 output_asm_insn (info.shift1, operands);
3353 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3354 names_big[REGNO (operands[4])]);
3355 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3356 output_asm_insn (info.shift1, operands);
3357 output_asm_insn ("add #0xff,%X4", operands);
3358 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3369 h8300_asm_insn_count (template)
3370 const char *template;
3372 unsigned int count = 1;
3374 for (; *template; template++)
3375 if (*template == '\n')
3382 compute_a_shift_length (insn, operands)
3383 rtx insn ATTRIBUTE_UNUSED;
3386 rtx shift = operands[3];
3387 enum machine_mode mode = GET_MODE (shift);
3388 enum rtx_code code = GET_CODE (shift);
3389 enum shift_type shift_type;
3390 enum shift_mode shift_mode;
3391 struct shift_info info;
3392 unsigned int wlength = 0;
3397 shift_mode = QIshift;
3400 shift_mode = HIshift;
3403 shift_mode = SIshift;
3412 shift_type = SHIFT_ASHIFTRT;
3415 shift_type = SHIFT_LSHIFTRT;
3418 shift_type = SHIFT_ASHIFT;
3424 if (GET_CODE (operands[2]) != CONST_INT)
3426 /* Get the assembler code to do one shift. */
3427 get_shift_alg (shift_type, shift_mode, 1, &info);
3429 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3433 int n = INTVAL (operands[2]);
3435 /* If the count is negative, make it 0. */
3438 /* If the count is too big, truncate it.
3439 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3440 do the intuitive thing. */
3441 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3442 n = GET_MODE_BITSIZE (mode);
3444 get_shift_alg (shift_type, shift_mode, n, &info);
3449 wlength += h8300_asm_insn_count (info.special);
3451 /* Every assembly instruction used in SHIFT_SPECIAL case
3452 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3453 see xor.l, we just pretend that xor.l counts as two insns
3454 so that the insn length will be computed correctly. */
3455 if (strstr (info.special, "xor.l") != NULL)
3463 if (info.shift2 != NULL)
3465 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3469 wlength += h8300_asm_insn_count (info.shift1) * n;
3475 int m = GET_MODE_BITSIZE (mode) - n;
3477 /* Not all possibilities of rotate are supported. They shouldn't
3478 be generated, but let's watch for 'em. */
3479 if (info.shift1 == 0)
3482 if (info.shift2 != NULL)
3484 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3488 wlength += h8300_asm_insn_count (info.shift1) * m;
3490 /* Now mask off the high bits. */
3511 /* A loop to shift by a "large" constant value.
3512 If we have shift-by-2 insns, use them. */
3513 if (info.shift2 != NULL)
3515 wlength += 3 + h8300_asm_insn_count (info.shift2);
3517 wlength += h8300_asm_insn_count (info.shift1);
3521 wlength += 3 + h8300_asm_insn_count (info.shift1);
3531 /* A rotation by a non-constant will cause a loop to be generated, in
3532 which a rotation by one bit is used. A rotation by a constant,
3533 including the one in the loop, will be taken care of by
3534 emit_a_rotate () at the insn emit time. */
3537 expand_a_rotate (code, operands)
3541 rtx dst = operands[0];
3542 rtx src = operands[1];
3543 rtx rotate_amount = operands[2];
3544 enum machine_mode mode = GET_MODE (dst);
3547 /* We rotate in place. */
3548 emit_move_insn (dst, src);
3550 if (GET_CODE (rotate_amount) != CONST_INT)
3552 rtx counter = gen_reg_rtx (QImode);
3553 rtx start_label = gen_label_rtx ();
3554 rtx end_label = gen_label_rtx ();
3556 /* If the rotate amount is less than or equal to 0,
3557 we go out of the loop. */
3558 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3559 QImode, 0, end_label);
3561 /* Initialize the loop counter. */
3562 emit_move_insn (counter, rotate_amount);
3564 emit_label (start_label);
3566 /* Rotate by one bit. */
3567 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3568 emit_insn (gen_rtx_SET (mode, dst, tmp));
3570 /* Decrement the counter by 1. */
3571 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3572 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3574 /* If the loop counter is nonzero, we go back to the beginning
3576 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3579 emit_label (end_label);
3583 /* Rotate by AMOUNT bits. */
3584 tmp = gen_rtx (code, mode, dst, rotate_amount);
3585 emit_insn (gen_rtx_SET (mode, dst, tmp));
3591 /* Emit rotate insns. */
3594 emit_a_rotate (code, operands)
3598 rtx dst = operands[0];
3599 rtx rotate_amount = operands[2];
3600 enum shift_mode rotate_mode;
3601 enum shift_type rotate_type;
3602 const char *insn_buf;
3605 enum machine_mode mode = GET_MODE (dst);
3607 if (GET_CODE (rotate_amount) != CONST_INT)
3613 rotate_mode = QIshift;
3616 rotate_mode = HIshift;
3619 rotate_mode = SIshift;
3628 rotate_type = SHIFT_ASHIFT;
3631 rotate_type = SHIFT_LSHIFTRT;
3637 amount = INTVAL (rotate_amount);
3639 /* Clean up AMOUNT. */
3642 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3643 amount = GET_MODE_BITSIZE (mode);
3645 /* Determine the faster direction. After this phase, amount will be
3646 at most a half of GET_MODE_BITSIZE (mode). */
3647 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3649 /* Flip the direction. */
3650 amount = GET_MODE_BITSIZE (mode) - amount;
3652 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3655 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3656 boost up the rotation. */
3657 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3658 || (mode == HImode && TARGET_H8300H && amount >= 6)
3659 || (mode == HImode && TARGET_H8300S && amount == 8)
3660 || (mode == SImode && TARGET_H8300H && amount >= 10)
3661 || (mode == SImode && TARGET_H8300S && amount >= 13))
3666 /* This code works on any family. */
3667 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3668 output_asm_insn (insn_buf, operands);
3672 /* This code works on the H8/300H and H8S. */
3673 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3674 output_asm_insn (insn_buf, operands);
3681 /* Adjust AMOUNT and flip the direction. */
3682 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3684 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3687 /* Emit rotate insns. */
3688 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3691 insn_buf = rotate_two[rotate_type][rotate_mode];
3693 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3695 for (; amount >= bits; amount -= bits)
3696 output_asm_insn (insn_buf, operands);
3702 /* Fix the operands of a gen_xxx so that it could become a bit
3706 fix_bit_operand (operands, what, type)
3711 /* The bit_operand predicate accepts any memory during RTL generation, but
3712 only 'U' memory afterwards, so if this is a MEM operand, we must force
3713 it to be valid for 'U' by reloading the address. */
3715 if ((what == 0 && single_zero_operand (operands[2], QImode))
3716 || (what == 1 && single_one_operand (operands[2], QImode)))
3718 /* OK to have a memory dest. */
3719 if (GET_CODE (operands[0]) == MEM
3720 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3722 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3723 copy_to_mode_reg (Pmode,
3724 XEXP (operands[0], 0)));
3725 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3729 if (GET_CODE (operands[1]) == MEM
3730 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3732 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3733 copy_to_mode_reg (Pmode,
3734 XEXP (operands[1], 0)));
3735 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3741 /* Dest and src op must be register. */
3743 operands[1] = force_reg (QImode, operands[1]);
3745 rtx res = gen_reg_rtx (QImode);
3746 emit_insn (gen_rtx_SET (VOIDmode, res,
3747 gen_rtx (type, QImode, operands[1], operands[2])));
3748 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3753 /* Return nonzero if FUNC is an interrupt function as specified
3754 by the "interrupt" attribute. */
3757 h8300_interrupt_function_p (func)
3762 if (TREE_CODE (func) != FUNCTION_DECL)
3765 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3766 return a != NULL_TREE;
3769 /* Return nonzero if FUNC is an OS_Task function as specified
3770 by the "OS_Task" attribute. */
3773 h8300_os_task_function_p (func)
3778 if (TREE_CODE (func) != FUNCTION_DECL)
3781 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3782 return a != NULL_TREE;
3785 /* Return nonzero if FUNC is a monitor function as specified
3786 by the "monitor" attribute. */
3789 h8300_monitor_function_p (func)
3794 if (TREE_CODE (func) != FUNCTION_DECL)
3797 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
3798 return a != NULL_TREE;
3801 /* Return nonzero if FUNC is a function that should be called
3802 through the function vector. */
3805 h8300_funcvec_function_p (func)
3810 if (TREE_CODE (func) != FUNCTION_DECL)
3813 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
3814 return a != NULL_TREE;
3817 /* Return nonzero if DECL is a variable that's in the eight bit
3821 h8300_eightbit_data_p (decl)
3826 if (TREE_CODE (decl) != VAR_DECL)
3829 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
3830 return a != NULL_TREE;
3833 /* Return nonzero if DECL is a variable that's in the tiny
3837 h8300_tiny_data_p (decl)
3842 if (TREE_CODE (decl) != VAR_DECL)
3845 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
3846 return a != NULL_TREE;
3849 /* Generate an 'interrupt_handler' attribute for decls. */
3852 h8300_insert_attributes (node, attributes)
3856 if (!pragma_interrupt
3857 || TREE_CODE (node) != FUNCTION_DECL)
3860 pragma_interrupt = 0;
3862 /* Add an 'interrupt_handler' attribute. */
3863 *attributes = tree_cons (get_identifier ("interrupt_handler"),
3867 /* Supported attributes:
3869 interrupt_handler: output a prologue and epilogue suitable for an
3872 function_vector: This function should be called through the
3875 eightbit_data: This variable lives in the 8-bit data area and can
3876 be referenced with 8-bit absolute memory addresses.
3878 tiny_data: This variable lives in the tiny data area and can be
3879 referenced with 16-bit absolute memory references. */
3881 const struct attribute_spec h8300_attribute_table[] =
3883 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3884 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3885 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3886 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3887 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3888 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
3889 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
3890 { NULL, 0, 0, false, false, false, NULL }
3894 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
3895 struct attribute_spec.handler. */
3897 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
3900 tree args ATTRIBUTE_UNUSED;
3901 int flags ATTRIBUTE_UNUSED;
3904 if (TREE_CODE (*node) != FUNCTION_DECL)
3906 warning ("`%s' attribute only applies to functions",
3907 IDENTIFIER_POINTER (name));
3908 *no_add_attrs = true;
3914 /* Handle an "eightbit_data" attribute; arguments as in
3915 struct attribute_spec.handler. */
3917 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
3920 tree args ATTRIBUTE_UNUSED;
3921 int flags ATTRIBUTE_UNUSED;
3926 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3928 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3932 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3933 *no_add_attrs = true;
3939 /* Handle an "tiny_data" attribute; arguments as in
3940 struct attribute_spec.handler. */
3942 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
3945 tree args ATTRIBUTE_UNUSED;
3946 int flags ATTRIBUTE_UNUSED;
3951 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3953 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3957 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3958 *no_add_attrs = true;
3965 h8300_encode_label (decl)
3968 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3969 const int len = strlen (str);
3970 char *newstr = alloca (len + 2);
3973 strcpy (&newstr[1], str);
3975 XSTR (XEXP (DECL_RTL (decl), 0), 0) =
3976 ggc_alloc_string (newstr, len + 1);
3979 /* If we are referencing a function that is supposed to be called
3980 through the function vector, the SYMBOL_REF_FLAG in the rtl
3981 so the call patterns can generate the correct code. */
3984 h8300_encode_section_info (decl, first)
3988 if (TREE_CODE (decl) == FUNCTION_DECL
3989 && h8300_funcvec_function_p (decl))
3990 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
3991 else if (TREE_CODE (decl) == VAR_DECL
3992 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3994 if (h8300_eightbit_data_p (decl))
3995 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
3996 else if (first && h8300_tiny_data_p (decl))
3997 h8300_encode_label (decl);
4001 /* Undo the effects of the above. */
4004 h8300_strip_name_encoding (str)
4007 return str + (*str == '*' || *str == '@' || *str == '&');
4011 output_simode_bld (bild, operands)
4017 /* Clear the destination register. */
4018 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4020 /* Now output the bit load or bit inverse load, and store it in
4023 output_asm_insn ("bild\t%Z2,%Y1", operands);
4025 output_asm_insn ("bld\t%Z2,%Y1", operands);
4027 output_asm_insn ("bst\t#0,%w0", operands);
4031 /* Output the bit load or bit inverse load. */
4033 output_asm_insn ("bild\t%Z2,%Y1", operands);
4035 output_asm_insn ("bld\t%Z2,%Y1", operands);
4037 /* Clear the destination register and perform the bit store. */
4038 output_asm_insn ("xor.l\t%S0,%S0\n\tbst\t#0,%w0", operands);
4045 /* Given INSN and its current length LENGTH, return the adjustment
4046 (in bytes) to correctly compute INSN's length.
4048 We use this to get the lengths of various memory references correct. */
4051 h8300_adjust_insn_length (insn, length)
4053 int length ATTRIBUTE_UNUSED;
4055 rtx pat = PATTERN (insn);
4057 /* We must filter these out before calling get_attr_adjust_length. */
4058 if (GET_CODE (pat) == USE
4059 || GET_CODE (pat) == CLOBBER
4060 || GET_CODE (pat) == SEQUENCE
4061 || GET_CODE (pat) == ADDR_VEC
4062 || GET_CODE (pat) == ADDR_DIFF_VEC)
4065 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
4068 /* Adjust length for reg->mem and mem->reg copies. */
4069 if (GET_CODE (pat) == SET
4070 && (GET_CODE (SET_SRC (pat)) == MEM
4071 || GET_CODE (SET_DEST (pat)) == MEM))
4073 /* This insn might need a length adjustment. */
4076 if (GET_CODE (SET_SRC (pat)) == MEM)
4077 addr = XEXP (SET_SRC (pat), 0);
4079 addr = XEXP (SET_DEST (pat), 0);
4083 /* On the H8/300, we subtract the difference between the
4084 actual length and the longest one, which is @(d:16,ERs). */
4086 /* @Rs is 2 bytes shorter than the longest. */
4087 if (GET_CODE (addr) == REG)
4090 /* @aa:8 is 2 bytes shorter than the longest. */
4091 if (GET_MODE (SET_SRC (pat)) == QImode
4092 && h8300_eightbit_constant_address_p (addr))
4097 /* On the H8/300H and H8S, we subtract the difference
4098 between the actual length and the longest one, which is
4101 /* @ERs is 6 bytes shorter than the longest. */
4102 if (GET_CODE (addr) == REG)
4105 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4106 if (GET_CODE (addr) == PLUS
4107 && GET_CODE (XEXP (addr, 0)) == REG
4108 && GET_CODE (XEXP (addr, 1)) == CONST_INT
4109 && INTVAL (XEXP (addr, 1)) > -32768
4110 && INTVAL (XEXP (addr, 1)) < 32767)
4113 /* @aa:8 is 6 bytes shorter than the longest. */
4114 if (GET_MODE (SET_SRC (pat)) == QImode
4115 && h8300_eightbit_constant_address_p (addr))
4118 /* @aa:16 is 4 bytes shorter than the longest. */
4119 if (h8300_tiny_constant_address_p (addr))
4122 /* @aa:24 is 2 bytes shorter than the longest. */
4123 if (GET_CODE (addr) == CONST_INT)
4128 /* Loading some constants needs adjustment. */
4129 if (GET_CODE (pat) == SET
4130 && GET_CODE (SET_SRC (pat)) == CONST_INT
4131 && GET_MODE (SET_DEST (pat)) == SImode
4132 && INTVAL (SET_SRC (pat)) != 0)
4134 int val = INTVAL (SET_SRC (pat));
4137 && ((val & 0xffff) == 0
4138 || ((val >> 16) & 0xffff) == 0))
4141 if (TARGET_H8300H || TARGET_H8300S)
4143 if (val == (val & 0xff)
4144 || val == (val & 0xff00))
4147 switch (val & 0xffffffff)
4163 /* Rotations need various adjustments. */
4164 if (GET_CODE (pat) == SET
4165 && (GET_CODE (SET_SRC (pat)) == ROTATE
4166 || GET_CODE (SET_SRC (pat)) == ROTATERT))
4168 rtx src = SET_SRC (pat);
4169 enum machine_mode mode = GET_MODE (src);
4173 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
4176 amount = INTVAL (XEXP (src, 1));
4178 /* Clean up AMOUNT. */
4181 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4182 amount = GET_MODE_BITSIZE (mode);
4184 /* Determine the faster direction. After this phase, amount
4185 will be at most a half of GET_MODE_BITSIZE (mode). */
4186 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4187 /* Flip the direction. */
4188 amount = GET_MODE_BITSIZE (mode) - amount;
4190 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4191 boost up the rotation. */
4192 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4193 || (mode == HImode && TARGET_H8300H && amount >= 6)
4194 || (mode == HImode && TARGET_H8300S && amount == 8)
4195 || (mode == SImode && TARGET_H8300H && amount >= 10)
4196 || (mode == SImode && TARGET_H8300S && amount >= 13))
4198 /* Adjust AMOUNT and flip the direction. */
4199 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4203 /* We use 2-bit rotations on the H8S. */
4205 amount = amount / 2 + amount % 2;
4207 /* The H8/300 uses three insns to rotate one bit, taking 6
4209 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4211 return -(20 - states);
4217 #ifndef OBJECT_FORMAT_ELF
4219 h8300_asm_named_section (name, flags)
4221 unsigned int flags ATTRIBUTE_UNUSED;
4223 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4224 fprintf (asm_out_file, "\t.section %s\n", name);
4226 #endif /* ! OBJECT_FORMAT_ELF */
4228 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4229 which is a special case of the 'R' operand. */
4232 h8300_eightbit_constant_address_p (x)
4235 /* The ranges of the 8-bit area. */
4236 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4237 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4238 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4239 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4240 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4241 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4243 unsigned HOST_WIDE_INT addr;
4245 /* We accept symbols declared with eightbit_data. */
4246 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_FLAG (x))
4249 if (GET_CODE (x) != CONST_INT)
4255 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4256 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4257 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4260 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4261 on H8/300H and H8S. */
4264 h8300_tiny_constant_address_p (x)
4267 /* The ranges of the 16-bit area. */
4268 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4269 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4270 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4271 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4272 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4273 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4274 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4275 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4277 unsigned HOST_WIDE_INT addr;
4279 /* We accept symbols declared with tiny_data. */
4280 if (GET_CODE (x) == SYMBOL_REF && TINY_DATA_NAME_P (XSTR (x, 0)))
4283 if (GET_CODE (x) != CONST_INT)
4289 || ((TARGET_H8300H && !TARGET_NORMAL_MODE)
4290 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4291 || ((TARGET_H8300S && !TARGET_NORMAL_MODE)
4292 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));