1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg PARAMS ((rtx, int));
50 static int h8300_interrupt_function_p PARAMS ((tree));
51 static int h8300_monitor_function_p PARAMS ((tree));
52 static int h8300_os_task_function_p PARAMS ((tree));
53 static void dosize PARAMS ((int, unsigned int));
54 static int round_frame_size PARAMS ((int));
55 static unsigned int compute_saved_regs PARAMS ((void));
56 static void push PARAMS ((int));
57 static void pop PARAMS ((int));
58 static const char *cond_string PARAMS ((enum rtx_code));
59 static unsigned int h8300_asm_insn_count PARAMS ((const char *));
60 const struct attribute_spec h8300_attribute_table[];
61 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
62 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
63 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
64 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
65 static void h8300_insert_attributes PARAMS ((tree, tree *));
66 static void h8300_file_end PARAMS ((void));
67 #ifndef OBJECT_FORMAT_ELF
68 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
70 static void h8300_encode_section_info PARAMS ((tree, rtx, int));
71 static int const_costs PARAMS ((rtx, enum rtx_code, enum rtx_code));
72 static int h8300_and_costs PARAMS ((rtx));
73 static int h8300_shift_costs PARAMS ((rtx));
74 static bool h8300_rtx_costs PARAMS ((rtx, int, int, int *));
76 /* CPU_TYPE, says what cpu we're compiling for. */
79 /* True if a #pragma interrupt has been seen for the current function. */
80 static int pragma_interrupt;
82 /* True if a #pragma saveall has been seen for the current function. */
83 static int pragma_saveall;
85 static const char *const names_big[] =
86 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
88 static const char *const names_extended[] =
89 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
91 static const char *const names_upper_extended[] =
92 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
94 /* Points to one of the above. */
95 /* ??? The above could be put in an array indexed by CPU_TYPE. */
96 const char * const *h8_reg_names;
98 /* Various operations needed by the following, indexed by CPU_TYPE. */
100 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
102 /* Machine-specific symbol_ref flags. */
103 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
104 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
105 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
107 /* Initialize the GCC target structure. */
108 #undef TARGET_ATTRIBUTE_TABLE
109 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
111 #undef TARGET_ASM_ALIGNED_HI_OP
112 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
114 #undef TARGET_ASM_FUNCTION_EPILOGUE
115 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
117 #undef TARGET_ASM_FILE_END
118 #define TARGET_ASM_FILE_END h8300_file_end
120 #undef TARGET_ENCODE_SECTION_INFO
121 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
123 #undef TARGET_INSERT_ATTRIBUTES
124 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
126 #undef TARGET_RTX_COSTS
127 #define TARGET_RTX_COSTS h8300_rtx_costs
129 struct gcc_target targetm = TARGET_INITIALIZER;
131 /* See below where shifts are handled for explanation of this enum. */
141 /* Symbols of the various shifts which can be used as indices. */
145 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
148 /* Macros to keep the shift algorithm tables small. */
149 #define INL SHIFT_INLINE
150 #define ROT SHIFT_ROT_AND
151 #define LOP SHIFT_LOOP
152 #define SPC SHIFT_SPECIAL
154 /* The shift algorithms for each machine, mode, shift type, and shift
155 count are defined below. The three tables below correspond to
156 QImode, HImode, and SImode, respectively. Each table is organized
157 by, in the order of indices, machine, shift type, and shift count. */
159 static enum shift_alg shift_alg_qi[3][3][8] = {
162 /* 0 1 2 3 4 5 6 7 */
163 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
164 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
165 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
169 /* 0 1 2 3 4 5 6 7 */
170 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
171 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
172 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
176 /* 0 1 2 3 4 5 6 7 */
177 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
178 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
179 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
183 static enum shift_alg shift_alg_hi[3][3][16] = {
186 /* 0 1 2 3 4 5 6 7 */
187 /* 8 9 10 11 12 13 14 15 */
188 { INL, INL, INL, INL, INL, INL, INL, SPC,
189 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
190 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
191 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
192 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
193 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
197 /* 0 1 2 3 4 5 6 7 */
198 /* 8 9 10 11 12 13 14 15 */
199 { INL, INL, INL, INL, INL, INL, INL, SPC,
200 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, INL, INL, INL, INL, SPC,
202 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
203 { INL, INL, INL, INL, INL, INL, INL, SPC,
204 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
208 /* 0 1 2 3 4 5 6 7 */
209 /* 8 9 10 11 12 13 14 15 */
210 { INL, INL, INL, INL, INL, INL, INL, INL,
211 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
212 { INL, INL, INL, INL, INL, INL, INL, INL,
213 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
214 { INL, INL, INL, INL, INL, INL, INL, INL,
215 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
219 static enum shift_alg shift_alg_si[3][3][32] = {
222 /* 0 1 2 3 4 5 6 7 */
223 /* 8 9 10 11 12 13 14 15 */
224 /* 16 17 18 19 20 21 22 23 */
225 /* 24 25 26 27 28 29 30 31 */
226 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
228 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
229 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
230 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
231 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
232 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
233 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
234 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
235 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
236 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
237 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
241 /* 0 1 2 3 4 5 6 7 */
242 /* 8 9 10 11 12 13 14 15 */
243 /* 16 17 18 19 20 21 22 23 */
244 /* 24 25 26 27 28 29 30 31 */
245 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
246 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
247 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
248 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
249 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
250 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
251 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
252 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
253 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
254 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
255 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
256 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
260 /* 0 1 2 3 4 5 6 7 */
261 /* 8 9 10 11 12 13 14 15 */
262 /* 16 17 18 19 20 21 22 23 */
263 /* 24 25 26 27 28 29 30 31 */
264 { INL, INL, INL, INL, INL, INL, INL, INL,
265 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
266 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
267 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
268 { INL, INL, INL, INL, INL, INL, INL, INL,
269 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
270 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
271 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
272 { INL, INL, INL, INL, INL, INL, INL, INL,
273 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
274 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
275 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
291 /* Initialize various cpu specific globals at start up. */
296 static const char *const h8_push_ops[2] = { "push" , "push.l" };
297 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
298 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
302 cpu_type = (int) CPU_H8300;
303 h8_reg_names = names_big;
307 /* For this we treat the H8/300H and H8S the same. */
308 cpu_type = (int) CPU_H8300H;
309 h8_reg_names = names_extended;
311 h8_push_op = h8_push_ops[cpu_type];
312 h8_pop_op = h8_pop_ops[cpu_type];
313 h8_mov_op = h8_mov_ops[cpu_type];
315 if (!TARGET_H8300S && TARGET_MAC)
317 error ("-ms2600 is used without -ms");
318 target_flags |= MASK_H8300S;
321 if (TARGET_H8300 && TARGET_NORMAL_MODE)
323 error ("-mn is used without -mh or -ms");
324 target_flags ^= MASK_NORMAL_MODE;
327 /* Some of the shifts are optimized for speed by default.
328 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
329 If optimizing for size, change shift_alg for those shift to
334 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
335 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
336 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
337 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
339 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
340 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
342 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
343 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
346 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
347 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
349 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
350 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
352 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
353 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
354 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
355 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
358 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
367 static const char *const names_small[] = {
368 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
369 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
372 return names_small[REGNO (x) * 2 + b];
375 /* REGNO must be saved/restored across calls if this macro is true. */
377 #define WORD_REG_USED(regno) \
379 /* No need to save registers if this function will not return. */ \
380 && ! TREE_THIS_VOLATILE (current_function_decl) \
382 /* Save any call saved register that was used. */ \
383 || (regs_ever_live[regno] && !call_used_regs[regno]) \
384 /* Save the frame pointer if it was used. */ \
385 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
386 /* Save any register used in an interrupt handler. */ \
387 || (h8300_current_function_interrupt_function_p () \
388 && regs_ever_live[regno]) \
389 /* Save call clobbered registers in non-leaf interrupt \
391 || (h8300_current_function_interrupt_function_p () \
392 && call_used_regs[regno] \
393 && !current_function_is_leaf)))
395 /* Output assembly language to FILE for the operation OP with operand size
396 SIZE to adjust the stack pointer. */
403 /* H8/300 cannot add/subtract a large constant with a single
404 instruction. If a temporary register is available, load the
405 constant to it and then do the addition. */
408 && !h8300_current_function_interrupt_function_p ()
409 && !(current_function_needs_context && sign < 0))
412 rtx r3 = gen_rtx_REG (Pmode, 3);
413 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
414 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
415 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
419 /* The stack adjustment made here is further optimized by the
420 splitter. In case of H8/300, the splitter always splits the
421 addition emitted here to make the adjustment
423 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
424 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
428 /* Round up frame size SIZE. */
431 round_frame_size (size)
434 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
435 & -STACK_BOUNDARY / BITS_PER_UNIT);
438 /* Compute which registers to push/pop.
439 Return a bit vector of registers. */
442 compute_saved_regs ()
444 unsigned int saved_regs = 0;
447 /* Construct a bit vector of registers to be pushed/popped. */
448 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
450 if (WORD_REG_USED (regno))
451 saved_regs |= 1 << regno;
454 /* Don't push/pop the frame pointer as it is treated separately. */
455 if (frame_pointer_needed)
456 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
461 /* Emit an insn to push register RN. */
467 rtx reg = gen_rtx_REG (word_mode, rn);
471 x = gen_push_h8300 (reg);
473 x = gen_push_h8300hs (reg);
475 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
478 /* Emit an insn to pop register RN. */
484 rtx reg = gen_rtx_REG (word_mode, rn);
488 x = gen_pop_h8300 (reg);
490 x = gen_pop_h8300hs (reg);
492 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
495 /* This is what the stack looks like after the prolog of
496 a function with a frame has been set up:
502 <saved registers> <- sp
504 This is what the stack looks like after the prolog of
505 a function which doesn't have a frame:
510 <saved registers> <- sp
513 /* Generate RTL code for the function prologue. */
516 h8300_expand_prologue ()
522 /* If the current function has the OS_Task attribute set, then
523 we have a naked prologue. */
524 if (h8300_os_task_function_p (current_function_decl))
527 if (h8300_monitor_function_p (current_function_decl))
528 /* My understanding of monitor functions is they act just like
529 interrupt functions, except the prologue must mask
531 emit_insn (gen_monitor_prologue ());
533 if (frame_pointer_needed)
536 push (FRAME_POINTER_REGNUM);
537 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
540 /* Leave room for locals. */
541 dosize (-1, round_frame_size (get_frame_size ()));
543 /* Push the rest of the registers in ascending order. */
544 saved_regs = compute_saved_regs ();
545 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
548 if (saved_regs & (1 << regno))
552 /* See how many registers we can push at the same time. */
553 if ((regno == 0 || regno == 4)
554 && ((saved_regs >> regno) & 0x0f) == 0x0f)
557 else if ((regno == 0 || regno == 4)
558 && ((saved_regs >> regno) & 0x07) == 0x07)
561 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
562 && ((saved_regs >> regno) & 0x03) == 0x03)
572 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
573 gen_rtx_REG (SImode, regno + 1)));
576 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
577 gen_rtx_REG (SImode, regno + 1),
578 gen_rtx_REG (SImode, regno + 2)));
581 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
582 gen_rtx_REG (SImode, regno + 1),
583 gen_rtx_REG (SImode, regno + 2),
584 gen_rtx_REG (SImode, regno + 3)));
594 h8300_can_use_return_insn_p ()
596 return (reload_completed
597 && !frame_pointer_needed
598 && get_frame_size () == 0
599 && compute_saved_regs () == 0);
602 /* Generate RTL code for the function epilogue. */
605 h8300_expand_epilogue ()
611 if (h8300_os_task_function_p (current_function_decl))
612 /* OS_Task epilogues are nearly naked -- they just have an
616 /* Pop the saved registers in descending order. */
617 saved_regs = compute_saved_regs ();
618 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
621 if (saved_regs & (1 << regno))
625 /* See how many registers we can pop at the same time. */
626 if ((regno == 7 || regno == 3)
627 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
630 else if ((regno == 6 || regno == 2)
631 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
634 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
635 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
645 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
646 gen_rtx_REG (SImode, regno)));
649 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
650 gen_rtx_REG (SImode, regno - 1),
651 gen_rtx_REG (SImode, regno)));
654 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
655 gen_rtx_REG (SImode, regno - 2),
656 gen_rtx_REG (SImode, regno - 1),
657 gen_rtx_REG (SImode, regno)));
665 /* Deallocate locals. */
666 dosize (1, round_frame_size (get_frame_size ()));
668 /* Pop frame pointer if we had one. */
669 if (frame_pointer_needed)
670 pop (FRAME_POINTER_REGNUM);
673 /* Output assembly language code for the function epilogue. */
676 h8300_output_function_epilogue (file, size)
677 FILE *file ATTRIBUTE_UNUSED;
678 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
683 /* Return nonzero if the current function is an interrupt
687 h8300_current_function_interrupt_function_p ()
689 return (h8300_interrupt_function_p (current_function_decl)
690 || h8300_monitor_function_p (current_function_decl));
693 /* Output assembly code for the start of the file. */
696 asm_file_start (file)
699 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
700 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
703 fprintf (file, "; -Os\n");
705 fprintf (file, "; -O%d\n", optimize);
707 if (TARGET_NORMAL_MODE)
708 fprintf (file, "\n\t.h8300hn\n");
710 fprintf (file, "\n\t.h8300h\n");
711 else if (TARGET_H8300S)
712 if (TARGET_NORMAL_MODE)
713 fprintf (file, "\n\t.h8300sn\n");
715 fprintf (file, "\n\t.h8300s\n");
717 fprintf (file, "\n\n");
718 output_file_directive (file, main_input_filename);
721 /* Output assembly language code for the end of file. */
726 fputs ("\t.end\n", asm_out_file);
729 /* Return true if OP is a valid source operand for an integer move
733 general_operand_src (op, mode)
735 enum machine_mode mode;
737 if (GET_MODE (op) == mode
738 && GET_CODE (op) == MEM
739 && GET_CODE (XEXP (op, 0)) == POST_INC)
741 return general_operand (op, mode);
744 /* Return true if OP is a valid destination operand for an integer move
748 general_operand_dst (op, mode)
750 enum machine_mode mode;
752 if (GET_MODE (op) == mode
753 && GET_CODE (op) == MEM
754 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
756 return general_operand (op, mode);
759 /* Return true if OP is a constant that contains only one 1 in its
760 binary representation. */
763 single_one_operand (operand, mode)
765 enum machine_mode mode ATTRIBUTE_UNUSED;
767 if (GET_CODE (operand) == CONST_INT)
769 /* We really need to do this masking because 0x80 in QImode is
770 represented as -128 for example. */
771 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
778 /* Return true if OP is a constant that contains only one 0 in its
779 binary representation. */
782 single_zero_operand (operand, mode)
784 enum machine_mode mode ATTRIBUTE_UNUSED;
786 if (GET_CODE (operand) == CONST_INT)
788 /* We really need to do this masking because 0x80 in QImode is
789 represented as -128 for example. */
790 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
797 /* Return true if OP is a valid call operand. */
800 call_insn_operand (op, mode)
802 enum machine_mode mode ATTRIBUTE_UNUSED;
804 if (GET_CODE (op) == MEM)
806 rtx inside = XEXP (op, 0);
807 if (register_operand (inside, Pmode))
809 if (CONSTANT_ADDRESS_P (inside))
815 /* Return 1 if an addition/subtraction of a constant integer can be
816 transformed into two consecutive adds/subs that are faster than the
817 straightforward way. Otherwise, return 0. */
820 two_insn_adds_subs_operand (op, mode)
822 enum machine_mode mode;
824 if (GET_CODE (op) == CONST_INT)
826 HOST_WIDE_INT value = INTVAL (op);
828 /* Force VALUE to be positive so that we do not have to consider
829 the negative case. */
832 if (TARGET_H8300H || TARGET_H8300S)
834 /* A constant addition/subtraction takes 2 states in QImode,
835 4 states in HImode, and 6 states in SImode. Thus, the
836 only case we can win is when SImode is used, in which
837 case, two adds/subs are used, taking 4 states. */
847 /* We do not profit directly by splitting addition or
848 subtraction of 3 and 4. However, since these are
849 implemented as a sequence of adds or subs, they do not
850 clobber (cc0) unlike a sequence of add.b and add.x. */
861 /* Split an add of a small constant into two adds/subs insns.
863 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
864 instead of adds/subs. */
867 split_adds_subs (mode, operands)
868 enum machine_mode mode;
871 HOST_WIDE_INT val = INTVAL (operands[1]);
872 rtx reg = operands[0];
873 HOST_WIDE_INT sign = 1;
874 HOST_WIDE_INT amount;
875 rtx (*gen_add) (rtx, rtx, rtx);
877 /* Force VAL to be positive so that we do not have to consider the
888 gen_add = gen_addhi3;
892 gen_add = gen_addsi3;
899 /* Try different amounts in descending order. */
900 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
904 for (; val >= amount; val -= amount)
905 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
911 /* Return true if OP is a valid call operand, and OP represents
912 an operand for a small call (4 bytes instead of 6 bytes). */
915 small_call_insn_operand (op, mode)
917 enum machine_mode mode ATTRIBUTE_UNUSED;
919 if (GET_CODE (op) == MEM)
921 rtx inside = XEXP (op, 0);
923 /* Register indirect is a small call. */
924 if (register_operand (inside, Pmode))
927 /* A call through the function vector is a small call too. */
928 if (GET_CODE (inside) == SYMBOL_REF
929 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
932 /* Otherwise it's a large call. */
936 /* Return true if OP is a valid jump operand. */
939 jump_address_operand (op, mode)
941 enum machine_mode mode;
943 if (GET_CODE (op) == REG)
944 return mode == Pmode;
946 if (GET_CODE (op) == MEM)
948 rtx inside = XEXP (op, 0);
949 if (register_operand (inside, Pmode))
951 if (CONSTANT_ADDRESS_P (inside))
957 /* Recognize valid operands for bit-field instructions. */
959 extern int rtx_equal_function_value_matters;
962 bit_operand (op, mode)
964 enum machine_mode mode;
966 /* We can accept any general operand, except that MEM operands must
967 be limited to those that use addresses valid for the 'U' constraint. */
968 if (!general_operand (op, mode))
971 /* Accept any mem during RTL generation. Otherwise, the code that does
972 insv and extzv will think that we can not handle memory. However,
973 to avoid reload problems, we only accept 'U' MEM operands after RTL
974 generation. This means that any named pattern which uses this predicate
975 must force its operands to match 'U' before emitting RTL. */
977 if (GET_CODE (op) == REG)
979 if (GET_CODE (op) == SUBREG)
981 return (GET_CODE (op) == MEM
982 && EXTRA_CONSTRAINT (op, 'U'));
986 bit_memory_operand (op, mode)
988 enum machine_mode mode ATTRIBUTE_UNUSED;
990 return (GET_CODE (op) == MEM
991 && EXTRA_CONSTRAINT (op, 'U'));
994 /* Handle machine specific pragmas for compatibility with existing
995 compilers for the H8/300.
997 pragma saveall generates prologue/epilogue code which saves and
998 restores all the registers on function entry.
1000 pragma interrupt saves and restores all registers, and exits with
1001 an rte instruction rather than an rts. A pointer to a function
1002 with this attribute may be safely used in an interrupt vector. */
1005 h8300_pr_interrupt (pfile)
1006 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1008 pragma_interrupt = 1;
1012 h8300_pr_saveall (pfile)
1013 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1018 /* If the next function argument with MODE and TYPE is to be passed in
1019 a register, return a reg RTX for the hard register in which to pass
1020 the argument. CUM represents the state after the last argument.
1021 If the argument is to be pushed, NULL_RTX is returned. */
1024 function_arg (cum, mode, type, named)
1025 CUMULATIVE_ARGS *cum;
1026 enum machine_mode mode;
1030 static const char *const hand_list[] = {
1049 rtx result = NULL_RTX;
1053 /* Never pass unnamed arguments in registers. */
1057 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1058 if (TARGET_QUICKCALL)
1061 /* If calling hand written assembler, use 4 regs of args. */
1064 const char * const *p;
1066 fname = XSTR (cum->libcall, 0);
1068 /* See if this libcall is one of the hand coded ones. */
1069 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1080 if (mode == BLKmode)
1081 size = int_size_in_bytes (type);
1083 size = GET_MODE_SIZE (mode);
1085 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1086 && cum->nbytes / UNITS_PER_WORD <= 3)
1087 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1093 /* Return the cost of the rtx R with code CODE. */
1096 const_costs (r, c, outer_code)
1099 enum rtx_code outer_code;
1105 HOST_WIDE_INT n = INTVAL (r);
1107 if (-4 <= n || n <= 4)
1117 return 0 + (outer_code == SET);
1120 if (TARGET_H8300H || TARGET_H8300S)
1121 return 0 + (outer_code == SET);
1148 if (GET_MODE (x) == QImode)
1151 if (GET_MODE (x) != HImode
1152 && GET_MODE (x) != SImode)
1157 operands[2] = XEXP (x, 1);
1159 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1163 h8300_shift_costs (x)
1168 if (GET_MODE (x) != QImode
1169 && GET_MODE (x) != HImode
1170 && GET_MODE (x) != SImode)
1175 operands[2] = XEXP (x, 1);
1177 return compute_a_shift_length (NULL, operands) / 2;
1181 h8300_rtx_costs (x, code, outer_code, total)
1183 int code, outer_code;
1189 *total = COSTS_N_INSNS (h8300_and_costs (x));
1192 /* We say that MOD and DIV are so expensive because otherwise we'll
1193 generate some really horrible code for division of a power of two. */
1206 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1211 if (GET_MODE (x) == HImode)
1218 *total = const_costs (x, code, outer_code);
1223 /* Documentation for the machine specific operand escapes:
1225 'E' like s but negative.
1226 'F' like t but negative.
1227 'G' constant just the negative
1228 'R' print operand as a byte:8 address if appropriate, else fall back to
1230 'S' print operand as a long word
1231 'T' print operand as a word
1232 'V' find the set bit, and print its number.
1233 'W' find the clear bit, and print its number.
1234 'X' print operand as a byte
1235 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1236 If this operand isn't a register, fall back to 'R' handling.
1238 'c' print the opcode corresponding to rtl
1239 'e' first word of 32 bit value - if reg, then least reg. if mem
1240 then least. if const then most sig word
1241 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1242 then +2. if const then least sig word
1243 'j' print operand as condition code.
1244 'k' print operand as reverse condition code.
1245 's' print as low byte of 16 bit value
1246 't' print as high byte of 16 bit value
1247 'w' print as low byte of 32 bit value
1248 'x' print as 2nd byte of 32 bit value
1249 'y' print as 3rd byte of 32 bit value
1250 'z' print as msb of 32 bit value
1253 /* Return assembly language string which identifies a comparison type. */
1286 /* Print operand X using operand code CODE to assembly language output file
1290 print_operand (file, x, code)
1295 /* This is used for communication between codes V,W,Z and Y. */
1301 switch (GET_CODE (x))
1304 fprintf (file, "%sl", names_big[REGNO (x)]);
1307 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1314 switch (GET_CODE (x))
1317 fprintf (file, "%sh", names_big[REGNO (x)]);
1320 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1327 if (GET_CODE (x) != CONST_INT)
1329 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1332 if (GET_CODE (x) == REG)
1333 fprintf (file, "%s", names_extended[REGNO (x)]);
1338 if (GET_CODE (x) == REG)
1339 fprintf (file, "%s", names_big[REGNO (x)]);
1344 bitint = exact_log2 (INTVAL (x) & 0xff);
1347 fprintf (file, "#%d", bitint);
1350 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1353 fprintf (file, "#%d", bitint);
1357 if (GET_CODE (x) == REG)
1358 fprintf (file, "%s", byte_reg (x, 0));
1365 if (GET_CODE (x) == REG)
1366 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1368 print_operand (file, x, 'R');
1372 bitint = INTVAL (x);
1373 fprintf (file, "#%d", bitint & 7);
1376 switch (GET_CODE (x))
1379 fprintf (file, "or");
1382 fprintf (file, "xor");
1385 fprintf (file, "and");
1392 switch (GET_CODE (x))
1396 fprintf (file, "%s", names_big[REGNO (x)]);
1398 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1401 print_operand (file, x, 0);
1404 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1410 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1411 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1412 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1421 switch (GET_CODE (x))
1425 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1427 fprintf (file, "%s", names_big[REGNO (x)]);
1430 x = adjust_address (x, HImode, 2);
1431 print_operand (file, x, 0);
1434 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1440 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1441 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1442 fprintf (file, "#%ld", (val & 0xffff));
1450 fputs (cond_string (GET_CODE (x)), file);
1453 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1456 if (GET_CODE (x) == CONST_INT)
1457 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1459 fprintf (file, "%s", byte_reg (x, 0));
1462 if (GET_CODE (x) == CONST_INT)
1463 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1465 fprintf (file, "%s", byte_reg (x, 1));
1468 if (GET_CODE (x) == CONST_INT)
1469 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1471 fprintf (file, "%s",
1472 byte_reg (x, TARGET_H8300 ? 2 : 0));
1475 if (GET_CODE (x) == CONST_INT)
1476 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1478 fprintf (file, "%s",
1479 byte_reg (x, TARGET_H8300 ? 3 : 1));
1482 if (GET_CODE (x) == CONST_INT)
1483 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1485 fprintf (file, "%s", byte_reg (x, 0));
1488 if (GET_CODE (x) == CONST_INT)
1489 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1491 fprintf (file, "%s", byte_reg (x, 1));
1496 switch (GET_CODE (x))
1499 switch (GET_MODE (x))
1502 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1503 fprintf (file, "%s", byte_reg (x, 0));
1504 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1505 fprintf (file, "%s", names_big[REGNO (x)]);
1509 fprintf (file, "%s", names_big[REGNO (x)]);
1513 fprintf (file, "%s", names_extended[REGNO (x)]);
1522 rtx addr = XEXP (x, 0);
1524 fprintf (file, "@");
1525 output_address (addr);
1527 /* We fall back from smaller addressing to larger
1528 addressing in various ways depending on CODE. */
1532 /* Used for mov.b and bit operations. */
1533 if (h8300_eightbit_constant_address_p (addr))
1535 fprintf (file, ":8");
1539 /* Fall through. We should not get here if we are
1540 processing bit operations on H8/300 or H8/300H
1541 because 'U' constraint does not allow bit
1542 operations on the tiny area on these machines. */
1546 /* Used for mov.w and mov.l. */
1547 if (h8300_tiny_constant_address_p (addr))
1548 fprintf (file, ":16");
1560 fprintf (file, "#");
1561 print_operand_address (file, x);
1567 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1568 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1569 fprintf (file, "#%ld", val);
1578 /* Output assembly language output for the address ADDR to FILE. */
1581 print_operand_address (file, addr)
1585 switch (GET_CODE (addr))
1588 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1592 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1596 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1600 fprintf (file, "(");
1601 if (GET_CODE (XEXP (addr, 0)) == REG)
1604 print_operand_address (file, XEXP (addr, 1));
1605 fprintf (file, ",");
1606 print_operand_address (file, XEXP (addr, 0));
1611 print_operand_address (file, XEXP (addr, 0));
1612 fprintf (file, "+");
1613 print_operand_address (file, XEXP (addr, 1));
1615 fprintf (file, ")");
1620 /* Since the H8/300 only has 16 bit pointers, negative values are also
1621 those >= 32768. This happens for example with pointer minus a
1622 constant. We don't want to turn (char *p - 2) into
1623 (char *p + 65534) because loop unrolling can build upon this
1624 (IE: char *p + 131068). */
1625 int n = INTVAL (addr);
1627 n = (int) (short) n;
1628 fprintf (file, "%d", n);
1633 output_addr_const (file, addr);
1638 /* Output all insn addresses and their sizes into the assembly language
1639 output file. This is helpful for debugging whether the length attributes
1640 in the md file are correct. This is not meant to be a user selectable
1644 final_prescan_insn (insn, operand, num_operands)
1645 rtx insn, *operand ATTRIBUTE_UNUSED;
1646 int num_operands ATTRIBUTE_UNUSED;
1648 /* This holds the last insn address. */
1649 static int last_insn_address = 0;
1651 const int uid = INSN_UID (insn);
1653 if (TARGET_ADDRESSES)
1655 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1656 INSN_ADDRESSES (uid) - last_insn_address);
1657 last_insn_address = INSN_ADDRESSES (uid);
1661 /* Prepare for an SI sized move. */
1667 rtx src = operands[1];
1668 rtx dst = operands[0];
1669 if (!reload_in_progress && !reload_completed)
1671 if (!register_operand (dst, GET_MODE (dst)))
1673 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1674 emit_move_insn (tmp, src);
1681 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1682 Define the offset between two registers, one to be eliminated, and
1683 the other its replacement, at the start of a routine. */
1686 h8300_initial_elimination_offset (from, to)
1690 /* The number of bytes that the return address takes on the stack. */
1691 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1693 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1694 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1695 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1696 offset = frame_pointer_needed * UNITS_PER_WORD;
1701 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1702 if (WORD_REG_USED (regno))
1703 offset += UNITS_PER_WORD;
1705 /* See the comments for get_frame_size. We need to round it up to
1708 offset += round_frame_size (get_frame_size ());
1710 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1711 /* Skip saved PC. */
1719 h8300_return_addr_rtx (count, frame)
1726 ret = gen_rtx_MEM (Pmode,
1727 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1728 else if (flag_omit_frame_pointer)
1731 ret = gen_rtx_MEM (Pmode,
1732 memory_address (Pmode,
1733 plus_constant (frame, UNITS_PER_WORD)));
1734 set_mem_alias_set (ret, get_frame_alias_set ());
1738 /* Update the condition code from the insn. */
1741 notice_update_cc (body, insn)
1747 switch (get_attr_cc (insn))
1750 /* Insn does not affect CC at all. */
1754 /* Insn does not change CC, but the 0'th operand has been changed. */
1755 if (cc_status.value1 != 0
1756 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1757 cc_status.value1 = 0;
1758 if (cc_status.value2 != 0
1759 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1760 cc_status.value2 = 0;
1764 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1765 The V flag is unusable. The C flag may or may not be known but
1766 that's ok because alter_cond will change tests to use EQ/NE. */
1768 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1769 set = single_set (insn);
1770 cc_status.value1 = SET_SRC (set);
1771 if (SET_DEST (set) != cc0_rtx)
1772 cc_status.value2 = SET_DEST (set);
1776 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1777 The C flag may or may not be known but that's ok because
1778 alter_cond will change tests to use EQ/NE. */
1780 cc_status.flags |= CC_NO_CARRY;
1781 set = single_set (insn);
1782 cc_status.value1 = SET_SRC (set);
1783 if (SET_DEST (set) != cc0_rtx)
1785 /* If the destination is STRICT_LOW_PART, strip off
1787 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1788 cc_status.value2 = XEXP (SET_DEST (set), 0);
1790 cc_status.value2 = SET_DEST (set);
1795 /* The insn is a compare instruction. */
1797 cc_status.value1 = SET_SRC (body);
1801 /* Insn doesn't leave CC in a usable state. */
1807 /* Return nonzero if X is a stack pointer. */
1810 stack_pointer_operand (x, mode)
1812 enum machine_mode mode ATTRIBUTE_UNUSED;
1814 return x == stack_pointer_rtx;
1817 /* Return nonzero if X is a constant whose absolute value is greater
1821 const_int_gt_2_operand (x, mode)
1823 enum machine_mode mode ATTRIBUTE_UNUSED;
1825 return (GET_CODE (x) == CONST_INT
1826 && abs (INTVAL (x)) > 2);
1829 /* Return nonzero if X is a constant whose absolute value is no
1833 const_int_ge_8_operand (x, mode)
1835 enum machine_mode mode ATTRIBUTE_UNUSED;
1837 return (GET_CODE (x) == CONST_INT
1838 && abs (INTVAL (x)) >= 8);
1841 /* Return nonzero if X is a constant expressible in QImode. */
1844 const_int_qi_operand (x, mode)
1846 enum machine_mode mode ATTRIBUTE_UNUSED;
1848 return (GET_CODE (x) == CONST_INT
1849 && (INTVAL (x) & 0xff) == INTVAL (x));
1852 /* Return nonzero if X is a constant expressible in HImode. */
1855 const_int_hi_operand (x, mode)
1857 enum machine_mode mode ATTRIBUTE_UNUSED;
1859 return (GET_CODE (x) == CONST_INT
1860 && (INTVAL (x) & 0xffff) == INTVAL (x));
1863 /* Return nonzero if X is a constant suitable for inc/dec. */
1866 incdec_operand (x, mode)
1868 enum machine_mode mode ATTRIBUTE_UNUSED;
1870 return (GET_CODE (x) == CONST_INT
1871 && (CONST_OK_FOR_M (INTVAL (x))
1872 || CONST_OK_FOR_O (INTVAL (x))));
1875 /* Return nonzero if X is either EQ or NE. */
1878 eqne_operator (x, mode)
1880 enum machine_mode mode ATTRIBUTE_UNUSED;
1882 enum rtx_code code = GET_CODE (x);
1884 return (code == EQ || code == NE);
1887 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1890 gtle_operator (x, mode)
1892 enum machine_mode mode ATTRIBUTE_UNUSED;
1894 enum rtx_code code = GET_CODE (x);
1896 return (code == GT || code == LE || code == GTU || code == LEU);
1899 /* Return nonzero if X is either GTU or LEU. */
1902 gtuleu_operator (x, mode)
1904 enum machine_mode mode ATTRIBUTE_UNUSED;
1906 enum rtx_code code = GET_CODE (x);
1908 return (code == GTU || code == LEU);
1911 /* Return nonzero if X is either IOR or XOR. */
1914 iorxor_operator (x, mode)
1916 enum machine_mode mode ATTRIBUTE_UNUSED;
1918 enum rtx_code code = GET_CODE (x);
1920 return (code == IOR || code == XOR);
1923 /* Recognize valid operators for bit instructions. */
1926 bit_operator (x, mode)
1928 enum machine_mode mode ATTRIBUTE_UNUSED;
1930 enum rtx_code code = GET_CODE (x);
1938 output_plussi (operands)
1941 enum machine_mode mode = GET_MODE (operands[0]);
1948 if (GET_CODE (operands[2]) == REG)
1949 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1951 if (GET_CODE (operands[2]) == CONST_INT)
1953 HOST_WIDE_INT n = INTVAL (operands[2]);
1955 if ((n & 0xffffff) == 0)
1956 return "add\t%z2,%z0";
1957 if ((n & 0xffff) == 0)
1958 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
1959 if ((n & 0xff) == 0)
1960 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1963 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1967 if (GET_CODE (operands[2]) == REG)
1968 return "add.l\t%S2,%S0";
1970 if (GET_CODE (operands[2]) == CONST_INT)
1972 HOST_WIDE_INT intval = INTVAL (operands[2]);
1974 /* See if we can finish with 2 bytes. */
1976 switch ((unsigned int) intval & 0xffffffff)
1981 return "adds\t%2,%S0";
1986 return "subs\t%G2,%S0";
1990 operands[2] = GEN_INT (intval >> 16);
1991 return "inc.w\t%2,%e0";
1995 operands[2] = GEN_INT (intval >> 16);
1996 return "dec.w\t%G2,%e0";
1999 /* See if we can finish with 4 bytes. */
2000 if ((intval & 0xffff) == 0)
2002 operands[2] = GEN_INT (intval >> 16);
2003 return "add.w\t%2,%e0";
2007 return "add.l\t%S2,%S0";
2012 compute_plussi_length (operands)
2015 enum machine_mode mode = GET_MODE (operands[0]);
2022 if (GET_CODE (operands[2]) == REG)
2025 if (GET_CODE (operands[2]) == CONST_INT)
2027 HOST_WIDE_INT n = INTVAL (operands[2]);
2029 if ((n & 0xffffff) == 0)
2031 if ((n & 0xffff) == 0)
2033 if ((n & 0xff) == 0)
2041 if (GET_CODE (operands[2]) == REG)
2044 if (GET_CODE (operands[2]) == CONST_INT)
2046 HOST_WIDE_INT intval = INTVAL (operands[2]);
2048 /* See if we can finish with 2 bytes. */
2050 switch ((unsigned int) intval & 0xffffffff)
2071 /* See if we can finish with 4 bytes. */
2072 if ((intval & 0xffff) == 0)
2081 compute_plussi_cc (operands)
2084 enum machine_mode mode = GET_MODE (operands[0]);
2095 if (GET_CODE (operands[2]) == REG)
2098 if (GET_CODE (operands[2]) == CONST_INT)
2100 HOST_WIDE_INT intval = INTVAL (operands[2]);
2102 /* See if we can finish with 2 bytes. */
2104 switch ((unsigned int) intval & 0xffffffff)
2109 return CC_NONE_0HIT;
2114 return CC_NONE_0HIT;
2125 /* See if we can finish with 4 bytes. */
2126 if ((intval & 0xffff) == 0)
2135 output_logical_op (mode, operands)
2136 enum machine_mode mode;
2139 /* Figure out the logical op that we need to perform. */
2140 enum rtx_code code = GET_CODE (operands[3]);
2141 /* Pretend that every byte is affected if both operands are registers. */
2142 const unsigned HOST_WIDE_INT intval =
2143 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2144 ? INTVAL (operands[2]) : 0x55555555);
2145 /* The determinant of the algorithm. If we perform an AND, 0
2146 affects a bit. Otherwise, 1 affects a bit. */
2147 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2148 /* Break up DET into pieces. */
2149 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2150 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2151 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2152 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2153 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2154 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2155 int lower_half_easy_p = 0;
2156 int upper_half_easy_p = 0;
2157 /* The name of an insn. */
2179 /* First, see if we can finish with one insn. */
2180 if ((TARGET_H8300H || TARGET_H8300S)
2184 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2185 output_asm_insn (insn_buf, operands);
2189 /* Take care of the lower byte. */
2192 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2193 output_asm_insn (insn_buf, operands);
2195 /* Take care of the upper byte. */
2198 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2199 output_asm_insn (insn_buf, operands);
2204 if (TARGET_H8300H || TARGET_H8300S)
2206 /* Determine if the lower half can be taken care of in no more
2208 lower_half_easy_p = (b0 == 0
2210 || (code != IOR && w0 == 0xffff));
2212 /* Determine if the upper half can be taken care of in no more
2214 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2215 || (code == AND && w1 == 0xff00));
2218 /* Check if doing everything with one insn is no worse than
2219 using multiple insns. */
2220 if ((TARGET_H8300H || TARGET_H8300S)
2221 && w0 != 0 && w1 != 0
2222 && !(lower_half_easy_p && upper_half_easy_p)
2223 && !(code == IOR && w1 == 0xffff
2224 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2226 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2227 output_asm_insn (insn_buf, operands);
2231 /* Take care of the lower and upper words individually. For
2232 each word, we try different methods in the order of
2234 1) the special insn (in case of AND or XOR),
2235 2) the word-wise insn, and
2236 3) The byte-wise insn. */
2238 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2239 output_asm_insn ((code == AND)
2240 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2242 else if ((TARGET_H8300H || TARGET_H8300S)
2246 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2247 output_asm_insn (insn_buf, operands);
2253 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2254 output_asm_insn (insn_buf, operands);
2258 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2259 output_asm_insn (insn_buf, operands);
2264 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2265 output_asm_insn ((code == AND)
2266 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2268 else if ((TARGET_H8300H || TARGET_H8300S)
2271 && (w0 & 0x8000) != 0)
2273 output_asm_insn ("exts.l\t%S0", operands);
2275 else if ((TARGET_H8300H || TARGET_H8300S)
2279 output_asm_insn ("extu.w\t%e0", operands);
2281 else if (TARGET_H8300H || TARGET_H8300S)
2285 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2286 output_asm_insn (insn_buf, operands);
2293 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2294 output_asm_insn (insn_buf, operands);
2298 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2299 output_asm_insn (insn_buf, operands);
2311 compute_logical_op_length (mode, operands)
2312 enum machine_mode mode;
2315 /* Figure out the logical op that we need to perform. */
2316 enum rtx_code code = GET_CODE (operands[3]);
2317 /* Pretend that every byte is affected if both operands are registers. */
2318 const unsigned HOST_WIDE_INT intval =
2319 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2320 ? INTVAL (operands[2]) : 0x55555555);
2321 /* The determinant of the algorithm. If we perform an AND, 0
2322 affects a bit. Otherwise, 1 affects a bit. */
2323 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2324 /* Break up DET into pieces. */
2325 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2326 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2327 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2328 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2329 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2330 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2331 int lower_half_easy_p = 0;
2332 int upper_half_easy_p = 0;
2334 unsigned int length = 0;
2339 /* First, see if we can finish with one insn. */
2340 if ((TARGET_H8300H || TARGET_H8300S)
2344 if (REG_P (operands[2]))
2351 /* Take care of the lower byte. */
2355 /* Take care of the upper byte. */
2361 if (TARGET_H8300H || TARGET_H8300S)
2363 /* Determine if the lower half can be taken care of in no more
2365 lower_half_easy_p = (b0 == 0
2367 || (code != IOR && w0 == 0xffff));
2369 /* Determine if the upper half can be taken care of in no more
2371 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2372 || (code == AND && w1 == 0xff00));
2375 /* Check if doing everything with one insn is no worse than
2376 using multiple insns. */
2377 if ((TARGET_H8300H || TARGET_H8300S)
2378 && w0 != 0 && w1 != 0
2379 && !(lower_half_easy_p && upper_half_easy_p)
2380 && !(code == IOR && w1 == 0xffff
2381 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2383 if (REG_P (operands[2]))
2390 /* Take care of the lower and upper words individually. For
2391 each word, we try different methods in the order of
2393 1) the special insn (in case of AND or XOR),
2394 2) the word-wise insn, and
2395 3) The byte-wise insn. */
2397 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2401 else if ((TARGET_H8300H || TARGET_H8300S)
2417 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2421 else if ((TARGET_H8300H || TARGET_H8300S)
2424 && (w0 & 0x8000) != 0)
2428 else if ((TARGET_H8300H || TARGET_H8300S)
2434 else if (TARGET_H8300H || TARGET_H8300S)
2456 compute_logical_op_cc (mode, operands)
2457 enum machine_mode mode;
2460 /* Figure out the logical op that we need to perform. */
2461 enum rtx_code code = GET_CODE (operands[3]);
2462 /* Pretend that every byte is affected if both operands are registers. */
2463 const unsigned HOST_WIDE_INT intval =
2464 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2465 ? INTVAL (operands[2]) : 0x55555555);
2466 /* The determinant of the algorithm. If we perform an AND, 0
2467 affects a bit. Otherwise, 1 affects a bit. */
2468 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2469 /* Break up DET into pieces. */
2470 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2471 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2472 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2473 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2474 int lower_half_easy_p = 0;
2475 int upper_half_easy_p = 0;
2476 /* Condition code. */
2477 enum attr_cc cc = CC_CLOBBER;
2482 /* First, see if we can finish with one insn. */
2483 if ((TARGET_H8300H || TARGET_H8300S)
2491 if (TARGET_H8300H || TARGET_H8300S)
2493 /* Determine if the lower half can be taken care of in no more
2495 lower_half_easy_p = (b0 == 0
2497 || (code != IOR && w0 == 0xffff));
2499 /* Determine if the upper half can be taken care of in no more
2501 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2502 || (code == AND && w1 == 0xff00));
2505 /* Check if doing everything with one insn is no worse than
2506 using multiple insns. */
2507 if ((TARGET_H8300H || TARGET_H8300S)
2508 && w0 != 0 && w1 != 0
2509 && !(lower_half_easy_p && upper_half_easy_p)
2510 && !(code == IOR && w1 == 0xffff
2511 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2517 if ((TARGET_H8300H || TARGET_H8300S)
2520 && (w0 & 0x8000) != 0)
2534 We devote a fair bit of code to getting efficient shifts since we
2535 can only shift one bit at a time on the H8/300 and H8/300H and only
2536 one or two bits at a time on the H8S.
2538 All shift code falls into one of the following ways of
2541 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2542 when a straight line shift is about the same size or smaller than
2545 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2546 off the bits we don't need. This is used when only a few of the
2547 bits in the original value will survive in the shifted value.
2549 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2550 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2551 shifts can be added if the shift count is slightly more than 8 or
2552 16. This case also includes other oddballs that are not worth
2555 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2557 For each shift count, we try to use code that has no trade-off
2558 between code size and speed whenever possible.
2560 If the trade-off is unavoidable, we try to be reasonable.
2561 Specifically, the fastest version is one instruction longer than
2562 the shortest version, we take the fastest version. We also provide
2563 the use a way to switch back to the shortest version with -Os.
2565 For the details of the shift algorithms for various shift counts,
2566 refer to shift_alg_[qhs]i. */
2569 nshift_operator (x, mode)
2571 enum machine_mode mode ATTRIBUTE_UNUSED;
2573 switch (GET_CODE (x))
2585 /* Emit code to do shifts. */
2588 expand_a_shift (mode, code, operands)
2589 enum machine_mode mode;
2593 emit_move_insn (operands[0], operands[1]);
2595 /* Need a loop to get all the bits we want - we generate the
2596 code at emit time, but need to allocate a scratch reg now. */
2598 emit_insn (gen_rtx_PARALLEL
2601 gen_rtx_SET (VOIDmode, operands[0],
2602 gen_rtx (code, mode, operands[0],
2604 gen_rtx_CLOBBER (VOIDmode,
2605 gen_rtx_SCRATCH (QImode)))));
2608 /* Symbols of the various modes which can be used as indices. */
2612 QIshift, HIshift, SIshift
2615 /* For single bit shift insns, record assembler and what bits of the
2616 condition code are valid afterwards (represented as various CC_FOO
2617 bits, 0 means CC isn't left in a usable state). */
2621 const char *const assembler;
2625 /* Assembler instruction shift table.
2627 These tables are used to look up the basic shifts.
2628 They are indexed by cpu, shift_type, and mode. */
2630 static const struct shift_insn shift_one[2][3][3] =
2636 { "shll\t%X0", CC_SET_ZNV },
2637 { "add.w\t%T0,%T0", CC_SET_ZN },
2638 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2640 /* SHIFT_LSHIFTRT */
2642 { "shlr\t%X0", CC_SET_ZNV },
2643 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2644 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2646 /* SHIFT_ASHIFTRT */
2648 { "shar\t%X0", CC_SET_ZNV },
2649 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2650 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2657 { "shll.b\t%X0", CC_SET_ZNV },
2658 { "shll.w\t%T0", CC_SET_ZNV },
2659 { "shll.l\t%S0", CC_SET_ZNV }
2661 /* SHIFT_LSHIFTRT */
2663 { "shlr.b\t%X0", CC_SET_ZNV },
2664 { "shlr.w\t%T0", CC_SET_ZNV },
2665 { "shlr.l\t%S0", CC_SET_ZNV }
2667 /* SHIFT_ASHIFTRT */
2669 { "shar.b\t%X0", CC_SET_ZNV },
2670 { "shar.w\t%T0", CC_SET_ZNV },
2671 { "shar.l\t%S0", CC_SET_ZNV }
2676 static const struct shift_insn shift_two[3][3] =
2680 { "shll.b\t#2,%X0", CC_SET_ZNV },
2681 { "shll.w\t#2,%T0", CC_SET_ZNV },
2682 { "shll.l\t#2,%S0", CC_SET_ZNV }
2684 /* SHIFT_LSHIFTRT */
2686 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2687 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2688 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2690 /* SHIFT_ASHIFTRT */
2692 { "shar.b\t#2,%X0", CC_SET_ZNV },
2693 { "shar.w\t#2,%T0", CC_SET_ZNV },
2694 { "shar.l\t#2,%S0", CC_SET_ZNV }
2698 /* Rotates are organized by which shift they'll be used in implementing.
2699 There's no need to record whether the cc is valid afterwards because
2700 it is the AND insn that will decide this. */
2702 static const char *const rotate_one[2][3][3] =
2709 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2712 /* SHIFT_LSHIFTRT */
2715 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2718 /* SHIFT_ASHIFTRT */
2721 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2733 /* SHIFT_LSHIFTRT */
2739 /* SHIFT_ASHIFTRT */
2748 static const char *const rotate_two[3][3] =
2756 /* SHIFT_LSHIFTRT */
2762 /* SHIFT_ASHIFTRT */
2771 /* Shift algorithm. */
2774 /* The number of bits to be shifted by shift1 and shift2. Valid
2775 when ALG is SHIFT_SPECIAL. */
2776 unsigned int remainder;
2778 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2779 const char *special;
2781 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2782 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2785 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2786 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2789 /* CC status for SHIFT_INLINE. */
2792 /* CC status for SHIFT_SPECIAL. */
2796 static void get_shift_alg PARAMS ((enum shift_type,
2797 enum shift_mode, unsigned int,
2798 struct shift_info *));
2800 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2801 best algorithm for doing the shift. The assembler code is stored
2802 in the pointers in INFO. We achieve the maximum efficiency in most
2803 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2804 SImode in particular have a lot of room to optimize.
2806 We first determine the strategy of the shift algorithm by a table
2807 lookup. If that tells us to use a hand crafted assembly code, we
2808 go into the big switch statement to find what that is. Otherwise,
2809 we resort to a generic way, such as inlining. In either case, the
2810 result is returned through INFO. */
2813 get_shift_alg (shift_type, shift_mode, count, info)
2814 enum shift_type shift_type;
2815 enum shift_mode shift_mode;
2817 struct shift_info *info;
2821 /* Find the target CPU. */
2824 else if (TARGET_H8300H)
2829 /* Find the shift algorithm. */
2830 info->alg = SHIFT_LOOP;
2834 if (count < GET_MODE_BITSIZE (QImode))
2835 info->alg = shift_alg_qi[cpu][shift_type][count];
2839 if (count < GET_MODE_BITSIZE (HImode))
2840 info->alg = shift_alg_hi[cpu][shift_type][count];
2844 if (count < GET_MODE_BITSIZE (SImode))
2845 info->alg = shift_alg_si[cpu][shift_type][count];
2852 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2856 info->remainder = count;
2860 /* It is up to the caller to know that looping clobbers cc. */
2861 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2862 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2863 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2867 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2868 info->shift2 = rotate_two[shift_type][shift_mode];
2869 info->cc_inline = CC_CLOBBER;
2873 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2874 info->remainder = 0;
2875 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2876 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2877 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2878 info->cc_special = CC_CLOBBER;
2882 /* Here we only deal with SHIFT_SPECIAL. */
2886 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2887 through the entire value. */
2888 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2890 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2902 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2904 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2906 case SHIFT_LSHIFTRT:
2908 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2910 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2912 case SHIFT_ASHIFTRT:
2913 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2917 else if ((8 <= count && count <= 13)
2918 || (TARGET_H8300S && count == 14))
2920 info->remainder = count - 8;
2925 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2927 case SHIFT_LSHIFTRT:
2930 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2931 info->shift1 = "shlr.b\t%s0";
2932 info->cc_inline = CC_SET_ZNV;
2936 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
2937 info->cc_special = CC_SET_ZNV;
2940 case SHIFT_ASHIFTRT:
2943 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2944 info->shift1 = "shar.b\t%s0";
2948 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2949 info->cc_special = CC_SET_ZNV;
2954 else if (count == 14)
2960 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2962 case SHIFT_LSHIFTRT:
2964 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2966 case SHIFT_ASHIFTRT:
2968 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2969 else if (TARGET_H8300H)
2971 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2972 info->cc_special = CC_SET_ZNV;
2974 else /* TARGET_H8300S */
2979 else if (count == 15)
2984 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
2986 case SHIFT_LSHIFTRT:
2987 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
2989 case SHIFT_ASHIFTRT:
2990 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2997 if (TARGET_H8300 && 8 <= count && count <= 9)
2999 info->remainder = count - 8;
3004 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3006 case SHIFT_LSHIFTRT:
3007 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3008 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3010 case SHIFT_ASHIFTRT:
3011 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3015 else if (count == 8 && !TARGET_H8300)
3020 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3022 case SHIFT_LSHIFTRT:
3023 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3025 case SHIFT_ASHIFTRT:
3026 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3030 else if (count == 15 && TARGET_H8300)
3036 case SHIFT_LSHIFTRT:
3037 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3039 case SHIFT_ASHIFTRT:
3040 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3044 else if (count == 15 && !TARGET_H8300)
3049 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3050 info->cc_special = CC_SET_ZNV;
3052 case SHIFT_LSHIFTRT:
3053 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3054 info->cc_special = CC_SET_ZNV;
3056 case SHIFT_ASHIFTRT:
3060 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3061 || (TARGET_H8300H && 16 <= count && count <= 19)
3062 || (TARGET_H8300S && 16 <= count && count <= 21))
3064 info->remainder = count - 16;
3069 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3071 info->shift1 = "add.w\t%e0,%e0";
3073 case SHIFT_LSHIFTRT:
3076 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3077 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3081 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3082 info->cc_special = CC_SET_ZNV;
3085 case SHIFT_ASHIFTRT:
3088 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3089 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3093 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3094 info->cc_special = CC_SET_ZNV;
3099 else if (TARGET_H8300 && 24 <= count && count <= 28)
3101 info->remainder = count - 24;
3106 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3107 info->shift1 = "shll.b\t%z0";
3108 info->cc_inline = CC_SET_ZNV;
3110 case SHIFT_LSHIFTRT:
3111 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3112 info->shift1 = "shlr.b\t%w0";
3113 info->cc_inline = CC_SET_ZNV;
3115 case SHIFT_ASHIFTRT:
3116 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3117 info->shift1 = "shar.b\t%w0";
3118 info->cc_inline = CC_SET_ZNV;
3122 else if ((TARGET_H8300H && count == 24)
3123 || (TARGET_H8300S && 24 <= count && count <= 25))
3125 info->remainder = count - 24;
3130 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3132 case SHIFT_LSHIFTRT:
3133 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3134 info->cc_special = CC_SET_ZNV;
3136 case SHIFT_ASHIFTRT:
3137 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3138 info->cc_special = CC_SET_ZNV;
3142 else if (!TARGET_H8300 && count == 28)
3148 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3150 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3152 case SHIFT_LSHIFTRT:
3155 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3156 info->cc_special = CC_SET_ZNV;
3159 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3161 case SHIFT_ASHIFTRT:
3165 else if (!TARGET_H8300 && count == 29)
3171 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3173 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3175 case SHIFT_LSHIFTRT:
3178 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3179 info->cc_special = CC_SET_ZNV;
3183 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3184 info->cc_special = CC_SET_ZNV;
3187 case SHIFT_ASHIFTRT:
3191 else if (!TARGET_H8300 && count == 30)
3197 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3199 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3201 case SHIFT_LSHIFTRT:
3203 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3205 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3207 case SHIFT_ASHIFTRT:
3211 else if (count == 31)
3218 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3220 case SHIFT_LSHIFTRT:
3221 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3223 case SHIFT_ASHIFTRT:
3224 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3233 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3234 info->cc_special = CC_SET_ZNV;
3236 case SHIFT_LSHIFTRT:
3237 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3238 info->cc_special = CC_SET_ZNV;
3240 case SHIFT_ASHIFTRT:
3241 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3242 info->cc_special = CC_SET_ZNV;
3255 info->shift2 = NULL;
3258 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3259 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3262 h8300_shift_needs_scratch_p (count, mode)
3264 enum machine_mode mode;
3269 if (GET_MODE_BITSIZE (mode) <= count)
3272 /* Find out the target CPU. */
3275 else if (TARGET_H8300H)
3280 /* Find the shift algorithm. */
3284 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3285 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3286 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3290 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3291 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3292 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3296 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3297 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3298 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3305 /* On H8/300H, count == 8 uses a scratch register. */
3306 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3307 || (TARGET_H8300H && mode == SImode && count == 8));
3310 /* Emit the assembler code for doing shifts. */
3313 output_a_shift (operands)
3316 static int loopend_lab;
3317 rtx shift = operands[3];
3318 enum machine_mode mode = GET_MODE (shift);
3319 enum rtx_code code = GET_CODE (shift);
3320 enum shift_type shift_type;
3321 enum shift_mode shift_mode;
3322 struct shift_info info;
3329 shift_mode = QIshift;
3332 shift_mode = HIshift;
3335 shift_mode = SIshift;
3344 shift_type = SHIFT_ASHIFTRT;
3347 shift_type = SHIFT_LSHIFTRT;
3350 shift_type = SHIFT_ASHIFT;
3356 if (GET_CODE (operands[2]) != CONST_INT)
3358 /* This case must be taken care of by one of the two splitters
3359 that convert a variable shift into a loop. */
3364 int n = INTVAL (operands[2]);
3366 /* If the count is negative, make it 0. */
3369 /* If the count is too big, truncate it.
3370 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3371 do the intuitive thing. */
3372 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3373 n = GET_MODE_BITSIZE (mode);
3375 get_shift_alg (shift_type, shift_mode, n, &info);
3380 output_asm_insn (info.special, operands);
3386 /* Emit two bit shifts first. */
3387 if (info.shift2 != NULL)
3389 for (; n > 1; n -= 2)
3390 output_asm_insn (info.shift2, operands);
3393 /* Now emit one bit shifts for any residual. */
3395 output_asm_insn (info.shift1, operands);
3400 int m = GET_MODE_BITSIZE (mode) - n;
3401 const int mask = (shift_type == SHIFT_ASHIFT
3402 ? ((1 << m) - 1) << n
3406 /* Not all possibilities of rotate are supported. They shouldn't
3407 be generated, but let's watch for 'em. */
3408 if (info.shift1 == 0)
3411 /* Emit two bit rotates first. */
3412 if (info.shift2 != NULL)
3414 for (; m > 1; m -= 2)
3415 output_asm_insn (info.shift2, operands);
3418 /* Now single bit rotates for any residual. */
3420 output_asm_insn (info.shift1, operands);
3422 /* Now mask off the high bits. */
3424 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3425 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3426 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3430 output_asm_insn (insn_buf, operands);
3435 /* A loop to shift by a "large" constant value.
3436 If we have shift-by-2 insns, use them. */
3437 if (info.shift2 != NULL)
3439 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3440 names_big[REGNO (operands[4])]);
3441 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3442 output_asm_insn (info.shift2, operands);
3443 output_asm_insn ("add #0xff,%X4", operands);
3444 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3446 output_asm_insn (info.shift1, operands);
3450 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3451 names_big[REGNO (operands[4])]);
3452 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3453 output_asm_insn (info.shift1, operands);
3454 output_asm_insn ("add #0xff,%X4", operands);
3455 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3466 h8300_asm_insn_count (template)
3467 const char *template;
3469 unsigned int count = 1;
3471 for (; *template; template++)
3472 if (*template == '\n')
3479 compute_a_shift_length (insn, operands)
3480 rtx insn ATTRIBUTE_UNUSED;
3483 rtx shift = operands[3];
3484 enum machine_mode mode = GET_MODE (shift);
3485 enum rtx_code code = GET_CODE (shift);
3486 enum shift_type shift_type;
3487 enum shift_mode shift_mode;
3488 struct shift_info info;
3489 unsigned int wlength = 0;
3494 shift_mode = QIshift;
3497 shift_mode = HIshift;
3500 shift_mode = SIshift;
3509 shift_type = SHIFT_ASHIFTRT;
3512 shift_type = SHIFT_LSHIFTRT;
3515 shift_type = SHIFT_ASHIFT;
3521 if (GET_CODE (operands[2]) != CONST_INT)
3523 /* Get the assembler code to do one shift. */
3524 get_shift_alg (shift_type, shift_mode, 1, &info);
3526 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3530 int n = INTVAL (operands[2]);
3532 /* If the count is negative, make it 0. */
3535 /* If the count is too big, truncate it.
3536 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3537 do the intuitive thing. */
3538 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3539 n = GET_MODE_BITSIZE (mode);
3541 get_shift_alg (shift_type, shift_mode, n, &info);
3546 wlength += h8300_asm_insn_count (info.special);
3548 /* Every assembly instruction used in SHIFT_SPECIAL case
3549 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3550 see xor.l, we just pretend that xor.l counts as two insns
3551 so that the insn length will be computed correctly. */
3552 if (strstr (info.special, "xor.l") != NULL)
3560 if (info.shift2 != NULL)
3562 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3566 wlength += h8300_asm_insn_count (info.shift1) * n;
3572 int m = GET_MODE_BITSIZE (mode) - n;
3574 /* Not all possibilities of rotate are supported. They shouldn't
3575 be generated, but let's watch for 'em. */
3576 if (info.shift1 == 0)
3579 if (info.shift2 != NULL)
3581 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3585 wlength += h8300_asm_insn_count (info.shift1) * m;
3587 /* Now mask off the high bits. */
3608 /* A loop to shift by a "large" constant value.
3609 If we have shift-by-2 insns, use them. */
3610 if (info.shift2 != NULL)
3612 wlength += 3 + h8300_asm_insn_count (info.shift2);
3614 wlength += h8300_asm_insn_count (info.shift1);
3618 wlength += 3 + h8300_asm_insn_count (info.shift1);
3629 compute_a_shift_cc (insn, operands)
3630 rtx insn ATTRIBUTE_UNUSED;
3633 rtx shift = operands[3];
3634 enum machine_mode mode = GET_MODE (shift);
3635 enum rtx_code code = GET_CODE (shift);
3636 enum shift_type shift_type;
3637 enum shift_mode shift_mode;
3638 struct shift_info info;
3643 shift_mode = QIshift;
3646 shift_mode = HIshift;
3649 shift_mode = SIshift;
3658 shift_type = SHIFT_ASHIFTRT;
3661 shift_type = SHIFT_LSHIFTRT;
3664 shift_type = SHIFT_ASHIFT;
3670 if (GET_CODE (operands[2]) != CONST_INT)
3672 /* This case must be taken care of by one of the two splitters
3673 that convert a variable shift into a loop. */
3678 int n = INTVAL (operands[2]);
3680 /* If the count is negative, make it 0. */
3683 /* If the count is too big, truncate it.
3684 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3685 do the intuitive thing. */
3686 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3687 n = GET_MODE_BITSIZE (mode);
3689 get_shift_alg (shift_type, shift_mode, n, &info);
3694 if (info.remainder == 0)
3695 return info.cc_special;
3700 return info.cc_inline;
3703 /* This case always ends with an and instruction. */
3707 /* A loop to shift by a "large" constant value.
3708 If we have shift-by-2 insns, use them. */
3709 if (info.shift2 != NULL)
3712 return info.cc_inline;
3722 /* A rotation by a non-constant will cause a loop to be generated, in
3723 which a rotation by one bit is used. A rotation by a constant,
3724 including the one in the loop, will be taken care of by
3725 emit_a_rotate () at the insn emit time. */
3728 expand_a_rotate (code, operands)
3732 rtx dst = operands[0];
3733 rtx src = operands[1];
3734 rtx rotate_amount = operands[2];
3735 enum machine_mode mode = GET_MODE (dst);
3738 /* We rotate in place. */
3739 emit_move_insn (dst, src);
3741 if (GET_CODE (rotate_amount) != CONST_INT)
3743 rtx counter = gen_reg_rtx (QImode);
3744 rtx start_label = gen_label_rtx ();
3745 rtx end_label = gen_label_rtx ();
3747 /* If the rotate amount is less than or equal to 0,
3748 we go out of the loop. */
3749 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3750 QImode, 0, end_label);
3752 /* Initialize the loop counter. */
3753 emit_move_insn (counter, rotate_amount);
3755 emit_label (start_label);
3757 /* Rotate by one bit. */
3758 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3759 emit_insn (gen_rtx_SET (mode, dst, tmp));
3761 /* Decrement the counter by 1. */
3762 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3763 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3765 /* If the loop counter is nonzero, we go back to the beginning
3767 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3770 emit_label (end_label);
3774 /* Rotate by AMOUNT bits. */
3775 tmp = gen_rtx (code, mode, dst, rotate_amount);
3776 emit_insn (gen_rtx_SET (mode, dst, tmp));
3782 /* Emit rotate insns. */
3785 emit_a_rotate (code, operands)
3789 rtx dst = operands[0];
3790 rtx rotate_amount = operands[2];
3791 enum shift_mode rotate_mode;
3792 enum shift_type rotate_type;
3793 const char *insn_buf;
3796 enum machine_mode mode = GET_MODE (dst);
3798 if (GET_CODE (rotate_amount) != CONST_INT)
3804 rotate_mode = QIshift;
3807 rotate_mode = HIshift;
3810 rotate_mode = SIshift;
3819 rotate_type = SHIFT_ASHIFT;
3822 rotate_type = SHIFT_LSHIFTRT;
3828 amount = INTVAL (rotate_amount);
3830 /* Clean up AMOUNT. */
3833 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3834 amount = GET_MODE_BITSIZE (mode);
3836 /* Determine the faster direction. After this phase, amount will be
3837 at most a half of GET_MODE_BITSIZE (mode). */
3838 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3840 /* Flip the direction. */
3841 amount = GET_MODE_BITSIZE (mode) - amount;
3843 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3846 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3847 boost up the rotation. */
3848 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3849 || (mode == HImode && TARGET_H8300H && amount >= 6)
3850 || (mode == HImode && TARGET_H8300S && amount == 8)
3851 || (mode == SImode && TARGET_H8300H && amount >= 10)
3852 || (mode == SImode && TARGET_H8300S && amount >= 13))
3857 /* This code works on any family. */
3858 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3859 output_asm_insn (insn_buf, operands);
3863 /* This code works on the H8/300H and H8S. */
3864 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3865 output_asm_insn (insn_buf, operands);
3872 /* Adjust AMOUNT and flip the direction. */
3873 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3875 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3878 /* Emit rotate insns. */
3879 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3882 insn_buf = rotate_two[rotate_type][rotate_mode];
3884 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3886 for (; amount >= bits; amount -= bits)
3887 output_asm_insn (insn_buf, operands);
3893 /* Fix the operands of a gen_xxx so that it could become a bit
3897 fix_bit_operand (operands, what, type)
3902 /* The bit_operand predicate accepts any memory during RTL generation, but
3903 only 'U' memory afterwards, so if this is a MEM operand, we must force
3904 it to be valid for 'U' by reloading the address. */
3906 if ((what == 0 && single_zero_operand (operands[2], QImode))
3907 || (what == 1 && single_one_operand (operands[2], QImode)))
3909 /* OK to have a memory dest. */
3910 if (GET_CODE (operands[0]) == MEM
3911 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3913 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3914 copy_to_mode_reg (Pmode,
3915 XEXP (operands[0], 0)));
3916 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3920 if (GET_CODE (operands[1]) == MEM
3921 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3923 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3924 copy_to_mode_reg (Pmode,
3925 XEXP (operands[1], 0)));
3926 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3932 /* Dest and src op must be register. */
3934 operands[1] = force_reg (QImode, operands[1]);
3936 rtx res = gen_reg_rtx (QImode);
3937 emit_insn (gen_rtx_SET (VOIDmode, res,
3938 gen_rtx (type, QImode, operands[1], operands[2])));
3939 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3944 /* Return nonzero if FUNC is an interrupt function as specified
3945 by the "interrupt" attribute. */
3948 h8300_interrupt_function_p (func)
3953 if (TREE_CODE (func) != FUNCTION_DECL)
3956 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3957 return a != NULL_TREE;
3960 /* Return nonzero if FUNC is an OS_Task function as specified
3961 by the "OS_Task" attribute. */
3964 h8300_os_task_function_p (func)
3969 if (TREE_CODE (func) != FUNCTION_DECL)
3972 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3973 return a != NULL_TREE;
3976 /* Return nonzero if FUNC is a monitor function as specified
3977 by the "monitor" attribute. */
3980 h8300_monitor_function_p (func)
3985 if (TREE_CODE (func) != FUNCTION_DECL)
3988 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
3989 return a != NULL_TREE;
3992 /* Return nonzero if FUNC is a function that should be called
3993 through the function vector. */
3996 h8300_funcvec_function_p (func)
4001 if (TREE_CODE (func) != FUNCTION_DECL)
4004 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4005 return a != NULL_TREE;
4008 /* Return nonzero if DECL is a variable that's in the eight bit
4012 h8300_eightbit_data_p (decl)
4017 if (TREE_CODE (decl) != VAR_DECL)
4020 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4021 return a != NULL_TREE;
4024 /* Return nonzero if DECL is a variable that's in the tiny
4028 h8300_tiny_data_p (decl)
4033 if (TREE_CODE (decl) != VAR_DECL)
4036 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4037 return a != NULL_TREE;
4040 /* Generate an 'interrupt_handler' attribute for decls. */
4043 h8300_insert_attributes (node, attributes)
4047 if (!pragma_interrupt
4048 || TREE_CODE (node) != FUNCTION_DECL)
4051 pragma_interrupt = 0;
4053 /* Add an 'interrupt_handler' attribute. */
4054 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4058 /* Supported attributes:
4060 interrupt_handler: output a prologue and epilogue suitable for an
4063 function_vector: This function should be called through the
4066 eightbit_data: This variable lives in the 8-bit data area and can
4067 be referenced with 8-bit absolute memory addresses.
4069 tiny_data: This variable lives in the tiny data area and can be
4070 referenced with 16-bit absolute memory references. */
4072 const struct attribute_spec h8300_attribute_table[] =
4074 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4075 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4076 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4077 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4078 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4079 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4080 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4081 { NULL, 0, 0, false, false, false, NULL }
4085 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4086 struct attribute_spec.handler. */
4088 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
4091 tree args ATTRIBUTE_UNUSED;
4092 int flags ATTRIBUTE_UNUSED;
4095 if (TREE_CODE (*node) != FUNCTION_DECL)
4097 warning ("`%s' attribute only applies to functions",
4098 IDENTIFIER_POINTER (name));
4099 *no_add_attrs = true;
4105 /* Handle an "eightbit_data" attribute; arguments as in
4106 struct attribute_spec.handler. */
4108 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
4111 tree args ATTRIBUTE_UNUSED;
4112 int flags ATTRIBUTE_UNUSED;
4117 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4119 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4123 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4124 *no_add_attrs = true;
4130 /* Handle an "tiny_data" attribute; arguments as in
4131 struct attribute_spec.handler. */
4133 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
4136 tree args ATTRIBUTE_UNUSED;
4137 int flags ATTRIBUTE_UNUSED;
4142 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4144 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4148 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4149 *no_add_attrs = true;
4155 /* Mark function vectors, and various small data objects. */
4158 h8300_encode_section_info (decl, rtl, first)
4163 int extra_flags = 0;
4165 default_encode_section_info (decl, rtl, first);
4167 if (TREE_CODE (decl) == FUNCTION_DECL
4168 && h8300_funcvec_function_p (decl))
4169 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4170 else if (TREE_CODE (decl) == VAR_DECL
4171 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4173 if (h8300_eightbit_data_p (decl))
4174 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4175 else if (first && h8300_tiny_data_p (decl))
4176 extra_flags = SYMBOL_FLAG_TINY_DATA;
4180 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4184 output_simode_bld (bild, operands)
4190 /* Clear the destination register. */
4191 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4193 /* Now output the bit load or bit inverse load, and store it in
4196 output_asm_insn ("bild\t%Z2,%Y1", operands);
4198 output_asm_insn ("bld\t%Z2,%Y1", operands);
4200 output_asm_insn ("bst\t#0,%w0", operands);
4204 /* Determine if we can clear the destination first. */
4205 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4206 && REGNO (operands[0]) != REGNO (operands[1]));
4209 output_asm_insn ("sub.l\t%S0,%S0", operands);
4211 /* Output the bit load or bit inverse load. */
4213 output_asm_insn ("bild\t%Z2,%Y1", operands);
4215 output_asm_insn ("bld\t%Z2,%Y1", operands);
4218 output_asm_insn ("xor.l\t%S0,%S0", operands);
4220 /* Perform the bit store. */
4221 output_asm_insn ("bst\t#0,%w0", operands);
4228 /* Given INSN and its current length LENGTH, return the adjustment
4229 (in bytes) to correctly compute INSN's length.
4231 We use this to get the lengths of various memory references correct. */
4234 h8300_adjust_insn_length (insn, length)
4236 int length ATTRIBUTE_UNUSED;
4238 rtx pat = PATTERN (insn);
4240 /* We must filter these out before calling get_attr_adjust_length. */
4241 if (GET_CODE (pat) == USE
4242 || GET_CODE (pat) == CLOBBER
4243 || GET_CODE (pat) == SEQUENCE
4244 || GET_CODE (pat) == ADDR_VEC
4245 || GET_CODE (pat) == ADDR_DIFF_VEC)
4248 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
4251 /* Adjust length for reg->mem and mem->reg copies. */
4252 if (GET_CODE (pat) == SET
4253 && (GET_CODE (SET_SRC (pat)) == MEM
4254 || GET_CODE (SET_DEST (pat)) == MEM))
4256 /* This insn might need a length adjustment. */
4259 if (GET_CODE (SET_SRC (pat)) == MEM)
4260 addr = XEXP (SET_SRC (pat), 0);
4262 addr = XEXP (SET_DEST (pat), 0);
4266 /* On the H8/300, we subtract the difference between the
4267 actual length and the longest one, which is @(d:16,ERs). */
4269 /* @Rs is 2 bytes shorter than the longest. */
4270 if (GET_CODE (addr) == REG)
4273 /* @aa:8 is 2 bytes shorter than the longest. */
4274 if (GET_MODE (SET_SRC (pat)) == QImode
4275 && h8300_eightbit_constant_address_p (addr))
4280 /* On the H8/300H and H8S, we subtract the difference
4281 between the actual length and the longest one, which is
4284 /* @ERs is 6 bytes shorter than the longest. */
4285 if (GET_CODE (addr) == REG)
4288 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4289 if (GET_CODE (addr) == PLUS
4290 && GET_CODE (XEXP (addr, 0)) == REG
4291 && GET_CODE (XEXP (addr, 1)) == CONST_INT
4292 && INTVAL (XEXP (addr, 1)) > -32768
4293 && INTVAL (XEXP (addr, 1)) < 32767)
4296 /* @aa:8 is 6 bytes shorter than the longest. */
4297 if (GET_MODE (SET_SRC (pat)) == QImode
4298 && h8300_eightbit_constant_address_p (addr))
4301 /* @aa:16 is 4 bytes shorter than the longest. */
4302 if (h8300_tiny_constant_address_p (addr))
4305 /* @aa:24 is 2 bytes shorter than the longest. */
4306 if (GET_CODE (addr) == CONST_INT)
4311 /* Loading some constants needs adjustment. */
4312 if (GET_CODE (pat) == SET
4313 && GET_CODE (SET_SRC (pat)) == CONST_INT
4314 && GET_MODE (SET_DEST (pat)) == SImode
4315 && INTVAL (SET_SRC (pat)) != 0)
4317 int val = INTVAL (SET_SRC (pat));
4320 && ((val & 0xffff) == 0
4321 || ((val >> 16) & 0xffff) == 0))
4324 if (TARGET_H8300H || TARGET_H8300S)
4326 if (val == (val & 0xff)
4327 || val == (val & 0xff00))
4330 switch (val & 0xffffffff)
4346 /* Rotations need various adjustments. */
4347 if (GET_CODE (pat) == SET
4348 && (GET_CODE (SET_SRC (pat)) == ROTATE
4349 || GET_CODE (SET_SRC (pat)) == ROTATERT))
4351 rtx src = SET_SRC (pat);
4352 enum machine_mode mode = GET_MODE (src);
4356 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
4359 amount = INTVAL (XEXP (src, 1));
4361 /* Clean up AMOUNT. */
4364 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4365 amount = GET_MODE_BITSIZE (mode);
4367 /* Determine the faster direction. After this phase, amount
4368 will be at most a half of GET_MODE_BITSIZE (mode). */
4369 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4370 /* Flip the direction. */
4371 amount = GET_MODE_BITSIZE (mode) - amount;
4373 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4374 boost up the rotation. */
4375 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4376 || (mode == HImode && TARGET_H8300H && amount >= 6)
4377 || (mode == HImode && TARGET_H8300S && amount == 8)
4378 || (mode == SImode && TARGET_H8300H && amount >= 10)
4379 || (mode == SImode && TARGET_H8300S && amount >= 13))
4381 /* Adjust AMOUNT and flip the direction. */
4382 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4386 /* We use 2-bit rotations on the H8S. */
4388 amount = amount / 2 + amount % 2;
4390 /* The H8/300 uses three insns to rotate one bit, taking 6
4392 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4394 return -(20 - states);
4400 #ifndef OBJECT_FORMAT_ELF
4402 h8300_asm_named_section (name, flags)
4404 unsigned int flags ATTRIBUTE_UNUSED;
4406 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4407 fprintf (asm_out_file, "\t.section %s\n", name);
4409 #endif /* ! OBJECT_FORMAT_ELF */
4411 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4412 which is a special case of the 'R' operand. */
4415 h8300_eightbit_constant_address_p (x)
4418 /* The ranges of the 8-bit area. */
4419 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4420 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4421 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4422 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4423 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4424 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4426 unsigned HOST_WIDE_INT addr;
4428 /* We accept symbols declared with eightbit_data. */
4429 if (GET_CODE (x) == SYMBOL_REF)
4430 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4432 if (GET_CODE (x) != CONST_INT)
4438 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4439 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4440 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4443 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4444 on H8/300H and H8S. */
4447 h8300_tiny_constant_address_p (x)
4450 /* The ranges of the 16-bit area. */
4451 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4452 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4453 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4454 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4455 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4456 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4457 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4458 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4460 unsigned HOST_WIDE_INT addr;
4462 /* We accept symbols declared with tiny_data. */
4463 if (GET_CODE (x) == SYMBOL_REF)
4464 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
4466 if (GET_CODE (x) != CONST_INT)
4472 || TARGET_NORMAL_MODE
4474 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4476 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4480 byte_accesses_mergeable_p (addr1, addr2)
4483 HOST_WIDE_INT offset1, offset2;
4491 else if (GET_CODE (addr1) == PLUS
4492 && REG_P (XEXP (addr1, 0))
4493 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4495 reg1 = XEXP (addr1, 0);
4496 offset1 = INTVAL (XEXP (addr1, 1));
4506 else if (GET_CODE (addr2) == PLUS
4507 && REG_P (XEXP (addr2, 0))
4508 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4510 reg2 = XEXP (addr2, 0);
4511 offset2 = INTVAL (XEXP (addr2, 1));
4516 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4517 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4519 && offset1 + 1 == offset2)