1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Forward declarations. */
50 static const char *byte_reg (rtx, int);
51 static int h8300_interrupt_function_p (tree);
52 static int h8300_saveall_function_p (tree);
53 static int h8300_monitor_function_p (tree);
54 static int h8300_os_task_function_p (tree);
55 static void h8300_emit_stack_adjustment (int, unsigned int);
56 static int round_frame_size (int);
57 static unsigned int compute_saved_regs (void);
58 static void push (int);
59 static void pop (int);
60 static const char *cond_string (enum rtx_code);
61 static unsigned int h8300_asm_insn_count (const char *);
62 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
65 #ifndef OBJECT_FORMAT_ELF
66 static void h8300_asm_named_section (const char *, unsigned int);
68 static int h8300_and_costs (rtx);
69 static int h8300_shift_costs (rtx);
71 /* CPU_TYPE, says what cpu we're compiling for. */
74 /* True if a #pragma interrupt has been seen for the current function. */
75 static int pragma_interrupt;
77 /* True if a #pragma saveall has been seen for the current function. */
78 static int pragma_saveall;
80 static const char *const names_big[] =
81 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
83 static const char *const names_extended[] =
84 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
86 static const char *const names_upper_extended[] =
87 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
89 /* Points to one of the above. */
90 /* ??? The above could be put in an array indexed by CPU_TYPE. */
91 const char * const *h8_reg_names;
93 /* Various operations needed by the following, indexed by CPU_TYPE. */
95 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
97 /* Machine-specific symbol_ref flags. */
98 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
102 /* See below where shifts are handled for explanation of this enum. */
112 /* Symbols of the various shifts which can be used as indices. */
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
119 /* Macros to keep the shift algorithm tables small. */
120 #define INL SHIFT_INLINE
121 #define ROT SHIFT_ROT_AND
122 #define LOP SHIFT_LOOP
123 #define SPC SHIFT_SPECIAL
125 /* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
128 by, in the order of indices, machine, shift type, and shift count. */
130 static enum shift_alg shift_alg_qi[3][3][8] = {
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
154 static enum shift_alg shift_alg_hi[3][3][16] = {
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
190 static enum shift_alg shift_alg_si[3][3][32] = {
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
262 /* Initialize various cpu specific globals at start up. */
265 h8300_init_once (void)
267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
278 /* For this we treat the H8/300H and H8S the same. */
279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
286 if (!TARGET_H8300S && TARGET_MAC)
288 error ("-ms2600 is used without -ms");
289 target_flags |= MASK_H8300S;
292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
294 error ("-mn is used without -mh or -ms");
295 target_flags ^= MASK_NORMAL_MODE;
298 /* Some of the shifts are optimized for speed by default.
299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
300 If optimizing for size, change shift_alg for those shift to
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
333 /* Return the byte register name for a register rtx X. B should be 0
334 if you want a lower byte register. B should be 1 if you want an
335 upper byte register. */
338 byte_reg (rtx x, int b)
340 static const char *const names_small[] = {
341 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
342 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
348 return names_small[REGNO (x) * 2 + b];
351 /* REGNO must be saved/restored across calls if this macro is true. */
353 #define WORD_REG_USED(regno) \
355 /* No need to save registers if this function will not return. */ \
356 && ! TREE_THIS_VOLATILE (current_function_decl) \
357 && (h8300_saveall_function_p (current_function_decl) \
358 /* Save any call saved register that was used. */ \
359 || (regs_ever_live[regno] && !call_used_regs[regno]) \
360 /* Save the frame pointer if it was used. */ \
361 || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
362 /* Save any register used in an interrupt handler. */ \
363 || (h8300_current_function_interrupt_function_p () \
364 && regs_ever_live[regno]) \
365 /* Save call clobbered registers in non-leaf interrupt \
367 || (h8300_current_function_interrupt_function_p () \
368 && call_used_regs[regno] \
369 && !current_function_is_leaf)))
371 /* Output assembly language to FILE for the operation OP with operand size
372 SIZE to adjust the stack pointer. */
375 h8300_emit_stack_adjustment (int sign, unsigned int size)
377 /* If the frame size is 0, we don't have anything to do. */
381 /* H8/300 cannot add/subtract a large constant with a single
382 instruction. If a temporary register is available, load the
383 constant to it and then do the addition. */
386 && !h8300_current_function_interrupt_function_p ()
387 && !(current_function_needs_context && sign < 0))
389 rtx r3 = gen_rtx_REG (Pmode, 3);
390 emit_insn (gen_movhi (r3, GEN_INT (sign * size)));
391 emit_insn (gen_addhi3 (stack_pointer_rtx,
392 stack_pointer_rtx, r3));
396 /* The stack adjustment made here is further optimized by the
397 splitter. In case of H8/300, the splitter always splits the
398 addition emitted here to make the adjustment
401 emit_insn (gen_addhi3 (stack_pointer_rtx,
402 stack_pointer_rtx, GEN_INT (sign * size)));
404 emit_insn (gen_addsi3 (stack_pointer_rtx,
405 stack_pointer_rtx, GEN_INT (sign * size)));
409 /* Round up frame size SIZE. */
412 round_frame_size (int size)
414 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
415 & -STACK_BOUNDARY / BITS_PER_UNIT);
418 /* Compute which registers to push/pop.
419 Return a bit vector of registers. */
422 compute_saved_regs (void)
424 unsigned int saved_regs = 0;
427 /* Construct a bit vector of registers to be pushed/popped. */
428 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
430 if (WORD_REG_USED (regno))
431 saved_regs |= 1 << regno;
434 /* Don't push/pop the frame pointer as it is treated separately. */
435 if (frame_pointer_needed)
436 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
441 /* Emit an insn to push register RN. */
446 rtx reg = gen_rtx_REG (word_mode, rn);
450 x = gen_push_h8300 (reg);
451 else if (!TARGET_NORMAL_MODE)
452 x = gen_push_h8300hs_advanced (reg);
454 x = gen_push_h8300hs_normal (reg);
456 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
459 /* Emit an insn to pop register RN. */
464 rtx reg = gen_rtx_REG (word_mode, rn);
468 x = gen_pop_h8300 (reg);
469 else if (!TARGET_NORMAL_MODE)
470 x = gen_pop_h8300hs_advanced (reg);
472 x = gen_pop_h8300hs_normal (reg);
474 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
477 /* This is what the stack looks like after the prolog of
478 a function with a frame has been set up:
484 <saved registers> <- sp
486 This is what the stack looks like after the prolog of
487 a function which doesn't have a frame:
492 <saved registers> <- sp
495 /* Generate RTL code for the function prologue. */
498 h8300_expand_prologue (void)
504 /* If the current function has the OS_Task attribute set, then
505 we have a naked prologue. */
506 if (h8300_os_task_function_p (current_function_decl))
509 if (h8300_monitor_function_p (current_function_decl))
510 /* My understanding of monitor functions is they act just like
511 interrupt functions, except the prologue must mask
513 emit_insn (gen_monitor_prologue ());
515 if (frame_pointer_needed)
518 push (HARD_FRAME_POINTER_REGNUM);
519 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
522 /* Push the rest of the registers in ascending order. */
523 saved_regs = compute_saved_regs ();
524 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
527 if (saved_regs & (1 << regno))
531 /* See how many registers we can push at the same time. */
532 if ((regno == 0 || regno == 4)
533 && ((saved_regs >> regno) & 0x0f) == 0x0f)
536 else if ((regno == 0 || regno == 4)
537 && ((saved_regs >> regno) & 0x07) == 0x07)
540 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
541 && ((saved_regs >> regno) & 0x03) == 0x03)
551 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
552 gen_rtx_REG (SImode, regno + 1)));
555 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
556 gen_rtx_REG (SImode, regno + 1),
557 gen_rtx_REG (SImode, regno + 2)));
560 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
561 gen_rtx_REG (SImode, regno + 1),
562 gen_rtx_REG (SImode, regno + 2),
563 gen_rtx_REG (SImode, regno + 3)));
571 /* Leave room for locals. */
572 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
575 /* Return nonzero if we can use "rts" for the function currently being
579 h8300_can_use_return_insn_p (void)
581 return (reload_completed
582 && !frame_pointer_needed
583 && get_frame_size () == 0
584 && compute_saved_regs () == 0);
587 /* Generate RTL code for the function epilogue. */
590 h8300_expand_epilogue (void)
596 if (h8300_os_task_function_p (current_function_decl))
597 /* OS_Task epilogues are nearly naked -- they just have an
601 /* Deallocate locals. */
602 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
604 /* Pop the saved registers in descending order. */
605 saved_regs = compute_saved_regs ();
606 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
609 if (saved_regs & (1 << regno))
613 /* See how many registers we can pop at the same time. */
614 if ((regno == 7 || regno == 3)
615 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
618 else if ((regno == 6 || regno == 2)
619 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
622 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
623 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
633 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
634 gen_rtx_REG (SImode, regno)));
637 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
638 gen_rtx_REG (SImode, regno - 1),
639 gen_rtx_REG (SImode, regno)));
642 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
643 gen_rtx_REG (SImode, regno - 2),
644 gen_rtx_REG (SImode, regno - 1),
645 gen_rtx_REG (SImode, regno)));
653 /* Pop frame pointer if we had one. */
654 if (frame_pointer_needed)
655 pop (HARD_FRAME_POINTER_REGNUM);
658 /* Return nonzero if the current function is an interrupt
662 h8300_current_function_interrupt_function_p (void)
664 return (h8300_interrupt_function_p (current_function_decl)
665 || h8300_monitor_function_p (current_function_decl));
668 /* Output assembly code for the start of the file. */
671 h8300_file_start (void)
673 default_file_start ();
676 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
677 else if (TARGET_H8300S)
678 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
681 /* Output assembly language code for the end of file. */
684 h8300_file_end (void)
686 fputs ("\t.end\n", asm_out_file);
689 /* Return true if OP is a valid source operand for an integer move
693 general_operand_src (rtx op, enum machine_mode mode)
695 if (GET_MODE (op) == mode
696 && GET_CODE (op) == MEM
697 && GET_CODE (XEXP (op, 0)) == POST_INC)
699 return general_operand (op, mode);
702 /* Return true if OP is a valid destination operand for an integer move
706 general_operand_dst (rtx op, enum machine_mode mode)
708 if (GET_MODE (op) == mode
709 && GET_CODE (op) == MEM
710 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
712 return general_operand (op, mode);
715 /* Return true if OP is a constant that contains only one 1 in its
716 binary representation. */
719 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
721 if (GET_CODE (operand) == CONST_INT)
723 /* We really need to do this masking because 0x80 in QImode is
724 represented as -128 for example. */
725 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
732 /* Return true if OP is a constant that contains only one 0 in its
733 binary representation. */
736 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
738 if (GET_CODE (operand) == CONST_INT)
740 /* We really need to do this masking because 0x80 in QImode is
741 represented as -128 for example. */
742 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
749 /* Return true if OP is a valid call operand. */
752 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
754 if (GET_CODE (op) == MEM)
756 rtx inside = XEXP (op, 0);
757 if (register_operand (inside, Pmode))
759 if (CONSTANT_ADDRESS_P (inside))
765 /* Return 1 if an addition/subtraction of a constant integer can be
766 transformed into two consecutive adds/subs that are faster than the
767 straightforward way. Otherwise, return 0. */
770 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
772 if (GET_CODE (op) == CONST_INT)
774 HOST_WIDE_INT value = INTVAL (op);
776 /* Force VALUE to be positive so that we do not have to consider
777 the negative case. */
780 if (TARGET_H8300H || TARGET_H8300S)
782 /* A constant addition/subtraction takes 2 states in QImode,
783 4 states in HImode, and 6 states in SImode. Thus, the
784 only case we can win is when SImode is used, in which
785 case, two adds/subs are used, taking 4 states. */
795 /* We do not profit directly by splitting addition or
796 subtraction of 3 and 4. However, since these are
797 implemented as a sequence of adds or subs, they do not
798 clobber (cc0) unlike a sequence of add.b and add.x. */
809 /* Split an add of a small constant into two adds/subs insns.
811 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
812 instead of adds/subs. */
815 split_adds_subs (enum machine_mode mode, rtx *operands)
817 HOST_WIDE_INT val = INTVAL (operands[1]);
818 rtx reg = operands[0];
819 HOST_WIDE_INT sign = 1;
820 HOST_WIDE_INT amount;
821 rtx (*gen_add) (rtx, rtx, rtx);
823 /* Force VAL to be positive so that we do not have to consider the
834 gen_add = gen_addhi3;
838 gen_add = gen_addsi3;
845 /* Try different amounts in descending order. */
846 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
850 for (; val >= amount; val -= amount)
851 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
857 /* Return true if OP is a valid call operand, and OP represents
858 an operand for a small call (4 bytes instead of 6 bytes). */
861 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
863 if (GET_CODE (op) == MEM)
865 rtx inside = XEXP (op, 0);
867 /* Register indirect is a small call. */
868 if (register_operand (inside, Pmode))
871 /* A call through the function vector is a small call too. */
872 if (GET_CODE (inside) == SYMBOL_REF
873 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
876 /* Otherwise it's a large call. */
880 /* Return true if OP is a valid jump operand. */
883 jump_address_operand (rtx op, enum machine_mode mode)
885 if (GET_CODE (op) == REG)
886 return mode == Pmode;
888 if (GET_CODE (op) == MEM)
890 rtx inside = XEXP (op, 0);
891 if (register_operand (inside, Pmode))
893 if (CONSTANT_ADDRESS_P (inside))
899 /* Recognize valid operands for bit-field instructions. */
902 bit_operand (rtx op, enum machine_mode mode)
904 /* We can accept any general operand, except that MEM operands must
905 be limited to those that use addresses valid for the 'U' constraint. */
906 if (!general_operand (op, mode))
909 /* Accept any mem during RTL generation. Otherwise, the code that does
910 insv and extzv will think that we can not handle memory. However,
911 to avoid reload problems, we only accept 'U' MEM operands after RTL
912 generation. This means that any named pattern which uses this predicate
913 must force its operands to match 'U' before emitting RTL. */
915 if (GET_CODE (op) == REG)
917 if (GET_CODE (op) == SUBREG)
919 return (GET_CODE (op) == MEM
920 && EXTRA_CONSTRAINT (op, 'U'));
923 /* Return nonzero if OP is a MEM suitable for bit manipulation insns. */
926 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
928 return (GET_CODE (op) == MEM
929 && EXTRA_CONSTRAINT (op, 'U'));
932 /* Handle machine specific pragmas for compatibility with existing
933 compilers for the H8/300.
935 pragma saveall generates prologue/epilogue code which saves and
936 restores all the registers on function entry.
938 pragma interrupt saves and restores all registers, and exits with
939 an rte instruction rather than an rts. A pointer to a function
940 with this attribute may be safely used in an interrupt vector. */
943 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
945 pragma_interrupt = 1;
949 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
954 /* If the next function argument with MODE and TYPE is to be passed in
955 a register, return a reg RTX for the hard register in which to pass
956 the argument. CUM represents the state after the last argument.
957 If the argument is to be pushed, NULL_RTX is returned. */
960 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
961 tree type, int named)
963 static const char *const hand_list[] = {
982 rtx result = NULL_RTX;
986 /* Never pass unnamed arguments in registers. */
990 /* Pass 3 regs worth of data in regs when user asked on the command line. */
991 if (TARGET_QUICKCALL)
994 /* If calling hand written assembler, use 4 regs of args. */
997 const char * const *p;
999 fname = XSTR (cum->libcall, 0);
1001 /* See if this libcall is one of the hand coded ones. */
1002 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1013 if (mode == BLKmode)
1014 size = int_size_in_bytes (type);
1016 size = GET_MODE_SIZE (mode);
1018 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1019 && cum->nbytes / UNITS_PER_WORD <= 3)
1020 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1026 /* Compute the cost of an and insn. */
1029 h8300_and_costs (rtx x)
1033 if (GET_MODE (x) == QImode)
1036 if (GET_MODE (x) != HImode
1037 && GET_MODE (x) != SImode)
1042 operands[2] = XEXP (x, 1);
1044 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1047 /* Compute the cost of a shift insn. */
1050 h8300_shift_costs (rtx x)
1054 if (GET_MODE (x) != QImode
1055 && GET_MODE (x) != HImode
1056 && GET_MODE (x) != SImode)
1061 operands[2] = XEXP (x, 1);
1063 return compute_a_shift_length (NULL, operands) / 2;
1066 /* Worker function for TARGET_RTX_COSTS. */
1069 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1075 HOST_WIDE_INT n = INTVAL (x);
1077 if (-4 <= n || n <= 4)
1088 *total = 0 + (outer_code == SET);
1092 if (TARGET_H8300H || TARGET_H8300S)
1093 *total = 0 + (outer_code == SET);
1114 *total = COSTS_N_INSNS (h8300_and_costs (x));
1117 /* We say that MOD and DIV are so expensive because otherwise we'll
1118 generate some really horrible code for division of a power of two. */
1131 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1136 if (GET_MODE (x) == HImode)
1148 /* Documentation for the machine specific operand escapes:
1150 'E' like s but negative.
1151 'F' like t but negative.
1152 'G' constant just the negative
1153 'R' print operand as a byte:8 address if appropriate, else fall back to
1155 'S' print operand as a long word
1156 'T' print operand as a word
1157 'V' find the set bit, and print its number.
1158 'W' find the clear bit, and print its number.
1159 'X' print operand as a byte
1160 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1161 If this operand isn't a register, fall back to 'R' handling.
1163 'c' print the opcode corresponding to rtl
1164 'e' first word of 32 bit value - if reg, then least reg. if mem
1165 then least. if const then most sig word
1166 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1167 then +2. if const then least sig word
1168 'j' print operand as condition code.
1169 'k' print operand as reverse condition code.
1170 's' print as low byte of 16 bit value
1171 't' print as high byte of 16 bit value
1172 'w' print as low byte of 32 bit value
1173 'x' print as 2nd byte of 32 bit value
1174 'y' print as 3rd byte of 32 bit value
1175 'z' print as msb of 32 bit value
1178 /* Return assembly language string which identifies a comparison type. */
1181 cond_string (enum rtx_code code)
1210 /* Print operand X using operand code CODE to assembly language output file
1214 print_operand (FILE *file, rtx x, int code)
1216 /* This is used for communication between codes V,W,Z and Y. */
1222 switch (GET_CODE (x))
1225 fprintf (file, "%sl", names_big[REGNO (x)]);
1228 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1235 switch (GET_CODE (x))
1238 fprintf (file, "%sh", names_big[REGNO (x)]);
1241 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1248 if (GET_CODE (x) != CONST_INT)
1250 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1253 if (GET_CODE (x) == REG)
1254 fprintf (file, "%s", names_extended[REGNO (x)]);
1259 if (GET_CODE (x) == REG)
1260 fprintf (file, "%s", names_big[REGNO (x)]);
1265 bitint = exact_log2 (INTVAL (x) & 0xff);
1268 fprintf (file, "#%d", bitint);
1271 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1274 fprintf (file, "#%d", bitint);
1278 if (GET_CODE (x) == REG)
1279 fprintf (file, "%s", byte_reg (x, 0));
1286 if (GET_CODE (x) == REG)
1287 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1289 print_operand (file, x, 'R');
1293 bitint = INTVAL (x);
1294 fprintf (file, "#%d", bitint & 7);
1297 switch (GET_CODE (x))
1300 fprintf (file, "or");
1303 fprintf (file, "xor");
1306 fprintf (file, "and");
1313 switch (GET_CODE (x))
1317 fprintf (file, "%s", names_big[REGNO (x)]);
1319 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1322 print_operand (file, x, 0);
1325 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1331 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1332 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1333 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1342 switch (GET_CODE (x))
1346 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1348 fprintf (file, "%s", names_big[REGNO (x)]);
1351 x = adjust_address (x, HImode, 2);
1352 print_operand (file, x, 0);
1355 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1361 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1362 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1363 fprintf (file, "#%ld", (val & 0xffff));
1371 fputs (cond_string (GET_CODE (x)), file);
1374 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1377 if (GET_CODE (x) == CONST_INT)
1378 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1380 fprintf (file, "%s", byte_reg (x, 0));
1383 if (GET_CODE (x) == CONST_INT)
1384 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1386 fprintf (file, "%s", byte_reg (x, 1));
1389 if (GET_CODE (x) == CONST_INT)
1390 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1392 fprintf (file, "%s",
1393 byte_reg (x, TARGET_H8300 ? 2 : 0));
1396 if (GET_CODE (x) == CONST_INT)
1397 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1399 fprintf (file, "%s",
1400 byte_reg (x, TARGET_H8300 ? 3 : 1));
1403 if (GET_CODE (x) == CONST_INT)
1404 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1406 fprintf (file, "%s", byte_reg (x, 0));
1409 if (GET_CODE (x) == CONST_INT)
1410 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1412 fprintf (file, "%s", byte_reg (x, 1));
1417 switch (GET_CODE (x))
1420 switch (GET_MODE (x))
1423 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1424 fprintf (file, "%s", byte_reg (x, 0));
1425 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1426 fprintf (file, "%s", names_big[REGNO (x)]);
1430 fprintf (file, "%s", names_big[REGNO (x)]);
1434 fprintf (file, "%s", names_extended[REGNO (x)]);
1443 rtx addr = XEXP (x, 0);
1445 fprintf (file, "@");
1446 output_address (addr);
1448 /* We fall back from smaller addressing to larger
1449 addressing in various ways depending on CODE. */
1453 /* Used for mov.b and bit operations. */
1454 if (h8300_eightbit_constant_address_p (addr))
1456 fprintf (file, ":8");
1460 /* Fall through. We should not get here if we are
1461 processing bit operations on H8/300 or H8/300H
1462 because 'U' constraint does not allow bit
1463 operations on the tiny area on these machines. */
1467 /* Used for mov.w and mov.l. */
1468 if (h8300_tiny_constant_address_p (addr))
1469 fprintf (file, ":16");
1481 fprintf (file, "#");
1482 print_operand_address (file, x);
1488 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1489 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1490 fprintf (file, "#%ld", val);
1499 /* Output assembly language output for the address ADDR to FILE. */
1502 print_operand_address (FILE *file, rtx addr)
1504 switch (GET_CODE (addr))
1507 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1511 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1515 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1519 fprintf (file, "(");
1520 if (GET_CODE (XEXP (addr, 0)) == REG)
1523 print_operand_address (file, XEXP (addr, 1));
1524 fprintf (file, ",");
1525 print_operand_address (file, XEXP (addr, 0));
1530 print_operand_address (file, XEXP (addr, 0));
1531 fprintf (file, "+");
1532 print_operand_address (file, XEXP (addr, 1));
1534 fprintf (file, ")");
1539 /* Since the H8/300 only has 16 bit pointers, negative values are also
1540 those >= 32768. This happens for example with pointer minus a
1541 constant. We don't want to turn (char *p - 2) into
1542 (char *p + 65534) because loop unrolling can build upon this
1543 (IE: char *p + 131068). */
1544 int n = INTVAL (addr);
1546 n = (int) (short) n;
1547 fprintf (file, "%d", n);
1552 output_addr_const (file, addr);
1557 /* Output all insn addresses and their sizes into the assembly language
1558 output file. This is helpful for debugging whether the length attributes
1559 in the md file are correct. This is not meant to be a user selectable
1563 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1564 int num_operands ATTRIBUTE_UNUSED)
1566 /* This holds the last insn address. */
1567 static int last_insn_address = 0;
1569 const int uid = INSN_UID (insn);
1571 if (TARGET_ADDRESSES)
1573 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1574 INSN_ADDRESSES (uid) - last_insn_address);
1575 last_insn_address = INSN_ADDRESSES (uid);
1579 /* Prepare for an SI sized move. */
1582 h8300_expand_movsi (rtx operands[])
1584 rtx src = operands[1];
1585 rtx dst = operands[0];
1586 if (!reload_in_progress && !reload_completed)
1588 if (!register_operand (dst, GET_MODE (dst)))
1590 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1591 emit_move_insn (tmp, src);
1598 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1599 Define the offset between two registers, one to be eliminated, and
1600 the other its replacement, at the start of a routine. */
1603 h8300_initial_elimination_offset (int from, int to)
1605 /* The number of bytes that the return address takes on the stack. */
1606 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1608 /* The number of bytes that the saved frame pointer takes on the stack. */
1609 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1611 /* The number of bytes that the saved registers, excluding the frame
1612 pointer, take on the stack. */
1613 int saved_regs_size = 0;
1615 /* The number of bytes that the locals takes on the stack. */
1616 int frame_size = round_frame_size (get_frame_size ());
1620 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1621 if (WORD_REG_USED (regno))
1622 saved_regs_size += UNITS_PER_WORD;
1624 /* Adjust saved_regs_size because the above loop took the frame
1625 pointer int account. */
1626 saved_regs_size -= fp_size;
1628 if (to == HARD_FRAME_POINTER_REGNUM)
1632 case ARG_POINTER_REGNUM:
1633 return pc_size + fp_size;
1634 case RETURN_ADDRESS_POINTER_REGNUM:
1636 case FRAME_POINTER_REGNUM:
1637 return -saved_regs_size;
1642 else if (to == STACK_POINTER_REGNUM)
1646 case ARG_POINTER_REGNUM:
1647 return pc_size + saved_regs_size + frame_size;
1648 case RETURN_ADDRESS_POINTER_REGNUM:
1649 return saved_regs_size + frame_size;
1650 case FRAME_POINTER_REGNUM:
1660 /* Worker function for RETURN_ADDR_RTX. */
1663 h8300_return_addr_rtx (int count, rtx frame)
1668 ret = gen_rtx_MEM (Pmode,
1669 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1670 else if (flag_omit_frame_pointer)
1673 ret = gen_rtx_MEM (Pmode,
1674 memory_address (Pmode,
1675 plus_constant (frame, UNITS_PER_WORD)));
1676 set_mem_alias_set (ret, get_frame_alias_set ());
1680 /* Update the condition code from the insn. */
1683 notice_update_cc (rtx body, rtx insn)
1687 switch (get_attr_cc (insn))
1690 /* Insn does not affect CC at all. */
1694 /* Insn does not change CC, but the 0'th operand has been changed. */
1695 if (cc_status.value1 != 0
1696 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1697 cc_status.value1 = 0;
1698 if (cc_status.value2 != 0
1699 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1700 cc_status.value2 = 0;
1704 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1705 The V flag is unusable. The C flag may or may not be known but
1706 that's ok because alter_cond will change tests to use EQ/NE. */
1708 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1709 set = single_set (insn);
1710 cc_status.value1 = SET_SRC (set);
1711 if (SET_DEST (set) != cc0_rtx)
1712 cc_status.value2 = SET_DEST (set);
1716 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1717 The C flag may or may not be known but that's ok because
1718 alter_cond will change tests to use EQ/NE. */
1720 cc_status.flags |= CC_NO_CARRY;
1721 set = single_set (insn);
1722 cc_status.value1 = SET_SRC (set);
1723 if (SET_DEST (set) != cc0_rtx)
1725 /* If the destination is STRICT_LOW_PART, strip off
1727 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1728 cc_status.value2 = XEXP (SET_DEST (set), 0);
1730 cc_status.value2 = SET_DEST (set);
1735 /* The insn is a compare instruction. */
1737 cc_status.value1 = SET_SRC (body);
1741 /* Insn doesn't leave CC in a usable state. */
1747 /* Return nonzero if X is a stack pointer. */
1750 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1752 return x == stack_pointer_rtx;
1755 /* Return nonzero if X is a constant whose absolute value is greater
1759 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1761 return (GET_CODE (x) == CONST_INT
1762 && abs (INTVAL (x)) > 2);
1765 /* Return nonzero if X is a constant whose absolute value is no
1769 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1771 return (GET_CODE (x) == CONST_INT
1772 && abs (INTVAL (x)) >= 8);
1775 /* Return nonzero if X is a constant expressible in QImode. */
1778 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1780 return (GET_CODE (x) == CONST_INT
1781 && (INTVAL (x) & 0xff) == INTVAL (x));
1784 /* Return nonzero if X is a constant expressible in HImode. */
1787 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1789 return (GET_CODE (x) == CONST_INT
1790 && (INTVAL (x) & 0xffff) == INTVAL (x));
1793 /* Return nonzero if X is a constant suitable for inc/dec. */
1796 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1798 return (GET_CODE (x) == CONST_INT
1799 && (CONST_OK_FOR_M (INTVAL (x))
1800 || CONST_OK_FOR_O (INTVAL (x))));
1803 /* Return nonzero if X is either EQ or NE. */
1806 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1808 enum rtx_code code = GET_CODE (x);
1810 return (code == EQ || code == NE);
1813 /* Return nonzero if X is either GT or LE. */
1816 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1818 enum rtx_code code = GET_CODE (x);
1820 return (code == GT || code == LE);
1823 /* Return nonzero if X is either GTU or LEU. */
1826 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1828 enum rtx_code code = GET_CODE (x);
1830 return (code == GTU || code == LEU);
1833 /* Return nonzero if X is either IOR or XOR. */
1836 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1838 enum rtx_code code = GET_CODE (x);
1840 return (code == IOR || code == XOR);
1843 /* Recognize valid operators for bit instructions. */
1846 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1848 enum rtx_code code = GET_CODE (x);
1855 /* Return the length of mov instruction. */
1858 compute_mov_length (rtx *operands)
1860 /* If the mov instruction involves a memory operand, we compute the
1861 length, assuming the largest addressing mode is used, and then
1862 adjust later in the function. Otherwise, we compute and return
1863 the exact length in one step. */
1864 enum machine_mode mode = GET_MODE (operands[0]);
1865 rtx dest = operands[0];
1866 rtx src = operands[1];
1869 if (GET_CODE (src) == MEM)
1870 addr = XEXP (src, 0);
1871 else if (GET_CODE (dest) == MEM)
1872 addr = XEXP (dest, 0);
1878 unsigned int base_length;
1883 if (addr == NULL_RTX)
1886 /* The eightbit addressing is available only in QImode, so
1887 go ahead and take care of it. */
1888 if (h8300_eightbit_constant_address_p (addr))
1895 if (addr == NULL_RTX)
1900 if (src == const0_rtx)
1910 if (addr == NULL_RTX)
1915 if (GET_CODE (src) == CONST_INT)
1917 if (src == const0_rtx)
1920 if ((INTVAL (src) & 0xffff) == 0)
1923 if ((INTVAL (src) & 0xffff) == 0)
1926 if ((INTVAL (src) & 0xffff)
1927 == ((INTVAL (src) >> 16) & 0xffff))
1937 if (addr == NULL_RTX)
1942 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1955 /* Adjust the length based on the addressing mode used.
1956 Specifically, we subtract the difference between the actual
1957 length and the longest one, which is @(d:16,Rs). For SImode
1958 and SFmode, we double the adjustment because two mov.w are
1959 used to do the job. */
1961 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1962 if (GET_CODE (addr) == PRE_DEC
1963 || GET_CODE (addr) == POST_INC)
1965 if (mode == QImode || mode == HImode)
1966 return base_length - 2;
1968 /* In SImode and SFmode, we use two mov.w instructions, so
1969 double the adjustment. */
1970 return base_length - 4;
1973 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1974 in SImode and SFmode, the second mov.w involves an address
1975 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1977 if (GET_CODE (addr) == REG)
1978 return base_length - 2;
1984 unsigned int base_length;
1989 if (addr == NULL_RTX)
1992 /* The eightbit addressing is available only in QImode, so
1993 go ahead and take care of it. */
1994 if (h8300_eightbit_constant_address_p (addr))
2001 if (addr == NULL_RTX)
2006 if (src == const0_rtx)
2016 if (addr == NULL_RTX)
2020 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2026 if (GET_CODE (src) == CONST_INT)
2028 int val = INTVAL (src);
2033 if (val == (val & 0x00ff) || val == (val & 0xff00))
2036 switch (val & 0xffffffff)
2057 if (addr == NULL_RTX)
2062 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2075 /* Adjust the length based on the addressing mode used.
2076 Specifically, we subtract the difference between the actual
2077 length and the longest one, which is @(d:24,ERs). */
2079 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2080 if (GET_CODE (addr) == PRE_DEC
2081 || GET_CODE (addr) == POST_INC)
2082 return base_length - 6;
2084 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2085 if (GET_CODE (addr) == REG)
2086 return base_length - 6;
2088 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2090 if (GET_CODE (addr) == PLUS
2091 && GET_CODE (XEXP (addr, 0)) == REG
2092 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2093 && INTVAL (XEXP (addr, 1)) > -32768
2094 && INTVAL (XEXP (addr, 1)) < 32767)
2095 return base_length - 4;
2097 /* @aa:16 is 4 bytes shorter than the longest. */
2098 if (h8300_tiny_constant_address_p (addr))
2099 return base_length - 4;
2101 /* @aa:24 is 2 bytes shorter than the longest. */
2102 if (CONSTANT_P (addr))
2103 return base_length - 2;
2109 /* Output an addition insn. */
2112 output_plussi (rtx *operands)
2114 enum machine_mode mode = GET_MODE (operands[0]);
2121 if (GET_CODE (operands[2]) == REG)
2122 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2124 if (GET_CODE (operands[2]) == CONST_INT)
2126 HOST_WIDE_INT n = INTVAL (operands[2]);
2128 if ((n & 0xffffff) == 0)
2129 return "add\t%z2,%z0";
2130 if ((n & 0xffff) == 0)
2131 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2132 if ((n & 0xff) == 0)
2133 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2136 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2140 if (GET_CODE (operands[2]) == REG)
2141 return "add.l\t%S2,%S0";
2143 if (GET_CODE (operands[2]) == CONST_INT)
2145 HOST_WIDE_INT intval = INTVAL (operands[2]);
2147 /* See if we can finish with 2 bytes. */
2149 switch ((unsigned int) intval & 0xffffffff)
2154 return "adds\t%2,%S0";
2159 return "subs\t%G2,%S0";
2163 operands[2] = GEN_INT (intval >> 16);
2164 return "inc.w\t%2,%e0";
2168 operands[2] = GEN_INT (intval >> 16);
2169 return "dec.w\t%G2,%e0";
2172 /* See if we can finish with 4 bytes. */
2173 if ((intval & 0xffff) == 0)
2175 operands[2] = GEN_INT (intval >> 16);
2176 return "add.w\t%2,%e0";
2180 return "add.l\t%S2,%S0";
2184 /* Compute the length of an addition insn. */
2187 compute_plussi_length (rtx *operands)
2189 enum machine_mode mode = GET_MODE (operands[0]);
2196 if (GET_CODE (operands[2]) == REG)
2199 if (GET_CODE (operands[2]) == CONST_INT)
2201 HOST_WIDE_INT n = INTVAL (operands[2]);
2203 if ((n & 0xffffff) == 0)
2205 if ((n & 0xffff) == 0)
2207 if ((n & 0xff) == 0)
2215 if (GET_CODE (operands[2]) == REG)
2218 if (GET_CODE (operands[2]) == CONST_INT)
2220 HOST_WIDE_INT intval = INTVAL (operands[2]);
2222 /* See if we can finish with 2 bytes. */
2224 switch ((unsigned int) intval & 0xffffffff)
2245 /* See if we can finish with 4 bytes. */
2246 if ((intval & 0xffff) == 0)
2254 /* Compute which flag bits are valid after an addition insn. */
2257 compute_plussi_cc (rtx *operands)
2259 enum machine_mode mode = GET_MODE (operands[0]);
2270 if (GET_CODE (operands[2]) == REG)
2273 if (GET_CODE (operands[2]) == CONST_INT)
2275 HOST_WIDE_INT intval = INTVAL (operands[2]);
2277 /* See if we can finish with 2 bytes. */
2279 switch ((unsigned int) intval & 0xffffffff)
2284 return CC_NONE_0HIT;
2289 return CC_NONE_0HIT;
2300 /* See if we can finish with 4 bytes. */
2301 if ((intval & 0xffff) == 0)
2309 /* Output a logical insn. */
2312 output_logical_op (enum machine_mode mode, rtx *operands)
2314 /* Figure out the logical op that we need to perform. */
2315 enum rtx_code code = GET_CODE (operands[3]);
2316 /* Pretend that every byte is affected if both operands are registers. */
2317 const unsigned HOST_WIDE_INT intval =
2318 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2319 ? INTVAL (operands[2]) : 0x55555555);
2320 /* The determinant of the algorithm. If we perform an AND, 0
2321 affects a bit. Otherwise, 1 affects a bit. */
2322 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2323 /* Break up DET into pieces. */
2324 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2325 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2326 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2327 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2328 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2329 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2330 int lower_half_easy_p = 0;
2331 int upper_half_easy_p = 0;
2332 /* The name of an insn. */
2354 /* First, see if we can finish with one insn. */
2355 if ((TARGET_H8300H || TARGET_H8300S)
2359 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2360 output_asm_insn (insn_buf, operands);
2364 /* Take care of the lower byte. */
2367 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2368 output_asm_insn (insn_buf, operands);
2370 /* Take care of the upper byte. */
2373 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2374 output_asm_insn (insn_buf, operands);
2379 if (TARGET_H8300H || TARGET_H8300S)
2381 /* Determine if the lower half can be taken care of in no more
2383 lower_half_easy_p = (b0 == 0
2385 || (code != IOR && w0 == 0xffff));
2387 /* Determine if the upper half can be taken care of in no more
2389 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2390 || (code == AND && w1 == 0xff00));
2393 /* Check if doing everything with one insn is no worse than
2394 using multiple insns. */
2395 if ((TARGET_H8300H || TARGET_H8300S)
2396 && w0 != 0 && w1 != 0
2397 && !(lower_half_easy_p && upper_half_easy_p)
2398 && !(code == IOR && w1 == 0xffff
2399 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2401 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2402 output_asm_insn (insn_buf, operands);
2406 /* Take care of the lower and upper words individually. For
2407 each word, we try different methods in the order of
2409 1) the special insn (in case of AND or XOR),
2410 2) the word-wise insn, and
2411 3) The byte-wise insn. */
2413 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2414 output_asm_insn ((code == AND)
2415 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2417 else if ((TARGET_H8300H || TARGET_H8300S)
2421 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2422 output_asm_insn (insn_buf, operands);
2428 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2429 output_asm_insn (insn_buf, operands);
2433 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2434 output_asm_insn (insn_buf, operands);
2439 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2440 output_asm_insn ((code == AND)
2441 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2443 else if ((TARGET_H8300H || TARGET_H8300S)
2446 && (w0 & 0x8000) != 0)
2448 output_asm_insn ("exts.l\t%S0", operands);
2450 else if ((TARGET_H8300H || TARGET_H8300S)
2454 output_asm_insn ("extu.w\t%e0", operands);
2456 else if (TARGET_H8300H || TARGET_H8300S)
2460 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2461 output_asm_insn (insn_buf, operands);
2468 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2469 output_asm_insn (insn_buf, operands);
2473 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2474 output_asm_insn (insn_buf, operands);
2485 /* Compute the length of a logical insn. */
2488 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2490 /* Figure out the logical op that we need to perform. */
2491 enum rtx_code code = GET_CODE (operands[3]);
2492 /* Pretend that every byte is affected if both operands are registers. */
2493 const unsigned HOST_WIDE_INT intval =
2494 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2495 ? INTVAL (operands[2]) : 0x55555555);
2496 /* The determinant of the algorithm. If we perform an AND, 0
2497 affects a bit. Otherwise, 1 affects a bit. */
2498 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2499 /* Break up DET into pieces. */
2500 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2501 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2502 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2503 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2504 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2505 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2506 int lower_half_easy_p = 0;
2507 int upper_half_easy_p = 0;
2509 unsigned int length = 0;
2514 /* First, see if we can finish with one insn. */
2515 if ((TARGET_H8300H || TARGET_H8300S)
2519 if (REG_P (operands[2]))
2526 /* Take care of the lower byte. */
2530 /* Take care of the upper byte. */
2536 if (TARGET_H8300H || TARGET_H8300S)
2538 /* Determine if the lower half can be taken care of in no more
2540 lower_half_easy_p = (b0 == 0
2542 || (code != IOR && w0 == 0xffff));
2544 /* Determine if the upper half can be taken care of in no more
2546 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2547 || (code == AND && w1 == 0xff00));
2550 /* Check if doing everything with one insn is no worse than
2551 using multiple insns. */
2552 if ((TARGET_H8300H || TARGET_H8300S)
2553 && w0 != 0 && w1 != 0
2554 && !(lower_half_easy_p && upper_half_easy_p)
2555 && !(code == IOR && w1 == 0xffff
2556 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2558 if (REG_P (operands[2]))
2565 /* Take care of the lower and upper words individually. For
2566 each word, we try different methods in the order of
2568 1) the special insn (in case of AND or XOR),
2569 2) the word-wise insn, and
2570 3) The byte-wise insn. */
2572 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2576 else if ((TARGET_H8300H || TARGET_H8300S)
2592 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2596 else if ((TARGET_H8300H || TARGET_H8300S)
2599 && (w0 & 0x8000) != 0)
2603 else if ((TARGET_H8300H || TARGET_H8300S)
2609 else if (TARGET_H8300H || TARGET_H8300S)
2630 /* Compute which flag bits are valid after a logical insn. */
2633 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2635 /* Figure out the logical op that we need to perform. */
2636 enum rtx_code code = GET_CODE (operands[3]);
2637 /* Pretend that every byte is affected if both operands are registers. */
2638 const unsigned HOST_WIDE_INT intval =
2639 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2640 ? INTVAL (operands[2]) : 0x55555555);
2641 /* The determinant of the algorithm. If we perform an AND, 0
2642 affects a bit. Otherwise, 1 affects a bit. */
2643 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2644 /* Break up DET into pieces. */
2645 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2646 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2647 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2648 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2649 int lower_half_easy_p = 0;
2650 int upper_half_easy_p = 0;
2651 /* Condition code. */
2652 enum attr_cc cc = CC_CLOBBER;
2657 /* First, see if we can finish with one insn. */
2658 if ((TARGET_H8300H || TARGET_H8300S)
2666 if (TARGET_H8300H || TARGET_H8300S)
2668 /* Determine if the lower half can be taken care of in no more
2670 lower_half_easy_p = (b0 == 0
2672 || (code != IOR && w0 == 0xffff));
2674 /* Determine if the upper half can be taken care of in no more
2676 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2677 || (code == AND && w1 == 0xff00));
2680 /* Check if doing everything with one insn is no worse than
2681 using multiple insns. */
2682 if ((TARGET_H8300H || TARGET_H8300S)
2683 && w0 != 0 && w1 != 0
2684 && !(lower_half_easy_p && upper_half_easy_p)
2685 && !(code == IOR && w1 == 0xffff
2686 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2692 if ((TARGET_H8300H || TARGET_H8300S)
2695 && (w0 & 0x8000) != 0)
2707 /* Expand a conditional branch. */
2710 h8300_expand_branch (enum rtx_code code, rtx label)
2714 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
2715 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
2716 gen_rtx_LABEL_REF (VOIDmode, label),
2718 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
2723 We devote a fair bit of code to getting efficient shifts since we
2724 can only shift one bit at a time on the H8/300 and H8/300H and only
2725 one or two bits at a time on the H8S.
2727 All shift code falls into one of the following ways of
2730 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2731 when a straight line shift is about the same size or smaller than
2734 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2735 off the bits we don't need. This is used when only a few of the
2736 bits in the original value will survive in the shifted value.
2738 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2739 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2740 shifts can be added if the shift count is slightly more than 8 or
2741 16. This case also includes other oddballs that are not worth
2744 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2746 For each shift count, we try to use code that has no trade-off
2747 between code size and speed whenever possible.
2749 If the trade-off is unavoidable, we try to be reasonable.
2750 Specifically, the fastest version is one instruction longer than
2751 the shortest version, we take the fastest version. We also provide
2752 the use a way to switch back to the shortest version with -Os.
2754 For the details of the shift algorithms for various shift counts,
2755 refer to shift_alg_[qhs]i. */
2758 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2760 switch (GET_CODE (x))
2772 /* Emit code to do shifts. */
2775 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2777 emit_move_insn (operands[0], operands[1]);
2779 /* Need a loop to get all the bits we want - we generate the
2780 code at emit time, but need to allocate a scratch reg now. */
2782 emit_insn (gen_rtx_PARALLEL
2785 gen_rtx_SET (VOIDmode, operands[0],
2786 gen_rtx_fmt_ee (code, mode,
2787 operands[0], operands[2])),
2788 gen_rtx_CLOBBER (VOIDmode,
2789 gen_rtx_SCRATCH (QImode)))));
2792 /* Symbols of the various modes which can be used as indices. */
2796 QIshift, HIshift, SIshift
2799 /* For single bit shift insns, record assembler and what bits of the
2800 condition code are valid afterwards (represented as various CC_FOO
2801 bits, 0 means CC isn't left in a usable state). */
2805 const char *const assembler;
2809 /* Assembler instruction shift table.
2811 These tables are used to look up the basic shifts.
2812 They are indexed by cpu, shift_type, and mode. */
2814 static const struct shift_insn shift_one[2][3][3] =
2820 { "shll\t%X0", CC_SET_ZNV },
2821 { "add.w\t%T0,%T0", CC_SET_ZN },
2822 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2824 /* SHIFT_LSHIFTRT */
2826 { "shlr\t%X0", CC_SET_ZNV },
2827 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2828 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2830 /* SHIFT_ASHIFTRT */
2832 { "shar\t%X0", CC_SET_ZNV },
2833 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2834 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2841 { "shll.b\t%X0", CC_SET_ZNV },
2842 { "shll.w\t%T0", CC_SET_ZNV },
2843 { "shll.l\t%S0", CC_SET_ZNV }
2845 /* SHIFT_LSHIFTRT */
2847 { "shlr.b\t%X0", CC_SET_ZNV },
2848 { "shlr.w\t%T0", CC_SET_ZNV },
2849 { "shlr.l\t%S0", CC_SET_ZNV }
2851 /* SHIFT_ASHIFTRT */
2853 { "shar.b\t%X0", CC_SET_ZNV },
2854 { "shar.w\t%T0", CC_SET_ZNV },
2855 { "shar.l\t%S0", CC_SET_ZNV }
2860 static const struct shift_insn shift_two[3][3] =
2864 { "shll.b\t#2,%X0", CC_SET_ZNV },
2865 { "shll.w\t#2,%T0", CC_SET_ZNV },
2866 { "shll.l\t#2,%S0", CC_SET_ZNV }
2868 /* SHIFT_LSHIFTRT */
2870 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2871 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2872 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2874 /* SHIFT_ASHIFTRT */
2876 { "shar.b\t#2,%X0", CC_SET_ZNV },
2877 { "shar.w\t#2,%T0", CC_SET_ZNV },
2878 { "shar.l\t#2,%S0", CC_SET_ZNV }
2882 /* Rotates are organized by which shift they'll be used in implementing.
2883 There's no need to record whether the cc is valid afterwards because
2884 it is the AND insn that will decide this. */
2886 static const char *const rotate_one[2][3][3] =
2893 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2896 /* SHIFT_LSHIFTRT */
2899 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2902 /* SHIFT_ASHIFTRT */
2905 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2917 /* SHIFT_LSHIFTRT */
2923 /* SHIFT_ASHIFTRT */
2932 static const char *const rotate_two[3][3] =
2940 /* SHIFT_LSHIFTRT */
2946 /* SHIFT_ASHIFTRT */
2955 /* Shift algorithm. */
2958 /* The number of bits to be shifted by shift1 and shift2. Valid
2959 when ALG is SHIFT_SPECIAL. */
2960 unsigned int remainder;
2962 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2963 const char *special;
2965 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2966 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2969 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2970 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2973 /* CC status for SHIFT_INLINE. */
2976 /* CC status for SHIFT_SPECIAL. */
2980 static void get_shift_alg (enum shift_type,
2981 enum shift_mode, unsigned int,
2982 struct shift_info *);
2984 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2985 best algorithm for doing the shift. The assembler code is stored
2986 in the pointers in INFO. We achieve the maximum efficiency in most
2987 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2988 SImode in particular have a lot of room to optimize.
2990 We first determine the strategy of the shift algorithm by a table
2991 lookup. If that tells us to use a hand crafted assembly code, we
2992 go into the big switch statement to find what that is. Otherwise,
2993 we resort to a generic way, such as inlining. In either case, the
2994 result is returned through INFO. */
2997 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2998 unsigned int count, struct shift_info *info)
3002 /* Find the target CPU. */
3005 else if (TARGET_H8300H)
3010 /* Find the shift algorithm. */
3011 info->alg = SHIFT_LOOP;
3015 if (count < GET_MODE_BITSIZE (QImode))
3016 info->alg = shift_alg_qi[cpu][shift_type][count];
3020 if (count < GET_MODE_BITSIZE (HImode))
3021 info->alg = shift_alg_hi[cpu][shift_type][count];
3025 if (count < GET_MODE_BITSIZE (SImode))
3026 info->alg = shift_alg_si[cpu][shift_type][count];
3033 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
3037 info->remainder = count;
3041 /* It is up to the caller to know that looping clobbers cc. */
3042 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3043 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3044 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3048 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3049 info->shift2 = rotate_two[shift_type][shift_mode];
3050 info->cc_inline = CC_CLOBBER;
3054 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3055 info->remainder = 0;
3056 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3057 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3058 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3059 info->cc_special = CC_CLOBBER;
3063 /* Here we only deal with SHIFT_SPECIAL. */
3067 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3068 through the entire value. */
3069 if (shift_type == SHIFT_ASHIFTRT && count == 7)
3071 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3083 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3085 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3087 case SHIFT_LSHIFTRT:
3089 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3091 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3093 case SHIFT_ASHIFTRT:
3094 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3098 else if ((8 <= count && count <= 13)
3099 || (TARGET_H8300S && count == 14))
3101 info->remainder = count - 8;
3106 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3108 case SHIFT_LSHIFTRT:
3111 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3112 info->shift1 = "shlr.b\t%s0";
3113 info->cc_inline = CC_SET_ZNV;
3117 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3118 info->cc_special = CC_SET_ZNV;
3121 case SHIFT_ASHIFTRT:
3124 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3125 info->shift1 = "shar.b\t%s0";
3129 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3130 info->cc_special = CC_SET_ZNV;
3135 else if (count == 14)
3141 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3143 case SHIFT_LSHIFTRT:
3145 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3147 case SHIFT_ASHIFTRT:
3149 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3150 else if (TARGET_H8300H)
3152 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3153 info->cc_special = CC_SET_ZNV;
3155 else /* TARGET_H8300S */
3160 else if (count == 15)
3165 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3167 case SHIFT_LSHIFTRT:
3168 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3170 case SHIFT_ASHIFTRT:
3171 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3178 if (TARGET_H8300 && 8 <= count && count <= 9)
3180 info->remainder = count - 8;
3185 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3187 case SHIFT_LSHIFTRT:
3188 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3189 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3191 case SHIFT_ASHIFTRT:
3192 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3196 else if (count == 8 && !TARGET_H8300)
3201 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3203 case SHIFT_LSHIFTRT:
3204 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3206 case SHIFT_ASHIFTRT:
3207 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3211 else if (count == 15 && TARGET_H8300)
3217 case SHIFT_LSHIFTRT:
3218 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3220 case SHIFT_ASHIFTRT:
3221 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3225 else if (count == 15 && !TARGET_H8300)
3230 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3231 info->cc_special = CC_SET_ZNV;
3233 case SHIFT_LSHIFTRT:
3234 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3235 info->cc_special = CC_SET_ZNV;
3237 case SHIFT_ASHIFTRT:
3241 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3242 || (TARGET_H8300H && 16 <= count && count <= 19)
3243 || (TARGET_H8300S && 16 <= count && count <= 21))
3245 info->remainder = count - 16;
3250 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3252 info->shift1 = "add.w\t%e0,%e0";
3254 case SHIFT_LSHIFTRT:
3257 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3258 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3262 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3263 info->cc_special = CC_SET_ZNV;
3266 case SHIFT_ASHIFTRT:
3269 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3270 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3274 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3275 info->cc_special = CC_SET_ZNV;
3280 else if (TARGET_H8300 && 24 <= count && count <= 28)
3282 info->remainder = count - 24;
3287 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3288 info->shift1 = "shll.b\t%z0";
3289 info->cc_inline = CC_SET_ZNV;
3291 case SHIFT_LSHIFTRT:
3292 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3293 info->shift1 = "shlr.b\t%w0";
3294 info->cc_inline = CC_SET_ZNV;
3296 case SHIFT_ASHIFTRT:
3297 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3298 info->shift1 = "shar.b\t%w0";
3299 info->cc_inline = CC_SET_ZNV;
3303 else if ((TARGET_H8300H && count == 24)
3304 || (TARGET_H8300S && 24 <= count && count <= 25))
3306 info->remainder = count - 24;
3311 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3313 case SHIFT_LSHIFTRT:
3314 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3315 info->cc_special = CC_SET_ZNV;
3317 case SHIFT_ASHIFTRT:
3318 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3319 info->cc_special = CC_SET_ZNV;
3323 else if (!TARGET_H8300 && count == 28)
3329 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3331 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3333 case SHIFT_LSHIFTRT:
3336 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3337 info->cc_special = CC_SET_ZNV;
3340 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3342 case SHIFT_ASHIFTRT:
3346 else if (!TARGET_H8300 && count == 29)
3352 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3354 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3356 case SHIFT_LSHIFTRT:
3359 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3360 info->cc_special = CC_SET_ZNV;
3364 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3365 info->cc_special = CC_SET_ZNV;
3368 case SHIFT_ASHIFTRT:
3372 else if (!TARGET_H8300 && count == 30)
3378 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3380 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3382 case SHIFT_LSHIFTRT:
3384 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3386 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3388 case SHIFT_ASHIFTRT:
3392 else if (count == 31)
3399 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3401 case SHIFT_LSHIFTRT:
3402 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3404 case SHIFT_ASHIFTRT:
3405 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3414 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3415 info->cc_special = CC_SET_ZNV;
3417 case SHIFT_LSHIFTRT:
3418 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3419 info->cc_special = CC_SET_ZNV;
3421 case SHIFT_ASHIFTRT:
3422 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3423 info->cc_special = CC_SET_ZNV;
3436 info->shift2 = NULL;
3439 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3440 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3443 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3448 if (GET_MODE_BITSIZE (mode) <= count)
3451 /* Find out the target CPU. */
3454 else if (TARGET_H8300H)
3459 /* Find the shift algorithm. */
3463 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3464 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3465 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3469 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3470 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3471 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3475 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3476 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3477 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3484 /* On H8/300H, count == 8 uses a scratch register. */
3485 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3486 || (TARGET_H8300H && mode == SImode && count == 8));
3489 /* Output the assembler code for doing shifts. */
3492 output_a_shift (rtx *operands)
3494 static int loopend_lab;
3495 rtx shift = operands[3];
3496 enum machine_mode mode = GET_MODE (shift);
3497 enum rtx_code code = GET_CODE (shift);
3498 enum shift_type shift_type;
3499 enum shift_mode shift_mode;
3500 struct shift_info info;
3507 shift_mode = QIshift;
3510 shift_mode = HIshift;
3513 shift_mode = SIshift;
3522 shift_type = SHIFT_ASHIFTRT;
3525 shift_type = SHIFT_LSHIFTRT;
3528 shift_type = SHIFT_ASHIFT;
3534 if (GET_CODE (operands[2]) != CONST_INT)
3536 /* This case must be taken care of by one of the two splitters
3537 that convert a variable shift into a loop. */
3542 int n = INTVAL (operands[2]);
3544 /* If the count is negative, make it 0. */
3547 /* If the count is too big, truncate it.
3548 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3549 do the intuitive thing. */
3550 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3551 n = GET_MODE_BITSIZE (mode);
3553 get_shift_alg (shift_type, shift_mode, n, &info);
3558 output_asm_insn (info.special, operands);
3564 /* Emit two bit shifts first. */
3565 if (info.shift2 != NULL)
3567 for (; n > 1; n -= 2)
3568 output_asm_insn (info.shift2, operands);
3571 /* Now emit one bit shifts for any residual. */
3573 output_asm_insn (info.shift1, operands);
3578 int m = GET_MODE_BITSIZE (mode) - n;
3579 const int mask = (shift_type == SHIFT_ASHIFT
3580 ? ((1 << m) - 1) << n
3584 /* Not all possibilities of rotate are supported. They shouldn't
3585 be generated, but let's watch for 'em. */
3586 if (info.shift1 == 0)
3589 /* Emit two bit rotates first. */
3590 if (info.shift2 != NULL)
3592 for (; m > 1; m -= 2)
3593 output_asm_insn (info.shift2, operands);
3596 /* Now single bit rotates for any residual. */
3598 output_asm_insn (info.shift1, operands);
3600 /* Now mask off the high bits. */
3602 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3603 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3604 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3608 output_asm_insn (insn_buf, operands);
3613 /* A loop to shift by a "large" constant value.
3614 If we have shift-by-2 insns, use them. */
3615 if (info.shift2 != NULL)
3617 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3618 names_big[REGNO (operands[4])]);
3619 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3620 output_asm_insn (info.shift2, operands);
3621 output_asm_insn ("add #0xff,%X4", operands);
3622 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3624 output_asm_insn (info.shift1, operands);
3628 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3629 names_big[REGNO (operands[4])]);
3630 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3631 output_asm_insn (info.shift1, operands);
3632 output_asm_insn ("add #0xff,%X4", operands);
3633 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3643 /* Count the number of assembly instructions in a string TEMPLATE. */
3646 h8300_asm_insn_count (const char *template)
3648 unsigned int count = 1;
3650 for (; *template; template++)
3651 if (*template == '\n')
3657 /* Compute the length of a shift insn. */
3660 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3662 rtx shift = operands[3];
3663 enum machine_mode mode = GET_MODE (shift);
3664 enum rtx_code code = GET_CODE (shift);
3665 enum shift_type shift_type;
3666 enum shift_mode shift_mode;
3667 struct shift_info info;
3668 unsigned int wlength = 0;
3673 shift_mode = QIshift;
3676 shift_mode = HIshift;
3679 shift_mode = SIshift;
3688 shift_type = SHIFT_ASHIFTRT;
3691 shift_type = SHIFT_LSHIFTRT;
3694 shift_type = SHIFT_ASHIFT;
3700 if (GET_CODE (operands[2]) != CONST_INT)
3702 /* Get the assembler code to do one shift. */
3703 get_shift_alg (shift_type, shift_mode, 1, &info);
3705 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3709 int n = INTVAL (operands[2]);
3711 /* If the count is negative, make it 0. */
3714 /* If the count is too big, truncate it.
3715 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3716 do the intuitive thing. */
3717 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3718 n = GET_MODE_BITSIZE (mode);
3720 get_shift_alg (shift_type, shift_mode, n, &info);
3725 wlength += h8300_asm_insn_count (info.special);
3727 /* Every assembly instruction used in SHIFT_SPECIAL case
3728 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3729 see xor.l, we just pretend that xor.l counts as two insns
3730 so that the insn length will be computed correctly. */
3731 if (strstr (info.special, "xor.l") != NULL)
3739 if (info.shift2 != NULL)
3741 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3745 wlength += h8300_asm_insn_count (info.shift1) * n;
3751 int m = GET_MODE_BITSIZE (mode) - n;
3753 /* Not all possibilities of rotate are supported. They shouldn't
3754 be generated, but let's watch for 'em. */
3755 if (info.shift1 == 0)
3758 if (info.shift2 != NULL)
3760 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3764 wlength += h8300_asm_insn_count (info.shift1) * m;
3766 /* Now mask off the high bits. */
3787 /* A loop to shift by a "large" constant value.
3788 If we have shift-by-2 insns, use them. */
3789 if (info.shift2 != NULL)
3791 wlength += 3 + h8300_asm_insn_count (info.shift2);
3793 wlength += h8300_asm_insn_count (info.shift1);
3797 wlength += 3 + h8300_asm_insn_count (info.shift1);
3807 /* Compute which flag bits are valid after a shift insn. */
3810 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3812 rtx shift = operands[3];
3813 enum machine_mode mode = GET_MODE (shift);
3814 enum rtx_code code = GET_CODE (shift);
3815 enum shift_type shift_type;
3816 enum shift_mode shift_mode;
3817 struct shift_info info;
3822 shift_mode = QIshift;
3825 shift_mode = HIshift;
3828 shift_mode = SIshift;
3837 shift_type = SHIFT_ASHIFTRT;
3840 shift_type = SHIFT_LSHIFTRT;
3843 shift_type = SHIFT_ASHIFT;
3849 if (GET_CODE (operands[2]) != CONST_INT)
3851 /* This case must be taken care of by one of the two splitters
3852 that convert a variable shift into a loop. */
3857 int n = INTVAL (operands[2]);
3859 /* If the count is negative, make it 0. */
3862 /* If the count is too big, truncate it.
3863 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3864 do the intuitive thing. */
3865 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3866 n = GET_MODE_BITSIZE (mode);
3868 get_shift_alg (shift_type, shift_mode, n, &info);
3873 if (info.remainder == 0)
3874 return info.cc_special;
3879 return info.cc_inline;
3882 /* This case always ends with an and instruction. */
3886 /* A loop to shift by a "large" constant value.
3887 If we have shift-by-2 insns, use them. */
3888 if (info.shift2 != NULL)
3891 return info.cc_inline;
3901 /* A rotation by a non-constant will cause a loop to be generated, in
3902 which a rotation by one bit is used. A rotation by a constant,
3903 including the one in the loop, will be taken care of by
3904 output_a_rotate () at the insn emit time. */
3907 expand_a_rotate (rtx operands[])
3909 rtx dst = operands[0];
3910 rtx src = operands[1];
3911 rtx rotate_amount = operands[2];
3912 enum machine_mode mode = GET_MODE (dst);
3914 /* We rotate in place. */
3915 emit_move_insn (dst, src);
3917 if (GET_CODE (rotate_amount) != CONST_INT)
3919 rtx counter = gen_reg_rtx (QImode);
3920 rtx start_label = gen_label_rtx ();
3921 rtx end_label = gen_label_rtx ();
3923 /* If the rotate amount is less than or equal to 0,
3924 we go out of the loop. */
3925 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
3926 QImode, 0, end_label);
3928 /* Initialize the loop counter. */
3929 emit_move_insn (counter, rotate_amount);
3931 emit_label (start_label);
3933 /* Rotate by one bit. */
3937 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
3940 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
3943 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
3949 /* Decrement the counter by 1. */
3950 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
3952 /* If the loop counter is nonzero, we go back to the beginning
3954 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
3957 emit_label (end_label);
3961 /* Rotate by AMOUNT bits. */
3965 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
3968 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
3971 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
3981 /* Output a rotate insn. */
3984 output_a_rotate (enum rtx_code code, rtx *operands)
3986 rtx dst = operands[0];
3987 rtx rotate_amount = operands[2];
3988 enum shift_mode rotate_mode;
3989 enum shift_type rotate_type;
3990 const char *insn_buf;
3993 enum machine_mode mode = GET_MODE (dst);
3995 if (GET_CODE (rotate_amount) != CONST_INT)
4001 rotate_mode = QIshift;
4004 rotate_mode = HIshift;
4007 rotate_mode = SIshift;
4016 rotate_type = SHIFT_ASHIFT;
4019 rotate_type = SHIFT_LSHIFTRT;
4025 amount = INTVAL (rotate_amount);
4027 /* Clean up AMOUNT. */
4030 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4031 amount = GET_MODE_BITSIZE (mode);
4033 /* Determine the faster direction. After this phase, amount will be
4034 at most a half of GET_MODE_BITSIZE (mode). */
4035 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4037 /* Flip the direction. */
4038 amount = GET_MODE_BITSIZE (mode) - amount;
4040 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4043 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4044 boost up the rotation. */
4045 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4046 || (mode == HImode && TARGET_H8300H && amount >= 6)
4047 || (mode == HImode && TARGET_H8300S && amount == 8)
4048 || (mode == SImode && TARGET_H8300H && amount >= 10)
4049 || (mode == SImode && TARGET_H8300S && amount >= 13))
4054 /* This code works on any family. */
4055 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
4056 output_asm_insn (insn_buf, operands);
4060 /* This code works on the H8/300H and H8S. */
4061 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
4062 output_asm_insn (insn_buf, operands);
4069 /* Adjust AMOUNT and flip the direction. */
4070 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4072 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4075 /* Output rotate insns. */
4076 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4079 insn_buf = rotate_two[rotate_type][rotate_mode];
4081 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
4083 for (; amount >= bits; amount -= bits)
4084 output_asm_insn (insn_buf, operands);
4090 /* Compute the length of a rotate insn. */
4093 compute_a_rotate_length (rtx *operands)
4095 rtx src = operands[1];
4096 rtx amount_rtx = operands[2];
4097 enum machine_mode mode = GET_MODE (src);
4099 unsigned int length = 0;
4101 if (GET_CODE (amount_rtx) != CONST_INT)
4104 amount = INTVAL (amount_rtx);
4106 /* Clean up AMOUNT. */
4109 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4110 amount = GET_MODE_BITSIZE (mode);
4112 /* Determine the faster direction. After this phase, amount
4113 will be at most a half of GET_MODE_BITSIZE (mode). */
4114 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4115 /* Flip the direction. */
4116 amount = GET_MODE_BITSIZE (mode) - amount;
4118 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4119 boost up the rotation. */
4120 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4121 || (mode == HImode && TARGET_H8300H && amount >= 6)
4122 || (mode == HImode && TARGET_H8300S && amount == 8)
4123 || (mode == SImode && TARGET_H8300H && amount >= 10)
4124 || (mode == SImode && TARGET_H8300S && amount >= 13))
4126 /* Adjust AMOUNT and flip the direction. */
4127 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4131 /* We use 2-bit rotations on the H8S. */
4133 amount = amount / 2 + amount % 2;
4135 /* The H8/300 uses three insns to rotate one bit, taking 6
4137 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4142 /* Fix the operands of a gen_xxx so that it could become a bit
4146 fix_bit_operand (rtx *operands, enum rtx_code code)
4148 /* The bit_operand predicate accepts any memory during RTL generation, but
4149 only 'U' memory afterwards, so if this is a MEM operand, we must force
4150 it to be valid for 'U' by reloading the address. */
4153 ? single_zero_operand (operands[2], QImode)
4154 : single_one_operand (operands[2], QImode))
4156 /* OK to have a memory dest. */
4157 if (GET_CODE (operands[0]) == MEM
4158 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4160 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4161 copy_to_mode_reg (Pmode,
4162 XEXP (operands[0], 0)));
4163 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4167 if (GET_CODE (operands[1]) == MEM
4168 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4170 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4171 copy_to_mode_reg (Pmode,
4172 XEXP (operands[1], 0)));
4173 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4179 /* Dest and src op must be register. */
4181 operands[1] = force_reg (QImode, operands[1]);
4183 rtx res = gen_reg_rtx (QImode);
4187 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
4190 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
4193 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
4198 emit_insn (gen_movqi (operands[0], res));
4203 /* Return nonzero if FUNC is an interrupt function as specified
4204 by the "interrupt" attribute. */
4207 h8300_interrupt_function_p (tree func)
4211 if (TREE_CODE (func) != FUNCTION_DECL)
4214 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4215 return a != NULL_TREE;
4218 /* Return nonzero if FUNC is a saveall function as specified by the
4219 "saveall" attribute. */
4222 h8300_saveall_function_p (tree func)
4226 if (TREE_CODE (func) != FUNCTION_DECL)
4229 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4230 return a != NULL_TREE;
4233 /* Return nonzero if FUNC is an OS_Task function as specified
4234 by the "OS_Task" attribute. */
4237 h8300_os_task_function_p (tree func)
4241 if (TREE_CODE (func) != FUNCTION_DECL)
4244 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4245 return a != NULL_TREE;
4248 /* Return nonzero if FUNC is a monitor function as specified
4249 by the "monitor" attribute. */
4252 h8300_monitor_function_p (tree func)
4256 if (TREE_CODE (func) != FUNCTION_DECL)
4259 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4260 return a != NULL_TREE;
4263 /* Return nonzero if FUNC is a function that should be called
4264 through the function vector. */
4267 h8300_funcvec_function_p (tree func)
4271 if (TREE_CODE (func) != FUNCTION_DECL)
4274 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4275 return a != NULL_TREE;
4278 /* Return nonzero if DECL is a variable that's in the eight bit
4282 h8300_eightbit_data_p (tree decl)
4286 if (TREE_CODE (decl) != VAR_DECL)
4289 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4290 return a != NULL_TREE;
4293 /* Return nonzero if DECL is a variable that's in the tiny
4297 h8300_tiny_data_p (tree decl)
4301 if (TREE_CODE (decl) != VAR_DECL)
4304 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4305 return a != NULL_TREE;
4308 /* Generate an 'interrupt_handler' attribute for decls. We convert
4309 all the pragmas to corresponding attributes. */
4312 h8300_insert_attributes (tree node, tree *attributes)
4314 if (TREE_CODE (node) == FUNCTION_DECL)
4316 if (pragma_interrupt)
4318 pragma_interrupt = 0;
4320 /* Add an 'interrupt_handler' attribute. */
4321 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4329 /* Add an 'saveall' attribute. */
4330 *attributes = tree_cons (get_identifier ("saveall"),
4336 /* Supported attributes:
4338 interrupt_handler: output a prologue and epilogue suitable for an
4341 saveall: output a prologue and epilogue that saves and restores
4342 all registers except the stack pointer.
4344 function_vector: This function should be called through the
4347 eightbit_data: This variable lives in the 8-bit data area and can
4348 be referenced with 8-bit absolute memory addresses.
4350 tiny_data: This variable lives in the tiny data area and can be
4351 referenced with 16-bit absolute memory references. */
4353 const struct attribute_spec h8300_attribute_table[] =
4355 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4356 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4357 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4358 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4359 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4360 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4361 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4362 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4363 { NULL, 0, 0, false, false, false, NULL }
4367 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4368 struct attribute_spec.handler. */
4370 h8300_handle_fndecl_attribute (tree *node, tree name,
4371 tree args ATTRIBUTE_UNUSED,
4372 int flags ATTRIBUTE_UNUSED,
4375 if (TREE_CODE (*node) != FUNCTION_DECL)
4377 warning ("`%s' attribute only applies to functions",
4378 IDENTIFIER_POINTER (name));
4379 *no_add_attrs = true;
4385 /* Handle an "eightbit_data" attribute; arguments as in
4386 struct attribute_spec.handler. */
4388 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4389 tree args ATTRIBUTE_UNUSED,
4390 int flags ATTRIBUTE_UNUSED,
4395 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4397 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4401 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4402 *no_add_attrs = true;
4408 /* Handle an "tiny_data" attribute; arguments as in
4409 struct attribute_spec.handler. */
4411 h8300_handle_tiny_data_attribute (tree *node, tree name,
4412 tree args ATTRIBUTE_UNUSED,
4413 int flags ATTRIBUTE_UNUSED,
4418 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4420 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4424 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4425 *no_add_attrs = true;
4431 /* Mark function vectors, and various small data objects. */
4434 h8300_encode_section_info (tree decl, rtx rtl, int first)
4436 int extra_flags = 0;
4438 default_encode_section_info (decl, rtl, first);
4440 if (TREE_CODE (decl) == FUNCTION_DECL
4441 && h8300_funcvec_function_p (decl))
4442 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4443 else if (TREE_CODE (decl) == VAR_DECL
4444 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4446 if (h8300_eightbit_data_p (decl))
4447 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4448 else if (first && h8300_tiny_data_p (decl))
4449 extra_flags = SYMBOL_FLAG_TINY_DATA;
4453 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4456 /* Output a single-bit extraction. */
4459 output_simode_bld (int bild, rtx operands[])
4463 /* Clear the destination register. */
4464 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4466 /* Now output the bit load or bit inverse load, and store it in
4469 output_asm_insn ("bild\t%Z2,%Y1", operands);
4471 output_asm_insn ("bld\t%Z2,%Y1", operands);
4473 output_asm_insn ("bst\t#0,%w0", operands);
4477 /* Determine if we can clear the destination first. */
4478 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4479 && REGNO (operands[0]) != REGNO (operands[1]));
4482 output_asm_insn ("sub.l\t%S0,%S0", operands);
4484 /* Output the bit load or bit inverse load. */
4486 output_asm_insn ("bild\t%Z2,%Y1", operands);
4488 output_asm_insn ("bld\t%Z2,%Y1", operands);
4491 output_asm_insn ("xor.l\t%S0,%S0", operands);
4493 /* Perform the bit store. */
4494 output_asm_insn ("rotxl.l\t%S0", operands);
4501 #ifndef OBJECT_FORMAT_ELF
4503 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4505 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4506 fprintf (asm_out_file, "\t.section %s\n", name);
4508 #endif /* ! OBJECT_FORMAT_ELF */
4510 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4511 which is a special case of the 'R' operand. */
4514 h8300_eightbit_constant_address_p (rtx x)
4516 /* The ranges of the 8-bit area. */
4517 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4518 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4519 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4520 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4521 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4522 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4524 unsigned HOST_WIDE_INT addr;
4526 /* We accept symbols declared with eightbit_data. */
4527 if (GET_CODE (x) == SYMBOL_REF)
4528 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4530 if (GET_CODE (x) != CONST_INT)
4536 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4537 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4538 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4541 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4542 on H8/300H and H8S. */
4545 h8300_tiny_constant_address_p (rtx x)
4547 /* The ranges of the 16-bit area. */
4548 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4549 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4550 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4551 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4552 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4553 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4554 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4555 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4557 unsigned HOST_WIDE_INT addr;
4559 switch (GET_CODE (x))
4562 /* In the normal mode, any symbol fits in the 16-bit absolute
4563 address range. We also accept symbols declared with
4565 return (TARGET_NORMAL_MODE
4566 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
4570 return (TARGET_NORMAL_MODE
4572 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4574 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4577 return TARGET_NORMAL_MODE;
4585 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
4586 locations that can be accessed as a 16-bit word. */
4589 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4591 HOST_WIDE_INT offset1, offset2;
4599 else if (GET_CODE (addr1) == PLUS
4600 && REG_P (XEXP (addr1, 0))
4601 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4603 reg1 = XEXP (addr1, 0);
4604 offset1 = INTVAL (XEXP (addr1, 1));
4614 else if (GET_CODE (addr2) == PLUS
4615 && REG_P (XEXP (addr2, 0))
4616 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4618 reg2 = XEXP (addr2, 0);
4619 offset2 = INTVAL (XEXP (addr2, 1));
4624 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4625 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4627 && offset1 + 1 == offset2)
4633 /* Return nonzero if we have the same comparison insn as I3 two insns
4634 before I3. I3 is assumed to be a comparison insn. */
4637 same_cmp_preceding_p (rtx i3)
4641 /* Make sure we have a sequence of three insns. */
4642 i2 = prev_nonnote_insn (i3);
4645 i1 = prev_nonnote_insn (i2);
4649 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4650 && any_condjump_p (i2) && onlyjump_p (i2));
4653 /* Return nonzero if we have the same comparison insn as I1 two insns
4654 after I1. I1 is assumed to be a comparison insn. */
4657 same_cmp_following_p (rtx i1)
4661 /* Make sure we have a sequence of three insns. */
4662 i2 = next_nonnote_insn (i1);
4665 i3 = next_nonnote_insn (i2);
4669 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4670 && any_condjump_p (i2) && onlyjump_p (i2));
4673 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
4674 (or pops) N registers. OPERANDS are assumed to be an array of
4678 h8300_regs_ok_for_stm (int n, rtx operands[])
4683 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4684 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4685 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
4687 return ((REGNO (operands[0]) == 0
4688 && REGNO (operands[1]) == 1
4689 && REGNO (operands[2]) == 2)
4690 || (REGNO (operands[0]) == 4
4691 && REGNO (operands[1]) == 5
4692 && REGNO (operands[2]) == 6));
4695 return (REGNO (operands[0]) == 0
4696 && REGNO (operands[1]) == 1
4697 && REGNO (operands[2]) == 2
4698 && REGNO (operands[3]) == 3);
4704 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4707 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4708 unsigned int new_reg)
4710 /* Interrupt functions can only use registers that have already been
4711 saved by the prologue, even if they would normally be
4714 if (h8300_current_function_interrupt_function_p ()
4715 && !regs_ever_live[new_reg])
4721 /* Return nonzero if X is a legitimate constant. */
4724 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
4729 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
4732 h8300_rtx_ok_for_base_p (rtx x, int strict)
4734 /* Strip off SUBREG if any. */
4735 if (GET_CODE (x) == SUBREG)
4740 ? REG_OK_FOR_BASE_STRICT_P (x)
4741 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
4744 /* Return nozero if X is a legitimate address. On the H8/300, a
4745 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
4746 CONSTANT_ADDRESS. */
4749 h8300_legitimate_address_p (rtx x, int strict)
4751 /* The register indirect addresses like @er0 is always valid. */
4752 if (h8300_rtx_ok_for_base_p (x, strict))
4755 if (CONSTANT_ADDRESS_P (x))
4758 if (GET_CODE (x) == PLUS
4759 && CONSTANT_ADDRESS_P (XEXP (x, 1))
4760 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
4766 /* Worker function for HARD_REGNO_NREGS.
4768 We pretend the MAC register is 32bits -- we don't have any data
4769 types on the H8 series to handle more than 32bits. */
4772 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
4774 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4777 /* Worker function for HARD_REGNO_MODE_OK. */
4780 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
4783 /* If an even reg, then anything goes. Otherwise the mode must be
4785 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
4787 /* MAC register can only be of SImode. Otherwise, anything
4789 return regno == MAC_REG ? mode == SImode : 1;
4792 /* Perform target dependent optabs initialization. */
4794 h8300_init_libfuncs (void)
4796 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4797 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4798 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4799 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4800 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4803 /* Worker function for TARGET_RETURN_IN_MEMORY. */
4806 h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4808 return (TYPE_MODE (type) == BLKmode
4809 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
4812 /* Initialize the GCC target structure. */
4813 #undef TARGET_ATTRIBUTE_TABLE
4814 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4816 #undef TARGET_ASM_ALIGNED_HI_OP
4817 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4819 #undef TARGET_ASM_FILE_START
4820 #define TARGET_ASM_FILE_START h8300_file_start
4821 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4822 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4824 #undef TARGET_ASM_FILE_END
4825 #define TARGET_ASM_FILE_END h8300_file_end
4827 #undef TARGET_ENCODE_SECTION_INFO
4828 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4830 #undef TARGET_INSERT_ATTRIBUTES
4831 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4833 #undef TARGET_RTX_COSTS
4834 #define TARGET_RTX_COSTS h8300_rtx_costs
4836 #undef TARGET_INIT_LIBFUNCS
4837 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4839 #undef TARGET_RETURN_IN_MEMORY
4840 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
4842 struct gcc_target targetm = TARGET_INITIALIZER;