1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Forward declarations. */
50 static const char *byte_reg (rtx, int);
51 static int h8300_interrupt_function_p (tree);
52 static int h8300_saveall_function_p (tree);
53 static int h8300_monitor_function_p (tree);
54 static int h8300_os_task_function_p (tree);
55 static void h8300_emit_stack_adjustment (int, unsigned int);
56 static int round_frame_size (int);
57 static unsigned int compute_saved_regs (void);
58 static void push (int);
59 static void pop (int);
60 static const char *cond_string (enum rtx_code);
61 static unsigned int h8300_asm_insn_count (const char *);
62 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
63 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
64 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
65 #ifndef OBJECT_FORMAT_ELF
66 static void h8300_asm_named_section (const char *, unsigned int);
68 static int h8300_and_costs (rtx);
69 static int h8300_shift_costs (rtx);
71 /* CPU_TYPE, says what cpu we're compiling for. */
74 /* True if a #pragma interrupt has been seen for the current function. */
75 static int pragma_interrupt;
77 /* True if a #pragma saveall has been seen for the current function. */
78 static int pragma_saveall;
80 static const char *const names_big[] =
81 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
83 static const char *const names_extended[] =
84 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
86 static const char *const names_upper_extended[] =
87 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
89 /* Points to one of the above. */
90 /* ??? The above could be put in an array indexed by CPU_TYPE. */
91 const char * const *h8_reg_names;
93 /* Various operations needed by the following, indexed by CPU_TYPE. */
95 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
97 /* Machine-specific symbol_ref flags. */
98 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
99 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
100 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
102 /* See below where shifts are handled for explanation of this enum. */
112 /* Symbols of the various shifts which can be used as indices. */
116 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
119 /* Macros to keep the shift algorithm tables small. */
120 #define INL SHIFT_INLINE
121 #define ROT SHIFT_ROT_AND
122 #define LOP SHIFT_LOOP
123 #define SPC SHIFT_SPECIAL
125 /* The shift algorithms for each machine, mode, shift type, and shift
126 count are defined below. The three tables below correspond to
127 QImode, HImode, and SImode, respectively. Each table is organized
128 by, in the order of indices, machine, shift type, and shift count. */
130 static enum shift_alg shift_alg_qi[3][3][8] = {
133 /* 0 1 2 3 4 5 6 7 */
134 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
135 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
136 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
140 /* 0 1 2 3 4 5 6 7 */
141 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
142 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
143 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
147 /* 0 1 2 3 4 5 6 7 */
148 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
149 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
150 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
154 static enum shift_alg shift_alg_hi[3][3][16] = {
157 /* 0 1 2 3 4 5 6 7 */
158 /* 8 9 10 11 12 13 14 15 */
159 { INL, INL, INL, INL, INL, INL, INL, SPC,
160 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
161 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
162 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
163 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
164 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
168 /* 0 1 2 3 4 5 6 7 */
169 /* 8 9 10 11 12 13 14 15 */
170 { INL, INL, INL, INL, INL, INL, INL, SPC,
171 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, INL, SPC,
173 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC,
175 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
179 /* 0 1 2 3 4 5 6 7 */
180 /* 8 9 10 11 12 13 14 15 */
181 { INL, INL, INL, INL, INL, INL, INL, INL,
182 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
183 { INL, INL, INL, INL, INL, INL, INL, INL,
184 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
185 { INL, INL, INL, INL, INL, INL, INL, INL,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
190 static enum shift_alg shift_alg_si[3][3][32] = {
193 /* 0 1 2 3 4 5 6 7 */
194 /* 8 9 10 11 12 13 14 15 */
195 /* 16 17 18 19 20 21 22 23 */
196 /* 24 25 26 27 28 29 30 31 */
197 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
198 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
200 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
201 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
202 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
203 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
204 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
205 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
206 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
207 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
208 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
212 /* 0 1 2 3 4 5 6 7 */
213 /* 8 9 10 11 12 13 14 15 */
214 /* 16 17 18 19 20 21 22 23 */
215 /* 24 25 26 27 28 29 30 31 */
216 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
217 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
218 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
219 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
220 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
222 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
223 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
225 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
227 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 /* 16 17 18 19 20 21 22 23 */
234 /* 24 25 26 27 28 29 30 31 */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
237 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
238 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
239 { INL, INL, INL, INL, INL, INL, INL, INL,
240 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
242 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
243 { INL, INL, INL, INL, INL, INL, INL, INL,
244 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
245 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
246 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
262 /* Initialize various cpu specific globals at start up. */
265 h8300_init_once (void)
267 static const char *const h8_push_ops[2] = { "push" , "push.l" };
268 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
269 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
273 cpu_type = (int) CPU_H8300;
274 h8_reg_names = names_big;
278 /* For this we treat the H8/300H and H8S the same. */
279 cpu_type = (int) CPU_H8300H;
280 h8_reg_names = names_extended;
282 h8_push_op = h8_push_ops[cpu_type];
283 h8_pop_op = h8_pop_ops[cpu_type];
284 h8_mov_op = h8_mov_ops[cpu_type];
286 if (!TARGET_H8300S && TARGET_MAC)
288 error ("-ms2600 is used without -ms");
289 target_flags |= MASK_H8300S;
292 if (TARGET_H8300 && TARGET_NORMAL_MODE)
294 error ("-mn is used without -mh or -ms");
295 target_flags ^= MASK_NORMAL_MODE;
298 /* Some of the shifts are optimized for speed by default.
299 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
300 If optimizing for size, change shift_alg for those shift to
305 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
306 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
307 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
308 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
310 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
311 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
313 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
314 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
317 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
318 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
320 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
321 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
323 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
324 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
325 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
326 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
329 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
334 byte_reg (rtx x, int b)
336 static const char *const names_small[] = {
337 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
338 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
344 return names_small[REGNO (x) * 2 + b];
347 /* REGNO must be saved/restored across calls if this macro is true. */
349 #define WORD_REG_USED(regno) \
351 /* No need to save registers if this function will not return. */ \
352 && ! TREE_THIS_VOLATILE (current_function_decl) \
353 && (h8300_saveall_function_p (current_function_decl) \
354 /* Save any call saved register that was used. */ \
355 || (regs_ever_live[regno] && !call_used_regs[regno]) \
356 /* Save the frame pointer if it was used. */ \
357 || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
358 /* Save any register used in an interrupt handler. */ \
359 || (h8300_current_function_interrupt_function_p () \
360 && regs_ever_live[regno]) \
361 /* Save call clobbered registers in non-leaf interrupt \
363 || (h8300_current_function_interrupt_function_p () \
364 && call_used_regs[regno] \
365 && !current_function_is_leaf)))
367 /* Output assembly language to FILE for the operation OP with operand size
368 SIZE to adjust the stack pointer. */
371 h8300_emit_stack_adjustment (int sign, unsigned int size)
373 /* H8/300 cannot add/subtract a large constant with a single
374 instruction. If a temporary register is available, load the
375 constant to it and then do the addition. */
378 && !h8300_current_function_interrupt_function_p ()
379 && !(current_function_needs_context && sign < 0))
382 rtx r3 = gen_rtx_REG (Pmode, 3);
383 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
384 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
385 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
389 /* The stack adjustment made here is further optimized by the
390 splitter. In case of H8/300, the splitter always splits the
391 addition emitted here to make the adjustment
393 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
394 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
398 /* Round up frame size SIZE. */
401 round_frame_size (int size)
403 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
404 & -STACK_BOUNDARY / BITS_PER_UNIT);
407 /* Compute which registers to push/pop.
408 Return a bit vector of registers. */
411 compute_saved_regs (void)
413 unsigned int saved_regs = 0;
416 /* Construct a bit vector of registers to be pushed/popped. */
417 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
419 if (WORD_REG_USED (regno))
420 saved_regs |= 1 << regno;
423 /* Don't push/pop the frame pointer as it is treated separately. */
424 if (frame_pointer_needed)
425 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
430 /* Emit an insn to push register RN. */
435 rtx reg = gen_rtx_REG (word_mode, rn);
439 x = gen_push_h8300 (reg);
440 else if (!TARGET_NORMAL_MODE)
441 x = gen_push_h8300hs_advanced (reg);
443 x = gen_push_h8300hs_normal (reg);
445 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
448 /* Emit an insn to pop register RN. */
453 rtx reg = gen_rtx_REG (word_mode, rn);
457 x = gen_pop_h8300 (reg);
458 else if (!TARGET_NORMAL_MODE)
459 x = gen_pop_h8300hs_advanced (reg);
461 x = gen_pop_h8300hs_normal (reg);
463 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
466 /* This is what the stack looks like after the prolog of
467 a function with a frame has been set up:
473 <saved registers> <- sp
475 This is what the stack looks like after the prolog of
476 a function which doesn't have a frame:
481 <saved registers> <- sp
484 /* Generate RTL code for the function prologue. */
487 h8300_expand_prologue (void)
493 /* If the current function has the OS_Task attribute set, then
494 we have a naked prologue. */
495 if (h8300_os_task_function_p (current_function_decl))
498 if (h8300_monitor_function_p (current_function_decl))
499 /* My understanding of monitor functions is they act just like
500 interrupt functions, except the prologue must mask
502 emit_insn (gen_monitor_prologue ());
504 if (frame_pointer_needed)
507 push (HARD_FRAME_POINTER_REGNUM);
508 emit_insn (gen_rtx_SET (Pmode, hard_frame_pointer_rtx,
512 /* Push the rest of the registers in ascending order. */
513 saved_regs = compute_saved_regs ();
514 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
517 if (saved_regs & (1 << regno))
521 /* See how many registers we can push at the same time. */
522 if ((regno == 0 || regno == 4)
523 && ((saved_regs >> regno) & 0x0f) == 0x0f)
526 else if ((regno == 0 || regno == 4)
527 && ((saved_regs >> regno) & 0x07) == 0x07)
530 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
531 && ((saved_regs >> regno) & 0x03) == 0x03)
541 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
542 gen_rtx_REG (SImode, regno + 1)));
545 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
546 gen_rtx_REG (SImode, regno + 1),
547 gen_rtx_REG (SImode, regno + 2)));
550 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
551 gen_rtx_REG (SImode, regno + 1),
552 gen_rtx_REG (SImode, regno + 2),
553 gen_rtx_REG (SImode, regno + 3)));
561 /* Leave room for locals. */
562 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
566 h8300_can_use_return_insn_p (void)
568 return (reload_completed
569 && !frame_pointer_needed
570 && get_frame_size () == 0
571 && compute_saved_regs () == 0);
574 /* Generate RTL code for the function epilogue. */
577 h8300_expand_epilogue (void)
583 if (h8300_os_task_function_p (current_function_decl))
584 /* OS_Task epilogues are nearly naked -- they just have an
588 /* Deallocate locals. */
589 h8300_emit_stack_adjustment (1, round_frame_size (get_frame_size ()));
591 /* Pop the saved registers in descending order. */
592 saved_regs = compute_saved_regs ();
593 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
596 if (saved_regs & (1 << regno))
600 /* See how many registers we can pop at the same time. */
601 if ((regno == 7 || regno == 3)
602 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
605 else if ((regno == 6 || regno == 2)
606 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
609 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
610 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
620 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
621 gen_rtx_REG (SImode, regno)));
624 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
625 gen_rtx_REG (SImode, regno - 1),
626 gen_rtx_REG (SImode, regno)));
629 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
630 gen_rtx_REG (SImode, regno - 2),
631 gen_rtx_REG (SImode, regno - 1),
632 gen_rtx_REG (SImode, regno)));
640 /* Pop frame pointer if we had one. */
641 if (frame_pointer_needed)
642 pop (HARD_FRAME_POINTER_REGNUM);
645 /* Return nonzero if the current function is an interrupt
649 h8300_current_function_interrupt_function_p (void)
651 return (h8300_interrupt_function_p (current_function_decl)
652 || h8300_monitor_function_p (current_function_decl));
655 /* Output assembly code for the start of the file. */
658 h8300_file_start (void)
660 default_file_start ();
663 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
664 else if (TARGET_H8300S)
665 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
668 /* Output assembly language code for the end of file. */
671 h8300_file_end (void)
673 fputs ("\t.end\n", asm_out_file);
676 /* Return true if OP is a valid source operand for an integer move
680 general_operand_src (rtx op, enum machine_mode mode)
682 if (GET_MODE (op) == mode
683 && GET_CODE (op) == MEM
684 && GET_CODE (XEXP (op, 0)) == POST_INC)
686 return general_operand (op, mode);
689 /* Return true if OP is a valid destination operand for an integer move
693 general_operand_dst (rtx op, enum machine_mode mode)
695 if (GET_MODE (op) == mode
696 && GET_CODE (op) == MEM
697 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
699 return general_operand (op, mode);
702 /* Return true if OP is a constant that contains only one 1 in its
703 binary representation. */
706 single_one_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
708 if (GET_CODE (operand) == CONST_INT)
710 /* We really need to do this masking because 0x80 in QImode is
711 represented as -128 for example. */
712 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
719 /* Return true if OP is a constant that contains only one 0 in its
720 binary representation. */
723 single_zero_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
725 if (GET_CODE (operand) == CONST_INT)
727 /* We really need to do this masking because 0x80 in QImode is
728 represented as -128 for example. */
729 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
736 /* Return true if OP is a valid call operand. */
739 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
741 if (GET_CODE (op) == MEM)
743 rtx inside = XEXP (op, 0);
744 if (register_operand (inside, Pmode))
746 if (CONSTANT_ADDRESS_P (inside))
752 /* Return 1 if an addition/subtraction of a constant integer can be
753 transformed into two consecutive adds/subs that are faster than the
754 straightforward way. Otherwise, return 0. */
757 two_insn_adds_subs_operand (rtx op, enum machine_mode mode)
759 if (GET_CODE (op) == CONST_INT)
761 HOST_WIDE_INT value = INTVAL (op);
763 /* Force VALUE to be positive so that we do not have to consider
764 the negative case. */
767 if (TARGET_H8300H || TARGET_H8300S)
769 /* A constant addition/subtraction takes 2 states in QImode,
770 4 states in HImode, and 6 states in SImode. Thus, the
771 only case we can win is when SImode is used, in which
772 case, two adds/subs are used, taking 4 states. */
782 /* We do not profit directly by splitting addition or
783 subtraction of 3 and 4. However, since these are
784 implemented as a sequence of adds or subs, they do not
785 clobber (cc0) unlike a sequence of add.b and add.x. */
796 /* Split an add of a small constant into two adds/subs insns.
798 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
799 instead of adds/subs. */
802 split_adds_subs (enum machine_mode mode, rtx *operands)
804 HOST_WIDE_INT val = INTVAL (operands[1]);
805 rtx reg = operands[0];
806 HOST_WIDE_INT sign = 1;
807 HOST_WIDE_INT amount;
808 rtx (*gen_add) (rtx, rtx, rtx);
810 /* Force VAL to be positive so that we do not have to consider the
821 gen_add = gen_addhi3;
825 gen_add = gen_addsi3;
832 /* Try different amounts in descending order. */
833 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
837 for (; val >= amount; val -= amount)
838 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
844 /* Return true if OP is a valid call operand, and OP represents
845 an operand for a small call (4 bytes instead of 6 bytes). */
848 small_call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
850 if (GET_CODE (op) == MEM)
852 rtx inside = XEXP (op, 0);
854 /* Register indirect is a small call. */
855 if (register_operand (inside, Pmode))
858 /* A call through the function vector is a small call too. */
859 if (GET_CODE (inside) == SYMBOL_REF
860 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
863 /* Otherwise it's a large call. */
867 /* Return true if OP is a valid jump operand. */
870 jump_address_operand (rtx op, enum machine_mode mode)
872 if (GET_CODE (op) == REG)
873 return mode == Pmode;
875 if (GET_CODE (op) == MEM)
877 rtx inside = XEXP (op, 0);
878 if (register_operand (inside, Pmode))
880 if (CONSTANT_ADDRESS_P (inside))
886 /* Recognize valid operands for bit-field instructions. */
888 extern int rtx_equal_function_value_matters;
891 bit_operand (rtx op, enum machine_mode mode)
893 /* We can accept any general operand, except that MEM operands must
894 be limited to those that use addresses valid for the 'U' constraint. */
895 if (!general_operand (op, mode))
898 /* Accept any mem during RTL generation. Otherwise, the code that does
899 insv and extzv will think that we can not handle memory. However,
900 to avoid reload problems, we only accept 'U' MEM operands after RTL
901 generation. This means that any named pattern which uses this predicate
902 must force its operands to match 'U' before emitting RTL. */
904 if (GET_CODE (op) == REG)
906 if (GET_CODE (op) == SUBREG)
908 return (GET_CODE (op) == MEM
909 && EXTRA_CONSTRAINT (op, 'U'));
913 bit_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
915 return (GET_CODE (op) == MEM
916 && EXTRA_CONSTRAINT (op, 'U'));
919 /* Handle machine specific pragmas for compatibility with existing
920 compilers for the H8/300.
922 pragma saveall generates prologue/epilogue code which saves and
923 restores all the registers on function entry.
925 pragma interrupt saves and restores all registers, and exits with
926 an rte instruction rather than an rts. A pointer to a function
927 with this attribute may be safely used in an interrupt vector. */
930 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
932 pragma_interrupt = 1;
936 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
941 /* If the next function argument with MODE and TYPE is to be passed in
942 a register, return a reg RTX for the hard register in which to pass
943 the argument. CUM represents the state after the last argument.
944 If the argument is to be pushed, NULL_RTX is returned. */
947 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
948 tree type, int named)
950 static const char *const hand_list[] = {
969 rtx result = NULL_RTX;
973 /* Never pass unnamed arguments in registers. */
977 /* Pass 3 regs worth of data in regs when user asked on the command line. */
978 if (TARGET_QUICKCALL)
981 /* If calling hand written assembler, use 4 regs of args. */
984 const char * const *p;
986 fname = XSTR (cum->libcall, 0);
988 /* See if this libcall is one of the hand coded ones. */
989 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1000 if (mode == BLKmode)
1001 size = int_size_in_bytes (type);
1003 size = GET_MODE_SIZE (mode);
1005 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1006 && cum->nbytes / UNITS_PER_WORD <= 3)
1007 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1014 h8300_and_costs (rtx x)
1018 if (GET_MODE (x) == QImode)
1021 if (GET_MODE (x) != HImode
1022 && GET_MODE (x) != SImode)
1027 operands[2] = XEXP (x, 1);
1029 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1033 h8300_shift_costs (rtx x)
1037 if (GET_MODE (x) != QImode
1038 && GET_MODE (x) != HImode
1039 && GET_MODE (x) != SImode)
1044 operands[2] = XEXP (x, 1);
1046 return compute_a_shift_length (NULL, operands) / 2;
1050 h8300_rtx_costs (rtx x, int code, int outer_code, int *total)
1056 HOST_WIDE_INT n = INTVAL (x);
1058 if (-4 <= n || n <= 4)
1069 *total = 0 + (outer_code == SET);
1073 if (TARGET_H8300H || TARGET_H8300S)
1074 *total = 0 + (outer_code == SET);
1095 *total = COSTS_N_INSNS (h8300_and_costs (x));
1098 /* We say that MOD and DIV are so expensive because otherwise we'll
1099 generate some really horrible code for division of a power of two. */
1112 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1117 if (GET_MODE (x) == HImode)
1129 /* Documentation for the machine specific operand escapes:
1131 'E' like s but negative.
1132 'F' like t but negative.
1133 'G' constant just the negative
1134 'R' print operand as a byte:8 address if appropriate, else fall back to
1136 'S' print operand as a long word
1137 'T' print operand as a word
1138 'V' find the set bit, and print its number.
1139 'W' find the clear bit, and print its number.
1140 'X' print operand as a byte
1141 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1142 If this operand isn't a register, fall back to 'R' handling.
1144 'c' print the opcode corresponding to rtl
1145 'e' first word of 32 bit value - if reg, then least reg. if mem
1146 then least. if const then most sig word
1147 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1148 then +2. if const then least sig word
1149 'j' print operand as condition code.
1150 'k' print operand as reverse condition code.
1151 's' print as low byte of 16 bit value
1152 't' print as high byte of 16 bit value
1153 'w' print as low byte of 32 bit value
1154 'x' print as 2nd byte of 32 bit value
1155 'y' print as 3rd byte of 32 bit value
1156 'z' print as msb of 32 bit value
1159 /* Return assembly language string which identifies a comparison type. */
1162 cond_string (enum rtx_code code)
1191 /* Print operand X using operand code CODE to assembly language output file
1195 print_operand (FILE *file, rtx x, int code)
1197 /* This is used for communication between codes V,W,Z and Y. */
1203 switch (GET_CODE (x))
1206 fprintf (file, "%sl", names_big[REGNO (x)]);
1209 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1216 switch (GET_CODE (x))
1219 fprintf (file, "%sh", names_big[REGNO (x)]);
1222 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1229 if (GET_CODE (x) != CONST_INT)
1231 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1234 if (GET_CODE (x) == REG)
1235 fprintf (file, "%s", names_extended[REGNO (x)]);
1240 if (GET_CODE (x) == REG)
1241 fprintf (file, "%s", names_big[REGNO (x)]);
1246 bitint = exact_log2 (INTVAL (x) & 0xff);
1249 fprintf (file, "#%d", bitint);
1252 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1255 fprintf (file, "#%d", bitint);
1259 if (GET_CODE (x) == REG)
1260 fprintf (file, "%s", byte_reg (x, 0));
1267 if (GET_CODE (x) == REG)
1268 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1270 print_operand (file, x, 'R');
1274 bitint = INTVAL (x);
1275 fprintf (file, "#%d", bitint & 7);
1278 switch (GET_CODE (x))
1281 fprintf (file, "or");
1284 fprintf (file, "xor");
1287 fprintf (file, "and");
1294 switch (GET_CODE (x))
1298 fprintf (file, "%s", names_big[REGNO (x)]);
1300 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1303 print_operand (file, x, 0);
1306 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1312 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1313 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1314 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1323 switch (GET_CODE (x))
1327 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1329 fprintf (file, "%s", names_big[REGNO (x)]);
1332 x = adjust_address (x, HImode, 2);
1333 print_operand (file, x, 0);
1336 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1342 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1343 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1344 fprintf (file, "#%ld", (val & 0xffff));
1352 fputs (cond_string (GET_CODE (x)), file);
1355 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1358 if (GET_CODE (x) == CONST_INT)
1359 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1361 fprintf (file, "%s", byte_reg (x, 0));
1364 if (GET_CODE (x) == CONST_INT)
1365 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1367 fprintf (file, "%s", byte_reg (x, 1));
1370 if (GET_CODE (x) == CONST_INT)
1371 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1373 fprintf (file, "%s",
1374 byte_reg (x, TARGET_H8300 ? 2 : 0));
1377 if (GET_CODE (x) == CONST_INT)
1378 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1380 fprintf (file, "%s",
1381 byte_reg (x, TARGET_H8300 ? 3 : 1));
1384 if (GET_CODE (x) == CONST_INT)
1385 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1387 fprintf (file, "%s", byte_reg (x, 0));
1390 if (GET_CODE (x) == CONST_INT)
1391 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1393 fprintf (file, "%s", byte_reg (x, 1));
1398 switch (GET_CODE (x))
1401 switch (GET_MODE (x))
1404 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1405 fprintf (file, "%s", byte_reg (x, 0));
1406 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1407 fprintf (file, "%s", names_big[REGNO (x)]);
1411 fprintf (file, "%s", names_big[REGNO (x)]);
1415 fprintf (file, "%s", names_extended[REGNO (x)]);
1424 rtx addr = XEXP (x, 0);
1426 fprintf (file, "@");
1427 output_address (addr);
1429 /* We fall back from smaller addressing to larger
1430 addressing in various ways depending on CODE. */
1434 /* Used for mov.b and bit operations. */
1435 if (h8300_eightbit_constant_address_p (addr))
1437 fprintf (file, ":8");
1441 /* Fall through. We should not get here if we are
1442 processing bit operations on H8/300 or H8/300H
1443 because 'U' constraint does not allow bit
1444 operations on the tiny area on these machines. */
1448 /* Used for mov.w and mov.l. */
1449 if (h8300_tiny_constant_address_p (addr))
1450 fprintf (file, ":16");
1462 fprintf (file, "#");
1463 print_operand_address (file, x);
1469 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1470 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1471 fprintf (file, "#%ld", val);
1480 /* Output assembly language output for the address ADDR to FILE. */
1483 print_operand_address (FILE *file, rtx addr)
1485 switch (GET_CODE (addr))
1488 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1492 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1496 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1500 fprintf (file, "(");
1501 if (GET_CODE (XEXP (addr, 0)) == REG)
1504 print_operand_address (file, XEXP (addr, 1));
1505 fprintf (file, ",");
1506 print_operand_address (file, XEXP (addr, 0));
1511 print_operand_address (file, XEXP (addr, 0));
1512 fprintf (file, "+");
1513 print_operand_address (file, XEXP (addr, 1));
1515 fprintf (file, ")");
1520 /* Since the H8/300 only has 16 bit pointers, negative values are also
1521 those >= 32768. This happens for example with pointer minus a
1522 constant. We don't want to turn (char *p - 2) into
1523 (char *p + 65534) because loop unrolling can build upon this
1524 (IE: char *p + 131068). */
1525 int n = INTVAL (addr);
1527 n = (int) (short) n;
1528 fprintf (file, "%d", n);
1533 output_addr_const (file, addr);
1538 /* Output all insn addresses and their sizes into the assembly language
1539 output file. This is helpful for debugging whether the length attributes
1540 in the md file are correct. This is not meant to be a user selectable
1544 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1545 int num_operands ATTRIBUTE_UNUSED)
1547 /* This holds the last insn address. */
1548 static int last_insn_address = 0;
1550 const int uid = INSN_UID (insn);
1552 if (TARGET_ADDRESSES)
1554 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1555 INSN_ADDRESSES (uid) - last_insn_address);
1556 last_insn_address = INSN_ADDRESSES (uid);
1560 /* Prepare for an SI sized move. */
1563 h8300_expand_movsi (rtx operands[])
1565 rtx src = operands[1];
1566 rtx dst = operands[0];
1567 if (!reload_in_progress && !reload_completed)
1569 if (!register_operand (dst, GET_MODE (dst)))
1571 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1572 emit_move_insn (tmp, src);
1579 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1580 Define the offset between two registers, one to be eliminated, and
1581 the other its replacement, at the start of a routine. */
1584 h8300_initial_elimination_offset (int from, int to)
1586 /* The number of bytes that the return address takes on the stack. */
1587 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1589 /* The number of bytes that the saved frame pointer takes on the stack. */
1590 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1592 /* The number of bytes that the saved registers, excluding the frame
1593 pointer, take on the stack. */
1594 int saved_regs_size = 0;
1596 /* The number of bytes that the locals takes on the stack. */
1597 int frame_size = round_frame_size (get_frame_size ());
1601 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1602 if (WORD_REG_USED (regno))
1603 saved_regs_size += UNITS_PER_WORD;
1605 /* Adjust saved_regs_size because the above loop took the frame
1606 pointer int account. */
1607 saved_regs_size -= fp_size;
1609 if (to == HARD_FRAME_POINTER_REGNUM)
1613 case ARG_POINTER_REGNUM:
1614 return pc_size + fp_size;
1615 case RETURN_ADDRESS_POINTER_REGNUM:
1617 case FRAME_POINTER_REGNUM:
1618 return -saved_regs_size;
1623 else if (to == STACK_POINTER_REGNUM)
1627 case ARG_POINTER_REGNUM:
1628 return pc_size + saved_regs_size + frame_size;
1629 case RETURN_ADDRESS_POINTER_REGNUM:
1630 return saved_regs_size + frame_size;
1631 case FRAME_POINTER_REGNUM:
1642 h8300_return_addr_rtx (int count, rtx frame)
1647 ret = gen_rtx_MEM (Pmode,
1648 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1649 else if (flag_omit_frame_pointer)
1652 ret = gen_rtx_MEM (Pmode,
1653 memory_address (Pmode,
1654 plus_constant (frame, UNITS_PER_WORD)));
1655 set_mem_alias_set (ret, get_frame_alias_set ());
1659 /* Update the condition code from the insn. */
1662 notice_update_cc (rtx body, rtx insn)
1666 switch (get_attr_cc (insn))
1669 /* Insn does not affect CC at all. */
1673 /* Insn does not change CC, but the 0'th operand has been changed. */
1674 if (cc_status.value1 != 0
1675 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1676 cc_status.value1 = 0;
1677 if (cc_status.value2 != 0
1678 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1679 cc_status.value2 = 0;
1683 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1684 The V flag is unusable. The C flag may or may not be known but
1685 that's ok because alter_cond will change tests to use EQ/NE. */
1687 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1688 set = single_set (insn);
1689 cc_status.value1 = SET_SRC (set);
1690 if (SET_DEST (set) != cc0_rtx)
1691 cc_status.value2 = SET_DEST (set);
1695 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1696 The C flag may or may not be known but that's ok because
1697 alter_cond will change tests to use EQ/NE. */
1699 cc_status.flags |= CC_NO_CARRY;
1700 set = single_set (insn);
1701 cc_status.value1 = SET_SRC (set);
1702 if (SET_DEST (set) != cc0_rtx)
1704 /* If the destination is STRICT_LOW_PART, strip off
1706 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1707 cc_status.value2 = XEXP (SET_DEST (set), 0);
1709 cc_status.value2 = SET_DEST (set);
1714 /* The insn is a compare instruction. */
1716 cc_status.value1 = SET_SRC (body);
1720 /* Insn doesn't leave CC in a usable state. */
1726 /* Return nonzero if X is a stack pointer. */
1729 stack_pointer_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1731 return x == stack_pointer_rtx;
1734 /* Return nonzero if X is a constant whose absolute value is greater
1738 const_int_gt_2_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1740 return (GET_CODE (x) == CONST_INT
1741 && abs (INTVAL (x)) > 2);
1744 /* Return nonzero if X is a constant whose absolute value is no
1748 const_int_ge_8_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1750 return (GET_CODE (x) == CONST_INT
1751 && abs (INTVAL (x)) >= 8);
1754 /* Return nonzero if X is a constant expressible in QImode. */
1757 const_int_qi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1759 return (GET_CODE (x) == CONST_INT
1760 && (INTVAL (x) & 0xff) == INTVAL (x));
1763 /* Return nonzero if X is a constant expressible in HImode. */
1766 const_int_hi_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1768 return (GET_CODE (x) == CONST_INT
1769 && (INTVAL (x) & 0xffff) == INTVAL (x));
1772 /* Return nonzero if X is a constant suitable for inc/dec. */
1775 incdec_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1777 return (GET_CODE (x) == CONST_INT
1778 && (CONST_OK_FOR_M (INTVAL (x))
1779 || CONST_OK_FOR_O (INTVAL (x))));
1782 /* Return nonzero if X is either EQ or NE. */
1785 eqne_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1787 enum rtx_code code = GET_CODE (x);
1789 return (code == EQ || code == NE);
1792 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1795 gtle_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1797 enum rtx_code code = GET_CODE (x);
1799 return (code == GT || code == LE || code == GTU || code == LEU);
1802 /* Return nonzero if X is either GTU or LEU. */
1805 gtuleu_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1807 enum rtx_code code = GET_CODE (x);
1809 return (code == GTU || code == LEU);
1812 /* Return nonzero if X is either IOR or XOR. */
1815 iorxor_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1817 enum rtx_code code = GET_CODE (x);
1819 return (code == IOR || code == XOR);
1822 /* Recognize valid operators for bit instructions. */
1825 bit_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1827 enum rtx_code code = GET_CODE (x);
1834 /* Return the length of mov instruction. */
1837 compute_mov_length (rtx *operands)
1839 /* If the mov instruction involves a memory operand, we compute the
1840 length, assuming the largest addressing mode is used, and then
1841 adjust later in the function. Otherwise, we compute and return
1842 the exact length in one step. */
1843 enum machine_mode mode = GET_MODE (operands[0]);
1844 rtx dest = operands[0];
1845 rtx src = operands[1];
1848 if (GET_CODE (src) == MEM)
1849 addr = XEXP (src, 0);
1850 else if (GET_CODE (dest) == MEM)
1851 addr = XEXP (dest, 0);
1857 unsigned int base_length;
1862 if (addr == NULL_RTX)
1865 /* The eightbit addressing is available only in QImode, so
1866 go ahead and take care of it. */
1867 if (h8300_eightbit_constant_address_p (addr))
1874 if (addr == NULL_RTX)
1879 if (src == const0_rtx)
1889 if (addr == NULL_RTX)
1894 if (GET_CODE (src) == CONST_INT)
1896 if (src == const0_rtx)
1899 if ((INTVAL (src) & 0xffff) == 0)
1902 if ((INTVAL (src) & 0xffff) == 0)
1905 if ((INTVAL (src) & 0xffff)
1906 == ((INTVAL (src) >> 16) & 0xffff))
1916 if (addr == NULL_RTX)
1921 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
1934 /* Adjust the length based on the addressing mode used.
1935 Specifically, we subtract the difference between the actual
1936 length and the longest one, which is @(d:16,Rs). For SImode
1937 and SFmode, we double the adjustment because two mov.w are
1938 used to do the job. */
1940 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
1941 if (GET_CODE (addr) == PRE_DEC
1942 || GET_CODE (addr) == POST_INC)
1944 if (mode == QImode || mode == HImode)
1945 return base_length - 2;
1947 /* In SImode and SFmode, we use two mov.w instructions, so
1948 double the adjustment. */
1949 return base_length - 4;
1952 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
1953 in SImode and SFmode, the second mov.w involves an address
1954 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
1956 if (GET_CODE (addr) == REG)
1957 return base_length - 2;
1963 unsigned int base_length;
1968 if (addr == NULL_RTX)
1971 /* The eightbit addressing is available only in QImode, so
1972 go ahead and take care of it. */
1973 if (h8300_eightbit_constant_address_p (addr))
1980 if (addr == NULL_RTX)
1985 if (src == const0_rtx)
1995 if (addr == NULL_RTX)
1999 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2005 if (GET_CODE (src) == CONST_INT)
2007 int val = INTVAL (src);
2012 if (val == (val & 0x00ff) || val == (val & 0xff00))
2015 switch (val & 0xffffffff)
2036 if (addr == NULL_RTX)
2041 if (CONST_DOUBLE_OK_FOR_LETTER_P (src, 'G'))
2054 /* Adjust the length based on the addressing mode used.
2055 Specifically, we subtract the difference between the actual
2056 length and the longest one, which is @(d:24,ERs). */
2058 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2059 if (GET_CODE (addr) == PRE_DEC
2060 || GET_CODE (addr) == POST_INC)
2061 return base_length - 6;
2063 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2064 if (GET_CODE (addr) == REG)
2065 return base_length - 6;
2067 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2069 if (GET_CODE (addr) == PLUS
2070 && GET_CODE (XEXP (addr, 0)) == REG
2071 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2072 && INTVAL (XEXP (addr, 1)) > -32768
2073 && INTVAL (XEXP (addr, 1)) < 32767)
2074 return base_length - 4;
2076 /* @aa:16 is 4 bytes shorter than the longest. */
2077 if (h8300_tiny_constant_address_p (addr))
2078 return base_length - 4;
2080 /* @aa:24 is 2 bytes shorter than the longest. */
2081 if (CONSTANT_P (addr))
2082 return base_length - 2;
2089 output_plussi (rtx *operands)
2091 enum machine_mode mode = GET_MODE (operands[0]);
2098 if (GET_CODE (operands[2]) == REG)
2099 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2101 if (GET_CODE (operands[2]) == CONST_INT)
2103 HOST_WIDE_INT n = INTVAL (operands[2]);
2105 if ((n & 0xffffff) == 0)
2106 return "add\t%z2,%z0";
2107 if ((n & 0xffff) == 0)
2108 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2109 if ((n & 0xff) == 0)
2110 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2113 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2117 if (GET_CODE (operands[2]) == REG)
2118 return "add.l\t%S2,%S0";
2120 if (GET_CODE (operands[2]) == CONST_INT)
2122 HOST_WIDE_INT intval = INTVAL (operands[2]);
2124 /* See if we can finish with 2 bytes. */
2126 switch ((unsigned int) intval & 0xffffffff)
2131 return "adds\t%2,%S0";
2136 return "subs\t%G2,%S0";
2140 operands[2] = GEN_INT (intval >> 16);
2141 return "inc.w\t%2,%e0";
2145 operands[2] = GEN_INT (intval >> 16);
2146 return "dec.w\t%G2,%e0";
2149 /* See if we can finish with 4 bytes. */
2150 if ((intval & 0xffff) == 0)
2152 operands[2] = GEN_INT (intval >> 16);
2153 return "add.w\t%2,%e0";
2157 return "add.l\t%S2,%S0";
2162 compute_plussi_length (rtx *operands)
2164 enum machine_mode mode = GET_MODE (operands[0]);
2171 if (GET_CODE (operands[2]) == REG)
2174 if (GET_CODE (operands[2]) == CONST_INT)
2176 HOST_WIDE_INT n = INTVAL (operands[2]);
2178 if ((n & 0xffffff) == 0)
2180 if ((n & 0xffff) == 0)
2182 if ((n & 0xff) == 0)
2190 if (GET_CODE (operands[2]) == REG)
2193 if (GET_CODE (operands[2]) == CONST_INT)
2195 HOST_WIDE_INT intval = INTVAL (operands[2]);
2197 /* See if we can finish with 2 bytes. */
2199 switch ((unsigned int) intval & 0xffffffff)
2220 /* See if we can finish with 4 bytes. */
2221 if ((intval & 0xffff) == 0)
2230 compute_plussi_cc (rtx *operands)
2232 enum machine_mode mode = GET_MODE (operands[0]);
2243 if (GET_CODE (operands[2]) == REG)
2246 if (GET_CODE (operands[2]) == CONST_INT)
2248 HOST_WIDE_INT intval = INTVAL (operands[2]);
2250 /* See if we can finish with 2 bytes. */
2252 switch ((unsigned int) intval & 0xffffffff)
2257 return CC_NONE_0HIT;
2262 return CC_NONE_0HIT;
2273 /* See if we can finish with 4 bytes. */
2274 if ((intval & 0xffff) == 0)
2283 output_logical_op (enum machine_mode mode, rtx *operands)
2285 /* Figure out the logical op that we need to perform. */
2286 enum rtx_code code = GET_CODE (operands[3]);
2287 /* Pretend that every byte is affected if both operands are registers. */
2288 const unsigned HOST_WIDE_INT intval =
2289 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2290 ? INTVAL (operands[2]) : 0x55555555);
2291 /* The determinant of the algorithm. If we perform an AND, 0
2292 affects a bit. Otherwise, 1 affects a bit. */
2293 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2294 /* Break up DET into pieces. */
2295 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2296 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2297 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2298 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2299 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2300 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2301 int lower_half_easy_p = 0;
2302 int upper_half_easy_p = 0;
2303 /* The name of an insn. */
2325 /* First, see if we can finish with one insn. */
2326 if ((TARGET_H8300H || TARGET_H8300S)
2330 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2331 output_asm_insn (insn_buf, operands);
2335 /* Take care of the lower byte. */
2338 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2339 output_asm_insn (insn_buf, operands);
2341 /* Take care of the upper byte. */
2344 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2345 output_asm_insn (insn_buf, operands);
2350 if (TARGET_H8300H || TARGET_H8300S)
2352 /* Determine if the lower half can be taken care of in no more
2354 lower_half_easy_p = (b0 == 0
2356 || (code != IOR && w0 == 0xffff));
2358 /* Determine if the upper half can be taken care of in no more
2360 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2361 || (code == AND && w1 == 0xff00));
2364 /* Check if doing everything with one insn is no worse than
2365 using multiple insns. */
2366 if ((TARGET_H8300H || TARGET_H8300S)
2367 && w0 != 0 && w1 != 0
2368 && !(lower_half_easy_p && upper_half_easy_p)
2369 && !(code == IOR && w1 == 0xffff
2370 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2372 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2373 output_asm_insn (insn_buf, operands);
2377 /* Take care of the lower and upper words individually. For
2378 each word, we try different methods in the order of
2380 1) the special insn (in case of AND or XOR),
2381 2) the word-wise insn, and
2382 3) The byte-wise insn. */
2384 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2385 output_asm_insn ((code == AND)
2386 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2388 else if ((TARGET_H8300H || TARGET_H8300S)
2392 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2393 output_asm_insn (insn_buf, operands);
2399 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2400 output_asm_insn (insn_buf, operands);
2404 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2405 output_asm_insn (insn_buf, operands);
2410 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2411 output_asm_insn ((code == AND)
2412 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2414 else if ((TARGET_H8300H || TARGET_H8300S)
2417 && (w0 & 0x8000) != 0)
2419 output_asm_insn ("exts.l\t%S0", operands);
2421 else if ((TARGET_H8300H || TARGET_H8300S)
2425 output_asm_insn ("extu.w\t%e0", operands);
2427 else if (TARGET_H8300H || TARGET_H8300S)
2431 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2432 output_asm_insn (insn_buf, operands);
2439 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2440 output_asm_insn (insn_buf, operands);
2444 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2445 output_asm_insn (insn_buf, operands);
2457 compute_logical_op_length (enum machine_mode mode, rtx *operands)
2459 /* Figure out the logical op that we need to perform. */
2460 enum rtx_code code = GET_CODE (operands[3]);
2461 /* Pretend that every byte is affected if both operands are registers. */
2462 const unsigned HOST_WIDE_INT intval =
2463 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2464 ? INTVAL (operands[2]) : 0x55555555);
2465 /* The determinant of the algorithm. If we perform an AND, 0
2466 affects a bit. Otherwise, 1 affects a bit. */
2467 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2468 /* Break up DET into pieces. */
2469 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2470 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2471 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2472 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2473 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2474 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2475 int lower_half_easy_p = 0;
2476 int upper_half_easy_p = 0;
2478 unsigned int length = 0;
2483 /* First, see if we can finish with one insn. */
2484 if ((TARGET_H8300H || TARGET_H8300S)
2488 if (REG_P (operands[2]))
2495 /* Take care of the lower byte. */
2499 /* Take care of the upper byte. */
2505 if (TARGET_H8300H || TARGET_H8300S)
2507 /* Determine if the lower half can be taken care of in no more
2509 lower_half_easy_p = (b0 == 0
2511 || (code != IOR && w0 == 0xffff));
2513 /* Determine if the upper half can be taken care of in no more
2515 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2516 || (code == AND && w1 == 0xff00));
2519 /* Check if doing everything with one insn is no worse than
2520 using multiple insns. */
2521 if ((TARGET_H8300H || TARGET_H8300S)
2522 && w0 != 0 && w1 != 0
2523 && !(lower_half_easy_p && upper_half_easy_p)
2524 && !(code == IOR && w1 == 0xffff
2525 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2527 if (REG_P (operands[2]))
2534 /* Take care of the lower and upper words individually. For
2535 each word, we try different methods in the order of
2537 1) the special insn (in case of AND or XOR),
2538 2) the word-wise insn, and
2539 3) The byte-wise insn. */
2541 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2545 else if ((TARGET_H8300H || TARGET_H8300S)
2561 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2565 else if ((TARGET_H8300H || TARGET_H8300S)
2568 && (w0 & 0x8000) != 0)
2572 else if ((TARGET_H8300H || TARGET_H8300S)
2578 else if (TARGET_H8300H || TARGET_H8300S)
2600 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
2602 /* Figure out the logical op that we need to perform. */
2603 enum rtx_code code = GET_CODE (operands[3]);
2604 /* Pretend that every byte is affected if both operands are registers. */
2605 const unsigned HOST_WIDE_INT intval =
2606 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2607 ? INTVAL (operands[2]) : 0x55555555);
2608 /* The determinant of the algorithm. If we perform an AND, 0
2609 affects a bit. Otherwise, 1 affects a bit. */
2610 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2611 /* Break up DET into pieces. */
2612 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2613 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2614 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2615 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2616 int lower_half_easy_p = 0;
2617 int upper_half_easy_p = 0;
2618 /* Condition code. */
2619 enum attr_cc cc = CC_CLOBBER;
2624 /* First, see if we can finish with one insn. */
2625 if ((TARGET_H8300H || TARGET_H8300S)
2633 if (TARGET_H8300H || TARGET_H8300S)
2635 /* Determine if the lower half can be taken care of in no more
2637 lower_half_easy_p = (b0 == 0
2639 || (code != IOR && w0 == 0xffff));
2641 /* Determine if the upper half can be taken care of in no more
2643 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2644 || (code == AND && w1 == 0xff00));
2647 /* Check if doing everything with one insn is no worse than
2648 using multiple insns. */
2649 if ((TARGET_H8300H || TARGET_H8300S)
2650 && w0 != 0 && w1 != 0
2651 && !(lower_half_easy_p && upper_half_easy_p)
2652 && !(code == IOR && w1 == 0xffff
2653 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2659 if ((TARGET_H8300H || TARGET_H8300S)
2662 && (w0 & 0x8000) != 0)
2676 We devote a fair bit of code to getting efficient shifts since we
2677 can only shift one bit at a time on the H8/300 and H8/300H and only
2678 one or two bits at a time on the H8S.
2680 All shift code falls into one of the following ways of
2683 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2684 when a straight line shift is about the same size or smaller than
2687 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2688 off the bits we don't need. This is used when only a few of the
2689 bits in the original value will survive in the shifted value.
2691 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2692 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2693 shifts can be added if the shift count is slightly more than 8 or
2694 16. This case also includes other oddballs that are not worth
2697 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2699 For each shift count, we try to use code that has no trade-off
2700 between code size and speed whenever possible.
2702 If the trade-off is unavoidable, we try to be reasonable.
2703 Specifically, the fastest version is one instruction longer than
2704 the shortest version, we take the fastest version. We also provide
2705 the use a way to switch back to the shortest version with -Os.
2707 For the details of the shift algorithms for various shift counts,
2708 refer to shift_alg_[qhs]i. */
2711 nshift_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2713 switch (GET_CODE (x))
2725 /* Emit code to do shifts. */
2728 expand_a_shift (enum machine_mode mode, int code, rtx operands[])
2730 emit_move_insn (operands[0], operands[1]);
2732 /* Need a loop to get all the bits we want - we generate the
2733 code at emit time, but need to allocate a scratch reg now. */
2735 emit_insn (gen_rtx_PARALLEL
2738 gen_rtx_SET (VOIDmode, operands[0],
2739 gen_rtx_fmt_ee (code, mode,
2740 operands[0], operands[2])),
2741 gen_rtx_CLOBBER (VOIDmode,
2742 gen_rtx_SCRATCH (QImode)))));
2745 /* Symbols of the various modes which can be used as indices. */
2749 QIshift, HIshift, SIshift
2752 /* For single bit shift insns, record assembler and what bits of the
2753 condition code are valid afterwards (represented as various CC_FOO
2754 bits, 0 means CC isn't left in a usable state). */
2758 const char *const assembler;
2762 /* Assembler instruction shift table.
2764 These tables are used to look up the basic shifts.
2765 They are indexed by cpu, shift_type, and mode. */
2767 static const struct shift_insn shift_one[2][3][3] =
2773 { "shll\t%X0", CC_SET_ZNV },
2774 { "add.w\t%T0,%T0", CC_SET_ZN },
2775 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2777 /* SHIFT_LSHIFTRT */
2779 { "shlr\t%X0", CC_SET_ZNV },
2780 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2781 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2783 /* SHIFT_ASHIFTRT */
2785 { "shar\t%X0", CC_SET_ZNV },
2786 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2787 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2794 { "shll.b\t%X0", CC_SET_ZNV },
2795 { "shll.w\t%T0", CC_SET_ZNV },
2796 { "shll.l\t%S0", CC_SET_ZNV }
2798 /* SHIFT_LSHIFTRT */
2800 { "shlr.b\t%X0", CC_SET_ZNV },
2801 { "shlr.w\t%T0", CC_SET_ZNV },
2802 { "shlr.l\t%S0", CC_SET_ZNV }
2804 /* SHIFT_ASHIFTRT */
2806 { "shar.b\t%X0", CC_SET_ZNV },
2807 { "shar.w\t%T0", CC_SET_ZNV },
2808 { "shar.l\t%S0", CC_SET_ZNV }
2813 static const struct shift_insn shift_two[3][3] =
2817 { "shll.b\t#2,%X0", CC_SET_ZNV },
2818 { "shll.w\t#2,%T0", CC_SET_ZNV },
2819 { "shll.l\t#2,%S0", CC_SET_ZNV }
2821 /* SHIFT_LSHIFTRT */
2823 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2824 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2825 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2827 /* SHIFT_ASHIFTRT */
2829 { "shar.b\t#2,%X0", CC_SET_ZNV },
2830 { "shar.w\t#2,%T0", CC_SET_ZNV },
2831 { "shar.l\t#2,%S0", CC_SET_ZNV }
2835 /* Rotates are organized by which shift they'll be used in implementing.
2836 There's no need to record whether the cc is valid afterwards because
2837 it is the AND insn that will decide this. */
2839 static const char *const rotate_one[2][3][3] =
2846 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2849 /* SHIFT_LSHIFTRT */
2852 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2855 /* SHIFT_ASHIFTRT */
2858 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2870 /* SHIFT_LSHIFTRT */
2876 /* SHIFT_ASHIFTRT */
2885 static const char *const rotate_two[3][3] =
2893 /* SHIFT_LSHIFTRT */
2899 /* SHIFT_ASHIFTRT */
2908 /* Shift algorithm. */
2911 /* The number of bits to be shifted by shift1 and shift2. Valid
2912 when ALG is SHIFT_SPECIAL. */
2913 unsigned int remainder;
2915 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2916 const char *special;
2918 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2919 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2922 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2923 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2926 /* CC status for SHIFT_INLINE. */
2929 /* CC status for SHIFT_SPECIAL. */
2933 static void get_shift_alg (enum shift_type,
2934 enum shift_mode, unsigned int,
2935 struct shift_info *);
2937 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2938 best algorithm for doing the shift. The assembler code is stored
2939 in the pointers in INFO. We achieve the maximum efficiency in most
2940 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2941 SImode in particular have a lot of room to optimize.
2943 We first determine the strategy of the shift algorithm by a table
2944 lookup. If that tells us to use a hand crafted assembly code, we
2945 go into the big switch statement to find what that is. Otherwise,
2946 we resort to a generic way, such as inlining. In either case, the
2947 result is returned through INFO. */
2950 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
2951 unsigned int count, struct shift_info *info)
2955 /* Find the target CPU. */
2958 else if (TARGET_H8300H)
2963 /* Find the shift algorithm. */
2964 info->alg = SHIFT_LOOP;
2968 if (count < GET_MODE_BITSIZE (QImode))
2969 info->alg = shift_alg_qi[cpu][shift_type][count];
2973 if (count < GET_MODE_BITSIZE (HImode))
2974 info->alg = shift_alg_hi[cpu][shift_type][count];
2978 if (count < GET_MODE_BITSIZE (SImode))
2979 info->alg = shift_alg_si[cpu][shift_type][count];
2986 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2990 info->remainder = count;
2994 /* It is up to the caller to know that looping clobbers cc. */
2995 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2996 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2997 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3001 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
3002 info->shift2 = rotate_two[shift_type][shift_mode];
3003 info->cc_inline = CC_CLOBBER;
3007 /* REMAINDER is 0 for most cases, so initialize it to 0. */
3008 info->remainder = 0;
3009 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
3010 info->shift2 = shift_two[shift_type][shift_mode].assembler;
3011 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
3012 info->cc_special = CC_CLOBBER;
3016 /* Here we only deal with SHIFT_SPECIAL. */
3020 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
3021 through the entire value. */
3022 if (shift_type == SHIFT_ASHIFTRT && count == 7)
3024 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
3036 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
3038 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
3040 case SHIFT_LSHIFTRT:
3042 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
3044 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
3046 case SHIFT_ASHIFTRT:
3047 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
3051 else if ((8 <= count && count <= 13)
3052 || (TARGET_H8300S && count == 14))
3054 info->remainder = count - 8;
3059 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
3061 case SHIFT_LSHIFTRT:
3064 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
3065 info->shift1 = "shlr.b\t%s0";
3066 info->cc_inline = CC_SET_ZNV;
3070 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
3071 info->cc_special = CC_SET_ZNV;
3074 case SHIFT_ASHIFTRT:
3077 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
3078 info->shift1 = "shar.b\t%s0";
3082 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
3083 info->cc_special = CC_SET_ZNV;
3088 else if (count == 14)
3094 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
3096 case SHIFT_LSHIFTRT:
3098 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
3100 case SHIFT_ASHIFTRT:
3102 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
3103 else if (TARGET_H8300H)
3105 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
3106 info->cc_special = CC_SET_ZNV;
3108 else /* TARGET_H8300S */
3113 else if (count == 15)
3118 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3120 case SHIFT_LSHIFTRT:
3121 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3123 case SHIFT_ASHIFTRT:
3124 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3131 if (TARGET_H8300 && 8 <= count && count <= 9)
3133 info->remainder = count - 8;
3138 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3140 case SHIFT_LSHIFTRT:
3141 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3142 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3144 case SHIFT_ASHIFTRT:
3145 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3149 else if (count == 8 && !TARGET_H8300)
3154 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3156 case SHIFT_LSHIFTRT:
3157 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3159 case SHIFT_ASHIFTRT:
3160 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3164 else if (count == 15 && TARGET_H8300)
3170 case SHIFT_LSHIFTRT:
3171 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3173 case SHIFT_ASHIFTRT:
3174 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3178 else if (count == 15 && !TARGET_H8300)
3183 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3184 info->cc_special = CC_SET_ZNV;
3186 case SHIFT_LSHIFTRT:
3187 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3188 info->cc_special = CC_SET_ZNV;
3190 case SHIFT_ASHIFTRT:
3194 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3195 || (TARGET_H8300H && 16 <= count && count <= 19)
3196 || (TARGET_H8300S && 16 <= count && count <= 21))
3198 info->remainder = count - 16;
3203 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3205 info->shift1 = "add.w\t%e0,%e0";
3207 case SHIFT_LSHIFTRT:
3210 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3211 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3215 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3216 info->cc_special = CC_SET_ZNV;
3219 case SHIFT_ASHIFTRT:
3222 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3223 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3227 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3228 info->cc_special = CC_SET_ZNV;
3233 else if (TARGET_H8300 && 24 <= count && count <= 28)
3235 info->remainder = count - 24;
3240 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3241 info->shift1 = "shll.b\t%z0";
3242 info->cc_inline = CC_SET_ZNV;
3244 case SHIFT_LSHIFTRT:
3245 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3246 info->shift1 = "shlr.b\t%w0";
3247 info->cc_inline = CC_SET_ZNV;
3249 case SHIFT_ASHIFTRT:
3250 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3251 info->shift1 = "shar.b\t%w0";
3252 info->cc_inline = CC_SET_ZNV;
3256 else if ((TARGET_H8300H && count == 24)
3257 || (TARGET_H8300S && 24 <= count && count <= 25))
3259 info->remainder = count - 24;
3264 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3266 case SHIFT_LSHIFTRT:
3267 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3268 info->cc_special = CC_SET_ZNV;
3270 case SHIFT_ASHIFTRT:
3271 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3272 info->cc_special = CC_SET_ZNV;
3276 else if (!TARGET_H8300 && count == 28)
3282 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3284 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3286 case SHIFT_LSHIFTRT:
3289 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3290 info->cc_special = CC_SET_ZNV;
3293 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3295 case SHIFT_ASHIFTRT:
3299 else if (!TARGET_H8300 && count == 29)
3305 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3307 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3309 case SHIFT_LSHIFTRT:
3312 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3313 info->cc_special = CC_SET_ZNV;
3317 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3318 info->cc_special = CC_SET_ZNV;
3321 case SHIFT_ASHIFTRT:
3325 else if (!TARGET_H8300 && count == 30)
3331 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3333 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3335 case SHIFT_LSHIFTRT:
3337 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3339 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3341 case SHIFT_ASHIFTRT:
3345 else if (count == 31)
3352 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3354 case SHIFT_LSHIFTRT:
3355 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3357 case SHIFT_ASHIFTRT:
3358 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3367 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3368 info->cc_special = CC_SET_ZNV;
3370 case SHIFT_LSHIFTRT:
3371 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3372 info->cc_special = CC_SET_ZNV;
3374 case SHIFT_ASHIFTRT:
3375 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3376 info->cc_special = CC_SET_ZNV;
3389 info->shift2 = NULL;
3392 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3393 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3396 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
3401 if (GET_MODE_BITSIZE (mode) <= count)
3404 /* Find out the target CPU. */
3407 else if (TARGET_H8300H)
3412 /* Find the shift algorithm. */
3416 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3417 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3418 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3422 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3423 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3424 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3428 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3429 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3430 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3437 /* On H8/300H, count == 8 uses a scratch register. */
3438 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3439 || (TARGET_H8300H && mode == SImode && count == 8));
3442 /* Emit the assembler code for doing shifts. */
3445 output_a_shift (rtx *operands)
3447 static int loopend_lab;
3448 rtx shift = operands[3];
3449 enum machine_mode mode = GET_MODE (shift);
3450 enum rtx_code code = GET_CODE (shift);
3451 enum shift_type shift_type;
3452 enum shift_mode shift_mode;
3453 struct shift_info info;
3460 shift_mode = QIshift;
3463 shift_mode = HIshift;
3466 shift_mode = SIshift;
3475 shift_type = SHIFT_ASHIFTRT;
3478 shift_type = SHIFT_LSHIFTRT;
3481 shift_type = SHIFT_ASHIFT;
3487 if (GET_CODE (operands[2]) != CONST_INT)
3489 /* This case must be taken care of by one of the two splitters
3490 that convert a variable shift into a loop. */
3495 int n = INTVAL (operands[2]);
3497 /* If the count is negative, make it 0. */
3500 /* If the count is too big, truncate it.
3501 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3502 do the intuitive thing. */
3503 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3504 n = GET_MODE_BITSIZE (mode);
3506 get_shift_alg (shift_type, shift_mode, n, &info);
3511 output_asm_insn (info.special, operands);
3517 /* Emit two bit shifts first. */
3518 if (info.shift2 != NULL)
3520 for (; n > 1; n -= 2)
3521 output_asm_insn (info.shift2, operands);
3524 /* Now emit one bit shifts for any residual. */
3526 output_asm_insn (info.shift1, operands);
3531 int m = GET_MODE_BITSIZE (mode) - n;
3532 const int mask = (shift_type == SHIFT_ASHIFT
3533 ? ((1 << m) - 1) << n
3537 /* Not all possibilities of rotate are supported. They shouldn't
3538 be generated, but let's watch for 'em. */
3539 if (info.shift1 == 0)
3542 /* Emit two bit rotates first. */
3543 if (info.shift2 != NULL)
3545 for (; m > 1; m -= 2)
3546 output_asm_insn (info.shift2, operands);
3549 /* Now single bit rotates for any residual. */
3551 output_asm_insn (info.shift1, operands);
3553 /* Now mask off the high bits. */
3555 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3556 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3557 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3561 output_asm_insn (insn_buf, operands);
3566 /* A loop to shift by a "large" constant value.
3567 If we have shift-by-2 insns, use them. */
3568 if (info.shift2 != NULL)
3570 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3571 names_big[REGNO (operands[4])]);
3572 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3573 output_asm_insn (info.shift2, operands);
3574 output_asm_insn ("add #0xff,%X4", operands);
3575 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3577 output_asm_insn (info.shift1, operands);
3581 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3582 names_big[REGNO (operands[4])]);
3583 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3584 output_asm_insn (info.shift1, operands);
3585 output_asm_insn ("add #0xff,%X4", operands);
3586 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3597 h8300_asm_insn_count (const char *template)
3599 unsigned int count = 1;
3601 for (; *template; template++)
3602 if (*template == '\n')
3609 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3611 rtx shift = operands[3];
3612 enum machine_mode mode = GET_MODE (shift);
3613 enum rtx_code code = GET_CODE (shift);
3614 enum shift_type shift_type;
3615 enum shift_mode shift_mode;
3616 struct shift_info info;
3617 unsigned int wlength = 0;
3622 shift_mode = QIshift;
3625 shift_mode = HIshift;
3628 shift_mode = SIshift;
3637 shift_type = SHIFT_ASHIFTRT;
3640 shift_type = SHIFT_LSHIFTRT;
3643 shift_type = SHIFT_ASHIFT;
3649 if (GET_CODE (operands[2]) != CONST_INT)
3651 /* Get the assembler code to do one shift. */
3652 get_shift_alg (shift_type, shift_mode, 1, &info);
3654 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3658 int n = INTVAL (operands[2]);
3660 /* If the count is negative, make it 0. */
3663 /* If the count is too big, truncate it.
3664 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3665 do the intuitive thing. */
3666 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3667 n = GET_MODE_BITSIZE (mode);
3669 get_shift_alg (shift_type, shift_mode, n, &info);
3674 wlength += h8300_asm_insn_count (info.special);
3676 /* Every assembly instruction used in SHIFT_SPECIAL case
3677 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3678 see xor.l, we just pretend that xor.l counts as two insns
3679 so that the insn length will be computed correctly. */
3680 if (strstr (info.special, "xor.l") != NULL)
3688 if (info.shift2 != NULL)
3690 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3694 wlength += h8300_asm_insn_count (info.shift1) * n;
3700 int m = GET_MODE_BITSIZE (mode) - n;
3702 /* Not all possibilities of rotate are supported. They shouldn't
3703 be generated, but let's watch for 'em. */
3704 if (info.shift1 == 0)
3707 if (info.shift2 != NULL)
3709 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3713 wlength += h8300_asm_insn_count (info.shift1) * m;
3715 /* Now mask off the high bits. */
3736 /* A loop to shift by a "large" constant value.
3737 If we have shift-by-2 insns, use them. */
3738 if (info.shift2 != NULL)
3740 wlength += 3 + h8300_asm_insn_count (info.shift2);
3742 wlength += h8300_asm_insn_count (info.shift1);
3746 wlength += 3 + h8300_asm_insn_count (info.shift1);
3757 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
3759 rtx shift = operands[3];
3760 enum machine_mode mode = GET_MODE (shift);
3761 enum rtx_code code = GET_CODE (shift);
3762 enum shift_type shift_type;
3763 enum shift_mode shift_mode;
3764 struct shift_info info;
3769 shift_mode = QIshift;
3772 shift_mode = HIshift;
3775 shift_mode = SIshift;
3784 shift_type = SHIFT_ASHIFTRT;
3787 shift_type = SHIFT_LSHIFTRT;
3790 shift_type = SHIFT_ASHIFT;
3796 if (GET_CODE (operands[2]) != CONST_INT)
3798 /* This case must be taken care of by one of the two splitters
3799 that convert a variable shift into a loop. */
3804 int n = INTVAL (operands[2]);
3806 /* If the count is negative, make it 0. */
3809 /* If the count is too big, truncate it.
3810 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3811 do the intuitive thing. */
3812 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3813 n = GET_MODE_BITSIZE (mode);
3815 get_shift_alg (shift_type, shift_mode, n, &info);
3820 if (info.remainder == 0)
3821 return info.cc_special;
3826 return info.cc_inline;
3829 /* This case always ends with an and instruction. */
3833 /* A loop to shift by a "large" constant value.
3834 If we have shift-by-2 insns, use them. */
3835 if (info.shift2 != NULL)
3838 return info.cc_inline;
3848 /* A rotation by a non-constant will cause a loop to be generated, in
3849 which a rotation by one bit is used. A rotation by a constant,
3850 including the one in the loop, will be taken care of by
3851 output_a_rotate () at the insn emit time. */
3854 expand_a_rotate (enum rtx_code code, rtx operands[])
3856 rtx dst = operands[0];
3857 rtx src = operands[1];
3858 rtx rotate_amount = operands[2];
3859 enum machine_mode mode = GET_MODE (dst);
3862 /* We rotate in place. */
3863 emit_move_insn (dst, src);
3865 if (GET_CODE (rotate_amount) != CONST_INT)
3867 rtx counter = gen_reg_rtx (QImode);
3868 rtx start_label = gen_label_rtx ();
3869 rtx end_label = gen_label_rtx ();
3871 /* If the rotate amount is less than or equal to 0,
3872 we go out of the loop. */
3873 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
3874 QImode, 0, end_label);
3876 /* Initialize the loop counter. */
3877 emit_move_insn (counter, rotate_amount);
3879 emit_label (start_label);
3881 /* Rotate by one bit. */
3882 tmp = gen_rtx_fmt_ee (code, mode, dst, const1_rtx);
3883 emit_insn (gen_rtx_SET (mode, dst, tmp));
3885 /* Decrement the counter by 1. */
3886 tmp = gen_rtx_PLUS (QImode, counter, constm1_rtx);
3887 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3889 /* If the loop counter is nonzero, we go back to the beginning
3891 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
3894 emit_label (end_label);
3898 /* Rotate by AMOUNT bits. */
3899 tmp = gen_rtx_fmt_ee (code, mode, dst, rotate_amount);
3900 emit_insn (gen_rtx_SET (mode, dst, tmp));
3906 /* Output rotate insns. */
3909 output_a_rotate (enum rtx_code code, rtx *operands)
3911 rtx dst = operands[0];
3912 rtx rotate_amount = operands[2];
3913 enum shift_mode rotate_mode;
3914 enum shift_type rotate_type;
3915 const char *insn_buf;
3918 enum machine_mode mode = GET_MODE (dst);
3920 if (GET_CODE (rotate_amount) != CONST_INT)
3926 rotate_mode = QIshift;
3929 rotate_mode = HIshift;
3932 rotate_mode = SIshift;
3941 rotate_type = SHIFT_ASHIFT;
3944 rotate_type = SHIFT_LSHIFTRT;
3950 amount = INTVAL (rotate_amount);
3952 /* Clean up AMOUNT. */
3955 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3956 amount = GET_MODE_BITSIZE (mode);
3958 /* Determine the faster direction. After this phase, amount will be
3959 at most a half of GET_MODE_BITSIZE (mode). */
3960 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3962 /* Flip the direction. */
3963 amount = GET_MODE_BITSIZE (mode) - amount;
3965 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3968 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3969 boost up the rotation. */
3970 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3971 || (mode == HImode && TARGET_H8300H && amount >= 6)
3972 || (mode == HImode && TARGET_H8300S && amount == 8)
3973 || (mode == SImode && TARGET_H8300H && amount >= 10)
3974 || (mode == SImode && TARGET_H8300S && amount >= 13))
3979 /* This code works on any family. */
3980 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3981 output_asm_insn (insn_buf, operands);
3985 /* This code works on the H8/300H and H8S. */
3986 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3987 output_asm_insn (insn_buf, operands);
3994 /* Adjust AMOUNT and flip the direction. */
3995 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3997 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
4000 /* Emit rotate insns. */
4001 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
4004 insn_buf = rotate_two[rotate_type][rotate_mode];
4006 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
4008 for (; amount >= bits; amount -= bits)
4009 output_asm_insn (insn_buf, operands);
4016 compute_a_rotate_length (rtx *operands)
4018 rtx src = operands[1];
4019 rtx amount_rtx = operands[2];
4020 enum machine_mode mode = GET_MODE (src);
4022 unsigned int length = 0;
4024 if (GET_CODE (amount_rtx) != CONST_INT)
4027 amount = INTVAL (amount_rtx);
4029 /* Clean up AMOUNT. */
4032 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4033 amount = GET_MODE_BITSIZE (mode);
4035 /* Determine the faster direction. After this phase, amount
4036 will be at most a half of GET_MODE_BITSIZE (mode). */
4037 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4038 /* Flip the direction. */
4039 amount = GET_MODE_BITSIZE (mode) - amount;
4041 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4042 boost up the rotation. */
4043 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4044 || (mode == HImode && TARGET_H8300H && amount >= 6)
4045 || (mode == HImode && TARGET_H8300S && amount == 8)
4046 || (mode == SImode && TARGET_H8300H && amount >= 10)
4047 || (mode == SImode && TARGET_H8300S && amount >= 13))
4049 /* Adjust AMOUNT and flip the direction. */
4050 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4054 /* We use 2-bit rotations on the H8S. */
4056 amount = amount / 2 + amount % 2;
4058 /* The H8/300 uses three insns to rotate one bit, taking 6
4060 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4065 /* Fix the operands of a gen_xxx so that it could become a bit
4069 fix_bit_operand (rtx *operands, int what, enum rtx_code type)
4071 /* The bit_operand predicate accepts any memory during RTL generation, but
4072 only 'U' memory afterwards, so if this is a MEM operand, we must force
4073 it to be valid for 'U' by reloading the address. */
4075 if ((what == 0 && single_zero_operand (operands[2], QImode))
4076 || (what == 1 && single_one_operand (operands[2], QImode)))
4078 /* OK to have a memory dest. */
4079 if (GET_CODE (operands[0]) == MEM
4080 && !EXTRA_CONSTRAINT (operands[0], 'U'))
4082 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
4083 copy_to_mode_reg (Pmode,
4084 XEXP (operands[0], 0)));
4085 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4089 if (GET_CODE (operands[1]) == MEM
4090 && !EXTRA_CONSTRAINT (operands[1], 'U'))
4092 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
4093 copy_to_mode_reg (Pmode,
4094 XEXP (operands[1], 0)));
4095 MEM_COPY_ATTRIBUTES (mem, operands[0]);
4101 /* Dest and src op must be register. */
4103 operands[1] = force_reg (QImode, operands[1]);
4105 rtx res = gen_reg_rtx (QImode);
4106 emit_insn (gen_rtx_SET (VOIDmode, res,
4107 gen_rtx_fmt_ee (type, QImode,
4108 operands[1], operands[2])));
4109 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
4114 /* Return nonzero if FUNC is an interrupt function as specified
4115 by the "interrupt" attribute. */
4118 h8300_interrupt_function_p (tree func)
4122 if (TREE_CODE (func) != FUNCTION_DECL)
4125 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
4126 return a != NULL_TREE;
4129 /* Return nonzero if FUNC is a saveall function as specified by the
4130 "saveall" attribute. */
4133 h8300_saveall_function_p (tree func)
4137 if (TREE_CODE (func) != FUNCTION_DECL)
4140 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
4141 return a != NULL_TREE;
4144 /* Return nonzero if FUNC is an OS_Task function as specified
4145 by the "OS_Task" attribute. */
4148 h8300_os_task_function_p (tree func)
4152 if (TREE_CODE (func) != FUNCTION_DECL)
4155 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
4156 return a != NULL_TREE;
4159 /* Return nonzero if FUNC is a monitor function as specified
4160 by the "monitor" attribute. */
4163 h8300_monitor_function_p (tree func)
4167 if (TREE_CODE (func) != FUNCTION_DECL)
4170 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4171 return a != NULL_TREE;
4174 /* Return nonzero if FUNC is a function that should be called
4175 through the function vector. */
4178 h8300_funcvec_function_p (tree func)
4182 if (TREE_CODE (func) != FUNCTION_DECL)
4185 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4186 return a != NULL_TREE;
4189 /* Return nonzero if DECL is a variable that's in the eight bit
4193 h8300_eightbit_data_p (tree decl)
4197 if (TREE_CODE (decl) != VAR_DECL)
4200 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4201 return a != NULL_TREE;
4204 /* Return nonzero if DECL is a variable that's in the tiny
4208 h8300_tiny_data_p (tree decl)
4212 if (TREE_CODE (decl) != VAR_DECL)
4215 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4216 return a != NULL_TREE;
4219 /* Generate an 'interrupt_handler' attribute for decls. We convert
4220 all the pragmas to corresponding attributes. */
4223 h8300_insert_attributes (tree node, tree *attributes)
4225 if (TREE_CODE (node) == FUNCTION_DECL)
4227 if (pragma_interrupt)
4229 pragma_interrupt = 0;
4231 /* Add an 'interrupt_handler' attribute. */
4232 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4240 /* Add an 'saveall' attribute. */
4241 *attributes = tree_cons (get_identifier ("saveall"),
4247 /* Supported attributes:
4249 interrupt_handler: output a prologue and epilogue suitable for an
4252 saveall: output a prologue and epilogue that saves and restores
4253 all registers except the stack pointer.
4255 function_vector: This function should be called through the
4258 eightbit_data: This variable lives in the 8-bit data area and can
4259 be referenced with 8-bit absolute memory addresses.
4261 tiny_data: This variable lives in the tiny data area and can be
4262 referenced with 16-bit absolute memory references. */
4264 const struct attribute_spec h8300_attribute_table[] =
4266 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4267 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4268 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4269 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4270 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4271 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4272 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4273 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4274 { NULL, 0, 0, false, false, false, NULL }
4278 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4279 struct attribute_spec.handler. */
4281 h8300_handle_fndecl_attribute (tree *node, tree name,
4282 tree args ATTRIBUTE_UNUSED,
4283 int flags ATTRIBUTE_UNUSED,
4286 if (TREE_CODE (*node) != FUNCTION_DECL)
4288 warning ("`%s' attribute only applies to functions",
4289 IDENTIFIER_POINTER (name));
4290 *no_add_attrs = true;
4296 /* Handle an "eightbit_data" attribute; arguments as in
4297 struct attribute_spec.handler. */
4299 h8300_handle_eightbit_data_attribute (tree *node, tree name,
4300 tree args ATTRIBUTE_UNUSED,
4301 int flags ATTRIBUTE_UNUSED,
4306 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4308 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4312 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4313 *no_add_attrs = true;
4319 /* Handle an "tiny_data" attribute; arguments as in
4320 struct attribute_spec.handler. */
4322 h8300_handle_tiny_data_attribute (tree *node, tree name,
4323 tree args ATTRIBUTE_UNUSED,
4324 int flags ATTRIBUTE_UNUSED,
4329 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4331 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4335 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4336 *no_add_attrs = true;
4342 /* Mark function vectors, and various small data objects. */
4345 h8300_encode_section_info (tree decl, rtx rtl, int first)
4347 int extra_flags = 0;
4349 default_encode_section_info (decl, rtl, first);
4351 if (TREE_CODE (decl) == FUNCTION_DECL
4352 && h8300_funcvec_function_p (decl))
4353 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4354 else if (TREE_CODE (decl) == VAR_DECL
4355 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4357 if (h8300_eightbit_data_p (decl))
4358 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4359 else if (first && h8300_tiny_data_p (decl))
4360 extra_flags = SYMBOL_FLAG_TINY_DATA;
4364 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4368 output_simode_bld (int bild, rtx operands[])
4372 /* Clear the destination register. */
4373 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4375 /* Now output the bit load or bit inverse load, and store it in
4378 output_asm_insn ("bild\t%Z2,%Y1", operands);
4380 output_asm_insn ("bld\t%Z2,%Y1", operands);
4382 output_asm_insn ("bst\t#0,%w0", operands);
4386 /* Determine if we can clear the destination first. */
4387 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4388 && REGNO (operands[0]) != REGNO (operands[1]));
4391 output_asm_insn ("sub.l\t%S0,%S0", operands);
4393 /* Output the bit load or bit inverse load. */
4395 output_asm_insn ("bild\t%Z2,%Y1", operands);
4397 output_asm_insn ("bld\t%Z2,%Y1", operands);
4400 output_asm_insn ("xor.l\t%S0,%S0", operands);
4402 /* Perform the bit store. */
4403 output_asm_insn ("rotxl.l\t%S0", operands);
4410 #ifndef OBJECT_FORMAT_ELF
4412 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED)
4414 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4415 fprintf (asm_out_file, "\t.section %s\n", name);
4417 #endif /* ! OBJECT_FORMAT_ELF */
4419 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4420 which is a special case of the 'R' operand. */
4423 h8300_eightbit_constant_address_p (rtx x)
4425 /* The ranges of the 8-bit area. */
4426 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4427 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4428 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4429 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4430 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4431 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4433 unsigned HOST_WIDE_INT addr;
4435 /* We accept symbols declared with eightbit_data. */
4436 if (GET_CODE (x) == SYMBOL_REF)
4437 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4439 if (GET_CODE (x) != CONST_INT)
4445 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4446 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4447 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4450 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4451 on H8/300H and H8S. */
4454 h8300_tiny_constant_address_p (rtx x)
4456 /* The ranges of the 16-bit area. */
4457 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4458 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4459 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4460 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4461 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4462 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4463 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4464 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4466 unsigned HOST_WIDE_INT addr;
4468 switch (GET_CODE (x))
4471 /* In the normal mode, any symbol fits in the 16-bit absolute
4472 address range. We also accept symbols declared with
4474 return (TARGET_NORMAL_MODE
4475 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
4479 return (TARGET_NORMAL_MODE
4481 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4483 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4486 return TARGET_NORMAL_MODE;
4495 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
4497 HOST_WIDE_INT offset1, offset2;
4505 else if (GET_CODE (addr1) == PLUS
4506 && REG_P (XEXP (addr1, 0))
4507 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4509 reg1 = XEXP (addr1, 0);
4510 offset1 = INTVAL (XEXP (addr1, 1));
4520 else if (GET_CODE (addr2) == PLUS
4521 && REG_P (XEXP (addr2, 0))
4522 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4524 reg2 = XEXP (addr2, 0);
4525 offset2 = INTVAL (XEXP (addr2, 1));
4530 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4531 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4533 && offset1 + 1 == offset2)
4539 /* Return nonzero if we have the same comparison insn as I3 two insns
4540 before I3. I3 is assumed to be a comparison insn. */
4543 same_cmp_preceding_p (rtx i3)
4547 /* Make sure we have a sequence of three insns. */
4548 i2 = prev_nonnote_insn (i3);
4551 i1 = prev_nonnote_insn (i2);
4555 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4556 && any_condjump_p (i2) && onlyjump_p (i2));
4559 /* Return nonzero if we have the same comparison insn as I1 two insns
4560 after I1. I1 is assumed to be a comparison insn. */
4563 same_cmp_following_p (rtx i1)
4567 /* Make sure we have a sequence of three insns. */
4568 i2 = next_nonnote_insn (i1);
4571 i3 = next_nonnote_insn (i2);
4575 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
4576 && any_condjump_p (i2) && onlyjump_p (i2));
4579 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
4582 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4583 unsigned int new_reg)
4585 /* Interrupt functions can only use registers that have already been
4586 saved by the prologue, even if they would normally be
4589 if (h8300_current_function_interrupt_function_p ()
4590 && !regs_ever_live[new_reg])
4596 /* Return nonzero if X is a legitimate constant. */
4599 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
4604 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
4607 h8300_rtx_ok_for_base_p (rtx x, int strict)
4609 /* Strip off SUBREG if any. */
4610 if (GET_CODE (x) == SUBREG)
4615 ? REG_OK_FOR_BASE_STRICT_P (x)
4616 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
4619 /* Return nozero if X is a legitimate address. On the H8/300, a
4620 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
4621 CONSTANT_ADDRESS. */
4624 h8300_legitimate_address_p (rtx x, int strict)
4626 /* The register indirect addresses like @er0 is always valid. */
4627 if (h8300_rtx_ok_for_base_p (x, strict))
4630 if (CONSTANT_ADDRESS_P (x))
4633 if (GET_CODE (x) == PLUS
4634 && CONSTANT_ADDRESS_P (XEXP (x, 1))
4635 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
4641 /* Perform target dependent optabs initialization. */
4643 h8300_init_libfuncs (void)
4645 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
4646 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
4647 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
4648 set_optab_libfunc (smod_optab, HImode, "__modhi3");
4649 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
4653 h8300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4655 return (TYPE_MODE (type) == BLKmode
4656 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
4659 /* Initialize the GCC target structure. */
4660 #undef TARGET_ATTRIBUTE_TABLE
4661 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
4663 #undef TARGET_ASM_ALIGNED_HI_OP
4664 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
4666 #undef TARGET_ASM_FILE_START
4667 #define TARGET_ASM_FILE_START h8300_file_start
4668 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
4669 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
4671 #undef TARGET_ASM_FILE_END
4672 #define TARGET_ASM_FILE_END h8300_file_end
4674 #undef TARGET_ENCODE_SECTION_INFO
4675 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
4677 #undef TARGET_INSERT_ATTRIBUTES
4678 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
4680 #undef TARGET_RTX_COSTS
4681 #define TARGET_RTX_COSTS h8300_rtx_costs
4683 #undef TARGET_INIT_LIBFUNCS
4684 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
4686 #undef TARGET_RETURN_IN_MEMORY
4687 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
4689 struct gcc_target targetm = TARGET_INITIALIZER;