1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "target-def.h"
46 /* Forward declarations. */
47 static int h8300_interrupt_function_p PARAMS ((tree));
48 static int h8300_monitor_function_p PARAMS ((tree));
49 static int h8300_os_task_function_p PARAMS ((tree));
50 static void dosize PARAMS ((FILE *, const char *, unsigned int));
51 static int round_frame_size PARAMS ((int));
52 static unsigned int compute_saved_regs PARAMS ((void));
53 static void push PARAMS ((FILE *, int));
54 static void pop PARAMS ((FILE *, int));
55 static const char *cond_string PARAMS ((enum rtx_code));
56 static int h8300_valid_decl_attribute PARAMS ((tree, tree, tree, tree));
57 static void h8300_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
58 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
60 /* CPU_TYPE, says what cpu we're compiling for. */
63 /* True if the current function is an interrupt handler
64 (either via #pragma or an attribute specification). */
65 int interrupt_handler;
67 /* True if the current function is an OS Task
68 (via an attribute specification). */
71 /* True if the current function is a monitor
72 (via an attribute specification). */
75 /* True if a #pragma saveall has been seen for the current function. */
78 static const char *const names_big[] =
79 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
81 static const char *const names_extended[] =
82 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
84 static const char *const names_upper_extended[] =
85 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
87 /* Points to one of the above. */
88 /* ??? The above could be put in an array indexed by CPU_TYPE. */
89 const char * const *h8_reg_names;
91 /* Various operations needed by the following, indexed by CPU_TYPE. */
93 static const char *const h8_push_ops[2] = { "push", "push.l" };
94 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
95 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
97 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
99 /* Initialize the GCC target structure. */
100 #undef TARGET_VALID_DECL_ATTRIBUTE
101 #define TARGET_VALID_DECL_ATTRIBUTE h8300_valid_decl_attribute
103 #undef TARGET_ASM_FUNCTION_PROLOGUE
104 #define TARGET_ASM_FUNCTION_PROLOGUE h8300_output_function_prologue
105 #undef TARGET_ASM_FUNCTION_EPILOGUE
106 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
108 struct gcc_target targetm = TARGET_INITIALIZER;
110 /* Initialize various cpu specific globals at start up. */
117 cpu_type = (int) CPU_H8300;
118 h8_reg_names = names_big;
122 /* For this we treat the H8/300H and H8/S the same. */
123 cpu_type = (int) CPU_H8300H;
124 h8_reg_names = names_extended;
126 h8_push_op = h8_push_ops[cpu_type];
127 h8_pop_op = h8_pop_ops[cpu_type];
128 h8_mov_op = h8_mov_ops[cpu_type];
130 if (!TARGET_H8300S && TARGET_MAC)
132 error ("-ms2600 is used without -ms.");
142 static const char *const names_small[] =
143 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
144 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
146 return names_small[REGNO (x) * 2 + b];
149 /* REGNO must be saved/restored across calls if this macro is true. */
151 #define WORD_REG_USED(regno) \
153 /* No need to save registers if this function will not return. */\
154 && ! TREE_THIS_VOLATILE (current_function_decl) \
156 /* Save any call saved register that was used. */ \
157 || (regs_ever_live[regno] && !call_used_regs[regno]) \
158 /* Save the frame pointer if it was used. */ \
159 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
160 /* Save any register used in an interrupt handler. */ \
161 || (interrupt_handler && regs_ever_live[regno]) \
162 /* Save call clobbered registers in non-leaf interrupt \
164 || (interrupt_handler \
165 && call_used_regs[regno] \
166 && !current_function_is_leaf)))
168 /* Output assembly language to FILE for the operation OP with operand size
169 SIZE to adjust the stack pointer. */
172 dosize (file, op, size)
177 /* On the H8/300H and H8/S, for sizes <= 8 bytes, it is as good or
178 better to use adds/subs insns rather than add.l/sub.l with an
181 Also, on the H8/300, if we don't have a temporary to hold the
182 size of the frame in the prologue, we simply emit a sequence of
183 subs since this shouldn't happen often. */
184 if ((TARGET_H8300 && size <= 4)
185 || ((TARGET_H8300H || TARGET_H8300S) && size <= 8)
186 || (TARGET_H8300 && current_function_needs_context
187 && strcmp (op, "sub")))
189 unsigned HOST_WIDE_INT amount;
191 /* Try different amounts in descending order. */
192 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
196 for (; size >= amount; size -= amount)
197 fprintf (file, "\t%ss\t#%d,sp\n", op, amount);
203 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
205 fprintf (file, "\t%s.l\t#%d,sp\n", op, size);
209 /* Round up frame size SIZE. */
212 round_frame_size (size)
215 return (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
218 /* Compute which registers to push/pop.
219 Return a bit vector of registers. */
222 compute_saved_regs ()
224 unsigned int saved_regs = 0;
227 /* Construct a bit vector of registers to be pushed/popped. */
228 for (regno = 0; regno <= 6; regno++)
230 if (WORD_REG_USED (regno))
231 saved_regs |= 1 << regno;
234 /* Don't push/pop the frame pointer as it is treated separately. */
235 if (frame_pointer_needed)
236 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
241 /* Output assembly language code to push register RN. */
248 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[rn]);
251 /* Output assembly language code to pop register RN. */
258 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[rn]);
261 /* This is what the stack looks like after the prolog of
262 a function with a frame has been set up:
268 <saved registers> <- sp
270 This is what the stack looks like after the prolog of
271 a function which doesn't have a frame:
276 <saved registers> <- sp
279 /* Output assembly language code for the function prologue. */
282 h8300_output_function_prologue (file, size)
286 int fsize = round_frame_size (size);
291 /* Note a function with the interrupt attribute and set interrupt_handler
293 if (h8300_interrupt_function_p (current_function_decl))
294 interrupt_handler = 1;
296 /* If the current function has the OS_Task attribute set, then
297 we have a naked prologue. */
298 if (h8300_os_task_function_p (current_function_decl))
300 fprintf (file, ";OS_Task prologue\n");
305 if (h8300_monitor_function_p (current_function_decl))
307 /* My understanding of monitor functions is they act just
308 like interrupt functions, except the prologue must
310 fprintf (file, ";monitor prologue\n");
311 interrupt_handler = 1;
315 fprintf (file, "\tsubs\t#2,sp\n");
317 fprintf (file, "\tstc\tccr,r0l\n");
318 fprintf (file, "\tmov.b\tr0l,@(2,sp)\n");
320 fprintf (file, "\torc\t#128,ccr\n");
322 else if (TARGET_H8300H)
325 fprintf (file, "\tstc\tccr,r0l\n");
326 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
328 fprintf (file, "\torc\t#128,ccr\n");
330 else if (TARGET_H8300S)
332 fprintf (file, "\tstc\texr,@-sp\n");
334 fprintf (file, "\tstc\tccr,r0l\n");
335 fprintf (file, "\tmov.b\tr0l,@(6,sp)\n");
337 fprintf (file, "\torc\t#128,ccr\n");
343 if (frame_pointer_needed)
346 push (file, FRAME_POINTER_REGNUM);
347 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
348 h8_reg_names[STACK_POINTER_REGNUM],
349 h8_reg_names[FRAME_POINTER_REGNUM]);
352 /* Leave room for locals. */
353 dosize (file, "sub", fsize);
355 /* Push the rest of the registers in ascending order. */
356 saved_regs = compute_saved_regs ();
357 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
362 if (saved_regs & (1 << regno))
366 /* See how many registers we can push at the same time. */
367 if ((regno == 0 || regno == 4)
368 && ((saved_regs >> regno) & 0x0f) == 0x0f)
371 else if ((regno == 0 || regno == 4)
372 && ((saved_regs >> regno) & 0x07) == 0x07)
375 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
376 && ((saved_regs >> regno) & 0x03) == 0x03)
383 fprintf (file, "\tstm.l\t%s-%s,@-sp\n",
385 h8_reg_names[regno + (n_regs - 1)]);
390 /* Output assembly language code for the function epilogue. */
393 h8300_output_function_epilogue (file, size)
397 int fsize = round_frame_size (size);
399 rtx insn = get_last_insn ();
405 /* OS_Task epilogues are nearly naked -- they just have an
407 fprintf (file, ";OS_task epilogue\n");
408 fprintf (file, "\trts\n");
412 /* Monitor epilogues are the same as interrupt function epilogues.
413 Just make a note that we're in an monitor epilogue. */
415 fprintf (file, ";monitor epilogue\n");
417 /* If the last insn was a BARRIER, we don't have to write any code. */
418 if (GET_CODE (insn) == NOTE)
419 insn = prev_nonnote_insn (insn);
420 if (insn && GET_CODE (insn) == BARRIER)
423 /* Pop the saved registers in descending order. */
424 saved_regs = compute_saved_regs ();
425 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
427 int regno = (FIRST_PSEUDO_REGISTER - 1) - idx;
430 if (saved_regs & (1 << regno))
434 /* See how many registers we can pop at the same time. */
435 if ((regno == 7 || regno == 3)
436 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
439 else if ((regno == 6 || regno == 2)
440 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
443 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
444 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
451 fprintf (file, "\tldm.l\t@sp+,%s-%s\n",
452 h8_reg_names[regno - (n_regs - 1)],
453 h8_reg_names[regno]);
457 /* Deallocate locals. */
458 dosize (file, "add", fsize);
460 /* Pop frame pointer if we had one. */
461 if (frame_pointer_needed)
462 pop (file, FRAME_POINTER_REGNUM);
464 if (interrupt_handler)
465 fprintf (file, "\trte\n");
467 fprintf (file, "\trts\n");
470 interrupt_handler = 0;
476 /* Output assembly code for the start of the file. */
479 asm_file_start (file)
482 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
483 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
485 fprintf (file, "; -O%d\n", optimize);
487 fprintf (file, "\n\t.h8300h\n");
488 else if (TARGET_H8300S)
489 fprintf (file, "\n\t.h8300s\n");
491 fprintf (file, "\n\n");
492 output_file_directive (file, main_input_filename);
495 /* Output assembly language code for the end of file. */
501 fprintf (file, "\t.end\n");
504 /* Return true if VALUE is a valid constant for constraint 'P'.
505 IE: VALUE is a power of two <= 2**15. */
508 small_power_of_two (value)
511 int power = exact_log2 (value);
512 return power >= 0 && power <= 15;
515 /* Return true if VALUE is a valid constant for constraint 'O', which
516 means that the constant would be ok to use as a bit for a bclr
523 return small_power_of_two ((~value) & 0xff);
526 /* Return true if OP is a valid source operand for an integer move
530 general_operand_src (op, mode)
532 enum machine_mode mode;
534 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
536 return general_operand (op, mode);
539 /* Return true if OP is a valid destination operand for an integer move
543 general_operand_dst (op, mode)
545 enum machine_mode mode;
547 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
549 return general_operand (op, mode);
552 /* Return true if OP is a const valid for a bit clear instruction. */
555 o_operand (operand, mode)
557 enum machine_mode mode ATTRIBUTE_UNUSED;
559 return (GET_CODE (operand) == CONST_INT
560 && CONST_OK_FOR_O (INTVAL (operand)));
563 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
566 p_operand (operand, mode)
568 enum machine_mode mode ATTRIBUTE_UNUSED;
570 return (GET_CODE (operand) == CONST_INT
571 && CONST_OK_FOR_P (INTVAL (operand)));
574 /* Return true if OP is a valid call operand. */
577 call_insn_operand (op, mode)
579 enum machine_mode mode ATTRIBUTE_UNUSED;
581 if (GET_CODE (op) == MEM)
583 rtx inside = XEXP (op, 0);
584 if (register_operand (inside, Pmode))
586 if (CONSTANT_ADDRESS_P (inside))
592 /* Return 1 if an addition/subtraction of a constant integer can be
593 transformed into two consecutive adds/subs that are faster than the
594 straightforward way. Otherwise, return 0. */
597 two_insn_adds_subs_operand (op, mode)
599 enum machine_mode mode;
601 if (GET_CODE (op) == CONST_INT)
603 HOST_WIDE_INT value = INTVAL (op);
605 /* Force VALUE to be positive so that we do not have to consider
606 the negative case. */
609 if (TARGET_H8300H || TARGET_H8300S)
611 /* A constant addition/subtraction takes 2 states in QImode,
612 4 states in HImode, and 6 states in SImode. Thus, the
613 only case we can win is when SImode is used, in which
614 case, two adds/subs are used, taking 4 states. */
624 /* A constant addition/subtraction takes 2 states in
625 QImode. It takes 6 states in HImode, requiring the
626 constant to be loaded to a register first, and a lot more
627 in SImode. Thus the only case we can win is when either
628 HImode or SImode is used. */
639 /* Split an add of a small constant into two adds/subs insns. */
642 split_adds_subs (mode, operands)
643 enum machine_mode mode;
646 HOST_WIDE_INT val = INTVAL (operands[1]);
647 rtx reg = operands[0];
648 HOST_WIDE_INT sign = 1;
649 HOST_WIDE_INT amount;
651 /* Force VAL to be positive so that we do not have to consider the
659 /* Try different amounts in descending order. */
660 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
664 for (; val >= amount; val -= amount)
666 rtx tmp = gen_rtx_PLUS (mode, reg, GEN_INT (sign * amount));
667 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
674 /* Return true if OP is a valid call operand, and OP represents
675 an operand for a small call (4 bytes instead of 6 bytes). */
678 small_call_insn_operand (op, mode)
680 enum machine_mode mode ATTRIBUTE_UNUSED;
682 if (GET_CODE (op) == MEM)
684 rtx inside = XEXP (op, 0);
686 /* Register indirect is a small call. */
687 if (register_operand (inside, Pmode))
690 /* A call through the function vector is a small
692 if (GET_CODE (inside) == SYMBOL_REF
693 && SYMBOL_REF_FLAG (inside))
696 /* Otherwise it's a large call. */
700 /* Return true if OP is a valid jump operand. */
703 jump_address_operand (op, mode)
705 enum machine_mode mode;
707 if (GET_CODE (op) == REG)
708 return mode == Pmode;
710 if (GET_CODE (op) == MEM)
712 rtx inside = XEXP (op, 0);
713 if (register_operand (inside, Pmode))
715 if (CONSTANT_ADDRESS_P (inside))
721 /* Recognize valid operands for bitfield instructions. */
723 extern int rtx_equal_function_value_matters;
726 bit_operand (op, mode)
728 enum machine_mode mode;
730 /* We can except any general operand, expept that MEM operands must
731 be limited to those that use addresses valid for the 'U' constraint. */
732 if (!general_operand (op, mode))
735 /* Accept any mem during RTL generation. Otherwise, the code that does
736 insv and extzv will think that we can not handle memory. However,
737 to avoid reload problems, we only accept 'U' MEM operands after RTL
738 generation. This means that any named pattern which uses this predicate
739 must force its operands to match 'U' before emitting RTL. */
741 if (GET_CODE (op) == REG)
743 if (GET_CODE (op) == SUBREG)
745 if (!rtx_equal_function_value_matters)
746 /* We're building rtl. */
747 return GET_CODE (op) == MEM;
749 return (GET_CODE (op) == MEM
750 && EXTRA_CONSTRAINT (op, 'U'));
754 bit_memory_operand (op, mode)
756 enum machine_mode mode ATTRIBUTE_UNUSED;
758 return (GET_CODE (op) == MEM
759 && EXTRA_CONSTRAINT (op, 'U'));
762 /* Recognize valid operators for bit test. */
765 eq_operator (x, mode)
767 enum machine_mode mode ATTRIBUTE_UNUSED;
769 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
772 /* Handle machine specific pragmas for compatibility with existing
773 compilers for the H8/300.
775 pragma saveall generates prolog/epilog code which saves and
776 restores all the registers on function entry.
778 pragma interrupt saves and restores all registers, and exits with
779 an rte instruction rather than an rts. A pointer to a function
780 with this attribute may be safely used in an interrupt vector. */
783 h8300_pr_interrupt (pfile)
784 cpp_reader *pfile ATTRIBUTE_UNUSED;
786 interrupt_handler = 1;
790 h8300_pr_saveall (pfile)
791 cpp_reader *pfile ATTRIBUTE_UNUSED;
796 /* If the next arg with MODE and TYPE is to be passed in a register, return
797 the rtx to represent where it is passed. CUM represents the state after
798 the last argument. NAMED is not used. */
800 static const char *const hand_list[] =
820 /* Return an RTX to represent where a value with mode MODE will be returned
821 from a function. If the result is 0, the argument is pushed. */
824 function_arg (cum, mode, type, named)
825 CUMULATIVE_ARGS *cum;
826 enum machine_mode mode;
834 /* Never pass unnamed arguments in registers. */
838 /* Pass 3 regs worth of data in regs when user asked on the command line. */
839 if (TARGET_QUICKCALL)
842 /* If calling hand written assembler, use 4 regs of args. */
846 const char * const *p;
848 fname = XSTR (cum->libcall, 0);
850 /* See if this libcall is one of the hand coded ones. */
852 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
864 size = int_size_in_bytes (type);
866 size = GET_MODE_SIZE (mode);
868 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
874 switch (cum->nbytes / UNITS_PER_WORD)
877 result = gen_rtx_REG (mode, 0);
880 result = gen_rtx_REG (mode, 1);
883 result = gen_rtx_REG (mode, 2);
886 result = gen_rtx_REG (mode, 3);
897 /* Return the cost of the rtx R with code CODE. */
917 if (TARGET_H8300H || TARGET_H8300S)
938 /* Documentation for the machine specific operand escapes:
940 'A' print rn in H8/300 mode, erN in H8/300H mode
941 'C' print (operand - 2).
942 'E' like s but negative.
943 'F' like t but negative.
944 'G' constant just the negative
945 'M' turn a 'M' constant into its negative mod 2.
946 'P' if operand is incing/decing sp, print .w, otherwise .b.
947 'R' print operand as a byte:8 address if appropriate, else fall back to
949 'S' print operand as a long word
950 'T' print operand as a word
951 'U' if operand is incing/decing sp, print l, otherwise nothing.
952 'V' find the set bit, and print its number.
953 'W' find the clear bit, and print its number.
954 'X' print operand as a byte
955 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
956 If this operand isn't a register, fall back to 'R' handling.
958 'b' print the bit opcode
959 'c' print the ibit opcode
960 'd' bcc if EQ, bcs if NE
961 'e' first word of 32 bit value - if reg, then least reg. if mem
962 then least. if const then most sig word
963 'f' second word of 32 bit value - if reg, then biggest reg. if mem
964 then +2. if const then least sig word
965 'g' bcs if EQ, bcc if NE
966 'j' print operand as condition code.
967 'k' print operand as reverse condition code.
968 's' print as low byte of 16 bit value
969 't' print as high byte of 16 bit value
970 'w' print as low byte of 32 bit value
971 'x' print as 2nd byte of 32 bit value
972 'y' print as 3rd byte of 32 bit value
973 'z' print as msb of 32 bit value
976 /* Return assembly language string which identifies a comparison type. */
1009 /* Print operand X using operand code CODE to assembly language output file
1013 print_operand (file, x, code)
1018 /* This is used for communication between the 'P' and 'U' codes. */
1019 static const char *last_p;
1021 /* This is used for communication between codes V,W,Z and Y. */
1027 if (GET_CODE (x) == REG)
1028 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1033 fprintf (file, "#%d", INTVAL (x) - 2);
1036 switch (GET_CODE (x))
1039 fprintf (file, "%sl", names_big[REGNO (x)]);
1042 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1049 switch (GET_CODE (x))
1052 fprintf (file, "%sh", names_big[REGNO (x)]);
1055 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1062 if (GET_CODE (x) != CONST_INT)
1064 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1067 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1074 fprintf (file, "#2");
1080 fprintf (file, "#1");
1087 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1090 fprintf (file, ".w");
1095 fprintf (file, ".b");
1099 if (GET_CODE (x) == REG)
1100 fprintf (file, "%s", names_extended[REGNO (x)]);
1105 if (GET_CODE (x) == REG)
1106 fprintf (file, "%s", names_big[REGNO (x)]);
1111 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1114 bitint = exact_log2 (INTVAL (x));
1117 fprintf (file, "#%d", bitint & 7);
1120 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1123 fprintf (file, "#%d", bitint & 7);
1127 if (GET_CODE (x) == REG)
1128 fprintf (file, "%s", byte_reg (x, 0));
1135 if (GET_CODE (x) == REG)
1136 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1138 print_operand (file, x, 'R');
1142 bitint = INTVAL (x);
1143 fprintf (file, "#%d", bitint & 7);
1146 switch (GET_CODE (x))
1149 fprintf (file, "bor");
1152 fprintf (file, "bxor");
1155 fprintf (file, "band");
1162 switch (GET_CODE (x))
1165 fprintf (file, "bior");
1168 fprintf (file, "bixor");
1171 fprintf (file, "biand");
1178 switch (GET_CODE (x))
1181 fprintf (file, "bcc");
1184 fprintf (file, "bcs");
1191 switch (GET_CODE (x))
1195 fprintf (file, "%s", names_big[REGNO (x)]);
1197 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1200 print_operand (file, x, 0);
1203 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1209 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1210 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1211 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1220 switch (GET_CODE (x))
1224 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1226 fprintf (file, "%s", names_big[REGNO (x)]);
1229 x = adjust_address (x, HImode, 2);
1230 print_operand (file, x, 0);
1233 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1239 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1240 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1241 fprintf (file, "#%ld", (val & 0xffff));
1249 switch (GET_CODE (x))
1252 fprintf (file, "bcc");
1255 fprintf (file, "bcs");
1262 asm_fprintf (file, cond_string (GET_CODE (x)));
1265 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1268 if (GET_CODE (x) == CONST_INT)
1269 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1271 fprintf (file, "%s", byte_reg (x, 0));
1274 if (GET_CODE (x) == CONST_INT)
1275 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1277 fprintf (file, "%s", byte_reg (x, 1));
1280 if (GET_CODE (x) != CONST_INT)
1282 fprintf (file, "%d", INTVAL (x));
1285 if (GET_CODE (x) == CONST_INT)
1286 fprintf (file, "#%d", INTVAL (x) & 0xff);
1288 fprintf (file, "%s",
1289 byte_reg (x, TARGET_H8300 ? 2 : 0));
1292 if (GET_CODE (x) == CONST_INT)
1293 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1295 fprintf (file, "%s",
1296 byte_reg (x, TARGET_H8300 ? 3 : 1));
1299 if (GET_CODE (x) == CONST_INT)
1300 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1302 fprintf (file, "%s", byte_reg (x, 0));
1305 if (GET_CODE (x) == CONST_INT)
1306 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1308 fprintf (file, "%s", byte_reg (x, 1));
1313 switch (GET_CODE (x))
1316 switch (GET_MODE (x))
1319 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1320 fprintf (file, "%s", byte_reg (x, 0));
1321 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1322 fprintf (file, "%s", names_big[REGNO (x)]);
1326 fprintf (file, "%s", names_big[REGNO (x)]);
1330 fprintf (file, "%s", names_extended[REGNO (x)]);
1338 fprintf (file, "@");
1339 output_address (XEXP (x, 0));
1341 /* If this is an 'R' operand (reference into the 8-bit
1342 area), then specify a symbolic address as "foo:8",
1343 otherwise if operand is still in eight bit section, use
1345 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1346 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1347 fprintf (file, (code == 'R' ? ":8" : ":16"));
1348 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1349 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1350 fprintf (file, ":16");
1351 else if ((code == 'R')
1352 && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0)))
1353 fprintf (file, ":8");
1360 fprintf (file, "#");
1361 print_operand_address (file, x);
1367 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1368 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1369 fprintf (file, "#%ld", val);
1378 /* Output assembly language output for the address ADDR to FILE. */
1381 print_operand_address (file, addr)
1385 switch (GET_CODE (addr))
1388 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1392 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1396 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1400 fprintf (file, "(");
1401 if (GET_CODE (XEXP (addr, 0)) == REG)
1404 print_operand_address (file, XEXP (addr, 1));
1405 fprintf (file, ",");
1406 print_operand_address (file, XEXP (addr, 0));
1411 print_operand_address (file, XEXP (addr, 0));
1412 fprintf (file, "+");
1413 print_operand_address (file, XEXP (addr, 1));
1415 fprintf (file, ")");
1420 /* Since the H8/300 only has 16 bit pointers, negative values are also
1421 those >= 32768. This happens for example with pointer minus a
1422 constant. We don't want to turn (char *p - 2) into
1423 (char *p + 65534) because loop unrolling can build upon this
1424 (IE: char *p + 131068). */
1425 int n = INTVAL (addr);
1427 n = (int) (short) n;
1429 /* ??? Why the special case for -ve values? */
1430 fprintf (file, "-%d", -n);
1432 fprintf (file, "%d", n);
1437 output_addr_const (file, addr);
1442 /* Output all insn addresses and their sizes into the assembly language
1443 output file. This is helpful for debugging whether the length attributes
1444 in the md file are correct. This is not meant to be a user selectable
1448 final_prescan_insn (insn, operand, num_operands)
1449 rtx insn, *operand ATTRIBUTE_UNUSED;
1450 int num_operands ATTRIBUTE_UNUSED;
1452 /* This holds the last insn address. */
1453 static int last_insn_address = 0;
1455 int uid = INSN_UID (insn);
1457 if (TARGET_RTL_DUMP)
1459 fprintf (asm_out_file, "\n****************");
1460 print_rtl (asm_out_file, PATTERN (insn));
1461 fprintf (asm_out_file, "\n");
1464 if (TARGET_ADDRESSES)
1466 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1467 INSN_ADDRESSES (uid) - last_insn_address);
1468 last_insn_address = INSN_ADDRESSES (uid);
1472 /* Prepare for an SI sized move. */
1478 rtx src = operands[1];
1479 rtx dst = operands[0];
1480 if (!reload_in_progress && !reload_completed)
1482 if (!register_operand (dst, GET_MODE (dst)))
1484 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1485 emit_move_insn (tmp, src);
1492 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1493 Define the offset between two registers, one to be eliminated, and
1494 the other its replacement, at the start of a routine. */
1497 initial_offset (from, to)
1502 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1503 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1508 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1509 if (WORD_REG_USED (regno))
1510 offset += UNITS_PER_WORD;
1512 /* See the comments for get_frame_size. We need to round it up to
1515 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1516 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1518 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1519 offset += UNITS_PER_WORD; /* Skip saved PC */
1524 /* Update the condition code from the insn. */
1527 notice_update_cc (body, insn)
1531 switch (get_attr_cc (insn))
1534 /* Insn does not affect CC at all. */
1538 /* Insn does not change CC, but the 0'th operand has been changed. */
1539 if (cc_status.value1 != 0
1540 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1541 cc_status.value1 = 0;
1545 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1546 The V flag is unusable. The C flag may or may not be known but
1547 that's ok because alter_cond will change tests to use EQ/NE. */
1549 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1550 cc_status.value1 = recog_data.operand[0];
1554 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1555 The C flag may or may not be known but that's ok because
1556 alter_cond will change tests to use EQ/NE. */
1558 cc_status.flags |= CC_NO_CARRY;
1559 cc_status.value1 = recog_data.operand[0];
1563 /* The insn is a compare instruction. */
1565 cc_status.value1 = SET_SRC (body);
1569 /* Insn doesn't leave CC in a usable state. */
1575 /* Recognize valid operators for bit instructions. */
1578 bit_operator (x, mode)
1580 enum machine_mode mode ATTRIBUTE_UNUSED;
1582 enum rtx_code code = GET_CODE (x);
1591 We devote a fair bit of code to getting efficient shifts since we can only
1592 shift one bit at a time on the H8/300 and H8/300H and only one or two
1593 bits at a time on the H8/S.
1595 The basic shift methods:
1597 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1598 this is the default. SHIFT_LOOP
1600 * inlined shifts -- emit straight line code for the shift; this is
1601 used when a straight line shift is about the same size or smaller
1602 than a loop. We allow the inline version to be slightly longer in
1603 some cases as it saves a register. SHIFT_INLINE
1605 * rotate + and -- rotate the value the opposite direction, then
1606 mask off the values we don't need. This is used when only a few
1607 of the bits in the original value will survive in the shifted value.
1608 Again, this is used when it's about the same size or smaller than
1609 a loop. We allow this version to be slightly longer as it is usually
1610 much faster than a loop. SHIFT_ROT_AND
1612 * swap (+ shifts) -- often it's possible to swap bytes/words to
1613 simulate a shift by 8/16. Once swapped a few inline shifts can be
1614 added if the shift count is slightly more than 8 or 16. This is used
1615 when it's about the same size or smaller than a loop. We allow this
1616 version to be slightly longer as it is usually much faster than a loop.
1619 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1621 Here are some thoughts on what the absolutely positively best code is.
1622 "Best" here means some rational trade-off between code size and speed,
1623 where speed is more preferred but not at the expense of generating 20 insns.
1625 A trailing '*' after the shift count indicates the "best" mode isn't
1628 H8/300 QImode shifts
1629 1-4 - do them inline
1630 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1632 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1633 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1635 H8/300 HImode shifts
1636 1-4 - do them inline
1638 7 - shift 2nd half other way into carry.
1639 copy 1st half into 2nd half
1640 rotate 2nd half other way with carry
1641 rotate 1st half other way (no carry)
1642 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1643 sign extend 1st half (ASHIFTRT)
1644 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1645 9-12 - do shift by 8, inline remaining shifts
1646 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1648 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1649 - ASHIFTRT: shll, subx, set other byte
1651 H8/300 SImode shifts
1652 1-2 - do them inline
1654 7* - shift other way once, move bytes into place,
1655 move carry into place (possibly with sign extension)
1656 8 - move bytes into place, zero or sign extend other
1658 15* - shift other way once, move word into place, move carry into place
1659 16 - move word, zero or sign extend other
1661 24* - move bytes into place, zero or sign extend other
1663 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1666 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1668 ASHIFTRT: shll top byte, subx, copy to other bytes
1670 H8/300H QImode shifts (same as H8/300 QImode shifts)
1671 1-4 - do them inline
1672 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1674 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1675 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1677 H8/300H HImode shifts
1678 1-4 - do them inline
1680 7 - shift 2nd half other way into carry.
1681 copy 1st half into 2nd half
1682 rotate entire word other way using carry
1683 mask off remaining bits (ASHIFT | LSHIFTRT)
1684 sign extend remaining bits (ASHIFTRT)
1685 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1686 9-12 - do shift by 8, inline remaining shifts
1687 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1689 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1690 - ASHIFTRT: shll, subx, set other byte
1692 H8/300H SImode shifts
1693 (These are complicated by the fact that we don't have byte level access to
1695 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1696 1-4 - do them inline
1698 15* - shift other way once, move word into place, move carry into place
1699 (with sign extension for ASHIFTRT)
1700 16 - move word into place, zero or sign extend other
1701 17-20 - do 16bit shift, then inline remaining shifts
1703 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1704 move word 0 to word 1, zero word 0
1705 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1706 zero word 1, zero byte 1
1707 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1708 sign extend byte 0, sign extend word 0
1709 25-27* - either loop, or
1710 do 24 bit shift, inline rest
1711 28-30 - ASHIFT: rotate 4/3/2, mask
1712 LSHIFTRT: rotate 4/3/2, mask
1714 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1717 1-6 - do them inline
1718 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1719 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1722 1-7 - do them inline
1723 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1724 9-12 - do shift by 8, inline remaining shifts
1725 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1727 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1728 - ASHIFTRT: shll, subx, set other byte
1731 (These are complicated by the fact that we don't have byte level access to
1733 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1734 1-10 - do them inline
1736 15* - shift other way once, move word into place, move carry into place
1737 (with sign extension for ASHIFTRT)
1738 16 - move word into place, zero or sign extend other
1739 17-20 - do 16bit shift, then inline remaining shifts
1741 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1742 move word 0 to word 1, zero word 0
1743 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1744 zero word 1, zero byte 1
1745 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1746 sign extend byte 0, sign extend word 0
1747 25-27* - either loop, or
1748 do 24 bit shift, inline rest
1749 28-30 - ASHIFT: rotate 4/3/2, mask
1750 LSHIFTRT: rotate 4/3/2, mask
1752 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1757 nshift_operator (x, mode)
1759 enum machine_mode mode ATTRIBUTE_UNUSED;
1761 switch (GET_CODE (x))
1773 /* Called from the .md file to emit code to do shifts.
1774 Return a boolean indicating success.
1775 (Currently this is always TRUE). */
1778 expand_a_shift (mode, code, operands)
1779 enum machine_mode mode;
1783 emit_move_insn (operands[0], operands[1]);
1785 /* Need a loop to get all the bits we want - we generate the
1786 code at emit time, but need to allocate a scratch reg now. */
1788 emit_insn (gen_rtx_PARALLEL
1791 gen_rtx_SET (VOIDmode, operands[0],
1792 gen_rtx (code, mode, operands[0],
1794 gen_rtx_CLOBBER (VOIDmode,
1795 gen_rtx_SCRATCH (QImode)))));
1800 /* Shift algorithm determination.
1802 There are various ways of doing a shift:
1803 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1805 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1806 necessary bits into position and then set the rest to zero.
1807 SHIFT_SPECIAL: Hand crafted assembler.
1808 SHIFT_LOOP: If the above methods fail, just loop. */
1819 /* Symbols of the various shifts which can be used as indices. */
1823 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1826 /* Symbols of the various modes which can be used as indices. */
1830 QIshift, HIshift, SIshift
1833 /* For single bit shift insns, record assembler and what bits of the
1834 condition code are valid afterwards (represented as various CC_FOO
1835 bits, 0 means CC isn't left in a usable state). */
1839 const char *assembler;
1843 /* Assembler instruction shift table.
1845 These tables are used to look up the basic shifts.
1846 They are indexed by cpu, shift_type, and mode. */
1848 static const struct shift_insn shift_one[2][3][3] =
1854 { "shll\t%X0", CC_NO_CARRY },
1855 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1856 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
1858 /* SHIFT_LSHIFTRT */
1860 { "shlr\t%X0", CC_NO_CARRY },
1861 { "shlr\t%t0\n\trotxr\t%s0", 0 },
1862 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1864 /* SHIFT_ASHIFTRT */
1866 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1867 { "shar\t%t0\n\trotxr\t%s0", 0 },
1868 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1875 { "shll.b\t%X0", CC_NO_CARRY },
1876 { "shll.w\t%T0", CC_NO_CARRY },
1877 { "shll.l\t%S0", CC_NO_CARRY }
1879 /* SHIFT_LSHIFTRT */
1881 { "shlr.b\t%X0", CC_NO_CARRY },
1882 { "shlr.w\t%T0", CC_NO_CARRY },
1883 { "shlr.l\t%S0", CC_NO_CARRY }
1885 /* SHIFT_ASHIFTRT */
1887 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1888 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1889 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1894 static const struct shift_insn shift_two[3][3] =
1898 { "shll.b\t#2,%X0", CC_NO_CARRY },
1899 { "shll.w\t#2,%T0", CC_NO_CARRY },
1900 { "shll.l\t#2,%S0", CC_NO_CARRY }
1902 /* SHIFT_LSHIFTRT */
1904 { "shlr.b\t#2,%X0", CC_NO_CARRY },
1905 { "shlr.w\t#2,%T0", CC_NO_CARRY },
1906 { "shlr.l\t#2,%S0", CC_NO_CARRY }
1908 /* SHIFT_ASHIFTRT */
1910 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1911 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1912 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1916 /* Rotates are organized by which shift they'll be used in implementing.
1917 There's no need to record whether the cc is valid afterwards because
1918 it is the AND insn that will decide this. */
1920 static const char *const rotate_one[2][3][3] =
1927 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
1930 /* SHIFT_LSHIFTRT */
1933 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
1936 /* SHIFT_ASHIFTRT */
1939 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
1951 /* SHIFT_LSHIFTRT */
1957 /* SHIFT_ASHIFTRT */
1966 static const char *const rotate_two[3][3] =
1974 /* SHIFT_LSHIFTRT */
1980 /* SHIFT_ASHIFTRT */
1989 /* Shift algorithm. */
1992 /* The number of bits to be shifted by shift1 and shift2. Valid
1993 when ALG is SHIFT_SPECIAL. */
1994 unsigned int remainder;
1996 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
1997 const char *special;
1999 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2000 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2003 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2004 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2007 /* Valid CC flags. */
2011 static enum shift_alg get_shift_alg PARAMS ((enum shift_type,
2012 enum shift_mode, int,
2013 struct shift_info *));
2015 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2016 best algorithm for doing the shift. The assembler code is stored
2017 in the pointers in INFO. We don't achieve maximum efficiency in
2018 all cases, but the hooks are here to do so.
2020 For now we just use lots of switch statements. Since we don't even come
2021 close to supporting all the cases, this is simplest. If this function ever
2022 gets too big, perhaps resort to a more table based lookup. Of course,
2023 at this point you may just wish to do it all in rtl.
2025 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2026 1,2,3,4 will be inlined (1,2 for SI). */
2028 static enum shift_alg
2029 get_shift_alg (shift_type, shift_mode, count, info)
2030 enum shift_type shift_type;
2031 enum shift_mode shift_mode;
2033 struct shift_info *info;
2035 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
2036 It is up to the caller to know that looping clobbers cc. */
2037 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2039 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2041 info->shift2 = NULL;
2042 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2044 /* Now look for cases we want to optimize. */
2050 return SHIFT_INLINE;
2053 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
2054 fast as SHIFT_ROT_AND, plus CC is valid. */
2055 if (TARGET_H8300S && count <= 6)
2056 return SHIFT_INLINE;
2058 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2059 through the entire value. */
2060 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2062 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2063 info->cc_valid_p = 0;
2064 return SHIFT_SPECIAL;
2067 /* Other ASHIFTRTs are too much of a pain. */
2068 if (shift_type == SHIFT_ASHIFTRT)
2071 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */
2072 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2074 info->shift2 = rotate_two[shift_type][shift_mode];
2075 info->cc_valid_p = 0;
2076 return SHIFT_ROT_AND;
2081 return SHIFT_INLINE;
2082 else if (TARGET_H8300S && count <= 7)
2083 return SHIFT_INLINE;
2084 else if (count == 7)
2086 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2088 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2089 info->cc_valid_p = 0;
2090 return SHIFT_SPECIAL;
2093 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2095 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2096 info->cc_valid_p = 0;
2097 return SHIFT_SPECIAL;
2100 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2102 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2103 info->cc_valid_p = 0;
2104 return SHIFT_SPECIAL;
2107 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2109 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2110 info->cc_valid_p = 0;
2111 return SHIFT_SPECIAL;
2114 if (shift_type == SHIFT_ASHIFTRT)
2116 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2117 info->cc_valid_p = 0;
2118 return SHIFT_SPECIAL;
2121 else if (count == 8)
2126 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2127 info->cc_valid_p = 0;
2128 return SHIFT_SPECIAL;
2129 case SHIFT_LSHIFTRT:
2130 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2131 info->cc_valid_p = 0;
2132 return SHIFT_SPECIAL;
2133 case SHIFT_ASHIFTRT:
2135 info->special = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0";
2137 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2138 info->cc_valid_p = 0;
2139 return SHIFT_SPECIAL;
2142 else if (count == 9)
2147 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
2148 info->cc_valid_p = 0;
2149 return SHIFT_SPECIAL;
2150 case SHIFT_LSHIFTRT:
2151 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
2152 info->cc_valid_p = 0;
2153 return SHIFT_SPECIAL;
2154 case SHIFT_ASHIFTRT:
2156 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
2158 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
2159 info->cc_valid_p = 0;
2160 return SHIFT_SPECIAL;
2163 else if (count == 10)
2169 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0";
2171 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2172 info->cc_valid_p = 0;
2173 return SHIFT_SPECIAL;
2174 case SHIFT_LSHIFTRT:
2176 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
2178 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2179 info->cc_valid_p = 0;
2180 return SHIFT_SPECIAL;
2181 case SHIFT_ASHIFTRT:
2183 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2184 else if (TARGET_H8300H)
2185 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2186 else if (TARGET_H8300S)
2187 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
2188 info->cc_valid_p = 0;
2189 return SHIFT_SPECIAL;
2192 else if (count == 11)
2198 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
2200 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2201 info->cc_valid_p = 0;
2202 return SHIFT_SPECIAL;
2203 case SHIFT_LSHIFTRT:
2205 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
2207 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2208 info->cc_valid_p = 0;
2209 return SHIFT_SPECIAL;
2210 case SHIFT_ASHIFTRT:
2212 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2213 else if (TARGET_H8300H)
2214 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2215 else if (TARGET_H8300S)
2216 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
2217 info->cc_valid_p = 0;
2218 return SHIFT_SPECIAL;
2221 else if (count == 12)
2227 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
2229 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2230 info->cc_valid_p = 0;
2231 return SHIFT_SPECIAL;
2232 case SHIFT_LSHIFTRT:
2234 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
2236 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2237 info->cc_valid_p = 0;
2238 return SHIFT_SPECIAL;
2239 case SHIFT_ASHIFTRT:
2241 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2242 else if (TARGET_H8300H)
2243 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2244 else if (TARGET_H8300S)
2245 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
2246 info->cc_valid_p = 0;
2247 return SHIFT_SPECIAL;
2250 else if ((!TARGET_H8300 && (count == 13 || count == 14))
2253 if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2255 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2256 info->cc_valid_p = 0;
2257 return SHIFT_SPECIAL;
2259 else if (shift_type != SHIFT_ASHIFTRT)
2261 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2263 info->shift2 = rotate_two[shift_type][shift_mode];
2265 info->shift2 = NULL;
2266 info->cc_valid_p = 0;
2267 return SHIFT_ROT_AND;
2273 if (count <= (TARGET_H8300 ? 2 : 4))
2274 return SHIFT_INLINE;
2275 else if (TARGET_H8300S && count <= 10)
2276 return SHIFT_INLINE;
2277 else if (count == 8 && TARGET_H8300)
2282 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2283 info->cc_valid_p = 0;
2284 return SHIFT_SPECIAL;
2285 case SHIFT_LSHIFTRT:
2286 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2287 info->cc_valid_p = 0;
2288 return SHIFT_SPECIAL;
2289 case SHIFT_ASHIFTRT:
2290 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2291 info->cc_valid_p = 0;
2292 return SHIFT_SPECIAL;
2295 else if (count == 8 && !TARGET_H8300)
2300 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2301 info->cc_valid_p = 0;
2302 return SHIFT_SPECIAL;
2303 case SHIFT_LSHIFTRT:
2304 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2305 info->cc_valid_p = 0;
2306 return SHIFT_SPECIAL;
2307 case SHIFT_ASHIFTRT:
2308 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2309 info->cc_valid_p = 0;
2310 return SHIFT_SPECIAL;
2313 else if (count == 16)
2318 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2319 info->cc_valid_p = 0;
2320 return SHIFT_SPECIAL;
2321 case SHIFT_LSHIFTRT:
2322 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2323 info->cc_valid_p = 0;
2324 return SHIFT_SPECIAL;
2325 case SHIFT_ASHIFTRT:
2327 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2329 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2330 info->cc_valid_p = 0;
2331 return SHIFT_SPECIAL;
2334 else if (count == 17 && !TARGET_H8300)
2339 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
2340 info->cc_valid_p = 0;
2341 return SHIFT_SPECIAL;
2342 case SHIFT_LSHIFTRT:
2343 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
2344 info->cc_valid_p = 0;
2345 return SHIFT_SPECIAL;
2346 case SHIFT_ASHIFTRT:
2347 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
2348 info->cc_valid_p = 0;
2349 return SHIFT_SPECIAL;
2352 else if (count == 18 && !TARGET_H8300)
2358 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
2360 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2361 info->cc_valid_p = 0;
2362 return SHIFT_SPECIAL;
2363 case SHIFT_LSHIFTRT:
2365 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
2367 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2368 info->cc_valid_p = 0;
2369 return SHIFT_SPECIAL;
2370 case SHIFT_ASHIFTRT:
2372 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
2374 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2375 info->cc_valid_p = 0;
2376 return SHIFT_SPECIAL;
2379 else if (count == 19 && !TARGET_H8300)
2385 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
2387 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2388 info->cc_valid_p = 0;
2389 return SHIFT_SPECIAL;
2390 case SHIFT_LSHIFTRT:
2392 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
2394 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2395 info->cc_valid_p = 0;
2396 return SHIFT_SPECIAL;
2397 case SHIFT_ASHIFTRT:
2399 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
2401 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2402 info->cc_valid_p = 0;
2403 return SHIFT_SPECIAL;
2406 else if (count == 20 && TARGET_H8300S)
2411 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
2412 info->cc_valid_p = 0;
2413 return SHIFT_SPECIAL;
2414 case SHIFT_LSHIFTRT:
2415 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
2416 info->cc_valid_p = 0;
2417 return SHIFT_SPECIAL;
2418 case SHIFT_ASHIFTRT:
2419 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
2420 info->cc_valid_p = 0;
2421 return SHIFT_SPECIAL;
2424 else if (count == 24 && !TARGET_H8300)
2429 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2430 info->cc_valid_p = 0;
2431 return SHIFT_SPECIAL;
2432 case SHIFT_LSHIFTRT:
2433 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2434 info->cc_valid_p = 0;
2435 return SHIFT_SPECIAL;
2436 case SHIFT_ASHIFTRT:
2437 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2438 info->cc_valid_p = 0;
2439 return SHIFT_SPECIAL;
2442 else if (count >= 28 && count <= 30 && !TARGET_H8300)
2444 if (shift_type == SHIFT_ASHIFTRT)
2450 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2452 info->shift2 = rotate_two[shift_type][shift_mode];
2454 info->shift2 = NULL;
2455 info->cc_valid_p = 0;
2456 return SHIFT_ROT_AND;
2459 else if (count == 31)
2461 if (shift_type == SHIFT_ASHIFTRT)
2464 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2466 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2467 info->cc_valid_p = 0;
2468 return SHIFT_SPECIAL;
2474 if (shift_type == SHIFT_ASHIFT)
2475 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2477 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2478 info->cc_valid_p = 0;
2479 return SHIFT_SPECIAL;
2483 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2485 info->shift2 = rotate_two[shift_type][shift_mode];
2487 info->shift2 = NULL;
2488 info->cc_valid_p = 0;
2489 return SHIFT_ROT_AND;
2499 /* No fancy method is available. Just loop. */
2503 /* Emit the assembler code for doing shifts. */
2506 emit_a_shift (insn, operands)
2507 rtx insn ATTRIBUTE_UNUSED;
2510 static int loopend_lab;
2511 rtx shift = operands[3];
2512 enum machine_mode mode = GET_MODE (shift);
2513 enum rtx_code code = GET_CODE (shift);
2514 enum shift_type shift_type;
2515 enum shift_mode shift_mode;
2516 struct shift_info info;
2523 shift_mode = QIshift;
2526 shift_mode = HIshift;
2529 shift_mode = SIshift;
2538 shift_type = SHIFT_ASHIFTRT;
2541 shift_type = SHIFT_LSHIFTRT;
2544 shift_type = SHIFT_ASHIFT;
2550 if (GET_CODE (operands[2]) != CONST_INT)
2552 /* Indexing by reg, so have to loop and test at top. */
2553 output_asm_insn ("mov.b %X2,%X4", operands);
2554 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2556 /* Get the assembler code to do one shift. */
2557 get_shift_alg (shift_type, shift_mode, 1, &info);
2559 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2560 output_asm_insn (info.shift1, operands);
2561 output_asm_insn ("add #0xff,%X4", operands);
2562 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2563 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2569 int n = INTVAL (operands[2]);
2572 /* If the count is negative, make it 0. */
2575 /* If the count is too big, truncate it.
2576 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2577 do the intuitive thing. */
2578 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
2579 n = GET_MODE_BITSIZE (mode);
2581 alg = get_shift_alg (shift_type, shift_mode, n, &info);
2586 /* Emit two bit shifts first. */
2587 while (n > 1 && info.shift2 != NULL)
2589 output_asm_insn (info.shift2, operands);
2593 /* Now emit one bit shifts for any residual. */
2596 output_asm_insn (info.shift1, operands);
2600 /* Keep track of CC. */
2601 if (info.cc_valid_p)
2603 cc_status.value1 = operands[0];
2604 cc_status.flags |= info.cc_valid_p;
2610 int m = GET_MODE_BITSIZE (mode) - n;
2611 int mask = (shift_type == SHIFT_ASHIFT
2612 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2613 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2616 /* Not all possibilities of rotate are supported. They shouldn't
2617 be generated, but let's watch for 'em. */
2618 if (info.shift1 == 0)
2621 /* Emit two bit rotates first. */
2622 while (m > 1 && info.shift2 != NULL)
2624 output_asm_insn (info.shift2, operands);
2628 /* Now single bit rotates for any residual. */
2631 output_asm_insn (info.shift1, operands);
2635 /* Now mask off the high bits. */
2641 sprintf (insn_buf, "and\t#%d,%%X0", mask);
2642 cc_status.value1 = operands[0];
2643 cc_status.flags |= CC_NO_CARRY;
2646 sprintf (insn_buf, "and\t#%d,%%s0\n\tand\t#%d,%%t0",
2647 mask & 255, mask >> 8);
2657 sprintf (insn_buf, "and.%c\t#%d,%%%c0",
2658 "bwl"[shift_mode], mask,
2659 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2660 cc_status.value1 = operands[0];
2661 cc_status.flags |= CC_NO_CARRY;
2663 output_asm_insn (insn_buf, operands);
2668 output_asm_insn (info.special, operands);
2672 /* A loop to shift by a "large" constant value.
2673 If we have shift-by-2 insns, use them. */
2674 if (info.shift2 != NULL)
2676 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2677 names_big[REGNO (operands[4])]);
2678 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2679 output_asm_insn (info.shift2, operands);
2680 output_asm_insn ("add #0xff,%X4", operands);
2681 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2683 output_asm_insn (info.shift1, operands);
2687 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2688 names_big[REGNO (operands[4])]);
2689 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2690 output_asm_insn (info.shift1, operands);
2691 output_asm_insn ("add #0xff,%X4", operands);
2692 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2702 /* A rotation by a non-constant will cause a loop to be generated, in
2703 which a rotation by one bit is used. A rotation by a constant,
2704 including the one in the loop, will be taken care of by
2705 emit_a_rotate () at the insn emit time. */
2708 expand_a_rotate (code, operands)
2712 rtx dst = operands[0];
2713 rtx src = operands[1];
2714 rtx rotate_amount = operands[2];
2715 enum machine_mode mode = GET_MODE (dst);
2718 /* We rotate in place. */
2719 emit_move_insn (dst, src);
2721 if (GET_CODE (rotate_amount) != CONST_INT)
2723 rtx counter = gen_reg_rtx (QImode);
2724 rtx start_label = gen_label_rtx ();
2725 rtx end_label = gen_label_rtx ();
2727 /* If the rotate amount is less than or equal to 0,
2728 we go out of the loop. */
2729 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0),
2730 LE, NULL_RTX, QImode, 0, 0, end_label);
2732 /* Initialize the loop counter. */
2733 emit_move_insn (counter, rotate_amount);
2735 emit_label (start_label);
2737 /* Rotate by one bit. */
2738 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
2739 emit_insn (gen_rtx_SET (mode, dst, tmp));
2741 /* Decrement the counter by 1. */
2742 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
2743 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
2745 /* If the loop counter is non-zero, we go back to the beginning
2747 emit_cmp_and_jump_insns (counter, GEN_INT (0),
2748 NE, NULL_RTX, QImode, 1, 0, start_label);
2750 emit_label (end_label);
2754 /* Rotate by AMOUNT bits. */
2755 tmp = gen_rtx (code, mode, dst, rotate_amount);
2756 emit_insn (gen_rtx_SET (mode, dst, tmp));
2762 /* Emit rotate insns. */
2765 emit_a_rotate (code, operands)
2769 rtx dst = operands[0];
2770 rtx rotate_amount = operands[2];
2771 enum shift_mode rotate_mode;
2772 enum shift_type rotate_type;
2773 const char *insn_buf;
2776 enum machine_mode mode = GET_MODE (dst);
2778 if (GET_CODE (rotate_amount) != CONST_INT)
2784 rotate_mode = QIshift;
2787 rotate_mode = HIshift;
2790 rotate_mode = SIshift;
2799 rotate_type = SHIFT_ASHIFT;
2802 rotate_type = SHIFT_LSHIFTRT;
2808 amount = INTVAL (rotate_amount);
2810 /* Clean up AMOUNT. */
2813 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
2814 amount = GET_MODE_BITSIZE (mode);
2816 /* Determine the faster direction. After this phase, amount will be
2817 at most a half of GET_MODE_BITSIZE (mode). */
2818 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
2820 /* Flip the direction. */
2821 amount = GET_MODE_BITSIZE (mode) - amount;
2823 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2826 /* See if a byte swap (in HImode) or a word swap (in SImode) can
2827 boost up the rotation. */
2828 if ((mode == HImode && TARGET_H8300 && amount >= 5)
2829 || (mode == HImode && TARGET_H8300H && amount >= 6)
2830 || (mode == HImode && TARGET_H8300S && amount == 8)
2831 || (mode == SImode && TARGET_H8300H && amount >= 10)
2832 || (mode == SImode && TARGET_H8300S && amount >= 13))
2837 /* This code works on any family. */
2838 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
2839 output_asm_insn (insn_buf, operands);
2843 /* This code works on the H8/300H and H8/S. */
2844 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
2845 output_asm_insn (insn_buf, operands);
2852 /* Adjust AMOUNT and flip the direction. */
2853 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
2855 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2858 /* Emit rotate insns. */
2859 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
2862 insn_buf = rotate_two[rotate_type][rotate_mode];
2864 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2866 for (; amount >= bits; amount -= bits)
2867 output_asm_insn (insn_buf, operands);
2873 /* Fix the operands of a gen_xxx so that it could become a bit
2877 fix_bit_operand (operands, what, type)
2882 /* The bit_operand predicate accepts any memory during RTL generation, but
2883 only 'U' memory afterwards, so if this is a MEM operand, we must force
2884 it to be valid for 'U' by reloading the address. */
2886 if (GET_CODE (operands[2]) == CONST_INT)
2888 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
2890 /* Ok to have a memory dest. */
2891 if (GET_CODE (operands[0]) == MEM
2892 && !EXTRA_CONSTRAINT (operands[0], 'U'))
2894 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
2895 copy_to_mode_reg (Pmode,
2896 XEXP (operands[0], 0)));
2897 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2901 if (GET_CODE (operands[1]) == MEM
2902 && !EXTRA_CONSTRAINT (operands[1], 'U'))
2904 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
2905 copy_to_mode_reg (Pmode,
2906 XEXP (operands[1], 0)));
2907 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2914 /* Dest and src op must be register. */
2916 operands[1] = force_reg (QImode, operands[1]);
2918 rtx res = gen_reg_rtx (QImode);
2919 emit_insn (gen_rtx_SET (VOIDmode, res,
2920 gen_rtx (type, QImode, operands[1], operands[2])));
2921 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
2926 /* Return nonzero if FUNC is an interrupt function as specified
2927 by the "interrupt" attribute. */
2930 h8300_interrupt_function_p (func)
2935 if (TREE_CODE (func) != FUNCTION_DECL)
2938 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
2939 return a != NULL_TREE;
2942 /* Return nonzero if FUNC is an OS_Task function as specified
2943 by the "OS_Task" attribute. */
2946 h8300_os_task_function_p (func)
2951 if (TREE_CODE (func) != FUNCTION_DECL)
2954 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
2955 return a != NULL_TREE;
2958 /* Return nonzero if FUNC is a monitor function as specified
2959 by the "monitor" attribute. */
2962 h8300_monitor_function_p (func)
2967 if (TREE_CODE (func) != FUNCTION_DECL)
2970 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
2971 return a != NULL_TREE;
2974 /* Return nonzero if FUNC is a function that should be called
2975 through the function vector. */
2978 h8300_funcvec_function_p (func)
2983 if (TREE_CODE (func) != FUNCTION_DECL)
2986 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
2987 return a != NULL_TREE;
2990 /* Return nonzero if DECL is a variable that's in the eight bit
2994 h8300_eightbit_data_p (decl)
2999 if (TREE_CODE (decl) != VAR_DECL)
3002 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
3003 return a != NULL_TREE;
3006 /* Return nonzero if DECL is a variable that's in the tiny
3010 h8300_tiny_data_p (decl)
3015 if (TREE_CODE (decl) != VAR_DECL)
3018 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
3019 return a != NULL_TREE;
3022 /* Return nonzero if ATTR is a valid attribute for DECL.
3023 ATTRIBUTES are any existing attributes and ARGS are the arguments
3026 Supported attributes:
3028 interrupt_handler: output a prologue and epilogue suitable for an
3031 function_vector: This function should be called through the
3034 eightbit_data: This variable lives in the 8-bit data area and can
3035 be referenced with 8-bit absolute memory addresses.
3037 tiny_data: This variable lives in the tiny data area and can be
3038 referenced with 16-bit absolute memory references. */
3041 h8300_valid_decl_attribute (decl, attributes, attr, args)
3043 tree attributes ATTRIBUTE_UNUSED;
3047 if (args != NULL_TREE)
3050 if (is_attribute_p ("interrupt_handler", attr)
3051 || is_attribute_p ("OS_Task", attr)
3052 || is_attribute_p ("monitor", attr)
3053 || is_attribute_p ("function_vector", attr))
3054 return TREE_CODE (decl) == FUNCTION_DECL;
3056 if (is_attribute_p ("eightbit_data", attr)
3057 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3059 if (DECL_INITIAL (decl) == NULL_TREE)
3061 warning ("Only initialized variables can be placed into the 8-bit area.");
3064 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3068 if (is_attribute_p ("tiny_data", attr)
3069 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3071 if (DECL_INITIAL (decl) == NULL_TREE)
3073 warning ("Only initialized variables can be placed into the 8-bit area.");
3076 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3084 h8300_encode_label (decl)
3087 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3088 int len = strlen (str);
3091 newstr = ggc_alloc_string (NULL, len + 1);
3093 strcpy (newstr + 1, str);
3095 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3099 output_simode_bld (bild, log2, operands)
3104 /* Clear the destination register. */
3105 if (TARGET_H8300H || TARGET_H8300S)
3106 output_asm_insn ("sub.l\t%S0,%S0", operands);
3108 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3110 /* Get the bit number we want to load. */
3112 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3114 /* Now output the bit load or bit inverse load, and store it in
3117 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3119 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3125 /* Given INSN and its current length LENGTH, return the adjustment
3126 (in bytes) to correctly compute INSN's length.
3128 We use this to get the lengths of various memory references correct. */
3131 h8300_adjust_insn_length (insn, length)
3133 int length ATTRIBUTE_UNUSED;
3137 /* We must filter these ou before calling get_attr_adjust_length. */
3138 if (GET_CODE (PATTERN (insn)) == USE
3139 || GET_CODE (PATTERN (insn)) == CLOBBER
3140 || GET_CODE (PATTERN (insn)) == SEQUENCE
3141 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3142 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3145 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3148 pat = PATTERN (insn);
3150 /* Adjust length for reg->mem and mem->reg copies. */
3151 if (GET_CODE (pat) == SET
3152 && (GET_CODE (SET_SRC (pat)) == MEM
3153 || GET_CODE (SET_DEST (pat)) == MEM))
3155 /* This insn might need a length adjustment. */
3158 if (GET_CODE (SET_SRC (pat)) == MEM)
3159 addr = XEXP (SET_SRC (pat), 0);
3161 addr = XEXP (SET_DEST (pat), 0);
3163 /* On the H8/300, only one adjustment is necessary; if the
3164 address mode is register indirect, then this insn is two
3165 bytes shorter than indicated in the machine description. */
3166 if (TARGET_H8300 && GET_CODE (addr) == REG)
3169 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3170 indicated in the machine description. */
3171 if ((TARGET_H8300H || TARGET_H8300S)
3172 && GET_CODE (addr) == REG)
3175 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3176 bytes shorter than indicated in the machine description. */
3177 if ((TARGET_H8300H || TARGET_H8300S)
3178 && GET_CODE (addr) == PLUS
3179 && GET_CODE (XEXP (addr, 0)) == REG
3180 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3181 && INTVAL (XEXP (addr, 1)) > -32768
3182 && INTVAL (XEXP (addr, 1)) < 32767)
3185 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3186 more general abs:24. */
3187 if ((TARGET_H8300H || TARGET_H8300S)
3188 && GET_CODE (addr) == SYMBOL_REF
3189 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3193 /* Loading some constants needs adjustment. */
3194 if (GET_CODE (pat) == SET
3195 && GET_CODE (SET_SRC (pat)) == CONST_INT
3196 && GET_MODE (SET_DEST (pat)) == SImode
3197 && INTVAL (SET_SRC (pat)) != 0)
3199 int val = INTVAL (SET_SRC (pat));
3202 && ((val & 0xffff) == 0
3203 || ((val >> 16) & 0xffff) == 0))
3206 if (TARGET_H8300H || TARGET_H8300S)
3208 if (val == (val & 0xff)
3209 || val == (val & 0xff00))
3212 if (val == -4 || val == -2 || val == -1)
3217 /* Shifts need various adjustments. */
3218 if (GET_CODE (pat) == PARALLEL
3219 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3220 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3221 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3222 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3224 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3225 enum machine_mode mode = GET_MODE (src);
3228 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3231 shift = INTVAL (XEXP (src, 1));
3232 /* According to ANSI, negative shift is undefined. It is
3233 considered to be zero in this case (see function
3234 emit_a_shift above). */
3238 /* QImode shifts by small constants take one insn
3239 per shift. So the adjustment is 20 (md length) -
3241 if (mode == QImode && shift <= 4)
3242 return -(20 - shift * 2);
3244 /* Similarly for HImode and SImode shifts by
3245 small constants on the H8/300H and H8/300S. */
3246 if ((TARGET_H8300H || TARGET_H8300S)
3247 && (mode == HImode || mode == SImode) && shift <= 4)
3248 return -(20 - shift * 2);
3250 /* HImode shifts by small constants for the H8/300. */
3251 if (mode == HImode && shift <= 4)
3252 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3254 /* SImode shifts by small constants for the H8/300. */
3255 if (mode == SImode && shift <= 2)
3256 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3258 /* XXX ??? Could check for more shift/rotate cases here. */
3261 /* Rotations need various adjustments. */
3262 if (GET_CODE (pat) == SET
3263 && (GET_CODE (SET_SRC (pat)) == ROTATE
3264 || GET_CODE (SET_SRC (pat)) == ROTATERT))
3266 rtx src = SET_SRC (pat);
3267 enum machine_mode mode = GET_MODE (src);
3271 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3274 amount = INTVAL (XEXP (src, 1));
3276 /* Clean up AMOUNT. */
3279 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3280 amount = GET_MODE_BITSIZE (mode);
3282 /* Determine the faster direction. After this phase, amount
3283 will be at most a half of GET_MODE_BITSIZE (mode). */
3284 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
3285 /* Flip the direction. */
3286 amount = GET_MODE_BITSIZE (mode) - amount;
3288 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3289 boost up the rotation. */
3290 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3291 || (mode == HImode && TARGET_H8300H && amount >= 6)
3292 || (mode == HImode && TARGET_H8300S && amount == 8)
3293 || (mode == SImode && TARGET_H8300H && amount >= 10)
3294 || (mode == SImode && TARGET_H8300S && amount >= 13))
3296 /* Adjust AMOUNT and flip the direction. */
3297 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3301 /* We use 2-bit rotatations on the H8/S. */
3303 amount = amount / 2 + amount % 2;
3305 /* The H8/300 uses three insns to rotate one bit, taking 6
3307 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
3309 return -(20 - states);