1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
44 /* Forward declarations. */
45 static int h8300_interrupt_function_p PARAMS ((tree));
46 static int h8300_monitor_function_p PARAMS ((tree));
47 static int h8300_os_task_function_p PARAMS ((tree));
48 static void dosize PARAMS ((FILE *, const char *, unsigned int));
49 static const char *cond_string PARAMS ((enum rtx_code));
51 /* CPU_TYPE, says what cpu we're compiling for. */
54 /* True if the current function is an interrupt handler
55 (either via #pragma or an attribute specification). */
56 int interrupt_handler;
58 /* True if the current function is an OS Task
59 (via an attribute specification). */
62 /* True if the current function is a monitor
63 (via an attribute specification). */
66 /* True if a #pragma saveall has been seen for the current function. */
69 static const char *const names_big[] =
70 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
72 static const char *const names_extended[] =
73 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
75 static const char *const names_upper_extended[] =
76 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
78 /* Points to one of the above. */
79 /* ??? The above could be put in an array indexed by CPU_TYPE. */
80 const char * const *h8_reg_names;
82 /* Various operations needed by the following, indexed by CPU_TYPE. */
84 static const char *const h8_push_ops[2] = { "push", "push.l" };
85 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
86 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
88 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
90 /* Initialize various cpu specific globals at start up. */
97 cpu_type = (int) CPU_H8300;
98 h8_reg_names = names_big;
102 /* For this we treat the H8/300 and H8/S the same. */
103 cpu_type = (int) CPU_H8300H;
104 h8_reg_names = names_extended;
106 h8_push_op = h8_push_ops[cpu_type];
107 h8_pop_op = h8_pop_ops[cpu_type];
108 h8_mov_op = h8_mov_ops[cpu_type];
116 static const char *const names_small[] =
117 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
118 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
120 return names_small[REGNO (x) * 2 + b];
123 /* REGNO must be saved/restored across calls if this macro is true. */
125 #define WORD_REG_USED(regno) \
127 /* No need to save registers if this function will not return. */\
128 && ! TREE_THIS_VOLATILE (current_function_decl) \
130 /* Save any call saved register that was used. */ \
131 || (regs_ever_live[regno] && !call_used_regs[regno]) \
132 /* Save the frame pointer if it was used. */ \
133 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
134 /* Save any register used in an interrupt handler. */ \
135 || (interrupt_handler && regs_ever_live[regno]) \
136 /* Save call clobbered registers in non-leaf interrupt \
138 || (interrupt_handler \
139 && call_used_regs[regno] \
140 && !current_function_is_leaf)))
142 /* Output assembly language to FILE for the operation OP with operand size
143 SIZE to adjust the stack pointer. */
146 dosize (file, op, size)
151 /* On the h8300h and h8300s, for sizes <= 8 bytes it is as good or
152 better to use adds/subs insns rather than add.l/sub.l
153 with an immediate value. */
154 if (size > 4 && size <= 8 && (TARGET_H8300H || TARGET_H8300S))
156 /* Crank the size down to <= 4. */
157 fprintf (file, "\t%ss\t#%d,sp\n", op, 4);
164 if (TARGET_H8300H || TARGET_H8300S)
166 fprintf (file, "\t%ss\t#%d,sp\n", op, 4);
171 fprintf (file, "\t%ss\t#%d,sp\n", op, 2);
173 /* Fall through... */
176 fprintf (file, "\t%ss\t#%d,sp\n", op, size);
184 if (current_function_needs_context
185 && strcmp (op, "sub") == 0)
187 /* Egad. We don't have a temporary to hold the
188 size of the frame in the prologue! Just inline
189 the bastard since this shouldn't happen often. */
192 fprintf (file, "\tsubs\t#2,sp\n");
197 fprintf (file, "\tsubs\t#1,sp\n");
202 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
205 fprintf (file, "\t%s\t#%d,sp\n", op, size);
211 /* Output assembly language code for the function prologue. */
212 static int push_order[FIRST_PSEUDO_REGISTER] =
213 { 0, 1, 2, 3, 4, 5, 6, -1, -1, -1 };
214 static int pop_order[FIRST_PSEUDO_REGISTER] =
215 { 6, 5, 4, 3, 2, 1, 0, -1, -1, -1 };
217 /* This is what the stack looks like after the prolog of
218 a function with a frame has been set up:
224 <saved registers> <- sp
226 This is what the stack looks like after the prolog of
227 a function which doesn't have a frame:
232 <saved registers> <- sp
236 function_prologue (file, size)
240 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
243 /* Note a function with the interrupt attribute and set interrupt_handler
245 if (h8300_interrupt_function_p (current_function_decl))
246 interrupt_handler = 1;
248 /* If the current function has the OS_Task attribute set, then
249 we have a naked prologue. */
250 if (h8300_os_task_function_p (current_function_decl))
252 fprintf (file, ";OS_Task prologue\n");
257 if (h8300_monitor_function_p (current_function_decl))
259 /* My understanding of monitor functions is they act just
260 like interrupt functions, except the prologue must
262 fprintf (file, ";monitor prologue\n");
263 interrupt_handler = 1;
267 fprintf (file, "\tsubs\t#2,sp\n");
268 fprintf (file, "\tpush\tr0\n");
269 fprintf (file, "\tstc\tccr,r0l\n");
270 fprintf (file, "\torc\t#128,ccr\n");
271 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
275 fprintf (file, "\tpush\ter0\n");
276 fprintf (file, "\tstc\tccr,r0l\n");
277 fprintf (file, "\torc\t#128,ccr\n");
278 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
282 if (frame_pointer_needed)
285 fprintf (file, "\t%s\t%s\n", h8_push_op,
286 h8_reg_names[FRAME_POINTER_REGNUM]);
287 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
288 h8_reg_names[STACK_POINTER_REGNUM],
289 h8_reg_names[FRAME_POINTER_REGNUM]);
292 /* Leave room for locals. */
293 dosize (file, "sub", fsize);
295 /* Push the rest of the registers. */
296 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
298 int regno = push_order[idx];
301 && WORD_REG_USED (regno)
302 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
306 /* Try to push multiple registers. */
307 if (regno == 0 || regno == 4)
309 int second_regno = push_order[idx + 1];
310 int third_regno = push_order[idx + 2];
311 int fourth_regno = push_order[idx + 3];
313 if (fourth_regno >= 0
314 && WORD_REG_USED (fourth_regno)
315 && (!frame_pointer_needed
316 || fourth_regno != FRAME_POINTER_REGNUM)
318 && WORD_REG_USED (third_regno)
319 && (!frame_pointer_needed
320 || third_regno != FRAME_POINTER_REGNUM)
322 && WORD_REG_USED (second_regno)
323 && (!frame_pointer_needed
324 || second_regno != FRAME_POINTER_REGNUM))
326 fprintf (file, "\tstm.l %s-%s,@-sp\n",
328 h8_reg_names[fourth_regno]);
333 if (regno == 0 || regno == 4)
335 int second_regno = push_order[idx + 1];
336 int third_regno = push_order[idx + 2];
339 && WORD_REG_USED (third_regno)
340 && (!frame_pointer_needed
341 || third_regno != FRAME_POINTER_REGNUM)
343 && WORD_REG_USED (second_regno)
344 && (!frame_pointer_needed
345 || second_regno != FRAME_POINTER_REGNUM))
347 fprintf (file, "\tstm.l %s-%s,@-sp\n",
349 h8_reg_names[third_regno]);
354 if (regno == 0 || regno == 2 || regno == 4 || regno == 6)
356 int second_regno = push_order[idx + 1];
358 if (second_regno >= 0
359 && WORD_REG_USED (second_regno)
360 && (!frame_pointer_needed
361 || second_regno != FRAME_POINTER_REGNUM))
363 fprintf (file, "\tstm.l %s-%s,@-sp\n",
365 h8_reg_names[second_regno]);
371 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[regno]);
376 /* Output assembly language code for the function epilogue. */
379 function_epilogue (file, size)
383 int fsize = (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
385 rtx insn = get_last_insn ();
389 /* OS_Task epilogues are nearly naked -- they just have an
391 fprintf (file, ";OS_task epilogue\n");
392 fprintf (file, "\trts\n");
396 /* Monitor epilogues are the same as interrupt function epilogues.
397 Just make a note that we're in an monitor epilogue. */
399 fprintf (file, ";monitor epilogue\n");
401 /* If the last insn was a BARRIER, we don't have to write any code. */
402 if (GET_CODE (insn) == NOTE)
403 insn = prev_nonnote_insn (insn);
404 if (insn && GET_CODE (insn) == BARRIER)
407 /* Pop the saved registers. */
408 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
410 int regno = pop_order[idx];
413 && WORD_REG_USED (regno)
414 && (!frame_pointer_needed || regno != FRAME_POINTER_REGNUM))
418 /* Try to pop multiple registers. */
419 if (regno == 7 || regno == 3)
421 int second_regno = pop_order[idx + 1];
422 int third_regno = pop_order[idx + 2];
423 int fourth_regno = pop_order[idx + 3];
425 if (fourth_regno >= 0
426 && WORD_REG_USED (fourth_regno)
427 && (!frame_pointer_needed
428 || fourth_regno != FRAME_POINTER_REGNUM)
430 && WORD_REG_USED (third_regno)
431 && (!frame_pointer_needed
432 || third_regno != FRAME_POINTER_REGNUM)
434 && WORD_REG_USED (second_regno)
435 && (!frame_pointer_needed
436 || second_regno != FRAME_POINTER_REGNUM))
438 fprintf (file, "\tldm.l @sp+,%s-%s\n",
439 h8_reg_names[fourth_regno],
440 h8_reg_names[regno]);
445 if (regno == 6 || regno == 2)
447 int second_regno = pop_order[idx + 1];
448 int third_regno = pop_order[idx + 2];
451 && WORD_REG_USED (third_regno)
452 && (!frame_pointer_needed
453 || third_regno != FRAME_POINTER_REGNUM)
455 && WORD_REG_USED (second_regno)
456 && (!frame_pointer_needed
457 || second_regno != FRAME_POINTER_REGNUM))
459 fprintf (file, "\tldm.l @sp+,%s-%s\n",
460 h8_reg_names[third_regno],
461 h8_reg_names[regno]);
466 if (regno == 7 || regno == 5 || regno == 3 || regno == 1)
468 int second_regno = pop_order[idx + 1];
470 if (second_regno >= 0
471 && WORD_REG_USED (second_regno)
472 && (!frame_pointer_needed
473 || second_regno != FRAME_POINTER_REGNUM))
475 fprintf (file, "\tldm.l @sp+,%s-%s\n",
476 h8_reg_names[second_regno],
477 h8_reg_names[regno]);
483 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[regno]);
487 /* Deallocate locals. */
488 dosize (file, "add", fsize);
490 /* Pop frame pointer if we had one. */
491 if (frame_pointer_needed)
492 fprintf (file, "\t%s\t%s\n",
493 h8_pop_op, h8_reg_names[FRAME_POINTER_REGNUM]);
495 /* If this is a monitor function, there is one register still left on
498 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[0]);
500 if (interrupt_handler)
501 fprintf (file, "\trte\n");
503 fprintf (file, "\trts\n");
506 interrupt_handler = 0;
512 /* Output assembly code for the start of the file. */
515 asm_file_start (file)
518 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
519 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
520 fprintf (file, ";\trelease F-1\n");
522 fprintf (file, "; -O%d\n", optimize);
524 fprintf (file, "\n\t.h8300h\n");
525 else if (TARGET_H8300S)
526 fprintf (file, "\n\t.h8300s\n");
528 fprintf (file, "\n\n");
529 output_file_directive (file, main_input_filename);
532 /* Output assembly language code for the end of file. */
538 fprintf (file, "\t.end\n");
541 /* Return true if VALUE is a valid constant for constraint 'P'.
542 IE: VALUE is a power of two <= 2**15. */
545 small_power_of_two (value)
548 int power = exact_log2 (value);
549 return power >= 0 && power <= 15;
552 /* Return true if VALUE is a valid constant for constraint 'O', which
553 means that the constant would be ok to use as a bit for a bclr
560 return small_power_of_two ((~value) & 0xff);
563 /* Return true is OP is a valid source operand for an integer move
567 general_operand_src (op, mode)
569 enum machine_mode mode;
571 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
573 return general_operand (op, mode);
576 /* Return true if OP is a valid destination operand for an integer move
580 general_operand_dst (op, mode)
582 enum machine_mode mode;
584 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
586 return general_operand (op, mode);
589 /* Return true if OP is a const valid for a bit clear instruction. */
592 o_operand (operand, mode)
594 enum machine_mode mode ATTRIBUTE_UNUSED;
596 return (GET_CODE (operand) == CONST_INT
597 && CONST_OK_FOR_O (INTVAL (operand)));
600 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
603 p_operand (operand, mode)
605 enum machine_mode mode ATTRIBUTE_UNUSED;
607 return (GET_CODE (operand) == CONST_INT
608 && CONST_OK_FOR_P (INTVAL (operand)));
611 /* Return true if OP is a valid call operand. */
614 call_insn_operand (op, mode)
616 enum machine_mode mode ATTRIBUTE_UNUSED;
618 if (GET_CODE (op) == MEM)
620 rtx inside = XEXP (op, 0);
621 if (register_operand (inside, Pmode))
623 if (CONSTANT_ADDRESS_P (inside))
629 /* Return 1 if an addition/subtraction of a constant integer can be
630 transformed into two consecutive adds/subs that are faster than the
631 straightforward way. Otherwise, return 0. */
634 two_insn_adds_subs_operand (op, mode)
636 enum machine_mode mode;
638 if (GET_CODE (op) == CONST_INT)
640 HOST_WIDE_INT value = INTVAL (op);
642 /* Force VALUE to be positive so that we do not have to consider
643 the negative case. */
646 if (TARGET_H8300H || TARGET_H8300S)
648 /* A constant addition/subtraction takes 2 states in QImode,
649 4 states in HImode, and 6 states in SImode. Thus, the
650 only case we can win is when SImode is used, in which
651 case, two adds/subs are used, taking 4 states. */
661 /* A constant addition/subtraction takes 2 states in
662 QImode. It takes 6 states in HImode, requiring the
663 constant to be loaded to a register first, and a lot more
664 in SImode. Thus the only case we can win is when either
665 HImode or SImode is used. */
676 /* Split an add of a small constant into two adds/subs insns. */
679 split_adds_subs (mode, operands)
680 enum machine_mode mode;
683 HOST_WIDE_INT val = INTVAL (operands[1]);
684 rtx reg = operands[0];
687 /* Take care of +/- 4 for H8300H and H8300S. */
688 if (TARGET_H8300H || TARGET_H8300S)
690 /* Get the value in range of +/- 4. */
693 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (4));
694 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
699 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (-4));
700 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
704 if (val == 4 || val == -4)
706 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (val));
707 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
712 /* Get the value in range of +/- 2. */
715 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (2));
716 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
721 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (-2));
722 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
726 /* If not optimizing, we might be asked to add 0. */
730 /* We should have one or two now. */
731 if (val >= -2 && val <= 2)
733 tmp = gen_rtx_PLUS (mode, reg, GEN_INT (val));
734 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
738 /* In theory, this can't happen. */
742 /* Return true if OP is a valid call operand, and OP represents
743 an operand for a small call (4 bytes instead of 6 bytes). */
746 small_call_insn_operand (op, mode)
748 enum machine_mode mode ATTRIBUTE_UNUSED;
750 if (GET_CODE (op) == MEM)
752 rtx inside = XEXP (op, 0);
754 /* Register indirect is a small call. */
755 if (register_operand (inside, Pmode))
758 /* A call through the function vector is a small
760 if (GET_CODE (inside) == SYMBOL_REF
761 && SYMBOL_REF_FLAG (inside))
764 /* Otherwise it's a large call. */
768 /* Return true if OP is a valid jump operand. */
771 jump_address_operand (op, mode)
773 enum machine_mode mode;
775 if (GET_CODE (op) == REG)
776 return mode == Pmode;
778 if (GET_CODE (op) == MEM)
780 rtx inside = XEXP (op, 0);
781 if (register_operand (inside, Pmode))
783 if (CONSTANT_ADDRESS_P (inside))
789 /* Recognize valid operands for bitfield instructions. */
791 extern int rtx_equal_function_value_matters;
794 bit_operand (op, mode)
796 enum machine_mode mode;
798 /* We can except any general operand, expept that MEM operands must
799 be limited to those that use addresses valid for the 'U' constraint. */
800 if (!general_operand (op, mode))
803 /* Accept any mem during RTL generation. Otherwise, the code that does
804 insv and extzv will think that we can not handle memory. However,
805 to avoid reload problems, we only accept 'U' MEM operands after RTL
806 generation. This means that any named pattern which uses this predicate
807 must force its operands to match 'U' before emitting RTL. */
809 if (GET_CODE (op) == REG)
811 if (GET_CODE (op) == SUBREG)
813 if (!rtx_equal_function_value_matters)
814 /* We're building rtl. */
815 return GET_CODE (op) == MEM;
817 return (GET_CODE (op) == MEM
818 && EXTRA_CONSTRAINT (op, 'U'));
822 bit_memory_operand (op, mode)
824 enum machine_mode mode ATTRIBUTE_UNUSED;
826 return (GET_CODE (op) == MEM
827 && EXTRA_CONSTRAINT (op, 'U'));
830 /* Recognize valid operators for bit test. */
833 eq_operator (x, mode)
835 enum machine_mode mode ATTRIBUTE_UNUSED;
837 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
840 /* Handle machine specific pragmas for compatibility with existing
841 compilers for the H8/300.
843 pragma saveall generates prolog/epilog code which saves and
844 restores all the registers on function entry.
846 pragma interrupt saves and restores all registers, and exits with
847 an rte instruction rather than an rts. A pointer to a function
848 with this attribute may be safely used in an interrupt vector. */
851 handle_pragma (p_getc, p_ungetc, pname)
852 int (* ATTRIBUTE_UNUSED p_getc) PARAMS ((void));
853 void (* ATTRIBUTE_UNUSED p_ungetc) PARAMS ((int));
858 if (strcmp (pname, "interrupt") == 0)
859 interrupt_handler = retval = 1;
860 else if (strcmp (pname, "saveall") == 0)
861 pragma_saveall = retval = 1;
866 /* If the next arg with MODE and TYPE is to be passed in a register, return
867 the rtx to represent where it is passed. CUM represents the state after
868 the last argument. NAMED is not used. */
870 static const char *const hand_list[] =
890 /* Return an RTX to represent where a value with mode MODE will be returned
891 from a function. If the result is 0, the argument is pushed. */
894 function_arg (cum, mode, type, named)
895 CUMULATIVE_ARGS *cum;
896 enum machine_mode mode;
904 /* Never pass unnamed arguments in registers. */
908 /* Pass 3 regs worth of data in regs when user asked on the command line. */
909 if (TARGET_QUICKCALL)
912 /* If calling hand written assembler, use 4 regs of args. */
916 const char * const *p;
918 fname = XSTR (cum->libcall, 0);
920 /* See if this libcall is one of the hand coded ones. */
922 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
934 size = int_size_in_bytes (type);
936 size = GET_MODE_SIZE (mode);
938 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
944 switch (cum->nbytes / UNITS_PER_WORD)
947 result = gen_rtx_REG (mode, 0);
950 result = gen_rtx_REG (mode, 1);
953 result = gen_rtx_REG (mode, 2);
956 result = gen_rtx_REG (mode, 3);
967 /* Return the cost of the rtx R with code CODE. */
987 if (TARGET_H8300H || TARGET_H8300S)
1008 /* Documentation for the machine specific operand escapes:
1010 'A' print rn in h8/300 mode, erN in H8/300H mode
1011 'C' print (operand - 2).
1012 'E' like s but negative.
1013 'F' like t but negative.
1014 'G' constant just the negative
1015 'M' turn a 'M' constant into its negative mod 2.
1016 'P' if operand is incing/decing sp, print .w, otherwise .b.
1017 'R' print operand as a byte:8 address if appropriate, else fall back to
1019 'S' print operand as a long word
1020 'T' print operand as a word
1021 'U' if operand is incing/decing sp, print l, otherwise nothing.
1022 'V' find the set bit, and print its number.
1023 'W' find the clear bit, and print its number.
1024 'X' print operand as a byte
1025 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1026 If this operand isn't a register, fall back to 'R' handling.
1028 'b' print the bit opcode
1029 'c' print the ibit opcode
1030 'd' bcc if EQ, bcs if NE
1031 'e' first word of 32 bit value - if reg, then least reg. if mem
1032 then least. if const then most sig word
1033 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1034 then +2. if const then least sig word
1035 'g' bcs if EQ, bcc if NE
1036 'j' print operand as condition code.
1037 'k' print operand as reverse condition code.
1038 's' print as low byte of 16 bit value
1039 't' print as high byte of 16 bit value
1040 'w' print as low byte of 32 bit value
1041 'x' print as 2nd byte of 32 bit value
1042 'y' print as 3rd byte of 32 bit value
1043 'z' print as msb of 32 bit value
1046 /* Return assembly language string which identifies a comparison type. */
1079 /* Print operand X using operand code CODE to assembly language output file
1083 print_operand (file, x, code)
1088 /* This is used for communication between the 'P' and 'U' codes. */
1089 static const char *last_p;
1091 /* This is used for communication between codes V,W,Z and Y. */
1097 if (GET_CODE (x) == REG)
1098 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1103 fprintf (file, "#%d", INTVAL (x) - 2);
1106 switch (GET_CODE (x))
1109 fprintf (file, "%sl", names_big[REGNO (x)]);
1112 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1119 switch (GET_CODE (x))
1122 fprintf (file, "%sh", names_big[REGNO (x)]);
1125 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1132 if (GET_CODE (x) != CONST_INT)
1134 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1137 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1144 fprintf (file, "#2");
1150 fprintf (file, "#1");
1157 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1160 fprintf (file, ".w");
1165 fprintf (file, ".b");
1169 if (GET_CODE (x) == REG)
1170 fprintf (file, "%s", names_extended[REGNO (x)]);
1175 if (GET_CODE (x) == REG)
1176 fprintf (file, "%s", names_big[REGNO (x)]);
1181 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1184 bitint = exact_log2 (INTVAL (x));
1187 fprintf (file, "#%d", bitint & 7);
1190 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1193 fprintf (file, "#%d", bitint & 7);
1197 if (GET_CODE (x) == REG)
1198 fprintf (file, "%s", byte_reg (x, 0));
1205 if (GET_CODE (x) == REG)
1206 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1208 print_operand (file, x, 'R');
1212 bitint = INTVAL (x);
1213 fprintf (file, "#%d", bitint & 7);
1216 switch (GET_CODE (x))
1219 fprintf (file, "bor");
1222 fprintf (file, "bxor");
1225 fprintf (file, "band");
1232 switch (GET_CODE (x))
1235 fprintf (file, "bior");
1238 fprintf (file, "bixor");
1241 fprintf (file, "biand");
1248 switch (GET_CODE (x))
1251 fprintf (file, "bcc");
1254 fprintf (file, "bcs");
1261 switch (GET_CODE (x))
1265 fprintf (file, "%s", names_big[REGNO (x)]);
1267 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1270 x = adj_offsettable_operand (x, 0);
1271 print_operand (file, x, 0);
1274 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1280 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1281 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1282 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1291 switch (GET_CODE (x))
1295 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1297 fprintf (file, "%s", names_big[REGNO (x)]);
1300 x = adj_offsettable_operand (x, 2);
1301 print_operand (file, x, 0);
1304 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1310 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1311 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1312 fprintf (file, "#%ld", (val & 0xffff));
1320 switch (GET_CODE (x))
1323 fprintf (file, "bcc");
1326 fprintf (file, "bcs");
1333 asm_fprintf (file, cond_string (GET_CODE (x)));
1336 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1339 if (GET_CODE (x) == CONST_INT)
1340 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1342 fprintf (file, "%s", byte_reg (x, 0));
1345 if (GET_CODE (x) == CONST_INT)
1346 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1348 fprintf (file, "%s", byte_reg (x, 1));
1351 if (GET_CODE (x) != CONST_INT)
1353 fprintf (file, "%d", INTVAL (x));
1356 if (GET_CODE (x) == CONST_INT)
1357 fprintf (file, "#%d", INTVAL (x) & 0xff);
1359 fprintf (file, "%s",
1360 byte_reg (x, TARGET_H8300 ? 2 : 0));
1363 if (GET_CODE (x) == CONST_INT)
1364 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1366 fprintf (file, "%s",
1367 byte_reg (x, TARGET_H8300 ? 3 : 1));
1370 if (GET_CODE (x) == CONST_INT)
1371 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1373 fprintf (file, "%s", byte_reg (x, 0));
1376 if (GET_CODE (x) == CONST_INT)
1377 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1379 fprintf (file, "%s", byte_reg (x, 1));
1384 switch (GET_CODE (x))
1387 switch (GET_MODE (x))
1390 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1391 fprintf (file, "%s", byte_reg (x, 0));
1392 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1393 fprintf (file, "%s", names_big[REGNO (x)]);
1397 fprintf (file, "%s", names_big[REGNO (x)]);
1401 fprintf (file, "%s", names_extended[REGNO (x)]);
1409 fprintf (file, "@");
1410 output_address (XEXP (x, 0));
1412 /* If this is an 'R' operand (reference into the 8-bit
1413 area), then specify a symbolic address as "foo:8",
1414 otherwise if operand is still in eight bit section, use
1416 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1417 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1418 fprintf (file, (code == 'R' ? ":8" : ":16"));
1419 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1420 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1421 fprintf (file, ":16");
1422 else if ((code == 'R')
1423 && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0)))
1424 fprintf (file, ":8");
1431 fprintf (file, "#");
1432 print_operand_address (file, x);
1438 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1439 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1440 fprintf (file, "#%ld", val);
1449 /* Output assembly language output for the address ADDR to FILE. */
1452 print_operand_address (file, addr)
1456 switch (GET_CODE (addr))
1459 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1463 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1467 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1471 fprintf (file, "(");
1472 if (GET_CODE (XEXP (addr, 0)) == REG)
1475 print_operand_address (file, XEXP (addr, 1));
1476 fprintf (file, ",");
1477 print_operand_address (file, XEXP (addr, 0));
1482 print_operand_address (file, XEXP (addr, 0));
1483 fprintf (file, "+");
1484 print_operand_address (file, XEXP (addr, 1));
1486 fprintf (file, ")");
1491 /* Since the h8/300 only has 16 bit pointers, negative values are also
1492 those >= 32768. This happens for example with pointer minus a
1493 constant. We don't want to turn (char *p - 2) into
1494 (char *p + 65534) because loop unrolling can build upon this
1495 (IE: char *p + 131068). */
1496 int n = INTVAL (addr);
1498 n = (int) (short) n;
1500 /* ??? Why the special case for -ve values? */
1501 fprintf (file, "-%d", -n);
1503 fprintf (file, "%d", n);
1508 output_addr_const (file, addr);
1513 /* Output all insn addresses and their sizes into the assembly language
1514 output file. This is helpful for debugging whether the length attributes
1515 in the md file are correct. This is not meant to be a user selectable
1519 final_prescan_insn (insn, operand, num_operands)
1520 rtx insn, *operand ATTRIBUTE_UNUSED;
1521 int num_operands ATTRIBUTE_UNUSED;
1523 /* This holds the last insn address. */
1524 static int last_insn_address = 0;
1526 int uid = INSN_UID (insn);
1528 if (TARGET_RTL_DUMP)
1530 fprintf (asm_out_file, "\n****************");
1531 print_rtl (asm_out_file, PATTERN (insn));
1532 fprintf (asm_out_file, "\n");
1535 if (TARGET_ADDRESSES)
1537 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1538 INSN_ADDRESSES (uid) - last_insn_address);
1539 last_insn_address = INSN_ADDRESSES (uid);
1543 /* Prepare for an SI sized move. */
1549 rtx src = operands[1];
1550 rtx dst = operands[0];
1551 if (!reload_in_progress && !reload_completed)
1553 if (!register_operand (dst, GET_MODE (dst)))
1555 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1556 emit_move_insn (tmp, src);
1563 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1564 Define the offset between two registers, one to be eliminated, and
1565 the other its replacement, at the start of a routine. */
1568 initial_offset (from, to)
1573 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1574 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1579 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1580 if (WORD_REG_USED (regno))
1581 offset += UNITS_PER_WORD;
1583 /* See the comments for get_frame_size. We need to round it up to
1586 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1587 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1589 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1590 offset += UNITS_PER_WORD; /* Skip saved PC */
1595 /* Update the condition code from the insn. */
1598 notice_update_cc (body, insn)
1602 switch (get_attr_cc (insn))
1605 /* Insn does not affect CC at all. */
1609 /* Insn does not change CC, but the 0'th operand has been changed. */
1610 if (cc_status.value1 != 0
1611 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1612 cc_status.value1 = 0;
1616 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1617 The V flag is unusable. The C flag may or may not be known but
1618 that's ok because alter_cond will change tests to use EQ/NE. */
1620 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1621 cc_status.value1 = recog_data.operand[0];
1625 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1626 The C flag may or may not be known but that's ok because
1627 alter_cond will change tests to use EQ/NE. */
1629 cc_status.flags |= CC_NO_CARRY;
1630 cc_status.value1 = recog_data.operand[0];
1634 /* The insn is a compare instruction. */
1636 cc_status.value1 = SET_SRC (body);
1640 /* Insn doesn't leave CC in a usable state. */
1646 /* Recognize valid operators for bit instructions. */
1649 bit_operator (x, mode)
1651 enum machine_mode mode ATTRIBUTE_UNUSED;
1653 enum rtx_code code = GET_CODE (x);
1662 We devote a fair bit of code to getting efficient shifts since we can only
1663 shift one bit at a time on the H8/300 and H8/300H and only one or two
1664 bits at a time on the H8/S.
1666 The basic shift methods:
1668 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1669 this is the default. SHIFT_LOOP
1671 * inlined shifts -- emit straight line code for the shift; this is
1672 used when a straight line shift is about the same size or smaller
1673 than a loop. We allow the inline version to be slightly longer in
1674 some cases as it saves a register. SHIFT_INLINE
1676 * rotate + and -- rotate the value the opposite direction, then
1677 mask off the values we don't need. This is used when only a few
1678 of the bits in the original value will survive in the shifted value.
1679 Again, this is used when it's about the same size or smaller than
1680 a loop. We allow this version to be slightly longer as it is usually
1681 much faster than a loop. SHIFT_ROT_AND
1683 * swap (+ shifts) -- often it's possible to swap bytes/words to
1684 simulate a shift by 8/16. Once swapped a few inline shifts can be
1685 added if the shift count is slightly more than 8 or 16. This is used
1686 when it's about the same size or smaller than a loop. We allow this
1687 version to be slightly longer as it is usually much faster than a loop.
1690 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1692 Here are some thoughts on what the absolutely positively best code is.
1693 "Best" here means some rational trade-off between code size and speed,
1694 where speed is more preferred but not at the expense of generating 20 insns.
1696 A trailing '*' after the shift count indicates the "best" mode isn't
1699 H8/300 QImode shifts
1700 1-4 - do them inline
1701 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1703 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1704 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1706 H8/300 HImode shifts
1707 1-4 - do them inline
1709 7 - shift 2nd half other way into carry.
1710 copy 1st half into 2nd half
1711 rotate 2nd half other way with carry
1712 rotate 1st half other way (no carry)
1713 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1714 sign extend 1st half (ASHIFTRT)
1715 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1716 9-12 - do shift by 8, inline remaining shifts
1717 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1719 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1720 - ASHIFTRT: shll, subx, set other byte
1722 H8/300 SImode shifts
1723 1-2 - do them inline
1725 7* - shift other way once, move bytes into place,
1726 move carry into place (possibly with sign extension)
1727 8 - move bytes into place, zero or sign extend other
1729 15* - shift other way once, move word into place, move carry into place
1730 16 - move word, zero or sign extend other
1732 24* - move bytes into place, zero or sign extend other
1734 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1737 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1739 ASHIFTRT: shll top byte, subx, copy to other bytes
1741 H8/300H QImode shifts (same as H8/300 QImode shifts)
1742 1-4 - do them inline
1743 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1745 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1746 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1748 H8/300H HImode shifts
1749 1-4 - do them inline
1751 7 - shift 2nd half other way into carry.
1752 copy 1st half into 2nd half
1753 rotate entire word other way using carry
1754 mask off remaining bits (ASHIFT | LSHIFTRT)
1755 sign extend remaining bits (ASHIFTRT)
1756 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1757 9-12 - do shift by 8, inline remaining shifts
1758 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1760 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1761 - ASHIFTRT: shll, subx, set other byte
1763 H8/300H SImode shifts
1764 (These are complicated by the fact that we don't have byte level access to
1766 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1767 1-4 - do them inline
1769 15* - shift other way once, move word into place, move carry into place
1770 (with sign extension for ASHIFTRT)
1771 16 - move word into place, zero or sign extend other
1772 17-20 - do 16bit shift, then inline remaining shifts
1774 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1775 move word 0 to word 1, zero word 0
1776 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1777 zero word 1, zero byte 1
1778 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1779 sign extend byte 0, sign extend word 0
1780 25-27* - either loop, or
1781 do 24 bit shift, inline rest
1782 28-30 - ASHIFT: rotate 4/3/2, mask
1783 LSHIFTRT: rotate 4/3/2, mask
1785 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1788 1-6 - do them inline
1789 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1790 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1793 1-7 - do them inline
1794 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1795 9-12 - do shift by 8, inline remaining shifts
1796 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1798 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1799 - ASHIFTRT: shll, subx, set other byte
1802 (These are complicated by the fact that we don't have byte level access to
1804 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1805 1-10 - do them inline
1807 15* - shift other way once, move word into place, move carry into place
1808 (with sign extension for ASHIFTRT)
1809 16 - move word into place, zero or sign extend other
1810 17-20 - do 16bit shift, then inline remaining shifts
1812 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1813 move word 0 to word 1, zero word 0
1814 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1815 zero word 1, zero byte 1
1816 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1817 sign extend byte 0, sign extend word 0
1818 25-27* - either loop, or
1819 do 24 bit shift, inline rest
1820 28-30 - ASHIFT: rotate 4/3/2, mask
1821 LSHIFTRT: rotate 4/3/2, mask
1823 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1828 nshift_operator (x, mode)
1830 enum machine_mode mode ATTRIBUTE_UNUSED;
1832 switch (GET_CODE (x))
1844 /* Called from the .md file to emit code to do shifts.
1845 Returns a boolean indicating success
1846 (currently this is always TRUE). */
1849 expand_a_shift (mode, code, operands)
1850 enum machine_mode mode;
1854 emit_move_insn (operands[0], operands[1]);
1856 /* Need a loop to get all the bits we want - we generate the
1857 code at emit time, but need to allocate a scratch reg now. */
1859 emit_insn (gen_rtx_PARALLEL
1862 gen_rtx_SET (VOIDmode, operands[0],
1863 gen_rtx (code, mode, operands[0],
1865 gen_rtx_CLOBBER (VOIDmode,
1866 gen_rtx_SCRATCH (QImode)))));
1871 /* Shift algorithm determination.
1873 There are various ways of doing a shift:
1874 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1876 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1877 necessary bits into position and then set the rest to zero.
1878 SHIFT_SPECIAL: Hand crafted assembler.
1879 SHIFT_LOOP: If the above methods fail, just loop. */
1890 /* Symbols of the various shifts which can be used as indices. */
1894 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1897 /* Symbols of the various modes which can be used as indices. */
1901 QIshift, HIshift, SIshift
1904 /* For single bit shift insns, record assembler and what bits of the
1905 condition code are valid afterwards (represented as various CC_FOO
1906 bits, 0 means CC isn't left in a usable state). */
1910 const char *assembler;
1914 /* Assembler instruction shift table.
1916 These tables are used to look up the basic shifts.
1917 They are indexed by cpu, shift_type, and mode. */
1919 static const struct shift_insn shift_one[2][3][3] =
1925 { "shll\t%X0", CC_NO_CARRY },
1926 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1927 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
1929 /* SHIFT_LSHIFTRT */
1931 { "shlr\t%X0", CC_NO_CARRY },
1932 { "shlr\t%t0\n\trotxr\t%s0", 0 },
1933 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1935 /* SHIFT_ASHIFTRT */
1937 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1938 { "shar\t%t0\n\trotxr\t%s0", 0 },
1939 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1946 { "shll.b\t%X0", CC_NO_CARRY },
1947 { "shll.w\t%T0", CC_NO_CARRY },
1948 { "shll.l\t%S0", CC_NO_CARRY }
1950 /* SHIFT_LSHIFTRT */
1952 { "shlr.b\t%X0", CC_NO_CARRY },
1953 { "shlr.w\t%T0", CC_NO_CARRY },
1954 { "shlr.l\t%S0", CC_NO_CARRY }
1956 /* SHIFT_ASHIFTRT */
1958 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1959 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1960 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1965 static const struct shift_insn shift_two[3][3] =
1969 { "shll.b\t#2,%X0", CC_NO_CARRY },
1970 { "shll.w\t#2,%T0", CC_NO_CARRY },
1971 { "shll.l\t#2,%S0", CC_NO_CARRY }
1973 /* SHIFT_LSHIFTRT */
1975 { "shlr.b\t#2,%X0", CC_NO_CARRY },
1976 { "shlr.w\t#2,%T0", CC_NO_CARRY },
1977 { "shlr.l\t#2,%S0", CC_NO_CARRY }
1979 /* SHIFT_ASHIFTRT */
1981 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1982 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1983 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1987 /* Rotates are organized by which shift they'll be used in implementing.
1988 There's no need to record whether the cc is valid afterwards because
1989 it is the AND insn that will decide this. */
1991 static const char *const rotate_one[2][3][3] =
1998 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2001 /* SHIFT_LSHIFTRT */
2004 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2007 /* SHIFT_ASHIFTRT */
2010 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2022 /* SHIFT_LSHIFTRT */
2028 /* SHIFT_ASHIFTRT */
2037 static const char *const rotate_two[3][3] =
2045 /* SHIFT_LSHIFTRT */
2051 /* SHIFT_ASHIFTRT */
2059 static enum shift_alg get_shift_alg PARAMS ((enum attr_cpu, enum shift_type,
2060 enum machine_mode, int,
2061 const char **, const char **,
2064 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
2065 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
2066 We don't achieve maximum efficiency in all cases, but the hooks are here
2069 For now we just use lots of switch statements. Since we don't even come
2070 close to supporting all the cases, this is simplest. If this function ever
2071 gets too big, perhaps resort to a more table based lookup. Of course,
2072 at this point you may just wish to do it all in rtl.
2074 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2075 1,2,3,4 will be inlined (1,2 for SI). */
2077 static enum shift_alg
2078 get_shift_alg (cpu, shift_type, mode, count, assembler_p,
2079 assembler2_p, cc_valid_p)
2081 enum shift_type shift_type;
2082 enum machine_mode mode;
2084 const char **assembler_p;
2085 const char **assembler2_p;
2088 /* The default is to loop. */
2089 enum shift_alg alg = SHIFT_LOOP;
2090 enum shift_mode shift_mode;
2092 /* We don't handle negative shifts or shifts greater than the word size,
2093 they should have been handled already. */
2095 if (count < 0 || count > GET_MODE_BITSIZE (mode))
2101 shift_mode = QIshift;
2104 shift_mode = HIshift;
2107 shift_mode = SIshift;
2113 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
2114 It is up to the caller to know that looping clobbers cc. */
2115 *assembler_p = shift_one[cpu][shift_type][shift_mode].assembler;
2117 *assembler2_p = shift_two[shift_type][shift_mode].assembler;
2119 *assembler2_p = NULL;
2120 *cc_valid_p = shift_one[cpu][shift_type][shift_mode].cc_valid;
2122 /* Now look for cases we want to optimize. */
2128 return SHIFT_INLINE;
2131 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
2132 fast as SHIFT_ROT_AND, plus CC is valid. */
2133 if (TARGET_H8300S && count <= 6)
2134 return SHIFT_INLINE;
2136 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2137 through the entire value. */
2138 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2140 *assembler_p = "shll\t%X0\n\tsubx\t%X0,%X0";
2142 return SHIFT_SPECIAL;
2145 /* Other ASHIFTRTs are too much of a pain. */
2146 if (shift_type == SHIFT_ASHIFTRT)
2149 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */
2150 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2152 *assembler2_p = rotate_two[shift_type][shift_mode];
2154 return SHIFT_ROT_AND;
2159 return SHIFT_INLINE;
2160 else if (TARGET_H8300S && count <= 7)
2161 return SHIFT_INLINE;
2162 else if (count == 7)
2164 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2166 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2168 return SHIFT_SPECIAL;
2171 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2173 *assembler_p = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2175 return SHIFT_SPECIAL;
2178 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2180 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2182 return SHIFT_SPECIAL;
2185 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2187 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2189 return SHIFT_SPECIAL;
2192 if (shift_type == SHIFT_ASHIFTRT)
2194 *assembler_p = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2196 return SHIFT_SPECIAL;
2199 else if (count == 8)
2204 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2206 return SHIFT_SPECIAL;
2207 case SHIFT_LSHIFTRT:
2208 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2210 return SHIFT_SPECIAL;
2211 case SHIFT_ASHIFTRT:
2213 *assembler_p = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0\t";
2215 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2217 return SHIFT_SPECIAL;
2220 else if (count == 9)
2225 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
2227 return SHIFT_SPECIAL;
2228 case SHIFT_LSHIFTRT:
2229 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
2231 return SHIFT_SPECIAL;
2232 case SHIFT_ASHIFTRT:
2234 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
2236 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
2238 return SHIFT_SPECIAL;
2241 else if (count == 10)
2247 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\t";
2249 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2251 return SHIFT_SPECIAL;
2252 case SHIFT_LSHIFTRT:
2254 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
2256 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2258 return SHIFT_SPECIAL;
2259 case SHIFT_ASHIFTRT:
2261 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2262 else if (TARGET_H8300H)
2263 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2264 else if (TARGET_H8300S)
2265 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
2267 return SHIFT_SPECIAL;
2270 else if (count == 11)
2276 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
2278 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2280 return SHIFT_SPECIAL;
2281 case SHIFT_LSHIFTRT:
2283 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
2285 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2287 return SHIFT_SPECIAL;
2288 case SHIFT_ASHIFTRT:
2290 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2291 else if (TARGET_H8300H)
2292 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2293 else if (TARGET_H8300S)
2294 *assembler_p = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
2296 return SHIFT_SPECIAL;
2299 else if (count == 12)
2305 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
2307 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2309 return SHIFT_SPECIAL;
2310 case SHIFT_LSHIFTRT:
2312 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
2314 *assembler_p = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2316 return SHIFT_SPECIAL;
2317 case SHIFT_ASHIFTRT:
2319 *assembler_p = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2320 else if (TARGET_H8300H)
2321 *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2322 else if (TARGET_H8300S)
2323 *assembler_p = "mov.b\t%t0,%s0\n\textw.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
2325 return SHIFT_SPECIAL;
2328 else if ((!TARGET_H8300 && (count == 13 || count == 14))
2331 if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2333 *assembler_p = "shll\t%t0,%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2335 return SHIFT_SPECIAL;
2337 else if (shift_type != SHIFT_ASHIFTRT)
2339 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2341 *assembler2_p = rotate_two[shift_type][shift_mode];
2343 *assembler2_p = NULL;
2345 return SHIFT_ROT_AND;
2351 if (count <= (TARGET_H8300 ? 2 : 4))
2352 return SHIFT_INLINE;
2353 else if (TARGET_H8300S && count <= 10)
2354 return SHIFT_INLINE;
2355 else if (count == 8 && TARGET_H8300)
2360 *assembler_p = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2362 return SHIFT_SPECIAL;
2363 case SHIFT_LSHIFTRT:
2364 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2366 return SHIFT_SPECIAL;
2367 case SHIFT_ASHIFTRT:
2368 *assembler_p = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2370 return SHIFT_SPECIAL;
2373 else if (count == 8 && !TARGET_H8300)
2378 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2380 return SHIFT_SPECIAL;
2381 case SHIFT_LSHIFTRT:
2382 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2384 return SHIFT_SPECIAL;
2385 case SHIFT_ASHIFTRT:
2386 *assembler_p = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2388 return SHIFT_SPECIAL;
2391 else if (count == 16)
2396 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2398 return SHIFT_SPECIAL;
2399 case SHIFT_LSHIFTRT:
2400 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2402 return SHIFT_SPECIAL;
2403 case SHIFT_ASHIFTRT:
2405 *assembler_p = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2407 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2409 return SHIFT_SPECIAL;
2412 else if (count == 17 && !TARGET_H8300)
2417 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
2419 return SHIFT_SPECIAL;
2420 case SHIFT_LSHIFTRT:
2421 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
2423 return SHIFT_SPECIAL;
2424 case SHIFT_ASHIFTRT:
2425 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
2427 return SHIFT_SPECIAL;
2430 else if (count == 18 && !TARGET_H8300)
2436 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
2438 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2440 return SHIFT_SPECIAL;
2441 case SHIFT_LSHIFTRT:
2443 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
2445 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2447 return SHIFT_SPECIAL;
2448 case SHIFT_ASHIFTRT:
2450 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
2452 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2454 return SHIFT_SPECIAL;
2457 else if (count == 19 && !TARGET_H8300)
2463 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
2465 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2467 return SHIFT_SPECIAL;
2468 case SHIFT_LSHIFTRT:
2470 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
2472 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2474 return SHIFT_SPECIAL;
2475 case SHIFT_ASHIFTRT:
2477 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
2479 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2481 return SHIFT_SPECIAL;
2484 else if (count == 20 && TARGET_H8300S)
2489 *assembler_p = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
2491 return SHIFT_SPECIAL;
2492 case SHIFT_LSHIFTRT:
2493 *assembler_p = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
2495 return SHIFT_SPECIAL;
2496 case SHIFT_ASHIFTRT:
2497 *assembler_p = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
2499 return SHIFT_SPECIAL;
2502 else if (count == 24 && !TARGET_H8300)
2507 *assembler_p = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2509 return SHIFT_SPECIAL;
2510 case SHIFT_LSHIFTRT:
2511 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2513 return SHIFT_SPECIAL;
2514 case SHIFT_ASHIFTRT:
2515 *assembler_p = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2517 return SHIFT_SPECIAL;
2520 else if (count >= 28 && count <= 30 && !TARGET_H8300)
2522 if (shift_type == SHIFT_ASHIFTRT)
2528 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2530 *assembler2_p = rotate_two[shift_type][shift_mode];
2532 *assembler2_p = NULL;
2534 return SHIFT_ROT_AND;
2537 else if (count == 31)
2539 if (shift_type == SHIFT_ASHIFTRT)
2542 *assembler_p = "shll\t%z0\n\tsubx %w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2544 *assembler_p = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2546 return SHIFT_SPECIAL;
2552 if (shift_type == SHIFT_ASHIFT)
2553 *assembler_p = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2555 *assembler_p = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2557 return SHIFT_SPECIAL;
2561 *assembler_p = rotate_one[cpu][shift_type][shift_mode];
2563 *assembler2_p = rotate_two[shift_type][shift_mode];
2565 *assembler2_p = NULL;
2567 return SHIFT_ROT_AND;
2580 /* Emit the assembler code for doing shifts. */
2583 emit_a_shift (insn, operands)
2584 rtx insn ATTRIBUTE_UNUSED;
2587 static int loopend_lab;
2588 const char *assembler;
2589 const char *assembler2;
2591 rtx shift = operands[3];
2592 enum machine_mode mode = GET_MODE (shift);
2593 enum rtx_code code = GET_CODE (shift);
2594 enum shift_type shift_type;
2595 enum shift_mode shift_mode;
2602 shift_mode = QIshift;
2605 shift_mode = HIshift;
2608 shift_mode = SIshift;
2617 shift_type = SHIFT_ASHIFTRT;
2620 shift_type = SHIFT_LSHIFTRT;
2623 shift_type = SHIFT_ASHIFT;
2629 if (GET_CODE (operands[2]) != CONST_INT)
2631 /* Indexing by reg, so have to loop and test at top. */
2632 output_asm_insn ("mov.b %X2,%X4", operands);
2633 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2635 /* Get the assembler code to do one shift. */
2636 get_shift_alg (cpu_type, shift_type, mode, 1, &assembler,
2637 &assembler2, &cc_valid);
2641 int n = INTVAL (operands[2]);
2644 /* If the count is negative, make it 0. */
2647 /* If the count is too big, truncate it.
2648 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2649 do the intuitive thing. */
2650 else if (n > GET_MODE_BITSIZE (mode))
2651 n = GET_MODE_BITSIZE (mode);
2653 alg = get_shift_alg (cpu_type, shift_type, mode, n, &assembler,
2654 &assembler2, &cc_valid);
2659 /* Emit two bit shifts first. */
2660 while (n > 1 && assembler2 != NULL)
2662 output_asm_insn (assembler2, operands);
2666 /* Now emit one bit shifts for any residual. */
2669 output_asm_insn (assembler, operands);
2673 /* Keep track of CC. */
2676 cc_status.value1 = operands[0];
2677 cc_status.flags |= cc_valid;
2683 int m = GET_MODE_BITSIZE (mode) - n;
2684 int mask = (shift_type == SHIFT_ASHIFT
2685 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2686 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2688 /* Not all possibilities of rotate are supported. They shouldn't
2689 be generated, but let's watch for 'em. */
2693 /* Emit two bit rotates first. */
2694 while (m > 1 && assembler2 != NULL)
2696 output_asm_insn (assembler2, operands);
2700 /* Now single bit rotates for any residual. */
2703 output_asm_insn (assembler, operands);
2707 /* Now mask off the high bits. */
2713 sprintf (insn_buf, "and #%d,%%X0", mask);
2714 cc_status.value1 = operands[0];
2715 cc_status.flags |= CC_NO_CARRY;
2718 sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0",
2719 mask & 255, mask >> 8);
2729 sprintf (insn_buf, "and.%c #%d,%%%c0",
2730 "bwl"[shift_mode], mask,
2731 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2732 cc_status.value1 = operands[0];
2733 cc_status.flags |= CC_NO_CARRY;
2735 output_asm_insn (insn_buf, operands);
2739 output_asm_insn (assembler, operands);
2743 /* A loop to shift by a "large" constant value.
2744 If we have shift-by-2 insns, use them. */
2745 if (assembler2 != NULL)
2747 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2748 names_big[REGNO (operands[4])]);
2749 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2750 output_asm_insn (assembler2, operands);
2751 output_asm_insn ("add #0xff,%X4", operands);
2752 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2754 output_asm_insn (assembler, operands);
2759 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2760 names_big[REGNO (operands[4])]);
2761 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2762 output_asm_insn (assembler, operands);
2763 output_asm_insn ("add #0xff,%X4", operands);
2764 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2769 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2770 output_asm_insn (assembler, operands);
2771 output_asm_insn ("add #0xff,%X4", operands);
2772 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2773 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2778 /* Fix the operands of a gen_xxx so that it could become a bit
2782 fix_bit_operand (operands, what, type)
2787 /* The bit_operand predicate accepts any memory during RTL generation, but
2788 only 'U' memory afterwards, so if this is a MEM operand, we must force
2789 it to be valid for 'U' by reloading the address. */
2791 if (GET_CODE (operands[2]) == CONST_INT)
2793 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
2795 /* Ok to have a memory dest. */
2796 if (GET_CODE (operands[0]) == MEM && !EXTRA_CONSTRAINT (operands[0], 'U'))
2798 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
2799 copy_to_mode_reg (Pmode,
2800 XEXP (operands[0], 0)));
2801 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2805 if (GET_CODE (operands[1]) == MEM && !EXTRA_CONSTRAINT (operands[1], 'U'))
2807 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
2808 copy_to_mode_reg (Pmode,
2809 XEXP (operands[1], 0)));
2810 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2817 /* Dest and src op must be register. */
2819 operands[1] = force_reg (QImode, operands[1]);
2821 rtx res = gen_reg_rtx (QImode);
2822 emit_insn (gen_rtx_SET (VOIDmode, res,
2823 gen_rtx (type, QImode, operands[1], operands[2])));
2824 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
2829 /* Return nonzero if FUNC is an interrupt function as specified
2830 by the "interrupt" attribute. */
2833 h8300_interrupt_function_p (func)
2838 if (TREE_CODE (func) != FUNCTION_DECL)
2841 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
2842 return a != NULL_TREE;
2845 /* Return nonzero if FUNC is an OS_Task function as specified
2846 by the "OS_Task" attribute. */
2849 h8300_os_task_function_p (func)
2854 if (TREE_CODE (func) != FUNCTION_DECL)
2857 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
2858 return a != NULL_TREE;
2861 /* Return nonzero if FUNC is a monitor function as specified
2862 by the "monitor" attribute. */
2865 h8300_monitor_function_p (func)
2870 if (TREE_CODE (func) != FUNCTION_DECL)
2873 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
2874 return a != NULL_TREE;
2877 /* Return nonzero if FUNC is a function that should be called
2878 through the function vector. */
2881 h8300_funcvec_function_p (func)
2886 if (TREE_CODE (func) != FUNCTION_DECL)
2889 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
2890 return a != NULL_TREE;
2893 /* Return nonzero if DECL is a variable that's in the eight bit
2897 h8300_eightbit_data_p (decl)
2902 if (TREE_CODE (decl) != VAR_DECL)
2905 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
2906 return a != NULL_TREE;
2909 /* Return nonzero if DECL is a variable that's in the tiny
2913 h8300_tiny_data_p (decl)
2918 if (TREE_CODE (decl) != VAR_DECL)
2921 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
2922 return a != NULL_TREE;
2925 /* Return nonzero if ATTR is a valid attribute for DECL.
2926 ATTRIBUTES are any existing attributes and ARGS are the arguments
2929 Supported attributes:
2931 interrupt_handler: output a prologue and epilogue suitable for an
2934 function_vector: This function should be called through the
2937 eightbit_data: This variable lives in the 8-bit data area and can
2938 be referenced with 8-bit absolute memory addresses.
2940 tiny_data: This variable lives in the tiny data area and can be
2941 referenced with 16-bit absolute memory references. */
2944 h8300_valid_machine_decl_attribute (decl, attributes, attr, args)
2946 tree attributes ATTRIBUTE_UNUSED;
2950 if (args != NULL_TREE)
2953 if (is_attribute_p ("interrupt_handler", attr)
2954 || is_attribute_p ("OS_Task", attr)
2955 || is_attribute_p ("monitor", attr)
2956 || is_attribute_p ("function_vector", attr))
2957 return TREE_CODE (decl) == FUNCTION_DECL;
2959 if (is_attribute_p ("eightbit_data", attr)
2960 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
2962 if (DECL_INITIAL (decl) == NULL_TREE)
2964 warning ("Only initialized variables can be placed into the 8-bit area.");
2967 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
2971 if (is_attribute_p ("tiny_data", attr)
2972 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
2974 if (DECL_INITIAL (decl) == NULL_TREE)
2976 warning ("Only initialized variables can be placed into the 8-bit area.");
2979 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
2986 extern struct obstack *saveable_obstack;
2989 h8300_encode_label (decl)
2992 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2993 int len = strlen (str);
2996 newstr = obstack_alloc (saveable_obstack, len + 2);
2998 strcpy (newstr + 1, str);
3000 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3004 output_simode_bld (bild, log2, operands)
3009 /* Clear the destination register. */
3010 if (TARGET_H8300H || TARGET_H8300S)
3011 output_asm_insn ("sub.l\t%S0,%S0", operands);
3013 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3015 /* Get the bit number we want to load. */
3017 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3019 /* Now output the bit load or bit inverse load, and store it in
3022 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3024 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3030 /* Given INSN and its current length LENGTH, return the adjustment
3031 (in bytes) to correctly compute INSN's length.
3033 We use this to get the lengths of various memory references correct. */
3036 h8300_adjust_insn_length (insn, length)
3038 int length ATTRIBUTE_UNUSED;
3042 /* We must filter these ou before calling get_attr_adjust_length. */
3043 if (GET_CODE (PATTERN (insn)) == USE
3044 || GET_CODE (PATTERN (insn)) == CLOBBER
3045 || GET_CODE (PATTERN (insn)) == SEQUENCE
3046 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3047 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3050 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3053 pat = PATTERN (insn);
3055 /* Adjust length for reg->mem and mem->reg copies. */
3056 if (GET_CODE (pat) == SET
3057 && (GET_CODE (SET_SRC (pat)) == MEM
3058 || GET_CODE (SET_DEST (pat)) == MEM))
3060 /* This insn might need a length adjustment. */
3063 if (GET_CODE (SET_SRC (pat)) == MEM)
3064 addr = XEXP (SET_SRC (pat), 0);
3066 addr = XEXP (SET_DEST (pat), 0);
3068 /* On the H8/300, only one adjustment is necessary; if the
3069 address mode is register indirect, then this insn is two
3070 bytes shorter than indicated in the machine description. */
3071 if (TARGET_H8300 && GET_CODE (addr) == REG)
3074 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3075 indicated in the machine description. */
3076 if ((TARGET_H8300H || TARGET_H8300S)
3077 && GET_CODE (addr) == REG)
3080 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3081 bytes shorter than indicated in the machine description. */
3082 if ((TARGET_H8300H || TARGET_H8300S)
3083 && GET_CODE (addr) == PLUS
3084 && GET_CODE (XEXP (addr, 0)) == REG
3085 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3086 && INTVAL (XEXP (addr, 1)) > -32768
3087 && INTVAL (XEXP (addr, 1)) < 32767)
3090 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3091 more general abs:24. */
3092 if ((TARGET_H8300H || TARGET_H8300S)
3093 && GET_CODE (addr) == SYMBOL_REF
3094 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3098 /* Loading some constants needs adjustment. */
3099 if (GET_CODE (pat) == SET
3100 && GET_CODE (SET_SRC (pat)) == CONST_INT
3101 && GET_MODE (SET_DEST (pat)) == SImode
3102 && INTVAL (SET_SRC (pat)) != 0)
3105 && ((INTVAL (SET_SRC (pat)) & 0xffff) == 0
3106 || ((INTVAL (SET_SRC (pat)) >> 16) & 0xffff) == 0))
3109 if (TARGET_H8300H || TARGET_H8300S)
3111 int val = INTVAL (SET_SRC (pat));
3113 if (val == (val & 0xff)
3114 || val == (val & 0xff00))
3117 if (val == -4 || val == -2 || val == -1)
3122 /* Shifts need various adjustments. */
3123 if (GET_CODE (pat) == PARALLEL
3124 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3125 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3126 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3127 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3129 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3130 enum machine_mode mode = GET_MODE (src);
3133 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3136 shift = INTVAL (XEXP (src, 1));
3137 /* According to ANSI, negative shift is undefined. It is
3138 considered to be zero in this case (see function
3139 emit_a_shift above). */
3143 /* QImode shifts by small constants take one insn
3144 per shift. So the adjustment is 20 (md length) -
3146 if (mode == QImode && shift <= 4)
3147 return -(20 - shift * 2);
3149 /* Similarly for HImode and SImode shifts by
3150 small constants on the H8/300H and H8/300S. */
3151 if ((TARGET_H8300H || TARGET_H8300S)
3152 && (mode == HImode || mode == SImode) && shift <= 4)
3153 return -(20 - shift * 2);
3155 /* HImode shifts by small constants for the H8/300. */
3156 if (mode == HImode && shift <= 4)
3157 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3159 /* SImode shifts by small constants for the H8/300. */
3160 if (mode == SImode && shift <= 2)
3161 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3163 /* XXX ??? Could check for more shift/rotate cases here. */