1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 /* Forward declarations. */
46 static int h8300_interrupt_function_p PARAMS ((tree));
47 static int h8300_monitor_function_p PARAMS ((tree));
48 static int h8300_os_task_function_p PARAMS ((tree));
49 static void dosize PARAMS ((FILE *, const char *, unsigned int));
50 static int round_frame_size PARAMS ((int));
51 static unsigned int compute_saved_regs PARAMS ((void));
52 static void push PARAMS ((FILE *, int));
53 static void pop PARAMS ((FILE *, int));
54 static const char *cond_string PARAMS ((enum rtx_code));
56 /* CPU_TYPE, says what cpu we're compiling for. */
59 /* True if the current function is an interrupt handler
60 (either via #pragma or an attribute specification). */
61 int interrupt_handler;
63 /* True if the current function is an OS Task
64 (via an attribute specification). */
67 /* True if the current function is a monitor
68 (via an attribute specification). */
71 /* True if a #pragma saveall has been seen for the current function. */
74 static const char *const names_big[] =
75 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
77 static const char *const names_extended[] =
78 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
80 static const char *const names_upper_extended[] =
81 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
83 /* Points to one of the above. */
84 /* ??? The above could be put in an array indexed by CPU_TYPE. */
85 const char * const *h8_reg_names;
87 /* Various operations needed by the following, indexed by CPU_TYPE. */
89 static const char *const h8_push_ops[2] = { "push", "push.l" };
90 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
91 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
93 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
95 /* Initialize various cpu specific globals at start up. */
102 cpu_type = (int) CPU_H8300;
103 h8_reg_names = names_big;
107 /* For this we treat the H8/300H and H8/S the same. */
108 cpu_type = (int) CPU_H8300H;
109 h8_reg_names = names_extended;
111 h8_push_op = h8_push_ops[cpu_type];
112 h8_pop_op = h8_pop_ops[cpu_type];
113 h8_mov_op = h8_mov_ops[cpu_type];
115 if (!TARGET_H8300S && TARGET_MAC)
116 fatal ("-ms2600 is used without -ms.");
124 static const char *const names_small[] =
125 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
126 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
128 return names_small[REGNO (x) * 2 + b];
131 /* REGNO must be saved/restored across calls if this macro is true. */
133 #define WORD_REG_USED(regno) \
135 /* No need to save registers if this function will not return. */\
136 && ! TREE_THIS_VOLATILE (current_function_decl) \
138 /* Save any call saved register that was used. */ \
139 || (regs_ever_live[regno] && !call_used_regs[regno]) \
140 /* Save the frame pointer if it was used. */ \
141 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
142 /* Save any register used in an interrupt handler. */ \
143 || (interrupt_handler && regs_ever_live[regno]) \
144 /* Save call clobbered registers in non-leaf interrupt \
146 || (interrupt_handler \
147 && call_used_regs[regno] \
148 && !current_function_is_leaf)))
150 /* Output assembly language to FILE for the operation OP with operand size
151 SIZE to adjust the stack pointer. */
154 dosize (file, op, size)
159 /* On the H8/300H and H8/S, for sizes <= 8 bytes, it is as good or
160 better to use adds/subs insns rather than add.l/sub.l with an
163 Also, on the H8/300, if we don't have a temporary to hold the
164 size of the frame in the prologue, we simply emit a sequence of
165 subs since this shouldn't happen often. */
166 if ((TARGET_H8300 && size <= 4)
167 || ((TARGET_H8300H || TARGET_H8300S) && size <= 8)
168 || (TARGET_H8300 && current_function_needs_context
169 && strcmp (op, "sub")))
171 unsigned HOST_WIDE_INT amount;
173 /* Try different amounts in descending order. */
174 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
178 for (; size >= amount; size -= amount)
179 fprintf (file, "\t%ss\t#%d,sp\n", op, amount);
185 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
187 fprintf (file, "\t%s.l\t#%d,sp\n", op, size);
191 /* Round up frame size SIZE. */
194 round_frame_size (size)
197 return (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
200 /* Compute which registers to push/pop.
201 Return a bit vector of registers. */
204 compute_saved_regs ()
206 unsigned int saved_regs = 0;
209 /* Construct a bit vector of registers to be pushed/popped. */
210 for (regno = 0; regno <= 6; regno++)
212 if (WORD_REG_USED (regno))
213 saved_regs |= 1 << regno;
216 /* Don't push/pop the frame pointer as it is treated separately. */
217 if (frame_pointer_needed)
218 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
223 /* Output assembly language code to push register RN. */
230 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[rn]);
233 /* Output assembly language code to pop register RN. */
240 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[rn]);
243 /* This is what the stack looks like after the prolog of
244 a function with a frame has been set up:
250 <saved registers> <- sp
252 This is what the stack looks like after the prolog of
253 a function which doesn't have a frame:
258 <saved registers> <- sp
261 /* Output assembly language code for the function prologue. */
264 function_prologue (file, size)
268 int fsize = round_frame_size (size);
273 /* Note a function with the interrupt attribute and set interrupt_handler
275 if (h8300_interrupt_function_p (current_function_decl))
276 interrupt_handler = 1;
278 /* If the current function has the OS_Task attribute set, then
279 we have a naked prologue. */
280 if (h8300_os_task_function_p (current_function_decl))
282 fprintf (file, ";OS_Task prologue\n");
287 if (h8300_monitor_function_p (current_function_decl))
289 /* My understanding of monitor functions is they act just
290 like interrupt functions, except the prologue must
292 fprintf (file, ";monitor prologue\n");
293 interrupt_handler = 1;
297 fprintf (file, "\tsubs\t#2,sp\n");
299 fprintf (file, "\tstc\tccr,r0l\n");
300 fprintf (file, "\tmov.b\tr0l,@(2,sp)\n");
302 fprintf (file, "\torc\t#128,ccr\n");
304 else if (TARGET_H8300H)
307 fprintf (file, "\tstc\tccr,r0l\n");
308 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
310 fprintf (file, "\torc\t#128,ccr\n");
312 else if (TARGET_H8300S)
314 fprintf (file, "\tstc\texr,@-sp\n");
316 fprintf (file, "\tstc\tccr,r0l\n");
317 fprintf (file, "\tmov.b\tr0l,@(6,sp)\n");
319 fprintf (file, "\torc\t#128,ccr\n");
325 if (frame_pointer_needed)
328 push (file, FRAME_POINTER_REGNUM);
329 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
330 h8_reg_names[STACK_POINTER_REGNUM],
331 h8_reg_names[FRAME_POINTER_REGNUM]);
334 /* Leave room for locals. */
335 dosize (file, "sub", fsize);
337 /* Push the rest of the registers in ascending order. */
338 saved_regs = compute_saved_regs ();
339 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
344 if (saved_regs & (1 << regno))
348 /* See how many registers we can push at the same time. */
349 if ((regno == 0 || regno == 4)
350 && ((saved_regs >> regno) & 0x0f) == 0x0f)
353 else if ((regno == 0 || regno == 4)
354 && ((saved_regs >> regno) & 0x07) == 0x07)
357 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
358 && ((saved_regs >> regno) & 0x03) == 0x03)
365 fprintf (file, "\tstm.l\t%s-%s,@-sp\n",
367 h8_reg_names[regno + (n_regs - 1)]);
372 /* Output assembly language code for the function epilogue. */
375 function_epilogue (file, size)
379 int fsize = round_frame_size (size);
381 rtx insn = get_last_insn ();
387 /* OS_Task epilogues are nearly naked -- they just have an
389 fprintf (file, ";OS_task epilogue\n");
390 fprintf (file, "\trts\n");
394 /* Monitor epilogues are the same as interrupt function epilogues.
395 Just make a note that we're in an monitor epilogue. */
397 fprintf (file, ";monitor epilogue\n");
399 /* If the last insn was a BARRIER, we don't have to write any code. */
400 if (GET_CODE (insn) == NOTE)
401 insn = prev_nonnote_insn (insn);
402 if (insn && GET_CODE (insn) == BARRIER)
405 /* Pop the saved registers in descending order. */
406 saved_regs = compute_saved_regs ();
407 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
409 int regno = (FIRST_PSEUDO_REGISTER - 1) - idx;
412 if (saved_regs & (1 << regno))
416 /* See how many registers we can pop at the same time. */
417 if ((regno == 7 || regno == 3)
418 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
421 else if ((regno == 6 || regno == 2)
422 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
425 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
426 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
433 fprintf (file, "\tldm.l\t@sp+,%s-%s\n",
434 h8_reg_names[regno - (n_regs - 1)],
435 h8_reg_names[regno]);
439 /* Deallocate locals. */
440 dosize (file, "add", fsize);
442 /* Pop frame pointer if we had one. */
443 if (frame_pointer_needed)
444 pop (file, FRAME_POINTER_REGNUM);
446 if (interrupt_handler)
447 fprintf (file, "\trte\n");
449 fprintf (file, "\trts\n");
452 interrupt_handler = 0;
458 /* Output assembly code for the start of the file. */
461 asm_file_start (file)
464 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
465 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
466 fprintf (file, ";\trelease F-1\n");
468 fprintf (file, "; -O%d\n", optimize);
470 fprintf (file, "\n\t.h8300h\n");
471 else if (TARGET_H8300S)
472 fprintf (file, "\n\t.h8300s\n");
474 fprintf (file, "\n\n");
475 output_file_directive (file, main_input_filename);
478 /* Output assembly language code for the end of file. */
484 fprintf (file, "\t.end\n");
487 /* Return true if VALUE is a valid constant for constraint 'P'.
488 IE: VALUE is a power of two <= 2**15. */
491 small_power_of_two (value)
494 int power = exact_log2 (value);
495 return power >= 0 && power <= 15;
498 /* Return true if VALUE is a valid constant for constraint 'O', which
499 means that the constant would be ok to use as a bit for a bclr
506 return small_power_of_two ((~value) & 0xff);
509 /* Return true is OP is a valid source operand for an integer move
513 general_operand_src (op, mode)
515 enum machine_mode mode;
517 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
519 return general_operand (op, mode);
522 /* Return true if OP is a valid destination operand for an integer move
526 general_operand_dst (op, mode)
528 enum machine_mode mode;
530 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
532 return general_operand (op, mode);
535 /* Return true if OP is a const valid for a bit clear instruction. */
538 o_operand (operand, mode)
540 enum machine_mode mode ATTRIBUTE_UNUSED;
542 return (GET_CODE (operand) == CONST_INT
543 && CONST_OK_FOR_O (INTVAL (operand)));
546 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
549 p_operand (operand, mode)
551 enum machine_mode mode ATTRIBUTE_UNUSED;
553 return (GET_CODE (operand) == CONST_INT
554 && CONST_OK_FOR_P (INTVAL (operand)));
557 /* Return true if OP is a valid call operand. */
560 call_insn_operand (op, mode)
562 enum machine_mode mode ATTRIBUTE_UNUSED;
564 if (GET_CODE (op) == MEM)
566 rtx inside = XEXP (op, 0);
567 if (register_operand (inside, Pmode))
569 if (CONSTANT_ADDRESS_P (inside))
575 /* Return 1 if an addition/subtraction of a constant integer can be
576 transformed into two consecutive adds/subs that are faster than the
577 straightforward way. Otherwise, return 0. */
580 two_insn_adds_subs_operand (op, mode)
582 enum machine_mode mode;
584 if (GET_CODE (op) == CONST_INT)
586 HOST_WIDE_INT value = INTVAL (op);
588 /* Force VALUE to be positive so that we do not have to consider
589 the negative case. */
592 if (TARGET_H8300H || TARGET_H8300S)
594 /* A constant addition/subtraction takes 2 states in QImode,
595 4 states in HImode, and 6 states in SImode. Thus, the
596 only case we can win is when SImode is used, in which
597 case, two adds/subs are used, taking 4 states. */
607 /* A constant addition/subtraction takes 2 states in
608 QImode. It takes 6 states in HImode, requiring the
609 constant to be loaded to a register first, and a lot more
610 in SImode. Thus the only case we can win is when either
611 HImode or SImode is used. */
622 /* Split an add of a small constant into two adds/subs insns. */
625 split_adds_subs (mode, operands)
626 enum machine_mode mode;
629 HOST_WIDE_INT val = INTVAL (operands[1]);
630 rtx reg = operands[0];
631 HOST_WIDE_INT sign = 1;
632 HOST_WIDE_INT amount;
634 /* Force VAL to be positive so that we do not have to consider the
642 /* Try different amounts in descending order. */
643 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
647 for (; val >= amount; val -= amount)
649 rtx tmp = gen_rtx_PLUS (mode, reg, GEN_INT (sign * amount));
650 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
657 /* Return true if OP is a valid call operand, and OP represents
658 an operand for a small call (4 bytes instead of 6 bytes). */
661 small_call_insn_operand (op, mode)
663 enum machine_mode mode ATTRIBUTE_UNUSED;
665 if (GET_CODE (op) == MEM)
667 rtx inside = XEXP (op, 0);
669 /* Register indirect is a small call. */
670 if (register_operand (inside, Pmode))
673 /* A call through the function vector is a small
675 if (GET_CODE (inside) == SYMBOL_REF
676 && SYMBOL_REF_FLAG (inside))
679 /* Otherwise it's a large call. */
683 /* Return true if OP is a valid jump operand. */
686 jump_address_operand (op, mode)
688 enum machine_mode mode;
690 if (GET_CODE (op) == REG)
691 return mode == Pmode;
693 if (GET_CODE (op) == MEM)
695 rtx inside = XEXP (op, 0);
696 if (register_operand (inside, Pmode))
698 if (CONSTANT_ADDRESS_P (inside))
704 /* Recognize valid operands for bitfield instructions. */
706 extern int rtx_equal_function_value_matters;
709 bit_operand (op, mode)
711 enum machine_mode mode;
713 /* We can except any general operand, expept that MEM operands must
714 be limited to those that use addresses valid for the 'U' constraint. */
715 if (!general_operand (op, mode))
718 /* Accept any mem during RTL generation. Otherwise, the code that does
719 insv and extzv will think that we can not handle memory. However,
720 to avoid reload problems, we only accept 'U' MEM operands after RTL
721 generation. This means that any named pattern which uses this predicate
722 must force its operands to match 'U' before emitting RTL. */
724 if (GET_CODE (op) == REG)
726 if (GET_CODE (op) == SUBREG)
728 if (!rtx_equal_function_value_matters)
729 /* We're building rtl. */
730 return GET_CODE (op) == MEM;
732 return (GET_CODE (op) == MEM
733 && EXTRA_CONSTRAINT (op, 'U'));
737 bit_memory_operand (op, mode)
739 enum machine_mode mode ATTRIBUTE_UNUSED;
741 return (GET_CODE (op) == MEM
742 && EXTRA_CONSTRAINT (op, 'U'));
745 /* Recognize valid operators for bit test. */
748 eq_operator (x, mode)
750 enum machine_mode mode ATTRIBUTE_UNUSED;
752 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
755 /* Handle machine specific pragmas for compatibility with existing
756 compilers for the H8/300.
758 pragma saveall generates prolog/epilog code which saves and
759 restores all the registers on function entry.
761 pragma interrupt saves and restores all registers, and exits with
762 an rte instruction rather than an rts. A pointer to a function
763 with this attribute may be safely used in an interrupt vector. */
766 h8300_pr_interrupt (pfile)
767 cpp_reader *pfile ATTRIBUTE_UNUSED;
769 interrupt_handler = 1;
773 h8300_pr_saveall (pfile)
774 cpp_reader *pfile ATTRIBUTE_UNUSED;
779 /* If the next arg with MODE and TYPE is to be passed in a register, return
780 the rtx to represent where it is passed. CUM represents the state after
781 the last argument. NAMED is not used. */
783 static const char *const hand_list[] =
803 /* Return an RTX to represent where a value with mode MODE will be returned
804 from a function. If the result is 0, the argument is pushed. */
807 function_arg (cum, mode, type, named)
808 CUMULATIVE_ARGS *cum;
809 enum machine_mode mode;
817 /* Never pass unnamed arguments in registers. */
821 /* Pass 3 regs worth of data in regs when user asked on the command line. */
822 if (TARGET_QUICKCALL)
825 /* If calling hand written assembler, use 4 regs of args. */
829 const char * const *p;
831 fname = XSTR (cum->libcall, 0);
833 /* See if this libcall is one of the hand coded ones. */
835 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
847 size = int_size_in_bytes (type);
849 size = GET_MODE_SIZE (mode);
851 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
857 switch (cum->nbytes / UNITS_PER_WORD)
860 result = gen_rtx_REG (mode, 0);
863 result = gen_rtx_REG (mode, 1);
866 result = gen_rtx_REG (mode, 2);
869 result = gen_rtx_REG (mode, 3);
880 /* Return the cost of the rtx R with code CODE. */
900 if (TARGET_H8300H || TARGET_H8300S)
921 /* Documentation for the machine specific operand escapes:
923 'A' print rn in H8/300 mode, erN in H8/300H mode
924 'C' print (operand - 2).
925 'E' like s but negative.
926 'F' like t but negative.
927 'G' constant just the negative
928 'M' turn a 'M' constant into its negative mod 2.
929 'P' if operand is incing/decing sp, print .w, otherwise .b.
930 'R' print operand as a byte:8 address if appropriate, else fall back to
932 'S' print operand as a long word
933 'T' print operand as a word
934 'U' if operand is incing/decing sp, print l, otherwise nothing.
935 'V' find the set bit, and print its number.
936 'W' find the clear bit, and print its number.
937 'X' print operand as a byte
938 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
939 If this operand isn't a register, fall back to 'R' handling.
941 'b' print the bit opcode
942 'c' print the ibit opcode
943 'd' bcc if EQ, bcs if NE
944 'e' first word of 32 bit value - if reg, then least reg. if mem
945 then least. if const then most sig word
946 'f' second word of 32 bit value - if reg, then biggest reg. if mem
947 then +2. if const then least sig word
948 'g' bcs if EQ, bcc if NE
949 'j' print operand as condition code.
950 'k' print operand as reverse condition code.
951 's' print as low byte of 16 bit value
952 't' print as high byte of 16 bit value
953 'w' print as low byte of 32 bit value
954 'x' print as 2nd byte of 32 bit value
955 'y' print as 3rd byte of 32 bit value
956 'z' print as msb of 32 bit value
959 /* Return assembly language string which identifies a comparison type. */
992 /* Print operand X using operand code CODE to assembly language output file
996 print_operand (file, x, code)
1001 /* This is used for communication between the 'P' and 'U' codes. */
1002 static const char *last_p;
1004 /* This is used for communication between codes V,W,Z and Y. */
1010 if (GET_CODE (x) == REG)
1011 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1016 fprintf (file, "#%d", INTVAL (x) - 2);
1019 switch (GET_CODE (x))
1022 fprintf (file, "%sl", names_big[REGNO (x)]);
1025 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1032 switch (GET_CODE (x))
1035 fprintf (file, "%sh", names_big[REGNO (x)]);
1038 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1045 if (GET_CODE (x) != CONST_INT)
1047 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1050 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1057 fprintf (file, "#2");
1063 fprintf (file, "#1");
1070 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1073 fprintf (file, ".w");
1078 fprintf (file, ".b");
1082 if (GET_CODE (x) == REG)
1083 fprintf (file, "%s", names_extended[REGNO (x)]);
1088 if (GET_CODE (x) == REG)
1089 fprintf (file, "%s", names_big[REGNO (x)]);
1094 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1097 bitint = exact_log2 (INTVAL (x));
1100 fprintf (file, "#%d", bitint & 7);
1103 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1106 fprintf (file, "#%d", bitint & 7);
1110 if (GET_CODE (x) == REG)
1111 fprintf (file, "%s", byte_reg (x, 0));
1118 if (GET_CODE (x) == REG)
1119 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1121 print_operand (file, x, 'R');
1125 bitint = INTVAL (x);
1126 fprintf (file, "#%d", bitint & 7);
1129 switch (GET_CODE (x))
1132 fprintf (file, "bor");
1135 fprintf (file, "bxor");
1138 fprintf (file, "band");
1145 switch (GET_CODE (x))
1148 fprintf (file, "bior");
1151 fprintf (file, "bixor");
1154 fprintf (file, "biand");
1161 switch (GET_CODE (x))
1164 fprintf (file, "bcc");
1167 fprintf (file, "bcs");
1174 switch (GET_CODE (x))
1178 fprintf (file, "%s", names_big[REGNO (x)]);
1180 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1183 x = adj_offsettable_operand (x, 0);
1184 print_operand (file, x, 0);
1187 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1193 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1194 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1195 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1204 switch (GET_CODE (x))
1208 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1210 fprintf (file, "%s", names_big[REGNO (x)]);
1213 x = adj_offsettable_operand (x, 2);
1214 print_operand (file, x, 0);
1217 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1223 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1224 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1225 fprintf (file, "#%ld", (val & 0xffff));
1233 switch (GET_CODE (x))
1236 fprintf (file, "bcc");
1239 fprintf (file, "bcs");
1246 asm_fprintf (file, cond_string (GET_CODE (x)));
1249 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1252 if (GET_CODE (x) == CONST_INT)
1253 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1255 fprintf (file, "%s", byte_reg (x, 0));
1258 if (GET_CODE (x) == CONST_INT)
1259 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1261 fprintf (file, "%s", byte_reg (x, 1));
1264 if (GET_CODE (x) != CONST_INT)
1266 fprintf (file, "%d", INTVAL (x));
1269 if (GET_CODE (x) == CONST_INT)
1270 fprintf (file, "#%d", INTVAL (x) & 0xff);
1272 fprintf (file, "%s",
1273 byte_reg (x, TARGET_H8300 ? 2 : 0));
1276 if (GET_CODE (x) == CONST_INT)
1277 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1279 fprintf (file, "%s",
1280 byte_reg (x, TARGET_H8300 ? 3 : 1));
1283 if (GET_CODE (x) == CONST_INT)
1284 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1286 fprintf (file, "%s", byte_reg (x, 0));
1289 if (GET_CODE (x) == CONST_INT)
1290 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1292 fprintf (file, "%s", byte_reg (x, 1));
1297 switch (GET_CODE (x))
1300 switch (GET_MODE (x))
1303 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1304 fprintf (file, "%s", byte_reg (x, 0));
1305 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1306 fprintf (file, "%s", names_big[REGNO (x)]);
1310 fprintf (file, "%s", names_big[REGNO (x)]);
1314 fprintf (file, "%s", names_extended[REGNO (x)]);
1322 fprintf (file, "@");
1323 output_address (XEXP (x, 0));
1325 /* If this is an 'R' operand (reference into the 8-bit
1326 area), then specify a symbolic address as "foo:8",
1327 otherwise if operand is still in eight bit section, use
1329 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1330 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1331 fprintf (file, (code == 'R' ? ":8" : ":16"));
1332 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1333 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1334 fprintf (file, ":16");
1335 else if ((code == 'R')
1336 && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0)))
1337 fprintf (file, ":8");
1344 fprintf (file, "#");
1345 print_operand_address (file, x);
1351 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1352 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1353 fprintf (file, "#%ld", val);
1362 /* Output assembly language output for the address ADDR to FILE. */
1365 print_operand_address (file, addr)
1369 switch (GET_CODE (addr))
1372 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1376 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1380 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1384 fprintf (file, "(");
1385 if (GET_CODE (XEXP (addr, 0)) == REG)
1388 print_operand_address (file, XEXP (addr, 1));
1389 fprintf (file, ",");
1390 print_operand_address (file, XEXP (addr, 0));
1395 print_operand_address (file, XEXP (addr, 0));
1396 fprintf (file, "+");
1397 print_operand_address (file, XEXP (addr, 1));
1399 fprintf (file, ")");
1404 /* Since the H8/300 only has 16 bit pointers, negative values are also
1405 those >= 32768. This happens for example with pointer minus a
1406 constant. We don't want to turn (char *p - 2) into
1407 (char *p + 65534) because loop unrolling can build upon this
1408 (IE: char *p + 131068). */
1409 int n = INTVAL (addr);
1411 n = (int) (short) n;
1413 /* ??? Why the special case for -ve values? */
1414 fprintf (file, "-%d", -n);
1416 fprintf (file, "%d", n);
1421 output_addr_const (file, addr);
1426 /* Output all insn addresses and their sizes into the assembly language
1427 output file. This is helpful for debugging whether the length attributes
1428 in the md file are correct. This is not meant to be a user selectable
1432 final_prescan_insn (insn, operand, num_operands)
1433 rtx insn, *operand ATTRIBUTE_UNUSED;
1434 int num_operands ATTRIBUTE_UNUSED;
1436 /* This holds the last insn address. */
1437 static int last_insn_address = 0;
1439 int uid = INSN_UID (insn);
1441 if (TARGET_RTL_DUMP)
1443 fprintf (asm_out_file, "\n****************");
1444 print_rtl (asm_out_file, PATTERN (insn));
1445 fprintf (asm_out_file, "\n");
1448 if (TARGET_ADDRESSES)
1450 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1451 INSN_ADDRESSES (uid) - last_insn_address);
1452 last_insn_address = INSN_ADDRESSES (uid);
1456 /* Prepare for an SI sized move. */
1462 rtx src = operands[1];
1463 rtx dst = operands[0];
1464 if (!reload_in_progress && !reload_completed)
1466 if (!register_operand (dst, GET_MODE (dst)))
1468 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1469 emit_move_insn (tmp, src);
1476 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1477 Define the offset between two registers, one to be eliminated, and
1478 the other its replacement, at the start of a routine. */
1481 initial_offset (from, to)
1486 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1487 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1492 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1493 if (WORD_REG_USED (regno))
1494 offset += UNITS_PER_WORD;
1496 /* See the comments for get_frame_size. We need to round it up to
1499 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1500 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1502 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1503 offset += UNITS_PER_WORD; /* Skip saved PC */
1508 /* Update the condition code from the insn. */
1511 notice_update_cc (body, insn)
1515 switch (get_attr_cc (insn))
1518 /* Insn does not affect CC at all. */
1522 /* Insn does not change CC, but the 0'th operand has been changed. */
1523 if (cc_status.value1 != 0
1524 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1525 cc_status.value1 = 0;
1529 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1530 The V flag is unusable. The C flag may or may not be known but
1531 that's ok because alter_cond will change tests to use EQ/NE. */
1533 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1534 cc_status.value1 = recog_data.operand[0];
1538 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1539 The C flag may or may not be known but that's ok because
1540 alter_cond will change tests to use EQ/NE. */
1542 cc_status.flags |= CC_NO_CARRY;
1543 cc_status.value1 = recog_data.operand[0];
1547 /* The insn is a compare instruction. */
1549 cc_status.value1 = SET_SRC (body);
1553 /* Insn doesn't leave CC in a usable state. */
1559 /* Recognize valid operators for bit instructions. */
1562 bit_operator (x, mode)
1564 enum machine_mode mode ATTRIBUTE_UNUSED;
1566 enum rtx_code code = GET_CODE (x);
1575 We devote a fair bit of code to getting efficient shifts since we can only
1576 shift one bit at a time on the H8/300 and H8/300H and only one or two
1577 bits at a time on the H8/S.
1579 The basic shift methods:
1581 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1582 this is the default. SHIFT_LOOP
1584 * inlined shifts -- emit straight line code for the shift; this is
1585 used when a straight line shift is about the same size or smaller
1586 than a loop. We allow the inline version to be slightly longer in
1587 some cases as it saves a register. SHIFT_INLINE
1589 * rotate + and -- rotate the value the opposite direction, then
1590 mask off the values we don't need. This is used when only a few
1591 of the bits in the original value will survive in the shifted value.
1592 Again, this is used when it's about the same size or smaller than
1593 a loop. We allow this version to be slightly longer as it is usually
1594 much faster than a loop. SHIFT_ROT_AND
1596 * swap (+ shifts) -- often it's possible to swap bytes/words to
1597 simulate a shift by 8/16. Once swapped a few inline shifts can be
1598 added if the shift count is slightly more than 8 or 16. This is used
1599 when it's about the same size or smaller than a loop. We allow this
1600 version to be slightly longer as it is usually much faster than a loop.
1603 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1605 Here are some thoughts on what the absolutely positively best code is.
1606 "Best" here means some rational trade-off between code size and speed,
1607 where speed is more preferred but not at the expense of generating 20 insns.
1609 A trailing '*' after the shift count indicates the "best" mode isn't
1612 H8/300 QImode shifts
1613 1-4 - do them inline
1614 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1616 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1617 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1619 H8/300 HImode shifts
1620 1-4 - do them inline
1622 7 - shift 2nd half other way into carry.
1623 copy 1st half into 2nd half
1624 rotate 2nd half other way with carry
1625 rotate 1st half other way (no carry)
1626 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1627 sign extend 1st half (ASHIFTRT)
1628 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1629 9-12 - do shift by 8, inline remaining shifts
1630 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1632 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1633 - ASHIFTRT: shll, subx, set other byte
1635 H8/300 SImode shifts
1636 1-2 - do them inline
1638 7* - shift other way once, move bytes into place,
1639 move carry into place (possibly with sign extension)
1640 8 - move bytes into place, zero or sign extend other
1642 15* - shift other way once, move word into place, move carry into place
1643 16 - move word, zero or sign extend other
1645 24* - move bytes into place, zero or sign extend other
1647 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1650 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1652 ASHIFTRT: shll top byte, subx, copy to other bytes
1654 H8/300H QImode shifts (same as H8/300 QImode shifts)
1655 1-4 - do them inline
1656 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1658 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1659 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1661 H8/300H HImode shifts
1662 1-4 - do them inline
1664 7 - shift 2nd half other way into carry.
1665 copy 1st half into 2nd half
1666 rotate entire word other way using carry
1667 mask off remaining bits (ASHIFT | LSHIFTRT)
1668 sign extend remaining bits (ASHIFTRT)
1669 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1670 9-12 - do shift by 8, inline remaining shifts
1671 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1673 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1674 - ASHIFTRT: shll, subx, set other byte
1676 H8/300H SImode shifts
1677 (These are complicated by the fact that we don't have byte level access to
1679 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1680 1-4 - do them inline
1682 15* - shift other way once, move word into place, move carry into place
1683 (with sign extension for ASHIFTRT)
1684 16 - move word into place, zero or sign extend other
1685 17-20 - do 16bit shift, then inline remaining shifts
1687 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1688 move word 0 to word 1, zero word 0
1689 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1690 zero word 1, zero byte 1
1691 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1692 sign extend byte 0, sign extend word 0
1693 25-27* - either loop, or
1694 do 24 bit shift, inline rest
1695 28-30 - ASHIFT: rotate 4/3/2, mask
1696 LSHIFTRT: rotate 4/3/2, mask
1698 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1701 1-6 - do them inline
1702 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1703 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1706 1-7 - do them inline
1707 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1708 9-12 - do shift by 8, inline remaining shifts
1709 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1711 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1712 - ASHIFTRT: shll, subx, set other byte
1715 (These are complicated by the fact that we don't have byte level access to
1717 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1718 1-10 - do them inline
1720 15* - shift other way once, move word into place, move carry into place
1721 (with sign extension for ASHIFTRT)
1722 16 - move word into place, zero or sign extend other
1723 17-20 - do 16bit shift, then inline remaining shifts
1725 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1726 move word 0 to word 1, zero word 0
1727 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1728 zero word 1, zero byte 1
1729 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1730 sign extend byte 0, sign extend word 0
1731 25-27* - either loop, or
1732 do 24 bit shift, inline rest
1733 28-30 - ASHIFT: rotate 4/3/2, mask
1734 LSHIFTRT: rotate 4/3/2, mask
1736 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1741 nshift_operator (x, mode)
1743 enum machine_mode mode ATTRIBUTE_UNUSED;
1745 switch (GET_CODE (x))
1757 /* Called from the .md file to emit code to do shifts.
1758 Return a boolean indicating success.
1759 (Currently this is always TRUE). */
1762 expand_a_shift (mode, code, operands)
1763 enum machine_mode mode;
1767 emit_move_insn (operands[0], operands[1]);
1769 /* Need a loop to get all the bits we want - we generate the
1770 code at emit time, but need to allocate a scratch reg now. */
1772 emit_insn (gen_rtx_PARALLEL
1775 gen_rtx_SET (VOIDmode, operands[0],
1776 gen_rtx (code, mode, operands[0],
1778 gen_rtx_CLOBBER (VOIDmode,
1779 gen_rtx_SCRATCH (QImode)))));
1784 /* Shift algorithm determination.
1786 There are various ways of doing a shift:
1787 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1789 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1790 necessary bits into position and then set the rest to zero.
1791 SHIFT_SPECIAL: Hand crafted assembler.
1792 SHIFT_LOOP: If the above methods fail, just loop. */
1803 /* Symbols of the various shifts which can be used as indices. */
1807 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1810 /* Symbols of the various modes which can be used as indices. */
1814 QIshift, HIshift, SIshift
1817 /* For single bit shift insns, record assembler and what bits of the
1818 condition code are valid afterwards (represented as various CC_FOO
1819 bits, 0 means CC isn't left in a usable state). */
1823 const char *assembler;
1827 /* Assembler instruction shift table.
1829 These tables are used to look up the basic shifts.
1830 They are indexed by cpu, shift_type, and mode. */
1832 static const struct shift_insn shift_one[2][3][3] =
1838 { "shll\t%X0", CC_NO_CARRY },
1839 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1840 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
1842 /* SHIFT_LSHIFTRT */
1844 { "shlr\t%X0", CC_NO_CARRY },
1845 { "shlr\t%t0\n\trotxr\t%s0", 0 },
1846 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1848 /* SHIFT_ASHIFTRT */
1850 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1851 { "shar\t%t0\n\trotxr\t%s0", 0 },
1852 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
1859 { "shll.b\t%X0", CC_NO_CARRY },
1860 { "shll.w\t%T0", CC_NO_CARRY },
1861 { "shll.l\t%S0", CC_NO_CARRY }
1863 /* SHIFT_LSHIFTRT */
1865 { "shlr.b\t%X0", CC_NO_CARRY },
1866 { "shlr.w\t%T0", CC_NO_CARRY },
1867 { "shlr.l\t%S0", CC_NO_CARRY }
1869 /* SHIFT_ASHIFTRT */
1871 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1872 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1873 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1878 static const struct shift_insn shift_two[3][3] =
1882 { "shll.b\t#2,%X0", CC_NO_CARRY },
1883 { "shll.w\t#2,%T0", CC_NO_CARRY },
1884 { "shll.l\t#2,%S0", CC_NO_CARRY }
1886 /* SHIFT_LSHIFTRT */
1888 { "shlr.b\t#2,%X0", CC_NO_CARRY },
1889 { "shlr.w\t#2,%T0", CC_NO_CARRY },
1890 { "shlr.l\t#2,%S0", CC_NO_CARRY }
1892 /* SHIFT_ASHIFTRT */
1894 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1895 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
1896 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
1900 /* Rotates are organized by which shift they'll be used in implementing.
1901 There's no need to record whether the cc is valid afterwards because
1902 it is the AND insn that will decide this. */
1904 static const char *const rotate_one[2][3][3] =
1911 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
1914 /* SHIFT_LSHIFTRT */
1917 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
1920 /* SHIFT_ASHIFTRT */
1923 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
1935 /* SHIFT_LSHIFTRT */
1941 /* SHIFT_ASHIFTRT */
1950 static const char *const rotate_two[3][3] =
1958 /* SHIFT_LSHIFTRT */
1964 /* SHIFT_ASHIFTRT */
1973 /* Shift algorithm. */
1976 /* The number of bits to be shifted by shift1 and shift2. Valid
1977 when ALG is SHIFT_SPECIAL. */
1978 unsigned int remainder;
1980 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
1981 const char *special;
1983 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
1984 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
1987 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
1988 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
1991 /* Valid CC flags. */
1995 static enum shift_alg get_shift_alg PARAMS ((enum shift_type,
1996 enum shift_mode, int,
1997 struct shift_info *));
1999 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
2000 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
2001 We don't achieve maximum efficiency in all cases, but the hooks are here
2004 For now we just use lots of switch statements. Since we don't even come
2005 close to supporting all the cases, this is simplest. If this function ever
2006 gets too big, perhaps resort to a more table based lookup. Of course,
2007 at this point you may just wish to do it all in rtl.
2009 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2010 1,2,3,4 will be inlined (1,2 for SI). */
2012 static enum shift_alg
2013 get_shift_alg (shift_type, shift_mode, count, info)
2014 enum shift_type shift_type;
2015 enum shift_mode shift_mode;
2017 struct shift_info *info;
2019 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
2020 It is up to the caller to know that looping clobbers cc. */
2021 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2023 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2025 info->shift2 = NULL;
2026 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2028 /* Now look for cases we want to optimize. */
2034 return SHIFT_INLINE;
2037 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
2038 fast as SHIFT_ROT_AND, plus CC is valid. */
2039 if (TARGET_H8300S && count <= 6)
2040 return SHIFT_INLINE;
2042 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2043 through the entire value. */
2044 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2046 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2047 info->cc_valid_p = 0;
2048 return SHIFT_SPECIAL;
2051 /* Other ASHIFTRTs are too much of a pain. */
2052 if (shift_type == SHIFT_ASHIFTRT)
2055 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */
2056 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2058 info->shift2 = rotate_two[shift_type][shift_mode];
2059 info->cc_valid_p = 0;
2060 return SHIFT_ROT_AND;
2065 return SHIFT_INLINE;
2066 else if (TARGET_H8300S && count <= 7)
2067 return SHIFT_INLINE;
2068 else if (count == 7)
2070 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2072 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2073 info->cc_valid_p = 0;
2074 return SHIFT_SPECIAL;
2077 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2079 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2080 info->cc_valid_p = 0;
2081 return SHIFT_SPECIAL;
2084 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2086 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2087 info->cc_valid_p = 0;
2088 return SHIFT_SPECIAL;
2091 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2093 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2094 info->cc_valid_p = 0;
2095 return SHIFT_SPECIAL;
2098 if (shift_type == SHIFT_ASHIFTRT)
2100 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2101 info->cc_valid_p = 0;
2102 return SHIFT_SPECIAL;
2105 else if (count == 8)
2110 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2111 info->cc_valid_p = 0;
2112 return SHIFT_SPECIAL;
2113 case SHIFT_LSHIFTRT:
2114 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2115 info->cc_valid_p = 0;
2116 return SHIFT_SPECIAL;
2117 case SHIFT_ASHIFTRT:
2119 info->special = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0";
2121 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2122 info->cc_valid_p = 0;
2123 return SHIFT_SPECIAL;
2126 else if (count == 9)
2131 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
2132 info->cc_valid_p = 0;
2133 return SHIFT_SPECIAL;
2134 case SHIFT_LSHIFTRT:
2135 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
2136 info->cc_valid_p = 0;
2137 return SHIFT_SPECIAL;
2138 case SHIFT_ASHIFTRT:
2140 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
2142 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
2143 info->cc_valid_p = 0;
2144 return SHIFT_SPECIAL;
2147 else if (count == 10)
2153 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0";
2155 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2156 info->cc_valid_p = 0;
2157 return SHIFT_SPECIAL;
2158 case SHIFT_LSHIFTRT:
2160 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
2162 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2163 info->cc_valid_p = 0;
2164 return SHIFT_SPECIAL;
2165 case SHIFT_ASHIFTRT:
2167 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2168 else if (TARGET_H8300H)
2169 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2170 else if (TARGET_H8300S)
2171 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
2172 info->cc_valid_p = 0;
2173 return SHIFT_SPECIAL;
2176 else if (count == 11)
2182 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
2184 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2185 info->cc_valid_p = 0;
2186 return SHIFT_SPECIAL;
2187 case SHIFT_LSHIFTRT:
2189 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
2191 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2192 info->cc_valid_p = 0;
2193 return SHIFT_SPECIAL;
2194 case SHIFT_ASHIFTRT:
2196 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2197 else if (TARGET_H8300H)
2198 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2199 else if (TARGET_H8300S)
2200 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
2201 info->cc_valid_p = 0;
2202 return SHIFT_SPECIAL;
2205 else if (count == 12)
2211 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
2213 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2214 info->cc_valid_p = 0;
2215 return SHIFT_SPECIAL;
2216 case SHIFT_LSHIFTRT:
2218 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
2220 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2221 info->cc_valid_p = 0;
2222 return SHIFT_SPECIAL;
2223 case SHIFT_ASHIFTRT:
2225 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2226 else if (TARGET_H8300H)
2227 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2228 else if (TARGET_H8300S)
2229 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
2230 info->cc_valid_p = 0;
2231 return SHIFT_SPECIAL;
2234 else if ((!TARGET_H8300 && (count == 13 || count == 14))
2237 if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2239 info->special = "shll\t%t0,%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2240 info->cc_valid_p = 0;
2241 return SHIFT_SPECIAL;
2243 else if (shift_type != SHIFT_ASHIFTRT)
2245 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2247 info->shift2 = rotate_two[shift_type][shift_mode];
2249 info->shift2 = NULL;
2250 info->cc_valid_p = 0;
2251 return SHIFT_ROT_AND;
2257 if (count <= (TARGET_H8300 ? 2 : 4))
2258 return SHIFT_INLINE;
2259 else if (TARGET_H8300S && count <= 10)
2260 return SHIFT_INLINE;
2261 else if (count == 8 && TARGET_H8300)
2266 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2267 info->cc_valid_p = 0;
2268 return SHIFT_SPECIAL;
2269 case SHIFT_LSHIFTRT:
2270 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2271 info->cc_valid_p = 0;
2272 return SHIFT_SPECIAL;
2273 case SHIFT_ASHIFTRT:
2274 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2275 info->cc_valid_p = 0;
2276 return SHIFT_SPECIAL;
2279 else if (count == 8 && !TARGET_H8300)
2284 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2285 info->cc_valid_p = 0;
2286 return SHIFT_SPECIAL;
2287 case SHIFT_LSHIFTRT:
2288 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2289 info->cc_valid_p = 0;
2290 return SHIFT_SPECIAL;
2291 case SHIFT_ASHIFTRT:
2292 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2293 info->cc_valid_p = 0;
2294 return SHIFT_SPECIAL;
2297 else if (count == 16)
2302 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2303 info->cc_valid_p = 0;
2304 return SHIFT_SPECIAL;
2305 case SHIFT_LSHIFTRT:
2306 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2307 info->cc_valid_p = 0;
2308 return SHIFT_SPECIAL;
2309 case SHIFT_ASHIFTRT:
2311 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2313 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2314 info->cc_valid_p = 0;
2315 return SHIFT_SPECIAL;
2318 else if (count == 17 && !TARGET_H8300)
2323 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
2324 info->cc_valid_p = 0;
2325 return SHIFT_SPECIAL;
2326 case SHIFT_LSHIFTRT:
2327 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
2328 info->cc_valid_p = 0;
2329 return SHIFT_SPECIAL;
2330 case SHIFT_ASHIFTRT:
2331 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
2332 info->cc_valid_p = 0;
2333 return SHIFT_SPECIAL;
2336 else if (count == 18 && !TARGET_H8300)
2342 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
2344 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2345 info->cc_valid_p = 0;
2346 return SHIFT_SPECIAL;
2347 case SHIFT_LSHIFTRT:
2349 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
2351 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2352 info->cc_valid_p = 0;
2353 return SHIFT_SPECIAL;
2354 case SHIFT_ASHIFTRT:
2356 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
2358 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2359 info->cc_valid_p = 0;
2360 return SHIFT_SPECIAL;
2363 else if (count == 19 && !TARGET_H8300)
2369 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
2371 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2372 info->cc_valid_p = 0;
2373 return SHIFT_SPECIAL;
2374 case SHIFT_LSHIFTRT:
2376 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
2378 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2379 info->cc_valid_p = 0;
2380 return SHIFT_SPECIAL;
2381 case SHIFT_ASHIFTRT:
2383 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
2385 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2386 info->cc_valid_p = 0;
2387 return SHIFT_SPECIAL;
2390 else if (count == 20 && TARGET_H8300S)
2395 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
2396 info->cc_valid_p = 0;
2397 return SHIFT_SPECIAL;
2398 case SHIFT_LSHIFTRT:
2399 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
2400 info->cc_valid_p = 0;
2401 return SHIFT_SPECIAL;
2402 case SHIFT_ASHIFTRT:
2403 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
2404 info->cc_valid_p = 0;
2405 return SHIFT_SPECIAL;
2408 else if (count == 24 && !TARGET_H8300)
2413 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2414 info->cc_valid_p = 0;
2415 return SHIFT_SPECIAL;
2416 case SHIFT_LSHIFTRT:
2417 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2418 info->cc_valid_p = 0;
2419 return SHIFT_SPECIAL;
2420 case SHIFT_ASHIFTRT:
2421 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2422 info->cc_valid_p = 0;
2423 return SHIFT_SPECIAL;
2426 else if (count >= 28 && count <= 30 && !TARGET_H8300)
2428 if (shift_type == SHIFT_ASHIFTRT)
2434 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2436 info->shift2 = rotate_two[shift_type][shift_mode];
2438 info->shift2 = NULL;
2439 info->cc_valid_p = 0;
2440 return SHIFT_ROT_AND;
2443 else if (count == 31)
2445 if (shift_type == SHIFT_ASHIFTRT)
2448 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2450 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2451 info->cc_valid_p = 0;
2452 return SHIFT_SPECIAL;
2458 if (shift_type == SHIFT_ASHIFT)
2459 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2461 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2462 info->cc_valid_p = 0;
2463 return SHIFT_SPECIAL;
2467 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2469 info->shift2 = rotate_two[shift_type][shift_mode];
2471 info->shift2 = NULL;
2472 info->cc_valid_p = 0;
2473 return SHIFT_ROT_AND;
2483 /* No fancy method is available. Just loop. */
2487 /* Emit the assembler code for doing shifts. */
2490 emit_a_shift (insn, operands)
2491 rtx insn ATTRIBUTE_UNUSED;
2494 static int loopend_lab;
2495 rtx shift = operands[3];
2496 enum machine_mode mode = GET_MODE (shift);
2497 enum rtx_code code = GET_CODE (shift);
2498 enum shift_type shift_type;
2499 enum shift_mode shift_mode;
2500 struct shift_info info;
2507 shift_mode = QIshift;
2510 shift_mode = HIshift;
2513 shift_mode = SIshift;
2522 shift_type = SHIFT_ASHIFTRT;
2525 shift_type = SHIFT_LSHIFTRT;
2528 shift_type = SHIFT_ASHIFT;
2534 if (GET_CODE (operands[2]) != CONST_INT)
2536 /* Indexing by reg, so have to loop and test at top. */
2537 output_asm_insn ("mov.b %X2,%X4", operands);
2538 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2540 /* Get the assembler code to do one shift. */
2541 get_shift_alg (shift_type, shift_mode, 1, &info);
2543 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2544 output_asm_insn (info.shift1, operands);
2545 output_asm_insn ("add #0xff,%X4", operands);
2546 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2547 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2553 int n = INTVAL (operands[2]);
2556 /* If the count is negative, make it 0. */
2559 /* If the count is too big, truncate it.
2560 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2561 do the intuitive thing. */
2562 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
2563 n = GET_MODE_BITSIZE (mode);
2565 alg = get_shift_alg (shift_type, shift_mode, n, &info);
2570 /* Emit two bit shifts first. */
2571 while (n > 1 && info.shift2 != NULL)
2573 output_asm_insn (info.shift2, operands);
2577 /* Now emit one bit shifts for any residual. */
2580 output_asm_insn (info.shift1, operands);
2584 /* Keep track of CC. */
2585 if (info.cc_valid_p)
2587 cc_status.value1 = operands[0];
2588 cc_status.flags |= info.cc_valid_p;
2594 int m = GET_MODE_BITSIZE (mode) - n;
2595 int mask = (shift_type == SHIFT_ASHIFT
2596 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2597 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2600 /* Not all possibilities of rotate are supported. They shouldn't
2601 be generated, but let's watch for 'em. */
2602 if (info.shift1 == 0)
2605 /* Emit two bit rotates first. */
2606 while (m > 1 && info.shift2 != NULL)
2608 output_asm_insn (info.shift2, operands);
2612 /* Now single bit rotates for any residual. */
2615 output_asm_insn (info.shift1, operands);
2619 /* Now mask off the high bits. */
2625 sprintf (insn_buf, "and\t#%d,%%X0", mask);
2626 cc_status.value1 = operands[0];
2627 cc_status.flags |= CC_NO_CARRY;
2630 sprintf (insn_buf, "and\t#%d,%%s0\n\tand\t#%d,%%t0",
2631 mask & 255, mask >> 8);
2641 sprintf (insn_buf, "and.%c\t#%d,%%%c0",
2642 "bwl"[shift_mode], mask,
2643 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2644 cc_status.value1 = operands[0];
2645 cc_status.flags |= CC_NO_CARRY;
2647 output_asm_insn (insn_buf, operands);
2652 output_asm_insn (info.special, operands);
2656 /* A loop to shift by a "large" constant value.
2657 If we have shift-by-2 insns, use them. */
2658 if (info.shift2 != NULL)
2660 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2661 names_big[REGNO (operands[4])]);
2662 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2663 output_asm_insn (info.shift2, operands);
2664 output_asm_insn ("add #0xff,%X4", operands);
2665 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2667 output_asm_insn (info.shift1, operands);
2671 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2672 names_big[REGNO (operands[4])]);
2673 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2674 output_asm_insn (info.shift1, operands);
2675 output_asm_insn ("add #0xff,%X4", operands);
2676 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2686 /* A rotation by a non-constant will cause a loop to be generated, in
2687 which a rotation by one bit is used. A rotation by a constant,
2688 including the one in the loop, will be taken care of by
2689 emit_a_rotate () at the insn emit time. */
2692 expand_a_rotate (code, operands)
2696 rtx dst = operands[0];
2697 rtx src = operands[1];
2698 rtx rotate_amount = operands[2];
2699 enum machine_mode mode = GET_MODE (dst);
2702 /* We rotate in place. */
2703 emit_move_insn (dst, src);
2705 if (GET_CODE (rotate_amount) != CONST_INT)
2707 rtx counter = gen_reg_rtx (QImode);
2708 rtx start_label = gen_label_rtx ();
2709 rtx end_label = gen_label_rtx ();
2711 /* If the rotate amount is less than or equal to 0,
2712 we go out of the loop. */
2713 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0),
2714 LE, NULL_RTX, QImode, 0, 0, end_label);
2716 /* Initialize the loop counter. */
2717 emit_move_insn (counter, rotate_amount);
2719 emit_label (start_label);
2721 /* Rotate by one bit. */
2722 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
2723 emit_insn (gen_rtx_SET (mode, dst, tmp));
2725 /* Decrement the counter by 1. */
2726 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
2727 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
2729 /* If the loop counter is non-zero, we go back to the beginning
2731 emit_cmp_and_jump_insns (counter, GEN_INT (0),
2732 NE, NULL_RTX, QImode, 1, 0, start_label);
2734 emit_label (end_label);
2738 /* Rotate by AMOUNT bits. */
2739 tmp = gen_rtx (code, mode, dst, rotate_amount);
2740 emit_insn (gen_rtx_SET (mode, dst, tmp));
2746 /* Emit rotate insns. */
2749 emit_a_rotate (code, operands)
2753 rtx dst = operands[0];
2754 rtx rotate_amount = operands[2];
2755 enum shift_mode rotate_mode;
2756 enum shift_type rotate_type;
2757 const char *insn_buf;
2760 enum machine_mode mode = GET_MODE (dst);
2762 if (GET_CODE (rotate_amount) != CONST_INT)
2768 rotate_mode = QIshift;
2771 rotate_mode = HIshift;
2774 rotate_mode = SIshift;
2783 rotate_type = SHIFT_ASHIFT;
2786 rotate_type = SHIFT_LSHIFTRT;
2792 amount = INTVAL (rotate_amount);
2794 /* Clean up AMOUNT. */
2797 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
2798 amount = GET_MODE_BITSIZE (mode);
2800 /* Determine the faster direction. After this phase, amount will be
2801 at most a half of GET_MODE_BITSIZE (mode). */
2802 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
2804 /* Flip the direction. */
2805 amount = GET_MODE_BITSIZE (mode) - amount;
2807 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2810 /* See if a byte swap (in HImode) or a word swap (in SImode) can
2811 boost up the rotation. */
2812 if ((mode == HImode && TARGET_H8300 && amount >= 5)
2813 || (mode == HImode && TARGET_H8300H && amount >= 6)
2814 || (mode == HImode && TARGET_H8300S && amount == 8)
2815 || (mode == SImode && TARGET_H8300H && amount >= 10)
2816 || (mode == SImode && TARGET_H8300S && amount >= 13))
2821 /* This code works on any family. */
2822 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
2823 output_asm_insn (insn_buf, operands);
2827 /* This code works on the H8/300H and H8/S. */
2828 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
2829 output_asm_insn (insn_buf, operands);
2836 /* Adjust AMOUNT and flip the direction. */
2837 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
2839 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2842 /* Emit rotate insns. */
2843 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
2846 insn_buf = rotate_two[rotate_type][rotate_mode];
2848 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2850 for (; amount >= bits; amount -= bits)
2851 output_asm_insn (insn_buf, operands);
2857 /* Fix the operands of a gen_xxx so that it could become a bit
2861 fix_bit_operand (operands, what, type)
2866 /* The bit_operand predicate accepts any memory during RTL generation, but
2867 only 'U' memory afterwards, so if this is a MEM operand, we must force
2868 it to be valid for 'U' by reloading the address. */
2870 if (GET_CODE (operands[2]) == CONST_INT)
2872 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
2874 /* Ok to have a memory dest. */
2875 if (GET_CODE (operands[0]) == MEM
2876 && !EXTRA_CONSTRAINT (operands[0], 'U'))
2878 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
2879 copy_to_mode_reg (Pmode,
2880 XEXP (operands[0], 0)));
2881 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2885 if (GET_CODE (operands[1]) == MEM
2886 && !EXTRA_CONSTRAINT (operands[1], 'U'))
2888 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
2889 copy_to_mode_reg (Pmode,
2890 XEXP (operands[1], 0)));
2891 MEM_COPY_ATTRIBUTES (mem, operands[0]);
2898 /* Dest and src op must be register. */
2900 operands[1] = force_reg (QImode, operands[1]);
2902 rtx res = gen_reg_rtx (QImode);
2903 emit_insn (gen_rtx_SET (VOIDmode, res,
2904 gen_rtx (type, QImode, operands[1], operands[2])));
2905 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
2910 /* Return nonzero if FUNC is an interrupt function as specified
2911 by the "interrupt" attribute. */
2914 h8300_interrupt_function_p (func)
2919 if (TREE_CODE (func) != FUNCTION_DECL)
2922 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
2923 return a != NULL_TREE;
2926 /* Return nonzero if FUNC is an OS_Task function as specified
2927 by the "OS_Task" attribute. */
2930 h8300_os_task_function_p (func)
2935 if (TREE_CODE (func) != FUNCTION_DECL)
2938 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
2939 return a != NULL_TREE;
2942 /* Return nonzero if FUNC is a monitor function as specified
2943 by the "monitor" attribute. */
2946 h8300_monitor_function_p (func)
2951 if (TREE_CODE (func) != FUNCTION_DECL)
2954 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
2955 return a != NULL_TREE;
2958 /* Return nonzero if FUNC is a function that should be called
2959 through the function vector. */
2962 h8300_funcvec_function_p (func)
2967 if (TREE_CODE (func) != FUNCTION_DECL)
2970 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
2971 return a != NULL_TREE;
2974 /* Return nonzero if DECL is a variable that's in the eight bit
2978 h8300_eightbit_data_p (decl)
2983 if (TREE_CODE (decl) != VAR_DECL)
2986 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
2987 return a != NULL_TREE;
2990 /* Return nonzero if DECL is a variable that's in the tiny
2994 h8300_tiny_data_p (decl)
2999 if (TREE_CODE (decl) != VAR_DECL)
3002 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
3003 return a != NULL_TREE;
3006 /* Return nonzero if ATTR is a valid attribute for DECL.
3007 ATTRIBUTES are any existing attributes and ARGS are the arguments
3010 Supported attributes:
3012 interrupt_handler: output a prologue and epilogue suitable for an
3015 function_vector: This function should be called through the
3018 eightbit_data: This variable lives in the 8-bit data area and can
3019 be referenced with 8-bit absolute memory addresses.
3021 tiny_data: This variable lives in the tiny data area and can be
3022 referenced with 16-bit absolute memory references. */
3025 h8300_valid_machine_decl_attribute (decl, attributes, attr, args)
3027 tree attributes ATTRIBUTE_UNUSED;
3031 if (args != NULL_TREE)
3034 if (is_attribute_p ("interrupt_handler", attr)
3035 || is_attribute_p ("OS_Task", attr)
3036 || is_attribute_p ("monitor", attr)
3037 || is_attribute_p ("function_vector", attr))
3038 return TREE_CODE (decl) == FUNCTION_DECL;
3040 if (is_attribute_p ("eightbit_data", attr)
3041 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3043 if (DECL_INITIAL (decl) == NULL_TREE)
3045 warning ("Only initialized variables can be placed into the 8-bit area.");
3048 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3052 if (is_attribute_p ("tiny_data", attr)
3053 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3055 if (DECL_INITIAL (decl) == NULL_TREE)
3057 warning ("Only initialized variables can be placed into the 8-bit area.");
3060 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3068 h8300_encode_label (decl)
3071 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3072 int len = strlen (str);
3075 newstr = ggc_alloc_string (NULL, len + 1);
3077 strcpy (newstr + 1, str);
3079 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3083 output_simode_bld (bild, log2, operands)
3088 /* Clear the destination register. */
3089 if (TARGET_H8300H || TARGET_H8300S)
3090 output_asm_insn ("sub.l\t%S0,%S0", operands);
3092 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3094 /* Get the bit number we want to load. */
3096 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3098 /* Now output the bit load or bit inverse load, and store it in
3101 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3103 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3109 /* Given INSN and its current length LENGTH, return the adjustment
3110 (in bytes) to correctly compute INSN's length.
3112 We use this to get the lengths of various memory references correct. */
3115 h8300_adjust_insn_length (insn, length)
3117 int length ATTRIBUTE_UNUSED;
3121 /* We must filter these ou before calling get_attr_adjust_length. */
3122 if (GET_CODE (PATTERN (insn)) == USE
3123 || GET_CODE (PATTERN (insn)) == CLOBBER
3124 || GET_CODE (PATTERN (insn)) == SEQUENCE
3125 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3126 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3129 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3132 pat = PATTERN (insn);
3134 /* Adjust length for reg->mem and mem->reg copies. */
3135 if (GET_CODE (pat) == SET
3136 && (GET_CODE (SET_SRC (pat)) == MEM
3137 || GET_CODE (SET_DEST (pat)) == MEM))
3139 /* This insn might need a length adjustment. */
3142 if (GET_CODE (SET_SRC (pat)) == MEM)
3143 addr = XEXP (SET_SRC (pat), 0);
3145 addr = XEXP (SET_DEST (pat), 0);
3147 /* On the H8/300, only one adjustment is necessary; if the
3148 address mode is register indirect, then this insn is two
3149 bytes shorter than indicated in the machine description. */
3150 if (TARGET_H8300 && GET_CODE (addr) == REG)
3153 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3154 indicated in the machine description. */
3155 if ((TARGET_H8300H || TARGET_H8300S)
3156 && GET_CODE (addr) == REG)
3159 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3160 bytes shorter than indicated in the machine description. */
3161 if ((TARGET_H8300H || TARGET_H8300S)
3162 && GET_CODE (addr) == PLUS
3163 && GET_CODE (XEXP (addr, 0)) == REG
3164 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3165 && INTVAL (XEXP (addr, 1)) > -32768
3166 && INTVAL (XEXP (addr, 1)) < 32767)
3169 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3170 more general abs:24. */
3171 if ((TARGET_H8300H || TARGET_H8300S)
3172 && GET_CODE (addr) == SYMBOL_REF
3173 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3177 /* Loading some constants needs adjustment. */
3178 if (GET_CODE (pat) == SET
3179 && GET_CODE (SET_SRC (pat)) == CONST_INT
3180 && GET_MODE (SET_DEST (pat)) == SImode
3181 && INTVAL (SET_SRC (pat)) != 0)
3183 int val = INTVAL (SET_SRC (pat));
3186 && ((val & 0xffff) == 0
3187 || ((val >> 16) & 0xffff) == 0))
3190 if (TARGET_H8300H || TARGET_H8300S)
3192 if (val == (val & 0xff)
3193 || val == (val & 0xff00))
3196 if (val == -4 || val == -2 || val == -1)
3201 /* Shifts need various adjustments. */
3202 if (GET_CODE (pat) == PARALLEL
3203 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3204 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3205 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3206 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3208 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3209 enum machine_mode mode = GET_MODE (src);
3212 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3215 shift = INTVAL (XEXP (src, 1));
3216 /* According to ANSI, negative shift is undefined. It is
3217 considered to be zero in this case (see function
3218 emit_a_shift above). */
3222 /* QImode shifts by small constants take one insn
3223 per shift. So the adjustment is 20 (md length) -
3225 if (mode == QImode && shift <= 4)
3226 return -(20 - shift * 2);
3228 /* Similarly for HImode and SImode shifts by
3229 small constants on the H8/300H and H8/300S. */
3230 if ((TARGET_H8300H || TARGET_H8300S)
3231 && (mode == HImode || mode == SImode) && shift <= 4)
3232 return -(20 - shift * 2);
3234 /* HImode shifts by small constants for the H8/300. */
3235 if (mode == HImode && shift <= 4)
3236 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3238 /* SImode shifts by small constants for the H8/300. */
3239 if (mode == SImode && shift <= 2)
3240 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3242 /* XXX ??? Could check for more shift/rotate cases here. */
3245 /* Rotations need various adjustments. */
3246 if (GET_CODE (pat) == SET
3247 && (GET_CODE (SET_SRC (pat)) == ROTATE
3248 || GET_CODE (SET_SRC (pat)) == ROTATERT))
3250 rtx src = SET_SRC (pat);
3251 enum machine_mode mode = GET_MODE (src);
3255 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3258 amount = INTVAL (XEXP (src, 1));
3260 /* Clean up AMOUNT. */
3263 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3264 amount = GET_MODE_BITSIZE (mode);
3266 /* Determine the faster direction. After this phase, amount
3267 will be at most a half of GET_MODE_BITSIZE (mode). */
3268 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
3269 /* Flip the direction. */
3270 amount = GET_MODE_BITSIZE (mode) - amount;
3272 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3273 boost up the rotation. */
3274 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3275 || (mode == HImode && TARGET_H8300H && amount >= 6)
3276 || (mode == HImode && TARGET_H8300S && amount == 8)
3277 || (mode == SImode && TARGET_H8300H && amount >= 10)
3278 || (mode == SImode && TARGET_H8300S && amount >= 13))
3280 /* Adjust AMOUNT and flip the direction. */
3281 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3285 /* We use 2-bit rotatations on the H8/S. */
3287 amount = amount / 2 + amount % 2;
3289 /* The H8/300 uses three insns to rotate one bit, taking 6
3291 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
3293 return -(20 - states);