1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg PARAMS ((rtx, int));
50 static int h8300_interrupt_function_p PARAMS ((tree));
51 static int h8300_monitor_function_p PARAMS ((tree));
52 static int h8300_os_task_function_p PARAMS ((tree));
53 static void dosize PARAMS ((int, unsigned int));
54 static int round_frame_size PARAMS ((int));
55 static unsigned int compute_saved_regs PARAMS ((void));
56 static void push PARAMS ((int));
57 static void pop PARAMS ((int));
58 static const char *cond_string PARAMS ((enum rtx_code));
59 static unsigned int h8300_asm_insn_count PARAMS ((const char *));
60 const struct attribute_spec h8300_attribute_table[];
61 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
62 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
63 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
64 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
65 static void h8300_insert_attributes PARAMS ((tree, tree *));
66 #ifndef OBJECT_FORMAT_ELF
67 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
69 static void h8300_encode_section_info PARAMS ((tree, rtx, int));
70 static int const_costs PARAMS ((rtx, enum rtx_code, enum rtx_code));
71 static int h8300_and_costs PARAMS ((rtx));
72 static int h8300_shift_costs PARAMS ((rtx));
73 static bool h8300_rtx_costs PARAMS ((rtx, int, int, int *));
75 /* CPU_TYPE, says what cpu we're compiling for. */
78 /* True if a #pragma interrupt has been seen for the current function. */
79 static int pragma_interrupt;
81 /* True if a #pragma saveall has been seen for the current function. */
82 static int pragma_saveall;
84 static const char *const names_big[] =
85 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
87 static const char *const names_extended[] =
88 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
90 static const char *const names_upper_extended[] =
91 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
93 /* Points to one of the above. */
94 /* ??? The above could be put in an array indexed by CPU_TYPE. */
95 const char * const *h8_reg_names;
97 /* Various operations needed by the following, indexed by CPU_TYPE. */
99 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
101 /* Machine-specific symbol_ref flags. */
102 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
103 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
104 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
106 /* Initialize the GCC target structure. */
107 #undef TARGET_ATTRIBUTE_TABLE
108 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
110 #undef TARGET_ASM_ALIGNED_HI_OP
111 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
113 #undef TARGET_ASM_FUNCTION_EPILOGUE
114 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
115 #undef TARGET_ENCODE_SECTION_INFO
116 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
118 #undef TARGET_INSERT_ATTRIBUTES
119 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
121 #undef TARGET_RTX_COSTS
122 #define TARGET_RTX_COSTS h8300_rtx_costs
124 struct gcc_target targetm = TARGET_INITIALIZER;
126 /* See below where shifts are handled for explanation of this enum. */
136 /* Symbols of the various shifts which can be used as indices. */
140 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
143 /* Macros to keep the shift algorithm tables small. */
144 #define INL SHIFT_INLINE
145 #define ROT SHIFT_ROT_AND
146 #define LOP SHIFT_LOOP
147 #define SPC SHIFT_SPECIAL
149 /* The shift algorithms for each machine, mode, shift type, and shift
150 count are defined below. The three tables below correspond to
151 QImode, HImode, and SImode, respectively. Each table is organized
152 by, in the order of indices, machine, shift type, and shift count. */
154 static enum shift_alg shift_alg_qi[3][3][8] = {
157 /* 0 1 2 3 4 5 6 7 */
158 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
159 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
160 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
164 /* 0 1 2 3 4 5 6 7 */
165 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
166 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
167 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
171 /* 0 1 2 3 4 5 6 7 */
172 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
173 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
178 static enum shift_alg shift_alg_hi[3][3][16] = {
181 /* 0 1 2 3 4 5 6 7 */
182 /* 8 9 10 11 12 13 14 15 */
183 { INL, INL, INL, INL, INL, INL, INL, SPC,
184 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
185 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
187 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
188 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
192 /* 0 1 2 3 4 5 6 7 */
193 /* 8 9 10 11 12 13 14 15 */
194 { INL, INL, INL, INL, INL, INL, INL, SPC,
195 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
196 { INL, INL, INL, INL, INL, INL, INL, SPC,
197 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
198 { INL, INL, INL, INL, INL, INL, INL, SPC,
199 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
203 /* 0 1 2 3 4 5 6 7 */
204 /* 8 9 10 11 12 13 14 15 */
205 { INL, INL, INL, INL, INL, INL, INL, INL,
206 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
207 { INL, INL, INL, INL, INL, INL, INL, INL,
208 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
209 { INL, INL, INL, INL, INL, INL, INL, INL,
210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
214 static enum shift_alg shift_alg_si[3][3][32] = {
217 /* 0 1 2 3 4 5 6 7 */
218 /* 8 9 10 11 12 13 14 15 */
219 /* 16 17 18 19 20 21 22 23 */
220 /* 24 25 26 27 28 29 30 31 */
221 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
222 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
223 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
224 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
225 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
227 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
228 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
230 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
231 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
232 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
236 /* 0 1 2 3 4 5 6 7 */
237 /* 8 9 10 11 12 13 14 15 */
238 /* 16 17 18 19 20 21 22 23 */
239 /* 24 25 26 27 28 29 30 31 */
240 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
241 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
242 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
243 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
244 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
245 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
246 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
247 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
248 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
249 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
250 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
251 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
255 /* 0 1 2 3 4 5 6 7 */
256 /* 8 9 10 11 12 13 14 15 */
257 /* 16 17 18 19 20 21 22 23 */
258 /* 24 25 26 27 28 29 30 31 */
259 { INL, INL, INL, INL, INL, INL, INL, INL,
260 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
261 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
262 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
263 { INL, INL, INL, INL, INL, INL, INL, INL,
264 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
265 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
266 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
267 { INL, INL, INL, INL, INL, INL, INL, INL,
268 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
269 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
270 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
286 /* Initialize various cpu specific globals at start up. */
291 static const char *const h8_push_ops[2] = { "push" , "push.l" };
292 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
293 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
297 cpu_type = (int) CPU_H8300;
298 h8_reg_names = names_big;
302 /* For this we treat the H8/300H and H8S the same. */
303 cpu_type = (int) CPU_H8300H;
304 h8_reg_names = names_extended;
306 h8_push_op = h8_push_ops[cpu_type];
307 h8_pop_op = h8_pop_ops[cpu_type];
308 h8_mov_op = h8_mov_ops[cpu_type];
310 if (!TARGET_H8300S && TARGET_MAC)
312 error ("-ms2600 is used without -ms");
313 target_flags |= MASK_H8300S;
316 if (TARGET_H8300 && TARGET_NORMAL_MODE)
318 error ("-mn is used without -mh or -ms");
319 target_flags ^= MASK_NORMAL_MODE;
322 /* Some of the shifts are optimized for speed by default.
323 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
324 If optimizing for size, change shift_alg for those shift to
329 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
330 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
331 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
332 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
334 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
335 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
337 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
338 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
341 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
342 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
344 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
345 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
347 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
348 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
349 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
350 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
353 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
362 static const char *const names_small[] = {
363 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
364 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
367 return names_small[REGNO (x) * 2 + b];
370 /* REGNO must be saved/restored across calls if this macro is true. */
372 #define WORD_REG_USED(regno) \
374 /* No need to save registers if this function will not return. */ \
375 && ! TREE_THIS_VOLATILE (current_function_decl) \
377 /* Save any call saved register that was used. */ \
378 || (regs_ever_live[regno] && !call_used_regs[regno]) \
379 /* Save the frame pointer if it was used. */ \
380 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
381 /* Save any register used in an interrupt handler. */ \
382 || (h8300_current_function_interrupt_function_p () \
383 && regs_ever_live[regno]) \
384 /* Save call clobbered registers in non-leaf interrupt \
386 || (h8300_current_function_interrupt_function_p () \
387 && call_used_regs[regno] \
388 && !current_function_is_leaf)))
390 /* Output assembly language to FILE for the operation OP with operand size
391 SIZE to adjust the stack pointer. */
398 /* H8/300 cannot add/subtract a large constant with a single
399 instruction. If a temporary register is available, load the
400 constant to it and then do the addition. */
403 && !h8300_current_function_interrupt_function_p ()
404 && !(current_function_needs_context && sign < 0))
407 rtx r3 = gen_rtx_REG (Pmode, 3);
408 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
409 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
410 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
414 /* The stack adjustment made here is further optimized by the
415 splitter. In case of H8/300, the splitter always splits the
416 addition emitted here to make the adjustment
418 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
419 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
423 /* Round up frame size SIZE. */
426 round_frame_size (size)
429 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
430 & -STACK_BOUNDARY / BITS_PER_UNIT);
433 /* Compute which registers to push/pop.
434 Return a bit vector of registers. */
437 compute_saved_regs ()
439 unsigned int saved_regs = 0;
442 /* Construct a bit vector of registers to be pushed/popped. */
443 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
445 if (WORD_REG_USED (regno))
446 saved_regs |= 1 << regno;
449 /* Don't push/pop the frame pointer as it is treated separately. */
450 if (frame_pointer_needed)
451 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
456 /* Emit an insn to push register RN. */
462 rtx reg = gen_rtx_REG (word_mode, rn);
466 x = gen_push_h8300 (reg);
468 x = gen_push_h8300hs (reg);
470 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
473 /* Emit an insn to pop register RN. */
479 rtx reg = gen_rtx_REG (word_mode, rn);
483 x = gen_pop_h8300 (reg);
485 x = gen_pop_h8300hs (reg);
487 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
490 /* This is what the stack looks like after the prolog of
491 a function with a frame has been set up:
497 <saved registers> <- sp
499 This is what the stack looks like after the prolog of
500 a function which doesn't have a frame:
505 <saved registers> <- sp
508 /* Generate RTL code for the function prologue. */
511 h8300_expand_prologue ()
517 /* If the current function has the OS_Task attribute set, then
518 we have a naked prologue. */
519 if (h8300_os_task_function_p (current_function_decl))
522 if (h8300_monitor_function_p (current_function_decl))
523 /* My understanding of monitor functions is they act just like
524 interrupt functions, except the prologue must mask
526 emit_insn (gen_monitor_prologue ());
528 if (frame_pointer_needed)
531 push (FRAME_POINTER_REGNUM);
532 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
535 /* Leave room for locals. */
536 dosize (-1, round_frame_size (get_frame_size ()));
538 /* Push the rest of the registers in ascending order. */
539 saved_regs = compute_saved_regs ();
540 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
543 if (saved_regs & (1 << regno))
547 /* See how many registers we can push at the same time. */
548 if ((regno == 0 || regno == 4)
549 && ((saved_regs >> regno) & 0x0f) == 0x0f)
552 else if ((regno == 0 || regno == 4)
553 && ((saved_regs >> regno) & 0x07) == 0x07)
556 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
557 && ((saved_regs >> regno) & 0x03) == 0x03)
567 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
568 gen_rtx_REG (SImode, regno + 1)));
571 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
572 gen_rtx_REG (SImode, regno + 1),
573 gen_rtx_REG (SImode, regno + 2)));
576 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
577 gen_rtx_REG (SImode, regno + 1),
578 gen_rtx_REG (SImode, regno + 2),
579 gen_rtx_REG (SImode, regno + 3)));
589 h8300_can_use_return_insn_p ()
591 return (reload_completed
592 && !frame_pointer_needed
593 && get_frame_size () == 0
594 && compute_saved_regs () == 0);
597 /* Generate RTL code for the function epilogue. */
600 h8300_expand_epilogue ()
606 if (h8300_os_task_function_p (current_function_decl))
607 /* OS_Task epilogues are nearly naked -- they just have an
611 /* Pop the saved registers in descending order. */
612 saved_regs = compute_saved_regs ();
613 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
616 if (saved_regs & (1 << regno))
620 /* See how many registers we can pop at the same time. */
621 if ((regno == 7 || regno == 3)
622 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
625 else if ((regno == 6 || regno == 2)
626 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
629 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
630 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
640 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
641 gen_rtx_REG (SImode, regno)));
644 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
645 gen_rtx_REG (SImode, regno - 1),
646 gen_rtx_REG (SImode, regno)));
649 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
650 gen_rtx_REG (SImode, regno - 2),
651 gen_rtx_REG (SImode, regno - 1),
652 gen_rtx_REG (SImode, regno)));
660 /* Deallocate locals. */
661 dosize (1, round_frame_size (get_frame_size ()));
663 /* Pop frame pointer if we had one. */
664 if (frame_pointer_needed)
665 pop (FRAME_POINTER_REGNUM);
668 /* Output assembly language code for the function epilogue. */
671 h8300_output_function_epilogue (file, size)
672 FILE *file ATTRIBUTE_UNUSED;
673 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
678 /* Return nonzero if the current function is an interrupt
682 h8300_current_function_interrupt_function_p ()
684 return (h8300_interrupt_function_p (current_function_decl)
685 || h8300_monitor_function_p (current_function_decl));
688 /* Output assembly code for the start of the file. */
691 asm_file_start (file)
694 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
695 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
698 fprintf (file, "; -Os\n");
700 fprintf (file, "; -O%d\n", optimize);
702 if (TARGET_NORMAL_MODE)
703 fprintf (file, "\n\t.h8300hn\n");
705 fprintf (file, "\n\t.h8300h\n");
706 else if (TARGET_H8300S)
707 if (TARGET_NORMAL_MODE)
708 fprintf (file, "\n\t.h8300sn\n");
710 fprintf (file, "\n\t.h8300s\n");
712 fprintf (file, "\n\n");
713 output_file_directive (file, main_input_filename);
716 /* Output assembly language code for the end of file. */
722 fprintf (file, "\t.end\n");
725 /* Return true if OP is a valid source operand for an integer move
729 general_operand_src (op, mode)
731 enum machine_mode mode;
733 if (GET_MODE (op) == mode
734 && GET_CODE (op) == MEM
735 && GET_CODE (XEXP (op, 0)) == POST_INC)
737 return general_operand (op, mode);
740 /* Return true if OP is a valid destination operand for an integer move
744 general_operand_dst (op, mode)
746 enum machine_mode mode;
748 if (GET_MODE (op) == mode
749 && GET_CODE (op) == MEM
750 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
752 return general_operand (op, mode);
755 /* Return true if OP is a constant that contains only one 1 in its
756 binary representation. */
759 single_one_operand (operand, mode)
761 enum machine_mode mode ATTRIBUTE_UNUSED;
763 if (GET_CODE (operand) == CONST_INT)
765 /* We really need to do this masking because 0x80 in QImode is
766 represented as -128 for example. */
767 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
774 /* Return true if OP is a constant that contains only one 0 in its
775 binary representation. */
778 single_zero_operand (operand, mode)
780 enum machine_mode mode ATTRIBUTE_UNUSED;
782 if (GET_CODE (operand) == CONST_INT)
784 /* We really need to do this masking because 0x80 in QImode is
785 represented as -128 for example. */
786 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
793 /* Return true if OP is a valid call operand. */
796 call_insn_operand (op, mode)
798 enum machine_mode mode ATTRIBUTE_UNUSED;
800 if (GET_CODE (op) == MEM)
802 rtx inside = XEXP (op, 0);
803 if (register_operand (inside, Pmode))
805 if (CONSTANT_ADDRESS_P (inside))
811 /* Return 1 if an addition/subtraction of a constant integer can be
812 transformed into two consecutive adds/subs that are faster than the
813 straightforward way. Otherwise, return 0. */
816 two_insn_adds_subs_operand (op, mode)
818 enum machine_mode mode;
820 if (GET_CODE (op) == CONST_INT)
822 HOST_WIDE_INT value = INTVAL (op);
824 /* Force VALUE to be positive so that we do not have to consider
825 the negative case. */
828 if (TARGET_H8300H || TARGET_H8300S)
830 /* A constant addition/subtraction takes 2 states in QImode,
831 4 states in HImode, and 6 states in SImode. Thus, the
832 only case we can win is when SImode is used, in which
833 case, two adds/subs are used, taking 4 states. */
843 /* We do not profit directly by splitting addition or
844 subtraction of 3 and 4. However, since these are
845 implemented as a sequence of adds or subs, they do not
846 clobber (cc0) unlike a sequence of add.b and add.x. */
857 /* Split an add of a small constant into two adds/subs insns.
859 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
860 instead of adds/subs. */
863 split_adds_subs (mode, operands)
864 enum machine_mode mode;
867 HOST_WIDE_INT val = INTVAL (operands[1]);
868 rtx reg = operands[0];
869 HOST_WIDE_INT sign = 1;
870 HOST_WIDE_INT amount;
871 rtx (*gen_add) (rtx, rtx, rtx);
873 /* Force VAL to be positive so that we do not have to consider the
884 gen_add = gen_addhi3;
888 gen_add = gen_addsi3;
895 /* Try different amounts in descending order. */
896 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
900 for (; val >= amount; val -= amount)
901 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
907 /* Return true if OP is a valid call operand, and OP represents
908 an operand for a small call (4 bytes instead of 6 bytes). */
911 small_call_insn_operand (op, mode)
913 enum machine_mode mode ATTRIBUTE_UNUSED;
915 if (GET_CODE (op) == MEM)
917 rtx inside = XEXP (op, 0);
919 /* Register indirect is a small call. */
920 if (register_operand (inside, Pmode))
923 /* A call through the function vector is a small call too. */
924 if (GET_CODE (inside) == SYMBOL_REF
925 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
928 /* Otherwise it's a large call. */
932 /* Return true if OP is a valid jump operand. */
935 jump_address_operand (op, mode)
937 enum machine_mode mode;
939 if (GET_CODE (op) == REG)
940 return mode == Pmode;
942 if (GET_CODE (op) == MEM)
944 rtx inside = XEXP (op, 0);
945 if (register_operand (inside, Pmode))
947 if (CONSTANT_ADDRESS_P (inside))
953 /* Recognize valid operands for bit-field instructions. */
955 extern int rtx_equal_function_value_matters;
958 bit_operand (op, mode)
960 enum machine_mode mode;
962 /* We can accept any general operand, except that MEM operands must
963 be limited to those that use addresses valid for the 'U' constraint. */
964 if (!general_operand (op, mode))
967 /* Accept any mem during RTL generation. Otherwise, the code that does
968 insv and extzv will think that we can not handle memory. However,
969 to avoid reload problems, we only accept 'U' MEM operands after RTL
970 generation. This means that any named pattern which uses this predicate
971 must force its operands to match 'U' before emitting RTL. */
973 if (GET_CODE (op) == REG)
975 if (GET_CODE (op) == SUBREG)
977 return (GET_CODE (op) == MEM
978 && EXTRA_CONSTRAINT (op, 'U'));
982 bit_memory_operand (op, mode)
984 enum machine_mode mode ATTRIBUTE_UNUSED;
986 return (GET_CODE (op) == MEM
987 && EXTRA_CONSTRAINT (op, 'U'));
990 /* Handle machine specific pragmas for compatibility with existing
991 compilers for the H8/300.
993 pragma saveall generates prologue/epilogue code which saves and
994 restores all the registers on function entry.
996 pragma interrupt saves and restores all registers, and exits with
997 an rte instruction rather than an rts. A pointer to a function
998 with this attribute may be safely used in an interrupt vector. */
1001 h8300_pr_interrupt (pfile)
1002 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1004 pragma_interrupt = 1;
1008 h8300_pr_saveall (pfile)
1009 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1014 /* If the next function argument with MODE and TYPE is to be passed in
1015 a register, return a reg RTX for the hard register in which to pass
1016 the argument. CUM represents the state after the last argument.
1017 If the argument is to be pushed, NULL_RTX is returned. */
1020 function_arg (cum, mode, type, named)
1021 CUMULATIVE_ARGS *cum;
1022 enum machine_mode mode;
1026 static const char *const hand_list[] = {
1045 rtx result = NULL_RTX;
1049 /* Never pass unnamed arguments in registers. */
1053 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1054 if (TARGET_QUICKCALL)
1057 /* If calling hand written assembler, use 4 regs of args. */
1060 const char * const *p;
1062 fname = XSTR (cum->libcall, 0);
1064 /* See if this libcall is one of the hand coded ones. */
1065 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1076 if (mode == BLKmode)
1077 size = int_size_in_bytes (type);
1079 size = GET_MODE_SIZE (mode);
1081 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1082 && cum->nbytes / UNITS_PER_WORD <= 3)
1083 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1089 /* Return the cost of the rtx R with code CODE. */
1092 const_costs (r, c, outer_code)
1095 enum rtx_code outer_code;
1101 HOST_WIDE_INT n = INTVAL (r);
1103 if (-4 <= n || n <= 4)
1113 return 0 + (outer_code == SET);
1116 if (TARGET_H8300H || TARGET_H8300S)
1117 return 0 + (outer_code == SET);
1144 if (GET_MODE (x) == QImode)
1147 if (GET_MODE (x) != HImode
1148 && GET_MODE (x) != SImode)
1153 operands[2] = XEXP (x, 1);
1155 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1159 h8300_shift_costs (x)
1164 if (GET_MODE (x) != QImode
1165 && GET_MODE (x) != HImode
1166 && GET_MODE (x) != SImode)
1171 operands[2] = XEXP (x, 1);
1173 return compute_a_shift_length (NULL, operands) / 2;
1177 h8300_rtx_costs (x, code, outer_code, total)
1179 int code, outer_code;
1185 *total = COSTS_N_INSNS (h8300_and_costs (x));
1188 /* We say that MOD and DIV are so expensive because otherwise we'll
1189 generate some really horrible code for division of a power of two. */
1202 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1207 if (GET_MODE (x) == HImode)
1214 *total = const_costs (x, code, outer_code);
1219 /* Documentation for the machine specific operand escapes:
1221 'E' like s but negative.
1222 'F' like t but negative.
1223 'G' constant just the negative
1224 'R' print operand as a byte:8 address if appropriate, else fall back to
1226 'S' print operand as a long word
1227 'T' print operand as a word
1228 'V' find the set bit, and print its number.
1229 'W' find the clear bit, and print its number.
1230 'X' print operand as a byte
1231 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1232 If this operand isn't a register, fall back to 'R' handling.
1234 'b' print the bit opcode
1235 'c' print the opcode corresponding to rtl
1236 'e' first word of 32 bit value - if reg, then least reg. if mem
1237 then least. if const then most sig word
1238 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1239 then +2. if const then least sig word
1240 'j' print operand as condition code.
1241 'k' print operand as reverse condition code.
1242 's' print as low byte of 16 bit value
1243 't' print as high byte of 16 bit value
1244 'w' print as low byte of 32 bit value
1245 'x' print as 2nd byte of 32 bit value
1246 'y' print as 3rd byte of 32 bit value
1247 'z' print as msb of 32 bit value
1250 /* Return assembly language string which identifies a comparison type. */
1283 /* Print operand X using operand code CODE to assembly language output file
1287 print_operand (file, x, code)
1292 /* This is used for communication between codes V,W,Z and Y. */
1298 switch (GET_CODE (x))
1301 fprintf (file, "%sl", names_big[REGNO (x)]);
1304 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1311 switch (GET_CODE (x))
1314 fprintf (file, "%sh", names_big[REGNO (x)]);
1317 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1324 if (GET_CODE (x) != CONST_INT)
1326 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1329 if (GET_CODE (x) == REG)
1330 fprintf (file, "%s", names_extended[REGNO (x)]);
1335 if (GET_CODE (x) == REG)
1336 fprintf (file, "%s", names_big[REGNO (x)]);
1341 bitint = exact_log2 (INTVAL (x) & 0xff);
1344 fprintf (file, "#%d", bitint);
1347 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1350 fprintf (file, "#%d", bitint);
1354 if (GET_CODE (x) == REG)
1355 fprintf (file, "%s", byte_reg (x, 0));
1362 if (GET_CODE (x) == REG)
1363 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1365 print_operand (file, x, 'R');
1369 bitint = INTVAL (x);
1370 fprintf (file, "#%d", bitint & 7);
1373 switch (GET_CODE (x))
1376 fprintf (file, "bor");
1379 fprintf (file, "bxor");
1382 fprintf (file, "band");
1389 switch (GET_CODE (x))
1392 fprintf (file, "or");
1395 fprintf (file, "xor");
1402 switch (GET_CODE (x))
1406 fprintf (file, "%s", names_big[REGNO (x)]);
1408 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1411 print_operand (file, x, 0);
1414 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1420 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1421 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1422 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1431 switch (GET_CODE (x))
1435 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1437 fprintf (file, "%s", names_big[REGNO (x)]);
1440 x = adjust_address (x, HImode, 2);
1441 print_operand (file, x, 0);
1444 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1450 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1451 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1452 fprintf (file, "#%ld", (val & 0xffff));
1460 fputs (cond_string (GET_CODE (x)), file);
1463 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1466 if (GET_CODE (x) == CONST_INT)
1467 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1469 fprintf (file, "%s", byte_reg (x, 0));
1472 if (GET_CODE (x) == CONST_INT)
1473 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1475 fprintf (file, "%s", byte_reg (x, 1));
1478 if (GET_CODE (x) != CONST_INT)
1480 fprintf (file, "%ld", INTVAL (x));
1483 if (GET_CODE (x) == CONST_INT)
1484 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1486 fprintf (file, "%s",
1487 byte_reg (x, TARGET_H8300 ? 2 : 0));
1490 if (GET_CODE (x) == CONST_INT)
1491 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1493 fprintf (file, "%s",
1494 byte_reg (x, TARGET_H8300 ? 3 : 1));
1497 if (GET_CODE (x) == CONST_INT)
1498 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1500 fprintf (file, "%s", byte_reg (x, 0));
1503 if (GET_CODE (x) == CONST_INT)
1504 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1506 fprintf (file, "%s", byte_reg (x, 1));
1511 switch (GET_CODE (x))
1514 switch (GET_MODE (x))
1517 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1518 fprintf (file, "%s", byte_reg (x, 0));
1519 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1520 fprintf (file, "%s", names_big[REGNO (x)]);
1524 fprintf (file, "%s", names_big[REGNO (x)]);
1528 fprintf (file, "%s", names_extended[REGNO (x)]);
1537 rtx addr = XEXP (x, 0);
1539 fprintf (file, "@");
1540 output_address (addr);
1542 /* We fall back from smaller addressing to larger
1543 addressing in various ways depending on CODE. */
1547 /* Used for mov.b and bit operations. */
1548 if (h8300_eightbit_constant_address_p (addr))
1550 fprintf (file, ":8");
1554 /* Fall through. We should not get here if we are
1555 processing bit operations on H8/300 or H8/300H
1556 because 'U' constraint does not allow bit
1557 operations on the tiny area on these machines. */
1561 /* Used for mov.w and mov.l. */
1562 if (h8300_tiny_constant_address_p (addr))
1563 fprintf (file, ":16");
1575 fprintf (file, "#");
1576 print_operand_address (file, x);
1582 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1583 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1584 fprintf (file, "#%ld", val);
1593 /* Output assembly language output for the address ADDR to FILE. */
1596 print_operand_address (file, addr)
1600 switch (GET_CODE (addr))
1603 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1607 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1611 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1615 fprintf (file, "(");
1616 if (GET_CODE (XEXP (addr, 0)) == REG)
1619 print_operand_address (file, XEXP (addr, 1));
1620 fprintf (file, ",");
1621 print_operand_address (file, XEXP (addr, 0));
1626 print_operand_address (file, XEXP (addr, 0));
1627 fprintf (file, "+");
1628 print_operand_address (file, XEXP (addr, 1));
1630 fprintf (file, ")");
1635 /* Since the H8/300 only has 16 bit pointers, negative values are also
1636 those >= 32768. This happens for example with pointer minus a
1637 constant. We don't want to turn (char *p - 2) into
1638 (char *p + 65534) because loop unrolling can build upon this
1639 (IE: char *p + 131068). */
1640 int n = INTVAL (addr);
1642 n = (int) (short) n;
1643 fprintf (file, "%d", n);
1648 output_addr_const (file, addr);
1653 /* Output all insn addresses and their sizes into the assembly language
1654 output file. This is helpful for debugging whether the length attributes
1655 in the md file are correct. This is not meant to be a user selectable
1659 final_prescan_insn (insn, operand, num_operands)
1660 rtx insn, *operand ATTRIBUTE_UNUSED;
1661 int num_operands ATTRIBUTE_UNUSED;
1663 /* This holds the last insn address. */
1664 static int last_insn_address = 0;
1666 const int uid = INSN_UID (insn);
1668 if (TARGET_RTL_DUMP)
1670 fprintf (asm_out_file, "\n****************");
1671 print_rtl (asm_out_file, PATTERN (insn));
1672 fprintf (asm_out_file, "\n");
1675 if (TARGET_ADDRESSES)
1677 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1678 INSN_ADDRESSES (uid) - last_insn_address);
1679 last_insn_address = INSN_ADDRESSES (uid);
1683 /* Prepare for an SI sized move. */
1689 rtx src = operands[1];
1690 rtx dst = operands[0];
1691 if (!reload_in_progress && !reload_completed)
1693 if (!register_operand (dst, GET_MODE (dst)))
1695 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1696 emit_move_insn (tmp, src);
1703 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1704 Define the offset between two registers, one to be eliminated, and
1705 the other its replacement, at the start of a routine. */
1708 h8300_initial_elimination_offset (from, to)
1712 /* The number of bytes that the return address takes on the stack. */
1713 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1715 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1716 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1717 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1718 offset = frame_pointer_needed * UNITS_PER_WORD;
1723 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1724 if (WORD_REG_USED (regno))
1725 offset += UNITS_PER_WORD;
1727 /* See the comments for get_frame_size. We need to round it up to
1730 offset += round_frame_size (get_frame_size ());
1732 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1733 /* Skip saved PC. */
1741 h8300_return_addr_rtx (count, frame)
1748 ret = gen_rtx_MEM (Pmode,
1749 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1750 else if (flag_omit_frame_pointer)
1753 ret = gen_rtx_MEM (Pmode,
1754 memory_address (Pmode,
1755 plus_constant (frame, UNITS_PER_WORD)));
1756 set_mem_alias_set (ret, get_frame_alias_set ());
1760 /* Update the condition code from the insn. */
1763 notice_update_cc (body, insn)
1769 switch (get_attr_cc (insn))
1772 /* Insn does not affect CC at all. */
1776 /* Insn does not change CC, but the 0'th operand has been changed. */
1777 if (cc_status.value1 != 0
1778 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1779 cc_status.value1 = 0;
1780 if (cc_status.value2 != 0
1781 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1782 cc_status.value2 = 0;
1786 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1787 The V flag is unusable. The C flag may or may not be known but
1788 that's ok because alter_cond will change tests to use EQ/NE. */
1790 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1791 set = single_set (insn);
1792 cc_status.value1 = SET_SRC (set);
1793 if (SET_DEST (set) != cc0_rtx)
1794 cc_status.value2 = SET_DEST (set);
1798 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1799 The C flag may or may not be known but that's ok because
1800 alter_cond will change tests to use EQ/NE. */
1802 cc_status.flags |= CC_NO_CARRY;
1803 set = single_set (insn);
1804 cc_status.value1 = SET_SRC (set);
1805 if (SET_DEST (set) != cc0_rtx)
1807 /* If the destination is STRICT_LOW_PART, strip off
1809 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1810 cc_status.value2 = XEXP (SET_DEST (set), 0);
1812 cc_status.value2 = SET_DEST (set);
1817 /* The insn is a compare instruction. */
1819 cc_status.value1 = SET_SRC (body);
1823 /* Insn doesn't leave CC in a usable state. */
1829 /* Return nonzero if X is a stack pointer. */
1832 stack_pointer_operand (x, mode)
1834 enum machine_mode mode ATTRIBUTE_UNUSED;
1836 return x == stack_pointer_rtx;
1839 /* Return nonzero if X is a constant whose absolute value is greater
1843 const_int_gt_2_operand (x, mode)
1845 enum machine_mode mode ATTRIBUTE_UNUSED;
1847 return (GET_CODE (x) == CONST_INT
1848 && abs (INTVAL (x)) > 2);
1851 /* Return nonzero if X is a constant whose absolute value is no
1855 const_int_ge_8_operand (x, mode)
1857 enum machine_mode mode ATTRIBUTE_UNUSED;
1859 return (GET_CODE (x) == CONST_INT
1860 && abs (INTVAL (x)) >= 8);
1863 /* Return nonzero if X is a constant expressible in QImode. */
1866 const_int_qi_operand (x, mode)
1868 enum machine_mode mode ATTRIBUTE_UNUSED;
1870 return (GET_CODE (x) == CONST_INT
1871 && (INTVAL (x) & 0xff) == INTVAL (x));
1874 /* Return nonzero if X is a constant expressible in HImode. */
1877 const_int_hi_operand (x, mode)
1879 enum machine_mode mode ATTRIBUTE_UNUSED;
1881 return (GET_CODE (x) == CONST_INT
1882 && (INTVAL (x) & 0xffff) == INTVAL (x));
1885 /* Return nonzero if X is a constant suitable for inc/dec. */
1888 incdec_operand (x, mode)
1890 enum machine_mode mode ATTRIBUTE_UNUSED;
1892 return (GET_CODE (x) == CONST_INT
1893 && (CONST_OK_FOR_M (INTVAL (x))
1894 || CONST_OK_FOR_O (INTVAL (x))));
1897 /* Return nonzero if X is either EQ or NE. */
1900 eqne_operator (x, mode)
1902 enum machine_mode mode ATTRIBUTE_UNUSED;
1904 enum rtx_code code = GET_CODE (x);
1906 return (code == EQ || code == NE);
1909 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1912 gtle_operator (x, mode)
1914 enum machine_mode mode ATTRIBUTE_UNUSED;
1916 enum rtx_code code = GET_CODE (x);
1918 return (code == GT || code == LE || code == GTU || code == LEU);
1921 /* Return nonzero if X is either GTU or LEU. */
1924 gtuleu_operator (x, mode)
1926 enum machine_mode mode ATTRIBUTE_UNUSED;
1928 enum rtx_code code = GET_CODE (x);
1930 return (code == GTU || code == LEU);
1933 /* Return nonzero if X is either IOR or XOR. */
1936 iorxor_operator (x, mode)
1938 enum machine_mode mode ATTRIBUTE_UNUSED;
1940 enum rtx_code code = GET_CODE (x);
1942 return (code == IOR || code == XOR);
1945 /* Recognize valid operators for bit instructions. */
1948 bit_operator (x, mode)
1950 enum machine_mode mode ATTRIBUTE_UNUSED;
1952 enum rtx_code code = GET_CODE (x);
1960 output_plussi (operands)
1963 enum machine_mode mode = GET_MODE (operands[0]);
1970 if (GET_CODE (operands[2]) == REG)
1971 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1973 if (GET_CODE (operands[2]) == CONST_INT)
1975 HOST_WIDE_INT n = INTVAL (operands[2]);
1977 if ((n & 0xffffff) == 0)
1978 return "add\t%z2,%z0";
1979 if ((n & 0xffff) == 0)
1980 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
1981 if ((n & 0xff) == 0)
1982 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1985 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1989 if (GET_CODE (operands[2]) == REG)
1990 return "add.l\t%S2,%S0";
1992 if (GET_CODE (operands[2]) == CONST_INT)
1994 HOST_WIDE_INT intval = INTVAL (operands[2]);
1996 /* See if we can finish with 2 bytes. */
1998 switch ((unsigned int) intval & 0xffffffff)
2003 return "adds\t%2,%S0";
2008 return "subs\t%G2,%S0";
2012 operands[2] = GEN_INT (intval >> 16);
2013 return "inc.w\t%2,%e0";
2017 operands[2] = GEN_INT (intval >> 16);
2018 return "dec.w\t%G2,%e0";
2021 /* See if we can finish with 4 bytes. */
2022 if ((intval & 0xffff) == 0)
2024 operands[2] = GEN_INT (intval >> 16);
2025 return "add.w\t%2,%e0";
2029 return "add.l\t%S2,%S0";
2034 compute_plussi_length (operands)
2037 enum machine_mode mode = GET_MODE (operands[0]);
2044 if (GET_CODE (operands[2]) == REG)
2047 if (GET_CODE (operands[2]) == CONST_INT)
2049 HOST_WIDE_INT n = INTVAL (operands[2]);
2051 if ((n & 0xffffff) == 0)
2053 if ((n & 0xffff) == 0)
2055 if ((n & 0xff) == 0)
2063 if (GET_CODE (operands[2]) == REG)
2066 if (GET_CODE (operands[2]) == CONST_INT)
2068 HOST_WIDE_INT intval = INTVAL (operands[2]);
2070 /* See if we can finish with 2 bytes. */
2072 switch ((unsigned int) intval & 0xffffffff)
2093 /* See if we can finish with 4 bytes. */
2094 if ((intval & 0xffff) == 0)
2103 compute_plussi_cc (operands)
2106 enum machine_mode mode = GET_MODE (operands[0]);
2117 if (GET_CODE (operands[2]) == REG)
2120 if (GET_CODE (operands[2]) == CONST_INT)
2122 HOST_WIDE_INT intval = INTVAL (operands[2]);
2124 /* See if we can finish with 2 bytes. */
2126 switch ((unsigned int) intval & 0xffffffff)
2131 return CC_NONE_0HIT;
2136 return CC_NONE_0HIT;
2147 /* See if we can finish with 4 bytes. */
2148 if ((intval & 0xffff) == 0)
2157 output_logical_op (mode, operands)
2158 enum machine_mode mode;
2161 /* Figure out the logical op that we need to perform. */
2162 enum rtx_code code = GET_CODE (operands[3]);
2163 /* Pretend that every byte is affected if both operands are registers. */
2164 const unsigned HOST_WIDE_INT intval =
2165 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2166 ? INTVAL (operands[2]) : 0x55555555);
2167 /* The determinant of the algorithm. If we perform an AND, 0
2168 affects a bit. Otherwise, 1 affects a bit. */
2169 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2170 /* Break up DET into pieces. */
2171 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2172 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2173 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2174 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2175 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2176 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2177 int lower_half_easy_p = 0;
2178 int upper_half_easy_p = 0;
2179 /* The name of an insn. */
2201 /* First, see if we can finish with one insn. */
2202 if ((TARGET_H8300H || TARGET_H8300S)
2206 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2207 output_asm_insn (insn_buf, operands);
2211 /* Take care of the lower byte. */
2214 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2215 output_asm_insn (insn_buf, operands);
2217 /* Take care of the upper byte. */
2220 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2221 output_asm_insn (insn_buf, operands);
2226 if (TARGET_H8300H || TARGET_H8300S)
2228 /* Determine if the lower half can be taken care of in no more
2230 lower_half_easy_p = (b0 == 0
2232 || (code != IOR && w0 == 0xffff));
2234 /* Determine if the upper half can be taken care of in no more
2236 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2237 || (code == AND && w1 == 0xff00));
2240 /* Check if doing everything with one insn is no worse than
2241 using multiple insns. */
2242 if ((TARGET_H8300H || TARGET_H8300S)
2243 && w0 != 0 && w1 != 0
2244 && !(lower_half_easy_p && upper_half_easy_p)
2245 && !(code == IOR && w1 == 0xffff
2246 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2248 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2249 output_asm_insn (insn_buf, operands);
2253 /* Take care of the lower and upper words individually. For
2254 each word, we try different methods in the order of
2256 1) the special insn (in case of AND or XOR),
2257 2) the word-wise insn, and
2258 3) The byte-wise insn. */
2260 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2261 output_asm_insn ((code == AND)
2262 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2264 else if ((TARGET_H8300H || TARGET_H8300S)
2268 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2269 output_asm_insn (insn_buf, operands);
2275 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2276 output_asm_insn (insn_buf, operands);
2280 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2281 output_asm_insn (insn_buf, operands);
2286 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2287 output_asm_insn ((code == AND)
2288 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2290 else if ((TARGET_H8300H || TARGET_H8300S)
2293 && (w0 & 0x8000) != 0)
2295 output_asm_insn ("exts.l\t%S0", operands);
2297 else if ((TARGET_H8300H || TARGET_H8300S)
2301 output_asm_insn ("extu.w\t%e0", operands);
2303 else if (TARGET_H8300H || TARGET_H8300S)
2307 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2308 output_asm_insn (insn_buf, operands);
2315 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2316 output_asm_insn (insn_buf, operands);
2320 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2321 output_asm_insn (insn_buf, operands);
2333 compute_logical_op_length (mode, operands)
2334 enum machine_mode mode;
2337 /* Figure out the logical op that we need to perform. */
2338 enum rtx_code code = GET_CODE (operands[3]);
2339 /* Pretend that every byte is affected if both operands are registers. */
2340 const unsigned HOST_WIDE_INT intval =
2341 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2342 ? INTVAL (operands[2]) : 0x55555555);
2343 /* The determinant of the algorithm. If we perform an AND, 0
2344 affects a bit. Otherwise, 1 affects a bit. */
2345 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2346 /* Break up DET into pieces. */
2347 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2348 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2349 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2350 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2351 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2352 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2353 int lower_half_easy_p = 0;
2354 int upper_half_easy_p = 0;
2356 unsigned int length = 0;
2361 /* First, see if we can finish with one insn. */
2362 if ((TARGET_H8300H || TARGET_H8300S)
2366 if (REG_P (operands[2]))
2373 /* Take care of the lower byte. */
2377 /* Take care of the upper byte. */
2383 if (TARGET_H8300H || TARGET_H8300S)
2385 /* Determine if the lower half can be taken care of in no more
2387 lower_half_easy_p = (b0 == 0
2389 || (code != IOR && w0 == 0xffff));
2391 /* Determine if the upper half can be taken care of in no more
2393 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2394 || (code == AND && w1 == 0xff00));
2397 /* Check if doing everything with one insn is no worse than
2398 using multiple insns. */
2399 if ((TARGET_H8300H || TARGET_H8300S)
2400 && w0 != 0 && w1 != 0
2401 && !(lower_half_easy_p && upper_half_easy_p)
2402 && !(code == IOR && w1 == 0xffff
2403 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2405 if (REG_P (operands[2]))
2412 /* Take care of the lower and upper words individually. For
2413 each word, we try different methods in the order of
2415 1) the special insn (in case of AND or XOR),
2416 2) the word-wise insn, and
2417 3) The byte-wise insn. */
2419 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2423 else if ((TARGET_H8300H || TARGET_H8300S)
2439 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2443 else if ((TARGET_H8300H || TARGET_H8300S)
2446 && (w0 & 0x8000) != 0)
2450 else if ((TARGET_H8300H || TARGET_H8300S)
2456 else if (TARGET_H8300H || TARGET_H8300S)
2478 compute_logical_op_cc (mode, operands)
2479 enum machine_mode mode;
2482 /* Figure out the logical op that we need to perform. */
2483 enum rtx_code code = GET_CODE (operands[3]);
2484 /* Pretend that every byte is affected if both operands are registers. */
2485 const unsigned HOST_WIDE_INT intval =
2486 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2487 ? INTVAL (operands[2]) : 0x55555555);
2488 /* The determinant of the algorithm. If we perform an AND, 0
2489 affects a bit. Otherwise, 1 affects a bit. */
2490 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2491 /* Break up DET into pieces. */
2492 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2493 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2494 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2495 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2496 int lower_half_easy_p = 0;
2497 int upper_half_easy_p = 0;
2498 /* Condition code. */
2499 enum attr_cc cc = CC_CLOBBER;
2504 /* First, see if we can finish with one insn. */
2505 if ((TARGET_H8300H || TARGET_H8300S)
2513 if (TARGET_H8300H || TARGET_H8300S)
2515 /* Determine if the lower half can be taken care of in no more
2517 lower_half_easy_p = (b0 == 0
2519 || (code != IOR && w0 == 0xffff));
2521 /* Determine if the upper half can be taken care of in no more
2523 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2524 || (code == AND && w1 == 0xff00));
2527 /* Check if doing everything with one insn is no worse than
2528 using multiple insns. */
2529 if ((TARGET_H8300H || TARGET_H8300S)
2530 && w0 != 0 && w1 != 0
2531 && !(lower_half_easy_p && upper_half_easy_p)
2532 && !(code == IOR && w1 == 0xffff
2533 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2539 if ((TARGET_H8300H || TARGET_H8300S)
2542 && (w0 & 0x8000) != 0)
2556 We devote a fair bit of code to getting efficient shifts since we
2557 can only shift one bit at a time on the H8/300 and H8/300H and only
2558 one or two bits at a time on the H8S.
2560 All shift code falls into one of the following ways of
2563 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2564 when a straight line shift is about the same size or smaller than
2567 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2568 off the bits we don't need. This is used when only a few of the
2569 bits in the original value will survive in the shifted value.
2571 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2572 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2573 shifts can be added if the shift count is slightly more than 8 or
2574 16. This case also includes other oddballs that are not worth
2577 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2579 For each shift count, we try to use code that has no trade-off
2580 between code size and speed whenever possible.
2582 If the trade-off is unavoidable, we try to be reasonable.
2583 Specifically, the fastest version is one instruction longer than
2584 the shortest version, we take the fastest version. We also provide
2585 the use a way to switch back to the shortest version with -Os.
2587 For the details of the shift algorithms for various shift counts,
2588 refer to shift_alg_[qhs]i. */
2591 nshift_operator (x, mode)
2593 enum machine_mode mode ATTRIBUTE_UNUSED;
2595 switch (GET_CODE (x))
2607 /* Emit code to do shifts. */
2610 expand_a_shift (mode, code, operands)
2611 enum machine_mode mode;
2615 emit_move_insn (operands[0], operands[1]);
2617 /* Need a loop to get all the bits we want - we generate the
2618 code at emit time, but need to allocate a scratch reg now. */
2620 emit_insn (gen_rtx_PARALLEL
2623 gen_rtx_SET (VOIDmode, operands[0],
2624 gen_rtx (code, mode, operands[0],
2626 gen_rtx_CLOBBER (VOIDmode,
2627 gen_rtx_SCRATCH (QImode)))));
2630 /* Symbols of the various modes which can be used as indices. */
2634 QIshift, HIshift, SIshift
2637 /* For single bit shift insns, record assembler and what bits of the
2638 condition code are valid afterwards (represented as various CC_FOO
2639 bits, 0 means CC isn't left in a usable state). */
2643 const char *const assembler;
2647 /* Assembler instruction shift table.
2649 These tables are used to look up the basic shifts.
2650 They are indexed by cpu, shift_type, and mode. */
2652 static const struct shift_insn shift_one[2][3][3] =
2658 { "shll\t%X0", CC_SET_ZNV },
2659 { "add.w\t%T0,%T0", CC_SET_ZN },
2660 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2662 /* SHIFT_LSHIFTRT */
2664 { "shlr\t%X0", CC_SET_ZNV },
2665 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2666 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2668 /* SHIFT_ASHIFTRT */
2670 { "shar\t%X0", CC_SET_ZNV },
2671 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2672 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2679 { "shll.b\t%X0", CC_SET_ZNV },
2680 { "shll.w\t%T0", CC_SET_ZNV },
2681 { "shll.l\t%S0", CC_SET_ZNV }
2683 /* SHIFT_LSHIFTRT */
2685 { "shlr.b\t%X0", CC_SET_ZNV },
2686 { "shlr.w\t%T0", CC_SET_ZNV },
2687 { "shlr.l\t%S0", CC_SET_ZNV }
2689 /* SHIFT_ASHIFTRT */
2691 { "shar.b\t%X0", CC_SET_ZNV },
2692 { "shar.w\t%T0", CC_SET_ZNV },
2693 { "shar.l\t%S0", CC_SET_ZNV }
2698 static const struct shift_insn shift_two[3][3] =
2702 { "shll.b\t#2,%X0", CC_SET_ZNV },
2703 { "shll.w\t#2,%T0", CC_SET_ZNV },
2704 { "shll.l\t#2,%S0", CC_SET_ZNV }
2706 /* SHIFT_LSHIFTRT */
2708 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2709 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2710 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2712 /* SHIFT_ASHIFTRT */
2714 { "shar.b\t#2,%X0", CC_SET_ZNV },
2715 { "shar.w\t#2,%T0", CC_SET_ZNV },
2716 { "shar.l\t#2,%S0", CC_SET_ZNV }
2720 /* Rotates are organized by which shift they'll be used in implementing.
2721 There's no need to record whether the cc is valid afterwards because
2722 it is the AND insn that will decide this. */
2724 static const char *const rotate_one[2][3][3] =
2731 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2734 /* SHIFT_LSHIFTRT */
2737 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2740 /* SHIFT_ASHIFTRT */
2743 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2755 /* SHIFT_LSHIFTRT */
2761 /* SHIFT_ASHIFTRT */
2770 static const char *const rotate_two[3][3] =
2778 /* SHIFT_LSHIFTRT */
2784 /* SHIFT_ASHIFTRT */
2793 /* Shift algorithm. */
2796 /* The number of bits to be shifted by shift1 and shift2. Valid
2797 when ALG is SHIFT_SPECIAL. */
2798 unsigned int remainder;
2800 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2801 const char *special;
2803 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2804 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2807 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2808 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2811 /* CC status for SHIFT_INLINE. */
2814 /* CC status for SHIFT_SPECIAL. */
2818 static void get_shift_alg PARAMS ((enum shift_type,
2819 enum shift_mode, unsigned int,
2820 struct shift_info *));
2822 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2823 best algorithm for doing the shift. The assembler code is stored
2824 in the pointers in INFO. We achieve the maximum efficiency in most
2825 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2826 SImode in particular have a lot of room to optimize.
2828 We first determine the strategy of the shift algorithm by a table
2829 lookup. If that tells us to use a hand crafted assembly code, we
2830 go into the big switch statement to find what that is. Otherwise,
2831 we resort to a generic way, such as inlining. In either case, the
2832 result is returned through INFO. */
2835 get_shift_alg (shift_type, shift_mode, count, info)
2836 enum shift_type shift_type;
2837 enum shift_mode shift_mode;
2839 struct shift_info *info;
2843 /* Find the target CPU. */
2846 else if (TARGET_H8300H)
2851 /* Find the shift algorithm. */
2852 info->alg = SHIFT_LOOP;
2856 if (count < GET_MODE_BITSIZE (QImode))
2857 info->alg = shift_alg_qi[cpu][shift_type][count];
2861 if (count < GET_MODE_BITSIZE (HImode))
2862 info->alg = shift_alg_hi[cpu][shift_type][count];
2866 if (count < GET_MODE_BITSIZE (SImode))
2867 info->alg = shift_alg_si[cpu][shift_type][count];
2874 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2878 info->remainder = count;
2882 /* It is up to the caller to know that looping clobbers cc. */
2883 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2884 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2885 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2889 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2890 info->shift2 = rotate_two[shift_type][shift_mode];
2891 info->cc_inline = CC_CLOBBER;
2895 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2896 info->remainder = 0;
2897 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2898 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2899 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2900 info->cc_special = CC_CLOBBER;
2904 /* Here we only deal with SHIFT_SPECIAL. */
2908 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2909 through the entire value. */
2910 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2912 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2924 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2926 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2928 case SHIFT_LSHIFTRT:
2930 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2932 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2934 case SHIFT_ASHIFTRT:
2935 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2939 else if ((8 <= count && count <= 13)
2940 || (TARGET_H8300S && count == 14))
2942 info->remainder = count - 8;
2947 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2949 case SHIFT_LSHIFTRT:
2952 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2953 info->shift1 = "shlr.b\t%s0";
2954 info->cc_inline = CC_SET_ZNV;
2958 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
2959 info->cc_special = CC_SET_ZNV;
2962 case SHIFT_ASHIFTRT:
2965 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2966 info->shift1 = "shar.b\t%s0";
2970 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2971 info->cc_special = CC_SET_ZNV;
2976 else if (count == 14)
2982 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2984 case SHIFT_LSHIFTRT:
2986 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2988 case SHIFT_ASHIFTRT:
2990 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2991 else if (TARGET_H8300H)
2993 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2994 info->cc_special = CC_SET_ZNV;
2996 else /* TARGET_H8300S */
3001 else if (count == 15)
3006 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3008 case SHIFT_LSHIFTRT:
3009 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3011 case SHIFT_ASHIFTRT:
3012 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3019 if (TARGET_H8300 && 8 <= count && count <= 9)
3021 info->remainder = count - 8;
3026 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3028 case SHIFT_LSHIFTRT:
3029 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3030 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3032 case SHIFT_ASHIFTRT:
3033 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3037 else if (count == 8 && !TARGET_H8300)
3042 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3044 case SHIFT_LSHIFTRT:
3045 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3047 case SHIFT_ASHIFTRT:
3048 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3052 else if (count == 15 && TARGET_H8300)
3058 case SHIFT_LSHIFTRT:
3059 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\trotxl\t%y0,%y0";
3061 case SHIFT_ASHIFTRT:
3062 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3066 else if (count == 15 && !TARGET_H8300)
3071 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3072 info->cc_special = CC_SET_ZNV;
3074 case SHIFT_LSHIFTRT:
3075 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3076 info->cc_special = CC_SET_ZNV;
3078 case SHIFT_ASHIFTRT:
3082 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3083 || (TARGET_H8300H && 16 <= count && count <= 19)
3084 || (TARGET_H8300S && 16 <= count && count <= 21))
3086 info->remainder = count - 16;
3091 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3093 info->shift1 = "add.w\t%e0,%e0";
3095 case SHIFT_LSHIFTRT:
3098 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3099 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3103 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3104 info->cc_special = CC_SET_ZNV;
3107 case SHIFT_ASHIFTRT:
3110 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3111 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3115 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3116 info->cc_special = CC_SET_ZNV;
3121 else if (TARGET_H8300 && 24 <= count && count <= 28)
3123 info->remainder = count - 24;
3128 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3129 info->shift1 = "shll.b\t%z0";
3130 info->cc_inline = CC_SET_ZNV;
3132 case SHIFT_LSHIFTRT:
3133 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3134 info->shift1 = "shlr.b\t%w0";
3135 info->cc_inline = CC_SET_ZNV;
3137 case SHIFT_ASHIFTRT:
3138 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3139 info->shift1 = "shar.b\t%w0";
3140 info->cc_inline = CC_SET_ZNV;
3144 else if ((TARGET_H8300H && count == 24)
3145 || (TARGET_H8300S && 24 <= count && count <= 25))
3147 info->remainder = count - 24;
3152 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3154 case SHIFT_LSHIFTRT:
3155 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3156 info->cc_special = CC_SET_ZNV;
3158 case SHIFT_ASHIFTRT:
3159 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3160 info->cc_special = CC_SET_ZNV;
3164 else if (!TARGET_H8300 && count == 28)
3170 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3172 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3174 case SHIFT_LSHIFTRT:
3177 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3178 info->cc_special = CC_SET_ZNV;
3181 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3183 case SHIFT_ASHIFTRT:
3187 else if (!TARGET_H8300 && count == 29)
3193 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3195 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3197 case SHIFT_LSHIFTRT:
3200 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3201 info->cc_special = CC_SET_ZNV;
3205 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3206 info->cc_special = CC_SET_ZNV;
3209 case SHIFT_ASHIFTRT:
3213 else if (!TARGET_H8300 && count == 30)
3219 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3221 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3223 case SHIFT_LSHIFTRT:
3225 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3227 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3229 case SHIFT_ASHIFTRT:
3233 else if (count == 31)
3240 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3242 case SHIFT_LSHIFTRT:
3243 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3245 case SHIFT_ASHIFTRT:
3246 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3255 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3256 info->cc_special = CC_SET_ZNV;
3258 case SHIFT_LSHIFTRT:
3259 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3260 info->cc_special = CC_SET_ZNV;
3262 case SHIFT_ASHIFTRT:
3263 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3264 info->cc_special = CC_SET_ZNV;
3277 info->shift2 = NULL;
3280 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3281 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3284 h8300_shift_needs_scratch_p (count, mode)
3286 enum machine_mode mode;
3291 if (GET_MODE_BITSIZE (mode) <= count)
3294 /* Find out the target CPU. */
3297 else if (TARGET_H8300H)
3302 /* Find the shift algorithm. */
3306 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3307 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3308 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3312 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3313 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3314 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3318 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3319 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3320 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3327 /* On H8/300H, count == 8 uses a scratch register. */
3328 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3329 || (TARGET_H8300H && mode == SImode && count == 8));
3332 /* Emit the assembler code for doing shifts. */
3335 output_a_shift (operands)
3338 static int loopend_lab;
3339 rtx shift = operands[3];
3340 enum machine_mode mode = GET_MODE (shift);
3341 enum rtx_code code = GET_CODE (shift);
3342 enum shift_type shift_type;
3343 enum shift_mode shift_mode;
3344 struct shift_info info;
3351 shift_mode = QIshift;
3354 shift_mode = HIshift;
3357 shift_mode = SIshift;
3366 shift_type = SHIFT_ASHIFTRT;
3369 shift_type = SHIFT_LSHIFTRT;
3372 shift_type = SHIFT_ASHIFT;
3378 if (GET_CODE (operands[2]) != CONST_INT)
3380 /* This case must be taken care of by one of the two splitters
3381 that convert a variable shift into a loop. */
3386 int n = INTVAL (operands[2]);
3388 /* If the count is negative, make it 0. */
3391 /* If the count is too big, truncate it.
3392 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3393 do the intuitive thing. */
3394 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3395 n = GET_MODE_BITSIZE (mode);
3397 get_shift_alg (shift_type, shift_mode, n, &info);
3402 output_asm_insn (info.special, operands);
3408 /* Emit two bit shifts first. */
3409 if (info.shift2 != NULL)
3411 for (; n > 1; n -= 2)
3412 output_asm_insn (info.shift2, operands);
3415 /* Now emit one bit shifts for any residual. */
3417 output_asm_insn (info.shift1, operands);
3422 int m = GET_MODE_BITSIZE (mode) - n;
3423 const int mask = (shift_type == SHIFT_ASHIFT
3424 ? ((1 << m) - 1) << n
3428 /* Not all possibilities of rotate are supported. They shouldn't
3429 be generated, but let's watch for 'em. */
3430 if (info.shift1 == 0)
3433 /* Emit two bit rotates first. */
3434 if (info.shift2 != NULL)
3436 for (; m > 1; m -= 2)
3437 output_asm_insn (info.shift2, operands);
3440 /* Now single bit rotates for any residual. */
3442 output_asm_insn (info.shift1, operands);
3444 /* Now mask off the high bits. */
3446 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3447 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3448 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3452 output_asm_insn (insn_buf, operands);
3457 /* A loop to shift by a "large" constant value.
3458 If we have shift-by-2 insns, use them. */
3459 if (info.shift2 != NULL)
3461 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3462 names_big[REGNO (operands[4])]);
3463 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3464 output_asm_insn (info.shift2, operands);
3465 output_asm_insn ("add #0xff,%X4", operands);
3466 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3468 output_asm_insn (info.shift1, operands);
3472 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3473 names_big[REGNO (operands[4])]);
3474 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3475 output_asm_insn (info.shift1, operands);
3476 output_asm_insn ("add #0xff,%X4", operands);
3477 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3488 h8300_asm_insn_count (template)
3489 const char *template;
3491 unsigned int count = 1;
3493 for (; *template; template++)
3494 if (*template == '\n')
3501 compute_a_shift_length (insn, operands)
3502 rtx insn ATTRIBUTE_UNUSED;
3505 rtx shift = operands[3];
3506 enum machine_mode mode = GET_MODE (shift);
3507 enum rtx_code code = GET_CODE (shift);
3508 enum shift_type shift_type;
3509 enum shift_mode shift_mode;
3510 struct shift_info info;
3511 unsigned int wlength = 0;
3516 shift_mode = QIshift;
3519 shift_mode = HIshift;
3522 shift_mode = SIshift;
3531 shift_type = SHIFT_ASHIFTRT;
3534 shift_type = SHIFT_LSHIFTRT;
3537 shift_type = SHIFT_ASHIFT;
3543 if (GET_CODE (operands[2]) != CONST_INT)
3545 /* Get the assembler code to do one shift. */
3546 get_shift_alg (shift_type, shift_mode, 1, &info);
3548 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3552 int n = INTVAL (operands[2]);
3554 /* If the count is negative, make it 0. */
3557 /* If the count is too big, truncate it.
3558 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3559 do the intuitive thing. */
3560 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3561 n = GET_MODE_BITSIZE (mode);
3563 get_shift_alg (shift_type, shift_mode, n, &info);
3568 wlength += h8300_asm_insn_count (info.special);
3570 /* Every assembly instruction used in SHIFT_SPECIAL case
3571 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3572 see xor.l, we just pretend that xor.l counts as two insns
3573 so that the insn length will be computed correctly. */
3574 if (strstr (info.special, "xor.l") != NULL)
3582 if (info.shift2 != NULL)
3584 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3588 wlength += h8300_asm_insn_count (info.shift1) * n;
3594 int m = GET_MODE_BITSIZE (mode) - n;
3596 /* Not all possibilities of rotate are supported. They shouldn't
3597 be generated, but let's watch for 'em. */
3598 if (info.shift1 == 0)
3601 if (info.shift2 != NULL)
3603 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3607 wlength += h8300_asm_insn_count (info.shift1) * m;
3609 /* Now mask off the high bits. */
3630 /* A loop to shift by a "large" constant value.
3631 If we have shift-by-2 insns, use them. */
3632 if (info.shift2 != NULL)
3634 wlength += 3 + h8300_asm_insn_count (info.shift2);
3636 wlength += h8300_asm_insn_count (info.shift1);
3640 wlength += 3 + h8300_asm_insn_count (info.shift1);
3651 compute_a_shift_cc (insn, operands)
3652 rtx insn ATTRIBUTE_UNUSED;
3655 rtx shift = operands[3];
3656 enum machine_mode mode = GET_MODE (shift);
3657 enum rtx_code code = GET_CODE (shift);
3658 enum shift_type shift_type;
3659 enum shift_mode shift_mode;
3660 struct shift_info info;
3665 shift_mode = QIshift;
3668 shift_mode = HIshift;
3671 shift_mode = SIshift;
3680 shift_type = SHIFT_ASHIFTRT;
3683 shift_type = SHIFT_LSHIFTRT;
3686 shift_type = SHIFT_ASHIFT;
3692 if (GET_CODE (operands[2]) != CONST_INT)
3694 /* This case must be taken care of by one of the two splitters
3695 that convert a variable shift into a loop. */
3700 int n = INTVAL (operands[2]);
3702 /* If the count is negative, make it 0. */
3705 /* If the count is too big, truncate it.
3706 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3707 do the intuitive thing. */
3708 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3709 n = GET_MODE_BITSIZE (mode);
3711 get_shift_alg (shift_type, shift_mode, n, &info);
3716 if (info.remainder == 0)
3717 return info.cc_special;
3722 return info.cc_inline;
3725 /* This case always ends with an and instruction. */
3729 /* A loop to shift by a "large" constant value.
3730 If we have shift-by-2 insns, use them. */
3731 if (info.shift2 != NULL)
3734 return info.cc_inline;
3744 /* A rotation by a non-constant will cause a loop to be generated, in
3745 which a rotation by one bit is used. A rotation by a constant,
3746 including the one in the loop, will be taken care of by
3747 emit_a_rotate () at the insn emit time. */
3750 expand_a_rotate (code, operands)
3754 rtx dst = operands[0];
3755 rtx src = operands[1];
3756 rtx rotate_amount = operands[2];
3757 enum machine_mode mode = GET_MODE (dst);
3760 /* We rotate in place. */
3761 emit_move_insn (dst, src);
3763 if (GET_CODE (rotate_amount) != CONST_INT)
3765 rtx counter = gen_reg_rtx (QImode);
3766 rtx start_label = gen_label_rtx ();
3767 rtx end_label = gen_label_rtx ();
3769 /* If the rotate amount is less than or equal to 0,
3770 we go out of the loop. */
3771 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3772 QImode, 0, end_label);
3774 /* Initialize the loop counter. */
3775 emit_move_insn (counter, rotate_amount);
3777 emit_label (start_label);
3779 /* Rotate by one bit. */
3780 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3781 emit_insn (gen_rtx_SET (mode, dst, tmp));
3783 /* Decrement the counter by 1. */
3784 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3785 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3787 /* If the loop counter is nonzero, we go back to the beginning
3789 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3792 emit_label (end_label);
3796 /* Rotate by AMOUNT bits. */
3797 tmp = gen_rtx (code, mode, dst, rotate_amount);
3798 emit_insn (gen_rtx_SET (mode, dst, tmp));
3804 /* Emit rotate insns. */
3807 emit_a_rotate (code, operands)
3811 rtx dst = operands[0];
3812 rtx rotate_amount = operands[2];
3813 enum shift_mode rotate_mode;
3814 enum shift_type rotate_type;
3815 const char *insn_buf;
3818 enum machine_mode mode = GET_MODE (dst);
3820 if (GET_CODE (rotate_amount) != CONST_INT)
3826 rotate_mode = QIshift;
3829 rotate_mode = HIshift;
3832 rotate_mode = SIshift;
3841 rotate_type = SHIFT_ASHIFT;
3844 rotate_type = SHIFT_LSHIFTRT;
3850 amount = INTVAL (rotate_amount);
3852 /* Clean up AMOUNT. */
3855 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3856 amount = GET_MODE_BITSIZE (mode);
3858 /* Determine the faster direction. After this phase, amount will be
3859 at most a half of GET_MODE_BITSIZE (mode). */
3860 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3862 /* Flip the direction. */
3863 amount = GET_MODE_BITSIZE (mode) - amount;
3865 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3868 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3869 boost up the rotation. */
3870 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3871 || (mode == HImode && TARGET_H8300H && amount >= 6)
3872 || (mode == HImode && TARGET_H8300S && amount == 8)
3873 || (mode == SImode && TARGET_H8300H && amount >= 10)
3874 || (mode == SImode && TARGET_H8300S && amount >= 13))
3879 /* This code works on any family. */
3880 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3881 output_asm_insn (insn_buf, operands);
3885 /* This code works on the H8/300H and H8S. */
3886 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3887 output_asm_insn (insn_buf, operands);
3894 /* Adjust AMOUNT and flip the direction. */
3895 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3897 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3900 /* Emit rotate insns. */
3901 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3904 insn_buf = rotate_two[rotate_type][rotate_mode];
3906 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3908 for (; amount >= bits; amount -= bits)
3909 output_asm_insn (insn_buf, operands);
3915 /* Fix the operands of a gen_xxx so that it could become a bit
3919 fix_bit_operand (operands, what, type)
3924 /* The bit_operand predicate accepts any memory during RTL generation, but
3925 only 'U' memory afterwards, so if this is a MEM operand, we must force
3926 it to be valid for 'U' by reloading the address. */
3928 if ((what == 0 && single_zero_operand (operands[2], QImode))
3929 || (what == 1 && single_one_operand (operands[2], QImode)))
3931 /* OK to have a memory dest. */
3932 if (GET_CODE (operands[0]) == MEM
3933 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3935 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3936 copy_to_mode_reg (Pmode,
3937 XEXP (operands[0], 0)));
3938 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3942 if (GET_CODE (operands[1]) == MEM
3943 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3945 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3946 copy_to_mode_reg (Pmode,
3947 XEXP (operands[1], 0)));
3948 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3954 /* Dest and src op must be register. */
3956 operands[1] = force_reg (QImode, operands[1]);
3958 rtx res = gen_reg_rtx (QImode);
3959 emit_insn (gen_rtx_SET (VOIDmode, res,
3960 gen_rtx (type, QImode, operands[1], operands[2])));
3961 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3966 /* Return nonzero if FUNC is an interrupt function as specified
3967 by the "interrupt" attribute. */
3970 h8300_interrupt_function_p (func)
3975 if (TREE_CODE (func) != FUNCTION_DECL)
3978 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3979 return a != NULL_TREE;
3982 /* Return nonzero if FUNC is an OS_Task function as specified
3983 by the "OS_Task" attribute. */
3986 h8300_os_task_function_p (func)
3991 if (TREE_CODE (func) != FUNCTION_DECL)
3994 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3995 return a != NULL_TREE;
3998 /* Return nonzero if FUNC is a monitor function as specified
3999 by the "monitor" attribute. */
4002 h8300_monitor_function_p (func)
4007 if (TREE_CODE (func) != FUNCTION_DECL)
4010 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4011 return a != NULL_TREE;
4014 /* Return nonzero if FUNC is a function that should be called
4015 through the function vector. */
4018 h8300_funcvec_function_p (func)
4023 if (TREE_CODE (func) != FUNCTION_DECL)
4026 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4027 return a != NULL_TREE;
4030 /* Return nonzero if DECL is a variable that's in the eight bit
4034 h8300_eightbit_data_p (decl)
4039 if (TREE_CODE (decl) != VAR_DECL)
4042 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4043 return a != NULL_TREE;
4046 /* Return nonzero if DECL is a variable that's in the tiny
4050 h8300_tiny_data_p (decl)
4055 if (TREE_CODE (decl) != VAR_DECL)
4058 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4059 return a != NULL_TREE;
4062 /* Generate an 'interrupt_handler' attribute for decls. */
4065 h8300_insert_attributes (node, attributes)
4069 if (!pragma_interrupt
4070 || TREE_CODE (node) != FUNCTION_DECL)
4073 pragma_interrupt = 0;
4075 /* Add an 'interrupt_handler' attribute. */
4076 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4080 /* Supported attributes:
4082 interrupt_handler: output a prologue and epilogue suitable for an
4085 function_vector: This function should be called through the
4088 eightbit_data: This variable lives in the 8-bit data area and can
4089 be referenced with 8-bit absolute memory addresses.
4091 tiny_data: This variable lives in the tiny data area and can be
4092 referenced with 16-bit absolute memory references. */
4094 const struct attribute_spec h8300_attribute_table[] =
4096 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4097 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4098 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4099 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4100 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4101 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4102 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4103 { NULL, 0, 0, false, false, false, NULL }
4107 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4108 struct attribute_spec.handler. */
4110 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
4113 tree args ATTRIBUTE_UNUSED;
4114 int flags ATTRIBUTE_UNUSED;
4117 if (TREE_CODE (*node) != FUNCTION_DECL)
4119 warning ("`%s' attribute only applies to functions",
4120 IDENTIFIER_POINTER (name));
4121 *no_add_attrs = true;
4127 /* Handle an "eightbit_data" attribute; arguments as in
4128 struct attribute_spec.handler. */
4130 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
4133 tree args ATTRIBUTE_UNUSED;
4134 int flags ATTRIBUTE_UNUSED;
4139 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4141 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4145 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4146 *no_add_attrs = true;
4152 /* Handle an "tiny_data" attribute; arguments as in
4153 struct attribute_spec.handler. */
4155 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
4158 tree args ATTRIBUTE_UNUSED;
4159 int flags ATTRIBUTE_UNUSED;
4164 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4166 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4170 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4171 *no_add_attrs = true;
4177 /* Mark function vectors, and various small data objects. */
4180 h8300_encode_section_info (decl, rtl, first)
4185 int extra_flags = 0;
4187 default_encode_section_info (decl, rtl, first);
4189 if (TREE_CODE (decl) == FUNCTION_DECL
4190 && h8300_funcvec_function_p (decl))
4191 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4192 else if (TREE_CODE (decl) == VAR_DECL
4193 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4195 if (h8300_eightbit_data_p (decl))
4196 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4197 else if (first && h8300_tiny_data_p (decl))
4198 extra_flags = SYMBOL_FLAG_TINY_DATA;
4202 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4206 output_simode_bld (bild, operands)
4212 /* Clear the destination register. */
4213 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4215 /* Now output the bit load or bit inverse load, and store it in
4218 output_asm_insn ("bild\t%Z2,%Y1", operands);
4220 output_asm_insn ("bld\t%Z2,%Y1", operands);
4222 output_asm_insn ("bst\t#0,%w0", operands);
4226 /* Determine if we can clear the destination first. */
4227 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4228 && REGNO (operands[0]) != REGNO (operands[1]));
4231 output_asm_insn ("sub.l\t%S0,%S0", operands);
4233 /* Output the bit load or bit inverse load. */
4235 output_asm_insn ("bild\t%Z2,%Y1", operands);
4237 output_asm_insn ("bld\t%Z2,%Y1", operands);
4240 output_asm_insn ("xor.l\t%S0,%S0", operands);
4242 /* Perform the bit store. */
4243 output_asm_insn ("bst\t#0,%w0", operands);
4250 /* Given INSN and its current length LENGTH, return the adjustment
4251 (in bytes) to correctly compute INSN's length.
4253 We use this to get the lengths of various memory references correct. */
4256 h8300_adjust_insn_length (insn, length)
4258 int length ATTRIBUTE_UNUSED;
4260 rtx pat = PATTERN (insn);
4262 /* We must filter these out before calling get_attr_adjust_length. */
4263 if (GET_CODE (pat) == USE
4264 || GET_CODE (pat) == CLOBBER
4265 || GET_CODE (pat) == SEQUENCE
4266 || GET_CODE (pat) == ADDR_VEC
4267 || GET_CODE (pat) == ADDR_DIFF_VEC)
4270 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
4273 /* Adjust length for reg->mem and mem->reg copies. */
4274 if (GET_CODE (pat) == SET
4275 && (GET_CODE (SET_SRC (pat)) == MEM
4276 || GET_CODE (SET_DEST (pat)) == MEM))
4278 /* This insn might need a length adjustment. */
4281 if (GET_CODE (SET_SRC (pat)) == MEM)
4282 addr = XEXP (SET_SRC (pat), 0);
4284 addr = XEXP (SET_DEST (pat), 0);
4288 /* On the H8/300, we subtract the difference between the
4289 actual length and the longest one, which is @(d:16,ERs). */
4291 /* @Rs is 2 bytes shorter than the longest. */
4292 if (GET_CODE (addr) == REG)
4295 /* @aa:8 is 2 bytes shorter than the longest. */
4296 if (GET_MODE (SET_SRC (pat)) == QImode
4297 && h8300_eightbit_constant_address_p (addr))
4302 /* On the H8/300H and H8S, we subtract the difference
4303 between the actual length and the longest one, which is
4306 /* @ERs is 6 bytes shorter than the longest. */
4307 if (GET_CODE (addr) == REG)
4310 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4311 if (GET_CODE (addr) == PLUS
4312 && GET_CODE (XEXP (addr, 0)) == REG
4313 && GET_CODE (XEXP (addr, 1)) == CONST_INT
4314 && INTVAL (XEXP (addr, 1)) > -32768
4315 && INTVAL (XEXP (addr, 1)) < 32767)
4318 /* @aa:8 is 6 bytes shorter than the longest. */
4319 if (GET_MODE (SET_SRC (pat)) == QImode
4320 && h8300_eightbit_constant_address_p (addr))
4323 /* @aa:16 is 4 bytes shorter than the longest. */
4324 if (h8300_tiny_constant_address_p (addr))
4327 /* @aa:24 is 2 bytes shorter than the longest. */
4328 if (GET_CODE (addr) == CONST_INT)
4333 /* Loading some constants needs adjustment. */
4334 if (GET_CODE (pat) == SET
4335 && GET_CODE (SET_SRC (pat)) == CONST_INT
4336 && GET_MODE (SET_DEST (pat)) == SImode
4337 && INTVAL (SET_SRC (pat)) != 0)
4339 int val = INTVAL (SET_SRC (pat));
4342 && ((val & 0xffff) == 0
4343 || ((val >> 16) & 0xffff) == 0))
4346 if (TARGET_H8300H || TARGET_H8300S)
4348 if (val == (val & 0xff)
4349 || val == (val & 0xff00))
4352 switch (val & 0xffffffff)
4368 /* Rotations need various adjustments. */
4369 if (GET_CODE (pat) == SET
4370 && (GET_CODE (SET_SRC (pat)) == ROTATE
4371 || GET_CODE (SET_SRC (pat)) == ROTATERT))
4373 rtx src = SET_SRC (pat);
4374 enum machine_mode mode = GET_MODE (src);
4378 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
4381 amount = INTVAL (XEXP (src, 1));
4383 /* Clean up AMOUNT. */
4386 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4387 amount = GET_MODE_BITSIZE (mode);
4389 /* Determine the faster direction. After this phase, amount
4390 will be at most a half of GET_MODE_BITSIZE (mode). */
4391 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4392 /* Flip the direction. */
4393 amount = GET_MODE_BITSIZE (mode) - amount;
4395 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4396 boost up the rotation. */
4397 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4398 || (mode == HImode && TARGET_H8300H && amount >= 6)
4399 || (mode == HImode && TARGET_H8300S && amount == 8)
4400 || (mode == SImode && TARGET_H8300H && amount >= 10)
4401 || (mode == SImode && TARGET_H8300S && amount >= 13))
4403 /* Adjust AMOUNT and flip the direction. */
4404 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4408 /* We use 2-bit rotations on the H8S. */
4410 amount = amount / 2 + amount % 2;
4412 /* The H8/300 uses three insns to rotate one bit, taking 6
4414 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4416 return -(20 - states);
4422 #ifndef OBJECT_FORMAT_ELF
4424 h8300_asm_named_section (name, flags)
4426 unsigned int flags ATTRIBUTE_UNUSED;
4428 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4429 fprintf (asm_out_file, "\t.section %s\n", name);
4431 #endif /* ! OBJECT_FORMAT_ELF */
4433 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4434 which is a special case of the 'R' operand. */
4437 h8300_eightbit_constant_address_p (x)
4440 /* The ranges of the 8-bit area. */
4441 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4442 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4443 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4444 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4445 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4446 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4448 unsigned HOST_WIDE_INT addr;
4450 /* We accept symbols declared with eightbit_data. */
4451 if (GET_CODE (x) == SYMBOL_REF)
4452 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4454 if (GET_CODE (x) != CONST_INT)
4460 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4461 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4462 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4465 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4466 on H8/300H and H8S. */
4469 h8300_tiny_constant_address_p (x)
4472 /* The ranges of the 16-bit area. */
4473 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4474 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4475 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4476 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4477 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4478 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4479 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4480 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4482 unsigned HOST_WIDE_INT addr;
4484 /* We accept symbols declared with tiny_data. */
4485 if (GET_CODE (x) == SYMBOL_REF)
4486 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
4488 if (GET_CODE (x) != CONST_INT)
4494 || TARGET_NORMAL_MODE
4496 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4498 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4502 byte_accesses_mergeable_p (addr1, addr2)
4505 HOST_WIDE_INT offset1, offset2;
4513 else if (GET_CODE (addr1) == PLUS
4514 && REG_P (XEXP (addr1, 0))
4515 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4517 reg1 = XEXP (addr1, 0);
4518 offset1 = INTVAL (XEXP (addr1, 1));
4528 else if (GET_CODE (addr2) == PLUS
4529 && REG_P (XEXP (addr2, 0))
4530 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4532 reg2 = XEXP (addr2, 0);
4533 offset2 = INTVAL (XEXP (addr2, 1));
4538 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4539 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4541 && offset1 + 1 == offset2)