1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg PARAMS ((rtx, int));
50 static int h8300_interrupt_function_p PARAMS ((tree));
51 static int h8300_monitor_function_p PARAMS ((tree));
52 static int h8300_os_task_function_p PARAMS ((tree));
53 static void dosize PARAMS ((int, unsigned int));
54 static int round_frame_size PARAMS ((int));
55 static unsigned int compute_saved_regs PARAMS ((void));
56 static void push PARAMS ((int));
57 static void pop PARAMS ((int));
58 static const char *cond_string PARAMS ((enum rtx_code));
59 static unsigned int h8300_asm_insn_count PARAMS ((const char *));
60 const struct attribute_spec h8300_attribute_table[];
61 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
62 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
63 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
64 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
65 static void h8300_insert_attributes PARAMS ((tree, tree *));
66 static void h8300_file_end PARAMS ((void));
67 #ifndef OBJECT_FORMAT_ELF
68 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
70 static void h8300_encode_section_info PARAMS ((tree, rtx, int));
71 static int h8300_and_costs PARAMS ((rtx));
72 static int h8300_shift_costs PARAMS ((rtx));
73 static bool h8300_rtx_costs PARAMS ((rtx, int, int, int *));
75 /* CPU_TYPE, says what cpu we're compiling for. */
78 /* True if a #pragma interrupt has been seen for the current function. */
79 static int pragma_interrupt;
81 /* True if a #pragma saveall has been seen for the current function. */
82 static int pragma_saveall;
84 static const char *const names_big[] =
85 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
87 static const char *const names_extended[] =
88 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
90 static const char *const names_upper_extended[] =
91 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
93 /* Points to one of the above. */
94 /* ??? The above could be put in an array indexed by CPU_TYPE. */
95 const char * const *h8_reg_names;
97 /* Various operations needed by the following, indexed by CPU_TYPE. */
99 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
101 /* Machine-specific symbol_ref flags. */
102 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
103 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
104 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
106 /* Initialize the GCC target structure. */
107 #undef TARGET_ATTRIBUTE_TABLE
108 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
110 #undef TARGET_ASM_ALIGNED_HI_OP
111 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
113 #undef TARGET_ASM_FUNCTION_EPILOGUE
114 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
116 #undef TARGET_ASM_FILE_END
117 #define TARGET_ASM_FILE_END h8300_file_end
119 #undef TARGET_ENCODE_SECTION_INFO
120 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
122 #undef TARGET_INSERT_ATTRIBUTES
123 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
125 #undef TARGET_RTX_COSTS
126 #define TARGET_RTX_COSTS h8300_rtx_costs
128 struct gcc_target targetm = TARGET_INITIALIZER;
130 /* See below where shifts are handled for explanation of this enum. */
140 /* Symbols of the various shifts which can be used as indices. */
144 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
147 /* Macros to keep the shift algorithm tables small. */
148 #define INL SHIFT_INLINE
149 #define ROT SHIFT_ROT_AND
150 #define LOP SHIFT_LOOP
151 #define SPC SHIFT_SPECIAL
153 /* The shift algorithms for each machine, mode, shift type, and shift
154 count are defined below. The three tables below correspond to
155 QImode, HImode, and SImode, respectively. Each table is organized
156 by, in the order of indices, machine, shift type, and shift count. */
158 static enum shift_alg shift_alg_qi[3][3][8] = {
161 /* 0 1 2 3 4 5 6 7 */
162 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
163 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
164 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
168 /* 0 1 2 3 4 5 6 7 */
169 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
170 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
171 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
175 /* 0 1 2 3 4 5 6 7 */
176 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
177 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
178 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
182 static enum shift_alg shift_alg_hi[3][3][16] = {
185 /* 0 1 2 3 4 5 6 7 */
186 /* 8 9 10 11 12 13 14 15 */
187 { INL, INL, INL, INL, INL, INL, INL, SPC,
188 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
189 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
190 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
191 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
192 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
196 /* 0 1 2 3 4 5 6 7 */
197 /* 8 9 10 11 12 13 14 15 */
198 { INL, INL, INL, INL, INL, INL, INL, SPC,
199 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
200 { INL, INL, INL, INL, INL, INL, INL, SPC,
201 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
202 { INL, INL, INL, INL, INL, INL, INL, SPC,
203 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
207 /* 0 1 2 3 4 5 6 7 */
208 /* 8 9 10 11 12 13 14 15 */
209 { INL, INL, INL, INL, INL, INL, INL, INL,
210 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
211 { INL, INL, INL, INL, INL, INL, INL, INL,
212 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
213 { INL, INL, INL, INL, INL, INL, INL, INL,
214 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
218 static enum shift_alg shift_alg_si[3][3][32] = {
221 /* 0 1 2 3 4 5 6 7 */
222 /* 8 9 10 11 12 13 14 15 */
223 /* 16 17 18 19 20 21 22 23 */
224 /* 24 25 26 27 28 29 30 31 */
225 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
226 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
227 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
228 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
229 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
230 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
231 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
232 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
233 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
234 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
235 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
236 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
240 /* 0 1 2 3 4 5 6 7 */
241 /* 8 9 10 11 12 13 14 15 */
242 /* 16 17 18 19 20 21 22 23 */
243 /* 24 25 26 27 28 29 30 31 */
244 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
245 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
246 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
247 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
248 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
249 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
250 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
251 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
252 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
253 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
254 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
255 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
259 /* 0 1 2 3 4 5 6 7 */
260 /* 8 9 10 11 12 13 14 15 */
261 /* 16 17 18 19 20 21 22 23 */
262 /* 24 25 26 27 28 29 30 31 */
263 { INL, INL, INL, INL, INL, INL, INL, INL,
264 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
265 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
266 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
267 { INL, INL, INL, INL, INL, INL, INL, INL,
268 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
269 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
270 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
271 { INL, INL, INL, INL, INL, INL, INL, INL,
272 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
273 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
274 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
290 /* Initialize various cpu specific globals at start up. */
295 static const char *const h8_push_ops[2] = { "push" , "push.l" };
296 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
297 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
301 cpu_type = (int) CPU_H8300;
302 h8_reg_names = names_big;
306 /* For this we treat the H8/300H and H8S the same. */
307 cpu_type = (int) CPU_H8300H;
308 h8_reg_names = names_extended;
310 h8_push_op = h8_push_ops[cpu_type];
311 h8_pop_op = h8_pop_ops[cpu_type];
312 h8_mov_op = h8_mov_ops[cpu_type];
314 if (!TARGET_H8300S && TARGET_MAC)
316 error ("-ms2600 is used without -ms");
317 target_flags |= MASK_H8300S;
320 if (TARGET_H8300 && TARGET_NORMAL_MODE)
322 error ("-mn is used without -mh or -ms");
323 target_flags ^= MASK_NORMAL_MODE;
326 /* Some of the shifts are optimized for speed by default.
327 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
328 If optimizing for size, change shift_alg for those shift to
333 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
334 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
335 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
336 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
338 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
339 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
341 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
342 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
345 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
346 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
348 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
349 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
351 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
352 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
353 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
354 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
357 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
366 static const char *const names_small[] = {
367 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
368 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
371 return names_small[REGNO (x) * 2 + b];
374 /* REGNO must be saved/restored across calls if this macro is true. */
376 #define WORD_REG_USED(regno) \
378 /* No need to save registers if this function will not return. */ \
379 && ! TREE_THIS_VOLATILE (current_function_decl) \
381 /* Save any call saved register that was used. */ \
382 || (regs_ever_live[regno] && !call_used_regs[regno]) \
383 /* Save the frame pointer if it was used. */ \
384 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
385 /* Save any register used in an interrupt handler. */ \
386 || (h8300_current_function_interrupt_function_p () \
387 && regs_ever_live[regno]) \
388 /* Save call clobbered registers in non-leaf interrupt \
390 || (h8300_current_function_interrupt_function_p () \
391 && call_used_regs[regno] \
392 && !current_function_is_leaf)))
394 /* Output assembly language to FILE for the operation OP with operand size
395 SIZE to adjust the stack pointer. */
402 /* H8/300 cannot add/subtract a large constant with a single
403 instruction. If a temporary register is available, load the
404 constant to it and then do the addition. */
407 && !h8300_current_function_interrupt_function_p ()
408 && !(current_function_needs_context && sign < 0))
411 rtx r3 = gen_rtx_REG (Pmode, 3);
412 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
413 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
414 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
418 /* The stack adjustment made here is further optimized by the
419 splitter. In case of H8/300, the splitter always splits the
420 addition emitted here to make the adjustment
422 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
423 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
427 /* Round up frame size SIZE. */
430 round_frame_size (size)
433 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
434 & -STACK_BOUNDARY / BITS_PER_UNIT);
437 /* Compute which registers to push/pop.
438 Return a bit vector of registers. */
441 compute_saved_regs ()
443 unsigned int saved_regs = 0;
446 /* Construct a bit vector of registers to be pushed/popped. */
447 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
449 if (WORD_REG_USED (regno))
450 saved_regs |= 1 << regno;
453 /* Don't push/pop the frame pointer as it is treated separately. */
454 if (frame_pointer_needed)
455 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
460 /* Emit an insn to push register RN. */
466 rtx reg = gen_rtx_REG (word_mode, rn);
470 x = gen_push_h8300 (reg);
472 x = gen_push_h8300hs (reg);
474 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
477 /* Emit an insn to pop register RN. */
483 rtx reg = gen_rtx_REG (word_mode, rn);
487 x = gen_pop_h8300 (reg);
489 x = gen_pop_h8300hs (reg);
491 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
494 /* This is what the stack looks like after the prolog of
495 a function with a frame has been set up:
501 <saved registers> <- sp
503 This is what the stack looks like after the prolog of
504 a function which doesn't have a frame:
509 <saved registers> <- sp
512 /* Generate RTL code for the function prologue. */
515 h8300_expand_prologue ()
521 /* If the current function has the OS_Task attribute set, then
522 we have a naked prologue. */
523 if (h8300_os_task_function_p (current_function_decl))
526 if (h8300_monitor_function_p (current_function_decl))
527 /* My understanding of monitor functions is they act just like
528 interrupt functions, except the prologue must mask
530 emit_insn (gen_monitor_prologue ());
532 if (frame_pointer_needed)
535 push (FRAME_POINTER_REGNUM);
536 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
539 /* Leave room for locals. */
540 dosize (-1, round_frame_size (get_frame_size ()));
542 /* Push the rest of the registers in ascending order. */
543 saved_regs = compute_saved_regs ();
544 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
547 if (saved_regs & (1 << regno))
551 /* See how many registers we can push at the same time. */
552 if ((regno == 0 || regno == 4)
553 && ((saved_regs >> regno) & 0x0f) == 0x0f)
556 else if ((regno == 0 || regno == 4)
557 && ((saved_regs >> regno) & 0x07) == 0x07)
560 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
561 && ((saved_regs >> regno) & 0x03) == 0x03)
571 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
572 gen_rtx_REG (SImode, regno + 1)));
575 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
576 gen_rtx_REG (SImode, regno + 1),
577 gen_rtx_REG (SImode, regno + 2)));
580 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
581 gen_rtx_REG (SImode, regno + 1),
582 gen_rtx_REG (SImode, regno + 2),
583 gen_rtx_REG (SImode, regno + 3)));
593 h8300_can_use_return_insn_p ()
595 return (reload_completed
596 && !frame_pointer_needed
597 && get_frame_size () == 0
598 && compute_saved_regs () == 0);
601 /* Generate RTL code for the function epilogue. */
604 h8300_expand_epilogue ()
610 if (h8300_os_task_function_p (current_function_decl))
611 /* OS_Task epilogues are nearly naked -- they just have an
615 /* Pop the saved registers in descending order. */
616 saved_regs = compute_saved_regs ();
617 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
620 if (saved_regs & (1 << regno))
624 /* See how many registers we can pop at the same time. */
625 if ((regno == 7 || regno == 3)
626 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
629 else if ((regno == 6 || regno == 2)
630 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
633 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
634 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
644 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
645 gen_rtx_REG (SImode, regno)));
648 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
649 gen_rtx_REG (SImode, regno - 1),
650 gen_rtx_REG (SImode, regno)));
653 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
654 gen_rtx_REG (SImode, regno - 2),
655 gen_rtx_REG (SImode, regno - 1),
656 gen_rtx_REG (SImode, regno)));
664 /* Deallocate locals. */
665 dosize (1, round_frame_size (get_frame_size ()));
667 /* Pop frame pointer if we had one. */
668 if (frame_pointer_needed)
669 pop (FRAME_POINTER_REGNUM);
672 /* Output assembly language code for the function epilogue. */
675 h8300_output_function_epilogue (file, size)
676 FILE *file ATTRIBUTE_UNUSED;
677 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
682 /* Return nonzero if the current function is an interrupt
686 h8300_current_function_interrupt_function_p ()
688 return (h8300_interrupt_function_p (current_function_decl)
689 || h8300_monitor_function_p (current_function_decl));
692 /* Output assembly code for the start of the file. */
695 asm_file_start (file)
698 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
699 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
702 fprintf (file, "; -Os\n");
704 fprintf (file, "; -O%d\n", optimize);
706 if (TARGET_NORMAL_MODE)
707 fprintf (file, "\n\t.h8300hn\n");
709 fprintf (file, "\n\t.h8300h\n");
710 else if (TARGET_H8300S)
711 if (TARGET_NORMAL_MODE)
712 fprintf (file, "\n\t.h8300sn\n");
714 fprintf (file, "\n\t.h8300s\n");
716 fprintf (file, "\n\n");
717 output_file_directive (file, main_input_filename);
720 /* Output assembly language code for the end of file. */
725 fputs ("\t.end\n", asm_out_file);
728 /* Return true if OP is a valid source operand for an integer move
732 general_operand_src (op, mode)
734 enum machine_mode mode;
736 if (GET_MODE (op) == mode
737 && GET_CODE (op) == MEM
738 && GET_CODE (XEXP (op, 0)) == POST_INC)
740 return general_operand (op, mode);
743 /* Return true if OP is a valid destination operand for an integer move
747 general_operand_dst (op, mode)
749 enum machine_mode mode;
751 if (GET_MODE (op) == mode
752 && GET_CODE (op) == MEM
753 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
755 return general_operand (op, mode);
758 /* Return true if OP is a constant that contains only one 1 in its
759 binary representation. */
762 single_one_operand (operand, mode)
764 enum machine_mode mode ATTRIBUTE_UNUSED;
766 if (GET_CODE (operand) == CONST_INT)
768 /* We really need to do this masking because 0x80 in QImode is
769 represented as -128 for example. */
770 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
777 /* Return true if OP is a constant that contains only one 0 in its
778 binary representation. */
781 single_zero_operand (operand, mode)
783 enum machine_mode mode ATTRIBUTE_UNUSED;
785 if (GET_CODE (operand) == CONST_INT)
787 /* We really need to do this masking because 0x80 in QImode is
788 represented as -128 for example. */
789 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
796 /* Return true if OP is a valid call operand. */
799 call_insn_operand (op, mode)
801 enum machine_mode mode ATTRIBUTE_UNUSED;
803 if (GET_CODE (op) == MEM)
805 rtx inside = XEXP (op, 0);
806 if (register_operand (inside, Pmode))
808 if (CONSTANT_ADDRESS_P (inside))
814 /* Return 1 if an addition/subtraction of a constant integer can be
815 transformed into two consecutive adds/subs that are faster than the
816 straightforward way. Otherwise, return 0. */
819 two_insn_adds_subs_operand (op, mode)
821 enum machine_mode mode;
823 if (GET_CODE (op) == CONST_INT)
825 HOST_WIDE_INT value = INTVAL (op);
827 /* Force VALUE to be positive so that we do not have to consider
828 the negative case. */
831 if (TARGET_H8300H || TARGET_H8300S)
833 /* A constant addition/subtraction takes 2 states in QImode,
834 4 states in HImode, and 6 states in SImode. Thus, the
835 only case we can win is when SImode is used, in which
836 case, two adds/subs are used, taking 4 states. */
846 /* We do not profit directly by splitting addition or
847 subtraction of 3 and 4. However, since these are
848 implemented as a sequence of adds or subs, they do not
849 clobber (cc0) unlike a sequence of add.b and add.x. */
860 /* Split an add of a small constant into two adds/subs insns.
862 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
863 instead of adds/subs. */
866 split_adds_subs (mode, operands)
867 enum machine_mode mode;
870 HOST_WIDE_INT val = INTVAL (operands[1]);
871 rtx reg = operands[0];
872 HOST_WIDE_INT sign = 1;
873 HOST_WIDE_INT amount;
874 rtx (*gen_add) (rtx, rtx, rtx);
876 /* Force VAL to be positive so that we do not have to consider the
887 gen_add = gen_addhi3;
891 gen_add = gen_addsi3;
898 /* Try different amounts in descending order. */
899 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
903 for (; val >= amount; val -= amount)
904 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
910 /* Return true if OP is a valid call operand, and OP represents
911 an operand for a small call (4 bytes instead of 6 bytes). */
914 small_call_insn_operand (op, mode)
916 enum machine_mode mode ATTRIBUTE_UNUSED;
918 if (GET_CODE (op) == MEM)
920 rtx inside = XEXP (op, 0);
922 /* Register indirect is a small call. */
923 if (register_operand (inside, Pmode))
926 /* A call through the function vector is a small call too. */
927 if (GET_CODE (inside) == SYMBOL_REF
928 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
931 /* Otherwise it's a large call. */
935 /* Return true if OP is a valid jump operand. */
938 jump_address_operand (op, mode)
940 enum machine_mode mode;
942 if (GET_CODE (op) == REG)
943 return mode == Pmode;
945 if (GET_CODE (op) == MEM)
947 rtx inside = XEXP (op, 0);
948 if (register_operand (inside, Pmode))
950 if (CONSTANT_ADDRESS_P (inside))
956 /* Recognize valid operands for bit-field instructions. */
958 extern int rtx_equal_function_value_matters;
961 bit_operand (op, mode)
963 enum machine_mode mode;
965 /* We can accept any general operand, except that MEM operands must
966 be limited to those that use addresses valid for the 'U' constraint. */
967 if (!general_operand (op, mode))
970 /* Accept any mem during RTL generation. Otherwise, the code that does
971 insv and extzv will think that we can not handle memory. However,
972 to avoid reload problems, we only accept 'U' MEM operands after RTL
973 generation. This means that any named pattern which uses this predicate
974 must force its operands to match 'U' before emitting RTL. */
976 if (GET_CODE (op) == REG)
978 if (GET_CODE (op) == SUBREG)
980 return (GET_CODE (op) == MEM
981 && EXTRA_CONSTRAINT (op, 'U'));
985 bit_memory_operand (op, mode)
987 enum machine_mode mode ATTRIBUTE_UNUSED;
989 return (GET_CODE (op) == MEM
990 && EXTRA_CONSTRAINT (op, 'U'));
993 /* Handle machine specific pragmas for compatibility with existing
994 compilers for the H8/300.
996 pragma saveall generates prologue/epilogue code which saves and
997 restores all the registers on function entry.
999 pragma interrupt saves and restores all registers, and exits with
1000 an rte instruction rather than an rts. A pointer to a function
1001 with this attribute may be safely used in an interrupt vector. */
1004 h8300_pr_interrupt (pfile)
1005 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1007 pragma_interrupt = 1;
1011 h8300_pr_saveall (pfile)
1012 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1017 /* If the next function argument with MODE and TYPE is to be passed in
1018 a register, return a reg RTX for the hard register in which to pass
1019 the argument. CUM represents the state after the last argument.
1020 If the argument is to be pushed, NULL_RTX is returned. */
1023 function_arg (cum, mode, type, named)
1024 CUMULATIVE_ARGS *cum;
1025 enum machine_mode mode;
1029 static const char *const hand_list[] = {
1048 rtx result = NULL_RTX;
1052 /* Never pass unnamed arguments in registers. */
1056 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1057 if (TARGET_QUICKCALL)
1060 /* If calling hand written assembler, use 4 regs of args. */
1063 const char * const *p;
1065 fname = XSTR (cum->libcall, 0);
1067 /* See if this libcall is one of the hand coded ones. */
1068 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1079 if (mode == BLKmode)
1080 size = int_size_in_bytes (type);
1082 size = GET_MODE_SIZE (mode);
1084 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1085 && cum->nbytes / UNITS_PER_WORD <= 3)
1086 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1098 if (GET_MODE (x) == QImode)
1101 if (GET_MODE (x) != HImode
1102 && GET_MODE (x) != SImode)
1107 operands[2] = XEXP (x, 1);
1109 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1113 h8300_shift_costs (x)
1118 if (GET_MODE (x) != QImode
1119 && GET_MODE (x) != HImode
1120 && GET_MODE (x) != SImode)
1125 operands[2] = XEXP (x, 1);
1127 return compute_a_shift_length (NULL, operands) / 2;
1131 h8300_rtx_costs (x, code, outer_code, total)
1133 int code, outer_code;
1140 HOST_WIDE_INT n = INTVAL (x);
1142 if (-4 <= n || n <= 4)
1153 *total = 0 + (outer_code == SET);
1157 if (TARGET_H8300H || TARGET_H8300S)
1158 *total = 0 + (outer_code == SET);
1179 *total = COSTS_N_INSNS (h8300_and_costs (x));
1182 /* We say that MOD and DIV are so expensive because otherwise we'll
1183 generate some really horrible code for division of a power of two. */
1196 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1201 if (GET_MODE (x) == HImode)
1213 /* Documentation for the machine specific operand escapes:
1215 'E' like s but negative.
1216 'F' like t but negative.
1217 'G' constant just the negative
1218 'R' print operand as a byte:8 address if appropriate, else fall back to
1220 'S' print operand as a long word
1221 'T' print operand as a word
1222 'V' find the set bit, and print its number.
1223 'W' find the clear bit, and print its number.
1224 'X' print operand as a byte
1225 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1226 If this operand isn't a register, fall back to 'R' handling.
1228 'c' print the opcode corresponding to rtl
1229 'e' first word of 32 bit value - if reg, then least reg. if mem
1230 then least. if const then most sig word
1231 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1232 then +2. if const then least sig word
1233 'j' print operand as condition code.
1234 'k' print operand as reverse condition code.
1235 's' print as low byte of 16 bit value
1236 't' print as high byte of 16 bit value
1237 'w' print as low byte of 32 bit value
1238 'x' print as 2nd byte of 32 bit value
1239 'y' print as 3rd byte of 32 bit value
1240 'z' print as msb of 32 bit value
1243 /* Return assembly language string which identifies a comparison type. */
1276 /* Print operand X using operand code CODE to assembly language output file
1280 print_operand (file, x, code)
1285 /* This is used for communication between codes V,W,Z and Y. */
1291 switch (GET_CODE (x))
1294 fprintf (file, "%sl", names_big[REGNO (x)]);
1297 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1304 switch (GET_CODE (x))
1307 fprintf (file, "%sh", names_big[REGNO (x)]);
1310 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1317 if (GET_CODE (x) != CONST_INT)
1319 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1322 if (GET_CODE (x) == REG)
1323 fprintf (file, "%s", names_extended[REGNO (x)]);
1328 if (GET_CODE (x) == REG)
1329 fprintf (file, "%s", names_big[REGNO (x)]);
1334 bitint = exact_log2 (INTVAL (x) & 0xff);
1337 fprintf (file, "#%d", bitint);
1340 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1343 fprintf (file, "#%d", bitint);
1347 if (GET_CODE (x) == REG)
1348 fprintf (file, "%s", byte_reg (x, 0));
1355 if (GET_CODE (x) == REG)
1356 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1358 print_operand (file, x, 'R');
1362 bitint = INTVAL (x);
1363 fprintf (file, "#%d", bitint & 7);
1366 switch (GET_CODE (x))
1369 fprintf (file, "or");
1372 fprintf (file, "xor");
1375 fprintf (file, "and");
1382 switch (GET_CODE (x))
1386 fprintf (file, "%s", names_big[REGNO (x)]);
1388 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1391 print_operand (file, x, 0);
1394 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1400 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1401 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1402 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1411 switch (GET_CODE (x))
1415 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1417 fprintf (file, "%s", names_big[REGNO (x)]);
1420 x = adjust_address (x, HImode, 2);
1421 print_operand (file, x, 0);
1424 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1430 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1431 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1432 fprintf (file, "#%ld", (val & 0xffff));
1440 fputs (cond_string (GET_CODE (x)), file);
1443 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1446 if (GET_CODE (x) == CONST_INT)
1447 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1449 fprintf (file, "%s", byte_reg (x, 0));
1452 if (GET_CODE (x) == CONST_INT)
1453 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1455 fprintf (file, "%s", byte_reg (x, 1));
1458 if (GET_CODE (x) == CONST_INT)
1459 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1461 fprintf (file, "%s",
1462 byte_reg (x, TARGET_H8300 ? 2 : 0));
1465 if (GET_CODE (x) == CONST_INT)
1466 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1468 fprintf (file, "%s",
1469 byte_reg (x, TARGET_H8300 ? 3 : 1));
1472 if (GET_CODE (x) == CONST_INT)
1473 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1475 fprintf (file, "%s", byte_reg (x, 0));
1478 if (GET_CODE (x) == CONST_INT)
1479 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1481 fprintf (file, "%s", byte_reg (x, 1));
1486 switch (GET_CODE (x))
1489 switch (GET_MODE (x))
1492 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1493 fprintf (file, "%s", byte_reg (x, 0));
1494 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1495 fprintf (file, "%s", names_big[REGNO (x)]);
1499 fprintf (file, "%s", names_big[REGNO (x)]);
1503 fprintf (file, "%s", names_extended[REGNO (x)]);
1512 rtx addr = XEXP (x, 0);
1514 fprintf (file, "@");
1515 output_address (addr);
1517 /* We fall back from smaller addressing to larger
1518 addressing in various ways depending on CODE. */
1522 /* Used for mov.b and bit operations. */
1523 if (h8300_eightbit_constant_address_p (addr))
1525 fprintf (file, ":8");
1529 /* Fall through. We should not get here if we are
1530 processing bit operations on H8/300 or H8/300H
1531 because 'U' constraint does not allow bit
1532 operations on the tiny area on these machines. */
1536 /* Used for mov.w and mov.l. */
1537 if (h8300_tiny_constant_address_p (addr))
1538 fprintf (file, ":16");
1550 fprintf (file, "#");
1551 print_operand_address (file, x);
1557 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1558 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1559 fprintf (file, "#%ld", val);
1568 /* Output assembly language output for the address ADDR to FILE. */
1571 print_operand_address (file, addr)
1575 switch (GET_CODE (addr))
1578 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1582 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1586 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1590 fprintf (file, "(");
1591 if (GET_CODE (XEXP (addr, 0)) == REG)
1594 print_operand_address (file, XEXP (addr, 1));
1595 fprintf (file, ",");
1596 print_operand_address (file, XEXP (addr, 0));
1601 print_operand_address (file, XEXP (addr, 0));
1602 fprintf (file, "+");
1603 print_operand_address (file, XEXP (addr, 1));
1605 fprintf (file, ")");
1610 /* Since the H8/300 only has 16 bit pointers, negative values are also
1611 those >= 32768. This happens for example with pointer minus a
1612 constant. We don't want to turn (char *p - 2) into
1613 (char *p + 65534) because loop unrolling can build upon this
1614 (IE: char *p + 131068). */
1615 int n = INTVAL (addr);
1617 n = (int) (short) n;
1618 fprintf (file, "%d", n);
1623 output_addr_const (file, addr);
1628 /* Output all insn addresses and their sizes into the assembly language
1629 output file. This is helpful for debugging whether the length attributes
1630 in the md file are correct. This is not meant to be a user selectable
1634 final_prescan_insn (insn, operand, num_operands)
1635 rtx insn, *operand ATTRIBUTE_UNUSED;
1636 int num_operands ATTRIBUTE_UNUSED;
1638 /* This holds the last insn address. */
1639 static int last_insn_address = 0;
1641 const int uid = INSN_UID (insn);
1643 if (TARGET_ADDRESSES)
1645 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1646 INSN_ADDRESSES (uid) - last_insn_address);
1647 last_insn_address = INSN_ADDRESSES (uid);
1651 /* Prepare for an SI sized move. */
1657 rtx src = operands[1];
1658 rtx dst = operands[0];
1659 if (!reload_in_progress && !reload_completed)
1661 if (!register_operand (dst, GET_MODE (dst)))
1663 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1664 emit_move_insn (tmp, src);
1671 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1672 Define the offset between two registers, one to be eliminated, and
1673 the other its replacement, at the start of a routine. */
1676 h8300_initial_elimination_offset (from, to)
1680 /* The number of bytes that the return address takes on the stack. */
1681 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1683 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1684 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1685 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1686 offset = frame_pointer_needed * UNITS_PER_WORD;
1691 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1692 if (WORD_REG_USED (regno))
1693 offset += UNITS_PER_WORD;
1695 /* See the comments for get_frame_size. We need to round it up to
1698 offset += round_frame_size (get_frame_size ());
1700 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1701 /* Skip saved PC. */
1709 h8300_return_addr_rtx (count, frame)
1716 ret = gen_rtx_MEM (Pmode,
1717 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1718 else if (flag_omit_frame_pointer)
1721 ret = gen_rtx_MEM (Pmode,
1722 memory_address (Pmode,
1723 plus_constant (frame, UNITS_PER_WORD)));
1724 set_mem_alias_set (ret, get_frame_alias_set ());
1728 /* Update the condition code from the insn. */
1731 notice_update_cc (body, insn)
1737 switch (get_attr_cc (insn))
1740 /* Insn does not affect CC at all. */
1744 /* Insn does not change CC, but the 0'th operand has been changed. */
1745 if (cc_status.value1 != 0
1746 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1747 cc_status.value1 = 0;
1748 if (cc_status.value2 != 0
1749 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1750 cc_status.value2 = 0;
1754 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1755 The V flag is unusable. The C flag may or may not be known but
1756 that's ok because alter_cond will change tests to use EQ/NE. */
1758 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1759 set = single_set (insn);
1760 cc_status.value1 = SET_SRC (set);
1761 if (SET_DEST (set) != cc0_rtx)
1762 cc_status.value2 = SET_DEST (set);
1766 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1767 The C flag may or may not be known but that's ok because
1768 alter_cond will change tests to use EQ/NE. */
1770 cc_status.flags |= CC_NO_CARRY;
1771 set = single_set (insn);
1772 cc_status.value1 = SET_SRC (set);
1773 if (SET_DEST (set) != cc0_rtx)
1775 /* If the destination is STRICT_LOW_PART, strip off
1777 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1778 cc_status.value2 = XEXP (SET_DEST (set), 0);
1780 cc_status.value2 = SET_DEST (set);
1785 /* The insn is a compare instruction. */
1787 cc_status.value1 = SET_SRC (body);
1791 /* Insn doesn't leave CC in a usable state. */
1797 /* Return nonzero if X is a stack pointer. */
1800 stack_pointer_operand (x, mode)
1802 enum machine_mode mode ATTRIBUTE_UNUSED;
1804 return x == stack_pointer_rtx;
1807 /* Return nonzero if X is a constant whose absolute value is greater
1811 const_int_gt_2_operand (x, mode)
1813 enum machine_mode mode ATTRIBUTE_UNUSED;
1815 return (GET_CODE (x) == CONST_INT
1816 && abs (INTVAL (x)) > 2);
1819 /* Return nonzero if X is a constant whose absolute value is no
1823 const_int_ge_8_operand (x, mode)
1825 enum machine_mode mode ATTRIBUTE_UNUSED;
1827 return (GET_CODE (x) == CONST_INT
1828 && abs (INTVAL (x)) >= 8);
1831 /* Return nonzero if X is a constant expressible in QImode. */
1834 const_int_qi_operand (x, mode)
1836 enum machine_mode mode ATTRIBUTE_UNUSED;
1838 return (GET_CODE (x) == CONST_INT
1839 && (INTVAL (x) & 0xff) == INTVAL (x));
1842 /* Return nonzero if X is a constant expressible in HImode. */
1845 const_int_hi_operand (x, mode)
1847 enum machine_mode mode ATTRIBUTE_UNUSED;
1849 return (GET_CODE (x) == CONST_INT
1850 && (INTVAL (x) & 0xffff) == INTVAL (x));
1853 /* Return nonzero if X is a constant suitable for inc/dec. */
1856 incdec_operand (x, mode)
1858 enum machine_mode mode ATTRIBUTE_UNUSED;
1860 return (GET_CODE (x) == CONST_INT
1861 && (CONST_OK_FOR_M (INTVAL (x))
1862 || CONST_OK_FOR_O (INTVAL (x))));
1865 /* Return nonzero if X is either EQ or NE. */
1868 eqne_operator (x, mode)
1870 enum machine_mode mode ATTRIBUTE_UNUSED;
1872 enum rtx_code code = GET_CODE (x);
1874 return (code == EQ || code == NE);
1877 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1880 gtle_operator (x, mode)
1882 enum machine_mode mode ATTRIBUTE_UNUSED;
1884 enum rtx_code code = GET_CODE (x);
1886 return (code == GT || code == LE || code == GTU || code == LEU);
1889 /* Return nonzero if X is either GTU or LEU. */
1892 gtuleu_operator (x, mode)
1894 enum machine_mode mode ATTRIBUTE_UNUSED;
1896 enum rtx_code code = GET_CODE (x);
1898 return (code == GTU || code == LEU);
1901 /* Return nonzero if X is either IOR or XOR. */
1904 iorxor_operator (x, mode)
1906 enum machine_mode mode ATTRIBUTE_UNUSED;
1908 enum rtx_code code = GET_CODE (x);
1910 return (code == IOR || code == XOR);
1913 /* Recognize valid operators for bit instructions. */
1916 bit_operator (x, mode)
1918 enum machine_mode mode ATTRIBUTE_UNUSED;
1920 enum rtx_code code = GET_CODE (x);
1928 output_plussi (operands)
1931 enum machine_mode mode = GET_MODE (operands[0]);
1938 if (GET_CODE (operands[2]) == REG)
1939 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1941 if (GET_CODE (operands[2]) == CONST_INT)
1943 HOST_WIDE_INT n = INTVAL (operands[2]);
1945 if ((n & 0xffffff) == 0)
1946 return "add\t%z2,%z0";
1947 if ((n & 0xffff) == 0)
1948 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
1949 if ((n & 0xff) == 0)
1950 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1953 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1957 if (GET_CODE (operands[2]) == REG)
1958 return "add.l\t%S2,%S0";
1960 if (GET_CODE (operands[2]) == CONST_INT)
1962 HOST_WIDE_INT intval = INTVAL (operands[2]);
1964 /* See if we can finish with 2 bytes. */
1966 switch ((unsigned int) intval & 0xffffffff)
1971 return "adds\t%2,%S0";
1976 return "subs\t%G2,%S0";
1980 operands[2] = GEN_INT (intval >> 16);
1981 return "inc.w\t%2,%e0";
1985 operands[2] = GEN_INT (intval >> 16);
1986 return "dec.w\t%G2,%e0";
1989 /* See if we can finish with 4 bytes. */
1990 if ((intval & 0xffff) == 0)
1992 operands[2] = GEN_INT (intval >> 16);
1993 return "add.w\t%2,%e0";
1997 return "add.l\t%S2,%S0";
2002 compute_plussi_length (operands)
2005 enum machine_mode mode = GET_MODE (operands[0]);
2012 if (GET_CODE (operands[2]) == REG)
2015 if (GET_CODE (operands[2]) == CONST_INT)
2017 HOST_WIDE_INT n = INTVAL (operands[2]);
2019 if ((n & 0xffffff) == 0)
2021 if ((n & 0xffff) == 0)
2023 if ((n & 0xff) == 0)
2031 if (GET_CODE (operands[2]) == REG)
2034 if (GET_CODE (operands[2]) == CONST_INT)
2036 HOST_WIDE_INT intval = INTVAL (operands[2]);
2038 /* See if we can finish with 2 bytes. */
2040 switch ((unsigned int) intval & 0xffffffff)
2061 /* See if we can finish with 4 bytes. */
2062 if ((intval & 0xffff) == 0)
2071 compute_plussi_cc (operands)
2074 enum machine_mode mode = GET_MODE (operands[0]);
2085 if (GET_CODE (operands[2]) == REG)
2088 if (GET_CODE (operands[2]) == CONST_INT)
2090 HOST_WIDE_INT intval = INTVAL (operands[2]);
2092 /* See if we can finish with 2 bytes. */
2094 switch ((unsigned int) intval & 0xffffffff)
2099 return CC_NONE_0HIT;
2104 return CC_NONE_0HIT;
2115 /* See if we can finish with 4 bytes. */
2116 if ((intval & 0xffff) == 0)
2125 output_logical_op (mode, operands)
2126 enum machine_mode mode;
2129 /* Figure out the logical op that we need to perform. */
2130 enum rtx_code code = GET_CODE (operands[3]);
2131 /* Pretend that every byte is affected if both operands are registers. */
2132 const unsigned HOST_WIDE_INT intval =
2133 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2134 ? INTVAL (operands[2]) : 0x55555555);
2135 /* The determinant of the algorithm. If we perform an AND, 0
2136 affects a bit. Otherwise, 1 affects a bit. */
2137 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2138 /* Break up DET into pieces. */
2139 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2140 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2141 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2142 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2143 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2144 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2145 int lower_half_easy_p = 0;
2146 int upper_half_easy_p = 0;
2147 /* The name of an insn. */
2169 /* First, see if we can finish with one insn. */
2170 if ((TARGET_H8300H || TARGET_H8300S)
2174 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2175 output_asm_insn (insn_buf, operands);
2179 /* Take care of the lower byte. */
2182 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2183 output_asm_insn (insn_buf, operands);
2185 /* Take care of the upper byte. */
2188 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2189 output_asm_insn (insn_buf, operands);
2194 if (TARGET_H8300H || TARGET_H8300S)
2196 /* Determine if the lower half can be taken care of in no more
2198 lower_half_easy_p = (b0 == 0
2200 || (code != IOR && w0 == 0xffff));
2202 /* Determine if the upper half can be taken care of in no more
2204 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2205 || (code == AND && w1 == 0xff00));
2208 /* Check if doing everything with one insn is no worse than
2209 using multiple insns. */
2210 if ((TARGET_H8300H || TARGET_H8300S)
2211 && w0 != 0 && w1 != 0
2212 && !(lower_half_easy_p && upper_half_easy_p)
2213 && !(code == IOR && w1 == 0xffff
2214 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2216 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2217 output_asm_insn (insn_buf, operands);
2221 /* Take care of the lower and upper words individually. For
2222 each word, we try different methods in the order of
2224 1) the special insn (in case of AND or XOR),
2225 2) the word-wise insn, and
2226 3) The byte-wise insn. */
2228 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2229 output_asm_insn ((code == AND)
2230 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2232 else if ((TARGET_H8300H || TARGET_H8300S)
2236 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2237 output_asm_insn (insn_buf, operands);
2243 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2244 output_asm_insn (insn_buf, operands);
2248 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2249 output_asm_insn (insn_buf, operands);
2254 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2255 output_asm_insn ((code == AND)
2256 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2258 else if ((TARGET_H8300H || TARGET_H8300S)
2261 && (w0 & 0x8000) != 0)
2263 output_asm_insn ("exts.l\t%S0", operands);
2265 else if ((TARGET_H8300H || TARGET_H8300S)
2269 output_asm_insn ("extu.w\t%e0", operands);
2271 else if (TARGET_H8300H || TARGET_H8300S)
2275 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2276 output_asm_insn (insn_buf, operands);
2283 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2284 output_asm_insn (insn_buf, operands);
2288 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2289 output_asm_insn (insn_buf, operands);
2301 compute_logical_op_length (mode, operands)
2302 enum machine_mode mode;
2305 /* Figure out the logical op that we need to perform. */
2306 enum rtx_code code = GET_CODE (operands[3]);
2307 /* Pretend that every byte is affected if both operands are registers. */
2308 const unsigned HOST_WIDE_INT intval =
2309 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2310 ? INTVAL (operands[2]) : 0x55555555);
2311 /* The determinant of the algorithm. If we perform an AND, 0
2312 affects a bit. Otherwise, 1 affects a bit. */
2313 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2314 /* Break up DET into pieces. */
2315 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2316 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2317 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2318 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2319 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2320 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2321 int lower_half_easy_p = 0;
2322 int upper_half_easy_p = 0;
2324 unsigned int length = 0;
2329 /* First, see if we can finish with one insn. */
2330 if ((TARGET_H8300H || TARGET_H8300S)
2334 if (REG_P (operands[2]))
2341 /* Take care of the lower byte. */
2345 /* Take care of the upper byte. */
2351 if (TARGET_H8300H || TARGET_H8300S)
2353 /* Determine if the lower half can be taken care of in no more
2355 lower_half_easy_p = (b0 == 0
2357 || (code != IOR && w0 == 0xffff));
2359 /* Determine if the upper half can be taken care of in no more
2361 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2362 || (code == AND && w1 == 0xff00));
2365 /* Check if doing everything with one insn is no worse than
2366 using multiple insns. */
2367 if ((TARGET_H8300H || TARGET_H8300S)
2368 && w0 != 0 && w1 != 0
2369 && !(lower_half_easy_p && upper_half_easy_p)
2370 && !(code == IOR && w1 == 0xffff
2371 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2373 if (REG_P (operands[2]))
2380 /* Take care of the lower and upper words individually. For
2381 each word, we try different methods in the order of
2383 1) the special insn (in case of AND or XOR),
2384 2) the word-wise insn, and
2385 3) The byte-wise insn. */
2387 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2391 else if ((TARGET_H8300H || TARGET_H8300S)
2407 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2411 else if ((TARGET_H8300H || TARGET_H8300S)
2414 && (w0 & 0x8000) != 0)
2418 else if ((TARGET_H8300H || TARGET_H8300S)
2424 else if (TARGET_H8300H || TARGET_H8300S)
2446 compute_logical_op_cc (mode, operands)
2447 enum machine_mode mode;
2450 /* Figure out the logical op that we need to perform. */
2451 enum rtx_code code = GET_CODE (operands[3]);
2452 /* Pretend that every byte is affected if both operands are registers. */
2453 const unsigned HOST_WIDE_INT intval =
2454 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2455 ? INTVAL (operands[2]) : 0x55555555);
2456 /* The determinant of the algorithm. If we perform an AND, 0
2457 affects a bit. Otherwise, 1 affects a bit. */
2458 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2459 /* Break up DET into pieces. */
2460 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2461 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2462 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2463 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2464 int lower_half_easy_p = 0;
2465 int upper_half_easy_p = 0;
2466 /* Condition code. */
2467 enum attr_cc cc = CC_CLOBBER;
2472 /* First, see if we can finish with one insn. */
2473 if ((TARGET_H8300H || TARGET_H8300S)
2481 if (TARGET_H8300H || TARGET_H8300S)
2483 /* Determine if the lower half can be taken care of in no more
2485 lower_half_easy_p = (b0 == 0
2487 || (code != IOR && w0 == 0xffff));
2489 /* Determine if the upper half can be taken care of in no more
2491 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2492 || (code == AND && w1 == 0xff00));
2495 /* Check if doing everything with one insn is no worse than
2496 using multiple insns. */
2497 if ((TARGET_H8300H || TARGET_H8300S)
2498 && w0 != 0 && w1 != 0
2499 && !(lower_half_easy_p && upper_half_easy_p)
2500 && !(code == IOR && w1 == 0xffff
2501 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2507 if ((TARGET_H8300H || TARGET_H8300S)
2510 && (w0 & 0x8000) != 0)
2524 We devote a fair bit of code to getting efficient shifts since we
2525 can only shift one bit at a time on the H8/300 and H8/300H and only
2526 one or two bits at a time on the H8S.
2528 All shift code falls into one of the following ways of
2531 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2532 when a straight line shift is about the same size or smaller than
2535 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2536 off the bits we don't need. This is used when only a few of the
2537 bits in the original value will survive in the shifted value.
2539 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2540 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2541 shifts can be added if the shift count is slightly more than 8 or
2542 16. This case also includes other oddballs that are not worth
2545 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2547 For each shift count, we try to use code that has no trade-off
2548 between code size and speed whenever possible.
2550 If the trade-off is unavoidable, we try to be reasonable.
2551 Specifically, the fastest version is one instruction longer than
2552 the shortest version, we take the fastest version. We also provide
2553 the use a way to switch back to the shortest version with -Os.
2555 For the details of the shift algorithms for various shift counts,
2556 refer to shift_alg_[qhs]i. */
2559 nshift_operator (x, mode)
2561 enum machine_mode mode ATTRIBUTE_UNUSED;
2563 switch (GET_CODE (x))
2575 /* Emit code to do shifts. */
2578 expand_a_shift (mode, code, operands)
2579 enum machine_mode mode;
2583 emit_move_insn (operands[0], operands[1]);
2585 /* Need a loop to get all the bits we want - we generate the
2586 code at emit time, but need to allocate a scratch reg now. */
2588 emit_insn (gen_rtx_PARALLEL
2591 gen_rtx_SET (VOIDmode, operands[0],
2592 gen_rtx (code, mode, operands[0],
2594 gen_rtx_CLOBBER (VOIDmode,
2595 gen_rtx_SCRATCH (QImode)))));
2598 /* Symbols of the various modes which can be used as indices. */
2602 QIshift, HIshift, SIshift
2605 /* For single bit shift insns, record assembler and what bits of the
2606 condition code are valid afterwards (represented as various CC_FOO
2607 bits, 0 means CC isn't left in a usable state). */
2611 const char *const assembler;
2615 /* Assembler instruction shift table.
2617 These tables are used to look up the basic shifts.
2618 They are indexed by cpu, shift_type, and mode. */
2620 static const struct shift_insn shift_one[2][3][3] =
2626 { "shll\t%X0", CC_SET_ZNV },
2627 { "add.w\t%T0,%T0", CC_SET_ZN },
2628 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2630 /* SHIFT_LSHIFTRT */
2632 { "shlr\t%X0", CC_SET_ZNV },
2633 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2634 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2636 /* SHIFT_ASHIFTRT */
2638 { "shar\t%X0", CC_SET_ZNV },
2639 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2640 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2647 { "shll.b\t%X0", CC_SET_ZNV },
2648 { "shll.w\t%T0", CC_SET_ZNV },
2649 { "shll.l\t%S0", CC_SET_ZNV }
2651 /* SHIFT_LSHIFTRT */
2653 { "shlr.b\t%X0", CC_SET_ZNV },
2654 { "shlr.w\t%T0", CC_SET_ZNV },
2655 { "shlr.l\t%S0", CC_SET_ZNV }
2657 /* SHIFT_ASHIFTRT */
2659 { "shar.b\t%X0", CC_SET_ZNV },
2660 { "shar.w\t%T0", CC_SET_ZNV },
2661 { "shar.l\t%S0", CC_SET_ZNV }
2666 static const struct shift_insn shift_two[3][3] =
2670 { "shll.b\t#2,%X0", CC_SET_ZNV },
2671 { "shll.w\t#2,%T0", CC_SET_ZNV },
2672 { "shll.l\t#2,%S0", CC_SET_ZNV }
2674 /* SHIFT_LSHIFTRT */
2676 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2677 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2678 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2680 /* SHIFT_ASHIFTRT */
2682 { "shar.b\t#2,%X0", CC_SET_ZNV },
2683 { "shar.w\t#2,%T0", CC_SET_ZNV },
2684 { "shar.l\t#2,%S0", CC_SET_ZNV }
2688 /* Rotates are organized by which shift they'll be used in implementing.
2689 There's no need to record whether the cc is valid afterwards because
2690 it is the AND insn that will decide this. */
2692 static const char *const rotate_one[2][3][3] =
2699 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2702 /* SHIFT_LSHIFTRT */
2705 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2708 /* SHIFT_ASHIFTRT */
2711 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2723 /* SHIFT_LSHIFTRT */
2729 /* SHIFT_ASHIFTRT */
2738 static const char *const rotate_two[3][3] =
2746 /* SHIFT_LSHIFTRT */
2752 /* SHIFT_ASHIFTRT */
2761 /* Shift algorithm. */
2764 /* The number of bits to be shifted by shift1 and shift2. Valid
2765 when ALG is SHIFT_SPECIAL. */
2766 unsigned int remainder;
2768 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2769 const char *special;
2771 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2772 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2775 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2776 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2779 /* CC status for SHIFT_INLINE. */
2782 /* CC status for SHIFT_SPECIAL. */
2786 static void get_shift_alg PARAMS ((enum shift_type,
2787 enum shift_mode, unsigned int,
2788 struct shift_info *));
2790 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2791 best algorithm for doing the shift. The assembler code is stored
2792 in the pointers in INFO. We achieve the maximum efficiency in most
2793 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2794 SImode in particular have a lot of room to optimize.
2796 We first determine the strategy of the shift algorithm by a table
2797 lookup. If that tells us to use a hand crafted assembly code, we
2798 go into the big switch statement to find what that is. Otherwise,
2799 we resort to a generic way, such as inlining. In either case, the
2800 result is returned through INFO. */
2803 get_shift_alg (shift_type, shift_mode, count, info)
2804 enum shift_type shift_type;
2805 enum shift_mode shift_mode;
2807 struct shift_info *info;
2811 /* Find the target CPU. */
2814 else if (TARGET_H8300H)
2819 /* Find the shift algorithm. */
2820 info->alg = SHIFT_LOOP;
2824 if (count < GET_MODE_BITSIZE (QImode))
2825 info->alg = shift_alg_qi[cpu][shift_type][count];
2829 if (count < GET_MODE_BITSIZE (HImode))
2830 info->alg = shift_alg_hi[cpu][shift_type][count];
2834 if (count < GET_MODE_BITSIZE (SImode))
2835 info->alg = shift_alg_si[cpu][shift_type][count];
2842 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2846 info->remainder = count;
2850 /* It is up to the caller to know that looping clobbers cc. */
2851 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2852 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2853 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2857 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2858 info->shift2 = rotate_two[shift_type][shift_mode];
2859 info->cc_inline = CC_CLOBBER;
2863 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2864 info->remainder = 0;
2865 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2866 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2867 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2868 info->cc_special = CC_CLOBBER;
2872 /* Here we only deal with SHIFT_SPECIAL. */
2876 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2877 through the entire value. */
2878 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2880 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2892 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2894 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2896 case SHIFT_LSHIFTRT:
2898 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2900 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2902 case SHIFT_ASHIFTRT:
2903 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2907 else if ((8 <= count && count <= 13)
2908 || (TARGET_H8300S && count == 14))
2910 info->remainder = count - 8;
2915 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2917 case SHIFT_LSHIFTRT:
2920 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2921 info->shift1 = "shlr.b\t%s0";
2922 info->cc_inline = CC_SET_ZNV;
2926 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
2927 info->cc_special = CC_SET_ZNV;
2930 case SHIFT_ASHIFTRT:
2933 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2934 info->shift1 = "shar.b\t%s0";
2938 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2939 info->cc_special = CC_SET_ZNV;
2944 else if (count == 14)
2950 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2952 case SHIFT_LSHIFTRT:
2954 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2956 case SHIFT_ASHIFTRT:
2958 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2959 else if (TARGET_H8300H)
2961 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2962 info->cc_special = CC_SET_ZNV;
2964 else /* TARGET_H8300S */
2969 else if (count == 15)
2974 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
2976 case SHIFT_LSHIFTRT:
2977 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
2979 case SHIFT_ASHIFTRT:
2980 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2987 if (TARGET_H8300 && 8 <= count && count <= 9)
2989 info->remainder = count - 8;
2994 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2996 case SHIFT_LSHIFTRT:
2997 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2998 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3000 case SHIFT_ASHIFTRT:
3001 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3005 else if (count == 8 && !TARGET_H8300)
3010 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3012 case SHIFT_LSHIFTRT:
3013 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3015 case SHIFT_ASHIFTRT:
3016 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3020 else if (count == 15 && TARGET_H8300)
3026 case SHIFT_LSHIFTRT:
3027 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
3029 case SHIFT_ASHIFTRT:
3030 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3034 else if (count == 15 && !TARGET_H8300)
3039 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3040 info->cc_special = CC_SET_ZNV;
3042 case SHIFT_LSHIFTRT:
3043 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3044 info->cc_special = CC_SET_ZNV;
3046 case SHIFT_ASHIFTRT:
3050 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3051 || (TARGET_H8300H && 16 <= count && count <= 19)
3052 || (TARGET_H8300S && 16 <= count && count <= 21))
3054 info->remainder = count - 16;
3059 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3061 info->shift1 = "add.w\t%e0,%e0";
3063 case SHIFT_LSHIFTRT:
3066 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3067 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3071 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3072 info->cc_special = CC_SET_ZNV;
3075 case SHIFT_ASHIFTRT:
3078 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3079 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3083 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3084 info->cc_special = CC_SET_ZNV;
3089 else if (TARGET_H8300 && 24 <= count && count <= 28)
3091 info->remainder = count - 24;
3096 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3097 info->shift1 = "shll.b\t%z0";
3098 info->cc_inline = CC_SET_ZNV;
3100 case SHIFT_LSHIFTRT:
3101 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3102 info->shift1 = "shlr.b\t%w0";
3103 info->cc_inline = CC_SET_ZNV;
3105 case SHIFT_ASHIFTRT:
3106 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3107 info->shift1 = "shar.b\t%w0";
3108 info->cc_inline = CC_SET_ZNV;
3112 else if ((TARGET_H8300H && count == 24)
3113 || (TARGET_H8300S && 24 <= count && count <= 25))
3115 info->remainder = count - 24;
3120 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3122 case SHIFT_LSHIFTRT:
3123 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3124 info->cc_special = CC_SET_ZNV;
3126 case SHIFT_ASHIFTRT:
3127 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3128 info->cc_special = CC_SET_ZNV;
3132 else if (!TARGET_H8300 && count == 28)
3138 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3140 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3142 case SHIFT_LSHIFTRT:
3145 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3146 info->cc_special = CC_SET_ZNV;
3149 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3151 case SHIFT_ASHIFTRT:
3155 else if (!TARGET_H8300 && count == 29)
3161 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3163 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3165 case SHIFT_LSHIFTRT:
3168 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3169 info->cc_special = CC_SET_ZNV;
3173 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3174 info->cc_special = CC_SET_ZNV;
3177 case SHIFT_ASHIFTRT:
3181 else if (!TARGET_H8300 && count == 30)
3187 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3189 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3191 case SHIFT_LSHIFTRT:
3193 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3195 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3197 case SHIFT_ASHIFTRT:
3201 else if (count == 31)
3208 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3210 case SHIFT_LSHIFTRT:
3211 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3213 case SHIFT_ASHIFTRT:
3214 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3223 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3224 info->cc_special = CC_SET_ZNV;
3226 case SHIFT_LSHIFTRT:
3227 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3228 info->cc_special = CC_SET_ZNV;
3230 case SHIFT_ASHIFTRT:
3231 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3232 info->cc_special = CC_SET_ZNV;
3245 info->shift2 = NULL;
3248 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3249 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3252 h8300_shift_needs_scratch_p (count, mode)
3254 enum machine_mode mode;
3259 if (GET_MODE_BITSIZE (mode) <= count)
3262 /* Find out the target CPU. */
3265 else if (TARGET_H8300H)
3270 /* Find the shift algorithm. */
3274 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3275 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3276 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3280 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3281 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3282 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3286 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3287 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3288 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3295 /* On H8/300H, count == 8 uses a scratch register. */
3296 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3297 || (TARGET_H8300H && mode == SImode && count == 8));
3300 /* Emit the assembler code for doing shifts. */
3303 output_a_shift (operands)
3306 static int loopend_lab;
3307 rtx shift = operands[3];
3308 enum machine_mode mode = GET_MODE (shift);
3309 enum rtx_code code = GET_CODE (shift);
3310 enum shift_type shift_type;
3311 enum shift_mode shift_mode;
3312 struct shift_info info;
3319 shift_mode = QIshift;
3322 shift_mode = HIshift;
3325 shift_mode = SIshift;
3334 shift_type = SHIFT_ASHIFTRT;
3337 shift_type = SHIFT_LSHIFTRT;
3340 shift_type = SHIFT_ASHIFT;
3346 if (GET_CODE (operands[2]) != CONST_INT)
3348 /* This case must be taken care of by one of the two splitters
3349 that convert a variable shift into a loop. */
3354 int n = INTVAL (operands[2]);
3356 /* If the count is negative, make it 0. */
3359 /* If the count is too big, truncate it.
3360 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3361 do the intuitive thing. */
3362 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3363 n = GET_MODE_BITSIZE (mode);
3365 get_shift_alg (shift_type, shift_mode, n, &info);
3370 output_asm_insn (info.special, operands);
3376 /* Emit two bit shifts first. */
3377 if (info.shift2 != NULL)
3379 for (; n > 1; n -= 2)
3380 output_asm_insn (info.shift2, operands);
3383 /* Now emit one bit shifts for any residual. */
3385 output_asm_insn (info.shift1, operands);
3390 int m = GET_MODE_BITSIZE (mode) - n;
3391 const int mask = (shift_type == SHIFT_ASHIFT
3392 ? ((1 << m) - 1) << n
3396 /* Not all possibilities of rotate are supported. They shouldn't
3397 be generated, but let's watch for 'em. */
3398 if (info.shift1 == 0)
3401 /* Emit two bit rotates first. */
3402 if (info.shift2 != NULL)
3404 for (; m > 1; m -= 2)
3405 output_asm_insn (info.shift2, operands);
3408 /* Now single bit rotates for any residual. */
3410 output_asm_insn (info.shift1, operands);
3412 /* Now mask off the high bits. */
3414 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3415 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3416 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3420 output_asm_insn (insn_buf, operands);
3425 /* A loop to shift by a "large" constant value.
3426 If we have shift-by-2 insns, use them. */
3427 if (info.shift2 != NULL)
3429 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3430 names_big[REGNO (operands[4])]);
3431 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3432 output_asm_insn (info.shift2, operands);
3433 output_asm_insn ("add #0xff,%X4", operands);
3434 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3436 output_asm_insn (info.shift1, operands);
3440 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3441 names_big[REGNO (operands[4])]);
3442 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3443 output_asm_insn (info.shift1, operands);
3444 output_asm_insn ("add #0xff,%X4", operands);
3445 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3456 h8300_asm_insn_count (template)
3457 const char *template;
3459 unsigned int count = 1;
3461 for (; *template; template++)
3462 if (*template == '\n')
3469 compute_a_shift_length (insn, operands)
3470 rtx insn ATTRIBUTE_UNUSED;
3473 rtx shift = operands[3];
3474 enum machine_mode mode = GET_MODE (shift);
3475 enum rtx_code code = GET_CODE (shift);
3476 enum shift_type shift_type;
3477 enum shift_mode shift_mode;
3478 struct shift_info info;
3479 unsigned int wlength = 0;
3484 shift_mode = QIshift;
3487 shift_mode = HIshift;
3490 shift_mode = SIshift;
3499 shift_type = SHIFT_ASHIFTRT;
3502 shift_type = SHIFT_LSHIFTRT;
3505 shift_type = SHIFT_ASHIFT;
3511 if (GET_CODE (operands[2]) != CONST_INT)
3513 /* Get the assembler code to do one shift. */
3514 get_shift_alg (shift_type, shift_mode, 1, &info);
3516 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3520 int n = INTVAL (operands[2]);
3522 /* If the count is negative, make it 0. */
3525 /* If the count is too big, truncate it.
3526 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3527 do the intuitive thing. */
3528 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3529 n = GET_MODE_BITSIZE (mode);
3531 get_shift_alg (shift_type, shift_mode, n, &info);
3536 wlength += h8300_asm_insn_count (info.special);
3538 /* Every assembly instruction used in SHIFT_SPECIAL case
3539 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3540 see xor.l, we just pretend that xor.l counts as two insns
3541 so that the insn length will be computed correctly. */
3542 if (strstr (info.special, "xor.l") != NULL)
3550 if (info.shift2 != NULL)
3552 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3556 wlength += h8300_asm_insn_count (info.shift1) * n;
3562 int m = GET_MODE_BITSIZE (mode) - n;
3564 /* Not all possibilities of rotate are supported. They shouldn't
3565 be generated, but let's watch for 'em. */
3566 if (info.shift1 == 0)
3569 if (info.shift2 != NULL)
3571 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3575 wlength += h8300_asm_insn_count (info.shift1) * m;
3577 /* Now mask off the high bits. */
3598 /* A loop to shift by a "large" constant value.
3599 If we have shift-by-2 insns, use them. */
3600 if (info.shift2 != NULL)
3602 wlength += 3 + h8300_asm_insn_count (info.shift2);
3604 wlength += h8300_asm_insn_count (info.shift1);
3608 wlength += 3 + h8300_asm_insn_count (info.shift1);
3619 compute_a_shift_cc (insn, operands)
3620 rtx insn ATTRIBUTE_UNUSED;
3623 rtx shift = operands[3];
3624 enum machine_mode mode = GET_MODE (shift);
3625 enum rtx_code code = GET_CODE (shift);
3626 enum shift_type shift_type;
3627 enum shift_mode shift_mode;
3628 struct shift_info info;
3633 shift_mode = QIshift;
3636 shift_mode = HIshift;
3639 shift_mode = SIshift;
3648 shift_type = SHIFT_ASHIFTRT;
3651 shift_type = SHIFT_LSHIFTRT;
3654 shift_type = SHIFT_ASHIFT;
3660 if (GET_CODE (operands[2]) != CONST_INT)
3662 /* This case must be taken care of by one of the two splitters
3663 that convert a variable shift into a loop. */
3668 int n = INTVAL (operands[2]);
3670 /* If the count is negative, make it 0. */
3673 /* If the count is too big, truncate it.
3674 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3675 do the intuitive thing. */
3676 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3677 n = GET_MODE_BITSIZE (mode);
3679 get_shift_alg (shift_type, shift_mode, n, &info);
3684 if (info.remainder == 0)
3685 return info.cc_special;
3690 return info.cc_inline;
3693 /* This case always ends with an and instruction. */
3697 /* A loop to shift by a "large" constant value.
3698 If we have shift-by-2 insns, use them. */
3699 if (info.shift2 != NULL)
3702 return info.cc_inline;
3712 /* A rotation by a non-constant will cause a loop to be generated, in
3713 which a rotation by one bit is used. A rotation by a constant,
3714 including the one in the loop, will be taken care of by
3715 emit_a_rotate () at the insn emit time. */
3718 expand_a_rotate (code, operands)
3722 rtx dst = operands[0];
3723 rtx src = operands[1];
3724 rtx rotate_amount = operands[2];
3725 enum machine_mode mode = GET_MODE (dst);
3728 /* We rotate in place. */
3729 emit_move_insn (dst, src);
3731 if (GET_CODE (rotate_amount) != CONST_INT)
3733 rtx counter = gen_reg_rtx (QImode);
3734 rtx start_label = gen_label_rtx ();
3735 rtx end_label = gen_label_rtx ();
3737 /* If the rotate amount is less than or equal to 0,
3738 we go out of the loop. */
3739 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3740 QImode, 0, end_label);
3742 /* Initialize the loop counter. */
3743 emit_move_insn (counter, rotate_amount);
3745 emit_label (start_label);
3747 /* Rotate by one bit. */
3748 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3749 emit_insn (gen_rtx_SET (mode, dst, tmp));
3751 /* Decrement the counter by 1. */
3752 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3753 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3755 /* If the loop counter is nonzero, we go back to the beginning
3757 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3760 emit_label (end_label);
3764 /* Rotate by AMOUNT bits. */
3765 tmp = gen_rtx (code, mode, dst, rotate_amount);
3766 emit_insn (gen_rtx_SET (mode, dst, tmp));
3772 /* Emit rotate insns. */
3775 emit_a_rotate (code, operands)
3779 rtx dst = operands[0];
3780 rtx rotate_amount = operands[2];
3781 enum shift_mode rotate_mode;
3782 enum shift_type rotate_type;
3783 const char *insn_buf;
3786 enum machine_mode mode = GET_MODE (dst);
3788 if (GET_CODE (rotate_amount) != CONST_INT)
3794 rotate_mode = QIshift;
3797 rotate_mode = HIshift;
3800 rotate_mode = SIshift;
3809 rotate_type = SHIFT_ASHIFT;
3812 rotate_type = SHIFT_LSHIFTRT;
3818 amount = INTVAL (rotate_amount);
3820 /* Clean up AMOUNT. */
3823 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3824 amount = GET_MODE_BITSIZE (mode);
3826 /* Determine the faster direction. After this phase, amount will be
3827 at most a half of GET_MODE_BITSIZE (mode). */
3828 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3830 /* Flip the direction. */
3831 amount = GET_MODE_BITSIZE (mode) - amount;
3833 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3836 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3837 boost up the rotation. */
3838 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3839 || (mode == HImode && TARGET_H8300H && amount >= 6)
3840 || (mode == HImode && TARGET_H8300S && amount == 8)
3841 || (mode == SImode && TARGET_H8300H && amount >= 10)
3842 || (mode == SImode && TARGET_H8300S && amount >= 13))
3847 /* This code works on any family. */
3848 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3849 output_asm_insn (insn_buf, operands);
3853 /* This code works on the H8/300H and H8S. */
3854 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3855 output_asm_insn (insn_buf, operands);
3862 /* Adjust AMOUNT and flip the direction. */
3863 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3865 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3868 /* Emit rotate insns. */
3869 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3872 insn_buf = rotate_two[rotate_type][rotate_mode];
3874 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3876 for (; amount >= bits; amount -= bits)
3877 output_asm_insn (insn_buf, operands);
3883 /* Fix the operands of a gen_xxx so that it could become a bit
3887 fix_bit_operand (operands, what, type)
3892 /* The bit_operand predicate accepts any memory during RTL generation, but
3893 only 'U' memory afterwards, so if this is a MEM operand, we must force
3894 it to be valid for 'U' by reloading the address. */
3896 if ((what == 0 && single_zero_operand (operands[2], QImode))
3897 || (what == 1 && single_one_operand (operands[2], QImode)))
3899 /* OK to have a memory dest. */
3900 if (GET_CODE (operands[0]) == MEM
3901 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3903 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3904 copy_to_mode_reg (Pmode,
3905 XEXP (operands[0], 0)));
3906 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3910 if (GET_CODE (operands[1]) == MEM
3911 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3913 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3914 copy_to_mode_reg (Pmode,
3915 XEXP (operands[1], 0)));
3916 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3922 /* Dest and src op must be register. */
3924 operands[1] = force_reg (QImode, operands[1]);
3926 rtx res = gen_reg_rtx (QImode);
3927 emit_insn (gen_rtx_SET (VOIDmode, res,
3928 gen_rtx (type, QImode, operands[1], operands[2])));
3929 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3934 /* Return nonzero if FUNC is an interrupt function as specified
3935 by the "interrupt" attribute. */
3938 h8300_interrupt_function_p (func)
3943 if (TREE_CODE (func) != FUNCTION_DECL)
3946 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3947 return a != NULL_TREE;
3950 /* Return nonzero if FUNC is an OS_Task function as specified
3951 by the "OS_Task" attribute. */
3954 h8300_os_task_function_p (func)
3959 if (TREE_CODE (func) != FUNCTION_DECL)
3962 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3963 return a != NULL_TREE;
3966 /* Return nonzero if FUNC is a monitor function as specified
3967 by the "monitor" attribute. */
3970 h8300_monitor_function_p (func)
3975 if (TREE_CODE (func) != FUNCTION_DECL)
3978 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
3979 return a != NULL_TREE;
3982 /* Return nonzero if FUNC is a function that should be called
3983 through the function vector. */
3986 h8300_funcvec_function_p (func)
3991 if (TREE_CODE (func) != FUNCTION_DECL)
3994 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
3995 return a != NULL_TREE;
3998 /* Return nonzero if DECL is a variable that's in the eight bit
4002 h8300_eightbit_data_p (decl)
4007 if (TREE_CODE (decl) != VAR_DECL)
4010 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4011 return a != NULL_TREE;
4014 /* Return nonzero if DECL is a variable that's in the tiny
4018 h8300_tiny_data_p (decl)
4023 if (TREE_CODE (decl) != VAR_DECL)
4026 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4027 return a != NULL_TREE;
4030 /* Generate an 'interrupt_handler' attribute for decls. */
4033 h8300_insert_attributes (node, attributes)
4037 if (!pragma_interrupt
4038 || TREE_CODE (node) != FUNCTION_DECL)
4041 pragma_interrupt = 0;
4043 /* Add an 'interrupt_handler' attribute. */
4044 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4048 /* Supported attributes:
4050 interrupt_handler: output a prologue and epilogue suitable for an
4053 function_vector: This function should be called through the
4056 eightbit_data: This variable lives in the 8-bit data area and can
4057 be referenced with 8-bit absolute memory addresses.
4059 tiny_data: This variable lives in the tiny data area and can be
4060 referenced with 16-bit absolute memory references. */
4062 const struct attribute_spec h8300_attribute_table[] =
4064 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4065 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4066 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4067 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4068 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4069 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4070 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4071 { NULL, 0, 0, false, false, false, NULL }
4075 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4076 struct attribute_spec.handler. */
4078 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
4081 tree args ATTRIBUTE_UNUSED;
4082 int flags ATTRIBUTE_UNUSED;
4085 if (TREE_CODE (*node) != FUNCTION_DECL)
4087 warning ("`%s' attribute only applies to functions",
4088 IDENTIFIER_POINTER (name));
4089 *no_add_attrs = true;
4095 /* Handle an "eightbit_data" attribute; arguments as in
4096 struct attribute_spec.handler. */
4098 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
4101 tree args ATTRIBUTE_UNUSED;
4102 int flags ATTRIBUTE_UNUSED;
4107 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4109 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4113 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4114 *no_add_attrs = true;
4120 /* Handle an "tiny_data" attribute; arguments as in
4121 struct attribute_spec.handler. */
4123 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
4126 tree args ATTRIBUTE_UNUSED;
4127 int flags ATTRIBUTE_UNUSED;
4132 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4134 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4138 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4139 *no_add_attrs = true;
4145 /* Mark function vectors, and various small data objects. */
4148 h8300_encode_section_info (decl, rtl, first)
4153 int extra_flags = 0;
4155 default_encode_section_info (decl, rtl, first);
4157 if (TREE_CODE (decl) == FUNCTION_DECL
4158 && h8300_funcvec_function_p (decl))
4159 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4160 else if (TREE_CODE (decl) == VAR_DECL
4161 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4163 if (h8300_eightbit_data_p (decl))
4164 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4165 else if (first && h8300_tiny_data_p (decl))
4166 extra_flags = SYMBOL_FLAG_TINY_DATA;
4170 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4174 output_simode_bld (bild, operands)
4180 /* Clear the destination register. */
4181 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4183 /* Now output the bit load or bit inverse load, and store it in
4186 output_asm_insn ("bild\t%Z2,%Y1", operands);
4188 output_asm_insn ("bld\t%Z2,%Y1", operands);
4190 output_asm_insn ("bst\t#0,%w0", operands);
4194 /* Determine if we can clear the destination first. */
4195 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4196 && REGNO (operands[0]) != REGNO (operands[1]));
4199 output_asm_insn ("sub.l\t%S0,%S0", operands);
4201 /* Output the bit load or bit inverse load. */
4203 output_asm_insn ("bild\t%Z2,%Y1", operands);
4205 output_asm_insn ("bld\t%Z2,%Y1", operands);
4208 output_asm_insn ("xor.l\t%S0,%S0", operands);
4210 /* Perform the bit store. */
4211 output_asm_insn ("bst\t#0,%w0", operands);
4218 /* Given INSN and its current length LENGTH, return the adjustment
4219 (in bytes) to correctly compute INSN's length.
4221 We use this to get the lengths of various memory references correct. */
4224 h8300_adjust_insn_length (insn, length)
4226 int length ATTRIBUTE_UNUSED;
4228 rtx pat = PATTERN (insn);
4230 /* We must filter these out before calling get_attr_adjust_length. */
4231 if (GET_CODE (pat) == USE
4232 || GET_CODE (pat) == CLOBBER
4233 || GET_CODE (pat) == SEQUENCE
4234 || GET_CODE (pat) == ADDR_VEC
4235 || GET_CODE (pat) == ADDR_DIFF_VEC)
4238 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
4241 /* Adjust length for reg->mem and mem->reg copies. */
4242 if (GET_CODE (pat) == SET
4243 && (GET_CODE (SET_SRC (pat)) == MEM
4244 || GET_CODE (SET_DEST (pat)) == MEM))
4246 /* This insn might need a length adjustment. */
4249 if (GET_CODE (SET_SRC (pat)) == MEM)
4250 addr = XEXP (SET_SRC (pat), 0);
4252 addr = XEXP (SET_DEST (pat), 0);
4256 /* On the H8/300, we subtract the difference between the
4257 actual length and the longest one, which is @(d:16,ERs). */
4259 /* @Rs is 2 bytes shorter than the longest. */
4260 if (GET_CODE (addr) == REG)
4263 /* @aa:8 is 2 bytes shorter than the longest. */
4264 if (GET_MODE (SET_SRC (pat)) == QImode
4265 && h8300_eightbit_constant_address_p (addr))
4270 /* On the H8/300H and H8S, we subtract the difference
4271 between the actual length and the longest one, which is
4274 /* @ERs is 6 bytes shorter than the longest. */
4275 if (GET_CODE (addr) == REG)
4278 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4279 if (GET_CODE (addr) == PLUS
4280 && GET_CODE (XEXP (addr, 0)) == REG
4281 && GET_CODE (XEXP (addr, 1)) == CONST_INT
4282 && INTVAL (XEXP (addr, 1)) > -32768
4283 && INTVAL (XEXP (addr, 1)) < 32767)
4286 /* @aa:8 is 6 bytes shorter than the longest. */
4287 if (GET_MODE (SET_SRC (pat)) == QImode
4288 && h8300_eightbit_constant_address_p (addr))
4291 /* @aa:16 is 4 bytes shorter than the longest. */
4292 if (h8300_tiny_constant_address_p (addr))
4295 /* @aa:24 is 2 bytes shorter than the longest. */
4296 if (GET_CODE (addr) == CONST_INT)
4301 /* Loading some constants needs adjustment. */
4302 if (GET_CODE (pat) == SET
4303 && GET_CODE (SET_SRC (pat)) == CONST_INT
4304 && GET_MODE (SET_DEST (pat)) == SImode
4305 && INTVAL (SET_SRC (pat)) != 0)
4307 int val = INTVAL (SET_SRC (pat));
4310 && ((val & 0xffff) == 0
4311 || ((val >> 16) & 0xffff) == 0))
4314 if (TARGET_H8300H || TARGET_H8300S)
4316 if (val == (val & 0xff)
4317 || val == (val & 0xff00))
4320 switch (val & 0xffffffff)
4336 /* Rotations need various adjustments. */
4337 if (GET_CODE (pat) == SET
4338 && (GET_CODE (SET_SRC (pat)) == ROTATE
4339 || GET_CODE (SET_SRC (pat)) == ROTATERT))
4341 rtx src = SET_SRC (pat);
4342 enum machine_mode mode = GET_MODE (src);
4346 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
4349 amount = INTVAL (XEXP (src, 1));
4351 /* Clean up AMOUNT. */
4354 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4355 amount = GET_MODE_BITSIZE (mode);
4357 /* Determine the faster direction. After this phase, amount
4358 will be at most a half of GET_MODE_BITSIZE (mode). */
4359 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4360 /* Flip the direction. */
4361 amount = GET_MODE_BITSIZE (mode) - amount;
4363 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4364 boost up the rotation. */
4365 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4366 || (mode == HImode && TARGET_H8300H && amount >= 6)
4367 || (mode == HImode && TARGET_H8300S && amount == 8)
4368 || (mode == SImode && TARGET_H8300H && amount >= 10)
4369 || (mode == SImode && TARGET_H8300S && amount >= 13))
4371 /* Adjust AMOUNT and flip the direction. */
4372 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4376 /* We use 2-bit rotations on the H8S. */
4378 amount = amount / 2 + amount % 2;
4380 /* The H8/300 uses three insns to rotate one bit, taking 6
4382 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4384 return -(20 - states);
4390 #ifndef OBJECT_FORMAT_ELF
4392 h8300_asm_named_section (name, flags)
4394 unsigned int flags ATTRIBUTE_UNUSED;
4396 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4397 fprintf (asm_out_file, "\t.section %s\n", name);
4399 #endif /* ! OBJECT_FORMAT_ELF */
4401 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4402 which is a special case of the 'R' operand. */
4405 h8300_eightbit_constant_address_p (x)
4408 /* The ranges of the 8-bit area. */
4409 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4410 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4411 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4412 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4413 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4414 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4416 unsigned HOST_WIDE_INT addr;
4418 /* We accept symbols declared with eightbit_data. */
4419 if (GET_CODE (x) == SYMBOL_REF)
4420 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4422 if (GET_CODE (x) != CONST_INT)
4428 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4429 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4430 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4433 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4434 on H8/300H and H8S. */
4437 h8300_tiny_constant_address_p (x)
4440 /* The ranges of the 16-bit area. */
4441 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4442 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4443 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4444 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4445 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4446 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4447 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4448 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4450 unsigned HOST_WIDE_INT addr;
4452 /* We accept symbols declared with tiny_data. */
4453 if (GET_CODE (x) == SYMBOL_REF)
4454 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
4456 if (GET_CODE (x) != CONST_INT)
4462 || TARGET_NORMAL_MODE
4464 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4466 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4470 byte_accesses_mergeable_p (addr1, addr2)
4473 HOST_WIDE_INT offset1, offset2;
4481 else if (GET_CODE (addr1) == PLUS
4482 && REG_P (XEXP (addr1, 0))
4483 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4485 reg1 = XEXP (addr1, 0);
4486 offset1 = INTVAL (XEXP (addr1, 1));
4496 else if (GET_CODE (addr2) == PLUS
4497 && REG_P (XEXP (addr2, 0))
4498 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4500 reg2 = XEXP (addr2, 0);
4501 offset2 = INTVAL (XEXP (addr2, 1));
4506 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4507 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4509 && offset1 + 1 == offset2)