1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "target-def.h"
46 /* Forward declarations. */
47 static int h8300_interrupt_function_p PARAMS ((tree));
48 static int h8300_monitor_function_p PARAMS ((tree));
49 static int h8300_os_task_function_p PARAMS ((tree));
50 static void dosize PARAMS ((FILE *, const char *, unsigned int));
51 static int round_frame_size PARAMS ((int));
52 static unsigned int compute_saved_regs PARAMS ((void));
53 static void push PARAMS ((FILE *, int));
54 static void pop PARAMS ((FILE *, int));
55 static const char *cond_string PARAMS ((enum rtx_code));
56 const struct attribute_spec h8300_attribute_table[];
57 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
58 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
59 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
60 static void h8300_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
61 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
62 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
64 /* CPU_TYPE, says what cpu we're compiling for. */
67 /* True if the current function is an interrupt handler
68 (either via #pragma or an attribute specification). */
69 int interrupt_handler;
71 /* True if the current function is an OS Task
72 (via an attribute specification). */
75 /* True if the current function is a monitor
76 (via an attribute specification). */
79 /* True if a #pragma saveall has been seen for the current function. */
82 static const char *const names_big[] =
83 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
85 static const char *const names_extended[] =
86 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
88 static const char *const names_upper_extended[] =
89 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
91 /* Points to one of the above. */
92 /* ??? The above could be put in an array indexed by CPU_TYPE. */
93 const char * const *h8_reg_names;
95 /* Various operations needed by the following, indexed by CPU_TYPE. */
97 static const char *const h8_push_ops[2] = { "push", "push.l" };
98 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
99 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
101 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
103 /* Initialize the GCC target structure. */
104 #undef TARGET_ATTRIBUTE_TABLE
105 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
107 #undef TARGET_ASM_FUNCTION_PROLOGUE
108 #define TARGET_ASM_FUNCTION_PROLOGUE h8300_output_function_prologue
109 #undef TARGET_ASM_FUNCTION_EPILOGUE
110 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
112 struct gcc_target targetm = TARGET_INITIALIZER;
114 /* Initialize various cpu specific globals at start up. */
121 cpu_type = (int) CPU_H8300;
122 h8_reg_names = names_big;
126 /* For this we treat the H8/300H and H8/S the same. */
127 cpu_type = (int) CPU_H8300H;
128 h8_reg_names = names_extended;
130 h8_push_op = h8_push_ops[cpu_type];
131 h8_pop_op = h8_pop_ops[cpu_type];
132 h8_mov_op = h8_mov_ops[cpu_type];
134 if (!TARGET_H8300S && TARGET_MAC)
136 error ("-ms2600 is used without -ms.");
146 static const char *const names_small[] =
147 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
148 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
150 return names_small[REGNO (x) * 2 + b];
153 /* REGNO must be saved/restored across calls if this macro is true. */
155 #define WORD_REG_USED(regno) \
157 /* No need to save registers if this function will not return. */\
158 && ! TREE_THIS_VOLATILE (current_function_decl) \
160 /* Save any call saved register that was used. */ \
161 || (regs_ever_live[regno] && !call_used_regs[regno]) \
162 /* Save the frame pointer if it was used. */ \
163 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
164 /* Save any register used in an interrupt handler. */ \
165 || (interrupt_handler && regs_ever_live[regno]) \
166 /* Save call clobbered registers in non-leaf interrupt \
168 || (interrupt_handler \
169 && call_used_regs[regno] \
170 && !current_function_is_leaf)))
172 /* Output assembly language to FILE for the operation OP with operand size
173 SIZE to adjust the stack pointer. */
176 dosize (file, op, size)
181 /* On the H8/300H and H8/S, for sizes <= 8 bytes, it is as good or
182 better to use adds/subs insns rather than add.l/sub.l with an
185 Also, on the H8/300, if we don't have a temporary to hold the
186 size of the frame in the prologue, we simply emit a sequence of
187 subs since this shouldn't happen often. */
188 if ((TARGET_H8300 && size <= 4)
189 || ((TARGET_H8300H || TARGET_H8300S) && size <= 8)
190 || (TARGET_H8300 && interrupt_handler)
191 || (TARGET_H8300 && current_function_needs_context
192 && ! strcmp (op, "sub")))
194 unsigned HOST_WIDE_INT amount;
196 /* Try different amounts in descending order. */
197 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
201 for (; size >= amount; size -= amount)
202 fprintf (file, "\t%ss\t#%d,sp\n", op, amount);
208 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
210 fprintf (file, "\t%s.l\t#%d,sp\n", op, size);
214 /* Round up frame size SIZE. */
217 round_frame_size (size)
220 return (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
223 /* Compute which registers to push/pop.
224 Return a bit vector of registers. */
227 compute_saved_regs ()
229 unsigned int saved_regs = 0;
232 /* Construct a bit vector of registers to be pushed/popped. */
233 for (regno = 0; regno <= 6; regno++)
235 if (WORD_REG_USED (regno))
236 saved_regs |= 1 << regno;
239 /* Don't push/pop the frame pointer as it is treated separately. */
240 if (frame_pointer_needed)
241 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
246 /* Output assembly language code to push register RN. */
253 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[rn]);
256 /* Output assembly language code to pop register RN. */
263 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[rn]);
266 /* This is what the stack looks like after the prolog of
267 a function with a frame has been set up:
273 <saved registers> <- sp
275 This is what the stack looks like after the prolog of
276 a function which doesn't have a frame:
281 <saved registers> <- sp
284 /* Output assembly language code for the function prologue. */
287 h8300_output_function_prologue (file, size)
291 int fsize = round_frame_size (size);
296 /* Note a function with the interrupt attribute and set interrupt_handler
298 if (h8300_interrupt_function_p (current_function_decl))
299 interrupt_handler = 1;
301 /* If the current function has the OS_Task attribute set, then
302 we have a naked prologue. */
303 if (h8300_os_task_function_p (current_function_decl))
305 fprintf (file, ";OS_Task prologue\n");
310 if (h8300_monitor_function_p (current_function_decl))
312 /* My understanding of monitor functions is they act just
313 like interrupt functions, except the prologue must
315 fprintf (file, ";monitor prologue\n");
316 interrupt_handler = 1;
320 fprintf (file, "\tsubs\t#2,sp\n");
322 fprintf (file, "\tstc\tccr,r0l\n");
323 fprintf (file, "\tmov.b\tr0l,@(2,sp)\n");
325 fprintf (file, "\torc\t#128,ccr\n");
327 else if (TARGET_H8300H)
330 fprintf (file, "\tstc\tccr,r0l\n");
331 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
333 fprintf (file, "\torc\t#128,ccr\n");
335 else if (TARGET_H8300S)
337 fprintf (file, "\tstc\texr,@-sp\n");
339 fprintf (file, "\tstc\tccr,r0l\n");
340 fprintf (file, "\tmov.b\tr0l,@(6,sp)\n");
342 fprintf (file, "\torc\t#128,ccr\n");
348 if (frame_pointer_needed)
351 push (file, FRAME_POINTER_REGNUM);
352 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
353 h8_reg_names[STACK_POINTER_REGNUM],
354 h8_reg_names[FRAME_POINTER_REGNUM]);
357 /* Leave room for locals. */
358 dosize (file, "sub", fsize);
360 /* Push the rest of the registers in ascending order. */
361 saved_regs = compute_saved_regs ();
362 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
367 if (saved_regs & (1 << regno))
371 /* See how many registers we can push at the same time. */
372 if ((regno == 0 || regno == 4)
373 && ((saved_regs >> regno) & 0x0f) == 0x0f)
376 else if ((regno == 0 || regno == 4)
377 && ((saved_regs >> regno) & 0x07) == 0x07)
380 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
381 && ((saved_regs >> regno) & 0x03) == 0x03)
388 fprintf (file, "\tstm.l\t%s-%s,@-sp\n",
390 h8_reg_names[regno + (n_regs - 1)]);
395 /* Output assembly language code for the function epilogue. */
398 h8300_output_function_epilogue (file, size)
402 int fsize = round_frame_size (size);
404 rtx insn = get_last_insn ();
410 /* OS_Task epilogues are nearly naked -- they just have an
412 fprintf (file, ";OS_task epilogue\n");
413 fprintf (file, "\trts\n");
417 /* Monitor epilogues are the same as interrupt function epilogues.
418 Just make a note that we're in an monitor epilogue. */
420 fprintf (file, ";monitor epilogue\n");
422 /* If the last insn was a BARRIER, we don't have to write any code. */
423 if (GET_CODE (insn) == NOTE)
424 insn = prev_nonnote_insn (insn);
425 if (insn && GET_CODE (insn) == BARRIER)
428 /* Pop the saved registers in descending order. */
429 saved_regs = compute_saved_regs ();
430 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
432 int regno = (FIRST_PSEUDO_REGISTER - 1) - idx;
435 if (saved_regs & (1 << regno))
439 /* See how many registers we can pop at the same time. */
440 if ((regno == 7 || regno == 3)
441 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
444 else if ((regno == 6 || regno == 2)
445 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
448 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
449 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
456 fprintf (file, "\tldm.l\t@sp+,%s-%s\n",
457 h8_reg_names[regno - (n_regs - 1)],
458 h8_reg_names[regno]);
462 /* Deallocate locals. */
463 dosize (file, "add", fsize);
465 /* Pop frame pointer if we had one. */
466 if (frame_pointer_needed)
467 pop (file, FRAME_POINTER_REGNUM);
469 if (interrupt_handler)
470 fprintf (file, "\trte\n");
472 fprintf (file, "\trts\n");
475 interrupt_handler = 0;
481 /* Output assembly code for the start of the file. */
484 asm_file_start (file)
487 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
488 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
490 fprintf (file, "; -O%d\n", optimize);
492 fprintf (file, "\n\t.h8300h\n");
493 else if (TARGET_H8300S)
494 fprintf (file, "\n\t.h8300s\n");
496 fprintf (file, "\n\n");
497 output_file_directive (file, main_input_filename);
500 /* Output assembly language code for the end of file. */
506 fprintf (file, "\t.end\n");
509 /* Return true if VALUE is a valid constant for constraint 'P'.
510 IE: VALUE is a power of two <= 2**15. */
513 small_power_of_two (value)
516 int power = exact_log2 (value);
517 return power >= 0 && power <= 15;
520 /* Return true if VALUE is a valid constant for constraint 'O', which
521 means that the constant would be ok to use as a bit for a bclr
528 return small_power_of_two ((~value) & 0xff);
531 /* Return true if OP is a valid source operand for an integer move
535 general_operand_src (op, mode)
537 enum machine_mode mode;
539 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
541 return general_operand (op, mode);
544 /* Return true if OP is a valid destination operand for an integer move
548 general_operand_dst (op, mode)
550 enum machine_mode mode;
552 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
554 return general_operand (op, mode);
557 /* Return true if OP is a const valid for a bit clear instruction. */
560 o_operand (operand, mode)
562 enum machine_mode mode ATTRIBUTE_UNUSED;
564 return (GET_CODE (operand) == CONST_INT
565 && CONST_OK_FOR_O (INTVAL (operand)));
568 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
571 p_operand (operand, mode)
573 enum machine_mode mode ATTRIBUTE_UNUSED;
575 return (GET_CODE (operand) == CONST_INT
576 && CONST_OK_FOR_P (INTVAL (operand)));
579 /* Return true if OP is a valid call operand. */
582 call_insn_operand (op, mode)
584 enum machine_mode mode ATTRIBUTE_UNUSED;
586 if (GET_CODE (op) == MEM)
588 rtx inside = XEXP (op, 0);
589 if (register_operand (inside, Pmode))
591 if (CONSTANT_ADDRESS_P (inside))
597 /* Return 1 if an addition/subtraction of a constant integer can be
598 transformed into two consecutive adds/subs that are faster than the
599 straightforward way. Otherwise, return 0. */
602 two_insn_adds_subs_operand (op, mode)
604 enum machine_mode mode;
606 if (GET_CODE (op) == CONST_INT)
608 HOST_WIDE_INT value = INTVAL (op);
610 /* Force VALUE to be positive so that we do not have to consider
611 the negative case. */
614 if (TARGET_H8300H || TARGET_H8300S)
616 /* A constant addition/subtraction takes 2 states in QImode,
617 4 states in HImode, and 6 states in SImode. Thus, the
618 only case we can win is when SImode is used, in which
619 case, two adds/subs are used, taking 4 states. */
629 /* A constant addition/subtraction takes 2 states in
630 QImode. It takes 6 states in HImode, requiring the
631 constant to be loaded to a register first, and a lot more
632 in SImode. Thus the only case we can win is when either
633 HImode or SImode is used. */
644 /* Split an add of a small constant into two adds/subs insns. */
647 split_adds_subs (mode, operands)
648 enum machine_mode mode;
651 HOST_WIDE_INT val = INTVAL (operands[1]);
652 rtx reg = operands[0];
653 HOST_WIDE_INT sign = 1;
654 HOST_WIDE_INT amount;
656 /* Force VAL to be positive so that we do not have to consider the
664 /* Try different amounts in descending order. */
665 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
669 for (; val >= amount; val -= amount)
671 rtx tmp = gen_rtx_PLUS (mode, reg, GEN_INT (sign * amount));
672 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
679 /* Return true if OP is a valid call operand, and OP represents
680 an operand for a small call (4 bytes instead of 6 bytes). */
683 small_call_insn_operand (op, mode)
685 enum machine_mode mode ATTRIBUTE_UNUSED;
687 if (GET_CODE (op) == MEM)
689 rtx inside = XEXP (op, 0);
691 /* Register indirect is a small call. */
692 if (register_operand (inside, Pmode))
695 /* A call through the function vector is a small
697 if (GET_CODE (inside) == SYMBOL_REF
698 && SYMBOL_REF_FLAG (inside))
701 /* Otherwise it's a large call. */
705 /* Return true if OP is a valid jump operand. */
708 jump_address_operand (op, mode)
710 enum machine_mode mode;
712 if (GET_CODE (op) == REG)
713 return mode == Pmode;
715 if (GET_CODE (op) == MEM)
717 rtx inside = XEXP (op, 0);
718 if (register_operand (inside, Pmode))
720 if (CONSTANT_ADDRESS_P (inside))
726 /* Recognize valid operands for bitfield instructions. */
728 extern int rtx_equal_function_value_matters;
731 bit_operand (op, mode)
733 enum machine_mode mode;
735 /* We can except any general operand, expept that MEM operands must
736 be limited to those that use addresses valid for the 'U' constraint. */
737 if (!general_operand (op, mode))
740 /* Accept any mem during RTL generation. Otherwise, the code that does
741 insv and extzv will think that we can not handle memory. However,
742 to avoid reload problems, we only accept 'U' MEM operands after RTL
743 generation. This means that any named pattern which uses this predicate
744 must force its operands to match 'U' before emitting RTL. */
746 if (GET_CODE (op) == REG)
748 if (GET_CODE (op) == SUBREG)
750 if (!rtx_equal_function_value_matters)
751 /* We're building rtl. */
752 return GET_CODE (op) == MEM;
754 return (GET_CODE (op) == MEM
755 && EXTRA_CONSTRAINT (op, 'U'));
759 bit_memory_operand (op, mode)
761 enum machine_mode mode ATTRIBUTE_UNUSED;
763 return (GET_CODE (op) == MEM
764 && EXTRA_CONSTRAINT (op, 'U'));
767 /* Recognize valid operators for bit test. */
770 eq_operator (x, mode)
772 enum machine_mode mode ATTRIBUTE_UNUSED;
774 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
777 /* Handle machine specific pragmas for compatibility with existing
778 compilers for the H8/300.
780 pragma saveall generates prolog/epilog code which saves and
781 restores all the registers on function entry.
783 pragma interrupt saves and restores all registers, and exits with
784 an rte instruction rather than an rts. A pointer to a function
785 with this attribute may be safely used in an interrupt vector. */
788 h8300_pr_interrupt (pfile)
789 cpp_reader *pfile ATTRIBUTE_UNUSED;
791 interrupt_handler = 1;
795 h8300_pr_saveall (pfile)
796 cpp_reader *pfile ATTRIBUTE_UNUSED;
801 /* If the next arg with MODE and TYPE is to be passed in a register, return
802 the rtx to represent where it is passed. CUM represents the state after
803 the last argument. NAMED is not used. */
805 static const char *const hand_list[] =
825 /* Return an RTX to represent where a value with mode MODE will be returned
826 from a function. If the result is 0, the argument is pushed. */
829 function_arg (cum, mode, type, named)
830 CUMULATIVE_ARGS *cum;
831 enum machine_mode mode;
839 /* Never pass unnamed arguments in registers. */
843 /* Pass 3 regs worth of data in regs when user asked on the command line. */
844 if (TARGET_QUICKCALL)
847 /* If calling hand written assembler, use 4 regs of args. */
851 const char * const *p;
853 fname = XSTR (cum->libcall, 0);
855 /* See if this libcall is one of the hand coded ones. */
857 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
869 size = int_size_in_bytes (type);
871 size = GET_MODE_SIZE (mode);
873 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
879 switch (cum->nbytes / UNITS_PER_WORD)
882 result = gen_rtx_REG (mode, 0);
885 result = gen_rtx_REG (mode, 1);
888 result = gen_rtx_REG (mode, 2);
891 result = gen_rtx_REG (mode, 3);
902 /* Return the cost of the rtx R with code CODE. */
922 if (TARGET_H8300H || TARGET_H8300S)
943 /* Documentation for the machine specific operand escapes:
945 'A' print rn in H8/300 mode, erN in H8/300H mode
946 'C' print (operand - 2).
947 'E' like s but negative.
948 'F' like t but negative.
949 'G' constant just the negative
950 'M' turn a 'M' constant into its negative mod 2.
951 'P' if operand is incing/decing sp, print .w, otherwise .b.
952 'R' print operand as a byte:8 address if appropriate, else fall back to
954 'S' print operand as a long word
955 'T' print operand as a word
956 'U' if operand is incing/decing sp, print l, otherwise nothing.
957 'V' find the set bit, and print its number.
958 'W' find the clear bit, and print its number.
959 'X' print operand as a byte
960 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
961 If this operand isn't a register, fall back to 'R' handling.
963 'b' print the bit opcode
964 'c' print the ibit opcode
965 'd' bcc if EQ, bcs if NE
966 'e' first word of 32 bit value - if reg, then least reg. if mem
967 then least. if const then most sig word
968 'f' second word of 32 bit value - if reg, then biggest reg. if mem
969 then +2. if const then least sig word
970 'g' bcs if EQ, bcc if NE
971 'j' print operand as condition code.
972 'k' print operand as reverse condition code.
973 's' print as low byte of 16 bit value
974 't' print as high byte of 16 bit value
975 'w' print as low byte of 32 bit value
976 'x' print as 2nd byte of 32 bit value
977 'y' print as 3rd byte of 32 bit value
978 'z' print as msb of 32 bit value
981 /* Return assembly language string which identifies a comparison type. */
1014 /* Print operand X using operand code CODE to assembly language output file
1018 print_operand (file, x, code)
1023 /* This is used for communication between the 'P' and 'U' codes. */
1024 static const char *last_p;
1026 /* This is used for communication between codes V,W,Z and Y. */
1032 if (GET_CODE (x) == REG)
1033 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1038 fprintf (file, "#%d", INTVAL (x) - 2);
1041 switch (GET_CODE (x))
1044 fprintf (file, "%sl", names_big[REGNO (x)]);
1047 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1054 switch (GET_CODE (x))
1057 fprintf (file, "%sh", names_big[REGNO (x)]);
1060 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1067 if (GET_CODE (x) != CONST_INT)
1069 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1072 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1079 fprintf (file, "#2");
1085 fprintf (file, "#1");
1092 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1095 fprintf (file, ".w");
1100 fprintf (file, ".b");
1104 if (GET_CODE (x) == REG)
1105 fprintf (file, "%s", names_extended[REGNO (x)]);
1110 if (GET_CODE (x) == REG)
1111 fprintf (file, "%s", names_big[REGNO (x)]);
1116 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1119 bitint = exact_log2 (INTVAL (x));
1122 fprintf (file, "#%d", bitint & 7);
1125 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1128 fprintf (file, "#%d", bitint & 7);
1132 if (GET_CODE (x) == REG)
1133 fprintf (file, "%s", byte_reg (x, 0));
1140 if (GET_CODE (x) == REG)
1141 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1143 print_operand (file, x, 'R');
1147 bitint = INTVAL (x);
1148 fprintf (file, "#%d", bitint & 7);
1151 switch (GET_CODE (x))
1154 fprintf (file, "bor");
1157 fprintf (file, "bxor");
1160 fprintf (file, "band");
1167 switch (GET_CODE (x))
1170 fprintf (file, "bior");
1173 fprintf (file, "bixor");
1176 fprintf (file, "biand");
1183 switch (GET_CODE (x))
1186 fprintf (file, "bcc");
1189 fprintf (file, "bcs");
1196 switch (GET_CODE (x))
1200 fprintf (file, "%s", names_big[REGNO (x)]);
1202 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1205 print_operand (file, x, 0);
1208 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1214 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1215 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1216 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1225 switch (GET_CODE (x))
1229 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1231 fprintf (file, "%s", names_big[REGNO (x)]);
1234 x = adjust_address (x, HImode, 2);
1235 print_operand (file, x, 0);
1238 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1244 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1245 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1246 fprintf (file, "#%ld", (val & 0xffff));
1254 switch (GET_CODE (x))
1257 fprintf (file, "bcc");
1260 fprintf (file, "bcs");
1267 asm_fprintf (file, cond_string (GET_CODE (x)));
1270 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1273 if (GET_CODE (x) == CONST_INT)
1274 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1276 fprintf (file, "%s", byte_reg (x, 0));
1279 if (GET_CODE (x) == CONST_INT)
1280 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1282 fprintf (file, "%s", byte_reg (x, 1));
1285 if (GET_CODE (x) != CONST_INT)
1287 fprintf (file, "%d", INTVAL (x));
1290 if (GET_CODE (x) == CONST_INT)
1291 fprintf (file, "#%d", INTVAL (x) & 0xff);
1293 fprintf (file, "%s",
1294 byte_reg (x, TARGET_H8300 ? 2 : 0));
1297 if (GET_CODE (x) == CONST_INT)
1298 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1300 fprintf (file, "%s",
1301 byte_reg (x, TARGET_H8300 ? 3 : 1));
1304 if (GET_CODE (x) == CONST_INT)
1305 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1307 fprintf (file, "%s", byte_reg (x, 0));
1310 if (GET_CODE (x) == CONST_INT)
1311 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1313 fprintf (file, "%s", byte_reg (x, 1));
1318 switch (GET_CODE (x))
1321 switch (GET_MODE (x))
1324 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1325 fprintf (file, "%s", byte_reg (x, 0));
1326 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1327 fprintf (file, "%s", names_big[REGNO (x)]);
1331 fprintf (file, "%s", names_big[REGNO (x)]);
1335 fprintf (file, "%s", names_extended[REGNO (x)]);
1343 fprintf (file, "@");
1344 output_address (XEXP (x, 0));
1346 /* If this is an 'R' operand (reference into the 8-bit
1347 area), then specify a symbolic address as "foo:8",
1348 otherwise if operand is still in eight bit section, use
1350 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1351 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1352 fprintf (file, (code == 'R' ? ":8" : ":16"));
1353 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1354 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1355 fprintf (file, ":16");
1356 else if ((code == 'R')
1357 && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0)))
1358 fprintf (file, ":8");
1365 fprintf (file, "#");
1366 print_operand_address (file, x);
1372 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1373 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1374 fprintf (file, "#%ld", val);
1383 /* Output assembly language output for the address ADDR to FILE. */
1386 print_operand_address (file, addr)
1390 switch (GET_CODE (addr))
1393 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1397 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1401 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1405 fprintf (file, "(");
1406 if (GET_CODE (XEXP (addr, 0)) == REG)
1409 print_operand_address (file, XEXP (addr, 1));
1410 fprintf (file, ",");
1411 print_operand_address (file, XEXP (addr, 0));
1416 print_operand_address (file, XEXP (addr, 0));
1417 fprintf (file, "+");
1418 print_operand_address (file, XEXP (addr, 1));
1420 fprintf (file, ")");
1425 /* Since the H8/300 only has 16 bit pointers, negative values are also
1426 those >= 32768. This happens for example with pointer minus a
1427 constant. We don't want to turn (char *p - 2) into
1428 (char *p + 65534) because loop unrolling can build upon this
1429 (IE: char *p + 131068). */
1430 int n = INTVAL (addr);
1432 n = (int) (short) n;
1434 /* ??? Why the special case for -ve values? */
1435 fprintf (file, "-%d", -n);
1437 fprintf (file, "%d", n);
1442 output_addr_const (file, addr);
1447 /* Output all insn addresses and their sizes into the assembly language
1448 output file. This is helpful for debugging whether the length attributes
1449 in the md file are correct. This is not meant to be a user selectable
1453 final_prescan_insn (insn, operand, num_operands)
1454 rtx insn, *operand ATTRIBUTE_UNUSED;
1455 int num_operands ATTRIBUTE_UNUSED;
1457 /* This holds the last insn address. */
1458 static int last_insn_address = 0;
1460 int uid = INSN_UID (insn);
1462 if (TARGET_RTL_DUMP)
1464 fprintf (asm_out_file, "\n****************");
1465 print_rtl (asm_out_file, PATTERN (insn));
1466 fprintf (asm_out_file, "\n");
1469 if (TARGET_ADDRESSES)
1471 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1472 INSN_ADDRESSES (uid) - last_insn_address);
1473 last_insn_address = INSN_ADDRESSES (uid);
1477 /* Prepare for an SI sized move. */
1483 rtx src = operands[1];
1484 rtx dst = operands[0];
1485 if (!reload_in_progress && !reload_completed)
1487 if (!register_operand (dst, GET_MODE (dst)))
1489 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1490 emit_move_insn (tmp, src);
1497 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1498 Define the offset between two registers, one to be eliminated, and
1499 the other its replacement, at the start of a routine. */
1502 initial_offset (from, to)
1507 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1508 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1509 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1510 offset = frame_pointer_needed * UNITS_PER_WORD;
1515 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1516 if (WORD_REG_USED (regno))
1517 offset += UNITS_PER_WORD;
1519 /* See the comments for get_frame_size. We need to round it up to
1522 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1523 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1525 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1526 offset += UNITS_PER_WORD; /* Skip saved PC */
1532 h8300_return_addr_rtx (count, frame)
1539 ret = gen_rtx_MEM (Pmode,
1540 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1541 else if (flag_omit_frame_pointer)
1544 ret = gen_rtx_MEM (Pmode,
1545 memory_address (Pmode,
1546 plus_constant (frame, UNITS_PER_WORD)));
1547 set_mem_alias_set (ret, get_frame_alias_set ());
1551 /* Update the condition code from the insn. */
1554 notice_update_cc (body, insn)
1558 switch (get_attr_cc (insn))
1561 /* Insn does not affect CC at all. */
1565 /* Insn does not change CC, but the 0'th operand has been changed. */
1566 if (cc_status.value1 != 0
1567 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1568 cc_status.value1 = 0;
1572 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1573 The V flag is unusable. The C flag may or may not be known but
1574 that's ok because alter_cond will change tests to use EQ/NE. */
1576 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1577 cc_status.value1 = recog_data.operand[0];
1581 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1582 The C flag may or may not be known but that's ok because
1583 alter_cond will change tests to use EQ/NE. */
1585 cc_status.flags |= CC_NO_CARRY;
1586 cc_status.value1 = recog_data.operand[0];
1590 /* The insn is a compare instruction. */
1592 cc_status.value1 = SET_SRC (body);
1596 /* Insn doesn't leave CC in a usable state. */
1602 /* Recognize valid operators for bit instructions. */
1605 bit_operator (x, mode)
1607 enum machine_mode mode ATTRIBUTE_UNUSED;
1609 enum rtx_code code = GET_CODE (x);
1617 output_logical_op (mode, code, operands)
1618 enum machine_mode mode;
1622 /* Pretend that every byte is affected if both operands are registers. */
1623 unsigned HOST_WIDE_INT intval =
1624 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
1625 ? INTVAL (operands[2]) : 0x55555555);
1626 /* The determinant of the algorithm. If we perform an AND, 0
1627 affects a bit. Otherwise, 1 affects a bit. */
1628 unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
1629 /* The name of an insn. */
1651 /* First, see if we can finish with one insn. */
1652 if ((TARGET_H8300H || TARGET_H8300S)
1653 && ((det & 0x00ff) != 0)
1654 && ((det & 0xff00) != 0))
1656 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
1657 output_asm_insn (insn_buf, operands);
1661 /* Take care of the lower byte. */
1662 if ((det & 0x00ff) != 0)
1664 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
1665 output_asm_insn (insn_buf, operands);
1667 /* Take care of the upper byte. */
1668 if ((det & 0xff00) != 0)
1670 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
1671 output_asm_insn (insn_buf, operands);
1676 /* First, see if we can finish with one insn.
1678 If code is either AND or XOR, we exclude two special cases,
1679 0xffffff00 and 0xffff00ff, because insns like sub.w or neg.w
1680 can do a better job. */
1681 if ((TARGET_H8300H || TARGET_H8300S)
1682 && ((det & 0x0000ffff) != 0)
1683 && ((det & 0xffff0000) != 0)
1684 && (code == IOR || det != 0xffffff00)
1685 && (code == IOR || det != 0xffff00ff))
1687 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
1688 output_asm_insn (insn_buf, operands);
1692 /* Take care of the lower and upper words individually. For
1693 each word, we try different methods in the order of
1695 1) the special insn (in case of AND or XOR),
1696 2) the word-wise insn, and
1697 3) The byte-wise insn. */
1698 if ((TARGET_H8300H || TARGET_H8300S)
1699 && ((det & 0x0000ffff) == 0x0000ffff)
1701 output_asm_insn ((code == AND)
1702 ? "sub.w\t%f0,%f0" : "neg.w\t%f0",
1704 else if ((TARGET_H8300H || TARGET_H8300S)
1705 && ((det & 0x000000ff) != 0)
1706 && ((det & 0x0000ff00) != 0))
1708 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
1709 output_asm_insn (insn_buf, operands);
1713 if ((det & 0x000000ff) != 0)
1715 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
1716 output_asm_insn (insn_buf, operands);
1718 if ((det & 0x0000ff00) != 0)
1720 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
1721 output_asm_insn (insn_buf, operands);
1725 if ((TARGET_H8300H || TARGET_H8300S)
1726 && ((det & 0xffff0000) == 0xffff0000)
1728 output_asm_insn ((code == AND)
1729 ? "sub.w\t%e0,%e0" : "neg.w\t%e0",
1731 else if (TARGET_H8300H || TARGET_H8300S)
1733 if ((det & 0xffff0000) != 0)
1735 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
1736 output_asm_insn (insn_buf, operands);
1741 if ((det & 0x00ff0000) != 0)
1743 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
1744 output_asm_insn (insn_buf, operands);
1746 if ((det & 0xff000000) != 0)
1748 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
1749 output_asm_insn (insn_buf, operands);
1762 We devote a fair bit of code to getting efficient shifts since we can only
1763 shift one bit at a time on the H8/300 and H8/300H and only one or two
1764 bits at a time on the H8/S.
1766 The basic shift methods:
1768 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1769 this is the default. SHIFT_LOOP
1771 * inlined shifts -- emit straight line code for the shift; this is
1772 used when a straight line shift is about the same size or smaller
1773 than a loop. We allow the inline version to be slightly longer in
1774 some cases as it saves a register. SHIFT_INLINE
1776 * rotate + and -- rotate the value the opposite direction, then
1777 mask off the values we don't need. This is used when only a few
1778 of the bits in the original value will survive in the shifted value.
1779 Again, this is used when it's about the same size or smaller than
1780 a loop. We allow this version to be slightly longer as it is usually
1781 much faster than a loop. SHIFT_ROT_AND
1783 * swap (+ shifts) -- often it's possible to swap bytes/words to
1784 simulate a shift by 8/16. Once swapped a few inline shifts can be
1785 added if the shift count is slightly more than 8 or 16. This is used
1786 when it's about the same size or smaller than a loop. We allow this
1787 version to be slightly longer as it is usually much faster than a loop.
1790 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1792 Here are some thoughts on what the absolutely positively best code is.
1793 "Best" here means some rational trade-off between code size and speed,
1794 where speed is more preferred but not at the expense of generating 20 insns.
1796 A trailing '*' after the shift count indicates the "best" mode isn't
1799 H8/300 QImode shifts
1800 1-4 - do them inline
1801 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1803 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1804 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1806 H8/300 HImode shifts
1807 1-4 - do them inline
1809 7 - shift 2nd half other way into carry.
1810 copy 1st half into 2nd half
1811 rotate 2nd half other way with carry
1812 rotate 1st half other way (no carry)
1813 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1814 sign extend 1st half (ASHIFTRT)
1815 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1816 9-12 - do shift by 8, inline remaining shifts
1817 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1819 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1820 - ASHIFTRT: shll, subx, set other byte
1822 H8/300 SImode shifts
1823 1-2 - do them inline
1825 7* - shift other way once, move bytes into place,
1826 move carry into place (possibly with sign extension)
1827 8 - move bytes into place, zero or sign extend other
1829 15* - shift other way once, move word into place, move carry into place
1830 16 - move word, zero or sign extend other
1832 24* - move bytes into place, zero or sign extend other
1834 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1837 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1839 ASHIFTRT: shll top byte, subx, copy to other bytes
1841 H8/300H QImode shifts (same as H8/300 QImode shifts)
1842 1-4 - do them inline
1843 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1845 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1846 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1848 H8/300H HImode shifts
1849 1-4 - do them inline
1851 7 - shift 2nd half other way into carry.
1852 copy 1st half into 2nd half
1853 rotate entire word other way using carry
1854 mask off remaining bits (ASHIFT | LSHIFTRT)
1855 sign extend remaining bits (ASHIFTRT)
1856 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1857 9-12 - do shift by 8, inline remaining shifts
1858 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1860 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1861 - ASHIFTRT: shll, subx, set other byte
1863 H8/300H SImode shifts
1864 (These are complicated by the fact that we don't have byte level access to
1866 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1867 1-4 - do them inline
1869 15* - shift other way once, move word into place, move carry into place
1870 (with sign extension for ASHIFTRT)
1871 16 - move word into place, zero or sign extend other
1872 17-20 - do 16bit shift, then inline remaining shifts
1874 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1875 move word 0 to word 1, zero word 0
1876 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1877 zero word 1, zero byte 1
1878 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1879 sign extend byte 0, sign extend word 0
1880 25-27* - either loop, or
1881 do 24 bit shift, inline rest
1882 28-30 - ASHIFT: rotate 4/3/2, mask
1883 LSHIFTRT: rotate 4/3/2, mask
1885 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1888 1-6 - do them inline
1889 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1890 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1893 1-7 - do them inline
1894 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1895 9-12 - do shift by 8, inline remaining shifts
1896 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1898 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1899 - ASHIFTRT: shll, subx, set other byte
1902 (These are complicated by the fact that we don't have byte level access to
1904 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1905 1-10 - do them inline
1907 15* - shift other way once, move word into place, move carry into place
1908 (with sign extension for ASHIFTRT)
1909 16 - move word into place, zero or sign extend other
1910 17-20 - do 16bit shift, then inline remaining shifts
1912 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1913 move word 0 to word 1, zero word 0
1914 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1915 zero word 1, zero byte 1
1916 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1917 sign extend byte 0, sign extend word 0
1918 25-27* - either loop, or
1919 do 24 bit shift, inline rest
1920 28-30 - ASHIFT: rotate 4/3/2, mask
1921 LSHIFTRT: rotate 4/3/2, mask
1923 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1928 nshift_operator (x, mode)
1930 enum machine_mode mode ATTRIBUTE_UNUSED;
1932 switch (GET_CODE (x))
1944 /* Called from the .md file to emit code to do shifts.
1945 Return a boolean indicating success.
1946 (Currently this is always TRUE). */
1949 expand_a_shift (mode, code, operands)
1950 enum machine_mode mode;
1954 emit_move_insn (operands[0], operands[1]);
1956 /* Need a loop to get all the bits we want - we generate the
1957 code at emit time, but need to allocate a scratch reg now. */
1959 emit_insn (gen_rtx_PARALLEL
1962 gen_rtx_SET (VOIDmode, operands[0],
1963 gen_rtx (code, mode, operands[0],
1965 gen_rtx_CLOBBER (VOIDmode,
1966 gen_rtx_SCRATCH (QImode)))));
1971 /* Shift algorithm determination.
1973 There are various ways of doing a shift:
1974 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1976 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1977 necessary bits into position and then set the rest to zero.
1978 SHIFT_SPECIAL: Hand crafted assembler.
1979 SHIFT_LOOP: If the above methods fail, just loop. */
1989 /* Symbols of the various shifts which can be used as indices. */
1993 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1996 /* Symbols of the various modes which can be used as indices. */
2000 QIshift, HIshift, SIshift
2003 /* For single bit shift insns, record assembler and what bits of the
2004 condition code are valid afterwards (represented as various CC_FOO
2005 bits, 0 means CC isn't left in a usable state). */
2009 const char *const assembler;
2013 /* Assembler instruction shift table.
2015 These tables are used to look up the basic shifts.
2016 They are indexed by cpu, shift_type, and mode. */
2018 static const struct shift_insn shift_one[2][3][3] =
2024 { "shll\t%X0", CC_NO_CARRY },
2025 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2026 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
2028 /* SHIFT_LSHIFTRT */
2030 { "shlr\t%X0", CC_NO_CARRY },
2031 { "shlr\t%t0\n\trotxr\t%s0", 0 },
2032 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2034 /* SHIFT_ASHIFTRT */
2036 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2037 { "shar\t%t0\n\trotxr\t%s0", 0 },
2038 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2045 { "shll.b\t%X0", CC_NO_CARRY },
2046 { "shll.w\t%T0", CC_NO_CARRY },
2047 { "shll.l\t%S0", CC_NO_CARRY }
2049 /* SHIFT_LSHIFTRT */
2051 { "shlr.b\t%X0", CC_NO_CARRY },
2052 { "shlr.w\t%T0", CC_NO_CARRY },
2053 { "shlr.l\t%S0", CC_NO_CARRY }
2055 /* SHIFT_ASHIFTRT */
2057 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2058 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2059 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2064 static const struct shift_insn shift_two[3][3] =
2068 { "shll.b\t#2,%X0", CC_NO_CARRY },
2069 { "shll.w\t#2,%T0", CC_NO_CARRY },
2070 { "shll.l\t#2,%S0", CC_NO_CARRY }
2072 /* SHIFT_LSHIFTRT */
2074 { "shlr.b\t#2,%X0", CC_NO_CARRY },
2075 { "shlr.w\t#2,%T0", CC_NO_CARRY },
2076 { "shlr.l\t#2,%S0", CC_NO_CARRY }
2078 /* SHIFT_ASHIFTRT */
2080 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2081 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2082 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2086 /* Rotates are organized by which shift they'll be used in implementing.
2087 There's no need to record whether the cc is valid afterwards because
2088 it is the AND insn that will decide this. */
2090 static const char *const rotate_one[2][3][3] =
2097 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2100 /* SHIFT_LSHIFTRT */
2103 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2106 /* SHIFT_ASHIFTRT */
2109 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2121 /* SHIFT_LSHIFTRT */
2127 /* SHIFT_ASHIFTRT */
2136 static const char *const rotate_two[3][3] =
2144 /* SHIFT_LSHIFTRT */
2150 /* SHIFT_ASHIFTRT */
2158 /* Macros to keep the shift algorithm tables small. */
2159 #define INL SHIFT_INLINE
2160 #define ROT SHIFT_ROT_AND
2161 #define LOP SHIFT_LOOP
2162 #define SPC SHIFT_SPECIAL
2164 /* The shift algorithms for each machine, mode, shift type, and shift
2165 count are defined below. The three tables below correspond to
2166 QImode, HImode, and SImode, respectively. Each table is organized
2167 by, in the order of indecies, machine, shift type, and shift count. */
2169 static const enum shift_alg shift_alg_qi[3][3][8] = {
2172 /* 0 1 2 3 4 5 6 7 */
2173 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
2174 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
2175 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
2179 /* 0 1 2 3 4 5 6 7 */
2180 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
2181 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
2182 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
2186 /* 0 1 2 3 4 5 6 7 */
2187 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
2188 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
2189 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
2193 static const enum shift_alg shift_alg_hi[3][3][16] = {
2196 /* 0 1 2 3 4 5 6 7 */
2197 /* 8 9 10 11 12 13 14 15 */
2198 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2199 SPC, SPC, SPC, SPC, SPC, LOP, LOP, ROT }, /* SHIFT_ASHIFT */
2200 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2201 SPC, SPC, SPC, SPC, SPC, LOP, LOP, ROT }, /* SHIFT_LSHIFTRT */
2202 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2203 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2207 /* 0 1 2 3 4 5 6 7 */
2208 /* 8 9 10 11 12 13 14 15 */
2209 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2210 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
2211 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2212 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
2213 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2214 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2218 /* 0 1 2 3 4 5 6 7 */
2219 /* 8 9 10 11 12 13 14 15 */
2220 { INL, INL, INL, INL, INL, INL, INL, INL,
2221 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
2222 { INL, INL, INL, INL, INL, INL, INL, INL,
2223 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
2224 { INL, INL, INL, INL, INL, INL, INL, INL,
2225 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2229 static const enum shift_alg shift_alg_si[3][3][32] = {
2232 /* 0 1 2 3 4 5 6 7 */
2233 /* 8 9 10 11 12 13 14 15 */
2234 /* 16 17 18 19 20 21 22 23 */
2235 /* 24 25 26 27 28 29 30 31 */
2236 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
2237 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2238 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2239 LOP, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
2240 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
2241 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2242 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2243 LOP, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
2244 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
2245 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2246 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2247 LOP, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2251 /* 0 1 2 3 4 5 6 7 */
2252 /* 8 9 10 11 12 13 14 15 */
2253 /* 16 17 18 19 20 21 22 23 */
2254 /* 24 25 26 27 28 29 30 31 */
2255 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
2256 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
2257 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
2258 SPC, LOP, LOP, LOP, ROT, ROT, ROT, SPC }, /* SHIFT_ASHIFT */
2259 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
2260 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
2261 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
2262 SPC, LOP, LOP, LOP, ROT, ROT, ROT, SPC }, /* SHIFT_LSHIFTRT */
2263 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
2264 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2265 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
2266 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2270 /* 0 1 2 3 4 5 6 7 */
2271 /* 8 9 10 11 12 13 14 15 */
2272 /* 16 17 18 19 20 21 22 23 */
2273 /* 24 25 26 27 28 29 30 31 */
2274 { INL, INL, INL, INL, INL, INL, INL, INL,
2275 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
2276 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
2277 SPC, SPC, LOP, LOP, ROT, ROT, ROT, SPC }, /* SHIFT_ASHIFT */
2278 { INL, INL, INL, INL, INL, INL, INL, INL,
2279 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
2280 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
2281 SPC, SPC, LOP, LOP, ROT, ROT, ROT, SPC }, /* SHIFT_LSHIFTRT */
2282 { INL, INL, INL, INL, INL, INL, INL, INL,
2283 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
2284 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
2285 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2295 /* Shift algorithm. */
2298 /* The number of bits to be shifted by shift1 and shift2. Valid
2299 when ALG is SHIFT_SPECIAL. */
2300 unsigned int remainder;
2302 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2303 const char *special;
2305 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2306 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2309 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2310 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2313 /* Valid CC flags. */
2317 static void get_shift_alg PARAMS ((enum shift_type,
2318 enum shift_mode, unsigned int,
2319 struct shift_info *));
2321 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2322 best algorithm for doing the shift. The assembler code is stored
2323 in the pointers in INFO. We don't achieve maximum efficiency in
2324 all cases, but the hooks are here to do so.
2326 For now we just use lots of switch statements. Since we don't even come
2327 close to supporting all the cases, this is simplest. If this function ever
2328 gets too big, perhaps resort to a more table based lookup. Of course,
2329 at this point you may just wish to do it all in rtl.
2331 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2332 1,2,3,4 will be inlined (1,2 for SI). */
2335 get_shift_alg (shift_type, shift_mode, count, info)
2336 enum shift_type shift_type;
2337 enum shift_mode shift_mode;
2339 struct shift_info *info;
2343 /* Find the target CPU. */
2346 else if (TARGET_H8300H)
2351 /* Find the shift algorithm. */
2355 if (GET_MODE_BITSIZE (QImode) <= count)
2356 info->alg = SHIFT_LOOP;
2358 info->alg = shift_alg_qi[cpu][shift_type][count];
2362 if (GET_MODE_BITSIZE (HImode) <= count)
2363 info->alg = SHIFT_LOOP;
2365 info->alg = shift_alg_hi[cpu][shift_type][count];
2369 if (GET_MODE_BITSIZE (SImode) <= count)
2370 info->alg = SHIFT_LOOP;
2372 info->alg = shift_alg_si[cpu][shift_type][count];
2379 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2383 info->remainder = count;
2387 /* It is up to the caller to know that looping clobbers cc. */
2388 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2389 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2390 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2394 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2395 info->shift2 = rotate_two[shift_type][shift_mode];
2396 info->cc_valid_p = 0;
2400 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2401 info->remainder = 0;
2402 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2403 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2404 info->cc_valid_p = 0;
2408 /* Here we only deal with SHIFT_SPECIAL. */
2412 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2413 through the entire value. */
2414 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2416 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2428 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2430 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2432 case SHIFT_LSHIFTRT:
2434 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2436 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2438 case SHIFT_ASHIFTRT:
2439 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2443 else if (8 <= count && count <= 12)
2445 info->remainder = count - 8;
2450 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2451 info->shift1 = "shal.b\t%t0";
2452 info->shift2 = "shal.b\t#2,%t0";
2454 case SHIFT_LSHIFTRT:
2455 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2456 info->shift1 = "shlr.b\t%s0";
2457 info->shift2 = "shlr.b\t#2,%s0";
2459 case SHIFT_ASHIFTRT:
2461 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2463 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2464 info->shift1 = "shar.b\t%s0";
2465 info->shift2 = "shar.b\t#2,%s0";
2469 else if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2471 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2477 if (count == 8 && TARGET_H8300)
2482 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2484 case SHIFT_LSHIFTRT:
2485 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2487 case SHIFT_ASHIFTRT:
2488 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2492 else if (count == 8 && !TARGET_H8300)
2497 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2499 case SHIFT_LSHIFTRT:
2500 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2502 case SHIFT_ASHIFTRT:
2503 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2507 else if (count == 15 && !TARGET_H8300)
2512 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
2514 case SHIFT_LSHIFTRT:
2515 info->special = "shll.w\t%e0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
2519 else if ((TARGET_H8300 && count == 16)
2520 || (TARGET_H8300H && 16 <= count && count <= 19)
2521 || (TARGET_H8300S && 16 <= count && count <= 21))
2523 info->remainder = count - 16;
2528 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2529 info->shift1 = "shll.l\t%S0";
2530 info->shift2 = "shll.l\t#2,%S0";
2532 case SHIFT_LSHIFTRT:
2533 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2534 info->shift1 = "shlr.l\t%S0";
2535 info->shift2 = "shlr.l\t#2,%S0";
2537 case SHIFT_ASHIFTRT:
2539 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2541 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2542 info->shift1 = "shar.l\t%S0";
2543 info->shift2 = "shar.l\t#2,%S0";
2547 else if ((TARGET_H8300H && count == 24)
2548 || (TARGET_H8300S && 24 <= count && count <= 25))
2550 info->remainder = count - 24;
2555 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2556 info->shift1 = "shll.l\t%S0";
2557 info->shift2 = "shll.l\t#2,%S0";
2559 case SHIFT_LSHIFTRT:
2560 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2561 info->shift1 = "shlr.l\t%S0";
2562 info->shift2 = "shlr.l\t#2,%S0";
2564 case SHIFT_ASHIFTRT:
2565 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2566 info->shift1 = "shar.l\t%S0";
2567 info->shift2 = "shar.l\t#2,%S0";
2571 else if (count == 31)
2578 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2580 case SHIFT_LSHIFTRT:
2581 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2583 case SHIFT_ASHIFTRT:
2584 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2593 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
2595 case SHIFT_LSHIFTRT:
2596 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
2598 case SHIFT_ASHIFTRT:
2599 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2612 info->shift2 = NULL;
2615 /* Emit the assembler code for doing shifts. */
2618 emit_a_shift (insn, operands)
2619 rtx insn ATTRIBUTE_UNUSED;
2622 static int loopend_lab;
2623 rtx shift = operands[3];
2624 enum machine_mode mode = GET_MODE (shift);
2625 enum rtx_code code = GET_CODE (shift);
2626 enum shift_type shift_type;
2627 enum shift_mode shift_mode;
2628 struct shift_info info;
2635 shift_mode = QIshift;
2638 shift_mode = HIshift;
2641 shift_mode = SIshift;
2650 shift_type = SHIFT_ASHIFTRT;
2653 shift_type = SHIFT_LSHIFTRT;
2656 shift_type = SHIFT_ASHIFT;
2662 if (GET_CODE (operands[2]) != CONST_INT)
2664 /* Indexing by reg, so have to loop and test at top. */
2665 output_asm_insn ("mov.b %X2,%X4", operands);
2666 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2668 /* Get the assembler code to do one shift. */
2669 get_shift_alg (shift_type, shift_mode, 1, &info);
2671 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2672 output_asm_insn (info.shift1, operands);
2673 output_asm_insn ("add #0xff,%X4", operands);
2674 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2675 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2681 int n = INTVAL (operands[2]);
2683 /* If the count is negative, make it 0. */
2686 /* If the count is too big, truncate it.
2687 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2688 do the intuitive thing. */
2689 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
2690 n = GET_MODE_BITSIZE (mode);
2692 get_shift_alg (shift_type, shift_mode, n, &info);
2697 output_asm_insn (info.special, operands);
2703 /* Emit two bit shifts first. */
2704 while (n > 1 && info.shift2 != NULL)
2706 output_asm_insn (info.shift2, operands);
2710 /* Now emit one bit shifts for any residual. */
2713 output_asm_insn (info.shift1, operands);
2717 /* Keep track of CC. */
2718 if (info.cc_valid_p)
2720 cc_status.value1 = operands[0];
2721 cc_status.flags |= info.cc_valid_p;
2727 int m = GET_MODE_BITSIZE (mode) - n;
2728 int mask = (shift_type == SHIFT_ASHIFT
2729 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2730 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2733 /* Not all possibilities of rotate are supported. They shouldn't
2734 be generated, but let's watch for 'em. */
2735 if (info.shift1 == 0)
2738 /* Emit two bit rotates first. */
2739 while (m > 1 && info.shift2 != NULL)
2741 output_asm_insn (info.shift2, operands);
2745 /* Now single bit rotates for any residual. */
2748 output_asm_insn (info.shift1, operands);
2752 /* Now mask off the high bits. */
2758 sprintf (insn_buf, "and\t#%d,%%X0", mask);
2759 cc_status.value1 = operands[0];
2760 cc_status.flags |= CC_NO_CARRY;
2763 sprintf (insn_buf, "and\t#%d,%%s0\n\tand\t#%d,%%t0",
2764 mask & 255, mask >> 8);
2774 sprintf (insn_buf, "and.%c\t#%d,%%%c0",
2775 "bwl"[shift_mode], mask,
2776 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2777 cc_status.value1 = operands[0];
2778 cc_status.flags |= CC_NO_CARRY;
2780 output_asm_insn (insn_buf, operands);
2785 /* A loop to shift by a "large" constant value.
2786 If we have shift-by-2 insns, use them. */
2787 if (info.shift2 != NULL)
2789 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2790 names_big[REGNO (operands[4])]);
2791 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2792 output_asm_insn (info.shift2, operands);
2793 output_asm_insn ("add #0xff,%X4", operands);
2794 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2796 output_asm_insn (info.shift1, operands);
2800 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2801 names_big[REGNO (operands[4])]);
2802 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2803 output_asm_insn (info.shift1, operands);
2804 output_asm_insn ("add #0xff,%X4", operands);
2805 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2815 /* A rotation by a non-constant will cause a loop to be generated, in
2816 which a rotation by one bit is used. A rotation by a constant,
2817 including the one in the loop, will be taken care of by
2818 emit_a_rotate () at the insn emit time. */
2821 expand_a_rotate (code, operands)
2825 rtx dst = operands[0];
2826 rtx src = operands[1];
2827 rtx rotate_amount = operands[2];
2828 enum machine_mode mode = GET_MODE (dst);
2831 /* We rotate in place. */
2832 emit_move_insn (dst, src);
2834 if (GET_CODE (rotate_amount) != CONST_INT)
2836 rtx counter = gen_reg_rtx (QImode);
2837 rtx start_label = gen_label_rtx ();
2838 rtx end_label = gen_label_rtx ();
2840 /* If the rotate amount is less than or equal to 0,
2841 we go out of the loop. */
2842 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0),
2843 LE, NULL_RTX, QImode, 0, 0, end_label);
2845 /* Initialize the loop counter. */
2846 emit_move_insn (counter, rotate_amount);
2848 emit_label (start_label);
2850 /* Rotate by one bit. */
2851 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
2852 emit_insn (gen_rtx_SET (mode, dst, tmp));
2854 /* Decrement the counter by 1. */
2855 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
2856 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
2858 /* If the loop counter is non-zero, we go back to the beginning
2860 emit_cmp_and_jump_insns (counter, GEN_INT (0),
2861 NE, NULL_RTX, QImode, 1, 0, start_label);
2863 emit_label (end_label);
2867 /* Rotate by AMOUNT bits. */
2868 tmp = gen_rtx (code, mode, dst, rotate_amount);
2869 emit_insn (gen_rtx_SET (mode, dst, tmp));
2875 /* Emit rotate insns. */
2878 emit_a_rotate (code, operands)
2882 rtx dst = operands[0];
2883 rtx rotate_amount = operands[2];
2884 enum shift_mode rotate_mode;
2885 enum shift_type rotate_type;
2886 const char *insn_buf;
2889 enum machine_mode mode = GET_MODE (dst);
2891 if (GET_CODE (rotate_amount) != CONST_INT)
2897 rotate_mode = QIshift;
2900 rotate_mode = HIshift;
2903 rotate_mode = SIshift;
2912 rotate_type = SHIFT_ASHIFT;
2915 rotate_type = SHIFT_LSHIFTRT;
2921 amount = INTVAL (rotate_amount);
2923 /* Clean up AMOUNT. */
2926 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
2927 amount = GET_MODE_BITSIZE (mode);
2929 /* Determine the faster direction. After this phase, amount will be
2930 at most a half of GET_MODE_BITSIZE (mode). */
2931 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
2933 /* Flip the direction. */
2934 amount = GET_MODE_BITSIZE (mode) - amount;
2936 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2939 /* See if a byte swap (in HImode) or a word swap (in SImode) can
2940 boost up the rotation. */
2941 if ((mode == HImode && TARGET_H8300 && amount >= 5)
2942 || (mode == HImode && TARGET_H8300H && amount >= 6)
2943 || (mode == HImode && TARGET_H8300S && amount == 8)
2944 || (mode == SImode && TARGET_H8300H && amount >= 10)
2945 || (mode == SImode && TARGET_H8300S && amount >= 13))
2950 /* This code works on any family. */
2951 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
2952 output_asm_insn (insn_buf, operands);
2956 /* This code works on the H8/300H and H8/S. */
2957 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
2958 output_asm_insn (insn_buf, operands);
2965 /* Adjust AMOUNT and flip the direction. */
2966 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
2968 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2971 /* Emit rotate insns. */
2972 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
2975 insn_buf = rotate_two[rotate_type][rotate_mode];
2977 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2979 for (; amount >= bits; amount -= bits)
2980 output_asm_insn (insn_buf, operands);
2986 /* Fix the operands of a gen_xxx so that it could become a bit
2990 fix_bit_operand (operands, what, type)
2995 /* The bit_operand predicate accepts any memory during RTL generation, but
2996 only 'U' memory afterwards, so if this is a MEM operand, we must force
2997 it to be valid for 'U' by reloading the address. */
2999 if (GET_CODE (operands[2]) == CONST_INT)
3001 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
3003 /* Ok to have a memory dest. */
3004 if (GET_CODE (operands[0]) == MEM
3005 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3007 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3008 copy_to_mode_reg (Pmode,
3009 XEXP (operands[0], 0)));
3010 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3014 if (GET_CODE (operands[1]) == MEM
3015 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3017 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3018 copy_to_mode_reg (Pmode,
3019 XEXP (operands[1], 0)));
3020 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3027 /* Dest and src op must be register. */
3029 operands[1] = force_reg (QImode, operands[1]);
3031 rtx res = gen_reg_rtx (QImode);
3032 emit_insn (gen_rtx_SET (VOIDmode, res,
3033 gen_rtx (type, QImode, operands[1], operands[2])));
3034 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3039 /* Return nonzero if FUNC is an interrupt function as specified
3040 by the "interrupt" attribute. */
3043 h8300_interrupt_function_p (func)
3048 if (TREE_CODE (func) != FUNCTION_DECL)
3051 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3052 return a != NULL_TREE;
3055 /* Return nonzero if FUNC is an OS_Task function as specified
3056 by the "OS_Task" attribute. */
3059 h8300_os_task_function_p (func)
3064 if (TREE_CODE (func) != FUNCTION_DECL)
3067 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3068 return a != NULL_TREE;
3071 /* Return nonzero if FUNC is a monitor function as specified
3072 by the "monitor" attribute. */
3075 h8300_monitor_function_p (func)
3080 if (TREE_CODE (func) != FUNCTION_DECL)
3083 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
3084 return a != NULL_TREE;
3087 /* Return nonzero if FUNC is a function that should be called
3088 through the function vector. */
3091 h8300_funcvec_function_p (func)
3096 if (TREE_CODE (func) != FUNCTION_DECL)
3099 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
3100 return a != NULL_TREE;
3103 /* Return nonzero if DECL is a variable that's in the eight bit
3107 h8300_eightbit_data_p (decl)
3112 if (TREE_CODE (decl) != VAR_DECL)
3115 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
3116 return a != NULL_TREE;
3119 /* Return nonzero if DECL is a variable that's in the tiny
3123 h8300_tiny_data_p (decl)
3128 if (TREE_CODE (decl) != VAR_DECL)
3131 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
3132 return a != NULL_TREE;
3135 /* Supported attributes:
3137 interrupt_handler: output a prologue and epilogue suitable for an
3140 function_vector: This function should be called through the
3143 eightbit_data: This variable lives in the 8-bit data area and can
3144 be referenced with 8-bit absolute memory addresses.
3146 tiny_data: This variable lives in the tiny data area and can be
3147 referenced with 16-bit absolute memory references. */
3149 const struct attribute_spec h8300_attribute_table[] =
3151 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3152 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3153 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3154 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3155 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3156 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
3157 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
3158 { NULL, 0, 0, false, false, false, NULL }
3162 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
3163 struct attribute_spec.handler. */
3165 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
3168 tree args ATTRIBUTE_UNUSED;
3169 int flags ATTRIBUTE_UNUSED;
3172 if (TREE_CODE (*node) != FUNCTION_DECL)
3174 warning ("`%s' attribute only applies to functions",
3175 IDENTIFIER_POINTER (name));
3176 *no_add_attrs = true;
3182 /* Handle an "eightbit_data" attribute; arguments as in
3183 struct attribute_spec.handler. */
3185 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
3188 tree args ATTRIBUTE_UNUSED;
3189 int flags ATTRIBUTE_UNUSED;
3194 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3196 if (DECL_INITIAL (decl) == NULL_TREE)
3198 warning ("Only initialized variables can be placed into the 8-bit area.");
3199 *no_add_attrs = true;
3202 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3206 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3207 *no_add_attrs = true;
3213 /* Handle an "tiny_data" attribute; arguments as in
3214 struct attribute_spec.handler. */
3216 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
3219 tree args ATTRIBUTE_UNUSED;
3220 int flags ATTRIBUTE_UNUSED;
3225 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3227 if (DECL_INITIAL (decl) == NULL_TREE)
3229 warning ("Only initialized variables can be placed into the 8-bit area.");
3230 *no_add_attrs = true;
3233 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3237 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3238 *no_add_attrs = true;
3245 h8300_encode_label (decl)
3248 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3249 int len = strlen (str);
3250 char *newstr = alloca (len + 2);
3253 strcpy (&newstr[1], str);
3255 XSTR (XEXP (DECL_RTL (decl), 0), 0) =
3256 ggc_alloc_string (newstr, len + 1);
3260 output_simode_bld (bild, log2, operands)
3265 /* Clear the destination register. */
3266 if (TARGET_H8300H || TARGET_H8300S)
3267 output_asm_insn ("sub.l\t%S0,%S0", operands);
3269 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3271 /* Get the bit number we want to load. */
3273 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3275 /* Now output the bit load or bit inverse load, and store it in
3278 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3280 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3286 /* Given INSN and its current length LENGTH, return the adjustment
3287 (in bytes) to correctly compute INSN's length.
3289 We use this to get the lengths of various memory references correct. */
3292 h8300_adjust_insn_length (insn, length)
3294 int length ATTRIBUTE_UNUSED;
3298 /* We must filter these ou before calling get_attr_adjust_length. */
3299 if (GET_CODE (PATTERN (insn)) == USE
3300 || GET_CODE (PATTERN (insn)) == CLOBBER
3301 || GET_CODE (PATTERN (insn)) == SEQUENCE
3302 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3303 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3306 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3309 pat = PATTERN (insn);
3311 /* Adjust length for reg->mem and mem->reg copies. */
3312 if (GET_CODE (pat) == SET
3313 && (GET_CODE (SET_SRC (pat)) == MEM
3314 || GET_CODE (SET_DEST (pat)) == MEM))
3316 /* This insn might need a length adjustment. */
3319 if (GET_CODE (SET_SRC (pat)) == MEM)
3320 addr = XEXP (SET_SRC (pat), 0);
3322 addr = XEXP (SET_DEST (pat), 0);
3324 /* On the H8/300, only one adjustment is necessary; if the
3325 address mode is register indirect, then this insn is two
3326 bytes shorter than indicated in the machine description. */
3327 if (TARGET_H8300 && GET_CODE (addr) == REG)
3330 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3331 indicated in the machine description. */
3332 if ((TARGET_H8300H || TARGET_H8300S)
3333 && GET_CODE (addr) == REG)
3336 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3337 bytes shorter than indicated in the machine description. */
3338 if ((TARGET_H8300H || TARGET_H8300S)
3339 && GET_CODE (addr) == PLUS
3340 && GET_CODE (XEXP (addr, 0)) == REG
3341 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3342 && INTVAL (XEXP (addr, 1)) > -32768
3343 && INTVAL (XEXP (addr, 1)) < 32767)
3346 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3347 more general abs:24. */
3348 if ((TARGET_H8300H || TARGET_H8300S)
3349 && GET_CODE (addr) == SYMBOL_REF
3350 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3354 /* Loading some constants needs adjustment. */
3355 if (GET_CODE (pat) == SET
3356 && GET_CODE (SET_SRC (pat)) == CONST_INT
3357 && GET_MODE (SET_DEST (pat)) == SImode
3358 && INTVAL (SET_SRC (pat)) != 0)
3360 int val = INTVAL (SET_SRC (pat));
3363 && ((val & 0xffff) == 0
3364 || ((val >> 16) & 0xffff) == 0))
3367 if (TARGET_H8300H || TARGET_H8300S)
3369 if (val == (val & 0xff)
3370 || val == (val & 0xff00))
3373 if (val == -4 || val == -2 || val == -1)
3378 /* Shifts need various adjustments. */
3379 if (GET_CODE (pat) == PARALLEL
3380 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3381 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3382 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3383 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3385 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3386 enum machine_mode mode = GET_MODE (src);
3389 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3392 shift = INTVAL (XEXP (src, 1));
3393 /* According to ANSI, negative shift is undefined. It is
3394 considered to be zero in this case (see function
3395 emit_a_shift above). */
3399 /* QImode shifts by small constants take one insn
3400 per shift. So the adjustment is 20 (md length) -
3402 if (mode == QImode && shift <= 4)
3403 return -(20 - shift * 2);
3405 /* Similarly for HImode and SImode shifts by
3406 small constants on the H8/300H and H8/300S. */
3407 if ((TARGET_H8300H || TARGET_H8300S)
3408 && (mode == HImode || mode == SImode) && shift <= 4)
3409 return -(20 - shift * 2);
3411 /* HImode shifts by small constants for the H8/300. */
3412 if (mode == HImode && shift <= 4)
3413 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3415 /* SImode shifts by small constants for the H8/300. */
3416 if (mode == SImode && shift <= 2)
3417 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3419 /* XXX ??? Could check for more shift/rotate cases here. */
3422 /* Rotations need various adjustments. */
3423 if (GET_CODE (pat) == SET
3424 && (GET_CODE (SET_SRC (pat)) == ROTATE
3425 || GET_CODE (SET_SRC (pat)) == ROTATERT))
3427 rtx src = SET_SRC (pat);
3428 enum machine_mode mode = GET_MODE (src);
3432 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3435 amount = INTVAL (XEXP (src, 1));
3437 /* Clean up AMOUNT. */
3440 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3441 amount = GET_MODE_BITSIZE (mode);
3443 /* Determine the faster direction. After this phase, amount
3444 will be at most a half of GET_MODE_BITSIZE (mode). */
3445 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
3446 /* Flip the direction. */
3447 amount = GET_MODE_BITSIZE (mode) - amount;
3449 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3450 boost up the rotation. */
3451 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3452 || (mode == HImode && TARGET_H8300H && amount >= 6)
3453 || (mode == HImode && TARGET_H8300S && amount == 8)
3454 || (mode == SImode && TARGET_H8300H && amount >= 10)
3455 || (mode == SImode && TARGET_H8300S && amount >= 13))
3457 /* Adjust AMOUNT and flip the direction. */
3458 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3462 /* We use 2-bit rotatations on the H8/S. */
3464 amount = amount / 2 + amount % 2;
3466 /* The H8/300 uses three insns to rotate one bit, taking 6
3468 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
3470 return -(20 - states);
3477 h8300_asm_named_section (name, flags)
3479 unsigned int flags ATTRIBUTE_UNUSED;
3481 /* ??? Perhaps we should be using default_coff_asm_named_section. */
3482 fprintf (asm_out_file, "\t.section %s\n", name);