1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "target-def.h"
46 /* Forward declarations. */
47 static int h8300_interrupt_function_p PARAMS ((tree));
48 static int h8300_monitor_function_p PARAMS ((tree));
49 static int h8300_os_task_function_p PARAMS ((tree));
50 static void dosize PARAMS ((FILE *, const char *, unsigned int));
51 static int round_frame_size PARAMS ((int));
52 static unsigned int compute_saved_regs PARAMS ((void));
53 static void push PARAMS ((FILE *, int));
54 static void pop PARAMS ((FILE *, int));
55 static const char *cond_string PARAMS ((enum rtx_code));
56 const struct attribute_spec h8300_attribute_table[];
57 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
58 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
59 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
60 static void h8300_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
61 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
62 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
64 /* CPU_TYPE, says what cpu we're compiling for. */
67 /* True if the current function is an interrupt handler
68 (either via #pragma or an attribute specification). */
69 int interrupt_handler;
71 /* True if the current function is an OS Task
72 (via an attribute specification). */
75 /* True if the current function is a monitor
76 (via an attribute specification). */
79 /* True if a #pragma saveall has been seen for the current function. */
82 static const char *const names_big[] =
83 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
85 static const char *const names_extended[] =
86 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
88 static const char *const names_upper_extended[] =
89 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
91 /* Points to one of the above. */
92 /* ??? The above could be put in an array indexed by CPU_TYPE. */
93 const char * const *h8_reg_names;
95 /* Various operations needed by the following, indexed by CPU_TYPE. */
97 static const char *const h8_push_ops[2] = { "push", "push.l" };
98 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
99 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
101 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
103 /* Initialize the GCC target structure. */
104 #undef TARGET_ATTRIBUTE_TABLE
105 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
107 #undef TARGET_ASM_FUNCTION_PROLOGUE
108 #define TARGET_ASM_FUNCTION_PROLOGUE h8300_output_function_prologue
109 #undef TARGET_ASM_FUNCTION_EPILOGUE
110 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
112 struct gcc_target targetm = TARGET_INITIALIZER;
114 /* Initialize various cpu specific globals at start up. */
121 cpu_type = (int) CPU_H8300;
122 h8_reg_names = names_big;
126 /* For this we treat the H8/300H and H8/S the same. */
127 cpu_type = (int) CPU_H8300H;
128 h8_reg_names = names_extended;
130 h8_push_op = h8_push_ops[cpu_type];
131 h8_pop_op = h8_pop_ops[cpu_type];
132 h8_mov_op = h8_mov_ops[cpu_type];
134 if (!TARGET_H8300S && TARGET_MAC)
136 error ("-ms2600 is used without -ms.");
146 static const char *const names_small[] =
147 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
148 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
150 return names_small[REGNO (x) * 2 + b];
153 /* REGNO must be saved/restored across calls if this macro is true. */
155 #define WORD_REG_USED(regno) \
157 /* No need to save registers if this function will not return. */\
158 && ! TREE_THIS_VOLATILE (current_function_decl) \
160 /* Save any call saved register that was used. */ \
161 || (regs_ever_live[regno] && !call_used_regs[regno]) \
162 /* Save the frame pointer if it was used. */ \
163 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
164 /* Save any register used in an interrupt handler. */ \
165 || (interrupt_handler && regs_ever_live[regno]) \
166 /* Save call clobbered registers in non-leaf interrupt \
168 || (interrupt_handler \
169 && call_used_regs[regno] \
170 && !current_function_is_leaf)))
172 /* Output assembly language to FILE for the operation OP with operand size
173 SIZE to adjust the stack pointer. */
176 dosize (file, op, size)
181 /* On the H8/300H and H8/S, for sizes <= 8 bytes, it is as good or
182 better to use adds/subs insns rather than add.l/sub.l with an
185 Also, on the H8/300, if we don't have a temporary to hold the
186 size of the frame in the prologue, we simply emit a sequence of
187 subs since this shouldn't happen often. */
188 if ((TARGET_H8300 && size <= 4)
189 || ((TARGET_H8300H || TARGET_H8300S) && size <= 8)
190 || (TARGET_H8300 && current_function_needs_context
191 && ! strcmp (op, "sub")))
193 unsigned HOST_WIDE_INT amount;
195 /* Try different amounts in descending order. */
196 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
200 for (; size >= amount; size -= amount)
201 fprintf (file, "\t%ss\t#%d,sp\n", op, amount);
207 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
209 fprintf (file, "\t%s.l\t#%d,sp\n", op, size);
213 /* Round up frame size SIZE. */
216 round_frame_size (size)
219 return (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
222 /* Compute which registers to push/pop.
223 Return a bit vector of registers. */
226 compute_saved_regs ()
228 unsigned int saved_regs = 0;
231 /* Construct a bit vector of registers to be pushed/popped. */
232 for (regno = 0; regno <= 6; regno++)
234 if (WORD_REG_USED (regno))
235 saved_regs |= 1 << regno;
238 /* Don't push/pop the frame pointer as it is treated separately. */
239 if (frame_pointer_needed)
240 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
245 /* Output assembly language code to push register RN. */
252 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[rn]);
255 /* Output assembly language code to pop register RN. */
262 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[rn]);
265 /* This is what the stack looks like after the prolog of
266 a function with a frame has been set up:
272 <saved registers> <- sp
274 This is what the stack looks like after the prolog of
275 a function which doesn't have a frame:
280 <saved registers> <- sp
283 /* Output assembly language code for the function prologue. */
286 h8300_output_function_prologue (file, size)
290 int fsize = round_frame_size (size);
295 /* Note a function with the interrupt attribute and set interrupt_handler
297 if (h8300_interrupt_function_p (current_function_decl))
298 interrupt_handler = 1;
300 /* If the current function has the OS_Task attribute set, then
301 we have a naked prologue. */
302 if (h8300_os_task_function_p (current_function_decl))
304 fprintf (file, ";OS_Task prologue\n");
309 if (h8300_monitor_function_p (current_function_decl))
311 /* My understanding of monitor functions is they act just
312 like interrupt functions, except the prologue must
314 fprintf (file, ";monitor prologue\n");
315 interrupt_handler = 1;
319 fprintf (file, "\tsubs\t#2,sp\n");
321 fprintf (file, "\tstc\tccr,r0l\n");
322 fprintf (file, "\tmov.b\tr0l,@(2,sp)\n");
324 fprintf (file, "\torc\t#128,ccr\n");
326 else if (TARGET_H8300H)
329 fprintf (file, "\tstc\tccr,r0l\n");
330 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
332 fprintf (file, "\torc\t#128,ccr\n");
334 else if (TARGET_H8300S)
336 fprintf (file, "\tstc\texr,@-sp\n");
338 fprintf (file, "\tstc\tccr,r0l\n");
339 fprintf (file, "\tmov.b\tr0l,@(6,sp)\n");
341 fprintf (file, "\torc\t#128,ccr\n");
347 if (frame_pointer_needed)
350 push (file, FRAME_POINTER_REGNUM);
351 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
352 h8_reg_names[STACK_POINTER_REGNUM],
353 h8_reg_names[FRAME_POINTER_REGNUM]);
356 /* Leave room for locals. */
357 dosize (file, "sub", fsize);
359 /* Push the rest of the registers in ascending order. */
360 saved_regs = compute_saved_regs ();
361 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
366 if (saved_regs & (1 << regno))
370 /* See how many registers we can push at the same time. */
371 if ((regno == 0 || regno == 4)
372 && ((saved_regs >> regno) & 0x0f) == 0x0f)
375 else if ((regno == 0 || regno == 4)
376 && ((saved_regs >> regno) & 0x07) == 0x07)
379 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
380 && ((saved_regs >> regno) & 0x03) == 0x03)
387 fprintf (file, "\tstm.l\t%s-%s,@-sp\n",
389 h8_reg_names[regno + (n_regs - 1)]);
394 /* Output assembly language code for the function epilogue. */
397 h8300_output_function_epilogue (file, size)
401 int fsize = round_frame_size (size);
403 rtx insn = get_last_insn ();
409 /* OS_Task epilogues are nearly naked -- they just have an
411 fprintf (file, ";OS_task epilogue\n");
412 fprintf (file, "\trts\n");
416 /* Monitor epilogues are the same as interrupt function epilogues.
417 Just make a note that we're in an monitor epilogue. */
419 fprintf (file, ";monitor epilogue\n");
421 /* If the last insn was a BARRIER, we don't have to write any code. */
422 if (GET_CODE (insn) == NOTE)
423 insn = prev_nonnote_insn (insn);
424 if (insn && GET_CODE (insn) == BARRIER)
427 /* Pop the saved registers in descending order. */
428 saved_regs = compute_saved_regs ();
429 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
431 int regno = (FIRST_PSEUDO_REGISTER - 1) - idx;
434 if (saved_regs & (1 << regno))
438 /* See how many registers we can pop at the same time. */
439 if ((regno == 7 || regno == 3)
440 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
443 else if ((regno == 6 || regno == 2)
444 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
447 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
448 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
455 fprintf (file, "\tldm.l\t@sp+,%s-%s\n",
456 h8_reg_names[regno - (n_regs - 1)],
457 h8_reg_names[regno]);
461 /* Deallocate locals. */
462 dosize (file, "add", fsize);
464 /* Pop frame pointer if we had one. */
465 if (frame_pointer_needed)
466 pop (file, FRAME_POINTER_REGNUM);
468 if (interrupt_handler)
469 fprintf (file, "\trte\n");
471 fprintf (file, "\trts\n");
474 interrupt_handler = 0;
480 /* Output assembly code for the start of the file. */
483 asm_file_start (file)
486 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
487 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
489 fprintf (file, "; -O%d\n", optimize);
491 fprintf (file, "\n\t.h8300h\n");
492 else if (TARGET_H8300S)
493 fprintf (file, "\n\t.h8300s\n");
495 fprintf (file, "\n\n");
496 output_file_directive (file, main_input_filename);
499 /* Output assembly language code for the end of file. */
505 fprintf (file, "\t.end\n");
508 /* Return true if VALUE is a valid constant for constraint 'P'.
509 IE: VALUE is a power of two <= 2**15. */
512 small_power_of_two (value)
515 int power = exact_log2 (value);
516 return power >= 0 && power <= 15;
519 /* Return true if VALUE is a valid constant for constraint 'O', which
520 means that the constant would be ok to use as a bit for a bclr
527 return small_power_of_two ((~value) & 0xff);
530 /* Return true if OP is a valid source operand for an integer move
534 general_operand_src (op, mode)
536 enum machine_mode mode;
538 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
540 return general_operand (op, mode);
543 /* Return true if OP is a valid destination operand for an integer move
547 general_operand_dst (op, mode)
549 enum machine_mode mode;
551 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
553 return general_operand (op, mode);
556 /* Return true if OP is a const valid for a bit clear instruction. */
559 o_operand (operand, mode)
561 enum machine_mode mode ATTRIBUTE_UNUSED;
563 return (GET_CODE (operand) == CONST_INT
564 && CONST_OK_FOR_O (INTVAL (operand)));
567 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
570 p_operand (operand, mode)
572 enum machine_mode mode ATTRIBUTE_UNUSED;
574 return (GET_CODE (operand) == CONST_INT
575 && CONST_OK_FOR_P (INTVAL (operand)));
578 /* Return true if OP is a valid call operand. */
581 call_insn_operand (op, mode)
583 enum machine_mode mode ATTRIBUTE_UNUSED;
585 if (GET_CODE (op) == MEM)
587 rtx inside = XEXP (op, 0);
588 if (register_operand (inside, Pmode))
590 if (CONSTANT_ADDRESS_P (inside))
596 /* Return 1 if an addition/subtraction of a constant integer can be
597 transformed into two consecutive adds/subs that are faster than the
598 straightforward way. Otherwise, return 0. */
601 two_insn_adds_subs_operand (op, mode)
603 enum machine_mode mode;
605 if (GET_CODE (op) == CONST_INT)
607 HOST_WIDE_INT value = INTVAL (op);
609 /* Force VALUE to be positive so that we do not have to consider
610 the negative case. */
613 if (TARGET_H8300H || TARGET_H8300S)
615 /* A constant addition/subtraction takes 2 states in QImode,
616 4 states in HImode, and 6 states in SImode. Thus, the
617 only case we can win is when SImode is used, in which
618 case, two adds/subs are used, taking 4 states. */
628 /* A constant addition/subtraction takes 2 states in
629 QImode. It takes 6 states in HImode, requiring the
630 constant to be loaded to a register first, and a lot more
631 in SImode. Thus the only case we can win is when either
632 HImode or SImode is used. */
643 /* Split an add of a small constant into two adds/subs insns. */
646 split_adds_subs (mode, operands)
647 enum machine_mode mode;
650 HOST_WIDE_INT val = INTVAL (operands[1]);
651 rtx reg = operands[0];
652 HOST_WIDE_INT sign = 1;
653 HOST_WIDE_INT amount;
655 /* Force VAL to be positive so that we do not have to consider the
663 /* Try different amounts in descending order. */
664 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
668 for (; val >= amount; val -= amount)
670 rtx tmp = gen_rtx_PLUS (mode, reg, GEN_INT (sign * amount));
671 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
678 /* Return true if OP is a valid call operand, and OP represents
679 an operand for a small call (4 bytes instead of 6 bytes). */
682 small_call_insn_operand (op, mode)
684 enum machine_mode mode ATTRIBUTE_UNUSED;
686 if (GET_CODE (op) == MEM)
688 rtx inside = XEXP (op, 0);
690 /* Register indirect is a small call. */
691 if (register_operand (inside, Pmode))
694 /* A call through the function vector is a small
696 if (GET_CODE (inside) == SYMBOL_REF
697 && SYMBOL_REF_FLAG (inside))
700 /* Otherwise it's a large call. */
704 /* Return true if OP is a valid jump operand. */
707 jump_address_operand (op, mode)
709 enum machine_mode mode;
711 if (GET_CODE (op) == REG)
712 return mode == Pmode;
714 if (GET_CODE (op) == MEM)
716 rtx inside = XEXP (op, 0);
717 if (register_operand (inside, Pmode))
719 if (CONSTANT_ADDRESS_P (inside))
725 /* Recognize valid operands for bitfield instructions. */
727 extern int rtx_equal_function_value_matters;
730 bit_operand (op, mode)
732 enum machine_mode mode;
734 /* We can except any general operand, expept that MEM operands must
735 be limited to those that use addresses valid for the 'U' constraint. */
736 if (!general_operand (op, mode))
739 /* Accept any mem during RTL generation. Otherwise, the code that does
740 insv and extzv will think that we can not handle memory. However,
741 to avoid reload problems, we only accept 'U' MEM operands after RTL
742 generation. This means that any named pattern which uses this predicate
743 must force its operands to match 'U' before emitting RTL. */
745 if (GET_CODE (op) == REG)
747 if (GET_CODE (op) == SUBREG)
749 if (!rtx_equal_function_value_matters)
750 /* We're building rtl. */
751 return GET_CODE (op) == MEM;
753 return (GET_CODE (op) == MEM
754 && EXTRA_CONSTRAINT (op, 'U'));
758 bit_memory_operand (op, mode)
760 enum machine_mode mode ATTRIBUTE_UNUSED;
762 return (GET_CODE (op) == MEM
763 && EXTRA_CONSTRAINT (op, 'U'));
766 /* Recognize valid operators for bit test. */
769 eq_operator (x, mode)
771 enum machine_mode mode ATTRIBUTE_UNUSED;
773 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
776 /* Handle machine specific pragmas for compatibility with existing
777 compilers for the H8/300.
779 pragma saveall generates prolog/epilog code which saves and
780 restores all the registers on function entry.
782 pragma interrupt saves and restores all registers, and exits with
783 an rte instruction rather than an rts. A pointer to a function
784 with this attribute may be safely used in an interrupt vector. */
787 h8300_pr_interrupt (pfile)
788 cpp_reader *pfile ATTRIBUTE_UNUSED;
790 interrupt_handler = 1;
794 h8300_pr_saveall (pfile)
795 cpp_reader *pfile ATTRIBUTE_UNUSED;
800 /* If the next arg with MODE and TYPE is to be passed in a register, return
801 the rtx to represent where it is passed. CUM represents the state after
802 the last argument. NAMED is not used. */
804 static const char *const hand_list[] =
824 /* Return an RTX to represent where a value with mode MODE will be returned
825 from a function. If the result is 0, the argument is pushed. */
828 function_arg (cum, mode, type, named)
829 CUMULATIVE_ARGS *cum;
830 enum machine_mode mode;
838 /* Never pass unnamed arguments in registers. */
842 /* Pass 3 regs worth of data in regs when user asked on the command line. */
843 if (TARGET_QUICKCALL)
846 /* If calling hand written assembler, use 4 regs of args. */
850 const char * const *p;
852 fname = XSTR (cum->libcall, 0);
854 /* See if this libcall is one of the hand coded ones. */
856 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
868 size = int_size_in_bytes (type);
870 size = GET_MODE_SIZE (mode);
872 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
878 switch (cum->nbytes / UNITS_PER_WORD)
881 result = gen_rtx_REG (mode, 0);
884 result = gen_rtx_REG (mode, 1);
887 result = gen_rtx_REG (mode, 2);
890 result = gen_rtx_REG (mode, 3);
901 /* Return the cost of the rtx R with code CODE. */
921 if (TARGET_H8300H || TARGET_H8300S)
942 /* Documentation for the machine specific operand escapes:
944 'A' print rn in H8/300 mode, erN in H8/300H mode
945 'C' print (operand - 2).
946 'E' like s but negative.
947 'F' like t but negative.
948 'G' constant just the negative
949 'M' turn a 'M' constant into its negative mod 2.
950 'P' if operand is incing/decing sp, print .w, otherwise .b.
951 'R' print operand as a byte:8 address if appropriate, else fall back to
953 'S' print operand as a long word
954 'T' print operand as a word
955 'U' if operand is incing/decing sp, print l, otherwise nothing.
956 'V' find the set bit, and print its number.
957 'W' find the clear bit, and print its number.
958 'X' print operand as a byte
959 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
960 If this operand isn't a register, fall back to 'R' handling.
962 'b' print the bit opcode
963 'c' print the ibit opcode
964 'd' bcc if EQ, bcs if NE
965 'e' first word of 32 bit value - if reg, then least reg. if mem
966 then least. if const then most sig word
967 'f' second word of 32 bit value - if reg, then biggest reg. if mem
968 then +2. if const then least sig word
969 'g' bcs if EQ, bcc if NE
970 'j' print operand as condition code.
971 'k' print operand as reverse condition code.
972 's' print as low byte of 16 bit value
973 't' print as high byte of 16 bit value
974 'w' print as low byte of 32 bit value
975 'x' print as 2nd byte of 32 bit value
976 'y' print as 3rd byte of 32 bit value
977 'z' print as msb of 32 bit value
980 /* Return assembly language string which identifies a comparison type. */
1013 /* Print operand X using operand code CODE to assembly language output file
1017 print_operand (file, x, code)
1022 /* This is used for communication between the 'P' and 'U' codes. */
1023 static const char *last_p;
1025 /* This is used for communication between codes V,W,Z and Y. */
1031 if (GET_CODE (x) == REG)
1032 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1037 fprintf (file, "#%d", INTVAL (x) - 2);
1040 switch (GET_CODE (x))
1043 fprintf (file, "%sl", names_big[REGNO (x)]);
1046 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1053 switch (GET_CODE (x))
1056 fprintf (file, "%sh", names_big[REGNO (x)]);
1059 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1066 if (GET_CODE (x) != CONST_INT)
1068 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1071 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1078 fprintf (file, "#2");
1084 fprintf (file, "#1");
1091 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1094 fprintf (file, ".w");
1099 fprintf (file, ".b");
1103 if (GET_CODE (x) == REG)
1104 fprintf (file, "%s", names_extended[REGNO (x)]);
1109 if (GET_CODE (x) == REG)
1110 fprintf (file, "%s", names_big[REGNO (x)]);
1115 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1118 bitint = exact_log2 (INTVAL (x));
1121 fprintf (file, "#%d", bitint & 7);
1124 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1127 fprintf (file, "#%d", bitint & 7);
1131 if (GET_CODE (x) == REG)
1132 fprintf (file, "%s", byte_reg (x, 0));
1139 if (GET_CODE (x) == REG)
1140 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1142 print_operand (file, x, 'R');
1146 bitint = INTVAL (x);
1147 fprintf (file, "#%d", bitint & 7);
1150 switch (GET_CODE (x))
1153 fprintf (file, "bor");
1156 fprintf (file, "bxor");
1159 fprintf (file, "band");
1166 switch (GET_CODE (x))
1169 fprintf (file, "bior");
1172 fprintf (file, "bixor");
1175 fprintf (file, "biand");
1182 switch (GET_CODE (x))
1185 fprintf (file, "bcc");
1188 fprintf (file, "bcs");
1195 switch (GET_CODE (x))
1199 fprintf (file, "%s", names_big[REGNO (x)]);
1201 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1204 print_operand (file, x, 0);
1207 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1213 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1214 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1215 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1224 switch (GET_CODE (x))
1228 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1230 fprintf (file, "%s", names_big[REGNO (x)]);
1233 x = adjust_address (x, HImode, 2);
1234 print_operand (file, x, 0);
1237 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1243 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1244 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1245 fprintf (file, "#%ld", (val & 0xffff));
1253 switch (GET_CODE (x))
1256 fprintf (file, "bcc");
1259 fprintf (file, "bcs");
1266 asm_fprintf (file, cond_string (GET_CODE (x)));
1269 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1272 if (GET_CODE (x) == CONST_INT)
1273 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1275 fprintf (file, "%s", byte_reg (x, 0));
1278 if (GET_CODE (x) == CONST_INT)
1279 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1281 fprintf (file, "%s", byte_reg (x, 1));
1284 if (GET_CODE (x) != CONST_INT)
1286 fprintf (file, "%d", INTVAL (x));
1289 if (GET_CODE (x) == CONST_INT)
1290 fprintf (file, "#%d", INTVAL (x) & 0xff);
1292 fprintf (file, "%s",
1293 byte_reg (x, TARGET_H8300 ? 2 : 0));
1296 if (GET_CODE (x) == CONST_INT)
1297 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1299 fprintf (file, "%s",
1300 byte_reg (x, TARGET_H8300 ? 3 : 1));
1303 if (GET_CODE (x) == CONST_INT)
1304 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1306 fprintf (file, "%s", byte_reg (x, 0));
1309 if (GET_CODE (x) == CONST_INT)
1310 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1312 fprintf (file, "%s", byte_reg (x, 1));
1317 switch (GET_CODE (x))
1320 switch (GET_MODE (x))
1323 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1324 fprintf (file, "%s", byte_reg (x, 0));
1325 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1326 fprintf (file, "%s", names_big[REGNO (x)]);
1330 fprintf (file, "%s", names_big[REGNO (x)]);
1334 fprintf (file, "%s", names_extended[REGNO (x)]);
1342 fprintf (file, "@");
1343 output_address (XEXP (x, 0));
1345 /* If this is an 'R' operand (reference into the 8-bit
1346 area), then specify a symbolic address as "foo:8",
1347 otherwise if operand is still in eight bit section, use
1349 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1350 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1351 fprintf (file, (code == 'R' ? ":8" : ":16"));
1352 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1353 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1354 fprintf (file, ":16");
1355 else if ((code == 'R')
1356 && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0)))
1357 fprintf (file, ":8");
1364 fprintf (file, "#");
1365 print_operand_address (file, x);
1371 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1372 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1373 fprintf (file, "#%ld", val);
1382 /* Output assembly language output for the address ADDR to FILE. */
1385 print_operand_address (file, addr)
1389 switch (GET_CODE (addr))
1392 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1396 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1400 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1404 fprintf (file, "(");
1405 if (GET_CODE (XEXP (addr, 0)) == REG)
1408 print_operand_address (file, XEXP (addr, 1));
1409 fprintf (file, ",");
1410 print_operand_address (file, XEXP (addr, 0));
1415 print_operand_address (file, XEXP (addr, 0));
1416 fprintf (file, "+");
1417 print_operand_address (file, XEXP (addr, 1));
1419 fprintf (file, ")");
1424 /* Since the H8/300 only has 16 bit pointers, negative values are also
1425 those >= 32768. This happens for example with pointer minus a
1426 constant. We don't want to turn (char *p - 2) into
1427 (char *p + 65534) because loop unrolling can build upon this
1428 (IE: char *p + 131068). */
1429 int n = INTVAL (addr);
1431 n = (int) (short) n;
1433 /* ??? Why the special case for -ve values? */
1434 fprintf (file, "-%d", -n);
1436 fprintf (file, "%d", n);
1441 output_addr_const (file, addr);
1446 /* Output all insn addresses and their sizes into the assembly language
1447 output file. This is helpful for debugging whether the length attributes
1448 in the md file are correct. This is not meant to be a user selectable
1452 final_prescan_insn (insn, operand, num_operands)
1453 rtx insn, *operand ATTRIBUTE_UNUSED;
1454 int num_operands ATTRIBUTE_UNUSED;
1456 /* This holds the last insn address. */
1457 static int last_insn_address = 0;
1459 int uid = INSN_UID (insn);
1461 if (TARGET_RTL_DUMP)
1463 fprintf (asm_out_file, "\n****************");
1464 print_rtl (asm_out_file, PATTERN (insn));
1465 fprintf (asm_out_file, "\n");
1468 if (TARGET_ADDRESSES)
1470 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1471 INSN_ADDRESSES (uid) - last_insn_address);
1472 last_insn_address = INSN_ADDRESSES (uid);
1476 /* Prepare for an SI sized move. */
1482 rtx src = operands[1];
1483 rtx dst = operands[0];
1484 if (!reload_in_progress && !reload_completed)
1486 if (!register_operand (dst, GET_MODE (dst)))
1488 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1489 emit_move_insn (tmp, src);
1496 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1497 Define the offset between two registers, one to be eliminated, and
1498 the other its replacement, at the start of a routine. */
1501 initial_offset (from, to)
1506 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1507 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1508 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1509 offset = frame_pointer_needed * UNITS_PER_WORD;
1514 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1515 if (WORD_REG_USED (regno))
1516 offset += UNITS_PER_WORD;
1518 /* See the comments for get_frame_size. We need to round it up to
1521 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1522 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1524 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1525 offset += UNITS_PER_WORD; /* Skip saved PC */
1531 h8300_return_addr_rtx (count, frame)
1538 ret = gen_rtx_MEM (Pmode,
1539 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1540 else if (flag_omit_frame_pointer)
1543 ret = gen_rtx_MEM (Pmode,
1544 memory_address (Pmode,
1545 plus_constant (frame, UNITS_PER_WORD)));
1546 set_mem_alias_set (ret, get_frame_alias_set ());
1550 /* Update the condition code from the insn. */
1553 notice_update_cc (body, insn)
1557 switch (get_attr_cc (insn))
1560 /* Insn does not affect CC at all. */
1564 /* Insn does not change CC, but the 0'th operand has been changed. */
1565 if (cc_status.value1 != 0
1566 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1567 cc_status.value1 = 0;
1571 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1572 The V flag is unusable. The C flag may or may not be known but
1573 that's ok because alter_cond will change tests to use EQ/NE. */
1575 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1576 cc_status.value1 = recog_data.operand[0];
1580 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1581 The C flag may or may not be known but that's ok because
1582 alter_cond will change tests to use EQ/NE. */
1584 cc_status.flags |= CC_NO_CARRY;
1585 cc_status.value1 = recog_data.operand[0];
1589 /* The insn is a compare instruction. */
1591 cc_status.value1 = SET_SRC (body);
1595 /* Insn doesn't leave CC in a usable state. */
1601 /* Recognize valid operators for bit instructions. */
1604 bit_operator (x, mode)
1606 enum machine_mode mode ATTRIBUTE_UNUSED;
1608 enum rtx_code code = GET_CODE (x);
1616 output_logical_op (mode, code, operands)
1617 enum machine_mode mode;
1621 /* Pretend that every byte is affected if both operands are registers. */
1622 unsigned HOST_WIDE_INT intval =
1623 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
1624 ? INTVAL (operands[2]) : 0x55555555);
1625 /* The determinant of the algorithm. If we perform an AND, 0
1626 affects a bit. Otherwise, 1 affects a bit. */
1627 unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
1628 /* The name of an insn. */
1650 /* First, see if we can finish with one insn. */
1651 if ((TARGET_H8300H || TARGET_H8300S)
1652 && ((det & 0x00ff) != 0)
1653 && ((det & 0xff00) != 0))
1655 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
1656 output_asm_insn (insn_buf, operands);
1660 /* Take care of the lower byte. */
1661 if ((det & 0x00ff) != 0)
1663 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
1664 output_asm_insn (insn_buf, operands);
1666 /* Take care of the upper byte. */
1667 if ((det & 0xff00) != 0)
1669 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
1670 output_asm_insn (insn_buf, operands);
1675 /* First, see if we can finish with one insn.
1677 If code is either AND or XOR, we exclude two special cases,
1678 0xffffff00 and 0xffff00ff, because insns like sub.w or neg.w
1679 can do a better job. */
1680 if ((TARGET_H8300H || TARGET_H8300S)
1681 && ((det & 0x0000ffff) != 0)
1682 && ((det & 0xffff0000) != 0)
1683 && (code == IOR || det != 0xffffff00)
1684 && (code == IOR || det != 0xffff00ff))
1686 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
1687 output_asm_insn (insn_buf, operands);
1691 /* Take care of the lower and upper words individually. For
1692 each word, we try different methods in the order of
1694 1) the special insn (in case of AND or XOR),
1695 2) the word-wise insn, and
1696 3) The byte-wise insn. */
1697 if ((TARGET_H8300H || TARGET_H8300S)
1698 && ((det & 0x0000ffff) == 0x0000ffff)
1700 output_asm_insn ((code == AND)
1701 ? "sub.w\t%f0,%f0" : "neg.w\t%f0",
1703 else if ((TARGET_H8300H || TARGET_H8300S)
1704 && ((det & 0x000000ff) != 0)
1705 && ((det & 0x0000ff00) != 0))
1707 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
1708 output_asm_insn (insn_buf, operands);
1712 if ((det & 0x000000ff) != 0)
1714 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
1715 output_asm_insn (insn_buf, operands);
1717 if ((det & 0x0000ff00) != 0)
1719 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
1720 output_asm_insn (insn_buf, operands);
1724 if ((TARGET_H8300H || TARGET_H8300S)
1725 && ((det & 0xffff0000) == 0xffff0000)
1727 output_asm_insn ((code == AND)
1728 ? "sub.w\t%e0,%e0" : "neg.w\t%e0",
1730 else if (TARGET_H8300H || TARGET_H8300S)
1732 if ((det & 0xffff0000) != 0)
1734 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
1735 output_asm_insn (insn_buf, operands);
1740 if ((det & 0x00ff0000) != 0)
1742 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
1743 output_asm_insn (insn_buf, operands);
1745 if ((det & 0xff000000) != 0)
1747 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
1748 output_asm_insn (insn_buf, operands);
1761 We devote a fair bit of code to getting efficient shifts since we can only
1762 shift one bit at a time on the H8/300 and H8/300H and only one or two
1763 bits at a time on the H8/S.
1765 The basic shift methods:
1767 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1768 this is the default. SHIFT_LOOP
1770 * inlined shifts -- emit straight line code for the shift; this is
1771 used when a straight line shift is about the same size or smaller
1772 than a loop. We allow the inline version to be slightly longer in
1773 some cases as it saves a register. SHIFT_INLINE
1775 * rotate + and -- rotate the value the opposite direction, then
1776 mask off the values we don't need. This is used when only a few
1777 of the bits in the original value will survive in the shifted value.
1778 Again, this is used when it's about the same size or smaller than
1779 a loop. We allow this version to be slightly longer as it is usually
1780 much faster than a loop. SHIFT_ROT_AND
1782 * swap (+ shifts) -- often it's possible to swap bytes/words to
1783 simulate a shift by 8/16. Once swapped a few inline shifts can be
1784 added if the shift count is slightly more than 8 or 16. This is used
1785 when it's about the same size or smaller than a loop. We allow this
1786 version to be slightly longer as it is usually much faster than a loop.
1789 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1791 Here are some thoughts on what the absolutely positively best code is.
1792 "Best" here means some rational trade-off between code size and speed,
1793 where speed is more preferred but not at the expense of generating 20 insns.
1795 A trailing '*' after the shift count indicates the "best" mode isn't
1798 H8/300 QImode shifts
1799 1-4 - do them inline
1800 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1802 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1803 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1805 H8/300 HImode shifts
1806 1-4 - do them inline
1808 7 - shift 2nd half other way into carry.
1809 copy 1st half into 2nd half
1810 rotate 2nd half other way with carry
1811 rotate 1st half other way (no carry)
1812 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1813 sign extend 1st half (ASHIFTRT)
1814 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1815 9-12 - do shift by 8, inline remaining shifts
1816 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1818 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1819 - ASHIFTRT: shll, subx, set other byte
1821 H8/300 SImode shifts
1822 1-2 - do them inline
1824 7* - shift other way once, move bytes into place,
1825 move carry into place (possibly with sign extension)
1826 8 - move bytes into place, zero or sign extend other
1828 15* - shift other way once, move word into place, move carry into place
1829 16 - move word, zero or sign extend other
1831 24* - move bytes into place, zero or sign extend other
1833 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1836 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1838 ASHIFTRT: shll top byte, subx, copy to other bytes
1840 H8/300H QImode shifts (same as H8/300 QImode shifts)
1841 1-4 - do them inline
1842 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1844 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1845 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1847 H8/300H HImode shifts
1848 1-4 - do them inline
1850 7 - shift 2nd half other way into carry.
1851 copy 1st half into 2nd half
1852 rotate entire word other way using carry
1853 mask off remaining bits (ASHIFT | LSHIFTRT)
1854 sign extend remaining bits (ASHIFTRT)
1855 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1856 9-12 - do shift by 8, inline remaining shifts
1857 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1859 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1860 - ASHIFTRT: shll, subx, set other byte
1862 H8/300H SImode shifts
1863 (These are complicated by the fact that we don't have byte level access to
1865 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1866 1-4 - do them inline
1868 15* - shift other way once, move word into place, move carry into place
1869 (with sign extension for ASHIFTRT)
1870 16 - move word into place, zero or sign extend other
1871 17-20 - do 16bit shift, then inline remaining shifts
1873 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1874 move word 0 to word 1, zero word 0
1875 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1876 zero word 1, zero byte 1
1877 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1878 sign extend byte 0, sign extend word 0
1879 25-27* - either loop, or
1880 do 24 bit shift, inline rest
1881 28-30 - ASHIFT: rotate 4/3/2, mask
1882 LSHIFTRT: rotate 4/3/2, mask
1884 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1887 1-6 - do them inline
1888 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1889 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1892 1-7 - do them inline
1893 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1894 9-12 - do shift by 8, inline remaining shifts
1895 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1897 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1898 - ASHIFTRT: shll, subx, set other byte
1901 (These are complicated by the fact that we don't have byte level access to
1903 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1904 1-10 - do them inline
1906 15* - shift other way once, move word into place, move carry into place
1907 (with sign extension for ASHIFTRT)
1908 16 - move word into place, zero or sign extend other
1909 17-20 - do 16bit shift, then inline remaining shifts
1911 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1912 move word 0 to word 1, zero word 0
1913 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1914 zero word 1, zero byte 1
1915 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1916 sign extend byte 0, sign extend word 0
1917 25-27* - either loop, or
1918 do 24 bit shift, inline rest
1919 28-30 - ASHIFT: rotate 4/3/2, mask
1920 LSHIFTRT: rotate 4/3/2, mask
1922 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1927 nshift_operator (x, mode)
1929 enum machine_mode mode ATTRIBUTE_UNUSED;
1931 switch (GET_CODE (x))
1943 /* Called from the .md file to emit code to do shifts.
1944 Return a boolean indicating success.
1945 (Currently this is always TRUE). */
1948 expand_a_shift (mode, code, operands)
1949 enum machine_mode mode;
1953 emit_move_insn (operands[0], operands[1]);
1955 /* Need a loop to get all the bits we want - we generate the
1956 code at emit time, but need to allocate a scratch reg now. */
1958 emit_insn (gen_rtx_PARALLEL
1961 gen_rtx_SET (VOIDmode, operands[0],
1962 gen_rtx (code, mode, operands[0],
1964 gen_rtx_CLOBBER (VOIDmode,
1965 gen_rtx_SCRATCH (QImode)))));
1970 /* Shift algorithm determination.
1972 There are various ways of doing a shift:
1973 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1975 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1976 necessary bits into position and then set the rest to zero.
1977 SHIFT_SPECIAL: Hand crafted assembler.
1978 SHIFT_LOOP: If the above methods fail, just loop. */
1988 /* Symbols of the various shifts which can be used as indices. */
1992 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
1995 /* Symbols of the various modes which can be used as indices. */
1999 QIshift, HIshift, SIshift
2002 /* For single bit shift insns, record assembler and what bits of the
2003 condition code are valid afterwards (represented as various CC_FOO
2004 bits, 0 means CC isn't left in a usable state). */
2008 const char *const assembler;
2012 /* Assembler instruction shift table.
2014 These tables are used to look up the basic shifts.
2015 They are indexed by cpu, shift_type, and mode. */
2017 static const struct shift_insn shift_one[2][3][3] =
2023 { "shll\t%X0", CC_NO_CARRY },
2024 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2025 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
2027 /* SHIFT_LSHIFTRT */
2029 { "shlr\t%X0", CC_NO_CARRY },
2030 { "shlr\t%t0\n\trotxr\t%s0", 0 },
2031 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2033 /* SHIFT_ASHIFTRT */
2035 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2036 { "shar\t%t0\n\trotxr\t%s0", 0 },
2037 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2044 { "shll.b\t%X0", CC_NO_CARRY },
2045 { "shll.w\t%T0", CC_NO_CARRY },
2046 { "shll.l\t%S0", CC_NO_CARRY }
2048 /* SHIFT_LSHIFTRT */
2050 { "shlr.b\t%X0", CC_NO_CARRY },
2051 { "shlr.w\t%T0", CC_NO_CARRY },
2052 { "shlr.l\t%S0", CC_NO_CARRY }
2054 /* SHIFT_ASHIFTRT */
2056 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2057 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2058 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2063 static const struct shift_insn shift_two[3][3] =
2067 { "shll.b\t#2,%X0", CC_NO_CARRY },
2068 { "shll.w\t#2,%T0", CC_NO_CARRY },
2069 { "shll.l\t#2,%S0", CC_NO_CARRY }
2071 /* SHIFT_LSHIFTRT */
2073 { "shlr.b\t#2,%X0", CC_NO_CARRY },
2074 { "shlr.w\t#2,%T0", CC_NO_CARRY },
2075 { "shlr.l\t#2,%S0", CC_NO_CARRY }
2077 /* SHIFT_ASHIFTRT */
2079 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2080 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2081 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2085 /* Rotates are organized by which shift they'll be used in implementing.
2086 There's no need to record whether the cc is valid afterwards because
2087 it is the AND insn that will decide this. */
2089 static const char *const rotate_one[2][3][3] =
2096 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2099 /* SHIFT_LSHIFTRT */
2102 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2105 /* SHIFT_ASHIFTRT */
2108 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2120 /* SHIFT_LSHIFTRT */
2126 /* SHIFT_ASHIFTRT */
2135 static const char *const rotate_two[3][3] =
2143 /* SHIFT_LSHIFTRT */
2149 /* SHIFT_ASHIFTRT */
2157 /* Macros to keep the shift algorithm tables small. */
2158 #define INL SHIFT_INLINE
2159 #define ROT SHIFT_ROT_AND
2160 #define LOP SHIFT_LOOP
2161 #define SPC SHIFT_SPECIAL
2163 /* The shift algorithms for each machine, mode, shift type, and shift
2164 count are defined below. The three tables below correspond to
2165 QImode, HImode, and SImode, respectively. Each table is organized
2166 by, in the order of indecies, machine, shift type, and shift count. */
2168 static const enum shift_alg shift_alg_qi[3][3][8] = {
2171 /* 0 1 2 3 4 5 6 7 */
2172 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
2173 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
2174 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
2178 /* 0 1 2 3 4 5 6 7 */
2179 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
2180 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
2181 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
2185 /* 0 1 2 3 4 5 6 7 */
2186 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
2187 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
2188 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
2192 static const enum shift_alg shift_alg_hi[3][3][16] = {
2195 /* 0 1 2 3 4 5 6 7 */
2196 /* 8 9 10 11 12 13 14 15 */
2197 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2198 SPC, SPC, SPC, SPC, SPC, LOP, LOP, ROT }, /* SHIFT_ASHIFT */
2199 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2200 SPC, SPC, SPC, SPC, SPC, LOP, LOP, ROT }, /* SHIFT_LSHIFTRT */
2201 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2202 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2206 /* 0 1 2 3 4 5 6 7 */
2207 /* 8 9 10 11 12 13 14 15 */
2208 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2209 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
2210 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2211 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
2212 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
2213 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2217 /* 0 1 2 3 4 5 6 7 */
2218 /* 8 9 10 11 12 13 14 15 */
2219 { INL, INL, INL, INL, INL, INL, INL, INL,
2220 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
2221 { INL, INL, INL, INL, INL, INL, INL, INL,
2222 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
2223 { INL, INL, INL, INL, INL, INL, INL, INL,
2224 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2228 static const enum shift_alg shift_alg_si[3][3][32] = {
2231 /* 0 1 2 3 4 5 6 7 */
2232 /* 8 9 10 11 12 13 14 15 */
2233 /* 16 17 18 19 20 21 22 23 */
2234 /* 24 25 26 27 28 29 30 31 */
2235 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
2236 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2237 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2238 LOP, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
2239 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
2240 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2241 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2242 LOP, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
2243 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
2244 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2245 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2246 LOP, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2250 /* 0 1 2 3 4 5 6 7 */
2251 /* 8 9 10 11 12 13 14 15 */
2252 /* 16 17 18 19 20 21 22 23 */
2253 /* 24 25 26 27 28 29 30 31 */
2254 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
2255 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
2256 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
2257 SPC, LOP, LOP, LOP, ROT, ROT, ROT, SPC }, /* SHIFT_ASHIFT */
2258 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
2259 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
2260 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
2261 SPC, LOP, LOP, LOP, ROT, ROT, ROT, SPC }, /* SHIFT_LSHIFTRT */
2262 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
2263 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
2264 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
2265 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2269 /* 0 1 2 3 4 5 6 7 */
2270 /* 8 9 10 11 12 13 14 15 */
2271 /* 16 17 18 19 20 21 22 23 */
2272 /* 24 25 26 27 28 29 30 31 */
2273 { INL, INL, INL, INL, INL, INL, INL, INL,
2274 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
2275 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
2276 SPC, LOP, LOP, LOP, ROT, ROT, ROT, SPC }, /* SHIFT_ASHIFT */
2277 { INL, INL, INL, INL, INL, INL, INL, INL,
2278 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
2279 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
2280 SPC, LOP, LOP, LOP, ROT, ROT, ROT, SPC }, /* SHIFT_LSHIFTRT */
2281 { INL, INL, INL, INL, INL, INL, INL, INL,
2282 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
2283 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
2284 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
2294 /* Shift algorithm. */
2297 /* The number of bits to be shifted by shift1 and shift2. Valid
2298 when ALG is SHIFT_SPECIAL. */
2299 unsigned int remainder;
2301 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2302 const char *special;
2304 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2305 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2308 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2309 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2312 /* Valid CC flags. */
2316 static void get_shift_alg PARAMS ((enum shift_type,
2317 enum shift_mode, unsigned int,
2318 struct shift_info *));
2320 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2321 best algorithm for doing the shift. The assembler code is stored
2322 in the pointers in INFO. We don't achieve maximum efficiency in
2323 all cases, but the hooks are here to do so.
2325 For now we just use lots of switch statements. Since we don't even come
2326 close to supporting all the cases, this is simplest. If this function ever
2327 gets too big, perhaps resort to a more table based lookup. Of course,
2328 at this point you may just wish to do it all in rtl.
2330 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2331 1,2,3,4 will be inlined (1,2 for SI). */
2334 get_shift_alg (shift_type, shift_mode, count, info)
2335 enum shift_type shift_type;
2336 enum shift_mode shift_mode;
2338 struct shift_info *info;
2342 /* Find the target CPU. */
2345 else if (TARGET_H8300H)
2350 /* Find the shift algorithm. */
2354 if (GET_MODE_BITSIZE (QImode) <= count)
2355 info->alg = SHIFT_LOOP;
2357 info->alg = shift_alg_qi[cpu][shift_type][count];
2361 if (GET_MODE_BITSIZE (HImode) <= count)
2362 info->alg = SHIFT_LOOP;
2364 info->alg = shift_alg_hi[cpu][shift_type][count];
2368 if (GET_MODE_BITSIZE (SImode) <= count)
2369 info->alg = SHIFT_LOOP;
2371 info->alg = shift_alg_si[cpu][shift_type][count];
2378 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2382 info->remainder = count;
2386 /* It is up to the caller to know that looping clobbers cc. */
2387 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2388 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2389 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2393 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2394 info->shift2 = rotate_two[shift_type][shift_mode];
2395 info->cc_valid_p = 0;
2399 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2400 info->remainder = 0;
2401 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2402 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2403 info->cc_valid_p = 0;
2407 /* Here we only deal with SHIFT_SPECIAL. */
2411 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2412 through the entire value. */
2413 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2415 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2423 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2425 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2429 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2431 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2435 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2437 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2441 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2443 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2447 if (shift_type == SHIFT_ASHIFTRT)
2449 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2453 else if (8 <= count && count <= 12)
2455 info->remainder = count - 8;
2460 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2461 info->shift1 = "shal.b\t%t0";
2462 info->shift2 = "shal.b\t#2,%t0";
2464 case SHIFT_LSHIFTRT:
2465 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2466 info->shift1 = "shlr.b\t%s0";
2467 info->shift2 = "shlr.b\t#2,%s0";
2469 case SHIFT_ASHIFTRT:
2471 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2473 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2474 info->shift1 = "shar.b\t%s0";
2475 info->shift2 = "shar.b\t#2,%s0";
2479 else if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2481 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2487 if (count == 8 && TARGET_H8300)
2492 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2494 case SHIFT_LSHIFTRT:
2495 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2497 case SHIFT_ASHIFTRT:
2498 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2502 else if (count == 8 && !TARGET_H8300)
2507 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2509 case SHIFT_LSHIFTRT:
2510 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2512 case SHIFT_ASHIFTRT:
2513 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2517 else if (count == 15 && !TARGET_H8300)
2522 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
2524 case SHIFT_LSHIFTRT:
2525 info->special = "shll.w\t%e0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
2529 else if ((TARGET_H8300 && count == 16)
2530 || (TARGET_H8300H && 16 <= count && count <= 19)
2531 || (TARGET_H8300S && 16 <= count && count <= 21))
2533 info->remainder = count - 16;
2538 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2539 info->shift1 = "shll.l\t%S0";
2540 info->shift2 = "shll.l\t#2,%S0";
2542 case SHIFT_LSHIFTRT:
2543 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2544 info->shift1 = "shlr.l\t%S0";
2545 info->shift2 = "shlr.l\t#2,%S0";
2547 case SHIFT_ASHIFTRT:
2549 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2551 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2552 info->shift1 = "shar.l\t%S0";
2553 info->shift2 = "shar.l\t#2,%S0";
2557 else if (count == 24 && !TARGET_H8300)
2562 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2564 case SHIFT_LSHIFTRT:
2565 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2567 case SHIFT_ASHIFTRT:
2568 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2572 else if (count == 31)
2579 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2581 case SHIFT_LSHIFTRT:
2582 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2584 case SHIFT_ASHIFTRT:
2585 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2594 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
2596 case SHIFT_LSHIFTRT:
2597 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
2599 case SHIFT_ASHIFTRT:
2600 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2613 info->shift2 = NULL;
2616 /* Emit the assembler code for doing shifts. */
2619 emit_a_shift (insn, operands)
2620 rtx insn ATTRIBUTE_UNUSED;
2623 static int loopend_lab;
2624 rtx shift = operands[3];
2625 enum machine_mode mode = GET_MODE (shift);
2626 enum rtx_code code = GET_CODE (shift);
2627 enum shift_type shift_type;
2628 enum shift_mode shift_mode;
2629 struct shift_info info;
2636 shift_mode = QIshift;
2639 shift_mode = HIshift;
2642 shift_mode = SIshift;
2651 shift_type = SHIFT_ASHIFTRT;
2654 shift_type = SHIFT_LSHIFTRT;
2657 shift_type = SHIFT_ASHIFT;
2663 if (GET_CODE (operands[2]) != CONST_INT)
2665 /* Indexing by reg, so have to loop and test at top. */
2666 output_asm_insn ("mov.b %X2,%X4", operands);
2667 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2669 /* Get the assembler code to do one shift. */
2670 get_shift_alg (shift_type, shift_mode, 1, &info);
2672 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2673 output_asm_insn (info.shift1, operands);
2674 output_asm_insn ("add #0xff,%X4", operands);
2675 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2676 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2682 int n = INTVAL (operands[2]);
2684 /* If the count is negative, make it 0. */
2687 /* If the count is too big, truncate it.
2688 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2689 do the intuitive thing. */
2690 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
2691 n = GET_MODE_BITSIZE (mode);
2693 get_shift_alg (shift_type, shift_mode, n, &info);
2698 output_asm_insn (info.special, operands);
2704 /* Emit two bit shifts first. */
2705 while (n > 1 && info.shift2 != NULL)
2707 output_asm_insn (info.shift2, operands);
2711 /* Now emit one bit shifts for any residual. */
2714 output_asm_insn (info.shift1, operands);
2718 /* Keep track of CC. */
2719 if (info.cc_valid_p)
2721 cc_status.value1 = operands[0];
2722 cc_status.flags |= info.cc_valid_p;
2728 int m = GET_MODE_BITSIZE (mode) - n;
2729 int mask = (shift_type == SHIFT_ASHIFT
2730 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2731 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2734 /* Not all possibilities of rotate are supported. They shouldn't
2735 be generated, but let's watch for 'em. */
2736 if (info.shift1 == 0)
2739 /* Emit two bit rotates first. */
2740 while (m > 1 && info.shift2 != NULL)
2742 output_asm_insn (info.shift2, operands);
2746 /* Now single bit rotates for any residual. */
2749 output_asm_insn (info.shift1, operands);
2753 /* Now mask off the high bits. */
2759 sprintf (insn_buf, "and\t#%d,%%X0", mask);
2760 cc_status.value1 = operands[0];
2761 cc_status.flags |= CC_NO_CARRY;
2764 sprintf (insn_buf, "and\t#%d,%%s0\n\tand\t#%d,%%t0",
2765 mask & 255, mask >> 8);
2775 sprintf (insn_buf, "and.%c\t#%d,%%%c0",
2776 "bwl"[shift_mode], mask,
2777 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2778 cc_status.value1 = operands[0];
2779 cc_status.flags |= CC_NO_CARRY;
2781 output_asm_insn (insn_buf, operands);
2786 /* A loop to shift by a "large" constant value.
2787 If we have shift-by-2 insns, use them. */
2788 if (info.shift2 != NULL)
2790 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2791 names_big[REGNO (operands[4])]);
2792 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2793 output_asm_insn (info.shift2, operands);
2794 output_asm_insn ("add #0xff,%X4", operands);
2795 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2797 output_asm_insn (info.shift1, operands);
2801 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2802 names_big[REGNO (operands[4])]);
2803 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2804 output_asm_insn (info.shift1, operands);
2805 output_asm_insn ("add #0xff,%X4", operands);
2806 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2816 /* A rotation by a non-constant will cause a loop to be generated, in
2817 which a rotation by one bit is used. A rotation by a constant,
2818 including the one in the loop, will be taken care of by
2819 emit_a_rotate () at the insn emit time. */
2822 expand_a_rotate (code, operands)
2826 rtx dst = operands[0];
2827 rtx src = operands[1];
2828 rtx rotate_amount = operands[2];
2829 enum machine_mode mode = GET_MODE (dst);
2832 /* We rotate in place. */
2833 emit_move_insn (dst, src);
2835 if (GET_CODE (rotate_amount) != CONST_INT)
2837 rtx counter = gen_reg_rtx (QImode);
2838 rtx start_label = gen_label_rtx ();
2839 rtx end_label = gen_label_rtx ();
2841 /* If the rotate amount is less than or equal to 0,
2842 we go out of the loop. */
2843 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0),
2844 LE, NULL_RTX, QImode, 0, 0, end_label);
2846 /* Initialize the loop counter. */
2847 emit_move_insn (counter, rotate_amount);
2849 emit_label (start_label);
2851 /* Rotate by one bit. */
2852 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
2853 emit_insn (gen_rtx_SET (mode, dst, tmp));
2855 /* Decrement the counter by 1. */
2856 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
2857 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
2859 /* If the loop counter is non-zero, we go back to the beginning
2861 emit_cmp_and_jump_insns (counter, GEN_INT (0),
2862 NE, NULL_RTX, QImode, 1, 0, start_label);
2864 emit_label (end_label);
2868 /* Rotate by AMOUNT bits. */
2869 tmp = gen_rtx (code, mode, dst, rotate_amount);
2870 emit_insn (gen_rtx_SET (mode, dst, tmp));
2876 /* Emit rotate insns. */
2879 emit_a_rotate (code, operands)
2883 rtx dst = operands[0];
2884 rtx rotate_amount = operands[2];
2885 enum shift_mode rotate_mode;
2886 enum shift_type rotate_type;
2887 const char *insn_buf;
2890 enum machine_mode mode = GET_MODE (dst);
2892 if (GET_CODE (rotate_amount) != CONST_INT)
2898 rotate_mode = QIshift;
2901 rotate_mode = HIshift;
2904 rotate_mode = SIshift;
2913 rotate_type = SHIFT_ASHIFT;
2916 rotate_type = SHIFT_LSHIFTRT;
2922 amount = INTVAL (rotate_amount);
2924 /* Clean up AMOUNT. */
2927 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
2928 amount = GET_MODE_BITSIZE (mode);
2930 /* Determine the faster direction. After this phase, amount will be
2931 at most a half of GET_MODE_BITSIZE (mode). */
2932 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
2934 /* Flip the direction. */
2935 amount = GET_MODE_BITSIZE (mode) - amount;
2937 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2940 /* See if a byte swap (in HImode) or a word swap (in SImode) can
2941 boost up the rotation. */
2942 if ((mode == HImode && TARGET_H8300 && amount >= 5)
2943 || (mode == HImode && TARGET_H8300H && amount >= 6)
2944 || (mode == HImode && TARGET_H8300S && amount == 8)
2945 || (mode == SImode && TARGET_H8300H && amount >= 10)
2946 || (mode == SImode && TARGET_H8300S && amount >= 13))
2951 /* This code works on any family. */
2952 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
2953 output_asm_insn (insn_buf, operands);
2957 /* This code works on the H8/300H and H8/S. */
2958 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
2959 output_asm_insn (insn_buf, operands);
2966 /* Adjust AMOUNT and flip the direction. */
2967 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
2969 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
2972 /* Emit rotate insns. */
2973 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
2976 insn_buf = rotate_two[rotate_type][rotate_mode];
2978 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
2980 for (; amount >= bits; amount -= bits)
2981 output_asm_insn (insn_buf, operands);
2987 /* Fix the operands of a gen_xxx so that it could become a bit
2991 fix_bit_operand (operands, what, type)
2996 /* The bit_operand predicate accepts any memory during RTL generation, but
2997 only 'U' memory afterwards, so if this is a MEM operand, we must force
2998 it to be valid for 'U' by reloading the address. */
3000 if (GET_CODE (operands[2]) == CONST_INT)
3002 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
3004 /* Ok to have a memory dest. */
3005 if (GET_CODE (operands[0]) == MEM
3006 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3008 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3009 copy_to_mode_reg (Pmode,
3010 XEXP (operands[0], 0)));
3011 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3015 if (GET_CODE (operands[1]) == MEM
3016 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3018 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3019 copy_to_mode_reg (Pmode,
3020 XEXP (operands[1], 0)));
3021 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3028 /* Dest and src op must be register. */
3030 operands[1] = force_reg (QImode, operands[1]);
3032 rtx res = gen_reg_rtx (QImode);
3033 emit_insn (gen_rtx_SET (VOIDmode, res,
3034 gen_rtx (type, QImode, operands[1], operands[2])));
3035 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3040 /* Return nonzero if FUNC is an interrupt function as specified
3041 by the "interrupt" attribute. */
3044 h8300_interrupt_function_p (func)
3049 if (TREE_CODE (func) != FUNCTION_DECL)
3052 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3053 return a != NULL_TREE;
3056 /* Return nonzero if FUNC is an OS_Task function as specified
3057 by the "OS_Task" attribute. */
3060 h8300_os_task_function_p (func)
3065 if (TREE_CODE (func) != FUNCTION_DECL)
3068 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3069 return a != NULL_TREE;
3072 /* Return nonzero if FUNC is a monitor function as specified
3073 by the "monitor" attribute. */
3076 h8300_monitor_function_p (func)
3081 if (TREE_CODE (func) != FUNCTION_DECL)
3084 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
3085 return a != NULL_TREE;
3088 /* Return nonzero if FUNC is a function that should be called
3089 through the function vector. */
3092 h8300_funcvec_function_p (func)
3097 if (TREE_CODE (func) != FUNCTION_DECL)
3100 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
3101 return a != NULL_TREE;
3104 /* Return nonzero if DECL is a variable that's in the eight bit
3108 h8300_eightbit_data_p (decl)
3113 if (TREE_CODE (decl) != VAR_DECL)
3116 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
3117 return a != NULL_TREE;
3120 /* Return nonzero if DECL is a variable that's in the tiny
3124 h8300_tiny_data_p (decl)
3129 if (TREE_CODE (decl) != VAR_DECL)
3132 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
3133 return a != NULL_TREE;
3136 /* Supported attributes:
3138 interrupt_handler: output a prologue and epilogue suitable for an
3141 function_vector: This function should be called through the
3144 eightbit_data: This variable lives in the 8-bit data area and can
3145 be referenced with 8-bit absolute memory addresses.
3147 tiny_data: This variable lives in the tiny data area and can be
3148 referenced with 16-bit absolute memory references. */
3150 const struct attribute_spec h8300_attribute_table[] =
3152 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3153 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3154 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3155 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3156 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3157 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
3158 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
3159 { NULL, 0, 0, false, false, false, NULL }
3163 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
3164 struct attribute_spec.handler. */
3166 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
3169 tree args ATTRIBUTE_UNUSED;
3170 int flags ATTRIBUTE_UNUSED;
3173 if (TREE_CODE (*node) != FUNCTION_DECL)
3175 warning ("`%s' attribute only applies to functions",
3176 IDENTIFIER_POINTER (name));
3177 *no_add_attrs = true;
3183 /* Handle an "eightbit_data" attribute; arguments as in
3184 struct attribute_spec.handler. */
3186 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
3189 tree args ATTRIBUTE_UNUSED;
3190 int flags ATTRIBUTE_UNUSED;
3195 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3197 if (DECL_INITIAL (decl) == NULL_TREE)
3199 warning ("Only initialized variables can be placed into the 8-bit area.");
3200 *no_add_attrs = true;
3203 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3207 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3208 *no_add_attrs = true;
3214 /* Handle an "tiny_data" attribute; arguments as in
3215 struct attribute_spec.handler. */
3217 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
3220 tree args ATTRIBUTE_UNUSED;
3221 int flags ATTRIBUTE_UNUSED;
3226 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
3228 if (DECL_INITIAL (decl) == NULL_TREE)
3230 warning ("Only initialized variables can be placed into the 8-bit area.");
3231 *no_add_attrs = true;
3234 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3238 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
3239 *no_add_attrs = true;
3246 h8300_encode_label (decl)
3249 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3250 int len = strlen (str);
3251 char *newstr = alloca (len + 2);
3254 strcpy (&newstr[1], str);
3256 XSTR (XEXP (DECL_RTL (decl), 0), 0) =
3257 ggc_alloc_string (newstr, len + 1);
3261 output_simode_bld (bild, log2, operands)
3266 /* Clear the destination register. */
3267 if (TARGET_H8300H || TARGET_H8300S)
3268 output_asm_insn ("sub.l\t%S0,%S0", operands);
3270 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3272 /* Get the bit number we want to load. */
3274 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3276 /* Now output the bit load or bit inverse load, and store it in
3279 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3281 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3287 /* Given INSN and its current length LENGTH, return the adjustment
3288 (in bytes) to correctly compute INSN's length.
3290 We use this to get the lengths of various memory references correct. */
3293 h8300_adjust_insn_length (insn, length)
3295 int length ATTRIBUTE_UNUSED;
3299 /* We must filter these ou before calling get_attr_adjust_length. */
3300 if (GET_CODE (PATTERN (insn)) == USE
3301 || GET_CODE (PATTERN (insn)) == CLOBBER
3302 || GET_CODE (PATTERN (insn)) == SEQUENCE
3303 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3304 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3307 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3310 pat = PATTERN (insn);
3312 /* Adjust length for reg->mem and mem->reg copies. */
3313 if (GET_CODE (pat) == SET
3314 && (GET_CODE (SET_SRC (pat)) == MEM
3315 || GET_CODE (SET_DEST (pat)) == MEM))
3317 /* This insn might need a length adjustment. */
3320 if (GET_CODE (SET_SRC (pat)) == MEM)
3321 addr = XEXP (SET_SRC (pat), 0);
3323 addr = XEXP (SET_DEST (pat), 0);
3325 /* On the H8/300, only one adjustment is necessary; if the
3326 address mode is register indirect, then this insn is two
3327 bytes shorter than indicated in the machine description. */
3328 if (TARGET_H8300 && GET_CODE (addr) == REG)
3331 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3332 indicated in the machine description. */
3333 if ((TARGET_H8300H || TARGET_H8300S)
3334 && GET_CODE (addr) == REG)
3337 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3338 bytes shorter than indicated in the machine description. */
3339 if ((TARGET_H8300H || TARGET_H8300S)
3340 && GET_CODE (addr) == PLUS
3341 && GET_CODE (XEXP (addr, 0)) == REG
3342 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3343 && INTVAL (XEXP (addr, 1)) > -32768
3344 && INTVAL (XEXP (addr, 1)) < 32767)
3347 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3348 more general abs:24. */
3349 if ((TARGET_H8300H || TARGET_H8300S)
3350 && GET_CODE (addr) == SYMBOL_REF
3351 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3355 /* Loading some constants needs adjustment. */
3356 if (GET_CODE (pat) == SET
3357 && GET_CODE (SET_SRC (pat)) == CONST_INT
3358 && GET_MODE (SET_DEST (pat)) == SImode
3359 && INTVAL (SET_SRC (pat)) != 0)
3361 int val = INTVAL (SET_SRC (pat));
3364 && ((val & 0xffff) == 0
3365 || ((val >> 16) & 0xffff) == 0))
3368 if (TARGET_H8300H || TARGET_H8300S)
3370 if (val == (val & 0xff)
3371 || val == (val & 0xff00))
3374 if (val == -4 || val == -2 || val == -1)
3379 /* Shifts need various adjustments. */
3380 if (GET_CODE (pat) == PARALLEL
3381 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3382 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3383 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3384 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3386 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3387 enum machine_mode mode = GET_MODE (src);
3390 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3393 shift = INTVAL (XEXP (src, 1));
3394 /* According to ANSI, negative shift is undefined. It is
3395 considered to be zero in this case (see function
3396 emit_a_shift above). */
3400 /* QImode shifts by small constants take one insn
3401 per shift. So the adjustment is 20 (md length) -
3403 if (mode == QImode && shift <= 4)
3404 return -(20 - shift * 2);
3406 /* Similarly for HImode and SImode shifts by
3407 small constants on the H8/300H and H8/300S. */
3408 if ((TARGET_H8300H || TARGET_H8300S)
3409 && (mode == HImode || mode == SImode) && shift <= 4)
3410 return -(20 - shift * 2);
3412 /* HImode shifts by small constants for the H8/300. */
3413 if (mode == HImode && shift <= 4)
3414 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3416 /* SImode shifts by small constants for the H8/300. */
3417 if (mode == SImode && shift <= 2)
3418 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3420 /* XXX ??? Could check for more shift/rotate cases here. */
3423 /* Rotations need various adjustments. */
3424 if (GET_CODE (pat) == SET
3425 && (GET_CODE (SET_SRC (pat)) == ROTATE
3426 || GET_CODE (SET_SRC (pat)) == ROTATERT))
3428 rtx src = SET_SRC (pat);
3429 enum machine_mode mode = GET_MODE (src);
3433 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3436 amount = INTVAL (XEXP (src, 1));
3438 /* Clean up AMOUNT. */
3441 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3442 amount = GET_MODE_BITSIZE (mode);
3444 /* Determine the faster direction. After this phase, amount
3445 will be at most a half of GET_MODE_BITSIZE (mode). */
3446 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
3447 /* Flip the direction. */
3448 amount = GET_MODE_BITSIZE (mode) - amount;
3450 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3451 boost up the rotation. */
3452 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3453 || (mode == HImode && TARGET_H8300H && amount >= 6)
3454 || (mode == HImode && TARGET_H8300S && amount == 8)
3455 || (mode == SImode && TARGET_H8300H && amount >= 10)
3456 || (mode == SImode && TARGET_H8300S && amount >= 13))
3458 /* Adjust AMOUNT and flip the direction. */
3459 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3463 /* We use 2-bit rotatations on the H8/S. */
3465 amount = amount / 2 + amount % 2;
3467 /* The H8/300 uses three insns to rotate one bit, taking 6
3469 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
3471 return -(20 - states);
3478 h8300_asm_named_section (name, flags)
3480 unsigned int flags ATTRIBUTE_UNUSED;
3482 /* ??? Perhaps we should be using default_coff_asm_named_section. */
3483 fprintf (asm_out_file, "\t.section %s\n", name);