1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Steve Chamberlain (sac@cygnus.com),
6 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
41 #include "diagnostic-core.h"
42 #include "c-family/c-pragma.h" /* ??? */
44 #include "tm-constrs.h"
47 #include "target-def.h"
50 /* Classifies a h8300_src_operand or h8300_dst_operand.
53 A constant operand of some sort.
59 A memory reference with a constant address.
62 A memory reference with a register as its address.
65 Some other kind of memory reference. */
66 enum h8300_operand_class
76 /* For a general two-operand instruction, element [X][Y] gives
77 the length of the opcode fields when the first operand has class
78 (X + 1) and the second has class Y. */
79 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS];
81 /* Forward declarations. */
82 static const char *byte_reg (rtx, int);
83 static int h8300_interrupt_function_p (tree);
84 static int h8300_saveall_function_p (tree);
85 static int h8300_monitor_function_p (tree);
86 static int h8300_os_task_function_p (tree);
87 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT, bool);
88 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT);
89 static unsigned int compute_saved_regs (void);
90 static void push (int);
91 static void pop (int);
92 static const char *cond_string (enum rtx_code);
93 static unsigned int h8300_asm_insn_count (const char *);
94 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
95 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *);
96 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *);
97 static void h8300_print_operand_address (FILE *, rtx);
98 static void h8300_print_operand (FILE *, rtx, int);
99 static bool h8300_print_operand_punct_valid_p (unsigned char code);
100 #ifndef OBJECT_FORMAT_ELF
101 static void h8300_asm_named_section (const char *, unsigned int, tree);
103 static int h8300_register_move_cost (enum machine_mode, reg_class_t, reg_class_t);
104 static int h8300_and_costs (rtx);
105 static int h8300_shift_costs (rtx);
106 static void h8300_push_pop (int, int, bool, bool);
107 static int h8300_stack_offset_p (rtx, int);
108 static int h8300_ldm_stm_regno (rtx, int, int, int);
109 static void h8300_reorg (void);
110 static unsigned int h8300_constant_length (rtx);
111 static unsigned int h8300_displacement_length (rtx, int);
112 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *);
113 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *);
114 static unsigned int h8300_unary_length (rtx);
115 static unsigned int h8300_short_immediate_length (rtx);
116 static unsigned int h8300_bitfield_length (rtx, rtx);
117 static unsigned int h8300_binary_length (rtx, const h8300_length_table *);
118 static bool h8300_short_move_mem_p (rtx, enum rtx_code);
119 static unsigned int h8300_move_length (rtx *, const h8300_length_table *);
120 static bool h8300_hard_regno_scratch_ok (unsigned int);
121 static rtx h8300_get_index (rtx, enum machine_mode mode, int *);
123 /* CPU_TYPE, says what cpu we're compiling for. */
126 /* True if a #pragma interrupt has been seen for the current function. */
127 static int pragma_interrupt;
129 /* True if a #pragma saveall has been seen for the current function. */
130 static int pragma_saveall;
132 static const char *const names_big[] =
133 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
135 static const char *const names_extended[] =
136 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
138 static const char *const names_upper_extended[] =
139 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
141 /* Points to one of the above. */
142 /* ??? The above could be put in an array indexed by CPU_TYPE. */
143 const char * const *h8_reg_names;
145 /* Various operations needed by the following, indexed by CPU_TYPE. */
147 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
149 /* Value of MOVE_RATIO. */
150 int h8300_move_ratio;
152 /* See below where shifts are handled for explanation of this enum. */
162 /* Symbols of the various shifts which can be used as indices. */
166 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
169 /* Macros to keep the shift algorithm tables small. */
170 #define INL SHIFT_INLINE
171 #define ROT SHIFT_ROT_AND
172 #define LOP SHIFT_LOOP
173 #define SPC SHIFT_SPECIAL
175 /* The shift algorithms for each machine, mode, shift type, and shift
176 count are defined below. The three tables below correspond to
177 QImode, HImode, and SImode, respectively. Each table is organized
178 by, in the order of indices, machine, shift type, and shift count. */
180 static enum shift_alg shift_alg_qi[3][3][8] = {
183 /* 0 1 2 3 4 5 6 7 */
184 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
185 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
186 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
190 /* 0 1 2 3 4 5 6 7 */
191 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
192 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
193 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
197 /* 0 1 2 3 4 5 6 7 */
198 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
199 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
200 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
204 static enum shift_alg shift_alg_hi[3][3][16] = {
207 /* 0 1 2 3 4 5 6 7 */
208 /* 8 9 10 11 12 13 14 15 */
209 { INL, INL, INL, INL, INL, INL, INL, SPC,
210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
211 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
212 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
213 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
214 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
218 /* 0 1 2 3 4 5 6 7 */
219 /* 8 9 10 11 12 13 14 15 */
220 { INL, INL, INL, INL, INL, INL, INL, SPC,
221 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
222 { INL, INL, INL, INL, INL, INL, INL, SPC,
223 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
224 { INL, INL, INL, INL, INL, INL, INL, SPC,
225 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
229 /* 0 1 2 3 4 5 6 7 */
230 /* 8 9 10 11 12 13 14 15 */
231 { INL, INL, INL, INL, INL, INL, INL, INL,
232 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
233 { INL, INL, INL, INL, INL, INL, INL, INL,
234 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
235 { INL, INL, INL, INL, INL, INL, INL, INL,
236 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
240 static enum shift_alg shift_alg_si[3][3][32] = {
243 /* 0 1 2 3 4 5 6 7 */
244 /* 8 9 10 11 12 13 14 15 */
245 /* 16 17 18 19 20 21 22 23 */
246 /* 24 25 26 27 28 29 30 31 */
247 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
248 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
249 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
250 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
251 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
252 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
253 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
254 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
255 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
256 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
257 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
258 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
262 /* 0 1 2 3 4 5 6 7 */
263 /* 8 9 10 11 12 13 14 15 */
264 /* 16 17 18 19 20 21 22 23 */
265 /* 24 25 26 27 28 29 30 31 */
266 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
267 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
268 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
269 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
270 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
271 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
272 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
273 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
274 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
275 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
276 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
277 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
281 /* 0 1 2 3 4 5 6 7 */
282 /* 8 9 10 11 12 13 14 15 */
283 /* 16 17 18 19 20 21 22 23 */
284 /* 24 25 26 27 28 29 30 31 */
285 { INL, INL, INL, INL, INL, INL, INL, INL,
286 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
287 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
288 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
289 { INL, INL, INL, INL, INL, INL, INL, INL,
290 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
291 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
292 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
293 { INL, INL, INL, INL, INL, INL, INL, INL,
294 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
295 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
296 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
312 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
314 static const struct default_options h8300_option_optimization_table[] =
316 /* Basic block reordering is only beneficial on targets with cache
317 and/or variable-cycle branches where (cycle count taken !=
318 cycle count not taken). */
319 { OPT_LEVELS_ALL, OPT_freorder_blocks, NULL, 0 },
320 { OPT_LEVELS_NONE, 0, NULL, 0 }
323 /* Initialize various cpu specific globals at start up. */
326 h8300_option_override (void)
328 static const char *const h8_push_ops[2] = { "push" , "push.l" };
329 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
330 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
334 cpu_type = (int) CPU_H8300;
335 h8_reg_names = names_big;
339 /* For this we treat the H8/300H and H8S the same. */
340 cpu_type = (int) CPU_H8300H;
341 h8_reg_names = names_extended;
343 h8_push_op = h8_push_ops[cpu_type];
344 h8_pop_op = h8_pop_ops[cpu_type];
345 h8_mov_op = h8_mov_ops[cpu_type];
347 if (!TARGET_H8300S && TARGET_MAC)
349 error ("-ms2600 is used without -ms");
350 target_flags |= MASK_H8300S_1;
353 if (TARGET_H8300 && TARGET_NORMAL_MODE)
355 error ("-mn is used without -mh or -ms");
356 target_flags ^= MASK_NORMAL_MODE;
359 /* Some of the shifts are optimized for speed by default.
360 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
361 If optimizing for size, change shift_alg for those shift to
366 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
367 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
368 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
369 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
371 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
372 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
374 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
375 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
378 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
379 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
381 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
382 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
384 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
385 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
386 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
387 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
390 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
393 /* Work out a value for MOVE_RATIO. */
396 /* Memory-memory moves are quite expensive without the
397 h8sx instructions. */
398 h8300_move_ratio = 3;
400 else if (flag_omit_frame_pointer)
402 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
403 sometimes be as short as two individual memory-to-memory moves,
404 but since they use all the call-saved registers, it seems better
405 to allow up to three moves here. */
406 h8300_move_ratio = 4;
408 else if (optimize_size)
410 /* In this case we don't use movmd sequences since they tend
411 to be longer than calls to memcpy(). Memory-to-memory
412 moves are cheaper than for !TARGET_H8300SX, so it makes
413 sense to have a slightly higher threshold. */
414 h8300_move_ratio = 4;
418 /* We use movmd sequences for some moves since it can be quicker
419 than calling memcpy(). The sequences will need to save and
420 restore er6 though, so bump up the cost. */
421 h8300_move_ratio = 6;
424 /* This target defaults to strict volatile bitfields. */
425 if (flag_strict_volatile_bitfields < 0)
426 flag_strict_volatile_bitfields = 1;
429 /* Return the byte register name for a register rtx X. B should be 0
430 if you want a lower byte register. B should be 1 if you want an
431 upper byte register. */
434 byte_reg (rtx x, int b)
436 static const char *const names_small[] = {
437 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
438 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
441 gcc_assert (REG_P (x));
443 return names_small[REGNO (x) * 2 + b];
446 /* REGNO must be saved/restored across calls if this macro is true. */
448 #define WORD_REG_USED(regno) \
450 /* No need to save registers if this function will not return. */ \
451 && ! TREE_THIS_VOLATILE (current_function_decl) \
452 && (h8300_saveall_function_p (current_function_decl) \
453 /* Save any call saved register that was used. */ \
454 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
455 /* Save the frame pointer if it was used. */ \
456 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
457 /* Save any register used in an interrupt handler. */ \
458 || (h8300_current_function_interrupt_function_p () \
459 && df_regs_ever_live_p (regno)) \
460 /* Save call clobbered registers in non-leaf interrupt \
462 || (h8300_current_function_interrupt_function_p () \
463 && call_used_regs[regno] \
464 && !current_function_is_leaf)))
466 /* We use this to wrap all emitted insns in the prologue. */
468 F (rtx x, bool set_it)
471 RTX_FRAME_RELATED_P (x) = 1;
475 /* Mark all the subexpressions of the PARALLEL rtx PAR as
476 frame-related. Return PAR.
478 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
479 PARALLEL rtx other than the first if they do not have the
480 FRAME_RELATED flag set on them. */
484 int len = XVECLEN (par, 0);
487 for (i = 0; i < len; i++)
488 F (XVECEXP (par, 0, i), true);
493 /* Output assembly language to FILE for the operation OP with operand size
494 SIZE to adjust the stack pointer. */
497 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
499 /* If the frame size is 0, we don't have anything to do. */
503 /* H8/300 cannot add/subtract a large constant with a single
504 instruction. If a temporary register is available, load the
505 constant to it and then do the addition. */
508 && !h8300_current_function_interrupt_function_p ()
509 && !(cfun->static_chain_decl != NULL && sign < 0))
511 rtx r3 = gen_rtx_REG (Pmode, 3);
512 F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
513 F (emit_insn (gen_addhi3 (stack_pointer_rtx,
514 stack_pointer_rtx, r3)), in_prologue);
518 /* The stack adjustment made here is further optimized by the
519 splitter. In case of H8/300, the splitter always splits the
520 addition emitted here to make the adjustment interrupt-safe.
521 FIXME: We don't always tag those, because we don't know what
522 the splitter will do. */
525 rtx x = emit_insn (gen_addhi3 (stack_pointer_rtx,
526 stack_pointer_rtx, GEN_INT (sign * size)));
531 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
532 stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
536 /* Round up frame size SIZE. */
539 round_frame_size (HOST_WIDE_INT size)
541 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
542 & -STACK_BOUNDARY / BITS_PER_UNIT);
545 /* Compute which registers to push/pop.
546 Return a bit vector of registers. */
549 compute_saved_regs (void)
551 unsigned int saved_regs = 0;
554 /* Construct a bit vector of registers to be pushed/popped. */
555 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
557 if (WORD_REG_USED (regno))
558 saved_regs |= 1 << regno;
561 /* Don't push/pop the frame pointer as it is treated separately. */
562 if (frame_pointer_needed)
563 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM);
568 /* Emit an insn to push register RN. */
573 rtx reg = gen_rtx_REG (word_mode, rn);
577 x = gen_push_h8300 (reg);
578 else if (!TARGET_NORMAL_MODE)
579 x = gen_push_h8300hs_advanced (reg);
581 x = gen_push_h8300hs_normal (reg);
582 x = F (emit_insn (x), true);
583 add_reg_note (x, REG_INC, stack_pointer_rtx);
586 /* Emit an insn to pop register RN. */
591 rtx reg = gen_rtx_REG (word_mode, rn);
595 x = gen_pop_h8300 (reg);
596 else if (!TARGET_NORMAL_MODE)
597 x = gen_pop_h8300hs_advanced (reg);
599 x = gen_pop_h8300hs_normal (reg);
601 add_reg_note (x, REG_INC, stack_pointer_rtx);
604 /* Emit an instruction to push or pop NREGS consecutive registers
605 starting at register REGNO. POP_P selects a pop rather than a
606 push and RETURN_P is true if the instruction should return.
608 It must be possible to do the requested operation in a single
609 instruction. If NREGS == 1 && !RETURN_P, use a normal push
610 or pop insn. Otherwise emit a parallel of the form:
613 [(return) ;; if RETURN_P
614 (save or restore REGNO)
615 (save or restore REGNO + 1)
617 (save or restore REGNO + NREGS - 1)
618 (set sp (plus sp (const_int adjust)))] */
621 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p)
627 /* See whether we can use a simple push or pop. */
628 if (!return_p && nregs == 1)
637 /* We need one element for the return insn, if present, one for each
638 register, and one for stack adjustment. */
639 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1);
640 sp = stack_pointer_rtx;
643 /* Add the return instruction. */
646 RTVEC_ELT (vec, i) = gen_rtx_RETURN (VOIDmode);
650 /* Add the register moves. */
651 for (j = 0; j < nregs; j++)
657 /* Register REGNO + NREGS - 1 is popped first. Before the
658 stack adjustment, its slot is at address @sp. */
659 lhs = gen_rtx_REG (SImode, regno + j);
660 rhs = gen_rtx_MEM (SImode, plus_constant (sp, (nregs - j - 1) * 4));
664 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
665 lhs = gen_rtx_MEM (SImode, plus_constant (sp, (j + 1) * -4));
666 rhs = gen_rtx_REG (SImode, regno + j);
668 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, lhs, rhs);
671 /* Add the stack adjustment. */
672 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4);
673 RTVEC_ELT (vec, i + j) = gen_rtx_SET (VOIDmode, sp,
674 gen_rtx_PLUS (Pmode, sp, offset));
676 x = gen_rtx_PARALLEL (VOIDmode, vec);
686 /* Return true if X has the value sp + OFFSET. */
689 h8300_stack_offset_p (rtx x, int offset)
692 return x == stack_pointer_rtx;
694 return (GET_CODE (x) == PLUS
695 && XEXP (x, 0) == stack_pointer_rtx
696 && GET_CODE (XEXP (x, 1)) == CONST_INT
697 && INTVAL (XEXP (x, 1)) == offset);
700 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
701 something that may be an ldm or stm instruction. If it fits
702 the required template, return the register it loads or stores,
705 LOAD_P is true if X should be a load, false if it should be a store.
706 NREGS is the number of registers that the whole instruction is expected
707 to load or store. INDEX is the index of the register that X should
708 load or store, relative to the lowest-numbered register. */
711 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
713 int regindex, memindex, offset;
716 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4;
718 memindex = 0, regindex = 1, offset = (index + 1) * -4;
720 if (GET_CODE (x) == SET
721 && GET_CODE (XEXP (x, regindex)) == REG
722 && GET_CODE (XEXP (x, memindex)) == MEM
723 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
724 return REGNO (XEXP (x, regindex));
729 /* Return true if the elements of VEC starting at FIRST describe an
730 ldm or stm instruction (LOAD_P says which). */
733 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first)
736 int nregs, i, regno, adjust;
738 /* There must be a stack adjustment, a register move, and at least one
739 other operation (a return or another register move). */
740 if (GET_NUM_ELEM (vec) < 3)
743 /* Get the range of registers to be pushed or popped. */
744 nregs = GET_NUM_ELEM (vec) - first - 1;
745 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs);
747 /* Check that the call to h8300_ldm_stm_regno succeeded and
748 that we're only dealing with GPRs. */
749 if (regno < 0 || regno + nregs > 8)
752 /* 2-register h8s instructions must start with an even-numbered register.
753 3- and 4-register instructions must start with er0 or er4. */
756 if ((regno & 1) != 0)
758 if (nregs > 2 && (regno & 3) != 0)
762 /* Check the other loads or stores. */
763 for (i = 1; i < nregs; i++)
764 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs)
768 /* Check the stack adjustment. */
769 last = RTVEC_ELT (vec, first + nregs);
770 adjust = (load_p ? nregs : -nregs) * 4;
771 return (GET_CODE (last) == SET
772 && SET_DEST (last) == stack_pointer_rtx
773 && h8300_stack_offset_p (SET_SRC (last), adjust));
776 /* This is what the stack looks like after the prolog of
777 a function with a frame has been set up:
783 <saved registers> <- sp
785 This is what the stack looks like after the prolog of
786 a function which doesn't have a frame:
791 <saved registers> <- sp
794 /* Generate RTL code for the function prologue. */
797 h8300_expand_prologue (void)
803 /* If the current function has the OS_Task attribute set, then
804 we have a naked prologue. */
805 if (h8300_os_task_function_p (current_function_decl))
808 if (h8300_monitor_function_p (current_function_decl))
809 /* My understanding of monitor functions is they act just like
810 interrupt functions, except the prologue must mask
812 emit_insn (gen_monitor_prologue ());
814 if (frame_pointer_needed)
817 push (HARD_FRAME_POINTER_REGNUM);
818 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), true);
821 /* Push the rest of the registers in ascending order. */
822 saved_regs = compute_saved_regs ();
823 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
826 if (saved_regs & (1 << regno))
830 /* See how many registers we can push at the same time. */
831 if ((!TARGET_H8300SX || (regno & 3) == 0)
832 && ((saved_regs >> regno) & 0x0f) == 0x0f)
835 else if ((!TARGET_H8300SX || (regno & 3) == 0)
836 && ((saved_regs >> regno) & 0x07) == 0x07)
839 else if ((!TARGET_H8300SX || (regno & 1) == 0)
840 && ((saved_regs >> regno) & 0x03) == 0x03)
844 h8300_push_pop (regno, n_regs, false, false);
848 /* Leave room for locals. */
849 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
852 /* Return nonzero if we can use "rts" for the function currently being
856 h8300_can_use_return_insn_p (void)
858 return (reload_completed
859 && !frame_pointer_needed
860 && get_frame_size () == 0
861 && compute_saved_regs () == 0);
864 /* Generate RTL code for the function epilogue. */
867 h8300_expand_epilogue (void)
872 HOST_WIDE_INT frame_size;
875 if (h8300_os_task_function_p (current_function_decl))
876 /* OS_Task epilogues are nearly naked -- they just have an
880 frame_size = round_frame_size (get_frame_size ());
883 /* Deallocate locals. */
884 h8300_emit_stack_adjustment (1, frame_size, false);
886 /* Pop the saved registers in descending order. */
887 saved_regs = compute_saved_regs ();
888 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
891 if (saved_regs & (1 << regno))
895 /* See how many registers we can pop at the same time. */
896 if ((TARGET_H8300SX || (regno & 3) == 3)
897 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f)
900 else if ((TARGET_H8300SX || (regno & 3) == 2)
901 && ((saved_regs << 2 >> regno) & 0x07) == 0x07)
904 else if ((TARGET_H8300SX || (regno & 1) == 1)
905 && ((saved_regs << 1 >> regno) & 0x03) == 0x03)
909 /* See if this pop would be the last insn before the return.
910 If so, use rte/l or rts/l instead of pop or ldm.l. */
912 && !frame_pointer_needed
914 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0)
917 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p);
921 /* Pop frame pointer if we had one. */
922 if (frame_pointer_needed)
926 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p);
930 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
933 /* Return nonzero if the current function is an interrupt
937 h8300_current_function_interrupt_function_p (void)
939 return (h8300_interrupt_function_p (current_function_decl)
940 || h8300_monitor_function_p (current_function_decl));
943 /* Output assembly code for the start of the file. */
946 h8300_file_start (void)
948 default_file_start ();
951 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file);
952 else if (TARGET_H8300SX)
953 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file);
954 else if (TARGET_H8300S)
955 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file);
958 /* Output assembly language code for the end of file. */
961 h8300_file_end (void)
963 fputs ("\t.end\n", asm_out_file);
966 /* Split an add of a small constant into two adds/subs insns.
968 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
969 instead of adds/subs. */
972 split_adds_subs (enum machine_mode mode, rtx *operands)
974 HOST_WIDE_INT val = INTVAL (operands[1]);
975 rtx reg = operands[0];
976 HOST_WIDE_INT sign = 1;
977 HOST_WIDE_INT amount;
978 rtx (*gen_add) (rtx, rtx, rtx);
980 /* Force VAL to be positive so that we do not have to consider the
991 gen_add = gen_addhi3;
995 gen_add = gen_addsi3;
1002 /* Try different amounts in descending order. */
1003 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
1007 for (; val >= amount; val -= amount)
1008 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
1014 /* Handle machine specific pragmas for compatibility with existing
1015 compilers for the H8/300.
1017 pragma saveall generates prologue/epilogue code which saves and
1018 restores all the registers on function entry.
1020 pragma interrupt saves and restores all registers, and exits with
1021 an rte instruction rather than an rts. A pointer to a function
1022 with this attribute may be safely used in an interrupt vector. */
1025 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1027 pragma_interrupt = 1;
1031 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED)
1036 /* If the next function argument with MODE and TYPE is to be passed in
1037 a register, return a reg RTX for the hard register in which to pass
1038 the argument. CUM represents the state after the last argument.
1039 If the argument is to be pushed, NULL_RTX is returned.
1041 On the H8/300 all normal args are pushed, unless -mquickcall in which
1042 case the first 3 arguments are passed in registers. */
1045 h8300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1046 const_tree type, bool named)
1048 static const char *const hand_list[] = {
1067 rtx result = NULL_RTX;
1071 /* Never pass unnamed arguments in registers. */
1075 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1076 if (TARGET_QUICKCALL)
1079 /* If calling hand written assembler, use 4 regs of args. */
1082 const char * const *p;
1084 fname = XSTR (cum->libcall, 0);
1086 /* See if this libcall is one of the hand coded ones. */
1087 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1098 if (mode == BLKmode)
1099 size = int_size_in_bytes (type);
1101 size = GET_MODE_SIZE (mode);
1103 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1104 && cum->nbytes / UNITS_PER_WORD <= 3)
1105 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1111 /* Update the data in CUM to advance over an argument
1112 of mode MODE and data type TYPE.
1113 (TYPE is null for libcalls where that information may not be available.) */
1116 h8300_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1117 const_tree type, bool named ATTRIBUTE_UNUSED)
1119 cum->nbytes += (mode != BLKmode
1120 ? (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD
1121 : (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD);
1125 /* Implements TARGET_REGISTER_MOVE_COST.
1127 Any SI register-to-register move may need to be reloaded,
1128 so inmplement h8300_register_move_cost to return > 2 so that reload never
1132 h8300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1133 reg_class_t from, reg_class_t to)
1135 if (from == MAC_REGS || to == MAC_REG)
1141 /* Compute the cost of an and insn. */
1144 h8300_and_costs (rtx x)
1148 if (GET_MODE (x) == QImode)
1151 if (GET_MODE (x) != HImode
1152 && GET_MODE (x) != SImode)
1156 operands[1] = XEXP (x, 0);
1157 operands[2] = XEXP (x, 1);
1159 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1162 /* Compute the cost of a shift insn. */
1165 h8300_shift_costs (rtx x)
1169 if (GET_MODE (x) != QImode
1170 && GET_MODE (x) != HImode
1171 && GET_MODE (x) != SImode)
1176 operands[2] = XEXP (x, 1);
1178 return compute_a_shift_length (NULL, operands) / 2;
1181 /* Worker function for TARGET_RTX_COSTS. */
1184 h8300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
1186 if (TARGET_H8300SX && outer_code == MEM)
1188 /* Estimate the number of execution states needed to calculate
1190 if (register_operand (x, VOIDmode)
1191 || GET_CODE (x) == POST_INC
1192 || GET_CODE (x) == POST_DEC
1196 *total = COSTS_N_INSNS (1);
1204 HOST_WIDE_INT n = INTVAL (x);
1208 /* Constant operands need the same number of processor
1209 states as register operands. Although we could try to
1210 use a size-based cost for !speed, the lack of
1211 of a mode makes the results very unpredictable. */
1215 if (-4 <= n || n <= 4)
1226 *total = 0 + (outer_code == SET);
1230 if (TARGET_H8300H || TARGET_H8300S)
1231 *total = 0 + (outer_code == SET);
1246 /* See comment for CONST_INT. */
1258 if (XEXP (x, 1) == const0_rtx)
1263 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode)
1264 || !h8300_src_operand (XEXP (x, 1), VOIDmode))
1266 *total = COSTS_N_INSNS (h8300_and_costs (x));
1269 /* We say that MOD and DIV are so expensive because otherwise we'll
1270 generate some really horrible code for division of a power of two. */
1276 switch (GET_MODE (x))
1280 *total = COSTS_N_INSNS (!speed ? 4 : 10);
1284 *total = COSTS_N_INSNS (!speed ? 4 : 18);
1290 *total = COSTS_N_INSNS (12);
1295 switch (GET_MODE (x))
1299 *total = COSTS_N_INSNS (2);
1303 *total = COSTS_N_INSNS (5);
1309 *total = COSTS_N_INSNS (4);
1315 if (h8sx_binary_shift_operator (x, VOIDmode))
1317 *total = COSTS_N_INSNS (2);
1320 else if (h8sx_unary_shift_operator (x, VOIDmode))
1322 *total = COSTS_N_INSNS (1);
1325 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1330 if (GET_MODE (x) == HImode)
1337 *total = COSTS_N_INSNS (1);
1342 /* Documentation for the machine specific operand escapes:
1344 'E' like s but negative.
1345 'F' like t but negative.
1346 'G' constant just the negative
1347 'R' print operand as a byte:8 address if appropriate, else fall back to
1349 'S' print operand as a long word
1350 'T' print operand as a word
1351 'V' find the set bit, and print its number.
1352 'W' find the clear bit, and print its number.
1353 'X' print operand as a byte
1354 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1355 If this operand isn't a register, fall back to 'R' handling.
1357 'c' print the opcode corresponding to rtl
1358 'e' first word of 32-bit value - if reg, then least reg. if mem
1359 then least. if const then most sig word
1360 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1361 then +2. if const then least sig word
1362 'j' print operand as condition code.
1363 'k' print operand as reverse condition code.
1364 'm' convert an integer operand to a size suffix (.b, .w or .l)
1365 'o' print an integer without a leading '#'
1366 's' print as low byte of 16-bit value
1367 't' print as high byte of 16-bit value
1368 'w' print as low byte of 32-bit value
1369 'x' print as 2nd byte of 32-bit value
1370 'y' print as 3rd byte of 32-bit value
1371 'z' print as msb of 32-bit value
1374 /* Return assembly language string which identifies a comparison type. */
1377 cond_string (enum rtx_code code)
1406 /* Print operand X using operand code CODE to assembly language output file
1410 h8300_print_operand (FILE *file, rtx x, int code)
1412 /* This is used for communication between codes V,W,Z and Y. */
1418 switch (GET_CODE (x))
1421 fprintf (file, "%sl", names_big[REGNO (x)]);
1424 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1431 switch (GET_CODE (x))
1434 fprintf (file, "%sh", names_big[REGNO (x)]);
1437 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1444 gcc_assert (GET_CODE (x) == CONST_INT);
1445 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1448 if (GET_CODE (x) == REG)
1449 fprintf (file, "%s", names_extended[REGNO (x)]);
1454 if (GET_CODE (x) == REG)
1455 fprintf (file, "%s", names_big[REGNO (x)]);
1460 bitint = (INTVAL (x) & 0xffff);
1461 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1)
1462 bitint = exact_log2 (bitint & 0xff);
1464 bitint = exact_log2 ((bitint >> 8) & 0xff);
1465 gcc_assert (bitint >= 0);
1466 fprintf (file, "#%d", bitint);
1469 bitint = ((~INTVAL (x)) & 0xffff);
1470 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 )
1471 bitint = exact_log2 (bitint & 0xff);
1473 bitint = (exact_log2 ((bitint >> 8) & 0xff));
1474 gcc_assert (bitint >= 0);
1475 fprintf (file, "#%d", bitint);
1479 if (GET_CODE (x) == REG)
1480 fprintf (file, "%s", byte_reg (x, 0));
1485 gcc_assert (bitint >= 0);
1486 if (GET_CODE (x) == REG)
1487 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1489 h8300_print_operand (file, x, 'R');
1493 bitint = INTVAL (x);
1494 fprintf (file, "#%d", bitint & 7);
1497 switch (GET_CODE (x))
1500 fprintf (file, "or");
1503 fprintf (file, "xor");
1506 fprintf (file, "and");
1513 switch (GET_CODE (x))
1517 fprintf (file, "%s", names_big[REGNO (x)]);
1519 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1522 h8300_print_operand (file, x, 0);
1525 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1531 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1532 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1533 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1542 switch (GET_CODE (x))
1546 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1548 fprintf (file, "%s", names_big[REGNO (x)]);
1551 x = adjust_address (x, HImode, 2);
1552 h8300_print_operand (file, x, 0);
1555 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1561 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1562 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1563 fprintf (file, "#%ld", (val & 0xffff));
1571 fputs (cond_string (GET_CODE (x)), file);
1574 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1577 gcc_assert (GET_CODE (x) == CONST_INT);
1597 h8300_print_operand_address (file, x);
1600 if (GET_CODE (x) == CONST_INT)
1601 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1603 fprintf (file, "%s", byte_reg (x, 0));
1606 if (GET_CODE (x) == CONST_INT)
1607 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1609 fprintf (file, "%s", byte_reg (x, 1));
1612 if (GET_CODE (x) == CONST_INT)
1613 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1615 fprintf (file, "%s",
1616 byte_reg (x, TARGET_H8300 ? 2 : 0));
1619 if (GET_CODE (x) == CONST_INT)
1620 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1622 fprintf (file, "%s",
1623 byte_reg (x, TARGET_H8300 ? 3 : 1));
1626 if (GET_CODE (x) == CONST_INT)
1627 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1629 fprintf (file, "%s", byte_reg (x, 0));
1632 if (GET_CODE (x) == CONST_INT)
1633 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1635 fprintf (file, "%s", byte_reg (x, 1));
1640 switch (GET_CODE (x))
1643 switch (GET_MODE (x))
1646 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1647 fprintf (file, "%s", byte_reg (x, 0));
1648 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1649 fprintf (file, "%s", names_big[REGNO (x)]);
1653 fprintf (file, "%s", names_big[REGNO (x)]);
1657 fprintf (file, "%s", names_extended[REGNO (x)]);
1666 rtx addr = XEXP (x, 0);
1668 fprintf (file, "@");
1669 output_address (addr);
1671 /* Add a length suffix to constant addresses. Although this
1672 is often unnecessary, it helps to avoid ambiguity in the
1673 syntax of mova. If we wrote an insn like:
1675 mova/w.l @(1,@foo.b),er0
1677 then .b would be considered part of the symbol name.
1678 Adding a length after foo will avoid this. */
1679 if (CONSTANT_P (addr))
1683 /* Used for mov.b and bit operations. */
1684 if (h8300_eightbit_constant_address_p (addr))
1686 fprintf (file, ":8");
1690 /* Fall through. We should not get here if we are
1691 processing bit operations on H8/300 or H8/300H
1692 because 'U' constraint does not allow bit
1693 operations on the tiny area on these machines. */
1698 if (h8300_constant_length (addr) == 2)
1699 fprintf (file, ":16");
1701 fprintf (file, ":32");
1713 fprintf (file, "#");
1714 h8300_print_operand_address (file, x);
1720 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1721 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1722 fprintf (file, "#%ld", val);
1731 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1734 h8300_print_operand_punct_valid_p (unsigned char code)
1736 return (code == '#');
1739 /* Output assembly language output for the address ADDR to FILE. */
1742 h8300_print_operand_address (FILE *file, rtx addr)
1747 switch (GET_CODE (addr))
1750 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1754 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1758 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1762 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1766 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]);
1770 fprintf (file, "(");
1772 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
1773 if (GET_CODE (index) == REG)
1776 h8300_print_operand_address (file, XEXP (addr, 1));
1777 fprintf (file, ",");
1781 h8300_print_operand_address (file, index);
1785 h8300_print_operand (file, index, 'X');
1790 h8300_print_operand (file, index, 'T');
1795 h8300_print_operand (file, index, 'S');
1799 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1804 h8300_print_operand_address (file, XEXP (addr, 0));
1805 fprintf (file, "+");
1806 h8300_print_operand_address (file, XEXP (addr, 1));
1808 fprintf (file, ")");
1813 /* Since the H8/300 only has 16-bit pointers, negative values are also
1814 those >= 32768. This happens for example with pointer minus a
1815 constant. We don't want to turn (char *p - 2) into
1816 (char *p + 65534) because loop unrolling can build upon this
1817 (IE: char *p + 131068). */
1818 int n = INTVAL (addr);
1820 n = (int) (short) n;
1821 fprintf (file, "%d", n);
1826 output_addr_const (file, addr);
1831 /* Output all insn addresses and their sizes into the assembly language
1832 output file. This is helpful for debugging whether the length attributes
1833 in the md file are correct. This is not meant to be a user selectable
1837 final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
1838 int num_operands ATTRIBUTE_UNUSED)
1840 /* This holds the last insn address. */
1841 static int last_insn_address = 0;
1843 const int uid = INSN_UID (insn);
1845 if (TARGET_ADDRESSES)
1847 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1848 INSN_ADDRESSES (uid) - last_insn_address);
1849 last_insn_address = INSN_ADDRESSES (uid);
1853 /* Prepare for an SI sized move. */
1856 h8300_expand_movsi (rtx operands[])
1858 rtx src = operands[1];
1859 rtx dst = operands[0];
1860 if (!reload_in_progress && !reload_completed)
1862 if (!register_operand (dst, GET_MODE (dst)))
1864 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1865 emit_move_insn (tmp, src);
1872 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1873 Frame pointer elimination is automatically handled.
1875 For the h8300, if frame pointer elimination is being done, we would like to
1876 convert ap and rp into sp, not fp.
1878 All other eliminations are valid. */
1881 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
1883 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
1886 /* Conditionally modify register usage based on target flags. */
1889 h8300_conditional_register_usage (void)
1892 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1;
1895 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1896 Define the offset between two registers, one to be eliminated, and
1897 the other its replacement, at the start of a routine. */
1900 h8300_initial_elimination_offset (int from, int to)
1902 /* The number of bytes that the return address takes on the stack. */
1903 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1905 /* The number of bytes that the saved frame pointer takes on the stack. */
1906 int fp_size = frame_pointer_needed * UNITS_PER_WORD;
1908 /* The number of bytes that the saved registers, excluding the frame
1909 pointer, take on the stack. */
1910 int saved_regs_size = 0;
1912 /* The number of bytes that the locals takes on the stack. */
1913 int frame_size = round_frame_size (get_frame_size ());
1917 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++)
1918 if (WORD_REG_USED (regno))
1919 saved_regs_size += UNITS_PER_WORD;
1921 /* Adjust saved_regs_size because the above loop took the frame
1922 pointer int account. */
1923 saved_regs_size -= fp_size;
1927 case HARD_FRAME_POINTER_REGNUM:
1930 case ARG_POINTER_REGNUM:
1931 return pc_size + fp_size;
1932 case RETURN_ADDRESS_POINTER_REGNUM:
1934 case FRAME_POINTER_REGNUM:
1935 return -saved_regs_size;
1940 case STACK_POINTER_REGNUM:
1943 case ARG_POINTER_REGNUM:
1944 return pc_size + saved_regs_size + frame_size;
1945 case RETURN_ADDRESS_POINTER_REGNUM:
1946 return saved_regs_size + frame_size;
1947 case FRAME_POINTER_REGNUM:
1959 /* Worker function for RETURN_ADDR_RTX. */
1962 h8300_return_addr_rtx (int count, rtx frame)
1967 ret = gen_rtx_MEM (Pmode,
1968 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1969 else if (flag_omit_frame_pointer)
1972 ret = gen_rtx_MEM (Pmode,
1973 memory_address (Pmode,
1974 plus_constant (frame, UNITS_PER_WORD)));
1975 set_mem_alias_set (ret, get_frame_alias_set ());
1979 /* Update the condition code from the insn. */
1982 notice_update_cc (rtx body, rtx insn)
1986 switch (get_attr_cc (insn))
1989 /* Insn does not affect CC at all. */
1993 /* Insn does not change CC, but the 0'th operand has been changed. */
1994 if (cc_status.value1 != 0
1995 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1996 cc_status.value1 = 0;
1997 if (cc_status.value2 != 0
1998 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1999 cc_status.value2 = 0;
2003 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2004 The V flag is unusable. The C flag may or may not be known but
2005 that's ok because alter_cond will change tests to use EQ/NE. */
2007 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
2008 set = single_set (insn);
2009 cc_status.value1 = SET_SRC (set);
2010 if (SET_DEST (set) != cc0_rtx)
2011 cc_status.value2 = SET_DEST (set);
2015 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2016 The C flag may or may not be known but that's ok because
2017 alter_cond will change tests to use EQ/NE. */
2019 cc_status.flags |= CC_NO_CARRY;
2020 set = single_set (insn);
2021 cc_status.value1 = SET_SRC (set);
2022 if (SET_DEST (set) != cc0_rtx)
2024 /* If the destination is STRICT_LOW_PART, strip off
2026 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
2027 cc_status.value2 = XEXP (SET_DEST (set), 0);
2029 cc_status.value2 = SET_DEST (set);
2034 /* The insn is a compare instruction. */
2036 cc_status.value1 = SET_SRC (body);
2040 /* Insn doesn't leave CC in a usable state. */
2046 /* Given that X occurs in an address of the form (plus X constant),
2047 return the part of X that is expected to be a register. There are
2048 four kinds of addressing mode to recognize:
2055 If SIZE is nonnull, and the address is one of the last three forms,
2056 set *SIZE to the index multiplication factor. Set it to 0 for
2057 plain @(dd,Rn) addresses.
2059 MODE is the mode of the value being accessed. It can be VOIDmode
2060 if the address is known to be valid, but its mode is unknown. */
2063 h8300_get_index (rtx x, enum machine_mode mode, int *size)
2070 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode));
2073 && (mode == VOIDmode
2074 || GET_MODE_CLASS (mode) == MODE_INT
2075 || GET_MODE_CLASS (mode) == MODE_FLOAT))
2077 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND)
2079 /* When accessing byte-sized values, the index can be
2080 a zero-extended QImode or HImode register. */
2081 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0)));
2086 /* We're looking for addresses of the form:
2089 or (mult (zero_extend X) I)
2091 where I is the size of the operand being accessed.
2092 The canonical form of the second expression is:
2094 (and (mult (subreg X) I) J)
2096 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2099 if (GET_CODE (x) == AND
2100 && GET_CODE (XEXP (x, 1)) == CONST_INT
2102 || INTVAL (XEXP (x, 1)) == 0xff * factor
2103 || INTVAL (XEXP (x, 1)) == 0xffff * factor))
2105 index = XEXP (x, 0);
2106 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1);
2114 if (GET_CODE (index) == MULT
2115 && GET_CODE (XEXP (index, 1)) == CONST_INT
2116 && (factor == 0 || factor == INTVAL (XEXP (index, 1))))
2117 return XEXP (index, 0);
2124 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2126 On the H8/300, the predecrement and postincrement address depend thus
2127 (the amount of decrement or increment being the length of the operand). */
2130 h8300_mode_dependent_address_p (const_rtx addr)
2132 if (GET_CODE (addr) == PLUS
2133 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0))
2139 static const h8300_length_table addb_length_table =
2141 /* #xx Rs @aa @Rs @xx */
2142 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2143 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2144 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2145 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2148 static const h8300_length_table addw_length_table =
2150 /* #xx Rs @aa @Rs @xx */
2151 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2152 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2153 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2154 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2157 static const h8300_length_table addl_length_table =
2159 /* #xx Rs @aa @Rs @xx */
2160 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2161 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2162 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2163 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2166 #define logicb_length_table addb_length_table
2167 #define logicw_length_table addw_length_table
2169 static const h8300_length_table logicl_length_table =
2171 /* #xx Rs @aa @Rs @xx */
2172 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2173 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2174 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2175 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2178 static const h8300_length_table movb_length_table =
2180 /* #xx Rs @aa @Rs @xx */
2181 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2182 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2183 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2184 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2187 #define movw_length_table movb_length_table
2189 static const h8300_length_table movl_length_table =
2191 /* #xx Rs @aa @Rs @xx */
2192 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2193 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2194 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2195 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2198 /* Return the size of the given address or displacement constant. */
2201 h8300_constant_length (rtx constant)
2203 /* Check for (@d:16,Reg). */
2204 if (GET_CODE (constant) == CONST_INT
2205 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
2208 /* Check for (@d:16,Reg) in cases where the displacement is
2209 an absolute address. */
2210 if (Pmode == HImode || h8300_tiny_constant_address_p (constant))
2216 /* Return the size of a displacement field in address ADDR, which should
2217 have the form (plus X constant). SIZE is the number of bytes being
2221 h8300_displacement_length (rtx addr, int size)
2225 offset = XEXP (addr, 1);
2227 /* Check for @(d:2,Reg). */
2228 if (register_operand (XEXP (addr, 0), VOIDmode)
2229 && GET_CODE (offset) == CONST_INT
2230 && (INTVAL (offset) == size
2231 || INTVAL (offset) == size * 2
2232 || INTVAL (offset) == size * 3))
2235 return h8300_constant_length (offset);
2238 /* Store the class of operand OP in *OPCLASS and return the length of any
2239 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2240 can be null if only the length is needed. */
2243 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
2245 enum h8300_operand_class dummy;
2250 if (CONSTANT_P (op))
2252 *opclass = H8OP_IMMEDIATE;
2254 /* Byte-sized immediates are stored in the opcode fields. */
2258 /* If this is a 32-bit instruction, see whether the constant
2259 will fit into a 16-bit immediate field. */
2262 && GET_CODE (op) == CONST_INT
2263 && IN_RANGE (INTVAL (op), 0, 0xffff))
2268 else if (GET_CODE (op) == MEM)
2271 if (CONSTANT_P (op))
2273 *opclass = H8OP_MEM_ABSOLUTE;
2274 return h8300_constant_length (op);
2276 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1)))
2278 *opclass = H8OP_MEM_COMPLEX;
2279 return h8300_displacement_length (op, size);
2281 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC)
2283 *opclass = H8OP_MEM_COMPLEX;
2286 else if (register_operand (op, VOIDmode))
2288 *opclass = H8OP_MEM_BASE;
2292 gcc_assert (register_operand (op, VOIDmode));
2293 *opclass = H8OP_REGISTER;
2297 /* Return the length of the instruction described by TABLE given that
2298 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2299 and OP2 must be an h8300_src_operand. */
2302 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table)
2304 enum h8300_operand_class op1_class, op2_class;
2305 unsigned int size, immediate_length;
2307 size = GET_MODE_SIZE (GET_MODE (op1));
2308 immediate_length = (h8300_classify_operand (op1, size, &op1_class)
2309 + h8300_classify_operand (op2, size, &op2_class));
2310 return immediate_length + (*table)[op1_class - 1][op2_class];
2313 /* Return the length of a unary instruction such as neg or not given that
2314 its operand is OP. */
2317 h8300_unary_length (rtx op)
2319 enum h8300_operand_class opclass;
2320 unsigned int size, operand_length;
2322 size = GET_MODE_SIZE (GET_MODE (op));
2323 operand_length = h8300_classify_operand (op, size, &opclass);
2330 return (size == 4 ? 6 : 4);
2332 case H8OP_MEM_ABSOLUTE:
2333 return operand_length + (size == 4 ? 6 : 4);
2335 case H8OP_MEM_COMPLEX:
2336 return operand_length + 6;
2343 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2346 h8300_short_immediate_length (rtx op)
2348 enum h8300_operand_class opclass;
2349 unsigned int size, operand_length;
2351 size = GET_MODE_SIZE (GET_MODE (op));
2352 operand_length = h8300_classify_operand (op, size, &opclass);
2360 case H8OP_MEM_ABSOLUTE:
2361 case H8OP_MEM_COMPLEX:
2362 return 4 + operand_length;
2369 /* Likewise bitfield load and store instructions. */
2372 h8300_bitfield_length (rtx op, rtx op2)
2374 enum h8300_operand_class opclass;
2375 unsigned int size, operand_length;
2377 if (GET_CODE (op) == REG)
2379 gcc_assert (GET_CODE (op) != REG);
2381 size = GET_MODE_SIZE (GET_MODE (op));
2382 operand_length = h8300_classify_operand (op, size, &opclass);
2387 case H8OP_MEM_ABSOLUTE:
2388 case H8OP_MEM_COMPLEX:
2389 return 4 + operand_length;
2396 /* Calculate the length of general binary instruction INSN using TABLE. */
2399 h8300_binary_length (rtx insn, const h8300_length_table *table)
2403 set = single_set (insn);
2406 if (BINARY_P (SET_SRC (set)))
2407 return h8300_length_from_table (XEXP (SET_SRC (set), 0),
2408 XEXP (SET_SRC (set), 1), table);
2411 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY);
2412 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0),
2413 XEXP (XEXP (SET_SRC (set), 1), 1),
2418 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2419 memory reference and either (1) it has the form @(d:16,Rn) or
2420 (2) its address has the code given by INC_CODE. */
2423 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
2428 if (GET_CODE (op) != MEM)
2431 addr = XEXP (op, 0);
2432 size = GET_MODE_SIZE (GET_MODE (op));
2433 if (size != 1 && size != 2)
2436 return (GET_CODE (addr) == inc_code
2437 || (GET_CODE (addr) == PLUS
2438 && GET_CODE (XEXP (addr, 0)) == REG
2439 && h8300_displacement_length (addr, size) == 2));
2442 /* Calculate the length of move instruction INSN using the given length
2443 table. Although the tables are correct for most cases, there is some
2444 irregularity in the length of mov.b and mov.w. The following forms:
2451 are two bytes shorter than most other "mov Rs, @complex" or
2452 "mov @complex,Rd" combinations. */
2455 h8300_move_length (rtx *operands, const h8300_length_table *table)
2459 size = h8300_length_from_table (operands[0], operands[1], table);
2460 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC))
2462 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC))
2467 /* Return the length of a mova instruction with the given operands.
2468 DEST is the register destination, SRC is the source address and
2469 OFFSET is the 16-bit or 32-bit displacement. */
2472 h8300_mova_length (rtx dest, rtx src, rtx offset)
2477 + h8300_constant_length (offset)
2478 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0));
2479 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest))
2484 /* Compute the length of INSN based on its length_table attribute.
2485 OPERANDS is the array of its operands. */
2488 h8300_insn_length_from_table (rtx insn, rtx * operands)
2490 switch (get_attr_length_table (insn))
2492 case LENGTH_TABLE_NONE:
2495 case LENGTH_TABLE_ADDB:
2496 return h8300_binary_length (insn, &addb_length_table);
2498 case LENGTH_TABLE_ADDW:
2499 return h8300_binary_length (insn, &addw_length_table);
2501 case LENGTH_TABLE_ADDL:
2502 return h8300_binary_length (insn, &addl_length_table);
2504 case LENGTH_TABLE_LOGICB:
2505 return h8300_binary_length (insn, &logicb_length_table);
2507 case LENGTH_TABLE_MOVB:
2508 return h8300_move_length (operands, &movb_length_table);
2510 case LENGTH_TABLE_MOVW:
2511 return h8300_move_length (operands, &movw_length_table);
2513 case LENGTH_TABLE_MOVL:
2514 return h8300_move_length (operands, &movl_length_table);
2516 case LENGTH_TABLE_MOVA:
2517 return h8300_mova_length (operands[0], operands[1], operands[2]);
2519 case LENGTH_TABLE_MOVA_ZERO:
2520 return h8300_mova_length (operands[0], operands[1], const0_rtx);
2522 case LENGTH_TABLE_UNARY:
2523 return h8300_unary_length (operands[0]);
2525 case LENGTH_TABLE_MOV_IMM4:
2526 return 2 + h8300_classify_operand (operands[0], 0, 0);
2528 case LENGTH_TABLE_SHORT_IMMEDIATE:
2529 return h8300_short_immediate_length (operands[0]);
2531 case LENGTH_TABLE_BITFIELD:
2532 return h8300_bitfield_length (operands[0], operands[1]);
2534 case LENGTH_TABLE_BITBRANCH:
2535 return h8300_bitfield_length (operands[1], operands[2]) - 2;
2542 /* Return true if LHS and RHS are memory references that can be mapped
2543 to the same h8sx assembly operand. LHS appears as the destination of
2544 an instruction and RHS appears as a source.
2546 Three cases are allowed:
2548 - RHS is @+Rn or @-Rn, LHS is @Rn
2549 - RHS is @Rn, LHS is @Rn+ or @Rn-
2550 - RHS and LHS have the same address and neither has side effects. */
2553 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
2555 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
2557 rhs = XEXP (rhs, 0);
2558 lhs = XEXP (lhs, 0);
2560 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC)
2561 return rtx_equal_p (XEXP (rhs, 0), lhs);
2563 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC)
2564 return rtx_equal_p (rhs, XEXP (lhs, 0));
2566 if (rtx_equal_p (rhs, lhs))
2572 /* Return true if OPERANDS[1] can be mapped to the same assembly
2573 operand as OPERANDS[0]. */
2576 h8300_operands_match_p (rtx *operands)
2578 if (register_operand (operands[0], VOIDmode)
2579 && register_operand (operands[1], VOIDmode))
2582 if (h8sx_mergeable_memrefs_p (operands[0], operands[1]))
2588 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2589 region DEST. The two regions do not overlap and have the common
2590 alignment given by ALIGNMENT. Return true on success.
2592 Using movmd for variable-length moves seems to involve some
2593 complex trade-offs. For instance:
2595 - Preparing for a movmd instruction is similar to preparing
2596 for a memcpy. The main difference is that the arguments
2597 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2599 - Since movmd clobbers the frame pointer, we need to save
2600 and restore it somehow when frame_pointer_needed. This can
2601 sometimes make movmd sequences longer than calls to memcpy().
2603 - The counter register is 16 bits, so the instruction is only
2604 suitable for variable-length moves when sizeof (size_t) == 2.
2605 That's only true in normal mode.
2607 - We will often lack static alignment information. Falling back
2608 on movmd.b would likely be slower than calling memcpy(), at least
2611 This function therefore only uses movmd when the length is a
2612 known constant, and only then if -fomit-frame-pointer is in
2613 effect or if we're not optimizing for size.
2615 At the moment the function uses movmd for all in-range constants,
2616 but it might be better to fall back on memcpy() for large moves
2617 if ALIGNMENT == 1. */
2620 h8sx_emit_movmd (rtx dest, rtx src, rtx length,
2621 HOST_WIDE_INT alignment)
2623 if (!flag_omit_frame_pointer && optimize_size)
2626 if (GET_CODE (length) == CONST_INT)
2628 rtx dest_reg, src_reg, first_dest, first_src;
2632 /* Use movmd.l if the alignment allows it, otherwise fall back
2634 factor = (alignment >= 2 ? 4 : 1);
2636 /* Make sure the length is within range. We can handle counter
2637 values up to 65536, although HImode truncation will make
2638 the count appear negative in rtl dumps. */
2639 n = INTVAL (length);
2640 if (n <= 0 || n / factor > 65536)
2643 /* Create temporary registers for the source and destination
2644 pointers. Initialize them to the start of each region. */
2645 dest_reg = copy_addr_to_reg (XEXP (dest, 0));
2646 src_reg = copy_addr_to_reg (XEXP (src, 0));
2648 /* Create references to the movmd source and destination blocks. */
2649 first_dest = replace_equiv_address (dest, dest_reg);
2650 first_src = replace_equiv_address (src, src_reg);
2652 set_mem_size (first_dest, GEN_INT (n & -factor));
2653 set_mem_size (first_src, GEN_INT (n & -factor));
2655 length = copy_to_mode_reg (HImode, gen_int_mode (n / factor, HImode));
2656 emit_insn (gen_movmd (first_dest, first_src, length, GEN_INT (factor)));
2658 if ((n & -factor) != n)
2660 /* Move SRC and DEST past the region we just copied.
2661 This is done to update the memory attributes. */
2662 dest = adjust_address (dest, BLKmode, n & -factor);
2663 src = adjust_address (src, BLKmode, n & -factor);
2665 /* Replace the addresses with the source and destination
2666 registers, which movmd has left with the right values. */
2667 dest = replace_equiv_address (dest, dest_reg);
2668 src = replace_equiv_address (src, src_reg);
2670 /* Mop up the left-over bytes. */
2672 emit_move_insn (adjust_address (dest, HImode, 0),
2673 adjust_address (src, HImode, 0));
2675 emit_move_insn (adjust_address (dest, QImode, n & 2),
2676 adjust_address (src, QImode, n & 2));
2683 /* Move ADDR into er6 after pushing its old value onto the stack. */
2686 h8300_swap_into_er6 (rtx addr)
2688 push (HARD_FRAME_POINTER_REGNUM);
2689 emit_move_insn (hard_frame_pointer_rtx, addr);
2690 if (REGNO (addr) == SP_REG)
2691 emit_move_insn (hard_frame_pointer_rtx,
2692 plus_constant (hard_frame_pointer_rtx,
2693 GET_MODE_SIZE (word_mode)));
2696 /* Move the current value of er6 into ADDR and pop its old value
2700 h8300_swap_out_of_er6 (rtx addr)
2702 if (REGNO (addr) != SP_REG)
2703 emit_move_insn (addr, hard_frame_pointer_rtx);
2704 pop (HARD_FRAME_POINTER_REGNUM);
2707 /* Return the length of mov instruction. */
2710 compute_mov_length (rtx *operands)
2712 /* If the mov instruction involves a memory operand, we compute the
2713 length, assuming the largest addressing mode is used, and then
2714 adjust later in the function. Otherwise, we compute and return
2715 the exact length in one step. */
2716 enum machine_mode mode = GET_MODE (operands[0]);
2717 rtx dest = operands[0];
2718 rtx src = operands[1];
2721 if (GET_CODE (src) == MEM)
2722 addr = XEXP (src, 0);
2723 else if (GET_CODE (dest) == MEM)
2724 addr = XEXP (dest, 0);
2730 unsigned int base_length;
2735 if (addr == NULL_RTX)
2738 /* The eightbit addressing is available only in QImode, so
2739 go ahead and take care of it. */
2740 if (h8300_eightbit_constant_address_p (addr))
2747 if (addr == NULL_RTX)
2752 if (src == const0_rtx)
2762 if (addr == NULL_RTX)
2767 if (GET_CODE (src) == CONST_INT)
2769 if (src == const0_rtx)
2772 if ((INTVAL (src) & 0xffff) == 0)
2775 if ((INTVAL (src) & 0xffff) == 0)
2778 if ((INTVAL (src) & 0xffff)
2779 == ((INTVAL (src) >> 16) & 0xffff))
2789 if (addr == NULL_RTX)
2794 if (satisfies_constraint_G (src))
2807 /* Adjust the length based on the addressing mode used.
2808 Specifically, we subtract the difference between the actual
2809 length and the longest one, which is @(d:16,Rs). For SImode
2810 and SFmode, we double the adjustment because two mov.w are
2811 used to do the job. */
2813 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2814 if (GET_CODE (addr) == PRE_DEC
2815 || GET_CODE (addr) == POST_INC)
2817 if (mode == QImode || mode == HImode)
2818 return base_length - 2;
2820 /* In SImode and SFmode, we use two mov.w instructions, so
2821 double the adjustment. */
2822 return base_length - 4;
2825 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2826 in SImode and SFmode, the second mov.w involves an address
2827 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2829 if (GET_CODE (addr) == REG)
2830 return base_length - 2;
2836 unsigned int base_length;
2841 if (addr == NULL_RTX)
2844 /* The eightbit addressing is available only in QImode, so
2845 go ahead and take care of it. */
2846 if (h8300_eightbit_constant_address_p (addr))
2853 if (addr == NULL_RTX)
2858 if (src == const0_rtx)
2868 if (addr == NULL_RTX)
2872 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
2878 if (GET_CODE (src) == CONST_INT)
2880 int val = INTVAL (src);
2885 if (val == (val & 0x00ff) || val == (val & 0xff00))
2888 switch (val & 0xffffffff)
2909 if (addr == NULL_RTX)
2914 if (satisfies_constraint_G (src))
2927 /* Adjust the length based on the addressing mode used.
2928 Specifically, we subtract the difference between the actual
2929 length and the longest one, which is @(d:24,ERs). */
2931 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
2932 if (GET_CODE (addr) == PRE_DEC
2933 || GET_CODE (addr) == POST_INC)
2934 return base_length - 6;
2936 /* @ERs and @ERd are 6 bytes shorter than the longest. */
2937 if (GET_CODE (addr) == REG)
2938 return base_length - 6;
2940 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
2942 if (GET_CODE (addr) == PLUS
2943 && GET_CODE (XEXP (addr, 0)) == REG
2944 && GET_CODE (XEXP (addr, 1)) == CONST_INT
2945 && INTVAL (XEXP (addr, 1)) > -32768
2946 && INTVAL (XEXP (addr, 1)) < 32767)
2947 return base_length - 4;
2949 /* @aa:16 is 4 bytes shorter than the longest. */
2950 if (h8300_tiny_constant_address_p (addr))
2951 return base_length - 4;
2953 /* @aa:24 is 2 bytes shorter than the longest. */
2954 if (CONSTANT_P (addr))
2955 return base_length - 2;
2961 /* Output an addition insn. */
2964 output_plussi (rtx *operands)
2966 enum machine_mode mode = GET_MODE (operands[0]);
2968 gcc_assert (mode == SImode);
2972 if (GET_CODE (operands[2]) == REG)
2973 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2975 if (GET_CODE (operands[2]) == CONST_INT)
2977 HOST_WIDE_INT n = INTVAL (operands[2]);
2979 if ((n & 0xffffff) == 0)
2980 return "add\t%z2,%z0";
2981 if ((n & 0xffff) == 0)
2982 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
2983 if ((n & 0xff) == 0)
2984 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2987 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
2991 if (GET_CODE (operands[2]) == CONST_INT
2992 && register_operand (operands[1], VOIDmode))
2994 HOST_WIDE_INT intval = INTVAL (operands[2]);
2996 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
2997 return "add.l\t%S2,%S0";
2998 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
2999 return "sub.l\t%G2,%S0";
3001 /* See if we can finish with 2 bytes. */
3003 switch ((unsigned int) intval & 0xffffffff)
3008 return "adds\t%2,%S0";
3013 return "subs\t%G2,%S0";
3017 operands[2] = GEN_INT (intval >> 16);
3018 return "inc.w\t%2,%e0";
3022 operands[2] = GEN_INT (intval >> 16);
3023 return "dec.w\t%G2,%e0";
3026 /* See if we can finish with 4 bytes. */
3027 if ((intval & 0xffff) == 0)
3029 operands[2] = GEN_INT (intval >> 16);
3030 return "add.w\t%2,%e0";
3034 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3036 operands[2] = GEN_INT (-INTVAL (operands[2]));
3037 return "sub.l\t%S2,%S0";
3039 return "add.l\t%S2,%S0";
3043 /* ??? It would be much easier to add the h8sx stuff if a single function
3044 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3045 /* Compute the length of an addition insn. */
3048 compute_plussi_length (rtx *operands)
3050 enum machine_mode mode = GET_MODE (operands[0]);
3052 gcc_assert (mode == SImode);
3056 if (GET_CODE (operands[2]) == REG)
3059 if (GET_CODE (operands[2]) == CONST_INT)
3061 HOST_WIDE_INT n = INTVAL (operands[2]);
3063 if ((n & 0xffffff) == 0)
3065 if ((n & 0xffff) == 0)
3067 if ((n & 0xff) == 0)
3075 if (GET_CODE (operands[2]) == CONST_INT
3076 && register_operand (operands[1], VOIDmode))
3078 HOST_WIDE_INT intval = INTVAL (operands[2]);
3080 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3082 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3085 /* See if we can finish with 2 bytes. */
3087 switch ((unsigned int) intval & 0xffffffff)
3108 /* See if we can finish with 4 bytes. */
3109 if ((intval & 0xffff) == 0)
3113 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3114 return h8300_length_from_table (operands[0],
3115 GEN_INT (-INTVAL (operands[2])),
3116 &addl_length_table);
3118 return h8300_length_from_table (operands[0], operands[2],
3119 &addl_length_table);
3124 /* Compute which flag bits are valid after an addition insn. */
3127 compute_plussi_cc (rtx *operands)
3129 enum machine_mode mode = GET_MODE (operands[0]);
3131 gcc_assert (mode == SImode);
3139 if (GET_CODE (operands[2]) == CONST_INT
3140 && register_operand (operands[1], VOIDmode))
3142 HOST_WIDE_INT intval = INTVAL (operands[2]);
3144 if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
3146 if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
3149 /* See if we can finish with 2 bytes. */
3151 switch ((unsigned int) intval & 0xffffffff)
3156 return CC_NONE_0HIT;
3161 return CC_NONE_0HIT;
3172 /* See if we can finish with 4 bytes. */
3173 if ((intval & 0xffff) == 0)
3181 /* Output a logical insn. */
3184 output_logical_op (enum machine_mode mode, rtx *operands)
3186 /* Figure out the logical op that we need to perform. */
3187 enum rtx_code code = GET_CODE (operands[3]);
3188 /* Pretend that every byte is affected if both operands are registers. */
3189 const unsigned HOST_WIDE_INT intval =
3190 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3191 /* Always use the full instruction if the
3192 first operand is in memory. It is better
3193 to use define_splits to generate the shorter
3194 sequence where valid. */
3195 && register_operand (operands[1], VOIDmode)
3196 ? INTVAL (operands[2]) : 0x55555555);
3197 /* The determinant of the algorithm. If we perform an AND, 0
3198 affects a bit. Otherwise, 1 affects a bit. */
3199 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3200 /* Break up DET into pieces. */
3201 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3202 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3203 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3204 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3205 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3206 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3207 int lower_half_easy_p = 0;
3208 int upper_half_easy_p = 0;
3209 /* The name of an insn. */
3231 /* First, see if we can finish with one insn. */
3232 if ((TARGET_H8300H || TARGET_H8300S)
3236 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
3237 output_asm_insn (insn_buf, operands);
3241 /* Take care of the lower byte. */
3244 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
3245 output_asm_insn (insn_buf, operands);
3247 /* Take care of the upper byte. */
3250 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
3251 output_asm_insn (insn_buf, operands);
3256 if (TARGET_H8300H || TARGET_H8300S)
3258 /* Determine if the lower half can be taken care of in no more
3260 lower_half_easy_p = (b0 == 0
3262 || (code != IOR && w0 == 0xffff));
3264 /* Determine if the upper half can be taken care of in no more
3266 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3267 || (code == AND && w1 == 0xff00));
3270 /* Check if doing everything with one insn is no worse than
3271 using multiple insns. */
3272 if ((TARGET_H8300H || TARGET_H8300S)
3273 && w0 != 0 && w1 != 0
3274 && !(lower_half_easy_p && upper_half_easy_p)
3275 && !(code == IOR && w1 == 0xffff
3276 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3278 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
3279 output_asm_insn (insn_buf, operands);
3283 /* Take care of the lower and upper words individually. For
3284 each word, we try different methods in the order of
3286 1) the special insn (in case of AND or XOR),
3287 2) the word-wise insn, and
3288 3) The byte-wise insn. */
3290 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3291 output_asm_insn ((code == AND)
3292 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3294 else if ((TARGET_H8300H || TARGET_H8300S)
3298 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
3299 output_asm_insn (insn_buf, operands);
3305 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
3306 output_asm_insn (insn_buf, operands);
3310 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
3311 output_asm_insn (insn_buf, operands);
3316 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3317 output_asm_insn ((code == AND)
3318 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3320 else if ((TARGET_H8300H || TARGET_H8300S)
3323 && (w0 & 0x8000) != 0)
3325 output_asm_insn ("exts.l\t%S0", operands);
3327 else if ((TARGET_H8300H || TARGET_H8300S)
3331 output_asm_insn ("extu.w\t%e0", operands);
3333 else if (TARGET_H8300H || TARGET_H8300S)
3337 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
3338 output_asm_insn (insn_buf, operands);
3345 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
3346 output_asm_insn (insn_buf, operands);
3350 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
3351 output_asm_insn (insn_buf, operands);
3362 /* Compute the length of a logical insn. */
3365 compute_logical_op_length (enum machine_mode mode, rtx *operands)
3367 /* Figure out the logical op that we need to perform. */
3368 enum rtx_code code = GET_CODE (operands[3]);
3369 /* Pretend that every byte is affected if both operands are registers. */
3370 const unsigned HOST_WIDE_INT intval =
3371 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3372 /* Always use the full instruction if the
3373 first operand is in memory. It is better
3374 to use define_splits to generate the shorter
3375 sequence where valid. */
3376 && register_operand (operands[1], VOIDmode)
3377 ? INTVAL (operands[2]) : 0x55555555);
3378 /* The determinant of the algorithm. If we perform an AND, 0
3379 affects a bit. Otherwise, 1 affects a bit. */
3380 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3381 /* Break up DET into pieces. */
3382 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3383 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3384 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
3385 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
3386 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3387 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3388 int lower_half_easy_p = 0;
3389 int upper_half_easy_p = 0;
3391 unsigned int length = 0;
3396 /* First, see if we can finish with one insn. */
3397 if ((TARGET_H8300H || TARGET_H8300S)
3401 length = h8300_length_from_table (operands[1], operands[2],
3402 &logicw_length_table);
3406 /* Take care of the lower byte. */
3410 /* Take care of the upper byte. */
3416 if (TARGET_H8300H || TARGET_H8300S)
3418 /* Determine if the lower half can be taken care of in no more
3420 lower_half_easy_p = (b0 == 0
3422 || (code != IOR && w0 == 0xffff));
3424 /* Determine if the upper half can be taken care of in no more
3426 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3427 || (code == AND && w1 == 0xff00));
3430 /* Check if doing everything with one insn is no worse than
3431 using multiple insns. */
3432 if ((TARGET_H8300H || TARGET_H8300S)
3433 && w0 != 0 && w1 != 0
3434 && !(lower_half_easy_p && upper_half_easy_p)
3435 && !(code == IOR && w1 == 0xffff
3436 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3438 length = h8300_length_from_table (operands[1], operands[2],
3439 &logicl_length_table);
3443 /* Take care of the lower and upper words individually. For
3444 each word, we try different methods in the order of
3446 1) the special insn (in case of AND or XOR),
3447 2) the word-wise insn, and
3448 3) The byte-wise insn. */
3450 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3454 else if ((TARGET_H8300H || TARGET_H8300S)
3470 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
3474 else if ((TARGET_H8300H || TARGET_H8300S)
3477 && (w0 & 0x8000) != 0)
3481 else if ((TARGET_H8300H || TARGET_H8300S)
3487 else if (TARGET_H8300H || TARGET_H8300S)
3508 /* Compute which flag bits are valid after a logical insn. */
3511 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
3513 /* Figure out the logical op that we need to perform. */
3514 enum rtx_code code = GET_CODE (operands[3]);
3515 /* Pretend that every byte is affected if both operands are registers. */
3516 const unsigned HOST_WIDE_INT intval =
3517 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
3518 /* Always use the full instruction if the
3519 first operand is in memory. It is better
3520 to use define_splits to generate the shorter
3521 sequence where valid. */
3522 && register_operand (operands[1], VOIDmode)
3523 ? INTVAL (operands[2]) : 0x55555555);
3524 /* The determinant of the algorithm. If we perform an AND, 0
3525 affects a bit. Otherwise, 1 affects a bit. */
3526 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
3527 /* Break up DET into pieces. */
3528 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
3529 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
3530 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
3531 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
3532 int lower_half_easy_p = 0;
3533 int upper_half_easy_p = 0;
3534 /* Condition code. */
3535 enum attr_cc cc = CC_CLOBBER;
3540 /* First, see if we can finish with one insn. */
3541 if ((TARGET_H8300H || TARGET_H8300S)
3549 if (TARGET_H8300H || TARGET_H8300S)
3551 /* Determine if the lower half can be taken care of in no more
3553 lower_half_easy_p = (b0 == 0
3555 || (code != IOR && w0 == 0xffff));
3557 /* Determine if the upper half can be taken care of in no more
3559 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
3560 || (code == AND && w1 == 0xff00));
3563 /* Check if doing everything with one insn is no worse than
3564 using multiple insns. */
3565 if ((TARGET_H8300H || TARGET_H8300S)
3566 && w0 != 0 && w1 != 0
3567 && !(lower_half_easy_p && upper_half_easy_p)
3568 && !(code == IOR && w1 == 0xffff
3569 && (w0 & 0x8000) != 0 && lower_half_easy_p))
3575 if ((TARGET_H8300H || TARGET_H8300S)
3578 && (w0 & 0x8000) != 0)
3590 /* Expand a conditional branch. */
3593 h8300_expand_branch (rtx operands[])
3595 enum rtx_code code = GET_CODE (operands[0]);
3596 rtx op0 = operands[1];
3597 rtx op1 = operands[2];
3598 rtx label = operands[3];
3601 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3602 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3604 tmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
3605 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
3606 gen_rtx_LABEL_REF (VOIDmode, label),
3608 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
3612 /* Expand a conditional store. */
3615 h8300_expand_store (rtx operands[])
3617 rtx dest = operands[0];
3618 enum rtx_code code = GET_CODE (operands[1]);
3619 rtx op0 = operands[2];
3620 rtx op1 = operands[3];
3623 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1);
3624 emit_insn (gen_rtx_SET (VOIDmode, cc0_rtx, tmp));
3626 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx);
3627 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
3632 We devote a fair bit of code to getting efficient shifts since we
3633 can only shift one bit at a time on the H8/300 and H8/300H and only
3634 one or two bits at a time on the H8S.
3636 All shift code falls into one of the following ways of
3639 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3640 when a straight line shift is about the same size or smaller than
3643 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3644 off the bits we don't need. This is used when only a few of the
3645 bits in the original value will survive in the shifted value.
3647 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3648 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3649 shifts can be added if the shift count is slightly more than 8 or
3650 16. This case also includes other oddballs that are not worth
3653 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3655 For each shift count, we try to use code that has no trade-off
3656 between code size and speed whenever possible.
3658 If the trade-off is unavoidable, we try to be reasonable.
3659 Specifically, the fastest version is one instruction longer than
3660 the shortest version, we take the fastest version. We also provide
3661 the use a way to switch back to the shortest version with -Os.
3663 For the details of the shift algorithms for various shift counts,
3664 refer to shift_alg_[qhs]i. */
3666 /* Classify a shift with the given mode and code. OP is the shift amount. */
3668 enum h8sx_shift_type
3669 h8sx_classify_shift (enum machine_mode mode, enum rtx_code code, rtx op)
3671 if (!TARGET_H8300SX)
3672 return H8SX_SHIFT_NONE;
3678 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3679 if (GET_CODE (op) != CONST_INT)
3680 return H8SX_SHIFT_BINARY;
3682 /* Reject out-of-range shift amounts. */
3683 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode))
3684 return H8SX_SHIFT_NONE;
3686 /* Power-of-2 shifts are effectively unary operations. */
3687 if (exact_log2 (INTVAL (op)) >= 0)
3688 return H8SX_SHIFT_UNARY;
3690 return H8SX_SHIFT_BINARY;
3693 if (op == const1_rtx || op == const2_rtx)
3694 return H8SX_SHIFT_UNARY;
3695 return H8SX_SHIFT_NONE;
3698 if (GET_CODE (op) == CONST_INT
3699 && (INTVAL (op) == 1
3701 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
3702 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1))
3703 return H8SX_SHIFT_UNARY;
3704 return H8SX_SHIFT_NONE;
3707 return H8SX_SHIFT_NONE;
3711 /* Return the asm template for a single h8sx shift instruction.
3712 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3713 is the source and OPERANDS[3] is the shift. SUFFIX is the
3714 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3715 prefix for the destination operand. */
3718 output_h8sx_shift (rtx *operands, int suffix, int optype)
3720 static char buffer[16];
3723 switch (GET_CODE (operands[3]))
3739 if (INTVAL (operands[2]) > 2)
3741 /* This is really a right rotate. */
3742 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0]))
3743 - INTVAL (operands[2]));
3751 if (operands[2] == const1_rtx)
3752 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype);
3754 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype);
3758 /* Emit code to do shifts. */
3761 expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
3763 switch (h8sx_classify_shift (mode, code, operands[2]))
3765 case H8SX_SHIFT_BINARY:
3766 operands[1] = force_reg (mode, operands[1]);
3769 case H8SX_SHIFT_UNARY:
3772 case H8SX_SHIFT_NONE:
3776 emit_move_insn (copy_rtx (operands[0]), operands[1]);
3778 /* Need a loop to get all the bits we want - we generate the
3779 code at emit time, but need to allocate a scratch reg now. */
3781 emit_insn (gen_rtx_PARALLEL
3784 gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
3785 gen_rtx_fmt_ee (code, mode,
3786 copy_rtx (operands[0]), operands[2])),
3787 gen_rtx_CLOBBER (VOIDmode,
3788 gen_rtx_SCRATCH (QImode)))));
3792 /* Symbols of the various modes which can be used as indices. */
3796 QIshift, HIshift, SIshift
3799 /* For single bit shift insns, record assembler and what bits of the
3800 condition code are valid afterwards (represented as various CC_FOO
3801 bits, 0 means CC isn't left in a usable state). */
3805 const char *const assembler;
3806 const enum attr_cc cc_valid;
3809 /* Assembler instruction shift table.
3811 These tables are used to look up the basic shifts.
3812 They are indexed by cpu, shift_type, and mode. */
3814 static const struct shift_insn shift_one[2][3][3] =
3820 { "shll\t%X0", CC_SET_ZNV },
3821 { "add.w\t%T0,%T0", CC_SET_ZN },
3822 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
3824 /* SHIFT_LSHIFTRT */
3826 { "shlr\t%X0", CC_SET_ZNV },
3827 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3828 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3830 /* SHIFT_ASHIFTRT */
3832 { "shar\t%X0", CC_SET_ZNV },
3833 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
3834 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
3841 { "shll.b\t%X0", CC_SET_ZNV },
3842 { "shll.w\t%T0", CC_SET_ZNV },
3843 { "shll.l\t%S0", CC_SET_ZNV }
3845 /* SHIFT_LSHIFTRT */
3847 { "shlr.b\t%X0", CC_SET_ZNV },
3848 { "shlr.w\t%T0", CC_SET_ZNV },
3849 { "shlr.l\t%S0", CC_SET_ZNV }
3851 /* SHIFT_ASHIFTRT */
3853 { "shar.b\t%X0", CC_SET_ZNV },
3854 { "shar.w\t%T0", CC_SET_ZNV },
3855 { "shar.l\t%S0", CC_SET_ZNV }
3860 static const struct shift_insn shift_two[3][3] =
3864 { "shll.b\t#2,%X0", CC_SET_ZNV },
3865 { "shll.w\t#2,%T0", CC_SET_ZNV },
3866 { "shll.l\t#2,%S0", CC_SET_ZNV }
3868 /* SHIFT_LSHIFTRT */
3870 { "shlr.b\t#2,%X0", CC_SET_ZNV },
3871 { "shlr.w\t#2,%T0", CC_SET_ZNV },
3872 { "shlr.l\t#2,%S0", CC_SET_ZNV }
3874 /* SHIFT_ASHIFTRT */
3876 { "shar.b\t#2,%X0", CC_SET_ZNV },
3877 { "shar.w\t#2,%T0", CC_SET_ZNV },
3878 { "shar.l\t#2,%S0", CC_SET_ZNV }
3882 /* Rotates are organized by which shift they'll be used in implementing.
3883 There's no need to record whether the cc is valid afterwards because
3884 it is the AND insn that will decide this. */
3886 static const char *const rotate_one[2][3][3] =
3893 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3896 /* SHIFT_LSHIFTRT */
3899 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3902 /* SHIFT_ASHIFTRT */
3905 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3917 /* SHIFT_LSHIFTRT */
3923 /* SHIFT_ASHIFTRT */
3932 static const char *const rotate_two[3][3] =
3940 /* SHIFT_LSHIFTRT */
3946 /* SHIFT_ASHIFTRT */
3955 /* Shift algorithm. */
3958 /* The number of bits to be shifted by shift1 and shift2. Valid
3959 when ALG is SHIFT_SPECIAL. */
3960 unsigned int remainder;
3962 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
3963 const char *special;
3965 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
3966 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3969 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
3970 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
3973 /* CC status for SHIFT_INLINE. */
3974 enum attr_cc cc_inline;
3976 /* CC status for SHIFT_SPECIAL. */
3977 enum attr_cc cc_special;
3980 static void get_shift_alg (enum shift_type,
3981 enum shift_mode, unsigned int,
3982 struct shift_info *);
3984 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
3985 best algorithm for doing the shift. The assembler code is stored
3986 in the pointers in INFO. We achieve the maximum efficiency in most
3987 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
3988 SImode in particular have a lot of room to optimize.
3990 We first determine the strategy of the shift algorithm by a table
3991 lookup. If that tells us to use a hand crafted assembly code, we
3992 go into the big switch statement to find what that is. Otherwise,
3993 we resort to a generic way, such as inlining. In either case, the
3994 result is returned through INFO. */
3997 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
3998 unsigned int count, struct shift_info *info)
4002 /* Find the target CPU. */
4005 else if (TARGET_H8300H)
4010 /* Find the shift algorithm. */
4011 info->alg = SHIFT_LOOP;
4015 if (count < GET_MODE_BITSIZE (QImode))
4016 info->alg = shift_alg_qi[cpu][shift_type][count];
4020 if (count < GET_MODE_BITSIZE (HImode))
4021 info->alg = shift_alg_hi[cpu][shift_type][count];
4025 if (count < GET_MODE_BITSIZE (SImode))
4026 info->alg = shift_alg_si[cpu][shift_type][count];
4033 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4037 info->remainder = count;
4041 /* It is up to the caller to know that looping clobbers cc. */
4042 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4043 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4044 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4048 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
4049 info->shift2 = rotate_two[shift_type][shift_mode];
4050 info->cc_inline = CC_CLOBBER;
4054 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4055 info->remainder = 0;
4056 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
4057 info->shift2 = shift_two[shift_type][shift_mode].assembler;
4058 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
4059 info->cc_special = CC_CLOBBER;
4063 /* Here we only deal with SHIFT_SPECIAL. */
4067 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4068 through the entire value. */
4069 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7);
4070 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
4080 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4082 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4084 case SHIFT_LSHIFTRT:
4086 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4088 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4090 case SHIFT_ASHIFTRT:
4091 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4095 else if ((8 <= count && count <= 13)
4096 || (TARGET_H8300S && count == 14))
4098 info->remainder = count - 8;
4103 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4105 case SHIFT_LSHIFTRT:
4108 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4109 info->shift1 = "shlr.b\t%s0";
4110 info->cc_inline = CC_SET_ZNV;
4114 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
4115 info->cc_special = CC_SET_ZNV;
4118 case SHIFT_ASHIFTRT:
4121 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4122 info->shift1 = "shar.b\t%s0";
4126 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
4127 info->cc_special = CC_SET_ZNV;
4132 else if (count == 14)
4138 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4140 case SHIFT_LSHIFTRT:
4142 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4144 case SHIFT_ASHIFTRT:
4146 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4147 else if (TARGET_H8300H)
4149 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4150 info->cc_special = CC_SET_ZNV;
4152 else /* TARGET_H8300S */
4157 else if (count == 15)
4162 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4164 case SHIFT_LSHIFTRT:
4165 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4167 case SHIFT_ASHIFTRT:
4168 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4175 if (TARGET_H8300 && 8 <= count && count <= 9)
4177 info->remainder = count - 8;
4182 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4184 case SHIFT_LSHIFTRT:
4185 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4186 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4188 case SHIFT_ASHIFTRT:
4189 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4193 else if (count == 8 && !TARGET_H8300)
4198 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4200 case SHIFT_LSHIFTRT:
4201 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4203 case SHIFT_ASHIFTRT:
4204 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4208 else if (count == 15 && TARGET_H8300)
4214 case SHIFT_LSHIFTRT:
4215 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4217 case SHIFT_ASHIFTRT:
4218 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4222 else if (count == 15 && !TARGET_H8300)
4227 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4228 info->cc_special = CC_SET_ZNV;
4230 case SHIFT_LSHIFTRT:
4231 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4232 info->cc_special = CC_SET_ZNV;
4234 case SHIFT_ASHIFTRT:
4238 else if ((TARGET_H8300 && 16 <= count && count <= 20)
4239 || (TARGET_H8300H && 16 <= count && count <= 19)
4240 || (TARGET_H8300S && 16 <= count && count <= 21))
4242 info->remainder = count - 16;
4247 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4249 info->shift1 = "add.w\t%e0,%e0";
4251 case SHIFT_LSHIFTRT:
4254 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4255 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
4259 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
4260 info->cc_special = CC_SET_ZNV;
4263 case SHIFT_ASHIFTRT:
4266 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4267 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
4271 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
4272 info->cc_special = CC_SET_ZNV;
4277 else if (TARGET_H8300 && 24 <= count && count <= 28)
4279 info->remainder = count - 24;
4284 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4285 info->shift1 = "shll.b\t%z0";
4286 info->cc_inline = CC_SET_ZNV;
4288 case SHIFT_LSHIFTRT:
4289 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4290 info->shift1 = "shlr.b\t%w0";
4291 info->cc_inline = CC_SET_ZNV;
4293 case SHIFT_ASHIFTRT:
4294 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4295 info->shift1 = "shar.b\t%w0";
4296 info->cc_inline = CC_SET_ZNV;
4300 else if ((TARGET_H8300H && count == 24)
4301 || (TARGET_H8300S && 24 <= count && count <= 25))
4303 info->remainder = count - 24;
4308 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4310 case SHIFT_LSHIFTRT:
4311 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4312 info->cc_special = CC_SET_ZNV;
4314 case SHIFT_ASHIFTRT:
4315 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4316 info->cc_special = CC_SET_ZNV;
4320 else if (!TARGET_H8300 && count == 28)
4326 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4328 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4330 case SHIFT_LSHIFTRT:
4333 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4334 info->cc_special = CC_SET_ZNV;
4337 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4339 case SHIFT_ASHIFTRT:
4343 else if (!TARGET_H8300 && count == 29)
4349 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4351 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4353 case SHIFT_LSHIFTRT:
4356 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4357 info->cc_special = CC_SET_ZNV;
4361 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4362 info->cc_special = CC_SET_ZNV;
4365 case SHIFT_ASHIFTRT:
4369 else if (!TARGET_H8300 && count == 30)
4375 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4377 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4379 case SHIFT_LSHIFTRT:
4381 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4383 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4385 case SHIFT_ASHIFTRT:
4389 else if (count == 31)
4396 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4398 case SHIFT_LSHIFTRT:
4399 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4401 case SHIFT_ASHIFTRT:
4402 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4411 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4412 info->cc_special = CC_SET_ZNV;
4414 case SHIFT_LSHIFTRT:
4415 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4416 info->cc_special = CC_SET_ZNV;
4418 case SHIFT_ASHIFTRT:
4419 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4420 info->cc_special = CC_SET_ZNV;
4433 info->shift2 = NULL;
4436 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4437 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4440 h8300_shift_needs_scratch_p (int count, enum machine_mode mode)
4445 if (GET_MODE_BITSIZE (mode) <= count)
4448 /* Find out the target CPU. */
4451 else if (TARGET_H8300H)
4456 /* Find the shift algorithm. */
4460 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
4461 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
4462 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
4466 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
4467 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
4468 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
4472 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
4473 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
4474 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
4481 /* On H8/300H, count == 8 uses a scratch register. */
4482 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
4483 || (TARGET_H8300H && mode == SImode && count == 8));
4486 /* Output the assembler code for doing shifts. */
4489 output_a_shift (rtx *operands)
4491 static int loopend_lab;
4492 rtx shift = operands[3];
4493 enum machine_mode mode = GET_MODE (shift);
4494 enum rtx_code code = GET_CODE (shift);
4495 enum shift_type shift_type;
4496 enum shift_mode shift_mode;
4497 struct shift_info info;
4505 shift_mode = QIshift;
4508 shift_mode = HIshift;
4511 shift_mode = SIshift;
4520 shift_type = SHIFT_ASHIFTRT;
4523 shift_type = SHIFT_LSHIFTRT;
4526 shift_type = SHIFT_ASHIFT;
4532 /* This case must be taken care of by one of the two splitters
4533 that convert a variable shift into a loop. */
4534 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4536 n = INTVAL (operands[2]);
4538 /* If the count is negative, make it 0. */
4541 /* If the count is too big, truncate it.
4542 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4543 do the intuitive thing. */
4544 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4545 n = GET_MODE_BITSIZE (mode);
4547 get_shift_alg (shift_type, shift_mode, n, &info);
4552 output_asm_insn (info.special, operands);
4558 /* Emit two bit shifts first. */
4559 if (info.shift2 != NULL)
4561 for (; n > 1; n -= 2)
4562 output_asm_insn (info.shift2, operands);
4565 /* Now emit one bit shifts for any residual. */
4567 output_asm_insn (info.shift1, operands);
4572 int m = GET_MODE_BITSIZE (mode) - n;
4573 const int mask = (shift_type == SHIFT_ASHIFT
4574 ? ((1 << m) - 1) << n
4578 /* Not all possibilities of rotate are supported. They shouldn't
4579 be generated, but let's watch for 'em. */
4580 gcc_assert (info.shift1);
4582 /* Emit two bit rotates first. */
4583 if (info.shift2 != NULL)
4585 for (; m > 1; m -= 2)
4586 output_asm_insn (info.shift2, operands);
4589 /* Now single bit rotates for any residual. */
4591 output_asm_insn (info.shift1, operands);
4593 /* Now mask off the high bits. */
4597 sprintf (insn_buf, "and\t#%d,%%X0", mask);
4601 gcc_assert (TARGET_H8300H || TARGET_H8300S);
4602 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
4609 output_asm_insn (insn_buf, operands);
4614 /* A loop to shift by a "large" constant value.
4615 If we have shift-by-2 insns, use them. */
4616 if (info.shift2 != NULL)
4618 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
4619 names_big[REGNO (operands[4])]);
4620 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4621 output_asm_insn (info.shift2, operands);
4622 output_asm_insn ("add #0xff,%X4", operands);
4623 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4625 output_asm_insn (info.shift1, operands);
4629 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
4630 names_big[REGNO (operands[4])]);
4631 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
4632 output_asm_insn (info.shift1, operands);
4633 output_asm_insn ("add #0xff,%X4", operands);
4634 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
4643 /* Count the number of assembly instructions in a string TEMPL. */
4646 h8300_asm_insn_count (const char *templ)
4648 unsigned int count = 1;
4650 for (; *templ; templ++)
4657 /* Compute the length of a shift insn. */
4660 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4662 rtx shift = operands[3];
4663 enum machine_mode mode = GET_MODE (shift);
4664 enum rtx_code code = GET_CODE (shift);
4665 enum shift_type shift_type;
4666 enum shift_mode shift_mode;
4667 struct shift_info info;
4668 unsigned int wlength = 0;
4673 shift_mode = QIshift;
4676 shift_mode = HIshift;
4679 shift_mode = SIshift;
4688 shift_type = SHIFT_ASHIFTRT;
4691 shift_type = SHIFT_LSHIFTRT;
4694 shift_type = SHIFT_ASHIFT;
4700 if (GET_CODE (operands[2]) != CONST_INT)
4702 /* Get the assembler code to do one shift. */
4703 get_shift_alg (shift_type, shift_mode, 1, &info);
4705 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
4709 int n = INTVAL (operands[2]);
4711 /* If the count is negative, make it 0. */
4714 /* If the count is too big, truncate it.
4715 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4716 do the intuitive thing. */
4717 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4718 n = GET_MODE_BITSIZE (mode);
4720 get_shift_alg (shift_type, shift_mode, n, &info);
4725 wlength += h8300_asm_insn_count (info.special);
4727 /* Every assembly instruction used in SHIFT_SPECIAL case
4728 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4729 see xor.l, we just pretend that xor.l counts as two insns
4730 so that the insn length will be computed correctly. */
4731 if (strstr (info.special, "xor.l") != NULL)
4739 if (info.shift2 != NULL)
4741 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
4745 wlength += h8300_asm_insn_count (info.shift1) * n;
4751 int m = GET_MODE_BITSIZE (mode) - n;
4753 /* Not all possibilities of rotate are supported. They shouldn't
4754 be generated, but let's watch for 'em. */
4755 gcc_assert (info.shift1);
4757 if (info.shift2 != NULL)
4759 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
4763 wlength += h8300_asm_insn_count (info.shift1) * m;
4765 /* Now mask off the high bits. */
4775 gcc_assert (!TARGET_H8300);
4785 /* A loop to shift by a "large" constant value.
4786 If we have shift-by-2 insns, use them. */
4787 if (info.shift2 != NULL)
4789 wlength += 3 + h8300_asm_insn_count (info.shift2);
4791 wlength += h8300_asm_insn_count (info.shift1);
4795 wlength += 3 + h8300_asm_insn_count (info.shift1);
4805 /* Compute which flag bits are valid after a shift insn. */
4808 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
4810 rtx shift = operands[3];
4811 enum machine_mode mode = GET_MODE (shift);
4812 enum rtx_code code = GET_CODE (shift);
4813 enum shift_type shift_type;
4814 enum shift_mode shift_mode;
4815 struct shift_info info;
4821 shift_mode = QIshift;
4824 shift_mode = HIshift;
4827 shift_mode = SIshift;
4836 shift_type = SHIFT_ASHIFTRT;
4839 shift_type = SHIFT_LSHIFTRT;
4842 shift_type = SHIFT_ASHIFT;
4848 /* This case must be taken care of by one of the two splitters
4849 that convert a variable shift into a loop. */
4850 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
4852 n = INTVAL (operands[2]);
4854 /* If the count is negative, make it 0. */
4857 /* If the count is too big, truncate it.
4858 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4859 do the intuitive thing. */
4860 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
4861 n = GET_MODE_BITSIZE (mode);
4863 get_shift_alg (shift_type, shift_mode, n, &info);
4868 if (info.remainder == 0)
4869 return info.cc_special;
4874 return info.cc_inline;
4877 /* This case always ends with an and instruction. */
4881 /* A loop to shift by a "large" constant value.
4882 If we have shift-by-2 insns, use them. */
4883 if (info.shift2 != NULL)
4886 return info.cc_inline;
4895 /* A rotation by a non-constant will cause a loop to be generated, in
4896 which a rotation by one bit is used. A rotation by a constant,
4897 including the one in the loop, will be taken care of by
4898 output_a_rotate () at the insn emit time. */
4901 expand_a_rotate (rtx operands[])
4903 rtx dst = operands[0];
4904 rtx src = operands[1];
4905 rtx rotate_amount = operands[2];
4906 enum machine_mode mode = GET_MODE (dst);
4908 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY)
4911 /* We rotate in place. */
4912 emit_move_insn (dst, src);
4914 if (GET_CODE (rotate_amount) != CONST_INT)
4916 rtx counter = gen_reg_rtx (QImode);
4917 rtx start_label = gen_label_rtx ();
4918 rtx end_label = gen_label_rtx ();
4920 /* If the rotate amount is less than or equal to 0,
4921 we go out of the loop. */
4922 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX,
4923 QImode, 0, end_label);
4925 /* Initialize the loop counter. */
4926 emit_move_insn (counter, rotate_amount);
4928 emit_label (start_label);
4930 /* Rotate by one bit. */
4934 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx));
4937 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx));
4940 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx));
4946 /* Decrement the counter by 1. */
4947 emit_insn (gen_addqi3 (counter, counter, constm1_rtx));
4949 /* If the loop counter is nonzero, we go back to the beginning
4951 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1,
4954 emit_label (end_label);
4958 /* Rotate by AMOUNT bits. */
4962 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount));
4965 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount));
4968 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount));
4978 /* Output a rotate insn. */
4981 output_a_rotate (enum rtx_code code, rtx *operands)
4983 rtx dst = operands[0];
4984 rtx rotate_amount = operands[2];
4985 enum shift_mode rotate_mode;
4986 enum shift_type rotate_type;
4987 const char *insn_buf;
4990 enum machine_mode mode = GET_MODE (dst);
4992 gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
4997 rotate_mode = QIshift;
5000 rotate_mode = HIshift;
5003 rotate_mode = SIshift;
5012 rotate_type = SHIFT_ASHIFT;
5015 rotate_type = SHIFT_LSHIFTRT;
5021 amount = INTVAL (rotate_amount);
5023 /* Clean up AMOUNT. */
5026 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5027 amount = GET_MODE_BITSIZE (mode);
5029 /* Determine the faster direction. After this phase, amount will be
5030 at most a half of GET_MODE_BITSIZE (mode). */
5031 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5033 /* Flip the direction. */
5034 amount = GET_MODE_BITSIZE (mode) - amount;
5036 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5039 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5040 boost up the rotation. */
5041 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5042 || (mode == HImode && TARGET_H8300H && amount >= 6)
5043 || (mode == HImode && TARGET_H8300S && amount == 8)
5044 || (mode == SImode && TARGET_H8300H && amount >= 10)
5045 || (mode == SImode && TARGET_H8300S && amount >= 13))
5050 /* This code works on any family. */
5051 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5052 output_asm_insn (insn_buf, operands);
5056 /* This code works on the H8/300H and H8S. */
5057 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5058 output_asm_insn (insn_buf, operands);
5065 /* Adjust AMOUNT and flip the direction. */
5066 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5068 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
5071 /* Output rotate insns. */
5072 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
5075 insn_buf = rotate_two[rotate_type][rotate_mode];
5077 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
5079 for (; amount >= bits; amount -= bits)
5080 output_asm_insn (insn_buf, operands);
5086 /* Compute the length of a rotate insn. */
5089 compute_a_rotate_length (rtx *operands)
5091 rtx src = operands[1];
5092 rtx amount_rtx = operands[2];
5093 enum machine_mode mode = GET_MODE (src);
5095 unsigned int length = 0;
5097 gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
5099 amount = INTVAL (amount_rtx);
5101 /* Clean up AMOUNT. */
5104 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
5105 amount = GET_MODE_BITSIZE (mode);
5107 /* Determine the faster direction. After this phase, amount
5108 will be at most a half of GET_MODE_BITSIZE (mode). */
5109 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
5110 /* Flip the direction. */
5111 amount = GET_MODE_BITSIZE (mode) - amount;
5113 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5114 boost up the rotation. */
5115 if ((mode == HImode && TARGET_H8300 && amount >= 5)
5116 || (mode == HImode && TARGET_H8300H && amount >= 6)
5117 || (mode == HImode && TARGET_H8300S && amount == 8)
5118 || (mode == SImode && TARGET_H8300H && amount >= 10)
5119 || (mode == SImode && TARGET_H8300S && amount >= 13))
5121 /* Adjust AMOUNT and flip the direction. */
5122 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
5126 /* We use 2-bit rotations on the H8S. */
5128 amount = amount / 2 + amount % 2;
5130 /* The H8/300 uses three insns to rotate one bit, taking 6
5132 length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
5137 /* Fix the operands of a gen_xxx so that it could become a bit
5141 fix_bit_operand (rtx *operands, enum rtx_code code)
5143 /* The bit_operand predicate accepts any memory during RTL generation, but
5144 only 'U' memory afterwards, so if this is a MEM operand, we must force
5145 it to be valid for 'U' by reloading the address. */
5148 ? single_zero_operand (operands[2], QImode)
5149 : single_one_operand (operands[2], QImode))
5151 /* OK to have a memory dest. */
5152 if (GET_CODE (operands[0]) == MEM
5153 && !satisfies_constraint_U (operands[0]))
5155 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
5156 copy_to_mode_reg (Pmode,
5157 XEXP (operands[0], 0)));
5158 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5162 if (GET_CODE (operands[1]) == MEM
5163 && !satisfies_constraint_U (operands[1]))
5165 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
5166 copy_to_mode_reg (Pmode,
5167 XEXP (operands[1], 0)));
5168 MEM_COPY_ATTRIBUTES (mem, operands[0]);
5174 /* Dest and src op must be register. */
5176 operands[1] = force_reg (QImode, operands[1]);
5178 rtx res = gen_reg_rtx (QImode);
5182 emit_insn (gen_andqi3_1 (res, operands[1], operands[2]));
5185 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2]));
5188 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2]));
5193 emit_insn (gen_movqi (operands[0], res));
5198 /* Return nonzero if FUNC is an interrupt function as specified
5199 by the "interrupt" attribute. */
5202 h8300_interrupt_function_p (tree func)
5206 if (TREE_CODE (func) != FUNCTION_DECL)
5209 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
5210 return a != NULL_TREE;
5213 /* Return nonzero if FUNC is a saveall function as specified by the
5214 "saveall" attribute. */
5217 h8300_saveall_function_p (tree func)
5221 if (TREE_CODE (func) != FUNCTION_DECL)
5224 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func));
5225 return a != NULL_TREE;
5228 /* Return nonzero if FUNC is an OS_Task function as specified
5229 by the "OS_Task" attribute. */
5232 h8300_os_task_function_p (tree func)
5236 if (TREE_CODE (func) != FUNCTION_DECL)
5239 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
5240 return a != NULL_TREE;
5243 /* Return nonzero if FUNC is a monitor function as specified
5244 by the "monitor" attribute. */
5247 h8300_monitor_function_p (tree func)
5251 if (TREE_CODE (func) != FUNCTION_DECL)
5254 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
5255 return a != NULL_TREE;
5258 /* Return nonzero if FUNC is a function that should be called
5259 through the function vector. */
5262 h8300_funcvec_function_p (tree func)
5266 if (TREE_CODE (func) != FUNCTION_DECL)
5269 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
5270 return a != NULL_TREE;
5273 /* Return nonzero if DECL is a variable that's in the eight bit
5277 h8300_eightbit_data_p (tree decl)
5281 if (TREE_CODE (decl) != VAR_DECL)
5284 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
5285 return a != NULL_TREE;
5288 /* Return nonzero if DECL is a variable that's in the tiny
5292 h8300_tiny_data_p (tree decl)
5296 if (TREE_CODE (decl) != VAR_DECL)
5299 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
5300 return a != NULL_TREE;
5303 /* Generate an 'interrupt_handler' attribute for decls. We convert
5304 all the pragmas to corresponding attributes. */
5307 h8300_insert_attributes (tree node, tree *attributes)
5309 if (TREE_CODE (node) == FUNCTION_DECL)
5311 if (pragma_interrupt)
5313 pragma_interrupt = 0;
5315 /* Add an 'interrupt_handler' attribute. */
5316 *attributes = tree_cons (get_identifier ("interrupt_handler"),
5324 /* Add an 'saveall' attribute. */
5325 *attributes = tree_cons (get_identifier ("saveall"),
5331 /* Supported attributes:
5333 interrupt_handler: output a prologue and epilogue suitable for an
5336 saveall: output a prologue and epilogue that saves and restores
5337 all registers except the stack pointer.
5339 function_vector: This function should be called through the
5342 eightbit_data: This variable lives in the 8-bit data area and can
5343 be referenced with 8-bit absolute memory addresses.
5345 tiny_data: This variable lives in the tiny data area and can be
5346 referenced with 16-bit absolute memory references. */
5348 static const struct attribute_spec h8300_attribute_table[] =
5350 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5351 affects_type_identity } */
5352 { "interrupt_handler", 0, 0, true, false, false,
5353 h8300_handle_fndecl_attribute, false },
5354 { "saveall", 0, 0, true, false, false,
5355 h8300_handle_fndecl_attribute, false },
5356 { "OS_Task", 0, 0, true, false, false,
5357 h8300_handle_fndecl_attribute, false },
5358 { "monitor", 0, 0, true, false, false,
5359 h8300_handle_fndecl_attribute, false },
5360 { "function_vector", 0, 0, true, false, false,
5361 h8300_handle_fndecl_attribute, false },
5362 { "eightbit_data", 0, 0, true, false, false,
5363 h8300_handle_eightbit_data_attribute, false },
5364 { "tiny_data", 0, 0, true, false, false,
5365 h8300_handle_tiny_data_attribute, false },
5366 { NULL, 0, 0, false, false, false, NULL, false }
5370 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5371 struct attribute_spec.handler. */
5373 h8300_handle_fndecl_attribute (tree *node, tree name,
5374 tree args ATTRIBUTE_UNUSED,
5375 int flags ATTRIBUTE_UNUSED,
5378 if (TREE_CODE (*node) != FUNCTION_DECL)
5380 warning (OPT_Wattributes, "%qE attribute only applies to functions",
5382 *no_add_attrs = true;
5388 /* Handle an "eightbit_data" attribute; arguments as in
5389 struct attribute_spec.handler. */
5391 h8300_handle_eightbit_data_attribute (tree *node, tree name,
5392 tree args ATTRIBUTE_UNUSED,
5393 int flags ATTRIBUTE_UNUSED,
5398 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5400 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
5404 warning (OPT_Wattributes, "%qE attribute ignored",
5406 *no_add_attrs = true;
5412 /* Handle an "tiny_data" attribute; arguments as in
5413 struct attribute_spec.handler. */
5415 h8300_handle_tiny_data_attribute (tree *node, tree name,
5416 tree args ATTRIBUTE_UNUSED,
5417 int flags ATTRIBUTE_UNUSED,
5422 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
5424 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
5428 warning (OPT_Wattributes, "%qE attribute ignored",
5430 *no_add_attrs = true;
5436 /* Mark function vectors, and various small data objects. */
5439 h8300_encode_section_info (tree decl, rtx rtl, int first)
5441 int extra_flags = 0;
5443 default_encode_section_info (decl, rtl, first);
5445 if (TREE_CODE (decl) == FUNCTION_DECL
5446 && h8300_funcvec_function_p (decl))
5447 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
5448 else if (TREE_CODE (decl) == VAR_DECL
5449 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
5451 if (h8300_eightbit_data_p (decl))
5452 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
5453 else if (first && h8300_tiny_data_p (decl))
5454 extra_flags = SYMBOL_FLAG_TINY_DATA;
5458 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
5461 /* Output a single-bit extraction. */
5464 output_simode_bld (int bild, rtx operands[])
5468 /* Clear the destination register. */
5469 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
5471 /* Now output the bit load or bit inverse load, and store it in
5474 output_asm_insn ("bild\t%Z2,%Y1", operands);
5476 output_asm_insn ("bld\t%Z2,%Y1", operands);
5478 output_asm_insn ("bst\t#0,%w0", operands);
5482 /* Determine if we can clear the destination first. */
5483 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
5484 && REGNO (operands[0]) != REGNO (operands[1]));
5487 output_asm_insn ("sub.l\t%S0,%S0", operands);
5489 /* Output the bit load or bit inverse load. */
5491 output_asm_insn ("bild\t%Z2,%Y1", operands);
5493 output_asm_insn ("bld\t%Z2,%Y1", operands);
5496 output_asm_insn ("xor.l\t%S0,%S0", operands);
5498 /* Perform the bit store. */
5499 output_asm_insn ("rotxl.l\t%S0", operands);
5506 /* Delayed-branch scheduling is more effective if we have some idea
5507 how long each instruction will be. Use a shorten_branches pass
5508 to get an initial estimate. */
5513 if (flag_delayed_branch)
5514 shorten_branches (get_insns ());
5517 #ifndef OBJECT_FORMAT_ELF
5519 h8300_asm_named_section (const char *name, unsigned int flags ATTRIBUTE_UNUSED,
5522 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5523 fprintf (asm_out_file, "\t.section %s\n", name);
5525 #endif /* ! OBJECT_FORMAT_ELF */
5527 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5528 which is a special case of the 'R' operand. */
5531 h8300_eightbit_constant_address_p (rtx x)
5533 /* The ranges of the 8-bit area. */
5534 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
5535 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
5536 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
5537 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
5538 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
5539 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
5541 unsigned HOST_WIDE_INT addr;
5543 /* We accept symbols declared with eightbit_data. */
5544 if (GET_CODE (x) == SYMBOL_REF)
5545 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
5547 if (GET_CODE (x) != CONST_INT)
5553 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
5554 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
5555 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
5558 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5559 on H8/300H and H8S. */
5562 h8300_tiny_constant_address_p (rtx x)
5564 /* The ranges of the 16-bit area. */
5565 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
5566 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
5567 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
5568 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
5569 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
5570 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
5571 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
5572 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
5574 unsigned HOST_WIDE_INT addr;
5576 switch (GET_CODE (x))
5579 /* In the normal mode, any symbol fits in the 16-bit absolute
5580 address range. We also accept symbols declared with
5582 return (TARGET_NORMAL_MODE
5583 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0);
5587 return (TARGET_NORMAL_MODE
5589 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
5591 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
5594 return TARGET_NORMAL_MODE;
5602 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5603 locations that can be accessed as a 16-bit word. */
5606 byte_accesses_mergeable_p (rtx addr1, rtx addr2)
5608 HOST_WIDE_INT offset1, offset2;
5616 else if (GET_CODE (addr1) == PLUS
5617 && REG_P (XEXP (addr1, 0))
5618 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
5620 reg1 = XEXP (addr1, 0);
5621 offset1 = INTVAL (XEXP (addr1, 1));
5631 else if (GET_CODE (addr2) == PLUS
5632 && REG_P (XEXP (addr2, 0))
5633 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
5635 reg2 = XEXP (addr2, 0);
5636 offset2 = INTVAL (XEXP (addr2, 1));
5641 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
5642 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
5644 && offset1 + 1 == offset2)
5650 /* Return nonzero if we have the same comparison insn as I3 two insns
5651 before I3. I3 is assumed to be a comparison insn. */
5654 same_cmp_preceding_p (rtx i3)
5658 /* Make sure we have a sequence of three insns. */
5659 i2 = prev_nonnote_insn (i3);
5662 i1 = prev_nonnote_insn (i2);
5666 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5667 && any_condjump_p (i2) && onlyjump_p (i2));
5670 /* Return nonzero if we have the same comparison insn as I1 two insns
5671 after I1. I1 is assumed to be a comparison insn. */
5674 same_cmp_following_p (rtx i1)
5678 /* Make sure we have a sequence of three insns. */
5679 i2 = next_nonnote_insn (i1);
5682 i3 = next_nonnote_insn (i2);
5686 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
5687 && any_condjump_p (i2) && onlyjump_p (i2));
5690 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5691 (or pops) N registers. OPERANDS are assumed to be an array of
5695 h8300_regs_ok_for_stm (int n, rtx operands[])
5700 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
5701 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
5702 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5));
5704 return ((REGNO (operands[0]) == 0
5705 && REGNO (operands[1]) == 1
5706 && REGNO (operands[2]) == 2)
5707 || (REGNO (operands[0]) == 4
5708 && REGNO (operands[1]) == 5
5709 && REGNO (operands[2]) == 6));
5712 return (REGNO (operands[0]) == 0
5713 && REGNO (operands[1]) == 1
5714 && REGNO (operands[2]) == 2
5715 && REGNO (operands[3]) == 3);
5721 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5724 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5725 unsigned int new_reg)
5727 /* Interrupt functions can only use registers that have already been
5728 saved by the prologue, even if they would normally be
5731 if (h8300_current_function_interrupt_function_p ()
5732 && !df_regs_ever_live_p (new_reg))
5738 /* Returns true if register REGNO is safe to be allocated as a scratch
5739 register in the current function. */
5742 h8300_hard_regno_scratch_ok (unsigned int regno)
5744 if (h8300_current_function_interrupt_function_p ()
5745 && ! WORD_REG_USED (regno))
5752 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5755 h8300_rtx_ok_for_base_p (rtx x, int strict)
5757 /* Strip off SUBREG if any. */
5758 if (GET_CODE (x) == SUBREG)
5763 ? REG_OK_FOR_BASE_STRICT_P (x)
5764 : REG_OK_FOR_BASE_NONSTRICT_P (x)));
5767 /* Return nozero if X is a legitimate address. On the H8/300, a
5768 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5769 CONSTANT_ADDRESS. */
5772 h8300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
5774 /* The register indirect addresses like @er0 is always valid. */
5775 if (h8300_rtx_ok_for_base_p (x, strict))
5778 if (CONSTANT_ADDRESS_P (x))
5782 && ( GET_CODE (x) == PRE_INC
5783 || GET_CODE (x) == PRE_DEC
5784 || GET_CODE (x) == POST_INC
5785 || GET_CODE (x) == POST_DEC)
5786 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict))
5789 if (GET_CODE (x) == PLUS
5790 && CONSTANT_ADDRESS_P (XEXP (x, 1))
5791 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0),
5798 /* Worker function for HARD_REGNO_NREGS.
5800 We pretend the MAC register is 32bits -- we don't have any data
5801 types on the H8 series to handle more than 32bits. */
5804 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED, enum machine_mode mode)
5806 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5809 /* Worker function for HARD_REGNO_MODE_OK. */
5812 h8300_hard_regno_mode_ok (int regno, enum machine_mode mode)
5815 /* If an even reg, then anything goes. Otherwise the mode must be
5817 return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
5819 /* MAC register can only be of SImode. Otherwise, anything
5821 return regno == MAC_REG ? mode == SImode : 1;
5824 /* Perform target dependent optabs initialization. */
5826 h8300_init_libfuncs (void)
5828 set_optab_libfunc (smul_optab, HImode, "__mulhi3");
5829 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
5830 set_optab_libfunc (udiv_optab, HImode, "__udivhi3");
5831 set_optab_libfunc (smod_optab, HImode, "__modhi3");
5832 set_optab_libfunc (umod_optab, HImode, "__umodhi3");
5835 /* Worker function for TARGET_FUNCTION_VALUE.
5837 On the H8 the return value is in R0/R1. */
5840 h8300_function_value (const_tree ret_type,
5841 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
5842 bool outgoing ATTRIBUTE_UNUSED)
5844 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG);
5847 /* Worker function for TARGET_LIBCALL_VALUE.
5849 On the H8 the return value is in R0/R1. */
5852 h8300_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5854 return gen_rtx_REG (mode, R0_REG);
5857 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5859 On the H8, R0 is the only register thus used. */
5862 h8300_function_value_regno_p (const unsigned int regno)
5864 return (regno == R0_REG);
5867 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5870 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5872 return (TYPE_MODE (type) == BLKmode
5873 || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
5876 /* We emit the entire trampoline here. Depending on the pointer size,
5877 we use a different trampoline.
5881 1 0000 7903xxxx mov.w #0x1234,r3
5882 2 0004 5A00xxxx jmp @0x1234
5887 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
5888 3 0006 5Axxxxxx jmp @0x123456
5893 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
5895 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
5898 if (Pmode == HImode)
5900 mem = adjust_address (m_tramp, HImode, 0);
5901 emit_move_insn (mem, GEN_INT (0x7903));
5902 mem = adjust_address (m_tramp, Pmode, 2);
5903 emit_move_insn (mem, cxt);
5904 mem = adjust_address (m_tramp, HImode, 4);
5905 emit_move_insn (mem, GEN_INT (0x5a00));
5906 mem = adjust_address (m_tramp, Pmode, 6);
5907 emit_move_insn (mem, fnaddr);
5913 mem = adjust_address (m_tramp, HImode, 0);
5914 emit_move_insn (mem, GEN_INT (0x7a03));
5915 mem = adjust_address (m_tramp, Pmode, 2);
5916 emit_move_insn (mem, cxt);
5918 tem = copy_to_reg (fnaddr);
5919 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff)));
5920 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000)));
5921 mem = adjust_address (m_tramp, SImode, 6);
5922 emit_move_insn (mem, tem);
5926 /* Initialize the GCC target structure. */
5927 #undef TARGET_ATTRIBUTE_TABLE
5928 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
5930 #undef TARGET_ASM_ALIGNED_HI_OP
5931 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
5933 #undef TARGET_ASM_FILE_START
5934 #define TARGET_ASM_FILE_START h8300_file_start
5935 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
5936 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
5938 #undef TARGET_ASM_FILE_END
5939 #define TARGET_ASM_FILE_END h8300_file_end
5941 #undef TARGET_PRINT_OPERAND
5942 #define TARGET_PRINT_OPERAND h8300_print_operand
5943 #undef TARGET_PRINT_OPERAND_ADDRESS
5944 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
5945 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
5946 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
5948 #undef TARGET_ENCODE_SECTION_INFO
5949 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
5951 #undef TARGET_INSERT_ATTRIBUTES
5952 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
5954 #undef TARGET_REGISTER_MOVE_COST
5955 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
5957 #undef TARGET_RTX_COSTS
5958 #define TARGET_RTX_COSTS h8300_rtx_costs
5960 #undef TARGET_INIT_LIBFUNCS
5961 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
5963 #undef TARGET_FUNCTION_VALUE
5964 #define TARGET_FUNCTION_VALUE h8300_function_value
5966 #undef TARGET_LIBCALL_VALUE
5967 #define TARGET_LIBCALL_VALUE h8300_libcall_value
5969 #undef TARGET_FUNCTION_VALUE_REGNO_P
5970 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
5972 #undef TARGET_RETURN_IN_MEMORY
5973 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
5975 #undef TARGET_FUNCTION_ARG
5976 #define TARGET_FUNCTION_ARG h8300_function_arg
5978 #undef TARGET_FUNCTION_ARG_ADVANCE
5979 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
5981 #undef TARGET_MACHINE_DEPENDENT_REORG
5982 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
5984 #undef TARGET_HARD_REGNO_SCRATCH_OK
5985 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
5987 #undef TARGET_LEGITIMATE_ADDRESS_P
5988 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
5990 #undef TARGET_DEFAULT_TARGET_FLAGS
5991 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
5993 #undef TARGET_CAN_ELIMINATE
5994 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
5996 #undef TARGET_CONDITIONAL_REGISTER_USAGE
5997 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
5999 #undef TARGET_TRAMPOLINE_INIT
6000 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6002 #undef TARGET_OPTION_OVERRIDE
6003 #define TARGET_OPTION_OVERRIDE h8300_option_override
6005 #undef TARGET_OPTION_OPTIMIZATION_TABLE
6006 #define TARGET_OPTION_OPTIMIZATION_TABLE h8300_option_optimization_table
6008 #undef TARGET_EXCEPT_UNWIND_INFO
6009 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
6011 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6012 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6014 struct gcc_target targetm = TARGET_INITIALIZER;