1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "target-def.h"
46 /* Forward declarations. */
47 static int h8300_interrupt_function_p PARAMS ((tree));
48 static int h8300_monitor_function_p PARAMS ((tree));
49 static int h8300_os_task_function_p PARAMS ((tree));
50 static void dosize PARAMS ((FILE *, const char *, unsigned int));
51 static int round_frame_size PARAMS ((int));
52 static unsigned int compute_saved_regs PARAMS ((void));
53 static void push PARAMS ((FILE *, int));
54 static void pop PARAMS ((FILE *, int));
55 static const char *cond_string PARAMS ((enum rtx_code));
56 static int h8300_valid_decl_attribute PARAMS ((tree, tree, tree, tree));
57 static void h8300_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
58 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
59 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
61 /* CPU_TYPE, says what cpu we're compiling for. */
64 /* True if the current function is an interrupt handler
65 (either via #pragma or an attribute specification). */
66 int interrupt_handler;
68 /* True if the current function is an OS Task
69 (via an attribute specification). */
72 /* True if the current function is a monitor
73 (via an attribute specification). */
76 /* True if a #pragma saveall has been seen for the current function. */
79 static const char *const names_big[] =
80 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
82 static const char *const names_extended[] =
83 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
85 static const char *const names_upper_extended[] =
86 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
88 /* Points to one of the above. */
89 /* ??? The above could be put in an array indexed by CPU_TYPE. */
90 const char * const *h8_reg_names;
92 /* Various operations needed by the following, indexed by CPU_TYPE. */
94 static const char *const h8_push_ops[2] = { "push", "push.l" };
95 static const char *const h8_pop_ops[2] = { "pop", "pop.l" };
96 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
98 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
100 /* Initialize the GCC target structure. */
101 #undef TARGET_VALID_DECL_ATTRIBUTE
102 #define TARGET_VALID_DECL_ATTRIBUTE h8300_valid_decl_attribute
104 #undef TARGET_ASM_FUNCTION_PROLOGUE
105 #define TARGET_ASM_FUNCTION_PROLOGUE h8300_output_function_prologue
106 #undef TARGET_ASM_FUNCTION_EPILOGUE
107 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
109 struct gcc_target targetm = TARGET_INITIALIZER;
111 /* Initialize various cpu specific globals at start up. */
118 cpu_type = (int) CPU_H8300;
119 h8_reg_names = names_big;
123 /* For this we treat the H8/300H and H8/S the same. */
124 cpu_type = (int) CPU_H8300H;
125 h8_reg_names = names_extended;
127 h8_push_op = h8_push_ops[cpu_type];
128 h8_pop_op = h8_pop_ops[cpu_type];
129 h8_mov_op = h8_mov_ops[cpu_type];
131 if (!TARGET_H8300S && TARGET_MAC)
133 error ("-ms2600 is used without -ms.");
143 static const char *const names_small[] =
144 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
145 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
147 return names_small[REGNO (x) * 2 + b];
150 /* REGNO must be saved/restored across calls if this macro is true. */
152 #define WORD_REG_USED(regno) \
154 /* No need to save registers if this function will not return. */\
155 && ! TREE_THIS_VOLATILE (current_function_decl) \
157 /* Save any call saved register that was used. */ \
158 || (regs_ever_live[regno] && !call_used_regs[regno]) \
159 /* Save the frame pointer if it was used. */ \
160 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno])\
161 /* Save any register used in an interrupt handler. */ \
162 || (interrupt_handler && regs_ever_live[regno]) \
163 /* Save call clobbered registers in non-leaf interrupt \
165 || (interrupt_handler \
166 && call_used_regs[regno] \
167 && !current_function_is_leaf)))
169 /* Output assembly language to FILE for the operation OP with operand size
170 SIZE to adjust the stack pointer. */
173 dosize (file, op, size)
178 /* On the H8/300H and H8/S, for sizes <= 8 bytes, it is as good or
179 better to use adds/subs insns rather than add.l/sub.l with an
182 Also, on the H8/300, if we don't have a temporary to hold the
183 size of the frame in the prologue, we simply emit a sequence of
184 subs since this shouldn't happen often. */
185 if ((TARGET_H8300 && size <= 4)
186 || ((TARGET_H8300H || TARGET_H8300S) && size <= 8)
187 || (TARGET_H8300 && current_function_needs_context
188 && ! strcmp (op, "sub")))
190 unsigned HOST_WIDE_INT amount;
192 /* Try different amounts in descending order. */
193 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
197 for (; size >= amount; size -= amount)
198 fprintf (file, "\t%ss\t#%d,sp\n", op, amount);
204 fprintf (file, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size, op);
206 fprintf (file, "\t%s.l\t#%d,sp\n", op, size);
210 /* Round up frame size SIZE. */
213 round_frame_size (size)
216 return (size + STACK_BOUNDARY / 8 - 1) & -STACK_BOUNDARY / 8;
219 /* Compute which registers to push/pop.
220 Return a bit vector of registers. */
223 compute_saved_regs ()
225 unsigned int saved_regs = 0;
228 /* Construct a bit vector of registers to be pushed/popped. */
229 for (regno = 0; regno <= 6; regno++)
231 if (WORD_REG_USED (regno))
232 saved_regs |= 1 << regno;
235 /* Don't push/pop the frame pointer as it is treated separately. */
236 if (frame_pointer_needed)
237 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
242 /* Output assembly language code to push register RN. */
249 fprintf (file, "\t%s\t%s\n", h8_push_op, h8_reg_names[rn]);
252 /* Output assembly language code to pop register RN. */
259 fprintf (file, "\t%s\t%s\n", h8_pop_op, h8_reg_names[rn]);
262 /* This is what the stack looks like after the prolog of
263 a function with a frame has been set up:
269 <saved registers> <- sp
271 This is what the stack looks like after the prolog of
272 a function which doesn't have a frame:
277 <saved registers> <- sp
280 /* Output assembly language code for the function prologue. */
283 h8300_output_function_prologue (file, size)
287 int fsize = round_frame_size (size);
292 /* Note a function with the interrupt attribute and set interrupt_handler
294 if (h8300_interrupt_function_p (current_function_decl))
295 interrupt_handler = 1;
297 /* If the current function has the OS_Task attribute set, then
298 we have a naked prologue. */
299 if (h8300_os_task_function_p (current_function_decl))
301 fprintf (file, ";OS_Task prologue\n");
306 if (h8300_monitor_function_p (current_function_decl))
308 /* My understanding of monitor functions is they act just
309 like interrupt functions, except the prologue must
311 fprintf (file, ";monitor prologue\n");
312 interrupt_handler = 1;
316 fprintf (file, "\tsubs\t#2,sp\n");
318 fprintf (file, "\tstc\tccr,r0l\n");
319 fprintf (file, "\tmov.b\tr0l,@(2,sp)\n");
321 fprintf (file, "\torc\t#128,ccr\n");
323 else if (TARGET_H8300H)
326 fprintf (file, "\tstc\tccr,r0l\n");
327 fprintf (file, "\tmov.b\tr0l,@(4,sp)\n");
329 fprintf (file, "\torc\t#128,ccr\n");
331 else if (TARGET_H8300S)
333 fprintf (file, "\tstc\texr,@-sp\n");
335 fprintf (file, "\tstc\tccr,r0l\n");
336 fprintf (file, "\tmov.b\tr0l,@(6,sp)\n");
338 fprintf (file, "\torc\t#128,ccr\n");
344 if (frame_pointer_needed)
347 push (file, FRAME_POINTER_REGNUM);
348 fprintf (file, "\t%s\t%s,%s\n", h8_mov_op,
349 h8_reg_names[STACK_POINTER_REGNUM],
350 h8_reg_names[FRAME_POINTER_REGNUM]);
353 /* Leave room for locals. */
354 dosize (file, "sub", fsize);
356 /* Push the rest of the registers in ascending order. */
357 saved_regs = compute_saved_regs ();
358 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
363 if (saved_regs & (1 << regno))
367 /* See how many registers we can push at the same time. */
368 if ((regno == 0 || regno == 4)
369 && ((saved_regs >> regno) & 0x0f) == 0x0f)
372 else if ((regno == 0 || regno == 4)
373 && ((saved_regs >> regno) & 0x07) == 0x07)
376 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
377 && ((saved_regs >> regno) & 0x03) == 0x03)
384 fprintf (file, "\tstm.l\t%s-%s,@-sp\n",
386 h8_reg_names[regno + (n_regs - 1)]);
391 /* Output assembly language code for the function epilogue. */
394 h8300_output_function_epilogue (file, size)
398 int fsize = round_frame_size (size);
400 rtx insn = get_last_insn ();
406 /* OS_Task epilogues are nearly naked -- they just have an
408 fprintf (file, ";OS_task epilogue\n");
409 fprintf (file, "\trts\n");
413 /* Monitor epilogues are the same as interrupt function epilogues.
414 Just make a note that we're in an monitor epilogue. */
416 fprintf (file, ";monitor epilogue\n");
418 /* If the last insn was a BARRIER, we don't have to write any code. */
419 if (GET_CODE (insn) == NOTE)
420 insn = prev_nonnote_insn (insn);
421 if (insn && GET_CODE (insn) == BARRIER)
424 /* Pop the saved registers in descending order. */
425 saved_regs = compute_saved_regs ();
426 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx += n_regs)
428 int regno = (FIRST_PSEUDO_REGISTER - 1) - idx;
431 if (saved_regs & (1 << regno))
435 /* See how many registers we can pop at the same time. */
436 if ((regno == 7 || regno == 3)
437 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
440 else if ((regno == 6 || regno == 2)
441 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
444 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
445 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
452 fprintf (file, "\tldm.l\t@sp+,%s-%s\n",
453 h8_reg_names[regno - (n_regs - 1)],
454 h8_reg_names[regno]);
458 /* Deallocate locals. */
459 dosize (file, "add", fsize);
461 /* Pop frame pointer if we had one. */
462 if (frame_pointer_needed)
463 pop (file, FRAME_POINTER_REGNUM);
465 if (interrupt_handler)
466 fprintf (file, "\trte\n");
468 fprintf (file, "\trts\n");
471 interrupt_handler = 0;
477 /* Output assembly code for the start of the file. */
480 asm_file_start (file)
483 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
484 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
486 fprintf (file, "; -O%d\n", optimize);
488 fprintf (file, "\n\t.h8300h\n");
489 else if (TARGET_H8300S)
490 fprintf (file, "\n\t.h8300s\n");
492 fprintf (file, "\n\n");
493 output_file_directive (file, main_input_filename);
496 /* Output assembly language code for the end of file. */
502 fprintf (file, "\t.end\n");
505 /* Return true if VALUE is a valid constant for constraint 'P'.
506 IE: VALUE is a power of two <= 2**15. */
509 small_power_of_two (value)
512 int power = exact_log2 (value);
513 return power >= 0 && power <= 15;
516 /* Return true if VALUE is a valid constant for constraint 'O', which
517 means that the constant would be ok to use as a bit for a bclr
524 return small_power_of_two ((~value) & 0xff);
527 /* Return true if OP is a valid source operand for an integer move
531 general_operand_src (op, mode)
533 enum machine_mode mode;
535 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
537 return general_operand (op, mode);
540 /* Return true if OP is a valid destination operand for an integer move
541 instruction, excluding those involving pre_modify. */
544 general_operand_dst (op, mode)
546 enum machine_mode mode;
548 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == PRE_DEC)
550 return general_operand (op, mode);
553 /* Return true if OP is a valid destination operand for an integer move
554 instruction, including those involving pre_modify. */
557 general_operand_dst_push (op, mode)
559 enum machine_mode mode;
561 if (push_operand (op, mode))
564 return general_operand_dst (op, mode);
567 /* Return true if OP is a const valid for a bit clear instruction. */
570 o_operand (operand, mode)
572 enum machine_mode mode ATTRIBUTE_UNUSED;
574 return (GET_CODE (operand) == CONST_INT
575 && CONST_OK_FOR_O (INTVAL (operand)));
578 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
581 p_operand (operand, mode)
583 enum machine_mode mode ATTRIBUTE_UNUSED;
585 return (GET_CODE (operand) == CONST_INT
586 && CONST_OK_FOR_P (INTVAL (operand)));
589 /* Return true if OP is a valid call operand. */
592 call_insn_operand (op, mode)
594 enum machine_mode mode ATTRIBUTE_UNUSED;
596 if (GET_CODE (op) == MEM)
598 rtx inside = XEXP (op, 0);
599 if (register_operand (inside, Pmode))
601 if (CONSTANT_ADDRESS_P (inside))
607 /* Return 1 if an addition/subtraction of a constant integer can be
608 transformed into two consecutive adds/subs that are faster than the
609 straightforward way. Otherwise, return 0. */
612 two_insn_adds_subs_operand (op, mode)
614 enum machine_mode mode;
616 if (GET_CODE (op) == CONST_INT)
618 HOST_WIDE_INT value = INTVAL (op);
620 /* Force VALUE to be positive so that we do not have to consider
621 the negative case. */
624 if (TARGET_H8300H || TARGET_H8300S)
626 /* A constant addition/subtraction takes 2 states in QImode,
627 4 states in HImode, and 6 states in SImode. Thus, the
628 only case we can win is when SImode is used, in which
629 case, two adds/subs are used, taking 4 states. */
639 /* A constant addition/subtraction takes 2 states in
640 QImode. It takes 6 states in HImode, requiring the
641 constant to be loaded to a register first, and a lot more
642 in SImode. Thus the only case we can win is when either
643 HImode or SImode is used. */
654 /* Split an add of a small constant into two adds/subs insns. */
657 split_adds_subs (mode, operands)
658 enum machine_mode mode;
661 HOST_WIDE_INT val = INTVAL (operands[1]);
662 rtx reg = operands[0];
663 HOST_WIDE_INT sign = 1;
664 HOST_WIDE_INT amount;
666 /* Force VAL to be positive so that we do not have to consider the
674 /* Try different amounts in descending order. */
675 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
679 for (; val >= amount; val -= amount)
681 rtx tmp = gen_rtx_PLUS (mode, reg, GEN_INT (sign * amount));
682 emit_insn (gen_rtx_SET (VOIDmode, reg, tmp));
689 /* Return true if OP is a valid call operand, and OP represents
690 an operand for a small call (4 bytes instead of 6 bytes). */
693 small_call_insn_operand (op, mode)
695 enum machine_mode mode ATTRIBUTE_UNUSED;
697 if (GET_CODE (op) == MEM)
699 rtx inside = XEXP (op, 0);
701 /* Register indirect is a small call. */
702 if (register_operand (inside, Pmode))
705 /* A call through the function vector is a small
707 if (GET_CODE (inside) == SYMBOL_REF
708 && SYMBOL_REF_FLAG (inside))
711 /* Otherwise it's a large call. */
715 /* Return true if OP is a valid jump operand. */
718 jump_address_operand (op, mode)
720 enum machine_mode mode;
722 if (GET_CODE (op) == REG)
723 return mode == Pmode;
725 if (GET_CODE (op) == MEM)
727 rtx inside = XEXP (op, 0);
728 if (register_operand (inside, Pmode))
730 if (CONSTANT_ADDRESS_P (inside))
736 /* Recognize valid operands for bitfield instructions. */
738 extern int rtx_equal_function_value_matters;
741 bit_operand (op, mode)
743 enum machine_mode mode;
745 /* We can except any general operand, expept that MEM operands must
746 be limited to those that use addresses valid for the 'U' constraint. */
747 if (!general_operand (op, mode))
750 /* Accept any mem during RTL generation. Otherwise, the code that does
751 insv and extzv will think that we can not handle memory. However,
752 to avoid reload problems, we only accept 'U' MEM operands after RTL
753 generation. This means that any named pattern which uses this predicate
754 must force its operands to match 'U' before emitting RTL. */
756 if (GET_CODE (op) == REG)
758 if (GET_CODE (op) == SUBREG)
760 if (!rtx_equal_function_value_matters)
761 /* We're building rtl. */
762 return GET_CODE (op) == MEM;
764 return (GET_CODE (op) == MEM
765 && EXTRA_CONSTRAINT (op, 'U'));
769 bit_memory_operand (op, mode)
771 enum machine_mode mode ATTRIBUTE_UNUSED;
773 return (GET_CODE (op) == MEM
774 && EXTRA_CONSTRAINT (op, 'U'));
777 /* Recognize valid operators for bit test. */
780 eq_operator (x, mode)
782 enum machine_mode mode ATTRIBUTE_UNUSED;
784 return (GET_CODE (x) == EQ || GET_CODE (x) == NE);
787 /* Handle machine specific pragmas for compatibility with existing
788 compilers for the H8/300.
790 pragma saveall generates prolog/epilog code which saves and
791 restores all the registers on function entry.
793 pragma interrupt saves and restores all registers, and exits with
794 an rte instruction rather than an rts. A pointer to a function
795 with this attribute may be safely used in an interrupt vector. */
798 h8300_pr_interrupt (pfile)
799 cpp_reader *pfile ATTRIBUTE_UNUSED;
801 interrupt_handler = 1;
805 h8300_pr_saveall (pfile)
806 cpp_reader *pfile ATTRIBUTE_UNUSED;
811 /* If the next arg with MODE and TYPE is to be passed in a register, return
812 the rtx to represent where it is passed. CUM represents the state after
813 the last argument. NAMED is not used. */
815 static const char *const hand_list[] =
835 /* Return an RTX to represent where a value with mode MODE will be returned
836 from a function. If the result is 0, the argument is pushed. */
839 function_arg (cum, mode, type, named)
840 CUMULATIVE_ARGS *cum;
841 enum machine_mode mode;
849 /* Never pass unnamed arguments in registers. */
853 /* Pass 3 regs worth of data in regs when user asked on the command line. */
854 if (TARGET_QUICKCALL)
857 /* If calling hand written assembler, use 4 regs of args. */
861 const char * const *p;
863 fname = XSTR (cum->libcall, 0);
865 /* See if this libcall is one of the hand coded ones. */
867 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
879 size = int_size_in_bytes (type);
881 size = GET_MODE_SIZE (mode);
883 if (size + cum->nbytes > regpass * UNITS_PER_WORD)
889 switch (cum->nbytes / UNITS_PER_WORD)
892 result = gen_rtx_REG (mode, 0);
895 result = gen_rtx_REG (mode, 1);
898 result = gen_rtx_REG (mode, 2);
901 result = gen_rtx_REG (mode, 3);
912 /* Return the cost of the rtx R with code CODE. */
932 if (TARGET_H8300H || TARGET_H8300S)
953 /* Documentation for the machine specific operand escapes:
955 'A' print rn in H8/300 mode, erN in H8/300H mode
956 'C' print (operand - 2).
957 'E' like s but negative.
958 'F' like t but negative.
959 'G' constant just the negative
960 'M' turn a 'M' constant into its negative mod 2.
961 'P' if operand is incing/decing sp, print .w, otherwise .b.
962 'R' print operand as a byte:8 address if appropriate, else fall back to
964 'S' print operand as a long word
965 'T' print operand as a word
966 'U' if operand is incing/decing sp, print l, otherwise nothing.
967 'V' find the set bit, and print its number.
968 'W' find the clear bit, and print its number.
969 'X' print operand as a byte
970 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
971 If this operand isn't a register, fall back to 'R' handling.
973 'b' print the bit opcode
974 'c' print the ibit opcode
975 'd' bcc if EQ, bcs if NE
976 'e' first word of 32 bit value - if reg, then least reg. if mem
977 then least. if const then most sig word
978 'f' second word of 32 bit value - if reg, then biggest reg. if mem
979 then +2. if const then least sig word
980 'g' bcs if EQ, bcc if NE
981 'j' print operand as condition code.
982 'k' print operand as reverse condition code.
983 's' print as low byte of 16 bit value
984 't' print as high byte of 16 bit value
985 'w' print as low byte of 32 bit value
986 'x' print as 2nd byte of 32 bit value
987 'y' print as 3rd byte of 32 bit value
988 'z' print as msb of 32 bit value
991 /* Return assembly language string which identifies a comparison type. */
1024 /* Print operand X using operand code CODE to assembly language output file
1028 print_operand (file, x, code)
1033 /* This is used for communication between the 'P' and 'U' codes. */
1034 static const char *last_p;
1036 /* This is used for communication between codes V,W,Z and Y. */
1042 if (GET_CODE (x) == REG)
1043 fprintf (file, "%s", h8_reg_names[REGNO (x)]);
1048 fprintf (file, "#%d", INTVAL (x) - 2);
1051 switch (GET_CODE (x))
1054 fprintf (file, "%sl", names_big[REGNO (x)]);
1057 fprintf (file, "#%d", (-INTVAL (x)) & 0xff);
1064 switch (GET_CODE (x))
1067 fprintf (file, "%sh", names_big[REGNO (x)]);
1070 fprintf (file, "#%d", ((-INTVAL (x)) & 0xff00) >> 8);
1077 if (GET_CODE (x) != CONST_INT)
1079 fprintf (file, "#%d", 0xff & (-INTVAL (x)));
1082 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1089 fprintf (file, "#2");
1095 fprintf (file, "#1");
1102 if (REGNO (XEXP (XEXP (x, 0), 0)) == STACK_POINTER_REGNUM)
1105 fprintf (file, ".w");
1110 fprintf (file, ".b");
1114 if (GET_CODE (x) == REG)
1115 fprintf (file, "%s", names_extended[REGNO (x)]);
1120 if (GET_CODE (x) == REG)
1121 fprintf (file, "%s", names_big[REGNO (x)]);
1126 fprintf (file, "%s%s", names_big[REGNO (x)], last_p);
1129 bitint = exact_log2 (INTVAL (x));
1132 fprintf (file, "#%d", bitint & 7);
1135 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1138 fprintf (file, "#%d", bitint & 7);
1142 if (GET_CODE (x) == REG)
1143 fprintf (file, "%s", byte_reg (x, 0));
1150 if (GET_CODE (x) == REG)
1151 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1153 print_operand (file, x, 'R');
1157 bitint = INTVAL (x);
1158 fprintf (file, "#%d", bitint & 7);
1161 switch (GET_CODE (x))
1164 fprintf (file, "bor");
1167 fprintf (file, "bxor");
1170 fprintf (file, "band");
1177 switch (GET_CODE (x))
1180 fprintf (file, "bior");
1183 fprintf (file, "bixor");
1186 fprintf (file, "biand");
1193 switch (GET_CODE (x))
1196 fprintf (file, "bcc");
1199 fprintf (file, "bcs");
1206 switch (GET_CODE (x))
1210 fprintf (file, "%s", names_big[REGNO (x)]);
1212 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1215 print_operand (file, x, 0);
1218 fprintf (file, "#%d", ((INTVAL (x) >> 16) & 0xffff));
1224 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1225 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1226 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1235 switch (GET_CODE (x))
1239 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1241 fprintf (file, "%s", names_big[REGNO (x)]);
1244 x = adjust_address (x, HImode, 2);
1245 print_operand (file, x, 0);
1248 fprintf (file, "#%d", INTVAL (x) & 0xffff);
1254 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1255 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1256 fprintf (file, "#%ld", (val & 0xffff));
1264 switch (GET_CODE (x))
1267 fprintf (file, "bcc");
1270 fprintf (file, "bcs");
1277 asm_fprintf (file, cond_string (GET_CODE (x)));
1280 asm_fprintf (file, cond_string (reverse_condition (GET_CODE (x))));
1283 if (GET_CODE (x) == CONST_INT)
1284 fprintf (file, "#%d", (INTVAL (x)) & 0xff);
1286 fprintf (file, "%s", byte_reg (x, 0));
1289 if (GET_CODE (x) == CONST_INT)
1290 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1292 fprintf (file, "%s", byte_reg (x, 1));
1295 if (GET_CODE (x) != CONST_INT)
1297 fprintf (file, "%d", INTVAL (x));
1300 if (GET_CODE (x) == CONST_INT)
1301 fprintf (file, "#%d", INTVAL (x) & 0xff);
1303 fprintf (file, "%s",
1304 byte_reg (x, TARGET_H8300 ? 2 : 0));
1307 if (GET_CODE (x) == CONST_INT)
1308 fprintf (file, "#%d", (INTVAL (x) >> 8) & 0xff);
1310 fprintf (file, "%s",
1311 byte_reg (x, TARGET_H8300 ? 3 : 1));
1314 if (GET_CODE (x) == CONST_INT)
1315 fprintf (file, "#%d", (INTVAL (x) >> 16) & 0xff);
1317 fprintf (file, "%s", byte_reg (x, 0));
1320 if (GET_CODE (x) == CONST_INT)
1321 fprintf (file, "#%d", (INTVAL (x) >> 24) & 0xff);
1323 fprintf (file, "%s", byte_reg (x, 1));
1328 switch (GET_CODE (x))
1331 switch (GET_MODE (x))
1334 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1335 fprintf (file, "%s", byte_reg (x, 0));
1336 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1337 fprintf (file, "%s", names_big[REGNO (x)]);
1341 fprintf (file, "%s", names_big[REGNO (x)]);
1345 fprintf (file, "%s", names_extended[REGNO (x)]);
1353 fprintf (file, "@");
1354 output_address (XEXP (x, 0));
1356 /* If this is an 'R' operand (reference into the 8-bit
1357 area), then specify a symbolic address as "foo:8",
1358 otherwise if operand is still in eight bit section, use
1360 if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1361 && SYMBOL_REF_FLAG (XEXP (x, 0)))
1362 fprintf (file, (code == 'R' ? ":8" : ":16"));
1363 else if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1364 && TINY_DATA_NAME_P (XSTR (XEXP (x, 0), 0)))
1365 fprintf (file, ":16");
1366 else if ((code == 'R')
1367 && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (x, 0)))
1368 fprintf (file, ":8");
1375 fprintf (file, "#");
1376 print_operand_address (file, x);
1382 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1383 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1384 fprintf (file, "#%ld", val);
1393 /* Output assembly language output for the address ADDR to FILE. */
1396 print_operand_address (file, addr)
1400 switch (GET_CODE (addr))
1403 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1407 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1411 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1415 fprintf (file, "(");
1416 if (GET_CODE (XEXP (addr, 0)) == REG)
1419 print_operand_address (file, XEXP (addr, 1));
1420 fprintf (file, ",");
1421 print_operand_address (file, XEXP (addr, 0));
1426 print_operand_address (file, XEXP (addr, 0));
1427 fprintf (file, "+");
1428 print_operand_address (file, XEXP (addr, 1));
1430 fprintf (file, ")");
1435 /* Since the H8/300 only has 16 bit pointers, negative values are also
1436 those >= 32768. This happens for example with pointer minus a
1437 constant. We don't want to turn (char *p - 2) into
1438 (char *p + 65534) because loop unrolling can build upon this
1439 (IE: char *p + 131068). */
1440 int n = INTVAL (addr);
1442 n = (int) (short) n;
1444 /* ??? Why the special case for -ve values? */
1445 fprintf (file, "-%d", -n);
1447 fprintf (file, "%d", n);
1452 output_addr_const (file, addr);
1457 /* Output all insn addresses and their sizes into the assembly language
1458 output file. This is helpful for debugging whether the length attributes
1459 in the md file are correct. This is not meant to be a user selectable
1463 final_prescan_insn (insn, operand, num_operands)
1464 rtx insn, *operand ATTRIBUTE_UNUSED;
1465 int num_operands ATTRIBUTE_UNUSED;
1467 /* This holds the last insn address. */
1468 static int last_insn_address = 0;
1470 int uid = INSN_UID (insn);
1472 if (TARGET_RTL_DUMP)
1474 fprintf (asm_out_file, "\n****************");
1475 print_rtl (asm_out_file, PATTERN (insn));
1476 fprintf (asm_out_file, "\n");
1479 if (TARGET_ADDRESSES)
1481 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1482 INSN_ADDRESSES (uid) - last_insn_address);
1483 last_insn_address = INSN_ADDRESSES (uid);
1487 /* Prepare for an SI sized move. */
1493 rtx src = operands[1];
1494 rtx dst = operands[0];
1495 if (!reload_in_progress && !reload_completed)
1497 if (!register_operand (dst, GET_MODE (dst)))
1499 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1500 emit_move_insn (tmp, src);
1507 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1508 Define the offset between two registers, one to be eliminated, and
1509 the other its replacement, at the start of a routine. */
1512 initial_offset (from, to)
1517 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1518 offset = UNITS_PER_WORD + frame_pointer_needed * UNITS_PER_WORD;
1519 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1520 offset = frame_pointer_needed * UNITS_PER_WORD;
1525 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1526 if (WORD_REG_USED (regno))
1527 offset += UNITS_PER_WORD;
1529 /* See the comments for get_frame_size. We need to round it up to
1532 offset += ((get_frame_size () + STACK_BOUNDARY / BITS_PER_UNIT - 1)
1533 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
1535 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1536 offset += UNITS_PER_WORD; /* Skip saved PC */
1542 h8300_return_addr_rtx (count, frame)
1549 ret = gen_rtx_MEM (Pmode,
1550 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1551 else if (flag_omit_frame_pointer)
1554 ret = gen_rtx_MEM (Pmode,
1555 memory_address (Pmode,
1556 plus_constant (frame, UNITS_PER_WORD)));
1557 set_mem_alias_set (ret, get_frame_alias_set ());
1561 /* Update the condition code from the insn. */
1564 notice_update_cc (body, insn)
1568 switch (get_attr_cc (insn))
1571 /* Insn does not affect CC at all. */
1575 /* Insn does not change CC, but the 0'th operand has been changed. */
1576 if (cc_status.value1 != 0
1577 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1578 cc_status.value1 = 0;
1582 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1583 The V flag is unusable. The C flag may or may not be known but
1584 that's ok because alter_cond will change tests to use EQ/NE. */
1586 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1587 cc_status.value1 = recog_data.operand[0];
1591 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1592 The C flag may or may not be known but that's ok because
1593 alter_cond will change tests to use EQ/NE. */
1595 cc_status.flags |= CC_NO_CARRY;
1596 cc_status.value1 = recog_data.operand[0];
1600 /* The insn is a compare instruction. */
1602 cc_status.value1 = SET_SRC (body);
1606 /* Insn doesn't leave CC in a usable state. */
1612 /* Recognize valid operators for bit instructions. */
1615 bit_operator (x, mode)
1617 enum machine_mode mode ATTRIBUTE_UNUSED;
1619 enum rtx_code code = GET_CODE (x);
1627 output_logical_op (mode, code, operands)
1628 enum machine_mode mode;
1632 /* Pretend that every byte is affected if both operands are registers. */
1633 unsigned HOST_WIDE_INT intval =
1634 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
1635 ? INTVAL (operands[2]) : 0x55555555);
1636 /* The determinant of the algorithm. If we perform an AND, 0
1637 affects a bit. Otherwise, 1 affects a bit. */
1638 unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
1639 /* The name of an insn. */
1661 /* First, see if we can finish with one insn. */
1662 if ((TARGET_H8300H || TARGET_H8300S)
1663 && ((det & 0x00ff) != 0)
1664 && ((det & 0xff00) != 0))
1666 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
1667 output_asm_insn (insn_buf, operands);
1671 /* Take care of the lower byte. */
1672 if ((det & 0x00ff) != 0)
1674 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
1675 output_asm_insn (insn_buf, operands);
1677 /* Take care of the upper byte. */
1678 if ((det & 0xff00) != 0)
1680 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
1681 output_asm_insn (insn_buf, operands);
1686 /* First, see if we can finish with one insn.
1688 If code is either AND or XOR, we exclude two special cases,
1689 0xffffff00 and 0xffff00ff, because insns like sub.w or neg.w
1690 can do a better job. */
1691 if ((TARGET_H8300H || TARGET_H8300S)
1692 && ((det & 0x0000ffff) != 0)
1693 && ((det & 0xffff0000) != 0)
1694 && (code == IOR || det != 0xffffff00)
1695 && (code == IOR || det != 0xffff00ff))
1697 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
1698 output_asm_insn (insn_buf, operands);
1702 /* Take care of the lower and upper words individually. For
1703 each word, we try different methods in the order of
1705 1) the special insn (in case of AND or XOR),
1706 2) the word-wise insn, and
1707 3) The byte-wise insn. */
1708 if ((TARGET_H8300H || TARGET_H8300S)
1709 && ((det & 0x0000ffff) == 0x0000ffff)
1711 output_asm_insn ((code == AND)
1712 ? "sub.w\t%f0,%f0" : "neg.w\t%f0",
1714 else if ((TARGET_H8300H || TARGET_H8300S)
1715 && ((det & 0x000000ff) != 0)
1716 && ((det & 0x0000ff00) != 0))
1718 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
1719 output_asm_insn (insn_buf, operands);
1723 if ((det & 0x000000ff) != 0)
1725 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
1726 output_asm_insn (insn_buf, operands);
1728 if ((det & 0x0000ff00) != 0)
1730 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
1731 output_asm_insn (insn_buf, operands);
1735 if ((TARGET_H8300H || TARGET_H8300S)
1736 && ((det & 0xffff0000) == 0xffff0000)
1738 output_asm_insn ((code == AND)
1739 ? "sub.w\t%e0,%e0" : "neg.w\t%e0",
1741 else if (TARGET_H8300H || TARGET_H8300S)
1743 if ((det & 0xffff0000) != 0)
1745 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
1746 output_asm_insn (insn_buf, operands);
1751 if ((det & 0x00ff0000) != 0)
1753 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
1754 output_asm_insn (insn_buf, operands);
1756 if ((det & 0xff000000) != 0)
1758 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
1759 output_asm_insn (insn_buf, operands);
1772 We devote a fair bit of code to getting efficient shifts since we can only
1773 shift one bit at a time on the H8/300 and H8/300H and only one or two
1774 bits at a time on the H8/S.
1776 The basic shift methods:
1778 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
1779 this is the default. SHIFT_LOOP
1781 * inlined shifts -- emit straight line code for the shift; this is
1782 used when a straight line shift is about the same size or smaller
1783 than a loop. We allow the inline version to be slightly longer in
1784 some cases as it saves a register. SHIFT_INLINE
1786 * rotate + and -- rotate the value the opposite direction, then
1787 mask off the values we don't need. This is used when only a few
1788 of the bits in the original value will survive in the shifted value.
1789 Again, this is used when it's about the same size or smaller than
1790 a loop. We allow this version to be slightly longer as it is usually
1791 much faster than a loop. SHIFT_ROT_AND
1793 * swap (+ shifts) -- often it's possible to swap bytes/words to
1794 simulate a shift by 8/16. Once swapped a few inline shifts can be
1795 added if the shift count is slightly more than 8 or 16. This is used
1796 when it's about the same size or smaller than a loop. We allow this
1797 version to be slightly longer as it is usually much faster than a loop.
1800 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
1802 Here are some thoughts on what the absolutely positively best code is.
1803 "Best" here means some rational trade-off between code size and speed,
1804 where speed is more preferred but not at the expense of generating 20 insns.
1806 A trailing '*' after the shift count indicates the "best" mode isn't
1809 H8/300 QImode shifts
1810 1-4 - do them inline
1811 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1813 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1814 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1816 H8/300 HImode shifts
1817 1-4 - do them inline
1819 7 - shift 2nd half other way into carry.
1820 copy 1st half into 2nd half
1821 rotate 2nd half other way with carry
1822 rotate 1st half other way (no carry)
1823 mask off bits in 1st half (ASHIFT | LSHIFTRT).
1824 sign extend 1st half (ASHIFTRT)
1825 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1826 9-12 - do shift by 8, inline remaining shifts
1827 13-14* - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1829 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1830 - ASHIFTRT: shll, subx, set other byte
1832 H8/300 SImode shifts
1833 1-2 - do them inline
1835 7* - shift other way once, move bytes into place,
1836 move carry into place (possibly with sign extension)
1837 8 - move bytes into place, zero or sign extend other
1839 15* - shift other way once, move word into place, move carry into place
1840 16 - move word, zero or sign extend other
1842 24* - move bytes into place, zero or sign extend other
1844 28-30* - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1847 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1849 ASHIFTRT: shll top byte, subx, copy to other bytes
1851 H8/300H QImode shifts (same as H8/300 QImode shifts)
1852 1-4 - do them inline
1853 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1855 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1856 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1858 H8/300H HImode shifts
1859 1-4 - do them inline
1861 7 - shift 2nd half other way into carry.
1862 copy 1st half into 2nd half
1863 rotate entire word other way using carry
1864 mask off remaining bits (ASHIFT | LSHIFTRT)
1865 sign extend remaining bits (ASHIFTRT)
1866 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1867 9-12 - do shift by 8, inline remaining shifts
1868 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1870 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1871 - ASHIFTRT: shll, subx, set other byte
1873 H8/300H SImode shifts
1874 (These are complicated by the fact that we don't have byte level access to
1876 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1877 1-4 - do them inline
1879 15* - shift other way once, move word into place, move carry into place
1880 (with sign extension for ASHIFTRT)
1881 16 - move word into place, zero or sign extend other
1882 17-20 - do 16bit shift, then inline remaining shifts
1884 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1885 move word 0 to word 1, zero word 0
1886 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1887 zero word 1, zero byte 1
1888 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1889 sign extend byte 0, sign extend word 0
1890 25-27* - either loop, or
1891 do 24 bit shift, inline rest
1892 28-30 - ASHIFT: rotate 4/3/2, mask
1893 LSHIFTRT: rotate 4/3/2, mask
1895 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1898 1-6 - do them inline
1899 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1900 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1903 1-7 - do them inline
1904 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1905 9-12 - do shift by 8, inline remaining shifts
1906 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1908 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1909 - ASHIFTRT: shll, subx, set other byte
1912 (These are complicated by the fact that we don't have byte level access to
1914 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1915 1-10 - do them inline
1917 15* - shift other way once, move word into place, move carry into place
1918 (with sign extension for ASHIFTRT)
1919 16 - move word into place, zero or sign extend other
1920 17-20 - do 16bit shift, then inline remaining shifts
1922 24* - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1923 move word 0 to word 1, zero word 0
1924 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1925 zero word 1, zero byte 1
1926 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1927 sign extend byte 0, sign extend word 0
1928 25-27* - either loop, or
1929 do 24 bit shift, inline rest
1930 28-30 - ASHIFT: rotate 4/3/2, mask
1931 LSHIFTRT: rotate 4/3/2, mask
1933 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1938 nshift_operator (x, mode)
1940 enum machine_mode mode ATTRIBUTE_UNUSED;
1942 switch (GET_CODE (x))
1954 /* Called from the .md file to emit code to do shifts.
1955 Return a boolean indicating success.
1956 (Currently this is always TRUE). */
1959 expand_a_shift (mode, code, operands)
1960 enum machine_mode mode;
1964 emit_move_insn (operands[0], operands[1]);
1966 /* Need a loop to get all the bits we want - we generate the
1967 code at emit time, but need to allocate a scratch reg now. */
1969 emit_insn (gen_rtx_PARALLEL
1972 gen_rtx_SET (VOIDmode, operands[0],
1973 gen_rtx (code, mode, operands[0],
1975 gen_rtx_CLOBBER (VOIDmode,
1976 gen_rtx_SCRATCH (QImode)))));
1981 /* Shift algorithm determination.
1983 There are various ways of doing a shift:
1984 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1986 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1987 necessary bits into position and then set the rest to zero.
1988 SHIFT_SPECIAL: Hand crafted assembler.
1989 SHIFT_LOOP: If the above methods fail, just loop. */
2000 /* Symbols of the various shifts which can be used as indices. */
2004 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
2007 /* Symbols of the various modes which can be used as indices. */
2011 QIshift, HIshift, SIshift
2014 /* For single bit shift insns, record assembler and what bits of the
2015 condition code are valid afterwards (represented as various CC_FOO
2016 bits, 0 means CC isn't left in a usable state). */
2020 const char *assembler;
2024 /* Assembler instruction shift table.
2026 These tables are used to look up the basic shifts.
2027 They are indexed by cpu, shift_type, and mode. */
2029 static const struct shift_insn shift_one[2][3][3] =
2035 { "shll\t%X0", CC_NO_CARRY },
2036 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2037 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
2039 /* SHIFT_LSHIFTRT */
2041 { "shlr\t%X0", CC_NO_CARRY },
2042 { "shlr\t%t0\n\trotxr\t%s0", 0 },
2043 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2045 /* SHIFT_ASHIFTRT */
2047 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2048 { "shar\t%t0\n\trotxr\t%s0", 0 },
2049 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2056 { "shll.b\t%X0", CC_NO_CARRY },
2057 { "shll.w\t%T0", CC_NO_CARRY },
2058 { "shll.l\t%S0", CC_NO_CARRY }
2060 /* SHIFT_LSHIFTRT */
2062 { "shlr.b\t%X0", CC_NO_CARRY },
2063 { "shlr.w\t%T0", CC_NO_CARRY },
2064 { "shlr.l\t%S0", CC_NO_CARRY }
2066 /* SHIFT_ASHIFTRT */
2068 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2069 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2070 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2075 static const struct shift_insn shift_two[3][3] =
2079 { "shll.b\t#2,%X0", CC_NO_CARRY },
2080 { "shll.w\t#2,%T0", CC_NO_CARRY },
2081 { "shll.l\t#2,%S0", CC_NO_CARRY }
2083 /* SHIFT_LSHIFTRT */
2085 { "shlr.b\t#2,%X0", CC_NO_CARRY },
2086 { "shlr.w\t#2,%T0", CC_NO_CARRY },
2087 { "shlr.l\t#2,%S0", CC_NO_CARRY }
2089 /* SHIFT_ASHIFTRT */
2091 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2092 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2093 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2097 /* Rotates are organized by which shift they'll be used in implementing.
2098 There's no need to record whether the cc is valid afterwards because
2099 it is the AND insn that will decide this. */
2101 static const char *const rotate_one[2][3][3] =
2108 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2111 /* SHIFT_LSHIFTRT */
2114 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2117 /* SHIFT_ASHIFTRT */
2120 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2132 /* SHIFT_LSHIFTRT */
2138 /* SHIFT_ASHIFTRT */
2147 static const char *const rotate_two[3][3] =
2155 /* SHIFT_LSHIFTRT */
2161 /* SHIFT_ASHIFTRT */
2170 /* Shift algorithm. */
2173 /* The number of bits to be shifted by shift1 and shift2. Valid
2174 when ALG is SHIFT_SPECIAL. */
2175 unsigned int remainder;
2177 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2178 const char *special;
2180 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2181 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2184 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2185 or SHIFT_SPECIAL, and REMAINDER is non-zero. */
2188 /* Valid CC flags. */
2192 static enum shift_alg get_shift_alg PARAMS ((enum shift_type,
2193 enum shift_mode, int,
2194 struct shift_info *));
2196 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2197 best algorithm for doing the shift. The assembler code is stored
2198 in the pointers in INFO. We don't achieve maximum efficiency in
2199 all cases, but the hooks are here to do so.
2201 For now we just use lots of switch statements. Since we don't even come
2202 close to supporting all the cases, this is simplest. If this function ever
2203 gets too big, perhaps resort to a more table based lookup. Of course,
2204 at this point you may just wish to do it all in rtl.
2206 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
2207 1,2,3,4 will be inlined (1,2 for SI). */
2209 static enum shift_alg
2210 get_shift_alg (shift_type, shift_mode, count, info)
2211 enum shift_type shift_type;
2212 enum shift_mode shift_mode;
2214 struct shift_info *info;
2216 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
2217 It is up to the caller to know that looping clobbers cc. */
2218 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2220 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2222 info->shift2 = NULL;
2223 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2225 /* Now look for cases we want to optimize. */
2231 return SHIFT_INLINE;
2234 /* Shift by 5/6 are only 3 insns on the H8/S, so it's just as
2235 fast as SHIFT_ROT_AND, plus CC is valid. */
2236 if (TARGET_H8300S && count <= 6)
2237 return SHIFT_INLINE;
2239 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2240 through the entire value. */
2241 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2243 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2244 info->cc_valid_p = 0;
2245 return SHIFT_SPECIAL;
2248 /* Other ASHIFTRTs are too much of a pain. */
2249 if (shift_type == SHIFT_ASHIFTRT)
2252 /* Other shifts by 5, 6, or 7 bits use SHIFT_ROT_AND. */
2253 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2255 info->shift2 = rotate_two[shift_type][shift_mode];
2256 info->cc_valid_p = 0;
2257 return SHIFT_ROT_AND;
2262 return SHIFT_INLINE;
2263 else if (TARGET_H8300S && count <= 7)
2264 return SHIFT_INLINE;
2265 else if (count == 7)
2267 if (shift_type == SHIFT_ASHIFT && TARGET_H8300)
2269 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2270 info->cc_valid_p = 0;
2271 return SHIFT_SPECIAL;
2274 if (shift_type == SHIFT_ASHIFT && TARGET_H8300H)
2276 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2277 info->cc_valid_p = 0;
2278 return SHIFT_SPECIAL;
2281 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300)
2283 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2284 info->cc_valid_p = 0;
2285 return SHIFT_SPECIAL;
2288 if (shift_type == SHIFT_LSHIFTRT && TARGET_H8300H)
2290 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2291 info->cc_valid_p = 0;
2292 return SHIFT_SPECIAL;
2295 if (shift_type == SHIFT_ASHIFTRT)
2297 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2298 info->cc_valid_p = 0;
2299 return SHIFT_SPECIAL;
2302 else if (count == 8)
2307 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2308 info->cc_valid_p = 0;
2309 return SHIFT_SPECIAL;
2310 case SHIFT_LSHIFTRT:
2311 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2312 info->cc_valid_p = 0;
2313 return SHIFT_SPECIAL;
2314 case SHIFT_ASHIFTRT:
2316 info->special = "mov.b\t%t0,%s0\n\tshll\t%t0\n\tsubx\t%t0,%t0";
2318 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2319 info->cc_valid_p = 0;
2320 return SHIFT_SPECIAL;
2323 else if (count == 9)
2328 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0";
2329 info->cc_valid_p = 0;
2330 return SHIFT_SPECIAL;
2331 case SHIFT_LSHIFTRT:
2332 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0";
2333 info->cc_valid_p = 0;
2334 return SHIFT_SPECIAL;
2335 case SHIFT_ASHIFTRT:
2337 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0";
2339 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0";
2340 info->cc_valid_p = 0;
2341 return SHIFT_SPECIAL;
2344 else if (count == 10)
2350 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0";
2352 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2353 info->cc_valid_p = 0;
2354 return SHIFT_SPECIAL;
2355 case SHIFT_LSHIFTRT:
2357 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0";
2359 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2360 info->cc_valid_p = 0;
2361 return SHIFT_SPECIAL;
2362 case SHIFT_ASHIFTRT:
2364 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2365 else if (TARGET_H8300H)
2366 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2367 else if (TARGET_H8300S)
2368 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0";
2369 info->cc_valid_p = 0;
2370 return SHIFT_SPECIAL;
2373 else if (count == 11)
2379 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t%t0";
2381 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2382 info->cc_valid_p = 0;
2383 return SHIFT_SPECIAL;
2384 case SHIFT_LSHIFTRT:
2386 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t%s0";
2388 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2389 info->cc_valid_p = 0;
2390 return SHIFT_SPECIAL;
2391 case SHIFT_ASHIFTRT:
2393 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2394 else if (TARGET_H8300H)
2395 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2396 else if (TARGET_H8300S)
2397 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t%s0";
2398 info->cc_valid_p = 0;
2399 return SHIFT_SPECIAL;
2402 else if (count == 12)
2408 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t#2,%t0\n\tshal.b\t#2,%t0";
2410 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0\n\tshal.b\t%t0";
2411 info->cc_valid_p = 0;
2412 return SHIFT_SPECIAL;
2413 case SHIFT_LSHIFTRT:
2415 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t#2,%s0\n\tshlr.b\t#2,%s0";
2417 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0\n\tshlr.b\t%s0";
2418 info->cc_valid_p = 0;
2419 return SHIFT_SPECIAL;
2420 case SHIFT_ASHIFTRT:
2422 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2423 else if (TARGET_H8300H)
2424 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0\n\tshar.b\t%s0";
2425 else if (TARGET_H8300S)
2426 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0\n\tshar.b\t#2,%s0\n\tshar.b\t#2,%s0";
2427 info->cc_valid_p = 0;
2428 return SHIFT_SPECIAL;
2431 else if ((!TARGET_H8300 && (count == 13 || count == 14))
2434 if (count == 15 && shift_type == SHIFT_ASHIFTRT)
2436 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
2437 info->cc_valid_p = 0;
2438 return SHIFT_SPECIAL;
2440 else if (shift_type != SHIFT_ASHIFTRT)
2442 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2444 info->shift2 = rotate_two[shift_type][shift_mode];
2446 info->shift2 = NULL;
2447 info->cc_valid_p = 0;
2448 return SHIFT_ROT_AND;
2454 if (count <= (TARGET_H8300 ? 2 : 4))
2455 return SHIFT_INLINE;
2456 else if (TARGET_H8300S && count <= 10)
2457 return SHIFT_INLINE;
2458 else if (count == 8 && TARGET_H8300)
2463 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
2464 info->cc_valid_p = 0;
2465 return SHIFT_SPECIAL;
2466 case SHIFT_LSHIFTRT:
2467 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
2468 info->cc_valid_p = 0;
2469 return SHIFT_SPECIAL;
2470 case SHIFT_ASHIFTRT:
2471 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
2472 info->cc_valid_p = 0;
2473 return SHIFT_SPECIAL;
2476 else if (count == 8 && !TARGET_H8300)
2481 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
2482 info->cc_valid_p = 0;
2483 return SHIFT_SPECIAL;
2484 case SHIFT_LSHIFTRT:
2485 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
2486 info->cc_valid_p = 0;
2487 return SHIFT_SPECIAL;
2488 case SHIFT_ASHIFTRT:
2489 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
2490 info->cc_valid_p = 0;
2491 return SHIFT_SPECIAL;
2494 else if (count == 16)
2499 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2500 info->cc_valid_p = 0;
2501 return SHIFT_SPECIAL;
2502 case SHIFT_LSHIFTRT:
2503 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
2504 info->cc_valid_p = 0;
2505 return SHIFT_SPECIAL;
2506 case SHIFT_ASHIFTRT:
2508 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
2510 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
2511 info->cc_valid_p = 0;
2512 return SHIFT_SPECIAL;
2515 else if (count == 17 && !TARGET_H8300)
2520 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0";
2521 info->cc_valid_p = 0;
2522 return SHIFT_SPECIAL;
2523 case SHIFT_LSHIFTRT:
2524 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0";
2525 info->cc_valid_p = 0;
2526 return SHIFT_SPECIAL;
2527 case SHIFT_ASHIFTRT:
2528 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0";
2529 info->cc_valid_p = 0;
2530 return SHIFT_SPECIAL;
2533 else if (count == 18 && !TARGET_H8300)
2539 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0";
2541 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2542 info->cc_valid_p = 0;
2543 return SHIFT_SPECIAL;
2544 case SHIFT_LSHIFTRT:
2546 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0";
2548 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2549 info->cc_valid_p = 0;
2550 return SHIFT_SPECIAL;
2551 case SHIFT_ASHIFTRT:
2553 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0";
2555 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2556 info->cc_valid_p = 0;
2557 return SHIFT_SPECIAL;
2560 else if (count == 19 && !TARGET_H8300)
2566 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t%S0";
2568 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t%S0\n\tshll.l\t%S0\n\tshll.l\t%S0";
2569 info->cc_valid_p = 0;
2570 return SHIFT_SPECIAL;
2571 case SHIFT_LSHIFTRT:
2573 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t%S0";
2575 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t%S0\n\tshlr.l\t%S0\n\tshlr.l\t%S0";
2576 info->cc_valid_p = 0;
2577 return SHIFT_SPECIAL;
2578 case SHIFT_ASHIFTRT:
2580 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t%S0";
2582 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0\n\tshar.l\t%S0";
2583 info->cc_valid_p = 0;
2584 return SHIFT_SPECIAL;
2587 else if (count == 20 && TARGET_H8300S)
2592 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0\n\tshll.l\t#2,%S0\n\tshll.l\t#2,%S0";
2593 info->cc_valid_p = 0;
2594 return SHIFT_SPECIAL;
2595 case SHIFT_LSHIFTRT:
2596 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0\n\tshlr.l\t#2,%S0\n\tshlr.l\t#2,%S0";
2597 info->cc_valid_p = 0;
2598 return SHIFT_SPECIAL;
2599 case SHIFT_ASHIFTRT:
2600 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0\n\tshar.l\t#2,%S0\n\tshar.l\t#2,%S0";
2601 info->cc_valid_p = 0;
2602 return SHIFT_SPECIAL;
2605 else if (count == 24 && !TARGET_H8300)
2610 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
2611 info->cc_valid_p = 0;
2612 return SHIFT_SPECIAL;
2613 case SHIFT_LSHIFTRT:
2614 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
2615 info->cc_valid_p = 0;
2616 return SHIFT_SPECIAL;
2617 case SHIFT_ASHIFTRT:
2618 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
2619 info->cc_valid_p = 0;
2620 return SHIFT_SPECIAL;
2623 else if (count >= 28 && count <= 30 && !TARGET_H8300)
2625 if (shift_type == SHIFT_ASHIFTRT)
2631 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2633 info->shift2 = rotate_two[shift_type][shift_mode];
2635 info->shift2 = NULL;
2636 info->cc_valid_p = 0;
2637 return SHIFT_ROT_AND;
2640 else if (count == 31)
2642 if (shift_type == SHIFT_ASHIFTRT)
2645 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2647 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
2648 info->cc_valid_p = 0;
2649 return SHIFT_SPECIAL;
2655 if (shift_type == SHIFT_ASHIFT)
2656 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
2658 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
2659 info->cc_valid_p = 0;
2660 return SHIFT_SPECIAL;
2664 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2666 info->shift2 = rotate_two[shift_type][shift_mode];
2668 info->shift2 = NULL;
2669 info->cc_valid_p = 0;
2670 return SHIFT_ROT_AND;
2680 /* No fancy method is available. Just loop. */
2684 /* Emit the assembler code for doing shifts. */
2687 emit_a_shift (insn, operands)
2688 rtx insn ATTRIBUTE_UNUSED;
2691 static int loopend_lab;
2692 rtx shift = operands[3];
2693 enum machine_mode mode = GET_MODE (shift);
2694 enum rtx_code code = GET_CODE (shift);
2695 enum shift_type shift_type;
2696 enum shift_mode shift_mode;
2697 struct shift_info info;
2704 shift_mode = QIshift;
2707 shift_mode = HIshift;
2710 shift_mode = SIshift;
2719 shift_type = SHIFT_ASHIFTRT;
2722 shift_type = SHIFT_LSHIFTRT;
2725 shift_type = SHIFT_ASHIFT;
2731 if (GET_CODE (operands[2]) != CONST_INT)
2733 /* Indexing by reg, so have to loop and test at top. */
2734 output_asm_insn ("mov.b %X2,%X4", operands);
2735 fprintf (asm_out_file, "\tble .Lle%d\n", loopend_lab);
2737 /* Get the assembler code to do one shift. */
2738 get_shift_alg (shift_type, shift_mode, 1, &info);
2740 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2741 output_asm_insn (info.shift1, operands);
2742 output_asm_insn ("add #0xff,%X4", operands);
2743 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2744 fprintf (asm_out_file, ".Lle%d:\n", loopend_lab);
2750 int n = INTVAL (operands[2]);
2753 /* If the count is negative, make it 0. */
2756 /* If the count is too big, truncate it.
2757 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2758 do the intuitive thing. */
2759 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
2760 n = GET_MODE_BITSIZE (mode);
2762 alg = get_shift_alg (shift_type, shift_mode, n, &info);
2767 /* Emit two bit shifts first. */
2768 while (n > 1 && info.shift2 != NULL)
2770 output_asm_insn (info.shift2, operands);
2774 /* Now emit one bit shifts for any residual. */
2777 output_asm_insn (info.shift1, operands);
2781 /* Keep track of CC. */
2782 if (info.cc_valid_p)
2784 cc_status.value1 = operands[0];
2785 cc_status.flags |= info.cc_valid_p;
2791 int m = GET_MODE_BITSIZE (mode) - n;
2792 int mask = (shift_type == SHIFT_ASHIFT
2793 ? ((1 << (GET_MODE_BITSIZE (mode) - n)) - 1) << n
2794 : (1 << (GET_MODE_BITSIZE (mode) - n)) - 1);
2797 /* Not all possibilities of rotate are supported. They shouldn't
2798 be generated, but let's watch for 'em. */
2799 if (info.shift1 == 0)
2802 /* Emit two bit rotates first. */
2803 while (m > 1 && info.shift2 != NULL)
2805 output_asm_insn (info.shift2, operands);
2809 /* Now single bit rotates for any residual. */
2812 output_asm_insn (info.shift1, operands);
2816 /* Now mask off the high bits. */
2822 sprintf (insn_buf, "and\t#%d,%%X0", mask);
2823 cc_status.value1 = operands[0];
2824 cc_status.flags |= CC_NO_CARRY;
2827 sprintf (insn_buf, "and\t#%d,%%s0\n\tand\t#%d,%%t0",
2828 mask & 255, mask >> 8);
2838 sprintf (insn_buf, "and.%c\t#%d,%%%c0",
2839 "bwl"[shift_mode], mask,
2840 mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
2841 cc_status.value1 = operands[0];
2842 cc_status.flags |= CC_NO_CARRY;
2844 output_asm_insn (insn_buf, operands);
2849 output_asm_insn (info.special, operands);
2853 /* A loop to shift by a "large" constant value.
2854 If we have shift-by-2 insns, use them. */
2855 if (info.shift2 != NULL)
2857 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
2858 names_big[REGNO (operands[4])]);
2859 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2860 output_asm_insn (info.shift2, operands);
2861 output_asm_insn ("add #0xff,%X4", operands);
2862 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2864 output_asm_insn (info.shift1, operands);
2868 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
2869 names_big[REGNO (operands[4])]);
2870 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
2871 output_asm_insn (info.shift1, operands);
2872 output_asm_insn ("add #0xff,%X4", operands);
2873 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
2883 /* A rotation by a non-constant will cause a loop to be generated, in
2884 which a rotation by one bit is used. A rotation by a constant,
2885 including the one in the loop, will be taken care of by
2886 emit_a_rotate () at the insn emit time. */
2889 expand_a_rotate (code, operands)
2893 rtx dst = operands[0];
2894 rtx src = operands[1];
2895 rtx rotate_amount = operands[2];
2896 enum machine_mode mode = GET_MODE (dst);
2899 /* We rotate in place. */
2900 emit_move_insn (dst, src);
2902 if (GET_CODE (rotate_amount) != CONST_INT)
2904 rtx counter = gen_reg_rtx (QImode);
2905 rtx start_label = gen_label_rtx ();
2906 rtx end_label = gen_label_rtx ();
2908 /* If the rotate amount is less than or equal to 0,
2909 we go out of the loop. */
2910 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0),
2911 LE, NULL_RTX, QImode, 0, 0, end_label);
2913 /* Initialize the loop counter. */
2914 emit_move_insn (counter, rotate_amount);
2916 emit_label (start_label);
2918 /* Rotate by one bit. */
2919 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
2920 emit_insn (gen_rtx_SET (mode, dst, tmp));
2922 /* Decrement the counter by 1. */
2923 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
2924 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
2926 /* If the loop counter is non-zero, we go back to the beginning
2928 emit_cmp_and_jump_insns (counter, GEN_INT (0),
2929 NE, NULL_RTX, QImode, 1, 0, start_label);
2931 emit_label (end_label);
2935 /* Rotate by AMOUNT bits. */
2936 tmp = gen_rtx (code, mode, dst, rotate_amount);
2937 emit_insn (gen_rtx_SET (mode, dst, tmp));
2943 /* Emit rotate insns. */
2946 emit_a_rotate (code, operands)
2950 rtx dst = operands[0];
2951 rtx rotate_amount = operands[2];
2952 enum shift_mode rotate_mode;
2953 enum shift_type rotate_type;
2954 const char *insn_buf;
2957 enum machine_mode mode = GET_MODE (dst);
2959 if (GET_CODE (rotate_amount) != CONST_INT)
2965 rotate_mode = QIshift;
2968 rotate_mode = HIshift;
2971 rotate_mode = SIshift;
2980 rotate_type = SHIFT_ASHIFT;
2983 rotate_type = SHIFT_LSHIFTRT;
2989 amount = INTVAL (rotate_amount);
2991 /* Clean up AMOUNT. */
2994 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
2995 amount = GET_MODE_BITSIZE (mode);
2997 /* Determine the faster direction. After this phase, amount will be
2998 at most a half of GET_MODE_BITSIZE (mode). */
2999 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
3001 /* Flip the direction. */
3002 amount = GET_MODE_BITSIZE (mode) - amount;
3004 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3007 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3008 boost up the rotation. */
3009 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3010 || (mode == HImode && TARGET_H8300H && amount >= 6)
3011 || (mode == HImode && TARGET_H8300S && amount == 8)
3012 || (mode == SImode && TARGET_H8300H && amount >= 10)
3013 || (mode == SImode && TARGET_H8300S && amount >= 13))
3018 /* This code works on any family. */
3019 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3020 output_asm_insn (insn_buf, operands);
3024 /* This code works on the H8/300H and H8/S. */
3025 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3026 output_asm_insn (insn_buf, operands);
3033 /* Adjust AMOUNT and flip the direction. */
3034 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3036 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3039 /* Emit rotate insns. */
3040 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3043 insn_buf = rotate_two[rotate_type][rotate_mode];
3045 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3047 for (; amount >= bits; amount -= bits)
3048 output_asm_insn (insn_buf, operands);
3054 /* Fix the operands of a gen_xxx so that it could become a bit
3058 fix_bit_operand (operands, what, type)
3063 /* The bit_operand predicate accepts any memory during RTL generation, but
3064 only 'U' memory afterwards, so if this is a MEM operand, we must force
3065 it to be valid for 'U' by reloading the address. */
3067 if (GET_CODE (operands[2]) == CONST_INT)
3069 if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), what))
3071 /* Ok to have a memory dest. */
3072 if (GET_CODE (operands[0]) == MEM
3073 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3075 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3076 copy_to_mode_reg (Pmode,
3077 XEXP (operands[0], 0)));
3078 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3082 if (GET_CODE (operands[1]) == MEM
3083 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3085 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3086 copy_to_mode_reg (Pmode,
3087 XEXP (operands[1], 0)));
3088 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3095 /* Dest and src op must be register. */
3097 operands[1] = force_reg (QImode, operands[1]);
3099 rtx res = gen_reg_rtx (QImode);
3100 emit_insn (gen_rtx_SET (VOIDmode, res,
3101 gen_rtx (type, QImode, operands[1], operands[2])));
3102 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3107 /* Return nonzero if FUNC is an interrupt function as specified
3108 by the "interrupt" attribute. */
3111 h8300_interrupt_function_p (func)
3116 if (TREE_CODE (func) != FUNCTION_DECL)
3119 a = lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func));
3120 return a != NULL_TREE;
3123 /* Return nonzero if FUNC is an OS_Task function as specified
3124 by the "OS_Task" attribute. */
3127 h8300_os_task_function_p (func)
3132 if (TREE_CODE (func) != FUNCTION_DECL)
3135 a = lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func));
3136 return a != NULL_TREE;
3139 /* Return nonzero if FUNC is a monitor function as specified
3140 by the "monitor" attribute. */
3143 h8300_monitor_function_p (func)
3148 if (TREE_CODE (func) != FUNCTION_DECL)
3151 a = lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func));
3152 return a != NULL_TREE;
3155 /* Return nonzero if FUNC is a function that should be called
3156 through the function vector. */
3159 h8300_funcvec_function_p (func)
3164 if (TREE_CODE (func) != FUNCTION_DECL)
3167 a = lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func));
3168 return a != NULL_TREE;
3171 /* Return nonzero if DECL is a variable that's in the eight bit
3175 h8300_eightbit_data_p (decl)
3180 if (TREE_CODE (decl) != VAR_DECL)
3183 a = lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl));
3184 return a != NULL_TREE;
3187 /* Return nonzero if DECL is a variable that's in the tiny
3191 h8300_tiny_data_p (decl)
3196 if (TREE_CODE (decl) != VAR_DECL)
3199 a = lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl));
3200 return a != NULL_TREE;
3203 /* Return nonzero if ATTR is a valid attribute for DECL.
3204 ATTRIBUTES are any existing attributes and ARGS are the arguments
3207 Supported attributes:
3209 interrupt_handler: output a prologue and epilogue suitable for an
3212 function_vector: This function should be called through the
3215 eightbit_data: This variable lives in the 8-bit data area and can
3216 be referenced with 8-bit absolute memory addresses.
3218 tiny_data: This variable lives in the tiny data area and can be
3219 referenced with 16-bit absolute memory references. */
3222 h8300_valid_decl_attribute (decl, attributes, attr, args)
3224 tree attributes ATTRIBUTE_UNUSED;
3228 if (args != NULL_TREE)
3231 if (is_attribute_p ("interrupt_handler", attr)
3232 || is_attribute_p ("OS_Task", attr)
3233 || is_attribute_p ("monitor", attr)
3234 || is_attribute_p ("function_vector", attr))
3235 return TREE_CODE (decl) == FUNCTION_DECL;
3237 if (is_attribute_p ("eightbit_data", attr)
3238 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3240 if (DECL_INITIAL (decl) == NULL_TREE)
3242 warning ("Only initialized variables can be placed into the 8-bit area.");
3245 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
3249 if (is_attribute_p ("tiny_data", attr)
3250 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
3252 if (DECL_INITIAL (decl) == NULL_TREE)
3254 warning ("Only initialized variables can be placed into the 8-bit area.");
3257 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
3265 h8300_encode_label (decl)
3268 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
3269 int len = strlen (str);
3272 newstr = ggc_alloc_string (NULL, len + 1);
3274 strcpy (newstr + 1, str);
3276 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
3280 output_simode_bld (bild, log2, operands)
3285 /* Clear the destination register. */
3286 if (TARGET_H8300H || TARGET_H8300S)
3287 output_asm_insn ("sub.l\t%S0,%S0", operands);
3289 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
3291 /* Get the bit number we want to load. */
3293 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
3295 /* Now output the bit load or bit inverse load, and store it in
3298 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3300 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
3306 /* Given INSN and its current length LENGTH, return the adjustment
3307 (in bytes) to correctly compute INSN's length.
3309 We use this to get the lengths of various memory references correct. */
3312 h8300_adjust_insn_length (insn, length)
3314 int length ATTRIBUTE_UNUSED;
3318 /* We must filter these ou before calling get_attr_adjust_length. */
3319 if (GET_CODE (PATTERN (insn)) == USE
3320 || GET_CODE (PATTERN (insn)) == CLOBBER
3321 || GET_CODE (PATTERN (insn)) == SEQUENCE
3322 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3323 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
3326 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
3329 pat = PATTERN (insn);
3331 /* Adjust length for reg->mem and mem->reg copies. */
3332 if (GET_CODE (pat) == SET
3333 && (GET_CODE (SET_SRC (pat)) == MEM
3334 || GET_CODE (SET_DEST (pat)) == MEM))
3336 /* This insn might need a length adjustment. */
3339 if (GET_CODE (SET_SRC (pat)) == MEM)
3340 addr = XEXP (SET_SRC (pat), 0);
3342 addr = XEXP (SET_DEST (pat), 0);
3344 /* On the H8/300, only one adjustment is necessary; if the
3345 address mode is register indirect, then this insn is two
3346 bytes shorter than indicated in the machine description. */
3347 if (TARGET_H8300 && GET_CODE (addr) == REG)
3350 /* On the H8/300H and H8/S, register indirect is 6 bytes shorter than
3351 indicated in the machine description. */
3352 if ((TARGET_H8300H || TARGET_H8300S)
3353 && GET_CODE (addr) == REG)
3356 /* On the H8/300H and H8/300S, reg + d, for small displacements is 4
3357 bytes shorter than indicated in the machine description. */
3358 if ((TARGET_H8300H || TARGET_H8300S)
3359 && GET_CODE (addr) == PLUS
3360 && GET_CODE (XEXP (addr, 0)) == REG
3361 && GET_CODE (XEXP (addr, 1)) == CONST_INT
3362 && INTVAL (XEXP (addr, 1)) > -32768
3363 && INTVAL (XEXP (addr, 1)) < 32767)
3366 /* On the H8/300H and H8/300S, abs:16 is two bytes shorter than the
3367 more general abs:24. */
3368 if ((TARGET_H8300H || TARGET_H8300S)
3369 && GET_CODE (addr) == SYMBOL_REF
3370 && TINY_DATA_NAME_P (XSTR (addr, 0)))
3374 /* Loading some constants needs adjustment. */
3375 if (GET_CODE (pat) == SET
3376 && GET_CODE (SET_SRC (pat)) == CONST_INT
3377 && GET_MODE (SET_DEST (pat)) == SImode
3378 && INTVAL (SET_SRC (pat)) != 0)
3380 int val = INTVAL (SET_SRC (pat));
3383 && ((val & 0xffff) == 0
3384 || ((val >> 16) & 0xffff) == 0))
3387 if (TARGET_H8300H || TARGET_H8300S)
3389 if (val == (val & 0xff)
3390 || val == (val & 0xff00))
3393 if (val == -4 || val == -2 || val == -1)
3398 /* Shifts need various adjustments. */
3399 if (GET_CODE (pat) == PARALLEL
3400 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
3401 && (GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFTRT
3402 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == LSHIFTRT
3403 || GET_CODE (SET_SRC (XVECEXP (pat, 0, 0))) == ASHIFT))
3405 rtx src = SET_SRC (XVECEXP (pat, 0, 0));
3406 enum machine_mode mode = GET_MODE (src);
3409 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3412 shift = INTVAL (XEXP (src, 1));
3413 /* According to ANSI, negative shift is undefined. It is
3414 considered to be zero in this case (see function
3415 emit_a_shift above). */
3419 /* QImode shifts by small constants take one insn
3420 per shift. So the adjustment is 20 (md length) -
3422 if (mode == QImode && shift <= 4)
3423 return -(20 - shift * 2);
3425 /* Similarly for HImode and SImode shifts by
3426 small constants on the H8/300H and H8/300S. */
3427 if ((TARGET_H8300H || TARGET_H8300S)
3428 && (mode == HImode || mode == SImode) && shift <= 4)
3429 return -(20 - shift * 2);
3431 /* HImode shifts by small constants for the H8/300. */
3432 if (mode == HImode && shift <= 4)
3433 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 2 : 4)));
3435 /* SImode shifts by small constants for the H8/300. */
3436 if (mode == SImode && shift <= 2)
3437 return -(20 - (shift * (GET_CODE (src) == ASHIFT ? 6 : 8)));
3439 /* XXX ??? Could check for more shift/rotate cases here. */
3442 /* Rotations need various adjustments. */
3443 if (GET_CODE (pat) == SET
3444 && (GET_CODE (SET_SRC (pat)) == ROTATE
3445 || GET_CODE (SET_SRC (pat)) == ROTATERT))
3447 rtx src = SET_SRC (pat);
3448 enum machine_mode mode = GET_MODE (src);
3452 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
3455 amount = INTVAL (XEXP (src, 1));
3457 /* Clean up AMOUNT. */
3460 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3461 amount = GET_MODE_BITSIZE (mode);
3463 /* Determine the faster direction. After this phase, amount
3464 will be at most a half of GET_MODE_BITSIZE (mode). */
3465 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / 2)
3466 /* Flip the direction. */
3467 amount = GET_MODE_BITSIZE (mode) - amount;
3469 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3470 boost up the rotation. */
3471 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3472 || (mode == HImode && TARGET_H8300H && amount >= 6)
3473 || (mode == HImode && TARGET_H8300S && amount == 8)
3474 || (mode == SImode && TARGET_H8300H && amount >= 10)
3475 || (mode == SImode && TARGET_H8300S && amount >= 13))
3477 /* Adjust AMOUNT and flip the direction. */
3478 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3482 /* We use 2-bit rotatations on the H8/S. */
3484 amount = amount / 2 + amount % 2;
3486 /* The H8/300 uses three insns to rotate one bit, taking 6
3488 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
3490 return -(20 - states);
3497 h8300_asm_named_section (name, flags)
3499 unsigned int flags ATTRIBUTE_UNUSED;
3501 /* ??? Perhaps we should be using default_coff_asm_named_section. */
3502 fprintf (asm_out_file, "\t.section %s\n", name);