1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg PARAMS ((rtx, int));
50 static int h8300_interrupt_function_p PARAMS ((tree));
51 static int h8300_monitor_function_p PARAMS ((tree));
52 static int h8300_os_task_function_p PARAMS ((tree));
53 static void dosize PARAMS ((int, unsigned int));
54 static int round_frame_size PARAMS ((int));
55 static unsigned int compute_saved_regs PARAMS ((void));
56 static void push PARAMS ((int));
57 static void pop PARAMS ((int));
58 static const char *cond_string PARAMS ((enum rtx_code));
59 static unsigned int h8300_asm_insn_count PARAMS ((const char *));
60 const struct attribute_spec h8300_attribute_table[];
61 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
62 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
63 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
64 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
65 static void h8300_insert_attributes PARAMS ((tree, tree *));
66 #ifndef OBJECT_FORMAT_ELF
67 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
69 static void h8300_encode_label PARAMS ((tree));
70 static void h8300_encode_section_info PARAMS ((tree, int));
71 static const char *h8300_strip_name_encoding PARAMS ((const char *));
72 static int const_costs PARAMS ((rtx, enum rtx_code, enum rtx_code));
73 static int h8300_and_costs PARAMS ((rtx));
74 static int h8300_shift_costs PARAMS ((rtx));
75 static bool h8300_rtx_costs PARAMS ((rtx, int, int, int *));
77 /* CPU_TYPE, says what cpu we're compiling for. */
80 /* True if a #pragma interrupt has been seen for the current function. */
81 static int pragma_interrupt;
83 /* True if a #pragma saveall has been seen for the current function. */
84 static int pragma_saveall;
86 static const char *const names_big[] =
87 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
89 static const char *const names_extended[] =
90 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
92 static const char *const names_upper_extended[] =
93 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
95 /* Points to one of the above. */
96 /* ??? The above could be put in an array indexed by CPU_TYPE. */
97 const char * const *h8_reg_names;
99 /* Various operations needed by the following, indexed by CPU_TYPE. */
101 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
103 /* Initialize the GCC target structure. */
104 #undef TARGET_ATTRIBUTE_TABLE
105 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
107 #undef TARGET_ASM_ALIGNED_HI_OP
108 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
110 #undef TARGET_ASM_FUNCTION_EPILOGUE
111 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
112 #undef TARGET_ENCODE_SECTION_INFO
113 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
114 #undef TARGET_STRIP_NAME_ENCODING
115 #define TARGET_STRIP_NAME_ENCODING h8300_strip_name_encoding
117 #undef TARGET_INSERT_ATTRIBUTES
118 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
120 #undef TARGET_RTX_COSTS
121 #define TARGET_RTX_COSTS h8300_rtx_costs
123 struct gcc_target targetm = TARGET_INITIALIZER;
125 /* See below where shifts are handled for explanation of this enum. */
135 /* Symbols of the various shifts which can be used as indices. */
139 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
142 /* Macros to keep the shift algorithm tables small. */
143 #define INL SHIFT_INLINE
144 #define ROT SHIFT_ROT_AND
145 #define LOP SHIFT_LOOP
146 #define SPC SHIFT_SPECIAL
148 /* The shift algorithms for each machine, mode, shift type, and shift
149 count are defined below. The three tables below correspond to
150 QImode, HImode, and SImode, respectively. Each table is organized
151 by, in the order of indices, machine, shift type, and shift count. */
153 static enum shift_alg shift_alg_qi[3][3][8] = {
156 /* 0 1 2 3 4 5 6 7 */
157 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
158 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
159 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
163 /* 0 1 2 3 4 5 6 7 */
164 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
165 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
166 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
170 /* 0 1 2 3 4 5 6 7 */
171 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
172 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
173 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
177 static enum shift_alg shift_alg_hi[3][3][16] = {
180 /* 0 1 2 3 4 5 6 7 */
181 /* 8 9 10 11 12 13 14 15 */
182 { INL, INL, INL, INL, INL, INL, INL, SPC,
183 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
184 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
185 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
186 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
187 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
191 /* 0 1 2 3 4 5 6 7 */
192 /* 8 9 10 11 12 13 14 15 */
193 { INL, INL, INL, INL, INL, INL, INL, SPC,
194 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
195 { INL, INL, INL, INL, INL, INL, INL, SPC,
196 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
197 { INL, INL, INL, INL, INL, INL, INL, SPC,
198 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
202 /* 0 1 2 3 4 5 6 7 */
203 /* 8 9 10 11 12 13 14 15 */
204 { INL, INL, INL, INL, INL, INL, INL, INL,
205 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
206 { INL, INL, INL, INL, INL, INL, INL, INL,
207 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
208 { INL, INL, INL, INL, INL, INL, INL, INL,
209 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
213 static enum shift_alg shift_alg_si[3][3][32] = {
216 /* 0 1 2 3 4 5 6 7 */
217 /* 8 9 10 11 12 13 14 15 */
218 /* 16 17 18 19 20 21 22 23 */
219 /* 24 25 26 27 28 29 30 31 */
220 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
221 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
222 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
223 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
224 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
225 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
226 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
227 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
228 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
229 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
230 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
231 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
235 /* 0 1 2 3 4 5 6 7 */
236 /* 8 9 10 11 12 13 14 15 */
237 /* 16 17 18 19 20 21 22 23 */
238 /* 24 25 26 27 28 29 30 31 */
239 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
240 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
241 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
242 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
243 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
244 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
245 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
246 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
247 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
248 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
249 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
250 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
254 /* 0 1 2 3 4 5 6 7 */
255 /* 8 9 10 11 12 13 14 15 */
256 /* 16 17 18 19 20 21 22 23 */
257 /* 24 25 26 27 28 29 30 31 */
258 { INL, INL, INL, INL, INL, INL, INL, INL,
259 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
260 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
261 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
262 { INL, INL, INL, INL, INL, INL, INL, INL,
263 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
264 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
265 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
266 { INL, INL, INL, INL, INL, INL, INL, INL,
267 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
268 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
269 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
285 /* Initialize various cpu specific globals at start up. */
290 static const char *const h8_push_ops[2] = { "push" , "push.l" };
291 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
292 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
296 cpu_type = (int) CPU_H8300;
297 h8_reg_names = names_big;
301 /* For this we treat the H8/300H and H8S the same. */
302 cpu_type = (int) CPU_H8300H;
303 h8_reg_names = names_extended;
305 h8_push_op = h8_push_ops[cpu_type];
306 h8_pop_op = h8_pop_ops[cpu_type];
307 h8_mov_op = h8_mov_ops[cpu_type];
309 if (!TARGET_H8300S && TARGET_MAC)
311 error ("-ms2600 is used without -ms");
312 target_flags |= MASK_H8300S;
315 if (TARGET_H8300 && TARGET_NORMAL_MODE)
317 error ("-mn is used without -mh or -ms");
318 target_flags ^= MASK_NORMAL_MODE;
321 /* Some of the shifts are optimized for speed by default.
322 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
323 If optimizing for size, change shift_alg for those shift to
328 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
329 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
330 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
331 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
333 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
334 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
336 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
337 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
340 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
341 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
343 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
344 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
346 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
347 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
348 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
349 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
352 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
361 static const char *const names_small[] = {
362 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
363 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
366 return names_small[REGNO (x) * 2 + b];
369 /* REGNO must be saved/restored across calls if this macro is true. */
371 #define WORD_REG_USED(regno) \
373 /* No need to save registers if this function will not return. */ \
374 && ! TREE_THIS_VOLATILE (current_function_decl) \
376 /* Save any call saved register that was used. */ \
377 || (regs_ever_live[regno] && !call_used_regs[regno]) \
378 /* Save the frame pointer if it was used. */ \
379 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
380 /* Save any register used in an interrupt handler. */ \
381 || (h8300_current_function_interrupt_function_p () \
382 && regs_ever_live[regno]) \
383 /* Save call clobbered registers in non-leaf interrupt \
385 || (h8300_current_function_interrupt_function_p () \
386 && call_used_regs[regno] \
387 && !current_function_is_leaf)))
389 /* Output assembly language to FILE for the operation OP with operand size
390 SIZE to adjust the stack pointer. */
397 /* H8/300 cannot add/subtract a large constant with a single
398 instruction. If a temporary register is available, load the
399 constant to it and then do the addition. */
402 && !h8300_current_function_interrupt_function_p ()
403 && !(current_function_needs_context && sign < 0))
406 rtx r3 = gen_rtx_REG (Pmode, 3);
407 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
408 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
409 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
413 /* The stack adjustment made here is further optimized by the
414 splitter. In case of H8/300, the splitter always splits the
415 addition emitted here to make the adjustment
417 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
418 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
422 /* Round up frame size SIZE. */
425 round_frame_size (size)
428 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
429 & -STACK_BOUNDARY / BITS_PER_UNIT);
432 /* Compute which registers to push/pop.
433 Return a bit vector of registers. */
436 compute_saved_regs ()
438 unsigned int saved_regs = 0;
441 /* Construct a bit vector of registers to be pushed/popped. */
442 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
444 if (WORD_REG_USED (regno))
445 saved_regs |= 1 << regno;
448 /* Don't push/pop the frame pointer as it is treated separately. */
449 if (frame_pointer_needed)
450 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
455 /* Emit an insn to push register RN. */
461 rtx reg = gen_rtx_REG (word_mode, rn);
465 x = gen_push_h8300 (reg);
467 x = gen_push_h8300hs (reg);
469 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
472 /* Emit an insn to pop register RN. */
478 rtx reg = gen_rtx_REG (word_mode, rn);
482 x = gen_pop_h8300 (reg);
484 x = gen_pop_h8300hs (reg);
486 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
489 /* This is what the stack looks like after the prolog of
490 a function with a frame has been set up:
496 <saved registers> <- sp
498 This is what the stack looks like after the prolog of
499 a function which doesn't have a frame:
504 <saved registers> <- sp
507 /* Generate RTL code for the function prologue. */
510 h8300_expand_prologue ()
516 /* If the current function has the OS_Task attribute set, then
517 we have a naked prologue. */
518 if (h8300_os_task_function_p (current_function_decl))
521 if (h8300_monitor_function_p (current_function_decl))
522 /* My understanding of monitor functions is they act just like
523 interrupt functions, except the prologue must mask
525 emit_insn (gen_monitor_prologue ());
527 if (frame_pointer_needed)
530 push (FRAME_POINTER_REGNUM);
531 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
534 /* Leave room for locals. */
535 dosize (-1, round_frame_size (get_frame_size ()));
537 /* Push the rest of the registers in ascending order. */
538 saved_regs = compute_saved_regs ();
539 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
542 if (saved_regs & (1 << regno))
546 /* See how many registers we can push at the same time. */
547 if ((regno == 0 || regno == 4)
548 && ((saved_regs >> regno) & 0x0f) == 0x0f)
551 else if ((regno == 0 || regno == 4)
552 && ((saved_regs >> regno) & 0x07) == 0x07)
555 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
556 && ((saved_regs >> regno) & 0x03) == 0x03)
566 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
567 gen_rtx_REG (SImode, regno + 1)));
570 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
571 gen_rtx_REG (SImode, regno + 1),
572 gen_rtx_REG (SImode, regno + 2)));
575 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
576 gen_rtx_REG (SImode, regno + 1),
577 gen_rtx_REG (SImode, regno + 2),
578 gen_rtx_REG (SImode, regno + 3)));
588 h8300_can_use_return_insn_p ()
590 return (reload_completed
591 && !frame_pointer_needed
592 && get_frame_size () == 0
593 && compute_saved_regs () == 0);
596 /* Generate RTL code for the function epilogue. */
599 h8300_expand_epilogue ()
605 if (h8300_os_task_function_p (current_function_decl))
606 /* OS_Task epilogues are nearly naked -- they just have an
610 /* Pop the saved registers in descending order. */
611 saved_regs = compute_saved_regs ();
612 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
615 if (saved_regs & (1 << regno))
619 /* See how many registers we can pop at the same time. */
620 if ((regno == 7 || regno == 3)
621 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
624 else if ((regno == 6 || regno == 2)
625 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
628 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
629 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
639 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
640 gen_rtx_REG (SImode, regno)));
643 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
644 gen_rtx_REG (SImode, regno - 1),
645 gen_rtx_REG (SImode, regno)));
648 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
649 gen_rtx_REG (SImode, regno - 2),
650 gen_rtx_REG (SImode, regno - 1),
651 gen_rtx_REG (SImode, regno)));
659 /* Deallocate locals. */
660 dosize (1, round_frame_size (get_frame_size ()));
662 /* Pop frame pointer if we had one. */
663 if (frame_pointer_needed)
664 pop (FRAME_POINTER_REGNUM);
667 /* Output assembly language code for the function epilogue. */
670 h8300_output_function_epilogue (file, size)
671 FILE *file ATTRIBUTE_UNUSED;
672 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
677 /* Return nonzero if the current function is an interrupt
681 h8300_current_function_interrupt_function_p ()
683 return (h8300_interrupt_function_p (current_function_decl)
684 || h8300_monitor_function_p (current_function_decl));
687 /* Output assembly code for the start of the file. */
690 asm_file_start (file)
693 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
694 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
697 fprintf (file, "; -Os\n");
699 fprintf (file, "; -O%d\n", optimize);
701 fprintf (file, "\n\t.h8300h\n");
702 else if (TARGET_H8300S)
703 fprintf (file, "\n\t.h8300s\n");
705 fprintf (file, "\n\n");
706 output_file_directive (file, main_input_filename);
709 /* Output assembly language code for the end of file. */
715 fprintf (file, "\t.end\n");
718 /* Return true if OP is a valid source operand for an integer move
722 general_operand_src (op, mode)
724 enum machine_mode mode;
726 if (GET_MODE (op) == mode
727 && GET_CODE (op) == MEM
728 && GET_CODE (XEXP (op, 0)) == POST_INC)
730 return general_operand (op, mode);
733 /* Return true if OP is a valid destination operand for an integer move
737 general_operand_dst (op, mode)
739 enum machine_mode mode;
741 if (GET_MODE (op) == mode
742 && GET_CODE (op) == MEM
743 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
745 return general_operand (op, mode);
748 /* Return true if OP is a constant that contains only one 1 in its
749 binary representation. */
752 single_one_operand (operand, mode)
754 enum machine_mode mode ATTRIBUTE_UNUSED;
756 if (GET_CODE (operand) == CONST_INT)
758 /* We really need to do this masking because 0x80 in QImode is
759 represented as -128 for example. */
760 unsigned HOST_WIDE_INT mask =
761 (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
762 ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
763 : ~(unsigned HOST_WIDE_INT) 0;
764 unsigned HOST_WIDE_INT value = INTVAL (operand);
766 if (exact_log2 (value & mask) >= 0)
773 /* Return true if OP is a constant that contains only one 0 in its
774 binary representation. */
777 single_zero_operand (operand, mode)
779 enum machine_mode mode ATTRIBUTE_UNUSED;
781 if (GET_CODE (operand) == CONST_INT)
783 /* We really need to do this masking because 0x80 in QImode is
784 represented as -128 for example. */
785 unsigned HOST_WIDE_INT mask =
786 (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
787 ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
788 : ~(unsigned HOST_WIDE_INT) 0;
789 unsigned HOST_WIDE_INT value = INTVAL (operand);
791 if (exact_log2 (~value & mask) >= 0)
798 /* Return true if OP is a valid call operand. */
801 call_insn_operand (op, mode)
803 enum machine_mode mode ATTRIBUTE_UNUSED;
805 if (GET_CODE (op) == MEM)
807 rtx inside = XEXP (op, 0);
808 if (register_operand (inside, Pmode))
810 if (CONSTANT_ADDRESS_P (inside))
816 /* Return 1 if an addition/subtraction of a constant integer can be
817 transformed into two consecutive adds/subs that are faster than the
818 straightforward way. Otherwise, return 0. */
821 two_insn_adds_subs_operand (op, mode)
823 enum machine_mode mode;
825 if (GET_CODE (op) == CONST_INT)
827 HOST_WIDE_INT value = INTVAL (op);
829 /* Force VALUE to be positive so that we do not have to consider
830 the negative case. */
833 if (TARGET_H8300H || TARGET_H8300S)
835 /* A constant addition/subtraction takes 2 states in QImode,
836 4 states in HImode, and 6 states in SImode. Thus, the
837 only case we can win is when SImode is used, in which
838 case, two adds/subs are used, taking 4 states. */
848 /* We do not profit directly by splitting addition or
849 subtraction of 3 and 4. However, since these are
850 implemented as a sequence of adds or subs, they do not
851 clobber (cc0) unlike a sequence of add.b and add.x. */
862 /* Split an add of a small constant into two adds/subs insns.
864 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
865 instead of adds/subs. */
868 split_adds_subs (mode, operands)
869 enum machine_mode mode;
872 HOST_WIDE_INT val = INTVAL (operands[1]);
873 rtx reg = operands[0];
874 HOST_WIDE_INT sign = 1;
875 HOST_WIDE_INT amount;
876 rtx (*gen_add) (rtx, rtx, rtx);
878 /* Force VAL to be positive so that we do not have to consider the
889 gen_add = gen_addhi3;
893 gen_add = gen_addsi3;
900 /* Try different amounts in descending order. */
901 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
905 for (; val >= amount; val -= amount)
906 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
912 /* Return true if OP is a valid call operand, and OP represents
913 an operand for a small call (4 bytes instead of 6 bytes). */
916 small_call_insn_operand (op, mode)
918 enum machine_mode mode ATTRIBUTE_UNUSED;
920 if (GET_CODE (op) == MEM)
922 rtx inside = XEXP (op, 0);
924 /* Register indirect is a small call. */
925 if (register_operand (inside, Pmode))
928 /* A call through the function vector is a small
930 if (GET_CODE (inside) == SYMBOL_REF
931 && SYMBOL_REF_FLAG (inside))
934 /* Otherwise it's a large call. */
938 /* Return true if OP is a valid jump operand. */
941 jump_address_operand (op, mode)
943 enum machine_mode mode;
945 if (GET_CODE (op) == REG)
946 return mode == Pmode;
948 if (GET_CODE (op) == MEM)
950 rtx inside = XEXP (op, 0);
951 if (register_operand (inside, Pmode))
953 if (CONSTANT_ADDRESS_P (inside))
959 /* Recognize valid operands for bit-field instructions. */
961 extern int rtx_equal_function_value_matters;
964 bit_operand (op, mode)
966 enum machine_mode mode;
968 /* We can accept any general operand, except that MEM operands must
969 be limited to those that use addresses valid for the 'U' constraint. */
970 if (!general_operand (op, mode))
973 /* Accept any mem during RTL generation. Otherwise, the code that does
974 insv and extzv will think that we can not handle memory. However,
975 to avoid reload problems, we only accept 'U' MEM operands after RTL
976 generation. This means that any named pattern which uses this predicate
977 must force its operands to match 'U' before emitting RTL. */
979 if (GET_CODE (op) == REG)
981 if (GET_CODE (op) == SUBREG)
983 return (GET_CODE (op) == MEM
984 && EXTRA_CONSTRAINT (op, 'U'));
988 bit_memory_operand (op, mode)
990 enum machine_mode mode ATTRIBUTE_UNUSED;
992 return (GET_CODE (op) == MEM
993 && EXTRA_CONSTRAINT (op, 'U'));
996 /* Handle machine specific pragmas for compatibility with existing
997 compilers for the H8/300.
999 pragma saveall generates prologue/epilogue code which saves and
1000 restores all the registers on function entry.
1002 pragma interrupt saves and restores all registers, and exits with
1003 an rte instruction rather than an rts. A pointer to a function
1004 with this attribute may be safely used in an interrupt vector. */
1007 h8300_pr_interrupt (pfile)
1008 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1010 pragma_interrupt = 1;
1014 h8300_pr_saveall (pfile)
1015 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1020 /* If the next function argument with MODE and TYPE is to be passed in
1021 a register, return a reg RTX for the hard register in which to pass
1022 the argument. CUM represents the state after the last argument.
1023 If the argument is to be pushed, NULL_RTX is returned. */
1026 function_arg (cum, mode, type, named)
1027 CUMULATIVE_ARGS *cum;
1028 enum machine_mode mode;
1032 static const char *const hand_list[] = {
1051 rtx result = NULL_RTX;
1055 /* Never pass unnamed arguments in registers. */
1059 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1060 if (TARGET_QUICKCALL)
1063 /* If calling hand written assembler, use 4 regs of args. */
1066 const char * const *p;
1068 fname = XSTR (cum->libcall, 0);
1070 /* See if this libcall is one of the hand coded ones. */
1071 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1082 if (mode == BLKmode)
1083 size = int_size_in_bytes (type);
1085 size = GET_MODE_SIZE (mode);
1087 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1088 && cum->nbytes / UNITS_PER_WORD <= 3)
1089 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1095 /* Return the cost of the rtx R with code CODE. */
1098 const_costs (r, c, outer_code)
1101 enum rtx_code outer_code;
1107 HOST_WIDE_INT n = INTVAL (r);
1109 if (-4 <= n || n <= 4)
1119 return 0 + (outer_code == SET);
1122 if (TARGET_H8300H || TARGET_H8300S)
1123 return 0 + (outer_code == SET);
1150 if (GET_MODE (x) == QImode)
1153 if (GET_MODE (x) != HImode
1154 && GET_MODE (x) != SImode)
1159 operands[2] = XEXP (x, 1);
1161 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1165 h8300_shift_costs (x)
1170 if (GET_MODE (x) != QImode
1171 && GET_MODE (x) != HImode
1172 && GET_MODE (x) != SImode)
1177 operands[2] = XEXP (x, 1);
1179 return compute_a_shift_length (NULL, operands) / 2;
1183 h8300_rtx_costs (x, code, outer_code, total)
1185 int code, outer_code;
1191 *total = COSTS_N_INSNS (h8300_and_costs (x));
1194 /* We say that MOD and DIV are so expensive because otherwise we'll
1195 generate some really horrible code for division of a power of two. */
1208 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1213 if (GET_MODE (x) == HImode)
1220 *total = const_costs (x, code, outer_code);
1225 /* Documentation for the machine specific operand escapes:
1227 'E' like s but negative.
1228 'F' like t but negative.
1229 'G' constant just the negative
1230 'R' print operand as a byte:8 address if appropriate, else fall back to
1232 'S' print operand as a long word
1233 'T' print operand as a word
1234 'V' find the set bit, and print its number.
1235 'W' find the clear bit, and print its number.
1236 'X' print operand as a byte
1237 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1238 If this operand isn't a register, fall back to 'R' handling.
1240 'b' print the bit opcode
1241 'c' print the opcode corresponding to rtl
1242 'e' first word of 32 bit value - if reg, then least reg. if mem
1243 then least. if const then most sig word
1244 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1245 then +2. if const then least sig word
1246 'j' print operand as condition code.
1247 'k' print operand as reverse condition code.
1248 's' print as low byte of 16 bit value
1249 't' print as high byte of 16 bit value
1250 'w' print as low byte of 32 bit value
1251 'x' print as 2nd byte of 32 bit value
1252 'y' print as 3rd byte of 32 bit value
1253 'z' print as msb of 32 bit value
1256 /* Return assembly language string which identifies a comparison type. */
1289 /* Print operand X using operand code CODE to assembly language output file
1293 print_operand (file, x, code)
1298 /* This is used for communication between codes V,W,Z and Y. */
1304 switch (GET_CODE (x))
1307 fprintf (file, "%sl", names_big[REGNO (x)]);
1310 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1317 switch (GET_CODE (x))
1320 fprintf (file, "%sh", names_big[REGNO (x)]);
1323 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1330 if (GET_CODE (x) != CONST_INT)
1332 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1335 if (GET_CODE (x) == REG)
1336 fprintf (file, "%s", names_extended[REGNO (x)]);
1341 if (GET_CODE (x) == REG)
1342 fprintf (file, "%s", names_big[REGNO (x)]);
1347 bitint = exact_log2 (INTVAL (x) & 0xff);
1350 fprintf (file, "#%d", bitint);
1353 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1356 fprintf (file, "#%d", bitint);
1360 if (GET_CODE (x) == REG)
1361 fprintf (file, "%s", byte_reg (x, 0));
1368 if (GET_CODE (x) == REG)
1369 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1371 print_operand (file, x, 'R');
1375 bitint = INTVAL (x);
1376 fprintf (file, "#%d", bitint & 7);
1379 switch (GET_CODE (x))
1382 fprintf (file, "bor");
1385 fprintf (file, "bxor");
1388 fprintf (file, "band");
1395 switch (GET_CODE (x))
1398 fprintf (file, "or");
1401 fprintf (file, "xor");
1408 switch (GET_CODE (x))
1412 fprintf (file, "%s", names_big[REGNO (x)]);
1414 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1417 print_operand (file, x, 0);
1420 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1426 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1427 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1428 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1437 switch (GET_CODE (x))
1441 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1443 fprintf (file, "%s", names_big[REGNO (x)]);
1446 x = adjust_address (x, HImode, 2);
1447 print_operand (file, x, 0);
1450 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1456 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1457 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1458 fprintf (file, "#%ld", (val & 0xffff));
1466 fputs (cond_string (GET_CODE (x)), file);
1469 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1472 if (GET_CODE (x) == CONST_INT)
1473 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1475 fprintf (file, "%s", byte_reg (x, 0));
1478 if (GET_CODE (x) == CONST_INT)
1479 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1481 fprintf (file, "%s", byte_reg (x, 1));
1484 if (GET_CODE (x) != CONST_INT)
1486 fprintf (file, "%ld", INTVAL (x));
1489 if (GET_CODE (x) == CONST_INT)
1490 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1492 fprintf (file, "%s",
1493 byte_reg (x, TARGET_H8300 ? 2 : 0));
1496 if (GET_CODE (x) == CONST_INT)
1497 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1499 fprintf (file, "%s",
1500 byte_reg (x, TARGET_H8300 ? 3 : 1));
1503 if (GET_CODE (x) == CONST_INT)
1504 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1506 fprintf (file, "%s", byte_reg (x, 0));
1509 if (GET_CODE (x) == CONST_INT)
1510 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1512 fprintf (file, "%s", byte_reg (x, 1));
1517 switch (GET_CODE (x))
1520 switch (GET_MODE (x))
1523 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1524 fprintf (file, "%s", byte_reg (x, 0));
1525 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1526 fprintf (file, "%s", names_big[REGNO (x)]);
1530 fprintf (file, "%s", names_big[REGNO (x)]);
1534 fprintf (file, "%s", names_extended[REGNO (x)]);
1543 rtx addr = XEXP (x, 0);
1545 fprintf (file, "@");
1546 output_address (addr);
1548 /* We fall back from smaller addressing to larger
1549 addressing in various ways depending on CODE. */
1553 /* Used for mov.b and bit operations. */
1554 if (h8300_eightbit_constant_address_p (addr))
1556 fprintf (file, ":8");
1560 /* Fall through. We should not get here if we are
1561 processing bit operations on H8/300 or H8/300H
1562 because 'U' constraint does not allow bit
1563 operations on the tiny area on these machines. */
1567 /* Used for mov.w and mov.l. */
1568 if (h8300_tiny_constant_address_p (addr))
1569 fprintf (file, ":16");
1581 fprintf (file, "#");
1582 print_operand_address (file, x);
1588 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1589 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1590 fprintf (file, "#%ld", val);
1599 /* Output assembly language output for the address ADDR to FILE. */
1602 print_operand_address (file, addr)
1606 switch (GET_CODE (addr))
1609 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1613 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1617 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1621 fprintf (file, "(");
1622 if (GET_CODE (XEXP (addr, 0)) == REG)
1625 print_operand_address (file, XEXP (addr, 1));
1626 fprintf (file, ",");
1627 print_operand_address (file, XEXP (addr, 0));
1632 print_operand_address (file, XEXP (addr, 0));
1633 fprintf (file, "+");
1634 print_operand_address (file, XEXP (addr, 1));
1636 fprintf (file, ")");
1641 /* Since the H8/300 only has 16 bit pointers, negative values are also
1642 those >= 32768. This happens for example with pointer minus a
1643 constant. We don't want to turn (char *p - 2) into
1644 (char *p + 65534) because loop unrolling can build upon this
1645 (IE: char *p + 131068). */
1646 int n = INTVAL (addr);
1648 n = (int) (short) n;
1649 fprintf (file, "%d", n);
1654 output_addr_const (file, addr);
1659 /* Output all insn addresses and their sizes into the assembly language
1660 output file. This is helpful for debugging whether the length attributes
1661 in the md file are correct. This is not meant to be a user selectable
1665 final_prescan_insn (insn, operand, num_operands)
1666 rtx insn, *operand ATTRIBUTE_UNUSED;
1667 int num_operands ATTRIBUTE_UNUSED;
1669 /* This holds the last insn address. */
1670 static int last_insn_address = 0;
1672 const int uid = INSN_UID (insn);
1674 if (TARGET_RTL_DUMP)
1676 fprintf (asm_out_file, "\n****************");
1677 print_rtl (asm_out_file, PATTERN (insn));
1678 fprintf (asm_out_file, "\n");
1681 if (TARGET_ADDRESSES)
1683 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1684 INSN_ADDRESSES (uid) - last_insn_address);
1685 last_insn_address = INSN_ADDRESSES (uid);
1689 /* Prepare for an SI sized move. */
1695 rtx src = operands[1];
1696 rtx dst = operands[0];
1697 if (!reload_in_progress && !reload_completed)
1699 if (!register_operand (dst, GET_MODE (dst)))
1701 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1702 emit_move_insn (tmp, src);
1709 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1710 Define the offset between two registers, one to be eliminated, and
1711 the other its replacement, at the start of a routine. */
1714 h8300_initial_elimination_offset (from, to)
1718 /* The number of bytes that the return address takes on the stack. */
1719 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1721 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1722 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1723 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1724 offset = frame_pointer_needed * UNITS_PER_WORD;
1729 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1730 if (WORD_REG_USED (regno))
1731 offset += UNITS_PER_WORD;
1733 /* See the comments for get_frame_size. We need to round it up to
1736 offset += round_frame_size (get_frame_size ());
1738 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1739 /* Skip saved PC. */
1747 h8300_return_addr_rtx (count, frame)
1754 ret = gen_rtx_MEM (Pmode,
1755 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1756 else if (flag_omit_frame_pointer)
1759 ret = gen_rtx_MEM (Pmode,
1760 memory_address (Pmode,
1761 plus_constant (frame, UNITS_PER_WORD)));
1762 set_mem_alias_set (ret, get_frame_alias_set ());
1766 /* Update the condition code from the insn. */
1769 notice_update_cc (body, insn)
1775 switch (get_attr_cc (insn))
1778 /* Insn does not affect CC at all. */
1782 /* Insn does not change CC, but the 0'th operand has been changed. */
1783 if (cc_status.value1 != 0
1784 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1785 cc_status.value1 = 0;
1786 if (cc_status.value2 != 0
1787 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1788 cc_status.value2 = 0;
1792 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1793 The V flag is unusable. The C flag may or may not be known but
1794 that's ok because alter_cond will change tests to use EQ/NE. */
1796 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1797 set = single_set (insn);
1798 cc_status.value1 = SET_SRC (set);
1799 if (SET_DEST (set) != cc0_rtx)
1800 cc_status.value2 = SET_DEST (set);
1804 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1805 The C flag may or may not be known but that's ok because
1806 alter_cond will change tests to use EQ/NE. */
1808 cc_status.flags |= CC_NO_CARRY;
1809 set = single_set (insn);
1810 cc_status.value1 = SET_SRC (set);
1811 if (SET_DEST (set) != cc0_rtx)
1813 /* If the destination is STRICT_LOW_PART, strip off
1815 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1816 cc_status.value2 = XEXP (SET_DEST (set), 0);
1818 cc_status.value2 = SET_DEST (set);
1823 /* The insn is a compare instruction. */
1825 cc_status.value1 = SET_SRC (body);
1829 /* Insn doesn't leave CC in a usable state. */
1835 /* Return nonzero if X is a stack pointer. */
1838 stack_pointer_operand (x, mode)
1840 enum machine_mode mode ATTRIBUTE_UNUSED;
1842 return x == stack_pointer_rtx;
1845 /* Return nonzero if X is a constant whose absolute value is greater
1849 const_int_gt_2_operand (x, mode)
1851 enum machine_mode mode ATTRIBUTE_UNUSED;
1853 return (GET_CODE (x) == CONST_INT
1854 && abs (INTVAL (x)) > 2);
1857 /* Return nonzero if X is a constant whose absolute value is no
1861 const_int_ge_8_operand (x, mode)
1863 enum machine_mode mode ATTRIBUTE_UNUSED;
1865 return (GET_CODE (x) == CONST_INT
1866 && abs (INTVAL (x)) >= 8);
1869 /* Return nonzero if X is a constant expressible in QImode. */
1872 const_int_qi_operand (x, mode)
1874 enum machine_mode mode ATTRIBUTE_UNUSED;
1876 return (GET_CODE (x) == CONST_INT
1877 && (INTVAL (x) & 0xff) == INTVAL (x));
1880 /* Return nonzero if X is a constant expressible in HImode. */
1883 const_int_hi_operand (x, mode)
1885 enum machine_mode mode ATTRIBUTE_UNUSED;
1887 return (GET_CODE (x) == CONST_INT
1888 && (INTVAL (x) & 0xffff) == INTVAL (x));
1891 /* Return nonzero if X is a constant suitable for inc/dec. */
1894 incdec_operand (x, mode)
1896 enum machine_mode mode ATTRIBUTE_UNUSED;
1898 return (GET_CODE (x) == CONST_INT
1899 && (CONST_OK_FOR_M (INTVAL (x))
1900 || CONST_OK_FOR_O (INTVAL (x))));
1903 /* Return nonzero if X is either EQ or NE. */
1906 eqne_operator (x, mode)
1908 enum machine_mode mode ATTRIBUTE_UNUSED;
1910 enum rtx_code code = GET_CODE (x);
1912 return (code == EQ || code == NE);
1915 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1918 gtle_operator (x, mode)
1920 enum machine_mode mode ATTRIBUTE_UNUSED;
1922 enum rtx_code code = GET_CODE (x);
1924 return (code == GT || code == LE || code == GTU || code == LEU);
1927 /* Return nonzero if X is either GTU or LEU. */
1930 gtuleu_operator (x, mode)
1932 enum machine_mode mode ATTRIBUTE_UNUSED;
1934 enum rtx_code code = GET_CODE (x);
1936 return (code == GTU || code == LEU);
1939 /* Return nonzero if X is either IOR or XOR. */
1942 iorxor_operator (x, mode)
1944 enum machine_mode mode ATTRIBUTE_UNUSED;
1946 enum rtx_code code = GET_CODE (x);
1948 return (code == IOR || code == XOR);
1951 /* Recognize valid operators for bit instructions. */
1954 bit_operator (x, mode)
1956 enum machine_mode mode ATTRIBUTE_UNUSED;
1958 enum rtx_code code = GET_CODE (x);
1966 output_plussi (operands)
1969 enum machine_mode mode = GET_MODE (operands[0]);
1976 if (GET_CODE (operands[2]) == REG)
1977 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1979 if (GET_CODE (operands[2]) == CONST_INT)
1981 HOST_WIDE_INT n = INTVAL (operands[2]);
1983 if ((n & 0xffffff) == 0)
1984 return "add\t%z2,%z0";
1985 if ((n & 0xffff) == 0)
1986 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
1987 if ((n & 0xff) == 0)
1988 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1991 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1995 if (GET_CODE (operands[2]) == REG)
1996 return "add.l\t%S2,%S0";
1998 if (GET_CODE (operands[2]) == CONST_INT)
2000 HOST_WIDE_INT intval = INTVAL (operands[2]);
2002 /* See if we can finish with 2 bytes. */
2004 switch ((unsigned int) intval & 0xffffffff)
2009 return "adds\t%2,%S0";
2014 return "subs\t%G2,%S0";
2018 operands[2] = GEN_INT (intval >> 16);
2019 return "inc.w\t%2,%e0";
2023 operands[2] = GEN_INT (intval >> 16);
2024 return "dec.w\t%G2,%e0";
2027 /* See if we can finish with 4 bytes. */
2028 if ((intval & 0xffff) == 0)
2030 operands[2] = GEN_INT (intval >> 16);
2031 return "add.w\t%2,%e0";
2035 return "add.l\t%S2,%S0";
2040 compute_plussi_length (operands)
2043 enum machine_mode mode = GET_MODE (operands[0]);
2050 if (GET_CODE (operands[2]) == REG)
2053 if (GET_CODE (operands[2]) == CONST_INT)
2055 HOST_WIDE_INT n = INTVAL (operands[2]);
2057 if ((n & 0xffffff) == 0)
2059 if ((n & 0xffff) == 0)
2061 if ((n & 0xff) == 0)
2069 if (GET_CODE (operands[2]) == REG)
2072 if (GET_CODE (operands[2]) == CONST_INT)
2074 HOST_WIDE_INT intval = INTVAL (operands[2]);
2076 /* See if we can finish with 2 bytes. */
2078 switch ((unsigned int) intval & 0xffffffff)
2099 /* See if we can finish with 4 bytes. */
2100 if ((intval & 0xffff) == 0)
2109 compute_plussi_cc (operands)
2112 enum machine_mode mode = GET_MODE (operands[0]);
2123 if (GET_CODE (operands[2]) == REG)
2126 if (GET_CODE (operands[2]) == CONST_INT)
2128 HOST_WIDE_INT intval = INTVAL (operands[2]);
2130 /* See if we can finish with 2 bytes. */
2132 switch ((unsigned int) intval & 0xffffffff)
2137 return CC_NONE_0HIT;
2142 return CC_NONE_0HIT;
2153 /* See if we can finish with 4 bytes. */
2154 if ((intval & 0xffff) == 0)
2163 output_logical_op (mode, operands)
2164 enum machine_mode mode;
2167 /* Figure out the logical op that we need to perform. */
2168 enum rtx_code code = GET_CODE (operands[3]);
2169 /* Pretend that every byte is affected if both operands are registers. */
2170 const unsigned HOST_WIDE_INT intval =
2171 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2172 ? INTVAL (operands[2]) : 0x55555555);
2173 /* The determinant of the algorithm. If we perform an AND, 0
2174 affects a bit. Otherwise, 1 affects a bit. */
2175 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2176 /* Break up DET into pieces. */
2177 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2178 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2179 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2180 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2181 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2182 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2183 int lower_half_easy_p = 0;
2184 int upper_half_easy_p = 0;
2185 /* The name of an insn. */
2207 /* First, see if we can finish with one insn. */
2208 if ((TARGET_H8300H || TARGET_H8300S)
2212 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2213 output_asm_insn (insn_buf, operands);
2217 /* Take care of the lower byte. */
2220 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2221 output_asm_insn (insn_buf, operands);
2223 /* Take care of the upper byte. */
2226 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2227 output_asm_insn (insn_buf, operands);
2232 if (TARGET_H8300H || TARGET_H8300S)
2234 /* Determine if the lower half can be taken care of in no more
2236 lower_half_easy_p = (b0 == 0
2238 || (code != IOR && w0 == 0xffff));
2240 /* Determine if the upper half can be taken care of in no more
2242 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2243 || (code == AND && w1 == 0xff00));
2246 /* Check if doing everything with one insn is no worse than
2247 using multiple insns. */
2248 if ((TARGET_H8300H || TARGET_H8300S)
2249 && w0 != 0 && w1 != 0
2250 && !(lower_half_easy_p && upper_half_easy_p)
2251 && !(code == IOR && w1 == 0xffff
2252 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2254 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2255 output_asm_insn (insn_buf, operands);
2259 /* Take care of the lower and upper words individually. For
2260 each word, we try different methods in the order of
2262 1) the special insn (in case of AND or XOR),
2263 2) the word-wise insn, and
2264 3) The byte-wise insn. */
2266 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2267 output_asm_insn ((code == AND)
2268 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2270 else if ((TARGET_H8300H || TARGET_H8300S)
2274 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2275 output_asm_insn (insn_buf, operands);
2281 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2282 output_asm_insn (insn_buf, operands);
2286 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2287 output_asm_insn (insn_buf, operands);
2292 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2293 output_asm_insn ((code == AND)
2294 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2296 else if ((TARGET_H8300H || TARGET_H8300S)
2299 && (w0 & 0x8000) != 0)
2301 output_asm_insn ("exts.l\t%S0", operands);
2303 else if ((TARGET_H8300H || TARGET_H8300S)
2307 output_asm_insn ("extu.w\t%e0", operands);
2309 else if (TARGET_H8300H || TARGET_H8300S)
2313 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2314 output_asm_insn (insn_buf, operands);
2321 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2322 output_asm_insn (insn_buf, operands);
2326 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2327 output_asm_insn (insn_buf, operands);
2339 compute_logical_op_length (mode, operands)
2340 enum machine_mode mode;
2343 /* Figure out the logical op that we need to perform. */
2344 enum rtx_code code = GET_CODE (operands[3]);
2345 /* Pretend that every byte is affected if both operands are registers. */
2346 const unsigned HOST_WIDE_INT intval =
2347 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2348 ? INTVAL (operands[2]) : 0x55555555);
2349 /* The determinant of the algorithm. If we perform an AND, 0
2350 affects a bit. Otherwise, 1 affects a bit. */
2351 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2352 /* Break up DET into pieces. */
2353 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2354 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2355 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2356 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2357 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2358 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2359 int lower_half_easy_p = 0;
2360 int upper_half_easy_p = 0;
2362 unsigned int length = 0;
2367 /* First, see if we can finish with one insn. */
2368 if ((TARGET_H8300H || TARGET_H8300S)
2372 if (REG_P (operands[2]))
2379 /* Take care of the lower byte. */
2383 /* Take care of the upper byte. */
2389 if (TARGET_H8300H || TARGET_H8300S)
2391 /* Determine if the lower half can be taken care of in no more
2393 lower_half_easy_p = (b0 == 0
2395 || (code != IOR && w0 == 0xffff));
2397 /* Determine if the upper half can be taken care of in no more
2399 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2400 || (code == AND && w1 == 0xff00));
2403 /* Check if doing everything with one insn is no worse than
2404 using multiple insns. */
2405 if ((TARGET_H8300H || TARGET_H8300S)
2406 && w0 != 0 && w1 != 0
2407 && !(lower_half_easy_p && upper_half_easy_p)
2408 && !(code == IOR && w1 == 0xffff
2409 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2411 if (REG_P (operands[2]))
2418 /* Take care of the lower and upper words individually. For
2419 each word, we try different methods in the order of
2421 1) the special insn (in case of AND or XOR),
2422 2) the word-wise insn, and
2423 3) The byte-wise insn. */
2425 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2429 else if ((TARGET_H8300H || TARGET_H8300S)
2445 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2449 else if ((TARGET_H8300H || TARGET_H8300S)
2452 && (w0 & 0x8000) != 0)
2456 else if ((TARGET_H8300H || TARGET_H8300S)
2462 else if (TARGET_H8300H || TARGET_H8300S)
2484 compute_logical_op_cc (mode, operands)
2485 enum machine_mode mode;
2488 /* Figure out the logical op that we need to perform. */
2489 enum rtx_code code = GET_CODE (operands[3]);
2490 /* Pretend that every byte is affected if both operands are registers. */
2491 const unsigned HOST_WIDE_INT intval =
2492 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2493 ? INTVAL (operands[2]) : 0x55555555);
2494 /* The determinant of the algorithm. If we perform an AND, 0
2495 affects a bit. Otherwise, 1 affects a bit. */
2496 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2497 /* Break up DET into pieces. */
2498 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2499 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2500 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2501 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2502 int lower_half_easy_p = 0;
2503 int upper_half_easy_p = 0;
2504 /* Condition code. */
2505 enum attr_cc cc = CC_CLOBBER;
2510 /* First, see if we can finish with one insn. */
2511 if ((TARGET_H8300H || TARGET_H8300S)
2519 if (TARGET_H8300H || TARGET_H8300S)
2521 /* Determine if the lower half can be taken care of in no more
2523 lower_half_easy_p = (b0 == 0
2525 || (code != IOR && w0 == 0xffff));
2527 /* Determine if the upper half can be taken care of in no more
2529 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2530 || (code == AND && w1 == 0xff00));
2533 /* Check if doing everything with one insn is no worse than
2534 using multiple insns. */
2535 if ((TARGET_H8300H || TARGET_H8300S)
2536 && w0 != 0 && w1 != 0
2537 && !(lower_half_easy_p && upper_half_easy_p)
2538 && !(code == IOR && w1 == 0xffff
2539 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2545 if ((TARGET_H8300H || TARGET_H8300S)
2548 && (w0 & 0x8000) != 0)
2562 We devote a fair bit of code to getting efficient shifts since we
2563 can only shift one bit at a time on the H8/300 and H8/300H and only
2564 one or two bits at a time on the H8S.
2566 All shift code falls into one of the following ways of
2569 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2570 when a straight line shift is about the same size or smaller than
2573 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2574 off the bits we don't need. This is used when only a few of the
2575 bits in the original value will survive in the shifted value.
2577 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2578 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2579 shifts can be added if the shift count is slightly more than 8 or
2580 16. This case also includes other oddballs that are not worth
2583 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2585 For each shift count, we try to use code that has no trade-off
2586 between code size and speed whenever possible.
2588 If the trade-off is unavoidable, we try to be reasonable.
2589 Specifically, the fastest version is one instruction longer than
2590 the shortest version, we take the fastest version. We also provide
2591 the use a way to switch back to the shortest version with -Os.
2593 For the details of the shift algorithms for various shift counts,
2594 refer to shift_alg_[qhs]i. */
2597 nshift_operator (x, mode)
2599 enum machine_mode mode ATTRIBUTE_UNUSED;
2601 switch (GET_CODE (x))
2613 /* Emit code to do shifts. */
2616 expand_a_shift (mode, code, operands)
2617 enum machine_mode mode;
2621 emit_move_insn (operands[0], operands[1]);
2623 /* Need a loop to get all the bits we want - we generate the
2624 code at emit time, but need to allocate a scratch reg now. */
2626 emit_insn (gen_rtx_PARALLEL
2629 gen_rtx_SET (VOIDmode, operands[0],
2630 gen_rtx (code, mode, operands[0],
2632 gen_rtx_CLOBBER (VOIDmode,
2633 gen_rtx_SCRATCH (QImode)))));
2636 /* Symbols of the various modes which can be used as indices. */
2640 QIshift, HIshift, SIshift
2643 /* For single bit shift insns, record assembler and what bits of the
2644 condition code are valid afterwards (represented as various CC_FOO
2645 bits, 0 means CC isn't left in a usable state). */
2649 const char *const assembler;
2653 /* Assembler instruction shift table.
2655 These tables are used to look up the basic shifts.
2656 They are indexed by cpu, shift_type, and mode. */
2658 static const struct shift_insn shift_one[2][3][3] =
2664 { "shll\t%X0", CC_NO_CARRY },
2665 { "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2666 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
2668 /* SHIFT_LSHIFTRT */
2670 { "shlr\t%X0", CC_NO_CARRY },
2671 { "shlr\t%t0\n\trotxr\t%s0", 0 },
2672 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2674 /* SHIFT_ASHIFTRT */
2676 { "shar\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2677 { "shar\t%t0\n\trotxr\t%s0", 0 },
2678 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
2685 { "shll.b\t%X0", CC_NO_CARRY },
2686 { "shll.w\t%T0", CC_NO_CARRY },
2687 { "shll.l\t%S0", CC_NO_CARRY }
2689 /* SHIFT_LSHIFTRT */
2691 { "shlr.b\t%X0", CC_NO_CARRY },
2692 { "shlr.w\t%T0", CC_NO_CARRY },
2693 { "shlr.l\t%S0", CC_NO_CARRY }
2695 /* SHIFT_ASHIFTRT */
2697 { "shar.b\t%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2698 { "shar.w\t%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2699 { "shar.l\t%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2704 static const struct shift_insn shift_two[3][3] =
2708 { "shll.b\t#2,%X0", CC_NO_CARRY },
2709 { "shll.w\t#2,%T0", CC_NO_CARRY },
2710 { "shll.l\t#2,%S0", CC_NO_CARRY }
2712 /* SHIFT_LSHIFTRT */
2714 { "shlr.b\t#2,%X0", CC_NO_CARRY },
2715 { "shlr.w\t#2,%T0", CC_NO_CARRY },
2716 { "shlr.l\t#2,%S0", CC_NO_CARRY }
2718 /* SHIFT_ASHIFTRT */
2720 { "shar.b\t#2,%X0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2721 { "shar.w\t#2,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
2722 { "shar.l\t#2,%S0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY }
2726 /* Rotates are organized by which shift they'll be used in implementing.
2727 There's no need to record whether the cc is valid afterwards because
2728 it is the AND insn that will decide this. */
2730 static const char *const rotate_one[2][3][3] =
2737 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2740 /* SHIFT_LSHIFTRT */
2743 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2746 /* SHIFT_ASHIFTRT */
2749 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2761 /* SHIFT_LSHIFTRT */
2767 /* SHIFT_ASHIFTRT */
2776 static const char *const rotate_two[3][3] =
2784 /* SHIFT_LSHIFTRT */
2790 /* SHIFT_ASHIFTRT */
2799 /* Shift algorithm. */
2802 /* The number of bits to be shifted by shift1 and shift2. Valid
2803 when ALG is SHIFT_SPECIAL. */
2804 unsigned int remainder;
2806 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2807 const char *special;
2809 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2810 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2813 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2814 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2817 /* Valid CC flags. */
2821 static void get_shift_alg PARAMS ((enum shift_type,
2822 enum shift_mode, unsigned int,
2823 struct shift_info *));
2825 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2826 best algorithm for doing the shift. The assembler code is stored
2827 in the pointers in INFO. We achieve the maximum efficiency in most
2828 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2829 SImode in particular have a lot of room to optimize.
2831 We first determine the strategy of the shift algorithm by a table
2832 lookup. If that tells us to use a hand crafted assembly code, we
2833 go into the big switch statement to find what that is. Otherwise,
2834 we resort to a generic way, such as inlining. In either case, the
2835 result is returned through INFO. */
2838 get_shift_alg (shift_type, shift_mode, count, info)
2839 enum shift_type shift_type;
2840 enum shift_mode shift_mode;
2842 struct shift_info *info;
2846 /* Find the target CPU. */
2849 else if (TARGET_H8300H)
2854 /* Find the shift algorithm. */
2855 info->alg = SHIFT_LOOP;
2859 if (count < GET_MODE_BITSIZE (QImode))
2860 info->alg = shift_alg_qi[cpu][shift_type][count];
2864 if (count < GET_MODE_BITSIZE (HImode))
2865 info->alg = shift_alg_hi[cpu][shift_type][count];
2869 if (count < GET_MODE_BITSIZE (SImode))
2870 info->alg = shift_alg_si[cpu][shift_type][count];
2877 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2881 info->remainder = count;
2885 /* It is up to the caller to know that looping clobbers cc. */
2886 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2887 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2888 info->cc_valid_p = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2892 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2893 info->shift2 = rotate_two[shift_type][shift_mode];
2894 info->cc_valid_p = 0;
2898 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2899 info->remainder = 0;
2900 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2901 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2902 info->cc_valid_p = 0;
2906 /* Here we only deal with SHIFT_SPECIAL. */
2910 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2911 through the entire value. */
2912 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2914 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2926 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2928 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2930 case SHIFT_LSHIFTRT:
2932 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2934 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2936 case SHIFT_ASHIFTRT:
2937 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2941 else if ((8 <= count && count <= 13)
2942 || (TARGET_H8300S && count == 14))
2944 info->remainder = count - 8;
2949 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2951 case SHIFT_LSHIFTRT:
2954 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2955 info->shift1 = "shlr.b\t%s0";
2959 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
2962 case SHIFT_ASHIFTRT:
2965 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2966 info->shift1 = "shar.b\t%s0";
2970 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2975 else if (count == 14)
2981 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2983 case SHIFT_LSHIFTRT:
2985 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2987 case SHIFT_ASHIFTRT:
2989 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2990 else if (TARGET_H8300H)
2991 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2992 else /* TARGET_H8300S */
2997 else if (count == 15)
3002 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3004 case SHIFT_LSHIFTRT:
3005 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3007 case SHIFT_ASHIFTRT:
3008 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3015 if (TARGET_H8300 && 8 <= count && count <= 9)
3017 info->remainder = count - 8;
3022 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3024 case SHIFT_LSHIFTRT:
3025 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3026 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3028 case SHIFT_ASHIFTRT:
3029 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3033 else if (count == 8 && !TARGET_H8300)
3038 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3040 case SHIFT_LSHIFTRT:
3041 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3043 case SHIFT_ASHIFTRT:
3044 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3048 else if (count == 15 && TARGET_H8300)
3054 case SHIFT_LSHIFTRT:
3055 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\trotxl\t%y0,%y0";
3057 case SHIFT_ASHIFTRT:
3058 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3062 else if (count == 15 && !TARGET_H8300)
3067 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3069 case SHIFT_LSHIFTRT:
3070 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3072 case SHIFT_ASHIFTRT:
3076 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3077 || (TARGET_H8300H && 16 <= count && count <= 19)
3078 || (TARGET_H8300S && 16 <= count && count <= 21))
3080 info->remainder = count - 16;
3085 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3087 info->shift1 = "add.w\t%e0,%e0";
3089 case SHIFT_LSHIFTRT:
3092 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3093 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3097 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3100 case SHIFT_ASHIFTRT:
3103 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3104 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3108 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3113 else if (TARGET_H8300 && 24 <= count && count <= 28)
3115 info->remainder = count - 24;
3120 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3121 info->shift1 = "shll.b\t%z0";
3123 case SHIFT_LSHIFTRT:
3124 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3125 info->shift1 = "shlr.b\t%w0";
3127 case SHIFT_ASHIFTRT:
3128 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3129 info->shift1 = "shar.b\t%w0";
3133 else if ((TARGET_H8300H && count == 24)
3134 || (TARGET_H8300S && 24 <= count && count <= 25))
3136 info->remainder = count - 24;
3141 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3143 case SHIFT_LSHIFTRT:
3144 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3146 case SHIFT_ASHIFTRT:
3147 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3151 else if (!TARGET_H8300 && count == 28)
3157 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3159 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3161 case SHIFT_LSHIFTRT:
3163 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3165 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3167 case SHIFT_ASHIFTRT:
3171 else if (!TARGET_H8300 && count == 29)
3177 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3179 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3181 case SHIFT_LSHIFTRT:
3183 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3185 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3187 case SHIFT_ASHIFTRT:
3191 else if (!TARGET_H8300 && count == 30)
3197 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3199 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3201 case SHIFT_LSHIFTRT:
3203 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3205 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3207 case SHIFT_ASHIFTRT:
3211 else if (count == 31)
3218 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3220 case SHIFT_LSHIFTRT:
3221 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3223 case SHIFT_ASHIFTRT:
3224 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3233 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3235 case SHIFT_LSHIFTRT:
3236 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3238 case SHIFT_ASHIFTRT:
3239 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3252 info->shift2 = NULL;
3255 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3256 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3259 h8300_shift_needs_scratch_p (count, mode)
3261 enum machine_mode mode;
3266 if (GET_MODE_BITSIZE (mode) <= count)
3269 /* Find out the target CPU. */
3272 else if (TARGET_H8300H)
3277 /* Find the shift algorithm. */
3281 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3282 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3283 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3287 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3288 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3289 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3293 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3294 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3295 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3302 /* On H8/300H, count == 8 uses a scratch register. */
3303 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3304 || (TARGET_H8300H && mode == SImode && count == 8));
3307 /* Emit the assembler code for doing shifts. */
3310 output_a_shift (operands)
3313 static int loopend_lab;
3314 rtx shift = operands[3];
3315 enum machine_mode mode = GET_MODE (shift);
3316 enum rtx_code code = GET_CODE (shift);
3317 enum shift_type shift_type;
3318 enum shift_mode shift_mode;
3319 struct shift_info info;
3326 shift_mode = QIshift;
3329 shift_mode = HIshift;
3332 shift_mode = SIshift;
3341 shift_type = SHIFT_ASHIFTRT;
3344 shift_type = SHIFT_LSHIFTRT;
3347 shift_type = SHIFT_ASHIFT;
3353 if (GET_CODE (operands[2]) != CONST_INT)
3355 /* This case must be taken care of by one of the two splitters
3356 that convert a variable shift into a loop. */
3361 int n = INTVAL (operands[2]);
3363 /* If the count is negative, make it 0. */
3366 /* If the count is too big, truncate it.
3367 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3368 do the intuitive thing. */
3369 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3370 n = GET_MODE_BITSIZE (mode);
3372 get_shift_alg (shift_type, shift_mode, n, &info);
3377 output_asm_insn (info.special, operands);
3383 /* Emit two bit shifts first. */
3384 if (info.shift2 != NULL)
3386 for (; n > 1; n -= 2)
3387 output_asm_insn (info.shift2, operands);
3390 /* Now emit one bit shifts for any residual. */
3392 output_asm_insn (info.shift1, operands);
3394 /* Keep track of CC. */
3395 if (info.cc_valid_p)
3397 cc_status.value1 = operands[0];
3398 cc_status.flags |= info.cc_valid_p;
3404 int m = GET_MODE_BITSIZE (mode) - n;
3405 const int mask = (shift_type == SHIFT_ASHIFT
3406 ? ((1 << m) - 1) << n
3410 /* Not all possibilities of rotate are supported. They shouldn't
3411 be generated, but let's watch for 'em. */
3412 if (info.shift1 == 0)
3415 /* Emit two bit rotates first. */
3416 if (info.shift2 != NULL)
3418 for (; m > 1; m -= 2)
3419 output_asm_insn (info.shift2, operands);
3422 /* Now single bit rotates for any residual. */
3424 output_asm_insn (info.shift1, operands);
3426 /* Now mask off the high bits. */
3428 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3429 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3430 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3434 cc_status.value1 = operands[0];
3435 cc_status.flags |= CC_NO_CARRY;
3436 output_asm_insn (insn_buf, operands);
3441 /* A loop to shift by a "large" constant value.
3442 If we have shift-by-2 insns, use them. */
3443 if (info.shift2 != NULL)
3445 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3446 names_big[REGNO (operands[4])]);
3447 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3448 output_asm_insn (info.shift2, operands);
3449 output_asm_insn ("add #0xff,%X4", operands);
3450 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3452 output_asm_insn (info.shift1, operands);
3456 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3457 names_big[REGNO (operands[4])]);
3458 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3459 output_asm_insn (info.shift1, operands);
3460 output_asm_insn ("add #0xff,%X4", operands);
3461 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3472 h8300_asm_insn_count (template)
3473 const char *template;
3475 unsigned int count = 1;
3477 for (; *template; template++)
3478 if (*template == '\n')
3485 compute_a_shift_length (insn, operands)
3486 rtx insn ATTRIBUTE_UNUSED;
3489 rtx shift = operands[3];
3490 enum machine_mode mode = GET_MODE (shift);
3491 enum rtx_code code = GET_CODE (shift);
3492 enum shift_type shift_type;
3493 enum shift_mode shift_mode;
3494 struct shift_info info;
3495 unsigned int wlength = 0;
3500 shift_mode = QIshift;
3503 shift_mode = HIshift;
3506 shift_mode = SIshift;
3515 shift_type = SHIFT_ASHIFTRT;
3518 shift_type = SHIFT_LSHIFTRT;
3521 shift_type = SHIFT_ASHIFT;
3527 if (GET_CODE (operands[2]) != CONST_INT)
3529 /* Get the assembler code to do one shift. */
3530 get_shift_alg (shift_type, shift_mode, 1, &info);
3532 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3536 int n = INTVAL (operands[2]);
3538 /* If the count is negative, make it 0. */
3541 /* If the count is too big, truncate it.
3542 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3543 do the intuitive thing. */
3544 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3545 n = GET_MODE_BITSIZE (mode);
3547 get_shift_alg (shift_type, shift_mode, n, &info);
3552 wlength += h8300_asm_insn_count (info.special);
3554 /* Every assembly instruction used in SHIFT_SPECIAL case
3555 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3556 see xor.l, we just pretend that xor.l counts as two insns
3557 so that the insn length will be computed correctly. */
3558 if (strstr (info.special, "xor.l") != NULL)
3566 if (info.shift2 != NULL)
3568 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3572 wlength += h8300_asm_insn_count (info.shift1) * n;
3578 int m = GET_MODE_BITSIZE (mode) - n;
3580 /* Not all possibilities of rotate are supported. They shouldn't
3581 be generated, but let's watch for 'em. */
3582 if (info.shift1 == 0)
3585 if (info.shift2 != NULL)
3587 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3591 wlength += h8300_asm_insn_count (info.shift1) * m;
3593 /* Now mask off the high bits. */
3614 /* A loop to shift by a "large" constant value.
3615 If we have shift-by-2 insns, use them. */
3616 if (info.shift2 != NULL)
3618 wlength += 3 + h8300_asm_insn_count (info.shift2);
3620 wlength += h8300_asm_insn_count (info.shift1);
3624 wlength += 3 + h8300_asm_insn_count (info.shift1);
3634 /* A rotation by a non-constant will cause a loop to be generated, in
3635 which a rotation by one bit is used. A rotation by a constant,
3636 including the one in the loop, will be taken care of by
3637 emit_a_rotate () at the insn emit time. */
3640 expand_a_rotate (code, operands)
3644 rtx dst = operands[0];
3645 rtx src = operands[1];
3646 rtx rotate_amount = operands[2];
3647 enum machine_mode mode = GET_MODE (dst);
3650 /* We rotate in place. */
3651 emit_move_insn (dst, src);
3653 if (GET_CODE (rotate_amount) != CONST_INT)
3655 rtx counter = gen_reg_rtx (QImode);
3656 rtx start_label = gen_label_rtx ();
3657 rtx end_label = gen_label_rtx ();
3659 /* If the rotate amount is less than or equal to 0,
3660 we go out of the loop. */
3661 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3662 QImode, 0, end_label);
3664 /* Initialize the loop counter. */
3665 emit_move_insn (counter, rotate_amount);
3667 emit_label (start_label);
3669 /* Rotate by one bit. */
3670 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3671 emit_insn (gen_rtx_SET (mode, dst, tmp));
3673 /* Decrement the counter by 1. */
3674 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3675 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3677 /* If the loop counter is nonzero, we go back to the beginning
3679 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3682 emit_label (end_label);
3686 /* Rotate by AMOUNT bits. */
3687 tmp = gen_rtx (code, mode, dst, rotate_amount);
3688 emit_insn (gen_rtx_SET (mode, dst, tmp));
3694 /* Emit rotate insns. */
3697 emit_a_rotate (code, operands)
3701 rtx dst = operands[0];
3702 rtx rotate_amount = operands[2];
3703 enum shift_mode rotate_mode;
3704 enum shift_type rotate_type;
3705 const char *insn_buf;
3708 enum machine_mode mode = GET_MODE (dst);
3710 if (GET_CODE (rotate_amount) != CONST_INT)
3716 rotate_mode = QIshift;
3719 rotate_mode = HIshift;
3722 rotate_mode = SIshift;
3731 rotate_type = SHIFT_ASHIFT;
3734 rotate_type = SHIFT_LSHIFTRT;
3740 amount = INTVAL (rotate_amount);
3742 /* Clean up AMOUNT. */
3745 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3746 amount = GET_MODE_BITSIZE (mode);
3748 /* Determine the faster direction. After this phase, amount will be
3749 at most a half of GET_MODE_BITSIZE (mode). */
3750 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3752 /* Flip the direction. */
3753 amount = GET_MODE_BITSIZE (mode) - amount;
3755 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3758 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3759 boost up the rotation. */
3760 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3761 || (mode == HImode && TARGET_H8300H && amount >= 6)
3762 || (mode == HImode && TARGET_H8300S && amount == 8)
3763 || (mode == SImode && TARGET_H8300H && amount >= 10)
3764 || (mode == SImode && TARGET_H8300S && amount >= 13))
3769 /* This code works on any family. */
3770 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3771 output_asm_insn (insn_buf, operands);
3775 /* This code works on the H8/300H and H8S. */
3776 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3777 output_asm_insn (insn_buf, operands);
3784 /* Adjust AMOUNT and flip the direction. */
3785 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3787 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3790 /* Emit rotate insns. */
3791 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3794 insn_buf = rotate_two[rotate_type][rotate_mode];
3796 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3798 for (; amount >= bits; amount -= bits)
3799 output_asm_insn (insn_buf, operands);
3805 /* Fix the operands of a gen_xxx so that it could become a bit
3809 fix_bit_operand (operands, what, type)
3814 /* The bit_operand predicate accepts any memory during RTL generation, but
3815 only 'U' memory afterwards, so if this is a MEM operand, we must force
3816 it to be valid for 'U' by reloading the address. */
3818 if ((what == 0 && single_zero_operand (operands[2], QImode))
3819 || (what == 1 && single_one_operand (operands[2], QImode)))
3821 /* OK to have a memory dest. */
3822 if (GET_CODE (operands[0]) == MEM
3823 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3825 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3826 copy_to_mode_reg (Pmode,
3827 XEXP (operands[0], 0)));
3828 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3832 if (GET_CODE (operands[1]) == MEM
3833 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3835 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3836 copy_to_mode_reg (Pmode,
3837 XEXP (operands[1], 0)));
3838 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3844 /* Dest and src op must be register. */
3846 operands[1] = force_reg (QImode, operands[1]);
3848 rtx res = gen_reg_rtx (QImode);
3849 emit_insn (gen_rtx_SET (VOIDmode, res,
3850 gen_rtx (type, QImode, operands[1], operands[2])));
3851 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3856 /* Return nonzero if FUNC is an interrupt function as specified
3857 by the "interrupt" attribute. */
3860 h8300_interrupt_function_p (func)
3865 if (TREE_CODE (func) != FUNCTION_DECL)
3868 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3869 return a != NULL_TREE;
3872 /* Return nonzero if FUNC is an OS_Task function as specified
3873 by the "OS_Task" attribute. */
3876 h8300_os_task_function_p (func)
3881 if (TREE_CODE (func) != FUNCTION_DECL)
3884 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3885 return a != NULL_TREE;
3888 /* Return nonzero if FUNC is a monitor function as specified
3889 by the "monitor" attribute. */
3892 h8300_monitor_function_p (func)
3897 if (TREE_CODE (func) != FUNCTION_DECL)
3900 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
3901 return a != NULL_TREE;
3904 /* Return nonzero if FUNC is a function that should be called
3905 through the function vector. */
3908 h8300_funcvec_function_p (func)
3913 if (TREE_CODE (func) != FUNCTION_DECL)
3916 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
3917 return a != NULL_TREE;
3920 /* Return nonzero if DECL is a variable that's in the eight bit
3924 h8300_eightbit_data_p (decl)
3929 if (TREE_CODE (decl) != VAR_DECL)
3932 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
3933 return a != NULL_TREE;
3936 /* Return nonzero if DECL is a variable that's in the tiny
3940 h8300_tiny_data_p (decl)
3945 if (TREE_CODE (decl) != VAR_DECL)
3948 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
3949 return a != NULL_TREE;
3952 /* Generate an 'interrupt_handler' attribute for decls. */
3955 h8300_insert_attributes (node, attributes)
3959 if (!pragma_interrupt
3960 || TREE_CODE (node) != FUNCTION_DECL)
3963 pragma_interrupt = 0;
3965 /* Add an 'interrupt_handler' attribute. */
3966 *attributes = tree_cons (get_identifier ("interrupt_handler"),
3970 /* Supported attributes:
3972 interrupt_handler: output a prologue and epilogue suitable for an
3975 function_vector: This function should be called through the
3978 eightbit_data: This variable lives in the 8-bit data area and can
3979 be referenced with 8-bit absolute memory addresses.
3981 tiny_data: This variable lives in the tiny data area and can be
3982 referenced with 16-bit absolute memory references. */
3984 const struct attribute_spec h8300_attribute_table[] =
3986 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3987 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3988 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3989 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3990 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
3991 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
3992 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
3993 { NULL, 0, 0, false, false, false, NULL }
3997 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
3998 struct attribute_spec.handler. */
4000 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
4003 tree args ATTRIBUTE_UNUSED;
4004 int flags ATTRIBUTE_UNUSED;
4007 if (TREE_CODE (*node) != FUNCTION_DECL)
4009 warning ("`%s' attribute only applies to functions",
4010 IDENTIFIER_POINTER (name));
4011 *no_add_attrs = true;
4017 /* Handle an "eightbit_data" attribute; arguments as in
4018 struct attribute_spec.handler. */
4020 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
4023 tree args ATTRIBUTE_UNUSED;
4024 int flags ATTRIBUTE_UNUSED;
4029 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4031 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4035 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4036 *no_add_attrs = true;
4042 /* Handle an "tiny_data" attribute; arguments as in
4043 struct attribute_spec.handler. */
4045 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
4048 tree args ATTRIBUTE_UNUSED;
4049 int flags ATTRIBUTE_UNUSED;
4054 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4056 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4060 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4061 *no_add_attrs = true;
4068 h8300_encode_label (decl)
4071 const char *str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
4072 const int len = strlen (str);
4073 char *newstr = alloca (len + 2);
4076 strcpy (&newstr[1], str);
4078 XSTR (XEXP (DECL_RTL (decl), 0), 0) =
4079 ggc_alloc_string (newstr, len + 1);
4082 /* If we are referencing a function that is supposed to be called
4083 through the function vector, the SYMBOL_REF_FLAG in the rtl
4084 so the call patterns can generate the correct code. */
4087 h8300_encode_section_info (decl, first)
4091 if (TREE_CODE (decl) == FUNCTION_DECL
4092 && h8300_funcvec_function_p (decl))
4093 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
4094 else if (TREE_CODE (decl) == VAR_DECL
4095 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4097 if (h8300_eightbit_data_p (decl))
4098 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
4099 else if (first && h8300_tiny_data_p (decl))
4100 h8300_encode_label (decl);
4104 /* Undo the effects of the above. */
4107 h8300_strip_name_encoding (str)
4110 return str + (*str == '*' || *str == '@' || *str == '&');
4114 output_simode_bld (bild, operands)
4120 /* Clear the destination register. */
4121 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4123 /* Now output the bit load or bit inverse load, and store it in
4126 output_asm_insn ("bild\t%Z2,%Y1", operands);
4128 output_asm_insn ("bld\t%Z2,%Y1", operands);
4130 output_asm_insn ("bst\t#0,%w0", operands);
4134 /* Determine if we can clear the destination first. */
4135 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4136 && REGNO (operands[0]) != REGNO (operands[1]));
4139 output_asm_insn ("sub.l\t%S0,%S0", operands);
4141 /* Output the bit load or bit inverse load. */
4143 output_asm_insn ("bild\t%Z2,%Y1", operands);
4145 output_asm_insn ("bld\t%Z2,%Y1", operands);
4148 output_asm_insn ("xor.l\t%S0,%S0", operands);
4150 /* Perform the bit store. */
4151 output_asm_insn ("bst\t#0,%w0", operands);
4158 /* Given INSN and its current length LENGTH, return the adjustment
4159 (in bytes) to correctly compute INSN's length.
4161 We use this to get the lengths of various memory references correct. */
4164 h8300_adjust_insn_length (insn, length)
4166 int length ATTRIBUTE_UNUSED;
4168 rtx pat = PATTERN (insn);
4170 /* We must filter these out before calling get_attr_adjust_length. */
4171 if (GET_CODE (pat) == USE
4172 || GET_CODE (pat) == CLOBBER
4173 || GET_CODE (pat) == SEQUENCE
4174 || GET_CODE (pat) == ADDR_VEC
4175 || GET_CODE (pat) == ADDR_DIFF_VEC)
4178 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
4181 /* Adjust length for reg->mem and mem->reg copies. */
4182 if (GET_CODE (pat) == SET
4183 && (GET_CODE (SET_SRC (pat)) == MEM
4184 || GET_CODE (SET_DEST (pat)) == MEM))
4186 /* This insn might need a length adjustment. */
4189 if (GET_CODE (SET_SRC (pat)) == MEM)
4190 addr = XEXP (SET_SRC (pat), 0);
4192 addr = XEXP (SET_DEST (pat), 0);
4196 /* On the H8/300, we subtract the difference between the
4197 actual length and the longest one, which is @(d:16,ERs). */
4199 /* @Rs is 2 bytes shorter than the longest. */
4200 if (GET_CODE (addr) == REG)
4203 /* @aa:8 is 2 bytes shorter than the longest. */
4204 if (GET_MODE (SET_SRC (pat)) == QImode
4205 && h8300_eightbit_constant_address_p (addr))
4210 /* On the H8/300H and H8S, we subtract the difference
4211 between the actual length and the longest one, which is
4214 /* @ERs is 6 bytes shorter than the longest. */
4215 if (GET_CODE (addr) == REG)
4218 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4219 if (GET_CODE (addr) == PLUS
4220 && GET_CODE (XEXP (addr, 0)) == REG
4221 && GET_CODE (XEXP (addr, 1)) == CONST_INT
4222 && INTVAL (XEXP (addr, 1)) > -32768
4223 && INTVAL (XEXP (addr, 1)) < 32767)
4226 /* @aa:8 is 6 bytes shorter than the longest. */
4227 if (GET_MODE (SET_SRC (pat)) == QImode
4228 && h8300_eightbit_constant_address_p (addr))
4231 /* @aa:16 is 4 bytes shorter than the longest. */
4232 if (h8300_tiny_constant_address_p (addr))
4235 /* @aa:24 is 2 bytes shorter than the longest. */
4236 if (GET_CODE (addr) == CONST_INT)
4241 /* Loading some constants needs adjustment. */
4242 if (GET_CODE (pat) == SET
4243 && GET_CODE (SET_SRC (pat)) == CONST_INT
4244 && GET_MODE (SET_DEST (pat)) == SImode
4245 && INTVAL (SET_SRC (pat)) != 0)
4247 int val = INTVAL (SET_SRC (pat));
4250 && ((val & 0xffff) == 0
4251 || ((val >> 16) & 0xffff) == 0))
4254 if (TARGET_H8300H || TARGET_H8300S)
4256 if (val == (val & 0xff)
4257 || val == (val & 0xff00))
4260 switch (val & 0xffffffff)
4276 /* Rotations need various adjustments. */
4277 if (GET_CODE (pat) == SET
4278 && (GET_CODE (SET_SRC (pat)) == ROTATE
4279 || GET_CODE (SET_SRC (pat)) == ROTATERT))
4281 rtx src = SET_SRC (pat);
4282 enum machine_mode mode = GET_MODE (src);
4286 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
4289 amount = INTVAL (XEXP (src, 1));
4291 /* Clean up AMOUNT. */
4294 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4295 amount = GET_MODE_BITSIZE (mode);
4297 /* Determine the faster direction. After this phase, amount
4298 will be at most a half of GET_MODE_BITSIZE (mode). */
4299 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4300 /* Flip the direction. */
4301 amount = GET_MODE_BITSIZE (mode) - amount;
4303 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4304 boost up the rotation. */
4305 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4306 || (mode == HImode && TARGET_H8300H && amount >= 6)
4307 || (mode == HImode && TARGET_H8300S && amount == 8)
4308 || (mode == SImode && TARGET_H8300H && amount >= 10)
4309 || (mode == SImode && TARGET_H8300S && amount >= 13))
4311 /* Adjust AMOUNT and flip the direction. */
4312 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4316 /* We use 2-bit rotations on the H8S. */
4318 amount = amount / 2 + amount % 2;
4320 /* The H8/300 uses three insns to rotate one bit, taking 6
4322 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4324 return -(20 - states);
4330 #ifndef OBJECT_FORMAT_ELF
4332 h8300_asm_named_section (name, flags)
4334 unsigned int flags ATTRIBUTE_UNUSED;
4336 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4337 fprintf (asm_out_file, "\t.section %s\n", name);
4339 #endif /* ! OBJECT_FORMAT_ELF */
4341 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4342 which is a special case of the 'R' operand. */
4345 h8300_eightbit_constant_address_p (x)
4348 /* The ranges of the 8-bit area. */
4349 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4350 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4351 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4352 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4353 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4354 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4356 unsigned HOST_WIDE_INT addr;
4358 /* We accept symbols declared with eightbit_data. */
4359 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_FLAG (x))
4362 if (GET_CODE (x) != CONST_INT)
4368 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4369 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4370 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4373 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4374 on H8/300H and H8S. */
4377 h8300_tiny_constant_address_p (x)
4380 /* The ranges of the 16-bit area. */
4381 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4382 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4383 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4384 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4385 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4386 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4387 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4388 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4390 unsigned HOST_WIDE_INT addr;
4392 /* We accept symbols declared with tiny_data. */
4393 if (GET_CODE (x) == SYMBOL_REF && TINY_DATA_NAME_P (XSTR (x, 0)))
4396 if (GET_CODE (x) != CONST_INT)
4402 || ((TARGET_H8300H && !TARGET_NORMAL_MODE)
4403 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4404 || ((TARGET_H8300S && !TARGET_NORMAL_MODE)
4405 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4409 byte_accesses_mergeable_p (addr1, addr2)
4412 HOST_WIDE_INT offset1, offset2;
4420 else if (GET_CODE (addr1) == PLUS
4421 && REG_P (XEXP (addr1, 0))
4422 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4424 reg1 = XEXP (addr1, 0);
4425 offset1 = INTVAL (XEXP (addr1, 1));
4435 else if (GET_CODE (addr2) == PLUS
4436 && REG_P (XEXP (addr2, 0))
4437 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4439 reg2 = XEXP (addr2, 0);
4440 offset2 = INTVAL (XEXP (addr2, 1));
4445 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4446 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4448 && offset1 + 1 == offset2)