1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Forward declarations. */
49 static const char *byte_reg PARAMS ((rtx, int));
50 static int h8300_interrupt_function_p PARAMS ((tree));
51 static int h8300_monitor_function_p PARAMS ((tree));
52 static int h8300_os_task_function_p PARAMS ((tree));
53 static void dosize PARAMS ((int, unsigned int));
54 static int round_frame_size PARAMS ((int));
55 static unsigned int compute_saved_regs PARAMS ((void));
56 static void push PARAMS ((int));
57 static void pop PARAMS ((int));
58 static const char *cond_string PARAMS ((enum rtx_code));
59 static unsigned int h8300_asm_insn_count PARAMS ((const char *));
60 const struct attribute_spec h8300_attribute_table[];
61 static tree h8300_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
62 static tree h8300_handle_eightbit_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
63 static tree h8300_handle_tiny_data_attribute PARAMS ((tree *, tree, tree, int, bool *));
64 static void h8300_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
65 static void h8300_insert_attributes PARAMS ((tree, tree *));
66 #ifndef OBJECT_FORMAT_ELF
67 static void h8300_asm_named_section PARAMS ((const char *, unsigned int));
69 static void h8300_encode_section_info PARAMS ((tree, rtx, int));
70 static int const_costs PARAMS ((rtx, enum rtx_code, enum rtx_code));
71 static int h8300_and_costs PARAMS ((rtx));
72 static int h8300_shift_costs PARAMS ((rtx));
73 static bool h8300_rtx_costs PARAMS ((rtx, int, int, int *));
75 /* CPU_TYPE, says what cpu we're compiling for. */
78 /* True if a #pragma interrupt has been seen for the current function. */
79 static int pragma_interrupt;
81 /* True if a #pragma saveall has been seen for the current function. */
82 static int pragma_saveall;
84 static const char *const names_big[] =
85 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
87 static const char *const names_extended[] =
88 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
90 static const char *const names_upper_extended[] =
91 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
93 /* Points to one of the above. */
94 /* ??? The above could be put in an array indexed by CPU_TYPE. */
95 const char * const *h8_reg_names;
97 /* Various operations needed by the following, indexed by CPU_TYPE. */
99 const char *h8_push_op, *h8_pop_op, *h8_mov_op;
101 /* Machine-specific symbol_ref flags. */
102 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
103 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
104 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
106 /* Initialize the GCC target structure. */
107 #undef TARGET_ATTRIBUTE_TABLE
108 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
110 #undef TARGET_ASM_ALIGNED_HI_OP
111 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
113 #undef TARGET_ASM_FUNCTION_EPILOGUE
114 #define TARGET_ASM_FUNCTION_EPILOGUE h8300_output_function_epilogue
115 #undef TARGET_ENCODE_SECTION_INFO
116 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
118 #undef TARGET_INSERT_ATTRIBUTES
119 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
121 #undef TARGET_RTX_COSTS
122 #define TARGET_RTX_COSTS h8300_rtx_costs
124 struct gcc_target targetm = TARGET_INITIALIZER;
126 /* See below where shifts are handled for explanation of this enum. */
136 /* Symbols of the various shifts which can be used as indices. */
140 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT
143 /* Macros to keep the shift algorithm tables small. */
144 #define INL SHIFT_INLINE
145 #define ROT SHIFT_ROT_AND
146 #define LOP SHIFT_LOOP
147 #define SPC SHIFT_SPECIAL
149 /* The shift algorithms for each machine, mode, shift type, and shift
150 count are defined below. The three tables below correspond to
151 QImode, HImode, and SImode, respectively. Each table is organized
152 by, in the order of indices, machine, shift type, and shift count. */
154 static enum shift_alg shift_alg_qi[3][3][8] = {
157 /* 0 1 2 3 4 5 6 7 */
158 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
159 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
160 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
164 /* 0 1 2 3 4 5 6 7 */
165 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
166 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
167 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */
171 /* 0 1 2 3 4 5 6 7 */
172 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */
173 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */
174 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */
178 static enum shift_alg shift_alg_hi[3][3][16] = {
181 /* 0 1 2 3 4 5 6 7 */
182 /* 8 9 10 11 12 13 14 15 */
183 { INL, INL, INL, INL, INL, INL, INL, SPC,
184 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
185 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
186 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
187 { INL, INL, INL, INL, INL, LOP, LOP, SPC,
188 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
192 /* 0 1 2 3 4 5 6 7 */
193 /* 8 9 10 11 12 13 14 15 */
194 { INL, INL, INL, INL, INL, INL, INL, SPC,
195 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
196 { INL, INL, INL, INL, INL, INL, INL, SPC,
197 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
198 { INL, INL, INL, INL, INL, INL, INL, SPC,
199 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
203 /* 0 1 2 3 4 5 6 7 */
204 /* 8 9 10 11 12 13 14 15 */
205 { INL, INL, INL, INL, INL, INL, INL, INL,
206 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */
207 { INL, INL, INL, INL, INL, INL, INL, INL,
208 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
209 { INL, INL, INL, INL, INL, INL, INL, INL,
210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
214 static enum shift_alg shift_alg_si[3][3][32] = {
217 /* 0 1 2 3 4 5 6 7 */
218 /* 8 9 10 11 12 13 14 15 */
219 /* 16 17 18 19 20 21 22 23 */
220 /* 24 25 26 27 28 29 30 31 */
221 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
222 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
223 SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
224 SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT */
225 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
226 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
227 SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
228 SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
229 { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
230 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
231 SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
232 SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
236 /* 0 1 2 3 4 5 6 7 */
237 /* 8 9 10 11 12 13 14 15 */
238 /* 16 17 18 19 20 21 22 23 */
239 /* 24 25 26 27 28 29 30 31 */
240 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
241 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
242 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
243 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
244 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
245 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
246 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
247 SPC, LOP, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
248 { INL, INL, INL, INL, INL, LOP, LOP, LOP,
249 SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
250 SPC, SPC, SPC, SPC, LOP, LOP, LOP, LOP,
251 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
255 /* 0 1 2 3 4 5 6 7 */
256 /* 8 9 10 11 12 13 14 15 */
257 /* 16 17 18 19 20 21 22 23 */
258 /* 24 25 26 27 28 29 30 31 */
259 { INL, INL, INL, INL, INL, INL, INL, INL,
260 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
261 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
262 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */
263 { INL, INL, INL, INL, INL, INL, INL, INL,
264 INL, INL, INL, LOP, LOP, LOP, LOP, SPC,
265 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
266 SPC, SPC, LOP, LOP, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
267 { INL, INL, INL, INL, INL, INL, INL, INL,
268 INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
269 SPC, SPC, SPC, SPC, SPC, SPC, LOP, LOP,
270 SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
286 /* Initialize various cpu specific globals at start up. */
291 static const char *const h8_push_ops[2] = { "push" , "push.l" };
292 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" };
293 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" };
297 cpu_type = (int) CPU_H8300;
298 h8_reg_names = names_big;
302 /* For this we treat the H8/300H and H8S the same. */
303 cpu_type = (int) CPU_H8300H;
304 h8_reg_names = names_extended;
306 h8_push_op = h8_push_ops[cpu_type];
307 h8_pop_op = h8_pop_ops[cpu_type];
308 h8_mov_op = h8_mov_ops[cpu_type];
310 if (!TARGET_H8300S && TARGET_MAC)
312 error ("-ms2600 is used without -ms");
313 target_flags |= MASK_H8300S;
316 if (TARGET_H8300 && TARGET_NORMAL_MODE)
318 error ("-mn is used without -mh or -ms");
319 target_flags ^= MASK_NORMAL_MODE;
322 /* Some of the shifts are optimized for speed by default.
323 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
324 If optimizing for size, change shift_alg for those shift to
329 shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
330 shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
331 shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
332 shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
334 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
335 shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
337 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
338 shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
341 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
342 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
344 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP;
345 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP;
347 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP;
348 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP;
349 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
350 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
353 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
362 static const char *const names_small[] = {
363 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
364 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
367 return names_small[REGNO (x) * 2 + b];
370 /* REGNO must be saved/restored across calls if this macro is true. */
372 #define WORD_REG_USED(regno) \
374 /* No need to save registers if this function will not return. */ \
375 && ! TREE_THIS_VOLATILE (current_function_decl) \
377 /* Save any call saved register that was used. */ \
378 || (regs_ever_live[regno] && !call_used_regs[regno]) \
379 /* Save the frame pointer if it was used. */ \
380 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
381 /* Save any register used in an interrupt handler. */ \
382 || (h8300_current_function_interrupt_function_p () \
383 && regs_ever_live[regno]) \
384 /* Save call clobbered registers in non-leaf interrupt \
386 || (h8300_current_function_interrupt_function_p () \
387 && call_used_regs[regno] \
388 && !current_function_is_leaf)))
390 /* Output assembly language to FILE for the operation OP with operand size
391 SIZE to adjust the stack pointer. */
398 /* H8/300 cannot add/subtract a large constant with a single
399 instruction. If a temporary register is available, load the
400 constant to it and then do the addition. */
403 && !h8300_current_function_interrupt_function_p ()
404 && !(current_function_needs_context && sign < 0))
407 rtx r3 = gen_rtx_REG (Pmode, 3);
408 emit_insn (gen_rtx_SET (Pmode, r3, GEN_INT (sign * size)));
409 new_sp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, r3);
410 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
414 /* The stack adjustment made here is further optimized by the
415 splitter. In case of H8/300, the splitter always splits the
416 addition emitted here to make the adjustment
418 rtx new_sp = plus_constant (stack_pointer_rtx, sign * size);
419 emit_insn (gen_rtx_SET (Pmode, stack_pointer_rtx, new_sp));
423 /* Round up frame size SIZE. */
426 round_frame_size (size)
429 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1)
430 & -STACK_BOUNDARY / BITS_PER_UNIT);
433 /* Compute which registers to push/pop.
434 Return a bit vector of registers. */
437 compute_saved_regs ()
439 unsigned int saved_regs = 0;
442 /* Construct a bit vector of registers to be pushed/popped. */
443 for (regno = 0; regno <= FRAME_POINTER_REGNUM; regno++)
445 if (WORD_REG_USED (regno))
446 saved_regs |= 1 << regno;
449 /* Don't push/pop the frame pointer as it is treated separately. */
450 if (frame_pointer_needed)
451 saved_regs &= ~(1 << FRAME_POINTER_REGNUM);
456 /* Emit an insn to push register RN. */
462 rtx reg = gen_rtx_REG (word_mode, rn);
466 x = gen_push_h8300 (reg);
468 x = gen_push_h8300hs (reg);
470 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
473 /* Emit an insn to pop register RN. */
479 rtx reg = gen_rtx_REG (word_mode, rn);
483 x = gen_pop_h8300 (reg);
485 x = gen_pop_h8300hs (reg);
487 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
490 /* This is what the stack looks like after the prolog of
491 a function with a frame has been set up:
497 <saved registers> <- sp
499 This is what the stack looks like after the prolog of
500 a function which doesn't have a frame:
505 <saved registers> <- sp
508 /* Generate RTL code for the function prologue. */
511 h8300_expand_prologue ()
517 /* If the current function has the OS_Task attribute set, then
518 we have a naked prologue. */
519 if (h8300_os_task_function_p (current_function_decl))
522 if (h8300_monitor_function_p (current_function_decl))
523 /* My understanding of monitor functions is they act just like
524 interrupt functions, except the prologue must mask
526 emit_insn (gen_monitor_prologue ());
528 if (frame_pointer_needed)
531 push (FRAME_POINTER_REGNUM);
532 emit_insn (gen_rtx_SET (Pmode, frame_pointer_rtx, stack_pointer_rtx));
535 /* Leave room for locals. */
536 dosize (-1, round_frame_size (get_frame_size ()));
538 /* Push the rest of the registers in ascending order. */
539 saved_regs = compute_saved_regs ();
540 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs)
543 if (saved_regs & (1 << regno))
547 /* See how many registers we can push at the same time. */
548 if ((regno == 0 || regno == 4)
549 && ((saved_regs >> regno) & 0x0f) == 0x0f)
552 else if ((regno == 0 || regno == 4)
553 && ((saved_regs >> regno) & 0x07) == 0x07)
556 else if ((regno == 0 || regno == 2 || regno == 4 || regno == 6)
557 && ((saved_regs >> regno) & 0x03) == 0x03)
567 emit_insn (gen_stm_h8300s_2 (gen_rtx_REG (SImode, regno),
568 gen_rtx_REG (SImode, regno + 1)));
571 emit_insn (gen_stm_h8300s_3 (gen_rtx_REG (SImode, regno),
572 gen_rtx_REG (SImode, regno + 1),
573 gen_rtx_REG (SImode, regno + 2)));
576 emit_insn (gen_stm_h8300s_4 (gen_rtx_REG (SImode, regno),
577 gen_rtx_REG (SImode, regno + 1),
578 gen_rtx_REG (SImode, regno + 2),
579 gen_rtx_REG (SImode, regno + 3)));
589 h8300_can_use_return_insn_p ()
591 return (reload_completed
592 && !frame_pointer_needed
593 && get_frame_size () == 0
594 && compute_saved_regs () == 0);
597 /* Generate RTL code for the function epilogue. */
600 h8300_expand_epilogue ()
606 if (h8300_os_task_function_p (current_function_decl))
607 /* OS_Task epilogues are nearly naked -- they just have an
611 /* Pop the saved registers in descending order. */
612 saved_regs = compute_saved_regs ();
613 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs)
616 if (saved_regs & (1 << regno))
620 /* See how many registers we can pop at the same time. */
621 if ((regno == 7 || regno == 3)
622 && ((saved_regs >> (regno - 3)) & 0x0f) == 0x0f)
625 else if ((regno == 6 || regno == 2)
626 && ((saved_regs >> (regno - 2)) & 0x07) == 0x07)
629 else if ((regno == 7 || regno == 5 || regno == 3 || regno == 1)
630 && ((saved_regs >> (regno - 1)) & 0x03) == 0x03)
640 emit_insn (gen_ldm_h8300s_2 (gen_rtx_REG (SImode, regno - 1),
641 gen_rtx_REG (SImode, regno)));
644 emit_insn (gen_ldm_h8300s_3 (gen_rtx_REG (SImode, regno - 2),
645 gen_rtx_REG (SImode, regno - 1),
646 gen_rtx_REG (SImode, regno)));
649 emit_insn (gen_ldm_h8300s_4 (gen_rtx_REG (SImode, regno - 3),
650 gen_rtx_REG (SImode, regno - 2),
651 gen_rtx_REG (SImode, regno - 1),
652 gen_rtx_REG (SImode, regno)));
660 /* Deallocate locals. */
661 dosize (1, round_frame_size (get_frame_size ()));
663 /* Pop frame pointer if we had one. */
664 if (frame_pointer_needed)
665 pop (FRAME_POINTER_REGNUM);
668 /* Output assembly language code for the function epilogue. */
671 h8300_output_function_epilogue (file, size)
672 FILE *file ATTRIBUTE_UNUSED;
673 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
678 /* Return nonzero if the current function is an interrupt
682 h8300_current_function_interrupt_function_p ()
684 return (h8300_interrupt_function_p (current_function_decl)
685 || h8300_monitor_function_p (current_function_decl));
688 /* Output assembly code for the start of the file. */
691 asm_file_start (file)
694 fprintf (file, ";\tGCC For the Hitachi H8/300\n");
695 fprintf (file, ";\tBy Hitachi America Ltd and Cygnus Support\n");
698 fprintf (file, "; -Os\n");
700 fprintf (file, "; -O%d\n", optimize);
702 fprintf (file, "\n\t.h8300h\n");
703 else if (TARGET_H8300S)
704 fprintf (file, "\n\t.h8300s\n");
706 fprintf (file, "\n\n");
707 output_file_directive (file, main_input_filename);
710 /* Output assembly language code for the end of file. */
716 fprintf (file, "\t.end\n");
719 /* Return true if OP is a valid source operand for an integer move
723 general_operand_src (op, mode)
725 enum machine_mode mode;
727 if (GET_MODE (op) == mode
728 && GET_CODE (op) == MEM
729 && GET_CODE (XEXP (op, 0)) == POST_INC)
731 return general_operand (op, mode);
734 /* Return true if OP is a valid destination operand for an integer move
738 general_operand_dst (op, mode)
740 enum machine_mode mode;
742 if (GET_MODE (op) == mode
743 && GET_CODE (op) == MEM
744 && GET_CODE (XEXP (op, 0)) == PRE_DEC)
746 return general_operand (op, mode);
749 /* Return true if OP is a constant that contains only one 1 in its
750 binary representation. */
753 single_one_operand (operand, mode)
755 enum machine_mode mode ATTRIBUTE_UNUSED;
757 if (GET_CODE (operand) == CONST_INT)
759 /* We really need to do this masking because 0x80 in QImode is
760 represented as -128 for example. */
761 if (exact_log2 (INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
768 /* Return true if OP is a constant that contains only one 0 in its
769 binary representation. */
772 single_zero_operand (operand, mode)
774 enum machine_mode mode ATTRIBUTE_UNUSED;
776 if (GET_CODE (operand) == CONST_INT)
778 /* We really need to do this masking because 0x80 in QImode is
779 represented as -128 for example. */
780 if (exact_log2 (~INTVAL (operand) & GET_MODE_MASK (mode)) >= 0)
787 /* Return true if OP is a valid call operand. */
790 call_insn_operand (op, mode)
792 enum machine_mode mode ATTRIBUTE_UNUSED;
794 if (GET_CODE (op) == MEM)
796 rtx inside = XEXP (op, 0);
797 if (register_operand (inside, Pmode))
799 if (CONSTANT_ADDRESS_P (inside))
805 /* Return 1 if an addition/subtraction of a constant integer can be
806 transformed into two consecutive adds/subs that are faster than the
807 straightforward way. Otherwise, return 0. */
810 two_insn_adds_subs_operand (op, mode)
812 enum machine_mode mode;
814 if (GET_CODE (op) == CONST_INT)
816 HOST_WIDE_INT value = INTVAL (op);
818 /* Force VALUE to be positive so that we do not have to consider
819 the negative case. */
822 if (TARGET_H8300H || TARGET_H8300S)
824 /* A constant addition/subtraction takes 2 states in QImode,
825 4 states in HImode, and 6 states in SImode. Thus, the
826 only case we can win is when SImode is used, in which
827 case, two adds/subs are used, taking 4 states. */
837 /* We do not profit directly by splitting addition or
838 subtraction of 3 and 4. However, since these are
839 implemented as a sequence of adds or subs, they do not
840 clobber (cc0) unlike a sequence of add.b and add.x. */
851 /* Split an add of a small constant into two adds/subs insns.
853 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
854 instead of adds/subs. */
857 split_adds_subs (mode, operands)
858 enum machine_mode mode;
861 HOST_WIDE_INT val = INTVAL (operands[1]);
862 rtx reg = operands[0];
863 HOST_WIDE_INT sign = 1;
864 HOST_WIDE_INT amount;
865 rtx (*gen_add) (rtx, rtx, rtx);
867 /* Force VAL to be positive so that we do not have to consider the
878 gen_add = gen_addhi3;
882 gen_add = gen_addsi3;
889 /* Try different amounts in descending order. */
890 for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
894 for (; val >= amount; val -= amount)
895 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
901 /* Return true if OP is a valid call operand, and OP represents
902 an operand for a small call (4 bytes instead of 6 bytes). */
905 small_call_insn_operand (op, mode)
907 enum machine_mode mode ATTRIBUTE_UNUSED;
909 if (GET_CODE (op) == MEM)
911 rtx inside = XEXP (op, 0);
913 /* Register indirect is a small call. */
914 if (register_operand (inside, Pmode))
917 /* A call through the function vector is a small call too. */
918 if (GET_CODE (inside) == SYMBOL_REF
919 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
922 /* Otherwise it's a large call. */
926 /* Return true if OP is a valid jump operand. */
929 jump_address_operand (op, mode)
931 enum machine_mode mode;
933 if (GET_CODE (op) == REG)
934 return mode == Pmode;
936 if (GET_CODE (op) == MEM)
938 rtx inside = XEXP (op, 0);
939 if (register_operand (inside, Pmode))
941 if (CONSTANT_ADDRESS_P (inside))
947 /* Recognize valid operands for bit-field instructions. */
949 extern int rtx_equal_function_value_matters;
952 bit_operand (op, mode)
954 enum machine_mode mode;
956 /* We can accept any general operand, except that MEM operands must
957 be limited to those that use addresses valid for the 'U' constraint. */
958 if (!general_operand (op, mode))
961 /* Accept any mem during RTL generation. Otherwise, the code that does
962 insv and extzv will think that we can not handle memory. However,
963 to avoid reload problems, we only accept 'U' MEM operands after RTL
964 generation. This means that any named pattern which uses this predicate
965 must force its operands to match 'U' before emitting RTL. */
967 if (GET_CODE (op) == REG)
969 if (GET_CODE (op) == SUBREG)
971 return (GET_CODE (op) == MEM
972 && EXTRA_CONSTRAINT (op, 'U'));
976 bit_memory_operand (op, mode)
978 enum machine_mode mode ATTRIBUTE_UNUSED;
980 return (GET_CODE (op) == MEM
981 && EXTRA_CONSTRAINT (op, 'U'));
984 /* Handle machine specific pragmas for compatibility with existing
985 compilers for the H8/300.
987 pragma saveall generates prologue/epilogue code which saves and
988 restores all the registers on function entry.
990 pragma interrupt saves and restores all registers, and exits with
991 an rte instruction rather than an rts. A pointer to a function
992 with this attribute may be safely used in an interrupt vector. */
995 h8300_pr_interrupt (pfile)
996 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
998 pragma_interrupt = 1;
1002 h8300_pr_saveall (pfile)
1003 struct cpp_reader *pfile ATTRIBUTE_UNUSED;
1008 /* If the next function argument with MODE and TYPE is to be passed in
1009 a register, return a reg RTX for the hard register in which to pass
1010 the argument. CUM represents the state after the last argument.
1011 If the argument is to be pushed, NULL_RTX is returned. */
1014 function_arg (cum, mode, type, named)
1015 CUMULATIVE_ARGS *cum;
1016 enum machine_mode mode;
1020 static const char *const hand_list[] = {
1039 rtx result = NULL_RTX;
1043 /* Never pass unnamed arguments in registers. */
1047 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1048 if (TARGET_QUICKCALL)
1051 /* If calling hand written assembler, use 4 regs of args. */
1054 const char * const *p;
1056 fname = XSTR (cum->libcall, 0);
1058 /* See if this libcall is one of the hand coded ones. */
1059 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++)
1070 if (mode == BLKmode)
1071 size = int_size_in_bytes (type);
1073 size = GET_MODE_SIZE (mode);
1075 if (size + cum->nbytes <= regpass * UNITS_PER_WORD
1076 && cum->nbytes / UNITS_PER_WORD <= 3)
1077 result = gen_rtx_REG (mode, cum->nbytes / UNITS_PER_WORD);
1083 /* Return the cost of the rtx R with code CODE. */
1086 const_costs (r, c, outer_code)
1089 enum rtx_code outer_code;
1095 HOST_WIDE_INT n = INTVAL (r);
1097 if (-4 <= n || n <= 4)
1107 return 0 + (outer_code == SET);
1110 if (TARGET_H8300H || TARGET_H8300S)
1111 return 0 + (outer_code == SET);
1138 if (GET_MODE (x) == QImode)
1141 if (GET_MODE (x) != HImode
1142 && GET_MODE (x) != SImode)
1147 operands[2] = XEXP (x, 1);
1149 return compute_logical_op_length (GET_MODE (x), operands) / 2;
1153 h8300_shift_costs (x)
1158 if (GET_MODE (x) != QImode
1159 && GET_MODE (x) != HImode
1160 && GET_MODE (x) != SImode)
1165 operands[2] = XEXP (x, 1);
1167 return compute_a_shift_length (NULL, operands) / 2;
1171 h8300_rtx_costs (x, code, outer_code, total)
1173 int code, outer_code;
1179 *total = COSTS_N_INSNS (h8300_and_costs (x));
1182 /* We say that MOD and DIV are so expensive because otherwise we'll
1183 generate some really horrible code for division of a power of two. */
1196 *total = COSTS_N_INSNS (h8300_shift_costs (x));
1201 if (GET_MODE (x) == HImode)
1208 *total = const_costs (x, code, outer_code);
1213 /* Documentation for the machine specific operand escapes:
1215 'E' like s but negative.
1216 'F' like t but negative.
1217 'G' constant just the negative
1218 'R' print operand as a byte:8 address if appropriate, else fall back to
1220 'S' print operand as a long word
1221 'T' print operand as a word
1222 'V' find the set bit, and print its number.
1223 'W' find the clear bit, and print its number.
1224 'X' print operand as a byte
1225 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1226 If this operand isn't a register, fall back to 'R' handling.
1228 'b' print the bit opcode
1229 'c' print the opcode corresponding to rtl
1230 'e' first word of 32 bit value - if reg, then least reg. if mem
1231 then least. if const then most sig word
1232 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1233 then +2. if const then least sig word
1234 'j' print operand as condition code.
1235 'k' print operand as reverse condition code.
1236 's' print as low byte of 16 bit value
1237 't' print as high byte of 16 bit value
1238 'w' print as low byte of 32 bit value
1239 'x' print as 2nd byte of 32 bit value
1240 'y' print as 3rd byte of 32 bit value
1241 'z' print as msb of 32 bit value
1244 /* Return assembly language string which identifies a comparison type. */
1277 /* Print operand X using operand code CODE to assembly language output file
1281 print_operand (file, x, code)
1286 /* This is used for communication between codes V,W,Z and Y. */
1292 switch (GET_CODE (x))
1295 fprintf (file, "%sl", names_big[REGNO (x)]);
1298 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff);
1305 switch (GET_CODE (x))
1308 fprintf (file, "%sh", names_big[REGNO (x)]);
1311 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8);
1318 if (GET_CODE (x) != CONST_INT)
1320 fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
1323 if (GET_CODE (x) == REG)
1324 fprintf (file, "%s", names_extended[REGNO (x)]);
1329 if (GET_CODE (x) == REG)
1330 fprintf (file, "%s", names_big[REGNO (x)]);
1335 bitint = exact_log2 (INTVAL (x) & 0xff);
1338 fprintf (file, "#%d", bitint);
1341 bitint = exact_log2 ((~INTVAL (x)) & 0xff);
1344 fprintf (file, "#%d", bitint);
1348 if (GET_CODE (x) == REG)
1349 fprintf (file, "%s", byte_reg (x, 0));
1356 if (GET_CODE (x) == REG)
1357 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
1359 print_operand (file, x, 'R');
1363 bitint = INTVAL (x);
1364 fprintf (file, "#%d", bitint & 7);
1367 switch (GET_CODE (x))
1370 fprintf (file, "bor");
1373 fprintf (file, "bxor");
1376 fprintf (file, "band");
1383 switch (GET_CODE (x))
1386 fprintf (file, "or");
1389 fprintf (file, "xor");
1396 switch (GET_CODE (x))
1400 fprintf (file, "%s", names_big[REGNO (x)]);
1402 fprintf (file, "%s", names_upper_extended[REGNO (x)]);
1405 print_operand (file, x, 0);
1408 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff));
1414 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1415 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1416 fprintf (file, "#%ld", ((val >> 16) & 0xffff));
1425 switch (GET_CODE (x))
1429 fprintf (file, "%s", names_big[REGNO (x) + 1]);
1431 fprintf (file, "%s", names_big[REGNO (x)]);
1434 x = adjust_address (x, HImode, 2);
1435 print_operand (file, x, 0);
1438 fprintf (file, "#%ld", INTVAL (x) & 0xffff);
1444 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1445 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1446 fprintf (file, "#%ld", (val & 0xffff));
1454 fputs (cond_string (GET_CODE (x)), file);
1457 fputs (cond_string (reverse_condition (GET_CODE (x))), file);
1460 if (GET_CODE (x) == CONST_INT)
1461 fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
1463 fprintf (file, "%s", byte_reg (x, 0));
1466 if (GET_CODE (x) == CONST_INT)
1467 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1469 fprintf (file, "%s", byte_reg (x, 1));
1472 if (GET_CODE (x) != CONST_INT)
1474 fprintf (file, "%ld", INTVAL (x));
1477 if (GET_CODE (x) == CONST_INT)
1478 fprintf (file, "#%ld", INTVAL (x) & 0xff);
1480 fprintf (file, "%s",
1481 byte_reg (x, TARGET_H8300 ? 2 : 0));
1484 if (GET_CODE (x) == CONST_INT)
1485 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
1487 fprintf (file, "%s",
1488 byte_reg (x, TARGET_H8300 ? 3 : 1));
1491 if (GET_CODE (x) == CONST_INT)
1492 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
1494 fprintf (file, "%s", byte_reg (x, 0));
1497 if (GET_CODE (x) == CONST_INT)
1498 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
1500 fprintf (file, "%s", byte_reg (x, 1));
1505 switch (GET_CODE (x))
1508 switch (GET_MODE (x))
1511 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1512 fprintf (file, "%s", byte_reg (x, 0));
1513 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1514 fprintf (file, "%s", names_big[REGNO (x)]);
1518 fprintf (file, "%s", names_big[REGNO (x)]);
1522 fprintf (file, "%s", names_extended[REGNO (x)]);
1531 rtx addr = XEXP (x, 0);
1533 fprintf (file, "@");
1534 output_address (addr);
1536 /* We fall back from smaller addressing to larger
1537 addressing in various ways depending on CODE. */
1541 /* Used for mov.b and bit operations. */
1542 if (h8300_eightbit_constant_address_p (addr))
1544 fprintf (file, ":8");
1548 /* Fall through. We should not get here if we are
1549 processing bit operations on H8/300 or H8/300H
1550 because 'U' constraint does not allow bit
1551 operations on the tiny area on these machines. */
1555 /* Used for mov.w and mov.l. */
1556 if (h8300_tiny_constant_address_p (addr))
1557 fprintf (file, ":16");
1569 fprintf (file, "#");
1570 print_operand_address (file, x);
1576 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
1577 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
1578 fprintf (file, "#%ld", val);
1587 /* Output assembly language output for the address ADDR to FILE. */
1590 print_operand_address (file, addr)
1594 switch (GET_CODE (addr))
1597 fprintf (file, "%s", h8_reg_names[REGNO (addr)]);
1601 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]);
1605 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]);
1609 fprintf (file, "(");
1610 if (GET_CODE (XEXP (addr, 0)) == REG)
1613 print_operand_address (file, XEXP (addr, 1));
1614 fprintf (file, ",");
1615 print_operand_address (file, XEXP (addr, 0));
1620 print_operand_address (file, XEXP (addr, 0));
1621 fprintf (file, "+");
1622 print_operand_address (file, XEXP (addr, 1));
1624 fprintf (file, ")");
1629 /* Since the H8/300 only has 16 bit pointers, negative values are also
1630 those >= 32768. This happens for example with pointer minus a
1631 constant. We don't want to turn (char *p - 2) into
1632 (char *p + 65534) because loop unrolling can build upon this
1633 (IE: char *p + 131068). */
1634 int n = INTVAL (addr);
1636 n = (int) (short) n;
1637 fprintf (file, "%d", n);
1642 output_addr_const (file, addr);
1647 /* Output all insn addresses and their sizes into the assembly language
1648 output file. This is helpful for debugging whether the length attributes
1649 in the md file are correct. This is not meant to be a user selectable
1653 final_prescan_insn (insn, operand, num_operands)
1654 rtx insn, *operand ATTRIBUTE_UNUSED;
1655 int num_operands ATTRIBUTE_UNUSED;
1657 /* This holds the last insn address. */
1658 static int last_insn_address = 0;
1660 const int uid = INSN_UID (insn);
1662 if (TARGET_RTL_DUMP)
1664 fprintf (asm_out_file, "\n****************");
1665 print_rtl (asm_out_file, PATTERN (insn));
1666 fprintf (asm_out_file, "\n");
1669 if (TARGET_ADDRESSES)
1671 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid),
1672 INSN_ADDRESSES (uid) - last_insn_address);
1673 last_insn_address = INSN_ADDRESSES (uid);
1677 /* Prepare for an SI sized move. */
1683 rtx src = operands[1];
1684 rtx dst = operands[0];
1685 if (!reload_in_progress && !reload_completed)
1687 if (!register_operand (dst, GET_MODE (dst)))
1689 rtx tmp = gen_reg_rtx (GET_MODE (dst));
1690 emit_move_insn (tmp, src);
1697 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1698 Define the offset between two registers, one to be eliminated, and
1699 the other its replacement, at the start of a routine. */
1702 h8300_initial_elimination_offset (from, to)
1706 /* The number of bytes that the return address takes on the stack. */
1707 int pc_size = POINTER_SIZE / BITS_PER_UNIT;
1709 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1710 offset = pc_size + frame_pointer_needed * UNITS_PER_WORD;
1711 else if (from == RETURN_ADDRESS_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1712 offset = frame_pointer_needed * UNITS_PER_WORD;
1717 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1718 if (WORD_REG_USED (regno))
1719 offset += UNITS_PER_WORD;
1721 /* See the comments for get_frame_size. We need to round it up to
1724 offset += round_frame_size (get_frame_size ());
1726 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1727 /* Skip saved PC. */
1735 h8300_return_addr_rtx (count, frame)
1742 ret = gen_rtx_MEM (Pmode,
1743 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM));
1744 else if (flag_omit_frame_pointer)
1747 ret = gen_rtx_MEM (Pmode,
1748 memory_address (Pmode,
1749 plus_constant (frame, UNITS_PER_WORD)));
1750 set_mem_alias_set (ret, get_frame_alias_set ());
1754 /* Update the condition code from the insn. */
1757 notice_update_cc (body, insn)
1763 switch (get_attr_cc (insn))
1766 /* Insn does not affect CC at all. */
1770 /* Insn does not change CC, but the 0'th operand has been changed. */
1771 if (cc_status.value1 != 0
1772 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1773 cc_status.value1 = 0;
1774 if (cc_status.value2 != 0
1775 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value2))
1776 cc_status.value2 = 0;
1780 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1781 The V flag is unusable. The C flag may or may not be known but
1782 that's ok because alter_cond will change tests to use EQ/NE. */
1784 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
1785 set = single_set (insn);
1786 cc_status.value1 = SET_SRC (set);
1787 if (SET_DEST (set) != cc0_rtx)
1788 cc_status.value2 = SET_DEST (set);
1792 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1793 The C flag may or may not be known but that's ok because
1794 alter_cond will change tests to use EQ/NE. */
1796 cc_status.flags |= CC_NO_CARRY;
1797 set = single_set (insn);
1798 cc_status.value1 = SET_SRC (set);
1799 if (SET_DEST (set) != cc0_rtx)
1801 /* If the destination is STRICT_LOW_PART, strip off
1803 if (GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
1804 cc_status.value2 = XEXP (SET_DEST (set), 0);
1806 cc_status.value2 = SET_DEST (set);
1811 /* The insn is a compare instruction. */
1813 cc_status.value1 = SET_SRC (body);
1817 /* Insn doesn't leave CC in a usable state. */
1823 /* Return nonzero if X is a stack pointer. */
1826 stack_pointer_operand (x, mode)
1828 enum machine_mode mode ATTRIBUTE_UNUSED;
1830 return x == stack_pointer_rtx;
1833 /* Return nonzero if X is a constant whose absolute value is greater
1837 const_int_gt_2_operand (x, mode)
1839 enum machine_mode mode ATTRIBUTE_UNUSED;
1841 return (GET_CODE (x) == CONST_INT
1842 && abs (INTVAL (x)) > 2);
1845 /* Return nonzero if X is a constant whose absolute value is no
1849 const_int_ge_8_operand (x, mode)
1851 enum machine_mode mode ATTRIBUTE_UNUSED;
1853 return (GET_CODE (x) == CONST_INT
1854 && abs (INTVAL (x)) >= 8);
1857 /* Return nonzero if X is a constant expressible in QImode. */
1860 const_int_qi_operand (x, mode)
1862 enum machine_mode mode ATTRIBUTE_UNUSED;
1864 return (GET_CODE (x) == CONST_INT
1865 && (INTVAL (x) & 0xff) == INTVAL (x));
1868 /* Return nonzero if X is a constant expressible in HImode. */
1871 const_int_hi_operand (x, mode)
1873 enum machine_mode mode ATTRIBUTE_UNUSED;
1875 return (GET_CODE (x) == CONST_INT
1876 && (INTVAL (x) & 0xffff) == INTVAL (x));
1879 /* Return nonzero if X is a constant suitable for inc/dec. */
1882 incdec_operand (x, mode)
1884 enum machine_mode mode ATTRIBUTE_UNUSED;
1886 return (GET_CODE (x) == CONST_INT
1887 && (CONST_OK_FOR_M (INTVAL (x))
1888 || CONST_OK_FOR_O (INTVAL (x))));
1891 /* Return nonzero if X is either EQ or NE. */
1894 eqne_operator (x, mode)
1896 enum machine_mode mode ATTRIBUTE_UNUSED;
1898 enum rtx_code code = GET_CODE (x);
1900 return (code == EQ || code == NE);
1903 /* Return nonzero if X is GT, LE, GTU, or LEU. */
1906 gtle_operator (x, mode)
1908 enum machine_mode mode ATTRIBUTE_UNUSED;
1910 enum rtx_code code = GET_CODE (x);
1912 return (code == GT || code == LE || code == GTU || code == LEU);
1915 /* Return nonzero if X is either GTU or LEU. */
1918 gtuleu_operator (x, mode)
1920 enum machine_mode mode ATTRIBUTE_UNUSED;
1922 enum rtx_code code = GET_CODE (x);
1924 return (code == GTU || code == LEU);
1927 /* Return nonzero if X is either IOR or XOR. */
1930 iorxor_operator (x, mode)
1932 enum machine_mode mode ATTRIBUTE_UNUSED;
1934 enum rtx_code code = GET_CODE (x);
1936 return (code == IOR || code == XOR);
1939 /* Recognize valid operators for bit instructions. */
1942 bit_operator (x, mode)
1944 enum machine_mode mode ATTRIBUTE_UNUSED;
1946 enum rtx_code code = GET_CODE (x);
1954 output_plussi (operands)
1957 enum machine_mode mode = GET_MODE (operands[0]);
1964 if (GET_CODE (operands[2]) == REG)
1965 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1967 if (GET_CODE (operands[2]) == CONST_INT)
1969 HOST_WIDE_INT n = INTVAL (operands[2]);
1971 if ((n & 0xffffff) == 0)
1972 return "add\t%z2,%z0";
1973 if ((n & 0xffff) == 0)
1974 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
1975 if ((n & 0xff) == 0)
1976 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1979 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
1983 if (GET_CODE (operands[2]) == REG)
1984 return "add.l\t%S2,%S0";
1986 if (GET_CODE (operands[2]) == CONST_INT)
1988 HOST_WIDE_INT intval = INTVAL (operands[2]);
1990 /* See if we can finish with 2 bytes. */
1992 switch ((unsigned int) intval & 0xffffffff)
1997 return "adds\t%2,%S0";
2002 return "subs\t%G2,%S0";
2006 operands[2] = GEN_INT (intval >> 16);
2007 return "inc.w\t%2,%e0";
2011 operands[2] = GEN_INT (intval >> 16);
2012 return "dec.w\t%G2,%e0";
2015 /* See if we can finish with 4 bytes. */
2016 if ((intval & 0xffff) == 0)
2018 operands[2] = GEN_INT (intval >> 16);
2019 return "add.w\t%2,%e0";
2023 return "add.l\t%S2,%S0";
2028 compute_plussi_length (operands)
2031 enum machine_mode mode = GET_MODE (operands[0]);
2038 if (GET_CODE (operands[2]) == REG)
2041 if (GET_CODE (operands[2]) == CONST_INT)
2043 HOST_WIDE_INT n = INTVAL (operands[2]);
2045 if ((n & 0xffffff) == 0)
2047 if ((n & 0xffff) == 0)
2049 if ((n & 0xff) == 0)
2057 if (GET_CODE (operands[2]) == REG)
2060 if (GET_CODE (operands[2]) == CONST_INT)
2062 HOST_WIDE_INT intval = INTVAL (operands[2]);
2064 /* See if we can finish with 2 bytes. */
2066 switch ((unsigned int) intval & 0xffffffff)
2087 /* See if we can finish with 4 bytes. */
2088 if ((intval & 0xffff) == 0)
2097 compute_plussi_cc (operands)
2100 enum machine_mode mode = GET_MODE (operands[0]);
2111 if (GET_CODE (operands[2]) == REG)
2114 if (GET_CODE (operands[2]) == CONST_INT)
2116 HOST_WIDE_INT intval = INTVAL (operands[2]);
2118 /* See if we can finish with 2 bytes. */
2120 switch ((unsigned int) intval & 0xffffffff)
2125 return CC_NONE_0HIT;
2130 return CC_NONE_0HIT;
2141 /* See if we can finish with 4 bytes. */
2142 if ((intval & 0xffff) == 0)
2151 output_logical_op (mode, operands)
2152 enum machine_mode mode;
2155 /* Figure out the logical op that we need to perform. */
2156 enum rtx_code code = GET_CODE (operands[3]);
2157 /* Pretend that every byte is affected if both operands are registers. */
2158 const unsigned HOST_WIDE_INT intval =
2159 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2160 ? INTVAL (operands[2]) : 0x55555555);
2161 /* The determinant of the algorithm. If we perform an AND, 0
2162 affects a bit. Otherwise, 1 affects a bit. */
2163 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2164 /* Break up DET into pieces. */
2165 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2166 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2167 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2168 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2169 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2170 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2171 int lower_half_easy_p = 0;
2172 int upper_half_easy_p = 0;
2173 /* The name of an insn. */
2195 /* First, see if we can finish with one insn. */
2196 if ((TARGET_H8300H || TARGET_H8300S)
2200 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
2201 output_asm_insn (insn_buf, operands);
2205 /* Take care of the lower byte. */
2208 sprintf (insn_buf, "%s\t%%s2,%%s0", opname);
2209 output_asm_insn (insn_buf, operands);
2211 /* Take care of the upper byte. */
2214 sprintf (insn_buf, "%s\t%%t2,%%t0", opname);
2215 output_asm_insn (insn_buf, operands);
2220 if (TARGET_H8300H || TARGET_H8300S)
2222 /* Determine if the lower half can be taken care of in no more
2224 lower_half_easy_p = (b0 == 0
2226 || (code != IOR && w0 == 0xffff));
2228 /* Determine if the upper half can be taken care of in no more
2230 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2231 || (code == AND && w1 == 0xff00));
2234 /* Check if doing everything with one insn is no worse than
2235 using multiple insns. */
2236 if ((TARGET_H8300H || TARGET_H8300S)
2237 && w0 != 0 && w1 != 0
2238 && !(lower_half_easy_p && upper_half_easy_p)
2239 && !(code == IOR && w1 == 0xffff
2240 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2242 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname);
2243 output_asm_insn (insn_buf, operands);
2247 /* Take care of the lower and upper words individually. For
2248 each word, we try different methods in the order of
2250 1) the special insn (in case of AND or XOR),
2251 2) the word-wise insn, and
2252 3) The byte-wise insn. */
2254 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2255 output_asm_insn ((code == AND)
2256 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
2258 else if ((TARGET_H8300H || TARGET_H8300S)
2262 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
2263 output_asm_insn (insn_buf, operands);
2269 sprintf (insn_buf, "%s\t%%w2,%%w0", opname);
2270 output_asm_insn (insn_buf, operands);
2274 sprintf (insn_buf, "%s\t%%x2,%%x0", opname);
2275 output_asm_insn (insn_buf, operands);
2280 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2281 output_asm_insn ((code == AND)
2282 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
2284 else if ((TARGET_H8300H || TARGET_H8300S)
2287 && (w0 & 0x8000) != 0)
2289 output_asm_insn ("exts.l\t%S0", operands);
2291 else if ((TARGET_H8300H || TARGET_H8300S)
2295 output_asm_insn ("extu.w\t%e0", operands);
2297 else if (TARGET_H8300H || TARGET_H8300S)
2301 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname);
2302 output_asm_insn (insn_buf, operands);
2309 sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
2310 output_asm_insn (insn_buf, operands);
2314 sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
2315 output_asm_insn (insn_buf, operands);
2327 compute_logical_op_length (mode, operands)
2328 enum machine_mode mode;
2331 /* Figure out the logical op that we need to perform. */
2332 enum rtx_code code = GET_CODE (operands[3]);
2333 /* Pretend that every byte is affected if both operands are registers. */
2334 const unsigned HOST_WIDE_INT intval =
2335 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2336 ? INTVAL (operands[2]) : 0x55555555);
2337 /* The determinant of the algorithm. If we perform an AND, 0
2338 affects a bit. Otherwise, 1 affects a bit. */
2339 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2340 /* Break up DET into pieces. */
2341 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2342 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2343 const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
2344 const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
2345 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2346 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2347 int lower_half_easy_p = 0;
2348 int upper_half_easy_p = 0;
2350 unsigned int length = 0;
2355 /* First, see if we can finish with one insn. */
2356 if ((TARGET_H8300H || TARGET_H8300S)
2360 if (REG_P (operands[2]))
2367 /* Take care of the lower byte. */
2371 /* Take care of the upper byte. */
2377 if (TARGET_H8300H || TARGET_H8300S)
2379 /* Determine if the lower half can be taken care of in no more
2381 lower_half_easy_p = (b0 == 0
2383 || (code != IOR && w0 == 0xffff));
2385 /* Determine if the upper half can be taken care of in no more
2387 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2388 || (code == AND && w1 == 0xff00));
2391 /* Check if doing everything with one insn is no worse than
2392 using multiple insns. */
2393 if ((TARGET_H8300H || TARGET_H8300S)
2394 && w0 != 0 && w1 != 0
2395 && !(lower_half_easy_p && upper_half_easy_p)
2396 && !(code == IOR && w1 == 0xffff
2397 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2399 if (REG_P (operands[2]))
2406 /* Take care of the lower and upper words individually. For
2407 each word, we try different methods in the order of
2409 1) the special insn (in case of AND or XOR),
2410 2) the word-wise insn, and
2411 3) The byte-wise insn. */
2413 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2417 else if ((TARGET_H8300H || TARGET_H8300S)
2433 && (TARGET_H8300 ? (code == AND) : (code != IOR)))
2437 else if ((TARGET_H8300H || TARGET_H8300S)
2440 && (w0 & 0x8000) != 0)
2444 else if ((TARGET_H8300H || TARGET_H8300S)
2450 else if (TARGET_H8300H || TARGET_H8300S)
2472 compute_logical_op_cc (mode, operands)
2473 enum machine_mode mode;
2476 /* Figure out the logical op that we need to perform. */
2477 enum rtx_code code = GET_CODE (operands[3]);
2478 /* Pretend that every byte is affected if both operands are registers. */
2479 const unsigned HOST_WIDE_INT intval =
2480 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
2481 ? INTVAL (operands[2]) : 0x55555555);
2482 /* The determinant of the algorithm. If we perform an AND, 0
2483 affects a bit. Otherwise, 1 affects a bit. */
2484 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval;
2485 /* Break up DET into pieces. */
2486 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff;
2487 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff;
2488 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff;
2489 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
2490 int lower_half_easy_p = 0;
2491 int upper_half_easy_p = 0;
2492 /* Condition code. */
2493 enum attr_cc cc = CC_CLOBBER;
2498 /* First, see if we can finish with one insn. */
2499 if ((TARGET_H8300H || TARGET_H8300S)
2507 if (TARGET_H8300H || TARGET_H8300S)
2509 /* Determine if the lower half can be taken care of in no more
2511 lower_half_easy_p = (b0 == 0
2513 || (code != IOR && w0 == 0xffff));
2515 /* Determine if the upper half can be taken care of in no more
2517 upper_half_easy_p = ((code != IOR && w1 == 0xffff)
2518 || (code == AND && w1 == 0xff00));
2521 /* Check if doing everything with one insn is no worse than
2522 using multiple insns. */
2523 if ((TARGET_H8300H || TARGET_H8300S)
2524 && w0 != 0 && w1 != 0
2525 && !(lower_half_easy_p && upper_half_easy_p)
2526 && !(code == IOR && w1 == 0xffff
2527 && (w0 & 0x8000) != 0 && lower_half_easy_p))
2533 if ((TARGET_H8300H || TARGET_H8300S)
2536 && (w0 & 0x8000) != 0)
2550 We devote a fair bit of code to getting efficient shifts since we
2551 can only shift one bit at a time on the H8/300 and H8/300H and only
2552 one or two bits at a time on the H8S.
2554 All shift code falls into one of the following ways of
2557 o SHIFT_INLINE: Emit straight line code for the shift; this is used
2558 when a straight line shift is about the same size or smaller than
2561 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
2562 off the bits we don't need. This is used when only a few of the
2563 bits in the original value will survive in the shifted value.
2565 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
2566 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
2567 shifts can be added if the shift count is slightly more than 8 or
2568 16. This case also includes other oddballs that are not worth
2571 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
2573 For each shift count, we try to use code that has no trade-off
2574 between code size and speed whenever possible.
2576 If the trade-off is unavoidable, we try to be reasonable.
2577 Specifically, the fastest version is one instruction longer than
2578 the shortest version, we take the fastest version. We also provide
2579 the use a way to switch back to the shortest version with -Os.
2581 For the details of the shift algorithms for various shift counts,
2582 refer to shift_alg_[qhs]i. */
2585 nshift_operator (x, mode)
2587 enum machine_mode mode ATTRIBUTE_UNUSED;
2589 switch (GET_CODE (x))
2601 /* Emit code to do shifts. */
2604 expand_a_shift (mode, code, operands)
2605 enum machine_mode mode;
2609 emit_move_insn (operands[0], operands[1]);
2611 /* Need a loop to get all the bits we want - we generate the
2612 code at emit time, but need to allocate a scratch reg now. */
2614 emit_insn (gen_rtx_PARALLEL
2617 gen_rtx_SET (VOIDmode, operands[0],
2618 gen_rtx (code, mode, operands[0],
2620 gen_rtx_CLOBBER (VOIDmode,
2621 gen_rtx_SCRATCH (QImode)))));
2624 /* Symbols of the various modes which can be used as indices. */
2628 QIshift, HIshift, SIshift
2631 /* For single bit shift insns, record assembler and what bits of the
2632 condition code are valid afterwards (represented as various CC_FOO
2633 bits, 0 means CC isn't left in a usable state). */
2637 const char *const assembler;
2641 /* Assembler instruction shift table.
2643 These tables are used to look up the basic shifts.
2644 They are indexed by cpu, shift_type, and mode. */
2646 static const struct shift_insn shift_one[2][3][3] =
2652 { "shll\t%X0", CC_SET_ZNV },
2653 { "add.w\t%T0,%T0", CC_SET_ZN },
2654 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER }
2656 /* SHIFT_LSHIFTRT */
2658 { "shlr\t%X0", CC_SET_ZNV },
2659 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2660 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2662 /* SHIFT_ASHIFTRT */
2664 { "shar\t%X0", CC_SET_ZNV },
2665 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER },
2666 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER }
2673 { "shll.b\t%X0", CC_SET_ZNV },
2674 { "shll.w\t%T0", CC_SET_ZNV },
2675 { "shll.l\t%S0", CC_SET_ZNV }
2677 /* SHIFT_LSHIFTRT */
2679 { "shlr.b\t%X0", CC_SET_ZNV },
2680 { "shlr.w\t%T0", CC_SET_ZNV },
2681 { "shlr.l\t%S0", CC_SET_ZNV }
2683 /* SHIFT_ASHIFTRT */
2685 { "shar.b\t%X0", CC_SET_ZNV },
2686 { "shar.w\t%T0", CC_SET_ZNV },
2687 { "shar.l\t%S0", CC_SET_ZNV }
2692 static const struct shift_insn shift_two[3][3] =
2696 { "shll.b\t#2,%X0", CC_SET_ZNV },
2697 { "shll.w\t#2,%T0", CC_SET_ZNV },
2698 { "shll.l\t#2,%S0", CC_SET_ZNV }
2700 /* SHIFT_LSHIFTRT */
2702 { "shlr.b\t#2,%X0", CC_SET_ZNV },
2703 { "shlr.w\t#2,%T0", CC_SET_ZNV },
2704 { "shlr.l\t#2,%S0", CC_SET_ZNV }
2706 /* SHIFT_ASHIFTRT */
2708 { "shar.b\t#2,%X0", CC_SET_ZNV },
2709 { "shar.w\t#2,%T0", CC_SET_ZNV },
2710 { "shar.l\t#2,%S0", CC_SET_ZNV }
2714 /* Rotates are organized by which shift they'll be used in implementing.
2715 There's no need to record whether the cc is valid afterwards because
2716 it is the AND insn that will decide this. */
2718 static const char *const rotate_one[2][3][3] =
2725 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
2728 /* SHIFT_LSHIFTRT */
2731 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2734 /* SHIFT_ASHIFTRT */
2737 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
2749 /* SHIFT_LSHIFTRT */
2755 /* SHIFT_ASHIFTRT */
2764 static const char *const rotate_two[3][3] =
2772 /* SHIFT_LSHIFTRT */
2778 /* SHIFT_ASHIFTRT */
2787 /* Shift algorithm. */
2790 /* The number of bits to be shifted by shift1 and shift2. Valid
2791 when ALG is SHIFT_SPECIAL. */
2792 unsigned int remainder;
2794 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
2795 const char *special;
2797 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
2798 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2801 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
2802 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
2805 /* CC status for SHIFT_INLINE. */
2808 /* CC status for SHIFT_SPECIAL. */
2812 static void get_shift_alg PARAMS ((enum shift_type,
2813 enum shift_mode, unsigned int,
2814 struct shift_info *));
2816 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
2817 best algorithm for doing the shift. The assembler code is stored
2818 in the pointers in INFO. We achieve the maximum efficiency in most
2819 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
2820 SImode in particular have a lot of room to optimize.
2822 We first determine the strategy of the shift algorithm by a table
2823 lookup. If that tells us to use a hand crafted assembly code, we
2824 go into the big switch statement to find what that is. Otherwise,
2825 we resort to a generic way, such as inlining. In either case, the
2826 result is returned through INFO. */
2829 get_shift_alg (shift_type, shift_mode, count, info)
2830 enum shift_type shift_type;
2831 enum shift_mode shift_mode;
2833 struct shift_info *info;
2837 /* Find the target CPU. */
2840 else if (TARGET_H8300H)
2845 /* Find the shift algorithm. */
2846 info->alg = SHIFT_LOOP;
2850 if (count < GET_MODE_BITSIZE (QImode))
2851 info->alg = shift_alg_qi[cpu][shift_type][count];
2855 if (count < GET_MODE_BITSIZE (HImode))
2856 info->alg = shift_alg_hi[cpu][shift_type][count];
2860 if (count < GET_MODE_BITSIZE (SImode))
2861 info->alg = shift_alg_si[cpu][shift_type][count];
2868 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
2872 info->remainder = count;
2876 /* It is up to the caller to know that looping clobbers cc. */
2877 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2878 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2879 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2883 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode];
2884 info->shift2 = rotate_two[shift_type][shift_mode];
2885 info->cc_inline = CC_CLOBBER;
2889 /* REMAINDER is 0 for most cases, so initialize it to 0. */
2890 info->remainder = 0;
2891 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler;
2892 info->shift2 = shift_two[shift_type][shift_mode].assembler;
2893 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid;
2894 info->cc_special = CC_CLOBBER;
2898 /* Here we only deal with SHIFT_SPECIAL. */
2902 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
2903 through the entire value. */
2904 if (shift_type == SHIFT_ASHIFTRT && count == 7)
2906 info->special = "shll\t%X0\n\tsubx\t%X0,%X0";
2918 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
2920 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
2922 case SHIFT_LSHIFTRT:
2924 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
2926 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
2928 case SHIFT_ASHIFTRT:
2929 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
2933 else if ((8 <= count && count <= 13)
2934 || (TARGET_H8300S && count == 14))
2936 info->remainder = count - 8;
2941 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
2943 case SHIFT_LSHIFTRT:
2946 info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
2947 info->shift1 = "shlr.b\t%s0";
2948 info->cc_inline = CC_SET_ZNV;
2952 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
2953 info->cc_special = CC_SET_ZNV;
2956 case SHIFT_ASHIFTRT:
2959 info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
2960 info->shift1 = "shar.b\t%s0";
2964 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
2965 info->cc_special = CC_SET_ZNV;
2970 else if (count == 14)
2976 info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
2978 case SHIFT_LSHIFTRT:
2980 info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
2982 case SHIFT_ASHIFTRT:
2984 info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
2985 else if (TARGET_H8300H)
2987 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
2988 info->cc_special = CC_SET_ZNV;
2990 else /* TARGET_H8300S */
2995 else if (count == 15)
3000 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
3002 case SHIFT_LSHIFTRT:
3003 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
3005 case SHIFT_ASHIFTRT:
3006 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
3013 if (TARGET_H8300 && 8 <= count && count <= 9)
3015 info->remainder = count - 8;
3020 info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
3022 case SHIFT_LSHIFTRT:
3023 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
3024 info->shift1 = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
3026 case SHIFT_ASHIFTRT:
3027 info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
3031 else if (count == 8 && !TARGET_H8300)
3036 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
3038 case SHIFT_LSHIFTRT:
3039 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
3041 case SHIFT_ASHIFTRT:
3042 info->special = "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
3046 else if (count == 15 && TARGET_H8300)
3052 case SHIFT_LSHIFTRT:
3053 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\trotxl\t%y0,%y0";
3055 case SHIFT_ASHIFTRT:
3056 info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0,%w0\n\trotxl\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
3060 else if (count == 15 && !TARGET_H8300)
3065 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
3066 info->cc_special = CC_SET_ZNV;
3068 case SHIFT_LSHIFTRT:
3069 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
3070 info->cc_special = CC_SET_ZNV;
3072 case SHIFT_ASHIFTRT:
3076 else if ((TARGET_H8300 && 16 <= count && count <= 20)
3077 || (TARGET_H8300H && 16 <= count && count <= 19)
3078 || (TARGET_H8300S && 16 <= count && count <= 21))
3080 info->remainder = count - 16;
3085 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3087 info->shift1 = "add.w\t%e0,%e0";
3089 case SHIFT_LSHIFTRT:
3092 info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
3093 info->shift1 = "shlr\t%x0\n\trotxr\t%w0";
3097 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
3098 info->cc_special = CC_SET_ZNV;
3101 case SHIFT_ASHIFTRT:
3104 info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
3105 info->shift1 = "shar\t%x0\n\trotxr\t%w0";
3109 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
3110 info->cc_special = CC_SET_ZNV;
3115 else if (TARGET_H8300 && 24 <= count && count <= 28)
3117 info->remainder = count - 24;
3122 info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
3123 info->shift1 = "shll.b\t%z0";
3124 info->cc_inline = CC_SET_ZNV;
3126 case SHIFT_LSHIFTRT:
3127 info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
3128 info->shift1 = "shlr.b\t%w0";
3129 info->cc_inline = CC_SET_ZNV;
3131 case SHIFT_ASHIFTRT:
3132 info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
3133 info->shift1 = "shar.b\t%w0";
3134 info->cc_inline = CC_SET_ZNV;
3138 else if ((TARGET_H8300H && count == 24)
3139 || (TARGET_H8300S && 24 <= count && count <= 25))
3141 info->remainder = count - 24;
3146 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
3148 case SHIFT_LSHIFTRT:
3149 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
3150 info->cc_special = CC_SET_ZNV;
3152 case SHIFT_ASHIFTRT:
3153 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
3154 info->cc_special = CC_SET_ZNV;
3158 else if (!TARGET_H8300 && count == 28)
3164 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3166 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3168 case SHIFT_LSHIFTRT:
3171 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3172 info->cc_special = CC_SET_ZNV;
3175 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3177 case SHIFT_ASHIFTRT:
3181 else if (!TARGET_H8300 && count == 29)
3187 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3189 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3191 case SHIFT_LSHIFTRT:
3194 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3195 info->cc_special = CC_SET_ZNV;
3199 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3200 info->cc_special = CC_SET_ZNV;
3203 case SHIFT_ASHIFTRT:
3207 else if (!TARGET_H8300 && count == 30)
3213 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
3215 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
3217 case SHIFT_LSHIFTRT:
3219 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
3221 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
3223 case SHIFT_ASHIFTRT:
3227 else if (count == 31)
3234 info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
3236 case SHIFT_LSHIFTRT:
3237 info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
3239 case SHIFT_ASHIFTRT:
3240 info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
3249 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
3250 info->cc_special = CC_SET_ZNV;
3252 case SHIFT_LSHIFTRT:
3253 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
3254 info->cc_special = CC_SET_ZNV;
3256 case SHIFT_ASHIFTRT:
3257 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
3258 info->cc_special = CC_SET_ZNV;
3271 info->shift2 = NULL;
3274 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
3275 needed for some shift with COUNT and MODE. Return 0 otherwise. */
3278 h8300_shift_needs_scratch_p (count, mode)
3280 enum machine_mode mode;
3285 if (GET_MODE_BITSIZE (mode) <= count)
3288 /* Find out the target CPU. */
3291 else if (TARGET_H8300H)
3296 /* Find the shift algorithm. */
3300 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count];
3301 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count];
3302 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count];
3306 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count];
3307 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count];
3308 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count];
3312 a = shift_alg_si[cpu][SHIFT_ASHIFT][count];
3313 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count];
3314 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count];
3321 /* On H8/300H, count == 8 uses a scratch register. */
3322 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP
3323 || (TARGET_H8300H && mode == SImode && count == 8));
3326 /* Emit the assembler code for doing shifts. */
3329 output_a_shift (operands)
3332 static int loopend_lab;
3333 rtx shift = operands[3];
3334 enum machine_mode mode = GET_MODE (shift);
3335 enum rtx_code code = GET_CODE (shift);
3336 enum shift_type shift_type;
3337 enum shift_mode shift_mode;
3338 struct shift_info info;
3345 shift_mode = QIshift;
3348 shift_mode = HIshift;
3351 shift_mode = SIshift;
3360 shift_type = SHIFT_ASHIFTRT;
3363 shift_type = SHIFT_LSHIFTRT;
3366 shift_type = SHIFT_ASHIFT;
3372 if (GET_CODE (operands[2]) != CONST_INT)
3374 /* This case must be taken care of by one of the two splitters
3375 that convert a variable shift into a loop. */
3380 int n = INTVAL (operands[2]);
3382 /* If the count is negative, make it 0. */
3385 /* If the count is too big, truncate it.
3386 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3387 do the intuitive thing. */
3388 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3389 n = GET_MODE_BITSIZE (mode);
3391 get_shift_alg (shift_type, shift_mode, n, &info);
3396 output_asm_insn (info.special, operands);
3402 /* Emit two bit shifts first. */
3403 if (info.shift2 != NULL)
3405 for (; n > 1; n -= 2)
3406 output_asm_insn (info.shift2, operands);
3409 /* Now emit one bit shifts for any residual. */
3411 output_asm_insn (info.shift1, operands);
3416 int m = GET_MODE_BITSIZE (mode) - n;
3417 const int mask = (shift_type == SHIFT_ASHIFT
3418 ? ((1 << m) - 1) << n
3422 /* Not all possibilities of rotate are supported. They shouldn't
3423 be generated, but let's watch for 'em. */
3424 if (info.shift1 == 0)
3427 /* Emit two bit rotates first. */
3428 if (info.shift2 != NULL)
3430 for (; m > 1; m -= 2)
3431 output_asm_insn (info.shift2, operands);
3434 /* Now single bit rotates for any residual. */
3436 output_asm_insn (info.shift1, operands);
3438 /* Now mask off the high bits. */
3440 sprintf (insn_buf, "and\t#%d,%%X0", mask);
3441 else if (mode == HImode && (TARGET_H8300H || TARGET_H8300S))
3442 sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
3446 output_asm_insn (insn_buf, operands);
3451 /* A loop to shift by a "large" constant value.
3452 If we have shift-by-2 insns, use them. */
3453 if (info.shift2 != NULL)
3455 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2,
3456 names_big[REGNO (operands[4])]);
3457 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3458 output_asm_insn (info.shift2, operands);
3459 output_asm_insn ("add #0xff,%X4", operands);
3460 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3462 output_asm_insn (info.shift1, operands);
3466 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n,
3467 names_big[REGNO (operands[4])]);
3468 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab);
3469 output_asm_insn (info.shift1, operands);
3470 output_asm_insn ("add #0xff,%X4", operands);
3471 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab);
3482 h8300_asm_insn_count (template)
3483 const char *template;
3485 unsigned int count = 1;
3487 for (; *template; template++)
3488 if (*template == '\n')
3495 compute_a_shift_length (insn, operands)
3496 rtx insn ATTRIBUTE_UNUSED;
3499 rtx shift = operands[3];
3500 enum machine_mode mode = GET_MODE (shift);
3501 enum rtx_code code = GET_CODE (shift);
3502 enum shift_type shift_type;
3503 enum shift_mode shift_mode;
3504 struct shift_info info;
3505 unsigned int wlength = 0;
3510 shift_mode = QIshift;
3513 shift_mode = HIshift;
3516 shift_mode = SIshift;
3525 shift_type = SHIFT_ASHIFTRT;
3528 shift_type = SHIFT_LSHIFTRT;
3531 shift_type = SHIFT_ASHIFT;
3537 if (GET_CODE (operands[2]) != CONST_INT)
3539 /* Get the assembler code to do one shift. */
3540 get_shift_alg (shift_type, shift_mode, 1, &info);
3542 return (4 + h8300_asm_insn_count (info.shift1)) * 2;
3546 int n = INTVAL (operands[2]);
3548 /* If the count is negative, make it 0. */
3551 /* If the count is too big, truncate it.
3552 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3553 do the intuitive thing. */
3554 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3555 n = GET_MODE_BITSIZE (mode);
3557 get_shift_alg (shift_type, shift_mode, n, &info);
3562 wlength += h8300_asm_insn_count (info.special);
3564 /* Every assembly instruction used in SHIFT_SPECIAL case
3565 takes 2 bytes except xor.l, which takes 4 bytes, so if we
3566 see xor.l, we just pretend that xor.l counts as two insns
3567 so that the insn length will be computed correctly. */
3568 if (strstr (info.special, "xor.l") != NULL)
3576 if (info.shift2 != NULL)
3578 wlength += h8300_asm_insn_count (info.shift2) * (n / 2);
3582 wlength += h8300_asm_insn_count (info.shift1) * n;
3588 int m = GET_MODE_BITSIZE (mode) - n;
3590 /* Not all possibilities of rotate are supported. They shouldn't
3591 be generated, but let's watch for 'em. */
3592 if (info.shift1 == 0)
3595 if (info.shift2 != NULL)
3597 wlength += h8300_asm_insn_count (info.shift2) * (m / 2);
3601 wlength += h8300_asm_insn_count (info.shift1) * m;
3603 /* Now mask off the high bits. */
3624 /* A loop to shift by a "large" constant value.
3625 If we have shift-by-2 insns, use them. */
3626 if (info.shift2 != NULL)
3628 wlength += 3 + h8300_asm_insn_count (info.shift2);
3630 wlength += h8300_asm_insn_count (info.shift1);
3634 wlength += 3 + h8300_asm_insn_count (info.shift1);
3645 compute_a_shift_cc (insn, operands)
3646 rtx insn ATTRIBUTE_UNUSED;
3649 rtx shift = operands[3];
3650 enum machine_mode mode = GET_MODE (shift);
3651 enum rtx_code code = GET_CODE (shift);
3652 enum shift_type shift_type;
3653 enum shift_mode shift_mode;
3654 struct shift_info info;
3659 shift_mode = QIshift;
3662 shift_mode = HIshift;
3665 shift_mode = SIshift;
3674 shift_type = SHIFT_ASHIFTRT;
3677 shift_type = SHIFT_LSHIFTRT;
3680 shift_type = SHIFT_ASHIFT;
3686 if (GET_CODE (operands[2]) != CONST_INT)
3688 /* This case must be taken care of by one of the two splitters
3689 that convert a variable shift into a loop. */
3694 int n = INTVAL (operands[2]);
3696 /* If the count is negative, make it 0. */
3699 /* If the count is too big, truncate it.
3700 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
3701 do the intuitive thing. */
3702 else if ((unsigned int) n > GET_MODE_BITSIZE (mode))
3703 n = GET_MODE_BITSIZE (mode);
3705 get_shift_alg (shift_type, shift_mode, n, &info);
3710 if (info.remainder == 0)
3711 return info.cc_special;
3716 return info.cc_inline;
3719 /* This case always ends with an and instruction. */
3723 /* A loop to shift by a "large" constant value.
3724 If we have shift-by-2 insns, use them. */
3725 if (info.shift2 != NULL)
3728 return info.cc_inline;
3738 /* A rotation by a non-constant will cause a loop to be generated, in
3739 which a rotation by one bit is used. A rotation by a constant,
3740 including the one in the loop, will be taken care of by
3741 emit_a_rotate () at the insn emit time. */
3744 expand_a_rotate (code, operands)
3748 rtx dst = operands[0];
3749 rtx src = operands[1];
3750 rtx rotate_amount = operands[2];
3751 enum machine_mode mode = GET_MODE (dst);
3754 /* We rotate in place. */
3755 emit_move_insn (dst, src);
3757 if (GET_CODE (rotate_amount) != CONST_INT)
3759 rtx counter = gen_reg_rtx (QImode);
3760 rtx start_label = gen_label_rtx ();
3761 rtx end_label = gen_label_rtx ();
3763 /* If the rotate amount is less than or equal to 0,
3764 we go out of the loop. */
3765 emit_cmp_and_jump_insns (rotate_amount, GEN_INT (0), LE, NULL_RTX,
3766 QImode, 0, end_label);
3768 /* Initialize the loop counter. */
3769 emit_move_insn (counter, rotate_amount);
3771 emit_label (start_label);
3773 /* Rotate by one bit. */
3774 tmp = gen_rtx (code, mode, dst, GEN_INT (1));
3775 emit_insn (gen_rtx_SET (mode, dst, tmp));
3777 /* Decrement the counter by 1. */
3778 tmp = gen_rtx_PLUS (QImode, counter, GEN_INT (-1));
3779 emit_insn (gen_rtx_SET (VOIDmode, counter, tmp));
3781 /* If the loop counter is nonzero, we go back to the beginning
3783 emit_cmp_and_jump_insns (counter, GEN_INT (0), NE, NULL_RTX, QImode, 1,
3786 emit_label (end_label);
3790 /* Rotate by AMOUNT bits. */
3791 tmp = gen_rtx (code, mode, dst, rotate_amount);
3792 emit_insn (gen_rtx_SET (mode, dst, tmp));
3798 /* Emit rotate insns. */
3801 emit_a_rotate (code, operands)
3805 rtx dst = operands[0];
3806 rtx rotate_amount = operands[2];
3807 enum shift_mode rotate_mode;
3808 enum shift_type rotate_type;
3809 const char *insn_buf;
3812 enum machine_mode mode = GET_MODE (dst);
3814 if (GET_CODE (rotate_amount) != CONST_INT)
3820 rotate_mode = QIshift;
3823 rotate_mode = HIshift;
3826 rotate_mode = SIshift;
3835 rotate_type = SHIFT_ASHIFT;
3838 rotate_type = SHIFT_LSHIFTRT;
3844 amount = INTVAL (rotate_amount);
3846 /* Clean up AMOUNT. */
3849 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
3850 amount = GET_MODE_BITSIZE (mode);
3852 /* Determine the faster direction. After this phase, amount will be
3853 at most a half of GET_MODE_BITSIZE (mode). */
3854 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
3856 /* Flip the direction. */
3857 amount = GET_MODE_BITSIZE (mode) - amount;
3859 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3862 /* See if a byte swap (in HImode) or a word swap (in SImode) can
3863 boost up the rotation. */
3864 if ((mode == HImode && TARGET_H8300 && amount >= 5)
3865 || (mode == HImode && TARGET_H8300H && amount >= 6)
3866 || (mode == HImode && TARGET_H8300S && amount == 8)
3867 || (mode == SImode && TARGET_H8300H && amount >= 10)
3868 || (mode == SImode && TARGET_H8300S && amount >= 13))
3873 /* This code works on any family. */
3874 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
3875 output_asm_insn (insn_buf, operands);
3879 /* This code works on the H8/300H and H8S. */
3880 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
3881 output_asm_insn (insn_buf, operands);
3888 /* Adjust AMOUNT and flip the direction. */
3889 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
3891 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT;
3894 /* Emit rotate insns. */
3895 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2)
3898 insn_buf = rotate_two[rotate_type][rotate_mode];
3900 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode];
3902 for (; amount >= bits; amount -= bits)
3903 output_asm_insn (insn_buf, operands);
3909 /* Fix the operands of a gen_xxx so that it could become a bit
3913 fix_bit_operand (operands, what, type)
3918 /* The bit_operand predicate accepts any memory during RTL generation, but
3919 only 'U' memory afterwards, so if this is a MEM operand, we must force
3920 it to be valid for 'U' by reloading the address. */
3922 if ((what == 0 && single_zero_operand (operands[2], QImode))
3923 || (what == 1 && single_one_operand (operands[2], QImode)))
3925 /* OK to have a memory dest. */
3926 if (GET_CODE (operands[0]) == MEM
3927 && !EXTRA_CONSTRAINT (operands[0], 'U'))
3929 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
3930 copy_to_mode_reg (Pmode,
3931 XEXP (operands[0], 0)));
3932 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3936 if (GET_CODE (operands[1]) == MEM
3937 && !EXTRA_CONSTRAINT (operands[1], 'U'))
3939 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
3940 copy_to_mode_reg (Pmode,
3941 XEXP (operands[1], 0)));
3942 MEM_COPY_ATTRIBUTES (mem, operands[0]);
3948 /* Dest and src op must be register. */
3950 operands[1] = force_reg (QImode, operands[1]);
3952 rtx res = gen_reg_rtx (QImode);
3953 emit_insn (gen_rtx_SET (VOIDmode, res,
3954 gen_rtx (type, QImode, operands[1], operands[2])));
3955 emit_insn (gen_rtx_SET (VOIDmode, operands[0], res));
3960 /* Return nonzero if FUNC is an interrupt function as specified
3961 by the "interrupt" attribute. */
3964 h8300_interrupt_function_p (func)
3969 if (TREE_CODE (func) != FUNCTION_DECL)
3972 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
3973 return a != NULL_TREE;
3976 /* Return nonzero if FUNC is an OS_Task function as specified
3977 by the "OS_Task" attribute. */
3980 h8300_os_task_function_p (func)
3985 if (TREE_CODE (func) != FUNCTION_DECL)
3988 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func));
3989 return a != NULL_TREE;
3992 /* Return nonzero if FUNC is a monitor function as specified
3993 by the "monitor" attribute. */
3996 h8300_monitor_function_p (func)
4001 if (TREE_CODE (func) != FUNCTION_DECL)
4004 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func));
4005 return a != NULL_TREE;
4008 /* Return nonzero if FUNC is a function that should be called
4009 through the function vector. */
4012 h8300_funcvec_function_p (func)
4017 if (TREE_CODE (func) != FUNCTION_DECL)
4020 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func));
4021 return a != NULL_TREE;
4024 /* Return nonzero if DECL is a variable that's in the eight bit
4028 h8300_eightbit_data_p (decl)
4033 if (TREE_CODE (decl) != VAR_DECL)
4036 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl));
4037 return a != NULL_TREE;
4040 /* Return nonzero if DECL is a variable that's in the tiny
4044 h8300_tiny_data_p (decl)
4049 if (TREE_CODE (decl) != VAR_DECL)
4052 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl));
4053 return a != NULL_TREE;
4056 /* Generate an 'interrupt_handler' attribute for decls. */
4059 h8300_insert_attributes (node, attributes)
4063 if (!pragma_interrupt
4064 || TREE_CODE (node) != FUNCTION_DECL)
4067 pragma_interrupt = 0;
4069 /* Add an 'interrupt_handler' attribute. */
4070 *attributes = tree_cons (get_identifier ("interrupt_handler"),
4074 /* Supported attributes:
4076 interrupt_handler: output a prologue and epilogue suitable for an
4079 function_vector: This function should be called through the
4082 eightbit_data: This variable lives in the 8-bit data area and can
4083 be referenced with 8-bit absolute memory addresses.
4085 tiny_data: This variable lives in the tiny data area and can be
4086 referenced with 16-bit absolute memory references. */
4088 const struct attribute_spec h8300_attribute_table[] =
4090 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
4091 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4092 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4093 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4094 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute },
4095 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute },
4096 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute },
4097 { NULL, 0, 0, false, false, false, NULL }
4101 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
4102 struct attribute_spec.handler. */
4104 h8300_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
4107 tree args ATTRIBUTE_UNUSED;
4108 int flags ATTRIBUTE_UNUSED;
4111 if (TREE_CODE (*node) != FUNCTION_DECL)
4113 warning ("`%s' attribute only applies to functions",
4114 IDENTIFIER_POINTER (name));
4115 *no_add_attrs = true;
4121 /* Handle an "eightbit_data" attribute; arguments as in
4122 struct attribute_spec.handler. */
4124 h8300_handle_eightbit_data_attribute (node, name, args, flags, no_add_attrs)
4127 tree args ATTRIBUTE_UNUSED;
4128 int flags ATTRIBUTE_UNUSED;
4133 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4135 DECL_SECTION_NAME (decl) = build_string (7, ".eight");
4139 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4140 *no_add_attrs = true;
4146 /* Handle an "tiny_data" attribute; arguments as in
4147 struct attribute_spec.handler. */
4149 h8300_handle_tiny_data_attribute (node, name, args, flags, no_add_attrs)
4152 tree args ATTRIBUTE_UNUSED;
4153 int flags ATTRIBUTE_UNUSED;
4158 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
4160 DECL_SECTION_NAME (decl) = build_string (6, ".tiny");
4164 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
4165 *no_add_attrs = true;
4171 /* Mark function vectors, and various small data objects. */
4174 h8300_encode_section_info (decl, rtl, first)
4179 int extra_flags = 0;
4181 default_encode_section_info (decl, rtl, first);
4183 if (TREE_CODE (decl) == FUNCTION_DECL
4184 && h8300_funcvec_function_p (decl))
4185 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4186 else if (TREE_CODE (decl) == VAR_DECL
4187 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
4189 if (h8300_eightbit_data_p (decl))
4190 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA;
4191 else if (first && h8300_tiny_data_p (decl))
4192 extra_flags = SYMBOL_FLAG_TINY_DATA;
4196 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4200 output_simode_bld (bild, operands)
4206 /* Clear the destination register. */
4207 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
4209 /* Now output the bit load or bit inverse load, and store it in
4212 output_asm_insn ("bild\t%Z2,%Y1", operands);
4214 output_asm_insn ("bld\t%Z2,%Y1", operands);
4216 output_asm_insn ("bst\t#0,%w0", operands);
4220 /* Determine if we can clear the destination first. */
4221 int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
4222 && REGNO (operands[0]) != REGNO (operands[1]));
4225 output_asm_insn ("sub.l\t%S0,%S0", operands);
4227 /* Output the bit load or bit inverse load. */
4229 output_asm_insn ("bild\t%Z2,%Y1", operands);
4231 output_asm_insn ("bld\t%Z2,%Y1", operands);
4234 output_asm_insn ("xor.l\t%S0,%S0", operands);
4236 /* Perform the bit store. */
4237 output_asm_insn ("bst\t#0,%w0", operands);
4244 /* Given INSN and its current length LENGTH, return the adjustment
4245 (in bytes) to correctly compute INSN's length.
4247 We use this to get the lengths of various memory references correct. */
4250 h8300_adjust_insn_length (insn, length)
4252 int length ATTRIBUTE_UNUSED;
4254 rtx pat = PATTERN (insn);
4256 /* We must filter these out before calling get_attr_adjust_length. */
4257 if (GET_CODE (pat) == USE
4258 || GET_CODE (pat) == CLOBBER
4259 || GET_CODE (pat) == SEQUENCE
4260 || GET_CODE (pat) == ADDR_VEC
4261 || GET_CODE (pat) == ADDR_DIFF_VEC)
4264 if (get_attr_adjust_length (insn) == ADJUST_LENGTH_NO)
4267 /* Adjust length for reg->mem and mem->reg copies. */
4268 if (GET_CODE (pat) == SET
4269 && (GET_CODE (SET_SRC (pat)) == MEM
4270 || GET_CODE (SET_DEST (pat)) == MEM))
4272 /* This insn might need a length adjustment. */
4275 if (GET_CODE (SET_SRC (pat)) == MEM)
4276 addr = XEXP (SET_SRC (pat), 0);
4278 addr = XEXP (SET_DEST (pat), 0);
4282 /* On the H8/300, we subtract the difference between the
4283 actual length and the longest one, which is @(d:16,ERs). */
4285 /* @Rs is 2 bytes shorter than the longest. */
4286 if (GET_CODE (addr) == REG)
4289 /* @aa:8 is 2 bytes shorter than the longest. */
4290 if (GET_MODE (SET_SRC (pat)) == QImode
4291 && h8300_eightbit_constant_address_p (addr))
4296 /* On the H8/300H and H8S, we subtract the difference
4297 between the actual length and the longest one, which is
4300 /* @ERs is 6 bytes shorter than the longest. */
4301 if (GET_CODE (addr) == REG)
4304 /* @(d:16,ERs) is 6 bytes shorter than the longest. */
4305 if (GET_CODE (addr) == PLUS
4306 && GET_CODE (XEXP (addr, 0)) == REG
4307 && GET_CODE (XEXP (addr, 1)) == CONST_INT
4308 && INTVAL (XEXP (addr, 1)) > -32768
4309 && INTVAL (XEXP (addr, 1)) < 32767)
4312 /* @aa:8 is 6 bytes shorter than the longest. */
4313 if (GET_MODE (SET_SRC (pat)) == QImode
4314 && h8300_eightbit_constant_address_p (addr))
4317 /* @aa:16 is 4 bytes shorter than the longest. */
4318 if (h8300_tiny_constant_address_p (addr))
4321 /* @aa:24 is 2 bytes shorter than the longest. */
4322 if (GET_CODE (addr) == CONST_INT)
4327 /* Loading some constants needs adjustment. */
4328 if (GET_CODE (pat) == SET
4329 && GET_CODE (SET_SRC (pat)) == CONST_INT
4330 && GET_MODE (SET_DEST (pat)) == SImode
4331 && INTVAL (SET_SRC (pat)) != 0)
4333 int val = INTVAL (SET_SRC (pat));
4336 && ((val & 0xffff) == 0
4337 || ((val >> 16) & 0xffff) == 0))
4340 if (TARGET_H8300H || TARGET_H8300S)
4342 if (val == (val & 0xff)
4343 || val == (val & 0xff00))
4346 switch (val & 0xffffffff)
4362 /* Rotations need various adjustments. */
4363 if (GET_CODE (pat) == SET
4364 && (GET_CODE (SET_SRC (pat)) == ROTATE
4365 || GET_CODE (SET_SRC (pat)) == ROTATERT))
4367 rtx src = SET_SRC (pat);
4368 enum machine_mode mode = GET_MODE (src);
4372 if (GET_CODE (XEXP (src, 1)) != CONST_INT)
4375 amount = INTVAL (XEXP (src, 1));
4377 /* Clean up AMOUNT. */
4380 if ((unsigned int) amount > GET_MODE_BITSIZE (mode))
4381 amount = GET_MODE_BITSIZE (mode);
4383 /* Determine the faster direction. After this phase, amount
4384 will be at most a half of GET_MODE_BITSIZE (mode). */
4385 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2)
4386 /* Flip the direction. */
4387 amount = GET_MODE_BITSIZE (mode) - amount;
4389 /* See if a byte swap (in HImode) or a word swap (in SImode) can
4390 boost up the rotation. */
4391 if ((mode == HImode && TARGET_H8300 && amount >= 5)
4392 || (mode == HImode && TARGET_H8300H && amount >= 6)
4393 || (mode == HImode && TARGET_H8300S && amount == 8)
4394 || (mode == SImode && TARGET_H8300H && amount >= 10)
4395 || (mode == SImode && TARGET_H8300S && amount >= 13))
4397 /* Adjust AMOUNT and flip the direction. */
4398 amount = GET_MODE_BITSIZE (mode) / 2 - amount;
4402 /* We use 2-bit rotations on the H8S. */
4404 amount = amount / 2 + amount % 2;
4406 /* The H8/300 uses three insns to rotate one bit, taking 6
4408 states += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
4410 return -(20 - states);
4416 #ifndef OBJECT_FORMAT_ELF
4418 h8300_asm_named_section (name, flags)
4420 unsigned int flags ATTRIBUTE_UNUSED;
4422 /* ??? Perhaps we should be using default_coff_asm_named_section. */
4423 fprintf (asm_out_file, "\t.section %s\n", name);
4425 #endif /* ! OBJECT_FORMAT_ELF */
4427 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
4428 which is a special case of the 'R' operand. */
4431 h8300_eightbit_constant_address_p (x)
4434 /* The ranges of the 8-bit area. */
4435 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode);
4436 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode);
4437 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode);
4438 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode);
4439 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode);
4440 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode);
4442 unsigned HOST_WIDE_INT addr;
4444 /* We accept symbols declared with eightbit_data. */
4445 if (GET_CODE (x) == SYMBOL_REF)
4446 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
4448 if (GET_CODE (x) != CONST_INT)
4454 || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
4455 || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
4456 || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
4459 /* Nonzero if X is a constant address suitable as an 16-bit absolute
4460 on H8/300H and H8S. */
4463 h8300_tiny_constant_address_p (x)
4466 /* The ranges of the 16-bit area. */
4467 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode);
4468 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode);
4469 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode);
4470 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode);
4471 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode);
4472 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode);
4473 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode);
4474 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode);
4476 unsigned HOST_WIDE_INT addr;
4478 /* We accept symbols declared with tiny_data. */
4479 if (GET_CODE (x) == SYMBOL_REF)
4480 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0;
4482 if (GET_CODE (x) != CONST_INT)
4488 || ((TARGET_H8300H && !TARGET_NORMAL_MODE)
4489 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4)))
4490 || ((TARGET_H8300S && !TARGET_NORMAL_MODE)
4491 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4))));
4495 byte_accesses_mergeable_p (addr1, addr2)
4498 HOST_WIDE_INT offset1, offset2;
4506 else if (GET_CODE (addr1) == PLUS
4507 && REG_P (XEXP (addr1, 0))
4508 && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
4510 reg1 = XEXP (addr1, 0);
4511 offset1 = INTVAL (XEXP (addr1, 1));
4521 else if (GET_CODE (addr2) == PLUS
4522 && REG_P (XEXP (addr2, 0))
4523 && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
4525 reg2 = XEXP (addr2, 0);
4526 offset2 = INTVAL (XEXP (addr2, 1));
4531 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx)
4532 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx))
4534 && offset1 + 1 == offset2)