1 /* Target macros for the FRV port of GCC.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009,
4 Free Software Foundation, Inc.
5 Contributed by Red Hat Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 /* Frv general purpose macros. */
27 /* Align an address. */
28 #define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1))
30 /* Driver configuration. */
32 /* -fpic and -fPIC used to imply the -mlibrary-pic multilib, but with
33 FDPIC which multilib to use depends on whether FDPIC is in use or
34 not. The trick we use is to introduce -multilib-library-pic as a
35 pseudo-flag that selects the library-pic multilib, and map fpic
36 and fPIC to it only if fdpic is not selected. Also, if fdpic is
37 selected and no PIC/PIE options are present, we imply -fPIE.
38 Otherwise, if -fpic or -fPIC are enabled and we're optimizing for
39 speed, or if we have -On with n>=3, enable inlining of PLTs. As
40 for -mgprel-ro, we want to enable it by default, but not for -fpic or
43 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS \
45 %{!mhard-float:-msoft-float}\
46 %{!mmedia:-mno-media}}\
47 %{!mfdpic:%{fpic|fPIC: -multilib-library-pic}}\
48 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
49 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fPIE}}}}}}}} \
50 %{!mno-inline-plt:%{O*:%{!O0:%{!Os:%{fpic|fPIC:-minline-plt} \
51 %{!fpic:%{!fPIC:%{!O:%{!O1:%{!O2:-minline-plt}}}}}}}}} \
52 %{!mno-gprel-ro:%{!fpic:%{!fpie:-mgprel-ro}}}} \
54 #ifndef SUBTARGET_DRIVER_SELF_SPECS
55 # define SUBTARGET_DRIVER_SELF_SPECS
65 %{msoft-float} %{mhard-float} \
66 %{mdword} %{mno-dword} \
67 %{mdouble} %{mno-double} \
68 %{mmedia} %{mno-media} \
69 %{mmuladd} %{mno-muladd} \
70 %{mpack} %{mno-pack} \
71 %{mno-fdpic:-mnopic} %{mfdpic} \
72 %{fpic|fpie: -mpic} %{fPIC|fPIE: -mPIC} %{mlibrary-pic}}"
75 #define STARTFILE_SPEC "crt0%O%s frvbegin%O%s"
78 #define ENDFILE_SPEC "frvend%O%s"
81 #define MASK_DEFAULT_FRV \
88 #define MASK_DEFAULT_FR500 \
89 (MASK_MEDIA | MASK_DWORD | MASK_PACK)
91 #define MASK_DEFAULT_FR550 \
92 (MASK_MEDIA | MASK_DWORD | MASK_PACK)
94 #define MASK_DEFAULT_FR450 \
102 #define MASK_DEFAULT_FR400 \
111 #define MASK_DEFAULT_SIMPLE \
112 (MASK_GPR_32 | MASK_SOFT_FLOAT)
114 /* A C string constant that tells the GCC driver program options to pass to
115 `cc1'. It can also specify how to translate options you give to GCC into
116 options for GCC to pass to the `cc1'.
118 Do not define this macro if it does not need to do anything. */
119 /* For ABI compliance, we need to put bss data into the normal data section. */
120 #define CC1_SPEC "%{G*}"
125 %{mfdpic:-melf32frvfd -z text} \
126 %{static:-dn -Bstatic} \
127 %{shared:-Bdynamic} \
128 %{symbolic:-Bsymbolic} \
132 #define LIB_SPEC "--start-group -lc -lsim --end-group"
135 #define CPU_TYPE FRV_CPU_FR500
138 /* Run-time target specifications */
140 #define TARGET_CPU_CPP_BUILTINS() \
145 builtin_define ("__frv__"); \
146 builtin_assert ("machine=frv"); \
148 issue_rate = frv_issue_rate (); \
149 if (issue_rate > 1) \
150 builtin_define_with_int_value ("__FRV_VLIW__", issue_rate); \
151 builtin_define_with_int_value ("__FRV_GPR__", NUM_GPRS); \
152 builtin_define_with_int_value ("__FRV_FPR__", NUM_FPRS); \
153 builtin_define_with_int_value ("__FRV_ACC__", NUM_ACCS); \
155 switch (frv_cpu_type) \
157 case FRV_CPU_GENERIC: \
158 builtin_define ("__CPU_GENERIC__"); \
160 case FRV_CPU_FR550: \
161 builtin_define ("__CPU_FR550__"); \
163 case FRV_CPU_FR500: \
164 case FRV_CPU_TOMCAT: \
165 builtin_define ("__CPU_FR500__"); \
167 case FRV_CPU_FR450: \
168 builtin_define ("__CPU_FR450__"); \
170 case FRV_CPU_FR405: \
171 builtin_define ("__CPU_FR405__"); \
173 case FRV_CPU_FR400: \
174 builtin_define ("__CPU_FR400__"); \
176 case FRV_CPU_FR300: \
177 case FRV_CPU_SIMPLE: \
178 builtin_define ("__CPU_FR300__"); \
182 if (TARGET_HARD_FLOAT) \
183 builtin_define ("__FRV_HARD_FLOAT__"); \
185 builtin_define ("__FRV_DWORD__"); \
187 builtin_define ("__FRV_FDPIC__"); \
188 if (flag_leading_underscore > 0) \
189 builtin_define ("__FRV_UNDERSCORE__"); \
194 #define TARGET_HAS_FPRS (TARGET_HARD_FLOAT || TARGET_MEDIA)
196 #define NUM_GPRS (TARGET_GPR_32? 32 : 64)
197 #define NUM_FPRS (!TARGET_HAS_FPRS? 0 : TARGET_FPR_32? 32 : 64)
198 #define NUM_ACCS (!TARGET_MEDIA? 0 : TARGET_ACC_4? 4 : 8)
200 /* X is a valid accumulator number if (X & ACC_MASK) == X. */
204 : frv_cpu_type == FRV_CPU_FR450 ? 11 \
207 /* Macros to identify the blend of media instructions available. Revision 1
208 is the one found on the FR500. Revision 2 includes the changes made for
211 Treat the generic processor as a revision 1 machine for now, for
212 compatibility with earlier releases. */
214 #define TARGET_MEDIA_REV1 \
216 && (frv_cpu_type == FRV_CPU_GENERIC \
217 || frv_cpu_type == FRV_CPU_FR500))
219 #define TARGET_MEDIA_REV2 \
221 && (frv_cpu_type == FRV_CPU_FR400 \
222 || frv_cpu_type == FRV_CPU_FR405 \
223 || frv_cpu_type == FRV_CPU_FR450 \
224 || frv_cpu_type == FRV_CPU_FR550))
226 #define TARGET_MEDIA_FR450 \
227 (frv_cpu_type == FRV_CPU_FR450)
229 #define TARGET_FR500_FR550_BUILTINS \
230 (frv_cpu_type == FRV_CPU_FR500 \
231 || frv_cpu_type == FRV_CPU_FR550)
233 #define TARGET_FR405_BUILTINS \
234 (frv_cpu_type == FRV_CPU_FR405 \
235 || frv_cpu_type == FRV_CPU_FR450)
238 #define HAVE_AS_TLS 0
241 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_ALIGN_LABELS ? 3 : 0)
243 /* Small Data Area Support. */
244 /* Maximum size of variables that go in .sdata/.sbss.
245 The -msdata=foo switch also controls how small variables are handled. */
246 #ifndef SDATA_DEFAULT_SIZE
247 #define SDATA_DEFAULT_SIZE 8
253 /* Define this macro to have the value 1 if the most significant bit in a byte
254 has the lowest number; otherwise define it to have the value zero. This
255 means that bit-field instructions count from the most significant bit. If
256 the machine has no bit-field instructions, then this must still be defined,
257 but it doesn't matter which value it is defined to. This macro need not be
260 This macro does not affect the way structure fields are packed into bytes or
261 words; that is controlled by `BYTES_BIG_ENDIAN'. */
262 #define BITS_BIG_ENDIAN 1
264 /* Define this macro to have the value 1 if the most significant byte in a word
265 has the lowest number. This macro need not be a constant. */
266 #define BYTES_BIG_ENDIAN 1
268 /* Define this macro to have the value 1 if, in a multiword object, the most
269 significant word has the lowest number. This applies to both memory
270 locations and registers; GCC fundamentally assumes that the order of
271 words in memory is the same as the order in registers. This macro need not
273 #define WORDS_BIG_ENDIAN 1
275 /* Number of storage units in a word; normally 4. */
276 #define UNITS_PER_WORD 4
278 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
279 which has the specified mode and signedness is to be stored in a register.
280 This macro is only called when TYPE is a scalar type.
282 On most RISC machines, which only have operations that operate on a full
283 register, define this macro to set M to `word_mode' if M is an integer mode
284 narrower than `BITS_PER_WORD'. In most cases, only integer modes should be
285 widened because wider-precision floating-point operations are usually more
286 expensive than their narrower counterparts.
288 For most machines, the macro definition does not change UNSIGNEDP. However,
289 some machines, have instructions that preferentially handle either signed or
290 unsigned quantities of certain modes. For example, on the DEC Alpha, 32-bit
291 loads from memory and 32-bit add instructions sign-extend the result to 64
292 bits. On such machines, set UNSIGNEDP according to which kind of extension
295 Do not define this macro if it would never modify MODE. */
296 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
299 if (GET_MODE_CLASS (MODE) == MODE_INT \
300 && GET_MODE_SIZE (MODE) < 4) \
305 /* Normal alignment required for function parameters on the stack, in bits.
306 All stack parameters receive at least this much alignment regardless of data
307 type. On most machines, this is the same as the size of an integer. */
308 #define PARM_BOUNDARY 32
310 /* Define this macro if you wish to preserve a certain alignment for the stack
311 pointer. The definition is a C expression for the desired alignment
314 If `PUSH_ROUNDING' is not defined, the stack will always be aligned to the
315 specified boundary. If `PUSH_ROUNDING' is defined and specifies a less
316 strict alignment than `STACK_BOUNDARY', the stack may be momentarily
317 unaligned while pushing arguments. */
318 #define STACK_BOUNDARY 64
320 /* Alignment required for a function entry point, in bits. */
321 #define FUNCTION_BOUNDARY 128
323 /* Biggest alignment that any data type can require on this machine,
325 #define BIGGEST_ALIGNMENT 64
327 /* @@@ A hack, needed because libobjc wants to use ADJUST_FIELD_ALIGN for
329 #ifdef IN_TARGET_LIBS
330 #define BIGGEST_FIELD_ALIGNMENT 64
332 /* An expression for the alignment of a structure field FIELD if the
333 alignment computed in the usual way is COMPUTED. GCC uses this
334 value instead of the value in `BIGGEST_ALIGNMENT' or
335 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
336 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
337 frv_adjust_field_align (FIELD, COMPUTED)
340 /* If defined, a C expression to compute the alignment for a static variable.
341 TYPE is the data type, and ALIGN is the alignment that the object
342 would ordinarily have. The value of this macro is used instead of that
343 alignment to align the object.
345 If this macro is not defined, then ALIGN is used.
347 One use of this macro is to increase alignment of medium-size data to make
348 it all fit in fewer cache lines. Another is to cause character arrays to be
349 word-aligned so that `strcpy' calls that copy constants to character arrays
350 can be done inline. */
351 #define DATA_ALIGNMENT(TYPE, ALIGN) \
352 (TREE_CODE (TYPE) == ARRAY_TYPE \
353 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
354 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
356 /* If defined, a C expression to compute the alignment given to a constant that
357 is being placed in memory. CONSTANT is the constant and ALIGN is the
358 alignment that the object would ordinarily have. The value of this macro is
359 used instead of that alignment to align the object.
361 If this macro is not defined, then ALIGN is used.
363 The typical use of this macro is to increase alignment for string constants
364 to be word aligned so that `strcpy' calls that copy constants can be done
366 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
367 (TREE_CODE (EXP) == STRING_CST \
368 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
370 /* Define this macro to be the value 1 if instructions will fail to work if
371 given data not on the nominal alignment. If instructions will merely go
372 slower in that case, define this macro as 0. */
373 #define STRICT_ALIGNMENT 1
375 #define PCC_BITFIELD_TYPE_MATTERS 1
378 /* Layout of Source Language Data Types. */
380 #define CHAR_TYPE_SIZE 8
381 #define SHORT_TYPE_SIZE 16
382 #define INT_TYPE_SIZE 32
383 #define LONG_TYPE_SIZE 32
384 #define LONG_LONG_TYPE_SIZE 64
385 #define FLOAT_TYPE_SIZE 32
386 #define DOUBLE_TYPE_SIZE 64
387 #define LONG_DOUBLE_TYPE_SIZE 64
389 /* An expression whose value is 1 or 0, according to whether the type `char'
390 should be signed or unsigned by default. The user can always override this
391 default with the options `-fsigned-char' and `-funsigned-char'. */
392 #define DEFAULT_SIGNED_CHAR 1
395 #define SIZE_TYPE "unsigned int"
398 #define PTRDIFF_TYPE "int"
401 #define WCHAR_TYPE "long int"
403 #undef WCHAR_TYPE_SIZE
404 #define WCHAR_TYPE_SIZE BITS_PER_WORD
407 /* General purpose registers. */
408 #define GPR_FIRST 0 /* First gpr */
409 #define GPR_LAST (GPR_FIRST + 63) /* Last gpr */
410 #define GPR_R0 GPR_FIRST /* R0, constant 0 */
411 #define GPR_FP (GPR_FIRST + 2) /* Frame pointer */
412 #define GPR_SP (GPR_FIRST + 1) /* Stack pointer */
413 /* small data register */
414 #define SDA_BASE_REG ((unsigned)(TARGET_FDPIC ? -1 : flag_pic ? PIC_REGNO : (GPR_FIRST + 16)))
415 #define PIC_REGNO (GPR_FIRST + (TARGET_FDPIC?15:17)) /* PIC register. */
416 #define FDPIC_FPTR_REGNO (GPR_FIRST + 14) /* uClinux PIC function pointer register. */
417 #define FDPIC_REGNO (GPR_FIRST + 15) /* uClinux PIC register. */
419 #define HARD_REGNO_RENAME_OK(from,to) (TARGET_FDPIC ? ((to) != FDPIC_REG) : 1)
421 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
423 #define FPR_FIRST 64 /* First FP reg */
424 #define FPR_LAST 127 /* Last FP reg */
426 #define GPR_TEMP_NUM frv_condexec_temps /* # gprs to reserve for temps */
428 /* We reserve the last CR and CCR in each category to be used as a reload
429 register to reload the CR/CCR registers. This is a kludge. */
430 #define CC_FIRST 128 /* First ICC/FCC reg */
431 #define CC_LAST 135 /* Last ICC/FCC reg */
432 #define ICC_FIRST (CC_FIRST + 4) /* First ICC reg */
433 #define ICC_LAST (CC_FIRST + 7) /* Last ICC reg */
434 #define ICC_TEMP (CC_FIRST + 7) /* Temporary ICC reg */
435 #define FCC_FIRST (CC_FIRST) /* First FCC reg */
436 #define FCC_LAST (CC_FIRST + 3) /* Last FCC reg */
438 /* Amount to shift a value to locate a ICC or FCC register in the CCR
439 register and shift it to the bottom 4 bits. */
440 #define CC_SHIFT_RIGHT(REGNO) (((REGNO) - CC_FIRST) << 2)
442 /* Mask to isolate a single ICC/FCC value. */
445 /* Masks to isolate the various bits in an ICC field. */
446 #define ICC_MASK_N 0x8 /* negative */
447 #define ICC_MASK_Z 0x4 /* zero */
448 #define ICC_MASK_V 0x2 /* overflow */
449 #define ICC_MASK_C 0x1 /* carry */
451 /* Mask to isolate the N/Z flags in an ICC. */
452 #define ICC_MASK_NZ (ICC_MASK_N | ICC_MASK_Z)
454 /* Mask to isolate the Z/C flags in an ICC. */
455 #define ICC_MASK_ZC (ICC_MASK_Z | ICC_MASK_C)
457 /* Masks to isolate the various bits in a FCC field. */
458 #define FCC_MASK_E 0x8 /* equal */
459 #define FCC_MASK_L 0x4 /* less than */
460 #define FCC_MASK_G 0x2 /* greater than */
461 #define FCC_MASK_U 0x1 /* unordered */
463 /* For CCR registers, the machine wants CR4..CR7 to be used for integer
464 code and CR0..CR3 to be used for floating point. */
465 #define CR_FIRST 136 /* First CCR */
466 #define CR_LAST 143 /* Last CCR */
467 #define CR_NUM (CR_LAST-CR_FIRST+1) /* # of CCRs (8) */
468 #define ICR_FIRST (CR_FIRST + 4) /* First integer CCR */
469 #define ICR_LAST (CR_FIRST + 7) /* Last integer CCR */
470 #define ICR_TEMP ICR_LAST /* Temp integer CCR */
471 #define FCR_FIRST (CR_FIRST + 0) /* First float CCR */
472 #define FCR_LAST (CR_FIRST + 3) /* Last float CCR */
474 /* Amount to shift a value to locate a CR register in the CCCR special purpose
475 register and shift it to the bottom 2 bits. */
476 #define CR_SHIFT_RIGHT(REGNO) (((REGNO) - CR_FIRST) << 1)
478 /* Mask to isolate a single CR value. */
481 #define ACC_FIRST 144 /* First acc register */
482 #define ACC_LAST 155 /* Last acc register */
484 #define ACCG_FIRST 156 /* First accg register */
485 #define ACCG_LAST 167 /* Last accg register */
487 #define AP_FIRST 168 /* fake argument pointer */
489 #define SPR_FIRST 169
491 #define LR_REGNO (SPR_FIRST)
492 #define LCR_REGNO (SPR_FIRST + 1)
493 #define IACC_FIRST (SPR_FIRST + 2)
494 #define IACC_LAST (SPR_FIRST + 3)
496 #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST)
497 #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM)
498 #define FPR_P(R) IN_RANGE (R, FPR_FIRST, FPR_LAST)
499 #define CC_P(R) IN_RANGE (R, CC_FIRST, CC_LAST)
500 #define ICC_P(R) IN_RANGE (R, ICC_FIRST, ICC_LAST)
501 #define FCC_P(R) IN_RANGE (R, FCC_FIRST, FCC_LAST)
502 #define CR_P(R) IN_RANGE (R, CR_FIRST, CR_LAST)
503 #define ICR_P(R) IN_RANGE (R, ICR_FIRST, ICR_LAST)
504 #define FCR_P(R) IN_RANGE (R, FCR_FIRST, FCR_LAST)
505 #define ACC_P(R) IN_RANGE (R, ACC_FIRST, ACC_LAST)
506 #define ACCG_P(R) IN_RANGE (R, ACCG_FIRST, ACCG_LAST)
507 #define SPR_P(R) IN_RANGE (R, SPR_FIRST, SPR_LAST)
509 #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
510 #define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
511 #define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
512 #define CC_OR_PSEUDO_P(R) (CC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
513 #define ICC_OR_PSEUDO_P(R) (ICC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
514 #define FCC_OR_PSEUDO_P(R) (FCC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
515 #define CR_OR_PSEUDO_P(R) (CR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
516 #define ICR_OR_PSEUDO_P(R) (ICR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
517 #define FCR_OR_PSEUDO_P(R) (FCR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
518 #define ACC_OR_PSEUDO_P(R) (ACC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
519 #define ACCG_OR_PSEUDO_P(R) (ACCG_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
521 #define MAX_STACK_IMMEDIATE_OFFSET 2047
524 /* Register Basics. */
526 /* Number of hardware registers known to the compiler. They receive numbers 0
527 through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number
528 really is assigned the number `FIRST_PSEUDO_REGISTER'. */
529 #define FIRST_PSEUDO_REGISTER (SPR_LAST + 1)
531 /* The first/last register that can contain the arguments to a function. */
532 #define FIRST_ARG_REGNUM (GPR_FIRST + 8)
533 #define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + FRV_NUM_ARG_REGS - 1)
535 /* Registers used by the exception handling functions. These should be
536 registers that are not otherwise used by the calling sequence. */
537 #define FIRST_EH_REGNUM 14
538 #define LAST_EH_REGNUM 15
540 /* Scratch registers used in the prologue, epilogue and thunks.
541 OFFSET_REGNO is for loading constant addends that are too big for a
542 single instruction. TEMP_REGNO is used for transferring SPRs to and from
543 the stack, and various other activities. */
544 #define OFFSET_REGNO 4
547 /* Registers used in the prologue. OLD_SP_REGNO is the old stack pointer,
548 which is sometimes used to set up the frame pointer. */
549 #define OLD_SP_REGNO 6
551 /* Registers used in the epilogue. STACKADJ_REGNO stores the exception
552 handler's stack adjustment. */
553 #define STACKADJ_REGNO 6
555 /* Registers used in thunks. JMP_REGNO is used for loading the target
559 #define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_EH_REGNUM - FIRST_EH_REGNUM)? \
560 (N) + FIRST_EH_REGNUM : INVALID_REGNUM)
561 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, STACKADJ_REGNO)
562 #define EH_RETURN_HANDLER_RTX RETURN_ADDR_RTX (0, frame_pointer_rtx)
564 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNO)
566 /* An initializer that says which registers are used for fixed purposes all
567 throughout the compiled code and are therefore not available for general
568 allocation. These would include the stack pointer, the frame pointer
569 (except on machines where that can be used as a general register when no
570 frame pointer is needed), the program counter on machines where that is
571 considered one of the addressable registers, and any other numbered register
574 This information is expressed as a sequence of numbers, separated by commas
575 and surrounded by braces. The Nth number is 1 if register N is fixed, 0
578 The table initialized from this macro, and the table initialized by the
579 following one, may be overridden at run time either automatically, by the
580 actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the
581 command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */
586 gr3 -- Hidden Parameter
587 gr16 -- Small Data reserved
593 cr3 -- reserved to reload FCC registers.
594 cr7 -- reserved to reload ICC registers. */
595 #define FIXED_REGISTERS \
596 { /* Integer Registers */ \
597 1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \
598 0, 0, 0, 0, 0, 0, 0, 0, /* 008-015, gr8 - gr15 */ \
599 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \
600 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \
601 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \
602 0, 0, 0, 0, 0, 0, 0, 0, /* 040-040, gr48 - gr47 */ \
603 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \
604 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \
605 /* Float Registers */ \
606 0, 0, 0, 0, 0, 0, 0, 0, /* 064-071, fr0 - fr7 */ \
607 0, 0, 0, 0, 0, 0, 0, 0, /* 072-079, fr8 - fr15 */ \
608 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \
609 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \
610 0, 0, 0, 0, 0, 0, 0, 0, /* 096-103, fr32 - fr39 */ \
611 0, 0, 0, 0, 0, 0, 0, 0, /* 104-111, fr48 - fr47 */ \
612 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \
613 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \
614 /* Condition Code Registers */ \
615 0, 0, 0, 0, /* 128-131, fcc0 - fcc3 */ \
616 0, 0, 0, 1, /* 132-135, icc0 - icc3 */ \
617 /* Conditional execution Registers (CCR) */ \
618 0, 0, 0, 0, 0, 0, 0, 1, /* 136-143, cr0 - cr7 */ \
620 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \
621 1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \
622 1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \
623 1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \
624 /* Other registers */ \
625 1, /* 168, AP - fake arg ptr */ \
626 1, /* 169, LR - Link register*/ \
627 0, /* 170, LCR - Loop count reg*/ \
628 1, 1 /* 171-172, iacc0 */ \
631 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in
632 general) by function calls as well as for fixed registers. This macro
633 therefore identifies the registers that are not available for general
634 allocation of values that must live across function calls.
636 If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically
637 saves it on function entry and restores it on function exit, if the register
638 is used within the function. */
639 #define CALL_USED_REGISTERS \
640 { /* Integer Registers */ \
641 1, 1, 1, 1, 1, 1, 1, 1, /* 000-007, gr0 - gr7 */ \
642 1, 1, 1, 1, 1, 1, 1, 1, /* 008-015, gr8 - gr15 */ \
643 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \
644 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \
645 1, 1, 1, 1, 1, 1, 1, 1, /* 032-039, gr32 - gr39 */ \
646 1, 1, 1, 1, 1, 1, 1, 1, /* 040-040, gr48 - gr47 */ \
647 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \
648 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \
649 /* Float Registers */ \
650 1, 1, 1, 1, 1, 1, 1, 1, /* 064-071, fr0 - fr7 */ \
651 1, 1, 1, 1, 1, 1, 1, 1, /* 072-079, fr8 - fr15 */ \
652 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \
653 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \
654 1, 1, 1, 1, 1, 1, 1, 1, /* 096-103, fr32 - fr39 */ \
655 1, 1, 1, 1, 1, 1, 1, 1, /* 104-111, fr48 - fr47 */ \
656 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \
657 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \
658 /* Condition Code Registers */ \
659 1, 1, 1, 1, /* 128-131, fcc0 - fcc3 */ \
660 1, 1, 1, 1, /* 132-135, icc0 - icc3 */ \
661 /* Conditional execution Registers (CCR) */ \
662 1, 1, 1, 1, 1, 1, 1, 1, /* 136-143, cr0 - cr7 */ \
664 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \
665 1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \
666 1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \
667 1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \
668 /* Other registers */ \
669 1, /* 168, AP - fake arg ptr */ \
670 1, /* 169, LR - Link register*/ \
671 1, /* 170, LCR - Loop count reg */ \
672 1, 1 /* 171-172, iacc0 */ \
676 /* Order of allocation of registers. */
678 /* If defined, an initializer for a vector of integers, containing the numbers
679 of hard registers in the order in which GCC should prefer to use them
680 (from most preferred to least).
682 If this macro is not defined, registers are used lowest numbered first (all
685 One use of this macro is on machines where the highest numbered registers
686 must always be saved and the save-multiple-registers instruction supports
687 only sequences of consecutive registers. On such machines, define
688 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
689 allocatable register first. */
691 /* On the FRV, allocate GR16 and GR17 after other saved registers so that we
692 have a better chance of allocating 2 registers at a time and can use the
693 double word load/store instructions in the prologue. */
694 #define REG_ALLOC_ORDER \
696 /* volatile registers */ \
697 GPR_FIRST + 4, GPR_FIRST + 5, GPR_FIRST + 6, GPR_FIRST + 7, \
698 GPR_FIRST + 8, GPR_FIRST + 9, GPR_FIRST + 10, GPR_FIRST + 11, \
699 GPR_FIRST + 12, GPR_FIRST + 13, GPR_FIRST + 14, GPR_FIRST + 15, \
700 GPR_FIRST + 32, GPR_FIRST + 33, GPR_FIRST + 34, GPR_FIRST + 35, \
701 GPR_FIRST + 36, GPR_FIRST + 37, GPR_FIRST + 38, GPR_FIRST + 39, \
702 GPR_FIRST + 40, GPR_FIRST + 41, GPR_FIRST + 42, GPR_FIRST + 43, \
703 GPR_FIRST + 44, GPR_FIRST + 45, GPR_FIRST + 46, GPR_FIRST + 47, \
705 FPR_FIRST + 0, FPR_FIRST + 1, FPR_FIRST + 2, FPR_FIRST + 3, \
706 FPR_FIRST + 4, FPR_FIRST + 5, FPR_FIRST + 6, FPR_FIRST + 7, \
707 FPR_FIRST + 8, FPR_FIRST + 9, FPR_FIRST + 10, FPR_FIRST + 11, \
708 FPR_FIRST + 12, FPR_FIRST + 13, FPR_FIRST + 14, FPR_FIRST + 15, \
709 FPR_FIRST + 32, FPR_FIRST + 33, FPR_FIRST + 34, FPR_FIRST + 35, \
710 FPR_FIRST + 36, FPR_FIRST + 37, FPR_FIRST + 38, FPR_FIRST + 39, \
711 FPR_FIRST + 40, FPR_FIRST + 41, FPR_FIRST + 42, FPR_FIRST + 43, \
712 FPR_FIRST + 44, FPR_FIRST + 45, FPR_FIRST + 46, FPR_FIRST + 47, \
714 ICC_FIRST + 0, ICC_FIRST + 1, ICC_FIRST + 2, ICC_FIRST + 3, \
715 FCC_FIRST + 0, FCC_FIRST + 1, FCC_FIRST + 2, FCC_FIRST + 3, \
716 CR_FIRST + 0, CR_FIRST + 1, CR_FIRST + 2, CR_FIRST + 3, \
717 CR_FIRST + 4, CR_FIRST + 5, CR_FIRST + 6, CR_FIRST + 7, \
719 /* saved registers */ \
720 GPR_FIRST + 18, GPR_FIRST + 19, \
721 GPR_FIRST + 20, GPR_FIRST + 21, GPR_FIRST + 22, GPR_FIRST + 23, \
722 GPR_FIRST + 24, GPR_FIRST + 25, GPR_FIRST + 26, GPR_FIRST + 27, \
723 GPR_FIRST + 48, GPR_FIRST + 49, GPR_FIRST + 50, GPR_FIRST + 51, \
724 GPR_FIRST + 52, GPR_FIRST + 53, GPR_FIRST + 54, GPR_FIRST + 55, \
725 GPR_FIRST + 56, GPR_FIRST + 57, GPR_FIRST + 58, GPR_FIRST + 59, \
726 GPR_FIRST + 60, GPR_FIRST + 61, GPR_FIRST + 62, GPR_FIRST + 63, \
727 GPR_FIRST + 16, GPR_FIRST + 17, \
729 FPR_FIRST + 16, FPR_FIRST + 17, FPR_FIRST + 18, FPR_FIRST + 19, \
730 FPR_FIRST + 20, FPR_FIRST + 21, FPR_FIRST + 22, FPR_FIRST + 23, \
731 FPR_FIRST + 24, FPR_FIRST + 25, FPR_FIRST + 26, FPR_FIRST + 27, \
732 FPR_FIRST + 28, FPR_FIRST + 29, FPR_FIRST + 30, FPR_FIRST + 31, \
733 FPR_FIRST + 48, FPR_FIRST + 49, FPR_FIRST + 50, FPR_FIRST + 51, \
734 FPR_FIRST + 52, FPR_FIRST + 53, FPR_FIRST + 54, FPR_FIRST + 55, \
735 FPR_FIRST + 56, FPR_FIRST + 57, FPR_FIRST + 58, FPR_FIRST + 59, \
736 FPR_FIRST + 60, FPR_FIRST + 61, FPR_FIRST + 62, FPR_FIRST + 63, \
738 /* special or fixed registers */ \
739 GPR_FIRST + 0, GPR_FIRST + 1, GPR_FIRST + 2, GPR_FIRST + 3, \
740 GPR_FIRST + 28, GPR_FIRST + 29, GPR_FIRST + 30, GPR_FIRST + 31, \
741 ACC_FIRST + 0, ACC_FIRST + 1, ACC_FIRST + 2, ACC_FIRST + 3, \
742 ACC_FIRST + 4, ACC_FIRST + 5, ACC_FIRST + 6, ACC_FIRST + 7, \
743 ACC_FIRST + 8, ACC_FIRST + 9, ACC_FIRST + 10, ACC_FIRST + 11, \
744 ACCG_FIRST + 0, ACCG_FIRST + 1, ACCG_FIRST + 2, ACCG_FIRST + 3, \
745 ACCG_FIRST + 4, ACCG_FIRST + 5, ACCG_FIRST + 6, ACCG_FIRST + 7, \
746 ACCG_FIRST + 8, ACCG_FIRST + 9, ACCG_FIRST + 10, ACCG_FIRST + 11, \
747 AP_FIRST, LR_REGNO, LCR_REGNO, \
748 IACC_FIRST + 0, IACC_FIRST + 1 \
752 /* How Values Fit in Registers. */
754 /* A C expression for the number of consecutive hard registers, starting at
755 register number REGNO, required to hold a value of mode MODE.
757 On a machine where all registers are exactly one word, a suitable definition
760 #define HARD_REGNO_NREGS(REGNO, MODE) \
761 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
762 / UNITS_PER_WORD)) */
764 /* On the FRV, make the CC modes take 3 words in the integer registers, so that
765 we can build the appropriate instructions to properly reload the values. */
766 #define HARD_REGNO_NREGS(REGNO, MODE) frv_hard_regno_nregs (REGNO, MODE)
768 /* A C expression that is nonzero if it is permissible to store a value of mode
769 MODE in hard register number REGNO (or in several registers starting with
770 that one). For a machine where all registers are equivalent, a suitable
773 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
775 It is not necessary for this macro to check for the numbers of fixed
776 registers, because the allocation mechanism considers them to be always
779 On some machines, double-precision values must be kept in even/odd register
780 pairs. The way to implement that is to define this macro to reject odd
781 register numbers for such modes.
783 The minimum requirement for a mode to be OK in a register is that the
784 `movMODE' instruction pattern support moves between the register and any
785 other hard register for which the mode is OK; and that moving a value into
786 the register and back out not alter it.
788 Since the same instruction used to move `SImode' will work for all narrower
789 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
790 to distinguish between these modes, provided you define patterns `movhi',
791 etc., to take advantage of this. This is useful because of the interaction
792 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
793 all integer modes to be tieable.
795 Many machines have special registers for floating point arithmetic. Often
796 people assume that floating point machine modes are allowed only in floating
797 point registers. This is not true. Any registers that can hold integers
798 can safely *hold* a floating point machine mode, whether or not floating
799 arithmetic can be done on it in those registers. Integer move instructions
800 can be used to move the values.
802 On some machines, though, the converse is true: fixed-point machine modes
803 may not go in floating registers. This is true if the floating registers
804 normalize any value stored in them, because storing a non-floating value
805 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
806 fixed-point machine modes in floating registers. But if the floating
807 registers do not automatically normalize, if you can store any bit pattern
808 in one and retrieve it unchanged without a trap, then any machine mode may
809 go in a floating register, so you can define this macro to say so.
811 The primary significance of special floating registers is rather that they
812 are the registers acceptable in floating point arithmetic instructions.
813 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
814 writing the proper constraints for those instructions.
816 On some machines, the floating registers are especially slow to access, so
817 that it is better to store a value in a stack frame than in such a register
818 if floating point arithmetic is not being done. As long as the floating
819 registers are not in class `GENERAL_REGS', they will not be used unless some
820 pattern's constraint asks for one. */
821 #define HARD_REGNO_MODE_OK(REGNO, MODE) frv_hard_regno_mode_ok (REGNO, MODE)
823 /* A C expression that is nonzero if it is desirable to choose register
824 allocation so as to avoid move instructions between a value of mode MODE1
825 and a value of mode MODE2.
827 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
828 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
830 #define MODES_TIEABLE_P(MODE1, MODE2) (MODE1 == MODE2)
832 /* Define this macro if the compiler should avoid copies to/from CCmode
833 registers. You should only define this macro if support fo copying to/from
834 CCmode is incomplete. */
835 #define AVOID_CCMODE_COPIES
838 /* Register Classes. */
840 /* An enumeral type that must be defined with all the register class names as
841 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
842 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
843 which is not a register class but rather tells how many classes there are.
845 Each register class has a number, which is the value of casting the class
846 name to type `int'. The number serves as an index in many of the tables
880 #define GENERAL_REGS GPR_REGS
882 /* The number of distinct register classes, defined as follows:
884 #define N_REG_CLASSES (int) LIM_REG_CLASSES */
885 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
887 /* An initializer containing the names of the register classes as C string
888 constants. These names are used in writing some of the debugging dumps. */
889 #define REG_CLASS_NAMES { \
919 /* An initializer containing the contents of the register classes, as integers
920 which are bit masks. The Nth integer specifies the contents of class N.
921 The way the integer MASK is interpreted is that register R is in the class
922 if `MASK & (1 << R)' is 1.
924 When the machine has more than 32 registers, an integer does not suffice.
925 Then the integers are replaced by sub-initializers, braced groupings
926 containing several integers. Each sub-initializer must be suitable as an
927 initializer for the type `HARD_REG_SET' which is defined in
929 #define REG_CLASS_CONTENTS \
930 { /* gr0-gr31 gr32-gr63 fr0-fr31 fr32-fr-63 cc/ccr/acc ap/spr */ \
931 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* NO_REGS */\
932 { 0x00000000,0x00000000,0x00000000,0x00000000,0x000000f0,0x0}, /* ICC_REGS */\
933 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000000f,0x0}, /* FCC_REGS */\
934 { 0x00000000,0x00000000,0x00000000,0x00000000,0x000000ff,0x0}, /* CC_REGS */\
935 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000f000,0x0}, /* ICR_REGS */\
936 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000f00,0x0}, /* FCR_REGS */\
937 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000ff00,0x0}, /* CR_REGS */\
938 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x400}, /* LCR_REGS */\
939 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x200}, /* LR_REGS */\
940 { 0x00000100,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR8_REGS */\
941 { 0x00000200,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR9_REGS */\
942 { 0x00000300,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR89_REGS */\
943 { 0x00008000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_REGS */\
944 { 0x00004000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_FPTR_REGS */\
945 { 0x0000c000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_CALL_REGS */\
946 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x1e00}, /* SPR_REGS */\
947 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* QUAD_ACC */\
948 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* EVEN_ACC */\
949 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* ACC_REGS */\
950 { 0x00000000,0x00000000,0x00000000,0x00000000,0xf0000000,0xff}, /* ACCG_REGS*/\
951 { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* QUAD_FPR */\
952 { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FEVEN_REG*/\
953 { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FPR_REGS */\
954 { 0x0ffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* QUAD_REGS*/\
955 { 0xfffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* EVEN_REGS*/\
956 { 0xffffffff,0xffffffff,0x00000000,0x00000000,0x00000000,0x100}, /* GPR_REGS */\
957 { 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\
960 /* A C expression whose value is a register class containing hard register
961 REGNO. In general there is more than one such class; choose a class which
962 is "minimal", meaning that no smaller class also contains the register. */
964 extern enum reg_class regno_reg_class[];
965 #define REGNO_REG_CLASS(REGNO) regno_reg_class [REGNO]
967 /* A macro whose definition is the name of the class to which a valid base
968 register must belong. A base register is one used in an address which is
969 the register value plus a displacement. */
970 #define BASE_REG_CLASS GPR_REGS
972 /* A macro whose definition is the name of the class to which a valid index
973 register must belong. An index register is one used in an address where its
974 value is either multiplied by a scale factor or added to another register
975 (as well as added to a displacement). */
976 #define INDEX_REG_CLASS GPR_REGS
978 /* A C expression which is nonzero if register number NUM is suitable for use
979 as a base register in operand addresses. It may be either a suitable hard
980 register or a pseudo register that has been allocated such a hard register. */
981 #define REGNO_OK_FOR_BASE_P(NUM) \
982 ((NUM) < FIRST_PSEUDO_REGISTER \
984 : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM])))
986 /* A C expression which is nonzero if register number NUM is suitable for use
987 as an index register in operand addresses. It may be either a suitable hard
988 register or a pseudo register that has been allocated such a hard register.
990 The difference between an index register and a base register is that the
991 index register may be scaled. If an address involves the sum of two
992 registers, neither one of them scaled, then either one may be labeled the
993 "base" and the other the "index"; but whichever labeling is used must fit
994 the machine's constraints of which registers may serve in each capacity.
995 The compiler will try both labelings, looking for one that is valid, and
996 will reload one or both registers only if neither labeling works. */
997 #define REGNO_OK_FOR_INDEX_P(NUM) \
998 ((NUM) < FIRST_PSEUDO_REGISTER \
1000 : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM])))
1002 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1003 frv_secondary_reload_class (CLASS, MODE, X)
1005 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1006 frv_secondary_reload_class (CLASS, MODE, X)
1008 /* A C expression for the maximum number of consecutive registers of
1009 class CLASS needed to hold a value of mode MODE.
1011 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
1012 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
1013 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
1015 This macro helps control the handling of multiple-word values in
1018 This declaration is required. */
1019 #define CLASS_MAX_NREGS(CLASS, MODE) frv_class_max_nregs (CLASS, MODE)
1021 #define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x)))
1024 /* Basic Stack Layout. */
1026 /* Structure to describe information about a saved range of registers */
1028 typedef struct frv_stack_regs {
1029 const char * name; /* name of the register ranges */
1030 int first; /* first register in the range */
1031 int last; /* last register in the range */
1032 int size_1word; /* # of bytes to be stored via 1 word stores */
1033 int size_2words; /* # of bytes to be stored via 2 word stores */
1034 unsigned char field_p; /* true if the registers are a single SPR */
1035 unsigned char dword_p; /* true if we can do dword stores */
1036 unsigned char special_p; /* true if the regs have a fixed save loc. */
1039 /* Register ranges to look into saving. */
1040 #define STACK_REGS_GPR 0 /* Gprs (normally gr16..gr31, gr48..gr63) */
1041 #define STACK_REGS_FPR 1 /* Fprs (normally fr16..fr31, fr48..fr63) */
1042 #define STACK_REGS_LR 2 /* LR register */
1043 #define STACK_REGS_CC 3 /* CCrs (normally not saved) */
1044 #define STACK_REGS_LCR 5 /* lcr register */
1045 #define STACK_REGS_STDARG 6 /* stdarg registers */
1046 #define STACK_REGS_STRUCT 7 /* structure return (gr3) */
1047 #define STACK_REGS_FP 8 /* FP register */
1048 #define STACK_REGS_MAX 9 /* # of register ranges */
1050 /* Values for save_p field. */
1051 #define REG_SAVE_NO_SAVE 0 /* register not saved */
1052 #define REG_SAVE_1WORD 1 /* save the register */
1053 #define REG_SAVE_2WORDS 2 /* save register and register+1 */
1055 /* Structure used to define the frv stack. */
1057 typedef struct frv_stack {
1058 int total_size; /* total bytes allocated for stack */
1059 int vars_size; /* variable save area size */
1060 int parameter_size; /* outgoing parameter size */
1061 int stdarg_size; /* size of regs needed to be saved for stdarg */
1062 int regs_size; /* size of the saved registers */
1063 int regs_size_1word; /* # of bytes to be stored via 1 word stores */
1064 int regs_size_2words; /* # of bytes to be stored via 2 word stores */
1065 int header_size; /* size of the old FP, struct ret., LR save */
1066 int pretend_size; /* size of pretend args */
1067 int vars_offset; /* offset to save local variables from new SP*/
1068 int regs_offset; /* offset to save registers from new SP */
1069 /* register range information */
1070 frv_stack_regs_t regs[STACK_REGS_MAX];
1071 /* offset to store each register */
1072 int reg_offset[FIRST_PSEUDO_REGISTER];
1073 /* whether to save register (& reg+1) */
1074 unsigned char save_p[FIRST_PSEUDO_REGISTER];
1077 /* Define this macro if pushing a word onto the stack moves the stack pointer
1078 to a smaller address. */
1079 #define STACK_GROWS_DOWNWARD 1
1081 /* Define this macro to nonzero if the addresses of local variable slots
1082 are at negative offsets from the frame pointer. */
1083 #define FRAME_GROWS_DOWNWARD 1
1085 /* Offset from the frame pointer to the first local variable slot to be
1088 If `FRAME_GROWS_DOWNWARD', find the next slot's offset by subtracting the
1089 first slot's length from `STARTING_FRAME_OFFSET'. Otherwise, it is found by
1090 adding the length of the first slot to the value `STARTING_FRAME_OFFSET'. */
1091 #define STARTING_FRAME_OFFSET 0
1093 /* Offset from the stack pointer register to the first location at which
1094 outgoing arguments are placed. If not specified, the default value of zero
1095 is used. This is the proper value for most machines.
1097 If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
1098 location at which outgoing arguments are placed. */
1099 #define STACK_POINTER_OFFSET 0
1101 /* Offset from the argument pointer register to the first argument's address.
1102 On some machines it may depend on the data type of the function.
1104 If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
1105 argument's address. */
1106 #define FIRST_PARM_OFFSET(FUNDECL) 0
1108 /* A C expression whose value is RTL representing the address in a stack frame
1109 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
1110 an RTL expression for the address of the stack frame itself.
1112 If you don't define this macro, the default is to return the value of
1113 FRAMEADDR--that is, the stack frame address is also the address of the stack
1114 word that points to the previous frame. */
1115 #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) frv_dynamic_chain_address (FRAMEADDR)
1117 /* A C expression whose value is RTL representing the value of the return
1118 address for the frame COUNT steps up from the current frame, after the
1119 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
1120 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
1123 The value of the expression must always be the correct address when COUNT is
1124 zero, but may be `NULL_RTX' if there is not way to determine the return
1125 address of other frames. */
1126 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) frv_return_addr_rtx (COUNT, FRAMEADDR)
1128 #define RETURN_POINTER_REGNUM LR_REGNO
1130 /* A C expression whose value is RTL representing the location of the incoming
1131 return address at the beginning of any function, before the prologue. This
1132 RTL is either a `REG', indicating that the return value is saved in `REG',
1133 or a `MEM' representing a location in the stack.
1135 You only need to define this macro if you want to support call frame
1136 debugging information like that provided by DWARF 2. */
1137 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, RETURN_POINTER_REGNUM)
1140 /* Register That Address the Stack Frame. */
1142 /* The register number of the stack pointer register, which must also be a
1143 fixed register according to `FIXED_REGISTERS'. On most machines, the
1144 hardware determines which register this is. */
1145 #define STACK_POINTER_REGNUM (GPR_FIRST + 1)
1147 /* The register number of the frame pointer register, which is used to access
1148 automatic variables in the stack frame. On some machines, the hardware
1149 determines which register this is. On other machines, you can choose any
1150 register you wish for this purpose. */
1151 #define FRAME_POINTER_REGNUM (GPR_FIRST + 2)
1153 /* The register number of the arg pointer register, which is used to access the
1154 function's argument list. On some machines, this is the same as the frame
1155 pointer register. On some machines, the hardware determines which register
1156 this is. On other machines, you can choose any register you wish for this
1157 purpose. If this is not the same register as the frame pointer register,
1158 then you must mark it as a fixed register according to `FIXED_REGISTERS', or
1159 arrange to be able to eliminate it. */
1161 /* On frv this is a fake register that is eliminated in
1162 terms of either the frame pointer or stack pointer. */
1163 #define ARG_POINTER_REGNUM AP_FIRST
1165 /* Register numbers used for passing a function's static chain pointer. If
1166 register windows are used, the register number as seen by the called
1167 function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as
1168 seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers
1169 are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined.
1171 The static chain register need not be a fixed register.
1173 If the static chain is passed in memory, these macros should not be defined;
1174 instead, the next two macros should be defined. */
1175 #define STATIC_CHAIN_REGNUM (GPR_FIRST + 7)
1176 #define STATIC_CHAIN_INCOMING_REGNUM (GPR_FIRST + 7)
1179 /* Eliminating the Frame Pointer and the Arg Pointer. */
1181 /* If defined, this macro specifies a table of register pairs used to eliminate
1182 unneeded registers that point into the stack frame. If it is not defined,
1183 the only elimination attempted by the compiler is to replace references to
1184 the frame pointer with references to the stack pointer.
1186 The definition of this macro is a list of structure initializations, each of
1187 which specifies an original and replacement register.
1189 On some machines, the position of the argument pointer is not known until
1190 the compilation is completed. In such a case, a separate hard register must
1191 be used for the argument pointer. This register can be eliminated by
1192 replacing it with either the frame pointer or the argument pointer,
1193 depending on whether or not the frame pointer has been eliminated.
1195 In this case, you might specify:
1196 #define ELIMINABLE_REGS \
1197 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1198 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1199 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1201 Note that the elimination of the argument pointer with the stack pointer is
1202 specified first since that is the preferred elimination. */
1204 #define ELIMINABLE_REGS \
1206 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1207 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1208 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
1211 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1212 initial difference between the specified pair of registers. This macro must
1213 be defined if `ELIMINABLE_REGS' is defined. */
1215 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1216 (OFFSET) = frv_initial_elimination_offset (FROM, TO)
1219 /* Passing Function Arguments on the Stack. */
1221 /* If defined, the maximum amount of space required for outgoing arguments will
1222 be computed and placed into the variable
1223 `crtl->outgoing_args_size'. No space will be pushed onto the
1224 stack for each call; instead, the function prologue should increase the
1225 stack frame size by this amount.
1227 Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not
1229 #define ACCUMULATE_OUTGOING_ARGS 1
1232 /* The number of register assigned to holding function arguments. */
1234 #define FRV_NUM_ARG_REGS 6
1236 /* A C type for declaring a variable that is used as the first argument of
1237 `FUNCTION_ARG' and other related values. For some target machines, the type
1238 `int' suffices and can hold the number of bytes of argument so far.
1240 There is no need to record in `CUMULATIVE_ARGS' anything about the arguments
1241 that have been passed on the stack. The compiler has other variables to
1242 keep track of that. For target machines on which all arguments are passed
1243 on the stack, there is no need to store anything in `CUMULATIVE_ARGS';
1244 however, the data structure must exist and should not be empty, so use
1246 #define CUMULATIVE_ARGS int
1248 /* A C statement (sans semicolon) for initializing the variable CUM for the
1249 state at the beginning of the argument list. The variable has type
1250 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1251 of the function which will receive the args, or 0 if the args are to a
1252 compiler support library function. The value of INDIRECT is nonzero when
1253 processing an indirect call, for example a call through a function pointer.
1254 The value of INDIRECT is zero for a call to an explicitly named function, a
1255 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1256 arguments for the function being compiled.
1258 When processing a call to a compiler support library function, LIBNAME
1259 identifies which one. It is a `symbol_ref' rtx which contains the name of
1260 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1261 being processed. Thus, each time this macro is called, either LIBNAME or
1262 FNTYPE is nonzero, but never both of them at once. */
1264 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1265 frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, FNDECL, FALSE)
1267 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1268 arguments for the function being compiled. If this macro is undefined,
1269 `INIT_CUMULATIVE_ARGS' is used instead.
1271 The value passed for LIBNAME is always 0, since library routines with
1272 special calling conventions are never compiled with GCC. The argument
1273 LIBNAME exists for symmetry with `INIT_CUMULATIVE_ARGS'. */
1275 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1276 frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, NULL, TRUE)
1278 /* A C expression that is nonzero if REGNO is the number of a hard register in
1279 which function arguments are sometimes passed. This does *not* include
1280 implicit arguments such as the static chain and the structure-value address.
1281 On many machines, no registers can be used for this purpose since all
1282 function arguments are pushed on the stack. */
1283 #define FUNCTION_ARG_REGNO_P(REGNO) \
1284 ((REGNO) >= FIRST_ARG_REGNUM && ((REGNO) <= LAST_ARG_REGNUM))
1287 /* How Scalar Function Values are Returned. */
1289 /* The number of the hard register that is used to return a scalar value from a
1291 #define RETURN_VALUE_REGNUM (GPR_FIRST + 8)
1293 #define FUNCTION_VALUE_REGNO_P(REGNO) frv_function_value_regno_p (REGNO)
1296 /* How Large Values are Returned. */
1298 /* The number of the register that is used to pass the structure
1300 #define FRV_STRUCT_VALUE_REGNUM (GPR_FIRST + 3)
1303 /* Function Entry and Exit. */
1305 /* Define this macro as a C expression that is nonzero if the return
1306 instruction or the function epilogue ignores the value of the stack pointer;
1307 in other words, if it is safe to delete an instruction to adjust the stack
1308 pointer before a return from the function.
1310 Note that this macro's value is relevant only for functions for which frame
1311 pointers are maintained. It is never safe to delete a final stack
1312 adjustment in a function that has no frame pointer, and the compiler knows
1313 this regardless of `EXIT_IGNORE_STACK'. */
1314 #define EXIT_IGNORE_STACK 1
1316 /* Generating Code for Profiling. */
1318 /* A C statement or compound statement to output to FILE some assembler code to
1319 call the profiling subroutine `mcount'. Before calling, the assembler code
1320 must load the address of a counter variable into a register where `mcount'
1321 expects to find the address. The name of this variable is `LP' followed by
1322 the number LABELNO, so you would generate the name using `LP%d' in a
1325 The details of how the address should be passed to `mcount' are determined
1326 by your operating system environment, not by GCC. To figure them out,
1327 compile a small program for profiling using the system's installed C
1328 compiler and look at the assembler code that results.
1330 This declaration must be present, but it can be an abort if profiling is
1333 #define FUNCTION_PROFILER(FILE, LABELNO)
1335 /* Trampolines for Nested Functions. */
1337 /* A C expression for the size in bytes of the trampoline, as an integer. */
1338 #define TRAMPOLINE_SIZE frv_trampoline_size ()
1340 /* Alignment required for trampolines, in bits.
1342 If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for
1343 aligning trampolines. */
1344 #define TRAMPOLINE_ALIGNMENT (TARGET_FDPIC ? 64 : 32)
1346 /* Define this macro if trampolines need a special subroutine to do their work.
1347 The macro should expand to a series of `asm' statements which will be
1348 compiled with GCC. They go in a library function named
1349 `__transfer_from_trampoline'.
1351 If you need to avoid executing the ordinary prologue code of a compiled C
1352 function when you jump to the subroutine, you can do so by placing a special
1353 label of your own in the assembler code. Use one `asm' statement to
1354 generate an assembler label, and another to make the label global. Then
1355 trampolines can use that label to jump directly to your special assembler
1358 #ifdef __FRV_UNDERSCORE__
1359 #define TRAMPOLINE_TEMPLATE_NAME "___trampoline_template"
1361 #define TRAMPOLINE_TEMPLATE_NAME "__trampoline_template"
1364 #define Twrite _write
1367 #define TRANSFER_FROM_TRAMPOLINE \
1368 extern int Twrite (int, const void *, unsigned); \
1371 __trampoline_setup (short * addr, int size, int fnaddr, int sc) \
1373 extern short __trampoline_template[]; \
1374 short * to = addr; \
1375 short * from = &__trampoline_template[0]; \
1380 Twrite (2, "__trampoline_setup bad size\n", \
1381 sizeof ("__trampoline_setup bad size\n") - 1); \
1386 to[1] = (short)(fnaddr); \
1388 to[3] = (short)(sc); \
1390 to[5] = (short)(fnaddr >> 16); \
1392 to[7] = (short)(sc >> 16); \
1396 for (i = 0; i < 20; i++) \
1397 __asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \
1401 "\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \
1403 TRAMPOLINE_TEMPLATE_NAME ":\n" \
1404 "\tsetlos #0, gr6\n" /* jump register */ \
1405 "\tsetlos #0, gr7\n" /* static chain */ \
1406 "\tsethi #0, gr6\n" \
1407 "\tsethi #0, gr7\n" \
1408 "\tjmpl @(gr0,gr6)\n");
1410 #define TRANSFER_FROM_TRAMPOLINE \
1411 extern int Twrite (int, const void *, unsigned); \
1414 __trampoline_setup (addr, size, fnaddr, sc) \
1420 extern short __trampoline_template[]; \
1421 short * from = &__trampoline_template[0]; \
1423 short **desc = (short **)addr; \
1424 short * to = addr + 4; \
1428 Twrite (2, "__trampoline_setup bad size\n", \
1429 sizeof ("__trampoline_setup bad size\n") - 1); \
1433 /* Create a function descriptor with the address of the code below \
1434 and NULL as the FDPIC value. We don't need the real GOT value \
1435 here, since we don't use it, so we use NULL, that is just as \
1442 to[1] = (short)(fnaddr); \
1444 to[3] = (short)(sc); \
1446 to[5] = (short)(fnaddr >> 16); \
1448 to[7] = (short)(sc >> 16); \
1451 to[10] = from[10]; \
1452 to[11] = from[11]; \
1454 for (i = 0; i < size; i++) \
1455 __asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \
1459 "\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \
1461 TRAMPOLINE_TEMPLATE_NAME ":\n" \
1462 "\tsetlos #0, gr6\n" /* Jump register. */ \
1463 "\tsetlos #0, gr7\n" /* Static chain. */ \
1464 "\tsethi #0, gr6\n" \
1465 "\tsethi #0, gr7\n" \
1466 "\tldd @(gr6,gr0),gr14\n" \
1467 "\tjmpl @(gr14,gr0)\n" \
1472 /* Addressing Modes. */
1474 /* A number, the maximum number of registers that can appear in a valid memory
1475 address. Note that it is up to you to specify a value equal to the maximum
1476 number that `TARGET_LEGITIMATE_ADDRESS_P' would ever accept. */
1477 #define MAX_REGS_PER_ADDRESS 2
1479 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1480 use as a base register. For hard registers, it should always accept those
1481 which the hardware permits and reject the others. Whether the macro accepts
1482 or rejects pseudo registers must be controlled by `REG_OK_STRICT' as
1483 described above. This usually requires two variant definitions, of which
1484 `REG_OK_STRICT' controls the one actually used. */
1485 #ifdef REG_OK_STRICT
1486 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1488 #define REG_OK_FOR_BASE_P(X) GPR_AP_OR_PSEUDO_P (REGNO (X))
1491 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1492 use as an index register.
1494 The difference between an index register and a base register is that the
1495 index register may be scaled. If an address involves the sum of two
1496 registers, neither one of them scaled, then either one may be labeled the
1497 "base" and the other the "index"; but whichever labeling is used must fit
1498 the machine's constraints of which registers may serve in each capacity.
1499 The compiler will try both labelings, looking for one that is valid, and
1500 will reload one or both registers only if neither labeling works. */
1501 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1503 #define FIND_BASE_TERM frv_find_base_term
1505 /* A C expression that is nonzero if X is a legitimate constant for an
1506 immediate operand on the target machine. You can assume that X satisfies
1507 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
1508 definition for this macro on machines where anything `CONSTANT_P' is valid. */
1509 #define LEGITIMATE_CONSTANT_P(X) frv_legitimate_constant_p (X)
1511 /* The load-and-update commands allow pre-modification in addresses.
1512 The index has to be in a register. */
1513 #define HAVE_PRE_MODIFY_REG 1
1516 /* We define extra CC modes in frv-modes.def so we need a selector. */
1518 #define SELECT_CC_MODE frv_select_cc_mode
1520 /* A C expression whose value is one if it is always safe to reverse a
1521 comparison whose mode is MODE. If `SELECT_CC_MODE' can ever return MODE for
1522 a floating-point inequality comparison, then `REVERSIBLE_CC_MODE (MODE)'
1525 You need not define this macro if it would always returns zero or if the
1526 floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For
1527 example, here is the definition used on the SPARC, where floating-point
1528 inequality comparisons are always given `CCFPEmode':
1530 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */
1532 /* On frv, don't consider floating point comparisons to be reversible. In
1533 theory, fp equality comparisons can be reversible. */
1534 #define REVERSIBLE_CC_MODE(MODE) \
1535 ((MODE) == CCmode || (MODE) == CC_UNSmode || (MODE) == CC_NZmode)
1537 /* Frv CCR_MODE's are not reversible. */
1538 #define REVERSE_CONDEXEC_PREDICATES_P(x,y) 0
1541 /* Describing Relative Costs of Operations. */
1543 /* A C expression for the cost of a branch instruction. A value of 1 is the
1544 default; other values are interpreted relative to that. */
1545 #define BRANCH_COST(speed_p, predictable_p) frv_branch_cost_int
1547 /* Define this macro as a C expression which is nonzero if accessing less than
1548 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1549 word of memory, i.e., if such access require more than one instruction or if
1550 there is no difference in cost between byte and (aligned) word loads.
1552 When this macro is not defined, the compiler will access a field by finding
1553 the smallest containing object; when it is defined, a fullword load will be
1554 used if alignment permits. Unless bytes accesses are faster than word
1555 accesses, using word accesses is preferable since it may eliminate
1556 subsequent memory access if subsequent accesses occur to other fields in the
1557 same word of the structure, but to different bytes. */
1558 #define SLOW_BYTE_ACCESS 1
1560 /* Define this macro if it is as good or better to call a constant function
1561 address than to call an address kept in a register. */
1562 #define NO_FUNCTION_CSE
1565 /* Dividing the output into sections. */
1567 /* A C expression whose value is a string containing the assembler operation
1568 that should precede instructions and read-only data. Normally `".text"' is
1570 #define TEXT_SECTION_ASM_OP "\t.text"
1572 /* A C expression whose value is a string containing the assembler operation to
1573 identify the following data as writable initialized data. Normally
1574 `".data"' is right. */
1575 #define DATA_SECTION_ASM_OP "\t.data"
1577 #define BSS_SECTION_ASM_OP "\t.section .bss,\"aw\""
1579 /* Short Data Support */
1580 #define SDATA_SECTION_ASM_OP "\t.section .sdata,\"aw\""
1582 #undef INIT_SECTION_ASM_OP
1583 #undef FINI_SECTION_ASM_OP
1584 #define INIT_SECTION_ASM_OP "\t.section .init,\"ax\""
1585 #define FINI_SECTION_ASM_OP "\t.section .fini,\"ax\""
1587 #undef CTORS_SECTION_ASM_OP
1588 #undef DTORS_SECTION_ASM_OP
1589 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
1590 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
1592 /* A C expression whose value is a string containing the assembler operation to
1593 switch to the fixup section that records all initialized pointers in a -fpic
1594 program so they can be changed program startup time if the program is loaded
1595 at a different address than linked for. */
1596 #define FIXUP_SECTION_ASM_OP "\t.section .rofixup,\"a\""
1598 /* Position Independent Code. */
1600 /* A C expression that is nonzero if X is a legitimate immediate operand on the
1601 target machine when generating position independent code. You can assume
1602 that X satisfies `CONSTANT_P', so you need not check this. You can also
1603 assume FLAG_PIC is true, so you need not check it either. You need not
1604 define this macro if all constants (including `SYMBOL_REF') can be immediate
1605 operands when generating position independent code. */
1606 #define LEGITIMATE_PIC_OPERAND_P(X) \
1607 ( GET_CODE (X) == CONST_INT \
1608 || GET_CODE (X) == CONST_DOUBLE \
1609 || (GET_CODE (X) == HIGH && GET_CODE (XEXP (X, 0)) == CONST_INT) \
1610 || got12_operand (X, VOIDmode)) \
1613 /* The Overall Framework of an Assembler File. */
1615 /* A C string constant describing how to begin a comment in the target
1616 assembler language. The compiler assumes that the comment will end at the
1618 #define ASM_COMMENT_START ";"
1620 /* A C string constant for text to be output before each `asm' statement or
1621 group of consecutive ones. Normally this is `"#APP"', which is a comment
1622 that has no effect on most assemblers but tells the GNU assembler that it
1623 must check the lines that follow for all valid assembler constructs. */
1624 #define ASM_APP_ON "#APP\n"
1626 /* A C string constant for text to be output after each `asm' statement or
1627 group of consecutive ones. Normally this is `"#NO_APP"', which tells the
1628 GNU assembler to resume making the time-saving assumptions that are valid
1629 for ordinary compiler output. */
1630 #define ASM_APP_OFF "#NO_APP\n"
1633 /* Output of Data. */
1635 /* This is how to output a label to dwarf/dwarf2. */
1636 #define ASM_OUTPUT_DWARF_ADDR(STREAM, LABEL) \
1638 fprintf (STREAM, "\t.picptr\t"); \
1639 assemble_name (STREAM, LABEL); \
1642 /* Whether to emit the gas specific dwarf2 line number support. */
1643 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DEBUG_LOC)
1645 /* Output of Uninitialized Variables. */
1647 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1648 assembler definition of a local-common-label named NAME whose size is SIZE
1649 bytes. The variable ROUNDED is the size rounded up to whatever alignment
1652 Use the expression `assemble_name (STREAM, NAME)' to output the name itself;
1653 before and after that, output the additional assembler syntax for defining
1654 the name, and a newline.
1656 This macro controls how the assembler definitions of uninitialized static
1657 variables are output. */
1658 #undef ASM_OUTPUT_LOCAL
1660 #undef ASM_OUTPUT_ALIGNED_LOCAL
1662 /* This is for final.c, because it is used by ASM_DECLARE_OBJECT_NAME. */
1663 extern int size_directive_output;
1665 /* Like `ASM_OUTPUT_ALIGNED_LOCAL' except that it takes an additional
1666 parameter - the DECL of variable to be output, if there is one.
1667 This macro can be called with DECL == NULL_TREE. If you define
1668 this macro, it is used in place of `ASM_OUTPUT_LOCAL' and
1669 `ASM_OUTPUT_ALIGNED_LOCAL', and gives you more flexibility in
1670 handling the destination of the variable. */
1671 #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
1672 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \
1674 if ((SIZE) > 0 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
1675 switch_to_section (get_named_section (NULL, ".sbss", 0)); \
1677 switch_to_section (bss_section); \
1678 ASM_OUTPUT_ALIGN (STREAM, floor_log2 ((ALIGN) / BITS_PER_UNIT)); \
1679 ASM_DECLARE_OBJECT_NAME (STREAM, NAME, DECL); \
1680 ASM_OUTPUT_SKIP (STREAM, (SIZE) ? (SIZE) : 1); \
1684 /* Output and Generation of Labels. */
1686 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1687 assembler definition of a label named NAME. Use the expression
1688 `assemble_name (STREAM, NAME)' to output the name itself; before and after
1689 that, output the additional assembler syntax for defining the name, and a
1691 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1693 assemble_name (STREAM, NAME); \
1694 fputs (":\n", STREAM); \
1697 /* Globalizing directive for a label. */
1698 #define GLOBAL_ASM_OP "\t.globl "
1700 #undef ASM_GENERATE_INTERNAL_LABEL
1701 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1703 sprintf (LABEL, "*.%s%ld", PREFIX, (long)NUM); \
1707 /* Macros Controlling Initialization Routines. */
1709 #undef INIT_SECTION_ASM_OP
1711 /* If defined, `main' will call `__main' despite the presence of
1712 `INIT_SECTION_ASM_OP'. This macro should be defined for systems where the
1713 init section is not actually run automatically, but is still useful for
1714 collecting the lists of constructors and destructors. */
1715 #define INVOKE__main
1717 /* Output of Assembler Instructions. */
1719 /* A C initializer containing the assembler's names for the machine registers,
1720 each one as a C string constant. This is what translates register numbers
1721 in the compiler into assembler language. */
1722 #define REGISTER_NAMES \
1724 "gr0", "sp", "fp", "gr3", "gr4", "gr5", "gr6", "gr7", \
1725 "gr8", "gr9", "gr10", "gr11", "gr12", "gr13", "gr14", "gr15", \
1726 "gr16", "gr17", "gr18", "gr19", "gr20", "gr21", "gr22", "gr23", \
1727 "gr24", "gr25", "gr26", "gr27", "gr28", "gr29", "gr30", "gr31", \
1728 "gr32", "gr33", "gr34", "gr35", "gr36", "gr37", "gr38", "gr39", \
1729 "gr40", "gr41", "gr42", "gr43", "gr44", "gr45", "gr46", "gr47", \
1730 "gr48", "gr49", "gr50", "gr51", "gr52", "gr53", "gr54", "gr55", \
1731 "gr56", "gr57", "gr58", "gr59", "gr60", "gr61", "gr62", "gr63", \
1733 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1734 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
1735 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
1736 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
1737 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
1738 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
1739 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
1740 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
1742 "fcc0", "fcc1", "fcc2", "fcc3", "icc0", "icc1", "icc2", "icc3", \
1743 "cc0", "cc1", "cc2", "cc3", "cc4", "cc5", "cc6", "cc7", \
1744 "acc0", "acc1", "acc2", "acc3", "acc4", "acc5", "acc6", "acc7", \
1745 "acc8", "acc9", "acc10", "acc11", \
1746 "accg0","accg1","accg2","accg3","accg4","accg5","accg6","accg7", \
1747 "accg8", "accg9", "accg10", "accg11", \
1748 "ap", "lr", "lcr", "iacc0h", "iacc0l" \
1751 /* Define this macro if you are using an unusual assembler that
1752 requires different names for the machine instructions.
1754 The definition is a C statement or statements which output an
1755 assembler instruction opcode to the stdio stream STREAM. The
1756 macro-operand PTR is a variable of type `char *' which points to
1757 the opcode name in its "internal" form--the form that is written
1758 in the machine description. The definition should output the
1759 opcode name to STREAM, performing any translation you desire, and
1760 increment the variable PTR to point at the end of the opcode so
1761 that it will not be output twice.
1763 In fact, your macro definition may process less than the entire
1764 opcode name, or more than the opcode name; but if you want to
1765 process text that includes `%'-sequences to substitute operands,
1766 you must take care of the substitution yourself. Just be sure to
1767 increment PTR over whatever text should not be output normally.
1769 If you need to look at the operand values, they can be found as the
1770 elements of `recog_operand'.
1772 If the macro definition does nothing, the instruction is output in
1775 #define ASM_OUTPUT_OPCODE(STREAM, PTR)\
1776 (PTR) = frv_asm_output_opcode (STREAM, PTR)
1778 /* If defined, a C statement to be executed just prior to the output
1779 of assembler code for INSN, to modify the extracted operands so
1780 they will be output differently.
1782 Here the argument OPVEC is the vector containing the operands
1783 extracted from INSN, and NOPERANDS is the number of elements of
1784 the vector which contain meaningful data for this insn. The
1785 contents of this vector are what will be used to convert the insn
1786 template into assembler code, so you can change the assembler
1787 output by changing the contents of the vector.
1789 This macro is useful when various assembler syntaxes share a single
1790 file of instruction patterns; by defining this macro differently,
1791 you can cause a large class of instructions to be output
1792 differently (such as with rearranged operands). Naturally,
1793 variations in assembler syntax affecting individual insn patterns
1794 ought to be handled by writing conditional output routines in
1797 If this macro is not defined, it is equivalent to a null statement. */
1799 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)\
1800 frv_final_prescan_insn (INSN, OPVEC, NOPERANDS)
1802 #undef USER_LABEL_PREFIX
1803 #define USER_LABEL_PREFIX ""
1804 #define REGISTER_PREFIX ""
1805 #define LOCAL_LABEL_PREFIX "."
1806 #define IMMEDIATE_PREFIX "#"
1809 /* Output of dispatch tables. */
1811 /* This macro should be provided on machines where the addresses in a dispatch
1812 table are relative to the table's own address.
1814 The definition should be a C statement to output to the stdio stream STREAM
1815 an assembler pseudo-instruction to generate a difference between two labels.
1816 VALUE and REL are the numbers of two internal labels. The definitions of
1817 these labels are output using `(*targetm.asm_out.internal_label)', and they must be
1818 printed in the same way here. For example,
1820 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */
1821 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1822 fprintf (STREAM, "\t.word .L%d-.L%d\n", VALUE, REL)
1824 /* This macro should be provided on machines where the addresses in a dispatch
1827 The definition should be a C statement to output to the stdio stream STREAM
1828 an assembler pseudo-instruction to generate a reference to a label. VALUE
1829 is the number of an internal label whose definition is output using
1830 `(*targetm.asm_out.internal_label)'. For example,
1832 fprintf (STREAM, "\t.word L%d\n", VALUE) */
1833 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1834 fprintf (STREAM, "\t.word .L%d\n", VALUE)
1836 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1838 /* Assembler Commands for Exception Regions. */
1840 /* Define this macro to 0 if your target supports DWARF 2 frame unwind
1841 information, but it does not yet work with exception handling. Otherwise,
1842 if your target supports this information (if it defines
1843 `INCOMING_RETURN_ADDR_RTX' and either `UNALIGNED_INT_ASM_OP' or
1844 `OBJECT_FORMAT_ELF'), GCC will provide a default definition of 1.
1846 If this macro is defined to 1, the DWARF 2 unwinder will be the default
1847 exception handling mechanism; otherwise, setjmp/longjmp will be used by
1850 If this macro is defined to anything, the DWARF 2 unwinder will be used
1851 instead of inline unwinders and __unwind_function in the non-setjmp case. */
1852 #define DWARF2_UNWIND_INFO 1
1854 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
1856 /* Assembler Commands for Alignment. */
1858 #undef ASM_OUTPUT_SKIP
1859 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1860 fprintf (STREAM, "\t.zero\t%u\n", (int)(NBYTES))
1862 /* A C statement to output to the stdio stream STREAM an assembler command to
1863 advance the location counter to a multiple of 2 to the POWER bytes. POWER
1864 will be a C expression of type `int'. */
1865 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1866 fprintf ((STREAM), "\t.p2align %d\n", (POWER))
1868 /* Inside the text section, align with unpacked nops rather than zeros. */
1869 #define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \
1870 fprintf ((STREAM), "\t.p2alignl %d,0x80880000\n", (POWER))
1872 /* Macros Affecting all Debug Formats. */
1874 /* A C expression that returns the DBX register number for the compiler
1875 register number REGNO. In simple cases, the value of this expression may be
1876 REGNO itself. But sometimes there are some registers that the compiler
1877 knows about and DBX does not, or vice versa. In such cases, some register
1878 may need to have one number in the compiler and another for DBX.
1880 If two registers have consecutive numbers inside GCC, and they can be
1881 used as a pair to hold a multiword value, then they *must* have consecutive
1882 numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers
1883 will be unable to access such a pair, because they expect register pairs to
1884 be consecutive in their own numbering scheme.
1886 If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not
1887 preserve register pairs, then what you must do instead is redefine the
1888 actual register numbering scheme.
1890 This declaration is required. */
1891 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1893 #undef PREFERRED_DEBUGGING_TYPE
1894 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1896 /* Miscellaneous Parameters. */
1898 /* An alias for a machine mode name. This is the machine mode that elements of
1899 a jump-table should have. */
1900 #define CASE_VECTOR_MODE SImode
1902 /* Define this macro if operations between registers with integral mode smaller
1903 than a word are always performed on the entire register. Most RISC machines
1904 have this property and most CISC machines do not. */
1905 #define WORD_REGISTER_OPERATIONS
1907 /* Define this macro to be a C expression indicating when insns that read
1908 memory in MODE, an integral mode narrower than a word, set the bits outside
1909 of MODE to be either the sign-extension or the zero-extension of the data
1910 read. Return `SIGN_EXTEND' for values of MODE for which the insn
1911 sign-extends, `ZERO_EXTEND' for which it zero-extends, and `UNKNOWN' for other
1914 This macro is not called with MODE non-integral or with a width greater than
1915 or equal to `BITS_PER_WORD', so you may return any value in this case. Do
1916 not define this macro if it would always return `UNKNOWN'. On machines where
1917 this macro is defined, you will normally define it as the constant
1918 `SIGN_EXTEND' or `ZERO_EXTEND'. */
1919 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1921 /* Define if loading short immediate values into registers sign extends. */
1922 #define SHORT_IMMEDIATES_SIGN_EXTEND
1924 /* The maximum number of bytes that a single instruction can move quickly from
1925 memory to memory. */
1928 /* A C expression which is nonzero if on this machine it is safe to "convert"
1929 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
1930 than INPREC) by merely operating on it as if it had only OUTPREC bits.
1932 On many machines, this expression can be 1.
1934 When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for
1935 which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the
1936 case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve
1938 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1940 /* An alias for the machine mode for pointers. On most machines, define this
1941 to be the integer mode corresponding to the width of a hardware pointer;
1942 `SImode' on 32-bit machine or `DImode' on 64-bit machines. On some machines
1943 you must define this to be one of the partial integer modes, such as
1946 The width of `Pmode' must be at least as large as the value of
1947 `POINTER_SIZE'. If it is not equal, you must define the macro
1948 `POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to `Pmode'. */
1949 #define Pmode SImode
1951 /* An alias for the machine mode used for memory references to functions being
1952 called, in `call' RTL expressions. On most machines this should be
1954 #define FUNCTION_MODE QImode
1956 /* A C expression for the maximum number of instructions to execute via
1957 conditional execution instructions instead of a branch. A value of
1958 BRANCH_COST+1 is the default if the machine does not use
1959 cc0, and 1 if it does use cc0. */
1960 #define MAX_CONDITIONAL_EXECUTE frv_condexec_insns
1962 /* A C expression to modify the code described by the conditional if
1963 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
1964 FALSE_EXPR for converting if-then and if-then-else code to conditional
1965 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
1966 tests cannot be converted. */
1967 #define IFCVT_MODIFY_TESTS(CE_INFO, TRUE_EXPR, FALSE_EXPR) \
1968 frv_ifcvt_modify_tests (CE_INFO, &TRUE_EXPR, &FALSE_EXPR)
1970 /* A C expression to modify the code described by the conditional if
1971 information CE_INFO, for the basic block BB, possibly updating the tests in
1972 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
1973 if-then-else code to conditional instructions. OLD_TRUE and OLD_FALSE are
1974 the previous tests. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if
1975 the tests cannot be converted. */
1976 #define IFCVT_MODIFY_MULTIPLE_TESTS(CE_INFO, BB, TRUE_EXPR, FALSE_EXPR) \
1977 frv_ifcvt_modify_multiple_tests (CE_INFO, BB, &TRUE_EXPR, &FALSE_EXPR)
1979 /* A C expression to modify the code described by the conditional if
1980 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
1981 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
1982 insn cannot be converted to be executed conditionally. */
1983 #define IFCVT_MODIFY_INSN(CE_INFO, PATTERN, INSN) \
1984 (PATTERN) = frv_ifcvt_modify_insn (CE_INFO, PATTERN, INSN)
1986 /* A C expression to perform any final machine dependent modifications in
1987 converting code to conditional execution in the code described by the
1988 conditional if information CE_INFO. */
1989 #define IFCVT_MODIFY_FINAL(CE_INFO) frv_ifcvt_modify_final (CE_INFO)
1991 /* A C expression to cancel any machine dependent modifications in converting
1992 code to conditional execution in the code described by the conditional if
1993 information CE_INFO. */
1994 #define IFCVT_MODIFY_CANCEL(CE_INFO) frv_ifcvt_modify_cancel (CE_INFO)
1996 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
1997 #define IFCVT_INIT_EXTRA_FIELDS(CE_INFO) frv_ifcvt_init_extra_fields (CE_INFO)
1999 /* The definition of the following macro results in that the 2nd jump
2000 optimization (after the 2nd insn scheduling) is minimal. It is
2001 necessary to define when start cycle marks of insns (TImode is used
2002 for this) is used for VLIW insn packing. Some jump optimizations
2003 make such marks invalid. These marks are corrected for some
2004 (minimal) optimizations. ??? Probably the macro is temporary.
2005 Final solution could making the 2nd jump optimizations before the
2006 2nd instruction scheduling or corrections of the marks for all jump
2007 optimizations. Although some jump optimizations are actually
2008 deoptimizations for VLIW (super-scalar) processors. */
2010 #define MINIMAL_SECOND_JUMP_OPTIMIZATION
2013 /* If the following macro is defined and nonzero and deterministic
2014 finite state automata are used for pipeline hazard recognition, we
2015 will try to exchange insns in queue ready to improve the schedule.
2016 The more macro value, the more tries will be made. */
2017 #define FIRST_CYCLE_MULTIPASS_SCHEDULING 1
2019 /* The following macro is used only when value of
2020 FIRST_CYCLE_MULTIPASS_SCHEDULING is nonzero. The more macro value,
2021 the more tries will be made to choose better schedule. If the
2022 macro value is zero or negative there will be no multi-pass
2024 #define FIRST_CYCLE_MULTIPASS_SCHEDULING_LOOKAHEAD frv_sched_lookahead
2035 FRV_BUILTIN_MADDHSS,
2036 FRV_BUILTIN_MADDHUS,
2037 FRV_BUILTIN_MSUBHSS,
2038 FRV_BUILTIN_MSUBHUS,
2040 FRV_BUILTIN_MQADDHSS,
2041 FRV_BUILTIN_MQADDHUS,
2042 FRV_BUILTIN_MQSUBHSS,
2043 FRV_BUILTIN_MQSUBHUS,
2044 FRV_BUILTIN_MUNPACKH,
2045 FRV_BUILTIN_MDPACKH,
2056 FRV_BUILTIN_MEXPDHW,
2057 FRV_BUILTIN_MEXPDHD,
2060 FRV_BUILTIN_MMULXHS,
2061 FRV_BUILTIN_MMULXHU,
2066 FRV_BUILTIN_MQMULHS,
2067 FRV_BUILTIN_MQMULHU,
2068 FRV_BUILTIN_MQMULXHU,
2069 FRV_BUILTIN_MQMULXHS,
2070 FRV_BUILTIN_MQMACHS,
2071 FRV_BUILTIN_MQMACHU,
2076 FRV_BUILTIN_MQCPXRS,
2077 FRV_BUILTIN_MQCPXRU,
2078 FRV_BUILTIN_MQCPXIS,
2079 FRV_BUILTIN_MQCPXIU,
2083 FRV_BUILTIN_MWTACCG,
2085 FRV_BUILTIN_MRDACCG,
2087 FRV_BUILTIN_MCLRACC,
2088 FRV_BUILTIN_MCLRACCA,
2089 FRV_BUILTIN_MDUNPACKH,
2091 FRV_BUILTIN_MQXMACHS,
2092 FRV_BUILTIN_MQXMACXHS,
2093 FRV_BUILTIN_MQMACXHS,
2094 FRV_BUILTIN_MADDACCS,
2095 FRV_BUILTIN_MSUBACCS,
2096 FRV_BUILTIN_MASACCS,
2097 FRV_BUILTIN_MDADDACCS,
2098 FRV_BUILTIN_MDSUBACCS,
2099 FRV_BUILTIN_MDASACCS,
2101 FRV_BUILTIN_MDROTLI,
2104 FRV_BUILTIN_MDCUTSSI,
2105 FRV_BUILTIN_MQSATHS,
2106 FRV_BUILTIN_MQLCLRHS,
2107 FRV_BUILTIN_MQLMTHS,
2108 FRV_BUILTIN_MQSLLHI,
2109 FRV_BUILTIN_MQSRAHI,
2110 FRV_BUILTIN_MHSETLOS,
2111 FRV_BUILTIN_MHSETLOH,
2112 FRV_BUILTIN_MHSETHIS,
2113 FRV_BUILTIN_MHSETHIH,
2114 FRV_BUILTIN_MHDSETS,
2115 FRV_BUILTIN_MHDSETH,
2118 FRV_BUILTIN_PREFETCH0,
2119 FRV_BUILTIN_PREFETCH,
2127 FRV_BUILTIN_IACCreadll,
2128 FRV_BUILTIN_IACCreadl,
2129 FRV_BUILTIN_IACCsetll,
2130 FRV_BUILTIN_IACCsetl,
2137 FRV_BUILTIN_WRITE16,
2138 FRV_BUILTIN_WRITE32,
2141 #define FRV_BUILTIN_FIRST_NONMEDIA FRV_BUILTIN_SMUL
2143 /* Enable prototypes on the call rtl functions. */
2144 #define MD_CALL_PROTOTYPES 1
2146 #define CPU_UNITS_QUERY 1
2148 #ifdef __FRV_FDPIC__
2149 #define CRT_GET_RFIB_DATA(dbase) \
2150 ({ extern void *_GLOBAL_OFFSET_TABLE_; (dbase) = &_GLOBAL_OFFSET_TABLE_; })
2153 #endif /* __FRV_H__ */
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