1 /* Target macros for the FRV port of GCC.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009,
4 Free Software Foundation, Inc.
5 Contributed by Red Hat Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 /* Frv general purpose macros. */
27 /* Align an address. */
28 #define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1))
30 /* Driver configuration. */
32 /* -fpic and -fPIC used to imply the -mlibrary-pic multilib, but with
33 FDPIC which multilib to use depends on whether FDPIC is in use or
34 not. The trick we use is to introduce -multilib-library-pic as a
35 pseudo-flag that selects the library-pic multilib, and map fpic
36 and fPIC to it only if fdpic is not selected. Also, if fdpic is
37 selected and no PIC/PIE options are present, we imply -fPIE.
38 Otherwise, if -fpic or -fPIC are enabled and we're optimizing for
39 speed, or if we have -On with n>=3, enable inlining of PLTs. As
40 for -mgprel-ro, we want to enable it by default, but not for -fpic or
43 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS \
45 %{!mhard-float:-msoft-float}\
46 %{!mmedia:-mno-media}}\
47 %{!mfdpic:%{fpic|fPIC: -multilib-library-pic}}\
48 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\
49 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fPIE}}}}}}}} \
50 %{!mno-inline-plt:%{O*:%{!O0:%{!Os:%{fpic|fPIC:-minline-plt} \
51 %{!fpic:%{!fPIC:%{!O:%{!O1:%{!O2:-minline-plt}}}}}}}}} \
52 %{!mno-gprel-ro:%{!fpic:%{!fpie:-mgprel-ro}}}} \
54 #ifndef SUBTARGET_DRIVER_SELF_SPECS
55 # define SUBTARGET_DRIVER_SELF_SPECS
65 %{msoft-float} %{mhard-float} \
66 %{mdword} %{mno-dword} \
67 %{mdouble} %{mno-double} \
68 %{mmedia} %{mno-media} \
69 %{mmuladd} %{mno-muladd} \
70 %{mpack} %{mno-pack} \
71 %{mno-fdpic:-mnopic} %{mfdpic} \
72 %{fpic|fpie: -mpic} %{fPIC|fPIE: -mPIC} %{mlibrary-pic}}"
75 #define STARTFILE_SPEC "crt0%O%s frvbegin%O%s"
78 #define ENDFILE_SPEC "frvend%O%s"
81 #define MASK_DEFAULT_FRV \
88 #define MASK_DEFAULT_FR500 \
89 (MASK_MEDIA | MASK_DWORD | MASK_PACK)
91 #define MASK_DEFAULT_FR550 \
92 (MASK_MEDIA | MASK_DWORD | MASK_PACK)
94 #define MASK_DEFAULT_FR450 \
102 #define MASK_DEFAULT_FR400 \
111 #define MASK_DEFAULT_SIMPLE \
112 (MASK_GPR_32 | MASK_SOFT_FLOAT)
114 /* A C string constant that tells the GCC driver program options to pass to
115 `cc1'. It can also specify how to translate options you give to GCC into
116 options for GCC to pass to the `cc1'.
118 Do not define this macro if it does not need to do anything. */
119 /* For ABI compliance, we need to put bss data into the normal data section. */
120 #define CC1_SPEC "%{G*}"
125 %{mfdpic:-melf32frvfd -z text} \
126 %{static:-dn -Bstatic} \
127 %{shared:-Bdynamic} \
128 %{symbolic:-Bsymbolic} \
132 #define LIB_SPEC "--start-group -lc -lsim --end-group"
135 #define CPU_TYPE FRV_CPU_FR500
138 /* Run-time target specifications */
140 #define TARGET_CPU_CPP_BUILTINS() \
145 builtin_define ("__frv__"); \
146 builtin_assert ("cpu=frv"); \
147 builtin_assert ("machine=frv"); \
149 issue_rate = frv_issue_rate (); \
150 if (issue_rate > 1) \
151 builtin_define_with_int_value ("__FRV_VLIW__", issue_rate); \
152 builtin_define_with_int_value ("__FRV_GPR__", NUM_GPRS); \
153 builtin_define_with_int_value ("__FRV_FPR__", NUM_FPRS); \
154 builtin_define_with_int_value ("__FRV_ACC__", NUM_ACCS); \
156 switch (frv_cpu_type) \
158 case FRV_CPU_GENERIC: \
159 builtin_define ("__CPU_GENERIC__"); \
161 case FRV_CPU_FR550: \
162 builtin_define ("__CPU_FR550__"); \
164 case FRV_CPU_FR500: \
165 case FRV_CPU_TOMCAT: \
166 builtin_define ("__CPU_FR500__"); \
168 case FRV_CPU_FR450: \
169 builtin_define ("__CPU_FR450__"); \
171 case FRV_CPU_FR405: \
172 builtin_define ("__CPU_FR405__"); \
174 case FRV_CPU_FR400: \
175 builtin_define ("__CPU_FR400__"); \
177 case FRV_CPU_FR300: \
178 case FRV_CPU_SIMPLE: \
179 builtin_define ("__CPU_FR300__"); \
183 if (TARGET_HARD_FLOAT) \
184 builtin_define ("__FRV_HARD_FLOAT__"); \
186 builtin_define ("__FRV_DWORD__"); \
188 builtin_define ("__FRV_FDPIC__"); \
189 if (flag_leading_underscore > 0) \
190 builtin_define ("__FRV_UNDERSCORE__"); \
195 #define TARGET_HAS_FPRS (TARGET_HARD_FLOAT || TARGET_MEDIA)
197 #define NUM_GPRS (TARGET_GPR_32? 32 : 64)
198 #define NUM_FPRS (!TARGET_HAS_FPRS? 0 : TARGET_FPR_32? 32 : 64)
199 #define NUM_ACCS (!TARGET_MEDIA? 0 : TARGET_ACC_4? 4 : 8)
201 /* X is a valid accumulator number if (X & ACC_MASK) == X. */
205 : frv_cpu_type == FRV_CPU_FR450 ? 11 \
208 /* Macros to identify the blend of media instructions available. Revision 1
209 is the one found on the FR500. Revision 2 includes the changes made for
212 Treat the generic processor as a revision 1 machine for now, for
213 compatibility with earlier releases. */
215 #define TARGET_MEDIA_REV1 \
217 && (frv_cpu_type == FRV_CPU_GENERIC \
218 || frv_cpu_type == FRV_CPU_FR500))
220 #define TARGET_MEDIA_REV2 \
222 && (frv_cpu_type == FRV_CPU_FR400 \
223 || frv_cpu_type == FRV_CPU_FR405 \
224 || frv_cpu_type == FRV_CPU_FR450 \
225 || frv_cpu_type == FRV_CPU_FR550))
227 #define TARGET_MEDIA_FR450 \
228 (frv_cpu_type == FRV_CPU_FR450)
230 #define TARGET_FR500_FR550_BUILTINS \
231 (frv_cpu_type == FRV_CPU_FR500 \
232 || frv_cpu_type == FRV_CPU_FR550)
234 #define TARGET_FR405_BUILTINS \
235 (frv_cpu_type == FRV_CPU_FR405 \
236 || frv_cpu_type == FRV_CPU_FR450)
239 #define HAVE_AS_TLS 0
242 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_ALIGN_LABELS ? 3 : 0)
244 /* Small Data Area Support. */
245 /* Maximum size of variables that go in .sdata/.sbss.
246 The -msdata=foo switch also controls how small variables are handled. */
247 #ifndef SDATA_DEFAULT_SIZE
248 #define SDATA_DEFAULT_SIZE 8
254 /* Define this macro to have the value 1 if the most significant bit in a byte
255 has the lowest number; otherwise define it to have the value zero. This
256 means that bit-field instructions count from the most significant bit. If
257 the machine has no bit-field instructions, then this must still be defined,
258 but it doesn't matter which value it is defined to. This macro need not be
261 This macro does not affect the way structure fields are packed into bytes or
262 words; that is controlled by `BYTES_BIG_ENDIAN'. */
263 #define BITS_BIG_ENDIAN 1
265 /* Define this macro to have the value 1 if the most significant byte in a word
266 has the lowest number. This macro need not be a constant. */
267 #define BYTES_BIG_ENDIAN 1
269 /* Define this macro to have the value 1 if, in a multiword object, the most
270 significant word has the lowest number. This applies to both memory
271 locations and registers; GCC fundamentally assumes that the order of
272 words in memory is the same as the order in registers. This macro need not
274 #define WORDS_BIG_ENDIAN 1
276 /* Number of storage units in a word; normally 4. */
277 #define UNITS_PER_WORD 4
279 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
280 which has the specified mode and signedness is to be stored in a register.
281 This macro is only called when TYPE is a scalar type.
283 On most RISC machines, which only have operations that operate on a full
284 register, define this macro to set M to `word_mode' if M is an integer mode
285 narrower than `BITS_PER_WORD'. In most cases, only integer modes should be
286 widened because wider-precision floating-point operations are usually more
287 expensive than their narrower counterparts.
289 For most machines, the macro definition does not change UNSIGNEDP. However,
290 some machines, have instructions that preferentially handle either signed or
291 unsigned quantities of certain modes. For example, on the DEC Alpha, 32-bit
292 loads from memory and 32-bit add instructions sign-extend the result to 64
293 bits. On such machines, set UNSIGNEDP according to which kind of extension
296 Do not define this macro if it would never modify MODE. */
297 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
300 if (GET_MODE_CLASS (MODE) == MODE_INT \
301 && GET_MODE_SIZE (MODE) < 4) \
306 /* Normal alignment required for function parameters on the stack, in bits.
307 All stack parameters receive at least this much alignment regardless of data
308 type. On most machines, this is the same as the size of an integer. */
309 #define PARM_BOUNDARY 32
311 /* Define this macro if you wish to preserve a certain alignment for the stack
312 pointer. The definition is a C expression for the desired alignment
315 If `PUSH_ROUNDING' is not defined, the stack will always be aligned to the
316 specified boundary. If `PUSH_ROUNDING' is defined and specifies a less
317 strict alignment than `STACK_BOUNDARY', the stack may be momentarily
318 unaligned while pushing arguments. */
319 #define STACK_BOUNDARY 64
321 /* Alignment required for a function entry point, in bits. */
322 #define FUNCTION_BOUNDARY 128
324 /* Biggest alignment that any data type can require on this machine,
326 #define BIGGEST_ALIGNMENT 64
328 /* @@@ A hack, needed because libobjc wants to use ADJUST_FIELD_ALIGN for
330 #ifdef IN_TARGET_LIBS
331 #define BIGGEST_FIELD_ALIGNMENT 64
333 /* An expression for the alignment of a structure field FIELD if the
334 alignment computed in the usual way is COMPUTED. GCC uses this
335 value instead of the value in `BIGGEST_ALIGNMENT' or
336 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
337 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
338 frv_adjust_field_align (FIELD, COMPUTED)
341 /* If defined, a C expression to compute the alignment for a static variable.
342 TYPE is the data type, and ALIGN is the alignment that the object
343 would ordinarily have. The value of this macro is used instead of that
344 alignment to align the object.
346 If this macro is not defined, then ALIGN is used.
348 One use of this macro is to increase alignment of medium-size data to make
349 it all fit in fewer cache lines. Another is to cause character arrays to be
350 word-aligned so that `strcpy' calls that copy constants to character arrays
351 can be done inline. */
352 #define DATA_ALIGNMENT(TYPE, ALIGN) \
353 (TREE_CODE (TYPE) == ARRAY_TYPE \
354 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
355 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
357 /* If defined, a C expression to compute the alignment given to a constant that
358 is being placed in memory. CONSTANT is the constant and ALIGN is the
359 alignment that the object would ordinarily have. The value of this macro is
360 used instead of that alignment to align the object.
362 If this macro is not defined, then ALIGN is used.
364 The typical use of this macro is to increase alignment for string constants
365 to be word aligned so that `strcpy' calls that copy constants can be done
367 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
368 (TREE_CODE (EXP) == STRING_CST \
369 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
371 /* Define this macro to be the value 1 if instructions will fail to work if
372 given data not on the nominal alignment. If instructions will merely go
373 slower in that case, define this macro as 0. */
374 #define STRICT_ALIGNMENT 1
376 #define PCC_BITFIELD_TYPE_MATTERS 1
379 /* Layout of Source Language Data Types. */
381 #define CHAR_TYPE_SIZE 8
382 #define SHORT_TYPE_SIZE 16
383 #define INT_TYPE_SIZE 32
384 #define LONG_TYPE_SIZE 32
385 #define LONG_LONG_TYPE_SIZE 64
386 #define FLOAT_TYPE_SIZE 32
387 #define DOUBLE_TYPE_SIZE 64
388 #define LONG_DOUBLE_TYPE_SIZE 64
390 /* An expression whose value is 1 or 0, according to whether the type `char'
391 should be signed or unsigned by default. The user can always override this
392 default with the options `-fsigned-char' and `-funsigned-char'. */
393 #define DEFAULT_SIGNED_CHAR 1
396 #define SIZE_TYPE "unsigned int"
399 #define PTRDIFF_TYPE "int"
402 #define WCHAR_TYPE "long int"
404 #undef WCHAR_TYPE_SIZE
405 #define WCHAR_TYPE_SIZE BITS_PER_WORD
408 /* General purpose registers. */
409 #define GPR_FIRST 0 /* First gpr */
410 #define GPR_LAST (GPR_FIRST + 63) /* Last gpr */
411 #define GPR_R0 GPR_FIRST /* R0, constant 0 */
412 #define GPR_FP (GPR_FIRST + 2) /* Frame pointer */
413 #define GPR_SP (GPR_FIRST + 1) /* Stack pointer */
414 /* small data register */
415 #define SDA_BASE_REG ((unsigned)(TARGET_FDPIC ? -1 : flag_pic ? PIC_REGNO : (GPR_FIRST + 16)))
416 #define PIC_REGNO (GPR_FIRST + (TARGET_FDPIC?15:17)) /* PIC register. */
417 #define FDPIC_FPTR_REGNO (GPR_FIRST + 14) /* uClinux PIC function pointer register. */
418 #define FDPIC_REGNO (GPR_FIRST + 15) /* uClinux PIC register. */
420 #define HARD_REGNO_RENAME_OK(from,to) (TARGET_FDPIC ? ((to) != FDPIC_REG) : 1)
422 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO)
424 #define FPR_FIRST 64 /* First FP reg */
425 #define FPR_LAST 127 /* Last FP reg */
427 #define GPR_TEMP_NUM frv_condexec_temps /* # gprs to reserve for temps */
429 /* We reserve the last CR and CCR in each category to be used as a reload
430 register to reload the CR/CCR registers. This is a kludge. */
431 #define CC_FIRST 128 /* First ICC/FCC reg */
432 #define CC_LAST 135 /* Last ICC/FCC reg */
433 #define ICC_FIRST (CC_FIRST + 4) /* First ICC reg */
434 #define ICC_LAST (CC_FIRST + 7) /* Last ICC reg */
435 #define ICC_TEMP (CC_FIRST + 7) /* Temporary ICC reg */
436 #define FCC_FIRST (CC_FIRST) /* First FCC reg */
437 #define FCC_LAST (CC_FIRST + 3) /* Last FCC reg */
439 /* Amount to shift a value to locate a ICC or FCC register in the CCR
440 register and shift it to the bottom 4 bits. */
441 #define CC_SHIFT_RIGHT(REGNO) (((REGNO) - CC_FIRST) << 2)
443 /* Mask to isolate a single ICC/FCC value. */
446 /* Masks to isolate the various bits in an ICC field. */
447 #define ICC_MASK_N 0x8 /* negative */
448 #define ICC_MASK_Z 0x4 /* zero */
449 #define ICC_MASK_V 0x2 /* overflow */
450 #define ICC_MASK_C 0x1 /* carry */
452 /* Mask to isolate the N/Z flags in an ICC. */
453 #define ICC_MASK_NZ (ICC_MASK_N | ICC_MASK_Z)
455 /* Mask to isolate the Z/C flags in an ICC. */
456 #define ICC_MASK_ZC (ICC_MASK_Z | ICC_MASK_C)
458 /* Masks to isolate the various bits in a FCC field. */
459 #define FCC_MASK_E 0x8 /* equal */
460 #define FCC_MASK_L 0x4 /* less than */
461 #define FCC_MASK_G 0x2 /* greater than */
462 #define FCC_MASK_U 0x1 /* unordered */
464 /* For CCR registers, the machine wants CR4..CR7 to be used for integer
465 code and CR0..CR3 to be used for floating point. */
466 #define CR_FIRST 136 /* First CCR */
467 #define CR_LAST 143 /* Last CCR */
468 #define CR_NUM (CR_LAST-CR_FIRST+1) /* # of CCRs (8) */
469 #define ICR_FIRST (CR_FIRST + 4) /* First integer CCR */
470 #define ICR_LAST (CR_FIRST + 7) /* Last integer CCR */
471 #define ICR_TEMP ICR_LAST /* Temp integer CCR */
472 #define FCR_FIRST (CR_FIRST + 0) /* First float CCR */
473 #define FCR_LAST (CR_FIRST + 3) /* Last float CCR */
475 /* Amount to shift a value to locate a CR register in the CCCR special purpose
476 register and shift it to the bottom 2 bits. */
477 #define CR_SHIFT_RIGHT(REGNO) (((REGNO) - CR_FIRST) << 1)
479 /* Mask to isolate a single CR value. */
482 #define ACC_FIRST 144 /* First acc register */
483 #define ACC_LAST 155 /* Last acc register */
485 #define ACCG_FIRST 156 /* First accg register */
486 #define ACCG_LAST 167 /* Last accg register */
488 #define AP_FIRST 168 /* fake argument pointer */
490 #define SPR_FIRST 169
492 #define LR_REGNO (SPR_FIRST)
493 #define LCR_REGNO (SPR_FIRST + 1)
494 #define IACC_FIRST (SPR_FIRST + 2)
495 #define IACC_LAST (SPR_FIRST + 3)
497 #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST)
498 #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM)
499 #define FPR_P(R) IN_RANGE (R, FPR_FIRST, FPR_LAST)
500 #define CC_P(R) IN_RANGE (R, CC_FIRST, CC_LAST)
501 #define ICC_P(R) IN_RANGE (R, ICC_FIRST, ICC_LAST)
502 #define FCC_P(R) IN_RANGE (R, FCC_FIRST, FCC_LAST)
503 #define CR_P(R) IN_RANGE (R, CR_FIRST, CR_LAST)
504 #define ICR_P(R) IN_RANGE (R, ICR_FIRST, ICR_LAST)
505 #define FCR_P(R) IN_RANGE (R, FCR_FIRST, FCR_LAST)
506 #define ACC_P(R) IN_RANGE (R, ACC_FIRST, ACC_LAST)
507 #define ACCG_P(R) IN_RANGE (R, ACCG_FIRST, ACCG_LAST)
508 #define SPR_P(R) IN_RANGE (R, SPR_FIRST, SPR_LAST)
510 #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
511 #define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
512 #define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
513 #define CC_OR_PSEUDO_P(R) (CC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
514 #define ICC_OR_PSEUDO_P(R) (ICC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
515 #define FCC_OR_PSEUDO_P(R) (FCC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
516 #define CR_OR_PSEUDO_P(R) (CR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
517 #define ICR_OR_PSEUDO_P(R) (ICR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
518 #define FCR_OR_PSEUDO_P(R) (FCR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
519 #define ACC_OR_PSEUDO_P(R) (ACC_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
520 #define ACCG_OR_PSEUDO_P(R) (ACCG_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
522 #define MAX_STACK_IMMEDIATE_OFFSET 2047
525 /* Register Basics. */
527 /* Number of hardware registers known to the compiler. They receive numbers 0
528 through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number
529 really is assigned the number `FIRST_PSEUDO_REGISTER'. */
530 #define FIRST_PSEUDO_REGISTER (SPR_LAST + 1)
532 /* The first/last register that can contain the arguments to a function. */
533 #define FIRST_ARG_REGNUM (GPR_FIRST + 8)
534 #define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + FRV_NUM_ARG_REGS - 1)
536 /* Registers used by the exception handling functions. These should be
537 registers that are not otherwise used by the calling sequence. */
538 #define FIRST_EH_REGNUM 14
539 #define LAST_EH_REGNUM 15
541 /* Scratch registers used in the prologue, epilogue and thunks.
542 OFFSET_REGNO is for loading constant addends that are too big for a
543 single instruction. TEMP_REGNO is used for transferring SPRs to and from
544 the stack, and various other activities. */
545 #define OFFSET_REGNO 4
548 /* Registers used in the prologue. OLD_SP_REGNO is the old stack pointer,
549 which is sometimes used to set up the frame pointer. */
550 #define OLD_SP_REGNO 6
552 /* Registers used in the epilogue. STACKADJ_REGNO stores the exception
553 handler's stack adjustment. */
554 #define STACKADJ_REGNO 6
556 /* Registers used in thunks. JMP_REGNO is used for loading the target
560 #define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_EH_REGNUM - FIRST_EH_REGNUM)? \
561 (N) + FIRST_EH_REGNUM : INVALID_REGNUM)
562 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, STACKADJ_REGNO)
563 #define EH_RETURN_HANDLER_RTX RETURN_ADDR_RTX (0, frame_pointer_rtx)
565 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNO)
567 /* An initializer that says which registers are used for fixed purposes all
568 throughout the compiled code and are therefore not available for general
569 allocation. These would include the stack pointer, the frame pointer
570 (except on machines where that can be used as a general register when no
571 frame pointer is needed), the program counter on machines where that is
572 considered one of the addressable registers, and any other numbered register
575 This information is expressed as a sequence of numbers, separated by commas
576 and surrounded by braces. The Nth number is 1 if register N is fixed, 0
579 The table initialized from this macro, and the table initialized by the
580 following one, may be overridden at run time either automatically, by the
581 actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the
582 command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */
587 gr3 -- Hidden Parameter
588 gr16 -- Small Data reserved
594 cr3 -- reserved to reload FCC registers.
595 cr7 -- reserved to reload ICC registers. */
596 #define FIXED_REGISTERS \
597 { /* Integer Registers */ \
598 1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \
599 0, 0, 0, 0, 0, 0, 0, 0, /* 008-015, gr8 - gr15 */ \
600 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \
601 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \
602 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \
603 0, 0, 0, 0, 0, 0, 0, 0, /* 040-040, gr48 - gr47 */ \
604 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \
605 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \
606 /* Float Registers */ \
607 0, 0, 0, 0, 0, 0, 0, 0, /* 064-071, fr0 - fr7 */ \
608 0, 0, 0, 0, 0, 0, 0, 0, /* 072-079, fr8 - fr15 */ \
609 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \
610 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \
611 0, 0, 0, 0, 0, 0, 0, 0, /* 096-103, fr32 - fr39 */ \
612 0, 0, 0, 0, 0, 0, 0, 0, /* 104-111, fr48 - fr47 */ \
613 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \
614 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \
615 /* Condition Code Registers */ \
616 0, 0, 0, 0, /* 128-131, fcc0 - fcc3 */ \
617 0, 0, 0, 1, /* 132-135, icc0 - icc3 */ \
618 /* Conditional execution Registers (CCR) */ \
619 0, 0, 0, 0, 0, 0, 0, 1, /* 136-143, cr0 - cr7 */ \
621 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \
622 1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \
623 1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \
624 1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \
625 /* Other registers */ \
626 1, /* 168, AP - fake arg ptr */ \
627 1, /* 169, LR - Link register*/ \
628 0, /* 170, LCR - Loop count reg*/ \
629 1, 1 /* 171-172, iacc0 */ \
632 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in
633 general) by function calls as well as for fixed registers. This macro
634 therefore identifies the registers that are not available for general
635 allocation of values that must live across function calls.
637 If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically
638 saves it on function entry and restores it on function exit, if the register
639 is used within the function. */
640 #define CALL_USED_REGISTERS \
641 { /* Integer Registers */ \
642 1, 1, 1, 1, 1, 1, 1, 1, /* 000-007, gr0 - gr7 */ \
643 1, 1, 1, 1, 1, 1, 1, 1, /* 008-015, gr8 - gr15 */ \
644 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \
645 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \
646 1, 1, 1, 1, 1, 1, 1, 1, /* 032-039, gr32 - gr39 */ \
647 1, 1, 1, 1, 1, 1, 1, 1, /* 040-040, gr48 - gr47 */ \
648 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \
649 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \
650 /* Float Registers */ \
651 1, 1, 1, 1, 1, 1, 1, 1, /* 064-071, fr0 - fr7 */ \
652 1, 1, 1, 1, 1, 1, 1, 1, /* 072-079, fr8 - fr15 */ \
653 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \
654 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \
655 1, 1, 1, 1, 1, 1, 1, 1, /* 096-103, fr32 - fr39 */ \
656 1, 1, 1, 1, 1, 1, 1, 1, /* 104-111, fr48 - fr47 */ \
657 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \
658 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \
659 /* Condition Code Registers */ \
660 1, 1, 1, 1, /* 128-131, fcc0 - fcc3 */ \
661 1, 1, 1, 1, /* 132-135, icc0 - icc3 */ \
662 /* Conditional execution Registers (CCR) */ \
663 1, 1, 1, 1, 1, 1, 1, 1, /* 136-143, cr0 - cr7 */ \
665 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \
666 1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \
667 1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \
668 1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \
669 /* Other registers */ \
670 1, /* 168, AP - fake arg ptr */ \
671 1, /* 169, LR - Link register*/ \
672 1, /* 170, LCR - Loop count reg */ \
673 1, 1 /* 171-172, iacc0 */ \
677 /* Order of allocation of registers. */
679 /* If defined, an initializer for a vector of integers, containing the numbers
680 of hard registers in the order in which GCC should prefer to use them
681 (from most preferred to least).
683 If this macro is not defined, registers are used lowest numbered first (all
686 One use of this macro is on machines where the highest numbered registers
687 must always be saved and the save-multiple-registers instruction supports
688 only sequences of consecutive registers. On such machines, define
689 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
690 allocatable register first. */
692 /* On the FRV, allocate GR16 and GR17 after other saved registers so that we
693 have a better chance of allocating 2 registers at a time and can use the
694 double word load/store instructions in the prologue. */
695 #define REG_ALLOC_ORDER \
697 /* volatile registers */ \
698 GPR_FIRST + 4, GPR_FIRST + 5, GPR_FIRST + 6, GPR_FIRST + 7, \
699 GPR_FIRST + 8, GPR_FIRST + 9, GPR_FIRST + 10, GPR_FIRST + 11, \
700 GPR_FIRST + 12, GPR_FIRST + 13, GPR_FIRST + 14, GPR_FIRST + 15, \
701 GPR_FIRST + 32, GPR_FIRST + 33, GPR_FIRST + 34, GPR_FIRST + 35, \
702 GPR_FIRST + 36, GPR_FIRST + 37, GPR_FIRST + 38, GPR_FIRST + 39, \
703 GPR_FIRST + 40, GPR_FIRST + 41, GPR_FIRST + 42, GPR_FIRST + 43, \
704 GPR_FIRST + 44, GPR_FIRST + 45, GPR_FIRST + 46, GPR_FIRST + 47, \
706 FPR_FIRST + 0, FPR_FIRST + 1, FPR_FIRST + 2, FPR_FIRST + 3, \
707 FPR_FIRST + 4, FPR_FIRST + 5, FPR_FIRST + 6, FPR_FIRST + 7, \
708 FPR_FIRST + 8, FPR_FIRST + 9, FPR_FIRST + 10, FPR_FIRST + 11, \
709 FPR_FIRST + 12, FPR_FIRST + 13, FPR_FIRST + 14, FPR_FIRST + 15, \
710 FPR_FIRST + 32, FPR_FIRST + 33, FPR_FIRST + 34, FPR_FIRST + 35, \
711 FPR_FIRST + 36, FPR_FIRST + 37, FPR_FIRST + 38, FPR_FIRST + 39, \
712 FPR_FIRST + 40, FPR_FIRST + 41, FPR_FIRST + 42, FPR_FIRST + 43, \
713 FPR_FIRST + 44, FPR_FIRST + 45, FPR_FIRST + 46, FPR_FIRST + 47, \
715 ICC_FIRST + 0, ICC_FIRST + 1, ICC_FIRST + 2, ICC_FIRST + 3, \
716 FCC_FIRST + 0, FCC_FIRST + 1, FCC_FIRST + 2, FCC_FIRST + 3, \
717 CR_FIRST + 0, CR_FIRST + 1, CR_FIRST + 2, CR_FIRST + 3, \
718 CR_FIRST + 4, CR_FIRST + 5, CR_FIRST + 6, CR_FIRST + 7, \
720 /* saved registers */ \
721 GPR_FIRST + 18, GPR_FIRST + 19, \
722 GPR_FIRST + 20, GPR_FIRST + 21, GPR_FIRST + 22, GPR_FIRST + 23, \
723 GPR_FIRST + 24, GPR_FIRST + 25, GPR_FIRST + 26, GPR_FIRST + 27, \
724 GPR_FIRST + 48, GPR_FIRST + 49, GPR_FIRST + 50, GPR_FIRST + 51, \
725 GPR_FIRST + 52, GPR_FIRST + 53, GPR_FIRST + 54, GPR_FIRST + 55, \
726 GPR_FIRST + 56, GPR_FIRST + 57, GPR_FIRST + 58, GPR_FIRST + 59, \
727 GPR_FIRST + 60, GPR_FIRST + 61, GPR_FIRST + 62, GPR_FIRST + 63, \
728 GPR_FIRST + 16, GPR_FIRST + 17, \
730 FPR_FIRST + 16, FPR_FIRST + 17, FPR_FIRST + 18, FPR_FIRST + 19, \
731 FPR_FIRST + 20, FPR_FIRST + 21, FPR_FIRST + 22, FPR_FIRST + 23, \
732 FPR_FIRST + 24, FPR_FIRST + 25, FPR_FIRST + 26, FPR_FIRST + 27, \
733 FPR_FIRST + 28, FPR_FIRST + 29, FPR_FIRST + 30, FPR_FIRST + 31, \
734 FPR_FIRST + 48, FPR_FIRST + 49, FPR_FIRST + 50, FPR_FIRST + 51, \
735 FPR_FIRST + 52, FPR_FIRST + 53, FPR_FIRST + 54, FPR_FIRST + 55, \
736 FPR_FIRST + 56, FPR_FIRST + 57, FPR_FIRST + 58, FPR_FIRST + 59, \
737 FPR_FIRST + 60, FPR_FIRST + 61, FPR_FIRST + 62, FPR_FIRST + 63, \
739 /* special or fixed registers */ \
740 GPR_FIRST + 0, GPR_FIRST + 1, GPR_FIRST + 2, GPR_FIRST + 3, \
741 GPR_FIRST + 28, GPR_FIRST + 29, GPR_FIRST + 30, GPR_FIRST + 31, \
742 ACC_FIRST + 0, ACC_FIRST + 1, ACC_FIRST + 2, ACC_FIRST + 3, \
743 ACC_FIRST + 4, ACC_FIRST + 5, ACC_FIRST + 6, ACC_FIRST + 7, \
744 ACC_FIRST + 8, ACC_FIRST + 9, ACC_FIRST + 10, ACC_FIRST + 11, \
745 ACCG_FIRST + 0, ACCG_FIRST + 1, ACCG_FIRST + 2, ACCG_FIRST + 3, \
746 ACCG_FIRST + 4, ACCG_FIRST + 5, ACCG_FIRST + 6, ACCG_FIRST + 7, \
747 ACCG_FIRST + 8, ACCG_FIRST + 9, ACCG_FIRST + 10, ACCG_FIRST + 11, \
748 AP_FIRST, LR_REGNO, LCR_REGNO, \
749 IACC_FIRST + 0, IACC_FIRST + 1 \
753 /* How Values Fit in Registers. */
755 /* A C expression for the number of consecutive hard registers, starting at
756 register number REGNO, required to hold a value of mode MODE.
758 On a machine where all registers are exactly one word, a suitable definition
761 #define HARD_REGNO_NREGS(REGNO, MODE) \
762 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
763 / UNITS_PER_WORD)) */
765 /* On the FRV, make the CC modes take 3 words in the integer registers, so that
766 we can build the appropriate instructions to properly reload the values. */
767 #define HARD_REGNO_NREGS(REGNO, MODE) frv_hard_regno_nregs (REGNO, MODE)
769 /* A C expression that is nonzero if it is permissible to store a value of mode
770 MODE in hard register number REGNO (or in several registers starting with
771 that one). For a machine where all registers are equivalent, a suitable
774 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
776 It is not necessary for this macro to check for the numbers of fixed
777 registers, because the allocation mechanism considers them to be always
780 On some machines, double-precision values must be kept in even/odd register
781 pairs. The way to implement that is to define this macro to reject odd
782 register numbers for such modes.
784 The minimum requirement for a mode to be OK in a register is that the
785 `movMODE' instruction pattern support moves between the register and any
786 other hard register for which the mode is OK; and that moving a value into
787 the register and back out not alter it.
789 Since the same instruction used to move `SImode' will work for all narrower
790 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
791 to distinguish between these modes, provided you define patterns `movhi',
792 etc., to take advantage of this. This is useful because of the interaction
793 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
794 all integer modes to be tieable.
796 Many machines have special registers for floating point arithmetic. Often
797 people assume that floating point machine modes are allowed only in floating
798 point registers. This is not true. Any registers that can hold integers
799 can safely *hold* a floating point machine mode, whether or not floating
800 arithmetic can be done on it in those registers. Integer move instructions
801 can be used to move the values.
803 On some machines, though, the converse is true: fixed-point machine modes
804 may not go in floating registers. This is true if the floating registers
805 normalize any value stored in them, because storing a non-floating value
806 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
807 fixed-point machine modes in floating registers. But if the floating
808 registers do not automatically normalize, if you can store any bit pattern
809 in one and retrieve it unchanged without a trap, then any machine mode may
810 go in a floating register, so you can define this macro to say so.
812 The primary significance of special floating registers is rather that they
813 are the registers acceptable in floating point arithmetic instructions.
814 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
815 writing the proper constraints for those instructions.
817 On some machines, the floating registers are especially slow to access, so
818 that it is better to store a value in a stack frame than in such a register
819 if floating point arithmetic is not being done. As long as the floating
820 registers are not in class `GENERAL_REGS', they will not be used unless some
821 pattern's constraint asks for one. */
822 #define HARD_REGNO_MODE_OK(REGNO, MODE) frv_hard_regno_mode_ok (REGNO, MODE)
824 /* A C expression that is nonzero if it is desirable to choose register
825 allocation so as to avoid move instructions between a value of mode MODE1
826 and a value of mode MODE2.
828 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
829 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
831 #define MODES_TIEABLE_P(MODE1, MODE2) (MODE1 == MODE2)
833 /* Define this macro if the compiler should avoid copies to/from CCmode
834 registers. You should only define this macro if support fo copying to/from
835 CCmode is incomplete. */
836 #define AVOID_CCMODE_COPIES
839 /* Register Classes. */
841 /* An enumeral type that must be defined with all the register class names as
842 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
843 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
844 which is not a register class but rather tells how many classes there are.
846 Each register class has a number, which is the value of casting the class
847 name to type `int'. The number serves as an index in many of the tables
876 #define GENERAL_REGS GPR_REGS
878 /* The number of distinct register classes, defined as follows:
880 #define N_REG_CLASSES (int) LIM_REG_CLASSES */
881 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
883 /* An initializer containing the names of the register classes as C string
884 constants. These names are used in writing some of the debugging dumps. */
885 #define REG_CLASS_NAMES { \
910 /* An initializer containing the contents of the register classes, as integers
911 which are bit masks. The Nth integer specifies the contents of class N.
912 The way the integer MASK is interpreted is that register R is in the class
913 if `MASK & (1 << R)' is 1.
915 When the machine has more than 32 registers, an integer does not suffice.
916 Then the integers are replaced by sub-initializers, braced groupings
917 containing several integers. Each sub-initializer must be suitable as an
918 initializer for the type `HARD_REG_SET' which is defined in
920 #define REG_CLASS_CONTENTS \
921 { /* gr0-gr31 gr32-gr63 fr0-fr31 fr32-fr-63 cc/ccr/acc ap/spr */ \
922 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* NO_REGS */\
923 { 0x00000000,0x00000000,0x00000000,0x00000000,0x000000f0,0x0}, /* ICC_REGS */\
924 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000000f,0x0}, /* FCC_REGS */\
925 { 0x00000000,0x00000000,0x00000000,0x00000000,0x000000ff,0x0}, /* CC_REGS */\
926 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000f000,0x0}, /* ICR_REGS */\
927 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000f00,0x0}, /* FCR_REGS */\
928 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000ff00,0x0}, /* CR_REGS */\
929 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x400}, /* LCR_REGS */\
930 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x200}, /* LR_REGS */\
931 { 0x00000100,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR8_REGS */\
932 { 0x00000200,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR9_REGS */\
933 { 0x00000300,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR89_REGS */\
934 { 0x00008000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_REGS */\
935 { 0x00004000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_FPTR_REGS */\
936 { 0x0000c000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_CALL_REGS */\
937 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x1e00}, /* SPR_REGS */\
938 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* QUAD_ACC */\
939 { 0x00000000,0x00000000,0x00000000,0x00000000,0xf0000000,0xff}, /* ACCG_REGS*/\
940 { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* QUAD_FPR */\
941 { 0x0ffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* QUAD_REGS*/\
942 { 0xffffffff,0xffffffff,0x00000000,0x00000000,0x00000000,0x100}, /* GPR_REGS */\
943 { 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\
946 #define EVEN_ACC_REGS QUAD_ACC_REGS
947 #define ACC_REGS QUAD_ACC_REGS
948 #define FEVEN_REGS QUAD_FPR_REGS
949 #define FPR_REGS QUAD_FPR_REGS
950 #define EVEN_REGS QUAD_REGS
952 /* A C expression whose value is a register class containing hard register
953 REGNO. In general there is more than one such class; choose a class which
954 is "minimal", meaning that no smaller class also contains the register. */
956 extern enum reg_class regno_reg_class[];
957 #define REGNO_REG_CLASS(REGNO) regno_reg_class [REGNO]
959 /* A macro whose definition is the name of the class to which a valid base
960 register must belong. A base register is one used in an address which is
961 the register value plus a displacement. */
962 #define BASE_REG_CLASS GPR_REGS
964 /* A macro whose definition is the name of the class to which a valid index
965 register must belong. An index register is one used in an address where its
966 value is either multiplied by a scale factor or added to another register
967 (as well as added to a displacement). */
968 #define INDEX_REG_CLASS GPR_REGS
970 /* A C expression which is nonzero if register number NUM is suitable for use
971 as a base register in operand addresses. It may be either a suitable hard
972 register or a pseudo register that has been allocated such a hard register. */
973 #define REGNO_OK_FOR_BASE_P(NUM) \
974 ((NUM) < FIRST_PSEUDO_REGISTER \
976 : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM])))
978 /* A C expression which is nonzero if register number NUM is suitable for use
979 as an index register in operand addresses. It may be either a suitable hard
980 register or a pseudo register that has been allocated such a hard register.
982 The difference between an index register and a base register is that the
983 index register may be scaled. If an address involves the sum of two
984 registers, neither one of them scaled, then either one may be labeled the
985 "base" and the other the "index"; but whichever labeling is used must fit
986 the machine's constraints of which registers may serve in each capacity.
987 The compiler will try both labelings, looking for one that is valid, and
988 will reload one or both registers only if neither labeling works. */
989 #define REGNO_OK_FOR_INDEX_P(NUM) \
990 ((NUM) < FIRST_PSEUDO_REGISTER \
992 : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM])))
994 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
995 frv_secondary_reload_class (CLASS, MODE, X)
997 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
998 frv_secondary_reload_class (CLASS, MODE, X)
1000 /* A C expression for the maximum number of consecutive registers of
1001 class CLASS needed to hold a value of mode MODE.
1003 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
1004 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
1005 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
1007 This macro helps control the handling of multiple-word values in
1010 This declaration is required. */
1011 #define CLASS_MAX_NREGS(CLASS, MODE) frv_class_max_nregs (CLASS, MODE)
1013 #define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x)))
1016 /* Basic Stack Layout. */
1018 /* Structure to describe information about a saved range of registers */
1020 typedef struct frv_stack_regs {
1021 const char * name; /* name of the register ranges */
1022 int first; /* first register in the range */
1023 int last; /* last register in the range */
1024 int size_1word; /* # of bytes to be stored via 1 word stores */
1025 int size_2words; /* # of bytes to be stored via 2 word stores */
1026 unsigned char field_p; /* true if the registers are a single SPR */
1027 unsigned char dword_p; /* true if we can do dword stores */
1028 unsigned char special_p; /* true if the regs have a fixed save loc. */
1031 /* Register ranges to look into saving. */
1032 #define STACK_REGS_GPR 0 /* Gprs (normally gr16..gr31, gr48..gr63) */
1033 #define STACK_REGS_FPR 1 /* Fprs (normally fr16..fr31, fr48..fr63) */
1034 #define STACK_REGS_LR 2 /* LR register */
1035 #define STACK_REGS_CC 3 /* CCrs (normally not saved) */
1036 #define STACK_REGS_LCR 5 /* lcr register */
1037 #define STACK_REGS_STDARG 6 /* stdarg registers */
1038 #define STACK_REGS_STRUCT 7 /* structure return (gr3) */
1039 #define STACK_REGS_FP 8 /* FP register */
1040 #define STACK_REGS_MAX 9 /* # of register ranges */
1042 /* Values for save_p field. */
1043 #define REG_SAVE_NO_SAVE 0 /* register not saved */
1044 #define REG_SAVE_1WORD 1 /* save the register */
1045 #define REG_SAVE_2WORDS 2 /* save register and register+1 */
1047 /* Structure used to define the frv stack. */
1049 typedef struct frv_stack {
1050 int total_size; /* total bytes allocated for stack */
1051 int vars_size; /* variable save area size */
1052 int parameter_size; /* outgoing parameter size */
1053 int stdarg_size; /* size of regs needed to be saved for stdarg */
1054 int regs_size; /* size of the saved registers */
1055 int regs_size_1word; /* # of bytes to be stored via 1 word stores */
1056 int regs_size_2words; /* # of bytes to be stored via 2 word stores */
1057 int header_size; /* size of the old FP, struct ret., LR save */
1058 int pretend_size; /* size of pretend args */
1059 int vars_offset; /* offset to save local variables from new SP*/
1060 int regs_offset; /* offset to save registers from new SP */
1061 /* register range information */
1062 frv_stack_regs_t regs[STACK_REGS_MAX];
1063 /* offset to store each register */
1064 int reg_offset[FIRST_PSEUDO_REGISTER];
1065 /* whether to save register (& reg+1) */
1066 unsigned char save_p[FIRST_PSEUDO_REGISTER];
1069 /* Define this macro if pushing a word onto the stack moves the stack pointer
1070 to a smaller address. */
1071 #define STACK_GROWS_DOWNWARD 1
1073 /* Define this macro to nonzero if the addresses of local variable slots
1074 are at negative offsets from the frame pointer. */
1075 #define FRAME_GROWS_DOWNWARD 1
1077 /* Offset from the frame pointer to the first local variable slot to be
1080 If `FRAME_GROWS_DOWNWARD', find the next slot's offset by subtracting the
1081 first slot's length from `STARTING_FRAME_OFFSET'. Otherwise, it is found by
1082 adding the length of the first slot to the value `STARTING_FRAME_OFFSET'. */
1083 #define STARTING_FRAME_OFFSET 0
1085 /* Offset from the stack pointer register to the first location at which
1086 outgoing arguments are placed. If not specified, the default value of zero
1087 is used. This is the proper value for most machines.
1089 If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
1090 location at which outgoing arguments are placed. */
1091 #define STACK_POINTER_OFFSET 0
1093 /* Offset from the argument pointer register to the first argument's address.
1094 On some machines it may depend on the data type of the function.
1096 If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first
1097 argument's address. */
1098 #define FIRST_PARM_OFFSET(FUNDECL) 0
1100 /* A C expression whose value is RTL representing the address in a stack frame
1101 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
1102 an RTL expression for the address of the stack frame itself.
1104 If you don't define this macro, the default is to return the value of
1105 FRAMEADDR--that is, the stack frame address is also the address of the stack
1106 word that points to the previous frame. */
1107 #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) frv_dynamic_chain_address (FRAMEADDR)
1109 /* A C expression whose value is RTL representing the value of the return
1110 address for the frame COUNT steps up from the current frame, after the
1111 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
1112 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
1115 The value of the expression must always be the correct address when COUNT is
1116 zero, but may be `NULL_RTX' if there is not way to determine the return
1117 address of other frames. */
1118 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) frv_return_addr_rtx (COUNT, FRAMEADDR)
1120 #define RETURN_POINTER_REGNUM LR_REGNO
1122 /* A C expression whose value is RTL representing the location of the incoming
1123 return address at the beginning of any function, before the prologue. This
1124 RTL is either a `REG', indicating that the return value is saved in `REG',
1125 or a `MEM' representing a location in the stack.
1127 You only need to define this macro if you want to support call frame
1128 debugging information like that provided by DWARF 2. */
1129 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, RETURN_POINTER_REGNUM)
1132 /* Register That Address the Stack Frame. */
1134 /* The register number of the stack pointer register, which must also be a
1135 fixed register according to `FIXED_REGISTERS'. On most machines, the
1136 hardware determines which register this is. */
1137 #define STACK_POINTER_REGNUM (GPR_FIRST + 1)
1139 /* The register number of the frame pointer register, which is used to access
1140 automatic variables in the stack frame. On some machines, the hardware
1141 determines which register this is. On other machines, you can choose any
1142 register you wish for this purpose. */
1143 #define FRAME_POINTER_REGNUM (GPR_FIRST + 2)
1145 /* The register number of the arg pointer register, which is used to access the
1146 function's argument list. On some machines, this is the same as the frame
1147 pointer register. On some machines, the hardware determines which register
1148 this is. On other machines, you can choose any register you wish for this
1149 purpose. If this is not the same register as the frame pointer register,
1150 then you must mark it as a fixed register according to `FIXED_REGISTERS', or
1151 arrange to be able to eliminate it. */
1153 /* On frv this is a fake register that is eliminated in
1154 terms of either the frame pointer or stack pointer. */
1155 #define ARG_POINTER_REGNUM AP_FIRST
1157 /* Register numbers used for passing a function's static chain pointer. If
1158 register windows are used, the register number as seen by the called
1159 function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as
1160 seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers
1161 are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined.
1163 The static chain register need not be a fixed register.
1165 If the static chain is passed in memory, these macros should not be defined;
1166 instead, the next two macros should be defined. */
1167 #define STATIC_CHAIN_REGNUM (GPR_FIRST + 7)
1168 #define STATIC_CHAIN_INCOMING_REGNUM (GPR_FIRST + 7)
1171 /* Eliminating the Frame Pointer and the Arg Pointer. */
1173 /* If defined, this macro specifies a table of register pairs used to eliminate
1174 unneeded registers that point into the stack frame. If it is not defined,
1175 the only elimination attempted by the compiler is to replace references to
1176 the frame pointer with references to the stack pointer.
1178 The definition of this macro is a list of structure initializations, each of
1179 which specifies an original and replacement register.
1181 On some machines, the position of the argument pointer is not known until
1182 the compilation is completed. In such a case, a separate hard register must
1183 be used for the argument pointer. This register can be eliminated by
1184 replacing it with either the frame pointer or the argument pointer,
1185 depending on whether or not the frame pointer has been eliminated.
1187 In this case, you might specify:
1188 #define ELIMINABLE_REGS \
1189 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1190 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1191 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1193 Note that the elimination of the argument pointer with the stack pointer is
1194 specified first since that is the preferred elimination. */
1196 #define ELIMINABLE_REGS \
1198 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1199 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1200 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \
1203 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
1204 initial difference between the specified pair of registers. This macro must
1205 be defined if `ELIMINABLE_REGS' is defined. */
1207 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1208 (OFFSET) = frv_initial_elimination_offset (FROM, TO)
1211 /* Passing Function Arguments on the Stack. */
1213 /* If defined, the maximum amount of space required for outgoing arguments will
1214 be computed and placed into the variable
1215 `crtl->outgoing_args_size'. No space will be pushed onto the
1216 stack for each call; instead, the function prologue should increase the
1217 stack frame size by this amount.
1219 Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not
1221 #define ACCUMULATE_OUTGOING_ARGS 1
1224 /* The number of register assigned to holding function arguments. */
1226 #define FRV_NUM_ARG_REGS 6
1228 /* A C type for declaring a variable that is used as the first argument of
1229 `FUNCTION_ARG' and other related values. For some target machines, the type
1230 `int' suffices and can hold the number of bytes of argument so far.
1232 There is no need to record in `CUMULATIVE_ARGS' anything about the arguments
1233 that have been passed on the stack. The compiler has other variables to
1234 keep track of that. For target machines on which all arguments are passed
1235 on the stack, there is no need to store anything in `CUMULATIVE_ARGS';
1236 however, the data structure must exist and should not be empty, so use
1238 #define CUMULATIVE_ARGS int
1240 /* A C statement (sans semicolon) for initializing the variable CUM for the
1241 state at the beginning of the argument list. The variable has type
1242 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
1243 of the function which will receive the args, or 0 if the args are to a
1244 compiler support library function. The value of INDIRECT is nonzero when
1245 processing an indirect call, for example a call through a function pointer.
1246 The value of INDIRECT is zero for a call to an explicitly named function, a
1247 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
1248 arguments for the function being compiled.
1250 When processing a call to a compiler support library function, LIBNAME
1251 identifies which one. It is a `symbol_ref' rtx which contains the name of
1252 the function, as a string. LIBNAME is 0 when an ordinary C function call is
1253 being processed. Thus, each time this macro is called, either LIBNAME or
1254 FNTYPE is nonzero, but never both of them at once. */
1256 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1257 frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, FNDECL, FALSE)
1259 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1260 arguments for the function being compiled. If this macro is undefined,
1261 `INIT_CUMULATIVE_ARGS' is used instead.
1263 The value passed for LIBNAME is always 0, since library routines with
1264 special calling conventions are never compiled with GCC. The argument
1265 LIBNAME exists for symmetry with `INIT_CUMULATIVE_ARGS'. */
1267 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1268 frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, NULL, TRUE)
1270 /* A C expression that is nonzero if REGNO is the number of a hard register in
1271 which function arguments are sometimes passed. This does *not* include
1272 implicit arguments such as the static chain and the structure-value address.
1273 On many machines, no registers can be used for this purpose since all
1274 function arguments are pushed on the stack. */
1275 #define FUNCTION_ARG_REGNO_P(REGNO) \
1276 ((REGNO) >= FIRST_ARG_REGNUM && ((REGNO) <= LAST_ARG_REGNUM))
1279 /* How Scalar Function Values are Returned. */
1281 /* The number of the hard register that is used to return a scalar value from a
1283 #define RETURN_VALUE_REGNUM (GPR_FIRST + 8)
1285 #define FUNCTION_VALUE_REGNO_P(REGNO) frv_function_value_regno_p (REGNO)
1288 /* How Large Values are Returned. */
1290 /* The number of the register that is used to pass the structure
1292 #define FRV_STRUCT_VALUE_REGNUM (GPR_FIRST + 3)
1295 /* Function Entry and Exit. */
1297 /* Define this macro as a C expression that is nonzero if the return
1298 instruction or the function epilogue ignores the value of the stack pointer;
1299 in other words, if it is safe to delete an instruction to adjust the stack
1300 pointer before a return from the function.
1302 Note that this macro's value is relevant only for functions for which frame
1303 pointers are maintained. It is never safe to delete a final stack
1304 adjustment in a function that has no frame pointer, and the compiler knows
1305 this regardless of `EXIT_IGNORE_STACK'. */
1306 #define EXIT_IGNORE_STACK 1
1308 /* Generating Code for Profiling. */
1310 /* A C statement or compound statement to output to FILE some assembler code to
1311 call the profiling subroutine `mcount'. Before calling, the assembler code
1312 must load the address of a counter variable into a register where `mcount'
1313 expects to find the address. The name of this variable is `LP' followed by
1314 the number LABELNO, so you would generate the name using `LP%d' in a
1317 The details of how the address should be passed to `mcount' are determined
1318 by your operating system environment, not by GCC. To figure them out,
1319 compile a small program for profiling using the system's installed C
1320 compiler and look at the assembler code that results.
1322 This declaration must be present, but it can be an abort if profiling is
1325 #define FUNCTION_PROFILER(FILE, LABELNO)
1327 /* Trampolines for Nested Functions. */
1329 /* A C expression for the size in bytes of the trampoline, as an integer. */
1330 #define TRAMPOLINE_SIZE frv_trampoline_size ()
1332 /* Alignment required for trampolines, in bits.
1334 If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for
1335 aligning trampolines. */
1336 #define TRAMPOLINE_ALIGNMENT (TARGET_FDPIC ? 64 : 32)
1338 /* Define this macro if trampolines need a special subroutine to do their work.
1339 The macro should expand to a series of `asm' statements which will be
1340 compiled with GCC. They go in a library function named
1341 `__transfer_from_trampoline'.
1343 If you need to avoid executing the ordinary prologue code of a compiled C
1344 function when you jump to the subroutine, you can do so by placing a special
1345 label of your own in the assembler code. Use one `asm' statement to
1346 generate an assembler label, and another to make the label global. Then
1347 trampolines can use that label to jump directly to your special assembler
1350 #ifdef __FRV_UNDERSCORE__
1351 #define TRAMPOLINE_TEMPLATE_NAME "___trampoline_template"
1353 #define TRAMPOLINE_TEMPLATE_NAME "__trampoline_template"
1356 #define Twrite _write
1359 #define TRANSFER_FROM_TRAMPOLINE \
1360 extern int Twrite (int, const void *, unsigned); \
1363 __trampoline_setup (short * addr, int size, int fnaddr, int sc) \
1365 extern short __trampoline_template[]; \
1366 short * to = addr; \
1367 short * from = &__trampoline_template[0]; \
1372 Twrite (2, "__trampoline_setup bad size\n", \
1373 sizeof ("__trampoline_setup bad size\n") - 1); \
1378 to[1] = (short)(fnaddr); \
1380 to[3] = (short)(sc); \
1382 to[5] = (short)(fnaddr >> 16); \
1384 to[7] = (short)(sc >> 16); \
1388 for (i = 0; i < 20; i++) \
1389 __asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \
1393 "\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \
1395 TRAMPOLINE_TEMPLATE_NAME ":\n" \
1396 "\tsetlos #0, gr6\n" /* jump register */ \
1397 "\tsetlos #0, gr7\n" /* static chain */ \
1398 "\tsethi #0, gr6\n" \
1399 "\tsethi #0, gr7\n" \
1400 "\tjmpl @(gr0,gr6)\n");
1402 #define TRANSFER_FROM_TRAMPOLINE \
1403 extern int Twrite (int, const void *, unsigned); \
1406 __trampoline_setup (addr, size, fnaddr, sc) \
1412 extern short __trampoline_template[]; \
1413 short * from = &__trampoline_template[0]; \
1415 short **desc = (short **)addr; \
1416 short * to = addr + 4; \
1420 Twrite (2, "__trampoline_setup bad size\n", \
1421 sizeof ("__trampoline_setup bad size\n") - 1); \
1425 /* Create a function descriptor with the address of the code below \
1426 and NULL as the FDPIC value. We don't need the real GOT value \
1427 here, since we don't use it, so we use NULL, that is just as \
1434 to[1] = (short)(fnaddr); \
1436 to[3] = (short)(sc); \
1438 to[5] = (short)(fnaddr >> 16); \
1440 to[7] = (short)(sc >> 16); \
1443 to[10] = from[10]; \
1444 to[11] = from[11]; \
1446 for (i = 0; i < size; i++) \
1447 __asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \
1451 "\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \
1453 TRAMPOLINE_TEMPLATE_NAME ":\n" \
1454 "\tsetlos #0, gr6\n" /* Jump register. */ \
1455 "\tsetlos #0, gr7\n" /* Static chain. */ \
1456 "\tsethi #0, gr6\n" \
1457 "\tsethi #0, gr7\n" \
1458 "\tldd @(gr6,gr0),gr14\n" \
1459 "\tjmpl @(gr14,gr0)\n" \
1464 /* Addressing Modes. */
1466 /* A number, the maximum number of registers that can appear in a valid memory
1467 address. Note that it is up to you to specify a value equal to the maximum
1468 number that `TARGET_LEGITIMATE_ADDRESS_P' would ever accept. */
1469 #define MAX_REGS_PER_ADDRESS 2
1471 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1472 use as a base register. For hard registers, it should always accept those
1473 which the hardware permits and reject the others. Whether the macro accepts
1474 or rejects pseudo registers must be controlled by `REG_OK_STRICT' as
1475 described above. This usually requires two variant definitions, of which
1476 `REG_OK_STRICT' controls the one actually used. */
1477 #ifdef REG_OK_STRICT
1478 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1480 #define REG_OK_FOR_BASE_P(X) GPR_AP_OR_PSEUDO_P (REGNO (X))
1483 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1484 use as an index register.
1486 The difference between an index register and a base register is that the
1487 index register may be scaled. If an address involves the sum of two
1488 registers, neither one of them scaled, then either one may be labeled the
1489 "base" and the other the "index"; but whichever labeling is used must fit
1490 the machine's constraints of which registers may serve in each capacity.
1491 The compiler will try both labelings, looking for one that is valid, and
1492 will reload one or both registers only if neither labeling works. */
1493 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1495 #define FIND_BASE_TERM frv_find_base_term
1497 /* The load-and-update commands allow pre-modification in addresses.
1498 The index has to be in a register. */
1499 #define HAVE_PRE_MODIFY_REG 1
1502 /* We define extra CC modes in frv-modes.def so we need a selector. */
1504 #define SELECT_CC_MODE frv_select_cc_mode
1506 /* A C expression whose value is one if it is always safe to reverse a
1507 comparison whose mode is MODE. If `SELECT_CC_MODE' can ever return MODE for
1508 a floating-point inequality comparison, then `REVERSIBLE_CC_MODE (MODE)'
1511 You need not define this macro if it would always returns zero or if the
1512 floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For
1513 example, here is the definition used on the SPARC, where floating-point
1514 inequality comparisons are always given `CCFPEmode':
1516 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */
1518 /* On frv, don't consider floating point comparisons to be reversible. In
1519 theory, fp equality comparisons can be reversible. */
1520 #define REVERSIBLE_CC_MODE(MODE) \
1521 ((MODE) == CCmode || (MODE) == CC_UNSmode || (MODE) == CC_NZmode)
1523 /* Frv CCR_MODE's are not reversible. */
1524 #define REVERSE_CONDEXEC_PREDICATES_P(x,y) 0
1527 /* Describing Relative Costs of Operations. */
1529 /* A C expression for the cost of a branch instruction. A value of 1 is the
1530 default; other values are interpreted relative to that. */
1531 #define BRANCH_COST(speed_p, predictable_p) frv_branch_cost_int
1533 /* Define this macro as a C expression which is nonzero if accessing less than
1534 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1535 word of memory, i.e., if such access require more than one instruction or if
1536 there is no difference in cost between byte and (aligned) word loads.
1538 When this macro is not defined, the compiler will access a field by finding
1539 the smallest containing object; when it is defined, a fullword load will be
1540 used if alignment permits. Unless bytes accesses are faster than word
1541 accesses, using word accesses is preferable since it may eliminate
1542 subsequent memory access if subsequent accesses occur to other fields in the
1543 same word of the structure, but to different bytes. */
1544 #define SLOW_BYTE_ACCESS 1
1546 /* Define this macro if it is as good or better to call a constant function
1547 address than to call an address kept in a register. */
1548 #define NO_FUNCTION_CSE
1551 /* Dividing the output into sections. */
1553 /* A C expression whose value is a string containing the assembler operation
1554 that should precede instructions and read-only data. Normally `".text"' is
1556 #define TEXT_SECTION_ASM_OP "\t.text"
1558 /* A C expression whose value is a string containing the assembler operation to
1559 identify the following data as writable initialized data. Normally
1560 `".data"' is right. */
1561 #define DATA_SECTION_ASM_OP "\t.data"
1563 #define BSS_SECTION_ASM_OP "\t.section .bss,\"aw\""
1565 /* Short Data Support */
1566 #define SDATA_SECTION_ASM_OP "\t.section .sdata,\"aw\""
1568 #undef INIT_SECTION_ASM_OP
1569 #undef FINI_SECTION_ASM_OP
1570 #define INIT_SECTION_ASM_OP "\t.section .init,\"ax\""
1571 #define FINI_SECTION_ASM_OP "\t.section .fini,\"ax\""
1573 #undef CTORS_SECTION_ASM_OP
1574 #undef DTORS_SECTION_ASM_OP
1575 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\""
1576 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\""
1578 /* A C expression whose value is a string containing the assembler operation to
1579 switch to the fixup section that records all initialized pointers in a -fpic
1580 program so they can be changed program startup time if the program is loaded
1581 at a different address than linked for. */
1582 #define FIXUP_SECTION_ASM_OP "\t.section .rofixup,\"a\""
1584 /* Position Independent Code. */
1586 /* A C expression that is nonzero if X is a legitimate immediate operand on the
1587 target machine when generating position independent code. You can assume
1588 that X satisfies `CONSTANT_P', so you need not check this. You can also
1589 assume FLAG_PIC is true, so you need not check it either. You need not
1590 define this macro if all constants (including `SYMBOL_REF') can be immediate
1591 operands when generating position independent code. */
1592 #define LEGITIMATE_PIC_OPERAND_P(X) \
1593 ( GET_CODE (X) == CONST_INT \
1594 || GET_CODE (X) == CONST_DOUBLE \
1595 || (GET_CODE (X) == HIGH && GET_CODE (XEXP (X, 0)) == CONST_INT) \
1596 || got12_operand (X, VOIDmode)) \
1599 /* The Overall Framework of an Assembler File. */
1601 /* A C string constant describing how to begin a comment in the target
1602 assembler language. The compiler assumes that the comment will end at the
1604 #define ASM_COMMENT_START ";"
1606 /* A C string constant for text to be output before each `asm' statement or
1607 group of consecutive ones. Normally this is `"#APP"', which is a comment
1608 that has no effect on most assemblers but tells the GNU assembler that it
1609 must check the lines that follow for all valid assembler constructs. */
1610 #define ASM_APP_ON "#APP\n"
1612 /* A C string constant for text to be output after each `asm' statement or
1613 group of consecutive ones. Normally this is `"#NO_APP"', which tells the
1614 GNU assembler to resume making the time-saving assumptions that are valid
1615 for ordinary compiler output. */
1616 #define ASM_APP_OFF "#NO_APP\n"
1619 /* Output of Data. */
1621 /* This is how to output a label to dwarf/dwarf2. */
1622 #define ASM_OUTPUT_DWARF_ADDR(STREAM, LABEL) \
1624 fprintf (STREAM, "\t.picptr\t"); \
1625 assemble_name (STREAM, LABEL); \
1628 /* Whether to emit the gas specific dwarf2 line number support. */
1629 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DEBUG_LOC)
1631 /* Output of Uninitialized Variables. */
1633 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1634 assembler definition of a local-common-label named NAME whose size is SIZE
1635 bytes. The variable ROUNDED is the size rounded up to whatever alignment
1638 Use the expression `assemble_name (STREAM, NAME)' to output the name itself;
1639 before and after that, output the additional assembler syntax for defining
1640 the name, and a newline.
1642 This macro controls how the assembler definitions of uninitialized static
1643 variables are output. */
1644 #undef ASM_OUTPUT_LOCAL
1646 #undef ASM_OUTPUT_ALIGNED_LOCAL
1648 /* This is for final.c, because it is used by ASM_DECLARE_OBJECT_NAME. */
1649 extern int size_directive_output;
1651 /* Like `ASM_OUTPUT_ALIGNED_LOCAL' except that it takes an additional
1652 parameter - the DECL of variable to be output, if there is one.
1653 This macro can be called with DECL == NULL_TREE. If you define
1654 this macro, it is used in place of `ASM_OUTPUT_LOCAL' and
1655 `ASM_OUTPUT_ALIGNED_LOCAL', and gives you more flexibility in
1656 handling the destination of the variable. */
1657 #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
1658 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \
1660 if ((SIZE) > 0 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
1661 switch_to_section (get_named_section (NULL, ".sbss", 0)); \
1663 switch_to_section (bss_section); \
1664 ASM_OUTPUT_ALIGN (STREAM, floor_log2 ((ALIGN) / BITS_PER_UNIT)); \
1665 ASM_DECLARE_OBJECT_NAME (STREAM, NAME, DECL); \
1666 ASM_OUTPUT_SKIP (STREAM, (SIZE) ? (SIZE) : 1); \
1670 /* Output and Generation of Labels. */
1672 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1673 assembler definition of a label named NAME. Use the expression
1674 `assemble_name (STREAM, NAME)' to output the name itself; before and after
1675 that, output the additional assembler syntax for defining the name, and a
1677 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1679 assemble_name (STREAM, NAME); \
1680 fputs (":\n", STREAM); \
1683 /* Globalizing directive for a label. */
1684 #define GLOBAL_ASM_OP "\t.globl "
1686 #undef ASM_GENERATE_INTERNAL_LABEL
1687 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1689 sprintf (LABEL, "*.%s%ld", PREFIX, (long)NUM); \
1693 /* Macros Controlling Initialization Routines. */
1695 #undef INIT_SECTION_ASM_OP
1697 /* If defined, `main' will call `__main' despite the presence of
1698 `INIT_SECTION_ASM_OP'. This macro should be defined for systems where the
1699 init section is not actually run automatically, but is still useful for
1700 collecting the lists of constructors and destructors. */
1701 #define INVOKE__main
1703 /* Output of Assembler Instructions. */
1705 /* A C initializer containing the assembler's names for the machine registers,
1706 each one as a C string constant. This is what translates register numbers
1707 in the compiler into assembler language. */
1708 #define REGISTER_NAMES \
1710 "gr0", "sp", "fp", "gr3", "gr4", "gr5", "gr6", "gr7", \
1711 "gr8", "gr9", "gr10", "gr11", "gr12", "gr13", "gr14", "gr15", \
1712 "gr16", "gr17", "gr18", "gr19", "gr20", "gr21", "gr22", "gr23", \
1713 "gr24", "gr25", "gr26", "gr27", "gr28", "gr29", "gr30", "gr31", \
1714 "gr32", "gr33", "gr34", "gr35", "gr36", "gr37", "gr38", "gr39", \
1715 "gr40", "gr41", "gr42", "gr43", "gr44", "gr45", "gr46", "gr47", \
1716 "gr48", "gr49", "gr50", "gr51", "gr52", "gr53", "gr54", "gr55", \
1717 "gr56", "gr57", "gr58", "gr59", "gr60", "gr61", "gr62", "gr63", \
1719 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1720 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
1721 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
1722 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
1723 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
1724 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
1725 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
1726 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
1728 "fcc0", "fcc1", "fcc2", "fcc3", "icc0", "icc1", "icc2", "icc3", \
1729 "cc0", "cc1", "cc2", "cc3", "cc4", "cc5", "cc6", "cc7", \
1730 "acc0", "acc1", "acc2", "acc3", "acc4", "acc5", "acc6", "acc7", \
1731 "acc8", "acc9", "acc10", "acc11", \
1732 "accg0","accg1","accg2","accg3","accg4","accg5","accg6","accg7", \
1733 "accg8", "accg9", "accg10", "accg11", \
1734 "ap", "lr", "lcr", "iacc0h", "iacc0l" \
1737 /* Define this macro if you are using an unusual assembler that
1738 requires different names for the machine instructions.
1740 The definition is a C statement or statements which output an
1741 assembler instruction opcode to the stdio stream STREAM. The
1742 macro-operand PTR is a variable of type `char *' which points to
1743 the opcode name in its "internal" form--the form that is written
1744 in the machine description. The definition should output the
1745 opcode name to STREAM, performing any translation you desire, and
1746 increment the variable PTR to point at the end of the opcode so
1747 that it will not be output twice.
1749 In fact, your macro definition may process less than the entire
1750 opcode name, or more than the opcode name; but if you want to
1751 process text that includes `%'-sequences to substitute operands,
1752 you must take care of the substitution yourself. Just be sure to
1753 increment PTR over whatever text should not be output normally.
1755 If you need to look at the operand values, they can be found as the
1756 elements of `recog_operand'.
1758 If the macro definition does nothing, the instruction is output in
1761 #define ASM_OUTPUT_OPCODE(STREAM, PTR)\
1762 (PTR) = frv_asm_output_opcode (STREAM, PTR)
1764 /* If defined, a C statement to be executed just prior to the output
1765 of assembler code for INSN, to modify the extracted operands so
1766 they will be output differently.
1768 Here the argument OPVEC is the vector containing the operands
1769 extracted from INSN, and NOPERANDS is the number of elements of
1770 the vector which contain meaningful data for this insn. The
1771 contents of this vector are what will be used to convert the insn
1772 template into assembler code, so you can change the assembler
1773 output by changing the contents of the vector.
1775 This macro is useful when various assembler syntaxes share a single
1776 file of instruction patterns; by defining this macro differently,
1777 you can cause a large class of instructions to be output
1778 differently (such as with rearranged operands). Naturally,
1779 variations in assembler syntax affecting individual insn patterns
1780 ought to be handled by writing conditional output routines in
1783 If this macro is not defined, it is equivalent to a null statement. */
1785 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)\
1786 frv_final_prescan_insn (INSN, OPVEC, NOPERANDS)
1788 #undef USER_LABEL_PREFIX
1789 #define USER_LABEL_PREFIX ""
1790 #define REGISTER_PREFIX ""
1791 #define LOCAL_LABEL_PREFIX "."
1792 #define IMMEDIATE_PREFIX "#"
1795 /* Output of dispatch tables. */
1797 /* This macro should be provided on machines where the addresses in a dispatch
1798 table are relative to the table's own address.
1800 The definition should be a C statement to output to the stdio stream STREAM
1801 an assembler pseudo-instruction to generate a difference between two labels.
1802 VALUE and REL are the numbers of two internal labels. The definitions of
1803 these labels are output using `(*targetm.asm_out.internal_label)', and they must be
1804 printed in the same way here. For example,
1806 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */
1807 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1808 fprintf (STREAM, "\t.word .L%d-.L%d\n", VALUE, REL)
1810 /* This macro should be provided on machines where the addresses in a dispatch
1813 The definition should be a C statement to output to the stdio stream STREAM
1814 an assembler pseudo-instruction to generate a reference to a label. VALUE
1815 is the number of an internal label whose definition is output using
1816 `(*targetm.asm_out.internal_label)'. For example,
1818 fprintf (STREAM, "\t.word L%d\n", VALUE) */
1819 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1820 fprintf (STREAM, "\t.word .L%d\n", VALUE)
1822 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1824 /* Assembler Commands for Exception Regions. */
1826 /* Define this macro to 0 if your target supports DWARF 2 frame unwind
1827 information, but it does not yet work with exception handling. Otherwise,
1828 if your target supports this information (if it defines
1829 `INCOMING_RETURN_ADDR_RTX' and either `UNALIGNED_INT_ASM_OP' or
1830 `OBJECT_FORMAT_ELF'), GCC will provide a default definition of 1.
1832 If this macro is defined to 1, the DWARF 2 unwinder will be the default
1833 exception handling mechanism; otherwise, setjmp/longjmp will be used by
1836 If this macro is defined to anything, the DWARF 2 unwinder will be used
1837 instead of inline unwinders and __unwind_function in the non-setjmp case. */
1838 #define DWARF2_UNWIND_INFO 1
1840 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
1842 /* Assembler Commands for Alignment. */
1844 #undef ASM_OUTPUT_SKIP
1845 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1846 fprintf (STREAM, "\t.zero\t%u\n", (int)(NBYTES))
1848 /* A C statement to output to the stdio stream STREAM an assembler command to
1849 advance the location counter to a multiple of 2 to the POWER bytes. POWER
1850 will be a C expression of type `int'. */
1851 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1852 fprintf ((STREAM), "\t.p2align %d\n", (POWER))
1854 /* Inside the text section, align with unpacked nops rather than zeros. */
1855 #define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \
1856 fprintf ((STREAM), "\t.p2alignl %d,0x80880000\n", (POWER))
1858 /* Macros Affecting all Debug Formats. */
1860 /* A C expression that returns the DBX register number for the compiler
1861 register number REGNO. In simple cases, the value of this expression may be
1862 REGNO itself. But sometimes there are some registers that the compiler
1863 knows about and DBX does not, or vice versa. In such cases, some register
1864 may need to have one number in the compiler and another for DBX.
1866 If two registers have consecutive numbers inside GCC, and they can be
1867 used as a pair to hold a multiword value, then they *must* have consecutive
1868 numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers
1869 will be unable to access such a pair, because they expect register pairs to
1870 be consecutive in their own numbering scheme.
1872 If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not
1873 preserve register pairs, then what you must do instead is redefine the
1874 actual register numbering scheme.
1876 This declaration is required. */
1877 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1879 #undef PREFERRED_DEBUGGING_TYPE
1880 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1882 /* Miscellaneous Parameters. */
1884 /* An alias for a machine mode name. This is the machine mode that elements of
1885 a jump-table should have. */
1886 #define CASE_VECTOR_MODE SImode
1888 /* Define this macro if operations between registers with integral mode smaller
1889 than a word are always performed on the entire register. Most RISC machines
1890 have this property and most CISC machines do not. */
1891 #define WORD_REGISTER_OPERATIONS
1893 /* Define this macro to be a C expression indicating when insns that read
1894 memory in MODE, an integral mode narrower than a word, set the bits outside
1895 of MODE to be either the sign-extension or the zero-extension of the data
1896 read. Return `SIGN_EXTEND' for values of MODE for which the insn
1897 sign-extends, `ZERO_EXTEND' for which it zero-extends, and `UNKNOWN' for other
1900 This macro is not called with MODE non-integral or with a width greater than
1901 or equal to `BITS_PER_WORD', so you may return any value in this case. Do
1902 not define this macro if it would always return `UNKNOWN'. On machines where
1903 this macro is defined, you will normally define it as the constant
1904 `SIGN_EXTEND' or `ZERO_EXTEND'. */
1905 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1907 /* Define if loading short immediate values into registers sign extends. */
1908 #define SHORT_IMMEDIATES_SIGN_EXTEND
1910 /* The maximum number of bytes that a single instruction can move quickly from
1911 memory to memory. */
1914 /* A C expression which is nonzero if on this machine it is safe to "convert"
1915 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
1916 than INPREC) by merely operating on it as if it had only OUTPREC bits.
1918 On many machines, this expression can be 1.
1920 When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for
1921 which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the
1922 case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve
1924 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1926 /* An alias for the machine mode for pointers. On most machines, define this
1927 to be the integer mode corresponding to the width of a hardware pointer;
1928 `SImode' on 32-bit machine or `DImode' on 64-bit machines. On some machines
1929 you must define this to be one of the partial integer modes, such as
1932 The width of `Pmode' must be at least as large as the value of
1933 `POINTER_SIZE'. If it is not equal, you must define the macro
1934 `POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to `Pmode'. */
1935 #define Pmode SImode
1937 /* An alias for the machine mode used for memory references to functions being
1938 called, in `call' RTL expressions. On most machines this should be
1940 #define FUNCTION_MODE QImode
1942 /* A C expression for the maximum number of instructions to execute via
1943 conditional execution instructions instead of a branch. A value of
1944 BRANCH_COST+1 is the default if the machine does not use
1945 cc0, and 1 if it does use cc0. */
1946 #define MAX_CONDITIONAL_EXECUTE frv_condexec_insns
1948 /* A C expression to modify the code described by the conditional if
1949 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
1950 FALSE_EXPR for converting if-then and if-then-else code to conditional
1951 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
1952 tests cannot be converted. */
1953 #define IFCVT_MODIFY_TESTS(CE_INFO, TRUE_EXPR, FALSE_EXPR) \
1954 frv_ifcvt_modify_tests (CE_INFO, &TRUE_EXPR, &FALSE_EXPR)
1956 /* A C expression to modify the code described by the conditional if
1957 information CE_INFO, for the basic block BB, possibly updating the tests in
1958 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
1959 if-then-else code to conditional instructions. OLD_TRUE and OLD_FALSE are
1960 the previous tests. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if
1961 the tests cannot be converted. */
1962 #define IFCVT_MODIFY_MULTIPLE_TESTS(CE_INFO, BB, TRUE_EXPR, FALSE_EXPR) \
1963 frv_ifcvt_modify_multiple_tests (CE_INFO, BB, &TRUE_EXPR, &FALSE_EXPR)
1965 /* A C expression to modify the code described by the conditional if
1966 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
1967 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
1968 insn cannot be converted to be executed conditionally. */
1969 #define IFCVT_MODIFY_INSN(CE_INFO, PATTERN, INSN) \
1970 (PATTERN) = frv_ifcvt_modify_insn (CE_INFO, PATTERN, INSN)
1972 /* A C expression to perform any final machine dependent modifications in
1973 converting code to conditional execution in the code described by the
1974 conditional if information CE_INFO. */
1975 #define IFCVT_MODIFY_FINAL(CE_INFO) frv_ifcvt_modify_final (CE_INFO)
1977 /* A C expression to cancel any machine dependent modifications in converting
1978 code to conditional execution in the code described by the conditional if
1979 information CE_INFO. */
1980 #define IFCVT_MODIFY_CANCEL(CE_INFO) frv_ifcvt_modify_cancel (CE_INFO)
1982 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
1983 #define IFCVT_INIT_EXTRA_FIELDS(CE_INFO) frv_ifcvt_init_extra_fields (CE_INFO)
1985 /* The definition of the following macro results in that the 2nd jump
1986 optimization (after the 2nd insn scheduling) is minimal. It is
1987 necessary to define when start cycle marks of insns (TImode is used
1988 for this) is used for VLIW insn packing. Some jump optimizations
1989 make such marks invalid. These marks are corrected for some
1990 (minimal) optimizations. ??? Probably the macro is temporary.
1991 Final solution could making the 2nd jump optimizations before the
1992 2nd instruction scheduling or corrections of the marks for all jump
1993 optimizations. Although some jump optimizations are actually
1994 deoptimizations for VLIW (super-scalar) processors. */
1996 #define MINIMAL_SECOND_JUMP_OPTIMIZATION
1999 /* If the following macro is defined and nonzero and deterministic
2000 finite state automata are used for pipeline hazard recognition, we
2001 will try to exchange insns in queue ready to improve the schedule.
2002 The more macro value, the more tries will be made. */
2003 #define FIRST_CYCLE_MULTIPASS_SCHEDULING 1
2005 /* The following macro is used only when value of
2006 FIRST_CYCLE_MULTIPASS_SCHEDULING is nonzero. The more macro value,
2007 the more tries will be made to choose better schedule. If the
2008 macro value is zero or negative there will be no multi-pass
2010 #define FIRST_CYCLE_MULTIPASS_SCHEDULING_LOOKAHEAD frv_sched_lookahead
2021 FRV_BUILTIN_MADDHSS,
2022 FRV_BUILTIN_MADDHUS,
2023 FRV_BUILTIN_MSUBHSS,
2024 FRV_BUILTIN_MSUBHUS,
2026 FRV_BUILTIN_MQADDHSS,
2027 FRV_BUILTIN_MQADDHUS,
2028 FRV_BUILTIN_MQSUBHSS,
2029 FRV_BUILTIN_MQSUBHUS,
2030 FRV_BUILTIN_MUNPACKH,
2031 FRV_BUILTIN_MDPACKH,
2042 FRV_BUILTIN_MEXPDHW,
2043 FRV_BUILTIN_MEXPDHD,
2046 FRV_BUILTIN_MMULXHS,
2047 FRV_BUILTIN_MMULXHU,
2052 FRV_BUILTIN_MQMULHS,
2053 FRV_BUILTIN_MQMULHU,
2054 FRV_BUILTIN_MQMULXHU,
2055 FRV_BUILTIN_MQMULXHS,
2056 FRV_BUILTIN_MQMACHS,
2057 FRV_BUILTIN_MQMACHU,
2062 FRV_BUILTIN_MQCPXRS,
2063 FRV_BUILTIN_MQCPXRU,
2064 FRV_BUILTIN_MQCPXIS,
2065 FRV_BUILTIN_MQCPXIU,
2069 FRV_BUILTIN_MWTACCG,
2071 FRV_BUILTIN_MRDACCG,
2073 FRV_BUILTIN_MCLRACC,
2074 FRV_BUILTIN_MCLRACCA,
2075 FRV_BUILTIN_MDUNPACKH,
2077 FRV_BUILTIN_MQXMACHS,
2078 FRV_BUILTIN_MQXMACXHS,
2079 FRV_BUILTIN_MQMACXHS,
2080 FRV_BUILTIN_MADDACCS,
2081 FRV_BUILTIN_MSUBACCS,
2082 FRV_BUILTIN_MASACCS,
2083 FRV_BUILTIN_MDADDACCS,
2084 FRV_BUILTIN_MDSUBACCS,
2085 FRV_BUILTIN_MDASACCS,
2087 FRV_BUILTIN_MDROTLI,
2090 FRV_BUILTIN_MDCUTSSI,
2091 FRV_BUILTIN_MQSATHS,
2092 FRV_BUILTIN_MQLCLRHS,
2093 FRV_BUILTIN_MQLMTHS,
2094 FRV_BUILTIN_MQSLLHI,
2095 FRV_BUILTIN_MQSRAHI,
2096 FRV_BUILTIN_MHSETLOS,
2097 FRV_BUILTIN_MHSETLOH,
2098 FRV_BUILTIN_MHSETHIS,
2099 FRV_BUILTIN_MHSETHIH,
2100 FRV_BUILTIN_MHDSETS,
2101 FRV_BUILTIN_MHDSETH,
2104 FRV_BUILTIN_PREFETCH0,
2105 FRV_BUILTIN_PREFETCH,
2113 FRV_BUILTIN_IACCreadll,
2114 FRV_BUILTIN_IACCreadl,
2115 FRV_BUILTIN_IACCsetll,
2116 FRV_BUILTIN_IACCsetl,
2123 FRV_BUILTIN_WRITE16,
2124 FRV_BUILTIN_WRITE32,
2127 #define FRV_BUILTIN_FIRST_NONMEDIA FRV_BUILTIN_SMUL
2129 /* Enable prototypes on the call rtl functions. */
2130 #define MD_CALL_PROTOTYPES 1
2132 #define CPU_UNITS_QUERY 1
2134 #ifdef __FRV_FDPIC__
2135 #define CRT_GET_RFIB_DATA(dbase) \
2136 ({ extern void *_GLOBAL_OFFSET_TABLE_; (dbase) = &_GLOBAL_OFFSET_TABLE_; })
2139 #endif /* __FRV_H__ */
OSDN Git Service
