1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
268 static int frv_default_flags_for_cpu (void);
269 static int frv_string_begins_with (const_tree, const char *);
270 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
271 static void frv_print_operand_memory_reference_reg
273 static void frv_print_operand_memory_reference (FILE *, rtx, int);
274 static int frv_print_operand_jump_hint (rtx);
275 static const char *comparison_string (enum rtx_code, rtx);
276 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
277 static rtx single_set_pattern (rtx);
278 static int frv_function_contains_far_jump (void);
279 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
283 static rtx frv_frame_offset_rtx (int);
284 static rtx frv_frame_mem (enum machine_mode, rtx, int);
285 static rtx frv_dwarf_store (rtx, int);
286 static void frv_frame_insn (rtx, rtx);
287 static void frv_frame_access (frv_frame_accessor_t*,
289 static void frv_frame_access_multi (frv_frame_accessor_t*,
291 static void frv_frame_access_standard_regs (enum frv_stack_op,
293 static struct machine_function *frv_init_machine_status (void);
294 static rtx frv_int_to_acc (enum insn_code, int, rtx);
295 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
296 static rtx frv_read_argument (tree, unsigned int);
297 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
298 static int frv_check_constant_argument (enum insn_code, int, rtx);
299 static rtx frv_legitimize_target (enum insn_code, rtx);
300 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
301 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
302 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
303 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
304 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
305 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
306 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
309 static rtx frv_expand_int_void2arg (enum insn_code, tree);
310 static rtx frv_expand_prefetches (enum insn_code, tree);
311 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
312 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
313 static rtx frv_expand_mclracc_builtin (tree);
314 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
315 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
316 static rtx frv_expand_noargs_builtin (enum insn_code);
317 static void frv_split_iacc_move (rtx, rtx);
318 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
319 static int frv_clear_registers_used (rtx *, void *);
320 static void frv_ifcvt_add_insn (rtx, rtx, int);
321 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
322 static rtx frv_ifcvt_load_value (rtx, rtx);
323 static int frv_acc_group_1 (rtx *, void *);
324 static unsigned int frv_insn_unit (rtx);
325 static bool frv_issues_to_branch_unit_p (rtx);
326 static int frv_cond_flags (rtx);
327 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
328 static int frv_registers_conflict_p_1 (rtx *, void *);
329 static bool frv_registers_conflict_p (rtx);
330 static void frv_registers_update_1 (rtx, const_rtx, void *);
331 static void frv_registers_update (rtx);
332 static void frv_start_packet (void);
333 static void frv_start_packet_block (void);
334 static void frv_finish_packet (void (*) (void));
335 static bool frv_pack_insn_p (rtx);
336 static void frv_add_insn_to_packet (rtx);
337 static void frv_insert_nop_in_packet (rtx);
338 static bool frv_for_each_packet (void (*) (void));
339 static bool frv_sort_insn_group_1 (enum frv_insn_group,
340 unsigned int, unsigned int,
341 unsigned int, unsigned int,
343 static int frv_compare_insns (const void *, const void *);
344 static void frv_sort_insn_group (enum frv_insn_group);
345 static void frv_reorder_packet (void);
346 static void frv_fill_unused_units (enum frv_insn_group);
347 static void frv_align_label (void);
348 static void frv_reorg_packet (void);
349 static void frv_register_nop (rtx);
350 static void frv_reorg (void);
351 static void frv_pack_insns (void);
352 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
353 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
354 static bool frv_assemble_integer (rtx, unsigned, int);
355 static void frv_init_builtins (void);
356 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
357 static void frv_init_libfuncs (void);
358 static bool frv_in_small_data_p (const_tree);
359 static void frv_asm_output_mi_thunk
360 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
361 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
364 static rtx frv_expand_builtin_saveregs (void);
365 static void frv_expand_builtin_va_start (tree, rtx);
366 static bool frv_rtx_costs (rtx, int, int, int*, bool);
367 static void frv_asm_out_constructor (rtx, int);
368 static void frv_asm_out_destructor (rtx, int);
369 static bool frv_function_symbol_referenced_p (rtx);
370 static bool frv_cannot_force_const_mem (rtx);
371 static const char *unspec_got_name (int);
372 static void frv_output_const_unspec (FILE *,
373 const struct frv_unspec *);
374 static bool frv_function_ok_for_sibcall (tree, tree);
375 static rtx frv_struct_value_rtx (tree, int);
376 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
377 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
379 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
381 static bool frv_secondary_reload (bool, rtx, enum reg_class,
383 secondary_reload_info *);
385 /* Allow us to easily change the default for -malloc-cc. */
386 #ifndef DEFAULT_NO_ALLOC_CC
387 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
389 #define MASK_DEFAULT_ALLOC_CC 0
392 /* Initialize the GCC target structure. */
393 #undef TARGET_ASM_FUNCTION_PROLOGUE
394 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
395 #undef TARGET_ASM_FUNCTION_EPILOGUE
396 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
397 #undef TARGET_ASM_INTEGER
398 #define TARGET_ASM_INTEGER frv_assemble_integer
399 #undef TARGET_DEFAULT_TARGET_FLAGS
400 #define TARGET_DEFAULT_TARGET_FLAGS \
401 (MASK_DEFAULT_ALLOC_CC \
408 #undef TARGET_HANDLE_OPTION
409 #define TARGET_HANDLE_OPTION frv_handle_option
410 #undef TARGET_INIT_BUILTINS
411 #define TARGET_INIT_BUILTINS frv_init_builtins
412 #undef TARGET_EXPAND_BUILTIN
413 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
414 #undef TARGET_INIT_LIBFUNCS
415 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
416 #undef TARGET_IN_SMALL_DATA_P
417 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
418 #undef TARGET_RTX_COSTS
419 #define TARGET_RTX_COSTS frv_rtx_costs
420 #undef TARGET_ASM_CONSTRUCTOR
421 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
422 #undef TARGET_ASM_DESTRUCTOR
423 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
425 #undef TARGET_ASM_OUTPUT_MI_THUNK
426 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
427 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
428 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
430 #undef TARGET_SCHED_ISSUE_RATE
431 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
433 #undef TARGET_LEGITIMIZE_ADDRESS
434 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
436 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
437 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
438 #undef TARGET_CANNOT_FORCE_CONST_MEM
439 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
441 #undef TARGET_HAVE_TLS
442 #define TARGET_HAVE_TLS HAVE_AS_TLS
444 #undef TARGET_STRUCT_VALUE_RTX
445 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
446 #undef TARGET_MUST_PASS_IN_STACK
447 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
448 #undef TARGET_PASS_BY_REFERENCE
449 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
450 #undef TARGET_ARG_PARTIAL_BYTES
451 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
453 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
454 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
455 #undef TARGET_SETUP_INCOMING_VARARGS
456 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
457 #undef TARGET_MACHINE_DEPENDENT_REORG
458 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
460 #undef TARGET_EXPAND_BUILTIN_VA_START
461 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
464 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
465 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
468 #undef TARGET_SECONDARY_RELOAD
469 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
471 #undef TARGET_LEGITIMATE_ADDRESS_P
472 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
474 struct gcc_target targetm = TARGET_INITIALIZER;
476 #define FRV_SYMBOL_REF_TLS_P(RTX) \
477 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
480 /* Any function call that satisfies the machine-independent
481 requirements is eligible on FR-V. */
484 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
485 tree exp ATTRIBUTE_UNUSED)
490 /* Return true if SYMBOL is a small data symbol and relocation RELOC
491 can be used to access it directly in a load or store. */
493 static FRV_INLINE bool
494 frv_small_data_reloc_p (rtx symbol, int reloc)
496 return (GET_CODE (symbol) == SYMBOL_REF
497 && SYMBOL_REF_SMALL_P (symbol)
498 && (!TARGET_FDPIC || flag_pic == 1)
499 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
502 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
506 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
508 if (GET_CODE (x) == CONST)
512 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
514 unspec->offset += INTVAL (XEXP (x, 1));
517 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
519 unspec->symbol = XVECEXP (x, 0, 0);
520 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
522 if (unspec->offset == 0)
525 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
526 && unspec->offset > 0
527 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
534 /* Decide whether we can force certain constants to memory. If we
535 decide we can't, the caller should be able to cope with it in
538 We never allow constants to be forced into memory for TARGET_FDPIC.
539 This is necessary for several reasons:
541 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
542 target-independent code will try to force them into the constant
543 pool, thus leading to infinite recursion.
545 2. We can never introduce new constant pool references during reload.
546 Any such reference would require use of the pseudo FDPIC register.
548 3. We can't represent a constant added to a function pointer (which is
549 not the same as a pointer to a function+constant).
551 4. In many cases, it's more efficient to calculate the constant in-line. */
554 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
559 /* Implement TARGET_HANDLE_OPTION. */
562 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
567 if (strcmp (arg, "simple") == 0)
568 frv_cpu_type = FRV_CPU_SIMPLE;
569 else if (strcmp (arg, "tomcat") == 0)
570 frv_cpu_type = FRV_CPU_TOMCAT;
571 else if (strcmp (arg, "fr550") == 0)
572 frv_cpu_type = FRV_CPU_FR550;
573 else if (strcmp (arg, "fr500") == 0)
574 frv_cpu_type = FRV_CPU_FR500;
575 else if (strcmp (arg, "fr450") == 0)
576 frv_cpu_type = FRV_CPU_FR450;
577 else if (strcmp (arg, "fr405") == 0)
578 frv_cpu_type = FRV_CPU_FR405;
579 else if (strcmp (arg, "fr400") == 0)
580 frv_cpu_type = FRV_CPU_FR400;
581 else if (strcmp (arg, "fr300") == 0)
582 frv_cpu_type = FRV_CPU_FR300;
583 else if (strcmp (arg, "frv") == 0)
584 frv_cpu_type = FRV_CPU_GENERIC;
595 frv_default_flags_for_cpu (void)
597 switch (frv_cpu_type)
599 case FRV_CPU_GENERIC:
600 return MASK_DEFAULT_FRV;
603 return MASK_DEFAULT_FR550;
607 return MASK_DEFAULT_FR500;
610 return MASK_DEFAULT_FR450;
614 return MASK_DEFAULT_FR400;
618 return MASK_DEFAULT_SIMPLE;
625 /* Sometimes certain combinations of command options do not make
626 sense on a particular target machine. You can define a macro
627 `OVERRIDE_OPTIONS' to take account of this. This macro, if
628 defined, is executed once just after all the command options have
631 Don't use this macro to turn on various extra optimizations for
632 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
635 frv_override_options (void)
640 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
642 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
643 linker about linking pic and non-pic code. */
646 if (!flag_pic) /* -fPIC */
649 if (! g_switch_set) /* -G0 */
656 /* A C expression whose value is a register class containing hard
657 register REGNO. In general there is more than one such class;
658 choose a class which is "minimal", meaning that no smaller class
659 also contains the register. */
661 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
663 enum reg_class rclass;
667 int gpr_reg = regno - GPR_FIRST;
669 if (gpr_reg == GR8_REG)
672 else if (gpr_reg == GR9_REG)
675 else if (gpr_reg == GR14_REG)
676 rclass = FDPIC_FPTR_REGS;
678 else if (gpr_reg == FDPIC_REGNO)
681 else if ((gpr_reg & 3) == 0)
684 else if ((gpr_reg & 1) == 0)
691 else if (FPR_P (regno))
693 int fpr_reg = regno - GPR_FIRST;
694 if ((fpr_reg & 3) == 0)
695 rclass = QUAD_FPR_REGS;
697 else if ((fpr_reg & 1) == 0)
704 else if (regno == LR_REGNO)
707 else if (regno == LCR_REGNO)
710 else if (ICC_P (regno))
713 else if (FCC_P (regno))
716 else if (ICR_P (regno))
719 else if (FCR_P (regno))
722 else if (ACC_P (regno))
724 int r = regno - ACC_FIRST;
726 rclass = QUAD_ACC_REGS;
727 else if ((r & 1) == 0)
728 rclass = EVEN_ACC_REGS;
733 else if (ACCG_P (regno))
739 regno_reg_class[regno] = rclass;
742 /* Check for small data option */
744 g_switch_value = SDATA_DEFAULT_SIZE;
746 /* A C expression which defines the machine-dependent operand
747 constraint letters for register classes. If CHAR is such a
748 letter, the value should be the register class corresponding to
749 it. Otherwise, the value should be `NO_REGS'. The register
750 letter `r', corresponding to class `GENERAL_REGS', will not be
751 passed to this macro; you do not need to handle it.
753 The following letters are unavailable, due to being used as
758 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
759 'Q', 'R', 'S', 'T', 'U'
761 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
763 for (i = 0; i < 256; i++)
764 reg_class_from_letter[i] = NO_REGS;
766 reg_class_from_letter['a'] = ACC_REGS;
767 reg_class_from_letter['b'] = EVEN_ACC_REGS;
768 reg_class_from_letter['c'] = CC_REGS;
769 reg_class_from_letter['d'] = GPR_REGS;
770 reg_class_from_letter['e'] = EVEN_REGS;
771 reg_class_from_letter['f'] = FPR_REGS;
772 reg_class_from_letter['h'] = FEVEN_REGS;
773 reg_class_from_letter['l'] = LR_REG;
774 reg_class_from_letter['q'] = QUAD_REGS;
775 reg_class_from_letter['t'] = ICC_REGS;
776 reg_class_from_letter['u'] = FCC_REGS;
777 reg_class_from_letter['v'] = ICR_REGS;
778 reg_class_from_letter['w'] = FCR_REGS;
779 reg_class_from_letter['x'] = QUAD_FPR_REGS;
780 reg_class_from_letter['y'] = LCR_REG;
781 reg_class_from_letter['z'] = SPR_REGS;
782 reg_class_from_letter['A'] = QUAD_ACC_REGS;
783 reg_class_from_letter['B'] = ACCG_REGS;
784 reg_class_from_letter['C'] = CR_REGS;
785 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
786 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
788 /* There is no single unaligned SI op for PIC code. Sometimes we
789 need to use ".4byte" and sometimes we need to use ".picptr".
790 See frv_assemble_integer for details. */
791 if (flag_pic || TARGET_FDPIC)
792 targetm.asm_out.unaligned_op.si = 0;
794 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
795 target_flags |= MASK_LINKED_FP;
797 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
798 target_flags |= MASK_OPTIMIZE_MEMBAR;
800 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
801 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
803 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
804 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
806 init_machine_status = frv_init_machine_status;
810 /* Some machines may desire to change what optimizations are performed for
811 various optimization levels. This macro, if defined, is executed once just
812 after the optimization level is determined and before the remainder of the
813 command options have been parsed. Values set in this macro are used as the
814 default values for the other command line options.
816 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
817 `-O' is specified, and 0 if neither is specified.
819 SIZE is nonzero if `-Os' is specified, 0 otherwise.
821 You should not use this macro to change options that are not
822 machine-specific. These should uniformly selected by the same optimization
823 level on all supported machines. Use this macro to enable machine-specific
826 *Do not examine `write_symbols' in this macro!* The debugging options are
827 *not supposed to alter the generated code. */
829 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
830 scheduling pass at the current time. */
832 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
836 #ifdef DISABLE_SCHED2
837 flag_schedule_insns_after_reload = 0;
846 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
849 frv_string_begins_with (const_tree name, const char *prefix)
851 const int prefix_len = strlen (prefix);
853 /* Remember: NAME's length includes the null terminator. */
854 return (TREE_STRING_LENGTH (name) > prefix_len
855 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
858 /* Zero or more C statements that may conditionally modify two variables
859 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
860 been initialized from the two preceding macros.
862 This is necessary in case the fixed or call-clobbered registers depend on
865 You need not define this macro if it has no work to do.
867 If the usage of an entire class of registers depends on the target flags,
868 you may indicate this to GCC by using this macro to modify `fixed_regs' and
869 `call_used_regs' to 1 for each of the registers in the classes which should
870 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
871 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
873 (However, if this class is not included in `GENERAL_REGS' and all of the
874 insn patterns whose constraints permit this class are controlled by target
875 switches, then GCC will automatically avoid using these registers when the
876 target switches are opposed to them.) */
879 frv_conditional_register_usage (void)
883 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
884 fixed_regs[i] = call_used_regs[i] = 1;
886 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
887 fixed_regs[i] = call_used_regs[i] = 1;
889 /* Reserve the registers used for conditional execution. At present, we need
890 1 ICC and 1 ICR register. */
891 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
892 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
896 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
897 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
898 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
899 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
903 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
904 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
907 /* If -fpic, SDA_BASE_REG is the PIC register. */
908 if (g_switch_value == 0 && !flag_pic)
909 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
912 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
918 * Compute the stack frame layout
921 * +---------------+-----------------------+-----------------------+
922 * |Register |type |caller-save/callee-save|
923 * +---------------+-----------------------+-----------------------+
924 * |GR0 |Zero register | - |
925 * |GR1 |Stack pointer(SP) | - |
926 * |GR2 |Frame pointer(FP) | - |
927 * |GR3 |Hidden parameter | caller save |
928 * |GR4-GR7 | - | caller save |
929 * |GR8-GR13 |Argument register | caller save |
930 * |GR14-GR15 | - | caller save |
931 * |GR16-GR31 | - | callee save |
932 * |GR32-GR47 | - | caller save |
933 * |GR48-GR63 | - | callee save |
934 * |FR0-FR15 | - | caller save |
935 * |FR16-FR31 | - | callee save |
936 * |FR32-FR47 | - | caller save |
937 * |FR48-FR63 | - | callee save |
938 * +---------------+-----------------------+-----------------------+
942 * SP-> |-----------------------------------|
944 * |-----------------------------------|
945 * | Register save area |
946 * |-----------------------------------|
947 * | Local variable save area |
948 * FP-> |-----------------------------------|
950 * |-----------------------------------|
951 * | Hidden parameter save area |
952 * |-----------------------------------|
953 * | Return address(LR) storage area |
954 * |-----------------------------------|
955 * | Padding for alignment |
956 * |-----------------------------------|
957 * | Register argument area |
958 * OLD SP-> |-----------------------------------|
960 * |-----------------------------------|
963 * Argument area/Parameter area:
965 * When a function is called, this area is used for argument transfer. When
966 * the argument is set up by the caller function, this area is referred to as
967 * the argument area. When the argument is referenced by the callee function,
968 * this area is referred to as the parameter area. The area is allocated when
969 * all arguments cannot be placed on the argument register at the time of
972 * Register save area:
974 * This is a register save area that must be guaranteed for the caller
975 * function. This area is not secured when the register save operation is not
978 * Local variable save area:
980 * This is the area for local variables and temporary variables.
984 * This area stores the FP value of the caller function.
986 * Hidden parameter save area:
988 * This area stores the start address of the return value storage
989 * area for a struct/union return function.
990 * When a struct/union is used as the return value, the caller
991 * function stores the return value storage area start address in
992 * register GR3 and passes it to the caller function.
993 * The callee function interprets the address stored in the GR3
994 * as the return value storage area start address.
995 * When register GR3 needs to be saved into memory, the callee
996 * function saves it in the hidden parameter save area. This
997 * area is not secured when the save operation is not needed.
999 * Return address(LR) storage area:
1001 * This area saves the LR. The LR stores the address of a return to the caller
1002 * function for the purpose of function calling.
1004 * Argument register area:
1006 * This area saves the argument register. This area is not secured when the
1007 * save operation is not needed.
1011 * Arguments, the count of which equals the count of argument registers (6
1012 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1013 * function. When a struct/union return function is called, the return value
1014 * area address is stored in register GR3. Arguments not placed in the
1015 * argument registers will be stored in the stack argument area for transfer
1016 * purposes. When an 8-byte type argument is to be delivered using registers,
1017 * it is divided into two and placed in two registers for transfer. When
1018 * argument registers must be saved to memory, the callee function secures an
1019 * argument register save area in the stack. In this case, a continuous
1020 * argument register save area must be established in the parameter area. The
1021 * argument register save area must be allocated as needed to cover the size of
1022 * the argument register to be saved. If the function has a variable count of
1023 * arguments, it saves all argument registers in the argument register save
1026 * Argument Extension Format:
1028 * When an argument is to be stored in the stack, its type is converted to an
1029 * extended type in accordance with the individual argument type. The argument
1030 * is freed by the caller function after the return from the callee function is
1033 * +-----------------------+---------------+------------------------+
1034 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1035 * +-----------------------+---------------+------------------------+
1037 * |signed char |int | 4 |
1038 * |unsigned char |int | 4 |
1039 * |[signed] short int |int | 4 |
1040 * |unsigned short int |int | 4 |
1041 * |[signed] int |No extension | 4 |
1042 * |unsigned int |No extension | 4 |
1043 * |[signed] long int |No extension | 4 |
1044 * |unsigned long int |No extension | 4 |
1045 * |[signed] long long int |No extension | 8 |
1046 * |unsigned long long int |No extension | 8 |
1047 * |float |double | 8 |
1048 * |double |No extension | 8 |
1049 * |long double |No extension | 8 |
1050 * |pointer |No extension | 4 |
1051 * |struct/union |- | 4 (*1) |
1052 * +-----------------------+---------------+------------------------+
1054 * When a struct/union is to be delivered as an argument, the caller copies it
1055 * to the local variable area and delivers the address of that area.
1059 * +-------------------------------+----------------------+
1060 * |Return Value Type |Return Value Interface|
1061 * +-------------------------------+----------------------+
1063 * |[signed|unsigned] char |GR8 |
1064 * |[signed|unsigned] short int |GR8 |
1065 * |[signed|unsigned] int |GR8 |
1066 * |[signed|unsigned] long int |GR8 |
1068 * |[signed|unsigned] long long int|GR8 & GR9 |
1070 * |double |GR8 & GR9 |
1071 * |long double |GR8 & GR9 |
1072 * |struct/union |(*1) |
1073 * +-------------------------------+----------------------+
1075 * When a struct/union is used as the return value, the caller function stores
1076 * the start address of the return value storage area into GR3 and then passes
1077 * it to the callee function. The callee function interprets GR3 as the start
1078 * address of the return value storage area. When this address needs to be
1079 * saved in memory, the callee function secures the hidden parameter save area
1080 * and saves the address in that area.
1084 frv_stack_info (void)
1086 static frv_stack_t info, zero_info;
1087 frv_stack_t *info_ptr = &info;
1088 tree fndecl = current_function_decl;
1096 /* If we've already calculated the values and reload is complete,
1098 if (frv_stack_cache)
1099 return frv_stack_cache;
1101 /* Zero all fields. */
1104 /* Set up the register range information. */
1105 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1106 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1107 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1108 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1110 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1111 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1112 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1113 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1115 info_ptr->regs[STACK_REGS_LR].name = "lr";
1116 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1117 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1118 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1120 info_ptr->regs[STACK_REGS_CC].name = "cc";
1121 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1122 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1123 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1125 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1126 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1127 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1129 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1130 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1131 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1132 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1133 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1135 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1136 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1137 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1138 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1140 info_ptr->regs[STACK_REGS_FP].name = "fp";
1141 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1142 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1143 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1145 /* Determine if this is a stdarg function. If so, allocate space to store
1152 /* Find the last argument, and see if it is __builtin_va_alist. */
1153 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1155 next_arg = TREE_CHAIN (cur_arg);
1156 if (next_arg == (tree)0)
1158 if (DECL_NAME (cur_arg)
1159 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1167 /* Iterate over all of the register ranges. */
1168 for (range = 0; range < STACK_REGS_MAX; range++)
1170 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1171 int first = reg_ptr->first;
1172 int last = reg_ptr->last;
1174 int size_2words = 0;
1177 /* Calculate which registers need to be saved & save area size. */
1181 for (regno = first; regno <= last; regno++)
1183 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1184 || (crtl->calls_eh_return
1185 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1186 || (!TARGET_FDPIC && flag_pic
1187 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1189 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1190 size_1word += UNITS_PER_WORD;
1195 /* Calculate whether we need to create a frame after everything else
1196 has been processed. */
1201 if (df_regs_ever_live_p (LR_REGNO)
1203 /* This is set for __builtin_return_address, etc. */
1204 || cfun->machine->frame_needed
1205 || (TARGET_LINKED_FP && frame_pointer_needed)
1206 || (!TARGET_FDPIC && flag_pic
1207 && crtl->uses_pic_offset_table))
1209 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1210 size_1word += UNITS_PER_WORD;
1214 case STACK_REGS_STDARG:
1217 /* If this is a stdarg function with a non varardic
1218 argument split between registers and the stack,
1219 adjust the saved registers downward. */
1220 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1223 for (regno = first; regno <= last; regno++)
1225 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1226 size_1word += UNITS_PER_WORD;
1229 info_ptr->stdarg_size = size_1word;
1233 case STACK_REGS_STRUCT:
1234 if (cfun->returns_struct)
1236 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1237 size_1word += UNITS_PER_WORD;
1245 /* If this is a field, it only takes one word. */
1246 if (reg_ptr->field_p)
1247 size_1word = UNITS_PER_WORD;
1249 /* Determine which register pairs can be saved together. */
1250 else if (reg_ptr->dword_p && TARGET_DWORD)
1252 for (regno = first; regno < last; regno += 2)
1254 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1256 size_2words += 2 * UNITS_PER_WORD;
1257 size_1word -= 2 * UNITS_PER_WORD;
1258 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1259 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1264 reg_ptr->size_1word = size_1word;
1265 reg_ptr->size_2words = size_2words;
1267 if (! reg_ptr->special_p)
1269 info_ptr->regs_size_1word += size_1word;
1270 info_ptr->regs_size_2words += size_2words;
1275 /* Set up the sizes of each each field in the frame body, making the sizes
1276 of each be divisible by the size of a dword if dword operations might
1277 be used, or the size of a word otherwise. */
1278 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1280 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1281 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1282 + info_ptr->regs_size_1word,
1284 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1286 info_ptr->pretend_size = crtl->args.pretend_args_size;
1288 /* Work out the size of the frame, excluding the header. Both the frame
1289 body and register parameter area will be dword-aligned. */
1290 info_ptr->total_size
1291 = (ADDR_ALIGN (info_ptr->parameter_size
1292 + info_ptr->regs_size
1293 + info_ptr->vars_size,
1295 + ADDR_ALIGN (info_ptr->pretend_size
1296 + info_ptr->stdarg_size,
1297 2 * UNITS_PER_WORD));
1299 /* See if we need to create a frame at all, if so add header area. */
1300 if (info_ptr->total_size > 0
1301 || frame_pointer_needed
1302 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1303 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1305 offset = info_ptr->parameter_size;
1306 info_ptr->header_size = 4 * UNITS_PER_WORD;
1307 info_ptr->total_size += 4 * UNITS_PER_WORD;
1309 /* Calculate the offsets to save normal register pairs. */
1310 for (range = 0; range < STACK_REGS_MAX; range++)
1312 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1313 if (! reg_ptr->special_p)
1315 int first = reg_ptr->first;
1316 int last = reg_ptr->last;
1319 for (regno = first; regno <= last; regno++)
1320 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1321 && regno != FRAME_POINTER_REGNUM
1322 && (regno < FIRST_ARG_REGNUM
1323 || regno > LAST_ARG_REGNUM))
1325 info_ptr->reg_offset[regno] = offset;
1326 offset += 2 * UNITS_PER_WORD;
1331 /* Calculate the offsets to save normal single registers. */
1332 for (range = 0; range < STACK_REGS_MAX; range++)
1334 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1335 if (! reg_ptr->special_p)
1337 int first = reg_ptr->first;
1338 int last = reg_ptr->last;
1341 for (regno = first; regno <= last; regno++)
1342 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1343 && regno != FRAME_POINTER_REGNUM
1344 && (regno < FIRST_ARG_REGNUM
1345 || regno > LAST_ARG_REGNUM))
1347 info_ptr->reg_offset[regno] = offset;
1348 offset += UNITS_PER_WORD;
1353 /* Calculate the offset to save the local variables at. */
1354 offset = ADDR_ALIGN (offset, alignment);
1355 if (info_ptr->vars_size)
1357 info_ptr->vars_offset = offset;
1358 offset += info_ptr->vars_size;
1361 /* Align header to a dword-boundary. */
1362 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1364 /* Calculate the offsets in the fixed frame. */
1365 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1366 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1367 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1369 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1370 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1371 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1373 if (cfun->returns_struct)
1375 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1376 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1377 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1380 /* Calculate the offsets to store the arguments passed in registers
1381 for stdarg functions. The register pairs are first and the single
1382 register if any is last. The register save area starts on a
1384 if (info_ptr->stdarg_size)
1386 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1387 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1390 /* Skip the header. */
1391 offset += 4 * UNITS_PER_WORD;
1392 for (regno = first; regno <= last; regno++)
1394 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1396 info_ptr->reg_offset[regno] = offset;
1397 offset += 2 * UNITS_PER_WORD;
1399 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1401 info_ptr->reg_offset[regno] = offset;
1402 offset += UNITS_PER_WORD;
1408 if (reload_completed)
1409 frv_stack_cache = info_ptr;
1415 /* Print the information about the frv stack offsets, etc. when debugging. */
1418 frv_debug_stack (frv_stack_t *info)
1423 info = frv_stack_info ();
1425 fprintf (stderr, "\nStack information for function %s:\n",
1426 ((current_function_decl && DECL_NAME (current_function_decl))
1427 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1430 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1431 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1432 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1433 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1434 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1436 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1437 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1438 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1439 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1441 for (range = 0; range < STACK_REGS_MAX; range++)
1443 frv_stack_regs_t *regs = &(info->regs[range]);
1444 if ((regs->size_1word + regs->size_2words) > 0)
1446 int first = regs->first;
1447 int last = regs->last;
1450 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1451 regs->name, regs->size_1word + regs->size_2words,
1452 regs->size_1word, regs->size_2words);
1454 for (regno = first; regno <= last; regno++)
1456 if (info->save_p[regno] == REG_SAVE_1WORD)
1457 fprintf (stderr, " %s (%d)", reg_names[regno],
1458 info->reg_offset[regno]);
1460 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1461 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1462 reg_names[regno+1], info->reg_offset[regno]);
1465 fputc ('\n', stderr);
1475 /* Used during final to control the packing of insns. The value is
1476 1 if the current instruction should be packed with the next one,
1477 0 if it shouldn't or -1 if packing is disabled altogether. */
1479 static int frv_insn_packing_flag;
1481 /* True if the current function contains a far jump. */
1484 frv_function_contains_far_jump (void)
1486 rtx insn = get_insns ();
1488 && !(GET_CODE (insn) == JUMP_INSN
1489 /* Ignore tablejump patterns. */
1490 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1491 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1492 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1493 insn = NEXT_INSN (insn);
1494 return (insn != NULL);
1497 /* For the FRV, this function makes sure that a function with far jumps
1498 will return correctly. It also does the VLIW packing. */
1501 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1503 /* If no frame was created, check whether the function uses a call
1504 instruction to implement a far jump. If so, save the link in gr3 and
1505 replace all returns to LR with returns to GR3. GR3 is used because it
1506 is call-clobbered, because is not available to the register allocator,
1507 and because all functions that take a hidden argument pointer will have
1509 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1513 /* Just to check that the above comment is true. */
1514 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1516 /* Generate the instruction that saves the link register. */
1517 fprintf (file, "\tmovsg lr,gr3\n");
1519 /* Replace the LR with GR3 in *return_internal patterns. The insn
1520 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1521 simply emit a different assembly directive because bralr and jmpl
1522 execute in different units. */
1523 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1524 if (GET_CODE (insn) == JUMP_INSN)
1526 rtx pattern = PATTERN (insn);
1527 if (GET_CODE (pattern) == PARALLEL
1528 && XVECLEN (pattern, 0) >= 2
1529 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1530 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1532 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1533 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1534 SET_REGNO (address, GPR_FIRST + 3);
1541 /* Allow the garbage collector to free the nops created by frv_reorg. */
1542 memset (frv_nops, 0, sizeof (frv_nops));
1546 /* Return the next available temporary register in a given class. */
1549 frv_alloc_temp_reg (
1550 frv_tmp_reg_t *info, /* which registers are available */
1551 enum reg_class rclass, /* register class desired */
1552 enum machine_mode mode, /* mode to allocate register with */
1553 int mark_as_used, /* register not available after allocation */
1554 int no_abort) /* return NULL instead of aborting */
1556 int regno = info->next_reg[ (int)rclass ];
1557 int orig_regno = regno;
1558 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1563 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1564 && TEST_HARD_REG_BIT (info->regs, regno))
1567 if (++regno >= FIRST_PSEUDO_REGISTER)
1569 if (regno == orig_regno)
1571 gcc_assert (no_abort);
1576 nr = HARD_REGNO_NREGS (regno, mode);
1577 info->next_reg[ (int)rclass ] = regno + nr;
1580 for (i = 0; i < nr; i++)
1581 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1583 return gen_rtx_REG (mode, regno);
1587 /* Return an rtx with the value OFFSET, which will either be a register or a
1588 signed 12-bit integer. It can be used as the second operand in an "add"
1589 instruction, or as the index in a load or store.
1591 The function returns a constant rtx if OFFSET is small enough, otherwise
1592 it loads the constant into register OFFSET_REGNO and returns that. */
1594 frv_frame_offset_rtx (int offset)
1596 rtx offset_rtx = GEN_INT (offset);
1597 if (IN_RANGE_P (offset, -2048, 2047))
1601 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1602 if (IN_RANGE_P (offset, -32768, 32767))
1603 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1606 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1607 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1613 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1614 prologue and epilogue uses such expressions to access the stack. */
1616 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1618 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1620 frv_frame_offset_rtx (offset)));
1623 /* Generate a frame-related expression:
1625 (set REG (mem (plus (sp) (const_int OFFSET)))).
1627 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1628 instructions. Marking the expressions as frame-related is superfluous if
1629 the note contains just a single set. But if the note contains a PARALLEL
1630 or SEQUENCE that has several sets, each set must be individually marked
1631 as frame-related. */
1633 frv_dwarf_store (rtx reg, int offset)
1635 rtx set = gen_rtx_SET (VOIDmode,
1636 gen_rtx_MEM (GET_MODE (reg),
1637 plus_constant (stack_pointer_rtx,
1640 RTX_FRAME_RELATED_P (set) = 1;
1644 /* Emit a frame-related instruction whose pattern is PATTERN. The
1645 instruction is the last in a sequence that cumulatively performs the
1646 operation described by DWARF_PATTERN. The instruction is marked as
1647 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1650 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1652 rtx insn = emit_insn (pattern);
1653 RTX_FRAME_RELATED_P (insn) = 1;
1654 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1659 /* Emit instructions that transfer REG to or from the memory location (sp +
1660 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1661 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1662 function to store registers and only the epilogue uses it to load them.
1664 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1665 The generated instruction will use BASE as its base register. BASE may
1666 simply be the stack pointer, but if several accesses are being made to a
1667 region far away from the stack pointer, it may be more efficient to set
1668 up a temporary instead.
1670 Store instructions will be frame-related and will be annotated with the
1671 overall effect of the store. Load instructions will be followed by a
1672 (use) to prevent later optimizations from zapping them.
1674 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1675 as a temporary in such cases. */
1677 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1679 enum machine_mode mode = GET_MODE (reg);
1680 rtx mem = frv_frame_mem (mode,
1682 stack_offset - accessor->base_offset);
1684 if (accessor->op == FRV_LOAD)
1686 if (SPR_P (REGNO (reg)))
1688 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1689 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1690 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1694 /* We cannot use reg+reg addressing for DImode access. */
1696 && GET_CODE (XEXP (mem, 0)) == PLUS
1697 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1698 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1700 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1701 rtx insn = emit_move_insn (temp,
1702 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1703 XEXP (XEXP (mem, 0), 1)));
1704 mem = gen_rtx_MEM (DImode, temp);
1706 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1712 if (SPR_P (REGNO (reg)))
1714 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1715 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1716 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1717 frv_dwarf_store (reg, stack_offset));
1719 else if (mode == DImode)
1721 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1722 with a separate save for each register. */
1723 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1724 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1725 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1726 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1728 /* Also we cannot use reg+reg addressing. */
1729 if (GET_CODE (XEXP (mem, 0)) == PLUS
1730 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1731 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1733 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1734 rtx insn = emit_move_insn (temp,
1735 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1736 XEXP (XEXP (mem, 0), 1)));
1737 mem = gen_rtx_MEM (DImode, temp);
1740 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1741 gen_rtx_PARALLEL (VOIDmode,
1742 gen_rtvec (2, set1, set2)));
1745 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1746 frv_dwarf_store (reg, stack_offset));
1750 /* A function that uses frv_frame_access to transfer a group of registers to
1751 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1752 is the stack information generated by frv_stack_info, and REG_SET is the
1753 number of the register set to transfer. */
1755 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1759 frv_stack_regs_t *regs_info;
1762 regs_info = &info->regs[reg_set];
1763 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1764 if (info->save_p[regno])
1765 frv_frame_access (accessor,
1766 info->save_p[regno] == REG_SAVE_2WORDS
1767 ? gen_rtx_REG (DImode, regno)
1768 : gen_rtx_REG (SImode, regno),
1769 info->reg_offset[regno]);
1772 /* Save or restore callee-saved registers that are kept outside the frame
1773 header. The function saves the registers if OP is FRV_STORE and restores
1774 them if OP is FRV_LOAD. INFO is the stack information generated by
1777 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1779 frv_frame_accessor_t accessor;
1782 accessor.base = stack_pointer_rtx;
1783 accessor.base_offset = 0;
1784 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1785 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1786 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1790 /* Called after register allocation to add any instructions needed for the
1791 prologue. Using a prologue insn is favored compared to putting all of the
1792 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1793 it allows the scheduler to intermix instructions with the saves of
1794 the caller saved registers. In some cases, it might be necessary
1795 to emit a barrier instruction as the last insn to prevent such
1798 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1799 so that the debug info generation code can handle them properly. */
1801 frv_expand_prologue (void)
1803 frv_stack_t *info = frv_stack_info ();
1804 rtx sp = stack_pointer_rtx;
1805 rtx fp = frame_pointer_rtx;
1806 frv_frame_accessor_t accessor;
1808 if (TARGET_DEBUG_STACK)
1809 frv_debug_stack (info);
1811 if (info->total_size == 0)
1814 /* We're interested in three areas of the frame here:
1816 A: the register save area
1818 C: the header after B
1820 If the frame pointer isn't used, we'll have to set up A, B and C
1821 using the stack pointer. If the frame pointer is used, we'll access
1825 B: set up using sp or a temporary (see below)
1828 We set up B using the stack pointer if the frame is small enough.
1829 Otherwise, it's more efficient to copy the old stack pointer into a
1830 temporary and use that.
1832 Note that it's important to make sure the prologue and epilogue use the
1833 same registers to access A and C, since doing otherwise will confuse
1834 the aliasing code. */
1836 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1837 isn't used, the same method will serve for C. */
1838 accessor.op = FRV_STORE;
1839 if (frame_pointer_needed && info->total_size > 2048)
1843 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1844 accessor.base_offset = info->total_size;
1845 insn = emit_insn (gen_movsi (accessor.base, sp));
1849 accessor.base = stack_pointer_rtx;
1850 accessor.base_offset = 0;
1853 /* Allocate the stack space. */
1855 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1856 rtx dwarf_offset = GEN_INT (-info->total_size);
1858 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1861 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1864 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1865 and point the new one to that location. */
1866 if (frame_pointer_needed)
1868 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1870 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1871 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1873 rtx asm_src = plus_constant (accessor.base,
1874 fp_offset - accessor.base_offset);
1875 rtx dwarf_src = plus_constant (sp, fp_offset);
1877 /* Store the old frame pointer at (sp + FP_OFFSET). */
1878 frv_frame_access (&accessor, fp, fp_offset);
1880 /* Set up the new frame pointer. */
1881 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1882 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1884 /* Access region C from the frame pointer. */
1886 accessor.base_offset = fp_offset;
1889 /* Set up region C. */
1890 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1891 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1892 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1894 /* Set up region A. */
1895 frv_frame_access_standard_regs (FRV_STORE, info);
1897 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1898 scheduler from moving loads before the stores saving the registers. */
1899 if (info->stdarg_size > 0)
1900 emit_insn (gen_blockage ());
1902 /* Set up pic register/small data register for this function. */
1903 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1904 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1905 gen_rtx_REG (Pmode, LR_REGNO),
1906 gen_rtx_REG (SImode, OFFSET_REGNO)));
1910 /* Under frv, all of the work is done via frv_expand_epilogue, but
1911 this function provides a convenient place to do cleanup. */
1914 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1915 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1917 frv_stack_cache = (frv_stack_t *)0;
1919 /* Zap last used registers for conditional execution. */
1920 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1922 /* Release the bitmap of created insns. */
1923 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1927 /* Called after register allocation to add any instructions needed for the
1928 epilogue. Using an epilogue insn is favored compared to putting all of the
1929 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1930 it allows the scheduler to intermix instructions with the saves of
1931 the caller saved registers. In some cases, it might be necessary
1932 to emit a barrier instruction as the last insn to prevent such
1936 frv_expand_epilogue (bool emit_return)
1938 frv_stack_t *info = frv_stack_info ();
1939 rtx fp = frame_pointer_rtx;
1940 rtx sp = stack_pointer_rtx;
1944 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1946 /* Restore the stack pointer to its original value if alloca or the like
1948 if (! current_function_sp_is_unchanging)
1949 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1951 /* Restore the callee-saved registers that were used in this function. */
1952 frv_frame_access_standard_regs (FRV_LOAD, info);
1954 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1955 no return instruction should be emitted. */
1956 if (info->save_p[LR_REGNO])
1961 /* Use the same method to access the link register's slot as we did in
1962 the prologue. In other words, use the frame pointer if available,
1963 otherwise use the stack pointer.
1965 LR_OFFSET is the offset of the link register's slot from the start
1966 of the frame and MEM is a memory rtx for it. */
1967 lr_offset = info->reg_offset[LR_REGNO];
1968 if (frame_pointer_needed)
1969 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1971 mem = frv_frame_mem (Pmode, sp, lr_offset);
1973 /* Load the old link register into a GPR. */
1974 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1975 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1978 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1980 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1981 the load is preserved. */
1982 if (frame_pointer_needed)
1984 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1988 /* Deallocate the stack frame. */
1989 if (info->total_size != 0)
1991 rtx offset = frv_frame_offset_rtx (info->total_size);
1992 emit_insn (gen_stack_adjust (sp, sp, offset));
1995 /* If this function uses eh_return, add the final stack adjustment now. */
1996 if (crtl->calls_eh_return)
1997 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2000 emit_jump_insn (gen_epilogue_return (return_addr));
2003 rtx lr = return_addr;
2005 if (REGNO (return_addr) != LR_REGNO)
2007 lr = gen_rtx_REG (Pmode, LR_REGNO);
2008 emit_move_insn (lr, return_addr);
2016 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2019 frv_asm_output_mi_thunk (FILE *file,
2020 tree thunk_fndecl ATTRIBUTE_UNUSED,
2021 HOST_WIDE_INT delta,
2022 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2025 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2026 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2027 const char *name_jmp = reg_names[JUMP_REGNO];
2028 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2030 /* Do the add using an addi if possible. */
2031 if (IN_RANGE_P (delta, -2048, 2047))
2032 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2035 const char *const name_add = reg_names[TEMP_REGNO];
2036 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2037 parallel, delta, name_add);
2038 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2040 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2045 const char *name_pic = reg_names[FDPIC_REGNO];
2046 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2050 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2051 assemble_name (file, name_func);
2052 fprintf (file, "),%s\n", name_jmp);
2054 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2055 assemble_name (file, name_func);
2056 fprintf (file, "),%s\n", name_jmp);
2058 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2062 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2063 assemble_name (file, name_func);
2064 fprintf (file, "\t)), %s\n", name_jmp);
2069 fprintf (file, "\tsethi%s #hi(", parallel);
2070 assemble_name (file, name_func);
2071 fprintf (file, "),%s\n", name_jmp);
2073 fprintf (file, "\tsetlo #lo(");
2074 assemble_name (file, name_func);
2075 fprintf (file, "),%s\n", name_jmp);
2079 /* Use JUMP_REGNO as a temporary PIC register. */
2080 const char *name_lr = reg_names[LR_REGNO];
2081 const char *name_gppic = name_jmp;
2082 const char *name_tmp = reg_names[TEMP_REGNO];
2084 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2085 fprintf (file, "\tcall 1f\n");
2086 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2087 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2088 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2089 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2090 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2092 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2093 assemble_name (file, name_func);
2094 fprintf (file, "),%s\n", name_tmp);
2096 fprintf (file, "\tsetlo #gprello(");
2097 assemble_name (file, name_func);
2098 fprintf (file, "),%s\n", name_tmp);
2100 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2103 /* Jump to the function address. */
2104 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2108 /* A C expression which is nonzero if a function must have and use a frame
2109 pointer. This expression is evaluated in the reload pass. If its value is
2110 nonzero the function will have a frame pointer.
2112 The expression can in principle examine the current function and decide
2113 according to the facts, but on most machines the constant 0 or the constant
2114 1 suffices. Use 0 when the machine allows code to be generated with no
2115 frame pointer, and doing so saves some time or space. Use 1 when there is
2116 no possible advantage to avoiding a frame pointer.
2118 In certain cases, the compiler does not know how to produce valid code
2119 without a frame pointer. The compiler recognizes those cases and
2120 automatically gives the function a frame pointer regardless of what
2121 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2123 In a function that does not require a frame pointer, the frame pointer
2124 register can be allocated for ordinary usage, unless you mark it as a fixed
2125 register. See `FIXED_REGISTERS' for more information. */
2127 /* On frv, create a frame whenever we need to create stack. */
2130 frv_frame_pointer_required (void)
2132 /* If we forgoing the usual linkage requirements, we only need
2133 a frame pointer if the stack pointer might change. */
2134 if (!TARGET_LINKED_FP)
2135 return !current_function_sp_is_unchanging;
2137 if (! current_function_is_leaf)
2140 if (get_frame_size () != 0)
2146 if (!current_function_sp_is_unchanging)
2149 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2155 if (cfun->machine->frame_needed)
2162 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2163 initial difference between the specified pair of registers. This macro must
2164 be defined if `ELIMINABLE_REGS' is defined. */
2166 /* See frv_stack_info for more details on the frv stack frame. */
2169 frv_initial_elimination_offset (int from, int to)
2171 frv_stack_t *info = frv_stack_info ();
2174 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2175 ret = info->total_size - info->pretend_size;
2177 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2178 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2180 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2181 ret = (info->total_size
2182 - info->reg_offset[FRAME_POINTER_REGNUM]
2183 - info->pretend_size);
2188 if (TARGET_DEBUG_STACK)
2189 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2190 reg_names [from], reg_names[to], ret);
2196 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2199 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2200 enum machine_mode mode,
2201 tree type ATTRIBUTE_UNUSED,
2205 if (TARGET_DEBUG_ARG)
2207 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2208 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2212 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2215 frv_expand_builtin_saveregs (void)
2217 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2219 if (TARGET_DEBUG_ARG)
2220 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2223 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2227 /* Expand __builtin_va_start to do the va_start macro. */
2230 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2233 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2235 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2236 GEN_INT (UNITS_PER_WORD * num));
2238 if (TARGET_DEBUG_ARG)
2240 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2241 crtl->args.info, num);
2243 debug_rtx (nextarg);
2246 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2247 fold_convert (TREE_TYPE (valist),
2248 make_tree (sizetype, nextarg)));
2249 TREE_SIDE_EFFECTS (t) = 1;
2251 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2255 /* Expand a block move operation, and return 1 if successful. Return 0
2256 if we should let the compiler generate normal code.
2258 operands[0] is the destination
2259 operands[1] is the source
2260 operands[2] is the length
2261 operands[3] is the alignment */
2263 /* Maximum number of loads to do before doing the stores */
2264 #ifndef MAX_MOVE_REG
2265 #define MAX_MOVE_REG 4
2268 /* Maximum number of total loads to do. */
2269 #ifndef TOTAL_MOVE_REG
2270 #define TOTAL_MOVE_REG 8
2274 frv_expand_block_move (rtx operands[])
2276 rtx orig_dest = operands[0];
2277 rtx orig_src = operands[1];
2278 rtx bytes_rtx = operands[2];
2279 rtx align_rtx = operands[3];
2280 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2293 rtx stores[MAX_MOVE_REG];
2295 enum machine_mode mode;
2297 /* If this is not a fixed size move, just call memcpy. */
2301 /* This should be a fixed size alignment. */
2302 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2304 align = INTVAL (align_rtx);
2306 /* Anything to move? */
2307 bytes = INTVAL (bytes_rtx);
2311 /* Don't support real large moves. */
2312 if (bytes > TOTAL_MOVE_REG*align)
2315 /* Move the address into scratch registers. */
2316 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2317 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2319 num_reg = offset = 0;
2320 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2322 /* Calculate the correct offset for src/dest. */
2326 dest_addr = dest_reg;
2330 src_addr = plus_constant (src_reg, offset);
2331 dest_addr = plus_constant (dest_reg, offset);
2334 /* Generate the appropriate load and store, saving the stores
2336 if (bytes >= 4 && align >= 4)
2338 else if (bytes >= 2 && align >= 2)
2343 move_bytes = GET_MODE_SIZE (mode);
2344 tmp_reg = gen_reg_rtx (mode);
2345 src_mem = change_address (orig_src, mode, src_addr);
2346 dest_mem = change_address (orig_dest, mode, dest_addr);
2347 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2348 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2350 if (num_reg >= MAX_MOVE_REG)
2352 for (i = 0; i < num_reg; i++)
2353 emit_insn (stores[i]);
2358 for (i = 0; i < num_reg; i++)
2359 emit_insn (stores[i]);
2365 /* Expand a block clear operation, and return 1 if successful. Return 0
2366 if we should let the compiler generate normal code.
2368 operands[0] is the destination
2369 operands[1] is the length
2370 operands[3] is the alignment */
2373 frv_expand_block_clear (rtx operands[])
2375 rtx orig_dest = operands[0];
2376 rtx bytes_rtx = operands[1];
2377 rtx align_rtx = operands[3];
2378 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2387 enum machine_mode mode;
2389 /* If this is not a fixed size move, just call memcpy. */
2393 /* This should be a fixed size alignment. */
2394 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2396 align = INTVAL (align_rtx);
2398 /* Anything to move? */
2399 bytes = INTVAL (bytes_rtx);
2403 /* Don't support real large clears. */
2404 if (bytes > TOTAL_MOVE_REG*align)
2407 /* Move the address into a scratch register. */
2408 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2410 num_reg = offset = 0;
2411 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2413 /* Calculate the correct offset for src/dest. */
2414 dest_addr = ((offset == 0)
2416 : plus_constant (dest_reg, offset));
2418 /* Generate the appropriate store of gr0. */
2419 if (bytes >= 4 && align >= 4)
2421 else if (bytes >= 2 && align >= 2)
2426 clear_bytes = GET_MODE_SIZE (mode);
2427 dest_mem = change_address (orig_dest, mode, dest_addr);
2428 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2435 /* The following variable is used to output modifiers of assembler
2436 code of the current output insn. */
2438 static rtx *frv_insn_operands;
2440 /* The following function is used to add assembler insn code suffix .p
2441 if it is necessary. */
2444 frv_asm_output_opcode (FILE *f, const char *ptr)
2448 if (frv_insn_packing_flag <= 0)
2451 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2454 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2455 || (*ptr >= 'A' && *ptr <= 'Z')))
2457 int letter = *ptr++;
2460 frv_print_operand (f, frv_insn_operands [c], letter);
2461 while ((c = *ptr) >= '0' && c <= '9')
2473 /* Set up the packing bit for the current output insn. Note that this
2474 function is not called for asm insns. */
2477 frv_final_prescan_insn (rtx insn, rtx *opvec,
2478 int noperands ATTRIBUTE_UNUSED)
2482 if (frv_insn_packing_flag >= 0)
2484 frv_insn_operands = opvec;
2485 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2487 else if (recog_memoized (insn) >= 0
2488 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2489 /* Packing optimizations have been disabled, but INSN can only
2490 be issued in M1. Insert an mnop in M0. */
2491 fprintf (asm_out_file, "\tmnop.p\n");
2497 /* A C expression whose value is RTL representing the address in a stack frame
2498 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2499 an RTL expression for the address of the stack frame itself.
2501 If you don't define this macro, the default is to return the value of
2502 FRAMEADDR--that is, the stack frame address is also the address of the stack
2503 word that points to the previous frame. */
2505 /* The default is correct, but we need to make sure the frame gets created. */
2507 frv_dynamic_chain_address (rtx frame)
2509 cfun->machine->frame_needed = 1;
2514 /* A C expression whose value is RTL representing the value of the return
2515 address for the frame COUNT steps up from the current frame, after the
2516 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2517 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2520 The value of the expression must always be the correct address when COUNT is
2521 zero, but may be `NULL_RTX' if there is not way to determine the return
2522 address of other frames. */
2525 frv_return_addr_rtx (int count, rtx frame)
2529 cfun->machine->frame_needed = 1;
2530 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2533 /* Given a memory reference MEMREF, interpret the referenced memory as
2534 an array of MODE values, and return a reference to the element
2535 specified by INDEX. Assume that any pre-modification implicit in
2536 MEMREF has already happened.
2538 MEMREF must be a legitimate operand for modes larger than SImode.
2539 frv_legitimate_address_p forbids register+register addresses, which
2540 this function cannot handle. */
2542 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2544 rtx base = XEXP (memref, 0);
2545 if (GET_CODE (base) == PRE_MODIFY)
2546 base = XEXP (base, 0);
2547 return change_address (memref, mode,
2548 plus_constant (base, index * GET_MODE_SIZE (mode)));
2552 /* Print a memory address as an operand to reference that memory location. */
2554 frv_print_operand_address (FILE * stream, rtx x)
2556 if (GET_CODE (x) == MEM)
2559 switch (GET_CODE (x))
2562 fputs (reg_names [ REGNO (x)], stream);
2566 fprintf (stream, "%ld", (long) INTVAL (x));
2570 assemble_name (stream, XSTR (x, 0));
2575 output_addr_const (stream, x);
2579 /* Poorly constructed asm statements can trigger this alternative.
2580 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2581 frv_print_operand_memory_reference (stream, x, 0);
2588 fatal_insn ("bad insn to frv_print_operand_address:", x);
2593 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2595 int regno = true_regnum (x);
2597 fputs (reg_names[regno], stream);
2599 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2602 /* Print a memory reference suitable for the ld/st instructions. */
2605 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2607 struct frv_unspec unspec;
2611 switch (GET_CODE (x))
2618 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2620 x1 = XEXP (XEXP (x, 1), 1);
2630 if (GET_CODE (x0) == CONST_INT)
2638 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2647 else if (GET_CODE (x1) != CONST_INT)
2648 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2651 fputs ("@(", stream);
2653 fputs (reg_names[GPR_R0], stream);
2654 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2655 frv_print_operand_memory_reference_reg (stream, x0);
2657 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2659 fputs (",", stream);
2661 fputs (reg_names [GPR_R0], stream);
2665 switch (GET_CODE (x1))
2669 frv_print_operand_memory_reference_reg (stream, x1);
2673 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2677 if (!frv_const_unspec_p (x1, &unspec))
2678 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2679 frv_output_const_unspec (stream, &unspec);
2683 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2687 fputs (")", stream);
2691 /* Return 2 for likely branches and 0 for non-likely branches */
2693 #define FRV_JUMP_LIKELY 2
2694 #define FRV_JUMP_NOT_LIKELY 0
2697 frv_print_operand_jump_hint (rtx insn)
2702 HOST_WIDE_INT prob = -1;
2703 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2705 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2707 /* Assume any non-conditional jump is likely. */
2708 if (! any_condjump_p (insn))
2709 ret = FRV_JUMP_LIKELY;
2713 labelref = condjump_label (insn);
2716 rtx label = XEXP (labelref, 0);
2717 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2722 note = find_reg_note (insn, REG_BR_PROB, 0);
2724 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2728 prob = INTVAL (XEXP (note, 0));
2729 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2731 : FRV_JUMP_NOT_LIKELY);
2743 case UNKNOWN: direction = "unknown jump direction"; break;
2744 case BACKWARD: direction = "jump backward"; break;
2745 case FORWARD: direction = "jump forward"; break;
2749 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2750 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2751 (long)INSN_UID (insn), direction, (long)prob,
2752 (long)REG_BR_PROB_BASE, ret);
2760 /* Return the comparison operator to use for CODE given that the ICC
2764 comparison_string (enum rtx_code code, rtx op0)
2766 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2769 default: output_operand_lossage ("bad condition code");
2770 case EQ: return "eq";
2771 case NE: return "ne";
2772 case LT: return is_nz_p ? "n" : "lt";
2773 case LE: return "le";
2774 case GT: return "gt";
2775 case GE: return is_nz_p ? "p" : "ge";
2776 case LTU: return is_nz_p ? "no" : "c";
2777 case LEU: return is_nz_p ? "eq" : "ls";
2778 case GTU: return is_nz_p ? "ne" : "hi";
2779 case GEU: return is_nz_p ? "ra" : "nc";
2783 /* Print an operand to an assembler instruction.
2785 `%' followed by a letter and a digit says to output an operand in an
2786 alternate fashion. Four letters have standard, built-in meanings described
2787 below. The machine description macro `PRINT_OPERAND' can define additional
2788 letters with nonstandard meanings.
2790 `%cDIGIT' can be used to substitute an operand that is a constant value
2791 without the syntax that normally indicates an immediate operand.
2793 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2796 `%aDIGIT' can be used to substitute an operand as if it were a memory
2797 reference, with the actual operand treated as the address. This may be
2798 useful when outputting a "load address" instruction, because often the
2799 assembler syntax for such an instruction requires you to write the operand
2800 as if it were a memory reference.
2802 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2804 `%=' outputs a number which is unique to each instruction in the entire
2805 compilation. This is useful for making local labels to be referred to more
2806 than once in a single template that generates multiple assembler
2809 `%' followed by a punctuation character specifies a substitution that does
2810 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2811 assembler code. Other nonstandard cases can be defined in the
2812 `PRINT_OPERAND' macro. You must also define which punctuation characters
2813 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2816 frv_print_operand (FILE * file, rtx x, int code)
2818 struct frv_unspec unspec;
2819 HOST_WIDE_INT value;
2822 if (code != 0 && !ISALPHA (code))
2825 else if (GET_CODE (x) == CONST_INT)
2828 else if (GET_CODE (x) == CONST_DOUBLE)
2830 if (GET_MODE (x) == SFmode)
2835 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2836 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2840 else if (GET_MODE (x) == VOIDmode)
2841 value = CONST_DOUBLE_LOW (x);
2844 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2855 fputs (reg_names[GPR_R0], file);
2859 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2863 /* Output small data area base register (gr16). */
2864 fputs (reg_names[SDA_BASE_REG], file);
2868 /* Output pic register (gr17). */
2869 fputs (reg_names[PIC_REGNO], file);
2873 /* Output the temporary integer CCR register. */
2874 fputs (reg_names[ICR_TEMP], file);
2878 /* Output the temporary integer CC register. */
2879 fputs (reg_names[ICC_TEMP], file);
2882 /* case 'a': print an address. */
2885 /* Print appropriate test for integer branch false operation. */
2886 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2887 XEXP (x, 0)), file);
2891 /* Print appropriate test for integer branch true operation. */
2892 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2896 /* Print 1 for a NE and 0 for an EQ to give the final argument
2897 for a conditional instruction. */
2898 if (GET_CODE (x) == NE)
2901 else if (GET_CODE (x) == EQ)
2905 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2909 /* Print appropriate test for floating point branch false operation. */
2910 switch (GET_CODE (x))
2913 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2915 case EQ: fputs ("ne", file); break;
2916 case NE: fputs ("eq", file); break;
2917 case LT: fputs ("uge", file); break;
2918 case LE: fputs ("ug", file); break;
2919 case GT: fputs ("ule", file); break;
2920 case GE: fputs ("ul", file); break;
2925 /* Print appropriate test for floating point branch true operation. */
2926 switch (GET_CODE (x))
2929 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2931 case EQ: fputs ("eq", file); break;
2932 case NE: fputs ("ne", file); break;
2933 case LT: fputs ("lt", file); break;
2934 case LE: fputs ("le", file); break;
2935 case GT: fputs ("gt", file); break;
2936 case GE: fputs ("ge", file); break;
2941 /* Print appropriate GOT function. */
2942 if (GET_CODE (x) != CONST_INT)
2943 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2944 fputs (unspec_got_name (INTVAL (x)), file);
2948 /* Print 'i' if the operand is a constant, or is a memory reference that
2950 if (GET_CODE (x) == MEM)
2951 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2952 ? XEXP (XEXP (x, 0), 1)
2954 else if (GET_CODE (x) == PLUS)
2957 switch (GET_CODE (x))
2971 /* For jump instructions, print 'i' if the operand is a constant or
2972 is an expression that adds a constant. */
2973 if (GET_CODE (x) == CONST_INT)
2978 if (GET_CODE (x) == CONST_INT
2979 || (GET_CODE (x) == PLUS
2980 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2981 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2987 /* Print the lower register of a double word register pair */
2988 if (GET_CODE (x) == REG)
2989 fputs (reg_names[ REGNO (x)+1 ], file);
2991 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2994 /* case 'l': print a LABEL_REF. */
2998 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2999 for the second word of double memory operations. */
3000 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3001 switch (GET_CODE (x))
3004 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3007 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3015 frv_print_operand_memory_reference (file, x, offset);
3021 /* Print the opcode of a command. */
3022 switch (GET_CODE (x))
3025 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3027 case PLUS: fputs ("add", file); break;
3028 case MINUS: fputs ("sub", file); break;
3029 case AND: fputs ("and", file); break;
3030 case IOR: fputs ("or", file); break;
3031 case XOR: fputs ("xor", file); break;
3032 case ASHIFT: fputs ("sll", file); break;
3033 case ASHIFTRT: fputs ("sra", file); break;
3034 case LSHIFTRT: fputs ("srl", file); break;
3038 /* case 'n': negate and print a constant int. */
3041 /* Print PIC label using operand as the number. */
3042 if (GET_CODE (x) != CONST_INT)
3043 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3045 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3049 /* Print 'u' if the operand is a update load/store. */
3050 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3055 /* If value is 0, print gr0, otherwise it must be a register. */
3056 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3057 fputs (reg_names[GPR_R0], file);
3059 else if (GET_CODE (x) == REG)
3060 fputs (reg_names [REGNO (x)], file);
3063 fatal_insn ("bad insn in frv_print_operand, z case", x);
3067 /* Print constant in hex. */
3068 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3070 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3077 if (GET_CODE (x) == REG)
3078 fputs (reg_names [REGNO (x)], file);
3080 else if (GET_CODE (x) == CONST_INT
3081 || GET_CODE (x) == CONST_DOUBLE)
3082 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3084 else if (frv_const_unspec_p (x, &unspec))
3085 frv_output_const_unspec (file, &unspec);
3087 else if (GET_CODE (x) == MEM)
3088 frv_print_operand_address (file, XEXP (x, 0));
3090 else if (CONSTANT_ADDRESS_P (x))
3091 frv_print_operand_address (file, x);
3094 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3099 fatal_insn ("frv_print_operand: unknown code", x);
3107 /* A C statement (sans semicolon) for initializing the variable CUM for the
3108 state at the beginning of the argument list. The variable has type
3109 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3110 of the function which will receive the args, or 0 if the args are to a
3111 compiler support library function. The value of INDIRECT is nonzero when
3112 processing an indirect call, for example a call through a function pointer.
3113 The value of INDIRECT is zero for a call to an explicitly named function, a
3114 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3115 arguments for the function being compiled.
3117 When processing a call to a compiler support library function, LIBNAME
3118 identifies which one. It is a `symbol_ref' rtx which contains the name of
3119 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3120 being processed. Thus, each time this macro is called, either LIBNAME or
3121 FNTYPE is nonzero, but never both of them at once. */
3124 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3130 *cum = FIRST_ARG_REGNUM;
3132 if (TARGET_DEBUG_ARG)
3134 fprintf (stderr, "\ninit_cumulative_args:");
3135 if (!fndecl && fntype)
3136 fputs (" indirect", stderr);
3139 fputs (" incoming", stderr);
3143 tree ret_type = TREE_TYPE (fntype);
3144 fprintf (stderr, " return=%s,",
3145 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3148 if (libname && GET_CODE (libname) == SYMBOL_REF)
3149 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3151 if (cfun->returns_struct)
3152 fprintf (stderr, " return-struct");
3154 putc ('\n', stderr);
3159 /* Return true if we should pass an argument on the stack rather than
3163 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3165 if (mode == BLKmode)
3169 return AGGREGATE_TYPE_P (type);
3172 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3173 argument with the specified mode and type. If it is not defined,
3174 `PARM_BOUNDARY' is used for all arguments. */
3177 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3178 tree type ATTRIBUTE_UNUSED)
3180 return BITS_PER_WORD;
3184 frv_function_arg (CUMULATIVE_ARGS *cum,
3185 enum machine_mode mode,
3186 tree type ATTRIBUTE_UNUSED,
3188 int incoming ATTRIBUTE_UNUSED)
3190 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3195 /* Return a marker for use in the call instruction. */
3196 if (xmode == VOIDmode)
3202 else if (arg_num <= LAST_ARG_REGNUM)
3204 ret = gen_rtx_REG (xmode, arg_num);
3205 debstr = reg_names[arg_num];
3214 if (TARGET_DEBUG_ARG)
3216 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3217 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3223 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3224 advance past an argument in the argument list. The values MODE, TYPE and
3225 NAMED describe that argument. Once this is done, the variable CUM is
3226 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3228 This macro need not do anything if the argument in question was passed on
3229 the stack. The compiler knows how to track the amount of stack space used
3230 for arguments without any special help. */
3233 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3234 enum machine_mode mode,
3235 tree type ATTRIBUTE_UNUSED,
3238 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3239 int bytes = GET_MODE_SIZE (xmode);
3240 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3243 *cum = arg_num + words;
3245 if (TARGET_DEBUG_ARG)
3247 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3248 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3252 /* A C expression for the number of words, at the beginning of an argument,
3253 must be put in registers. The value must be zero for arguments that are
3254 passed entirely in registers or that are entirely pushed on the stack.
3256 On some machines, certain arguments must be passed partially in registers
3257 and partially in memory. On these machines, typically the first N words of
3258 arguments are passed in registers, and the rest on the stack. If a
3259 multi-word argument (a `double' or a structure) crosses that boundary, its
3260 first few words must be passed in registers and the rest must be pushed.
3261 This macro tells the compiler when this occurs, and how many of the words
3262 should go in registers.
3264 `FUNCTION_ARG' for these arguments should return the first register to be
3265 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3266 the called function. */
3269 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3270 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3272 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3273 int bytes = GET_MODE_SIZE (xmode);
3274 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3278 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3279 ? LAST_ARG_REGNUM - arg_num + 1
3281 ret *= UNITS_PER_WORD;
3283 if (TARGET_DEBUG_ARG && ret)
3284 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3290 /* Return true if a register is ok to use as a base or index register. */
3292 static FRV_INLINE int
3293 frv_regno_ok_for_base_p (int regno, int strict_p)
3299 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3301 if (regno == ARG_POINTER_REGNUM)
3304 return (regno >= FIRST_PSEUDO_REGISTER);
3308 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3309 RTX) is a legitimate memory address on the target machine for a memory
3310 operand of mode MODE.
3312 It usually pays to define several simpler macros to serve as subroutines for
3313 this one. Otherwise it may be too complicated to understand.
3315 This macro must exist in two variants: a strict variant and a non-strict
3316 one. The strict variant is used in the reload pass. It must be defined so
3317 that any pseudo-register that has not been allocated a hard register is
3318 considered a memory reference. In contexts where some kind of register is
3319 required, a pseudo-register with no hard register must be rejected.
3321 The non-strict variant is used in other passes. It must be defined to
3322 accept all pseudo-registers in every context where some kind of register is
3325 Compiler source files that want to use the strict variant of this macro
3326 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3327 conditional to define the strict variant in that case and the non-strict
3330 Subroutines to check for acceptable registers for various purposes (one for
3331 base registers, one for index registers, and so on) are typically among the
3332 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3333 subroutine macros need have two variants; the higher levels of macros may be
3334 the same whether strict or not.
3336 Normally, constant addresses which are the sum of a `symbol_ref' and an
3337 integer are stored inside a `const' RTX to mark them as constant.
3338 Therefore, there is no need to recognize such sums specifically as
3339 legitimate addresses. Normally you would simply recognize any `const' as
3342 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3343 are not marked with `const'. It assumes that a naked `plus' indicates
3344 indexing. If so, then you *must* reject such naked constant sums as
3345 illegitimate addresses, so that none of them will be given to
3346 `PRINT_OPERAND_ADDRESS'.
3348 On some machines, whether a symbolic address is legitimate depends on the
3349 section that the address refers to. On these machines, define the macro
3350 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3351 then check for it here. When you see a `const', you will have to look
3352 inside it to find the `symbol_ref' in order to determine the section.
3354 The best way to modify the name string is by adding text to the beginning,
3355 with suitable punctuation to prevent any ambiguity. Allocate the new name
3356 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3357 remove and decode the added text and output the name accordingly, and define
3358 `(* targetm.strip_name_encoding)' to access the original name string.
3360 You can check the information stored here into the `symbol_ref' in the
3361 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3362 `PRINT_OPERAND_ADDRESS'. */
3365 frv_legitimate_address_p_1 (enum machine_mode mode,
3369 int allow_double_reg_p)
3373 HOST_WIDE_INT value;
3376 if (FRV_SYMBOL_REF_TLS_P (x))
3379 switch (GET_CODE (x))
3386 if (GET_CODE (x) != REG)
3392 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3398 if (GET_CODE (x0) != REG
3399 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3400 || GET_CODE (x1) != PLUS
3401 || ! rtx_equal_p (x0, XEXP (x1, 0))
3402 || GET_CODE (XEXP (x1, 1)) != REG
3403 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3410 /* 12-bit immediate */
3415 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3417 /* If we can't use load/store double operations, make sure we can
3418 address the second word. */
3419 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3420 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3429 if (GET_CODE (x0) == SUBREG)
3430 x0 = SUBREG_REG (x0);
3432 if (GET_CODE (x0) != REG)
3435 regno0 = REGNO (x0);
3436 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3439 switch (GET_CODE (x1))
3445 x1 = SUBREG_REG (x1);
3446 if (GET_CODE (x1) != REG)
3452 /* Do not allow reg+reg addressing for modes > 1 word if we
3453 can't depend on having move double instructions. */
3454 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3457 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3461 /* 12-bit immediate */
3466 value = INTVAL (x1);
3467 ret = IN_RANGE_P (value, -2048, 2047);
3469 /* If we can't use load/store double operations, make sure we can
3470 address the second word. */
3471 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3472 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3477 if (!condexec_p && got12_operand (x1, VOIDmode))
3485 if (TARGET_DEBUG_ADDR)
3487 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3488 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3489 (condexec_p) ? ", inside conditional code" : "");
3497 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3499 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3502 /* Given an ADDR, generate code to inline the PLT. */
3504 gen_inlined_tls_plt (rtx addr)
3507 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3510 dest = gen_reg_rtx (DImode);
3517 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3518 calll #gettlsoff(ADDR)@(gr8, gr0)
3520 emit_insn (gen_tls_lddi (dest, addr, picreg));
3527 sethi.p #gottlsdeschi(ADDR), gr8
3528 setlo #gottlsdesclo(ADDR), gr8
3529 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3530 calll #gettlsoff(ADDR)@(gr8, gr0)
3532 rtx reguse = gen_reg_rtx (Pmode);
3533 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3534 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3537 retval = gen_reg_rtx (Pmode);
3538 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3542 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3543 the destination address. */
3545 gen_tlsmoff (rtx addr, rtx reg)
3547 rtx dest = gen_reg_rtx (Pmode);
3551 /* sethi.p #tlsmoffhi(x), grA
3552 setlo #tlsmofflo(x), grA
3554 dest = gen_reg_rtx (Pmode);
3555 emit_insn (gen_tlsoff_hilo (dest, addr,
3556 GEN_INT (R_FRV_TLSMOFFHI)));
3557 dest = gen_rtx_PLUS (Pmode, dest, reg);
3561 /* addi grB, #tlsmoff12(x), grC
3563 ld/st @(grB, #tlsmoff12(x)), grC
3565 dest = gen_reg_rtx (Pmode);
3566 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3567 GEN_INT (R_FRV_TLSMOFF12)));
3572 /* Generate code for a TLS address. */
3574 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3576 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3577 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3581 case TLS_MODEL_INITIAL_EXEC:
3585 ldi @(gr15, #gottlsoff12(x)), gr5
3587 dest = gen_reg_rtx (Pmode);
3588 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3589 dest = gen_rtx_PLUS (Pmode, tp, dest);
3593 /* -fPIC or anything else.
3595 sethi.p #gottlsoffhi(x), gr14
3596 setlo #gottlsofflo(x), gr14
3597 ld #tlsoff(x)@(gr15, gr14), gr9
3599 rtx tmp = gen_reg_rtx (Pmode);
3600 dest = gen_reg_rtx (Pmode);
3601 emit_insn (gen_tlsoff_hilo (tmp, addr,
3602 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3604 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3605 dest = gen_rtx_PLUS (Pmode, tp, dest);
3608 case TLS_MODEL_LOCAL_DYNAMIC:
3612 if (TARGET_INLINE_PLT)
3613 retval = gen_inlined_tls_plt (GEN_INT (0));
3616 /* call #gettlsoff(0) */
3617 retval = gen_reg_rtx (Pmode);
3618 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3621 reg = gen_reg_rtx (Pmode);
3622 emit_insn (gen_rtx_SET (VOIDmode, reg,
3623 gen_rtx_PLUS (Pmode,
3626 dest = gen_tlsmoff (addr, reg);
3629 dest = gen_reg_rtx (Pmode);
3630 emit_insn (gen_tlsoff_hilo (dest, addr,
3631 GEN_INT (R_FRV_TLSMOFFHI)));
3632 dest = gen_rtx_PLUS (Pmode, dest, reg);
3636 case TLS_MODEL_LOCAL_EXEC:
3637 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3639 case TLS_MODEL_GLOBAL_DYNAMIC:
3643 if (TARGET_INLINE_PLT)
3644 retval = gen_inlined_tls_plt (addr);
3647 /* call #gettlsoff(x) */
3648 retval = gen_reg_rtx (Pmode);
3649 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3651 dest = gen_rtx_PLUS (Pmode, retval, tp);
3662 frv_legitimize_address (rtx x,
3663 rtx oldx ATTRIBUTE_UNUSED,
3664 enum machine_mode mode ATTRIBUTE_UNUSED)
3666 if (GET_CODE (x) == SYMBOL_REF)
3668 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3670 return frv_legitimize_tls_address (x, model);
3676 /* Test whether a local function descriptor is canonical, i.e.,
3677 whether we can use FUNCDESC_GOTOFF to compute the address of the
3681 frv_local_funcdesc_p (rtx fnx)
3684 enum symbol_visibility vis;
3687 if (! SYMBOL_REF_LOCAL_P (fnx))
3690 fn = SYMBOL_REF_DECL (fnx);
3695 vis = DECL_VISIBILITY (fn);
3697 if (vis == VISIBILITY_PROTECTED)
3698 /* Private function descriptors for protected functions are not
3699 canonical. Temporarily change the visibility to global. */
3700 vis = VISIBILITY_DEFAULT;
3701 else if (flag_shlib)
3702 /* If we're already compiling for a shared library (that, unlike
3703 executables, can't assume that the existence of a definition
3704 implies local binding), we can skip the re-testing. */
3707 ret = default_binds_local_p_1 (fn, flag_pic);
3709 DECL_VISIBILITY (fn) = vis;
3714 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3718 frv_gen_GPsym2reg (rtx dest, rtx src)
3720 tree gp = get_identifier ("_gp");
3721 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3723 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3727 unspec_got_name (int i)
3731 case R_FRV_GOT12: return "got12";
3732 case R_FRV_GOTHI: return "gothi";
3733 case R_FRV_GOTLO: return "gotlo";
3734 case R_FRV_FUNCDESC: return "funcdesc";
3735 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3736 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3737 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3738 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3739 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3740 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3741 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3742 case R_FRV_GOTOFF12: return "gotoff12";
3743 case R_FRV_GOTOFFHI: return "gotoffhi";
3744 case R_FRV_GOTOFFLO: return "gotofflo";
3745 case R_FRV_GPREL12: return "gprel12";
3746 case R_FRV_GPRELHI: return "gprelhi";
3747 case R_FRV_GPRELLO: return "gprello";
3748 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3749 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3750 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3751 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3752 case R_FRV_TLSMOFF12: return "tlsmoff12";
3753 case R_FRV_TLSDESCHI: return "tlsdeschi";
3754 case R_FRV_TLSDESCLO: return "tlsdesclo";
3755 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3756 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3757 default: gcc_unreachable ();
3761 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3762 is added inside the relocation operator. */
3765 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3767 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3768 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3769 fputs (")", stream);
3772 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3773 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3774 otherwise return ORIG_X. */
3777 frv_find_base_term (rtx x)
3779 struct frv_unspec unspec;
3781 if (frv_const_unspec_p (x, &unspec)
3782 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3783 return plus_constant (unspec.symbol, unspec.offset);
3788 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3789 the operand is used by a predicated instruction. */
3792 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3794 return ((GET_MODE (op) == mode || mode == VOIDmode)
3795 && GET_CODE (op) == MEM
3796 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3797 reload_completed, condexec_p, FALSE));
3801 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3803 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3804 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3810 rvrtx = operands[0];
3814 addr = XEXP (operands[0], 0);
3816 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3817 any calls that would involve a PLT, but can't tell, since we
3818 don't know whether an extern function is going to be provided by
3819 a separate translation unit or imported from a separate module.
3820 When compiling for shared libraries, if the function has default
3821 visibility, we assume it's overridable, so we inline the PLT, but
3822 for executables, we don't really have a way to make a good
3823 decision: a function is as likely to be imported from a shared
3824 library as it is to be defined in the executable itself. We
3825 assume executables will get global functions defined locally,
3826 whereas shared libraries will have them potentially overridden,
3827 so we only inline PLTs when compiling for shared libraries.
3829 In order to mark a function as local to a shared library, any
3830 non-default visibility attribute suffices. Unfortunately,
3831 there's no simple way to tag a function declaration as ``in a
3832 different module'', which we could then use to trigger PLT
3833 inlining on executables. There's -minline-plt, but it affects
3834 all external functions, so one would have to also mark function
3835 declarations available in the same module with non-default
3836 visibility, which is advantageous in itself. */
3837 if (GET_CODE (addr) == SYMBOL_REF
3838 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3842 dest = gen_reg_rtx (SImode);
3844 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3845 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3847 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3848 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3850 crtl->uses_pic_offset_table = TRUE;
3853 else if (GET_CODE (addr) == SYMBOL_REF)
3855 /* These are always either local, or handled through a local
3858 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3859 operands[2], picreg, lr);
3861 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3865 else if (! ldd_address_operand (addr, Pmode))
3866 addr = force_reg (Pmode, addr);
3868 picreg = gen_reg_rtx (DImode);
3869 emit_insn (gen_movdi_ldd (picreg, addr));
3871 if (sibcall && ret_value)
3872 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3874 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3876 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3878 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3882 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3883 process these separately from any offsets, such that we add any
3884 offsets to the function descriptor (the actual pointer), not to the
3885 function address. */
3888 frv_function_symbol_referenced_p (rtx x)
3894 if (GET_CODE (x) == SYMBOL_REF)
3895 return SYMBOL_REF_FUNCTION_P (x);
3897 length = GET_RTX_LENGTH (GET_CODE (x));
3898 format = GET_RTX_FORMAT (GET_CODE (x));
3900 for (j = 0; j < length; ++j)
3905 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3911 if (XVEC (x, j) != 0)
3914 for (k = 0; k < XVECLEN (x, j); ++k)
3915 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3921 /* Nothing to do. */
3929 /* Return true if the memory operand is one that can be conditionally
3933 condexec_memory_operand (rtx op, enum machine_mode mode)
3935 enum machine_mode op_mode = GET_MODE (op);
3938 if (mode != VOIDmode && op_mode != mode)
3953 if (GET_CODE (op) != MEM)
3956 addr = XEXP (op, 0);
3957 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3960 /* Return true if the bare return instruction can be used outside of the
3961 epilog code. For frv, we only do it if there was no stack allocation. */
3964 direct_return_p (void)
3968 if (!reload_completed)
3971 info = frv_stack_info ();
3972 return (info->total_size == 0);
3977 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3979 if (GET_CODE (src) == SYMBOL_REF)
3981 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3983 src = frv_legitimize_tls_address (src, model);
3989 if (frv_emit_movsi (dest, src))
3998 if (!reload_in_progress
3999 && !reload_completed
4000 && !register_operand (dest, mode)
4001 && !reg_or_0_operand (src, mode))
4002 src = copy_to_mode_reg (mode, src);
4009 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4012 /* Emit code to handle a MOVSI, adding in the small data register or pic
4013 register if needed to load up addresses. Return TRUE if the appropriate
4014 instructions are emitted. */
4017 frv_emit_movsi (rtx dest, rtx src)
4019 int base_regno = -1;
4022 struct frv_unspec old_unspec;
4024 if (!reload_in_progress
4025 && !reload_completed
4026 && !register_operand (dest, SImode)
4027 && (!reg_or_0_operand (src, SImode)
4028 /* Virtual registers will almost always be replaced by an
4029 add instruction, so expose this to CSE by copying to
4030 an intermediate register. */
4031 || (GET_CODE (src) == REG
4032 && IN_RANGE_P (REGNO (src),
4033 FIRST_VIRTUAL_REGISTER,
4034 LAST_VIRTUAL_REGISTER))))
4036 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4040 /* Explicitly add in the PIC or small data register if needed. */
4041 switch (GET_CODE (src))
4050 /* Using GPREL12, we use a single GOT entry for all symbols
4051 in read-only sections, but trade sequences such as:
4053 sethi #gothi(label), gr#
4054 setlo #gotlo(label), gr#
4059 ld @(gr15,#got12(_gp)), gr#
4060 sethi #gprelhi(label), gr##
4061 setlo #gprello(label), gr##
4064 We may often be able to share gr# for multiple
4065 computations of GPREL addresses, and we may often fold
4066 the final add into the pair of registers of a load or
4067 store instruction, so it's often profitable. Even when
4068 optimizing for size, we're trading a GOT entry for an
4069 additional instruction, which trades GOT space
4070 (read-write) for code size (read-only, shareable), as
4071 long as the symbol is not used in more than two different
4074 With -fpie/-fpic, we'd be trading a single load for a
4075 sequence of 4 instructions, because the offset of the
4076 label can't be assumed to be addressable with 12 bits, so
4077 we don't do this. */
4078 if (TARGET_GPREL_RO)
4079 unspec = R_FRV_GPREL12;
4081 unspec = R_FRV_GOT12;
4084 base_regno = PIC_REGNO;
4089 if (frv_const_unspec_p (src, &old_unspec))
4092 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4095 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4096 emit_move_insn (dest, src);
4101 sym = XEXP (sym, 0);
4102 if (GET_CODE (sym) == PLUS
4103 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4104 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4105 sym = XEXP (sym, 0);
4106 if (GET_CODE (sym) == SYMBOL_REF)
4108 else if (GET_CODE (sym) == LABEL_REF)
4111 goto handle_whatever;
4119 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4123 src = frv_legitimize_tls_address (src, model);
4124 emit_move_insn (dest, src);
4128 if (SYMBOL_REF_FUNCTION_P (sym))
4130 if (frv_local_funcdesc_p (sym))
4131 unspec = R_FRV_FUNCDESC_GOTOFF12;
4133 unspec = R_FRV_FUNCDESC_GOT12;
4137 if (CONSTANT_POOL_ADDRESS_P (sym))
4138 switch (GET_CODE (get_pool_constant (sym)))
4145 unspec = R_FRV_GOTOFF12;
4150 if (TARGET_GPREL_RO)
4151 unspec = R_FRV_GPREL12;
4153 unspec = R_FRV_GOT12;
4156 else if (SYMBOL_REF_LOCAL_P (sym)
4157 && !SYMBOL_REF_EXTERNAL_P (sym)
4158 && SYMBOL_REF_DECL (sym)
4159 && (!DECL_P (SYMBOL_REF_DECL (sym))
4160 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4162 tree decl = SYMBOL_REF_DECL (sym);
4163 tree init = TREE_CODE (decl) == VAR_DECL
4164 ? DECL_INITIAL (decl)
4165 : TREE_CODE (decl) == CONSTRUCTOR
4168 bool named_section, readonly;
4170 if (init && init != error_mark_node)
4171 reloc = compute_reloc_for_constant (init);
4173 named_section = TREE_CODE (decl) == VAR_DECL
4174 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4175 readonly = decl_readonly_section (decl, reloc);
4178 unspec = R_FRV_GOT12;
4180 unspec = R_FRV_GOTOFF12;
4181 else if (readonly && TARGET_GPREL_RO)
4182 unspec = R_FRV_GPREL12;
4184 unspec = R_FRV_GOT12;
4187 unspec = R_FRV_GOT12;
4191 else if (SYMBOL_REF_SMALL_P (sym))
4192 base_regno = SDA_BASE_REG;
4195 base_regno = PIC_REGNO;
4200 if (base_regno >= 0)
4202 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4203 emit_insn (gen_symGOTOFF2reg (dest, src,
4204 gen_rtx_REG (Pmode, base_regno),
4205 GEN_INT (R_FRV_GPREL12)));
4207 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4208 gen_rtx_REG (Pmode, base_regno),
4209 GEN_INT (R_FRV_GPREL12)));
4210 if (base_regno == PIC_REGNO)
4211 crtl->uses_pic_offset_table = TRUE;
4219 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4220 new uses of it once reload has begun. */
4221 gcc_assert (!reload_in_progress && !reload_completed);
4225 case R_FRV_GOTOFF12:
4226 if (!frv_small_data_reloc_p (sym, unspec))
4227 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4230 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4233 if (!frv_small_data_reloc_p (sym, unspec))
4234 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4237 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4239 case R_FRV_FUNCDESC_GOTOFF12:
4241 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4244 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4248 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4251 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4255 crtl->uses_pic_offset_table = TRUE;
4264 /* Return a string to output a single word move. */
4267 output_move_single (rtx operands[], rtx insn)
4269 rtx dest = operands[0];
4270 rtx src = operands[1];
4272 if (GET_CODE (dest) == REG)
4274 int dest_regno = REGNO (dest);
4275 enum machine_mode mode = GET_MODE (dest);
4277 if (GPR_P (dest_regno))
4279 if (GET_CODE (src) == REG)
4281 /* gpr <- some sort of register */
4282 int src_regno = REGNO (src);
4284 if (GPR_P (src_regno))
4285 return "mov %1, %0";
4287 else if (FPR_P (src_regno))
4288 return "movfg %1, %0";
4290 else if (SPR_P (src_regno))
4291 return "movsg %1, %0";
4294 else if (GET_CODE (src) == MEM)
4303 return "ldsb%I1%U1 %M1,%0";
4306 return "ldsh%I1%U1 %M1,%0";
4310 return "ld%I1%U1 %M1, %0";
4314 else if (GET_CODE (src) == CONST_INT
4315 || GET_CODE (src) == CONST_DOUBLE)
4317 /* gpr <- integer/floating constant */
4318 HOST_WIDE_INT value;
4320 if (GET_CODE (src) == CONST_INT)
4321 value = INTVAL (src);
4323 else if (mode == SFmode)
4328 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4329 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4334 value = CONST_DOUBLE_LOW (src);
4336 if (IN_RANGE_P (value, -32768, 32767))
4337 return "setlos %1, %0";
4342 else if (GET_CODE (src) == SYMBOL_REF
4343 || GET_CODE (src) == LABEL_REF
4344 || GET_CODE (src) == CONST)
4350 else if (FPR_P (dest_regno))
4352 if (GET_CODE (src) == REG)
4354 /* fpr <- some sort of register */
4355 int src_regno = REGNO (src);
4357 if (GPR_P (src_regno))
4358 return "movgf %1, %0";
4360 else if (FPR_P (src_regno))
4362 if (TARGET_HARD_FLOAT)
4363 return "fmovs %1, %0";
4365 return "mor %1, %1, %0";
4369 else if (GET_CODE (src) == MEM)
4378 return "ldbf%I1%U1 %M1,%0";
4381 return "ldhf%I1%U1 %M1,%0";
4385 return "ldf%I1%U1 %M1, %0";
4389 else if (ZERO_P (src))
4390 return "movgf %., %0";
4393 else if (SPR_P (dest_regno))
4395 if (GET_CODE (src) == REG)
4397 /* spr <- some sort of register */
4398 int src_regno = REGNO (src);
4400 if (GPR_P (src_regno))
4401 return "movgs %1, %0";
4403 else if (ZERO_P (src))
4404 return "movgs %., %0";
4408 else if (GET_CODE (dest) == MEM)
4410 if (GET_CODE (src) == REG)
4412 int src_regno = REGNO (src);
4413 enum machine_mode mode = GET_MODE (dest);
4415 if (GPR_P (src_regno))
4423 return "stb%I0%U0 %1, %M0";
4426 return "sth%I0%U0 %1, %M0";
4430 return "st%I0%U0 %1, %M0";
4434 else if (FPR_P (src_regno))
4442 return "stbf%I0%U0 %1, %M0";
4445 return "sthf%I0%U0 %1, %M0";
4449 return "stf%I0%U0 %1, %M0";
4454 else if (ZERO_P (src))
4456 switch (GET_MODE (dest))
4462 return "stb%I0%U0 %., %M0";
4465 return "sth%I0%U0 %., %M0";
4469 return "st%I0%U0 %., %M0";
4474 fatal_insn ("bad output_move_single operand", insn);
4479 /* Return a string to output a double word move. */
4482 output_move_double (rtx operands[], rtx insn)
4484 rtx dest = operands[0];
4485 rtx src = operands[1];
4486 enum machine_mode mode = GET_MODE (dest);
4488 if (GET_CODE (dest) == REG)
4490 int dest_regno = REGNO (dest);
4492 if (GPR_P (dest_regno))
4494 if (GET_CODE (src) == REG)
4496 /* gpr <- some sort of register */
4497 int src_regno = REGNO (src);
4499 if (GPR_P (src_regno))
4502 else if (FPR_P (src_regno))
4504 if (((dest_regno - GPR_FIRST) & 1) == 0
4505 && ((src_regno - FPR_FIRST) & 1) == 0)
4506 return "movfgd %1, %0";
4512 else if (GET_CODE (src) == MEM)
4515 if (dbl_memory_one_insn_operand (src, mode))
4516 return "ldd%I1%U1 %M1, %0";
4521 else if (GET_CODE (src) == CONST_INT
4522 || GET_CODE (src) == CONST_DOUBLE)
4526 else if (FPR_P (dest_regno))
4528 if (GET_CODE (src) == REG)
4530 /* fpr <- some sort of register */
4531 int src_regno = REGNO (src);
4533 if (GPR_P (src_regno))
4535 if (((dest_regno - FPR_FIRST) & 1) == 0
4536 && ((src_regno - GPR_FIRST) & 1) == 0)
4537 return "movgfd %1, %0";
4542 else if (FPR_P (src_regno))
4545 && ((dest_regno - FPR_FIRST) & 1) == 0
4546 && ((src_regno - FPR_FIRST) & 1) == 0)
4547 return "fmovd %1, %0";
4553 else if (GET_CODE (src) == MEM)
4556 if (dbl_memory_one_insn_operand (src, mode))
4557 return "lddf%I1%U1 %M1, %0";
4562 else if (ZERO_P (src))
4567 else if (GET_CODE (dest) == MEM)
4569 if (GET_CODE (src) == REG)
4571 int src_regno = REGNO (src);
4573 if (GPR_P (src_regno))
4575 if (((src_regno - GPR_FIRST) & 1) == 0
4576 && dbl_memory_one_insn_operand (dest, mode))
4577 return "std%I0%U0 %1, %M0";
4582 if (FPR_P (src_regno))
4584 if (((src_regno - FPR_FIRST) & 1) == 0
4585 && dbl_memory_one_insn_operand (dest, mode))
4586 return "stdf%I0%U0 %1, %M0";
4592 else if (ZERO_P (src))
4594 if (dbl_memory_one_insn_operand (dest, mode))
4595 return "std%I0%U0 %., %M0";
4601 fatal_insn ("bad output_move_double operand", insn);
4606 /* Return a string to output a single word conditional move.
4607 Operand0 -- EQ/NE of ccr register and 0
4608 Operand1 -- CCR register
4609 Operand2 -- destination
4610 Operand3 -- source */
4613 output_condmove_single (rtx operands[], rtx insn)
4615 rtx dest = operands[2];
4616 rtx src = operands[3];
4618 if (GET_CODE (dest) == REG)
4620 int dest_regno = REGNO (dest);
4621 enum machine_mode mode = GET_MODE (dest);
4623 if (GPR_P (dest_regno))
4625 if (GET_CODE (src) == REG)
4627 /* gpr <- some sort of register */
4628 int src_regno = REGNO (src);
4630 if (GPR_P (src_regno))
4631 return "cmov %z3, %2, %1, %e0";
4633 else if (FPR_P (src_regno))
4634 return "cmovfg %3, %2, %1, %e0";
4637 else if (GET_CODE (src) == MEM)
4646 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4649 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4653 return "cld%I3%U3 %M3, %2, %1, %e0";
4657 else if (ZERO_P (src))
4658 return "cmov %., %2, %1, %e0";
4661 else if (FPR_P (dest_regno))
4663 if (GET_CODE (src) == REG)
4665 /* fpr <- some sort of register */
4666 int src_regno = REGNO (src);
4668 if (GPR_P (src_regno))
4669 return "cmovgf %3, %2, %1, %e0";
4671 else if (FPR_P (src_regno))
4673 if (TARGET_HARD_FLOAT)
4674 return "cfmovs %3,%2,%1,%e0";
4676 return "cmor %3, %3, %2, %1, %e0";
4680 else if (GET_CODE (src) == MEM)
4683 if (mode == SImode || mode == SFmode)
4684 return "cldf%I3%U3 %M3, %2, %1, %e0";
4687 else if (ZERO_P (src))
4688 return "cmovgf %., %2, %1, %e0";
4692 else if (GET_CODE (dest) == MEM)
4694 if (GET_CODE (src) == REG)
4696 int src_regno = REGNO (src);
4697 enum machine_mode mode = GET_MODE (dest);
4699 if (GPR_P (src_regno))
4707 return "cstb%I2%U2 %3, %M2, %1, %e0";
4710 return "csth%I2%U2 %3, %M2, %1, %e0";
4714 return "cst%I2%U2 %3, %M2, %1, %e0";
4718 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4719 return "cstf%I2%U2 %3, %M2, %1, %e0";
4722 else if (ZERO_P (src))
4724 enum machine_mode mode = GET_MODE (dest);
4731 return "cstb%I2%U2 %., %M2, %1, %e0";
4734 return "csth%I2%U2 %., %M2, %1, %e0";
4738 return "cst%I2%U2 %., %M2, %1, %e0";
4743 fatal_insn ("bad output_condmove_single operand", insn);
4748 /* Emit the appropriate code to do a comparison, returning the register the
4749 comparison was done it. */
4752 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4754 enum machine_mode cc_mode;
4757 /* Floating point doesn't have comparison against a constant. */
4758 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4759 op1 = force_reg (GET_MODE (op0), op1);
4761 /* Possibly disable using anything but a fixed register in order to work
4762 around cse moving comparisons past function calls. */
4763 cc_mode = SELECT_CC_MODE (test, op0, op1);
4764 cc_reg = ((TARGET_ALLOC_CC)
4765 ? gen_reg_rtx (cc_mode)
4766 : gen_rtx_REG (cc_mode,
4767 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4769 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4770 gen_rtx_COMPARE (cc_mode, op0, op1)));
4776 /* Emit code for a conditional branch.
4777 XXX: I originally wanted to add a clobber of a CCR register to use in
4778 conditional execution, but that confuses the rest of the compiler. */
4781 frv_emit_cond_branch (rtx operands[])
4786 enum rtx_code test = GET_CODE (operands[0]);
4787 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4788 enum machine_mode cc_mode = GET_MODE (cc_reg);
4790 /* Branches generate:
4792 (if_then_else (<test>, <cc_reg>, (const_int 0))
4793 (label_ref <branch_label>)
4795 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4796 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4797 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4798 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4803 /* Emit code to set a gpr to 1/0 based on a comparison. */
4806 frv_emit_scc (rtx operands[])
4812 enum rtx_code test = GET_CODE (operands[1]);
4813 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4815 /* SCC instructions generate:
4816 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4817 (clobber (<ccr_reg>))]) */
4818 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4819 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4821 cr_reg = ((TARGET_ALLOC_CC)
4822 ? gen_reg_rtx (CC_CCRmode)
4823 : gen_rtx_REG (CC_CCRmode,
4824 ((GET_MODE (cc_reg) == CC_FPmode)
4828 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4829 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4834 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4835 the separate insns. */
4838 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4844 /* Set the appropriate CCR bit. */
4845 emit_insn (gen_rtx_SET (VOIDmode,
4847 gen_rtx_fmt_ee (GET_CODE (test),
4852 /* Move the value into the destination. */
4853 emit_move_insn (dest, GEN_INT (value));
4855 /* Move 0 into the destination if the test failed */
4856 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4857 gen_rtx_EQ (GET_MODE (cr_reg),
4860 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4862 /* Finish up, return sequence. */
4869 /* Emit the code for a conditional move, return TRUE if we could do the
4873 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4880 enum rtx_code test = GET_CODE (test_rtx);
4881 rtx cc_reg = frv_emit_comparison (test,
4882 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4883 enum machine_mode cc_mode = GET_MODE (cc_reg);
4885 /* Conditional move instructions generate:
4886 (parallel [(set <target>
4887 (if_then_else (<test> <cc_reg> (const_int 0))
4890 (clobber (<ccr_reg>))]) */
4892 /* Handle various cases of conditional move involving two constants. */
4893 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4895 HOST_WIDE_INT value1 = INTVAL (src1);
4896 HOST_WIDE_INT value2 = INTVAL (src2);
4898 /* Having 0 as one of the constants can be done by loading the other
4899 constant, and optionally moving in gr0. */
4900 if (value1 == 0 || value2 == 0)
4903 /* If the first value is within an addi range and also the difference
4904 between the two fits in an addi's range, load up the difference, then
4905 conditionally move in 0, and then unconditionally add the first
4907 else if (IN_RANGE_P (value1, -2048, 2047)
4908 && IN_RANGE_P (value2 - value1, -2048, 2047))
4911 /* If neither condition holds, just force the constant into a
4915 src1 = force_reg (GET_MODE (dest), src1);
4916 src2 = force_reg (GET_MODE (dest), src2);
4920 /* If one value is a register, insure the other value is either 0 or a
4924 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4925 src1 = force_reg (GET_MODE (dest), src1);
4927 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4928 src2 = force_reg (GET_MODE (dest), src2);
4931 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4932 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4934 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4936 cr_reg = ((TARGET_ALLOC_CC)
4937 ? gen_reg_rtx (CC_CCRmode)
4938 : gen_rtx_REG (CC_CCRmode,
4939 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4941 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4942 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4947 /* Split a conditional move into constituent parts, returning a SEQUENCE
4948 containing all of the insns. */
4951 frv_split_cond_move (rtx operands[])
4953 rtx dest = operands[0];
4954 rtx test = operands[1];
4955 rtx cc_reg = operands[2];
4956 rtx src1 = operands[3];
4957 rtx src2 = operands[4];
4958 rtx cr_reg = operands[5];
4960 enum machine_mode cr_mode = GET_MODE (cr_reg);
4964 /* Set the appropriate CCR bit. */
4965 emit_insn (gen_rtx_SET (VOIDmode,
4967 gen_rtx_fmt_ee (GET_CODE (test),
4972 /* Handle various cases of conditional move involving two constants. */
4973 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4975 HOST_WIDE_INT value1 = INTVAL (src1);
4976 HOST_WIDE_INT value2 = INTVAL (src2);
4978 /* Having 0 as one of the constants can be done by loading the other
4979 constant, and optionally moving in gr0. */
4982 emit_move_insn (dest, src2);
4983 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4984 gen_rtx_NE (cr_mode, cr_reg,
4986 gen_rtx_SET (VOIDmode, dest, src1)));
4989 else if (value2 == 0)
4991 emit_move_insn (dest, src1);
4992 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4993 gen_rtx_EQ (cr_mode, cr_reg,
4995 gen_rtx_SET (VOIDmode, dest, src2)));
4998 /* If the first value is within an addi range and also the difference
4999 between the two fits in an addi's range, load up the difference, then
5000 conditionally move in 0, and then unconditionally add the first
5002 else if (IN_RANGE_P (value1, -2048, 2047)
5003 && IN_RANGE_P (value2 - value1, -2048, 2047))
5005 rtx dest_si = ((GET_MODE (dest) == SImode)
5007 : gen_rtx_SUBREG (SImode, dest, 0));
5009 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5010 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5011 gen_rtx_NE (cr_mode, cr_reg,
5013 gen_rtx_SET (VOIDmode, dest_si,
5015 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5023 /* Emit the conditional move for the test being true if needed. */
5024 if (! rtx_equal_p (dest, src1))
5025 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5026 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5027 gen_rtx_SET (VOIDmode, dest, src1)));
5029 /* Emit the conditional move for the test being false if needed. */
5030 if (! rtx_equal_p (dest, src2))
5031 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5032 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5033 gen_rtx_SET (VOIDmode, dest, src2)));
5036 /* Finish up, return sequence. */
5043 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5044 memory location that is not known to be dword-aligned. */
5046 frv_split_double_load (rtx dest, rtx source)
5048 int regno = REGNO (dest);
5049 rtx dest1 = gen_highpart (SImode, dest);
5050 rtx dest2 = gen_lowpart (SImode, dest);
5051 rtx address = XEXP (source, 0);
5053 /* If the address is pre-modified, load the lower-numbered register
5054 first, then load the other register using an integer offset from
5055 the modified base register. This order should always be safe,
5056 since the pre-modification cannot affect the same registers as the
5059 The situation for other loads is more complicated. Loading one
5060 of the registers could affect the value of ADDRESS, so we must
5061 be careful which order we do them in. */
5062 if (GET_CODE (address) == PRE_MODIFY
5063 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5065 /* It is safe to load the lower-numbered register first. */
5066 emit_move_insn (dest1, change_address (source, SImode, NULL));
5067 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5071 /* ADDRESS is not pre-modified and the address depends on the
5072 lower-numbered register. Load the higher-numbered register
5074 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5075 emit_move_insn (dest1, change_address (source, SImode, NULL));
5079 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5080 and SOURCE is either a double register or the constant zero. */
5082 frv_split_double_store (rtx dest, rtx source)
5084 rtx dest1 = change_address (dest, SImode, NULL);
5085 rtx dest2 = frv_index_memory (dest, SImode, 1);
5086 if (ZERO_P (source))
5088 emit_move_insn (dest1, CONST0_RTX (SImode));
5089 emit_move_insn (dest2, CONST0_RTX (SImode));
5093 emit_move_insn (dest1, gen_highpart (SImode, source));
5094 emit_move_insn (dest2, gen_lowpart (SImode, source));
5099 /* Split a min/max operation returning a SEQUENCE containing all of the
5103 frv_split_minmax (rtx operands[])
5105 rtx dest = operands[0];
5106 rtx minmax = operands[1];
5107 rtx src1 = operands[2];
5108 rtx src2 = operands[3];
5109 rtx cc_reg = operands[4];
5110 rtx cr_reg = operands[5];
5112 enum rtx_code test_code;
5113 enum machine_mode cr_mode = GET_MODE (cr_reg);
5117 /* Figure out which test to use. */
5118 switch (GET_CODE (minmax))
5123 case SMIN: test_code = LT; break;
5124 case SMAX: test_code = GT; break;
5125 case UMIN: test_code = LTU; break;
5126 case UMAX: test_code = GTU; break;
5129 /* Issue the compare instruction. */
5130 emit_insn (gen_rtx_SET (VOIDmode,
5132 gen_rtx_COMPARE (GET_MODE (cc_reg),
5135 /* Set the appropriate CCR bit. */
5136 emit_insn (gen_rtx_SET (VOIDmode,
5138 gen_rtx_fmt_ee (test_code,
5143 /* If are taking the min/max of a nonzero constant, load that first, and
5144 then do a conditional move of the other value. */
5145 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5147 gcc_assert (!rtx_equal_p (dest, src1));
5149 emit_move_insn (dest, src2);
5150 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5151 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5152 gen_rtx_SET (VOIDmode, dest, src1)));
5155 /* Otherwise, do each half of the move. */
5158 /* Emit the conditional move for the test being true if needed. */
5159 if (! rtx_equal_p (dest, src1))
5160 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5161 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5162 gen_rtx_SET (VOIDmode, dest, src1)));
5164 /* Emit the conditional move for the test being false if needed. */
5165 if (! rtx_equal_p (dest, src2))
5166 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5167 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5168 gen_rtx_SET (VOIDmode, dest, src2)));
5171 /* Finish up, return sequence. */
5178 /* Split an integer abs operation returning a SEQUENCE containing all of the
5182 frv_split_abs (rtx operands[])
5184 rtx dest = operands[0];
5185 rtx src = operands[1];
5186 rtx cc_reg = operands[2];
5187 rtx cr_reg = operands[3];
5192 /* Issue the compare < 0 instruction. */
5193 emit_insn (gen_rtx_SET (VOIDmode,
5195 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5197 /* Set the appropriate CCR bit. */
5198 emit_insn (gen_rtx_SET (VOIDmode,
5200 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5202 /* Emit the conditional negate if the value is negative. */
5203 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5204 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5205 gen_negsi2 (dest, src)));
5207 /* Emit the conditional move for the test being false if needed. */
5208 if (! rtx_equal_p (dest, src))
5209 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5210 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5211 gen_rtx_SET (VOIDmode, dest, src)));
5213 /* Finish up, return sequence. */
5220 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5221 register used in an insn. */
5224 frv_clear_registers_used (rtx *ptr, void *data)
5226 if (GET_CODE (*ptr) == REG)
5228 int regno = REGNO (*ptr);
5229 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5231 if (regno < FIRST_PSEUDO_REGISTER)
5233 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5235 while (regno < reg_max)
5237 CLEAR_HARD_REG_BIT (*p_regs, regno);
5247 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5249 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5250 initialize the static storage. */
5252 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5254 frv_ifcvt.added_insns_list = NULL_RTX;
5255 frv_ifcvt.cur_scratch_regs = 0;
5256 frv_ifcvt.num_nested_cond_exec = 0;
5257 frv_ifcvt.cr_reg = NULL_RTX;
5258 frv_ifcvt.nested_cc_reg = NULL_RTX;
5259 frv_ifcvt.extra_int_cr = NULL_RTX;
5260 frv_ifcvt.extra_fp_cr = NULL_RTX;
5261 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5265 /* Internal function to add a potential insn to the list of insns to be inserted
5266 if the conditional execution conversion is successful. */
5269 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5271 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5273 link->jump = before_p; /* Mark to add this before or after insn. */
5274 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5275 frv_ifcvt.added_insns_list);
5277 if (TARGET_DEBUG_COND_EXEC)
5280 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5281 (before_p) ? "before" : "after",
5282 (int)INSN_UID (insn));
5284 debug_rtx (pattern);
5289 /* A C expression to modify the code described by the conditional if
5290 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5291 FALSE_EXPR for converting if-then and if-then-else code to conditional
5292 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5293 tests cannot be converted. */
5296 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5298 basic_block test_bb = ce_info->test_bb; /* test basic block */
5299 basic_block then_bb = ce_info->then_bb; /* THEN */
5300 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5301 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5302 rtx true_expr = *p_true;
5306 enum machine_mode mode = GET_MODE (true_expr);
5310 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5312 rtx sub_cond_exec_reg;
5314 enum rtx_code code_true;
5315 enum rtx_code code_false;
5316 enum reg_class cc_class;
5317 enum reg_class cr_class;
5320 reg_set_iterator rsi;
5322 /* Make sure we are only dealing with hard registers. Also honor the
5323 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5325 if (!reload_completed || !TARGET_COND_EXEC
5326 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5329 /* Figure out which registers we can allocate for our own purposes. Only
5330 consider registers that are not preserved across function calls and are
5331 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5332 if we did not need to use them in reloading other registers. */
5333 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5334 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5335 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5336 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5337 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5339 /* If this is a nested IF, we need to discover whether the CC registers that
5340 are set/used inside of the block are used anywhere else. If not, we can
5341 change them to be the CC register that is paired with the CR register that
5342 controls the outermost IF block. */
5343 if (ce_info->pass > 1)
5345 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5346 for (j = CC_FIRST; j <= CC_LAST; j++)
5347 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5349 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5353 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5357 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5360 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5364 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5365 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5367 frv_ifcvt.added_insns_list = NULL_RTX;
5368 frv_ifcvt.cur_scratch_regs = 0;
5370 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5371 * sizeof (basic_block));
5377 /* Remove anything live at the beginning of the join block from being
5378 available for allocation. */
5379 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5381 if (regno < FIRST_PSEUDO_REGISTER)
5382 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5386 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5388 if (ce_info->num_multiple_test_blocks)
5390 basic_block multiple_test_bb = ce_info->last_test_bb;
5392 while (multiple_test_bb != test_bb)
5394 bb[num_bb++] = multiple_test_bb;
5395 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5399 /* Add in the THEN and ELSE blocks to be scanned. */
5400 bb[num_bb++] = then_bb;
5402 bb[num_bb++] = else_bb;
5404 sub_cond_exec_reg = NULL_RTX;
5405 frv_ifcvt.num_nested_cond_exec = 0;
5407 /* Scan all of the blocks for registers that must not be allocated. */
5408 for (j = 0; j < num_bb; j++)
5410 rtx last_insn = BB_END (bb[j]);
5411 rtx insn = BB_HEAD (bb[j]);
5415 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5416 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5418 (int) INSN_UID (BB_HEAD (bb[j])),
5419 (int) INSN_UID (BB_END (bb[j])));
5421 /* Anything live at the beginning of the block is obviously unavailable
5423 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5425 if (regno < FIRST_PSEUDO_REGISTER)
5426 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5429 /* Loop through the insns in the block. */
5432 /* Mark any new registers that are created as being unavailable for
5433 allocation. Also see if the CC register used in nested IFs can be
5439 int skip_nested_if = FALSE;
5441 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5442 (void *)&tmp_reg->regs);
5444 pattern = PATTERN (insn);
5445 if (GET_CODE (pattern) == COND_EXEC)
5447 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5449 if (reg != sub_cond_exec_reg)
5451 sub_cond_exec_reg = reg;
5452 frv_ifcvt.num_nested_cond_exec++;
5456 set = single_set_pattern (pattern);
5459 rtx dest = SET_DEST (set);
5460 rtx src = SET_SRC (set);
5462 if (GET_CODE (dest) == REG)
5464 int regno = REGNO (dest);
5465 enum rtx_code src_code = GET_CODE (src);
5467 if (CC_P (regno) && src_code == COMPARE)
5468 skip_nested_if = TRUE;
5470 else if (CR_P (regno)
5471 && (src_code == IF_THEN_ELSE
5472 || COMPARISON_P (src)))
5473 skip_nested_if = TRUE;
5477 if (! skip_nested_if)
5478 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5479 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5482 if (insn == last_insn)
5485 insn = NEXT_INSN (insn);
5489 /* If this is a nested if, rewrite the CC registers that are available to
5490 include the ones that can be rewritten, to increase the chance of being
5491 able to allocate a paired CC/CR register combination. */
5492 if (ce_info->pass > 1)
5494 for (j = CC_FIRST; j <= CC_LAST; j++)
5495 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5496 SET_HARD_REG_BIT (tmp_reg->regs, j);
5498 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5504 fprintf (dump_file, "Available GPRs: ");
5506 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5507 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5509 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5510 if (++num_gprs > GPR_TEMP_NUM+2)
5514 fprintf (dump_file, "%s\nAvailable CRs: ",
5515 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5517 for (j = CR_FIRST; j <= CR_LAST; j++)
5518 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5519 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5521 fputs ("\n", dump_file);
5523 if (ce_info->pass > 1)
5525 fprintf (dump_file, "Modifiable CCs: ");
5526 for (j = CC_FIRST; j <= CC_LAST; j++)
5527 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5528 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5530 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5531 frv_ifcvt.num_nested_cond_exec);
5535 /* Allocate the appropriate temporary condition code register. Try to
5536 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5537 that conditional cmp's can be done. */
5538 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5540 cr_class = ICR_REGS;
5541 cc_class = ICC_REGS;
5542 cc_first = ICC_FIRST;
5545 else if (mode == CC_FPmode)
5547 cr_class = FCR_REGS;
5548 cc_class = FCC_REGS;
5549 cc_first = FCC_FIRST;
5554 cc_first = cc_last = 0;
5555 cr_class = cc_class = NO_REGS;
5558 cc = XEXP (true_expr, 0);
5559 nested_cc = cr = NULL_RTX;
5560 if (cc_class != NO_REGS)
5562 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5563 so we can execute a csubcc/caddcc/cfcmps instruction. */
5566 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5568 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5570 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5571 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5573 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5574 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5577 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5578 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5588 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5595 "Will use %s for conditional execution, %s for nested comparisons\n",
5596 reg_names[ REGNO (cr)],
5597 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5599 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5600 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5601 bit being true. We don't do this for floating point, because of NaNs. */
5602 code = GET_CODE (true_expr);
5603 if (GET_MODE (cc) != CC_FPmode)
5605 code = reverse_condition (code);
5615 check_insn = gen_rtx_SET (VOIDmode, cr,
5616 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5618 /* Record the check insn to be inserted later. */
5619 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5621 /* Update the tests. */
5622 frv_ifcvt.cr_reg = cr;
5623 frv_ifcvt.nested_cc_reg = nested_cc;
5624 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5625 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5628 /* Fail, don't do this conditional execution. */
5631 *p_false = NULL_RTX;
5633 fprintf (dump_file, "Disabling this conditional execution.\n");
5639 /* A C expression to modify the code described by the conditional if
5640 information CE_INFO, for the basic block BB, possibly updating the tests in
5641 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5642 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5643 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5645 /* p_true and p_false are given expressions of the form:
5647 (and (eq:CC_CCR (reg:CC_CCR)
5653 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5658 rtx old_true = XEXP (*p_true, 0);
5659 rtx old_false = XEXP (*p_false, 0);
5660 rtx true_expr = XEXP (*p_true, 1);
5661 rtx false_expr = XEXP (*p_false, 1);
5664 rtx cr = XEXP (old_true, 0);
5666 rtx new_cr = NULL_RTX;
5667 rtx *p_new_cr = (rtx *)0;
5671 enum reg_class cr_class;
5672 enum machine_mode mode = GET_MODE (true_expr);
5673 rtx (*logical_func)(rtx, rtx, rtx);
5675 if (TARGET_DEBUG_COND_EXEC)
5678 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5679 ce_info->and_and_p ? "&&" : "||");
5681 debug_rtx (*p_true);
5683 fputs ("\nfalse insn:\n", stderr);
5684 debug_rtx (*p_false);
5687 if (!TARGET_MULTI_CE)
5690 if (GET_CODE (cr) != REG)
5693 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5695 cr_class = ICR_REGS;
5696 p_new_cr = &frv_ifcvt.extra_int_cr;
5698 else if (mode == CC_FPmode)
5700 cr_class = FCR_REGS;
5701 p_new_cr = &frv_ifcvt.extra_fp_cr;
5706 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5707 more &&/|| tests. */
5711 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5712 CC_CCRmode, TRUE, TRUE);
5717 if (ce_info->and_and_p)
5719 old_test = old_false;
5720 test_expr = true_expr;
5721 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5722 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5723 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5727 old_test = old_false;
5728 test_expr = false_expr;
5729 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5730 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5731 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5734 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5735 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5737 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5739 /* Now add the conditional check insn. */
5740 cc = XEXP (test_expr, 0);
5741 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5742 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5744 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5746 /* Add the new check insn to the list of check insns that need to be
5748 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5750 if (TARGET_DEBUG_COND_EXEC)
5752 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5755 debug_rtx (*p_true);
5757 fputs ("\nfalse insn:\n", stderr);
5758 debug_rtx (*p_false);
5764 *p_true = *p_false = NULL_RTX;
5766 /* If we allocated a CR register, release it. */
5769 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5770 *p_new_cr = NULL_RTX;
5773 if (TARGET_DEBUG_COND_EXEC)
5774 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5780 /* Return a register which will be loaded with a value if an IF block is
5781 converted to conditional execution. This is used to rewrite instructions
5782 that use constants to ones that just use registers. */
5785 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5787 int num_alloc = frv_ifcvt.cur_scratch_regs;
5791 /* We know gr0 == 0, so replace any errant uses. */
5792 if (value == const0_rtx)
5793 return gen_rtx_REG (SImode, GPR_FIRST);
5795 /* First search all registers currently loaded to see if we have an
5796 applicable constant. */
5797 if (CONSTANT_P (value)
5798 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5800 for (i = 0; i < num_alloc; i++)
5802 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5803 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5807 /* Have we exhausted the number of registers available? */
5808 if (num_alloc >= GPR_TEMP_NUM)
5811 fprintf (dump_file, "Too many temporary registers allocated\n");
5816 /* Allocate the new register. */
5817 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5821 fputs ("Could not find a scratch register\n", dump_file);
5826 frv_ifcvt.cur_scratch_regs++;
5827 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5831 if (GET_CODE (value) == CONST_INT)
5832 fprintf (dump_file, "Register %s will hold %ld\n",
5833 reg_names[ REGNO (reg)], (long)INTVAL (value));
5835 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5836 fprintf (dump_file, "Register %s will hold LR\n",
5837 reg_names[ REGNO (reg)]);
5840 fprintf (dump_file, "Register %s will hold a saved value\n",
5841 reg_names[ REGNO (reg)]);
5848 /* Update a MEM used in conditional code that might contain an offset to put
5849 the offset into a scratch register, so that the conditional load/store
5850 operations can be used. This function returns the original pointer if the
5851 MEM is valid to use in conditional code, NULL if we can't load up the offset
5852 into a temporary register, or the new MEM if we were successful. */
5855 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5857 rtx addr = XEXP (mem, 0);
5859 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5861 if (GET_CODE (addr) == PLUS)
5863 rtx addr_op0 = XEXP (addr, 0);
5864 rtx addr_op1 = XEXP (addr, 1);
5866 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5868 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5872 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5879 else if (CONSTANT_P (addr))
5880 addr = frv_ifcvt_load_value (addr, insn);
5885 if (addr == NULL_RTX)
5888 else if (XEXP (mem, 0) != addr)
5889 return change_address (mem, mode, addr);
5896 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5897 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5900 single_set_pattern (rtx pattern)
5905 if (GET_CODE (pattern) == COND_EXEC)
5906 pattern = COND_EXEC_CODE (pattern);
5908 if (GET_CODE (pattern) == SET)
5911 else if (GET_CODE (pattern) == PARALLEL)
5913 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5915 rtx sub = XVECEXP (pattern, 0, i);
5917 switch (GET_CODE (sub))
5941 /* A C expression to modify the code described by the conditional if
5942 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5943 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5944 insn cannot be converted to be executed conditionally. */
5947 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5951 rtx orig_ce_pattern = pattern;
5957 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5959 test = COND_EXEC_TEST (pattern);
5960 if (GET_CODE (test) == AND)
5962 rtx cr = frv_ifcvt.cr_reg;
5965 op0 = XEXP (test, 0);
5966 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5969 op1 = XEXP (test, 1);
5970 test_reg = XEXP (op1, 0);
5971 if (GET_CODE (test_reg) != REG)
5974 /* Is this the first nested if block in this sequence? If so, generate
5975 an andcr or andncr. */
5976 if (! frv_ifcvt.last_nested_if_cr)
5980 frv_ifcvt.last_nested_if_cr = test_reg;
5981 if (GET_CODE (op0) == NE)
5982 and_op = gen_andcr (test_reg, cr, test_reg);
5984 and_op = gen_andncr (test_reg, cr, test_reg);
5986 frv_ifcvt_add_insn (and_op, insn, TRUE);
5989 /* If this isn't the first statement in the nested if sequence, see if we
5990 are dealing with the same register. */
5991 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5994 COND_EXEC_TEST (pattern) = test = op1;
5997 /* If this isn't a nested if, reset state variables. */
6000 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6003 set = single_set_pattern (pattern);
6006 rtx dest = SET_DEST (set);
6007 rtx src = SET_SRC (set);
6008 enum machine_mode mode = GET_MODE (dest);
6010 /* Check for normal binary operators. */
6011 if (mode == SImode && ARITHMETIC_P (src))
6013 op0 = XEXP (src, 0);
6014 op1 = XEXP (src, 1);
6016 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6018 op1 = frv_ifcvt_load_value (op1, insn);
6020 COND_EXEC_CODE (pattern)
6021 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6029 /* For multiply by a constant, we need to handle the sign extending
6030 correctly. Add a USE of the value after the multiply to prevent flow
6031 from cratering because only one register out of the two were used. */
6032 else if (mode == DImode && GET_CODE (src) == MULT)
6034 op0 = XEXP (src, 0);
6035 op1 = XEXP (src, 1);
6036 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6038 op1 = frv_ifcvt_load_value (op1, insn);
6041 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6042 COND_EXEC_CODE (pattern)
6043 = gen_rtx_SET (VOIDmode, dest,
6044 gen_rtx_MULT (DImode, op0, op1));
6050 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6053 /* If we are just loading a constant created for a nested conditional
6054 execution statement, just load the constant without any conditional
6055 execution, since we know that the constant will not interfere with any
6057 else if (frv_ifcvt.scratch_insns_bitmap
6058 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6060 && REG_P (SET_DEST (set))
6061 /* We must not unconditionally set a scratch reg chosen
6062 for a nested if-converted block if its incoming
6063 value from the TEST block (or the result of the THEN
6064 branch) could/should propagate to the JOIN block.
6065 It suffices to test whether the register is live at
6066 the JOIN point: if it's live there, we can infer
6067 that we set it in the former JOIN block of the
6068 nested if-converted block (otherwise it wouldn't
6069 have been available as a scratch register), and it
6070 is either propagated through or set in the other
6071 conditional block. It's probably not worth trying
6072 to catch the latter case, and it could actually
6073 limit scheduling of the combined block quite
6076 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6077 REGNO (SET_DEST (set))))
6078 /* Similarly, we must not unconditionally set a reg
6079 used as scratch in the THEN branch if the same reg
6080 is live in the ELSE branch. */
6081 && (! ce_info->else_bb
6082 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6083 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6084 REGNO (SET_DEST (set))))))
6087 else if (mode == QImode || mode == HImode || mode == SImode
6090 int changed_p = FALSE;
6092 /* Check for just loading up a constant */
6093 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6095 src = frv_ifcvt_load_value (src, insn);
6102 /* See if we need to fix up stores */
6103 if (GET_CODE (dest) == MEM)
6105 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6110 else if (new_mem != dest)
6117 /* See if we need to fix up loads */
6118 if (GET_CODE (src) == MEM)
6120 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6125 else if (new_mem != src)
6132 /* If either src or destination changed, redo SET. */
6134 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6137 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6138 rewriting the CC register to be the same as the paired CC/CR register
6140 else if (mode == CC_CCRmode && COMPARISON_P (src))
6142 int regno = REGNO (XEXP (src, 0));
6145 if (ce_info->pass > 1
6146 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6147 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6149 src = gen_rtx_fmt_ee (GET_CODE (src),
6151 frv_ifcvt.nested_cc_reg,
6155 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6156 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6159 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6160 else if (ce_info->pass > 1
6161 && GET_CODE (dest) == REG
6162 && CC_P (REGNO (dest))
6163 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6164 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6166 && GET_CODE (src) == COMPARE)
6168 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6169 COND_EXEC_CODE (pattern)
6170 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6174 if (TARGET_DEBUG_COND_EXEC)
6176 rtx orig_pattern = PATTERN (insn);
6178 PATTERN (insn) = pattern;
6180 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6184 PATTERN (insn) = orig_pattern;
6190 if (TARGET_DEBUG_COND_EXEC)
6192 rtx orig_pattern = PATTERN (insn);
6194 PATTERN (insn) = orig_ce_pattern;
6196 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6200 PATTERN (insn) = orig_pattern;
6207 /* A C expression to perform any final machine dependent modifications in
6208 converting code to conditional execution in the code described by the
6209 conditional if information CE_INFO. */
6212 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6216 rtx p = frv_ifcvt.added_insns_list;
6219 /* Loop inserting the check insns. The last check insn is the first test,
6220 and is the appropriate place to insert constants. */
6225 rtx check_and_insert_insns = XEXP (p, 0);
6228 check_insn = XEXP (check_and_insert_insns, 0);
6229 existing_insn = XEXP (check_and_insert_insns, 1);
6232 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6233 the existing insn, otherwise it is to be inserted AFTER. */
6234 if (check_and_insert_insns->jump)
6236 emit_insn_before (check_insn, existing_insn);
6237 check_and_insert_insns->jump = 0;
6240 emit_insn_after (check_insn, existing_insn);
6242 free_EXPR_LIST_node (check_and_insert_insns);
6243 free_EXPR_LIST_node (old_p);
6245 while (p != NULL_RTX);
6247 /* Load up any constants needed into temp gprs */
6248 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6250 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6251 if (! frv_ifcvt.scratch_insns_bitmap)
6252 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6253 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6254 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6257 frv_ifcvt.added_insns_list = NULL_RTX;
6258 frv_ifcvt.cur_scratch_regs = 0;
6262 /* A C expression to cancel any machine dependent modifications in converting
6263 code to conditional execution in the code described by the conditional if
6264 information CE_INFO. */
6267 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6270 rtx p = frv_ifcvt.added_insns_list;
6272 /* Loop freeing up the EXPR_LIST's allocated. */
6273 while (p != NULL_RTX)
6275 rtx check_and_jump = XEXP (p, 0);
6279 free_EXPR_LIST_node (check_and_jump);
6280 free_EXPR_LIST_node (old_p);
6283 /* Release any temporary gprs allocated. */
6284 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6285 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6287 frv_ifcvt.added_insns_list = NULL_RTX;
6288 frv_ifcvt.cur_scratch_regs = 0;
6292 /* A C expression for the size in bytes of the trampoline, as an integer.
6296 setlo #0, <static_chain>
6298 sethi #0, <static_chain>
6299 jmpl @(gr0,<jmp_reg>) */
6302 frv_trampoline_size (void)
6305 /* Allocate room for the function descriptor and the lddi
6308 return 5 /* instructions */ * 4 /* instruction size. */;
6312 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6313 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6314 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6315 should be passed to the function when it is called.
6320 setlo #0, <static_chain>
6322 sethi #0, <static_chain>
6323 jmpl @(gr0,<jmp_reg>) */
6326 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
6328 rtx sc_reg = force_reg (Pmode, static_chain);
6330 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6333 GEN_INT (frv_trampoline_size ()), SImode,
6339 /* Many machines have some registers that cannot be copied directly to or from
6340 memory or even from other types of registers. An example is the `MQ'
6341 register, which on most machines, can only be copied to or from general
6342 registers, but not memory. Some machines allow copying all registers to and
6343 from memory, but require a scratch register for stores to some memory
6344 locations (e.g., those with symbolic address on the RT, and those with
6345 certain symbolic address on the SPARC when compiling PIC). In some cases,
6346 both an intermediate and a scratch register are required.
6348 You should define these macros to indicate to the reload phase that it may
6349 need to allocate at least one register for a reload in addition to the
6350 register to contain the data. Specifically, if copying X to a register
6351 RCLASS in MODE requires an intermediate register, you should define
6352 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6353 whose registers can be used as intermediate registers or scratch registers.
6355 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6356 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6357 largest register class required. If the requirements for input and output
6358 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6359 instead of defining both macros identically.
6361 The values returned by these macros are often `GENERAL_REGS'. Return
6362 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6363 to or from a register of RCLASS in MODE without requiring a scratch register.
6364 Do not define this macro if it would always return `NO_REGS'.
6366 If a scratch register is required (either with or without an intermediate
6367 register), you should define patterns for `reload_inM' or `reload_outM', as
6368 required.. These patterns, which will normally be implemented with a
6369 `define_expand', should be similar to the `movM' patterns, except that
6370 operand 2 is the scratch register.
6372 Define constraints for the reload register and scratch register that contain
6373 a single register class. If the original reload register (whose class is
6374 RCLASS) can meet the constraint given in the pattern, the value returned by
6375 these macros is used for the class of the scratch register. Otherwise, two
6376 additional reload registers are required. Their classes are obtained from
6377 the constraints in the insn pattern.
6379 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6380 either be in a hard register or in memory. Use `true_regnum' to find out;
6381 it will return -1 if the pseudo is in memory and the hard register number if
6382 it is in a register.
6384 These macros should not be used in the case where a particular class of
6385 registers can only be copied to memory and not to another class of
6386 registers. In that case, secondary reload registers are not needed and
6387 would not be helpful. Instead, a stack location must be used to perform the
6388 copy and the `movM' pattern should use memory as an intermediate storage.
6389 This case often occurs between floating-point and general registers. */
6392 frv_secondary_reload_class (enum reg_class rclass,
6393 enum machine_mode mode ATTRIBUTE_UNUSED,
6404 /* Accumulators/Accumulator guard registers need to go through floating
6410 if (x && GET_CODE (x) == REG)
6412 int regno = REGNO (x);
6414 if (ACC_P (regno) || ACCG_P (regno))
6419 /* Nonzero constants should be loaded into an FPR through a GPR. */
6423 if (x && CONSTANT_P (x) && !ZERO_P (x))
6429 /* All of these types need gpr registers. */
6441 /* The accumulators need fpr registers. */
6453 /* This hook exists to catch the case where secondary_reload_class() is
6454 called from init_reg_autoinc() in regclass.c - before the reload optabs
6455 have been initialised. */
6458 frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
6459 enum machine_mode reload_mode,
6460 secondary_reload_info * sri)
6462 enum reg_class rclass = NO_REGS;
6464 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6466 sri->icode = sri->prev_sri->t_icode;
6470 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6472 if (rclass != NO_REGS)
6474 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
6475 : reload_out_optab[(int) reload_mode]);
6478 /* This happens when then the reload_[in|out]_optabs have
6479 not been initialised. */
6480 sri->t_icode = CODE_FOR_nothing;
6485 /* Fall back to the default secondary reload handler. */
6486 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6490 /* A C expression whose value is nonzero if pseudos that have been assigned to
6491 registers of class RCLASS would likely be spilled because registers of RCLASS
6492 are needed for spill registers.
6494 The default value of this macro returns 1 if RCLASS has exactly one register
6495 and zero otherwise. On most machines, this default should be used. Only
6496 define this macro to some other expression if pseudo allocated by
6497 `local-alloc.c' end up in memory because their hard registers were needed
6498 for spill registers. If this macro returns nonzero for those classes, those
6499 pseudos will only be allocated by `global.c', which knows how to reallocate
6500 the pseudo to another register. If there would not be another register
6501 available for reallocation, you should not change the definition of this
6502 macro since the only effect of such a definition would be to slow down
6503 register allocation. */
6506 frv_class_likely_spilled_p (enum reg_class rclass)
6516 case FDPIC_FPTR_REGS:
6538 /* An expression for the alignment of a structure field FIELD if the
6539 alignment computed in the usual way is COMPUTED. GCC uses this
6540 value instead of the value in `BIGGEST_ALIGNMENT' or
6541 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6543 /* The definition type of the bit field data is either char, short, long or
6544 long long. The maximum bit size is the number of bits of its own type.
6546 The bit field data is assigned to a storage unit that has an adequate size
6547 for bit field data retention and is located at the smallest address.
6549 Consecutive bit field data are packed at consecutive bits having the same
6550 storage unit, with regard to the type, beginning with the MSB and continuing
6553 If a field to be assigned lies over a bit field type boundary, its
6554 assignment is completed by aligning it with a boundary suitable for the
6557 When a bit field having a bit length of 0 is declared, it is forcibly
6558 assigned to the next storage unit.
6571 &x 00000000 00000000 00000000 00000000
6574 &x+4 00000000 00000000 00000000 00000000
6577 &x+8 00000000 00000000 00000000 00000000
6580 &x+12 00000000 00000000 00000000 00000000
6586 frv_adjust_field_align (tree field, int computed)
6588 /* Make sure that the bitfield is not wider than the type. */
6589 if (DECL_BIT_FIELD (field)
6590 && !DECL_ARTIFICIAL (field))
6592 tree parent = DECL_CONTEXT (field);
6593 tree prev = NULL_TREE;
6596 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6598 if (TREE_CODE (cur) != FIELD_DECL)
6606 /* If this isn't a :0 field and if the previous element is a bitfield
6607 also, see if the type is different, if so, we will need to align the
6608 bit-field to the next boundary. */
6610 && ! DECL_PACKED (field)
6611 && ! integer_zerop (DECL_SIZE (field))
6612 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6614 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6615 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6616 computed = (prev_align > cur_align) ? prev_align : cur_align;
6624 /* A C expression that is nonzero if it is permissible to store a value of mode
6625 MODE in hard register number REGNO (or in several registers starting with
6626 that one). For a machine where all registers are equivalent, a suitable
6629 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6631 It is not necessary for this macro to check for the numbers of fixed
6632 registers, because the allocation mechanism considers them to be always
6635 On some machines, double-precision values must be kept in even/odd register
6636 pairs. The way to implement that is to define this macro to reject odd
6637 register numbers for such modes.
6639 The minimum requirement for a mode to be OK in a register is that the
6640 `movMODE' instruction pattern support moves between the register and any
6641 other hard register for which the mode is OK; and that moving a value into
6642 the register and back out not alter it.
6644 Since the same instruction used to move `SImode' will work for all narrower
6645 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6646 to distinguish between these modes, provided you define patterns `movhi',
6647 etc., to take advantage of this. This is useful because of the interaction
6648 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6649 all integer modes to be tieable.
6651 Many machines have special registers for floating point arithmetic. Often
6652 people assume that floating point machine modes are allowed only in floating
6653 point registers. This is not true. Any registers that can hold integers
6654 can safely *hold* a floating point machine mode, whether or not floating
6655 arithmetic can be done on it in those registers. Integer move instructions
6656 can be used to move the values.
6658 On some machines, though, the converse is true: fixed-point machine modes
6659 may not go in floating registers. This is true if the floating registers
6660 normalize any value stored in them, because storing a non-floating value
6661 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6662 fixed-point machine modes in floating registers. But if the floating
6663 registers do not automatically normalize, if you can store any bit pattern
6664 in one and retrieve it unchanged without a trap, then any machine mode may
6665 go in a floating register, so you can define this macro to say so.
6667 The primary significance of special floating registers is rather that they
6668 are the registers acceptable in floating point arithmetic instructions.
6669 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6670 writing the proper constraints for those instructions.
6672 On some machines, the floating registers are especially slow to access, so
6673 that it is better to store a value in a stack frame than in such a register
6674 if floating point arithmetic is not being done. As long as the floating
6675 registers are not in class `GENERAL_REGS', they will not be used unless some
6676 pattern's constraint asks for one. */
6679 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6689 return ICC_P (regno) || GPR_P (regno);
6692 return CR_P (regno) || GPR_P (regno);
6695 return FCC_P (regno) || GPR_P (regno);
6701 /* Set BASE to the first register in REGNO's class. Set MASK to the
6702 bits that must be clear in (REGNO - BASE) for the register to be
6704 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6708 /* ACCGs store one byte. Two-byte quantities must start in
6709 even-numbered registers, four-byte ones in registers whose
6710 numbers are divisible by four, and so on. */
6712 mask = GET_MODE_SIZE (mode) - 1;
6716 /* The other registers store one word. */
6717 if (GPR_P (regno) || regno == AP_FIRST)
6720 else if (FPR_P (regno))
6723 else if (ACC_P (regno))
6726 else if (SPR_P (regno))
6727 return mode == SImode;
6729 /* Fill in the table. */
6733 /* Anything smaller than an SI is OK in any word-sized register. */
6734 if (GET_MODE_SIZE (mode) < 4)
6737 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6739 return (((regno - base) & mask) == 0);
6746 /* A C expression for the number of consecutive hard registers, starting at
6747 register number REGNO, required to hold a value of mode MODE.
6749 On a machine where all registers are exactly one word, a suitable definition
6752 #define HARD_REGNO_NREGS(REGNO, MODE) \
6753 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6754 / UNITS_PER_WORD)) */
6756 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6757 that we can build the appropriate instructions to properly reload the
6758 values. Also, make the byte-sized accumulator guards use one guard
6762 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6765 return GET_MODE_SIZE (mode);
6767 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6771 /* A C expression for the maximum number of consecutive registers of
6772 class RCLASS needed to hold a value of mode MODE.
6774 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6775 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6776 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6778 This macro helps control the handling of multiple-word values in
6781 This declaration is required. */
6784 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6786 if (rclass == ACCG_REGS)
6787 /* An N-byte value requires N accumulator guards. */
6788 return GET_MODE_SIZE (mode);
6790 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6794 /* A C expression that is nonzero if X is a legitimate constant for an
6795 immediate operand on the target machine. You can assume that X satisfies
6796 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6797 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6800 frv_legitimate_constant_p (rtx x)
6802 enum machine_mode mode = GET_MODE (x);
6804 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6805 means that the move expanders will be expected to deal with most
6806 kinds of constant, regardless of what we return here.
6808 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6809 a constant can be entered into reg_equiv_constant[]. If we return true,
6810 reload can create new instances of the constant whenever it likes.
6812 The idea is therefore to accept as many constants as possible (to give
6813 reload more freedom) while rejecting constants that can only be created
6814 at certain times. In particular, anything with a symbolic component will
6815 require use of the pseudo FDPIC register, which is only available before
6818 return LEGITIMATE_PIC_OPERAND_P (x);
6820 /* All of the integer constants are ok. */
6821 if (GET_CODE (x) != CONST_DOUBLE)
6824 /* double integer constants are ok. */
6825 if (mode == VOIDmode || mode == DImode)
6828 /* 0 is always ok. */
6829 if (x == CONST0_RTX (mode))
6832 /* If floating point is just emulated, allow any constant, since it will be
6833 constructed in the GPRs. */
6834 if (!TARGET_HAS_FPRS)
6837 if (mode == DFmode && !TARGET_DOUBLE)
6840 /* Otherwise store the constant away and do a load. */
6844 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6845 CC_NZ for comparisons against zero in which a single Z or N flag test
6846 is enough, CC_UNS for other unsigned comparisons, and CC for other
6847 signed comparisons. */
6850 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6852 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6861 return y == const0_rtx ? CC_NZmode : CCmode;
6867 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6874 /* A C expression for the cost of moving data from a register in class FROM to
6875 one in class TO. The classes are expressed using the enumeration values
6876 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6877 interpreted relative to that.
6879 It is not required that the cost always equal 2 when FROM is the same as TO;
6880 on some machines it is expensive to move between registers if they are not
6883 If reload sees an insn consisting of a single `set' between two hard
6884 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6885 value of 2, reload does not check to ensure that the constraints of the insn
6886 are met. Setting a cost of other than 2 will allow reload to verify that
6887 the constraints are met. You should do this if the `movM' pattern's
6888 constraints do not allow such copying. */
6890 #define HIGH_COST 40
6891 #define MEDIUM_COST 3
6895 frv_register_move_cost (enum reg_class from, enum reg_class to)
6979 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6980 use ".picptr" to generate safe relocations for PIC code. We also
6981 need a fixup entry for aligned (non-debugging) code. */
6984 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6986 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6988 if (GET_CODE (value) == CONST
6989 || GET_CODE (value) == SYMBOL_REF
6990 || GET_CODE (value) == LABEL_REF)
6992 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6993 && SYMBOL_REF_FUNCTION_P (value))
6995 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6996 output_addr_const (asm_out_file, value);
6997 fputs (")\n", asm_out_file);
7000 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7001 && frv_function_symbol_referenced_p (value))
7003 if (aligned_p && !TARGET_FDPIC)
7005 static int label_num = 0;
7009 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7010 p = (* targetm.strip_name_encoding) (buf);
7012 fprintf (asm_out_file, "%s:\n", p);
7013 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7014 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7015 fprintf (asm_out_file, "\t.previous\n");
7017 assemble_integer_with_op ("\t.picptr\t", value);
7022 /* We've set the unaligned SI op to NULL, so we always have to
7023 handle the unaligned case here. */
7024 assemble_integer_with_op ("\t.4byte\t", value);
7028 return default_assemble_integer (value, size, aligned_p);
7031 /* Function to set up the backend function structure. */
7033 static struct machine_function *
7034 frv_init_machine_status (void)
7036 return GGC_CNEW (struct machine_function);
7039 /* Implement TARGET_SCHED_ISSUE_RATE. */
7042 frv_issue_rate (void)
7047 switch (frv_cpu_type)
7051 case FRV_CPU_SIMPLE:
7059 case FRV_CPU_GENERIC:
7061 case FRV_CPU_TOMCAT:
7069 /* A for_each_rtx callback. If X refers to an accumulator, return
7070 ACC_GROUP_ODD if the bit 2 of the register number is set and
7071 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7075 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7079 if (ACC_P (REGNO (*x)))
7080 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7081 if (ACCG_P (REGNO (*x)))
7082 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7087 /* Return the value of INSN's acc_group attribute. */
7090 frv_acc_group (rtx insn)
7092 /* This distinction only applies to the FR550 packing constraints. */
7093 if (frv_cpu_type != FRV_CPU_FR550)
7094 return ACC_GROUP_NONE;
7095 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7098 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7099 INSN will try to claim first. Since this value depends only on the
7100 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7103 frv_insn_unit (rtx insn)
7105 enum attr_type type;
7107 type = get_attr_type (insn);
7108 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7110 /* We haven't seen this type of instruction before. */
7114 /* Issue the instruction on its own to see which unit it prefers. */
7115 state = alloca (state_size ());
7116 state_reset (state);
7117 state_transition (state, insn);
7119 /* Find out which unit was taken. */
7120 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7121 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7124 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7126 frv_type_to_unit[type] = unit;
7128 return frv_type_to_unit[type];
7131 /* Return true if INSN issues to a branch unit. */
7134 frv_issues_to_branch_unit_p (rtx insn)
7136 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7139 /* The current state of the packing pass, implemented by frv_pack_insns. */
7141 /* The state of the pipeline DFA. */
7144 /* Which hardware registers are set within the current packet,
7145 and the conditions under which they are set. */
7146 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7148 /* The memory locations that have been modified so far in this
7149 packet. MEM is the memref and COND is the regstate_t condition
7150 under which it is set. */
7156 /* The number of valid entries in MEMS. The value is larger than
7157 ARRAY_SIZE (mems) if there were too many mems to record. */
7158 unsigned int num_mems;
7160 /* The maximum number of instructions that can be packed together. */
7161 unsigned int issue_rate;
7163 /* The instructions in the packet, partitioned into groups. */
7164 struct frv_packet_group {
7165 /* How many instructions in the packet belong to this group. */
7166 unsigned int num_insns;
7168 /* A list of the instructions that belong to this group, in the order
7169 they appear in the rtl stream. */
7170 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7172 /* The contents of INSNS after they have been sorted into the correct
7173 assembly-language order. Element X issues to unit X. The list may
7174 contain extra nops. */
7175 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7177 /* The member of frv_nops[] to use in sorted[]. */
7179 } groups[NUM_GROUPS];
7181 /* The instructions that make up the current packet. */
7182 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7183 unsigned int num_insns;
7186 /* Return the regstate_t flags for the given COND_EXEC condition.
7187 Abort if the condition isn't in the right form. */
7190 frv_cond_flags (rtx cond)
7192 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7193 && GET_CODE (XEXP (cond, 0)) == REG
7194 && CR_P (REGNO (XEXP (cond, 0)))
7195 && XEXP (cond, 1) == const0_rtx);
7196 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7197 | (GET_CODE (cond) == NE
7199 : REGSTATE_IF_FALSE));
7203 /* Return true if something accessed under condition COND2 can
7204 conflict with something written under condition COND1. */
7207 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7209 /* If either reference was unconditional, we have a conflict. */
7210 if ((cond1 & REGSTATE_IF_EITHER) == 0
7211 || (cond2 & REGSTATE_IF_EITHER) == 0)
7214 /* The references might conflict if they were controlled by
7216 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7219 /* They definitely conflict if they are controlled by the
7221 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7228 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7229 the current packet. DATA points to a regstate_t that describes the
7230 condition under which *X might be set or used. */
7233 frv_registers_conflict_p_1 (rtx *x, void *data)
7235 unsigned int regno, i;
7238 cond = *(regstate_t *) data;
7240 if (GET_CODE (*x) == REG)
7241 FOR_EACH_REGNO (regno, *x)
7242 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7243 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7246 if (GET_CODE (*x) == MEM)
7248 /* If we ran out of memory slots, assume a conflict. */
7249 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7252 /* Check for output or true dependencies with earlier MEMs. */
7253 for (i = 0; i < frv_packet.num_mems; i++)
7254 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7256 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7260 if (output_dependence (frv_packet.mems[i].mem, *x))
7265 /* The return values of calls aren't significant: they describe
7266 the effect of the call as a whole, not of the insn itself. */
7267 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7269 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7274 /* Check subexpressions. */
7279 /* Return true if something in X might depend on an instruction
7280 in the current packet. */
7283 frv_registers_conflict_p (rtx x)
7288 if (GET_CODE (x) == COND_EXEC)
7290 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7293 flags |= frv_cond_flags (XEXP (x, 0));
7296 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7300 /* A note_stores callback. DATA points to the regstate_t condition
7301 under which X is modified. Update FRV_PACKET accordingly. */
7304 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7308 if (GET_CODE (x) == REG)
7309 FOR_EACH_REGNO (regno, x)
7310 frv_packet.regstate[regno] |= *(regstate_t *) data;
7312 if (GET_CODE (x) == MEM)
7314 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7316 frv_packet.mems[frv_packet.num_mems].mem = x;
7317 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7319 frv_packet.num_mems++;
7324 /* Update the register state information for an instruction whose
7328 frv_registers_update (rtx x)
7332 flags = REGSTATE_MODIFIED;
7333 if (GET_CODE (x) == COND_EXEC)
7335 flags |= frv_cond_flags (XEXP (x, 0));
7338 note_stores (x, frv_registers_update_1, &flags);
7342 /* Initialize frv_packet for the start of a new packet. */
7345 frv_start_packet (void)
7347 enum frv_insn_group group;
7349 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7350 frv_packet.num_mems = 0;
7351 frv_packet.num_insns = 0;
7352 for (group = 0; group < NUM_GROUPS; group++)
7353 frv_packet.groups[group].num_insns = 0;
7357 /* Likewise for the start of a new basic block. */
7360 frv_start_packet_block (void)
7362 state_reset (frv_packet.dfa_state);
7363 frv_start_packet ();
7367 /* Finish the current packet, if any, and start a new one. Call
7368 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7371 frv_finish_packet (void (*handle_packet) (void))
7373 if (frv_packet.num_insns > 0)
7376 state_transition (frv_packet.dfa_state, 0);
7377 frv_start_packet ();
7382 /* Return true if INSN can be added to the current packet. Update
7383 the DFA state on success. */
7386 frv_pack_insn_p (rtx insn)
7388 /* See if the packet is already as long as it can be. */
7389 if (frv_packet.num_insns == frv_packet.issue_rate)
7392 /* If the scheduler thought that an instruction should start a packet,
7393 it's usually a good idea to believe it. It knows much more about
7394 the latencies than we do.
7396 There are some exceptions though:
7398 - Conditional instructions are scheduled on the assumption that
7399 they will be executed. This is usually a good thing, since it
7400 tends to avoid unnecessary stalls in the conditional code.
7401 But we want to pack conditional instructions as tightly as
7402 possible, in order to optimize the case where they aren't
7405 - The scheduler will always put branches on their own, even
7406 if there's no real dependency.
7408 - There's no point putting a call in its own packet unless
7410 if (frv_packet.num_insns > 0
7411 && GET_CODE (insn) == INSN
7412 && GET_MODE (insn) == TImode
7413 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7416 /* Check for register conflicts. Don't do this for setlo since any
7417 conflict will be with the partnering sethi, with which it can
7419 if (get_attr_type (insn) != TYPE_SETLO)
7420 if (frv_registers_conflict_p (PATTERN (insn)))
7423 return state_transition (frv_packet.dfa_state, insn) < 0;
7427 /* Add instruction INSN to the current packet. */
7430 frv_add_insn_to_packet (rtx insn)
7432 struct frv_packet_group *packet_group;
7434 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7435 packet_group->insns[packet_group->num_insns++] = insn;
7436 frv_packet.insns[frv_packet.num_insns++] = insn;
7438 frv_registers_update (PATTERN (insn));
7442 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7443 packet ends in a branch or call, insert the nop before it, otherwise
7447 frv_insert_nop_in_packet (rtx insn)
7449 struct frv_packet_group *packet_group;
7452 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7453 last = frv_packet.insns[frv_packet.num_insns - 1];
7454 if (GET_CODE (last) != INSN)
7456 insn = emit_insn_before (PATTERN (insn), last);
7457 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7458 frv_packet.insns[frv_packet.num_insns++] = last;
7462 insn = emit_insn_after (PATTERN (insn), last);
7463 frv_packet.insns[frv_packet.num_insns++] = insn;
7465 packet_group->insns[packet_group->num_insns++] = insn;
7469 /* If packing is enabled, divide the instructions into packets and
7470 return true. Call HANDLE_PACKET for each complete packet. */
7473 frv_for_each_packet (void (*handle_packet) (void))
7475 rtx insn, next_insn;
7477 frv_packet.issue_rate = frv_issue_rate ();
7479 /* Early exit if we don't want to pack insns. */
7481 || !flag_schedule_insns_after_reload
7482 || !TARGET_VLIW_BRANCH
7483 || frv_packet.issue_rate == 1)
7486 /* Set up the initial packing state. */
7488 frv_packet.dfa_state = alloca (state_size ());
7490 frv_start_packet_block ();
7491 for (insn = get_insns (); insn != 0; insn = next_insn)
7496 code = GET_CODE (insn);
7497 next_insn = NEXT_INSN (insn);
7499 if (code == CODE_LABEL)
7501 frv_finish_packet (handle_packet);
7502 frv_start_packet_block ();
7506 switch (GET_CODE (PATTERN (insn)))
7515 /* Calls mustn't be packed on a TOMCAT. */
7516 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7517 frv_finish_packet (handle_packet);
7519 /* Since the last instruction in a packet determines the EH
7520 region, any exception-throwing instruction must come at
7521 the end of reordered packet. Insns that issue to a
7522 branch unit are bound to come last; for others it's
7523 too hard to predict. */
7524 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7525 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7526 frv_finish_packet (handle_packet);
7528 /* Finish the current packet if we can't add INSN to it.
7529 Simulate cycles until INSN is ready to issue. */
7530 if (!frv_pack_insn_p (insn))
7532 frv_finish_packet (handle_packet);
7533 while (!frv_pack_insn_p (insn))
7534 state_transition (frv_packet.dfa_state, 0);
7537 /* Add the instruction to the packet. */
7538 frv_add_insn_to_packet (insn);
7540 /* Calls and jumps end a packet, as do insns that throw
7542 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7543 frv_finish_packet (handle_packet);
7547 frv_finish_packet (handle_packet);
7552 /* Subroutine of frv_sort_insn_group. We are trying to sort
7553 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7554 language order. We have already picked a new position for
7555 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7556 These instructions will occupy elements [0, LOWER_SLOT) and
7557 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7558 the DFA state after issuing these instructions.
7560 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7561 of the unused instructions. Return true if one such permutation gives
7562 a valid ordering, leaving the successful permutation in sorted[].
7563 Do not modify sorted[] until a valid permutation is found. */
7566 frv_sort_insn_group_1 (enum frv_insn_group group,
7567 unsigned int lower_slot, unsigned int upper_slot,
7568 unsigned int issued, unsigned int num_insns,
7571 struct frv_packet_group *packet_group;
7577 /* Early success if we've filled all the slots. */
7578 if (lower_slot == upper_slot)
7581 packet_group = &frv_packet.groups[group];
7582 dfa_size = state_size ();
7583 test_state = alloca (dfa_size);
7585 /* Try issuing each unused instruction. */
7586 for (i = num_insns - 1; i + 1 != 0; i--)
7587 if (~issued & (1 << i))
7589 insn = packet_group->sorted[i];
7590 memcpy (test_state, state, dfa_size);
7591 if (state_transition (test_state, insn) < 0
7592 && cpu_unit_reservation_p (test_state,
7593 NTH_UNIT (group, upper_slot - 1))
7594 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7595 issued | (1 << i), num_insns,
7598 packet_group->sorted[upper_slot - 1] = insn;
7606 /* Compare two instructions by their frv_insn_unit. */
7609 frv_compare_insns (const void *first, const void *second)
7611 const rtx *const insn1 = (rtx const *) first,
7612 *const insn2 = (rtx const *) second;
7613 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7616 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7617 and sort it into assembly language order. See frv.md for a description of
7621 frv_sort_insn_group (enum frv_insn_group group)
7623 struct frv_packet_group *packet_group;
7624 unsigned int first, i, nop, max_unit, num_slots;
7625 state_t state, test_state;
7628 packet_group = &frv_packet.groups[group];
7630 /* Assume no nop is needed. */
7631 packet_group->nop = 0;
7633 if (packet_group->num_insns == 0)
7636 /* Copy insns[] to sorted[]. */
7637 memcpy (packet_group->sorted, packet_group->insns,
7638 sizeof (rtx) * packet_group->num_insns);
7640 /* Sort sorted[] by the unit that each insn tries to take first. */
7641 if (packet_group->num_insns > 1)
7642 qsort (packet_group->sorted, packet_group->num_insns,
7643 sizeof (rtx), frv_compare_insns);
7645 /* That's always enough for branch and control insns. */
7646 if (group == GROUP_B || group == GROUP_C)
7649 dfa_size = state_size ();
7650 state = alloca (dfa_size);
7651 test_state = alloca (dfa_size);
7653 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7654 consecutively and such that the DFA takes unit X when sorted[X]
7655 is added. Set STATE to the new DFA state. */
7656 state_reset (test_state);
7657 for (first = 0; first < packet_group->num_insns; first++)
7659 memcpy (state, test_state, dfa_size);
7660 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7661 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7665 /* If all the instructions issued in ascending order, we're done. */
7666 if (first == packet_group->num_insns)
7669 /* Add nops to the end of sorted[] and try each permutation until
7670 we find one that works. */
7671 for (nop = 0; nop < frv_num_nops; nop++)
7673 max_unit = frv_insn_unit (frv_nops[nop]);
7674 if (frv_unit_groups[max_unit] == group)
7676 packet_group->nop = frv_nops[nop];
7677 num_slots = UNIT_NUMBER (max_unit) + 1;
7678 for (i = packet_group->num_insns; i < num_slots; i++)
7679 packet_group->sorted[i] = frv_nops[nop];
7680 if (frv_sort_insn_group_1 (group, first, num_slots,
7681 (1 << first) - 1, num_slots, state))
7688 /* Sort the current packet into assembly-language order. Set packing
7689 flags as appropriate. */
7692 frv_reorder_packet (void)
7694 unsigned int cursor[NUM_GROUPS];
7695 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7696 unsigned int unit, to, from;
7697 enum frv_insn_group group;
7698 struct frv_packet_group *packet_group;
7700 /* First sort each group individually. */
7701 for (group = 0; group < NUM_GROUPS; group++)
7704 frv_sort_insn_group (group);
7707 /* Go through the unit template and try add an instruction from
7708 that unit's group. */
7710 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7712 group = frv_unit_groups[unit];
7713 packet_group = &frv_packet.groups[group];
7714 if (cursor[group] < packet_group->num_insns)
7716 /* frv_reorg should have added nops for us. */
7717 gcc_assert (packet_group->sorted[cursor[group]]
7718 != packet_group->nop);
7719 insns[to++] = packet_group->sorted[cursor[group]++];
7723 gcc_assert (to == frv_packet.num_insns);
7725 /* Clear the last instruction's packing flag, thus marking the end of
7726 a packet. Reorder the other instructions relative to it. */
7727 CLEAR_PACKING_FLAG (insns[to - 1]);
7728 for (from = 0; from < to - 1; from++)
7730 remove_insn (insns[from]);
7731 add_insn_before (insns[from], insns[to - 1], NULL);
7732 SET_PACKING_FLAG (insns[from]);
7737 /* Divide instructions into packets. Reorder the contents of each
7738 packet so that they are in the correct assembly-language order.
7740 Since this pass can change the raw meaning of the rtl stream, it must
7741 only be called at the last minute, just before the instructions are
7745 frv_pack_insns (void)
7747 if (frv_for_each_packet (frv_reorder_packet))
7748 frv_insn_packing_flag = 0;
7750 frv_insn_packing_flag = -1;
7753 /* See whether we need to add nops to group GROUP in order to
7754 make a valid packet. */
7757 frv_fill_unused_units (enum frv_insn_group group)
7759 unsigned int non_nops, nops, i;
7760 struct frv_packet_group *packet_group;
7762 packet_group = &frv_packet.groups[group];
7764 /* Sort the instructions into assembly-language order.
7765 Use nops to fill slots that are otherwise unused. */
7766 frv_sort_insn_group (group);
7768 /* See how many nops are needed before the final useful instruction. */
7770 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7771 while (packet_group->sorted[i++] == packet_group->nop)
7774 /* Insert that many nops into the instruction stream. */
7776 frv_insert_nop_in_packet (packet_group->nop);
7779 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7782 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7784 if (io1->const_address != 0 && io2->const_address != 0)
7785 return io1->const_address == io2->const_address;
7787 if (io1->var_address != 0 && io2->var_address != 0)
7788 return rtx_equal_p (io1->var_address, io2->var_address);
7793 /* Return true if operations IO1 and IO2 are guaranteed to complete
7797 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7799 /* The order of writes is always preserved. */
7800 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7803 /* The order of reads isn't preserved. */
7804 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7807 /* One operation is a write and the other is (or could be) a read.
7808 The order is only guaranteed if the accesses are to the same
7810 return frv_same_doubleword_p (io1, io2);
7813 /* Generalize I/O operation X so that it covers both X and Y. */
7816 frv_io_union (struct frv_io *x, const struct frv_io *y)
7818 if (x->type != y->type)
7819 x->type = FRV_IO_UNKNOWN;
7820 if (!frv_same_doubleword_p (x, y))
7822 x->const_address = 0;
7827 /* Fill IO with information about the load or store associated with
7828 membar instruction INSN. */
7831 frv_extract_membar (struct frv_io *io, rtx insn)
7833 extract_insn (insn);
7834 io->type = INTVAL (recog_data.operand[2]);
7835 io->const_address = INTVAL (recog_data.operand[1]);
7836 io->var_address = XEXP (recog_data.operand[0], 0);
7839 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7840 if X is a register and *DATA depends on X. */
7843 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7845 rtx *other = (rtx *) data;
7847 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7851 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7852 Remove every modified register from the set. */
7855 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7857 HARD_REG_SET *set = (HARD_REG_SET *) data;
7861 FOR_EACH_REGNO (regno, x)
7862 CLEAR_HARD_REG_BIT (*set, regno);
7865 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7866 Add every register in *X to the set. */
7869 frv_io_handle_use_1 (rtx *x, void *data)
7871 HARD_REG_SET *set = (HARD_REG_SET *) data;
7875 FOR_EACH_REGNO (regno, *x)
7876 SET_HARD_REG_BIT (*set, regno);
7881 /* A note_stores callback that applies frv_io_handle_use_1 to an
7882 entire rhs value. */
7885 frv_io_handle_use (rtx *x, void *data)
7887 for_each_rtx (x, frv_io_handle_use_1, data);
7890 /* Go through block BB looking for membars to remove. There are two
7891 cases where intra-block analysis is enough:
7893 - a membar is redundant if it occurs between two consecutive I/O
7894 operations and if those operations are guaranteed to complete
7897 - a membar for a __builtin_read is redundant if the result is
7898 used before the next I/O operation is issued.
7900 If the last membar in the block could not be removed, and there
7901 are guaranteed to be no I/O operations between that membar and
7902 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7905 Describe the block's first I/O operation in *NEXT_IO. Describe
7906 an unknown operation if the block doesn't do any I/O. */
7909 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7912 HARD_REG_SET used_regs;
7913 rtx next_membar, set, insn;
7916 /* NEXT_IO is the next I/O operation to be performed after the current
7917 instruction. It starts off as being an unknown operation. */
7918 memset (next_io, 0, sizeof (*next_io));
7920 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7921 next_is_end_p = true;
7923 /* If the current instruction is a __builtin_read or __builtin_write,
7924 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7925 is null if the membar has already been deleted.
7927 Note that the initialization here should only be needed to
7928 suppress warnings. */
7931 /* USED_REGS is the set of registers that are used before the
7932 next I/O instruction. */
7933 CLEAR_HARD_REG_SET (used_regs);
7935 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7936 if (GET_CODE (insn) == CALL_INSN)
7938 /* We can't predict what a call will do to volatile memory. */
7939 memset (next_io, 0, sizeof (struct frv_io));
7940 next_is_end_p = false;
7941 CLEAR_HARD_REG_SET (used_regs);
7943 else if (INSN_P (insn))
7944 switch (recog_memoized (insn))
7946 case CODE_FOR_optional_membar_qi:
7947 case CODE_FOR_optional_membar_hi:
7948 case CODE_FOR_optional_membar_si:
7949 case CODE_FOR_optional_membar_di:
7953 /* Local information isn't enough to decide whether this
7954 membar is needed. Stash it away for later. */
7955 *last_membar = insn;
7956 frv_extract_membar (next_io, insn);
7957 next_is_end_p = false;
7961 /* Check whether the I/O operation before INSN could be
7962 reordered with one described by NEXT_IO. If it can't,
7963 INSN will not be needed. */
7964 struct frv_io prev_io;
7966 frv_extract_membar (&prev_io, insn);
7967 if (frv_io_fixed_order_p (&prev_io, next_io))
7971 ";; [Local] Removing membar %d since order"
7972 " of accesses is guaranteed\n",
7973 INSN_UID (next_membar));
7975 insn = NEXT_INSN (insn);
7976 delete_insn (next_membar);
7984 /* Invalidate NEXT_IO's address if it depends on something that
7985 is clobbered by INSN. */
7986 if (next_io->var_address)
7987 note_stores (PATTERN (insn), frv_io_check_address,
7988 &next_io->var_address);
7990 /* If the next membar is associated with a __builtin_read,
7991 see if INSN reads from that address. If it does, and if
7992 the destination register is used before the next I/O access,
7993 there is no need for the membar. */
7994 set = PATTERN (insn);
7995 if (next_io->type == FRV_IO_READ
7996 && next_io->var_address != 0
7998 && GET_CODE (set) == SET
7999 && GET_CODE (SET_DEST (set)) == REG
8000 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8004 src = SET_SRC (set);
8005 if (GET_CODE (src) == ZERO_EXTEND)
8006 src = XEXP (src, 0);
8008 if (GET_CODE (src) == MEM
8009 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8013 ";; [Local] Removing membar %d since the target"
8014 " of %d is used before the I/O operation\n",
8015 INSN_UID (next_membar), INSN_UID (insn));
8017 if (next_membar == *last_membar)
8020 delete_insn (next_membar);
8025 /* If INSN has volatile references, forget about any registers
8026 that are used after it. Otherwise forget about uses that
8027 are (or might be) defined by INSN. */
8028 if (volatile_refs_p (PATTERN (insn)))
8029 CLEAR_HARD_REG_SET (used_regs);
8031 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8033 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8038 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8039 FIRST_IO[X] describes the first operation performed by basic block X. */
8042 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8045 struct frv_io this_io, next_io;
8049 /* We need to keep the membar if there is an edge to the exit block. */
8050 FOR_EACH_EDGE (succ, ei, bb->succs)
8051 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8052 if (succ->dest == EXIT_BLOCK_PTR)
8055 /* Work out the union of all successor blocks. */
8056 ei = ei_start (bb->succs);
8057 ei_cond (ei, &succ);
8058 /* next_io = first_io[bb->succ->dest->index]; */
8059 next_io = first_io[succ->dest->index];
8060 ei = ei_start (bb->succs);
8061 if (ei_cond (ei, &succ))
8063 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8064 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8065 frv_io_union (&next_io, &first_io[succ->dest->index]);
8070 frv_extract_membar (&this_io, membar);
8071 if (frv_io_fixed_order_p (&this_io, &next_io))
8075 ";; [Global] Removing membar %d since order of accesses"
8076 " is guaranteed\n", INSN_UID (membar));
8078 delete_insn (membar);
8082 /* Remove redundant membars from the current function. */
8085 frv_optimize_membar (void)
8088 struct frv_io *first_io;
8091 compute_bb_for_insn ();
8092 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8093 last_membar = XCNEWVEC (rtx, last_basic_block);
8096 frv_optimize_membar_local (bb, &first_io[bb->index],
8097 &last_membar[bb->index]);
8100 if (last_membar[bb->index] != 0)
8101 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8107 /* Used by frv_reorg to keep track of the current packet's address. */
8108 static unsigned int frv_packet_address;
8110 /* If the current packet falls through to a label, try to pad the packet
8111 with nops in order to fit the label's alignment requirements. */
8114 frv_align_label (void)
8116 unsigned int alignment, target, nop;
8117 rtx x, last, barrier, label;
8119 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8120 maximum alignment of that packet, LABEL to the last label between
8121 the packets, and BARRIER to the last barrier. */
8122 last = frv_packet.insns[frv_packet.num_insns - 1];
8123 label = barrier = 0;
8125 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8129 unsigned int subalign = 1 << label_to_alignment (x);
8130 alignment = MAX (alignment, subalign);
8137 /* If -malign-labels, and the packet falls through to an unaligned
8138 label, try introducing a nop to align that label to 8 bytes. */
8139 if (TARGET_ALIGN_LABELS
8142 && frv_packet.num_insns < frv_packet.issue_rate)
8143 alignment = MAX (alignment, 8);
8145 /* Advance the address to the end of the current packet. */
8146 frv_packet_address += frv_packet.num_insns * 4;
8148 /* Work out the target address, after alignment. */
8149 target = (frv_packet_address + alignment - 1) & -alignment;
8151 /* If the packet falls through to the label, try to find an efficient
8152 padding sequence. */
8155 /* First try adding nops to the current packet. */
8156 for (nop = 0; nop < frv_num_nops; nop++)
8157 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8159 frv_insert_nop_in_packet (frv_nops[nop]);
8160 frv_packet_address += 4;
8163 /* If we still haven't reached the target, add some new packets that
8164 contain only nops. If there are two types of nop, insert an
8165 alternating sequence of frv_nops[0] and frv_nops[1], which will
8166 lead to packets like:
8173 etc. Just emit frv_nops[0] if that's the only nop we have. */
8174 last = frv_packet.insns[frv_packet.num_insns - 1];
8176 while (frv_packet_address < target)
8178 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8179 frv_packet_address += 4;
8180 if (frv_num_nops > 1)
8185 frv_packet_address = target;
8188 /* Subroutine of frv_reorg, called after each packet has been constructed
8192 frv_reorg_packet (void)
8194 frv_fill_unused_units (GROUP_I);
8195 frv_fill_unused_units (GROUP_FM);
8199 /* Add an instruction with pattern NOP to frv_nops[]. */
8202 frv_register_nop (rtx nop)
8204 nop = make_insn_raw (nop);
8205 NEXT_INSN (nop) = 0;
8206 PREV_INSN (nop) = 0;
8207 frv_nops[frv_num_nops++] = nop;
8210 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8211 into packets and check whether we need to insert nops in order to
8212 fulfill the processor's issue requirements. Also, if the user has
8213 requested a certain alignment for a label, try to meet that alignment
8214 by inserting nops in the previous packet. */
8219 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8220 frv_optimize_membar ();
8223 frv_register_nop (gen_nop ());
8225 frv_register_nop (gen_mnop ());
8226 if (TARGET_HARD_FLOAT)
8227 frv_register_nop (gen_fnop ());
8229 /* Estimate the length of each branch. Although this may change after
8230 we've inserted nops, it will only do so in big functions. */
8231 shorten_branches (get_insns ());
8233 frv_packet_address = 0;
8234 frv_for_each_packet (frv_reorg_packet);
8237 #define def_builtin(name, type, code) \
8238 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8240 struct builtin_description
8242 enum insn_code icode;
8244 enum frv_builtins code;
8245 enum rtx_code comparison;
8249 /* Media intrinsics that take a single, constant argument. */
8251 static struct builtin_description bdesc_set[] =
8253 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8256 /* Media intrinsics that take just one argument. */
8258 static struct builtin_description bdesc_1arg[] =
8260 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8261 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8262 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8263 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8264 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8265 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8268 /* Media intrinsics that take two arguments. */
8270 static struct builtin_description bdesc_2arg[] =
8272 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8273 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8274 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8275 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8276 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8277 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8278 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8279 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8280 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8281 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8282 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8283 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8284 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8285 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8286 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8287 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8288 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8289 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8290 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8291 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8292 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8293 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8294 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8295 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8296 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8297 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8298 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8301 /* Integer intrinsics that take two arguments and have no return value. */
8303 static struct builtin_description bdesc_int_void2arg[] =
8305 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8306 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8307 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8310 static struct builtin_description bdesc_prefetches[] =
8312 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8313 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8316 /* Media intrinsics that take two arguments, the first being an ACC number. */
8318 static struct builtin_description bdesc_cut[] =
8320 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8321 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8322 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8325 /* Two-argument media intrinsics with an immediate second argument. */
8327 static struct builtin_description bdesc_2argimm[] =
8329 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8330 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8331 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8332 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8333 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8334 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8335 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8336 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8337 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8338 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8339 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8340 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8341 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8342 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8343 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8344 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8345 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8348 /* Media intrinsics that take two arguments and return void, the first argument
8349 being a pointer to 4 words in memory. */
8351 static struct builtin_description bdesc_void2arg[] =
8353 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8354 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8357 /* Media intrinsics that take three arguments, the first being a const_int that
8358 denotes an accumulator, and that return void. */
8360 static struct builtin_description bdesc_void3arg[] =
8362 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8363 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8364 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8365 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8366 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8367 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8368 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8369 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8370 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8371 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8372 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8373 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8374 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8375 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8376 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8377 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8378 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8379 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8380 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8381 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8382 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8383 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8384 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8385 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8386 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8389 /* Media intrinsics that take two accumulator numbers as argument and
8392 static struct builtin_description bdesc_voidacc[] =
8394 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8395 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8396 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8397 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8398 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8399 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8402 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8403 a normal move and the ICODE is for the membar. */
8405 static struct builtin_description bdesc_loads[] =
8407 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8408 FRV_BUILTIN_READ8, 0, 0 },
8409 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8410 FRV_BUILTIN_READ16, 0, 0 },
8411 { CODE_FOR_optional_membar_si, "__builtin_read32",
8412 FRV_BUILTIN_READ32, 0, 0 },
8413 { CODE_FOR_optional_membar_di, "__builtin_read64",
8414 FRV_BUILTIN_READ64, 0, 0 }
8417 /* Likewise stores. */
8419 static struct builtin_description bdesc_stores[] =
8421 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8422 FRV_BUILTIN_WRITE8, 0, 0 },
8423 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8424 FRV_BUILTIN_WRITE16, 0, 0 },
8425 { CODE_FOR_optional_membar_si, "__builtin_write32",
8426 FRV_BUILTIN_WRITE32, 0, 0 },
8427 { CODE_FOR_optional_membar_di, "__builtin_write64",
8428 FRV_BUILTIN_WRITE64, 0, 0 },
8431 /* Initialize media builtins. */
8434 frv_init_builtins (void)
8436 tree endlink = void_list_node;
8437 tree accumulator = integer_type_node;
8438 tree integer = integer_type_node;
8439 tree voidt = void_type_node;
8440 tree uhalf = short_unsigned_type_node;
8441 tree sword1 = long_integer_type_node;
8442 tree uword1 = long_unsigned_type_node;
8443 tree sword2 = long_long_integer_type_node;
8444 tree uword2 = long_long_unsigned_type_node;
8445 tree uword4 = build_pointer_type (uword1);
8446 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8447 tree ubyte = unsigned_char_type_node;
8448 tree iacc = integer_type_node;
8450 #define UNARY(RET, T1) \
8451 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8453 #define BINARY(RET, T1, T2) \
8454 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8455 tree_cons (NULL_TREE, T2, endlink)))
8457 #define TRINARY(RET, T1, T2, T3) \
8458 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8459 tree_cons (NULL_TREE, T2, \
8460 tree_cons (NULL_TREE, T3, endlink))))
8462 #define QUAD(RET, T1, T2, T3, T4) \
8463 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8464 tree_cons (NULL_TREE, T2, \
8465 tree_cons (NULL_TREE, T3, \
8466 tree_cons (NULL_TREE, T4, endlink)))))
8468 tree void_ftype_void = build_function_type (voidt, endlink);
8470 tree void_ftype_acc = UNARY (voidt, accumulator);
8471 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8472 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8473 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8474 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8475 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8476 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8477 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8478 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8480 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8481 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8482 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8483 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8484 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8485 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8486 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8487 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8488 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8489 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8490 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8492 tree sw1_ftype_int = UNARY (sword1, integer);
8493 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8494 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8496 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8497 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8498 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8499 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8500 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8501 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8503 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8504 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8505 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8506 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8507 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8508 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8509 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8510 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8511 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8512 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8513 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8514 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8515 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8516 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8517 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8518 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8519 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8521 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8522 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8523 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8524 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8525 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8526 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8527 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8528 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8529 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8530 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8531 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8532 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8533 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8534 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8535 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8536 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8537 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8538 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8539 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8540 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8541 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8542 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8543 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8544 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8545 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8546 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8547 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8548 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8549 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8550 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8551 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8552 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8553 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8554 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8555 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8556 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8557 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8558 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8559 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8560 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8561 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8562 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8563 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8564 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8565 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8566 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8567 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8568 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8569 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8570 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8571 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8572 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8573 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8574 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8575 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8576 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8577 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8578 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8579 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8580 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8581 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8582 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8583 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8584 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8585 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8586 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8587 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8588 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8589 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8590 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8591 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8592 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8593 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8594 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8595 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8596 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8597 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8598 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8599 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8600 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8601 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8602 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8603 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8604 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8605 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8606 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8607 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8608 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8609 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8610 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8611 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8612 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8613 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8614 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8615 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8616 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8617 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8618 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8619 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8620 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8621 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8622 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8623 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8624 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8625 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8626 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8627 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8628 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8630 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8631 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8632 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8633 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8641 /* Set the names for various arithmetic operations according to the
8644 frv_init_libfuncs (void)
8646 set_optab_libfunc (smod_optab, SImode, "__modi");
8647 set_optab_libfunc (umod_optab, SImode, "__umodi");
8649 set_optab_libfunc (add_optab, DImode, "__addll");
8650 set_optab_libfunc (sub_optab, DImode, "__subll");
8651 set_optab_libfunc (smul_optab, DImode, "__mulll");
8652 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8653 set_optab_libfunc (smod_optab, DImode, "__modll");
8654 set_optab_libfunc (umod_optab, DImode, "__umodll");
8655 set_optab_libfunc (and_optab, DImode, "__andll");
8656 set_optab_libfunc (ior_optab, DImode, "__orll");
8657 set_optab_libfunc (xor_optab, DImode, "__xorll");
8658 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8660 set_optab_libfunc (add_optab, SFmode, "__addf");
8661 set_optab_libfunc (sub_optab, SFmode, "__subf");
8662 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8663 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8665 set_optab_libfunc (add_optab, DFmode, "__addd");
8666 set_optab_libfunc (sub_optab, DFmode, "__subd");
8667 set_optab_libfunc (smul_optab, DFmode, "__muld");
8668 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8670 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8671 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8673 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8674 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8675 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8676 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8678 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8679 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8680 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8681 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8683 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8684 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8685 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8686 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8689 /* Convert an integer constant to an accumulator register. ICODE is the
8690 code of the target instruction, OPNUM is the number of the
8691 accumulator operand and OPVAL is the constant integer. Try both
8692 ACC and ACCG registers; only report an error if neither fit the
8696 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8701 /* ACCs and ACCGs are implicit global registers if media intrinsics
8702 are being used. We set up this lazily to avoid creating lots of
8703 unnecessary call_insn rtl in non-media code. */
8704 for (i = 0; i <= ACC_MASK; i++)
8705 if ((i & ACC_MASK) == i)
8706 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8708 if (GET_CODE (opval) != CONST_INT)
8710 error ("accumulator is not a constant integer");
8713 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8715 error ("accumulator number is out of bounds");
8719 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8720 ACC_FIRST + INTVAL (opval));
8721 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8722 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8724 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8726 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8732 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8735 static enum machine_mode
8736 frv_matching_accg_mode (enum machine_mode mode)
8754 /* Given that a __builtin_read or __builtin_write function is accessing
8755 address ADDRESS, return the value that should be used as operand 1
8759 frv_io_address_cookie (rtx address)
8761 return (GET_CODE (address) == CONST_INT
8762 ? GEN_INT (INTVAL (address) / 8 * 8)
8766 /* Return the accumulator guard that should be paired with accumulator
8767 register ACC. The mode of the returned register is in the same
8768 class as ACC, but is four times smaller. */
8771 frv_matching_accg_for_acc (rtx acc)
8773 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8774 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8777 /* Read the requested argument from the call EXP given by INDEX.
8778 Return the value as an rtx. */
8781 frv_read_argument (tree exp, unsigned int index)
8783 return expand_expr (CALL_EXPR_ARG (exp, index),
8784 NULL_RTX, VOIDmode, 0);
8787 /* Like frv_read_argument, but interpret the argument as the number
8788 of an IACC register and return a (reg:MODE ...) rtx for it. */
8791 frv_read_iacc_argument (enum machine_mode mode, tree call,
8797 op = frv_read_argument (call, index);
8798 if (GET_CODE (op) != CONST_INT
8800 || INTVAL (op) > IACC_LAST - IACC_FIRST
8801 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8803 error ("invalid IACC argument");
8807 /* IACCs are implicit global registers. We set up this lazily to
8808 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8810 regno = INTVAL (op) + IACC_FIRST;
8811 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8812 global_regs[regno + i] = 1;
8814 return gen_rtx_REG (mode, regno);
8817 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8818 The instruction should require a constant operand of some sort. The
8819 function prints an error if OPVAL is not valid. */
8822 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8824 if (GET_CODE (opval) != CONST_INT)
8826 error ("%qs expects a constant argument", insn_data[icode].name);
8829 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8831 error ("constant argument out of range for %qs", insn_data[icode].name);
8837 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8838 if it's not null, has the right mode, and satisfies operand 0's
8842 frv_legitimize_target (enum insn_code icode, rtx target)
8844 enum machine_mode mode = insn_data[icode].operand[0].mode;
8847 || GET_MODE (target) != mode
8848 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8849 return gen_reg_rtx (mode);
8854 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8855 check whether ARG satisfies the operand's constraints. If it doesn't,
8856 copy ARG to a temporary register and return that. Otherwise return ARG
8860 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8862 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8864 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8867 return copy_to_mode_reg (mode, arg);
8870 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8873 frv_volatile_memref (enum machine_mode mode, rtx arg)
8877 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8878 MEM_VOLATILE_P (mem) = 1;
8882 /* Expand builtins that take a single, constant argument. At the moment,
8883 only MHDSETS falls into this category. */
8886 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8889 rtx op0 = frv_read_argument (call, 0);
8891 if (! frv_check_constant_argument (icode, 1, op0))
8894 target = frv_legitimize_target (icode, target);
8895 pat = GEN_FCN (icode) (target, op0);
8903 /* Expand builtins that take one operand. */
8906 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8909 rtx op0 = frv_read_argument (call, 0);
8911 target = frv_legitimize_target (icode, target);
8912 op0 = frv_legitimize_argument (icode, 1, op0);
8913 pat = GEN_FCN (icode) (target, op0);
8921 /* Expand builtins that take two operands. */
8924 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8927 rtx op0 = frv_read_argument (call, 0);
8928 rtx op1 = frv_read_argument (call, 1);
8930 target = frv_legitimize_target (icode, target);
8931 op0 = frv_legitimize_argument (icode, 1, op0);
8932 op1 = frv_legitimize_argument (icode, 2, op1);
8933 pat = GEN_FCN (icode) (target, op0, op1);
8941 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8945 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8948 rtx op0 = frv_read_argument (call, 0);
8949 rtx op1 = frv_read_argument (call, 1);
8952 target = frv_legitimize_target (icode, target);
8953 op0 = frv_int_to_acc (icode, 1, op0);
8957 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8959 if (! frv_check_constant_argument (icode, 2, op1))
8963 op1 = frv_legitimize_argument (icode, 2, op1);
8965 op2 = frv_matching_accg_for_acc (op0);
8966 pat = GEN_FCN (icode) (target, op0, op1, op2);
8974 /* Expand builtins that take two operands and the second is immediate. */
8977 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8980 rtx op0 = frv_read_argument (call, 0);
8981 rtx op1 = frv_read_argument (call, 1);
8983 if (! frv_check_constant_argument (icode, 2, op1))
8986 target = frv_legitimize_target (icode, target);
8987 op0 = frv_legitimize_argument (icode, 1, op0);
8988 pat = GEN_FCN (icode) (target, op0, op1);
8996 /* Expand builtins that take two operands, the first operand being a pointer to
8997 ints and return void. */
9000 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9003 rtx op0 = frv_read_argument (call, 0);
9004 rtx op1 = frv_read_argument (call, 1);
9005 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9008 if (GET_CODE (op0) != MEM)
9012 if (! offsettable_address_p (0, mode0, op0))
9014 reg = gen_reg_rtx (Pmode);
9015 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9018 op0 = gen_rtx_MEM (SImode, reg);
9021 addr = XEXP (op0, 0);
9022 if (! offsettable_address_p (0, mode0, addr))
9023 addr = copy_to_mode_reg (Pmode, op0);
9025 op0 = change_address (op0, V4SImode, addr);
9026 op1 = frv_legitimize_argument (icode, 1, op1);
9027 pat = GEN_FCN (icode) (op0, op1);
9035 /* Expand builtins that take two long operands and return void. */
9038 frv_expand_int_void2arg (enum insn_code icode, tree call)
9041 rtx op0 = frv_read_argument (call, 0);
9042 rtx op1 = frv_read_argument (call, 1);
9044 op0 = frv_legitimize_argument (icode, 1, op0);
9045 op1 = frv_legitimize_argument (icode, 1, op1);
9046 pat = GEN_FCN (icode) (op0, op1);
9054 /* Expand prefetch builtins. These take a single address as argument. */
9057 frv_expand_prefetches (enum insn_code icode, tree call)
9060 rtx op0 = frv_read_argument (call, 0);
9062 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9070 /* Expand builtins that take three operands and return void. The first
9071 argument must be a constant that describes a pair or quad accumulators. A
9072 fourth argument is created that is the accumulator guard register that
9073 corresponds to the accumulator. */
9076 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9079 rtx op0 = frv_read_argument (call, 0);
9080 rtx op1 = frv_read_argument (call, 1);
9081 rtx op2 = frv_read_argument (call, 2);
9084 op0 = frv_int_to_acc (icode, 0, op0);
9088 op1 = frv_legitimize_argument (icode, 1, op1);
9089 op2 = frv_legitimize_argument (icode, 2, op2);
9090 op3 = frv_matching_accg_for_acc (op0);
9091 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9099 /* Expand builtins that perform accumulator-to-accumulator operations.
9100 These builtins take two accumulator numbers as argument and return
9104 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9107 rtx op0 = frv_read_argument (call, 0);
9108 rtx op1 = frv_read_argument (call, 1);
9112 op0 = frv_int_to_acc (icode, 0, op0);
9116 op1 = frv_int_to_acc (icode, 1, op1);
9120 op2 = frv_matching_accg_for_acc (op0);
9121 op3 = frv_matching_accg_for_acc (op1);
9122 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9130 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9131 membar and TARGET_MODE is the mode that the loaded value should have. */
9134 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9135 tree call, rtx target)
9137 rtx op0 = frv_read_argument (call, 0);
9138 rtx cookie = frv_io_address_cookie (op0);
9140 if (target == 0 || !REG_P (target))
9141 target = gen_reg_rtx (target_mode);
9142 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9143 convert_move (target, op0, 1);
9144 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9145 cfun->machine->has_membar_p = 1;
9149 /* Likewise __builtin_write* functions. */
9152 frv_expand_store_builtin (enum insn_code icode, tree call)
9154 rtx op0 = frv_read_argument (call, 0);
9155 rtx op1 = frv_read_argument (call, 1);
9156 rtx cookie = frv_io_address_cookie (op0);
9158 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9159 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9160 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9161 cfun->machine->has_membar_p = 1;
9165 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9166 each argument forms one word of the two double-word input registers.
9167 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9168 to put the return value. */
9171 frv_expand_mdpackh_builtin (tree call, rtx target)
9173 enum insn_code icode = CODE_FOR_mdpackh;
9175 rtx arg1 = frv_read_argument (call, 0);
9176 rtx arg2 = frv_read_argument (call, 1);
9177 rtx arg3 = frv_read_argument (call, 2);
9178 rtx arg4 = frv_read_argument (call, 3);
9180 target = frv_legitimize_target (icode, target);
9181 op0 = gen_reg_rtx (DImode);
9182 op1 = gen_reg_rtx (DImode);
9184 /* The high half of each word is not explicitly initialized, so indicate
9185 that the input operands are not live before this point. */
9189 /* Move each argument into the low half of its associated input word. */
9190 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9191 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9192 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9193 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9195 pat = GEN_FCN (icode) (target, op0, op1);
9203 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9204 number as argument. */
9207 frv_expand_mclracc_builtin (tree call)
9209 enum insn_code icode = CODE_FOR_mclracc;
9211 rtx op0 = frv_read_argument (call, 0);
9213 op0 = frv_int_to_acc (icode, 0, op0);
9217 pat = GEN_FCN (icode) (op0);
9224 /* Expand builtins that take no arguments. */
9227 frv_expand_noargs_builtin (enum insn_code icode)
9229 rtx pat = GEN_FCN (icode) (const0_rtx);
9236 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9237 number or accumulator guard number as argument and return an SI integer. */
9240 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9243 rtx target = gen_reg_rtx (SImode);
9244 rtx op0 = frv_read_argument (call, 0);
9246 op0 = frv_int_to_acc (icode, 1, op0);
9250 pat = GEN_FCN (icode) (target, op0);
9258 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9259 accumulator guard as their first argument and an SImode value as their
9263 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9266 rtx op0 = frv_read_argument (call, 0);
9267 rtx op1 = frv_read_argument (call, 1);
9269 op0 = frv_int_to_acc (icode, 0, op0);
9273 op1 = frv_legitimize_argument (icode, 1, op1);
9274 pat = GEN_FCN (icode) (op0, op1);
9281 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9282 to move DImode values into and out of IACC0. */
9285 frv_split_iacc_move (rtx dest, rtx src)
9287 enum machine_mode inner;
9290 inner = GET_MODE (dest);
9291 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9292 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9293 simplify_gen_subreg (SImode, src, inner, i));
9296 /* Expand builtins. */
9299 frv_expand_builtin (tree exp,
9301 rtx subtarget ATTRIBUTE_UNUSED,
9302 enum machine_mode mode ATTRIBUTE_UNUSED,
9303 int ignore ATTRIBUTE_UNUSED)
9305 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9306 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9308 struct builtin_description *d;
9310 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9312 error ("media functions are not available unless -mmedia is used");
9318 case FRV_BUILTIN_MCOP1:
9319 case FRV_BUILTIN_MCOP2:
9320 case FRV_BUILTIN_MDUNPACKH:
9321 case FRV_BUILTIN_MBTOHE:
9322 if (! TARGET_MEDIA_REV1)
9324 error ("this media function is only available on the fr500");
9329 case FRV_BUILTIN_MQXMACHS:
9330 case FRV_BUILTIN_MQXMACXHS:
9331 case FRV_BUILTIN_MQMACXHS:
9332 case FRV_BUILTIN_MADDACCS:
9333 case FRV_BUILTIN_MSUBACCS:
9334 case FRV_BUILTIN_MASACCS:
9335 case FRV_BUILTIN_MDADDACCS:
9336 case FRV_BUILTIN_MDSUBACCS:
9337 case FRV_BUILTIN_MDASACCS:
9338 case FRV_BUILTIN_MABSHS:
9339 case FRV_BUILTIN_MDROTLI:
9340 case FRV_BUILTIN_MCPLHI:
9341 case FRV_BUILTIN_MCPLI:
9342 case FRV_BUILTIN_MDCUTSSI:
9343 case FRV_BUILTIN_MQSATHS:
9344 case FRV_BUILTIN_MHSETLOS:
9345 case FRV_BUILTIN_MHSETLOH:
9346 case FRV_BUILTIN_MHSETHIS:
9347 case FRV_BUILTIN_MHSETHIH:
9348 case FRV_BUILTIN_MHDSETS:
9349 case FRV_BUILTIN_MHDSETH:
9350 if (! TARGET_MEDIA_REV2)
9352 error ("this media function is only available on the fr400"
9358 case FRV_BUILTIN_SMASS:
9359 case FRV_BUILTIN_SMSSS:
9360 case FRV_BUILTIN_SMU:
9361 case FRV_BUILTIN_ADDSS:
9362 case FRV_BUILTIN_SUBSS:
9363 case FRV_BUILTIN_SLASS:
9364 case FRV_BUILTIN_SCUTSS:
9365 case FRV_BUILTIN_IACCreadll:
9366 case FRV_BUILTIN_IACCreadl:
9367 case FRV_BUILTIN_IACCsetll:
9368 case FRV_BUILTIN_IACCsetl:
9369 if (!TARGET_FR405_BUILTINS)
9371 error ("this builtin function is only available"
9372 " on the fr405 and fr450");
9377 case FRV_BUILTIN_PREFETCH:
9378 if (!TARGET_FR500_FR550_BUILTINS)
9380 error ("this builtin function is only available on the fr500"
9386 case FRV_BUILTIN_MQLCLRHS:
9387 case FRV_BUILTIN_MQLMTHS:
9388 case FRV_BUILTIN_MQSLLHI:
9389 case FRV_BUILTIN_MQSRAHI:
9390 if (!TARGET_MEDIA_FR450)
9392 error ("this builtin function is only available on the fr450");
9401 /* Expand unique builtins. */
9405 case FRV_BUILTIN_MTRAP:
9406 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9408 case FRV_BUILTIN_MCLRACC:
9409 return frv_expand_mclracc_builtin (exp);
9411 case FRV_BUILTIN_MCLRACCA:
9413 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9415 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9417 case FRV_BUILTIN_MRDACC:
9418 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9420 case FRV_BUILTIN_MRDACCG:
9421 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9423 case FRV_BUILTIN_MWTACC:
9424 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9426 case FRV_BUILTIN_MWTACCG:
9427 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9429 case FRV_BUILTIN_MDPACKH:
9430 return frv_expand_mdpackh_builtin (exp, target);
9432 case FRV_BUILTIN_IACCreadll:
9434 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9435 if (target == 0 || !REG_P (target))
9436 target = gen_reg_rtx (DImode);
9437 frv_split_iacc_move (target, src);
9441 case FRV_BUILTIN_IACCreadl:
9442 return frv_read_iacc_argument (SImode, exp, 0);
9444 case FRV_BUILTIN_IACCsetll:
9446 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9447 rtx src = frv_read_argument (exp, 1);
9448 frv_split_iacc_move (dest, force_reg (DImode, src));
9452 case FRV_BUILTIN_IACCsetl:
9454 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9455 rtx src = frv_read_argument (exp, 1);
9456 emit_move_insn (dest, force_reg (SImode, src));
9464 /* Expand groups of builtins. */
9466 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9467 if (d->code == fcode)
9468 return frv_expand_set_builtin (d->icode, exp, target);
9470 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9471 if (d->code == fcode)
9472 return frv_expand_unop_builtin (d->icode, exp, target);
9474 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9475 if (d->code == fcode)
9476 return frv_expand_binop_builtin (d->icode, exp, target);
9478 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9479 if (d->code == fcode)
9480 return frv_expand_cut_builtin (d->icode, exp, target);
9482 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9483 if (d->code == fcode)
9484 return frv_expand_binopimm_builtin (d->icode, exp, target);
9486 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9487 if (d->code == fcode)
9488 return frv_expand_voidbinop_builtin (d->icode, exp);
9490 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9491 if (d->code == fcode)
9492 return frv_expand_voidtriop_builtin (d->icode, exp);
9494 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9495 if (d->code == fcode)
9496 return frv_expand_voidaccop_builtin (d->icode, exp);
9498 for (i = 0, d = bdesc_int_void2arg;
9499 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9500 if (d->code == fcode)
9501 return frv_expand_int_void2arg (d->icode, exp);
9503 for (i = 0, d = bdesc_prefetches;
9504 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9505 if (d->code == fcode)
9506 return frv_expand_prefetches (d->icode, exp);
9508 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9509 if (d->code == fcode)
9510 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9513 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9514 if (d->code == fcode)
9515 return frv_expand_store_builtin (d->icode, exp);
9521 frv_in_small_data_p (const_tree decl)
9524 const_tree section_name;
9526 /* Don't apply the -G flag to internal compiler structures. We
9527 should leave such structures in the main data section, partly
9528 for efficiency and partly because the size of some of them
9529 (such as C++ typeinfos) is not known until later. */
9530 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9533 /* If we already know which section the decl should be in, see if
9534 it's a small data section. */
9535 section_name = DECL_SECTION_NAME (decl);
9538 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9539 if (frv_string_begins_with (section_name, ".sdata"))
9541 if (frv_string_begins_with (section_name, ".sbss"))
9546 size = int_size_in_bytes (TREE_TYPE (decl));
9547 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9554 frv_rtx_costs (rtx x,
9555 int code ATTRIBUTE_UNUSED,
9556 int outer_code ATTRIBUTE_UNUSED,
9558 bool speed ATTRIBUTE_UNUSED)
9560 if (outer_code == MEM)
9562 /* Don't differentiate between memory addresses. All the ones
9563 we accept have equal cost. */
9564 *total = COSTS_N_INSNS (0);
9571 /* Make 12-bit integers really cheap. */
9572 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9583 *total = COSTS_N_INSNS (2);
9597 if (GET_MODE (x) == SImode)
9598 *total = COSTS_N_INSNS (1);
9599 else if (GET_MODE (x) == DImode)
9600 *total = COSTS_N_INSNS (2);
9602 *total = COSTS_N_INSNS (3);
9606 if (GET_MODE (x) == SImode)
9607 *total = COSTS_N_INSNS (2);
9609 *total = COSTS_N_INSNS (6); /* guess */
9616 *total = COSTS_N_INSNS (18);
9620 *total = COSTS_N_INSNS (3);
9629 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9631 switch_to_section (ctors_section);
9632 assemble_align (POINTER_SIZE);
9635 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9640 assemble_integer_with_op ("\t.picptr\t", symbol);
9644 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9646 switch_to_section (dtors_section);
9647 assemble_align (POINTER_SIZE);
9650 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9655 assemble_integer_with_op ("\t.picptr\t", symbol);
9658 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9661 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9662 int incoming ATTRIBUTE_UNUSED)
9664 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9667 #define TLS_BIAS (2048 - 16)
9669 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9670 We need to emit DTP-relative relocations. */
9673 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9675 gcc_assert (size == 4);
9676 fputs ("\t.picptr\ttlsmoff(", file);
9677 /* We want the unbiased TLS offset, so add the bias to the
9678 expression, such that the implicit biasing cancels out. */
9679 output_addr_const (file, plus_constant (x, TLS_BIAS));