1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Return true if instruction INSN should be packed with the following
114 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
116 /* Set the value of PACKING_FLAG_P(INSN). */
117 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
118 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
120 /* Loop with REG set to each hard register in rtx X. */
121 #define FOR_EACH_REGNO(REG, X) \
122 for (REG = REGNO (X); \
123 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
126 /* Information about a relocation unspec. SYMBOL is the relocation symbol
127 (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
128 is the constant addend. */
132 HOST_WIDE_INT offset;
135 /* Temporary register allocation support structure. */
136 typedef struct frv_tmp_reg_struct
138 HARD_REG_SET regs; /* possible registers to allocate */
139 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
143 /* Register state information for VLIW re-packing phase. */
144 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
145 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
146 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
147 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
149 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
151 typedef unsigned char regstate_t;
153 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
161 /* Information required by frv_frame_access. */
164 /* This field is FRV_LOAD if registers are to be loaded from the stack and
165 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
166 the move is being done by the prologue code while FRV_LOAD implies it
167 is being done by the epilogue. */
168 enum frv_stack_op op;
170 /* The base register to use when accessing the stack. This may be the
171 frame pointer, stack pointer, or a temporary. The choice of register
172 depends on which part of the frame is being accessed and how big the
176 /* The offset of BASE from the bottom of the current frame, in bytes. */
178 } frv_frame_accessor_t;
180 /* Define the information needed to generate branch and scc insns. This is
181 stored from the compare operation. */
185 /* Conditional execution support gathered together in one structure. */
188 /* Linked list of insns to add if the conditional execution conversion was
189 successful. Each link points to an EXPR_LIST which points to the pattern
190 of the insn to add, and the insn to be inserted before. */
191 rtx added_insns_list;
193 /* Identify which registers are safe to allocate for if conversions to
194 conditional execution. We keep the last allocated register in the
195 register classes between COND_EXEC statements. This will mean we allocate
196 different registers for each different COND_EXEC group if we can. This
197 might allow the scheduler to intermix two different COND_EXEC sections. */
198 frv_tmp_reg_t tmp_reg;
200 /* For nested IFs, identify which CC registers are used outside of setting
201 via a compare isnsn, and using via a check insn. This will allow us to
202 know if we can rewrite the register to use a different register that will
203 be paired with the CR register controlling the nested IF-THEN blocks. */
204 HARD_REG_SET nested_cc_ok_rewrite;
206 /* Temporary registers allocated to hold constants during conditional
208 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
210 /* Current number of temp registers available. */
211 int cur_scratch_regs;
213 /* Number of nested conditional execution blocks. */
214 int num_nested_cond_exec;
216 /* Map of insns that set up constants in scratch registers. */
217 bitmap scratch_insns_bitmap;
219 /* Conditional execution test register (CC0..CC7). */
222 /* Conditional execution compare register that is paired with cr_reg, so that
223 nested compares can be done. The csubcc and caddcc instructions don't
224 have enough bits to specify both a CC register to be set and a CR register
225 to do the test on, so the same bit number is used for both. Needless to
226 say, this is rather inconvenient for GCC. */
229 /* Extra CR registers used for &&, ||. */
233 /* Previous CR used in nested if, to make sure we are dealing with the same
234 nested if as the previous statement. */
235 rtx last_nested_if_cr;
239 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
241 /* Map register number to smallest register class. */
242 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
244 /* Map class letter into register class. */
245 enum reg_class reg_class_from_letter[256];
247 /* Cached value of frv_stack_info. */
248 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
250 /* -mbranch-cost= support */
251 const char *frv_branch_cost_string;
252 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
255 const char *frv_cpu_string; /* -mcpu= option */
256 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
258 /* -mcond-exec-insns= support */
259 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
260 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
262 /* -mcond-exec-temps= support */
263 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
264 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
266 /* -msched-lookahead=n */
267 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
268 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
270 /* Forward references */
271 static int frv_default_flags_for_cpu (void);
272 static int frv_string_begins_with (tree, const char *);
273 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
274 static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static const char *comparison_string (enum rtx_code, rtx);
280 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
281 static rtx single_set_pattern (rtx);
282 static int frv_function_contains_far_jump (void);
283 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
287 static rtx frv_frame_offset_rtx (int);
288 static rtx frv_frame_mem (enum machine_mode, rtx, int);
289 static rtx frv_dwarf_store (rtx, int);
290 static void frv_frame_insn (rtx, rtx);
291 static void frv_frame_access (frv_frame_accessor_t*,
293 static void frv_frame_access_multi (frv_frame_accessor_t*,
295 static void frv_frame_access_standard_regs (enum frv_stack_op,
297 static struct machine_function *frv_init_machine_status (void);
298 static int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
299 static rtx frv_int_to_acc (enum insn_code, int, rtx);
300 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
301 static rtx frv_read_argument (tree *);
302 static rtx frv_read_iacc_argument (enum machine_mode, tree *);
303 static int frv_check_constant_argument (enum insn_code, int, rtx);
304 static rtx frv_legitimize_target (enum insn_code, rtx);
305 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
306 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
309 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
312 static rtx frv_expand_int_void2arg (enum insn_code, tree);
313 static rtx frv_expand_prefetches (enum insn_code, tree);
314 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
315 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
316 static rtx frv_expand_mclracc_builtin (tree);
317 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
318 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
319 static rtx frv_expand_noargs_builtin (enum insn_code);
320 static void frv_split_iacc_move (rtx, rtx);
321 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
322 static int frv_clear_registers_used (rtx *, void *);
323 static void frv_ifcvt_add_insn (rtx, rtx, int);
324 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
325 static rtx frv_ifcvt_load_value (rtx, rtx);
326 static int frv_acc_group_1 (rtx *, void *);
327 static unsigned int frv_insn_unit (rtx);
328 static bool frv_issues_to_branch_unit_p (rtx);
329 static int frv_cond_flags (rtx);
330 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
331 static int frv_registers_conflict_p_1 (rtx *, void *);
332 static bool frv_registers_conflict_p (rtx);
333 static void frv_registers_update_1 (rtx, rtx, void *);
334 static void frv_registers_update (rtx);
335 static void frv_start_packet (void);
336 static void frv_start_packet_block (void);
337 static void frv_finish_packet (void (*) (void));
338 static bool frv_pack_insn_p (rtx);
339 static void frv_add_insn_to_packet (rtx);
340 static void frv_insert_nop_in_packet (rtx);
341 static bool frv_for_each_packet (void (*) (void));
342 static bool frv_sort_insn_group_1 (enum frv_insn_group,
343 unsigned int, unsigned int,
344 unsigned int, unsigned int,
346 static int frv_compare_insns (const void *, const void *);
347 static void frv_sort_insn_group (enum frv_insn_group);
348 static void frv_reorder_packet (void);
349 static void frv_fill_unused_units (enum frv_insn_group);
350 static void frv_align_label (void);
351 static void frv_reorg_packet (void);
352 static void frv_register_nop (rtx);
353 static void frv_reorg (void);
354 static void frv_pack_insns (void);
355 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
356 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
357 static bool frv_assemble_integer (rtx, unsigned, int);
358 static void frv_init_builtins (void);
359 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
360 static void frv_init_libfuncs (void);
361 static bool frv_in_small_data_p (tree);
362 static void frv_asm_output_mi_thunk
363 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
364 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
367 static rtx frv_expand_builtin_saveregs (void);
368 static bool frv_rtx_costs (rtx, int, int, int*);
369 static void frv_asm_out_constructor (rtx, int);
370 static void frv_asm_out_destructor (rtx, int);
371 static bool frv_function_symbol_referenced_p (rtx);
372 static bool frv_cannot_force_const_mem (rtx);
373 static const char *unspec_got_name (int);
374 static void frv_output_const_unspec (FILE *,
375 const struct frv_unspec *);
376 static bool frv_function_ok_for_sibcall (tree, tree);
377 static rtx frv_struct_value_rtx (tree, int);
378 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
379 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
382 /* Initialize the GCC target structure. */
383 #undef TARGET_ASM_FUNCTION_PROLOGUE
384 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
385 #undef TARGET_ASM_FUNCTION_EPILOGUE
386 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
387 #undef TARGET_ASM_INTEGER
388 #define TARGET_ASM_INTEGER frv_assemble_integer
389 #undef TARGET_INIT_BUILTINS
390 #define TARGET_INIT_BUILTINS frv_init_builtins
391 #undef TARGET_EXPAND_BUILTIN
392 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
393 #undef TARGET_INIT_LIBFUNCS
394 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
395 #undef TARGET_IN_SMALL_DATA_P
396 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
397 #undef TARGET_RTX_COSTS
398 #define TARGET_RTX_COSTS frv_rtx_costs
399 #undef TARGET_ASM_CONSTRUCTOR
400 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
401 #undef TARGET_ASM_DESTRUCTOR
402 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
404 #undef TARGET_ASM_OUTPUT_MI_THUNK
405 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
406 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
407 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
409 #undef TARGET_SCHED_ISSUE_RATE
410 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
412 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
413 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
414 #undef TARGET_CANNOT_FORCE_CONST_MEM
415 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
417 #undef TARGET_STRUCT_VALUE_RTX
418 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
419 #undef TARGET_MUST_PASS_IN_STACK
420 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
421 #undef TARGET_PASS_BY_REFERENCE
422 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
423 #undef TARGET_ARG_PARTIAL_BYTES
424 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
426 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
427 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
428 #undef TARGET_SETUP_INCOMING_VARARGS
429 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
430 #undef TARGET_MACHINE_DEPENDENT_REORG
431 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
433 struct gcc_target targetm = TARGET_INITIALIZER;
435 /* Any function call that satisfies the machine-independent
436 requirements is eligible on FR-V. */
439 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
440 tree exp ATTRIBUTE_UNUSED)
445 /* Return true if SYMBOL is a small data symbol and relocation RELOC
446 can be used to access it directly in a load or store. */
448 static FRV_INLINE bool
449 frv_small_data_reloc_p (rtx symbol, int reloc)
451 return (GET_CODE (symbol) == SYMBOL_REF
452 && SYMBOL_REF_SMALL_P (symbol)
453 && (!TARGET_FDPIC || flag_pic == 1)
454 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
457 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
460 static FRV_INLINE bool
461 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
463 if (GET_CODE (x) == CONST)
467 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
469 unspec->offset += INTVAL (XEXP (x, 1));
472 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
474 unspec->symbol = XVECEXP (x, 0, 0);
475 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
477 if (unspec->offset == 0)
480 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
481 && unspec->offset > 0
482 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
489 /* Decide whether we can force certain constants to memory. If we
490 decide we can't, the caller should be able to cope with it in
493 We never allow constants to be forced into memory for TARGET_FDPIC.
494 This is necessary for several reasons:
496 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
497 target-independent code will try to force them into the constant
498 pool, thus leading to infinite recursion.
500 2. We can never introduce new constant pool references during reload.
501 Any such reference would require use of the pseudo FDPIC register.
503 3. We can't represent a constant added to a function pointer (which is
504 not the same as a pointer to a function+constant).
506 4. In many cases, it's more efficient to calculate the constant in-line. */
509 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
515 frv_default_flags_for_cpu (void)
517 switch (frv_cpu_type)
519 case FRV_CPU_GENERIC:
520 return MASK_DEFAULT_FRV;
523 return MASK_DEFAULT_FR550;
527 return MASK_DEFAULT_FR500;
530 return MASK_DEFAULT_FR450;
534 return MASK_DEFAULT_FR400;
538 return MASK_DEFAULT_SIMPLE;
543 /* Sometimes certain combinations of command options do not make
544 sense on a particular target machine. You can define a macro
545 `OVERRIDE_OPTIONS' to take account of this. This macro, if
546 defined, is executed once just after all the command options have
549 Don't use this macro to turn on various extra optimizations for
550 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
553 frv_override_options (void)
558 /* Set the cpu type. */
561 if (strcmp (frv_cpu_string, "simple") == 0)
562 frv_cpu_type = FRV_CPU_SIMPLE;
564 else if (strcmp (frv_cpu_string, "tomcat") == 0)
565 frv_cpu_type = FRV_CPU_TOMCAT;
567 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
568 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
572 const char *p = frv_cpu_string + sizeof ("fr") - 1;
573 if (strcmp (p, "550") == 0)
574 frv_cpu_type = FRV_CPU_FR550;
576 else if (strcmp (p, "500") == 0)
577 frv_cpu_type = FRV_CPU_FR500;
579 else if (strcmp (p, "450") == 0)
580 frv_cpu_type = FRV_CPU_FR450;
582 else if (strcmp (p, "405") == 0)
583 frv_cpu_type = FRV_CPU_FR405;
585 else if (strcmp (p, "400") == 0)
586 frv_cpu_type = FRV_CPU_FR400;
588 else if (strcmp (p, "300") == 0)
589 frv_cpu_type = FRV_CPU_FR300;
591 else if (strcmp (p, "v") == 0)
592 frv_cpu_type = FRV_CPU_GENERIC;
595 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
599 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
601 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
602 linker about linking pic and non-pic code. */
605 if (!flag_pic) /* -fPIC */
608 if (! g_switch_set) /* -G0 */
615 /* Change the branch cost value. */
616 if (frv_branch_cost_string)
617 frv_branch_cost_int = atoi (frv_branch_cost_string);
619 /* Change the # of insns to be converted to conditional execution. */
620 if (frv_condexec_insns_str)
621 frv_condexec_insns = atoi (frv_condexec_insns_str);
623 /* Change # of temporary registers used to hold integer constants. */
624 if (frv_condexec_temps_str)
625 frv_condexec_temps = atoi (frv_condexec_temps_str);
627 /* Change scheduling look ahead. */
628 if (frv_sched_lookahead_str)
629 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
631 /* A C expression whose value is a register class containing hard
632 register REGNO. In general there is more than one such class;
633 choose a class which is "minimal", meaning that no smaller class
634 also contains the register. */
636 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
638 enum reg_class class;
642 int gpr_reg = regno - GPR_FIRST;
643 if ((gpr_reg & 3) == 0)
646 else if ((gpr_reg & 1) == 0)
653 else if (FPR_P (regno))
655 int fpr_reg = regno - GPR_FIRST;
656 if ((fpr_reg & 3) == 0)
657 class = QUAD_FPR_REGS;
659 else if ((fpr_reg & 1) == 0)
666 else if (regno == LR_REGNO)
669 else if (regno == LCR_REGNO)
672 else if (ICC_P (regno))
675 else if (FCC_P (regno))
678 else if (ICR_P (regno))
681 else if (FCR_P (regno))
684 else if (ACC_P (regno))
686 int r = regno - ACC_FIRST;
688 class = QUAD_ACC_REGS;
689 else if ((r & 1) == 0)
690 class = EVEN_ACC_REGS;
695 else if (ACCG_P (regno))
701 regno_reg_class[regno] = class;
704 /* Check for small data option */
706 g_switch_value = SDATA_DEFAULT_SIZE;
708 /* A C expression which defines the machine-dependent operand
709 constraint letters for register classes. If CHAR is such a
710 letter, the value should be the register class corresponding to
711 it. Otherwise, the value should be `NO_REGS'. The register
712 letter `r', corresponding to class `GENERAL_REGS', will not be
713 passed to this macro; you do not need to handle it.
715 The following letters are unavailable, due to being used as
720 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
721 'Q', 'R', 'S', 'T', 'U'
723 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
725 for (i = 0; i < 256; i++)
726 reg_class_from_letter[i] = NO_REGS;
728 reg_class_from_letter['a'] = ACC_REGS;
729 reg_class_from_letter['b'] = EVEN_ACC_REGS;
730 reg_class_from_letter['c'] = CC_REGS;
731 reg_class_from_letter['d'] = GPR_REGS;
732 reg_class_from_letter['e'] = EVEN_REGS;
733 reg_class_from_letter['f'] = FPR_REGS;
734 reg_class_from_letter['h'] = FEVEN_REGS;
735 reg_class_from_letter['l'] = LR_REG;
736 reg_class_from_letter['q'] = QUAD_REGS;
737 reg_class_from_letter['t'] = ICC_REGS;
738 reg_class_from_letter['u'] = FCC_REGS;
739 reg_class_from_letter['v'] = ICR_REGS;
740 reg_class_from_letter['w'] = FCR_REGS;
741 reg_class_from_letter['x'] = QUAD_FPR_REGS;
742 reg_class_from_letter['y'] = LCR_REG;
743 reg_class_from_letter['z'] = SPR_REGS;
744 reg_class_from_letter['A'] = QUAD_ACC_REGS;
745 reg_class_from_letter['B'] = ACCG_REGS;
746 reg_class_from_letter['C'] = CR_REGS;
747 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
748 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
750 /* There is no single unaligned SI op for PIC code. Sometimes we
751 need to use ".4byte" and sometimes we need to use ".picptr".
752 See frv_assemble_integer for details. */
753 if (flag_pic || TARGET_FDPIC)
754 targetm.asm_out.unaligned_op.si = 0;
756 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
757 target_flags |= MASK_LINKED_FP;
759 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
760 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
762 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
763 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
765 init_machine_status = frv_init_machine_status;
769 /* Some machines may desire to change what optimizations are performed for
770 various optimization levels. This macro, if defined, is executed once just
771 after the optimization level is determined and before the remainder of the
772 command options have been parsed. Values set in this macro are used as the
773 default values for the other command line options.
775 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
776 `-O' is specified, and 0 if neither is specified.
778 SIZE is nonzero if `-Os' is specified, 0 otherwise.
780 You should not use this macro to change options that are not
781 machine-specific. These should uniformly selected by the same optimization
782 level on all supported machines. Use this macro to enable machbine-specific
785 *Do not examine `write_symbols' in this macro!* The debugging options are
786 *not supposed to alter the generated code. */
788 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
789 scheduling pass at the current time. */
791 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
795 #ifdef DISABLE_SCHED2
796 flag_schedule_insns_after_reload = 0;
805 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
808 frv_string_begins_with (tree name, const char *prefix)
810 int prefix_len = strlen (prefix);
812 /* Remember: NAME's length includes the null terminator. */
813 return (TREE_STRING_LENGTH (name) > prefix_len
814 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
817 /* Zero or more C statements that may conditionally modify two variables
818 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
819 been initialized from the two preceding macros.
821 This is necessary in case the fixed or call-clobbered registers depend on
824 You need not define this macro if it has no work to do.
826 If the usage of an entire class of registers depends on the target flags,
827 you may indicate this to GCC by using this macro to modify `fixed_regs' and
828 `call_used_regs' to 1 for each of the registers in the classes which should
829 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
830 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
832 (However, if this class is not included in `GENERAL_REGS' and all of the
833 insn patterns whose constraints permit this class are controlled by target
834 switches, then GCC will automatically avoid using these registers when the
835 target switches are opposed to them.) */
838 frv_conditional_register_usage (void)
842 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
843 fixed_regs[i] = call_used_regs[i] = 1;
845 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
846 fixed_regs[i] = call_used_regs[i] = 1;
848 /* Reserve the registers used for conditional execution. At present, we need
849 1 ICC and 1 ICR register. */
850 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
851 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
855 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
856 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
857 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
858 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
862 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
863 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
866 /* If -fpic, SDA_BASE_REG is the PIC register. */
867 if (g_switch_value == 0 && !flag_pic)
868 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
871 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
877 * Compute the stack frame layout
880 * +---------------+-----------------------+-----------------------+
881 * |Register |type |caller-save/callee-save|
882 * +---------------+-----------------------+-----------------------+
883 * |GR0 |Zero register | - |
884 * |GR1 |Stack pointer(SP) | - |
885 * |GR2 |Frame pointer(FP) | - |
886 * |GR3 |Hidden parameter | caller save |
887 * |GR4-GR7 | - | caller save |
888 * |GR8-GR13 |Argument register | caller save |
889 * |GR14-GR15 | - | caller save |
890 * |GR16-GR31 | - | callee save |
891 * |GR32-GR47 | - | caller save |
892 * |GR48-GR63 | - | callee save |
893 * |FR0-FR15 | - | caller save |
894 * |FR16-FR31 | - | callee save |
895 * |FR32-FR47 | - | caller save |
896 * |FR48-FR63 | - | callee save |
897 * +---------------+-----------------------+-----------------------+
901 * SP-> |-----------------------------------|
903 * |-----------------------------------|
904 * | Register save area |
905 * |-----------------------------------|
906 * | Local variable save area |
907 * FP-> |-----------------------------------|
909 * |-----------------------------------|
910 * | Hidden parameter save area |
911 * |-----------------------------------|
912 * | Return address(LR) storage area |
913 * |-----------------------------------|
914 * | Padding for alignment |
915 * |-----------------------------------|
916 * | Register argument area |
917 * OLD SP-> |-----------------------------------|
919 * |-----------------------------------|
922 * Argument area/Parameter area:
924 * When a function is called, this area is used for argument transfer. When
925 * the argument is set up by the caller function, this area is referred to as
926 * the argument area. When the argument is referenced by the callee function,
927 * this area is referred to as the parameter area. The area is allocated when
928 * all arguments cannot be placed on the argument register at the time of
931 * Register save area:
933 * This is a register save area that must be guaranteed for the caller
934 * function. This area is not secured when the register save operation is not
937 * Local variable save area:
939 * This is the area for local variables and temporary variables.
943 * This area stores the FP value of the caller function.
945 * Hidden parameter save area:
947 * This area stores the start address of the return value storage
948 * area for a struct/union return function.
949 * When a struct/union is used as the return value, the caller
950 * function stores the return value storage area start address in
951 * register GR3 and passes it to the caller function.
952 * The callee function interprets the address stored in the GR3
953 * as the return value storage area start address.
954 * When register GR3 needs to be saved into memory, the callee
955 * function saves it in the hidden parameter save area. This
956 * area is not secured when the save operation is not needed.
958 * Return address(LR) storage area:
960 * This area saves the LR. The LR stores the address of a return to the caller
961 * function for the purpose of function calling.
963 * Argument register area:
965 * This area saves the argument register. This area is not secured when the
966 * save operation is not needed.
970 * Arguments, the count of which equals the count of argument registers (6
971 * words), are positioned in registers GR8 to GR13 and delivered to the callee
972 * function. When a struct/union return function is called, the return value
973 * area address is stored in register GR3. Arguments not placed in the
974 * argument registers will be stored in the stack argument area for transfer
975 * purposes. When an 8-byte type argument is to be delivered using registers,
976 * it is divided into two and placed in two registers for transfer. When
977 * argument registers must be saved to memory, the callee function secures an
978 * argument register save area in the stack. In this case, a continuous
979 * argument register save area must be established in the parameter area. The
980 * argument register save area must be allocated as needed to cover the size of
981 * the argument register to be saved. If the function has a variable count of
982 * arguments, it saves all argument registers in the argument register save
985 * Argument Extension Format:
987 * When an argument is to be stored in the stack, its type is converted to an
988 * extended type in accordance with the individual argument type. The argument
989 * is freed by the caller function after the return from the callee function is
992 * +-----------------------+---------------+------------------------+
993 * | Argument Type |Extended Type |Stack Storage Size(byte)|
994 * +-----------------------+---------------+------------------------+
996 * |signed char |int | 4 |
997 * |unsigned char |int | 4 |
998 * |[signed] short int |int | 4 |
999 * |unsigned short int |int | 4 |
1000 * |[signed] int |No extension | 4 |
1001 * |unsigned int |No extension | 4 |
1002 * |[signed] long int |No extension | 4 |
1003 * |unsigned long int |No extension | 4 |
1004 * |[signed] long long int |No extension | 8 |
1005 * |unsigned long long int |No extension | 8 |
1006 * |float |double | 8 |
1007 * |double |No extension | 8 |
1008 * |long double |No extension | 8 |
1009 * |pointer |No extension | 4 |
1010 * |struct/union |- | 4 (*1) |
1011 * +-----------------------+---------------+------------------------+
1013 * When a struct/union is to be delivered as an argument, the caller copies it
1014 * to the local variable area and delivers the address of that area.
1018 * +-------------------------------+----------------------+
1019 * |Return Value Type |Return Value Interface|
1020 * +-------------------------------+----------------------+
1022 * |[signed|unsigned] char |GR8 |
1023 * |[signed|unsigned] short int |GR8 |
1024 * |[signed|unsigned] int |GR8 |
1025 * |[signed|unsigned] long int |GR8 |
1027 * |[signed|unsigned] long long int|GR8 & GR9 |
1029 * |double |GR8 & GR9 |
1030 * |long double |GR8 & GR9 |
1031 * |struct/union |(*1) |
1032 * +-------------------------------+----------------------+
1034 * When a struct/union is used as the return value, the caller function stores
1035 * the start address of the return value storage area into GR3 and then passes
1036 * it to the callee function. The callee function interprets GR3 as the start
1037 * address of the return value storage area. When this address needs to be
1038 * saved in memory, the callee function secures the hidden parameter save area
1039 * and saves the address in that area.
1043 frv_stack_info (void)
1045 static frv_stack_t info, zero_info;
1046 frv_stack_t *info_ptr = &info;
1047 tree fndecl = current_function_decl;
1055 /* If we've already calculated the values and reload is complete,
1057 if (frv_stack_cache)
1058 return frv_stack_cache;
1060 /* Zero all fields. */
1063 /* Set up the register range information. */
1064 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1065 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1066 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1067 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1069 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1070 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1071 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1072 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1074 info_ptr->regs[STACK_REGS_LR].name = "lr";
1075 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1076 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1077 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1079 info_ptr->regs[STACK_REGS_CC].name = "cc";
1080 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1081 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1082 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1084 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1085 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1086 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1088 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1089 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1090 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1091 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1092 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1094 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1095 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1096 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1097 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1099 info_ptr->regs[STACK_REGS_FP].name = "fp";
1100 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1101 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1102 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1104 /* Determine if this is a stdarg function. If so, allocate space to store
1111 /* Find the last argument, and see if it is __builtin_va_alist. */
1112 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1114 next_arg = TREE_CHAIN (cur_arg);
1115 if (next_arg == (tree)0)
1117 if (DECL_NAME (cur_arg)
1118 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1126 /* Iterate over all of the register ranges. */
1127 for (range = 0; range < STACK_REGS_MAX; range++)
1129 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1130 int first = reg_ptr->first;
1131 int last = reg_ptr->last;
1133 int size_2words = 0;
1136 /* Calculate which registers need to be saved & save area size. */
1140 for (regno = first; regno <= last; regno++)
1142 if ((regs_ever_live[regno] && !call_used_regs[regno])
1143 || (current_function_calls_eh_return
1144 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1145 || (!TARGET_FDPIC && flag_pic
1146 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1148 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1149 size_1word += UNITS_PER_WORD;
1154 /* Calculate whether we need to create a frame after everything else
1155 has been processed. */
1160 if (regs_ever_live[LR_REGNO]
1162 /* This is set for __builtin_return_address, etc. */
1163 || cfun->machine->frame_needed
1164 || (TARGET_LINKED_FP && frame_pointer_needed)
1165 || (!TARGET_FDPIC && flag_pic
1166 && cfun->uses_pic_offset_table))
1168 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1169 size_1word += UNITS_PER_WORD;
1173 case STACK_REGS_STDARG:
1176 /* If this is a stdarg function with a non varardic
1177 argument split between registers and the stack,
1178 adjust the saved registers downward. */
1179 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1182 for (regno = first; regno <= last; regno++)
1184 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1185 size_1word += UNITS_PER_WORD;
1188 info_ptr->stdarg_size = size_1word;
1192 case STACK_REGS_STRUCT:
1193 if (cfun->returns_struct)
1195 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1196 size_1word += UNITS_PER_WORD;
1204 /* If this is a field, it only takes one word. */
1205 if (reg_ptr->field_p)
1206 size_1word = UNITS_PER_WORD;
1208 /* Determine which register pairs can be saved together. */
1209 else if (reg_ptr->dword_p && TARGET_DWORD)
1211 for (regno = first; regno < last; regno += 2)
1213 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1215 size_2words += 2 * UNITS_PER_WORD;
1216 size_1word -= 2 * UNITS_PER_WORD;
1217 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1218 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1223 reg_ptr->size_1word = size_1word;
1224 reg_ptr->size_2words = size_2words;
1226 if (! reg_ptr->special_p)
1228 info_ptr->regs_size_1word += size_1word;
1229 info_ptr->regs_size_2words += size_2words;
1234 /* Set up the sizes of each each field in the frame body, making the sizes
1235 of each be divisible by the size of a dword if dword operations might
1236 be used, or the size of a word otherwise. */
1237 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1239 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1240 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1241 + info_ptr->regs_size_1word,
1243 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1245 info_ptr->pretend_size = cfun->pretend_args_size;
1247 /* Work out the size of the frame, excluding the header. Both the frame
1248 body and register parameter area will be dword-aligned. */
1249 info_ptr->total_size
1250 = (ADDR_ALIGN (info_ptr->parameter_size
1251 + info_ptr->regs_size
1252 + info_ptr->vars_size,
1254 + ADDR_ALIGN (info_ptr->pretend_size
1255 + info_ptr->stdarg_size,
1256 2 * UNITS_PER_WORD));
1258 /* See if we need to create a frame at all, if so add header area. */
1259 if (info_ptr->total_size > 0
1260 || frame_pointer_needed
1261 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1262 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1264 offset = info_ptr->parameter_size;
1265 info_ptr->header_size = 4 * UNITS_PER_WORD;
1266 info_ptr->total_size += 4 * UNITS_PER_WORD;
1268 /* Calculate the offsets to save normal register pairs. */
1269 for (range = 0; range < STACK_REGS_MAX; range++)
1271 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1272 if (! reg_ptr->special_p)
1274 int first = reg_ptr->first;
1275 int last = reg_ptr->last;
1278 for (regno = first; regno <= last; regno++)
1279 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1280 && regno != FRAME_POINTER_REGNUM
1281 && (regno < FIRST_ARG_REGNUM
1282 || regno > LAST_ARG_REGNUM))
1284 info_ptr->reg_offset[regno] = offset;
1285 offset += 2 * UNITS_PER_WORD;
1290 /* Calculate the offsets to save normal single registers. */
1291 for (range = 0; range < STACK_REGS_MAX; range++)
1293 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1294 if (! reg_ptr->special_p)
1296 int first = reg_ptr->first;
1297 int last = reg_ptr->last;
1300 for (regno = first; regno <= last; regno++)
1301 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1302 && regno != FRAME_POINTER_REGNUM
1303 && (regno < FIRST_ARG_REGNUM
1304 || regno > LAST_ARG_REGNUM))
1306 info_ptr->reg_offset[regno] = offset;
1307 offset += UNITS_PER_WORD;
1312 /* Calculate the offset to save the local variables at. */
1313 offset = ADDR_ALIGN (offset, alignment);
1314 if (info_ptr->vars_size)
1316 info_ptr->vars_offset = offset;
1317 offset += info_ptr->vars_size;
1320 /* Align header to a dword-boundary. */
1321 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1323 /* Calculate the offsets in the fixed frame. */
1324 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1325 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1326 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1328 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1329 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1330 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1332 if (cfun->returns_struct)
1334 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1335 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1336 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1339 /* Calculate the offsets to store the arguments passed in registers
1340 for stdarg functions. The register pairs are first and the single
1341 register if any is last. The register save area starts on a
1343 if (info_ptr->stdarg_size)
1345 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1346 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1349 /* Skip the header. */
1350 offset += 4 * UNITS_PER_WORD;
1351 for (regno = first; regno <= last; regno++)
1353 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1355 info_ptr->reg_offset[regno] = offset;
1356 offset += 2 * UNITS_PER_WORD;
1358 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1360 info_ptr->reg_offset[regno] = offset;
1361 offset += UNITS_PER_WORD;
1367 if (reload_completed)
1368 frv_stack_cache = info_ptr;
1374 /* Print the information about the frv stack offsets, etc. when debugging. */
1377 frv_debug_stack (frv_stack_t *info)
1382 info = frv_stack_info ();
1384 fprintf (stderr, "\nStack information for function %s:\n",
1385 ((current_function_decl && DECL_NAME (current_function_decl))
1386 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1389 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1390 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1391 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1392 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1393 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1395 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1396 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1397 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1398 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1400 for (range = 0; range < STACK_REGS_MAX; range++)
1402 frv_stack_regs_t *regs = &(info->regs[range]);
1403 if ((regs->size_1word + regs->size_2words) > 0)
1405 int first = regs->first;
1406 int last = regs->last;
1409 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1410 regs->name, regs->size_1word + regs->size_2words,
1411 regs->size_1word, regs->size_2words);
1413 for (regno = first; regno <= last; regno++)
1415 if (info->save_p[regno] == REG_SAVE_1WORD)
1416 fprintf (stderr, " %s (%d)", reg_names[regno],
1417 info->reg_offset[regno]);
1419 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1420 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1421 reg_names[regno+1], info->reg_offset[regno]);
1424 fputc ('\n', stderr);
1434 /* Used during final to control the packing of insns. The value is
1435 1 if the current instruction should be packed with the next one,
1436 0 if it shouldn't or -1 if packing is disabled altogether. */
1438 static int frv_insn_packing_flag;
1440 /* True if the current function contains a far jump. */
1443 frv_function_contains_far_jump (void)
1445 rtx insn = get_insns ();
1447 && !(GET_CODE (insn) == JUMP_INSN
1448 /* Ignore tablejump patterns. */
1449 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1450 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1451 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1452 insn = NEXT_INSN (insn);
1453 return (insn != NULL);
1456 /* For the FRV, this function makes sure that a function with far jumps
1457 will return correctly. It also does the VLIW packing. */
1460 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1462 /* If no frame was created, check whether the function uses a call
1463 instruction to implement a far jump. If so, save the link in gr3 and
1464 replace all returns to LR with returns to GR3. GR3 is used because it
1465 is call-clobbered, because is not available to the register allocator,
1466 and because all functions that take a hidden argument pointer will have
1468 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1472 /* Just to check that the above comment is true. */
1473 if (regs_ever_live[GPR_FIRST + 3])
1476 /* Generate the instruction that saves the link register. */
1477 fprintf (file, "\tmovsg lr,gr3\n");
1479 /* Replace the LR with GR3 in *return_internal patterns. The insn
1480 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1481 simply emit a different assembly directive because bralr and jmpl
1482 execute in different units. */
1483 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1484 if (GET_CODE (insn) == JUMP_INSN)
1486 rtx pattern = PATTERN (insn);
1487 if (GET_CODE (pattern) == PARALLEL
1488 && XVECLEN (pattern, 0) >= 2
1489 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1490 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1492 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1493 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1494 REGNO (address) = GPR_FIRST + 3;
1501 /* Allow the garbage collector to free the nops created by frv_reorg. */
1502 memset (frv_nops, 0, sizeof (frv_nops));
1506 /* Return the next available temporary register in a given class. */
1509 frv_alloc_temp_reg (
1510 frv_tmp_reg_t *info, /* which registers are available */
1511 enum reg_class class, /* register class desired */
1512 enum machine_mode mode, /* mode to allocate register with */
1513 int mark_as_used, /* register not available after allocation */
1514 int no_abort) /* return NULL instead of aborting */
1516 int regno = info->next_reg[ (int)class ];
1517 int orig_regno = regno;
1518 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1523 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1524 && TEST_HARD_REG_BIT (info->regs, regno))
1527 if (++regno >= FIRST_PSEUDO_REGISTER)
1529 if (regno == orig_regno)
1538 nr = HARD_REGNO_NREGS (regno, mode);
1539 info->next_reg[ (int)class ] = regno + nr;
1542 for (i = 0; i < nr; i++)
1543 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1545 return gen_rtx_REG (mode, regno);
1549 /* Return an rtx with the value OFFSET, which will either be a register or a
1550 signed 12-bit integer. It can be used as the second operand in an "add"
1551 instruction, or as the index in a load or store.
1553 The function returns a constant rtx if OFFSET is small enough, otherwise
1554 it loads the constant into register OFFSET_REGNO and returns that. */
1556 frv_frame_offset_rtx (int offset)
1558 rtx offset_rtx = GEN_INT (offset);
1559 if (IN_RANGE_P (offset, -2048, 2047))
1563 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1564 if (IN_RANGE_P (offset, -32768, 32767))
1565 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1568 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1569 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1575 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1576 prologue and epilogue uses such expressions to access the stack. */
1578 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1580 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1582 frv_frame_offset_rtx (offset)));
1585 /* Generate a frame-related expression:
1587 (set REG (mem (plus (sp) (const_int OFFSET)))).
1589 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1590 instructions. Marking the expressions as frame-related is superfluous if
1591 the note contains just a single set. But if the note contains a PARALLEL
1592 or SEQUENCE that has several sets, each set must be individually marked
1593 as frame-related. */
1595 frv_dwarf_store (rtx reg, int offset)
1597 rtx set = gen_rtx_SET (VOIDmode,
1598 gen_rtx_MEM (GET_MODE (reg),
1599 plus_constant (stack_pointer_rtx,
1602 RTX_FRAME_RELATED_P (set) = 1;
1606 /* Emit a frame-related instruction whose pattern is PATTERN. The
1607 instruction is the last in a sequence that cumulatively performs the
1608 operation described by DWARF_PATTERN. The instruction is marked as
1609 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1612 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1614 rtx insn = emit_insn (pattern);
1615 RTX_FRAME_RELATED_P (insn) = 1;
1616 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1621 /* Emit instructions that transfer REG to or from the memory location (sp +
1622 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1623 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1624 function to store registers and only the epilogue uses it to load them.
1626 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1627 The generated instruction will use BASE as its base register. BASE may
1628 simply be the stack pointer, but if several accesses are being made to a
1629 region far away from the stack pointer, it may be more efficient to set
1630 up a temporary instead.
1632 Store instructions will be frame-related and will be annotated with the
1633 overall effect of the store. Load instructions will be followed by a
1634 (use) to prevent later optimizations from zapping them.
1636 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1637 as a temporary in such cases. */
1639 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1641 enum machine_mode mode = GET_MODE (reg);
1642 rtx mem = frv_frame_mem (mode,
1644 stack_offset - accessor->base_offset);
1646 if (accessor->op == FRV_LOAD)
1648 if (SPR_P (REGNO (reg)))
1650 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1651 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1652 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1655 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1656 emit_insn (gen_rtx_USE (VOIDmode, reg));
1660 if (SPR_P (REGNO (reg)))
1662 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1663 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1664 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1665 frv_dwarf_store (reg, stack_offset));
1667 else if (GET_MODE (reg) == DImode)
1669 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1670 with a separate save for each register. */
1671 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1672 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1673 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1674 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1675 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1676 gen_rtx_PARALLEL (VOIDmode,
1677 gen_rtvec (2, set1, set2)));
1680 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1681 frv_dwarf_store (reg, stack_offset));
1685 /* A function that uses frv_frame_access to transfer a group of registers to
1686 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1687 is the stack information generated by frv_stack_info, and REG_SET is the
1688 number of the register set to transfer. */
1690 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1694 frv_stack_regs_t *regs_info;
1697 regs_info = &info->regs[reg_set];
1698 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1699 if (info->save_p[regno])
1700 frv_frame_access (accessor,
1701 info->save_p[regno] == REG_SAVE_2WORDS
1702 ? gen_rtx_REG (DImode, regno)
1703 : gen_rtx_REG (SImode, regno),
1704 info->reg_offset[regno]);
1707 /* Save or restore callee-saved registers that are kept outside the frame
1708 header. The function saves the registers if OP is FRV_STORE and restores
1709 them if OP is FRV_LOAD. INFO is the stack information generated by
1712 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1714 frv_frame_accessor_t accessor;
1717 accessor.base = stack_pointer_rtx;
1718 accessor.base_offset = 0;
1719 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1720 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1721 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1725 /* Called after register allocation to add any instructions needed for the
1726 prologue. Using a prologue insn is favored compared to putting all of the
1727 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1728 it allows the scheduler to intermix instructions with the saves of
1729 the caller saved registers. In some cases, it might be necessary
1730 to emit a barrier instruction as the last insn to prevent such
1733 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1734 so that the debug info generation code can handle them properly. */
1736 frv_expand_prologue (void)
1738 frv_stack_t *info = frv_stack_info ();
1739 rtx sp = stack_pointer_rtx;
1740 rtx fp = frame_pointer_rtx;
1741 frv_frame_accessor_t accessor;
1743 if (TARGET_DEBUG_STACK)
1744 frv_debug_stack (info);
1746 if (info->total_size == 0)
1749 /* We're interested in three areas of the frame here:
1751 A: the register save area
1753 C: the header after B
1755 If the frame pointer isn't used, we'll have to set up A, B and C
1756 using the stack pointer. If the frame pointer is used, we'll access
1760 B: set up using sp or a temporary (see below)
1763 We set up B using the stack pointer if the frame is small enough.
1764 Otherwise, it's more efficient to copy the old stack pointer into a
1765 temporary and use that.
1767 Note that it's important to make sure the prologue and epilogue use the
1768 same registers to access A and C, since doing otherwise will confuse
1769 the aliasing code. */
1771 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1772 isn't used, the same method will serve for C. */
1773 accessor.op = FRV_STORE;
1774 if (frame_pointer_needed && info->total_size > 2048)
1778 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1779 accessor.base_offset = info->total_size;
1780 insn = emit_insn (gen_movsi (accessor.base, sp));
1784 accessor.base = stack_pointer_rtx;
1785 accessor.base_offset = 0;
1788 /* Allocate the stack space. */
1790 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1791 rtx dwarf_offset = GEN_INT (-info->total_size);
1793 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1796 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1799 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1800 and point the new one to that location. */
1801 if (frame_pointer_needed)
1803 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1805 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1806 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1808 rtx asm_src = plus_constant (accessor.base,
1809 fp_offset - accessor.base_offset);
1810 rtx dwarf_src = plus_constant (sp, fp_offset);
1812 /* Store the old frame pointer at (sp + FP_OFFSET). */
1813 frv_frame_access (&accessor, fp, fp_offset);
1815 /* Set up the new frame pointer. */
1816 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1817 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1819 /* Access region C from the frame pointer. */
1821 accessor.base_offset = fp_offset;
1824 /* Set up region C. */
1825 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1826 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1827 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1829 /* Set up region A. */
1830 frv_frame_access_standard_regs (FRV_STORE, info);
1832 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1833 scheduler from moving loads before the stores saving the registers. */
1834 if (info->stdarg_size > 0)
1835 emit_insn (gen_blockage ());
1837 /* Set up pic register/small data register for this function. */
1838 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1839 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1840 gen_rtx_REG (Pmode, LR_REGNO),
1841 gen_rtx_REG (SImode, OFFSET_REGNO)));
1845 /* Under frv, all of the work is done via frv_expand_epilogue, but
1846 this function provides a convenient place to do cleanup. */
1849 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1850 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1852 frv_stack_cache = (frv_stack_t *)0;
1854 /* Zap last used registers for conditional execution. */
1855 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1857 /* Release the bitmap of created insns. */
1858 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1862 /* Called after register allocation to add any instructions needed for the
1863 epilogue. Using an epilogue insn is favored compared to putting all of the
1864 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1865 it allows the scheduler to intermix instructions with the saves of
1866 the caller saved registers. In some cases, it might be necessary
1867 to emit a barrier instruction as the last insn to prevent such
1871 frv_expand_epilogue (bool emit_return)
1873 frv_stack_t *info = frv_stack_info ();
1874 rtx fp = frame_pointer_rtx;
1875 rtx sp = stack_pointer_rtx;
1879 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1881 /* Restore the stack pointer to its original value if alloca or the like
1883 if (! current_function_sp_is_unchanging)
1884 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1886 /* Restore the callee-saved registers that were used in this function. */
1887 frv_frame_access_standard_regs (FRV_LOAD, info);
1889 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1890 no return instruction should be emitted. */
1891 if (info->save_p[LR_REGNO])
1896 /* Use the same method to access the link register's slot as we did in
1897 the prologue. In other words, use the frame pointer if available,
1898 otherwise use the stack pointer.
1900 LR_OFFSET is the offset of the link register's slot from the start
1901 of the frame and MEM is a memory rtx for it. */
1902 lr_offset = info->reg_offset[LR_REGNO];
1903 if (frame_pointer_needed)
1904 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1906 mem = frv_frame_mem (Pmode, sp, lr_offset);
1908 /* Load the old link register into a GPR. */
1909 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1910 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1913 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1915 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1916 the load is preserved. */
1917 if (frame_pointer_needed)
1919 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1920 emit_insn (gen_rtx_USE (VOIDmode, fp));
1923 /* Deallocate the stack frame. */
1924 if (info->total_size != 0)
1926 rtx offset = frv_frame_offset_rtx (info->total_size);
1927 emit_insn (gen_stack_adjust (sp, sp, offset));
1930 /* If this function uses eh_return, add the final stack adjustment now. */
1931 if (current_function_calls_eh_return)
1932 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1935 emit_jump_insn (gen_epilogue_return (return_addr));
1938 rtx lr = return_addr;
1940 if (REGNO (return_addr) != LR_REGNO)
1942 lr = gen_rtx_REG (Pmode, LR_REGNO);
1943 emit_move_insn (lr, return_addr);
1946 emit_insn (gen_rtx_USE (VOIDmode, lr));
1951 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1954 frv_asm_output_mi_thunk (FILE *file,
1955 tree thunk_fndecl ATTRIBUTE_UNUSED,
1956 HOST_WIDE_INT delta,
1957 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1960 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1961 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1962 const char *name_jmp = reg_names[JUMP_REGNO];
1963 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1965 /* Do the add using an addi if possible. */
1966 if (IN_RANGE_P (delta, -2048, 2047))
1967 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1970 const char *const name_add = reg_names[TEMP_REGNO];
1971 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1972 parallel, delta, name_add);
1973 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1975 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1980 const char *name_pic = reg_names[FDPIC_REGNO];
1981 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1985 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1986 assemble_name (file, name_func);
1987 fprintf (file, "),%s\n", name_jmp);
1989 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1990 assemble_name (file, name_func);
1991 fprintf (file, "),%s\n", name_jmp);
1993 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1997 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
1998 assemble_name (file, name_func);
1999 fprintf (file, "\t)), %s\n", name_jmp);
2004 fprintf (file, "\tsethi%s #hi(", parallel);
2005 assemble_name (file, name_func);
2006 fprintf (file, "),%s\n", name_jmp);
2008 fprintf (file, "\tsetlo #lo(");
2009 assemble_name (file, name_func);
2010 fprintf (file, "),%s\n", name_jmp);
2014 /* Use JUMP_REGNO as a temporary PIC register. */
2015 const char *name_lr = reg_names[LR_REGNO];
2016 const char *name_gppic = name_jmp;
2017 const char *name_tmp = reg_names[TEMP_REGNO];
2019 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2020 fprintf (file, "\tcall 1f\n");
2021 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2022 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2023 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2024 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2025 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2027 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2028 assemble_name (file, name_func);
2029 fprintf (file, "),%s\n", name_tmp);
2031 fprintf (file, "\tsetlo #gprello(");
2032 assemble_name (file, name_func);
2033 fprintf (file, "),%s\n", name_tmp);
2035 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2038 /* Jump to the function address. */
2039 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2043 /* A C expression which is nonzero if a function must have and use a frame
2044 pointer. This expression is evaluated in the reload pass. If its value is
2045 nonzero the function will have a frame pointer.
2047 The expression can in principle examine the current function and decide
2048 according to the facts, but on most machines the constant 0 or the constant
2049 1 suffices. Use 0 when the machine allows code to be generated with no
2050 frame pointer, and doing so saves some time or space. Use 1 when there is
2051 no possible advantage to avoiding a frame pointer.
2053 In certain cases, the compiler does not know how to produce valid code
2054 without a frame pointer. The compiler recognizes those cases and
2055 automatically gives the function a frame pointer regardless of what
2056 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2058 In a function that does not require a frame pointer, the frame pointer
2059 register can be allocated for ordinary usage, unless you mark it as a fixed
2060 register. See `FIXED_REGISTERS' for more information. */
2062 /* On frv, create a frame whenever we need to create stack. */
2065 frv_frame_pointer_required (void)
2067 /* If we forgoing the usual linkage requirements, we only need
2068 a frame pointer if the stack pointer might change. */
2069 if (!TARGET_LINKED_FP)
2070 return !current_function_sp_is_unchanging;
2072 if (! current_function_is_leaf)
2075 if (get_frame_size () != 0)
2081 if (!current_function_sp_is_unchanging)
2084 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
2090 if (cfun->machine->frame_needed)
2097 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2098 initial difference between the specified pair of registers. This macro must
2099 be defined if `ELIMINABLE_REGS' is defined. */
2101 /* See frv_stack_info for more details on the frv stack frame. */
2104 frv_initial_elimination_offset (int from, int to)
2106 frv_stack_t *info = frv_stack_info ();
2109 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2110 ret = info->total_size - info->pretend_size;
2112 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2113 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2115 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2116 ret = (info->total_size
2117 - info->reg_offset[FRAME_POINTER_REGNUM]
2118 - info->pretend_size);
2123 if (TARGET_DEBUG_STACK)
2124 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2125 reg_names [from], reg_names[to], ret);
2131 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2134 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2135 enum machine_mode mode,
2136 tree type ATTRIBUTE_UNUSED,
2140 if (TARGET_DEBUG_ARG)
2142 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2143 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2147 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2150 frv_expand_builtin_saveregs (void)
2152 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2154 if (TARGET_DEBUG_ARG)
2155 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2158 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2162 /* Expand __builtin_va_start to do the va_start macro. */
2165 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2168 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2170 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2171 GEN_INT (UNITS_PER_WORD * num));
2173 if (TARGET_DEBUG_ARG)
2175 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2176 cfun->args_info, num);
2178 debug_rtx (nextarg);
2181 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2182 make_tree (ptr_type_node, nextarg));
2183 TREE_SIDE_EFFECTS (t) = 1;
2185 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2189 /* Expand a block move operation, and return 1 if successful. Return 0
2190 if we should let the compiler generate normal code.
2192 operands[0] is the destination
2193 operands[1] is the source
2194 operands[2] is the length
2195 operands[3] is the alignment */
2197 /* Maximum number of loads to do before doing the stores */
2198 #ifndef MAX_MOVE_REG
2199 #define MAX_MOVE_REG 4
2202 /* Maximum number of total loads to do. */
2203 #ifndef TOTAL_MOVE_REG
2204 #define TOTAL_MOVE_REG 8
2208 frv_expand_block_move (rtx operands[])
2210 rtx orig_dest = operands[0];
2211 rtx orig_src = operands[1];
2212 rtx bytes_rtx = operands[2];
2213 rtx align_rtx = operands[3];
2214 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2227 rtx stores[MAX_MOVE_REG];
2229 enum machine_mode mode;
2231 /* If this is not a fixed size move, just call memcpy. */
2235 /* If this is not a fixed size alignment, abort. */
2236 if (GET_CODE (align_rtx) != CONST_INT)
2239 align = INTVAL (align_rtx);
2241 /* Anything to move? */
2242 bytes = INTVAL (bytes_rtx);
2246 /* Don't support real large moves. */
2247 if (bytes > TOTAL_MOVE_REG*align)
2250 /* Move the address into scratch registers. */
2251 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2252 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2254 num_reg = offset = 0;
2255 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2257 /* Calculate the correct offset for src/dest. */
2261 dest_addr = dest_reg;
2265 src_addr = plus_constant (src_reg, offset);
2266 dest_addr = plus_constant (dest_reg, offset);
2269 /* Generate the appropriate load and store, saving the stores
2271 if (bytes >= 4 && align >= 4)
2273 else if (bytes >= 2 && align >= 2)
2278 move_bytes = GET_MODE_SIZE (mode);
2279 tmp_reg = gen_reg_rtx (mode);
2280 src_mem = change_address (orig_src, mode, src_addr);
2281 dest_mem = change_address (orig_dest, mode, dest_addr);
2282 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2283 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2285 if (num_reg >= MAX_MOVE_REG)
2287 for (i = 0; i < num_reg; i++)
2288 emit_insn (stores[i]);
2293 for (i = 0; i < num_reg; i++)
2294 emit_insn (stores[i]);
2300 /* Expand a block clear operation, and return 1 if successful. Return 0
2301 if we should let the compiler generate normal code.
2303 operands[0] is the destination
2304 operands[1] is the length
2305 operands[2] is the alignment */
2308 frv_expand_block_clear (rtx operands[])
2310 rtx orig_dest = operands[0];
2311 rtx bytes_rtx = operands[1];
2312 rtx align_rtx = operands[2];
2313 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2322 enum machine_mode mode;
2324 /* If this is not a fixed size move, just call memcpy. */
2328 /* If this is not a fixed size alignment, abort. */
2329 if (GET_CODE (align_rtx) != CONST_INT)
2332 align = INTVAL (align_rtx);
2334 /* Anything to move? */
2335 bytes = INTVAL (bytes_rtx);
2339 /* Don't support real large clears. */
2340 if (bytes > TOTAL_MOVE_REG*align)
2343 /* Move the address into a scratch register. */
2344 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2346 num_reg = offset = 0;
2347 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2349 /* Calculate the correct offset for src/dest. */
2350 dest_addr = ((offset == 0)
2352 : plus_constant (dest_reg, offset));
2354 /* Generate the appropriate store of gr0. */
2355 if (bytes >= 4 && align >= 4)
2357 else if (bytes >= 2 && align >= 2)
2362 clear_bytes = GET_MODE_SIZE (mode);
2363 dest_mem = change_address (orig_dest, mode, dest_addr);
2364 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2371 /* The following variable is used to output modifiers of assembler
2372 code of the current output insn. */
2374 static rtx *frv_insn_operands;
2376 /* The following function is used to add assembler insn code suffix .p
2377 if it is necessary. */
2380 frv_asm_output_opcode (FILE *f, const char *ptr)
2384 if (frv_insn_packing_flag <= 0)
2387 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2390 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2391 || (*ptr >= 'A' && *ptr <= 'Z')))
2393 int letter = *ptr++;
2396 frv_print_operand (f, frv_insn_operands [c], letter);
2397 while ((c = *ptr) >= '0' && c <= '9')
2409 /* Set up the packing bit for the current output insn. Note that this
2410 function is not called for asm insns. */
2413 frv_final_prescan_insn (rtx insn, rtx *opvec,
2414 int noperands ATTRIBUTE_UNUSED)
2418 if (frv_insn_packing_flag >= 0)
2420 frv_insn_operands = opvec;
2421 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2423 else if (recog_memoized (insn) >= 0
2424 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2425 /* Packing optimizations have been disabled, but INSN can only
2426 be issued in M1. Insert an mnop in M0. */
2427 fprintf (asm_out_file, "\tmnop.p\n");
2433 /* A C expression whose value is RTL representing the address in a stack frame
2434 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2435 an RTL expression for the address of the stack frame itself.
2437 If you don't define this macro, the default is to return the value of
2438 FRAMEADDR--that is, the stack frame address is also the address of the stack
2439 word that points to the previous frame. */
2441 /* The default is correct, but we need to make sure the frame gets created. */
2443 frv_dynamic_chain_address (rtx frame)
2445 cfun->machine->frame_needed = 1;
2450 /* A C expression whose value is RTL representing the value of the return
2451 address for the frame COUNT steps up from the current frame, after the
2452 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2453 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2456 The value of the expression must always be the correct address when COUNT is
2457 zero, but may be `NULL_RTX' if there is not way to determine the return
2458 address of other frames. */
2461 frv_return_addr_rtx (int count, rtx frame)
2465 cfun->machine->frame_needed = 1;
2466 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2469 /* Given a memory reference MEMREF, interpret the referenced memory as
2470 an array of MODE values, and return a reference to the element
2471 specified by INDEX. Assume that any pre-modification implicit in
2472 MEMREF has already happened.
2474 MEMREF must be a legitimate operand for modes larger than SImode.
2475 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2476 this function cannot handle. */
2478 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2480 rtx base = XEXP (memref, 0);
2481 if (GET_CODE (base) == PRE_MODIFY)
2482 base = XEXP (base, 0);
2483 return change_address (memref, mode,
2484 plus_constant (base, index * GET_MODE_SIZE (mode)));
2488 /* Print a memory address as an operand to reference that memory location. */
2490 frv_print_operand_address (FILE * stream, rtx x)
2492 if (GET_CODE (x) == MEM)
2495 switch (GET_CODE (x))
2498 fputs (reg_names [ REGNO (x)], stream);
2502 fprintf (stream, "%ld", (long) INTVAL (x));
2506 assemble_name (stream, XSTR (x, 0));
2511 output_addr_const (stream, x);
2518 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2523 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2525 int regno = true_regnum (x);
2527 fputs (reg_names[regno], stream);
2529 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2532 /* Print a memory reference suitable for the ld/st instructions. */
2535 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2537 struct frv_unspec unspec;
2541 switch (GET_CODE (x))
2548 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2550 x1 = XEXP (XEXP (x, 1), 1);
2560 if (GET_CODE (x0) == CONST_INT)
2568 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2577 else if (GET_CODE (x1) != CONST_INT)
2578 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2581 fputs ("@(", stream);
2583 fputs (reg_names[GPR_R0], stream);
2584 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2585 frv_print_operand_memory_reference_reg (stream, x0);
2587 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2589 fputs (",", stream);
2591 fputs (reg_names [GPR_R0], stream);
2595 switch (GET_CODE (x1))
2599 frv_print_operand_memory_reference_reg (stream, x1);
2603 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2607 if (!frv_const_unspec_p (x1, &unspec))
2608 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2609 frv_output_const_unspec (stream, &unspec);
2613 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2617 fputs (")", stream);
2621 /* Return 2 for likely branches and 0 for non-likely branches */
2623 #define FRV_JUMP_LIKELY 2
2624 #define FRV_JUMP_NOT_LIKELY 0
2627 frv_print_operand_jump_hint (rtx insn)
2632 HOST_WIDE_INT prob = -1;
2633 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2635 if (GET_CODE (insn) != JUMP_INSN)
2638 /* Assume any non-conditional jump is likely. */
2639 if (! any_condjump_p (insn))
2640 ret = FRV_JUMP_LIKELY;
2644 labelref = condjump_label (insn);
2647 rtx label = XEXP (labelref, 0);
2648 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2653 note = find_reg_note (insn, REG_BR_PROB, 0);
2655 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2659 prob = INTVAL (XEXP (note, 0));
2660 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2662 : FRV_JUMP_NOT_LIKELY);
2674 case UNKNOWN: direction = "unknown jump direction"; break;
2675 case BACKWARD: direction = "jump backward"; break;
2676 case FORWARD: direction = "jump forward"; break;
2680 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2681 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2682 (long)INSN_UID (insn), direction, (long)prob,
2683 (long)REG_BR_PROB_BASE, ret);
2691 /* Return the comparison operator to use for CODE given that the ICC
2695 comparison_string (enum rtx_code code, rtx op0)
2697 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2700 default: output_operand_lossage ("bad condition code");
2701 case EQ: return "eq";
2702 case NE: return "ne";
2703 case LT: return is_nz_p ? "n" : "lt";
2704 case LE: return "le";
2705 case GT: return "gt";
2706 case GE: return is_nz_p ? "p" : "ge";
2707 case LTU: return is_nz_p ? "no" : "c";
2708 case LEU: return is_nz_p ? "eq" : "ls";
2709 case GTU: return is_nz_p ? "ne" : "hi";
2710 case GEU: return is_nz_p ? "ra" : "nc";
2714 /* Print an operand to an assembler instruction.
2716 `%' followed by a letter and a digit says to output an operand in an
2717 alternate fashion. Four letters have standard, built-in meanings described
2718 below. The machine description macro `PRINT_OPERAND' can define additional
2719 letters with nonstandard meanings.
2721 `%cDIGIT' can be used to substitute an operand that is a constant value
2722 without the syntax that normally indicates an immediate operand.
2724 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2727 `%aDIGIT' can be used to substitute an operand as if it were a memory
2728 reference, with the actual operand treated as the address. This may be
2729 useful when outputting a "load address" instruction, because often the
2730 assembler syntax for such an instruction requires you to write the operand
2731 as if it were a memory reference.
2733 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2735 `%=' outputs a number which is unique to each instruction in the entire
2736 compilation. This is useful for making local labels to be referred to more
2737 than once in a single template that generates multiple assembler
2740 `%' followed by a punctuation character specifies a substitution that does
2741 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2742 assembler code. Other nonstandard cases can be defined in the
2743 `PRINT_OPERAND' macro. You must also define which punctuation characters
2744 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2747 frv_print_operand (FILE * file, rtx x, int code)
2749 struct frv_unspec unspec;
2750 HOST_WIDE_INT value;
2753 if (code != 0 && !isalpha (code))
2756 else if (GET_CODE (x) == CONST_INT)
2759 else if (GET_CODE (x) == CONST_DOUBLE)
2761 if (GET_MODE (x) == SFmode)
2766 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2767 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2771 else if (GET_MODE (x) == VOIDmode)
2772 value = CONST_DOUBLE_LOW (x);
2775 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2786 fputs (reg_names[GPR_R0], file);
2790 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2794 /* Output small data area base register (gr16). */
2795 fputs (reg_names[SDA_BASE_REG], file);
2799 /* Output pic register (gr17). */
2800 fputs (reg_names[PIC_REGNO], file);
2804 /* Output the temporary integer CCR register. */
2805 fputs (reg_names[ICR_TEMP], file);
2809 /* Output the temporary integer CC register. */
2810 fputs (reg_names[ICC_TEMP], file);
2813 /* case 'a': print an address. */
2816 /* Print appropriate test for integer branch false operation. */
2817 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2818 XEXP (x, 0)), file);
2822 /* Print appropriate test for integer branch true operation. */
2823 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2827 /* Print 1 for a NE and 0 for an EQ to give the final argument
2828 for a conditional instruction. */
2829 if (GET_CODE (x) == NE)
2832 else if (GET_CODE (x) == EQ)
2836 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2840 /* Print appropriate test for floating point branch false operation. */
2841 switch (GET_CODE (x))
2844 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2846 case EQ: fputs ("ne", file); break;
2847 case NE: fputs ("eq", file); break;
2848 case LT: fputs ("uge", file); break;
2849 case LE: fputs ("ug", file); break;
2850 case GT: fputs ("ule", file); break;
2851 case GE: fputs ("ul", file); break;
2856 /* Print appropriate test for floating point branch true operation. */
2857 switch (GET_CODE (x))
2860 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2862 case EQ: fputs ("eq", file); break;
2863 case NE: fputs ("ne", file); break;
2864 case LT: fputs ("lt", file); break;
2865 case LE: fputs ("le", file); break;
2866 case GT: fputs ("gt", file); break;
2867 case GE: fputs ("ge", file); break;
2872 /* Print appropriate GOT function. */
2873 if (GET_CODE (x) != CONST_INT)
2874 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2875 fputs (unspec_got_name (INTVAL (x)), file);
2879 /* Print 'i' if the operand is a constant, or is a memory reference that
2881 if (GET_CODE (x) == MEM)
2882 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2883 ? XEXP (XEXP (x, 0), 1)
2885 else if (GET_CODE (x) == PLUS)
2888 switch (GET_CODE (x))
2902 /* For jump instructions, print 'i' if the operand is a constant or
2903 is an expression that adds a constant. */
2904 if (GET_CODE (x) == CONST_INT)
2909 if (GET_CODE (x) == CONST_INT
2910 || (GET_CODE (x) == PLUS
2911 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2912 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2918 /* Print the lower register of a double word register pair */
2919 if (GET_CODE (x) == REG)
2920 fputs (reg_names[ REGNO (x)+1 ], file);
2922 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2925 /* case 'l': print a LABEL_REF. */
2929 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2930 for the second word of double memory operations. */
2931 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2932 switch (GET_CODE (x))
2935 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2938 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2946 frv_print_operand_memory_reference (file, x, offset);
2952 /* Print the opcode of a command. */
2953 switch (GET_CODE (x))
2956 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2958 case PLUS: fputs ("add", file); break;
2959 case MINUS: fputs ("sub", file); break;
2960 case AND: fputs ("and", file); break;
2961 case IOR: fputs ("or", file); break;
2962 case XOR: fputs ("xor", file); break;
2963 case ASHIFT: fputs ("sll", file); break;
2964 case ASHIFTRT: fputs ("sra", file); break;
2965 case LSHIFTRT: fputs ("srl", file); break;
2969 /* case 'n': negate and print a constant int. */
2972 /* Print PIC label using operand as the number. */
2973 if (GET_CODE (x) != CONST_INT)
2974 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2976 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2980 /* Print 'u' if the operand is a update load/store. */
2981 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2986 /* If value is 0, print gr0, otherwise it must be a register. */
2987 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2988 fputs (reg_names[GPR_R0], file);
2990 else if (GET_CODE (x) == REG)
2991 fputs (reg_names [REGNO (x)], file);
2994 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2998 /* Print constant in hex. */
2999 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3001 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3008 if (GET_CODE (x) == REG)
3009 fputs (reg_names [REGNO (x)], file);
3011 else if (GET_CODE (x) == CONST_INT
3012 || GET_CODE (x) == CONST_DOUBLE)
3013 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3015 else if (frv_const_unspec_p (x, &unspec))
3016 frv_output_const_unspec (file, &unspec);
3018 else if (GET_CODE (x) == MEM)
3019 frv_print_operand_address (file, XEXP (x, 0));
3021 else if (CONSTANT_ADDRESS_P (x))
3022 frv_print_operand_address (file, x);
3025 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3030 fatal_insn ("frv_print_operand: unknown code", x);
3038 /* A C statement (sans semicolon) for initializing the variable CUM for the
3039 state at the beginning of the argument list. The variable has type
3040 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3041 of the function which will receive the args, or 0 if the args are to a
3042 compiler support library function. The value of INDIRECT is nonzero when
3043 processing an indirect call, for example a call through a function pointer.
3044 The value of INDIRECT is zero for a call to an explicitly named function, a
3045 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3046 arguments for the function being compiled.
3048 When processing a call to a compiler support library function, LIBNAME
3049 identifies which one. It is a `symbol_ref' rtx which contains the name of
3050 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3051 being processed. Thus, each time this macro is called, either LIBNAME or
3052 FNTYPE is nonzero, but never both of them at once. */
3055 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3061 *cum = FIRST_ARG_REGNUM;
3063 if (TARGET_DEBUG_ARG)
3065 fprintf (stderr, "\ninit_cumulative_args:");
3066 if (!fndecl && fntype)
3067 fputs (" indirect", stderr);
3070 fputs (" incoming", stderr);
3074 tree ret_type = TREE_TYPE (fntype);
3075 fprintf (stderr, " return=%s,",
3076 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3079 if (libname && GET_CODE (libname) == SYMBOL_REF)
3080 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3082 if (cfun->returns_struct)
3083 fprintf (stderr, " return-struct");
3085 putc ('\n', stderr);
3090 /* Return true if we should pass an argument on the stack rather than
3094 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3096 if (mode == BLKmode)
3100 return AGGREGATE_TYPE_P (type);
3103 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3104 argument with the specified mode and type. If it is not defined,
3105 `PARM_BOUNDARY' is used for all arguments. */
3108 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3109 tree type ATTRIBUTE_UNUSED)
3111 return BITS_PER_WORD;
3115 frv_function_arg (CUMULATIVE_ARGS *cum,
3116 enum machine_mode mode,
3117 tree type ATTRIBUTE_UNUSED,
3119 int incoming ATTRIBUTE_UNUSED)
3121 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3126 /* Return a marker for use in the call instruction. */
3127 if (xmode == VOIDmode)
3133 else if (arg_num <= LAST_ARG_REGNUM)
3135 ret = gen_rtx_REG (xmode, arg_num);
3136 debstr = reg_names[arg_num];
3145 if (TARGET_DEBUG_ARG)
3147 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3148 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3154 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3155 advance past an argument in the argument list. The values MODE, TYPE and
3156 NAMED describe that argument. Once this is done, the variable CUM is
3157 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3159 This macro need not do anything if the argument in question was passed on
3160 the stack. The compiler knows how to track the amount of stack space used
3161 for arguments without any special help. */
3164 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3165 enum machine_mode mode,
3166 tree type ATTRIBUTE_UNUSED,
3169 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3170 int bytes = GET_MODE_SIZE (xmode);
3171 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3174 *cum = arg_num + words;
3176 if (TARGET_DEBUG_ARG)
3178 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3179 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3183 /* A C expression for the number of words, at the beginning of an argument,
3184 must be put in registers. The value must be zero for arguments that are
3185 passed entirely in registers or that are entirely pushed on the stack.
3187 On some machines, certain arguments must be passed partially in registers
3188 and partially in memory. On these machines, typically the first N words of
3189 arguments are passed in registers, and the rest on the stack. If a
3190 multi-word argument (a `double' or a structure) crosses that boundary, its
3191 first few words must be passed in registers and the rest must be pushed.
3192 This macro tells the compiler when this occurs, and how many of the words
3193 should go in registers.
3195 `FUNCTION_ARG' for these arguments should return the first register to be
3196 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3197 the called function. */
3200 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3201 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3203 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3204 int bytes = GET_MODE_SIZE (xmode);
3205 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3209 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3210 ? LAST_ARG_REGNUM - arg_num + 1
3212 ret *= UNITS_PER_WORD;
3214 if (TARGET_DEBUG_ARG && ret)
3215 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3221 /* Return true if a register is ok to use as a base or index register. */
3223 static FRV_INLINE int
3224 frv_regno_ok_for_base_p (int regno, int strict_p)
3230 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3232 if (regno == ARG_POINTER_REGNUM)
3235 return (regno >= FIRST_PSEUDO_REGISTER);
3239 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3240 RTX) is a legitimate memory address on the target machine for a memory
3241 operand of mode MODE.
3243 It usually pays to define several simpler macros to serve as subroutines for
3244 this one. Otherwise it may be too complicated to understand.
3246 This macro must exist in two variants: a strict variant and a non-strict
3247 one. The strict variant is used in the reload pass. It must be defined so
3248 that any pseudo-register that has not been allocated a hard register is
3249 considered a memory reference. In contexts where some kind of register is
3250 required, a pseudo-register with no hard register must be rejected.
3252 The non-strict variant is used in other passes. It must be defined to
3253 accept all pseudo-registers in every context where some kind of register is
3256 Compiler source files that want to use the strict variant of this macro
3257 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3258 conditional to define the strict variant in that case and the non-strict
3261 Subroutines to check for acceptable registers for various purposes (one for
3262 base registers, one for index registers, and so on) are typically among the
3263 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3264 subroutine macros need have two variants; the higher levels of macros may be
3265 the same whether strict or not.
3267 Normally, constant addresses which are the sum of a `symbol_ref' and an
3268 integer are stored inside a `const' RTX to mark them as constant.
3269 Therefore, there is no need to recognize such sums specifically as
3270 legitimate addresses. Normally you would simply recognize any `const' as
3273 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3274 are not marked with `const'. It assumes that a naked `plus' indicates
3275 indexing. If so, then you *must* reject such naked constant sums as
3276 illegitimate addresses, so that none of them will be given to
3277 `PRINT_OPERAND_ADDRESS'.
3279 On some machines, whether a symbolic address is legitimate depends on the
3280 section that the address refers to. On these machines, define the macro
3281 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3282 then check for it here. When you see a `const', you will have to look
3283 inside it to find the `symbol_ref' in order to determine the section.
3285 The best way to modify the name string is by adding text to the beginning,
3286 with suitable punctuation to prevent any ambiguity. Allocate the new name
3287 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3288 remove and decode the added text and output the name accordingly, and define
3289 `(* targetm.strip_name_encoding)' to access the original name string.
3291 You can check the information stored here into the `symbol_ref' in the
3292 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3293 `PRINT_OPERAND_ADDRESS'. */
3296 frv_legitimate_address_p (enum machine_mode mode,
3300 int allow_double_reg_p)
3304 HOST_WIDE_INT value;
3307 switch (GET_CODE (x))
3314 if (GET_CODE (x) != REG)
3320 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3326 if (GET_CODE (x0) != REG
3327 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3328 || GET_CODE (x1) != PLUS
3329 || ! rtx_equal_p (x0, XEXP (x1, 0))
3330 || GET_CODE (XEXP (x1, 1)) != REG
3331 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3338 /* 12 bit immediate */
3343 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3345 /* If we can't use load/store double operations, make sure we can
3346 address the second word. */
3347 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3348 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3357 if (GET_CODE (x0) == SUBREG)
3358 x0 = SUBREG_REG (x0);
3360 if (GET_CODE (x0) != REG)
3363 regno0 = REGNO (x0);
3364 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3367 switch (GET_CODE (x1))
3373 x1 = SUBREG_REG (x1);
3374 if (GET_CODE (x1) != REG)
3380 /* Do not allow reg+reg addressing for modes > 1 word if we
3381 can't depend on having move double instructions. */
3382 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3385 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3389 /* 12 bit immediate */
3394 value = INTVAL (x1);
3395 ret = IN_RANGE_P (value, -2048, 2047);
3397 /* If we can't use load/store double operations, make sure we can
3398 address the second word. */
3399 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3400 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3405 if (!condexec_p && got12_operand (x1, VOIDmode))
3413 if (TARGET_DEBUG_ADDR)
3415 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3416 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3417 (condexec_p) ? ", inside conditional code" : "");
3425 frv_legitimize_address (rtx x ATTRIBUTE_UNUSED,
3426 rtx oldx ATTRIBUTE_UNUSED,
3427 enum machine_mode mode ATTRIBUTE_UNUSED)
3432 /* Test whether a local function descriptor is canonical, i.e.,
3433 whether we can use FUNCDESC_GOTOFF to compute the address of the
3437 frv_local_funcdesc_p (rtx fnx)
3440 enum symbol_visibility vis;
3443 if (! SYMBOL_REF_LOCAL_P (fnx))
3446 fn = SYMBOL_REF_DECL (fnx);
3451 vis = DECL_VISIBILITY (fn);
3453 if (vis == VISIBILITY_PROTECTED)
3454 /* Private function descriptors for protected functions are not
3455 canonical. Temporarily change the visibility to global. */
3456 vis = VISIBILITY_DEFAULT;
3457 else if (flag_shlib)
3458 /* If we're already compiling for a shared library (that, unlike
3459 executables, can't assume that the existence of a definition
3460 implies local binding), we can skip the re-testing. */
3463 ret = default_binds_local_p_1 (fn, flag_pic);
3465 DECL_VISIBILITY (fn) = vis;
3470 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3474 frv_gen_GPsym2reg (rtx dest, rtx src)
3476 tree gp = get_identifier ("_gp");
3477 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3479 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3483 unspec_got_name (int i)
3487 case R_FRV_GOT12: return "got12";
3488 case R_FRV_GOTHI: return "gothi";
3489 case R_FRV_GOTLO: return "gotlo";
3490 case R_FRV_FUNCDESC: return "funcdesc";
3491 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3492 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3493 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3494 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3495 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3496 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3497 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3498 case R_FRV_GOTOFF12: return "gotoff12";
3499 case R_FRV_GOTOFFHI: return "gotoffhi";
3500 case R_FRV_GOTOFFLO: return "gotofflo";
3501 case R_FRV_GPREL12: return "gprel12";
3502 case R_FRV_GPRELHI: return "gprelhi";
3503 case R_FRV_GPRELLO: return "gprello";
3508 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3509 is added inside the relocation operator. */
3512 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3514 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3515 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3516 fputs (")", stream);
3519 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3520 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3521 otherwise return ORIG_X. */
3524 frv_find_base_term (rtx x)
3526 struct frv_unspec unspec;
3528 if (frv_const_unspec_p (x, &unspec)
3529 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3530 return plus_constant (unspec.symbol, unspec.offset);
3535 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3536 the operand is used by a predicated instruction. */
3539 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3541 return ((GET_MODE (op) == mode || mode == VOIDmode)
3542 && GET_CODE (op) == MEM
3543 && frv_legitimate_address_p (mode, XEXP (op, 0),
3544 reload_completed, condexec_p, FALSE));
3548 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3550 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3551 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3557 rvrtx = operands[0];
3561 addr = XEXP (operands[0], 0);
3563 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3564 any calls that would involve a PLT, but can't tell, since we
3565 don't know whether an extern function is going to be provided by
3566 a separate translation unit or imported from a separate module.
3567 When compiling for shared libraries, if the function has default
3568 visibility, we assume it's overridable, so we inline the PLT, but
3569 for executables, we don't really have a way to make a good
3570 decision: a function is as likely to be imported from a shared
3571 library as it is to be defined in the executable itself. We
3572 assume executables will get global functions defined locally,
3573 whereas shared libraries will have them potentially overridden,
3574 so we only inline PLTs when compiling for shared libraries.
3576 In order to mark a function as local to a shared library, any
3577 non-default visibility attribute suffices. Unfortunately,
3578 there's no simple way to tag a function declaration as ``in a
3579 different module'', which we could then use to trigger PLT
3580 inlining on executables. There's -minline-plt, but it affects
3581 all external functions, so one would have to also mark function
3582 declarations available in the same module with non-default
3583 visibility, which is advantageous in itself. */
3584 if (GET_CODE (addr) == SYMBOL_REF
3585 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3589 dest = gen_reg_rtx (SImode);
3591 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3592 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3594 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3595 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3597 cfun->uses_pic_offset_table = TRUE;
3600 else if (GET_CODE (addr) == SYMBOL_REF)
3602 /* These are always either local, or handled through a local
3605 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3606 operands[2], picreg, lr);
3608 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3612 else if (! ldd_address_operand (addr, Pmode))
3613 addr = force_reg (Pmode, addr);
3615 picreg = gen_reg_rtx (DImode);
3616 emit_insn (gen_movdi_ldd (picreg, addr));
3618 if (sibcall && ret_value)
3619 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3621 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3623 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3625 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3629 /* An address operand that may use a pair of registers, an addressing
3630 mode that we reject in general. */
3633 ldd_address_operand (rtx x, enum machine_mode mode)
3635 if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode)
3638 return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE);
3642 fdpic_fptr_operand (rtx op, enum machine_mode mode)
3644 if (GET_MODE (op) != mode && mode != VOIDmode)
3646 if (GET_CODE (op) != REG)
3648 if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
3653 /* Return 1 is OP is a memory operand, or will be turned into one by
3657 frv_load_operand (rtx op, enum machine_mode mode)
3659 if (GET_MODE (op) != mode && mode != VOIDmode)
3662 if (reload_in_progress)
3665 if (GET_CODE (tmp) == SUBREG)
3666 tmp = SUBREG_REG (tmp);
3667 if (GET_CODE (tmp) == REG
3668 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3669 op = reg_equiv_memory_loc[REGNO (tmp)];
3672 return op && memory_operand (op, mode);
3676 /* Return 1 if operand is a GPR register or a FPR register. */
3679 gpr_or_fpr_operand (rtx op, enum machine_mode mode)
3683 if (GET_MODE (op) != mode && mode != VOIDmode)
3686 if (GET_CODE (op) == SUBREG)
3688 if (GET_CODE (SUBREG_REG (op)) != REG)
3689 return register_operand (op, mode);
3691 op = SUBREG_REG (op);
3694 if (GET_CODE (op) != REG)
3698 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3704 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3707 gpr_or_int12_operand (rtx op, enum machine_mode mode)
3709 if (GET_CODE (op) == CONST_INT)
3710 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3712 if (got12_operand (op, mode))
3715 if (GET_MODE (op) != mode && mode != VOIDmode)
3718 if (GET_CODE (op) == SUBREG)
3720 if (GET_CODE (SUBREG_REG (op)) != REG)
3721 return register_operand (op, mode);
3723 op = SUBREG_REG (op);
3726 if (GET_CODE (op) != REG)
3729 return GPR_OR_PSEUDO_P (REGNO (op));
3732 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3733 signed immediate. */
3736 gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode)
3740 if (GET_CODE (op) == CONST_INT)
3741 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3743 if (GET_MODE (op) != mode && mode != VOIDmode)
3746 if (GET_CODE (op) == SUBREG)
3748 if (GET_CODE (SUBREG_REG (op)) != REG)
3749 return register_operand (op, mode);
3751 op = SUBREG_REG (op);
3754 if (GET_CODE (op) != REG)
3758 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3764 /* Return 1 if operand is a register or 6 bit signed immediate. */
3767 fpr_or_int6_operand (rtx op, enum machine_mode mode)
3769 if (GET_CODE (op) == CONST_INT)
3770 return IN_RANGE_P (INTVAL (op), -32, 31);
3772 if (GET_MODE (op) != mode && mode != VOIDmode)
3775 if (GET_CODE (op) == SUBREG)
3777 if (GET_CODE (SUBREG_REG (op)) != REG)
3778 return register_operand (op, mode);
3780 op = SUBREG_REG (op);
3783 if (GET_CODE (op) != REG)
3786 return FPR_OR_PSEUDO_P (REGNO (op));
3789 /* Return 1 if operand is a register or 10 bit signed immediate. */
3792 gpr_or_int10_operand (rtx op, enum machine_mode mode)
3794 if (GET_CODE (op) == CONST_INT)
3795 return IN_RANGE_P (INTVAL (op), -512, 511);
3797 if (GET_MODE (op) != mode && mode != VOIDmode)
3800 if (GET_CODE (op) == SUBREG)
3802 if (GET_CODE (SUBREG_REG (op)) != REG)
3803 return register_operand (op, mode);
3805 op = SUBREG_REG (op);
3808 if (GET_CODE (op) != REG)
3811 return GPR_OR_PSEUDO_P (REGNO (op));
3814 /* Return 1 if operand is a register or an integer immediate. */
3817 gpr_or_int_operand (rtx op, enum machine_mode mode)
3819 if (GET_CODE (op) == CONST_INT)
3822 if (GET_MODE (op) != mode && mode != VOIDmode)
3825 if (GET_CODE (op) == SUBREG)
3827 if (GET_CODE (SUBREG_REG (op)) != REG)
3828 return register_operand (op, mode);
3830 op = SUBREG_REG (op);
3833 if (GET_CODE (op) != REG)
3836 return GPR_OR_PSEUDO_P (REGNO (op));
3839 /* Return 1 if operand is a 12 bit signed immediate. */
3842 int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3844 if (GET_CODE (op) != CONST_INT)
3847 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3850 /* Return 1 if operand is a 6 bit signed immediate. */
3853 int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3855 if (GET_CODE (op) != CONST_INT)
3858 return IN_RANGE_P (INTVAL (op), -32, 31);
3861 /* Return 1 if operand is a 5 bit signed immediate. */
3864 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3866 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3869 /* Return 1 if operand is a 5 bit unsigned immediate. */
3872 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3874 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3877 /* Return 1 if operand is a 4 bit unsigned immediate. */
3880 uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3882 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3885 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3888 uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3890 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3893 /* Return 1 if operand is an integer constant that takes 2 instructions
3894 to load up and can be split into sethi/setlo instructions.. */
3897 int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3899 HOST_WIDE_INT value;
3903 switch (GET_CODE (op))
3912 return (flag_pic == 0);
3915 if (flag_pic || TARGET_FDPIC)
3919 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
3921 return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
3927 /* small data references are already 1 word */
3928 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
3931 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3934 if (GET_MODE (op) == SFmode)
3936 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3937 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3939 return ! IN_RANGE_P (value, -32768, 32767);
3941 else if (GET_MODE (op) == VOIDmode)
3943 value = CONST_DOUBLE_LOW (op);
3944 return ! IN_RANGE_P (value, -32768, 32767);
3952 /* Return 1 if operand is a 16 bit unsigned immediate. */
3955 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3957 if (GET_CODE (op) != CONST_INT)
3960 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3963 /* Return 1 if operand is an integer constant with the bottom 16 bits
3967 upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3969 if (GET_CODE (op) != CONST_INT)
3972 return ((INTVAL (op) & 0xffff) == 0);
3975 /* Return true if operand is a GPR register. */
3978 integer_register_operand (rtx op, enum machine_mode mode)
3980 if (GET_MODE (op) != mode && mode != VOIDmode)
3983 if (GET_CODE (op) == SUBREG)
3985 if (GET_CODE (SUBREG_REG (op)) != REG)
3986 return register_operand (op, mode);
3988 op = SUBREG_REG (op);
3991 if (GET_CODE (op) != REG)
3994 return GPR_OR_PSEUDO_P (REGNO (op));
3997 /* Return true if operand is a GPR register. Do not allow SUBREG's
3998 here, in order to prevent a combine bug. */
4001 gpr_no_subreg_operand (rtx op, enum machine_mode mode)
4003 if (GET_MODE (op) != mode && mode != VOIDmode)
4006 if (GET_CODE (op) != REG)
4009 return GPR_OR_PSEUDO_P (REGNO (op));
4012 /* Return true if operand is a FPR register. */
4015 fpr_operand (rtx op, enum machine_mode mode)
4017 if (GET_MODE (op) != mode && mode != VOIDmode)
4020 if (GET_CODE (op) == SUBREG)
4022 if (GET_CODE (SUBREG_REG (op)) != REG)
4023 return register_operand (op, mode);
4025 op = SUBREG_REG (op);
4028 if (GET_CODE (op) != REG)
4031 return FPR_OR_PSEUDO_P (REGNO (op));
4034 /* Return true if operand is an even GPR or FPR register. */
4037 even_reg_operand (rtx op, enum machine_mode mode)
4041 if (GET_MODE (op) != mode && mode != VOIDmode)
4044 if (GET_CODE (op) == SUBREG)
4046 if (GET_CODE (SUBREG_REG (op)) != REG)
4047 return register_operand (op, mode);
4049 op = SUBREG_REG (op);
4052 if (GET_CODE (op) != REG)
4056 if (regno >= FIRST_PSEUDO_REGISTER)
4060 return (((regno - GPR_FIRST) & 1) == 0);
4063 return (((regno - FPR_FIRST) & 1) == 0);
4068 /* Return true if operand is an odd GPR register. */
4071 odd_reg_operand (rtx op, enum machine_mode mode)
4075 if (GET_MODE (op) != mode && mode != VOIDmode)
4078 if (GET_CODE (op) == SUBREG)
4080 if (GET_CODE (SUBREG_REG (op)) != REG)
4081 return register_operand (op, mode);
4083 op = SUBREG_REG (op);
4086 if (GET_CODE (op) != REG)
4090 /* Assume that reload will give us an even register. */
4091 if (regno >= FIRST_PSEUDO_REGISTER)
4095 return (((regno - GPR_FIRST) & 1) != 0);
4098 return (((regno - FPR_FIRST) & 1) != 0);
4103 /* Return true if operand is an even GPR register. */
4106 even_gpr_operand (rtx op, enum machine_mode mode)
4110 if (GET_MODE (op) != mode && mode != VOIDmode)
4113 if (GET_CODE (op) == SUBREG)
4115 if (GET_CODE (SUBREG_REG (op)) != REG)
4116 return register_operand (op, mode);
4118 op = SUBREG_REG (op);
4121 if (GET_CODE (op) != REG)
4125 if (regno >= FIRST_PSEUDO_REGISTER)
4128 if (! GPR_P (regno))
4131 return (((regno - GPR_FIRST) & 1) == 0);
4134 /* Return true if operand is an odd GPR register. */
4137 odd_gpr_operand (rtx op, enum machine_mode mode)
4141 if (GET_MODE (op) != mode && mode != VOIDmode)
4144 if (GET_CODE (op) == SUBREG)
4146 if (GET_CODE (SUBREG_REG (op)) != REG)
4147 return register_operand (op, mode);
4149 op = SUBREG_REG (op);
4152 if (GET_CODE (op) != REG)
4156 /* Assume that reload will give us an even register. */
4157 if (regno >= FIRST_PSEUDO_REGISTER)
4160 if (! GPR_P (regno))
4163 return (((regno - GPR_FIRST) & 1) != 0);
4166 /* Return true if operand is a quad aligned FPR register. */
4169 quad_fpr_operand (rtx op, enum machine_mode mode)
4173 if (GET_MODE (op) != mode && mode != VOIDmode)
4176 if (GET_CODE (op) == SUBREG)
4178 if (GET_CODE (SUBREG_REG (op)) != REG)
4179 return register_operand (op, mode);
4181 op = SUBREG_REG (op);
4184 if (GET_CODE (op) != REG)
4188 if (regno >= FIRST_PSEUDO_REGISTER)
4191 if (! FPR_P (regno))
4194 return (((regno - FPR_FIRST) & 3) == 0);
4197 /* Return true if operand is an even FPR register. */
4200 even_fpr_operand (rtx op, enum machine_mode mode)
4204 if (GET_MODE (op) != mode && mode != VOIDmode)
4207 if (GET_CODE (op) == SUBREG)
4209 if (GET_CODE (SUBREG_REG (op)) != REG)
4210 return register_operand (op, mode);
4212 op = SUBREG_REG (op);
4215 if (GET_CODE (op) != REG)
4219 if (regno >= FIRST_PSEUDO_REGISTER)
4222 if (! FPR_P (regno))
4225 return (((regno - FPR_FIRST) & 1) == 0);
4228 /* Return true if operand is an odd FPR register. */
4231 odd_fpr_operand (rtx op, enum machine_mode mode)
4235 if (GET_MODE (op) != mode && mode != VOIDmode)
4238 if (GET_CODE (op) == SUBREG)
4240 if (GET_CODE (SUBREG_REG (op)) != REG)
4241 return register_operand (op, mode);
4243 op = SUBREG_REG (op);
4246 if (GET_CODE (op) != REG)
4250 /* Assume that reload will give us an even register. */
4251 if (regno >= FIRST_PSEUDO_REGISTER)
4254 if (! FPR_P (regno))
4257 return (((regno - FPR_FIRST) & 1) != 0);
4260 /* Return true if operand is a 2 word memory address that can be loaded in one
4261 instruction to load or store. We assume the stack and frame pointers are
4262 suitably aligned, and variables in the small data area. FIXME -- at some we
4263 should recognize other globals and statics. We can't assume that any old
4264 pointer is aligned, given that arguments could be passed on an odd word on
4265 the stack and the address taken and passed through to another function. */
4268 dbl_memory_one_insn_operand (rtx op, enum machine_mode mode)
4276 if (GET_CODE (op) != MEM)
4279 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4282 addr = XEXP (op, 0);
4283 if (GET_CODE (addr) == REG)
4286 else if (GET_CODE (addr) == PLUS)
4288 rtx addr0 = XEXP (addr, 0);
4289 rtx addr1 = XEXP (addr, 1);
4291 if (GET_CODE (addr0) != REG)
4294 if (got12_operand (addr1, VOIDmode))
4297 if (GET_CODE (addr1) != CONST_INT)
4300 if ((INTVAL (addr1) & 7) != 0)
4309 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4315 /* Return true if operand is a 2 word memory address that needs to
4316 use two instructions to load or store. */
4319 dbl_memory_two_insn_operand (rtx op, enum machine_mode mode)
4321 if (GET_CODE (op) != MEM)
4324 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4330 return ! dbl_memory_one_insn_operand (op, mode);
4333 /* Return true if operand is something that can be an output for a move
4337 move_destination_operand (rtx op, enum machine_mode mode)
4342 switch (GET_CODE (op))
4348 if (GET_MODE (op) != mode && mode != VOIDmode)
4351 subreg = SUBREG_REG (op);
4352 code = GET_CODE (subreg);
4354 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4355 reload_completed, FALSE, FALSE);
4357 return (code == REG);
4360 if (GET_MODE (op) != mode && mode != VOIDmode)
4366 return frv_legitimate_memory_operand (op, mode, FALSE);
4372 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
4373 process these separately from any offsets, such that we add any
4374 offsets to the function descriptor (the actual pointer), not to the
4375 function address. */
4378 frv_function_symbol_referenced_p (rtx x)
4384 if (GET_CODE (x) == SYMBOL_REF)
4385 return SYMBOL_REF_FUNCTION_P (x);
4387 length = GET_RTX_LENGTH (GET_CODE (x));
4388 format = GET_RTX_FORMAT (GET_CODE (x));
4390 for (j = 0; j < length; ++j)
4395 if (frv_function_symbol_referenced_p (XEXP (x, j)))
4401 if (XVEC (x, j) != 0)
4404 for (k = 0; k < XVECLEN (x, j); ++k)
4405 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
4411 /* Nothing to do. */
4419 /* Return true if operand is something that can be an input for a move
4423 move_source_operand (rtx op, enum machine_mode mode)
4428 switch (GET_CODE (op))
4435 return immediate_operand (op, mode);
4438 if (GET_MODE (op) != mode && mode != VOIDmode)
4441 subreg = SUBREG_REG (op);
4442 code = GET_CODE (subreg);
4444 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4445 reload_completed, FALSE, FALSE);
4447 return (code == REG);
4450 if (GET_MODE (op) != mode && mode != VOIDmode)
4456 return frv_legitimate_memory_operand (op, mode, FALSE);
4462 /* Return true if operand is something that can be an output for a conditional
4466 condexec_dest_operand (rtx op, enum machine_mode mode)
4471 switch (GET_CODE (op))
4477 if (GET_MODE (op) != mode && mode != VOIDmode)
4480 subreg = SUBREG_REG (op);
4481 code = GET_CODE (subreg);
4483 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4484 reload_completed, TRUE, FALSE);
4486 return (code == REG);
4489 if (GET_MODE (op) != mode && mode != VOIDmode)
4495 return frv_legitimate_memory_operand (op, mode, TRUE);
4501 /* Return true if operand is something that can be an input for a conditional
4505 condexec_source_operand (rtx op, enum machine_mode mode)
4510 switch (GET_CODE (op))
4520 if (GET_MODE (op) != mode && mode != VOIDmode)
4523 subreg = SUBREG_REG (op);
4524 code = GET_CODE (subreg);
4526 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4527 reload_completed, TRUE, FALSE);
4529 return (code == REG);
4532 if (GET_MODE (op) != mode && mode != VOIDmode)
4538 return frv_legitimate_memory_operand (op, mode, TRUE);
4544 /* Return true if operand is a register of any flavor or a 0 of the
4545 appropriate type. */
4548 reg_or_0_operand (rtx op, enum machine_mode mode)
4550 switch (GET_CODE (op))
4557 if (GET_MODE (op) != mode && mode != VOIDmode)
4560 return register_operand (op, mode);
4570 /* Return true if operand is the link register. */
4573 lr_operand (rtx op, enum machine_mode mode)
4575 if (GET_CODE (op) != REG)
4578 if (GET_MODE (op) != mode && mode != VOIDmode)
4581 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4587 /* Return true if operand is the uClinux PIC register. */
4590 fdpic_operand (rtx op, enum machine_mode mode)
4595 if (GET_CODE (op) != REG)
4598 if (GET_MODE (op) != mode && mode != VOIDmode)
4601 if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4608 got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4610 struct frv_unspec unspec;
4612 if (frv_const_unspec_p (op, &unspec))
4613 switch (unspec.reloc)
4616 case R_FRV_GOTOFF12:
4617 case R_FRV_FUNCDESC_GOT12:
4618 case R_FRV_FUNCDESC_GOTOFF12:
4625 /* Return true if OP is a valid const-unspec expression. */
4628 const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4630 struct frv_unspec unspec;
4632 return frv_const_unspec_p (op, &unspec);
4634 /* Return true if operand is a gpr register or a valid memory operation. */
4637 gpr_or_memory_operand (rtx op, enum machine_mode mode)
4639 return (integer_register_operand (op, mode)
4640 || frv_legitimate_memory_operand (op, mode, FALSE));
4643 /* Return true if operand is a fpr register or a valid memory operation. */
4646 fpr_or_memory_operand (rtx op, enum machine_mode mode)
4648 return (fpr_operand (op, mode)
4649 || frv_legitimate_memory_operand (op, mode, FALSE));
4652 /* Return true if operand is an icc register. */
4655 icc_operand (rtx op, enum machine_mode mode)
4659 if (GET_MODE (op) != mode && mode != VOIDmode)
4662 if (GET_CODE (op) != REG)
4666 return ICC_OR_PSEUDO_P (regno);
4669 /* Return true if operand is an fcc register. */
4672 fcc_operand (rtx op, enum machine_mode mode)
4676 if (GET_MODE (op) != mode && mode != VOIDmode)
4679 if (GET_CODE (op) != REG)
4683 return FCC_OR_PSEUDO_P (regno);
4686 /* Return true if operand is either an fcc or icc register. */
4689 cc_operand (rtx op, enum machine_mode mode)
4693 if (GET_MODE (op) != mode && mode != VOIDmode)
4696 if (GET_CODE (op) != REG)
4700 if (CC_OR_PSEUDO_P (regno))
4706 /* Return true if operand is an integer CCR register. */
4709 icr_operand (rtx op, enum machine_mode mode)
4713 if (GET_MODE (op) != mode && mode != VOIDmode)
4716 if (GET_CODE (op) != REG)
4720 return ICR_OR_PSEUDO_P (regno);
4723 /* Return true if operand is an fcc register. */
4726 fcr_operand (rtx op, enum machine_mode mode)
4730 if (GET_MODE (op) != mode && mode != VOIDmode)
4733 if (GET_CODE (op) != REG)
4737 return FCR_OR_PSEUDO_P (regno);
4740 /* Return true if operand is either an fcc or icc register. */
4743 cr_operand (rtx op, enum machine_mode mode)
4747 if (GET_MODE (op) != mode && mode != VOIDmode)
4750 if (GET_CODE (op) != REG)
4754 if (CR_OR_PSEUDO_P (regno))
4760 /* Return true if operand is a memory reference suitable for a call. */
4763 call_operand (rtx op, enum machine_mode mode)
4765 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4768 if (GET_CODE (op) == SYMBOL_REF)
4769 return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op);
4771 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4772 never occur anyway), but prevents reload from not handling the case
4773 properly of a call through a pointer on a function that calls
4774 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4775 return gpr_or_int12_operand (op, mode);
4778 /* Return true if operand is a memory reference suitable for a sibcall. */
4781 sibcall_operand (rtx op, enum machine_mode mode)
4783 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4786 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4787 never occur anyway), but prevents reload from not handling the case
4788 properly of a call through a pointer on a function that calls
4789 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4790 return gpr_or_int12_operand (op, mode);
4793 /* Return true if operator is a kind of relational operator. */
4796 relational_operator (rtx op, enum machine_mode mode)
4798 return (integer_relational_operator (op, mode)
4799 || float_relational_operator (op, mode));
4802 /* Return true if OP is a relational operator suitable for CCmode,
4803 CC_UNSmode or CC_NZmode. */
4806 integer_relational_operator (rtx op, enum machine_mode mode)
4808 if (mode != VOIDmode && mode != GET_MODE (op))
4811 /* The allowable relations depend on the mode of the ICC register. */
4812 switch (GET_CODE (op))
4821 return (GET_MODE (XEXP (op, 0)) == CC_NZmode
4822 || GET_MODE (XEXP (op, 0)) == CCmode);
4826 return GET_MODE (XEXP (op, 0)) == CCmode;
4832 return (GET_MODE (XEXP (op, 0)) == CC_NZmode
4833 || GET_MODE (XEXP (op, 0)) == CC_UNSmode);
4837 /* Return true if operator is a floating point relational operator. */
4840 float_relational_operator (rtx op, enum machine_mode mode)
4842 if (mode != VOIDmode && mode != GET_MODE (op))
4845 switch (GET_CODE (op))
4860 return GET_MODE (XEXP (op, 0)) == CC_FPmode;
4864 /* Return true if operator is EQ/NE of a conditional execution register. */
4867 ccr_eqne_operator (rtx op, enum machine_mode mode)
4869 enum machine_mode op_mode = GET_MODE (op);
4874 if (mode != VOIDmode && op_mode != mode)
4877 switch (GET_CODE (op))
4888 if (op1 != const0_rtx)
4892 if (GET_CODE (op0) != REG)
4895 regno = REGNO (op0);
4896 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4902 /* Return true if operator is a minimum or maximum operator (both signed and
4906 minmax_operator (rtx op, enum machine_mode mode)
4908 if (mode != VOIDmode && mode != GET_MODE (op))
4911 switch (GET_CODE (op))
4923 if (! integer_register_operand (XEXP (op, 0), mode))
4926 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
4932 /* Return true if operator is an integer binary operator that can executed
4933 conditionally and takes 1 cycle. */
4936 condexec_si_binary_operator (rtx op, enum machine_mode mode)
4938 enum machine_mode op_mode = GET_MODE (op);
4940 if (mode != VOIDmode && op_mode != mode)
4943 switch (GET_CODE (op))
4960 /* Return true if operator is an integer binary operator that can be
4961 executed conditionally by a media instruction. */
4964 condexec_si_media_operator (rtx op, enum machine_mode mode)
4966 enum machine_mode op_mode = GET_MODE (op);
4968 if (mode != VOIDmode && op_mode != mode)
4971 switch (GET_CODE (op))
4983 /* Return true if operator is an integer division operator that can executed
4987 condexec_si_divide_operator (rtx op, enum machine_mode mode)
4989 enum machine_mode op_mode = GET_MODE (op);
4991 if (mode != VOIDmode && op_mode != mode)
4994 switch (GET_CODE (op))
5005 /* Return true if operator is an integer unary operator that can executed
5009 condexec_si_unary_operator (rtx op, enum machine_mode mode)
5011 enum machine_mode op_mode = GET_MODE (op);
5013 if (mode != VOIDmode && op_mode != mode)
5016 switch (GET_CODE (op))
5027 /* Return true if operator is a conversion-type expression that can be
5028 evaluated conditionally by floating-point instructions. */
5031 condexec_sf_conv_operator (rtx op, enum machine_mode mode)
5033 enum machine_mode op_mode = GET_MODE (op);
5035 if (mode != VOIDmode && op_mode != mode)
5038 switch (GET_CODE (op))
5049 /* Return true if operator is an addition or subtraction expression.
5050 Such expressions can be evaluated conditionally by floating-point
5054 condexec_sf_add_operator (rtx op, enum machine_mode mode)
5056 enum machine_mode op_mode = GET_MODE (op);
5058 if (mode != VOIDmode && op_mode != mode)
5061 switch (GET_CODE (op))
5072 /* Return true if the memory operand is one that can be conditionally
5076 condexec_memory_operand (rtx op, enum machine_mode mode)
5078 enum machine_mode op_mode = GET_MODE (op);
5081 if (mode != VOIDmode && op_mode != mode)
5096 if (GET_CODE (op) != MEM)
5099 addr = XEXP (op, 0);
5100 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
5103 /* Return true if OP is an integer binary operator that can be combined
5104 with a (set ... (compare:CC_NZ ...)) pattern. */
5107 intop_compare_operator (rtx op, enum machine_mode mode)
5109 if (mode != VOIDmode && GET_MODE (op) != mode)
5112 switch (GET_CODE (op))
5124 return GET_MODE (op) == SImode;
5128 /* Return 1 if operand is a valid ACC register number. */
5131 acc_operand (rtx op, enum machine_mode mode)
5133 return ((mode == VOIDmode || mode == GET_MODE (op))
5134 && REG_P (op) && ACC_P (REGNO (op))
5135 && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0);
5138 /* Return 1 if operand is a valid even ACC register number. */
5141 even_acc_operand (rtx op, enum machine_mode mode)
5143 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0;
5146 /* Return 1 if operand is zero or four. */
5149 quad_acc_operand (rtx op, enum machine_mode mode)
5151 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0;
5154 /* Return 1 if operand is a valid ACCG register number. */
5157 accg_operand (rtx op, enum machine_mode mode)
5159 return ((mode == VOIDmode || mode == GET_MODE (op))
5160 && REG_P (op) && ACCG_P (REGNO (op))
5161 && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0);
5165 /* Return true if the bare return instruction can be used outside of the
5166 epilog code. For frv, we only do it if there was no stack allocation. */
5169 direct_return_p (void)
5173 if (!reload_completed)
5176 info = frv_stack_info ();
5177 return (info->total_size == 0);
5182 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
5187 if (frv_emit_movsi (dest, src))
5196 if (!reload_in_progress
5197 && !reload_completed
5198 && !register_operand (dest, mode)
5199 && !reg_or_0_operand (src, mode))
5200 src = copy_to_mode_reg (mode, src);
5207 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
5210 /* Emit code to handle a MOVSI, adding in the small data register or pic
5211 register if needed to load up addresses. Return TRUE if the appropriate
5212 instructions are emitted. */
5215 frv_emit_movsi (rtx dest, rtx src)
5217 int base_regno = -1;
5220 struct frv_unspec old_unspec;
5222 if (!reload_in_progress
5223 && !reload_completed
5224 && !register_operand (dest, SImode)
5225 && (!reg_or_0_operand (src, SImode)
5226 /* Virtual registers will almost always be replaced by an
5227 add instruction, so expose this to CSE by copying to
5228 an intermediate register. */
5229 || (GET_CODE (src) == REG
5230 && IN_RANGE_P (REGNO (src),
5231 FIRST_VIRTUAL_REGISTER,
5232 LAST_VIRTUAL_REGISTER))))
5234 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5238 /* Explicitly add in the PIC or small data register if needed. */
5239 switch (GET_CODE (src))
5248 /* Using GPREL12, we use a single GOT entry for all symbols
5249 in read-only sections, but trade sequences such as:
5251 sethi #gothi(label), gr#
5252 setlo #gotlo(label), gr#
5257 ld @(gr15,#got12(_gp)), gr#
5258 sethi #gprelhi(label), gr##
5259 setlo #gprello(label), gr##
5262 We may often be able to share gr# for multiple
5263 computations of GPREL addresses, and we may often fold
5264 the final add into the pair of registers of a load or
5265 store instruction, so it's often profitable. Even when
5266 optimizing for size, we're trading a GOT entry for an
5267 additional instruction, which trades GOT space
5268 (read-write) for code size (read-only, shareable), as
5269 long as the symbol is not used in more than two different
5272 With -fpie/-fpic, we'd be trading a single load for a
5273 sequence of 4 instructions, because the offset of the
5274 label can't be assumed to be addressable with 12 bits, so
5275 we don't do this. */
5276 if (TARGET_GPREL_RO)
5277 unspec = R_FRV_GPREL12;
5279 unspec = R_FRV_GOT12;
5282 base_regno = PIC_REGNO;
5287 if (frv_const_unspec_p (src, &old_unspec))
5290 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
5293 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
5294 emit_move_insn (dest, src);
5299 sym = XEXP (sym, 0);
5300 if (GET_CODE (sym) == PLUS
5301 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
5302 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
5303 sym = XEXP (sym, 0);
5304 if (GET_CODE (sym) == SYMBOL_REF)
5306 else if (GET_CODE (sym) == LABEL_REF)
5309 goto handle_whatever;
5317 if (SYMBOL_REF_FUNCTION_P (sym))
5319 if (frv_local_funcdesc_p (sym))
5320 unspec = R_FRV_FUNCDESC_GOTOFF12;
5322 unspec = R_FRV_FUNCDESC_GOT12;
5326 if (CONSTANT_POOL_ADDRESS_P (sym))
5327 switch (GET_CODE (get_pool_constant (sym)))
5334 unspec = R_FRV_GOTOFF12;
5339 if (TARGET_GPREL_RO)
5340 unspec = R_FRV_GPREL12;
5342 unspec = R_FRV_GOT12;
5345 else if (SYMBOL_REF_LOCAL_P (sym)
5346 && !SYMBOL_REF_EXTERNAL_P (sym)
5347 && SYMBOL_REF_DECL (sym)
5348 && (!DECL_P (SYMBOL_REF_DECL (sym))
5349 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
5351 tree decl = SYMBOL_REF_DECL (sym);
5352 tree init = TREE_CODE (decl) == VAR_DECL
5353 ? DECL_INITIAL (decl)
5354 : TREE_CODE (decl) == CONSTRUCTOR
5357 bool named_section, readonly;
5359 if (init && init != error_mark_node)
5360 reloc = compute_reloc_for_constant (init);
5362 named_section = TREE_CODE (decl) == VAR_DECL
5363 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
5364 readonly = decl_readonly_section (decl, reloc);
5367 unspec = R_FRV_GOT12;
5369 unspec = R_FRV_GOTOFF12;
5370 else if (readonly && TARGET_GPREL_RO)
5371 unspec = R_FRV_GPREL12;
5373 unspec = R_FRV_GOT12;
5376 unspec = R_FRV_GOT12;
5380 else if (SYMBOL_REF_SMALL_P (sym))
5381 base_regno = SDA_BASE_REG;
5384 base_regno = PIC_REGNO;
5389 if (base_regno >= 0)
5391 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
5392 emit_insn (gen_symGOTOFF2reg (dest, src,
5393 gen_rtx_REG (Pmode, base_regno),
5394 GEN_INT (R_FRV_GPREL12)));
5396 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
5397 gen_rtx_REG (Pmode, base_regno),
5398 GEN_INT (R_FRV_GPREL12)));
5399 if (base_regno == PIC_REGNO)
5400 cfun->uses_pic_offset_table = TRUE;
5408 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
5409 new uses of it once reload has begun. */
5410 if (reload_in_progress || reload_completed)
5415 case R_FRV_GOTOFF12:
5416 if (!frv_small_data_reloc_p (sym, unspec))
5417 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5420 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5423 if (!frv_small_data_reloc_p (sym, unspec))
5424 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
5427 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5429 case R_FRV_FUNCDESC_GOTOFF12:
5431 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5434 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5438 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
5441 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5445 cfun->uses_pic_offset_table = TRUE;
5454 /* Return a string to output a single word move. */
5457 output_move_single (rtx operands[], rtx insn)
5459 rtx dest = operands[0];
5460 rtx src = operands[1];
5462 if (GET_CODE (dest) == REG)
5464 int dest_regno = REGNO (dest);
5465 enum machine_mode mode = GET_MODE (dest);
5467 if (GPR_P (dest_regno))
5469 if (GET_CODE (src) == REG)
5471 /* gpr <- some sort of register */
5472 int src_regno = REGNO (src);
5474 if (GPR_P (src_regno))
5475 return "mov %1, %0";
5477 else if (FPR_P (src_regno))
5478 return "movfg %1, %0";
5480 else if (SPR_P (src_regno))
5481 return "movsg %1, %0";
5484 else if (GET_CODE (src) == MEM)
5493 return "ldsb%I1%U1 %M1,%0";
5496 return "ldsh%I1%U1 %M1,%0";
5500 return "ld%I1%U1 %M1, %0";
5504 else if (GET_CODE (src) == CONST_INT
5505 || GET_CODE (src) == CONST_DOUBLE)
5507 /* gpr <- integer/floating constant */
5508 HOST_WIDE_INT value;
5510 if (GET_CODE (src) == CONST_INT)
5511 value = INTVAL (src);
5513 else if (mode == SFmode)
5518 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5519 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5524 value = CONST_DOUBLE_LOW (src);
5526 if (IN_RANGE_P (value, -32768, 32767))
5527 return "setlos %1, %0";
5532 else if (GET_CODE (src) == SYMBOL_REF
5533 || GET_CODE (src) == LABEL_REF
5534 || GET_CODE (src) == CONST)
5540 else if (FPR_P (dest_regno))
5542 if (GET_CODE (src) == REG)
5544 /* fpr <- some sort of register */
5545 int src_regno = REGNO (src);
5547 if (GPR_P (src_regno))
5548 return "movgf %1, %0";
5550 else if (FPR_P (src_regno))
5552 if (TARGET_HARD_FLOAT)
5553 return "fmovs %1, %0";
5555 return "mor %1, %1, %0";
5559 else if (GET_CODE (src) == MEM)
5568 return "ldbf%I1%U1 %M1,%0";
5571 return "ldhf%I1%U1 %M1,%0";
5575 return "ldf%I1%U1 %M1, %0";
5579 else if (ZERO_P (src))
5580 return "movgf %., %0";
5583 else if (SPR_P (dest_regno))
5585 if (GET_CODE (src) == REG)
5587 /* spr <- some sort of register */
5588 int src_regno = REGNO (src);
5590 if (GPR_P (src_regno))
5591 return "movgs %1, %0";
5593 else if (ZERO_P (src))
5594 return "movgs %., %0";
5598 else if (GET_CODE (dest) == MEM)
5600 if (GET_CODE (src) == REG)
5602 int src_regno = REGNO (src);
5603 enum machine_mode mode = GET_MODE (dest);
5605 if (GPR_P (src_regno))
5613 return "stb%I0%U0 %1, %M0";
5616 return "sth%I0%U0 %1, %M0";
5620 return "st%I0%U0 %1, %M0";
5624 else if (FPR_P (src_regno))
5632 return "stbf%I0%U0 %1, %M0";
5635 return "sthf%I0%U0 %1, %M0";
5639 return "stf%I0%U0 %1, %M0";
5644 else if (ZERO_P (src))
5646 switch (GET_MODE (dest))
5652 return "stb%I0%U0 %., %M0";
5655 return "sth%I0%U0 %., %M0";
5659 return "st%I0%U0 %., %M0";
5664 fatal_insn ("Bad output_move_single operand", insn);
5669 /* Return a string to output a double word move. */
5672 output_move_double (rtx operands[], rtx insn)
5674 rtx dest = operands[0];
5675 rtx src = operands[1];
5676 enum machine_mode mode = GET_MODE (dest);
5678 if (GET_CODE (dest) == REG)
5680 int dest_regno = REGNO (dest);
5682 if (GPR_P (dest_regno))
5684 if (GET_CODE (src) == REG)
5686 /* gpr <- some sort of register */
5687 int src_regno = REGNO (src);
5689 if (GPR_P (src_regno))
5692 else if (FPR_P (src_regno))
5694 if (((dest_regno - GPR_FIRST) & 1) == 0
5695 && ((src_regno - FPR_FIRST) & 1) == 0)
5696 return "movfgd %1, %0";
5702 else if (GET_CODE (src) == MEM)
5705 if (dbl_memory_one_insn_operand (src, mode))
5706 return "ldd%I1%U1 %M1, %0";
5711 else if (GET_CODE (src) == CONST_INT
5712 || GET_CODE (src) == CONST_DOUBLE)
5716 else if (FPR_P (dest_regno))
5718 if (GET_CODE (src) == REG)
5720 /* fpr <- some sort of register */
5721 int src_regno = REGNO (src);
5723 if (GPR_P (src_regno))
5725 if (((dest_regno - FPR_FIRST) & 1) == 0
5726 && ((src_regno - GPR_FIRST) & 1) == 0)
5727 return "movgfd %1, %0";
5732 else if (FPR_P (src_regno))
5735 && ((dest_regno - FPR_FIRST) & 1) == 0
5736 && ((src_regno - FPR_FIRST) & 1) == 0)
5737 return "fmovd %1, %0";
5743 else if (GET_CODE (src) == MEM)
5746 if (dbl_memory_one_insn_operand (src, mode))
5747 return "lddf%I1%U1 %M1, %0";
5752 else if (ZERO_P (src))
5757 else if (GET_CODE (dest) == MEM)
5759 if (GET_CODE (src) == REG)
5761 int src_regno = REGNO (src);
5763 if (GPR_P (src_regno))
5765 if (((src_regno - GPR_FIRST) & 1) == 0
5766 && dbl_memory_one_insn_operand (dest, mode))
5767 return "std%I0%U0 %1, %M0";
5772 if (FPR_P (src_regno))
5774 if (((src_regno - FPR_FIRST) & 1) == 0
5775 && dbl_memory_one_insn_operand (dest, mode))
5776 return "stdf%I0%U0 %1, %M0";
5782 else if (ZERO_P (src))
5784 if (dbl_memory_one_insn_operand (dest, mode))
5785 return "std%I0%U0 %., %M0";
5791 fatal_insn ("Bad output_move_double operand", insn);
5796 /* Return a string to output a single word conditional move.
5797 Operand0 -- EQ/NE of ccr register and 0
5798 Operand1 -- CCR register
5799 Operand2 -- destination
5800 Operand3 -- source */
5803 output_condmove_single (rtx operands[], rtx insn)
5805 rtx dest = operands[2];
5806 rtx src = operands[3];
5808 if (GET_CODE (dest) == REG)
5810 int dest_regno = REGNO (dest);
5811 enum machine_mode mode = GET_MODE (dest);
5813 if (GPR_P (dest_regno))
5815 if (GET_CODE (src) == REG)
5817 /* gpr <- some sort of register */
5818 int src_regno = REGNO (src);
5820 if (GPR_P (src_regno))
5821 return "cmov %z3, %2, %1, %e0";
5823 else if (FPR_P (src_regno))
5824 return "cmovfg %3, %2, %1, %e0";
5827 else if (GET_CODE (src) == MEM)
5836 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5839 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5843 return "cld%I3%U3 %M3, %2, %1, %e0";
5847 else if (ZERO_P (src))
5848 return "cmov %., %2, %1, %e0";
5851 else if (FPR_P (dest_regno))
5853 if (GET_CODE (src) == REG)
5855 /* fpr <- some sort of register */
5856 int src_regno = REGNO (src);
5858 if (GPR_P (src_regno))
5859 return "cmovgf %3, %2, %1, %e0";
5861 else if (FPR_P (src_regno))
5863 if (TARGET_HARD_FLOAT)
5864 return "cfmovs %3,%2,%1,%e0";
5866 return "cmor %3, %3, %2, %1, %e0";
5870 else if (GET_CODE (src) == MEM)
5873 if (mode == SImode || mode == SFmode)
5874 return "cldf%I3%U3 %M3, %2, %1, %e0";
5877 else if (ZERO_P (src))
5878 return "cmovgf %., %2, %1, %e0";
5882 else if (GET_CODE (dest) == MEM)
5884 if (GET_CODE (src) == REG)
5886 int src_regno = REGNO (src);
5887 enum machine_mode mode = GET_MODE (dest);
5889 if (GPR_P (src_regno))
5897 return "cstb%I2%U2 %3, %M2, %1, %e0";
5900 return "csth%I2%U2 %3, %M2, %1, %e0";
5904 return "cst%I2%U2 %3, %M2, %1, %e0";
5908 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
5909 return "cstf%I2%U2 %3, %M2, %1, %e0";
5912 else if (ZERO_P (src))
5914 enum machine_mode mode = GET_MODE (dest);
5921 return "cstb%I2%U2 %., %M2, %1, %e0";
5924 return "csth%I2%U2 %., %M2, %1, %e0";
5928 return "cst%I2%U2 %., %M2, %1, %e0";
5933 fatal_insn ("Bad output_condmove_single operand", insn);
5938 /* Emit the appropriate code to do a comparison, returning the register the
5939 comparison was done it. */
5942 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
5944 enum machine_mode cc_mode;
5947 /* Floating point doesn't have comparison against a constant. */
5948 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
5949 op1 = force_reg (GET_MODE (op0), op1);
5951 /* Possibly disable using anything but a fixed register in order to work
5952 around cse moving comparisons past function calls. */
5953 cc_mode = SELECT_CC_MODE (test, op0, op1);
5954 cc_reg = ((TARGET_ALLOC_CC)
5955 ? gen_reg_rtx (cc_mode)
5956 : gen_rtx_REG (cc_mode,
5957 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
5959 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5960 gen_rtx_COMPARE (cc_mode, op0, op1)));
5966 /* Emit code for a conditional branch. The comparison operands were previously
5967 stored in frv_compare_op0 and frv_compare_op1.
5969 XXX: I originally wanted to add a clobber of a CCR register to use in
5970 conditional execution, but that confuses the rest of the compiler. */
5973 frv_emit_cond_branch (enum rtx_code test, rtx label)
5978 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
5979 enum machine_mode cc_mode = GET_MODE (cc_reg);
5981 /* Branches generate:
5983 (if_then_else (<test>, <cc_reg>, (const_int 0))
5984 (label_ref <branch_label>)
5986 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
5987 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
5988 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
5989 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
5994 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
5995 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
5998 frv_emit_scc (enum rtx_code test, rtx target)
6004 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6006 /* SCC instructions generate:
6007 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6008 (clobber (<ccr_reg>))]) */
6009 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6010 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6012 cr_reg = ((TARGET_ALLOC_CC)
6013 ? gen_reg_rtx (CC_CCRmode)
6014 : gen_rtx_REG (CC_CCRmode,
6015 ((GET_MODE (cc_reg) == CC_FPmode)
6019 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6020 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6025 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6026 the separate insns. */
6029 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
6035 /* Set the appropriate CCR bit. */
6036 emit_insn (gen_rtx_SET (VOIDmode,
6038 gen_rtx_fmt_ee (GET_CODE (test),
6043 /* Move the value into the destination. */
6044 emit_move_insn (dest, GEN_INT (value));
6046 /* Move 0 into the destination if the test failed */
6047 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6048 gen_rtx_EQ (GET_MODE (cr_reg),
6051 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6053 /* Finish up, return sequence. */
6060 /* Emit the code for a conditional move, return TRUE if we could do the
6064 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
6071 enum rtx_code test = GET_CODE (test_rtx);
6072 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6073 enum machine_mode cc_mode = GET_MODE (cc_reg);
6075 /* Conditional move instructions generate:
6076 (parallel [(set <target>
6077 (if_then_else (<test> <cc_reg> (const_int 0))
6080 (clobber (<ccr_reg>))]) */
6082 /* Handle various cases of conditional move involving two constants. */
6083 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6085 HOST_WIDE_INT value1 = INTVAL (src1);
6086 HOST_WIDE_INT value2 = INTVAL (src2);
6088 /* Having 0 as one of the constants can be done by loading the other
6089 constant, and optionally moving in gr0. */
6090 if (value1 == 0 || value2 == 0)
6093 /* If the first value is within an addi range and also the difference
6094 between the two fits in an addi's range, load up the difference, then
6095 conditionally move in 0, and then unconditionally add the first
6097 else if (IN_RANGE_P (value1, -2048, 2047)
6098 && IN_RANGE_P (value2 - value1, -2048, 2047))
6101 /* If neither condition holds, just force the constant into a
6105 src1 = force_reg (GET_MODE (dest), src1);
6106 src2 = force_reg (GET_MODE (dest), src2);
6110 /* If one value is a register, insure the other value is either 0 or a
6114 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6115 src1 = force_reg (GET_MODE (dest), src1);
6117 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6118 src2 = force_reg (GET_MODE (dest), src2);
6121 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6122 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6124 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6126 cr_reg = ((TARGET_ALLOC_CC)
6127 ? gen_reg_rtx (CC_CCRmode)
6128 : gen_rtx_REG (CC_CCRmode,
6129 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6131 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6132 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6137 /* Split a conditional move into constituent parts, returning a SEQUENCE
6138 containing all of the insns. */
6141 frv_split_cond_move (rtx operands[])
6143 rtx dest = operands[0];
6144 rtx test = operands[1];
6145 rtx cc_reg = operands[2];
6146 rtx src1 = operands[3];
6147 rtx src2 = operands[4];
6148 rtx cr_reg = operands[5];
6150 enum machine_mode cr_mode = GET_MODE (cr_reg);
6154 /* Set the appropriate CCR bit. */
6155 emit_insn (gen_rtx_SET (VOIDmode,
6157 gen_rtx_fmt_ee (GET_CODE (test),
6162 /* Handle various cases of conditional move involving two constants. */
6163 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6165 HOST_WIDE_INT value1 = INTVAL (src1);
6166 HOST_WIDE_INT value2 = INTVAL (src2);
6168 /* Having 0 as one of the constants can be done by loading the other
6169 constant, and optionally moving in gr0. */
6172 emit_move_insn (dest, src2);
6173 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6174 gen_rtx_NE (cr_mode, cr_reg,
6176 gen_rtx_SET (VOIDmode, dest, src1)));
6179 else if (value2 == 0)
6181 emit_move_insn (dest, src1);
6182 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6183 gen_rtx_EQ (cr_mode, cr_reg,
6185 gen_rtx_SET (VOIDmode, dest, src2)));
6188 /* If the first value is within an addi range and also the difference
6189 between the two fits in an addi's range, load up the difference, then
6190 conditionally move in 0, and then unconditionally add the first
6192 else if (IN_RANGE_P (value1, -2048, 2047)
6193 && IN_RANGE_P (value2 - value1, -2048, 2047))
6195 rtx dest_si = ((GET_MODE (dest) == SImode)
6197 : gen_rtx_SUBREG (SImode, dest, 0));
6199 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6200 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6201 gen_rtx_NE (cr_mode, cr_reg,
6203 gen_rtx_SET (VOIDmode, dest_si,
6205 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6213 /* Emit the conditional move for the test being true if needed. */
6214 if (! rtx_equal_p (dest, src1))
6215 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6216 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6217 gen_rtx_SET (VOIDmode, dest, src1)));
6219 /* Emit the conditional move for the test being false if needed. */
6220 if (! rtx_equal_p (dest, src2))
6221 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6222 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6223 gen_rtx_SET (VOIDmode, dest, src2)));
6226 /* Finish up, return sequence. */
6233 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6234 memory location that is not known to be dword-aligned. */
6236 frv_split_double_load (rtx dest, rtx source)
6238 int regno = REGNO (dest);
6239 rtx dest1 = gen_highpart (SImode, dest);
6240 rtx dest2 = gen_lowpart (SImode, dest);
6241 rtx address = XEXP (source, 0);
6243 /* If the address is pre-modified, load the lower-numbered register
6244 first, then load the other register using an integer offset from
6245 the modified base register. This order should always be safe,
6246 since the pre-modification cannot affect the same registers as the
6249 The situation for other loads is more complicated. Loading one
6250 of the registers could affect the value of ADDRESS, so we must
6251 be careful which order we do them in. */
6252 if (GET_CODE (address) == PRE_MODIFY
6253 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6255 /* It is safe to load the lower-numbered register first. */
6256 emit_move_insn (dest1, change_address (source, SImode, NULL));
6257 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6261 /* ADDRESS is not pre-modified and the address depends on the
6262 lower-numbered register. Load the higher-numbered register
6264 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6265 emit_move_insn (dest1, change_address (source, SImode, NULL));
6269 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6270 and SOURCE is either a double register or the constant zero. */
6272 frv_split_double_store (rtx dest, rtx source)
6274 rtx dest1 = change_address (dest, SImode, NULL);
6275 rtx dest2 = frv_index_memory (dest, SImode, 1);
6276 if (ZERO_P (source))
6278 emit_move_insn (dest1, CONST0_RTX (SImode));
6279 emit_move_insn (dest2, CONST0_RTX (SImode));
6283 emit_move_insn (dest1, gen_highpart (SImode, source));
6284 emit_move_insn (dest2, gen_lowpart (SImode, source));
6289 /* Split a min/max operation returning a SEQUENCE containing all of the
6293 frv_split_minmax (rtx operands[])
6295 rtx dest = operands[0];
6296 rtx minmax = operands[1];
6297 rtx src1 = operands[2];
6298 rtx src2 = operands[3];
6299 rtx cc_reg = operands[4];
6300 rtx cr_reg = operands[5];
6302 enum rtx_code test_code;
6303 enum machine_mode cr_mode = GET_MODE (cr_reg);
6307 /* Figure out which test to use. */
6308 switch (GET_CODE (minmax))
6313 case SMIN: test_code = LT; break;
6314 case SMAX: test_code = GT; break;
6315 case UMIN: test_code = LTU; break;
6316 case UMAX: test_code = GTU; break;
6319 /* Issue the compare instruction. */
6320 emit_insn (gen_rtx_SET (VOIDmode,
6322 gen_rtx_COMPARE (GET_MODE (cc_reg),
6325 /* Set the appropriate CCR bit. */
6326 emit_insn (gen_rtx_SET (VOIDmode,
6328 gen_rtx_fmt_ee (test_code,
6333 /* If are taking the min/max of a nonzero constant, load that first, and
6334 then do a conditional move of the other value. */
6335 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6337 if (rtx_equal_p (dest, src1))
6340 emit_move_insn (dest, src2);
6341 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6342 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6343 gen_rtx_SET (VOIDmode, dest, src1)));
6346 /* Otherwise, do each half of the move. */
6349 /* Emit the conditional move for the test being true if needed. */
6350 if (! rtx_equal_p (dest, src1))
6351 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6352 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6353 gen_rtx_SET (VOIDmode, dest, src1)));
6355 /* Emit the conditional move for the test being false if needed. */
6356 if (! rtx_equal_p (dest, src2))
6357 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6358 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6359 gen_rtx_SET (VOIDmode, dest, src2)));
6362 /* Finish up, return sequence. */
6369 /* Split an integer abs operation returning a SEQUENCE containing all of the
6373 frv_split_abs (rtx operands[])
6375 rtx dest = operands[0];
6376 rtx src = operands[1];
6377 rtx cc_reg = operands[2];
6378 rtx cr_reg = operands[3];
6383 /* Issue the compare < 0 instruction. */
6384 emit_insn (gen_rtx_SET (VOIDmode,
6386 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6388 /* Set the appropriate CCR bit. */
6389 emit_insn (gen_rtx_SET (VOIDmode,
6391 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6393 /* Emit the conditional negate if the value is negative. */
6394 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6395 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6396 gen_negsi2 (dest, src)));
6398 /* Emit the conditional move for the test being false if needed. */
6399 if (! rtx_equal_p (dest, src))
6400 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6401 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6402 gen_rtx_SET (VOIDmode, dest, src)));
6404 /* Finish up, return sequence. */
6411 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6412 register used in an insn. */
6415 frv_clear_registers_used (rtx *ptr, void *data)
6417 if (GET_CODE (*ptr) == REG)
6419 int regno = REGNO (*ptr);
6420 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6422 if (regno < FIRST_PSEUDO_REGISTER)
6424 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6426 while (regno < reg_max)
6428 CLEAR_HARD_REG_BIT (*p_regs, regno);
6438 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6440 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6441 initialize the static storage. */
6443 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6445 frv_ifcvt.added_insns_list = NULL_RTX;
6446 frv_ifcvt.cur_scratch_regs = 0;
6447 frv_ifcvt.num_nested_cond_exec = 0;
6448 frv_ifcvt.cr_reg = NULL_RTX;
6449 frv_ifcvt.nested_cc_reg = NULL_RTX;
6450 frv_ifcvt.extra_int_cr = NULL_RTX;
6451 frv_ifcvt.extra_fp_cr = NULL_RTX;
6452 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6456 /* Internal function to add a potential insn to the list of insns to be inserted
6457 if the conditional execution conversion is successful. */
6460 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
6462 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6464 link->jump = before_p; /* Mark to add this before or after insn. */
6465 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6466 frv_ifcvt.added_insns_list);
6468 if (TARGET_DEBUG_COND_EXEC)
6471 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6472 (before_p) ? "before" : "after",
6473 (int)INSN_UID (insn));
6475 debug_rtx (pattern);
6480 /* A C expression to modify the code described by the conditional if
6481 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6482 FALSE_EXPR for converting if-then and if-then-else code to conditional
6483 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6484 tests cannot be converted. */
6487 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
6489 basic_block test_bb = ce_info->test_bb; /* test basic block */
6490 basic_block then_bb = ce_info->then_bb; /* THEN */
6491 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6492 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6493 rtx true_expr = *p_true;
6497 enum machine_mode mode = GET_MODE (true_expr);
6501 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6503 rtx sub_cond_exec_reg;
6505 enum rtx_code code_true;
6506 enum rtx_code code_false;
6507 enum reg_class cc_class;
6508 enum reg_class cr_class;
6511 reg_set_iterator rsi;
6513 /* Make sure we are only dealing with hard registers. Also honor the
6514 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6516 if (!reload_completed || TARGET_NO_COND_EXEC
6517 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6520 /* Figure out which registers we can allocate for our own purposes. Only
6521 consider registers that are not preserved across function calls and are
6522 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6523 if we did not need to use them in reloading other registers. */
6524 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6525 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6526 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6527 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6528 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6530 /* If this is a nested IF, we need to discover whether the CC registers that
6531 are set/used inside of the block are used anywhere else. If not, we can
6532 change them to be the CC register that is paired with the CR register that
6533 controls the outermost IF block. */
6534 if (ce_info->pass > 1)
6536 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6537 for (j = CC_FIRST; j <= CC_LAST; j++)
6538 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6540 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6543 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6546 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6549 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6553 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6554 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6556 frv_ifcvt.added_insns_list = NULL_RTX;
6557 frv_ifcvt.cur_scratch_regs = 0;
6559 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6560 * sizeof (basic_block));
6566 /* Remove anything live at the beginning of the join block from being
6567 available for allocation. */
6568 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno, rsi)
6570 if (regno < FIRST_PSEUDO_REGISTER)
6571 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6575 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6577 if (ce_info->num_multiple_test_blocks)
6579 basic_block multiple_test_bb = ce_info->last_test_bb;
6581 while (multiple_test_bb != test_bb)
6583 bb[num_bb++] = multiple_test_bb;
6584 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
6588 /* Add in the THEN and ELSE blocks to be scanned. */
6589 bb[num_bb++] = then_bb;
6591 bb[num_bb++] = else_bb;
6593 sub_cond_exec_reg = NULL_RTX;
6594 frv_ifcvt.num_nested_cond_exec = 0;
6596 /* Scan all of the blocks for registers that must not be allocated. */
6597 for (j = 0; j < num_bb; j++)
6599 rtx last_insn = BB_END (bb[j]);
6600 rtx insn = BB_HEAD (bb[j]);
6604 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
6605 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6607 (int) INSN_UID (BB_HEAD (bb[j])),
6608 (int) INSN_UID (BB_END (bb[j])));
6610 /* Anything live at the beginning of the block is obviously unavailable
6612 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno, rsi)
6614 if (regno < FIRST_PSEUDO_REGISTER)
6615 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6618 /* Loop through the insns in the block. */
6621 /* Mark any new registers that are created as being unavailable for
6622 allocation. Also see if the CC register used in nested IFs can be
6628 int skip_nested_if = FALSE;
6630 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6631 (void *)&tmp_reg->regs);
6633 pattern = PATTERN (insn);
6634 if (GET_CODE (pattern) == COND_EXEC)
6636 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6638 if (reg != sub_cond_exec_reg)
6640 sub_cond_exec_reg = reg;
6641 frv_ifcvt.num_nested_cond_exec++;
6645 set = single_set_pattern (pattern);
6648 rtx dest = SET_DEST (set);
6649 rtx src = SET_SRC (set);
6651 if (GET_CODE (dest) == REG)
6653 int regno = REGNO (dest);
6654 enum rtx_code src_code = GET_CODE (src);
6656 if (CC_P (regno) && src_code == COMPARE)
6657 skip_nested_if = TRUE;
6659 else if (CR_P (regno)
6660 && (src_code == IF_THEN_ELSE
6661 || COMPARISON_P (src)))
6662 skip_nested_if = TRUE;
6666 if (! skip_nested_if)
6667 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6668 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6671 if (insn == last_insn)
6674 insn = NEXT_INSN (insn);
6678 /* If this is a nested if, rewrite the CC registers that are available to
6679 include the ones that can be rewritten, to increase the chance of being
6680 able to allocate a paired CC/CR register combination. */
6681 if (ce_info->pass > 1)
6683 for (j = CC_FIRST; j <= CC_LAST; j++)
6684 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6685 SET_HARD_REG_BIT (tmp_reg->regs, j);
6687 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6693 fprintf (dump_file, "Available GPRs: ");
6695 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6696 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6698 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6699 if (++num_gprs > GPR_TEMP_NUM+2)
6703 fprintf (dump_file, "%s\nAvailable CRs: ",
6704 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6706 for (j = CR_FIRST; j <= CR_LAST; j++)
6707 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6708 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6710 fputs ("\n", dump_file);
6712 if (ce_info->pass > 1)
6714 fprintf (dump_file, "Modifiable CCs: ");
6715 for (j = CC_FIRST; j <= CC_LAST; j++)
6716 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6717 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6719 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
6720 frv_ifcvt.num_nested_cond_exec);
6724 /* Allocate the appropriate temporary condition code register. Try to
6725 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6726 that conditional cmp's can be done. */
6727 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
6729 cr_class = ICR_REGS;
6730 cc_class = ICC_REGS;
6731 cc_first = ICC_FIRST;
6734 else if (mode == CC_FPmode)
6736 cr_class = FCR_REGS;
6737 cc_class = FCC_REGS;
6738 cc_first = FCC_FIRST;
6743 cc_first = cc_last = 0;
6744 cr_class = cc_class = NO_REGS;
6747 cc = XEXP (true_expr, 0);
6748 nested_cc = cr = NULL_RTX;
6749 if (cc_class != NO_REGS)
6751 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6752 so we can execute a csubcc/caddcc/cfcmps instruction. */
6755 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6757 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6759 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6760 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6762 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6763 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6766 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6767 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6777 fprintf (dump_file, "Could not allocate a CR temporary register\n");
6784 "Will use %s for conditional execution, %s for nested comparisons\n",
6785 reg_names[ REGNO (cr)],
6786 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6788 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6789 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6790 bit being true. We don't do this for floating point, because of NaNs. */
6791 code = GET_CODE (true_expr);
6792 if (GET_MODE (cc) != CC_FPmode)
6794 code = reverse_condition (code);
6804 check_insn = gen_rtx_SET (VOIDmode, cr,
6805 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6807 /* Record the check insn to be inserted later. */
6808 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
6810 /* Update the tests. */
6811 frv_ifcvt.cr_reg = cr;
6812 frv_ifcvt.nested_cc_reg = nested_cc;
6813 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6814 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6817 /* Fail, don't do this conditional execution. */
6820 *p_false = NULL_RTX;
6822 fprintf (dump_file, "Disabling this conditional execution.\n");
6828 /* A C expression to modify the code described by the conditional if
6829 information CE_INFO, for the basic block BB, possibly updating the tests in
6830 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6831 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6832 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6834 /* p_true and p_false are given expressions of the form:
6836 (and (eq:CC_CCR (reg:CC_CCR)
6842 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
6847 rtx old_true = XEXP (*p_true, 0);
6848 rtx old_false = XEXP (*p_false, 0);
6849 rtx true_expr = XEXP (*p_true, 1);
6850 rtx false_expr = XEXP (*p_false, 1);
6853 rtx cr = XEXP (old_true, 0);
6855 rtx new_cr = NULL_RTX;
6856 rtx *p_new_cr = (rtx *)0;
6860 enum reg_class cr_class;
6861 enum machine_mode mode = GET_MODE (true_expr);
6862 rtx (*logical_func)(rtx, rtx, rtx);
6864 if (TARGET_DEBUG_COND_EXEC)
6867 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6868 ce_info->and_and_p ? "&&" : "||");
6870 debug_rtx (*p_true);
6872 fputs ("\nfalse insn:\n", stderr);
6873 debug_rtx (*p_false);
6876 if (TARGET_NO_MULTI_CE)
6879 if (GET_CODE (cr) != REG)
6882 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
6884 cr_class = ICR_REGS;
6885 p_new_cr = &frv_ifcvt.extra_int_cr;
6887 else if (mode == CC_FPmode)
6889 cr_class = FCR_REGS;
6890 p_new_cr = &frv_ifcvt.extra_fp_cr;
6895 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6896 more &&/|| tests. */
6900 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
6901 CC_CCRmode, TRUE, TRUE);
6906 if (ce_info->and_and_p)
6908 old_test = old_false;
6909 test_expr = true_expr;
6910 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
6911 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6912 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6916 old_test = old_false;
6917 test_expr = false_expr;
6918 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
6919 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6920 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6923 /* First add the andcr/andncr/orcr/orncr, which will be added after the
6924 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
6926 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
6928 /* Now add the conditional check insn. */
6929 cc = XEXP (test_expr, 0);
6930 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
6931 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
6933 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
6935 /* Add the new check insn to the list of check insns that need to be
6937 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
6939 if (TARGET_DEBUG_COND_EXEC)
6941 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
6944 debug_rtx (*p_true);
6946 fputs ("\nfalse insn:\n", stderr);
6947 debug_rtx (*p_false);
6953 *p_true = *p_false = NULL_RTX;
6955 /* If we allocated a CR register, release it. */
6958 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
6959 *p_new_cr = NULL_RTX;
6962 if (TARGET_DEBUG_COND_EXEC)
6963 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
6969 /* Return a register which will be loaded with a value if an IF block is
6970 converted to conditional execution. This is used to rewrite instructions
6971 that use constants to ones that just use registers. */
6974 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
6976 int num_alloc = frv_ifcvt.cur_scratch_regs;
6980 /* We know gr0 == 0, so replace any errant uses. */
6981 if (value == const0_rtx)
6982 return gen_rtx_REG (SImode, GPR_FIRST);
6984 /* First search all registers currently loaded to see if we have an
6985 applicable constant. */
6986 if (CONSTANT_P (value)
6987 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
6989 for (i = 0; i < num_alloc; i++)
6991 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
6992 return SET_DEST (frv_ifcvt.scratch_regs[i]);
6996 /* Have we exhausted the number of registers available? */
6997 if (num_alloc >= GPR_TEMP_NUM)
7000 fprintf (dump_file, "Too many temporary registers allocated\n");
7005 /* Allocate the new register. */
7006 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7010 fputs ("Could not find a scratch register\n", dump_file);
7015 frv_ifcvt.cur_scratch_regs++;
7016 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7020 if (GET_CODE (value) == CONST_INT)
7021 fprintf (dump_file, "Register %s will hold %ld\n",
7022 reg_names[ REGNO (reg)], (long)INTVAL (value));
7024 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7025 fprintf (dump_file, "Register %s will hold LR\n",
7026 reg_names[ REGNO (reg)]);
7029 fprintf (dump_file, "Register %s will hold a saved value\n",
7030 reg_names[ REGNO (reg)]);
7037 /* Update a MEM used in conditional code that might contain an offset to put
7038 the offset into a scratch register, so that the conditional load/store
7039 operations can be used. This function returns the original pointer if the
7040 MEM is valid to use in conditional code, NULL if we can't load up the offset
7041 into a temporary register, or the new MEM if we were successful. */
7044 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
7046 rtx addr = XEXP (mem, 0);
7048 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
7050 if (GET_CODE (addr) == PLUS)
7052 rtx addr_op0 = XEXP (addr, 0);
7053 rtx addr_op1 = XEXP (addr, 1);
7055 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7057 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7061 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7068 else if (CONSTANT_P (addr))
7069 addr = frv_ifcvt_load_value (addr, insn);
7074 if (addr == NULL_RTX)
7077 else if (XEXP (mem, 0) != addr)
7078 return change_address (mem, mode, addr);
7085 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7086 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7089 single_set_pattern (rtx pattern)
7094 if (GET_CODE (pattern) == COND_EXEC)
7095 pattern = COND_EXEC_CODE (pattern);
7097 if (GET_CODE (pattern) == SET)
7100 else if (GET_CODE (pattern) == PARALLEL)
7102 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7104 rtx sub = XVECEXP (pattern, 0, i);
7106 switch (GET_CODE (sub))
7130 /* A C expression to modify the code described by the conditional if
7131 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7132 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7133 insn cannot be converted to be executed conditionally. */
7136 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
7140 rtx orig_ce_pattern = pattern;
7146 if (GET_CODE (pattern) != COND_EXEC)
7149 test = COND_EXEC_TEST (pattern);
7150 if (GET_CODE (test) == AND)
7152 rtx cr = frv_ifcvt.cr_reg;
7155 op0 = XEXP (test, 0);
7156 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7159 op1 = XEXP (test, 1);
7160 test_reg = XEXP (op1, 0);
7161 if (GET_CODE (test_reg) != REG)
7164 /* Is this the first nested if block in this sequence? If so, generate
7165 an andcr or andncr. */
7166 if (! frv_ifcvt.last_nested_if_cr)
7170 frv_ifcvt.last_nested_if_cr = test_reg;
7171 if (GET_CODE (op0) == NE)
7172 and_op = gen_andcr (test_reg, cr, test_reg);
7174 and_op = gen_andncr (test_reg, cr, test_reg);
7176 frv_ifcvt_add_insn (and_op, insn, TRUE);
7179 /* If this isn't the first statement in the nested if sequence, see if we
7180 are dealing with the same register. */
7181 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7184 COND_EXEC_TEST (pattern) = test = op1;
7187 /* If this isn't a nested if, reset state variables. */
7190 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7193 set = single_set_pattern (pattern);
7196 rtx dest = SET_DEST (set);
7197 rtx src = SET_SRC (set);
7198 enum machine_mode mode = GET_MODE (dest);
7200 /* Check for normal binary operators. */
7201 if (mode == SImode && ARITHMETIC_P (src))
7203 op0 = XEXP (src, 0);
7204 op1 = XEXP (src, 1);
7206 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7208 op1 = frv_ifcvt_load_value (op1, insn);
7210 COND_EXEC_CODE (pattern)
7211 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7219 /* For multiply by a constant, we need to handle the sign extending
7220 correctly. Add a USE of the value after the multiply to prevent flow
7221 from cratering because only one register out of the two were used. */
7222 else if (mode == DImode && GET_CODE (src) == MULT)
7224 op0 = XEXP (src, 0);
7225 op1 = XEXP (src, 1);
7226 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7228 op1 = frv_ifcvt_load_value (op1, insn);
7231 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7232 COND_EXEC_CODE (pattern)
7233 = gen_rtx_SET (VOIDmode, dest,
7234 gen_rtx_MULT (DImode, op0, op1));
7240 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7243 /* If we are just loading a constant created for a nested conditional
7244 execution statement, just load the constant without any conditional
7245 execution, since we know that the constant will not interfere with any
7247 else if (frv_ifcvt.scratch_insns_bitmap
7248 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7250 && REG_P (SET_DEST (set))
7251 /* We must not unconditionally set a scratch reg chosen
7252 for a nested if-converted block if its incoming
7253 value from the TEST block (or the result of the THEN
7254 branch) could/should propagate to the JOIN block.
7255 It suffices to test whether the register is live at
7256 the JOIN point: if it's live there, we can infer
7257 that we set it in the former JOIN block of the
7258 nested if-converted block (otherwise it wouldn't
7259 have been available as a scratch register), and it
7260 is either propagated through or set in the other
7261 conditional block. It's probably not worth trying
7262 to catch the latter case, and it could actually
7263 limit scheduling of the combined block quite
7266 && ! (REGNO_REG_SET_P
7267 (ce_info->join_bb->global_live_at_start,
7268 REGNO (SET_DEST (set))))
7269 /* Similarly, we must not unconditionally set a reg
7270 used as scratch in the THEN branch if the same reg
7271 is live in the ELSE branch. */
7272 && (! ce_info->else_bb
7273 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
7274 || ! (REGNO_REG_SET_P
7275 (ce_info->else_bb->global_live_at_start,
7276 REGNO (SET_DEST (set))))))
7279 else if (mode == QImode || mode == HImode || mode == SImode
7282 int changed_p = FALSE;
7284 /* Check for just loading up a constant */
7285 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7287 src = frv_ifcvt_load_value (src, insn);
7294 /* See if we need to fix up stores */
7295 if (GET_CODE (dest) == MEM)
7297 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7302 else if (new_mem != dest)
7309 /* See if we need to fix up loads */
7310 if (GET_CODE (src) == MEM)
7312 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7317 else if (new_mem != src)
7324 /* If either src or destination changed, redo SET. */
7326 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7329 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7330 rewriting the CC register to be the same as the paired CC/CR register
7332 else if (mode == CC_CCRmode && COMPARISON_P (src))
7334 int regno = REGNO (XEXP (src, 0));
7337 if (ce_info->pass > 1
7338 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7339 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7341 src = gen_rtx_fmt_ee (GET_CODE (src),
7343 frv_ifcvt.nested_cc_reg,
7347 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7348 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7351 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7352 else if (ce_info->pass > 1
7353 && GET_CODE (dest) == REG
7354 && CC_P (REGNO (dest))
7355 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7356 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7358 && GET_CODE (src) == COMPARE)
7360 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7361 COND_EXEC_CODE (pattern)
7362 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7366 if (TARGET_DEBUG_COND_EXEC)
7368 rtx orig_pattern = PATTERN (insn);
7370 PATTERN (insn) = pattern;
7372 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7376 PATTERN (insn) = orig_pattern;
7382 if (TARGET_DEBUG_COND_EXEC)
7384 rtx orig_pattern = PATTERN (insn);
7386 PATTERN (insn) = orig_ce_pattern;
7388 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7392 PATTERN (insn) = orig_pattern;
7399 /* A C expression to perform any final machine dependent modifications in
7400 converting code to conditional execution in the code described by the
7401 conditional if information CE_INFO. */
7404 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7408 rtx p = frv_ifcvt.added_insns_list;
7411 /* Loop inserting the check insns. The last check insn is the first test,
7412 and is the appropriate place to insert constants. */
7418 rtx check_and_insert_insns = XEXP (p, 0);
7421 check_insn = XEXP (check_and_insert_insns, 0);
7422 existing_insn = XEXP (check_and_insert_insns, 1);
7425 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7426 the existing insn, otherwise it is to be inserted AFTER. */
7427 if (check_and_insert_insns->jump)
7429 emit_insn_before (check_insn, existing_insn);
7430 check_and_insert_insns->jump = 0;
7433 emit_insn_after (check_insn, existing_insn);
7435 free_EXPR_LIST_node (check_and_insert_insns);
7436 free_EXPR_LIST_node (old_p);
7438 while (p != NULL_RTX);
7440 /* Load up any constants needed into temp gprs */
7441 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7443 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7444 if (! frv_ifcvt.scratch_insns_bitmap)
7445 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7446 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7447 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7450 frv_ifcvt.added_insns_list = NULL_RTX;
7451 frv_ifcvt.cur_scratch_regs = 0;
7455 /* A C expression to cancel any machine dependent modifications in converting
7456 code to conditional execution in the code described by the conditional if
7457 information CE_INFO. */
7460 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7463 rtx p = frv_ifcvt.added_insns_list;
7465 /* Loop freeing up the EXPR_LIST's allocated. */
7466 while (p != NULL_RTX)
7468 rtx check_and_jump = XEXP (p, 0);
7472 free_EXPR_LIST_node (check_and_jump);
7473 free_EXPR_LIST_node (old_p);
7476 /* Release any temporary gprs allocated. */
7477 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7478 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7480 frv_ifcvt.added_insns_list = NULL_RTX;
7481 frv_ifcvt.cur_scratch_regs = 0;
7485 /* A C expression for the size in bytes of the trampoline, as an integer.
7489 setlo #0, <static_chain>
7491 sethi #0, <static_chain>
7492 jmpl @(gr0,<jmp_reg>) */
7495 frv_trampoline_size (void)
7498 /* Allocate room for the function descriptor and the lddi
7501 return 5 /* instructions */ * 4 /* instruction size. */;
7505 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7506 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7507 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7508 should be passed to the function when it is called.
7513 setlo #0, <static_chain>
7515 sethi #0, <static_chain>
7516 jmpl @(gr0,<jmp_reg>) */
7519 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
7521 rtx sc_reg = force_reg (Pmode, static_chain);
7523 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7526 GEN_INT (frv_trampoline_size ()), SImode,
7532 /* Many machines have some registers that cannot be copied directly to or from
7533 memory or even from other types of registers. An example is the `MQ'
7534 register, which on most machines, can only be copied to or from general
7535 registers, but not memory. Some machines allow copying all registers to and
7536 from memory, but require a scratch register for stores to some memory
7537 locations (e.g., those with symbolic address on the RT, and those with
7538 certain symbolic address on the SPARC when compiling PIC). In some cases,
7539 both an intermediate and a scratch register are required.
7541 You should define these macros to indicate to the reload phase that it may
7542 need to allocate at least one register for a reload in addition to the
7543 register to contain the data. Specifically, if copying X to a register
7544 CLASS in MODE requires an intermediate register, you should define
7545 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7546 whose registers can be used as intermediate registers or scratch registers.
7548 If copying a register CLASS in MODE to X requires an intermediate or scratch
7549 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7550 largest register class required. If the requirements for input and output
7551 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7552 instead of defining both macros identically.
7554 The values returned by these macros are often `GENERAL_REGS'. Return
7555 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7556 to or from a register of CLASS in MODE without requiring a scratch register.
7557 Do not define this macro if it would always return `NO_REGS'.
7559 If a scratch register is required (either with or without an intermediate
7560 register), you should define patterns for `reload_inM' or `reload_outM', as
7561 required.. These patterns, which will normally be implemented with a
7562 `define_expand', should be similar to the `movM' patterns, except that
7563 operand 2 is the scratch register.
7565 Define constraints for the reload register and scratch register that contain
7566 a single register class. If the original reload register (whose class is
7567 CLASS) can meet the constraint given in the pattern, the value returned by
7568 these macros is used for the class of the scratch register. Otherwise, two
7569 additional reload registers are required. Their classes are obtained from
7570 the constraints in the insn pattern.
7572 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7573 either be in a hard register or in memory. Use `true_regnum' to find out;
7574 it will return -1 if the pseudo is in memory and the hard register number if
7575 it is in a register.
7577 These macros should not be used in the case where a particular class of
7578 registers can only be copied to memory and not to another class of
7579 registers. In that case, secondary reload registers are not needed and
7580 would not be helpful. Instead, a stack location must be used to perform the
7581 copy and the `movM' pattern should use memory as an intermediate storage.
7582 This case often occurs between floating-point and general registers. */
7585 frv_secondary_reload_class (enum reg_class class,
7586 enum machine_mode mode ATTRIBUTE_UNUSED,
7588 int in_p ATTRIBUTE_UNUSED)
7598 /* Accumulators/Accumulator guard registers need to go through floating
7604 if (x && GET_CODE (x) == REG)
7606 int regno = REGNO (x);
7608 if (ACC_P (regno) || ACCG_P (regno))
7613 /* Nonzero constants should be loaded into an FPR through a GPR. */
7617 if (x && CONSTANT_P (x) && !ZERO_P (x))
7623 /* All of these types need gpr registers. */
7635 /* The accumulators need fpr registers */
7648 /* A C expression whose value is nonzero if pseudos that have been assigned to
7649 registers of class CLASS would likely be spilled because registers of CLASS
7650 are needed for spill registers.
7652 The default value of this macro returns 1 if CLASS has exactly one register
7653 and zero otherwise. On most machines, this default should be used. Only
7654 define this macro to some other expression if pseudo allocated by
7655 `local-alloc.c' end up in memory because their hard registers were needed
7656 for spill registers. If this macro returns nonzero for those classes, those
7657 pseudos will only be allocated by `global.c', which knows how to reallocate
7658 the pseudo to another register. If there would not be another register
7659 available for reallocation, you should not change the definition of this
7660 macro since the only effect of such a definition would be to slow down
7661 register allocation. */
7664 frv_class_likely_spilled_p (enum reg_class class)
7691 /* An expression for the alignment of a structure field FIELD if the
7692 alignment computed in the usual way is COMPUTED. GCC uses this
7693 value instead of the value in `BIGGEST_ALIGNMENT' or
7694 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7696 /* The definition type of the bit field data is either char, short, long or
7697 long long. The maximum bit size is the number of bits of its own type.
7699 The bit field data is assigned to a storage unit that has an adequate size
7700 for bit field data retention and is located at the smallest address.
7702 Consecutive bit field data are packed at consecutive bits having the same
7703 storage unit, with regard to the type, beginning with the MSB and continuing
7706 If a field to be assigned lies over a bit field type boundary, its
7707 assignment is completed by aligning it with a boundary suitable for the
7710 When a bit field having a bit length of 0 is declared, it is forcibly
7711 assigned to the next storage unit.
7724 &x 00000000 00000000 00000000 00000000
7727 &x+4 00000000 00000000 00000000 00000000
7730 &x+8 00000000 00000000 00000000 00000000
7733 &x+12 00000000 00000000 00000000 00000000
7739 frv_adjust_field_align (tree field, int computed)
7741 /* Make sure that the bitfield is not wider than the type. */
7742 if (DECL_BIT_FIELD (field)
7743 && !DECL_ARTIFICIAL (field))
7745 tree parent = DECL_CONTEXT (field);
7746 tree prev = NULL_TREE;
7749 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7751 if (TREE_CODE (cur) != FIELD_DECL)
7760 /* If this isn't a :0 field and if the previous element is a bitfield
7761 also, see if the type is different, if so, we will need to align the
7762 bit-field to the next boundary. */
7764 && ! DECL_PACKED (field)
7765 && ! integer_zerop (DECL_SIZE (field))
7766 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7768 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7769 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7770 computed = (prev_align > cur_align) ? prev_align : cur_align;
7778 /* A C expression that is nonzero if it is permissible to store a value of mode
7779 MODE in hard register number REGNO (or in several registers starting with
7780 that one). For a machine where all registers are equivalent, a suitable
7783 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7785 It is not necessary for this macro to check for the numbers of fixed
7786 registers, because the allocation mechanism considers them to be always
7789 On some machines, double-precision values must be kept in even/odd register
7790 pairs. The way to implement that is to define this macro to reject odd
7791 register numbers for such modes.
7793 The minimum requirement for a mode to be OK in a register is that the
7794 `movMODE' instruction pattern support moves between the register and any
7795 other hard register for which the mode is OK; and that moving a value into
7796 the register and back out not alter it.
7798 Since the same instruction used to move `SImode' will work for all narrower
7799 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7800 to distinguish between these modes, provided you define patterns `movhi',
7801 etc., to take advantage of this. This is useful because of the interaction
7802 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7803 all integer modes to be tieable.
7805 Many machines have special registers for floating point arithmetic. Often
7806 people assume that floating point machine modes are allowed only in floating
7807 point registers. This is not true. Any registers that can hold integers
7808 can safely *hold* a floating point machine mode, whether or not floating
7809 arithmetic can be done on it in those registers. Integer move instructions
7810 can be used to move the values.
7812 On some machines, though, the converse is true: fixed-point machine modes
7813 may not go in floating registers. This is true if the floating registers
7814 normalize any value stored in them, because storing a non-floating value
7815 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7816 fixed-point machine modes in floating registers. But if the floating
7817 registers do not automatically normalize, if you can store any bit pattern
7818 in one and retrieve it unchanged without a trap, then any machine mode may
7819 go in a floating register, so you can define this macro to say so.
7821 The primary significance of special floating registers is rather that they
7822 are the registers acceptable in floating point arithmetic instructions.
7823 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7824 writing the proper constraints for those instructions.
7826 On some machines, the floating registers are especially slow to access, so
7827 that it is better to store a value in a stack frame than in such a register
7828 if floating point arithmetic is not being done. As long as the floating
7829 registers are not in class `GENERAL_REGS', they will not be used unless some
7830 pattern's constraint asks for one. */
7833 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
7843 return ICC_P (regno) || GPR_P (regno);
7846 return CR_P (regno) || GPR_P (regno);
7849 return FCC_P (regno) || GPR_P (regno);
7855 /* Set BASE to the first register in REGNO's class. Set MASK to the
7856 bits that must be clear in (REGNO - BASE) for the register to be
7858 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7862 /* ACCGs store one byte. Two-byte quantities must start in
7863 even-numbered registers, four-byte ones in registers whose
7864 numbers are divisible by four, and so on. */
7866 mask = GET_MODE_SIZE (mode) - 1;
7870 /* The other registers store one word. */
7871 if (GPR_P (regno) || regno == AP_FIRST)
7874 else if (FPR_P (regno))
7877 else if (ACC_P (regno))
7880 else if (SPR_P (regno))
7881 return mode == SImode;
7883 /* Fill in the table. */
7887 /* Anything smaller than an SI is OK in any word-sized register. */
7888 if (GET_MODE_SIZE (mode) < 4)
7891 mask = (GET_MODE_SIZE (mode) / 4) - 1;
7893 return (((regno - base) & mask) == 0);
7900 /* A C expression for the number of consecutive hard registers, starting at
7901 register number REGNO, required to hold a value of mode MODE.
7903 On a machine where all registers are exactly one word, a suitable definition
7906 #define HARD_REGNO_NREGS(REGNO, MODE) \
7907 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
7908 / UNITS_PER_WORD)) */
7910 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
7911 that we can build the appropriate instructions to properly reload the
7912 values. Also, make the byte-sized accumulator guards use one guard
7916 frv_hard_regno_nregs (int regno, enum machine_mode mode)
7919 return GET_MODE_SIZE (mode);
7921 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7925 /* A C expression for the maximum number of consecutive registers of
7926 class CLASS needed to hold a value of mode MODE.
7928 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
7929 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
7930 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
7932 This macro helps control the handling of multiple-word values in
7935 This declaration is required. */
7938 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
7940 if (class == ACCG_REGS)
7941 /* An N-byte value requires N accumulator guards. */
7942 return GET_MODE_SIZE (mode);
7944 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7948 /* A C expression that is nonzero if X is a legitimate constant for an
7949 immediate operand on the target machine. You can assume that X satisfies
7950 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
7951 definition for this macro on machines where anything `CONSTANT_P' is valid. */
7954 frv_legitimate_constant_p (rtx x)
7956 enum machine_mode mode = GET_MODE (x);
7958 /* frv_cannot_force_const_mem always returns true for FDPIC. This
7959 means that the move expanders will be expected to deal with most
7960 kinds of constant, regardless of what we return here.
7962 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
7963 a constant can be entered into reg_equiv_constant[]. If we return true,
7964 reload can create new instances of the constant whenever it likes.
7966 The idea is therefore to accept as many constants as possible (to give
7967 reload more freedom) while rejecting constants that can only be created
7968 at certain times. In particular, anything with a symbolic component will
7969 require use of the pseudo FDPIC register, which is only available before
7972 return LEGITIMATE_PIC_OPERAND_P (x);
7974 /* All of the integer constants are ok. */
7975 if (GET_CODE (x) != CONST_DOUBLE)
7978 /* double integer constants are ok. */
7979 if (mode == VOIDmode || mode == DImode)
7982 /* 0 is always ok. */
7983 if (x == CONST0_RTX (mode))
7986 /* If floating point is just emulated, allow any constant, since it will be
7987 constructed in the GPRs. */
7988 if (!TARGET_HAS_FPRS)
7991 if (mode == DFmode && !TARGET_DOUBLE)
7994 /* Otherwise store the constant away and do a load. */
7998 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
7999 CC_NZ for comparisons against zero in which a single Z or N flag test
8000 is enough, CC_UNS for other unsigned comparisons, and CC for other
8001 signed comparisons. */
8004 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
8006 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
8015 return y == const0_rtx ? CC_NZmode : CCmode;
8021 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
8028 /* A C expression for the cost of moving data from a register in class FROM to
8029 one in class TO. The classes are expressed using the enumeration values
8030 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8031 interpreted relative to that.
8033 It is not required that the cost always equal 2 when FROM is the same as TO;
8034 on some machines it is expensive to move between registers if they are not
8037 If reload sees an insn consisting of a single `set' between two hard
8038 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8039 value of 2, reload does not check to ensure that the constraints of the insn
8040 are met. Setting a cost of other than 2 will allow reload to verify that
8041 the constraints are met. You should do this if the `movM' pattern's
8042 constraints do not allow such copying. */
8044 #define HIGH_COST 40
8045 #define MEDIUM_COST 3
8049 frv_register_move_cost (enum reg_class from, enum reg_class to)
8133 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8134 use ".picptr" to generate safe relocations for PIC code. We also
8135 need a fixup entry for aligned (non-debugging) code. */
8138 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
8140 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
8142 if (GET_CODE (value) == CONST
8143 || GET_CODE (value) == SYMBOL_REF
8144 || GET_CODE (value) == LABEL_REF)
8146 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
8147 && SYMBOL_REF_FUNCTION_P (value))
8149 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
8150 output_addr_const (asm_out_file, value);
8151 fputs (")\n", asm_out_file);
8154 else if (TARGET_FDPIC && GET_CODE (value) == CONST
8155 && frv_function_symbol_referenced_p (value))
8157 if (aligned_p && !TARGET_FDPIC)
8159 static int label_num = 0;
8163 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8164 p = (* targetm.strip_name_encoding) (buf);
8166 fprintf (asm_out_file, "%s:\n", p);
8167 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8168 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8169 fprintf (asm_out_file, "\t.previous\n");
8171 assemble_integer_with_op ("\t.picptr\t", value);
8176 /* We've set the unaligned SI op to NULL, so we always have to
8177 handle the unaligned case here. */
8178 assemble_integer_with_op ("\t.4byte\t", value);
8182 return default_assemble_integer (value, size, aligned_p);
8185 /* Function to set up the backend function structure. */
8187 static struct machine_function *
8188 frv_init_machine_status (void)
8190 return ggc_alloc_cleared (sizeof (struct machine_function));
8193 /* Implement TARGET_SCHED_ISSUE_RATE. */
8196 frv_issue_rate (void)
8201 switch (frv_cpu_type)
8205 case FRV_CPU_SIMPLE:
8213 case FRV_CPU_GENERIC:
8215 case FRV_CPU_TOMCAT:
8223 /* A for_each_rtx callback. If X refers to an accumulator, return
8224 ACC_GROUP_ODD if the bit 2 of the register number is set and
8225 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
8229 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
8233 if (ACC_P (REGNO (*x)))
8234 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8235 if (ACCG_P (REGNO (*x)))
8236 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8241 /* Return the value of INSN's acc_group attribute. */
8244 frv_acc_group (rtx insn)
8246 /* This distinction only applies to the FR550 packing constraints. */
8247 if (frv_cpu_type != FRV_CPU_FR550)
8248 return ACC_GROUP_NONE;
8249 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
8252 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
8253 INSN will try to claim first. Since this value depends only on the
8254 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
8257 frv_insn_unit (rtx insn)
8259 enum attr_type type;
8261 type = get_attr_type (insn);
8262 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
8264 /* We haven't seen this type of instruction before. */
8268 /* Issue the instruction on its own to see which unit it prefers. */
8269 state = alloca (state_size ());
8270 state_reset (state);
8271 state_transition (state, insn);
8273 /* Find out which unit was taken. */
8274 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
8275 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
8278 if (unit == ARRAY_SIZE (frv_unit_codes))
8281 frv_type_to_unit[type] = unit;
8283 return frv_type_to_unit[type];
8286 /* Return true if INSN issues to a branch unit. */
8289 frv_issues_to_branch_unit_p (rtx insn)
8291 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
8294 /* The current state of the packing pass, implemented by frv_pack_insns. */
8296 /* The state of the pipeline DFA. */
8299 /* Which hardware registers are set within the current packet,
8300 and the conditions under which they are set. */
8301 regstate_t regstate[FIRST_PSEUDO_REGISTER];
8303 /* The memory locations that have been modified so far in this
8304 packet. MEM is the memref and COND is the regstate_t condition
8305 under which it is set. */
8311 /* The number of valid entries in MEMS. The value is larger than
8312 ARRAY_SIZE (mems) if there were too many mems to record. */
8313 unsigned int num_mems;
8315 /* The maximum number of instructions that can be packed together. */
8316 unsigned int issue_rate;
8318 /* The instructions in the packet, partitioned into groups. */
8319 struct frv_packet_group {
8320 /* How many instructions in the packet belong to this group. */
8321 unsigned int num_insns;
8323 /* A list of the instructions that belong to this group, in the order
8324 they appear in the rtl stream. */
8325 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8327 /* The contents of INSNS after they have been sorted into the correct
8328 assembly-language order. Element X issues to unit X. The list may
8329 contain extra nops. */
8330 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
8332 /* The member of frv_nops[] to use in sorted[]. */
8334 } groups[NUM_GROUPS];
8336 /* The instructions that make up the current packet. */
8337 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8338 unsigned int num_insns;
8341 /* Return the regstate_t flags for the given COND_EXEC condition.
8342 Abort if the condition isn't in the right form. */
8345 frv_cond_flags (rtx cond)
8347 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8348 && GET_CODE (XEXP (cond, 0)) == REG
8349 && CR_P (REGNO (XEXP (cond, 0)))
8350 && XEXP (cond, 1) == const0_rtx)
8351 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8352 | (GET_CODE (cond) == NE
8354 : REGSTATE_IF_FALSE));
8359 /* Return true if something accessed under condition COND2 can
8360 conflict with something written under condition COND1. */
8363 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
8365 /* If either reference was unconditional, we have a conflict. */
8366 if ((cond1 & REGSTATE_IF_EITHER) == 0
8367 || (cond2 & REGSTATE_IF_EITHER) == 0)
8370 /* The references might conflict if they were controlled by
8372 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
8375 /* They definitely conflict if they are controlled by the
8377 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
8384 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
8385 the current packet. DATA points to a regstate_t that describes the
8386 condition under which *X might be set or used. */
8389 frv_registers_conflict_p_1 (rtx *x, void *data)
8391 unsigned int regno, i;
8394 cond = *(regstate_t *) data;
8396 if (GET_CODE (*x) == REG)
8397 FOR_EACH_REGNO (regno, *x)
8398 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
8399 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
8402 if (GET_CODE (*x) == MEM)
8404 /* If we ran out of memory slots, assume a conflict. */
8405 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
8408 /* Check for output or true dependencies with earlier MEMs. */
8409 for (i = 0; i < frv_packet.num_mems; i++)
8410 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
8412 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
8416 if (output_dependence (frv_packet.mems[i].mem, *x))
8421 /* The return values of calls aren't significant: they describe
8422 the effect of the call as a whole, not of the insn itself. */
8423 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
8425 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
8430 /* Check subexpressions. */
8435 /* Return true if something in X might depend on an instruction
8436 in the current packet. */
8439 frv_registers_conflict_p (rtx x)
8444 if (GET_CODE (x) == COND_EXEC)
8446 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
8449 flags |= frv_cond_flags (XEXP (x, 0));
8452 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
8456 /* A note_stores callback. DATA points to the regstate_t condition
8457 under which X is modified. Update FRV_PACKET accordingly. */
8460 frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8464 if (GET_CODE (x) == REG)
8465 FOR_EACH_REGNO (regno, x)
8466 frv_packet.regstate[regno] |= *(regstate_t *) data;
8468 if (GET_CODE (x) == MEM)
8470 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
8472 frv_packet.mems[frv_packet.num_mems].mem = x;
8473 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
8475 frv_packet.num_mems++;
8480 /* Update the register state information for an instruction whose
8484 frv_registers_update (rtx x)
8488 flags = REGSTATE_MODIFIED;
8489 if (GET_CODE (x) == COND_EXEC)
8491 flags |= frv_cond_flags (XEXP (x, 0));
8494 note_stores (x, frv_registers_update_1, &flags);
8498 /* Initialize frv_packet for the start of a new packet. */
8501 frv_start_packet (void)
8503 enum frv_insn_group group;
8505 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
8506 frv_packet.num_mems = 0;
8507 frv_packet.num_insns = 0;
8508 for (group = 0; group < NUM_GROUPS; group++)
8509 frv_packet.groups[group].num_insns = 0;
8513 /* Likewise for the start of a new basic block. */
8516 frv_start_packet_block (void)
8518 state_reset (frv_packet.dfa_state);
8519 frv_start_packet ();
8523 /* Finish the current packet, if any, and start a new one. Call
8524 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
8527 frv_finish_packet (void (*handle_packet) (void))
8529 if (frv_packet.num_insns > 0)
8532 state_transition (frv_packet.dfa_state, 0);
8533 frv_start_packet ();
8538 /* Return true if INSN can be added to the current packet. Update
8539 the DFA state on success. */
8542 frv_pack_insn_p (rtx insn)
8544 /* See if the packet is already as long as it can be. */
8545 if (frv_packet.num_insns == frv_packet.issue_rate)
8548 /* If the scheduler thought that an instruction should start a packet,
8549 it's usually a good idea to believe it. It knows much more about
8550 the latencies than we do.
8552 There are some exceptions though:
8554 - Conditional instructions are scheduled on the assumption that
8555 they will be executed. This is usually a good thing, since it
8556 tends to avoid unnecessary stalls in the conditional code.
8557 But we want to pack conditional instructions as tightly as
8558 possible, in order to optimize the case where they aren't
8561 - The scheduler will always put branches on their own, even
8562 if there's no real dependency.
8564 - There's no point putting a call in its own packet unless
8566 if (frv_packet.num_insns > 0
8567 && GET_CODE (insn) == INSN
8568 && GET_MODE (insn) == TImode
8569 && GET_CODE (PATTERN (insn)) != COND_EXEC)
8572 /* Check for register conflicts. Don't do this for setlo since any
8573 conflict will be with the partnering sethi, with which it can
8575 if (get_attr_type (insn) != TYPE_SETLO)
8576 if (frv_registers_conflict_p (PATTERN (insn)))
8579 return state_transition (frv_packet.dfa_state, insn) < 0;
8583 /* Add instruction INSN to the current packet. */
8586 frv_add_insn_to_packet (rtx insn)
8588 struct frv_packet_group *packet_group;
8590 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8591 packet_group->insns[packet_group->num_insns++] = insn;
8592 frv_packet.insns[frv_packet.num_insns++] = insn;
8594 frv_registers_update (PATTERN (insn));
8598 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
8599 packet ends in a branch or call, insert the nop before it, otherwise
8603 frv_insert_nop_in_packet (rtx insn)
8605 struct frv_packet_group *packet_group;
8608 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8609 last = frv_packet.insns[frv_packet.num_insns - 1];
8610 if (GET_CODE (last) != INSN)
8612 insn = emit_insn_before (PATTERN (insn), last);
8613 frv_packet.insns[frv_packet.num_insns - 1] = insn;
8614 frv_packet.insns[frv_packet.num_insns++] = last;
8618 insn = emit_insn_after (PATTERN (insn), last);
8619 frv_packet.insns[frv_packet.num_insns++] = insn;
8621 packet_group->insns[packet_group->num_insns++] = insn;
8625 /* If packing is enabled, divide the instructions into packets and
8626 return true. Call HANDLE_PACKET for each complete packet. */
8629 frv_for_each_packet (void (*handle_packet) (void))
8631 rtx insn, next_insn;
8633 frv_packet.issue_rate = frv_issue_rate ();
8635 /* Early exit if we don't want to pack insns. */
8637 || !flag_schedule_insns_after_reload
8638 || TARGET_NO_VLIW_BRANCH
8639 || frv_packet.issue_rate == 1)
8642 /* Set up the initial packing state. */
8644 frv_packet.dfa_state = alloca (state_size ());
8646 frv_start_packet_block ();
8647 for (insn = get_insns (); insn != 0; insn = next_insn)
8652 code = GET_CODE (insn);
8653 next_insn = NEXT_INSN (insn);
8655 if (code == CODE_LABEL)
8657 frv_finish_packet (handle_packet);
8658 frv_start_packet_block ();
8662 switch (GET_CODE (PATTERN (insn)))
8671 /* Calls mustn't be packed on a TOMCAT. */
8672 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
8673 frv_finish_packet (handle_packet);
8675 /* Since the last instruction in a packet determines the EH
8676 region, any exception-throwing instruction must come at
8677 the end of reordered packet. Insns that issue to a
8678 branch unit are bound to come last; for others it's
8679 too hard to predict. */
8680 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
8681 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
8682 frv_finish_packet (handle_packet);
8684 /* Finish the current packet if we can't add INSN to it.
8685 Simulate cycles until INSN is ready to issue. */
8686 if (!frv_pack_insn_p (insn))
8688 frv_finish_packet (handle_packet);
8689 while (!frv_pack_insn_p (insn))
8690 state_transition (frv_packet.dfa_state, 0);
8693 /* Add the instruction to the packet. */
8694 frv_add_insn_to_packet (insn);
8696 /* Calls and jumps end a packet, as do insns that throw
8698 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
8699 frv_finish_packet (handle_packet);
8703 frv_finish_packet (handle_packet);
8708 /* Subroutine of frv_sort_insn_group. We are trying to sort
8709 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
8710 language order. We have already picked a new position for
8711 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
8712 These instructions will occupy elements [0, LOWER_SLOT) and
8713 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
8714 the DFA state after issuing these instructions.
8716 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
8717 of the unused instructions. Return true if one such permutation gives
8718 a valid ordering, leaving the successful permutation in sorted[].
8719 Do not modify sorted[] until a valid permutation is found. */
8722 frv_sort_insn_group_1 (enum frv_insn_group group,
8723 unsigned int lower_slot, unsigned int upper_slot,
8724 unsigned int issued, unsigned int num_insns,
8727 struct frv_packet_group *packet_group;
8733 /* Early success if we've filled all the slots. */
8734 if (lower_slot == upper_slot)
8737 packet_group = &frv_packet.groups[group];
8738 dfa_size = state_size ();
8739 test_state = alloca (dfa_size);
8741 /* Try issuing each unused instruction. */
8742 for (i = num_insns - 1; i + 1 != 0; i--)
8743 if (~issued & (1 << i))
8745 insn = packet_group->sorted[i];
8746 memcpy (test_state, state, dfa_size);
8747 if (state_transition (test_state, insn) < 0
8748 && cpu_unit_reservation_p (test_state,
8749 NTH_UNIT (group, upper_slot - 1))
8750 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
8751 issued | (1 << i), num_insns,
8754 packet_group->sorted[upper_slot - 1] = insn;
8762 /* Compare two instructions by their frv_insn_unit. */
8765 frv_compare_insns (const void *first, const void *second)
8767 const rtx *insn1 = first, *insn2 = second;
8768 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
8771 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
8772 and sort it into assembly language order. See frv.md for a description of
8776 frv_sort_insn_group (enum frv_insn_group group)
8778 struct frv_packet_group *packet_group;
8779 unsigned int first, i, nop, max_unit, num_slots;
8780 state_t state, test_state;
8783 packet_group = &frv_packet.groups[group];
8785 /* Assume no nop is needed. */
8786 packet_group->nop = 0;
8788 if (packet_group->num_insns == 0)
8791 /* Copy insns[] to sorted[]. */
8792 memcpy (packet_group->sorted, packet_group->insns,
8793 sizeof (rtx) * packet_group->num_insns);
8795 /* Sort sorted[] by the unit that each insn tries to take first. */
8796 if (packet_group->num_insns > 1)
8797 qsort (packet_group->sorted, packet_group->num_insns,
8798 sizeof (rtx), frv_compare_insns);
8800 /* That's always enough for branch and control insns. */
8801 if (group == GROUP_B || group == GROUP_C)
8804 dfa_size = state_size ();
8805 state = alloca (dfa_size);
8806 test_state = alloca (dfa_size);
8808 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
8809 consecutively and such that the DFA takes unit X when sorted[X]
8810 is added. Set STATE to the new DFA state. */
8811 state_reset (test_state);
8812 for (first = 0; first < packet_group->num_insns; first++)
8814 memcpy (state, test_state, dfa_size);
8815 if (state_transition (test_state, packet_group->sorted[first]) >= 0
8816 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
8820 /* If all the instructions issued in ascending order, we're done. */
8821 if (first == packet_group->num_insns)
8824 /* Add nops to the end of sorted[] and try each permutation until
8825 we find one that works. */
8826 for (nop = 0; nop < frv_num_nops; nop++)
8828 max_unit = frv_insn_unit (frv_nops[nop]);
8829 if (frv_unit_groups[max_unit] == group)
8831 packet_group->nop = frv_nops[nop];
8832 num_slots = UNIT_NUMBER (max_unit) + 1;
8833 for (i = packet_group->num_insns; i < num_slots; i++)
8834 packet_group->sorted[i] = frv_nops[nop];
8835 if (frv_sort_insn_group_1 (group, first, num_slots,
8836 (1 << first) - 1, num_slots, state))
8843 /* Sort the current packet into assembly-language order. Set packing
8844 flags as appropriate. */
8847 frv_reorder_packet (void)
8849 unsigned int cursor[NUM_GROUPS];
8850 rtx insns[ARRAY_SIZE (frv_unit_groups)];
8851 unsigned int unit, to, from;
8852 enum frv_insn_group group;
8853 struct frv_packet_group *packet_group;
8855 /* First sort each group individually. */
8856 for (group = 0; group < NUM_GROUPS; group++)
8859 frv_sort_insn_group (group);
8862 /* Go through the unit template and try add an instruction from
8863 that unit's group. */
8865 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
8867 group = frv_unit_groups[unit];
8868 packet_group = &frv_packet.groups[group];
8869 if (cursor[group] < packet_group->num_insns)
8871 /* frv_reorg should have added nops for us. */
8872 if (packet_group->sorted[cursor[group]] == packet_group->nop)
8874 insns[to++] = packet_group->sorted[cursor[group]++];
8878 if (to != frv_packet.num_insns)
8881 /* Clear the last instruction's packing flag, thus marking the end of
8882 a packet. Reorder the other instructions relative to it. */
8883 CLEAR_PACKING_FLAG (insns[to - 1]);
8884 for (from = 0; from < to - 1; from++)
8886 remove_insn (insns[from]);
8887 add_insn_before (insns[from], insns[to - 1]);
8888 SET_PACKING_FLAG (insns[from]);
8893 /* Divide instructions into packets. Reorder the contents of each
8894 packet so that they are in the correct assembly-language order.
8896 Since this pass can change the raw meaning of the rtl stream, it must
8897 only be called at the last minute, just before the instructions are
8901 frv_pack_insns (void)
8903 if (frv_for_each_packet (frv_reorder_packet))
8904 frv_insn_packing_flag = 0;
8906 frv_insn_packing_flag = -1;
8909 /* See whether we need to add nops to group GROUP in order to
8910 make a valid packet. */
8913 frv_fill_unused_units (enum frv_insn_group group)
8915 unsigned int non_nops, nops, i;
8916 struct frv_packet_group *packet_group;
8918 packet_group = &frv_packet.groups[group];
8920 /* Sort the instructions into assembly-language order.
8921 Use nops to fill slots that are otherwise unused. */
8922 frv_sort_insn_group (group);
8924 /* See how many nops are needed before the final useful instruction. */
8926 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
8927 while (packet_group->sorted[i++] == packet_group->nop)
8930 /* Insert that many nops into the instruction stream. */
8932 frv_insert_nop_in_packet (packet_group->nop);
8935 /* Used by frv_reorg to keep track of the current packet's address. */
8936 static unsigned int frv_packet_address;
8938 /* If the current packet falls through to a label, try to pad the packet
8939 with nops in order to fit the label's alignment requirements. */
8942 frv_align_label (void)
8944 unsigned int alignment, target, nop;
8945 rtx x, last, barrier, label;
8947 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8948 maximum alignment of that packet, LABEL to the last label between
8949 the packets, and BARRIER to the last barrier. */
8950 last = frv_packet.insns[frv_packet.num_insns - 1];
8951 label = barrier = 0;
8953 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8957 unsigned int subalign = 1 << label_to_alignment (x);
8958 alignment = MAX (alignment, subalign);
8965 /* If -malign-labels, and the packet falls through to an unaligned
8966 label, try introducing a nop to align that label to 8 bytes. */
8967 if (TARGET_ALIGN_LABELS
8970 && frv_packet.num_insns < frv_packet.issue_rate)
8971 alignment = MAX (alignment, 8);
8973 /* Advance the address to the end of the current packet. */
8974 frv_packet_address += frv_packet.num_insns * 4;
8976 /* Work out the target address, after alignment. */
8977 target = (frv_packet_address + alignment - 1) & -alignment;
8979 /* If the packet falls through to the label, try to find an efficient
8980 padding sequence. */
8983 /* First try adding nops to the current packet. */
8984 for (nop = 0; nop < frv_num_nops; nop++)
8985 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8987 frv_insert_nop_in_packet (frv_nops[nop]);
8988 frv_packet_address += 4;
8991 /* If we still haven't reached the target, add some new packets that
8992 contain only nops. If there are two types of nop, insert an
8993 alternating sequence of frv_nops[0] and frv_nops[1], which will
8994 lead to packets like:
9001 etc. Just emit frv_nops[0] if that's the only nop we have. */
9002 last = frv_packet.insns[frv_packet.num_insns - 1];
9004 while (frv_packet_address < target)
9006 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
9007 frv_packet_address += 4;
9008 if (frv_num_nops > 1)
9013 frv_packet_address = target;
9016 /* Subroutine of frv_reorg, called after each packet has been constructed
9020 frv_reorg_packet (void)
9022 frv_fill_unused_units (GROUP_I);
9023 frv_fill_unused_units (GROUP_FM);
9027 /* Add an instruction with pattern NOP to frv_nops[]. */
9030 frv_register_nop (rtx nop)
9032 nop = make_insn_raw (nop);
9033 NEXT_INSN (nop) = 0;
9034 PREV_INSN (nop) = 0;
9035 frv_nops[frv_num_nops++] = nop;
9038 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
9039 into packets and check whether we need to insert nops in order to
9040 fulfill the processor's issue requirements. Also, if the user has
9041 requested a certain alignment for a label, try to meet that alignment
9042 by inserting nops in the previous packet. */
9048 frv_register_nop (gen_nop ());
9050 frv_register_nop (gen_mnop ());
9051 if (TARGET_HARD_FLOAT)
9052 frv_register_nop (gen_fnop ());
9054 /* Estimate the length of each branch. Although this may change after
9055 we've inserted nops, it will only do so in big functions. */
9056 shorten_branches (get_insns ());
9058 frv_packet_address = 0;
9059 frv_for_each_packet (frv_reorg_packet);
9062 #define def_builtin(name, type, code) \
9063 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
9065 struct builtin_description
9067 enum insn_code icode;
9069 enum frv_builtins code;
9070 enum rtx_code comparison;
9074 /* Media intrinsics that take a single, constant argument. */
9076 static struct builtin_description bdesc_set[] =
9078 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
9081 /* Media intrinsics that take just one argument. */
9083 static struct builtin_description bdesc_1arg[] =
9085 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
9086 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
9087 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
9088 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
9089 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
9090 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
9093 /* Media intrinsics that take two arguments. */
9095 static struct builtin_description bdesc_2arg[] =
9097 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
9098 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
9099 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
9100 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
9101 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
9102 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
9103 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
9104 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
9105 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
9106 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
9107 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
9108 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
9109 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
9110 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
9111 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
9112 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
9113 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
9114 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
9115 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
9116 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
9117 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
9118 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
9119 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
9120 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
9121 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
9122 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
9123 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
9124 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
9127 /* Integer intrinsics that take two arguments and have no return value. */
9129 static struct builtin_description bdesc_int_void2arg[] =
9131 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
9132 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
9133 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
9136 static struct builtin_description bdesc_prefetches[] =
9138 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
9139 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
9142 /* Media intrinsics that take two arguments, the first being an ACC number. */
9144 static struct builtin_description bdesc_cut[] =
9146 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
9147 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
9148 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
9151 /* Two-argument media intrinsics with an immediate second argument. */
9153 static struct builtin_description bdesc_2argimm[] =
9155 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
9156 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
9157 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
9158 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
9159 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
9160 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
9161 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
9162 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
9163 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
9164 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
9165 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
9166 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
9167 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
9168 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
9169 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
9170 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
9171 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
9174 /* Media intrinsics that take two arguments and return void, the first argument
9175 being a pointer to 4 words in memory. */
9177 static struct builtin_description bdesc_void2arg[] =
9179 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
9180 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
9183 /* Media intrinsics that take three arguments, the first being a const_int that
9184 denotes an accumulator, and that return void. */
9186 static struct builtin_description bdesc_void3arg[] =
9188 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
9189 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
9190 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
9191 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
9192 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
9193 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
9194 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
9195 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
9196 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
9197 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
9198 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
9199 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
9200 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
9201 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
9202 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
9203 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
9204 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
9205 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
9206 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
9207 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
9208 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
9209 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
9210 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
9211 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
9212 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
9215 /* Media intrinsics that take two accumulator numbers as argument and
9218 static struct builtin_description bdesc_voidacc[] =
9220 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
9221 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
9222 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
9223 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
9224 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
9225 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
9228 /* Initialize media builtins. */
9231 frv_init_builtins (void)
9233 tree endlink = void_list_node;
9234 tree accumulator = integer_type_node;
9235 tree integer = integer_type_node;
9236 tree voidt = void_type_node;
9237 tree uhalf = short_unsigned_type_node;
9238 tree sword1 = long_integer_type_node;
9239 tree uword1 = long_unsigned_type_node;
9240 tree sword2 = long_long_integer_type_node;
9241 tree uword2 = long_long_unsigned_type_node;
9242 tree uword4 = build_pointer_type (uword1);
9243 tree iacc = integer_type_node;
9245 #define UNARY(RET, T1) \
9246 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9248 #define BINARY(RET, T1, T2) \
9249 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9250 tree_cons (NULL_TREE, T2, endlink)))
9252 #define TRINARY(RET, T1, T2, T3) \
9253 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9254 tree_cons (NULL_TREE, T2, \
9255 tree_cons (NULL_TREE, T3, endlink))))
9257 tree void_ftype_void = build_function_type (voidt, endlink);
9259 tree void_ftype_acc = UNARY (voidt, accumulator);
9260 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9261 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9262 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9263 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9264 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9265 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9266 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9267 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9269 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9270 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9271 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9272 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9273 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9274 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9275 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9276 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9277 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9278 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9279 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9281 tree sw1_ftype_int = UNARY (sword1, integer);
9282 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9283 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9285 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9286 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9287 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9288 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9289 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9291 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9292 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
9293 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
9294 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
9295 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
9296 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
9297 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
9298 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
9299 tree sw2_ftype_iacc = UNARY (sword2, iacc);
9300 tree sw1_ftype_iacc = UNARY (sword1, iacc);
9301 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
9303 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9304 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9305 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9306 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9307 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9308 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9309 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9310 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9311 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9312 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9313 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9314 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9315 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9316 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9317 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9318 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9319 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9320 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9321 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9322 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9323 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9324 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9325 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9326 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9327 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9328 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9329 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9330 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9331 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9332 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9333 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9334 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9335 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9336 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9337 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9338 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9339 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9340 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9341 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9342 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9343 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9344 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9345 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9346 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9347 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9348 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9349 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9350 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9351 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9352 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9353 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9354 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9355 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9356 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9357 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9358 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9359 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9360 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9361 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9362 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9363 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9364 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9365 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9366 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9367 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9368 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9369 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9370 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9371 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9372 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9373 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9374 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9375 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9376 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9377 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9378 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9379 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9380 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9381 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9382 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9383 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9384 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9385 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9386 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9387 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
9388 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
9389 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
9390 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
9391 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
9392 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
9393 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
9394 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
9395 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
9396 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
9397 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
9398 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
9399 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
9400 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
9401 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
9402 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
9403 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
9404 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
9405 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
9406 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
9413 /* Set the names for various arithmetic operations according to the
9416 frv_init_libfuncs (void)
9418 set_optab_libfunc (smod_optab, SImode, "__modi");
9419 set_optab_libfunc (umod_optab, SImode, "__umodi");
9421 set_optab_libfunc (add_optab, DImode, "__addll");
9422 set_optab_libfunc (sub_optab, DImode, "__subll");
9423 set_optab_libfunc (smul_optab, DImode, "__mulll");
9424 set_optab_libfunc (sdiv_optab, DImode, "__divll");
9425 set_optab_libfunc (smod_optab, DImode, "__modll");
9426 set_optab_libfunc (umod_optab, DImode, "__umodll");
9427 set_optab_libfunc (and_optab, DImode, "__andll");
9428 set_optab_libfunc (ior_optab, DImode, "__orll");
9429 set_optab_libfunc (xor_optab, DImode, "__xorll");
9430 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
9432 set_optab_libfunc (add_optab, SFmode, "__addf");
9433 set_optab_libfunc (sub_optab, SFmode, "__subf");
9434 set_optab_libfunc (smul_optab, SFmode, "__mulf");
9435 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
9437 set_optab_libfunc (add_optab, DFmode, "__addd");
9438 set_optab_libfunc (sub_optab, DFmode, "__subd");
9439 set_optab_libfunc (smul_optab, DFmode, "__muld");
9440 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
9442 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
9443 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
9445 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
9446 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9447 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
9448 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9450 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
9451 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9452 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
9453 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9455 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
9456 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
9457 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
9458 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
9461 /* Convert an integer constant to an accumulator register. ICODE is the
9462 code of the target instruction, OPNUM is the number of the
9463 accumulator operand and OPVAL is the constant integer. Try both
9464 ACC and ACCG registers; only report an error if neither fit the
9468 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
9473 /* ACCs and ACCGs are implicity global registers if media intrinsics
9474 are being used. We set up this lazily to avoid creating lots of
9475 unnecessary call_insn rtl in non-media code. */
9476 for (i = 0; i <= ACC_MASK; i++)
9477 if ((i & ACC_MASK) == i)
9478 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
9480 if (GET_CODE (opval) != CONST_INT)
9482 error ("accumulator is not a constant integer");
9485 if ((INTVAL (opval) & ~ACC_MASK) != 0)
9487 error ("accumulator number is out of bounds");
9491 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9492 ACC_FIRST + INTVAL (opval));
9493 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9494 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9496 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9498 error ("inappropriate accumulator for %qs", insn_data[icode].name);
9504 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9507 static enum machine_mode
9508 frv_matching_accg_mode (enum machine_mode mode)
9526 /* Return the accumulator guard that should be paired with accumulator
9527 register ACC. The mode of the returned register is in the same
9528 class as ACC, but is four times smaller. */
9531 frv_matching_accg_for_acc (rtx acc)
9533 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9534 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9537 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9538 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9542 frv_read_argument (tree *arglistptr)
9544 tree next = TREE_VALUE (*arglistptr);
9545 *arglistptr = TREE_CHAIN (*arglistptr);
9546 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9549 /* Like frv_read_argument, but interpret the argument as the number
9550 of an IACC register and return a (reg:MODE ...) rtx for it. */
9553 frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr)
9558 op = frv_read_argument (arglistptr);
9559 if (GET_CODE (op) != CONST_INT
9561 || INTVAL (op) > IACC_LAST - IACC_FIRST
9562 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
9564 error ("invalid IACC argument");
9568 /* IACCs are implicity global registers. We set up this lazily to
9569 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
9571 regno = INTVAL (op) + IACC_FIRST;
9572 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
9573 global_regs[regno + i] = 1;
9575 return gen_rtx_REG (mode, regno);
9578 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9579 The instruction should require a constant operand of some sort. The
9580 function prints an error if OPVAL is not valid. */
9583 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
9585 if (GET_CODE (opval) != CONST_INT)
9587 error ("%qs expects a constant argument", insn_data[icode].name);
9590 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9592 error ("constant argument out of range for %qs", insn_data[icode].name);
9598 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9599 if it's not null, has the right mode, and satisfies operand 0's
9603 frv_legitimize_target (enum insn_code icode, rtx target)
9605 enum machine_mode mode = insn_data[icode].operand[0].mode;
9608 || GET_MODE (target) != mode
9609 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9610 return gen_reg_rtx (mode);
9615 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9616 check whether ARG satisfies the operand's constraints. If it doesn't,
9617 copy ARG to a temporary register and return that. Otherwise return ARG
9621 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
9623 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9625 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9628 return copy_to_mode_reg (mode, arg);
9631 /* Expand builtins that take a single, constant argument. At the moment,
9632 only MHDSETS falls into this category. */
9635 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
9638 rtx op0 = frv_read_argument (&arglist);
9640 if (! frv_check_constant_argument (icode, 1, op0))
9643 target = frv_legitimize_target (icode, target);
9644 pat = GEN_FCN (icode) (target, op0);
9652 /* Expand builtins that take one operand. */
9655 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
9658 rtx op0 = frv_read_argument (&arglist);
9660 target = frv_legitimize_target (icode, target);
9661 op0 = frv_legitimize_argument (icode, 1, op0);
9662 pat = GEN_FCN (icode) (target, op0);
9670 /* Expand builtins that take two operands. */
9673 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
9676 rtx op0 = frv_read_argument (&arglist);
9677 rtx op1 = frv_read_argument (&arglist);
9679 target = frv_legitimize_target (icode, target);
9680 op0 = frv_legitimize_argument (icode, 1, op0);
9681 op1 = frv_legitimize_argument (icode, 2, op1);
9682 pat = GEN_FCN (icode) (target, op0, op1);
9690 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9694 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
9697 rtx op0 = frv_read_argument (&arglist);
9698 rtx op1 = frv_read_argument (&arglist);
9701 target = frv_legitimize_target (icode, target);
9702 op0 = frv_int_to_acc (icode, 1, op0);
9706 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9708 if (! frv_check_constant_argument (icode, 2, op1))
9712 op1 = frv_legitimize_argument (icode, 2, op1);
9714 op2 = frv_matching_accg_for_acc (op0);
9715 pat = GEN_FCN (icode) (target, op0, op1, op2);
9723 /* Expand builtins that take two operands and the second is immediate. */
9726 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
9729 rtx op0 = frv_read_argument (&arglist);
9730 rtx op1 = frv_read_argument (&arglist);
9732 if (! frv_check_constant_argument (icode, 2, op1))
9735 target = frv_legitimize_target (icode, target);
9736 op0 = frv_legitimize_argument (icode, 1, op0);
9737 pat = GEN_FCN (icode) (target, op0, op1);
9745 /* Expand builtins that take two operands, the first operand being a pointer to
9746 ints and return void. */
9749 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
9752 rtx op0 = frv_read_argument (&arglist);
9753 rtx op1 = frv_read_argument (&arglist);
9754 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9757 if (GET_CODE (op0) != MEM)
9761 if (! offsettable_address_p (0, mode0, op0))
9763 reg = gen_reg_rtx (Pmode);
9764 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9767 op0 = gen_rtx_MEM (SImode, reg);
9770 addr = XEXP (op0, 0);
9771 if (! offsettable_address_p (0, mode0, addr))
9772 addr = copy_to_mode_reg (Pmode, op0);
9774 op0 = change_address (op0, V4SImode, addr);
9775 op1 = frv_legitimize_argument (icode, 1, op1);
9776 pat = GEN_FCN (icode) (op0, op1);
9784 /* Expand builtins that take two long operands and return void. */
9787 frv_expand_int_void2arg (enum insn_code icode, tree arglist)
9790 rtx op0 = frv_read_argument (&arglist);
9791 rtx op1 = frv_read_argument (&arglist);
9793 op0 = frv_legitimize_argument (icode, 1, op0);
9794 op1 = frv_legitimize_argument (icode, 1, op1);
9795 pat = GEN_FCN (icode) (op0, op1);
9803 /* Expand prefetch builtins. These take a single address as argument. */
9806 frv_expand_prefetches (enum insn_code icode, tree arglist)
9809 rtx op0 = frv_read_argument (&arglist);
9811 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9819 /* Expand builtins that take three operands and return void. The first
9820 argument must be a constant that describes a pair or quad accumulators. A
9821 fourth argument is created that is the accumulator guard register that
9822 corresponds to the accumulator. */
9825 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
9828 rtx op0 = frv_read_argument (&arglist);
9829 rtx op1 = frv_read_argument (&arglist);
9830 rtx op2 = frv_read_argument (&arglist);
9833 op0 = frv_int_to_acc (icode, 0, op0);
9837 op1 = frv_legitimize_argument (icode, 1, op1);
9838 op2 = frv_legitimize_argument (icode, 2, op2);
9839 op3 = frv_matching_accg_for_acc (op0);
9840 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9848 /* Expand builtins that perform accumulator-to-accumulator operations.
9849 These builtins take two accumulator numbers as argument and return
9853 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
9856 rtx op0 = frv_read_argument (&arglist);
9857 rtx op1 = frv_read_argument (&arglist);
9861 op0 = frv_int_to_acc (icode, 0, op0);
9865 op1 = frv_int_to_acc (icode, 1, op1);
9869 op2 = frv_matching_accg_for_acc (op0);
9870 op3 = frv_matching_accg_for_acc (op1);
9871 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9879 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9880 number as argument. */
9883 frv_expand_mclracc_builtin (tree arglist)
9885 enum insn_code icode = CODE_FOR_mclracc;
9887 rtx op0 = frv_read_argument (&arglist);
9889 op0 = frv_int_to_acc (icode, 0, op0);
9893 pat = GEN_FCN (icode) (op0);
9900 /* Expand builtins that take no arguments. */
9903 frv_expand_noargs_builtin (enum insn_code icode)
9905 rtx pat = GEN_FCN (icode) (const0_rtx);
9912 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9913 number or accumulator guard number as argument and return an SI integer. */
9916 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
9919 rtx target = gen_reg_rtx (SImode);
9920 rtx op0 = frv_read_argument (&arglist);
9922 op0 = frv_int_to_acc (icode, 1, op0);
9926 pat = GEN_FCN (icode) (target, op0);
9934 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9935 accumulator guard as their first argument and an SImode value as their
9939 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
9942 rtx op0 = frv_read_argument (&arglist);
9943 rtx op1 = frv_read_argument (&arglist);
9945 op0 = frv_int_to_acc (icode, 0, op0);
9949 op1 = frv_legitimize_argument (icode, 1, op1);
9950 pat = GEN_FCN (icode) (op0, op1);
9957 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9958 to move DImode values into and out of IACC0. */
9961 frv_split_iacc_move (rtx dest, rtx src)
9963 enum machine_mode inner;
9966 inner = GET_MODE (dest);
9967 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9968 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9969 simplify_gen_subreg (SImode, src, inner, i));
9972 /* Expand builtins. */
9975 frv_expand_builtin (tree exp,
9977 rtx subtarget ATTRIBUTE_UNUSED,
9978 enum machine_mode mode ATTRIBUTE_UNUSED,
9979 int ignore ATTRIBUTE_UNUSED)
9981 tree arglist = TREE_OPERAND (exp, 1);
9982 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9983 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9985 struct builtin_description *d;
9987 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9989 error ("media functions are not available unless -mmedia is used");
9995 case FRV_BUILTIN_MCOP1:
9996 case FRV_BUILTIN_MCOP2:
9997 case FRV_BUILTIN_MDUNPACKH:
9998 case FRV_BUILTIN_MBTOHE:
9999 if (! TARGET_MEDIA_REV1)
10001 error ("this media function is only available on the fr500");
10006 case FRV_BUILTIN_MQXMACHS:
10007 case FRV_BUILTIN_MQXMACXHS:
10008 case FRV_BUILTIN_MQMACXHS:
10009 case FRV_BUILTIN_MADDACCS:
10010 case FRV_BUILTIN_MSUBACCS:
10011 case FRV_BUILTIN_MASACCS:
10012 case FRV_BUILTIN_MDADDACCS:
10013 case FRV_BUILTIN_MDSUBACCS:
10014 case FRV_BUILTIN_MDASACCS:
10015 case FRV_BUILTIN_MABSHS:
10016 case FRV_BUILTIN_MDROTLI:
10017 case FRV_BUILTIN_MCPLHI:
10018 case FRV_BUILTIN_MCPLI:
10019 case FRV_BUILTIN_MDCUTSSI:
10020 case FRV_BUILTIN_MQSATHS:
10021 case FRV_BUILTIN_MHSETLOS:
10022 case FRV_BUILTIN_MHSETLOH:
10023 case FRV_BUILTIN_MHSETHIS:
10024 case FRV_BUILTIN_MHSETHIH:
10025 case FRV_BUILTIN_MHDSETS:
10026 case FRV_BUILTIN_MHDSETH:
10027 if (! TARGET_MEDIA_REV2)
10029 error ("this media function is only available on the fr400"
10035 case FRV_BUILTIN_SMASS:
10036 case FRV_BUILTIN_SMSSS:
10037 case FRV_BUILTIN_SMU:
10038 case FRV_BUILTIN_ADDSS:
10039 case FRV_BUILTIN_SUBSS:
10040 case FRV_BUILTIN_SLASS:
10041 case FRV_BUILTIN_SCUTSS:
10042 case FRV_BUILTIN_IACCreadll:
10043 case FRV_BUILTIN_IACCreadl:
10044 case FRV_BUILTIN_IACCsetll:
10045 case FRV_BUILTIN_IACCsetl:
10046 if (!TARGET_FR405_BUILTINS)
10048 error ("this builtin function is only available"
10049 " on the fr405 and fr450");
10054 case FRV_BUILTIN_PREFETCH:
10055 if (!TARGET_FR500_FR550_BUILTINS)
10057 error ("this builtin function is only available on the fr500"
10063 case FRV_BUILTIN_MQLCLRHS:
10064 case FRV_BUILTIN_MQLMTHS:
10065 case FRV_BUILTIN_MQSLLHI:
10066 case FRV_BUILTIN_MQSRAHI:
10067 if (!TARGET_MEDIA_FR450)
10069 error ("this builtin function is only available on the fr450");
10078 /* Expand unique builtins. */
10082 case FRV_BUILTIN_MTRAP:
10083 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
10085 case FRV_BUILTIN_MCLRACC:
10086 return frv_expand_mclracc_builtin (arglist);
10088 case FRV_BUILTIN_MCLRACCA:
10090 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
10092 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
10094 case FRV_BUILTIN_MRDACC:
10095 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
10097 case FRV_BUILTIN_MRDACCG:
10098 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
10100 case FRV_BUILTIN_MWTACC:
10101 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
10103 case FRV_BUILTIN_MWTACCG:
10104 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
10106 case FRV_BUILTIN_IACCreadll:
10108 rtx src = frv_read_iacc_argument (DImode, &arglist);
10109 if (target == 0 || !REG_P (target))
10110 target = gen_reg_rtx (DImode);
10111 frv_split_iacc_move (target, src);
10115 case FRV_BUILTIN_IACCreadl:
10116 return frv_read_iacc_argument (SImode, &arglist);
10118 case FRV_BUILTIN_IACCsetll:
10120 rtx dest = frv_read_iacc_argument (DImode, &arglist);
10121 rtx src = frv_read_argument (&arglist);
10122 frv_split_iacc_move (dest, force_reg (DImode, src));
10126 case FRV_BUILTIN_IACCsetl:
10128 rtx dest = frv_read_iacc_argument (SImode, &arglist);
10129 rtx src = frv_read_argument (&arglist);
10130 emit_move_insn (dest, force_reg (SImode, src));
10138 /* Expand groups of builtins. */
10140 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
10141 if (d->code == fcode)
10142 return frv_expand_set_builtin (d->icode, arglist, target);
10144 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10145 if (d->code == fcode)
10146 return frv_expand_unop_builtin (d->icode, arglist, target);
10148 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10149 if (d->code == fcode)
10150 return frv_expand_binop_builtin (d->icode, arglist, target);
10152 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
10153 if (d->code == fcode)
10154 return frv_expand_cut_builtin (d->icode, arglist, target);
10156 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
10157 if (d->code == fcode)
10158 return frv_expand_binopimm_builtin (d->icode, arglist, target);
10160 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
10161 if (d->code == fcode)
10162 return frv_expand_voidbinop_builtin (d->icode, arglist);
10164 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
10165 if (d->code == fcode)
10166 return frv_expand_voidtriop_builtin (d->icode, arglist);
10168 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
10169 if (d->code == fcode)
10170 return frv_expand_voidaccop_builtin (d->icode, arglist);
10172 for (i = 0, d = bdesc_int_void2arg;
10173 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
10174 if (d->code == fcode)
10175 return frv_expand_int_void2arg (d->icode, arglist);
10177 for (i = 0, d = bdesc_prefetches;
10178 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
10179 if (d->code == fcode)
10180 return frv_expand_prefetches (d->icode, arglist);
10186 frv_in_small_data_p (tree decl)
10188 HOST_WIDE_INT size;
10191 /* Don't apply the -G flag to internal compiler structures. We
10192 should leave such structures in the main data section, partly
10193 for efficiency and partly because the size of some of them
10194 (such as C++ typeinfos) is not known until later. */
10195 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
10198 /* If we already know which section the decl should be in, see if
10199 it's a small data section. */
10200 section_name = DECL_SECTION_NAME (decl);
10203 if (TREE_CODE (section_name) != STRING_CST)
10205 if (frv_string_begins_with (section_name, ".sdata"))
10207 if (frv_string_begins_with (section_name, ".sbss"))
10212 size = int_size_in_bytes (TREE_TYPE (decl));
10213 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
10220 frv_rtx_costs (rtx x,
10221 int code ATTRIBUTE_UNUSED,
10222 int outer_code ATTRIBUTE_UNUSED,
10225 if (outer_code == MEM)
10227 /* Don't differentiate between memory addresses. All the ones
10228 we accept have equal cost. */
10229 *total = COSTS_N_INSNS (0);
10236 /* Make 12 bit integers really cheap. */
10237 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
10242 /* Fall through. */
10248 *total = COSTS_N_INSNS (2);
10262 if (GET_MODE (x) == SImode)
10263 *total = COSTS_N_INSNS (1);
10264 else if (GET_MODE (x) == DImode)
10265 *total = COSTS_N_INSNS (2);
10267 *total = COSTS_N_INSNS (3);
10271 if (GET_MODE (x) == SImode)
10272 *total = COSTS_N_INSNS (2);
10274 *total = COSTS_N_INSNS (6); /* guess */
10281 *total = COSTS_N_INSNS (18);
10285 *total = COSTS_N_INSNS (3);
10294 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10297 assemble_align (POINTER_SIZE);
10300 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10304 assemble_integer_with_op ("\t.picptr\t", symbol);
10308 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10311 assemble_align (POINTER_SIZE);
10314 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10318 assemble_integer_with_op ("\t.picptr\t", symbol);
10321 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10324 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
10325 int incoming ATTRIBUTE_UNUSED)
10327 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
10330 #include "gt-frv.h"