1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Return true if instruction INSN should be packed with the following
114 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
116 /* Set the value of PACKING_FLAG_P(INSN). */
117 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
118 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
120 /* Loop with REG set to each hard register in rtx X. */
121 #define FOR_EACH_REGNO(REG, X) \
122 for (REG = REGNO (X); \
123 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
126 /* Temporary register allocation support structure. */
127 typedef struct frv_tmp_reg_struct
129 HARD_REG_SET regs; /* possible registers to allocate */
130 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
134 /* Register state information for VLIW re-packing phase. */
135 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
136 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
137 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
138 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
140 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
142 typedef unsigned char regstate_t;
144 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
152 /* Information required by frv_frame_access. */
155 /* This field is FRV_LOAD if registers are to be loaded from the stack and
156 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
157 the move is being done by the prologue code while FRV_LOAD implies it
158 is being done by the epilogue. */
159 enum frv_stack_op op;
161 /* The base register to use when accessing the stack. This may be the
162 frame pointer, stack pointer, or a temporary. The choice of register
163 depends on which part of the frame is being accessed and how big the
167 /* The offset of BASE from the bottom of the current frame, in bytes. */
169 } frv_frame_accessor_t;
171 /* Define the information needed to generate branch and scc insns. This is
172 stored from the compare operation. */
176 /* Conditional execution support gathered together in one structure. */
179 /* Linked list of insns to add if the conditional execution conversion was
180 successful. Each link points to an EXPR_LIST which points to the pattern
181 of the insn to add, and the insn to be inserted before. */
182 rtx added_insns_list;
184 /* Identify which registers are safe to allocate for if conversions to
185 conditional execution. We keep the last allocated register in the
186 register classes between COND_EXEC statements. This will mean we allocate
187 different registers for each different COND_EXEC group if we can. This
188 might allow the scheduler to intermix two different COND_EXEC sections. */
189 frv_tmp_reg_t tmp_reg;
191 /* For nested IFs, identify which CC registers are used outside of setting
192 via a compare isnsn, and using via a check insn. This will allow us to
193 know if we can rewrite the register to use a different register that will
194 be paired with the CR register controlling the nested IF-THEN blocks. */
195 HARD_REG_SET nested_cc_ok_rewrite;
197 /* Temporary registers allocated to hold constants during conditional
199 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
201 /* Current number of temp registers available. */
202 int cur_scratch_regs;
204 /* Number of nested conditional execution blocks. */
205 int num_nested_cond_exec;
207 /* Map of insns that set up constants in scratch registers. */
208 bitmap scratch_insns_bitmap;
210 /* Conditional execution test register (CC0..CC7). */
213 /* Conditional execution compare register that is paired with cr_reg, so that
214 nested compares can be done. The csubcc and caddcc instructions don't
215 have enough bits to specify both a CC register to be set and a CR register
216 to do the test on, so the same bit number is used for both. Needless to
217 say, this is rather inconvenient for GCC. */
220 /* Extra CR registers used for &&, ||. */
224 /* Previous CR used in nested if, to make sure we are dealing with the same
225 nested if as the previous statement. */
226 rtx last_nested_if_cr;
230 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
232 /* Map register number to smallest register class. */
233 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
235 /* Map class letter into register class. */
236 enum reg_class reg_class_from_letter[256];
238 /* Cached value of frv_stack_info. */
239 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
242 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
244 /* Forward references */
246 static bool frv_handle_option (size_t, const char *, int);
247 static int frv_default_flags_for_cpu (void);
248 static int frv_string_begins_with (tree, const char *);
249 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
250 static void frv_print_operand_memory_reference_reg
252 static void frv_print_operand_memory_reference (FILE *, rtx, int);
253 static int frv_print_operand_jump_hint (rtx);
254 static const char *comparison_string (enum rtx_code, rtx);
255 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
256 static rtx single_set_pattern (rtx);
257 static int frv_function_contains_far_jump (void);
258 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
262 static rtx frv_frame_offset_rtx (int);
263 static rtx frv_frame_mem (enum machine_mode, rtx, int);
264 static rtx frv_dwarf_store (rtx, int);
265 static void frv_frame_insn (rtx, rtx);
266 static void frv_frame_access (frv_frame_accessor_t*,
268 static void frv_frame_access_multi (frv_frame_accessor_t*,
270 static void frv_frame_access_standard_regs (enum frv_stack_op,
272 static struct machine_function *frv_init_machine_status (void);
273 static rtx frv_int_to_acc (enum insn_code, int, rtx);
274 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
275 static rtx frv_read_argument (tree *);
276 static rtx frv_read_iacc_argument (enum machine_mode, tree *);
277 static int frv_check_constant_argument (enum insn_code, int, rtx);
278 static rtx frv_legitimize_target (enum insn_code, rtx);
279 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
280 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
281 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
282 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
283 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
284 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
285 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
286 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
287 static rtx frv_expand_int_void2arg (enum insn_code, tree);
288 static rtx frv_expand_prefetches (enum insn_code, tree);
289 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
290 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
291 static rtx frv_expand_mclracc_builtin (tree);
292 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
293 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
294 static rtx frv_expand_noargs_builtin (enum insn_code);
295 static void frv_split_iacc_move (rtx, rtx);
296 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
297 static int frv_clear_registers_used (rtx *, void *);
298 static void frv_ifcvt_add_insn (rtx, rtx, int);
299 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
300 static rtx frv_ifcvt_load_value (rtx, rtx);
301 static int frv_acc_group_1 (rtx *, void *);
302 static unsigned int frv_insn_unit (rtx);
303 static bool frv_issues_to_branch_unit_p (rtx);
304 static int frv_cond_flags (rtx);
305 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
306 static int frv_registers_conflict_p_1 (rtx *, void *);
307 static bool frv_registers_conflict_p (rtx);
308 static void frv_registers_update_1 (rtx, rtx, void *);
309 static void frv_registers_update (rtx);
310 static void frv_start_packet (void);
311 static void frv_start_packet_block (void);
312 static void frv_finish_packet (void (*) (void));
313 static bool frv_pack_insn_p (rtx);
314 static void frv_add_insn_to_packet (rtx);
315 static void frv_insert_nop_in_packet (rtx);
316 static bool frv_for_each_packet (void (*) (void));
317 static bool frv_sort_insn_group_1 (enum frv_insn_group,
318 unsigned int, unsigned int,
319 unsigned int, unsigned int,
321 static int frv_compare_insns (const void *, const void *);
322 static void frv_sort_insn_group (enum frv_insn_group);
323 static void frv_reorder_packet (void);
324 static void frv_fill_unused_units (enum frv_insn_group);
325 static void frv_align_label (void);
326 static void frv_reorg_packet (void);
327 static void frv_register_nop (rtx);
328 static void frv_reorg (void);
329 static void frv_pack_insns (void);
330 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
331 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
332 static bool frv_assemble_integer (rtx, unsigned, int);
333 static void frv_init_builtins (void);
334 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
335 static void frv_init_libfuncs (void);
336 static bool frv_in_small_data_p (tree);
337 static void frv_asm_output_mi_thunk
338 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
339 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
342 static rtx frv_expand_builtin_saveregs (void);
343 static bool frv_rtx_costs (rtx, int, int, int*);
344 static void frv_asm_out_constructor (rtx, int);
345 static void frv_asm_out_destructor (rtx, int);
346 static bool frv_function_symbol_referenced_p (rtx);
347 static bool frv_cannot_force_const_mem (rtx);
348 static const char *unspec_got_name (int);
349 static void frv_output_const_unspec (FILE *,
350 const struct frv_unspec *);
351 static bool frv_function_ok_for_sibcall (tree, tree);
352 static rtx frv_struct_value_rtx (tree, int);
353 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
354 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
356 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
359 /* Allow us to easily change the default for -malloc-cc. */
360 #ifndef DEFAULT_NO_ALLOC_CC
361 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
363 #define MASK_DEFAULT_ALLOC_CC 0
366 /* Initialize the GCC target structure. */
367 #undef TARGET_ASM_FUNCTION_PROLOGUE
368 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
369 #undef TARGET_ASM_FUNCTION_EPILOGUE
370 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
371 #undef TARGET_ASM_INTEGER
372 #define TARGET_ASM_INTEGER frv_assemble_integer
373 #undef TARGET_DEFAULT_TARGET_FLAGS
374 #define TARGET_DEFAULT_TARGET_FLAGS \
375 (MASK_DEFAULT_ALLOC_CC \
382 #undef TARGET_HANDLE_OPTION
383 #define TARGET_HANDLE_OPTION frv_handle_option
384 #undef TARGET_INIT_BUILTINS
385 #define TARGET_INIT_BUILTINS frv_init_builtins
386 #undef TARGET_EXPAND_BUILTIN
387 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
388 #undef TARGET_INIT_LIBFUNCS
389 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
390 #undef TARGET_IN_SMALL_DATA_P
391 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
392 #undef TARGET_RTX_COSTS
393 #define TARGET_RTX_COSTS frv_rtx_costs
394 #undef TARGET_ASM_CONSTRUCTOR
395 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
396 #undef TARGET_ASM_DESTRUCTOR
397 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
399 #undef TARGET_ASM_OUTPUT_MI_THUNK
400 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
401 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
402 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
404 #undef TARGET_SCHED_ISSUE_RATE
405 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
407 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
408 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
409 #undef TARGET_CANNOT_FORCE_CONST_MEM
410 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
412 #undef TARGET_HAVE_TLS
413 #define TARGET_HAVE_TLS HAVE_AS_TLS
415 #undef TARGET_STRUCT_VALUE_RTX
416 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
417 #undef TARGET_MUST_PASS_IN_STACK
418 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
419 #undef TARGET_PASS_BY_REFERENCE
420 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
421 #undef TARGET_ARG_PARTIAL_BYTES
422 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
424 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
425 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
426 #undef TARGET_SETUP_INCOMING_VARARGS
427 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
428 #undef TARGET_MACHINE_DEPENDENT_REORG
429 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
432 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
433 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
436 struct gcc_target targetm = TARGET_INITIALIZER;
438 #define FRV_SYMBOL_REF_TLS_P(RTX) \
439 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
442 /* Any function call that satisfies the machine-independent
443 requirements is eligible on FR-V. */
446 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
447 tree exp ATTRIBUTE_UNUSED)
452 /* Return true if SYMBOL is a small data symbol and relocation RELOC
453 can be used to access it directly in a load or store. */
455 static FRV_INLINE bool
456 frv_small_data_reloc_p (rtx symbol, int reloc)
458 return (GET_CODE (symbol) == SYMBOL_REF
459 && SYMBOL_REF_SMALL_P (symbol)
460 && (!TARGET_FDPIC || flag_pic == 1)
461 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
464 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
468 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
470 if (GET_CODE (x) == CONST)
474 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
476 unspec->offset += INTVAL (XEXP (x, 1));
479 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
481 unspec->symbol = XVECEXP (x, 0, 0);
482 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
484 if (unspec->offset == 0)
487 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
488 && unspec->offset > 0
489 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
496 /* Decide whether we can force certain constants to memory. If we
497 decide we can't, the caller should be able to cope with it in
500 We never allow constants to be forced into memory for TARGET_FDPIC.
501 This is necessary for several reasons:
503 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
504 target-independent code will try to force them into the constant
505 pool, thus leading to infinite recursion.
507 2. We can never introduce new constant pool references during reload.
508 Any such reference would require use of the pseudo FDPIC register.
510 3. We can't represent a constant added to a function pointer (which is
511 not the same as a pointer to a function+constant).
513 4. In many cases, it's more efficient to calculate the constant in-line. */
516 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
521 /* Implement TARGET_HANDLE_OPTION. */
524 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
529 if (strcmp (arg, "simple") == 0)
530 frv_cpu_type = FRV_CPU_SIMPLE;
531 else if (strcmp (arg, "tomcat") == 0)
532 frv_cpu_type = FRV_CPU_TOMCAT;
533 else if (strcmp (arg, "fr550") == 0)
534 frv_cpu_type = FRV_CPU_FR550;
535 else if (strcmp (arg, "fr500") == 0)
536 frv_cpu_type = FRV_CPU_FR500;
537 else if (strcmp (arg, "fr450") == 0)
538 frv_cpu_type = FRV_CPU_FR450;
539 else if (strcmp (arg, "fr405") == 0)
540 frv_cpu_type = FRV_CPU_FR405;
541 else if (strcmp (arg, "fr400") == 0)
542 frv_cpu_type = FRV_CPU_FR400;
543 else if (strcmp (arg, "fr300") == 0)
544 frv_cpu_type = FRV_CPU_FR300;
545 else if (strcmp (arg, "frv") == 0)
546 frv_cpu_type = FRV_CPU_GENERIC;
557 frv_default_flags_for_cpu (void)
559 switch (frv_cpu_type)
561 case FRV_CPU_GENERIC:
562 return MASK_DEFAULT_FRV;
565 return MASK_DEFAULT_FR550;
569 return MASK_DEFAULT_FR500;
572 return MASK_DEFAULT_FR450;
576 return MASK_DEFAULT_FR400;
580 return MASK_DEFAULT_SIMPLE;
587 /* Sometimes certain combinations of command options do not make
588 sense on a particular target machine. You can define a macro
589 `OVERRIDE_OPTIONS' to take account of this. This macro, if
590 defined, is executed once just after all the command options have
593 Don't use this macro to turn on various extra optimizations for
594 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
597 frv_override_options (void)
602 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
604 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
605 linker about linking pic and non-pic code. */
608 if (!flag_pic) /* -fPIC */
611 if (! g_switch_set) /* -G0 */
618 /* A C expression whose value is a register class containing hard
619 register REGNO. In general there is more than one such class;
620 choose a class which is "minimal", meaning that no smaller class
621 also contains the register. */
623 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
625 enum reg_class class;
629 int gpr_reg = regno - GPR_FIRST;
631 if (gpr_reg == GR8_REG)
634 else if (gpr_reg == GR9_REG)
637 else if (gpr_reg == GR14_REG)
638 class = FDPIC_FPTR_REGS;
640 else if (gpr_reg == FDPIC_REGNO)
643 else if ((gpr_reg & 3) == 0)
646 else if ((gpr_reg & 1) == 0)
653 else if (FPR_P (regno))
655 int fpr_reg = regno - GPR_FIRST;
656 if ((fpr_reg & 3) == 0)
657 class = QUAD_FPR_REGS;
659 else if ((fpr_reg & 1) == 0)
666 else if (regno == LR_REGNO)
669 else if (regno == LCR_REGNO)
672 else if (ICC_P (regno))
675 else if (FCC_P (regno))
678 else if (ICR_P (regno))
681 else if (FCR_P (regno))
684 else if (ACC_P (regno))
686 int r = regno - ACC_FIRST;
688 class = QUAD_ACC_REGS;
689 else if ((r & 1) == 0)
690 class = EVEN_ACC_REGS;
695 else if (ACCG_P (regno))
701 regno_reg_class[regno] = class;
704 /* Check for small data option */
706 g_switch_value = SDATA_DEFAULT_SIZE;
708 /* A C expression which defines the machine-dependent operand
709 constraint letters for register classes. If CHAR is such a
710 letter, the value should be the register class corresponding to
711 it. Otherwise, the value should be `NO_REGS'. The register
712 letter `r', corresponding to class `GENERAL_REGS', will not be
713 passed to this macro; you do not need to handle it.
715 The following letters are unavailable, due to being used as
720 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
721 'Q', 'R', 'S', 'T', 'U'
723 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
725 for (i = 0; i < 256; i++)
726 reg_class_from_letter[i] = NO_REGS;
728 reg_class_from_letter['a'] = ACC_REGS;
729 reg_class_from_letter['b'] = EVEN_ACC_REGS;
730 reg_class_from_letter['c'] = CC_REGS;
731 reg_class_from_letter['d'] = GPR_REGS;
732 reg_class_from_letter['e'] = EVEN_REGS;
733 reg_class_from_letter['f'] = FPR_REGS;
734 reg_class_from_letter['h'] = FEVEN_REGS;
735 reg_class_from_letter['l'] = LR_REG;
736 reg_class_from_letter['q'] = QUAD_REGS;
737 reg_class_from_letter['t'] = ICC_REGS;
738 reg_class_from_letter['u'] = FCC_REGS;
739 reg_class_from_letter['v'] = ICR_REGS;
740 reg_class_from_letter['w'] = FCR_REGS;
741 reg_class_from_letter['x'] = QUAD_FPR_REGS;
742 reg_class_from_letter['y'] = LCR_REG;
743 reg_class_from_letter['z'] = SPR_REGS;
744 reg_class_from_letter['A'] = QUAD_ACC_REGS;
745 reg_class_from_letter['B'] = ACCG_REGS;
746 reg_class_from_letter['C'] = CR_REGS;
747 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
748 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
750 /* There is no single unaligned SI op for PIC code. Sometimes we
751 need to use ".4byte" and sometimes we need to use ".picptr".
752 See frv_assemble_integer for details. */
753 if (flag_pic || TARGET_FDPIC)
754 targetm.asm_out.unaligned_op.si = 0;
756 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
757 target_flags |= MASK_LINKED_FP;
759 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
760 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
762 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
763 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
765 init_machine_status = frv_init_machine_status;
769 /* Some machines may desire to change what optimizations are performed for
770 various optimization levels. This macro, if defined, is executed once just
771 after the optimization level is determined and before the remainder of the
772 command options have been parsed. Values set in this macro are used as the
773 default values for the other command line options.
775 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
776 `-O' is specified, and 0 if neither is specified.
778 SIZE is nonzero if `-Os' is specified, 0 otherwise.
780 You should not use this macro to change options that are not
781 machine-specific. These should uniformly selected by the same optimization
782 level on all supported machines. Use this macro to enable machine-specific
785 *Do not examine `write_symbols' in this macro!* The debugging options are
786 *not supposed to alter the generated code. */
788 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
789 scheduling pass at the current time. */
791 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
795 #ifdef DISABLE_SCHED2
796 flag_schedule_insns_after_reload = 0;
805 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
808 frv_string_begins_with (tree name, const char *prefix)
810 int prefix_len = strlen (prefix);
812 /* Remember: NAME's length includes the null terminator. */
813 return (TREE_STRING_LENGTH (name) > prefix_len
814 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
817 /* Zero or more C statements that may conditionally modify two variables
818 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
819 been initialized from the two preceding macros.
821 This is necessary in case the fixed or call-clobbered registers depend on
824 You need not define this macro if it has no work to do.
826 If the usage of an entire class of registers depends on the target flags,
827 you may indicate this to GCC by using this macro to modify `fixed_regs' and
828 `call_used_regs' to 1 for each of the registers in the classes which should
829 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
830 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
832 (However, if this class is not included in `GENERAL_REGS' and all of the
833 insn patterns whose constraints permit this class are controlled by target
834 switches, then GCC will automatically avoid using these registers when the
835 target switches are opposed to them.) */
838 frv_conditional_register_usage (void)
842 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
843 fixed_regs[i] = call_used_regs[i] = 1;
845 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
846 fixed_regs[i] = call_used_regs[i] = 1;
848 /* Reserve the registers used for conditional execution. At present, we need
849 1 ICC and 1 ICR register. */
850 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
851 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
855 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
856 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
857 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
858 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
862 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
863 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
866 /* If -fpic, SDA_BASE_REG is the PIC register. */
867 if (g_switch_value == 0 && !flag_pic)
868 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
871 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
877 * Compute the stack frame layout
880 * +---------------+-----------------------+-----------------------+
881 * |Register |type |caller-save/callee-save|
882 * +---------------+-----------------------+-----------------------+
883 * |GR0 |Zero register | - |
884 * |GR1 |Stack pointer(SP) | - |
885 * |GR2 |Frame pointer(FP) | - |
886 * |GR3 |Hidden parameter | caller save |
887 * |GR4-GR7 | - | caller save |
888 * |GR8-GR13 |Argument register | caller save |
889 * |GR14-GR15 | - | caller save |
890 * |GR16-GR31 | - | callee save |
891 * |GR32-GR47 | - | caller save |
892 * |GR48-GR63 | - | callee save |
893 * |FR0-FR15 | - | caller save |
894 * |FR16-FR31 | - | callee save |
895 * |FR32-FR47 | - | caller save |
896 * |FR48-FR63 | - | callee save |
897 * +---------------+-----------------------+-----------------------+
901 * SP-> |-----------------------------------|
903 * |-----------------------------------|
904 * | Register save area |
905 * |-----------------------------------|
906 * | Local variable save area |
907 * FP-> |-----------------------------------|
909 * |-----------------------------------|
910 * | Hidden parameter save area |
911 * |-----------------------------------|
912 * | Return address(LR) storage area |
913 * |-----------------------------------|
914 * | Padding for alignment |
915 * |-----------------------------------|
916 * | Register argument area |
917 * OLD SP-> |-----------------------------------|
919 * |-----------------------------------|
922 * Argument area/Parameter area:
924 * When a function is called, this area is used for argument transfer. When
925 * the argument is set up by the caller function, this area is referred to as
926 * the argument area. When the argument is referenced by the callee function,
927 * this area is referred to as the parameter area. The area is allocated when
928 * all arguments cannot be placed on the argument register at the time of
931 * Register save area:
933 * This is a register save area that must be guaranteed for the caller
934 * function. This area is not secured when the register save operation is not
937 * Local variable save area:
939 * This is the area for local variables and temporary variables.
943 * This area stores the FP value of the caller function.
945 * Hidden parameter save area:
947 * This area stores the start address of the return value storage
948 * area for a struct/union return function.
949 * When a struct/union is used as the return value, the caller
950 * function stores the return value storage area start address in
951 * register GR3 and passes it to the caller function.
952 * The callee function interprets the address stored in the GR3
953 * as the return value storage area start address.
954 * When register GR3 needs to be saved into memory, the callee
955 * function saves it in the hidden parameter save area. This
956 * area is not secured when the save operation is not needed.
958 * Return address(LR) storage area:
960 * This area saves the LR. The LR stores the address of a return to the caller
961 * function for the purpose of function calling.
963 * Argument register area:
965 * This area saves the argument register. This area is not secured when the
966 * save operation is not needed.
970 * Arguments, the count of which equals the count of argument registers (6
971 * words), are positioned in registers GR8 to GR13 and delivered to the callee
972 * function. When a struct/union return function is called, the return value
973 * area address is stored in register GR3. Arguments not placed in the
974 * argument registers will be stored in the stack argument area for transfer
975 * purposes. When an 8-byte type argument is to be delivered using registers,
976 * it is divided into two and placed in two registers for transfer. When
977 * argument registers must be saved to memory, the callee function secures an
978 * argument register save area in the stack. In this case, a continuous
979 * argument register save area must be established in the parameter area. The
980 * argument register save area must be allocated as needed to cover the size of
981 * the argument register to be saved. If the function has a variable count of
982 * arguments, it saves all argument registers in the argument register save
985 * Argument Extension Format:
987 * When an argument is to be stored in the stack, its type is converted to an
988 * extended type in accordance with the individual argument type. The argument
989 * is freed by the caller function after the return from the callee function is
992 * +-----------------------+---------------+------------------------+
993 * | Argument Type |Extended Type |Stack Storage Size(byte)|
994 * +-----------------------+---------------+------------------------+
996 * |signed char |int | 4 |
997 * |unsigned char |int | 4 |
998 * |[signed] short int |int | 4 |
999 * |unsigned short int |int | 4 |
1000 * |[signed] int |No extension | 4 |
1001 * |unsigned int |No extension | 4 |
1002 * |[signed] long int |No extension | 4 |
1003 * |unsigned long int |No extension | 4 |
1004 * |[signed] long long int |No extension | 8 |
1005 * |unsigned long long int |No extension | 8 |
1006 * |float |double | 8 |
1007 * |double |No extension | 8 |
1008 * |long double |No extension | 8 |
1009 * |pointer |No extension | 4 |
1010 * |struct/union |- | 4 (*1) |
1011 * +-----------------------+---------------+------------------------+
1013 * When a struct/union is to be delivered as an argument, the caller copies it
1014 * to the local variable area and delivers the address of that area.
1018 * +-------------------------------+----------------------+
1019 * |Return Value Type |Return Value Interface|
1020 * +-------------------------------+----------------------+
1022 * |[signed|unsigned] char |GR8 |
1023 * |[signed|unsigned] short int |GR8 |
1024 * |[signed|unsigned] int |GR8 |
1025 * |[signed|unsigned] long int |GR8 |
1027 * |[signed|unsigned] long long int|GR8 & GR9 |
1029 * |double |GR8 & GR9 |
1030 * |long double |GR8 & GR9 |
1031 * |struct/union |(*1) |
1032 * +-------------------------------+----------------------+
1034 * When a struct/union is used as the return value, the caller function stores
1035 * the start address of the return value storage area into GR3 and then passes
1036 * it to the callee function. The callee function interprets GR3 as the start
1037 * address of the return value storage area. When this address needs to be
1038 * saved in memory, the callee function secures the hidden parameter save area
1039 * and saves the address in that area.
1043 frv_stack_info (void)
1045 static frv_stack_t info, zero_info;
1046 frv_stack_t *info_ptr = &info;
1047 tree fndecl = current_function_decl;
1055 /* If we've already calculated the values and reload is complete,
1057 if (frv_stack_cache)
1058 return frv_stack_cache;
1060 /* Zero all fields. */
1063 /* Set up the register range information. */
1064 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1065 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1066 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1067 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1069 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1070 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1071 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1072 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1074 info_ptr->regs[STACK_REGS_LR].name = "lr";
1075 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1076 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1077 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1079 info_ptr->regs[STACK_REGS_CC].name = "cc";
1080 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1081 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1082 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1084 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1085 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1086 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1088 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1089 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1090 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1091 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1092 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1094 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1095 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1096 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1097 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1099 info_ptr->regs[STACK_REGS_FP].name = "fp";
1100 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1101 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1102 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1104 /* Determine if this is a stdarg function. If so, allocate space to store
1111 /* Find the last argument, and see if it is __builtin_va_alist. */
1112 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1114 next_arg = TREE_CHAIN (cur_arg);
1115 if (next_arg == (tree)0)
1117 if (DECL_NAME (cur_arg)
1118 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1126 /* Iterate over all of the register ranges. */
1127 for (range = 0; range < STACK_REGS_MAX; range++)
1129 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1130 int first = reg_ptr->first;
1131 int last = reg_ptr->last;
1133 int size_2words = 0;
1136 /* Calculate which registers need to be saved & save area size. */
1140 for (regno = first; regno <= last; regno++)
1142 if ((regs_ever_live[regno] && !call_used_regs[regno])
1143 || (current_function_calls_eh_return
1144 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1145 || (!TARGET_FDPIC && flag_pic
1146 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1148 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1149 size_1word += UNITS_PER_WORD;
1154 /* Calculate whether we need to create a frame after everything else
1155 has been processed. */
1160 if (regs_ever_live[LR_REGNO]
1162 /* This is set for __builtin_return_address, etc. */
1163 || cfun->machine->frame_needed
1164 || (TARGET_LINKED_FP && frame_pointer_needed)
1165 || (!TARGET_FDPIC && flag_pic
1166 && cfun->uses_pic_offset_table))
1168 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1169 size_1word += UNITS_PER_WORD;
1173 case STACK_REGS_STDARG:
1176 /* If this is a stdarg function with a non varardic
1177 argument split between registers and the stack,
1178 adjust the saved registers downward. */
1179 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1182 for (regno = first; regno <= last; regno++)
1184 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1185 size_1word += UNITS_PER_WORD;
1188 info_ptr->stdarg_size = size_1word;
1192 case STACK_REGS_STRUCT:
1193 if (cfun->returns_struct)
1195 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1196 size_1word += UNITS_PER_WORD;
1204 /* If this is a field, it only takes one word. */
1205 if (reg_ptr->field_p)
1206 size_1word = UNITS_PER_WORD;
1208 /* Determine which register pairs can be saved together. */
1209 else if (reg_ptr->dword_p && TARGET_DWORD)
1211 for (regno = first; regno < last; regno += 2)
1213 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1215 size_2words += 2 * UNITS_PER_WORD;
1216 size_1word -= 2 * UNITS_PER_WORD;
1217 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1218 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1223 reg_ptr->size_1word = size_1word;
1224 reg_ptr->size_2words = size_2words;
1226 if (! reg_ptr->special_p)
1228 info_ptr->regs_size_1word += size_1word;
1229 info_ptr->regs_size_2words += size_2words;
1234 /* Set up the sizes of each each field in the frame body, making the sizes
1235 of each be divisible by the size of a dword if dword operations might
1236 be used, or the size of a word otherwise. */
1237 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1239 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1240 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1241 + info_ptr->regs_size_1word,
1243 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1245 info_ptr->pretend_size = cfun->pretend_args_size;
1247 /* Work out the size of the frame, excluding the header. Both the frame
1248 body and register parameter area will be dword-aligned. */
1249 info_ptr->total_size
1250 = (ADDR_ALIGN (info_ptr->parameter_size
1251 + info_ptr->regs_size
1252 + info_ptr->vars_size,
1254 + ADDR_ALIGN (info_ptr->pretend_size
1255 + info_ptr->stdarg_size,
1256 2 * UNITS_PER_WORD));
1258 /* See if we need to create a frame at all, if so add header area. */
1259 if (info_ptr->total_size > 0
1260 || frame_pointer_needed
1261 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1262 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1264 offset = info_ptr->parameter_size;
1265 info_ptr->header_size = 4 * UNITS_PER_WORD;
1266 info_ptr->total_size += 4 * UNITS_PER_WORD;
1268 /* Calculate the offsets to save normal register pairs. */
1269 for (range = 0; range < STACK_REGS_MAX; range++)
1271 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1272 if (! reg_ptr->special_p)
1274 int first = reg_ptr->first;
1275 int last = reg_ptr->last;
1278 for (regno = first; regno <= last; regno++)
1279 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1280 && regno != FRAME_POINTER_REGNUM
1281 && (regno < FIRST_ARG_REGNUM
1282 || regno > LAST_ARG_REGNUM))
1284 info_ptr->reg_offset[regno] = offset;
1285 offset += 2 * UNITS_PER_WORD;
1290 /* Calculate the offsets to save normal single registers. */
1291 for (range = 0; range < STACK_REGS_MAX; range++)
1293 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1294 if (! reg_ptr->special_p)
1296 int first = reg_ptr->first;
1297 int last = reg_ptr->last;
1300 for (regno = first; regno <= last; regno++)
1301 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1302 && regno != FRAME_POINTER_REGNUM
1303 && (regno < FIRST_ARG_REGNUM
1304 || regno > LAST_ARG_REGNUM))
1306 info_ptr->reg_offset[regno] = offset;
1307 offset += UNITS_PER_WORD;
1312 /* Calculate the offset to save the local variables at. */
1313 offset = ADDR_ALIGN (offset, alignment);
1314 if (info_ptr->vars_size)
1316 info_ptr->vars_offset = offset;
1317 offset += info_ptr->vars_size;
1320 /* Align header to a dword-boundary. */
1321 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1323 /* Calculate the offsets in the fixed frame. */
1324 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1325 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1326 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1328 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1329 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1330 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1332 if (cfun->returns_struct)
1334 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1335 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1336 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1339 /* Calculate the offsets to store the arguments passed in registers
1340 for stdarg functions. The register pairs are first and the single
1341 register if any is last. The register save area starts on a
1343 if (info_ptr->stdarg_size)
1345 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1346 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1349 /* Skip the header. */
1350 offset += 4 * UNITS_PER_WORD;
1351 for (regno = first; regno <= last; regno++)
1353 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1355 info_ptr->reg_offset[regno] = offset;
1356 offset += 2 * UNITS_PER_WORD;
1358 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1360 info_ptr->reg_offset[regno] = offset;
1361 offset += UNITS_PER_WORD;
1367 if (reload_completed)
1368 frv_stack_cache = info_ptr;
1374 /* Print the information about the frv stack offsets, etc. when debugging. */
1377 frv_debug_stack (frv_stack_t *info)
1382 info = frv_stack_info ();
1384 fprintf (stderr, "\nStack information for function %s:\n",
1385 ((current_function_decl && DECL_NAME (current_function_decl))
1386 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1389 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1390 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1391 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1392 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1393 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1395 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1396 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1397 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1398 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1400 for (range = 0; range < STACK_REGS_MAX; range++)
1402 frv_stack_regs_t *regs = &(info->regs[range]);
1403 if ((regs->size_1word + regs->size_2words) > 0)
1405 int first = regs->first;
1406 int last = regs->last;
1409 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1410 regs->name, regs->size_1word + regs->size_2words,
1411 regs->size_1word, regs->size_2words);
1413 for (regno = first; regno <= last; regno++)
1415 if (info->save_p[regno] == REG_SAVE_1WORD)
1416 fprintf (stderr, " %s (%d)", reg_names[regno],
1417 info->reg_offset[regno]);
1419 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1420 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1421 reg_names[regno+1], info->reg_offset[regno]);
1424 fputc ('\n', stderr);
1434 /* Used during final to control the packing of insns. The value is
1435 1 if the current instruction should be packed with the next one,
1436 0 if it shouldn't or -1 if packing is disabled altogether. */
1438 static int frv_insn_packing_flag;
1440 /* True if the current function contains a far jump. */
1443 frv_function_contains_far_jump (void)
1445 rtx insn = get_insns ();
1447 && !(GET_CODE (insn) == JUMP_INSN
1448 /* Ignore tablejump patterns. */
1449 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1450 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1451 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1452 insn = NEXT_INSN (insn);
1453 return (insn != NULL);
1456 /* For the FRV, this function makes sure that a function with far jumps
1457 will return correctly. It also does the VLIW packing. */
1460 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1462 /* If no frame was created, check whether the function uses a call
1463 instruction to implement a far jump. If so, save the link in gr3 and
1464 replace all returns to LR with returns to GR3. GR3 is used because it
1465 is call-clobbered, because is not available to the register allocator,
1466 and because all functions that take a hidden argument pointer will have
1468 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1472 /* Just to check that the above comment is true. */
1473 gcc_assert (!regs_ever_live[GPR_FIRST + 3]);
1475 /* Generate the instruction that saves the link register. */
1476 fprintf (file, "\tmovsg lr,gr3\n");
1478 /* Replace the LR with GR3 in *return_internal patterns. The insn
1479 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1480 simply emit a different assembly directive because bralr and jmpl
1481 execute in different units. */
1482 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1483 if (GET_CODE (insn) == JUMP_INSN)
1485 rtx pattern = PATTERN (insn);
1486 if (GET_CODE (pattern) == PARALLEL
1487 && XVECLEN (pattern, 0) >= 2
1488 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1489 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1491 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1492 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1493 REGNO (address) = GPR_FIRST + 3;
1500 /* Allow the garbage collector to free the nops created by frv_reorg. */
1501 memset (frv_nops, 0, sizeof (frv_nops));
1505 /* Return the next available temporary register in a given class. */
1508 frv_alloc_temp_reg (
1509 frv_tmp_reg_t *info, /* which registers are available */
1510 enum reg_class class, /* register class desired */
1511 enum machine_mode mode, /* mode to allocate register with */
1512 int mark_as_used, /* register not available after allocation */
1513 int no_abort) /* return NULL instead of aborting */
1515 int regno = info->next_reg[ (int)class ];
1516 int orig_regno = regno;
1517 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1522 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1523 && TEST_HARD_REG_BIT (info->regs, regno))
1526 if (++regno >= FIRST_PSEUDO_REGISTER)
1528 if (regno == orig_regno)
1530 gcc_assert (no_abort);
1535 nr = HARD_REGNO_NREGS (regno, mode);
1536 info->next_reg[ (int)class ] = regno + nr;
1539 for (i = 0; i < nr; i++)
1540 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1542 return gen_rtx_REG (mode, regno);
1546 /* Return an rtx with the value OFFSET, which will either be a register or a
1547 signed 12-bit integer. It can be used as the second operand in an "add"
1548 instruction, or as the index in a load or store.
1550 The function returns a constant rtx if OFFSET is small enough, otherwise
1551 it loads the constant into register OFFSET_REGNO and returns that. */
1553 frv_frame_offset_rtx (int offset)
1555 rtx offset_rtx = GEN_INT (offset);
1556 if (IN_RANGE_P (offset, -2048, 2047))
1560 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1561 if (IN_RANGE_P (offset, -32768, 32767))
1562 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1565 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1566 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1572 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1573 prologue and epilogue uses such expressions to access the stack. */
1575 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1577 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1579 frv_frame_offset_rtx (offset)));
1582 /* Generate a frame-related expression:
1584 (set REG (mem (plus (sp) (const_int OFFSET)))).
1586 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1587 instructions. Marking the expressions as frame-related is superfluous if
1588 the note contains just a single set. But if the note contains a PARALLEL
1589 or SEQUENCE that has several sets, each set must be individually marked
1590 as frame-related. */
1592 frv_dwarf_store (rtx reg, int offset)
1594 rtx set = gen_rtx_SET (VOIDmode,
1595 gen_rtx_MEM (GET_MODE (reg),
1596 plus_constant (stack_pointer_rtx,
1599 RTX_FRAME_RELATED_P (set) = 1;
1603 /* Emit a frame-related instruction whose pattern is PATTERN. The
1604 instruction is the last in a sequence that cumulatively performs the
1605 operation described by DWARF_PATTERN. The instruction is marked as
1606 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1609 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1611 rtx insn = emit_insn (pattern);
1612 RTX_FRAME_RELATED_P (insn) = 1;
1613 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1618 /* Emit instructions that transfer REG to or from the memory location (sp +
1619 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1620 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1621 function to store registers and only the epilogue uses it to load them.
1623 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1624 The generated instruction will use BASE as its base register. BASE may
1625 simply be the stack pointer, but if several accesses are being made to a
1626 region far away from the stack pointer, it may be more efficient to set
1627 up a temporary instead.
1629 Store instructions will be frame-related and will be annotated with the
1630 overall effect of the store. Load instructions will be followed by a
1631 (use) to prevent later optimizations from zapping them.
1633 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1634 as a temporary in such cases. */
1636 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1638 enum machine_mode mode = GET_MODE (reg);
1639 rtx mem = frv_frame_mem (mode,
1641 stack_offset - accessor->base_offset);
1643 if (accessor->op == FRV_LOAD)
1645 if (SPR_P (REGNO (reg)))
1647 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1648 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1649 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1652 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1653 emit_insn (gen_rtx_USE (VOIDmode, reg));
1657 if (SPR_P (REGNO (reg)))
1659 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1660 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1661 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1662 frv_dwarf_store (reg, stack_offset));
1664 else if (GET_MODE (reg) == DImode)
1666 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1667 with a separate save for each register. */
1668 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1669 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1670 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1671 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1672 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1673 gen_rtx_PARALLEL (VOIDmode,
1674 gen_rtvec (2, set1, set2)));
1677 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1678 frv_dwarf_store (reg, stack_offset));
1682 /* A function that uses frv_frame_access to transfer a group of registers to
1683 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1684 is the stack information generated by frv_stack_info, and REG_SET is the
1685 number of the register set to transfer. */
1687 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1691 frv_stack_regs_t *regs_info;
1694 regs_info = &info->regs[reg_set];
1695 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1696 if (info->save_p[regno])
1697 frv_frame_access (accessor,
1698 info->save_p[regno] == REG_SAVE_2WORDS
1699 ? gen_rtx_REG (DImode, regno)
1700 : gen_rtx_REG (SImode, regno),
1701 info->reg_offset[regno]);
1704 /* Save or restore callee-saved registers that are kept outside the frame
1705 header. The function saves the registers if OP is FRV_STORE and restores
1706 them if OP is FRV_LOAD. INFO is the stack information generated by
1709 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1711 frv_frame_accessor_t accessor;
1714 accessor.base = stack_pointer_rtx;
1715 accessor.base_offset = 0;
1716 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1717 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1718 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1722 /* Called after register allocation to add any instructions needed for the
1723 prologue. Using a prologue insn is favored compared to putting all of the
1724 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1725 it allows the scheduler to intermix instructions with the saves of
1726 the caller saved registers. In some cases, it might be necessary
1727 to emit a barrier instruction as the last insn to prevent such
1730 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1731 so that the debug info generation code can handle them properly. */
1733 frv_expand_prologue (void)
1735 frv_stack_t *info = frv_stack_info ();
1736 rtx sp = stack_pointer_rtx;
1737 rtx fp = frame_pointer_rtx;
1738 frv_frame_accessor_t accessor;
1740 if (TARGET_DEBUG_STACK)
1741 frv_debug_stack (info);
1743 if (info->total_size == 0)
1746 /* We're interested in three areas of the frame here:
1748 A: the register save area
1750 C: the header after B
1752 If the frame pointer isn't used, we'll have to set up A, B and C
1753 using the stack pointer. If the frame pointer is used, we'll access
1757 B: set up using sp or a temporary (see below)
1760 We set up B using the stack pointer if the frame is small enough.
1761 Otherwise, it's more efficient to copy the old stack pointer into a
1762 temporary and use that.
1764 Note that it's important to make sure the prologue and epilogue use the
1765 same registers to access A and C, since doing otherwise will confuse
1766 the aliasing code. */
1768 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1769 isn't used, the same method will serve for C. */
1770 accessor.op = FRV_STORE;
1771 if (frame_pointer_needed && info->total_size > 2048)
1775 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1776 accessor.base_offset = info->total_size;
1777 insn = emit_insn (gen_movsi (accessor.base, sp));
1781 accessor.base = stack_pointer_rtx;
1782 accessor.base_offset = 0;
1785 /* Allocate the stack space. */
1787 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1788 rtx dwarf_offset = GEN_INT (-info->total_size);
1790 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1793 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1796 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1797 and point the new one to that location. */
1798 if (frame_pointer_needed)
1800 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1802 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1803 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1805 rtx asm_src = plus_constant (accessor.base,
1806 fp_offset - accessor.base_offset);
1807 rtx dwarf_src = plus_constant (sp, fp_offset);
1809 /* Store the old frame pointer at (sp + FP_OFFSET). */
1810 frv_frame_access (&accessor, fp, fp_offset);
1812 /* Set up the new frame pointer. */
1813 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1814 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1816 /* Access region C from the frame pointer. */
1818 accessor.base_offset = fp_offset;
1821 /* Set up region C. */
1822 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1823 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1824 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1826 /* Set up region A. */
1827 frv_frame_access_standard_regs (FRV_STORE, info);
1829 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1830 scheduler from moving loads before the stores saving the registers. */
1831 if (info->stdarg_size > 0)
1832 emit_insn (gen_blockage ());
1834 /* Set up pic register/small data register for this function. */
1835 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1836 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1837 gen_rtx_REG (Pmode, LR_REGNO),
1838 gen_rtx_REG (SImode, OFFSET_REGNO)));
1842 /* Under frv, all of the work is done via frv_expand_epilogue, but
1843 this function provides a convenient place to do cleanup. */
1846 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1847 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1849 frv_stack_cache = (frv_stack_t *)0;
1851 /* Zap last used registers for conditional execution. */
1852 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1854 /* Release the bitmap of created insns. */
1855 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1859 /* Called after register allocation to add any instructions needed for the
1860 epilogue. Using an epilogue insn is favored compared to putting all of the
1861 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1862 it allows the scheduler to intermix instructions with the saves of
1863 the caller saved registers. In some cases, it might be necessary
1864 to emit a barrier instruction as the last insn to prevent such
1868 frv_expand_epilogue (bool emit_return)
1870 frv_stack_t *info = frv_stack_info ();
1871 rtx fp = frame_pointer_rtx;
1872 rtx sp = stack_pointer_rtx;
1876 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1878 /* Restore the stack pointer to its original value if alloca or the like
1880 if (! current_function_sp_is_unchanging)
1881 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1883 /* Restore the callee-saved registers that were used in this function. */
1884 frv_frame_access_standard_regs (FRV_LOAD, info);
1886 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1887 no return instruction should be emitted. */
1888 if (info->save_p[LR_REGNO])
1893 /* Use the same method to access the link register's slot as we did in
1894 the prologue. In other words, use the frame pointer if available,
1895 otherwise use the stack pointer.
1897 LR_OFFSET is the offset of the link register's slot from the start
1898 of the frame and MEM is a memory rtx for it. */
1899 lr_offset = info->reg_offset[LR_REGNO];
1900 if (frame_pointer_needed)
1901 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1903 mem = frv_frame_mem (Pmode, sp, lr_offset);
1905 /* Load the old link register into a GPR. */
1906 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1907 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1910 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1912 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1913 the load is preserved. */
1914 if (frame_pointer_needed)
1916 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1917 emit_insn (gen_rtx_USE (VOIDmode, fp));
1920 /* Deallocate the stack frame. */
1921 if (info->total_size != 0)
1923 rtx offset = frv_frame_offset_rtx (info->total_size);
1924 emit_insn (gen_stack_adjust (sp, sp, offset));
1927 /* If this function uses eh_return, add the final stack adjustment now. */
1928 if (current_function_calls_eh_return)
1929 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1932 emit_jump_insn (gen_epilogue_return (return_addr));
1935 rtx lr = return_addr;
1937 if (REGNO (return_addr) != LR_REGNO)
1939 lr = gen_rtx_REG (Pmode, LR_REGNO);
1940 emit_move_insn (lr, return_addr);
1943 emit_insn (gen_rtx_USE (VOIDmode, lr));
1948 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1951 frv_asm_output_mi_thunk (FILE *file,
1952 tree thunk_fndecl ATTRIBUTE_UNUSED,
1953 HOST_WIDE_INT delta,
1954 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1957 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1958 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1959 const char *name_jmp = reg_names[JUMP_REGNO];
1960 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1962 /* Do the add using an addi if possible. */
1963 if (IN_RANGE_P (delta, -2048, 2047))
1964 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1967 const char *const name_add = reg_names[TEMP_REGNO];
1968 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1969 parallel, delta, name_add);
1970 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1972 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1977 const char *name_pic = reg_names[FDPIC_REGNO];
1978 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1982 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1983 assemble_name (file, name_func);
1984 fprintf (file, "),%s\n", name_jmp);
1986 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1987 assemble_name (file, name_func);
1988 fprintf (file, "),%s\n", name_jmp);
1990 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1994 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
1995 assemble_name (file, name_func);
1996 fprintf (file, "\t)), %s\n", name_jmp);
2001 fprintf (file, "\tsethi%s #hi(", parallel);
2002 assemble_name (file, name_func);
2003 fprintf (file, "),%s\n", name_jmp);
2005 fprintf (file, "\tsetlo #lo(");
2006 assemble_name (file, name_func);
2007 fprintf (file, "),%s\n", name_jmp);
2011 /* Use JUMP_REGNO as a temporary PIC register. */
2012 const char *name_lr = reg_names[LR_REGNO];
2013 const char *name_gppic = name_jmp;
2014 const char *name_tmp = reg_names[TEMP_REGNO];
2016 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2017 fprintf (file, "\tcall 1f\n");
2018 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2019 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2020 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2021 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2022 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2024 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2025 assemble_name (file, name_func);
2026 fprintf (file, "),%s\n", name_tmp);
2028 fprintf (file, "\tsetlo #gprello(");
2029 assemble_name (file, name_func);
2030 fprintf (file, "),%s\n", name_tmp);
2032 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2035 /* Jump to the function address. */
2036 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2040 /* A C expression which is nonzero if a function must have and use a frame
2041 pointer. This expression is evaluated in the reload pass. If its value is
2042 nonzero the function will have a frame pointer.
2044 The expression can in principle examine the current function and decide
2045 according to the facts, but on most machines the constant 0 or the constant
2046 1 suffices. Use 0 when the machine allows code to be generated with no
2047 frame pointer, and doing so saves some time or space. Use 1 when there is
2048 no possible advantage to avoiding a frame pointer.
2050 In certain cases, the compiler does not know how to produce valid code
2051 without a frame pointer. The compiler recognizes those cases and
2052 automatically gives the function a frame pointer regardless of what
2053 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2055 In a function that does not require a frame pointer, the frame pointer
2056 register can be allocated for ordinary usage, unless you mark it as a fixed
2057 register. See `FIXED_REGISTERS' for more information. */
2059 /* On frv, create a frame whenever we need to create stack. */
2062 frv_frame_pointer_required (void)
2064 /* If we forgoing the usual linkage requirements, we only need
2065 a frame pointer if the stack pointer might change. */
2066 if (!TARGET_LINKED_FP)
2067 return !current_function_sp_is_unchanging;
2069 if (! current_function_is_leaf)
2072 if (get_frame_size () != 0)
2078 if (!current_function_sp_is_unchanging)
2081 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
2087 if (cfun->machine->frame_needed)
2094 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2095 initial difference between the specified pair of registers. This macro must
2096 be defined if `ELIMINABLE_REGS' is defined. */
2098 /* See frv_stack_info for more details on the frv stack frame. */
2101 frv_initial_elimination_offset (int from, int to)
2103 frv_stack_t *info = frv_stack_info ();
2106 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2107 ret = info->total_size - info->pretend_size;
2109 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2110 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2112 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2113 ret = (info->total_size
2114 - info->reg_offset[FRAME_POINTER_REGNUM]
2115 - info->pretend_size);
2120 if (TARGET_DEBUG_STACK)
2121 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2122 reg_names [from], reg_names[to], ret);
2128 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2131 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2132 enum machine_mode mode,
2133 tree type ATTRIBUTE_UNUSED,
2137 if (TARGET_DEBUG_ARG)
2139 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2140 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2144 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2147 frv_expand_builtin_saveregs (void)
2149 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2151 if (TARGET_DEBUG_ARG)
2152 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2155 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2159 /* Expand __builtin_va_start to do the va_start macro. */
2162 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2165 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2167 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2168 GEN_INT (UNITS_PER_WORD * num));
2170 if (TARGET_DEBUG_ARG)
2172 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2173 cfun->args_info, num);
2175 debug_rtx (nextarg);
2178 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2179 make_tree (ptr_type_node, nextarg));
2180 TREE_SIDE_EFFECTS (t) = 1;
2182 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2186 /* Expand a block move operation, and return 1 if successful. Return 0
2187 if we should let the compiler generate normal code.
2189 operands[0] is the destination
2190 operands[1] is the source
2191 operands[2] is the length
2192 operands[3] is the alignment */
2194 /* Maximum number of loads to do before doing the stores */
2195 #ifndef MAX_MOVE_REG
2196 #define MAX_MOVE_REG 4
2199 /* Maximum number of total loads to do. */
2200 #ifndef TOTAL_MOVE_REG
2201 #define TOTAL_MOVE_REG 8
2205 frv_expand_block_move (rtx operands[])
2207 rtx orig_dest = operands[0];
2208 rtx orig_src = operands[1];
2209 rtx bytes_rtx = operands[2];
2210 rtx align_rtx = operands[3];
2211 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2224 rtx stores[MAX_MOVE_REG];
2226 enum machine_mode mode;
2228 /* If this is not a fixed size move, just call memcpy. */
2232 /* This should be a fixed size alignment. */
2233 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2235 align = INTVAL (align_rtx);
2237 /* Anything to move? */
2238 bytes = INTVAL (bytes_rtx);
2242 /* Don't support real large moves. */
2243 if (bytes > TOTAL_MOVE_REG*align)
2246 /* Move the address into scratch registers. */
2247 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2248 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2250 num_reg = offset = 0;
2251 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2253 /* Calculate the correct offset for src/dest. */
2257 dest_addr = dest_reg;
2261 src_addr = plus_constant (src_reg, offset);
2262 dest_addr = plus_constant (dest_reg, offset);
2265 /* Generate the appropriate load and store, saving the stores
2267 if (bytes >= 4 && align >= 4)
2269 else if (bytes >= 2 && align >= 2)
2274 move_bytes = GET_MODE_SIZE (mode);
2275 tmp_reg = gen_reg_rtx (mode);
2276 src_mem = change_address (orig_src, mode, src_addr);
2277 dest_mem = change_address (orig_dest, mode, dest_addr);
2278 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2279 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2281 if (num_reg >= MAX_MOVE_REG)
2283 for (i = 0; i < num_reg; i++)
2284 emit_insn (stores[i]);
2289 for (i = 0; i < num_reg; i++)
2290 emit_insn (stores[i]);
2296 /* Expand a block clear operation, and return 1 if successful. Return 0
2297 if we should let the compiler generate normal code.
2299 operands[0] is the destination
2300 operands[1] is the length
2301 operands[2] is the alignment */
2304 frv_expand_block_clear (rtx operands[])
2306 rtx orig_dest = operands[0];
2307 rtx bytes_rtx = operands[1];
2308 rtx align_rtx = operands[2];
2309 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2318 enum machine_mode mode;
2320 /* If this is not a fixed size move, just call memcpy. */
2324 /* This should be a fixed size alignment. */
2325 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2327 align = INTVAL (align_rtx);
2329 /* Anything to move? */
2330 bytes = INTVAL (bytes_rtx);
2334 /* Don't support real large clears. */
2335 if (bytes > TOTAL_MOVE_REG*align)
2338 /* Move the address into a scratch register. */
2339 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2341 num_reg = offset = 0;
2342 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2344 /* Calculate the correct offset for src/dest. */
2345 dest_addr = ((offset == 0)
2347 : plus_constant (dest_reg, offset));
2349 /* Generate the appropriate store of gr0. */
2350 if (bytes >= 4 && align >= 4)
2352 else if (bytes >= 2 && align >= 2)
2357 clear_bytes = GET_MODE_SIZE (mode);
2358 dest_mem = change_address (orig_dest, mode, dest_addr);
2359 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2366 /* The following variable is used to output modifiers of assembler
2367 code of the current output insn. */
2369 static rtx *frv_insn_operands;
2371 /* The following function is used to add assembler insn code suffix .p
2372 if it is necessary. */
2375 frv_asm_output_opcode (FILE *f, const char *ptr)
2379 if (frv_insn_packing_flag <= 0)
2382 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2385 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2386 || (*ptr >= 'A' && *ptr <= 'Z')))
2388 int letter = *ptr++;
2391 frv_print_operand (f, frv_insn_operands [c], letter);
2392 while ((c = *ptr) >= '0' && c <= '9')
2404 /* Set up the packing bit for the current output insn. Note that this
2405 function is not called for asm insns. */
2408 frv_final_prescan_insn (rtx insn, rtx *opvec,
2409 int noperands ATTRIBUTE_UNUSED)
2413 if (frv_insn_packing_flag >= 0)
2415 frv_insn_operands = opvec;
2416 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2418 else if (recog_memoized (insn) >= 0
2419 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2420 /* Packing optimizations have been disabled, but INSN can only
2421 be issued in M1. Insert an mnop in M0. */
2422 fprintf (asm_out_file, "\tmnop.p\n");
2428 /* A C expression whose value is RTL representing the address in a stack frame
2429 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2430 an RTL expression for the address of the stack frame itself.
2432 If you don't define this macro, the default is to return the value of
2433 FRAMEADDR--that is, the stack frame address is also the address of the stack
2434 word that points to the previous frame. */
2436 /* The default is correct, but we need to make sure the frame gets created. */
2438 frv_dynamic_chain_address (rtx frame)
2440 cfun->machine->frame_needed = 1;
2445 /* A C expression whose value is RTL representing the value of the return
2446 address for the frame COUNT steps up from the current frame, after the
2447 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2448 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2451 The value of the expression must always be the correct address when COUNT is
2452 zero, but may be `NULL_RTX' if there is not way to determine the return
2453 address of other frames. */
2456 frv_return_addr_rtx (int count, rtx frame)
2460 cfun->machine->frame_needed = 1;
2461 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2464 /* Given a memory reference MEMREF, interpret the referenced memory as
2465 an array of MODE values, and return a reference to the element
2466 specified by INDEX. Assume that any pre-modification implicit in
2467 MEMREF has already happened.
2469 MEMREF must be a legitimate operand for modes larger than SImode.
2470 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2471 this function cannot handle. */
2473 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2475 rtx base = XEXP (memref, 0);
2476 if (GET_CODE (base) == PRE_MODIFY)
2477 base = XEXP (base, 0);
2478 return change_address (memref, mode,
2479 plus_constant (base, index * GET_MODE_SIZE (mode)));
2483 /* Print a memory address as an operand to reference that memory location. */
2485 frv_print_operand_address (FILE * stream, rtx x)
2487 if (GET_CODE (x) == MEM)
2490 switch (GET_CODE (x))
2493 fputs (reg_names [ REGNO (x)], stream);
2497 fprintf (stream, "%ld", (long) INTVAL (x));
2501 assemble_name (stream, XSTR (x, 0));
2506 output_addr_const (stream, x);
2513 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2518 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2520 int regno = true_regnum (x);
2522 fputs (reg_names[regno], stream);
2524 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2527 /* Print a memory reference suitable for the ld/st instructions. */
2530 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2532 struct frv_unspec unspec;
2536 switch (GET_CODE (x))
2543 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2545 x1 = XEXP (XEXP (x, 1), 1);
2555 if (GET_CODE (x0) == CONST_INT)
2563 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2572 else if (GET_CODE (x1) != CONST_INT)
2573 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2576 fputs ("@(", stream);
2578 fputs (reg_names[GPR_R0], stream);
2579 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2580 frv_print_operand_memory_reference_reg (stream, x0);
2582 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2584 fputs (",", stream);
2586 fputs (reg_names [GPR_R0], stream);
2590 switch (GET_CODE (x1))
2594 frv_print_operand_memory_reference_reg (stream, x1);
2598 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2602 if (!frv_const_unspec_p (x1, &unspec))
2603 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2604 frv_output_const_unspec (stream, &unspec);
2608 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2612 fputs (")", stream);
2616 /* Return 2 for likely branches and 0 for non-likely branches */
2618 #define FRV_JUMP_LIKELY 2
2619 #define FRV_JUMP_NOT_LIKELY 0
2622 frv_print_operand_jump_hint (rtx insn)
2627 HOST_WIDE_INT prob = -1;
2628 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2630 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2632 /* Assume any non-conditional jump is likely. */
2633 if (! any_condjump_p (insn))
2634 ret = FRV_JUMP_LIKELY;
2638 labelref = condjump_label (insn);
2641 rtx label = XEXP (labelref, 0);
2642 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2647 note = find_reg_note (insn, REG_BR_PROB, 0);
2649 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2653 prob = INTVAL (XEXP (note, 0));
2654 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2656 : FRV_JUMP_NOT_LIKELY);
2668 case UNKNOWN: direction = "unknown jump direction"; break;
2669 case BACKWARD: direction = "jump backward"; break;
2670 case FORWARD: direction = "jump forward"; break;
2674 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2675 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2676 (long)INSN_UID (insn), direction, (long)prob,
2677 (long)REG_BR_PROB_BASE, ret);
2685 /* Return the comparison operator to use for CODE given that the ICC
2689 comparison_string (enum rtx_code code, rtx op0)
2691 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2694 default: output_operand_lossage ("bad condition code");
2695 case EQ: return "eq";
2696 case NE: return "ne";
2697 case LT: return is_nz_p ? "n" : "lt";
2698 case LE: return "le";
2699 case GT: return "gt";
2700 case GE: return is_nz_p ? "p" : "ge";
2701 case LTU: return is_nz_p ? "no" : "c";
2702 case LEU: return is_nz_p ? "eq" : "ls";
2703 case GTU: return is_nz_p ? "ne" : "hi";
2704 case GEU: return is_nz_p ? "ra" : "nc";
2708 /* Print an operand to an assembler instruction.
2710 `%' followed by a letter and a digit says to output an operand in an
2711 alternate fashion. Four letters have standard, built-in meanings described
2712 below. The machine description macro `PRINT_OPERAND' can define additional
2713 letters with nonstandard meanings.
2715 `%cDIGIT' can be used to substitute an operand that is a constant value
2716 without the syntax that normally indicates an immediate operand.
2718 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2721 `%aDIGIT' can be used to substitute an operand as if it were a memory
2722 reference, with the actual operand treated as the address. This may be
2723 useful when outputting a "load address" instruction, because often the
2724 assembler syntax for such an instruction requires you to write the operand
2725 as if it were a memory reference.
2727 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2729 `%=' outputs a number which is unique to each instruction in the entire
2730 compilation. This is useful for making local labels to be referred to more
2731 than once in a single template that generates multiple assembler
2734 `%' followed by a punctuation character specifies a substitution that does
2735 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2736 assembler code. Other nonstandard cases can be defined in the
2737 `PRINT_OPERAND' macro. You must also define which punctuation characters
2738 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2741 frv_print_operand (FILE * file, rtx x, int code)
2743 struct frv_unspec unspec;
2744 HOST_WIDE_INT value;
2747 if (code != 0 && !isalpha (code))
2750 else if (GET_CODE (x) == CONST_INT)
2753 else if (GET_CODE (x) == CONST_DOUBLE)
2755 if (GET_MODE (x) == SFmode)
2760 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2761 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2765 else if (GET_MODE (x) == VOIDmode)
2766 value = CONST_DOUBLE_LOW (x);
2769 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2780 fputs (reg_names[GPR_R0], file);
2784 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2788 /* Output small data area base register (gr16). */
2789 fputs (reg_names[SDA_BASE_REG], file);
2793 /* Output pic register (gr17). */
2794 fputs (reg_names[PIC_REGNO], file);
2798 /* Output the temporary integer CCR register. */
2799 fputs (reg_names[ICR_TEMP], file);
2803 /* Output the temporary integer CC register. */
2804 fputs (reg_names[ICC_TEMP], file);
2807 /* case 'a': print an address. */
2810 /* Print appropriate test for integer branch false operation. */
2811 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2812 XEXP (x, 0)), file);
2816 /* Print appropriate test for integer branch true operation. */
2817 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2821 /* Print 1 for a NE and 0 for an EQ to give the final argument
2822 for a conditional instruction. */
2823 if (GET_CODE (x) == NE)
2826 else if (GET_CODE (x) == EQ)
2830 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2834 /* Print appropriate test for floating point branch false operation. */
2835 switch (GET_CODE (x))
2838 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2840 case EQ: fputs ("ne", file); break;
2841 case NE: fputs ("eq", file); break;
2842 case LT: fputs ("uge", file); break;
2843 case LE: fputs ("ug", file); break;
2844 case GT: fputs ("ule", file); break;
2845 case GE: fputs ("ul", file); break;
2850 /* Print appropriate test for floating point branch true operation. */
2851 switch (GET_CODE (x))
2854 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2856 case EQ: fputs ("eq", file); break;
2857 case NE: fputs ("ne", file); break;
2858 case LT: fputs ("lt", file); break;
2859 case LE: fputs ("le", file); break;
2860 case GT: fputs ("gt", file); break;
2861 case GE: fputs ("ge", file); break;
2866 /* Print appropriate GOT function. */
2867 if (GET_CODE (x) != CONST_INT)
2868 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2869 fputs (unspec_got_name (INTVAL (x)), file);
2873 /* Print 'i' if the operand is a constant, or is a memory reference that
2875 if (GET_CODE (x) == MEM)
2876 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2877 ? XEXP (XEXP (x, 0), 1)
2879 else if (GET_CODE (x) == PLUS)
2882 switch (GET_CODE (x))
2896 /* For jump instructions, print 'i' if the operand is a constant or
2897 is an expression that adds a constant. */
2898 if (GET_CODE (x) == CONST_INT)
2903 if (GET_CODE (x) == CONST_INT
2904 || (GET_CODE (x) == PLUS
2905 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2906 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2912 /* Print the lower register of a double word register pair */
2913 if (GET_CODE (x) == REG)
2914 fputs (reg_names[ REGNO (x)+1 ], file);
2916 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2919 /* case 'l': print a LABEL_REF. */
2923 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2924 for the second word of double memory operations. */
2925 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2926 switch (GET_CODE (x))
2929 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2932 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2940 frv_print_operand_memory_reference (file, x, offset);
2946 /* Print the opcode of a command. */
2947 switch (GET_CODE (x))
2950 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2952 case PLUS: fputs ("add", file); break;
2953 case MINUS: fputs ("sub", file); break;
2954 case AND: fputs ("and", file); break;
2955 case IOR: fputs ("or", file); break;
2956 case XOR: fputs ("xor", file); break;
2957 case ASHIFT: fputs ("sll", file); break;
2958 case ASHIFTRT: fputs ("sra", file); break;
2959 case LSHIFTRT: fputs ("srl", file); break;
2963 /* case 'n': negate and print a constant int. */
2966 /* Print PIC label using operand as the number. */
2967 if (GET_CODE (x) != CONST_INT)
2968 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2970 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2974 /* Print 'u' if the operand is a update load/store. */
2975 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2980 /* If value is 0, print gr0, otherwise it must be a register. */
2981 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2982 fputs (reg_names[GPR_R0], file);
2984 else if (GET_CODE (x) == REG)
2985 fputs (reg_names [REGNO (x)], file);
2988 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2992 /* Print constant in hex. */
2993 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2995 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3002 if (GET_CODE (x) == REG)
3003 fputs (reg_names [REGNO (x)], file);
3005 else if (GET_CODE (x) == CONST_INT
3006 || GET_CODE (x) == CONST_DOUBLE)
3007 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3009 else if (frv_const_unspec_p (x, &unspec))
3010 frv_output_const_unspec (file, &unspec);
3012 else if (GET_CODE (x) == MEM)
3013 frv_print_operand_address (file, XEXP (x, 0));
3015 else if (CONSTANT_ADDRESS_P (x))
3016 frv_print_operand_address (file, x);
3019 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3024 fatal_insn ("frv_print_operand: unknown code", x);
3032 /* A C statement (sans semicolon) for initializing the variable CUM for the
3033 state at the beginning of the argument list. The variable has type
3034 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3035 of the function which will receive the args, or 0 if the args are to a
3036 compiler support library function. The value of INDIRECT is nonzero when
3037 processing an indirect call, for example a call through a function pointer.
3038 The value of INDIRECT is zero for a call to an explicitly named function, a
3039 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3040 arguments for the function being compiled.
3042 When processing a call to a compiler support library function, LIBNAME
3043 identifies which one. It is a `symbol_ref' rtx which contains the name of
3044 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3045 being processed. Thus, each time this macro is called, either LIBNAME or
3046 FNTYPE is nonzero, but never both of them at once. */
3049 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3055 *cum = FIRST_ARG_REGNUM;
3057 if (TARGET_DEBUG_ARG)
3059 fprintf (stderr, "\ninit_cumulative_args:");
3060 if (!fndecl && fntype)
3061 fputs (" indirect", stderr);
3064 fputs (" incoming", stderr);
3068 tree ret_type = TREE_TYPE (fntype);
3069 fprintf (stderr, " return=%s,",
3070 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3073 if (libname && GET_CODE (libname) == SYMBOL_REF)
3074 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3076 if (cfun->returns_struct)
3077 fprintf (stderr, " return-struct");
3079 putc ('\n', stderr);
3084 /* Return true if we should pass an argument on the stack rather than
3088 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3090 if (mode == BLKmode)
3094 return AGGREGATE_TYPE_P (type);
3097 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3098 argument with the specified mode and type. If it is not defined,
3099 `PARM_BOUNDARY' is used for all arguments. */
3102 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3103 tree type ATTRIBUTE_UNUSED)
3105 return BITS_PER_WORD;
3109 frv_function_arg (CUMULATIVE_ARGS *cum,
3110 enum machine_mode mode,
3111 tree type ATTRIBUTE_UNUSED,
3113 int incoming ATTRIBUTE_UNUSED)
3115 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3120 /* Return a marker for use in the call instruction. */
3121 if (xmode == VOIDmode)
3127 else if (arg_num <= LAST_ARG_REGNUM)
3129 ret = gen_rtx_REG (xmode, arg_num);
3130 debstr = reg_names[arg_num];
3139 if (TARGET_DEBUG_ARG)
3141 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3142 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3148 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3149 advance past an argument in the argument list. The values MODE, TYPE and
3150 NAMED describe that argument. Once this is done, the variable CUM is
3151 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3153 This macro need not do anything if the argument in question was passed on
3154 the stack. The compiler knows how to track the amount of stack space used
3155 for arguments without any special help. */
3158 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3159 enum machine_mode mode,
3160 tree type ATTRIBUTE_UNUSED,
3163 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3164 int bytes = GET_MODE_SIZE (xmode);
3165 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3168 *cum = arg_num + words;
3170 if (TARGET_DEBUG_ARG)
3172 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3173 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3177 /* A C expression for the number of words, at the beginning of an argument,
3178 must be put in registers. The value must be zero for arguments that are
3179 passed entirely in registers or that are entirely pushed on the stack.
3181 On some machines, certain arguments must be passed partially in registers
3182 and partially in memory. On these machines, typically the first N words of
3183 arguments are passed in registers, and the rest on the stack. If a
3184 multi-word argument (a `double' or a structure) crosses that boundary, its
3185 first few words must be passed in registers and the rest must be pushed.
3186 This macro tells the compiler when this occurs, and how many of the words
3187 should go in registers.
3189 `FUNCTION_ARG' for these arguments should return the first register to be
3190 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3191 the called function. */
3194 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3195 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3197 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3198 int bytes = GET_MODE_SIZE (xmode);
3199 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3203 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3204 ? LAST_ARG_REGNUM - arg_num + 1
3206 ret *= UNITS_PER_WORD;
3208 if (TARGET_DEBUG_ARG && ret)
3209 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3215 /* Return true if a register is ok to use as a base or index register. */
3217 static FRV_INLINE int
3218 frv_regno_ok_for_base_p (int regno, int strict_p)
3224 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3226 if (regno == ARG_POINTER_REGNUM)
3229 return (regno >= FIRST_PSEUDO_REGISTER);
3233 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3234 RTX) is a legitimate memory address on the target machine for a memory
3235 operand of mode MODE.
3237 It usually pays to define several simpler macros to serve as subroutines for
3238 this one. Otherwise it may be too complicated to understand.
3240 This macro must exist in two variants: a strict variant and a non-strict
3241 one. The strict variant is used in the reload pass. It must be defined so
3242 that any pseudo-register that has not been allocated a hard register is
3243 considered a memory reference. In contexts where some kind of register is
3244 required, a pseudo-register with no hard register must be rejected.
3246 The non-strict variant is used in other passes. It must be defined to
3247 accept all pseudo-registers in every context where some kind of register is
3250 Compiler source files that want to use the strict variant of this macro
3251 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3252 conditional to define the strict variant in that case and the non-strict
3255 Subroutines to check for acceptable registers for various purposes (one for
3256 base registers, one for index registers, and so on) are typically among the
3257 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3258 subroutine macros need have two variants; the higher levels of macros may be
3259 the same whether strict or not.
3261 Normally, constant addresses which are the sum of a `symbol_ref' and an
3262 integer are stored inside a `const' RTX to mark them as constant.
3263 Therefore, there is no need to recognize such sums specifically as
3264 legitimate addresses. Normally you would simply recognize any `const' as
3267 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3268 are not marked with `const'. It assumes that a naked `plus' indicates
3269 indexing. If so, then you *must* reject such naked constant sums as
3270 illegitimate addresses, so that none of them will be given to
3271 `PRINT_OPERAND_ADDRESS'.
3273 On some machines, whether a symbolic address is legitimate depends on the
3274 section that the address refers to. On these machines, define the macro
3275 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3276 then check for it here. When you see a `const', you will have to look
3277 inside it to find the `symbol_ref' in order to determine the section.
3279 The best way to modify the name string is by adding text to the beginning,
3280 with suitable punctuation to prevent any ambiguity. Allocate the new name
3281 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3282 remove and decode the added text and output the name accordingly, and define
3283 `(* targetm.strip_name_encoding)' to access the original name string.
3285 You can check the information stored here into the `symbol_ref' in the
3286 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3287 `PRINT_OPERAND_ADDRESS'. */
3290 frv_legitimate_address_p (enum machine_mode mode,
3294 int allow_double_reg_p)
3298 HOST_WIDE_INT value;
3301 if (FRV_SYMBOL_REF_TLS_P (x))
3304 switch (GET_CODE (x))
3311 if (GET_CODE (x) != REG)
3317 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3323 if (GET_CODE (x0) != REG
3324 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3325 || GET_CODE (x1) != PLUS
3326 || ! rtx_equal_p (x0, XEXP (x1, 0))
3327 || GET_CODE (XEXP (x1, 1)) != REG
3328 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3335 /* 12 bit immediate */
3340 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3342 /* If we can't use load/store double operations, make sure we can
3343 address the second word. */
3344 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3345 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3354 if (GET_CODE (x0) == SUBREG)
3355 x0 = SUBREG_REG (x0);
3357 if (GET_CODE (x0) != REG)
3360 regno0 = REGNO (x0);
3361 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3364 switch (GET_CODE (x1))
3370 x1 = SUBREG_REG (x1);
3371 if (GET_CODE (x1) != REG)
3377 /* Do not allow reg+reg addressing for modes > 1 word if we
3378 can't depend on having move double instructions. */
3379 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3382 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3386 /* 12 bit immediate */
3391 value = INTVAL (x1);
3392 ret = IN_RANGE_P (value, -2048, 2047);
3394 /* If we can't use load/store double operations, make sure we can
3395 address the second word. */
3396 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3397 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3402 if (!condexec_p && got12_operand (x1, VOIDmode))
3410 if (TARGET_DEBUG_ADDR)
3412 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3413 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3414 (condexec_p) ? ", inside conditional code" : "");
3421 /* Given an ADDR, generate code to inline the PLT. */
3423 gen_inlined_tls_plt (rtx addr)
3426 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3429 dest = gen_reg_rtx (DImode);
3436 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3437 calll #gettlsoff(ADDR)@(gr8, gr0)
3439 emit_insn (gen_tls_lddi (dest, addr, picreg));
3446 sethi.p #gottlsdeschi(ADDR), gr8
3447 setlo #gottlsdesclo(ADDR), gr8
3448 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3449 calll #gettlsoff(ADDR)@(gr8, gr0)
3451 rtx reguse = gen_reg_rtx (Pmode);
3452 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3453 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3456 retval = gen_reg_rtx (Pmode);
3457 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3461 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3462 the destination address. */
3464 gen_tlsmoff (rtx addr, rtx reg)
3466 rtx dest = gen_reg_rtx (Pmode);
3470 /* sethi.p #tlsmoffhi(x), grA
3471 setlo #tlsmofflo(x), grA
3473 dest = gen_reg_rtx (Pmode);
3474 emit_insn (gen_tlsoff_hilo (dest, addr,
3475 GEN_INT (R_FRV_TLSMOFFHI)));
3476 dest = gen_rtx_PLUS (Pmode, dest, reg);
3480 /* addi grB, #tlsmoff12(x), grC
3482 ld/st @(grB, #tlsmoff12(x)), grC
3484 dest = gen_reg_rtx (Pmode);
3485 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3486 GEN_INT (R_FRV_TLSMOFF12)));
3491 /* Generate code for a TLS address. */
3493 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3495 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3496 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3500 case TLS_MODEL_INITIAL_EXEC:
3504 ldi @(gr15, #gottlsoff12(x)), gr5
3506 dest = gen_reg_rtx (Pmode);
3507 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3508 dest = gen_rtx_PLUS (Pmode, tp, dest);
3512 /* -fPIC or anything else.
3514 sethi.p #gottlsoffhi(x), gr14
3515 setlo #gottlsofflo(x), gr14
3516 ld #tlsoff(x)@(gr15, gr14), gr9
3518 rtx tmp = gen_reg_rtx (Pmode);
3519 dest = gen_reg_rtx (Pmode);
3520 emit_insn (gen_tlsoff_hilo (tmp, addr,
3521 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3523 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3524 dest = gen_rtx_PLUS (Pmode, tp, dest);
3527 case TLS_MODEL_LOCAL_DYNAMIC:
3531 if (TARGET_INLINE_PLT)
3532 retval = gen_inlined_tls_plt (GEN_INT (0));
3535 /* call #gettlsoff(0) */
3536 retval = gen_reg_rtx (Pmode);
3537 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3540 reg = gen_reg_rtx (Pmode);
3541 emit_insn (gen_rtx_SET (VOIDmode, reg,
3542 gen_rtx_PLUS (Pmode,
3545 dest = gen_tlsmoff (addr, reg);
3548 dest = gen_reg_rtx (Pmode);
3549 emit_insn (gen_tlsoff_hilo (dest, addr,
3550 GEN_INT (R_FRV_TLSMOFFHI)));
3551 dest = gen_rtx_PLUS (Pmode, dest, reg);
3555 case TLS_MODEL_LOCAL_EXEC:
3556 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3558 case TLS_MODEL_GLOBAL_DYNAMIC:
3562 if (TARGET_INLINE_PLT)
3563 retval = gen_inlined_tls_plt (addr);
3566 /* call #gettlsoff(x) */
3567 retval = gen_reg_rtx (Pmode);
3568 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3570 dest = gen_rtx_PLUS (Pmode, retval, tp);
3581 frv_legitimize_address (rtx x,
3582 rtx oldx ATTRIBUTE_UNUSED,
3583 enum machine_mode mode ATTRIBUTE_UNUSED)
3585 if (GET_CODE (x) == SYMBOL_REF)
3587 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3589 return frv_legitimize_tls_address (x, model);
3595 /* Test whether a local function descriptor is canonical, i.e.,
3596 whether we can use FUNCDESC_GOTOFF to compute the address of the
3600 frv_local_funcdesc_p (rtx fnx)
3603 enum symbol_visibility vis;
3606 if (! SYMBOL_REF_LOCAL_P (fnx))
3609 fn = SYMBOL_REF_DECL (fnx);
3614 vis = DECL_VISIBILITY (fn);
3616 if (vis == VISIBILITY_PROTECTED)
3617 /* Private function descriptors for protected functions are not
3618 canonical. Temporarily change the visibility to global. */
3619 vis = VISIBILITY_DEFAULT;
3620 else if (flag_shlib)
3621 /* If we're already compiling for a shared library (that, unlike
3622 executables, can't assume that the existence of a definition
3623 implies local binding), we can skip the re-testing. */
3626 ret = default_binds_local_p_1 (fn, flag_pic);
3628 DECL_VISIBILITY (fn) = vis;
3633 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3637 frv_gen_GPsym2reg (rtx dest, rtx src)
3639 tree gp = get_identifier ("_gp");
3640 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3642 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3646 unspec_got_name (int i)
3650 case R_FRV_GOT12: return "got12";
3651 case R_FRV_GOTHI: return "gothi";
3652 case R_FRV_GOTLO: return "gotlo";
3653 case R_FRV_FUNCDESC: return "funcdesc";
3654 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3655 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3656 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3657 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3658 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3659 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3660 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3661 case R_FRV_GOTOFF12: return "gotoff12";
3662 case R_FRV_GOTOFFHI: return "gotoffhi";
3663 case R_FRV_GOTOFFLO: return "gotofflo";
3664 case R_FRV_GPREL12: return "gprel12";
3665 case R_FRV_GPRELHI: return "gprelhi";
3666 case R_FRV_GPRELLO: return "gprello";
3667 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3668 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3669 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3670 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3671 case R_FRV_TLSMOFF12: return "tlsmoff12";
3672 case R_FRV_TLSDESCHI: return "tlsdeschi";
3673 case R_FRV_TLSDESCLO: return "tlsdesclo";
3674 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3675 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3676 default: gcc_unreachable ();
3680 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3681 is added inside the relocation operator. */
3684 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3686 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3687 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3688 fputs (")", stream);
3691 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3692 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3693 otherwise return ORIG_X. */
3696 frv_find_base_term (rtx x)
3698 struct frv_unspec unspec;
3700 if (frv_const_unspec_p (x, &unspec)
3701 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3702 return plus_constant (unspec.symbol, unspec.offset);
3707 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3708 the operand is used by a predicated instruction. */
3711 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3713 return ((GET_MODE (op) == mode || mode == VOIDmode)
3714 && GET_CODE (op) == MEM
3715 && frv_legitimate_address_p (mode, XEXP (op, 0),
3716 reload_completed, condexec_p, FALSE));
3720 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3722 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3723 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3729 rvrtx = operands[0];
3733 addr = XEXP (operands[0], 0);
3735 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3736 any calls that would involve a PLT, but can't tell, since we
3737 don't know whether an extern function is going to be provided by
3738 a separate translation unit or imported from a separate module.
3739 When compiling for shared libraries, if the function has default
3740 visibility, we assume it's overridable, so we inline the PLT, but
3741 for executables, we don't really have a way to make a good
3742 decision: a function is as likely to be imported from a shared
3743 library as it is to be defined in the executable itself. We
3744 assume executables will get global functions defined locally,
3745 whereas shared libraries will have them potentially overridden,
3746 so we only inline PLTs when compiling for shared libraries.
3748 In order to mark a function as local to a shared library, any
3749 non-default visibility attribute suffices. Unfortunately,
3750 there's no simple way to tag a function declaration as ``in a
3751 different module'', which we could then use to trigger PLT
3752 inlining on executables. There's -minline-plt, but it affects
3753 all external functions, so one would have to also mark function
3754 declarations available in the same module with non-default
3755 visibility, which is advantageous in itself. */
3756 if (GET_CODE (addr) == SYMBOL_REF
3757 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3761 dest = gen_reg_rtx (SImode);
3763 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3764 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3766 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3767 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3769 cfun->uses_pic_offset_table = TRUE;
3772 else if (GET_CODE (addr) == SYMBOL_REF)
3774 /* These are always either local, or handled through a local
3777 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3778 operands[2], picreg, lr);
3780 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3784 else if (! ldd_address_operand (addr, Pmode))
3785 addr = force_reg (Pmode, addr);
3787 picreg = gen_reg_rtx (DImode);
3788 emit_insn (gen_movdi_ldd (picreg, addr));
3790 if (sibcall && ret_value)
3791 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3793 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3795 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3797 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3801 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3802 process these separately from any offsets, such that we add any
3803 offsets to the function descriptor (the actual pointer), not to the
3804 function address. */
3807 frv_function_symbol_referenced_p (rtx x)
3813 if (GET_CODE (x) == SYMBOL_REF)
3814 return SYMBOL_REF_FUNCTION_P (x);
3816 length = GET_RTX_LENGTH (GET_CODE (x));
3817 format = GET_RTX_FORMAT (GET_CODE (x));
3819 for (j = 0; j < length; ++j)
3824 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3830 if (XVEC (x, j) != 0)
3833 for (k = 0; k < XVECLEN (x, j); ++k)
3834 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3840 /* Nothing to do. */
3848 /* Return true if the memory operand is one that can be conditionally
3852 condexec_memory_operand (rtx op, enum machine_mode mode)
3854 enum machine_mode op_mode = GET_MODE (op);
3857 if (mode != VOIDmode && op_mode != mode)
3872 if (GET_CODE (op) != MEM)
3875 addr = XEXP (op, 0);
3876 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
3879 /* Return true if the bare return instruction can be used outside of the
3880 epilog code. For frv, we only do it if there was no stack allocation. */
3883 direct_return_p (void)
3887 if (!reload_completed)
3890 info = frv_stack_info ();
3891 return (info->total_size == 0);
3896 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3898 if (GET_CODE (src) == SYMBOL_REF)
3900 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3902 src = frv_legitimize_tls_address (src, model);
3908 if (frv_emit_movsi (dest, src))
3917 if (!reload_in_progress
3918 && !reload_completed
3919 && !register_operand (dest, mode)
3920 && !reg_or_0_operand (src, mode))
3921 src = copy_to_mode_reg (mode, src);
3928 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3931 /* Emit code to handle a MOVSI, adding in the small data register or pic
3932 register if needed to load up addresses. Return TRUE if the appropriate
3933 instructions are emitted. */
3936 frv_emit_movsi (rtx dest, rtx src)
3938 int base_regno = -1;
3941 struct frv_unspec old_unspec;
3943 if (!reload_in_progress
3944 && !reload_completed
3945 && !register_operand (dest, SImode)
3946 && (!reg_or_0_operand (src, SImode)
3947 /* Virtual registers will almost always be replaced by an
3948 add instruction, so expose this to CSE by copying to
3949 an intermediate register. */
3950 || (GET_CODE (src) == REG
3951 && IN_RANGE_P (REGNO (src),
3952 FIRST_VIRTUAL_REGISTER,
3953 LAST_VIRTUAL_REGISTER))))
3955 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
3959 /* Explicitly add in the PIC or small data register if needed. */
3960 switch (GET_CODE (src))
3969 /* Using GPREL12, we use a single GOT entry for all symbols
3970 in read-only sections, but trade sequences such as:
3972 sethi #gothi(label), gr#
3973 setlo #gotlo(label), gr#
3978 ld @(gr15,#got12(_gp)), gr#
3979 sethi #gprelhi(label), gr##
3980 setlo #gprello(label), gr##
3983 We may often be able to share gr# for multiple
3984 computations of GPREL addresses, and we may often fold
3985 the final add into the pair of registers of a load or
3986 store instruction, so it's often profitable. Even when
3987 optimizing for size, we're trading a GOT entry for an
3988 additional instruction, which trades GOT space
3989 (read-write) for code size (read-only, shareable), as
3990 long as the symbol is not used in more than two different
3993 With -fpie/-fpic, we'd be trading a single load for a
3994 sequence of 4 instructions, because the offset of the
3995 label can't be assumed to be addressable with 12 bits, so
3996 we don't do this. */
3997 if (TARGET_GPREL_RO)
3998 unspec = R_FRV_GPREL12;
4000 unspec = R_FRV_GOT12;
4003 base_regno = PIC_REGNO;
4008 if (frv_const_unspec_p (src, &old_unspec))
4011 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4014 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4015 emit_move_insn (dest, src);
4020 sym = XEXP (sym, 0);
4021 if (GET_CODE (sym) == PLUS
4022 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4023 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4024 sym = XEXP (sym, 0);
4025 if (GET_CODE (sym) == SYMBOL_REF)
4027 else if (GET_CODE (sym) == LABEL_REF)
4030 goto handle_whatever;
4038 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4042 src = frv_legitimize_tls_address (src, model);
4043 emit_move_insn (dest, src);
4047 if (SYMBOL_REF_FUNCTION_P (sym))
4049 if (frv_local_funcdesc_p (sym))
4050 unspec = R_FRV_FUNCDESC_GOTOFF12;
4052 unspec = R_FRV_FUNCDESC_GOT12;
4056 if (CONSTANT_POOL_ADDRESS_P (sym))
4057 switch (GET_CODE (get_pool_constant (sym)))
4064 unspec = R_FRV_GOTOFF12;
4069 if (TARGET_GPREL_RO)
4070 unspec = R_FRV_GPREL12;
4072 unspec = R_FRV_GOT12;
4075 else if (SYMBOL_REF_LOCAL_P (sym)
4076 && !SYMBOL_REF_EXTERNAL_P (sym)
4077 && SYMBOL_REF_DECL (sym)
4078 && (!DECL_P (SYMBOL_REF_DECL (sym))
4079 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4081 tree decl = SYMBOL_REF_DECL (sym);
4082 tree init = TREE_CODE (decl) == VAR_DECL
4083 ? DECL_INITIAL (decl)
4084 : TREE_CODE (decl) == CONSTRUCTOR
4087 bool named_section, readonly;
4089 if (init && init != error_mark_node)
4090 reloc = compute_reloc_for_constant (init);
4092 named_section = TREE_CODE (decl) == VAR_DECL
4093 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4094 readonly = decl_readonly_section (decl, reloc);
4097 unspec = R_FRV_GOT12;
4099 unspec = R_FRV_GOTOFF12;
4100 else if (readonly && TARGET_GPREL_RO)
4101 unspec = R_FRV_GPREL12;
4103 unspec = R_FRV_GOT12;
4106 unspec = R_FRV_GOT12;
4110 else if (SYMBOL_REF_SMALL_P (sym))
4111 base_regno = SDA_BASE_REG;
4114 base_regno = PIC_REGNO;
4119 if (base_regno >= 0)
4121 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4122 emit_insn (gen_symGOTOFF2reg (dest, src,
4123 gen_rtx_REG (Pmode, base_regno),
4124 GEN_INT (R_FRV_GPREL12)));
4126 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4127 gen_rtx_REG (Pmode, base_regno),
4128 GEN_INT (R_FRV_GPREL12)));
4129 if (base_regno == PIC_REGNO)
4130 cfun->uses_pic_offset_table = TRUE;
4138 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4139 new uses of it once reload has begun. */
4140 gcc_assert (!reload_in_progress && !reload_completed);
4144 case R_FRV_GOTOFF12:
4145 if (!frv_small_data_reloc_p (sym, unspec))
4146 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4149 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4152 if (!frv_small_data_reloc_p (sym, unspec))
4153 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4156 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4158 case R_FRV_FUNCDESC_GOTOFF12:
4160 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4163 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4167 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4170 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4174 cfun->uses_pic_offset_table = TRUE;
4183 /* Return a string to output a single word move. */
4186 output_move_single (rtx operands[], rtx insn)
4188 rtx dest = operands[0];
4189 rtx src = operands[1];
4191 if (GET_CODE (dest) == REG)
4193 int dest_regno = REGNO (dest);
4194 enum machine_mode mode = GET_MODE (dest);
4196 if (GPR_P (dest_regno))
4198 if (GET_CODE (src) == REG)
4200 /* gpr <- some sort of register */
4201 int src_regno = REGNO (src);
4203 if (GPR_P (src_regno))
4204 return "mov %1, %0";
4206 else if (FPR_P (src_regno))
4207 return "movfg %1, %0";
4209 else if (SPR_P (src_regno))
4210 return "movsg %1, %0";
4213 else if (GET_CODE (src) == MEM)
4222 return "ldsb%I1%U1 %M1,%0";
4225 return "ldsh%I1%U1 %M1,%0";
4229 return "ld%I1%U1 %M1, %0";
4233 else if (GET_CODE (src) == CONST_INT
4234 || GET_CODE (src) == CONST_DOUBLE)
4236 /* gpr <- integer/floating constant */
4237 HOST_WIDE_INT value;
4239 if (GET_CODE (src) == CONST_INT)
4240 value = INTVAL (src);
4242 else if (mode == SFmode)
4247 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4248 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4253 value = CONST_DOUBLE_LOW (src);
4255 if (IN_RANGE_P (value, -32768, 32767))
4256 return "setlos %1, %0";
4261 else if (GET_CODE (src) == SYMBOL_REF
4262 || GET_CODE (src) == LABEL_REF
4263 || GET_CODE (src) == CONST)
4269 else if (FPR_P (dest_regno))
4271 if (GET_CODE (src) == REG)
4273 /* fpr <- some sort of register */
4274 int src_regno = REGNO (src);
4276 if (GPR_P (src_regno))
4277 return "movgf %1, %0";
4279 else if (FPR_P (src_regno))
4281 if (TARGET_HARD_FLOAT)
4282 return "fmovs %1, %0";
4284 return "mor %1, %1, %0";
4288 else if (GET_CODE (src) == MEM)
4297 return "ldbf%I1%U1 %M1,%0";
4300 return "ldhf%I1%U1 %M1,%0";
4304 return "ldf%I1%U1 %M1, %0";
4308 else if (ZERO_P (src))
4309 return "movgf %., %0";
4312 else if (SPR_P (dest_regno))
4314 if (GET_CODE (src) == REG)
4316 /* spr <- some sort of register */
4317 int src_regno = REGNO (src);
4319 if (GPR_P (src_regno))
4320 return "movgs %1, %0";
4322 else if (ZERO_P (src))
4323 return "movgs %., %0";
4327 else if (GET_CODE (dest) == MEM)
4329 if (GET_CODE (src) == REG)
4331 int src_regno = REGNO (src);
4332 enum machine_mode mode = GET_MODE (dest);
4334 if (GPR_P (src_regno))
4342 return "stb%I0%U0 %1, %M0";
4345 return "sth%I0%U0 %1, %M0";
4349 return "st%I0%U0 %1, %M0";
4353 else if (FPR_P (src_regno))
4361 return "stbf%I0%U0 %1, %M0";
4364 return "sthf%I0%U0 %1, %M0";
4368 return "stf%I0%U0 %1, %M0";
4373 else if (ZERO_P (src))
4375 switch (GET_MODE (dest))
4381 return "stb%I0%U0 %., %M0";
4384 return "sth%I0%U0 %., %M0";
4388 return "st%I0%U0 %., %M0";
4393 fatal_insn ("Bad output_move_single operand", insn);
4398 /* Return a string to output a double word move. */
4401 output_move_double (rtx operands[], rtx insn)
4403 rtx dest = operands[0];
4404 rtx src = operands[1];
4405 enum machine_mode mode = GET_MODE (dest);
4407 if (GET_CODE (dest) == REG)
4409 int dest_regno = REGNO (dest);
4411 if (GPR_P (dest_regno))
4413 if (GET_CODE (src) == REG)
4415 /* gpr <- some sort of register */
4416 int src_regno = REGNO (src);
4418 if (GPR_P (src_regno))
4421 else if (FPR_P (src_regno))
4423 if (((dest_regno - GPR_FIRST) & 1) == 0
4424 && ((src_regno - FPR_FIRST) & 1) == 0)
4425 return "movfgd %1, %0";
4431 else if (GET_CODE (src) == MEM)
4434 if (dbl_memory_one_insn_operand (src, mode))
4435 return "ldd%I1%U1 %M1, %0";
4440 else if (GET_CODE (src) == CONST_INT
4441 || GET_CODE (src) == CONST_DOUBLE)
4445 else if (FPR_P (dest_regno))
4447 if (GET_CODE (src) == REG)
4449 /* fpr <- some sort of register */
4450 int src_regno = REGNO (src);
4452 if (GPR_P (src_regno))
4454 if (((dest_regno - FPR_FIRST) & 1) == 0
4455 && ((src_regno - GPR_FIRST) & 1) == 0)
4456 return "movgfd %1, %0";
4461 else if (FPR_P (src_regno))
4464 && ((dest_regno - FPR_FIRST) & 1) == 0
4465 && ((src_regno - FPR_FIRST) & 1) == 0)
4466 return "fmovd %1, %0";
4472 else if (GET_CODE (src) == MEM)
4475 if (dbl_memory_one_insn_operand (src, mode))
4476 return "lddf%I1%U1 %M1, %0";
4481 else if (ZERO_P (src))
4486 else if (GET_CODE (dest) == MEM)
4488 if (GET_CODE (src) == REG)
4490 int src_regno = REGNO (src);
4492 if (GPR_P (src_regno))
4494 if (((src_regno - GPR_FIRST) & 1) == 0
4495 && dbl_memory_one_insn_operand (dest, mode))
4496 return "std%I0%U0 %1, %M0";
4501 if (FPR_P (src_regno))
4503 if (((src_regno - FPR_FIRST) & 1) == 0
4504 && dbl_memory_one_insn_operand (dest, mode))
4505 return "stdf%I0%U0 %1, %M0";
4511 else if (ZERO_P (src))
4513 if (dbl_memory_one_insn_operand (dest, mode))
4514 return "std%I0%U0 %., %M0";
4520 fatal_insn ("Bad output_move_double operand", insn);
4525 /* Return a string to output a single word conditional move.
4526 Operand0 -- EQ/NE of ccr register and 0
4527 Operand1 -- CCR register
4528 Operand2 -- destination
4529 Operand3 -- source */
4532 output_condmove_single (rtx operands[], rtx insn)
4534 rtx dest = operands[2];
4535 rtx src = operands[3];
4537 if (GET_CODE (dest) == REG)
4539 int dest_regno = REGNO (dest);
4540 enum machine_mode mode = GET_MODE (dest);
4542 if (GPR_P (dest_regno))
4544 if (GET_CODE (src) == REG)
4546 /* gpr <- some sort of register */
4547 int src_regno = REGNO (src);
4549 if (GPR_P (src_regno))
4550 return "cmov %z3, %2, %1, %e0";
4552 else if (FPR_P (src_regno))
4553 return "cmovfg %3, %2, %1, %e0";
4556 else if (GET_CODE (src) == MEM)
4565 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4568 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4572 return "cld%I3%U3 %M3, %2, %1, %e0";
4576 else if (ZERO_P (src))
4577 return "cmov %., %2, %1, %e0";
4580 else if (FPR_P (dest_regno))
4582 if (GET_CODE (src) == REG)
4584 /* fpr <- some sort of register */
4585 int src_regno = REGNO (src);
4587 if (GPR_P (src_regno))
4588 return "cmovgf %3, %2, %1, %e0";
4590 else if (FPR_P (src_regno))
4592 if (TARGET_HARD_FLOAT)
4593 return "cfmovs %3,%2,%1,%e0";
4595 return "cmor %3, %3, %2, %1, %e0";
4599 else if (GET_CODE (src) == MEM)
4602 if (mode == SImode || mode == SFmode)
4603 return "cldf%I3%U3 %M3, %2, %1, %e0";
4606 else if (ZERO_P (src))
4607 return "cmovgf %., %2, %1, %e0";
4611 else if (GET_CODE (dest) == MEM)
4613 if (GET_CODE (src) == REG)
4615 int src_regno = REGNO (src);
4616 enum machine_mode mode = GET_MODE (dest);
4618 if (GPR_P (src_regno))
4626 return "cstb%I2%U2 %3, %M2, %1, %e0";
4629 return "csth%I2%U2 %3, %M2, %1, %e0";
4633 return "cst%I2%U2 %3, %M2, %1, %e0";
4637 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4638 return "cstf%I2%U2 %3, %M2, %1, %e0";
4641 else if (ZERO_P (src))
4643 enum machine_mode mode = GET_MODE (dest);
4650 return "cstb%I2%U2 %., %M2, %1, %e0";
4653 return "csth%I2%U2 %., %M2, %1, %e0";
4657 return "cst%I2%U2 %., %M2, %1, %e0";
4662 fatal_insn ("Bad output_condmove_single operand", insn);
4667 /* Emit the appropriate code to do a comparison, returning the register the
4668 comparison was done it. */
4671 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4673 enum machine_mode cc_mode;
4676 /* Floating point doesn't have comparison against a constant. */
4677 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4678 op1 = force_reg (GET_MODE (op0), op1);
4680 /* Possibly disable using anything but a fixed register in order to work
4681 around cse moving comparisons past function calls. */
4682 cc_mode = SELECT_CC_MODE (test, op0, op1);
4683 cc_reg = ((TARGET_ALLOC_CC)
4684 ? gen_reg_rtx (cc_mode)
4685 : gen_rtx_REG (cc_mode,
4686 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4688 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4689 gen_rtx_COMPARE (cc_mode, op0, op1)));
4695 /* Emit code for a conditional branch. The comparison operands were previously
4696 stored in frv_compare_op0 and frv_compare_op1.
4698 XXX: I originally wanted to add a clobber of a CCR register to use in
4699 conditional execution, but that confuses the rest of the compiler. */
4702 frv_emit_cond_branch (enum rtx_code test, rtx label)
4707 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4708 enum machine_mode cc_mode = GET_MODE (cc_reg);
4710 /* Branches generate:
4712 (if_then_else (<test>, <cc_reg>, (const_int 0))
4713 (label_ref <branch_label>)
4715 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
4716 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4717 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4718 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4723 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
4724 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
4727 frv_emit_scc (enum rtx_code test, rtx target)
4733 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4735 /* SCC instructions generate:
4736 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4737 (clobber (<ccr_reg>))]) */
4738 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4739 set = gen_rtx_SET (VOIDmode, target, test_rtx);
4741 cr_reg = ((TARGET_ALLOC_CC)
4742 ? gen_reg_rtx (CC_CCRmode)
4743 : gen_rtx_REG (CC_CCRmode,
4744 ((GET_MODE (cc_reg) == CC_FPmode)
4748 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4749 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4754 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4755 the separate insns. */
4758 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4764 /* Set the appropriate CCR bit. */
4765 emit_insn (gen_rtx_SET (VOIDmode,
4767 gen_rtx_fmt_ee (GET_CODE (test),
4772 /* Move the value into the destination. */
4773 emit_move_insn (dest, GEN_INT (value));
4775 /* Move 0 into the destination if the test failed */
4776 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4777 gen_rtx_EQ (GET_MODE (cr_reg),
4780 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4782 /* Finish up, return sequence. */
4789 /* Emit the code for a conditional move, return TRUE if we could do the
4793 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4800 enum rtx_code test = GET_CODE (test_rtx);
4801 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4802 enum machine_mode cc_mode = GET_MODE (cc_reg);
4804 /* Conditional move instructions generate:
4805 (parallel [(set <target>
4806 (if_then_else (<test> <cc_reg> (const_int 0))
4809 (clobber (<ccr_reg>))]) */
4811 /* Handle various cases of conditional move involving two constants. */
4812 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4814 HOST_WIDE_INT value1 = INTVAL (src1);
4815 HOST_WIDE_INT value2 = INTVAL (src2);
4817 /* Having 0 as one of the constants can be done by loading the other
4818 constant, and optionally moving in gr0. */
4819 if (value1 == 0 || value2 == 0)
4822 /* If the first value is within an addi range and also the difference
4823 between the two fits in an addi's range, load up the difference, then
4824 conditionally move in 0, and then unconditionally add the first
4826 else if (IN_RANGE_P (value1, -2048, 2047)
4827 && IN_RANGE_P (value2 - value1, -2048, 2047))
4830 /* If neither condition holds, just force the constant into a
4834 src1 = force_reg (GET_MODE (dest), src1);
4835 src2 = force_reg (GET_MODE (dest), src2);
4839 /* If one value is a register, insure the other value is either 0 or a
4843 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4844 src1 = force_reg (GET_MODE (dest), src1);
4846 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4847 src2 = force_reg (GET_MODE (dest), src2);
4850 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4851 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4853 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4855 cr_reg = ((TARGET_ALLOC_CC)
4856 ? gen_reg_rtx (CC_CCRmode)
4857 : gen_rtx_REG (CC_CCRmode,
4858 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4860 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4861 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4866 /* Split a conditional move into constituent parts, returning a SEQUENCE
4867 containing all of the insns. */
4870 frv_split_cond_move (rtx operands[])
4872 rtx dest = operands[0];
4873 rtx test = operands[1];
4874 rtx cc_reg = operands[2];
4875 rtx src1 = operands[3];
4876 rtx src2 = operands[4];
4877 rtx cr_reg = operands[5];
4879 enum machine_mode cr_mode = GET_MODE (cr_reg);
4883 /* Set the appropriate CCR bit. */
4884 emit_insn (gen_rtx_SET (VOIDmode,
4886 gen_rtx_fmt_ee (GET_CODE (test),
4891 /* Handle various cases of conditional move involving two constants. */
4892 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4894 HOST_WIDE_INT value1 = INTVAL (src1);
4895 HOST_WIDE_INT value2 = INTVAL (src2);
4897 /* Having 0 as one of the constants can be done by loading the other
4898 constant, and optionally moving in gr0. */
4901 emit_move_insn (dest, src2);
4902 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4903 gen_rtx_NE (cr_mode, cr_reg,
4905 gen_rtx_SET (VOIDmode, dest, src1)));
4908 else if (value2 == 0)
4910 emit_move_insn (dest, src1);
4911 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4912 gen_rtx_EQ (cr_mode, cr_reg,
4914 gen_rtx_SET (VOIDmode, dest, src2)));
4917 /* If the first value is within an addi range and also the difference
4918 between the two fits in an addi's range, load up the difference, then
4919 conditionally move in 0, and then unconditionally add the first
4921 else if (IN_RANGE_P (value1, -2048, 2047)
4922 && IN_RANGE_P (value2 - value1, -2048, 2047))
4924 rtx dest_si = ((GET_MODE (dest) == SImode)
4926 : gen_rtx_SUBREG (SImode, dest, 0));
4928 emit_move_insn (dest_si, GEN_INT (value2 - value1));
4929 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4930 gen_rtx_NE (cr_mode, cr_reg,
4932 gen_rtx_SET (VOIDmode, dest_si,
4934 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
4942 /* Emit the conditional move for the test being true if needed. */
4943 if (! rtx_equal_p (dest, src1))
4944 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4945 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
4946 gen_rtx_SET (VOIDmode, dest, src1)));
4948 /* Emit the conditional move for the test being false if needed. */
4949 if (! rtx_equal_p (dest, src2))
4950 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4951 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
4952 gen_rtx_SET (VOIDmode, dest, src2)));
4955 /* Finish up, return sequence. */
4962 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
4963 memory location that is not known to be dword-aligned. */
4965 frv_split_double_load (rtx dest, rtx source)
4967 int regno = REGNO (dest);
4968 rtx dest1 = gen_highpart (SImode, dest);
4969 rtx dest2 = gen_lowpart (SImode, dest);
4970 rtx address = XEXP (source, 0);
4972 /* If the address is pre-modified, load the lower-numbered register
4973 first, then load the other register using an integer offset from
4974 the modified base register. This order should always be safe,
4975 since the pre-modification cannot affect the same registers as the
4978 The situation for other loads is more complicated. Loading one
4979 of the registers could affect the value of ADDRESS, so we must
4980 be careful which order we do them in. */
4981 if (GET_CODE (address) == PRE_MODIFY
4982 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
4984 /* It is safe to load the lower-numbered register first. */
4985 emit_move_insn (dest1, change_address (source, SImode, NULL));
4986 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
4990 /* ADDRESS is not pre-modified and the address depends on the
4991 lower-numbered register. Load the higher-numbered register
4993 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
4994 emit_move_insn (dest1, change_address (source, SImode, NULL));
4998 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
4999 and SOURCE is either a double register or the constant zero. */
5001 frv_split_double_store (rtx dest, rtx source)
5003 rtx dest1 = change_address (dest, SImode, NULL);
5004 rtx dest2 = frv_index_memory (dest, SImode, 1);
5005 if (ZERO_P (source))
5007 emit_move_insn (dest1, CONST0_RTX (SImode));
5008 emit_move_insn (dest2, CONST0_RTX (SImode));
5012 emit_move_insn (dest1, gen_highpart (SImode, source));
5013 emit_move_insn (dest2, gen_lowpart (SImode, source));
5018 /* Split a min/max operation returning a SEQUENCE containing all of the
5022 frv_split_minmax (rtx operands[])
5024 rtx dest = operands[0];
5025 rtx minmax = operands[1];
5026 rtx src1 = operands[2];
5027 rtx src2 = operands[3];
5028 rtx cc_reg = operands[4];
5029 rtx cr_reg = operands[5];
5031 enum rtx_code test_code;
5032 enum machine_mode cr_mode = GET_MODE (cr_reg);
5036 /* Figure out which test to use. */
5037 switch (GET_CODE (minmax))
5042 case SMIN: test_code = LT; break;
5043 case SMAX: test_code = GT; break;
5044 case UMIN: test_code = LTU; break;
5045 case UMAX: test_code = GTU; break;
5048 /* Issue the compare instruction. */
5049 emit_insn (gen_rtx_SET (VOIDmode,
5051 gen_rtx_COMPARE (GET_MODE (cc_reg),
5054 /* Set the appropriate CCR bit. */
5055 emit_insn (gen_rtx_SET (VOIDmode,
5057 gen_rtx_fmt_ee (test_code,
5062 /* If are taking the min/max of a nonzero constant, load that first, and
5063 then do a conditional move of the other value. */
5064 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5066 gcc_assert (!rtx_equal_p (dest, src1));
5068 emit_move_insn (dest, src2);
5069 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5070 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5071 gen_rtx_SET (VOIDmode, dest, src1)));
5074 /* Otherwise, do each half of the move. */
5077 /* Emit the conditional move for the test being true if needed. */
5078 if (! rtx_equal_p (dest, src1))
5079 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5080 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5081 gen_rtx_SET (VOIDmode, dest, src1)));
5083 /* Emit the conditional move for the test being false if needed. */
5084 if (! rtx_equal_p (dest, src2))
5085 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5086 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5087 gen_rtx_SET (VOIDmode, dest, src2)));
5090 /* Finish up, return sequence. */
5097 /* Split an integer abs operation returning a SEQUENCE containing all of the
5101 frv_split_abs (rtx operands[])
5103 rtx dest = operands[0];
5104 rtx src = operands[1];
5105 rtx cc_reg = operands[2];
5106 rtx cr_reg = operands[3];
5111 /* Issue the compare < 0 instruction. */
5112 emit_insn (gen_rtx_SET (VOIDmode,
5114 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5116 /* Set the appropriate CCR bit. */
5117 emit_insn (gen_rtx_SET (VOIDmode,
5119 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5121 /* Emit the conditional negate if the value is negative. */
5122 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5123 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5124 gen_negsi2 (dest, src)));
5126 /* Emit the conditional move for the test being false if needed. */
5127 if (! rtx_equal_p (dest, src))
5128 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5129 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5130 gen_rtx_SET (VOIDmode, dest, src)));
5132 /* Finish up, return sequence. */
5139 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5140 register used in an insn. */
5143 frv_clear_registers_used (rtx *ptr, void *data)
5145 if (GET_CODE (*ptr) == REG)
5147 int regno = REGNO (*ptr);
5148 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5150 if (regno < FIRST_PSEUDO_REGISTER)
5152 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5154 while (regno < reg_max)
5156 CLEAR_HARD_REG_BIT (*p_regs, regno);
5166 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5168 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5169 initialize the static storage. */
5171 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5173 frv_ifcvt.added_insns_list = NULL_RTX;
5174 frv_ifcvt.cur_scratch_regs = 0;
5175 frv_ifcvt.num_nested_cond_exec = 0;
5176 frv_ifcvt.cr_reg = NULL_RTX;
5177 frv_ifcvt.nested_cc_reg = NULL_RTX;
5178 frv_ifcvt.extra_int_cr = NULL_RTX;
5179 frv_ifcvt.extra_fp_cr = NULL_RTX;
5180 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5184 /* Internal function to add a potential insn to the list of insns to be inserted
5185 if the conditional execution conversion is successful. */
5188 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5190 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5192 link->jump = before_p; /* Mark to add this before or after insn. */
5193 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5194 frv_ifcvt.added_insns_list);
5196 if (TARGET_DEBUG_COND_EXEC)
5199 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5200 (before_p) ? "before" : "after",
5201 (int)INSN_UID (insn));
5203 debug_rtx (pattern);
5208 /* A C expression to modify the code described by the conditional if
5209 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5210 FALSE_EXPR for converting if-then and if-then-else code to conditional
5211 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5212 tests cannot be converted. */
5215 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5217 basic_block test_bb = ce_info->test_bb; /* test basic block */
5218 basic_block then_bb = ce_info->then_bb; /* THEN */
5219 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5220 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5221 rtx true_expr = *p_true;
5225 enum machine_mode mode = GET_MODE (true_expr);
5229 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5231 rtx sub_cond_exec_reg;
5233 enum rtx_code code_true;
5234 enum rtx_code code_false;
5235 enum reg_class cc_class;
5236 enum reg_class cr_class;
5239 reg_set_iterator rsi;
5241 /* Make sure we are only dealing with hard registers. Also honor the
5242 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5244 if (!reload_completed || !TARGET_COND_EXEC
5245 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5248 /* Figure out which registers we can allocate for our own purposes. Only
5249 consider registers that are not preserved across function calls and are
5250 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5251 if we did not need to use them in reloading other registers. */
5252 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5253 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5254 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5255 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5256 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5258 /* If this is a nested IF, we need to discover whether the CC registers that
5259 are set/used inside of the block are used anywhere else. If not, we can
5260 change them to be the CC register that is paired with the CR register that
5261 controls the outermost IF block. */
5262 if (ce_info->pass > 1)
5264 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5265 for (j = CC_FIRST; j <= CC_LAST; j++)
5266 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5268 if (REGNO_REG_SET_P (then_bb->il.rtl->global_live_at_start, j))
5272 && REGNO_REG_SET_P (else_bb->il.rtl->global_live_at_start, j))
5276 && REGNO_REG_SET_P (join_bb->il.rtl->global_live_at_start, j))
5279 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5283 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5284 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5286 frv_ifcvt.added_insns_list = NULL_RTX;
5287 frv_ifcvt.cur_scratch_regs = 0;
5289 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5290 * sizeof (basic_block));
5296 /* Remove anything live at the beginning of the join block from being
5297 available for allocation. */
5298 EXECUTE_IF_SET_IN_REG_SET (join_bb->il.rtl->global_live_at_start, 0, regno, rsi)
5300 if (regno < FIRST_PSEUDO_REGISTER)
5301 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5305 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5307 if (ce_info->num_multiple_test_blocks)
5309 basic_block multiple_test_bb = ce_info->last_test_bb;
5311 while (multiple_test_bb != test_bb)
5313 bb[num_bb++] = multiple_test_bb;
5314 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5318 /* Add in the THEN and ELSE blocks to be scanned. */
5319 bb[num_bb++] = then_bb;
5321 bb[num_bb++] = else_bb;
5323 sub_cond_exec_reg = NULL_RTX;
5324 frv_ifcvt.num_nested_cond_exec = 0;
5326 /* Scan all of the blocks for registers that must not be allocated. */
5327 for (j = 0; j < num_bb; j++)
5329 rtx last_insn = BB_END (bb[j]);
5330 rtx insn = BB_HEAD (bb[j]);
5334 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5335 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5337 (int) INSN_UID (BB_HEAD (bb[j])),
5338 (int) INSN_UID (BB_END (bb[j])));
5340 /* Anything live at the beginning of the block is obviously unavailable
5342 EXECUTE_IF_SET_IN_REG_SET (bb[j]->il.rtl->global_live_at_start, 0, regno, rsi)
5344 if (regno < FIRST_PSEUDO_REGISTER)
5345 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5348 /* Loop through the insns in the block. */
5351 /* Mark any new registers that are created as being unavailable for
5352 allocation. Also see if the CC register used in nested IFs can be
5358 int skip_nested_if = FALSE;
5360 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5361 (void *)&tmp_reg->regs);
5363 pattern = PATTERN (insn);
5364 if (GET_CODE (pattern) == COND_EXEC)
5366 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5368 if (reg != sub_cond_exec_reg)
5370 sub_cond_exec_reg = reg;
5371 frv_ifcvt.num_nested_cond_exec++;
5375 set = single_set_pattern (pattern);
5378 rtx dest = SET_DEST (set);
5379 rtx src = SET_SRC (set);
5381 if (GET_CODE (dest) == REG)
5383 int regno = REGNO (dest);
5384 enum rtx_code src_code = GET_CODE (src);
5386 if (CC_P (regno) && src_code == COMPARE)
5387 skip_nested_if = TRUE;
5389 else if (CR_P (regno)
5390 && (src_code == IF_THEN_ELSE
5391 || COMPARISON_P (src)))
5392 skip_nested_if = TRUE;
5396 if (! skip_nested_if)
5397 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5398 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5401 if (insn == last_insn)
5404 insn = NEXT_INSN (insn);
5408 /* If this is a nested if, rewrite the CC registers that are available to
5409 include the ones that can be rewritten, to increase the chance of being
5410 able to allocate a paired CC/CR register combination. */
5411 if (ce_info->pass > 1)
5413 for (j = CC_FIRST; j <= CC_LAST; j++)
5414 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5415 SET_HARD_REG_BIT (tmp_reg->regs, j);
5417 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5423 fprintf (dump_file, "Available GPRs: ");
5425 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5426 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5428 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5429 if (++num_gprs > GPR_TEMP_NUM+2)
5433 fprintf (dump_file, "%s\nAvailable CRs: ",
5434 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5436 for (j = CR_FIRST; j <= CR_LAST; j++)
5437 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5438 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5440 fputs ("\n", dump_file);
5442 if (ce_info->pass > 1)
5444 fprintf (dump_file, "Modifiable CCs: ");
5445 for (j = CC_FIRST; j <= CC_LAST; j++)
5446 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5447 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5449 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5450 frv_ifcvt.num_nested_cond_exec);
5454 /* Allocate the appropriate temporary condition code register. Try to
5455 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5456 that conditional cmp's can be done. */
5457 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5459 cr_class = ICR_REGS;
5460 cc_class = ICC_REGS;
5461 cc_first = ICC_FIRST;
5464 else if (mode == CC_FPmode)
5466 cr_class = FCR_REGS;
5467 cc_class = FCC_REGS;
5468 cc_first = FCC_FIRST;
5473 cc_first = cc_last = 0;
5474 cr_class = cc_class = NO_REGS;
5477 cc = XEXP (true_expr, 0);
5478 nested_cc = cr = NULL_RTX;
5479 if (cc_class != NO_REGS)
5481 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5482 so we can execute a csubcc/caddcc/cfcmps instruction. */
5485 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5487 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5489 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5490 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5492 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5493 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5496 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5497 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5507 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5514 "Will use %s for conditional execution, %s for nested comparisons\n",
5515 reg_names[ REGNO (cr)],
5516 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5518 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5519 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5520 bit being true. We don't do this for floating point, because of NaNs. */
5521 code = GET_CODE (true_expr);
5522 if (GET_MODE (cc) != CC_FPmode)
5524 code = reverse_condition (code);
5534 check_insn = gen_rtx_SET (VOIDmode, cr,
5535 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5537 /* Record the check insn to be inserted later. */
5538 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5540 /* Update the tests. */
5541 frv_ifcvt.cr_reg = cr;
5542 frv_ifcvt.nested_cc_reg = nested_cc;
5543 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5544 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5547 /* Fail, don't do this conditional execution. */
5550 *p_false = NULL_RTX;
5552 fprintf (dump_file, "Disabling this conditional execution.\n");
5558 /* A C expression to modify the code described by the conditional if
5559 information CE_INFO, for the basic block BB, possibly updating the tests in
5560 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5561 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5562 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5564 /* p_true and p_false are given expressions of the form:
5566 (and (eq:CC_CCR (reg:CC_CCR)
5572 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5577 rtx old_true = XEXP (*p_true, 0);
5578 rtx old_false = XEXP (*p_false, 0);
5579 rtx true_expr = XEXP (*p_true, 1);
5580 rtx false_expr = XEXP (*p_false, 1);
5583 rtx cr = XEXP (old_true, 0);
5585 rtx new_cr = NULL_RTX;
5586 rtx *p_new_cr = (rtx *)0;
5590 enum reg_class cr_class;
5591 enum machine_mode mode = GET_MODE (true_expr);
5592 rtx (*logical_func)(rtx, rtx, rtx);
5594 if (TARGET_DEBUG_COND_EXEC)
5597 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5598 ce_info->and_and_p ? "&&" : "||");
5600 debug_rtx (*p_true);
5602 fputs ("\nfalse insn:\n", stderr);
5603 debug_rtx (*p_false);
5606 if (!TARGET_MULTI_CE)
5609 if (GET_CODE (cr) != REG)
5612 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5614 cr_class = ICR_REGS;
5615 p_new_cr = &frv_ifcvt.extra_int_cr;
5617 else if (mode == CC_FPmode)
5619 cr_class = FCR_REGS;
5620 p_new_cr = &frv_ifcvt.extra_fp_cr;
5625 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5626 more &&/|| tests. */
5630 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5631 CC_CCRmode, TRUE, TRUE);
5636 if (ce_info->and_and_p)
5638 old_test = old_false;
5639 test_expr = true_expr;
5640 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5641 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5642 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5646 old_test = old_false;
5647 test_expr = false_expr;
5648 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5649 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5650 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5653 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5654 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5656 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5658 /* Now add the conditional check insn. */
5659 cc = XEXP (test_expr, 0);
5660 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5661 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5663 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5665 /* Add the new check insn to the list of check insns that need to be
5667 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5669 if (TARGET_DEBUG_COND_EXEC)
5671 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5674 debug_rtx (*p_true);
5676 fputs ("\nfalse insn:\n", stderr);
5677 debug_rtx (*p_false);
5683 *p_true = *p_false = NULL_RTX;
5685 /* If we allocated a CR register, release it. */
5688 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5689 *p_new_cr = NULL_RTX;
5692 if (TARGET_DEBUG_COND_EXEC)
5693 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5699 /* Return a register which will be loaded with a value if an IF block is
5700 converted to conditional execution. This is used to rewrite instructions
5701 that use constants to ones that just use registers. */
5704 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5706 int num_alloc = frv_ifcvt.cur_scratch_regs;
5710 /* We know gr0 == 0, so replace any errant uses. */
5711 if (value == const0_rtx)
5712 return gen_rtx_REG (SImode, GPR_FIRST);
5714 /* First search all registers currently loaded to see if we have an
5715 applicable constant. */
5716 if (CONSTANT_P (value)
5717 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5719 for (i = 0; i < num_alloc; i++)
5721 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5722 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5726 /* Have we exhausted the number of registers available? */
5727 if (num_alloc >= GPR_TEMP_NUM)
5730 fprintf (dump_file, "Too many temporary registers allocated\n");
5735 /* Allocate the new register. */
5736 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5740 fputs ("Could not find a scratch register\n", dump_file);
5745 frv_ifcvt.cur_scratch_regs++;
5746 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5750 if (GET_CODE (value) == CONST_INT)
5751 fprintf (dump_file, "Register %s will hold %ld\n",
5752 reg_names[ REGNO (reg)], (long)INTVAL (value));
5754 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5755 fprintf (dump_file, "Register %s will hold LR\n",
5756 reg_names[ REGNO (reg)]);
5759 fprintf (dump_file, "Register %s will hold a saved value\n",
5760 reg_names[ REGNO (reg)]);
5767 /* Update a MEM used in conditional code that might contain an offset to put
5768 the offset into a scratch register, so that the conditional load/store
5769 operations can be used. This function returns the original pointer if the
5770 MEM is valid to use in conditional code, NULL if we can't load up the offset
5771 into a temporary register, or the new MEM if we were successful. */
5774 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5776 rtx addr = XEXP (mem, 0);
5778 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
5780 if (GET_CODE (addr) == PLUS)
5782 rtx addr_op0 = XEXP (addr, 0);
5783 rtx addr_op1 = XEXP (addr, 1);
5785 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5787 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5791 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5798 else if (CONSTANT_P (addr))
5799 addr = frv_ifcvt_load_value (addr, insn);
5804 if (addr == NULL_RTX)
5807 else if (XEXP (mem, 0) != addr)
5808 return change_address (mem, mode, addr);
5815 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5816 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5819 single_set_pattern (rtx pattern)
5824 if (GET_CODE (pattern) == COND_EXEC)
5825 pattern = COND_EXEC_CODE (pattern);
5827 if (GET_CODE (pattern) == SET)
5830 else if (GET_CODE (pattern) == PARALLEL)
5832 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5834 rtx sub = XVECEXP (pattern, 0, i);
5836 switch (GET_CODE (sub))
5860 /* A C expression to modify the code described by the conditional if
5861 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5862 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5863 insn cannot be converted to be executed conditionally. */
5866 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5870 rtx orig_ce_pattern = pattern;
5876 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5878 test = COND_EXEC_TEST (pattern);
5879 if (GET_CODE (test) == AND)
5881 rtx cr = frv_ifcvt.cr_reg;
5884 op0 = XEXP (test, 0);
5885 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5888 op1 = XEXP (test, 1);
5889 test_reg = XEXP (op1, 0);
5890 if (GET_CODE (test_reg) != REG)
5893 /* Is this the first nested if block in this sequence? If so, generate
5894 an andcr or andncr. */
5895 if (! frv_ifcvt.last_nested_if_cr)
5899 frv_ifcvt.last_nested_if_cr = test_reg;
5900 if (GET_CODE (op0) == NE)
5901 and_op = gen_andcr (test_reg, cr, test_reg);
5903 and_op = gen_andncr (test_reg, cr, test_reg);
5905 frv_ifcvt_add_insn (and_op, insn, TRUE);
5908 /* If this isn't the first statement in the nested if sequence, see if we
5909 are dealing with the same register. */
5910 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5913 COND_EXEC_TEST (pattern) = test = op1;
5916 /* If this isn't a nested if, reset state variables. */
5919 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5922 set = single_set_pattern (pattern);
5925 rtx dest = SET_DEST (set);
5926 rtx src = SET_SRC (set);
5927 enum machine_mode mode = GET_MODE (dest);
5929 /* Check for normal binary operators. */
5930 if (mode == SImode && ARITHMETIC_P (src))
5932 op0 = XEXP (src, 0);
5933 op1 = XEXP (src, 1);
5935 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
5937 op1 = frv_ifcvt_load_value (op1, insn);
5939 COND_EXEC_CODE (pattern)
5940 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
5948 /* For multiply by a constant, we need to handle the sign extending
5949 correctly. Add a USE of the value after the multiply to prevent flow
5950 from cratering because only one register out of the two were used. */
5951 else if (mode == DImode && GET_CODE (src) == MULT)
5953 op0 = XEXP (src, 0);
5954 op1 = XEXP (src, 1);
5955 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
5957 op1 = frv_ifcvt_load_value (op1, insn);
5960 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
5961 COND_EXEC_CODE (pattern)
5962 = gen_rtx_SET (VOIDmode, dest,
5963 gen_rtx_MULT (DImode, op0, op1));
5969 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
5972 /* If we are just loading a constant created for a nested conditional
5973 execution statement, just load the constant without any conditional
5974 execution, since we know that the constant will not interfere with any
5976 else if (frv_ifcvt.scratch_insns_bitmap
5977 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
5979 && REG_P (SET_DEST (set))
5980 /* We must not unconditionally set a scratch reg chosen
5981 for a nested if-converted block if its incoming
5982 value from the TEST block (or the result of the THEN
5983 branch) could/should propagate to the JOIN block.
5984 It suffices to test whether the register is live at
5985 the JOIN point: if it's live there, we can infer
5986 that we set it in the former JOIN block of the
5987 nested if-converted block (otherwise it wouldn't
5988 have been available as a scratch register), and it
5989 is either propagated through or set in the other
5990 conditional block. It's probably not worth trying
5991 to catch the latter case, and it could actually
5992 limit scheduling of the combined block quite
5995 && ! (REGNO_REG_SET_P
5996 (ce_info->join_bb->il.rtl->global_live_at_start,
5997 REGNO (SET_DEST (set))))
5998 /* Similarly, we must not unconditionally set a reg
5999 used as scratch in the THEN branch if the same reg
6000 is live in the ELSE branch. */
6001 && (! ce_info->else_bb
6002 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6003 || ! (REGNO_REG_SET_P
6004 (ce_info->else_bb->il.rtl->global_live_at_start,
6005 REGNO (SET_DEST (set))))))
6008 else if (mode == QImode || mode == HImode || mode == SImode
6011 int changed_p = FALSE;
6013 /* Check for just loading up a constant */
6014 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6016 src = frv_ifcvt_load_value (src, insn);
6023 /* See if we need to fix up stores */
6024 if (GET_CODE (dest) == MEM)
6026 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6031 else if (new_mem != dest)
6038 /* See if we need to fix up loads */
6039 if (GET_CODE (src) == MEM)
6041 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6046 else if (new_mem != src)
6053 /* If either src or destination changed, redo SET. */
6055 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6058 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6059 rewriting the CC register to be the same as the paired CC/CR register
6061 else if (mode == CC_CCRmode && COMPARISON_P (src))
6063 int regno = REGNO (XEXP (src, 0));
6066 if (ce_info->pass > 1
6067 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6068 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6070 src = gen_rtx_fmt_ee (GET_CODE (src),
6072 frv_ifcvt.nested_cc_reg,
6076 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6077 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6080 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6081 else if (ce_info->pass > 1
6082 && GET_CODE (dest) == REG
6083 && CC_P (REGNO (dest))
6084 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6085 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6087 && GET_CODE (src) == COMPARE)
6089 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6090 COND_EXEC_CODE (pattern)
6091 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6095 if (TARGET_DEBUG_COND_EXEC)
6097 rtx orig_pattern = PATTERN (insn);
6099 PATTERN (insn) = pattern;
6101 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6105 PATTERN (insn) = orig_pattern;
6111 if (TARGET_DEBUG_COND_EXEC)
6113 rtx orig_pattern = PATTERN (insn);
6115 PATTERN (insn) = orig_ce_pattern;
6117 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6121 PATTERN (insn) = orig_pattern;
6128 /* A C expression to perform any final machine dependent modifications in
6129 converting code to conditional execution in the code described by the
6130 conditional if information CE_INFO. */
6133 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6137 rtx p = frv_ifcvt.added_insns_list;
6140 /* Loop inserting the check insns. The last check insn is the first test,
6141 and is the appropriate place to insert constants. */
6146 rtx check_and_insert_insns = XEXP (p, 0);
6149 check_insn = XEXP (check_and_insert_insns, 0);
6150 existing_insn = XEXP (check_and_insert_insns, 1);
6153 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6154 the existing insn, otherwise it is to be inserted AFTER. */
6155 if (check_and_insert_insns->jump)
6157 emit_insn_before (check_insn, existing_insn);
6158 check_and_insert_insns->jump = 0;
6161 emit_insn_after (check_insn, existing_insn);
6163 free_EXPR_LIST_node (check_and_insert_insns);
6164 free_EXPR_LIST_node (old_p);
6166 while (p != NULL_RTX);
6168 /* Load up any constants needed into temp gprs */
6169 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6171 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6172 if (! frv_ifcvt.scratch_insns_bitmap)
6173 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6174 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6175 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6178 frv_ifcvt.added_insns_list = NULL_RTX;
6179 frv_ifcvt.cur_scratch_regs = 0;
6183 /* A C expression to cancel any machine dependent modifications in converting
6184 code to conditional execution in the code described by the conditional if
6185 information CE_INFO. */
6188 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6191 rtx p = frv_ifcvt.added_insns_list;
6193 /* Loop freeing up the EXPR_LIST's allocated. */
6194 while (p != NULL_RTX)
6196 rtx check_and_jump = XEXP (p, 0);
6200 free_EXPR_LIST_node (check_and_jump);
6201 free_EXPR_LIST_node (old_p);
6204 /* Release any temporary gprs allocated. */
6205 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6206 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6208 frv_ifcvt.added_insns_list = NULL_RTX;
6209 frv_ifcvt.cur_scratch_regs = 0;
6213 /* A C expression for the size in bytes of the trampoline, as an integer.
6217 setlo #0, <static_chain>
6219 sethi #0, <static_chain>
6220 jmpl @(gr0,<jmp_reg>) */
6223 frv_trampoline_size (void)
6226 /* Allocate room for the function descriptor and the lddi
6229 return 5 /* instructions */ * 4 /* instruction size. */;
6233 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6234 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6235 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6236 should be passed to the function when it is called.
6241 setlo #0, <static_chain>
6243 sethi #0, <static_chain>
6244 jmpl @(gr0,<jmp_reg>) */
6247 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
6249 rtx sc_reg = force_reg (Pmode, static_chain);
6251 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6254 GEN_INT (frv_trampoline_size ()), SImode,
6260 /* Many machines have some registers that cannot be copied directly to or from
6261 memory or even from other types of registers. An example is the `MQ'
6262 register, which on most machines, can only be copied to or from general
6263 registers, but not memory. Some machines allow copying all registers to and
6264 from memory, but require a scratch register for stores to some memory
6265 locations (e.g., those with symbolic address on the RT, and those with
6266 certain symbolic address on the SPARC when compiling PIC). In some cases,
6267 both an intermediate and a scratch register are required.
6269 You should define these macros to indicate to the reload phase that it may
6270 need to allocate at least one register for a reload in addition to the
6271 register to contain the data. Specifically, if copying X to a register
6272 CLASS in MODE requires an intermediate register, you should define
6273 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6274 whose registers can be used as intermediate registers or scratch registers.
6276 If copying a register CLASS in MODE to X requires an intermediate or scratch
6277 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6278 largest register class required. If the requirements for input and output
6279 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6280 instead of defining both macros identically.
6282 The values returned by these macros are often `GENERAL_REGS'. Return
6283 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6284 to or from a register of CLASS in MODE without requiring a scratch register.
6285 Do not define this macro if it would always return `NO_REGS'.
6287 If a scratch register is required (either with or without an intermediate
6288 register), you should define patterns for `reload_inM' or `reload_outM', as
6289 required.. These patterns, which will normally be implemented with a
6290 `define_expand', should be similar to the `movM' patterns, except that
6291 operand 2 is the scratch register.
6293 Define constraints for the reload register and scratch register that contain
6294 a single register class. If the original reload register (whose class is
6295 CLASS) can meet the constraint given in the pattern, the value returned by
6296 these macros is used for the class of the scratch register. Otherwise, two
6297 additional reload registers are required. Their classes are obtained from
6298 the constraints in the insn pattern.
6300 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6301 either be in a hard register or in memory. Use `true_regnum' to find out;
6302 it will return -1 if the pseudo is in memory and the hard register number if
6303 it is in a register.
6305 These macros should not be used in the case where a particular class of
6306 registers can only be copied to memory and not to another class of
6307 registers. In that case, secondary reload registers are not needed and
6308 would not be helpful. Instead, a stack location must be used to perform the
6309 copy and the `movM' pattern should use memory as an intermediate storage.
6310 This case often occurs between floating-point and general registers. */
6313 frv_secondary_reload_class (enum reg_class class,
6314 enum machine_mode mode ATTRIBUTE_UNUSED,
6316 int in_p ATTRIBUTE_UNUSED)
6326 /* Accumulators/Accumulator guard registers need to go through floating
6332 if (x && GET_CODE (x) == REG)
6334 int regno = REGNO (x);
6336 if (ACC_P (regno) || ACCG_P (regno))
6341 /* Nonzero constants should be loaded into an FPR through a GPR. */
6345 if (x && CONSTANT_P (x) && !ZERO_P (x))
6351 /* All of these types need gpr registers. */
6363 /* The accumulators need fpr registers */
6376 /* A C expression whose value is nonzero if pseudos that have been assigned to
6377 registers of class CLASS would likely be spilled because registers of CLASS
6378 are needed for spill registers.
6380 The default value of this macro returns 1 if CLASS has exactly one register
6381 and zero otherwise. On most machines, this default should be used. Only
6382 define this macro to some other expression if pseudo allocated by
6383 `local-alloc.c' end up in memory because their hard registers were needed
6384 for spill registers. If this macro returns nonzero for those classes, those
6385 pseudos will only be allocated by `global.c', which knows how to reallocate
6386 the pseudo to another register. If there would not be another register
6387 available for reallocation, you should not change the definition of this
6388 macro since the only effect of such a definition would be to slow down
6389 register allocation. */
6392 frv_class_likely_spilled_p (enum reg_class class)
6402 case FDPIC_FPTR_REGS:
6424 /* An expression for the alignment of a structure field FIELD if the
6425 alignment computed in the usual way is COMPUTED. GCC uses this
6426 value instead of the value in `BIGGEST_ALIGNMENT' or
6427 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6429 /* The definition type of the bit field data is either char, short, long or
6430 long long. The maximum bit size is the number of bits of its own type.
6432 The bit field data is assigned to a storage unit that has an adequate size
6433 for bit field data retention and is located at the smallest address.
6435 Consecutive bit field data are packed at consecutive bits having the same
6436 storage unit, with regard to the type, beginning with the MSB and continuing
6439 If a field to be assigned lies over a bit field type boundary, its
6440 assignment is completed by aligning it with a boundary suitable for the
6443 When a bit field having a bit length of 0 is declared, it is forcibly
6444 assigned to the next storage unit.
6457 &x 00000000 00000000 00000000 00000000
6460 &x+4 00000000 00000000 00000000 00000000
6463 &x+8 00000000 00000000 00000000 00000000
6466 &x+12 00000000 00000000 00000000 00000000
6472 frv_adjust_field_align (tree field, int computed)
6474 /* Make sure that the bitfield is not wider than the type. */
6475 if (DECL_BIT_FIELD (field)
6476 && !DECL_ARTIFICIAL (field))
6478 tree parent = DECL_CONTEXT (field);
6479 tree prev = NULL_TREE;
6482 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6484 if (TREE_CODE (cur) != FIELD_DECL)
6492 /* If this isn't a :0 field and if the previous element is a bitfield
6493 also, see if the type is different, if so, we will need to align the
6494 bit-field to the next boundary. */
6496 && ! DECL_PACKED (field)
6497 && ! integer_zerop (DECL_SIZE (field))
6498 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6500 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6501 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6502 computed = (prev_align > cur_align) ? prev_align : cur_align;
6510 /* A C expression that is nonzero if it is permissible to store a value of mode
6511 MODE in hard register number REGNO (or in several registers starting with
6512 that one). For a machine where all registers are equivalent, a suitable
6515 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6517 It is not necessary for this macro to check for the numbers of fixed
6518 registers, because the allocation mechanism considers them to be always
6521 On some machines, double-precision values must be kept in even/odd register
6522 pairs. The way to implement that is to define this macro to reject odd
6523 register numbers for such modes.
6525 The minimum requirement for a mode to be OK in a register is that the
6526 `movMODE' instruction pattern support moves between the register and any
6527 other hard register for which the mode is OK; and that moving a value into
6528 the register and back out not alter it.
6530 Since the same instruction used to move `SImode' will work for all narrower
6531 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6532 to distinguish between these modes, provided you define patterns `movhi',
6533 etc., to take advantage of this. This is useful because of the interaction
6534 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6535 all integer modes to be tieable.
6537 Many machines have special registers for floating point arithmetic. Often
6538 people assume that floating point machine modes are allowed only in floating
6539 point registers. This is not true. Any registers that can hold integers
6540 can safely *hold* a floating point machine mode, whether or not floating
6541 arithmetic can be done on it in those registers. Integer move instructions
6542 can be used to move the values.
6544 On some machines, though, the converse is true: fixed-point machine modes
6545 may not go in floating registers. This is true if the floating registers
6546 normalize any value stored in them, because storing a non-floating value
6547 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6548 fixed-point machine modes in floating registers. But if the floating
6549 registers do not automatically normalize, if you can store any bit pattern
6550 in one and retrieve it unchanged without a trap, then any machine mode may
6551 go in a floating register, so you can define this macro to say so.
6553 The primary significance of special floating registers is rather that they
6554 are the registers acceptable in floating point arithmetic instructions.
6555 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6556 writing the proper constraints for those instructions.
6558 On some machines, the floating registers are especially slow to access, so
6559 that it is better to store a value in a stack frame than in such a register
6560 if floating point arithmetic is not being done. As long as the floating
6561 registers are not in class `GENERAL_REGS', they will not be used unless some
6562 pattern's constraint asks for one. */
6565 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6575 return ICC_P (regno) || GPR_P (regno);
6578 return CR_P (regno) || GPR_P (regno);
6581 return FCC_P (regno) || GPR_P (regno);
6587 /* Set BASE to the first register in REGNO's class. Set MASK to the
6588 bits that must be clear in (REGNO - BASE) for the register to be
6590 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6594 /* ACCGs store one byte. Two-byte quantities must start in
6595 even-numbered registers, four-byte ones in registers whose
6596 numbers are divisible by four, and so on. */
6598 mask = GET_MODE_SIZE (mode) - 1;
6602 /* The other registers store one word. */
6603 if (GPR_P (regno) || regno == AP_FIRST)
6606 else if (FPR_P (regno))
6609 else if (ACC_P (regno))
6612 else if (SPR_P (regno))
6613 return mode == SImode;
6615 /* Fill in the table. */
6619 /* Anything smaller than an SI is OK in any word-sized register. */
6620 if (GET_MODE_SIZE (mode) < 4)
6623 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6625 return (((regno - base) & mask) == 0);
6632 /* A C expression for the number of consecutive hard registers, starting at
6633 register number REGNO, required to hold a value of mode MODE.
6635 On a machine where all registers are exactly one word, a suitable definition
6638 #define HARD_REGNO_NREGS(REGNO, MODE) \
6639 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6640 / UNITS_PER_WORD)) */
6642 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6643 that we can build the appropriate instructions to properly reload the
6644 values. Also, make the byte-sized accumulator guards use one guard
6648 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6651 return GET_MODE_SIZE (mode);
6653 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6657 /* A C expression for the maximum number of consecutive registers of
6658 class CLASS needed to hold a value of mode MODE.
6660 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6661 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
6662 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
6664 This macro helps control the handling of multiple-word values in
6667 This declaration is required. */
6670 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
6672 if (class == ACCG_REGS)
6673 /* An N-byte value requires N accumulator guards. */
6674 return GET_MODE_SIZE (mode);
6676 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6680 /* A C expression that is nonzero if X is a legitimate constant for an
6681 immediate operand on the target machine. You can assume that X satisfies
6682 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6683 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6686 frv_legitimate_constant_p (rtx x)
6688 enum machine_mode mode = GET_MODE (x);
6690 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6691 means that the move expanders will be expected to deal with most
6692 kinds of constant, regardless of what we return here.
6694 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6695 a constant can be entered into reg_equiv_constant[]. If we return true,
6696 reload can create new instances of the constant whenever it likes.
6698 The idea is therefore to accept as many constants as possible (to give
6699 reload more freedom) while rejecting constants that can only be created
6700 at certain times. In particular, anything with a symbolic component will
6701 require use of the pseudo FDPIC register, which is only available before
6704 return LEGITIMATE_PIC_OPERAND_P (x);
6706 /* All of the integer constants are ok. */
6707 if (GET_CODE (x) != CONST_DOUBLE)
6710 /* double integer constants are ok. */
6711 if (mode == VOIDmode || mode == DImode)
6714 /* 0 is always ok. */
6715 if (x == CONST0_RTX (mode))
6718 /* If floating point is just emulated, allow any constant, since it will be
6719 constructed in the GPRs. */
6720 if (!TARGET_HAS_FPRS)
6723 if (mode == DFmode && !TARGET_DOUBLE)
6726 /* Otherwise store the constant away and do a load. */
6730 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6731 CC_NZ for comparisons against zero in which a single Z or N flag test
6732 is enough, CC_UNS for other unsigned comparisons, and CC for other
6733 signed comparisons. */
6736 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6738 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6747 return y == const0_rtx ? CC_NZmode : CCmode;
6753 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6760 /* A C expression for the cost of moving data from a register in class FROM to
6761 one in class TO. The classes are expressed using the enumeration values
6762 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6763 interpreted relative to that.
6765 It is not required that the cost always equal 2 when FROM is the same as TO;
6766 on some machines it is expensive to move between registers if they are not
6769 If reload sees an insn consisting of a single `set' between two hard
6770 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6771 value of 2, reload does not check to ensure that the constraints of the insn
6772 are met. Setting a cost of other than 2 will allow reload to verify that
6773 the constraints are met. You should do this if the `movM' pattern's
6774 constraints do not allow such copying. */
6776 #define HIGH_COST 40
6777 #define MEDIUM_COST 3
6781 frv_register_move_cost (enum reg_class from, enum reg_class to)
6865 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6866 use ".picptr" to generate safe relocations for PIC code. We also
6867 need a fixup entry for aligned (non-debugging) code. */
6870 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6872 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6874 if (GET_CODE (value) == CONST
6875 || GET_CODE (value) == SYMBOL_REF
6876 || GET_CODE (value) == LABEL_REF)
6878 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6879 && SYMBOL_REF_FUNCTION_P (value))
6881 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6882 output_addr_const (asm_out_file, value);
6883 fputs (")\n", asm_out_file);
6886 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6887 && frv_function_symbol_referenced_p (value))
6889 if (aligned_p && !TARGET_FDPIC)
6891 static int label_num = 0;
6895 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
6896 p = (* targetm.strip_name_encoding) (buf);
6898 fprintf (asm_out_file, "%s:\n", p);
6899 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
6900 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
6901 fprintf (asm_out_file, "\t.previous\n");
6903 assemble_integer_with_op ("\t.picptr\t", value);
6908 /* We've set the unaligned SI op to NULL, so we always have to
6909 handle the unaligned case here. */
6910 assemble_integer_with_op ("\t.4byte\t", value);
6914 return default_assemble_integer (value, size, aligned_p);
6917 /* Function to set up the backend function structure. */
6919 static struct machine_function *
6920 frv_init_machine_status (void)
6922 return ggc_alloc_cleared (sizeof (struct machine_function));
6925 /* Implement TARGET_SCHED_ISSUE_RATE. */
6928 frv_issue_rate (void)
6933 switch (frv_cpu_type)
6937 case FRV_CPU_SIMPLE:
6945 case FRV_CPU_GENERIC:
6947 case FRV_CPU_TOMCAT:
6955 /* A for_each_rtx callback. If X refers to an accumulator, return
6956 ACC_GROUP_ODD if the bit 2 of the register number is set and
6957 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
6961 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
6965 if (ACC_P (REGNO (*x)))
6966 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
6967 if (ACCG_P (REGNO (*x)))
6968 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
6973 /* Return the value of INSN's acc_group attribute. */
6976 frv_acc_group (rtx insn)
6978 /* This distinction only applies to the FR550 packing constraints. */
6979 if (frv_cpu_type != FRV_CPU_FR550)
6980 return ACC_GROUP_NONE;
6981 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
6984 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
6985 INSN will try to claim first. Since this value depends only on the
6986 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
6989 frv_insn_unit (rtx insn)
6991 enum attr_type type;
6993 type = get_attr_type (insn);
6994 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
6996 /* We haven't seen this type of instruction before. */
7000 /* Issue the instruction on its own to see which unit it prefers. */
7001 state = alloca (state_size ());
7002 state_reset (state);
7003 state_transition (state, insn);
7005 /* Find out which unit was taken. */
7006 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7007 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7010 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7012 frv_type_to_unit[type] = unit;
7014 return frv_type_to_unit[type];
7017 /* Return true if INSN issues to a branch unit. */
7020 frv_issues_to_branch_unit_p (rtx insn)
7022 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7025 /* The current state of the packing pass, implemented by frv_pack_insns. */
7027 /* The state of the pipeline DFA. */
7030 /* Which hardware registers are set within the current packet,
7031 and the conditions under which they are set. */
7032 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7034 /* The memory locations that have been modified so far in this
7035 packet. MEM is the memref and COND is the regstate_t condition
7036 under which it is set. */
7042 /* The number of valid entries in MEMS. The value is larger than
7043 ARRAY_SIZE (mems) if there were too many mems to record. */
7044 unsigned int num_mems;
7046 /* The maximum number of instructions that can be packed together. */
7047 unsigned int issue_rate;
7049 /* The instructions in the packet, partitioned into groups. */
7050 struct frv_packet_group {
7051 /* How many instructions in the packet belong to this group. */
7052 unsigned int num_insns;
7054 /* A list of the instructions that belong to this group, in the order
7055 they appear in the rtl stream. */
7056 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7058 /* The contents of INSNS after they have been sorted into the correct
7059 assembly-language order. Element X issues to unit X. The list may
7060 contain extra nops. */
7061 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7063 /* The member of frv_nops[] to use in sorted[]. */
7065 } groups[NUM_GROUPS];
7067 /* The instructions that make up the current packet. */
7068 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7069 unsigned int num_insns;
7072 /* Return the regstate_t flags for the given COND_EXEC condition.
7073 Abort if the condition isn't in the right form. */
7076 frv_cond_flags (rtx cond)
7078 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7079 && GET_CODE (XEXP (cond, 0)) == REG
7080 && CR_P (REGNO (XEXP (cond, 0)))
7081 && XEXP (cond, 1) == const0_rtx);
7082 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7083 | (GET_CODE (cond) == NE
7085 : REGSTATE_IF_FALSE));
7089 /* Return true if something accessed under condition COND2 can
7090 conflict with something written under condition COND1. */
7093 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7095 /* If either reference was unconditional, we have a conflict. */
7096 if ((cond1 & REGSTATE_IF_EITHER) == 0
7097 || (cond2 & REGSTATE_IF_EITHER) == 0)
7100 /* The references might conflict if they were controlled by
7102 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7105 /* They definitely conflict if they are controlled by the
7107 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7114 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7115 the current packet. DATA points to a regstate_t that describes the
7116 condition under which *X might be set or used. */
7119 frv_registers_conflict_p_1 (rtx *x, void *data)
7121 unsigned int regno, i;
7124 cond = *(regstate_t *) data;
7126 if (GET_CODE (*x) == REG)
7127 FOR_EACH_REGNO (regno, *x)
7128 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7129 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7132 if (GET_CODE (*x) == MEM)
7134 /* If we ran out of memory slots, assume a conflict. */
7135 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7138 /* Check for output or true dependencies with earlier MEMs. */
7139 for (i = 0; i < frv_packet.num_mems; i++)
7140 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7142 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7146 if (output_dependence (frv_packet.mems[i].mem, *x))
7151 /* The return values of calls aren't significant: they describe
7152 the effect of the call as a whole, not of the insn itself. */
7153 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7155 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7160 /* Check subexpressions. */
7165 /* Return true if something in X might depend on an instruction
7166 in the current packet. */
7169 frv_registers_conflict_p (rtx x)
7174 if (GET_CODE (x) == COND_EXEC)
7176 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7179 flags |= frv_cond_flags (XEXP (x, 0));
7182 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7186 /* A note_stores callback. DATA points to the regstate_t condition
7187 under which X is modified. Update FRV_PACKET accordingly. */
7190 frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
7194 if (GET_CODE (x) == REG)
7195 FOR_EACH_REGNO (regno, x)
7196 frv_packet.regstate[regno] |= *(regstate_t *) data;
7198 if (GET_CODE (x) == MEM)
7200 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7202 frv_packet.mems[frv_packet.num_mems].mem = x;
7203 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7205 frv_packet.num_mems++;
7210 /* Update the register state information for an instruction whose
7214 frv_registers_update (rtx x)
7218 flags = REGSTATE_MODIFIED;
7219 if (GET_CODE (x) == COND_EXEC)
7221 flags |= frv_cond_flags (XEXP (x, 0));
7224 note_stores (x, frv_registers_update_1, &flags);
7228 /* Initialize frv_packet for the start of a new packet. */
7231 frv_start_packet (void)
7233 enum frv_insn_group group;
7235 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7236 frv_packet.num_mems = 0;
7237 frv_packet.num_insns = 0;
7238 for (group = 0; group < NUM_GROUPS; group++)
7239 frv_packet.groups[group].num_insns = 0;
7243 /* Likewise for the start of a new basic block. */
7246 frv_start_packet_block (void)
7248 state_reset (frv_packet.dfa_state);
7249 frv_start_packet ();
7253 /* Finish the current packet, if any, and start a new one. Call
7254 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7257 frv_finish_packet (void (*handle_packet) (void))
7259 if (frv_packet.num_insns > 0)
7262 state_transition (frv_packet.dfa_state, 0);
7263 frv_start_packet ();
7268 /* Return true if INSN can be added to the current packet. Update
7269 the DFA state on success. */
7272 frv_pack_insn_p (rtx insn)
7274 /* See if the packet is already as long as it can be. */
7275 if (frv_packet.num_insns == frv_packet.issue_rate)
7278 /* If the scheduler thought that an instruction should start a packet,
7279 it's usually a good idea to believe it. It knows much more about
7280 the latencies than we do.
7282 There are some exceptions though:
7284 - Conditional instructions are scheduled on the assumption that
7285 they will be executed. This is usually a good thing, since it
7286 tends to avoid unnecessary stalls in the conditional code.
7287 But we want to pack conditional instructions as tightly as
7288 possible, in order to optimize the case where they aren't
7291 - The scheduler will always put branches on their own, even
7292 if there's no real dependency.
7294 - There's no point putting a call in its own packet unless
7296 if (frv_packet.num_insns > 0
7297 && GET_CODE (insn) == INSN
7298 && GET_MODE (insn) == TImode
7299 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7302 /* Check for register conflicts. Don't do this for setlo since any
7303 conflict will be with the partnering sethi, with which it can
7305 if (get_attr_type (insn) != TYPE_SETLO)
7306 if (frv_registers_conflict_p (PATTERN (insn)))
7309 return state_transition (frv_packet.dfa_state, insn) < 0;
7313 /* Add instruction INSN to the current packet. */
7316 frv_add_insn_to_packet (rtx insn)
7318 struct frv_packet_group *packet_group;
7320 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7321 packet_group->insns[packet_group->num_insns++] = insn;
7322 frv_packet.insns[frv_packet.num_insns++] = insn;
7324 frv_registers_update (PATTERN (insn));
7328 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7329 packet ends in a branch or call, insert the nop before it, otherwise
7333 frv_insert_nop_in_packet (rtx insn)
7335 struct frv_packet_group *packet_group;
7338 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7339 last = frv_packet.insns[frv_packet.num_insns - 1];
7340 if (GET_CODE (last) != INSN)
7342 insn = emit_insn_before (PATTERN (insn), last);
7343 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7344 frv_packet.insns[frv_packet.num_insns++] = last;
7348 insn = emit_insn_after (PATTERN (insn), last);
7349 frv_packet.insns[frv_packet.num_insns++] = insn;
7351 packet_group->insns[packet_group->num_insns++] = insn;
7355 /* If packing is enabled, divide the instructions into packets and
7356 return true. Call HANDLE_PACKET for each complete packet. */
7359 frv_for_each_packet (void (*handle_packet) (void))
7361 rtx insn, next_insn;
7363 frv_packet.issue_rate = frv_issue_rate ();
7365 /* Early exit if we don't want to pack insns. */
7367 || !flag_schedule_insns_after_reload
7368 || !TARGET_VLIW_BRANCH
7369 || frv_packet.issue_rate == 1)
7372 /* Set up the initial packing state. */
7374 frv_packet.dfa_state = alloca (state_size ());
7376 frv_start_packet_block ();
7377 for (insn = get_insns (); insn != 0; insn = next_insn)
7382 code = GET_CODE (insn);
7383 next_insn = NEXT_INSN (insn);
7385 if (code == CODE_LABEL)
7387 frv_finish_packet (handle_packet);
7388 frv_start_packet_block ();
7392 switch (GET_CODE (PATTERN (insn)))
7401 /* Calls mustn't be packed on a TOMCAT. */
7402 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7403 frv_finish_packet (handle_packet);
7405 /* Since the last instruction in a packet determines the EH
7406 region, any exception-throwing instruction must come at
7407 the end of reordered packet. Insns that issue to a
7408 branch unit are bound to come last; for others it's
7409 too hard to predict. */
7410 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7411 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7412 frv_finish_packet (handle_packet);
7414 /* Finish the current packet if we can't add INSN to it.
7415 Simulate cycles until INSN is ready to issue. */
7416 if (!frv_pack_insn_p (insn))
7418 frv_finish_packet (handle_packet);
7419 while (!frv_pack_insn_p (insn))
7420 state_transition (frv_packet.dfa_state, 0);
7423 /* Add the instruction to the packet. */
7424 frv_add_insn_to_packet (insn);
7426 /* Calls and jumps end a packet, as do insns that throw
7428 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7429 frv_finish_packet (handle_packet);
7433 frv_finish_packet (handle_packet);
7438 /* Subroutine of frv_sort_insn_group. We are trying to sort
7439 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7440 language order. We have already picked a new position for
7441 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7442 These instructions will occupy elements [0, LOWER_SLOT) and
7443 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7444 the DFA state after issuing these instructions.
7446 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7447 of the unused instructions. Return true if one such permutation gives
7448 a valid ordering, leaving the successful permutation in sorted[].
7449 Do not modify sorted[] until a valid permutation is found. */
7452 frv_sort_insn_group_1 (enum frv_insn_group group,
7453 unsigned int lower_slot, unsigned int upper_slot,
7454 unsigned int issued, unsigned int num_insns,
7457 struct frv_packet_group *packet_group;
7463 /* Early success if we've filled all the slots. */
7464 if (lower_slot == upper_slot)
7467 packet_group = &frv_packet.groups[group];
7468 dfa_size = state_size ();
7469 test_state = alloca (dfa_size);
7471 /* Try issuing each unused instruction. */
7472 for (i = num_insns - 1; i + 1 != 0; i--)
7473 if (~issued & (1 << i))
7475 insn = packet_group->sorted[i];
7476 memcpy (test_state, state, dfa_size);
7477 if (state_transition (test_state, insn) < 0
7478 && cpu_unit_reservation_p (test_state,
7479 NTH_UNIT (group, upper_slot - 1))
7480 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7481 issued | (1 << i), num_insns,
7484 packet_group->sorted[upper_slot - 1] = insn;
7492 /* Compare two instructions by their frv_insn_unit. */
7495 frv_compare_insns (const void *first, const void *second)
7497 const rtx *insn1 = first, *insn2 = second;
7498 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7501 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7502 and sort it into assembly language order. See frv.md for a description of
7506 frv_sort_insn_group (enum frv_insn_group group)
7508 struct frv_packet_group *packet_group;
7509 unsigned int first, i, nop, max_unit, num_slots;
7510 state_t state, test_state;
7513 packet_group = &frv_packet.groups[group];
7515 /* Assume no nop is needed. */
7516 packet_group->nop = 0;
7518 if (packet_group->num_insns == 0)
7521 /* Copy insns[] to sorted[]. */
7522 memcpy (packet_group->sorted, packet_group->insns,
7523 sizeof (rtx) * packet_group->num_insns);
7525 /* Sort sorted[] by the unit that each insn tries to take first. */
7526 if (packet_group->num_insns > 1)
7527 qsort (packet_group->sorted, packet_group->num_insns,
7528 sizeof (rtx), frv_compare_insns);
7530 /* That's always enough for branch and control insns. */
7531 if (group == GROUP_B || group == GROUP_C)
7534 dfa_size = state_size ();
7535 state = alloca (dfa_size);
7536 test_state = alloca (dfa_size);
7538 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7539 consecutively and such that the DFA takes unit X when sorted[X]
7540 is added. Set STATE to the new DFA state. */
7541 state_reset (test_state);
7542 for (first = 0; first < packet_group->num_insns; first++)
7544 memcpy (state, test_state, dfa_size);
7545 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7546 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7550 /* If all the instructions issued in ascending order, we're done. */
7551 if (first == packet_group->num_insns)
7554 /* Add nops to the end of sorted[] and try each permutation until
7555 we find one that works. */
7556 for (nop = 0; nop < frv_num_nops; nop++)
7558 max_unit = frv_insn_unit (frv_nops[nop]);
7559 if (frv_unit_groups[max_unit] == group)
7561 packet_group->nop = frv_nops[nop];
7562 num_slots = UNIT_NUMBER (max_unit) + 1;
7563 for (i = packet_group->num_insns; i < num_slots; i++)
7564 packet_group->sorted[i] = frv_nops[nop];
7565 if (frv_sort_insn_group_1 (group, first, num_slots,
7566 (1 << first) - 1, num_slots, state))
7573 /* Sort the current packet into assembly-language order. Set packing
7574 flags as appropriate. */
7577 frv_reorder_packet (void)
7579 unsigned int cursor[NUM_GROUPS];
7580 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7581 unsigned int unit, to, from;
7582 enum frv_insn_group group;
7583 struct frv_packet_group *packet_group;
7585 /* First sort each group individually. */
7586 for (group = 0; group < NUM_GROUPS; group++)
7589 frv_sort_insn_group (group);
7592 /* Go through the unit template and try add an instruction from
7593 that unit's group. */
7595 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7597 group = frv_unit_groups[unit];
7598 packet_group = &frv_packet.groups[group];
7599 if (cursor[group] < packet_group->num_insns)
7601 /* frv_reorg should have added nops for us. */
7602 gcc_assert (packet_group->sorted[cursor[group]]
7603 != packet_group->nop);
7604 insns[to++] = packet_group->sorted[cursor[group]++];
7608 gcc_assert (to == frv_packet.num_insns);
7610 /* Clear the last instruction's packing flag, thus marking the end of
7611 a packet. Reorder the other instructions relative to it. */
7612 CLEAR_PACKING_FLAG (insns[to - 1]);
7613 for (from = 0; from < to - 1; from++)
7615 remove_insn (insns[from]);
7616 add_insn_before (insns[from], insns[to - 1]);
7617 SET_PACKING_FLAG (insns[from]);
7622 /* Divide instructions into packets. Reorder the contents of each
7623 packet so that they are in the correct assembly-language order.
7625 Since this pass can change the raw meaning of the rtl stream, it must
7626 only be called at the last minute, just before the instructions are
7630 frv_pack_insns (void)
7632 if (frv_for_each_packet (frv_reorder_packet))
7633 frv_insn_packing_flag = 0;
7635 frv_insn_packing_flag = -1;
7638 /* See whether we need to add nops to group GROUP in order to
7639 make a valid packet. */
7642 frv_fill_unused_units (enum frv_insn_group group)
7644 unsigned int non_nops, nops, i;
7645 struct frv_packet_group *packet_group;
7647 packet_group = &frv_packet.groups[group];
7649 /* Sort the instructions into assembly-language order.
7650 Use nops to fill slots that are otherwise unused. */
7651 frv_sort_insn_group (group);
7653 /* See how many nops are needed before the final useful instruction. */
7655 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7656 while (packet_group->sorted[i++] == packet_group->nop)
7659 /* Insert that many nops into the instruction stream. */
7661 frv_insert_nop_in_packet (packet_group->nop);
7664 /* Used by frv_reorg to keep track of the current packet's address. */
7665 static unsigned int frv_packet_address;
7667 /* If the current packet falls through to a label, try to pad the packet
7668 with nops in order to fit the label's alignment requirements. */
7671 frv_align_label (void)
7673 unsigned int alignment, target, nop;
7674 rtx x, last, barrier, label;
7676 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
7677 maximum alignment of that packet, LABEL to the last label between
7678 the packets, and BARRIER to the last barrier. */
7679 last = frv_packet.insns[frv_packet.num_insns - 1];
7680 label = barrier = 0;
7682 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
7686 unsigned int subalign = 1 << label_to_alignment (x);
7687 alignment = MAX (alignment, subalign);
7694 /* If -malign-labels, and the packet falls through to an unaligned
7695 label, try introducing a nop to align that label to 8 bytes. */
7696 if (TARGET_ALIGN_LABELS
7699 && frv_packet.num_insns < frv_packet.issue_rate)
7700 alignment = MAX (alignment, 8);
7702 /* Advance the address to the end of the current packet. */
7703 frv_packet_address += frv_packet.num_insns * 4;
7705 /* Work out the target address, after alignment. */
7706 target = (frv_packet_address + alignment - 1) & -alignment;
7708 /* If the packet falls through to the label, try to find an efficient
7709 padding sequence. */
7712 /* First try adding nops to the current packet. */
7713 for (nop = 0; nop < frv_num_nops; nop++)
7714 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
7716 frv_insert_nop_in_packet (frv_nops[nop]);
7717 frv_packet_address += 4;
7720 /* If we still haven't reached the target, add some new packets that
7721 contain only nops. If there are two types of nop, insert an
7722 alternating sequence of frv_nops[0] and frv_nops[1], which will
7723 lead to packets like:
7730 etc. Just emit frv_nops[0] if that's the only nop we have. */
7731 last = frv_packet.insns[frv_packet.num_insns - 1];
7733 while (frv_packet_address < target)
7735 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
7736 frv_packet_address += 4;
7737 if (frv_num_nops > 1)
7742 frv_packet_address = target;
7745 /* Subroutine of frv_reorg, called after each packet has been constructed
7749 frv_reorg_packet (void)
7751 frv_fill_unused_units (GROUP_I);
7752 frv_fill_unused_units (GROUP_FM);
7756 /* Add an instruction with pattern NOP to frv_nops[]. */
7759 frv_register_nop (rtx nop)
7761 nop = make_insn_raw (nop);
7762 NEXT_INSN (nop) = 0;
7763 PREV_INSN (nop) = 0;
7764 frv_nops[frv_num_nops++] = nop;
7767 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
7768 into packets and check whether we need to insert nops in order to
7769 fulfill the processor's issue requirements. Also, if the user has
7770 requested a certain alignment for a label, try to meet that alignment
7771 by inserting nops in the previous packet. */
7777 frv_register_nop (gen_nop ());
7779 frv_register_nop (gen_mnop ());
7780 if (TARGET_HARD_FLOAT)
7781 frv_register_nop (gen_fnop ());
7783 /* Estimate the length of each branch. Although this may change after
7784 we've inserted nops, it will only do so in big functions. */
7785 shorten_branches (get_insns ());
7787 frv_packet_address = 0;
7788 frv_for_each_packet (frv_reorg_packet);
7791 #define def_builtin(name, type, code) \
7792 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
7794 struct builtin_description
7796 enum insn_code icode;
7798 enum frv_builtins code;
7799 enum rtx_code comparison;
7803 /* Media intrinsics that take a single, constant argument. */
7805 static struct builtin_description bdesc_set[] =
7807 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
7810 /* Media intrinsics that take just one argument. */
7812 static struct builtin_description bdesc_1arg[] =
7814 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
7815 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
7816 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
7817 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
7818 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
7819 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
7822 /* Media intrinsics that take two arguments. */
7824 static struct builtin_description bdesc_2arg[] =
7826 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
7827 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
7828 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
7829 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
7830 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
7831 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
7832 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
7833 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
7834 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
7835 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
7836 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
7837 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
7838 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
7839 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
7840 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
7841 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
7842 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
7843 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
7844 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
7845 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
7846 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
7847 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
7848 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
7849 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
7850 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
7851 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
7852 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
7855 /* Integer intrinsics that take two arguments and have no return value. */
7857 static struct builtin_description bdesc_int_void2arg[] =
7859 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
7860 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
7861 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
7864 static struct builtin_description bdesc_prefetches[] =
7866 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
7867 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
7870 /* Media intrinsics that take two arguments, the first being an ACC number. */
7872 static struct builtin_description bdesc_cut[] =
7874 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
7875 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
7876 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
7879 /* Two-argument media intrinsics with an immediate second argument. */
7881 static struct builtin_description bdesc_2argimm[] =
7883 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
7884 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
7885 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
7886 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
7887 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
7888 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
7889 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
7890 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
7891 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
7892 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
7893 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
7894 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
7895 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
7896 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
7897 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
7898 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
7899 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
7902 /* Media intrinsics that take two arguments and return void, the first argument
7903 being a pointer to 4 words in memory. */
7905 static struct builtin_description bdesc_void2arg[] =
7907 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
7908 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
7911 /* Media intrinsics that take three arguments, the first being a const_int that
7912 denotes an accumulator, and that return void. */
7914 static struct builtin_description bdesc_void3arg[] =
7916 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
7917 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
7918 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
7919 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
7920 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
7921 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
7922 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
7923 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
7924 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
7925 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
7926 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
7927 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
7928 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
7929 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
7930 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
7931 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
7932 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
7933 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
7934 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
7935 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
7936 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
7937 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
7938 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
7939 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
7940 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
7943 /* Media intrinsics that take two accumulator numbers as argument and
7946 static struct builtin_description bdesc_voidacc[] =
7948 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
7949 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
7950 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
7951 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
7952 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
7953 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
7956 /* Initialize media builtins. */
7959 frv_init_builtins (void)
7961 tree endlink = void_list_node;
7962 tree accumulator = integer_type_node;
7963 tree integer = integer_type_node;
7964 tree voidt = void_type_node;
7965 tree uhalf = short_unsigned_type_node;
7966 tree sword1 = long_integer_type_node;
7967 tree uword1 = long_unsigned_type_node;
7968 tree sword2 = long_long_integer_type_node;
7969 tree uword2 = long_long_unsigned_type_node;
7970 tree uword4 = build_pointer_type (uword1);
7971 tree iacc = integer_type_node;
7973 #define UNARY(RET, T1) \
7974 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
7976 #define BINARY(RET, T1, T2) \
7977 build_function_type (RET, tree_cons (NULL_TREE, T1, \
7978 tree_cons (NULL_TREE, T2, endlink)))
7980 #define TRINARY(RET, T1, T2, T3) \
7981 build_function_type (RET, tree_cons (NULL_TREE, T1, \
7982 tree_cons (NULL_TREE, T2, \
7983 tree_cons (NULL_TREE, T3, endlink))))
7985 #define QUAD(RET, T1, T2, T3, T4) \
7986 build_function_type (RET, tree_cons (NULL_TREE, T1, \
7987 tree_cons (NULL_TREE, T2, \
7988 tree_cons (NULL_TREE, T3, \
7989 tree_cons (NULL_TREE, T4, endlink)))))
7991 tree void_ftype_void = build_function_type (voidt, endlink);
7993 tree void_ftype_acc = UNARY (voidt, accumulator);
7994 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
7995 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
7996 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
7997 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
7998 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
7999 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8000 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8001 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8003 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8004 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8005 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8006 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8007 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8008 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8009 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8010 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8011 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8012 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8013 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8015 tree sw1_ftype_int = UNARY (sword1, integer);
8016 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8017 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8019 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8020 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8021 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8022 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8023 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8024 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8026 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8027 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8028 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8029 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8030 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8031 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8032 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8033 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8034 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8035 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8036 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8038 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8039 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8040 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8041 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8042 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8043 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8044 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8045 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8046 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8047 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8048 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8049 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8050 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8051 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8052 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8053 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8054 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8055 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8056 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8057 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8058 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8059 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8060 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8061 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8062 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8063 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8064 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8065 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8066 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8067 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8068 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8069 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8070 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8071 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8072 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8073 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8074 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8075 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8076 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8077 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8078 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8079 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8080 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8081 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8082 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8083 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8084 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8085 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8086 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8087 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8088 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8089 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8090 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8091 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8092 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8093 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8094 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8095 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8096 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8097 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8098 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8099 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8100 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8101 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8102 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8103 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8104 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8105 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8106 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8107 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8108 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8109 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8110 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8111 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8112 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8113 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8114 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8115 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8116 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8117 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8118 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8119 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8120 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8121 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8122 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8123 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8124 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8125 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8126 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8127 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8128 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8129 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8130 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8131 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8132 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8133 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8134 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8135 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8136 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8137 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8138 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8139 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8140 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8141 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8149 /* Set the names for various arithmetic operations according to the
8152 frv_init_libfuncs (void)
8154 set_optab_libfunc (smod_optab, SImode, "__modi");
8155 set_optab_libfunc (umod_optab, SImode, "__umodi");
8157 set_optab_libfunc (add_optab, DImode, "__addll");
8158 set_optab_libfunc (sub_optab, DImode, "__subll");
8159 set_optab_libfunc (smul_optab, DImode, "__mulll");
8160 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8161 set_optab_libfunc (smod_optab, DImode, "__modll");
8162 set_optab_libfunc (umod_optab, DImode, "__umodll");
8163 set_optab_libfunc (and_optab, DImode, "__andll");
8164 set_optab_libfunc (ior_optab, DImode, "__orll");
8165 set_optab_libfunc (xor_optab, DImode, "__xorll");
8166 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8168 set_optab_libfunc (add_optab, SFmode, "__addf");
8169 set_optab_libfunc (sub_optab, SFmode, "__subf");
8170 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8171 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8173 set_optab_libfunc (add_optab, DFmode, "__addd");
8174 set_optab_libfunc (sub_optab, DFmode, "__subd");
8175 set_optab_libfunc (smul_optab, DFmode, "__muld");
8176 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8178 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8179 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8181 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8182 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8183 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8184 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8186 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8187 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8188 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8189 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8191 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8192 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8193 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8194 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8197 /* Convert an integer constant to an accumulator register. ICODE is the
8198 code of the target instruction, OPNUM is the number of the
8199 accumulator operand and OPVAL is the constant integer. Try both
8200 ACC and ACCG registers; only report an error if neither fit the
8204 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8209 /* ACCs and ACCGs are implicit global registers if media intrinsics
8210 are being used. We set up this lazily to avoid creating lots of
8211 unnecessary call_insn rtl in non-media code. */
8212 for (i = 0; i <= ACC_MASK; i++)
8213 if ((i & ACC_MASK) == i)
8214 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8216 if (GET_CODE (opval) != CONST_INT)
8218 error ("accumulator is not a constant integer");
8221 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8223 error ("accumulator number is out of bounds");
8227 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8228 ACC_FIRST + INTVAL (opval));
8229 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8230 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
8232 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8234 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8240 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8243 static enum machine_mode
8244 frv_matching_accg_mode (enum machine_mode mode)
8262 /* Return the accumulator guard that should be paired with accumulator
8263 register ACC. The mode of the returned register is in the same
8264 class as ACC, but is four times smaller. */
8267 frv_matching_accg_for_acc (rtx acc)
8269 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8270 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8273 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
8274 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
8278 frv_read_argument (tree *arglistptr)
8280 tree next = TREE_VALUE (*arglistptr);
8281 *arglistptr = TREE_CHAIN (*arglistptr);
8282 return expand_expr (next, NULL_RTX, VOIDmode, 0);
8285 /* Like frv_read_argument, but interpret the argument as the number
8286 of an IACC register and return a (reg:MODE ...) rtx for it. */
8289 frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr)
8294 op = frv_read_argument (arglistptr);
8295 if (GET_CODE (op) != CONST_INT
8297 || INTVAL (op) > IACC_LAST - IACC_FIRST
8298 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8300 error ("invalid IACC argument");
8304 /* IACCs are implicit global registers. We set up this lazily to
8305 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8307 regno = INTVAL (op) + IACC_FIRST;
8308 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8309 global_regs[regno + i] = 1;
8311 return gen_rtx_REG (mode, regno);
8314 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8315 The instruction should require a constant operand of some sort. The
8316 function prints an error if OPVAL is not valid. */
8319 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8321 if (GET_CODE (opval) != CONST_INT)
8323 error ("%qs expects a constant argument", insn_data[icode].name);
8326 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8328 error ("constant argument out of range for %qs", insn_data[icode].name);
8334 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8335 if it's not null, has the right mode, and satisfies operand 0's
8339 frv_legitimize_target (enum insn_code icode, rtx target)
8341 enum machine_mode mode = insn_data[icode].operand[0].mode;
8344 || GET_MODE (target) != mode
8345 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8346 return gen_reg_rtx (mode);
8351 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8352 check whether ARG satisfies the operand's constraints. If it doesn't,
8353 copy ARG to a temporary register and return that. Otherwise return ARG
8357 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8359 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8361 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8364 return copy_to_mode_reg (mode, arg);
8367 /* Expand builtins that take a single, constant argument. At the moment,
8368 only MHDSETS falls into this category. */
8371 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
8374 rtx op0 = frv_read_argument (&arglist);
8376 if (! frv_check_constant_argument (icode, 1, op0))
8379 target = frv_legitimize_target (icode, target);
8380 pat = GEN_FCN (icode) (target, op0);
8388 /* Expand builtins that take one operand. */
8391 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
8394 rtx op0 = frv_read_argument (&arglist);
8396 target = frv_legitimize_target (icode, target);
8397 op0 = frv_legitimize_argument (icode, 1, op0);
8398 pat = GEN_FCN (icode) (target, op0);
8406 /* Expand builtins that take two operands. */
8409 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
8412 rtx op0 = frv_read_argument (&arglist);
8413 rtx op1 = frv_read_argument (&arglist);
8415 target = frv_legitimize_target (icode, target);
8416 op0 = frv_legitimize_argument (icode, 1, op0);
8417 op1 = frv_legitimize_argument (icode, 2, op1);
8418 pat = GEN_FCN (icode) (target, op0, op1);
8426 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8430 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
8433 rtx op0 = frv_read_argument (&arglist);
8434 rtx op1 = frv_read_argument (&arglist);
8437 target = frv_legitimize_target (icode, target);
8438 op0 = frv_int_to_acc (icode, 1, op0);
8442 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8444 if (! frv_check_constant_argument (icode, 2, op1))
8448 op1 = frv_legitimize_argument (icode, 2, op1);
8450 op2 = frv_matching_accg_for_acc (op0);
8451 pat = GEN_FCN (icode) (target, op0, op1, op2);
8459 /* Expand builtins that take two operands and the second is immediate. */
8462 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
8465 rtx op0 = frv_read_argument (&arglist);
8466 rtx op1 = frv_read_argument (&arglist);
8468 if (! frv_check_constant_argument (icode, 2, op1))
8471 target = frv_legitimize_target (icode, target);
8472 op0 = frv_legitimize_argument (icode, 1, op0);
8473 pat = GEN_FCN (icode) (target, op0, op1);
8481 /* Expand builtins that take two operands, the first operand being a pointer to
8482 ints and return void. */
8485 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
8488 rtx op0 = frv_read_argument (&arglist);
8489 rtx op1 = frv_read_argument (&arglist);
8490 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8493 if (GET_CODE (op0) != MEM)
8497 if (! offsettable_address_p (0, mode0, op0))
8499 reg = gen_reg_rtx (Pmode);
8500 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
8503 op0 = gen_rtx_MEM (SImode, reg);
8506 addr = XEXP (op0, 0);
8507 if (! offsettable_address_p (0, mode0, addr))
8508 addr = copy_to_mode_reg (Pmode, op0);
8510 op0 = change_address (op0, V4SImode, addr);
8511 op1 = frv_legitimize_argument (icode, 1, op1);
8512 pat = GEN_FCN (icode) (op0, op1);
8520 /* Expand builtins that take two long operands and return void. */
8523 frv_expand_int_void2arg (enum insn_code icode, tree arglist)
8526 rtx op0 = frv_read_argument (&arglist);
8527 rtx op1 = frv_read_argument (&arglist);
8529 op0 = frv_legitimize_argument (icode, 1, op0);
8530 op1 = frv_legitimize_argument (icode, 1, op1);
8531 pat = GEN_FCN (icode) (op0, op1);
8539 /* Expand prefetch builtins. These take a single address as argument. */
8542 frv_expand_prefetches (enum insn_code icode, tree arglist)
8545 rtx op0 = frv_read_argument (&arglist);
8547 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
8555 /* Expand builtins that take three operands and return void. The first
8556 argument must be a constant that describes a pair or quad accumulators. A
8557 fourth argument is created that is the accumulator guard register that
8558 corresponds to the accumulator. */
8561 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
8564 rtx op0 = frv_read_argument (&arglist);
8565 rtx op1 = frv_read_argument (&arglist);
8566 rtx op2 = frv_read_argument (&arglist);
8569 op0 = frv_int_to_acc (icode, 0, op0);
8573 op1 = frv_legitimize_argument (icode, 1, op1);
8574 op2 = frv_legitimize_argument (icode, 2, op2);
8575 op3 = frv_matching_accg_for_acc (op0);
8576 pat = GEN_FCN (icode) (op0, op1, op2, op3);
8584 /* Expand builtins that perform accumulator-to-accumulator operations.
8585 These builtins take two accumulator numbers as argument and return
8589 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
8592 rtx op0 = frv_read_argument (&arglist);
8593 rtx op1 = frv_read_argument (&arglist);
8597 op0 = frv_int_to_acc (icode, 0, op0);
8601 op1 = frv_int_to_acc (icode, 1, op1);
8605 op2 = frv_matching_accg_for_acc (op0);
8606 op3 = frv_matching_accg_for_acc (op1);
8607 pat = GEN_FCN (icode) (op0, op1, op2, op3);
8615 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
8616 each argument forms one word of the two double-word input registers.
8617 ARGLIST is a TREE_LIST of the arguments and TARGET, if nonnull,
8618 suggests a good place to put the return value. */
8621 frv_expand_mdpackh_builtin (tree arglist, rtx target)
8623 enum insn_code icode = CODE_FOR_mdpackh;
8625 rtx arg1 = frv_read_argument (&arglist);
8626 rtx arg2 = frv_read_argument (&arglist);
8627 rtx arg3 = frv_read_argument (&arglist);
8628 rtx arg4 = frv_read_argument (&arglist);
8630 target = frv_legitimize_target (icode, target);
8631 op0 = gen_reg_rtx (DImode);
8632 op1 = gen_reg_rtx (DImode);
8634 /* The high half of each word is not explicitly initialized, so indicate
8635 that the input operands are not live before this point. */
8636 emit_insn (gen_rtx_CLOBBER (DImode, op0));
8637 emit_insn (gen_rtx_CLOBBER (DImode, op1));
8639 /* Move each argument into the low half of its associated input word. */
8640 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
8641 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
8642 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
8643 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
8645 pat = GEN_FCN (icode) (target, op0, op1);
8653 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
8654 number as argument. */
8657 frv_expand_mclracc_builtin (tree arglist)
8659 enum insn_code icode = CODE_FOR_mclracc;
8661 rtx op0 = frv_read_argument (&arglist);
8663 op0 = frv_int_to_acc (icode, 0, op0);
8667 pat = GEN_FCN (icode) (op0);
8674 /* Expand builtins that take no arguments. */
8677 frv_expand_noargs_builtin (enum insn_code icode)
8679 rtx pat = GEN_FCN (icode) (const0_rtx);
8686 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
8687 number or accumulator guard number as argument and return an SI integer. */
8690 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
8693 rtx target = gen_reg_rtx (SImode);
8694 rtx op0 = frv_read_argument (&arglist);
8696 op0 = frv_int_to_acc (icode, 1, op0);
8700 pat = GEN_FCN (icode) (target, op0);
8708 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
8709 accumulator guard as their first argument and an SImode value as their
8713 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
8716 rtx op0 = frv_read_argument (&arglist);
8717 rtx op1 = frv_read_argument (&arglist);
8719 op0 = frv_int_to_acc (icode, 0, op0);
8723 op1 = frv_legitimize_argument (icode, 1, op1);
8724 pat = GEN_FCN (icode) (op0, op1);
8731 /* Emit a move from SRC to DEST in SImode chunks. This can be used
8732 to move DImode values into and out of IACC0. */
8735 frv_split_iacc_move (rtx dest, rtx src)
8737 enum machine_mode inner;
8740 inner = GET_MODE (dest);
8741 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
8742 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
8743 simplify_gen_subreg (SImode, src, inner, i));
8746 /* Expand builtins. */
8749 frv_expand_builtin (tree exp,
8751 rtx subtarget ATTRIBUTE_UNUSED,
8752 enum machine_mode mode ATTRIBUTE_UNUSED,
8753 int ignore ATTRIBUTE_UNUSED)
8755 tree arglist = TREE_OPERAND (exp, 1);
8756 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8757 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
8759 struct builtin_description *d;
8761 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
8763 error ("media functions are not available unless -mmedia is used");
8769 case FRV_BUILTIN_MCOP1:
8770 case FRV_BUILTIN_MCOP2:
8771 case FRV_BUILTIN_MDUNPACKH:
8772 case FRV_BUILTIN_MBTOHE:
8773 if (! TARGET_MEDIA_REV1)
8775 error ("this media function is only available on the fr500");
8780 case FRV_BUILTIN_MQXMACHS:
8781 case FRV_BUILTIN_MQXMACXHS:
8782 case FRV_BUILTIN_MQMACXHS:
8783 case FRV_BUILTIN_MADDACCS:
8784 case FRV_BUILTIN_MSUBACCS:
8785 case FRV_BUILTIN_MASACCS:
8786 case FRV_BUILTIN_MDADDACCS:
8787 case FRV_BUILTIN_MDSUBACCS:
8788 case FRV_BUILTIN_MDASACCS:
8789 case FRV_BUILTIN_MABSHS:
8790 case FRV_BUILTIN_MDROTLI:
8791 case FRV_BUILTIN_MCPLHI:
8792 case FRV_BUILTIN_MCPLI:
8793 case FRV_BUILTIN_MDCUTSSI:
8794 case FRV_BUILTIN_MQSATHS:
8795 case FRV_BUILTIN_MHSETLOS:
8796 case FRV_BUILTIN_MHSETLOH:
8797 case FRV_BUILTIN_MHSETHIS:
8798 case FRV_BUILTIN_MHSETHIH:
8799 case FRV_BUILTIN_MHDSETS:
8800 case FRV_BUILTIN_MHDSETH:
8801 if (! TARGET_MEDIA_REV2)
8803 error ("this media function is only available on the fr400"
8809 case FRV_BUILTIN_SMASS:
8810 case FRV_BUILTIN_SMSSS:
8811 case FRV_BUILTIN_SMU:
8812 case FRV_BUILTIN_ADDSS:
8813 case FRV_BUILTIN_SUBSS:
8814 case FRV_BUILTIN_SLASS:
8815 case FRV_BUILTIN_SCUTSS:
8816 case FRV_BUILTIN_IACCreadll:
8817 case FRV_BUILTIN_IACCreadl:
8818 case FRV_BUILTIN_IACCsetll:
8819 case FRV_BUILTIN_IACCsetl:
8820 if (!TARGET_FR405_BUILTINS)
8822 error ("this builtin function is only available"
8823 " on the fr405 and fr450");
8828 case FRV_BUILTIN_PREFETCH:
8829 if (!TARGET_FR500_FR550_BUILTINS)
8831 error ("this builtin function is only available on the fr500"
8837 case FRV_BUILTIN_MQLCLRHS:
8838 case FRV_BUILTIN_MQLMTHS:
8839 case FRV_BUILTIN_MQSLLHI:
8840 case FRV_BUILTIN_MQSRAHI:
8841 if (!TARGET_MEDIA_FR450)
8843 error ("this builtin function is only available on the fr450");
8852 /* Expand unique builtins. */
8856 case FRV_BUILTIN_MTRAP:
8857 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
8859 case FRV_BUILTIN_MCLRACC:
8860 return frv_expand_mclracc_builtin (arglist);
8862 case FRV_BUILTIN_MCLRACCA:
8864 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
8866 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
8868 case FRV_BUILTIN_MRDACC:
8869 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
8871 case FRV_BUILTIN_MRDACCG:
8872 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
8874 case FRV_BUILTIN_MWTACC:
8875 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
8877 case FRV_BUILTIN_MWTACCG:
8878 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
8880 case FRV_BUILTIN_MDPACKH:
8881 return frv_expand_mdpackh_builtin (arglist, target);
8883 case FRV_BUILTIN_IACCreadll:
8885 rtx src = frv_read_iacc_argument (DImode, &arglist);
8886 if (target == 0 || !REG_P (target))
8887 target = gen_reg_rtx (DImode);
8888 frv_split_iacc_move (target, src);
8892 case FRV_BUILTIN_IACCreadl:
8893 return frv_read_iacc_argument (SImode, &arglist);
8895 case FRV_BUILTIN_IACCsetll:
8897 rtx dest = frv_read_iacc_argument (DImode, &arglist);
8898 rtx src = frv_read_argument (&arglist);
8899 frv_split_iacc_move (dest, force_reg (DImode, src));
8903 case FRV_BUILTIN_IACCsetl:
8905 rtx dest = frv_read_iacc_argument (SImode, &arglist);
8906 rtx src = frv_read_argument (&arglist);
8907 emit_move_insn (dest, force_reg (SImode, src));
8915 /* Expand groups of builtins. */
8917 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
8918 if (d->code == fcode)
8919 return frv_expand_set_builtin (d->icode, arglist, target);
8921 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8922 if (d->code == fcode)
8923 return frv_expand_unop_builtin (d->icode, arglist, target);
8925 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8926 if (d->code == fcode)
8927 return frv_expand_binop_builtin (d->icode, arglist, target);
8929 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
8930 if (d->code == fcode)
8931 return frv_expand_cut_builtin (d->icode, arglist, target);
8933 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
8934 if (d->code == fcode)
8935 return frv_expand_binopimm_builtin (d->icode, arglist, target);
8937 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
8938 if (d->code == fcode)
8939 return frv_expand_voidbinop_builtin (d->icode, arglist);
8941 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
8942 if (d->code == fcode)
8943 return frv_expand_voidtriop_builtin (d->icode, arglist);
8945 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
8946 if (d->code == fcode)
8947 return frv_expand_voidaccop_builtin (d->icode, arglist);
8949 for (i = 0, d = bdesc_int_void2arg;
8950 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
8951 if (d->code == fcode)
8952 return frv_expand_int_void2arg (d->icode, arglist);
8954 for (i = 0, d = bdesc_prefetches;
8955 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
8956 if (d->code == fcode)
8957 return frv_expand_prefetches (d->icode, arglist);
8963 frv_in_small_data_p (tree decl)
8968 /* Don't apply the -G flag to internal compiler structures. We
8969 should leave such structures in the main data section, partly
8970 for efficiency and partly because the size of some of them
8971 (such as C++ typeinfos) is not known until later. */
8972 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
8975 /* If we already know which section the decl should be in, see if
8976 it's a small data section. */
8977 section_name = DECL_SECTION_NAME (decl);
8980 gcc_assert (TREE_CODE (section_name) == STRING_CST);
8981 if (frv_string_begins_with (section_name, ".sdata"))
8983 if (frv_string_begins_with (section_name, ".sbss"))
8988 size = int_size_in_bytes (TREE_TYPE (decl));
8989 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
8996 frv_rtx_costs (rtx x,
8997 int code ATTRIBUTE_UNUSED,
8998 int outer_code ATTRIBUTE_UNUSED,
9001 if (outer_code == MEM)
9003 /* Don't differentiate between memory addresses. All the ones
9004 we accept have equal cost. */
9005 *total = COSTS_N_INSNS (0);
9012 /* Make 12 bit integers really cheap. */
9013 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9024 *total = COSTS_N_INSNS (2);
9038 if (GET_MODE (x) == SImode)
9039 *total = COSTS_N_INSNS (1);
9040 else if (GET_MODE (x) == DImode)
9041 *total = COSTS_N_INSNS (2);
9043 *total = COSTS_N_INSNS (3);
9047 if (GET_MODE (x) == SImode)
9048 *total = COSTS_N_INSNS (2);
9050 *total = COSTS_N_INSNS (6); /* guess */
9057 *total = COSTS_N_INSNS (18);
9061 *total = COSTS_N_INSNS (3);
9070 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9073 assemble_align (POINTER_SIZE);
9076 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9081 assemble_integer_with_op ("\t.picptr\t", symbol);
9085 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9088 assemble_align (POINTER_SIZE);
9091 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9096 assemble_integer_with_op ("\t.picptr\t", symbol);
9099 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9102 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9103 int incoming ATTRIBUTE_UNUSED)
9105 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9108 #define TLS_BIAS (2048 - 16)
9110 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9111 We need to emit DTP-relative relocations. */
9114 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9116 gcc_assert (size == 4);
9117 fputs ("\t.picptr\ttlsmoff(", file);
9118 /* We want the unbiased TLS offset, so add the bias to the
9119 expression, such that the implicit biasing cancels out. */
9120 output_addr_const (file, plus_constant (x, TLS_BIAS));