1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
268 static int frv_default_flags_for_cpu (void);
269 static int frv_string_begins_with (const_tree, const char *);
270 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
271 static void frv_print_operand_memory_reference_reg
273 static void frv_print_operand_memory_reference (FILE *, rtx, int);
274 static int frv_print_operand_jump_hint (rtx);
275 static const char *comparison_string (enum rtx_code, rtx);
276 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
277 static rtx single_set_pattern (rtx);
278 static int frv_function_contains_far_jump (void);
279 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
283 static rtx frv_frame_offset_rtx (int);
284 static rtx frv_frame_mem (enum machine_mode, rtx, int);
285 static rtx frv_dwarf_store (rtx, int);
286 static void frv_frame_insn (rtx, rtx);
287 static void frv_frame_access (frv_frame_accessor_t*,
289 static void frv_frame_access_multi (frv_frame_accessor_t*,
291 static void frv_frame_access_standard_regs (enum frv_stack_op,
293 static struct machine_function *frv_init_machine_status (void);
294 static rtx frv_int_to_acc (enum insn_code, int, rtx);
295 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
296 static rtx frv_read_argument (tree, unsigned int);
297 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
298 static int frv_check_constant_argument (enum insn_code, int, rtx);
299 static rtx frv_legitimize_target (enum insn_code, rtx);
300 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
301 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
302 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
303 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
304 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
305 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
306 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
309 static rtx frv_expand_int_void2arg (enum insn_code, tree);
310 static rtx frv_expand_prefetches (enum insn_code, tree);
311 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
312 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
313 static rtx frv_expand_mclracc_builtin (tree);
314 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
315 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
316 static rtx frv_expand_noargs_builtin (enum insn_code);
317 static void frv_split_iacc_move (rtx, rtx);
318 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
319 static int frv_clear_registers_used (rtx *, void *);
320 static void frv_ifcvt_add_insn (rtx, rtx, int);
321 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
322 static rtx frv_ifcvt_load_value (rtx, rtx);
323 static int frv_acc_group_1 (rtx *, void *);
324 static unsigned int frv_insn_unit (rtx);
325 static bool frv_issues_to_branch_unit_p (rtx);
326 static int frv_cond_flags (rtx);
327 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
328 static int frv_registers_conflict_p_1 (rtx *, void *);
329 static bool frv_registers_conflict_p (rtx);
330 static void frv_registers_update_1 (rtx, const_rtx, void *);
331 static void frv_registers_update (rtx);
332 static void frv_start_packet (void);
333 static void frv_start_packet_block (void);
334 static void frv_finish_packet (void (*) (void));
335 static bool frv_pack_insn_p (rtx);
336 static void frv_add_insn_to_packet (rtx);
337 static void frv_insert_nop_in_packet (rtx);
338 static bool frv_for_each_packet (void (*) (void));
339 static bool frv_sort_insn_group_1 (enum frv_insn_group,
340 unsigned int, unsigned int,
341 unsigned int, unsigned int,
343 static int frv_compare_insns (const void *, const void *);
344 static void frv_sort_insn_group (enum frv_insn_group);
345 static void frv_reorder_packet (void);
346 static void frv_fill_unused_units (enum frv_insn_group);
347 static void frv_align_label (void);
348 static void frv_reorg_packet (void);
349 static void frv_register_nop (rtx);
350 static void frv_reorg (void);
351 static void frv_pack_insns (void);
352 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
353 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
354 static bool frv_assemble_integer (rtx, unsigned, int);
355 static void frv_init_builtins (void);
356 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
357 static void frv_init_libfuncs (void);
358 static bool frv_in_small_data_p (const_tree);
359 static void frv_asm_output_mi_thunk
360 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
361 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
364 static rtx frv_expand_builtin_saveregs (void);
365 static void frv_expand_builtin_va_start (tree, rtx);
366 static bool frv_rtx_costs (rtx, int, int, int*, bool);
367 static void frv_asm_out_constructor (rtx, int);
368 static void frv_asm_out_destructor (rtx, int);
369 static bool frv_function_symbol_referenced_p (rtx);
370 static bool frv_cannot_force_const_mem (rtx);
371 static const char *unspec_got_name (int);
372 static void frv_output_const_unspec (FILE *,
373 const struct frv_unspec *);
374 static bool frv_function_ok_for_sibcall (tree, tree);
375 static rtx frv_struct_value_rtx (tree, int);
376 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
377 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
379 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
381 static bool frv_secondary_reload (bool, rtx, enum reg_class,
383 secondary_reload_info *);
384 static bool frv_frame_pointer_required (void);
385 static bool frv_can_eliminate (const int, const int);
387 /* Allow us to easily change the default for -malloc-cc. */
388 #ifndef DEFAULT_NO_ALLOC_CC
389 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
391 #define MASK_DEFAULT_ALLOC_CC 0
394 /* Initialize the GCC target structure. */
395 #undef TARGET_ASM_FUNCTION_PROLOGUE
396 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
397 #undef TARGET_ASM_FUNCTION_EPILOGUE
398 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
399 #undef TARGET_ASM_INTEGER
400 #define TARGET_ASM_INTEGER frv_assemble_integer
401 #undef TARGET_DEFAULT_TARGET_FLAGS
402 #define TARGET_DEFAULT_TARGET_FLAGS \
403 (MASK_DEFAULT_ALLOC_CC \
410 #undef TARGET_HANDLE_OPTION
411 #define TARGET_HANDLE_OPTION frv_handle_option
412 #undef TARGET_INIT_BUILTINS
413 #define TARGET_INIT_BUILTINS frv_init_builtins
414 #undef TARGET_EXPAND_BUILTIN
415 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
416 #undef TARGET_INIT_LIBFUNCS
417 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
418 #undef TARGET_IN_SMALL_DATA_P
419 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
420 #undef TARGET_RTX_COSTS
421 #define TARGET_RTX_COSTS frv_rtx_costs
422 #undef TARGET_ASM_CONSTRUCTOR
423 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
424 #undef TARGET_ASM_DESTRUCTOR
425 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
427 #undef TARGET_ASM_OUTPUT_MI_THUNK
428 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
429 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
430 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
432 #undef TARGET_SCHED_ISSUE_RATE
433 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
435 #undef TARGET_LEGITIMIZE_ADDRESS
436 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
438 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
439 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
440 #undef TARGET_CANNOT_FORCE_CONST_MEM
441 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
443 #undef TARGET_HAVE_TLS
444 #define TARGET_HAVE_TLS HAVE_AS_TLS
446 #undef TARGET_STRUCT_VALUE_RTX
447 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
448 #undef TARGET_MUST_PASS_IN_STACK
449 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
450 #undef TARGET_PASS_BY_REFERENCE
451 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
452 #undef TARGET_ARG_PARTIAL_BYTES
453 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
455 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
456 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
457 #undef TARGET_SETUP_INCOMING_VARARGS
458 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
459 #undef TARGET_MACHINE_DEPENDENT_REORG
460 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
462 #undef TARGET_EXPAND_BUILTIN_VA_START
463 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
466 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
467 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
470 #undef TARGET_SECONDARY_RELOAD
471 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
473 #undef TARGET_LEGITIMATE_ADDRESS_P
474 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
476 #undef TARGET_FRAME_POINTER_REQUIRED
477 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
479 #undef TARGET_CAN_ELIMINATE
480 #define TARGET_CAN_ELIMINATE frv_can_eliminate
482 struct gcc_target targetm = TARGET_INITIALIZER;
484 #define FRV_SYMBOL_REF_TLS_P(RTX) \
485 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
488 /* Any function call that satisfies the machine-independent
489 requirements is eligible on FR-V. */
492 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
493 tree exp ATTRIBUTE_UNUSED)
498 /* Return true if SYMBOL is a small data symbol and relocation RELOC
499 can be used to access it directly in a load or store. */
501 static FRV_INLINE bool
502 frv_small_data_reloc_p (rtx symbol, int reloc)
504 return (GET_CODE (symbol) == SYMBOL_REF
505 && SYMBOL_REF_SMALL_P (symbol)
506 && (!TARGET_FDPIC || flag_pic == 1)
507 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
510 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
514 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
516 if (GET_CODE (x) == CONST)
520 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
522 unspec->offset += INTVAL (XEXP (x, 1));
525 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
527 unspec->symbol = XVECEXP (x, 0, 0);
528 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
530 if (unspec->offset == 0)
533 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
534 && unspec->offset > 0
535 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
542 /* Decide whether we can force certain constants to memory. If we
543 decide we can't, the caller should be able to cope with it in
546 We never allow constants to be forced into memory for TARGET_FDPIC.
547 This is necessary for several reasons:
549 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
550 target-independent code will try to force them into the constant
551 pool, thus leading to infinite recursion.
553 2. We can never introduce new constant pool references during reload.
554 Any such reference would require use of the pseudo FDPIC register.
556 3. We can't represent a constant added to a function pointer (which is
557 not the same as a pointer to a function+constant).
559 4. In many cases, it's more efficient to calculate the constant in-line. */
562 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
567 /* Implement TARGET_HANDLE_OPTION. */
570 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
575 if (strcmp (arg, "simple") == 0)
576 frv_cpu_type = FRV_CPU_SIMPLE;
577 else if (strcmp (arg, "tomcat") == 0)
578 frv_cpu_type = FRV_CPU_TOMCAT;
579 else if (strcmp (arg, "fr550") == 0)
580 frv_cpu_type = FRV_CPU_FR550;
581 else if (strcmp (arg, "fr500") == 0)
582 frv_cpu_type = FRV_CPU_FR500;
583 else if (strcmp (arg, "fr450") == 0)
584 frv_cpu_type = FRV_CPU_FR450;
585 else if (strcmp (arg, "fr405") == 0)
586 frv_cpu_type = FRV_CPU_FR405;
587 else if (strcmp (arg, "fr400") == 0)
588 frv_cpu_type = FRV_CPU_FR400;
589 else if (strcmp (arg, "fr300") == 0)
590 frv_cpu_type = FRV_CPU_FR300;
591 else if (strcmp (arg, "frv") == 0)
592 frv_cpu_type = FRV_CPU_GENERIC;
603 frv_default_flags_for_cpu (void)
605 switch (frv_cpu_type)
607 case FRV_CPU_GENERIC:
608 return MASK_DEFAULT_FRV;
611 return MASK_DEFAULT_FR550;
615 return MASK_DEFAULT_FR500;
618 return MASK_DEFAULT_FR450;
622 return MASK_DEFAULT_FR400;
626 return MASK_DEFAULT_SIMPLE;
633 /* Sometimes certain combinations of command options do not make
634 sense on a particular target machine. You can define a macro
635 `OVERRIDE_OPTIONS' to take account of this. This macro, if
636 defined, is executed once just after all the command options have
639 Don't use this macro to turn on various extra optimizations for
640 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
643 frv_override_options (void)
648 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
650 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
651 linker about linking pic and non-pic code. */
654 if (!flag_pic) /* -fPIC */
657 if (! g_switch_set) /* -G0 */
664 /* A C expression whose value is a register class containing hard
665 register REGNO. In general there is more than one such class;
666 choose a class which is "minimal", meaning that no smaller class
667 also contains the register. */
669 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
671 enum reg_class rclass;
675 int gpr_reg = regno - GPR_FIRST;
677 if (gpr_reg == GR8_REG)
680 else if (gpr_reg == GR9_REG)
683 else if (gpr_reg == GR14_REG)
684 rclass = FDPIC_FPTR_REGS;
686 else if (gpr_reg == FDPIC_REGNO)
689 else if ((gpr_reg & 3) == 0)
692 else if ((gpr_reg & 1) == 0)
699 else if (FPR_P (regno))
701 int fpr_reg = regno - GPR_FIRST;
702 if ((fpr_reg & 3) == 0)
703 rclass = QUAD_FPR_REGS;
705 else if ((fpr_reg & 1) == 0)
712 else if (regno == LR_REGNO)
715 else if (regno == LCR_REGNO)
718 else if (ICC_P (regno))
721 else if (FCC_P (regno))
724 else if (ICR_P (regno))
727 else if (FCR_P (regno))
730 else if (ACC_P (regno))
732 int r = regno - ACC_FIRST;
734 rclass = QUAD_ACC_REGS;
735 else if ((r & 1) == 0)
736 rclass = EVEN_ACC_REGS;
741 else if (ACCG_P (regno))
747 regno_reg_class[regno] = rclass;
750 /* Check for small data option */
752 g_switch_value = SDATA_DEFAULT_SIZE;
754 /* A C expression which defines the machine-dependent operand
755 constraint letters for register classes. If CHAR is such a
756 letter, the value should be the register class corresponding to
757 it. Otherwise, the value should be `NO_REGS'. The register
758 letter `r', corresponding to class `GENERAL_REGS', will not be
759 passed to this macro; you do not need to handle it.
761 The following letters are unavailable, due to being used as
766 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
767 'Q', 'R', 'S', 'T', 'U'
769 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
771 for (i = 0; i < 256; i++)
772 reg_class_from_letter[i] = NO_REGS;
774 reg_class_from_letter['a'] = ACC_REGS;
775 reg_class_from_letter['b'] = EVEN_ACC_REGS;
776 reg_class_from_letter['c'] = CC_REGS;
777 reg_class_from_letter['d'] = GPR_REGS;
778 reg_class_from_letter['e'] = EVEN_REGS;
779 reg_class_from_letter['f'] = FPR_REGS;
780 reg_class_from_letter['h'] = FEVEN_REGS;
781 reg_class_from_letter['l'] = LR_REG;
782 reg_class_from_letter['q'] = QUAD_REGS;
783 reg_class_from_letter['t'] = ICC_REGS;
784 reg_class_from_letter['u'] = FCC_REGS;
785 reg_class_from_letter['v'] = ICR_REGS;
786 reg_class_from_letter['w'] = FCR_REGS;
787 reg_class_from_letter['x'] = QUAD_FPR_REGS;
788 reg_class_from_letter['y'] = LCR_REG;
789 reg_class_from_letter['z'] = SPR_REGS;
790 reg_class_from_letter['A'] = QUAD_ACC_REGS;
791 reg_class_from_letter['B'] = ACCG_REGS;
792 reg_class_from_letter['C'] = CR_REGS;
793 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
794 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
796 /* There is no single unaligned SI op for PIC code. Sometimes we
797 need to use ".4byte" and sometimes we need to use ".picptr".
798 See frv_assemble_integer for details. */
799 if (flag_pic || TARGET_FDPIC)
800 targetm.asm_out.unaligned_op.si = 0;
802 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
803 target_flags |= MASK_LINKED_FP;
805 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
806 target_flags |= MASK_OPTIMIZE_MEMBAR;
808 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
809 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
811 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
812 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
814 init_machine_status = frv_init_machine_status;
818 /* Some machines may desire to change what optimizations are performed for
819 various optimization levels. This macro, if defined, is executed once just
820 after the optimization level is determined and before the remainder of the
821 command options have been parsed. Values set in this macro are used as the
822 default values for the other command line options.
824 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
825 `-O' is specified, and 0 if neither is specified.
827 SIZE is nonzero if `-Os' is specified, 0 otherwise.
829 You should not use this macro to change options that are not
830 machine-specific. These should uniformly selected by the same optimization
831 level on all supported machines. Use this macro to enable machine-specific
834 *Do not examine `write_symbols' in this macro!* The debugging options are
835 *not supposed to alter the generated code. */
837 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
838 scheduling pass at the current time. */
840 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
844 #ifdef DISABLE_SCHED2
845 flag_schedule_insns_after_reload = 0;
854 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
857 frv_string_begins_with (const_tree name, const char *prefix)
859 const int prefix_len = strlen (prefix);
861 /* Remember: NAME's length includes the null terminator. */
862 return (TREE_STRING_LENGTH (name) > prefix_len
863 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
866 /* Zero or more C statements that may conditionally modify two variables
867 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
868 been initialized from the two preceding macros.
870 This is necessary in case the fixed or call-clobbered registers depend on
873 You need not define this macro if it has no work to do.
875 If the usage of an entire class of registers depends on the target flags,
876 you may indicate this to GCC by using this macro to modify `fixed_regs' and
877 `call_used_regs' to 1 for each of the registers in the classes which should
878 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
879 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
881 (However, if this class is not included in `GENERAL_REGS' and all of the
882 insn patterns whose constraints permit this class are controlled by target
883 switches, then GCC will automatically avoid using these registers when the
884 target switches are opposed to them.) */
887 frv_conditional_register_usage (void)
891 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
892 fixed_regs[i] = call_used_regs[i] = 1;
894 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
895 fixed_regs[i] = call_used_regs[i] = 1;
897 /* Reserve the registers used for conditional execution. At present, we need
898 1 ICC and 1 ICR register. */
899 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
900 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
904 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
905 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
906 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
907 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
911 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
912 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
915 /* If -fpic, SDA_BASE_REG is the PIC register. */
916 if (g_switch_value == 0 && !flag_pic)
917 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
920 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
926 * Compute the stack frame layout
929 * +---------------+-----------------------+-----------------------+
930 * |Register |type |caller-save/callee-save|
931 * +---------------+-----------------------+-----------------------+
932 * |GR0 |Zero register | - |
933 * |GR1 |Stack pointer(SP) | - |
934 * |GR2 |Frame pointer(FP) | - |
935 * |GR3 |Hidden parameter | caller save |
936 * |GR4-GR7 | - | caller save |
937 * |GR8-GR13 |Argument register | caller save |
938 * |GR14-GR15 | - | caller save |
939 * |GR16-GR31 | - | callee save |
940 * |GR32-GR47 | - | caller save |
941 * |GR48-GR63 | - | callee save |
942 * |FR0-FR15 | - | caller save |
943 * |FR16-FR31 | - | callee save |
944 * |FR32-FR47 | - | caller save |
945 * |FR48-FR63 | - | callee save |
946 * +---------------+-----------------------+-----------------------+
950 * SP-> |-----------------------------------|
952 * |-----------------------------------|
953 * | Register save area |
954 * |-----------------------------------|
955 * | Local variable save area |
956 * FP-> |-----------------------------------|
958 * |-----------------------------------|
959 * | Hidden parameter save area |
960 * |-----------------------------------|
961 * | Return address(LR) storage area |
962 * |-----------------------------------|
963 * | Padding for alignment |
964 * |-----------------------------------|
965 * | Register argument area |
966 * OLD SP-> |-----------------------------------|
968 * |-----------------------------------|
971 * Argument area/Parameter area:
973 * When a function is called, this area is used for argument transfer. When
974 * the argument is set up by the caller function, this area is referred to as
975 * the argument area. When the argument is referenced by the callee function,
976 * this area is referred to as the parameter area. The area is allocated when
977 * all arguments cannot be placed on the argument register at the time of
980 * Register save area:
982 * This is a register save area that must be guaranteed for the caller
983 * function. This area is not secured when the register save operation is not
986 * Local variable save area:
988 * This is the area for local variables and temporary variables.
992 * This area stores the FP value of the caller function.
994 * Hidden parameter save area:
996 * This area stores the start address of the return value storage
997 * area for a struct/union return function.
998 * When a struct/union is used as the return value, the caller
999 * function stores the return value storage area start address in
1000 * register GR3 and passes it to the caller function.
1001 * The callee function interprets the address stored in the GR3
1002 * as the return value storage area start address.
1003 * When register GR3 needs to be saved into memory, the callee
1004 * function saves it in the hidden parameter save area. This
1005 * area is not secured when the save operation is not needed.
1007 * Return address(LR) storage area:
1009 * This area saves the LR. The LR stores the address of a return to the caller
1010 * function for the purpose of function calling.
1012 * Argument register area:
1014 * This area saves the argument register. This area is not secured when the
1015 * save operation is not needed.
1019 * Arguments, the count of which equals the count of argument registers (6
1020 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1021 * function. When a struct/union return function is called, the return value
1022 * area address is stored in register GR3. Arguments not placed in the
1023 * argument registers will be stored in the stack argument area for transfer
1024 * purposes. When an 8-byte type argument is to be delivered using registers,
1025 * it is divided into two and placed in two registers for transfer. When
1026 * argument registers must be saved to memory, the callee function secures an
1027 * argument register save area in the stack. In this case, a continuous
1028 * argument register save area must be established in the parameter area. The
1029 * argument register save area must be allocated as needed to cover the size of
1030 * the argument register to be saved. If the function has a variable count of
1031 * arguments, it saves all argument registers in the argument register save
1034 * Argument Extension Format:
1036 * When an argument is to be stored in the stack, its type is converted to an
1037 * extended type in accordance with the individual argument type. The argument
1038 * is freed by the caller function after the return from the callee function is
1041 * +-----------------------+---------------+------------------------+
1042 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1043 * +-----------------------+---------------+------------------------+
1045 * |signed char |int | 4 |
1046 * |unsigned char |int | 4 |
1047 * |[signed] short int |int | 4 |
1048 * |unsigned short int |int | 4 |
1049 * |[signed] int |No extension | 4 |
1050 * |unsigned int |No extension | 4 |
1051 * |[signed] long int |No extension | 4 |
1052 * |unsigned long int |No extension | 4 |
1053 * |[signed] long long int |No extension | 8 |
1054 * |unsigned long long int |No extension | 8 |
1055 * |float |double | 8 |
1056 * |double |No extension | 8 |
1057 * |long double |No extension | 8 |
1058 * |pointer |No extension | 4 |
1059 * |struct/union |- | 4 (*1) |
1060 * +-----------------------+---------------+------------------------+
1062 * When a struct/union is to be delivered as an argument, the caller copies it
1063 * to the local variable area and delivers the address of that area.
1067 * +-------------------------------+----------------------+
1068 * |Return Value Type |Return Value Interface|
1069 * +-------------------------------+----------------------+
1071 * |[signed|unsigned] char |GR8 |
1072 * |[signed|unsigned] short int |GR8 |
1073 * |[signed|unsigned] int |GR8 |
1074 * |[signed|unsigned] long int |GR8 |
1076 * |[signed|unsigned] long long int|GR8 & GR9 |
1078 * |double |GR8 & GR9 |
1079 * |long double |GR8 & GR9 |
1080 * |struct/union |(*1) |
1081 * +-------------------------------+----------------------+
1083 * When a struct/union is used as the return value, the caller function stores
1084 * the start address of the return value storage area into GR3 and then passes
1085 * it to the callee function. The callee function interprets GR3 as the start
1086 * address of the return value storage area. When this address needs to be
1087 * saved in memory, the callee function secures the hidden parameter save area
1088 * and saves the address in that area.
1092 frv_stack_info (void)
1094 static frv_stack_t info, zero_info;
1095 frv_stack_t *info_ptr = &info;
1096 tree fndecl = current_function_decl;
1104 /* If we've already calculated the values and reload is complete,
1106 if (frv_stack_cache)
1107 return frv_stack_cache;
1109 /* Zero all fields. */
1112 /* Set up the register range information. */
1113 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1114 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1115 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1116 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1118 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1119 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1120 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1121 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1123 info_ptr->regs[STACK_REGS_LR].name = "lr";
1124 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1125 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1126 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1128 info_ptr->regs[STACK_REGS_CC].name = "cc";
1129 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1130 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1131 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1133 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1134 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1135 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1137 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1138 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1139 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1140 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1141 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1143 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1144 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1145 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1146 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1148 info_ptr->regs[STACK_REGS_FP].name = "fp";
1149 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1150 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1151 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1153 /* Determine if this is a stdarg function. If so, allocate space to store
1160 /* Find the last argument, and see if it is __builtin_va_alist. */
1161 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1163 next_arg = TREE_CHAIN (cur_arg);
1164 if (next_arg == (tree)0)
1166 if (DECL_NAME (cur_arg)
1167 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1175 /* Iterate over all of the register ranges. */
1176 for (range = 0; range < STACK_REGS_MAX; range++)
1178 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1179 int first = reg_ptr->first;
1180 int last = reg_ptr->last;
1182 int size_2words = 0;
1185 /* Calculate which registers need to be saved & save area size. */
1189 for (regno = first; regno <= last; regno++)
1191 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1192 || (crtl->calls_eh_return
1193 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1194 || (!TARGET_FDPIC && flag_pic
1195 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1197 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1198 size_1word += UNITS_PER_WORD;
1203 /* Calculate whether we need to create a frame after everything else
1204 has been processed. */
1209 if (df_regs_ever_live_p (LR_REGNO)
1211 /* This is set for __builtin_return_address, etc. */
1212 || cfun->machine->frame_needed
1213 || (TARGET_LINKED_FP && frame_pointer_needed)
1214 || (!TARGET_FDPIC && flag_pic
1215 && crtl->uses_pic_offset_table))
1217 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1218 size_1word += UNITS_PER_WORD;
1222 case STACK_REGS_STDARG:
1225 /* If this is a stdarg function with a non varardic
1226 argument split between registers and the stack,
1227 adjust the saved registers downward. */
1228 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1231 for (regno = first; regno <= last; regno++)
1233 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1234 size_1word += UNITS_PER_WORD;
1237 info_ptr->stdarg_size = size_1word;
1241 case STACK_REGS_STRUCT:
1242 if (cfun->returns_struct)
1244 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1245 size_1word += UNITS_PER_WORD;
1253 /* If this is a field, it only takes one word. */
1254 if (reg_ptr->field_p)
1255 size_1word = UNITS_PER_WORD;
1257 /* Determine which register pairs can be saved together. */
1258 else if (reg_ptr->dword_p && TARGET_DWORD)
1260 for (regno = first; regno < last; regno += 2)
1262 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1264 size_2words += 2 * UNITS_PER_WORD;
1265 size_1word -= 2 * UNITS_PER_WORD;
1266 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1267 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1272 reg_ptr->size_1word = size_1word;
1273 reg_ptr->size_2words = size_2words;
1275 if (! reg_ptr->special_p)
1277 info_ptr->regs_size_1word += size_1word;
1278 info_ptr->regs_size_2words += size_2words;
1283 /* Set up the sizes of each each field in the frame body, making the sizes
1284 of each be divisible by the size of a dword if dword operations might
1285 be used, or the size of a word otherwise. */
1286 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1288 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1289 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1290 + info_ptr->regs_size_1word,
1292 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1294 info_ptr->pretend_size = crtl->args.pretend_args_size;
1296 /* Work out the size of the frame, excluding the header. Both the frame
1297 body and register parameter area will be dword-aligned. */
1298 info_ptr->total_size
1299 = (ADDR_ALIGN (info_ptr->parameter_size
1300 + info_ptr->regs_size
1301 + info_ptr->vars_size,
1303 + ADDR_ALIGN (info_ptr->pretend_size
1304 + info_ptr->stdarg_size,
1305 2 * UNITS_PER_WORD));
1307 /* See if we need to create a frame at all, if so add header area. */
1308 if (info_ptr->total_size > 0
1309 || frame_pointer_needed
1310 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1311 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1313 offset = info_ptr->parameter_size;
1314 info_ptr->header_size = 4 * UNITS_PER_WORD;
1315 info_ptr->total_size += 4 * UNITS_PER_WORD;
1317 /* Calculate the offsets to save normal register pairs. */
1318 for (range = 0; range < STACK_REGS_MAX; range++)
1320 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1321 if (! reg_ptr->special_p)
1323 int first = reg_ptr->first;
1324 int last = reg_ptr->last;
1327 for (regno = first; regno <= last; regno++)
1328 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1329 && regno != FRAME_POINTER_REGNUM
1330 && (regno < FIRST_ARG_REGNUM
1331 || regno > LAST_ARG_REGNUM))
1333 info_ptr->reg_offset[regno] = offset;
1334 offset += 2 * UNITS_PER_WORD;
1339 /* Calculate the offsets to save normal single registers. */
1340 for (range = 0; range < STACK_REGS_MAX; range++)
1342 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1343 if (! reg_ptr->special_p)
1345 int first = reg_ptr->first;
1346 int last = reg_ptr->last;
1349 for (regno = first; regno <= last; regno++)
1350 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1351 && regno != FRAME_POINTER_REGNUM
1352 && (regno < FIRST_ARG_REGNUM
1353 || regno > LAST_ARG_REGNUM))
1355 info_ptr->reg_offset[regno] = offset;
1356 offset += UNITS_PER_WORD;
1361 /* Calculate the offset to save the local variables at. */
1362 offset = ADDR_ALIGN (offset, alignment);
1363 if (info_ptr->vars_size)
1365 info_ptr->vars_offset = offset;
1366 offset += info_ptr->vars_size;
1369 /* Align header to a dword-boundary. */
1370 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1372 /* Calculate the offsets in the fixed frame. */
1373 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1374 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1375 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1377 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1378 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1379 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1381 if (cfun->returns_struct)
1383 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1384 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1385 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1388 /* Calculate the offsets to store the arguments passed in registers
1389 for stdarg functions. The register pairs are first and the single
1390 register if any is last. The register save area starts on a
1392 if (info_ptr->stdarg_size)
1394 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1395 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1398 /* Skip the header. */
1399 offset += 4 * UNITS_PER_WORD;
1400 for (regno = first; regno <= last; regno++)
1402 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1404 info_ptr->reg_offset[regno] = offset;
1405 offset += 2 * UNITS_PER_WORD;
1407 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1409 info_ptr->reg_offset[regno] = offset;
1410 offset += UNITS_PER_WORD;
1416 if (reload_completed)
1417 frv_stack_cache = info_ptr;
1423 /* Print the information about the frv stack offsets, etc. when debugging. */
1426 frv_debug_stack (frv_stack_t *info)
1431 info = frv_stack_info ();
1433 fprintf (stderr, "\nStack information for function %s:\n",
1434 ((current_function_decl && DECL_NAME (current_function_decl))
1435 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1438 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1439 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1440 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1441 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1442 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1444 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1445 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1446 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1447 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1449 for (range = 0; range < STACK_REGS_MAX; range++)
1451 frv_stack_regs_t *regs = &(info->regs[range]);
1452 if ((regs->size_1word + regs->size_2words) > 0)
1454 int first = regs->first;
1455 int last = regs->last;
1458 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1459 regs->name, regs->size_1word + regs->size_2words,
1460 regs->size_1word, regs->size_2words);
1462 for (regno = first; regno <= last; regno++)
1464 if (info->save_p[regno] == REG_SAVE_1WORD)
1465 fprintf (stderr, " %s (%d)", reg_names[regno],
1466 info->reg_offset[regno]);
1468 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1469 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1470 reg_names[regno+1], info->reg_offset[regno]);
1473 fputc ('\n', stderr);
1483 /* Used during final to control the packing of insns. The value is
1484 1 if the current instruction should be packed with the next one,
1485 0 if it shouldn't or -1 if packing is disabled altogether. */
1487 static int frv_insn_packing_flag;
1489 /* True if the current function contains a far jump. */
1492 frv_function_contains_far_jump (void)
1494 rtx insn = get_insns ();
1496 && !(GET_CODE (insn) == JUMP_INSN
1497 /* Ignore tablejump patterns. */
1498 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1499 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1500 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1501 insn = NEXT_INSN (insn);
1502 return (insn != NULL);
1505 /* For the FRV, this function makes sure that a function with far jumps
1506 will return correctly. It also does the VLIW packing. */
1509 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1511 /* If no frame was created, check whether the function uses a call
1512 instruction to implement a far jump. If so, save the link in gr3 and
1513 replace all returns to LR with returns to GR3. GR3 is used because it
1514 is call-clobbered, because is not available to the register allocator,
1515 and because all functions that take a hidden argument pointer will have
1517 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1521 /* Just to check that the above comment is true. */
1522 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1524 /* Generate the instruction that saves the link register. */
1525 fprintf (file, "\tmovsg lr,gr3\n");
1527 /* Replace the LR with GR3 in *return_internal patterns. The insn
1528 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1529 simply emit a different assembly directive because bralr and jmpl
1530 execute in different units. */
1531 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1532 if (GET_CODE (insn) == JUMP_INSN)
1534 rtx pattern = PATTERN (insn);
1535 if (GET_CODE (pattern) == PARALLEL
1536 && XVECLEN (pattern, 0) >= 2
1537 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1538 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1540 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1541 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1542 SET_REGNO (address, GPR_FIRST + 3);
1549 /* Allow the garbage collector to free the nops created by frv_reorg. */
1550 memset (frv_nops, 0, sizeof (frv_nops));
1554 /* Return the next available temporary register in a given class. */
1557 frv_alloc_temp_reg (
1558 frv_tmp_reg_t *info, /* which registers are available */
1559 enum reg_class rclass, /* register class desired */
1560 enum machine_mode mode, /* mode to allocate register with */
1561 int mark_as_used, /* register not available after allocation */
1562 int no_abort) /* return NULL instead of aborting */
1564 int regno = info->next_reg[ (int)rclass ];
1565 int orig_regno = regno;
1566 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1571 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1572 && TEST_HARD_REG_BIT (info->regs, regno))
1575 if (++regno >= FIRST_PSEUDO_REGISTER)
1577 if (regno == orig_regno)
1579 gcc_assert (no_abort);
1584 nr = HARD_REGNO_NREGS (regno, mode);
1585 info->next_reg[ (int)rclass ] = regno + nr;
1588 for (i = 0; i < nr; i++)
1589 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1591 return gen_rtx_REG (mode, regno);
1595 /* Return an rtx with the value OFFSET, which will either be a register or a
1596 signed 12-bit integer. It can be used as the second operand in an "add"
1597 instruction, or as the index in a load or store.
1599 The function returns a constant rtx if OFFSET is small enough, otherwise
1600 it loads the constant into register OFFSET_REGNO and returns that. */
1602 frv_frame_offset_rtx (int offset)
1604 rtx offset_rtx = GEN_INT (offset);
1605 if (IN_RANGE_P (offset, -2048, 2047))
1609 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1610 if (IN_RANGE_P (offset, -32768, 32767))
1611 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1614 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1615 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1621 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1622 prologue and epilogue uses such expressions to access the stack. */
1624 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1626 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1628 frv_frame_offset_rtx (offset)));
1631 /* Generate a frame-related expression:
1633 (set REG (mem (plus (sp) (const_int OFFSET)))).
1635 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1636 instructions. Marking the expressions as frame-related is superfluous if
1637 the note contains just a single set. But if the note contains a PARALLEL
1638 or SEQUENCE that has several sets, each set must be individually marked
1639 as frame-related. */
1641 frv_dwarf_store (rtx reg, int offset)
1643 rtx set = gen_rtx_SET (VOIDmode,
1644 gen_rtx_MEM (GET_MODE (reg),
1645 plus_constant (stack_pointer_rtx,
1648 RTX_FRAME_RELATED_P (set) = 1;
1652 /* Emit a frame-related instruction whose pattern is PATTERN. The
1653 instruction is the last in a sequence that cumulatively performs the
1654 operation described by DWARF_PATTERN. The instruction is marked as
1655 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1658 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1660 rtx insn = emit_insn (pattern);
1661 RTX_FRAME_RELATED_P (insn) = 1;
1662 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1667 /* Emit instructions that transfer REG to or from the memory location (sp +
1668 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1669 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1670 function to store registers and only the epilogue uses it to load them.
1672 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1673 The generated instruction will use BASE as its base register. BASE may
1674 simply be the stack pointer, but if several accesses are being made to a
1675 region far away from the stack pointer, it may be more efficient to set
1676 up a temporary instead.
1678 Store instructions will be frame-related and will be annotated with the
1679 overall effect of the store. Load instructions will be followed by a
1680 (use) to prevent later optimizations from zapping them.
1682 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1683 as a temporary in such cases. */
1685 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1687 enum machine_mode mode = GET_MODE (reg);
1688 rtx mem = frv_frame_mem (mode,
1690 stack_offset - accessor->base_offset);
1692 if (accessor->op == FRV_LOAD)
1694 if (SPR_P (REGNO (reg)))
1696 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1697 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1698 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1702 /* We cannot use reg+reg addressing for DImode access. */
1704 && GET_CODE (XEXP (mem, 0)) == PLUS
1705 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1706 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1708 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1709 rtx insn = emit_move_insn (temp,
1710 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1711 XEXP (XEXP (mem, 0), 1)));
1712 mem = gen_rtx_MEM (DImode, temp);
1714 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1720 if (SPR_P (REGNO (reg)))
1722 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1723 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1724 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1725 frv_dwarf_store (reg, stack_offset));
1727 else if (mode == DImode)
1729 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1730 with a separate save for each register. */
1731 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1732 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1733 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1734 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1736 /* Also we cannot use reg+reg addressing. */
1737 if (GET_CODE (XEXP (mem, 0)) == PLUS
1738 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1739 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1741 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1742 rtx insn = emit_move_insn (temp,
1743 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1744 XEXP (XEXP (mem, 0), 1)));
1745 mem = gen_rtx_MEM (DImode, temp);
1748 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1749 gen_rtx_PARALLEL (VOIDmode,
1750 gen_rtvec (2, set1, set2)));
1753 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1754 frv_dwarf_store (reg, stack_offset));
1758 /* A function that uses frv_frame_access to transfer a group of registers to
1759 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1760 is the stack information generated by frv_stack_info, and REG_SET is the
1761 number of the register set to transfer. */
1763 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1767 frv_stack_regs_t *regs_info;
1770 regs_info = &info->regs[reg_set];
1771 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1772 if (info->save_p[regno])
1773 frv_frame_access (accessor,
1774 info->save_p[regno] == REG_SAVE_2WORDS
1775 ? gen_rtx_REG (DImode, regno)
1776 : gen_rtx_REG (SImode, regno),
1777 info->reg_offset[regno]);
1780 /* Save or restore callee-saved registers that are kept outside the frame
1781 header. The function saves the registers if OP is FRV_STORE and restores
1782 them if OP is FRV_LOAD. INFO is the stack information generated by
1785 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1787 frv_frame_accessor_t accessor;
1790 accessor.base = stack_pointer_rtx;
1791 accessor.base_offset = 0;
1792 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1793 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1794 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1798 /* Called after register allocation to add any instructions needed for the
1799 prologue. Using a prologue insn is favored compared to putting all of the
1800 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1801 it allows the scheduler to intermix instructions with the saves of
1802 the caller saved registers. In some cases, it might be necessary
1803 to emit a barrier instruction as the last insn to prevent such
1806 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1807 so that the debug info generation code can handle them properly. */
1809 frv_expand_prologue (void)
1811 frv_stack_t *info = frv_stack_info ();
1812 rtx sp = stack_pointer_rtx;
1813 rtx fp = frame_pointer_rtx;
1814 frv_frame_accessor_t accessor;
1816 if (TARGET_DEBUG_STACK)
1817 frv_debug_stack (info);
1819 if (info->total_size == 0)
1822 /* We're interested in three areas of the frame here:
1824 A: the register save area
1826 C: the header after B
1828 If the frame pointer isn't used, we'll have to set up A, B and C
1829 using the stack pointer. If the frame pointer is used, we'll access
1833 B: set up using sp or a temporary (see below)
1836 We set up B using the stack pointer if the frame is small enough.
1837 Otherwise, it's more efficient to copy the old stack pointer into a
1838 temporary and use that.
1840 Note that it's important to make sure the prologue and epilogue use the
1841 same registers to access A and C, since doing otherwise will confuse
1842 the aliasing code. */
1844 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1845 isn't used, the same method will serve for C. */
1846 accessor.op = FRV_STORE;
1847 if (frame_pointer_needed && info->total_size > 2048)
1851 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1852 accessor.base_offset = info->total_size;
1853 insn = emit_insn (gen_movsi (accessor.base, sp));
1857 accessor.base = stack_pointer_rtx;
1858 accessor.base_offset = 0;
1861 /* Allocate the stack space. */
1863 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1864 rtx dwarf_offset = GEN_INT (-info->total_size);
1866 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1869 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1872 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1873 and point the new one to that location. */
1874 if (frame_pointer_needed)
1876 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1878 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1879 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1881 rtx asm_src = plus_constant (accessor.base,
1882 fp_offset - accessor.base_offset);
1883 rtx dwarf_src = plus_constant (sp, fp_offset);
1885 /* Store the old frame pointer at (sp + FP_OFFSET). */
1886 frv_frame_access (&accessor, fp, fp_offset);
1888 /* Set up the new frame pointer. */
1889 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1890 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1892 /* Access region C from the frame pointer. */
1894 accessor.base_offset = fp_offset;
1897 /* Set up region C. */
1898 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1899 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1900 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1902 /* Set up region A. */
1903 frv_frame_access_standard_regs (FRV_STORE, info);
1905 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1906 scheduler from moving loads before the stores saving the registers. */
1907 if (info->stdarg_size > 0)
1908 emit_insn (gen_blockage ());
1910 /* Set up pic register/small data register for this function. */
1911 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1912 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1913 gen_rtx_REG (Pmode, LR_REGNO),
1914 gen_rtx_REG (SImode, OFFSET_REGNO)));
1918 /* Under frv, all of the work is done via frv_expand_epilogue, but
1919 this function provides a convenient place to do cleanup. */
1922 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1923 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1925 frv_stack_cache = (frv_stack_t *)0;
1927 /* Zap last used registers for conditional execution. */
1928 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1930 /* Release the bitmap of created insns. */
1931 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1935 /* Called after register allocation to add any instructions needed for the
1936 epilogue. Using an epilogue insn is favored compared to putting all of the
1937 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1938 it allows the scheduler to intermix instructions with the saves of
1939 the caller saved registers. In some cases, it might be necessary
1940 to emit a barrier instruction as the last insn to prevent such
1944 frv_expand_epilogue (bool emit_return)
1946 frv_stack_t *info = frv_stack_info ();
1947 rtx fp = frame_pointer_rtx;
1948 rtx sp = stack_pointer_rtx;
1952 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1954 /* Restore the stack pointer to its original value if alloca or the like
1956 if (! current_function_sp_is_unchanging)
1957 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1959 /* Restore the callee-saved registers that were used in this function. */
1960 frv_frame_access_standard_regs (FRV_LOAD, info);
1962 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1963 no return instruction should be emitted. */
1964 if (info->save_p[LR_REGNO])
1969 /* Use the same method to access the link register's slot as we did in
1970 the prologue. In other words, use the frame pointer if available,
1971 otherwise use the stack pointer.
1973 LR_OFFSET is the offset of the link register's slot from the start
1974 of the frame and MEM is a memory rtx for it. */
1975 lr_offset = info->reg_offset[LR_REGNO];
1976 if (frame_pointer_needed)
1977 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1979 mem = frv_frame_mem (Pmode, sp, lr_offset);
1981 /* Load the old link register into a GPR. */
1982 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1983 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1986 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1988 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1989 the load is preserved. */
1990 if (frame_pointer_needed)
1992 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1996 /* Deallocate the stack frame. */
1997 if (info->total_size != 0)
1999 rtx offset = frv_frame_offset_rtx (info->total_size);
2000 emit_insn (gen_stack_adjust (sp, sp, offset));
2003 /* If this function uses eh_return, add the final stack adjustment now. */
2004 if (crtl->calls_eh_return)
2005 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2008 emit_jump_insn (gen_epilogue_return (return_addr));
2011 rtx lr = return_addr;
2013 if (REGNO (return_addr) != LR_REGNO)
2015 lr = gen_rtx_REG (Pmode, LR_REGNO);
2016 emit_move_insn (lr, return_addr);
2024 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2027 frv_asm_output_mi_thunk (FILE *file,
2028 tree thunk_fndecl ATTRIBUTE_UNUSED,
2029 HOST_WIDE_INT delta,
2030 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2033 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2034 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2035 const char *name_jmp = reg_names[JUMP_REGNO];
2036 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2038 /* Do the add using an addi if possible. */
2039 if (IN_RANGE_P (delta, -2048, 2047))
2040 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2043 const char *const name_add = reg_names[TEMP_REGNO];
2044 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2045 parallel, delta, name_add);
2046 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2048 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2053 const char *name_pic = reg_names[FDPIC_REGNO];
2054 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2058 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2059 assemble_name (file, name_func);
2060 fprintf (file, "),%s\n", name_jmp);
2062 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2063 assemble_name (file, name_func);
2064 fprintf (file, "),%s\n", name_jmp);
2066 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2070 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2071 assemble_name (file, name_func);
2072 fprintf (file, "\t)), %s\n", name_jmp);
2077 fprintf (file, "\tsethi%s #hi(", parallel);
2078 assemble_name (file, name_func);
2079 fprintf (file, "),%s\n", name_jmp);
2081 fprintf (file, "\tsetlo #lo(");
2082 assemble_name (file, name_func);
2083 fprintf (file, "),%s\n", name_jmp);
2087 /* Use JUMP_REGNO as a temporary PIC register. */
2088 const char *name_lr = reg_names[LR_REGNO];
2089 const char *name_gppic = name_jmp;
2090 const char *name_tmp = reg_names[TEMP_REGNO];
2092 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2093 fprintf (file, "\tcall 1f\n");
2094 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2095 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2096 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2097 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2098 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2100 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2101 assemble_name (file, name_func);
2102 fprintf (file, "),%s\n", name_tmp);
2104 fprintf (file, "\tsetlo #gprello(");
2105 assemble_name (file, name_func);
2106 fprintf (file, "),%s\n", name_tmp);
2108 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2111 /* Jump to the function address. */
2112 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2117 /* On frv, create a frame whenever we need to create stack. */
2120 frv_frame_pointer_required (void)
2122 /* If we forgoing the usual linkage requirements, we only need
2123 a frame pointer if the stack pointer might change. */
2124 if (!TARGET_LINKED_FP)
2125 return !current_function_sp_is_unchanging;
2127 if (! current_function_is_leaf)
2130 if (get_frame_size () != 0)
2136 if (!current_function_sp_is_unchanging)
2139 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2145 if (cfun->machine->frame_needed)
2152 /* Worker function for TARGET_CAN_ELIMINATE. */
2155 frv_can_eliminate (const int from, const int to)
2157 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2158 ? ! frame_pointer_needed
2162 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2163 initial difference between the specified pair of registers. This macro must
2164 be defined if `ELIMINABLE_REGS' is defined. */
2166 /* See frv_stack_info for more details on the frv stack frame. */
2169 frv_initial_elimination_offset (int from, int to)
2171 frv_stack_t *info = frv_stack_info ();
2174 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2175 ret = info->total_size - info->pretend_size;
2177 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2178 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2180 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2181 ret = (info->total_size
2182 - info->reg_offset[FRAME_POINTER_REGNUM]
2183 - info->pretend_size);
2188 if (TARGET_DEBUG_STACK)
2189 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2190 reg_names [from], reg_names[to], ret);
2196 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2199 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2200 enum machine_mode mode,
2201 tree type ATTRIBUTE_UNUSED,
2205 if (TARGET_DEBUG_ARG)
2207 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2208 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2212 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2215 frv_expand_builtin_saveregs (void)
2217 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2219 if (TARGET_DEBUG_ARG)
2220 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2223 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2227 /* Expand __builtin_va_start to do the va_start macro. */
2230 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2233 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2235 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2236 GEN_INT (UNITS_PER_WORD * num));
2238 if (TARGET_DEBUG_ARG)
2240 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2241 crtl->args.info, num);
2243 debug_rtx (nextarg);
2246 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2247 fold_convert (TREE_TYPE (valist),
2248 make_tree (sizetype, nextarg)));
2249 TREE_SIDE_EFFECTS (t) = 1;
2251 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2255 /* Expand a block move operation, and return 1 if successful. Return 0
2256 if we should let the compiler generate normal code.
2258 operands[0] is the destination
2259 operands[1] is the source
2260 operands[2] is the length
2261 operands[3] is the alignment */
2263 /* Maximum number of loads to do before doing the stores */
2264 #ifndef MAX_MOVE_REG
2265 #define MAX_MOVE_REG 4
2268 /* Maximum number of total loads to do. */
2269 #ifndef TOTAL_MOVE_REG
2270 #define TOTAL_MOVE_REG 8
2274 frv_expand_block_move (rtx operands[])
2276 rtx orig_dest = operands[0];
2277 rtx orig_src = operands[1];
2278 rtx bytes_rtx = operands[2];
2279 rtx align_rtx = operands[3];
2280 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2293 rtx stores[MAX_MOVE_REG];
2295 enum machine_mode mode;
2297 /* If this is not a fixed size move, just call memcpy. */
2301 /* This should be a fixed size alignment. */
2302 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2304 align = INTVAL (align_rtx);
2306 /* Anything to move? */
2307 bytes = INTVAL (bytes_rtx);
2311 /* Don't support real large moves. */
2312 if (bytes > TOTAL_MOVE_REG*align)
2315 /* Move the address into scratch registers. */
2316 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2317 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2319 num_reg = offset = 0;
2320 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2322 /* Calculate the correct offset for src/dest. */
2326 dest_addr = dest_reg;
2330 src_addr = plus_constant (src_reg, offset);
2331 dest_addr = plus_constant (dest_reg, offset);
2334 /* Generate the appropriate load and store, saving the stores
2336 if (bytes >= 4 && align >= 4)
2338 else if (bytes >= 2 && align >= 2)
2343 move_bytes = GET_MODE_SIZE (mode);
2344 tmp_reg = gen_reg_rtx (mode);
2345 src_mem = change_address (orig_src, mode, src_addr);
2346 dest_mem = change_address (orig_dest, mode, dest_addr);
2347 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2348 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2350 if (num_reg >= MAX_MOVE_REG)
2352 for (i = 0; i < num_reg; i++)
2353 emit_insn (stores[i]);
2358 for (i = 0; i < num_reg; i++)
2359 emit_insn (stores[i]);
2365 /* Expand a block clear operation, and return 1 if successful. Return 0
2366 if we should let the compiler generate normal code.
2368 operands[0] is the destination
2369 operands[1] is the length
2370 operands[3] is the alignment */
2373 frv_expand_block_clear (rtx operands[])
2375 rtx orig_dest = operands[0];
2376 rtx bytes_rtx = operands[1];
2377 rtx align_rtx = operands[3];
2378 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2387 enum machine_mode mode;
2389 /* If this is not a fixed size move, just call memcpy. */
2393 /* This should be a fixed size alignment. */
2394 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2396 align = INTVAL (align_rtx);
2398 /* Anything to move? */
2399 bytes = INTVAL (bytes_rtx);
2403 /* Don't support real large clears. */
2404 if (bytes > TOTAL_MOVE_REG*align)
2407 /* Move the address into a scratch register. */
2408 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2410 num_reg = offset = 0;
2411 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2413 /* Calculate the correct offset for src/dest. */
2414 dest_addr = ((offset == 0)
2416 : plus_constant (dest_reg, offset));
2418 /* Generate the appropriate store of gr0. */
2419 if (bytes >= 4 && align >= 4)
2421 else if (bytes >= 2 && align >= 2)
2426 clear_bytes = GET_MODE_SIZE (mode);
2427 dest_mem = change_address (orig_dest, mode, dest_addr);
2428 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2435 /* The following variable is used to output modifiers of assembler
2436 code of the current output insn. */
2438 static rtx *frv_insn_operands;
2440 /* The following function is used to add assembler insn code suffix .p
2441 if it is necessary. */
2444 frv_asm_output_opcode (FILE *f, const char *ptr)
2448 if (frv_insn_packing_flag <= 0)
2451 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2454 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2455 || (*ptr >= 'A' && *ptr <= 'Z')))
2457 int letter = *ptr++;
2460 frv_print_operand (f, frv_insn_operands [c], letter);
2461 while ((c = *ptr) >= '0' && c <= '9')
2473 /* Set up the packing bit for the current output insn. Note that this
2474 function is not called for asm insns. */
2477 frv_final_prescan_insn (rtx insn, rtx *opvec,
2478 int noperands ATTRIBUTE_UNUSED)
2482 if (frv_insn_packing_flag >= 0)
2484 frv_insn_operands = opvec;
2485 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2487 else if (recog_memoized (insn) >= 0
2488 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2489 /* Packing optimizations have been disabled, but INSN can only
2490 be issued in M1. Insert an mnop in M0. */
2491 fprintf (asm_out_file, "\tmnop.p\n");
2497 /* A C expression whose value is RTL representing the address in a stack frame
2498 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2499 an RTL expression for the address of the stack frame itself.
2501 If you don't define this macro, the default is to return the value of
2502 FRAMEADDR--that is, the stack frame address is also the address of the stack
2503 word that points to the previous frame. */
2505 /* The default is correct, but we need to make sure the frame gets created. */
2507 frv_dynamic_chain_address (rtx frame)
2509 cfun->machine->frame_needed = 1;
2514 /* A C expression whose value is RTL representing the value of the return
2515 address for the frame COUNT steps up from the current frame, after the
2516 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2517 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2520 The value of the expression must always be the correct address when COUNT is
2521 zero, but may be `NULL_RTX' if there is not way to determine the return
2522 address of other frames. */
2525 frv_return_addr_rtx (int count, rtx frame)
2529 cfun->machine->frame_needed = 1;
2530 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2533 /* Given a memory reference MEMREF, interpret the referenced memory as
2534 an array of MODE values, and return a reference to the element
2535 specified by INDEX. Assume that any pre-modification implicit in
2536 MEMREF has already happened.
2538 MEMREF must be a legitimate operand for modes larger than SImode.
2539 frv_legitimate_address_p forbids register+register addresses, which
2540 this function cannot handle. */
2542 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2544 rtx base = XEXP (memref, 0);
2545 if (GET_CODE (base) == PRE_MODIFY)
2546 base = XEXP (base, 0);
2547 return change_address (memref, mode,
2548 plus_constant (base, index * GET_MODE_SIZE (mode)));
2552 /* Print a memory address as an operand to reference that memory location. */
2554 frv_print_operand_address (FILE * stream, rtx x)
2556 if (GET_CODE (x) == MEM)
2559 switch (GET_CODE (x))
2562 fputs (reg_names [ REGNO (x)], stream);
2566 fprintf (stream, "%ld", (long) INTVAL (x));
2570 assemble_name (stream, XSTR (x, 0));
2575 output_addr_const (stream, x);
2579 /* Poorly constructed asm statements can trigger this alternative.
2580 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2581 frv_print_operand_memory_reference (stream, x, 0);
2588 fatal_insn ("bad insn to frv_print_operand_address:", x);
2593 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2595 int regno = true_regnum (x);
2597 fputs (reg_names[regno], stream);
2599 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2602 /* Print a memory reference suitable for the ld/st instructions. */
2605 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2607 struct frv_unspec unspec;
2611 switch (GET_CODE (x))
2618 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2620 x1 = XEXP (XEXP (x, 1), 1);
2630 if (GET_CODE (x0) == CONST_INT)
2638 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2647 else if (GET_CODE (x1) != CONST_INT)
2648 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2651 fputs ("@(", stream);
2653 fputs (reg_names[GPR_R0], stream);
2654 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2655 frv_print_operand_memory_reference_reg (stream, x0);
2657 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2659 fputs (",", stream);
2661 fputs (reg_names [GPR_R0], stream);
2665 switch (GET_CODE (x1))
2669 frv_print_operand_memory_reference_reg (stream, x1);
2673 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2677 if (!frv_const_unspec_p (x1, &unspec))
2678 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2679 frv_output_const_unspec (stream, &unspec);
2683 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2687 fputs (")", stream);
2691 /* Return 2 for likely branches and 0 for non-likely branches */
2693 #define FRV_JUMP_LIKELY 2
2694 #define FRV_JUMP_NOT_LIKELY 0
2697 frv_print_operand_jump_hint (rtx insn)
2702 HOST_WIDE_INT prob = -1;
2703 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2705 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2707 /* Assume any non-conditional jump is likely. */
2708 if (! any_condjump_p (insn))
2709 ret = FRV_JUMP_LIKELY;
2713 labelref = condjump_label (insn);
2716 rtx label = XEXP (labelref, 0);
2717 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2722 note = find_reg_note (insn, REG_BR_PROB, 0);
2724 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2728 prob = INTVAL (XEXP (note, 0));
2729 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2731 : FRV_JUMP_NOT_LIKELY);
2743 case UNKNOWN: direction = "unknown jump direction"; break;
2744 case BACKWARD: direction = "jump backward"; break;
2745 case FORWARD: direction = "jump forward"; break;
2749 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2750 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2751 (long)INSN_UID (insn), direction, (long)prob,
2752 (long)REG_BR_PROB_BASE, ret);
2760 /* Return the comparison operator to use for CODE given that the ICC
2764 comparison_string (enum rtx_code code, rtx op0)
2766 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2769 default: output_operand_lossage ("bad condition code");
2770 case EQ: return "eq";
2771 case NE: return "ne";
2772 case LT: return is_nz_p ? "n" : "lt";
2773 case LE: return "le";
2774 case GT: return "gt";
2775 case GE: return is_nz_p ? "p" : "ge";
2776 case LTU: return is_nz_p ? "no" : "c";
2777 case LEU: return is_nz_p ? "eq" : "ls";
2778 case GTU: return is_nz_p ? "ne" : "hi";
2779 case GEU: return is_nz_p ? "ra" : "nc";
2783 /* Print an operand to an assembler instruction.
2785 `%' followed by a letter and a digit says to output an operand in an
2786 alternate fashion. Four letters have standard, built-in meanings described
2787 below. The machine description macro `PRINT_OPERAND' can define additional
2788 letters with nonstandard meanings.
2790 `%cDIGIT' can be used to substitute an operand that is a constant value
2791 without the syntax that normally indicates an immediate operand.
2793 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2796 `%aDIGIT' can be used to substitute an operand as if it were a memory
2797 reference, with the actual operand treated as the address. This may be
2798 useful when outputting a "load address" instruction, because often the
2799 assembler syntax for such an instruction requires you to write the operand
2800 as if it were a memory reference.
2802 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2804 `%=' outputs a number which is unique to each instruction in the entire
2805 compilation. This is useful for making local labels to be referred to more
2806 than once in a single template that generates multiple assembler
2809 `%' followed by a punctuation character specifies a substitution that does
2810 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2811 assembler code. Other nonstandard cases can be defined in the
2812 `PRINT_OPERAND' macro. You must also define which punctuation characters
2813 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2816 frv_print_operand (FILE * file, rtx x, int code)
2818 struct frv_unspec unspec;
2819 HOST_WIDE_INT value;
2822 if (code != 0 && !ISALPHA (code))
2825 else if (GET_CODE (x) == CONST_INT)
2828 else if (GET_CODE (x) == CONST_DOUBLE)
2830 if (GET_MODE (x) == SFmode)
2835 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2836 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2840 else if (GET_MODE (x) == VOIDmode)
2841 value = CONST_DOUBLE_LOW (x);
2844 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2855 fputs (reg_names[GPR_R0], file);
2859 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2863 /* Output small data area base register (gr16). */
2864 fputs (reg_names[SDA_BASE_REG], file);
2868 /* Output pic register (gr17). */
2869 fputs (reg_names[PIC_REGNO], file);
2873 /* Output the temporary integer CCR register. */
2874 fputs (reg_names[ICR_TEMP], file);
2878 /* Output the temporary integer CC register. */
2879 fputs (reg_names[ICC_TEMP], file);
2882 /* case 'a': print an address. */
2885 /* Print appropriate test for integer branch false operation. */
2886 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2887 XEXP (x, 0)), file);
2891 /* Print appropriate test for integer branch true operation. */
2892 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2896 /* Print 1 for a NE and 0 for an EQ to give the final argument
2897 for a conditional instruction. */
2898 if (GET_CODE (x) == NE)
2901 else if (GET_CODE (x) == EQ)
2905 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2909 /* Print appropriate test for floating point branch false operation. */
2910 switch (GET_CODE (x))
2913 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2915 case EQ: fputs ("ne", file); break;
2916 case NE: fputs ("eq", file); break;
2917 case LT: fputs ("uge", file); break;
2918 case LE: fputs ("ug", file); break;
2919 case GT: fputs ("ule", file); break;
2920 case GE: fputs ("ul", file); break;
2925 /* Print appropriate test for floating point branch true operation. */
2926 switch (GET_CODE (x))
2929 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2931 case EQ: fputs ("eq", file); break;
2932 case NE: fputs ("ne", file); break;
2933 case LT: fputs ("lt", file); break;
2934 case LE: fputs ("le", file); break;
2935 case GT: fputs ("gt", file); break;
2936 case GE: fputs ("ge", file); break;
2941 /* Print appropriate GOT function. */
2942 if (GET_CODE (x) != CONST_INT)
2943 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2944 fputs (unspec_got_name (INTVAL (x)), file);
2948 /* Print 'i' if the operand is a constant, or is a memory reference that
2950 if (GET_CODE (x) == MEM)
2951 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2952 ? XEXP (XEXP (x, 0), 1)
2954 else if (GET_CODE (x) == PLUS)
2957 switch (GET_CODE (x))
2971 /* For jump instructions, print 'i' if the operand is a constant or
2972 is an expression that adds a constant. */
2973 if (GET_CODE (x) == CONST_INT)
2978 if (GET_CODE (x) == CONST_INT
2979 || (GET_CODE (x) == PLUS
2980 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2981 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2987 /* Print the lower register of a double word register pair */
2988 if (GET_CODE (x) == REG)
2989 fputs (reg_names[ REGNO (x)+1 ], file);
2991 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2994 /* case 'l': print a LABEL_REF. */
2998 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2999 for the second word of double memory operations. */
3000 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3001 switch (GET_CODE (x))
3004 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3007 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3015 frv_print_operand_memory_reference (file, x, offset);
3021 /* Print the opcode of a command. */
3022 switch (GET_CODE (x))
3025 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3027 case PLUS: fputs ("add", file); break;
3028 case MINUS: fputs ("sub", file); break;
3029 case AND: fputs ("and", file); break;
3030 case IOR: fputs ("or", file); break;
3031 case XOR: fputs ("xor", file); break;
3032 case ASHIFT: fputs ("sll", file); break;
3033 case ASHIFTRT: fputs ("sra", file); break;
3034 case LSHIFTRT: fputs ("srl", file); break;
3038 /* case 'n': negate and print a constant int. */
3041 /* Print PIC label using operand as the number. */
3042 if (GET_CODE (x) != CONST_INT)
3043 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3045 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3049 /* Print 'u' if the operand is a update load/store. */
3050 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3055 /* If value is 0, print gr0, otherwise it must be a register. */
3056 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3057 fputs (reg_names[GPR_R0], file);
3059 else if (GET_CODE (x) == REG)
3060 fputs (reg_names [REGNO (x)], file);
3063 fatal_insn ("bad insn in frv_print_operand, z case", x);
3067 /* Print constant in hex. */
3068 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3070 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3077 if (GET_CODE (x) == REG)
3078 fputs (reg_names [REGNO (x)], file);
3080 else if (GET_CODE (x) == CONST_INT
3081 || GET_CODE (x) == CONST_DOUBLE)
3082 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3084 else if (frv_const_unspec_p (x, &unspec))
3085 frv_output_const_unspec (file, &unspec);
3087 else if (GET_CODE (x) == MEM)
3088 frv_print_operand_address (file, XEXP (x, 0));
3090 else if (CONSTANT_ADDRESS_P (x))
3091 frv_print_operand_address (file, x);
3094 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3099 fatal_insn ("frv_print_operand: unknown code", x);
3107 /* A C statement (sans semicolon) for initializing the variable CUM for the
3108 state at the beginning of the argument list. The variable has type
3109 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3110 of the function which will receive the args, or 0 if the args are to a
3111 compiler support library function. The value of INDIRECT is nonzero when
3112 processing an indirect call, for example a call through a function pointer.
3113 The value of INDIRECT is zero for a call to an explicitly named function, a
3114 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3115 arguments for the function being compiled.
3117 When processing a call to a compiler support library function, LIBNAME
3118 identifies which one. It is a `symbol_ref' rtx which contains the name of
3119 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3120 being processed. Thus, each time this macro is called, either LIBNAME or
3121 FNTYPE is nonzero, but never both of them at once. */
3124 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3130 *cum = FIRST_ARG_REGNUM;
3132 if (TARGET_DEBUG_ARG)
3134 fprintf (stderr, "\ninit_cumulative_args:");
3135 if (!fndecl && fntype)
3136 fputs (" indirect", stderr);
3139 fputs (" incoming", stderr);
3143 tree ret_type = TREE_TYPE (fntype);
3144 fprintf (stderr, " return=%s,",
3145 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3148 if (libname && GET_CODE (libname) == SYMBOL_REF)
3149 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3151 if (cfun->returns_struct)
3152 fprintf (stderr, " return-struct");
3154 putc ('\n', stderr);
3159 /* Return true if we should pass an argument on the stack rather than
3163 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3165 if (mode == BLKmode)
3169 return AGGREGATE_TYPE_P (type);
3172 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3173 argument with the specified mode and type. If it is not defined,
3174 `PARM_BOUNDARY' is used for all arguments. */
3177 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3178 tree type ATTRIBUTE_UNUSED)
3180 return BITS_PER_WORD;
3184 frv_function_arg (CUMULATIVE_ARGS *cum,
3185 enum machine_mode mode,
3186 tree type ATTRIBUTE_UNUSED,
3188 int incoming ATTRIBUTE_UNUSED)
3190 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3195 /* Return a marker for use in the call instruction. */
3196 if (xmode == VOIDmode)
3202 else if (arg_num <= LAST_ARG_REGNUM)
3204 ret = gen_rtx_REG (xmode, arg_num);
3205 debstr = reg_names[arg_num];
3214 if (TARGET_DEBUG_ARG)
3216 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3217 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3223 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3224 advance past an argument in the argument list. The values MODE, TYPE and
3225 NAMED describe that argument. Once this is done, the variable CUM is
3226 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3228 This macro need not do anything if the argument in question was passed on
3229 the stack. The compiler knows how to track the amount of stack space used
3230 for arguments without any special help. */
3233 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3234 enum machine_mode mode,
3235 tree type ATTRIBUTE_UNUSED,
3238 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3239 int bytes = GET_MODE_SIZE (xmode);
3240 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3243 *cum = arg_num + words;
3245 if (TARGET_DEBUG_ARG)
3247 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3248 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3252 /* A C expression for the number of words, at the beginning of an argument,
3253 must be put in registers. The value must be zero for arguments that are
3254 passed entirely in registers or that are entirely pushed on the stack.
3256 On some machines, certain arguments must be passed partially in registers
3257 and partially in memory. On these machines, typically the first N words of
3258 arguments are passed in registers, and the rest on the stack. If a
3259 multi-word argument (a `double' or a structure) crosses that boundary, its
3260 first few words must be passed in registers and the rest must be pushed.
3261 This macro tells the compiler when this occurs, and how many of the words
3262 should go in registers.
3264 `FUNCTION_ARG' for these arguments should return the first register to be
3265 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3266 the called function. */
3269 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3270 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3272 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3273 int bytes = GET_MODE_SIZE (xmode);
3274 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3278 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3279 ? LAST_ARG_REGNUM - arg_num + 1
3281 ret *= UNITS_PER_WORD;
3283 if (TARGET_DEBUG_ARG && ret)
3284 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3290 /* Return true if a register is ok to use as a base or index register. */
3292 static FRV_INLINE int
3293 frv_regno_ok_for_base_p (int regno, int strict_p)
3299 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3301 if (regno == ARG_POINTER_REGNUM)
3304 return (regno >= FIRST_PSEUDO_REGISTER);
3308 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3309 RTX) is a legitimate memory address on the target machine for a memory
3310 operand of mode MODE.
3312 It usually pays to define several simpler macros to serve as subroutines for
3313 this one. Otherwise it may be too complicated to understand.
3315 This macro must exist in two variants: a strict variant and a non-strict
3316 one. The strict variant is used in the reload pass. It must be defined so
3317 that any pseudo-register that has not been allocated a hard register is
3318 considered a memory reference. In contexts where some kind of register is
3319 required, a pseudo-register with no hard register must be rejected.
3321 The non-strict variant is used in other passes. It must be defined to
3322 accept all pseudo-registers in every context where some kind of register is
3325 Compiler source files that want to use the strict variant of this macro
3326 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3327 conditional to define the strict variant in that case and the non-strict
3330 Normally, constant addresses which are the sum of a `symbol_ref' and an
3331 integer are stored inside a `const' RTX to mark them as constant.
3332 Therefore, there is no need to recognize such sums specifically as
3333 legitimate addresses. Normally you would simply recognize any `const' as
3336 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3337 are not marked with `const'. It assumes that a naked `plus' indicates
3338 indexing. If so, then you *must* reject such naked constant sums as
3339 illegitimate addresses, so that none of them will be given to
3340 `PRINT_OPERAND_ADDRESS'. */
3343 frv_legitimate_address_p_1 (enum machine_mode mode,
3347 int allow_double_reg_p)
3351 HOST_WIDE_INT value;
3354 if (FRV_SYMBOL_REF_TLS_P (x))
3357 switch (GET_CODE (x))
3364 if (GET_CODE (x) != REG)
3370 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3376 if (GET_CODE (x0) != REG
3377 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3378 || GET_CODE (x1) != PLUS
3379 || ! rtx_equal_p (x0, XEXP (x1, 0))
3380 || GET_CODE (XEXP (x1, 1)) != REG
3381 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3388 /* 12-bit immediate */
3393 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3395 /* If we can't use load/store double operations, make sure we can
3396 address the second word. */
3397 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3398 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3407 if (GET_CODE (x0) == SUBREG)
3408 x0 = SUBREG_REG (x0);
3410 if (GET_CODE (x0) != REG)
3413 regno0 = REGNO (x0);
3414 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3417 switch (GET_CODE (x1))
3423 x1 = SUBREG_REG (x1);
3424 if (GET_CODE (x1) != REG)
3430 /* Do not allow reg+reg addressing for modes > 1 word if we
3431 can't depend on having move double instructions. */
3432 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3435 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3439 /* 12-bit immediate */
3444 value = INTVAL (x1);
3445 ret = IN_RANGE_P (value, -2048, 2047);
3447 /* If we can't use load/store double operations, make sure we can
3448 address the second word. */
3449 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3450 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3455 if (!condexec_p && got12_operand (x1, VOIDmode))
3463 if (TARGET_DEBUG_ADDR)
3465 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3466 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3467 (condexec_p) ? ", inside conditional code" : "");
3475 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3477 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3480 /* Given an ADDR, generate code to inline the PLT. */
3482 gen_inlined_tls_plt (rtx addr)
3485 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3488 dest = gen_reg_rtx (DImode);
3495 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3496 calll #gettlsoff(ADDR)@(gr8, gr0)
3498 emit_insn (gen_tls_lddi (dest, addr, picreg));
3505 sethi.p #gottlsdeschi(ADDR), gr8
3506 setlo #gottlsdesclo(ADDR), gr8
3507 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3508 calll #gettlsoff(ADDR)@(gr8, gr0)
3510 rtx reguse = gen_reg_rtx (Pmode);
3511 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3512 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3515 retval = gen_reg_rtx (Pmode);
3516 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3520 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3521 the destination address. */
3523 gen_tlsmoff (rtx addr, rtx reg)
3525 rtx dest = gen_reg_rtx (Pmode);
3529 /* sethi.p #tlsmoffhi(x), grA
3530 setlo #tlsmofflo(x), grA
3532 dest = gen_reg_rtx (Pmode);
3533 emit_insn (gen_tlsoff_hilo (dest, addr,
3534 GEN_INT (R_FRV_TLSMOFFHI)));
3535 dest = gen_rtx_PLUS (Pmode, dest, reg);
3539 /* addi grB, #tlsmoff12(x), grC
3541 ld/st @(grB, #tlsmoff12(x)), grC
3543 dest = gen_reg_rtx (Pmode);
3544 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3545 GEN_INT (R_FRV_TLSMOFF12)));
3550 /* Generate code for a TLS address. */
3552 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3554 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3555 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3559 case TLS_MODEL_INITIAL_EXEC:
3563 ldi @(gr15, #gottlsoff12(x)), gr5
3565 dest = gen_reg_rtx (Pmode);
3566 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3567 dest = gen_rtx_PLUS (Pmode, tp, dest);
3571 /* -fPIC or anything else.
3573 sethi.p #gottlsoffhi(x), gr14
3574 setlo #gottlsofflo(x), gr14
3575 ld #tlsoff(x)@(gr15, gr14), gr9
3577 rtx tmp = gen_reg_rtx (Pmode);
3578 dest = gen_reg_rtx (Pmode);
3579 emit_insn (gen_tlsoff_hilo (tmp, addr,
3580 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3582 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3583 dest = gen_rtx_PLUS (Pmode, tp, dest);
3586 case TLS_MODEL_LOCAL_DYNAMIC:
3590 if (TARGET_INLINE_PLT)
3591 retval = gen_inlined_tls_plt (GEN_INT (0));
3594 /* call #gettlsoff(0) */
3595 retval = gen_reg_rtx (Pmode);
3596 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3599 reg = gen_reg_rtx (Pmode);
3600 emit_insn (gen_rtx_SET (VOIDmode, reg,
3601 gen_rtx_PLUS (Pmode,
3604 dest = gen_tlsmoff (addr, reg);
3607 dest = gen_reg_rtx (Pmode);
3608 emit_insn (gen_tlsoff_hilo (dest, addr,
3609 GEN_INT (R_FRV_TLSMOFFHI)));
3610 dest = gen_rtx_PLUS (Pmode, dest, reg);
3614 case TLS_MODEL_LOCAL_EXEC:
3615 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3617 case TLS_MODEL_GLOBAL_DYNAMIC:
3621 if (TARGET_INLINE_PLT)
3622 retval = gen_inlined_tls_plt (addr);
3625 /* call #gettlsoff(x) */
3626 retval = gen_reg_rtx (Pmode);
3627 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3629 dest = gen_rtx_PLUS (Pmode, retval, tp);
3640 frv_legitimize_address (rtx x,
3641 rtx oldx ATTRIBUTE_UNUSED,
3642 enum machine_mode mode ATTRIBUTE_UNUSED)
3644 if (GET_CODE (x) == SYMBOL_REF)
3646 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3648 return frv_legitimize_tls_address (x, model);
3654 /* Test whether a local function descriptor is canonical, i.e.,
3655 whether we can use FUNCDESC_GOTOFF to compute the address of the
3659 frv_local_funcdesc_p (rtx fnx)
3662 enum symbol_visibility vis;
3665 if (! SYMBOL_REF_LOCAL_P (fnx))
3668 fn = SYMBOL_REF_DECL (fnx);
3673 vis = DECL_VISIBILITY (fn);
3675 if (vis == VISIBILITY_PROTECTED)
3676 /* Private function descriptors for protected functions are not
3677 canonical. Temporarily change the visibility to global. */
3678 vis = VISIBILITY_DEFAULT;
3679 else if (flag_shlib)
3680 /* If we're already compiling for a shared library (that, unlike
3681 executables, can't assume that the existence of a definition
3682 implies local binding), we can skip the re-testing. */
3685 ret = default_binds_local_p_1 (fn, flag_pic);
3687 DECL_VISIBILITY (fn) = vis;
3692 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3696 frv_gen_GPsym2reg (rtx dest, rtx src)
3698 tree gp = get_identifier ("_gp");
3699 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3701 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3705 unspec_got_name (int i)
3709 case R_FRV_GOT12: return "got12";
3710 case R_FRV_GOTHI: return "gothi";
3711 case R_FRV_GOTLO: return "gotlo";
3712 case R_FRV_FUNCDESC: return "funcdesc";
3713 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3714 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3715 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3716 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3717 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3718 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3719 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3720 case R_FRV_GOTOFF12: return "gotoff12";
3721 case R_FRV_GOTOFFHI: return "gotoffhi";
3722 case R_FRV_GOTOFFLO: return "gotofflo";
3723 case R_FRV_GPREL12: return "gprel12";
3724 case R_FRV_GPRELHI: return "gprelhi";
3725 case R_FRV_GPRELLO: return "gprello";
3726 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3727 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3728 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3729 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3730 case R_FRV_TLSMOFF12: return "tlsmoff12";
3731 case R_FRV_TLSDESCHI: return "tlsdeschi";
3732 case R_FRV_TLSDESCLO: return "tlsdesclo";
3733 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3734 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3735 default: gcc_unreachable ();
3739 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3740 is added inside the relocation operator. */
3743 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3745 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3746 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3747 fputs (")", stream);
3750 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3751 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3752 otherwise return ORIG_X. */
3755 frv_find_base_term (rtx x)
3757 struct frv_unspec unspec;
3759 if (frv_const_unspec_p (x, &unspec)
3760 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3761 return plus_constant (unspec.symbol, unspec.offset);
3766 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3767 the operand is used by a predicated instruction. */
3770 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3772 return ((GET_MODE (op) == mode || mode == VOIDmode)
3773 && GET_CODE (op) == MEM
3774 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3775 reload_completed, condexec_p, FALSE));
3779 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3781 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3782 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3788 rvrtx = operands[0];
3792 addr = XEXP (operands[0], 0);
3794 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3795 any calls that would involve a PLT, but can't tell, since we
3796 don't know whether an extern function is going to be provided by
3797 a separate translation unit or imported from a separate module.
3798 When compiling for shared libraries, if the function has default
3799 visibility, we assume it's overridable, so we inline the PLT, but
3800 for executables, we don't really have a way to make a good
3801 decision: a function is as likely to be imported from a shared
3802 library as it is to be defined in the executable itself. We
3803 assume executables will get global functions defined locally,
3804 whereas shared libraries will have them potentially overridden,
3805 so we only inline PLTs when compiling for shared libraries.
3807 In order to mark a function as local to a shared library, any
3808 non-default visibility attribute suffices. Unfortunately,
3809 there's no simple way to tag a function declaration as ``in a
3810 different module'', which we could then use to trigger PLT
3811 inlining on executables. There's -minline-plt, but it affects
3812 all external functions, so one would have to also mark function
3813 declarations available in the same module with non-default
3814 visibility, which is advantageous in itself. */
3815 if (GET_CODE (addr) == SYMBOL_REF
3816 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3820 dest = gen_reg_rtx (SImode);
3822 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3823 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3825 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3826 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3828 crtl->uses_pic_offset_table = TRUE;
3831 else if (GET_CODE (addr) == SYMBOL_REF)
3833 /* These are always either local, or handled through a local
3836 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3837 operands[2], picreg, lr);
3839 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3843 else if (! ldd_address_operand (addr, Pmode))
3844 addr = force_reg (Pmode, addr);
3846 picreg = gen_reg_rtx (DImode);
3847 emit_insn (gen_movdi_ldd (picreg, addr));
3849 if (sibcall && ret_value)
3850 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3852 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3854 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3856 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3860 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3861 process these separately from any offsets, such that we add any
3862 offsets to the function descriptor (the actual pointer), not to the
3863 function address. */
3866 frv_function_symbol_referenced_p (rtx x)
3872 if (GET_CODE (x) == SYMBOL_REF)
3873 return SYMBOL_REF_FUNCTION_P (x);
3875 length = GET_RTX_LENGTH (GET_CODE (x));
3876 format = GET_RTX_FORMAT (GET_CODE (x));
3878 for (j = 0; j < length; ++j)
3883 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3889 if (XVEC (x, j) != 0)
3892 for (k = 0; k < XVECLEN (x, j); ++k)
3893 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3899 /* Nothing to do. */
3907 /* Return true if the memory operand is one that can be conditionally
3911 condexec_memory_operand (rtx op, enum machine_mode mode)
3913 enum machine_mode op_mode = GET_MODE (op);
3916 if (mode != VOIDmode && op_mode != mode)
3931 if (GET_CODE (op) != MEM)
3934 addr = XEXP (op, 0);
3935 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3938 /* Return true if the bare return instruction can be used outside of the
3939 epilog code. For frv, we only do it if there was no stack allocation. */
3942 direct_return_p (void)
3946 if (!reload_completed)
3949 info = frv_stack_info ();
3950 return (info->total_size == 0);
3955 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3957 if (GET_CODE (src) == SYMBOL_REF)
3959 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3961 src = frv_legitimize_tls_address (src, model);
3967 if (frv_emit_movsi (dest, src))
3976 if (!reload_in_progress
3977 && !reload_completed
3978 && !register_operand (dest, mode)
3979 && !reg_or_0_operand (src, mode))
3980 src = copy_to_mode_reg (mode, src);
3987 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3990 /* Emit code to handle a MOVSI, adding in the small data register or pic
3991 register if needed to load up addresses. Return TRUE if the appropriate
3992 instructions are emitted. */
3995 frv_emit_movsi (rtx dest, rtx src)
3997 int base_regno = -1;
4000 struct frv_unspec old_unspec;
4002 if (!reload_in_progress
4003 && !reload_completed
4004 && !register_operand (dest, SImode)
4005 && (!reg_or_0_operand (src, SImode)
4006 /* Virtual registers will almost always be replaced by an
4007 add instruction, so expose this to CSE by copying to
4008 an intermediate register. */
4009 || (GET_CODE (src) == REG
4010 && IN_RANGE_P (REGNO (src),
4011 FIRST_VIRTUAL_REGISTER,
4012 LAST_VIRTUAL_REGISTER))))
4014 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4018 /* Explicitly add in the PIC or small data register if needed. */
4019 switch (GET_CODE (src))
4028 /* Using GPREL12, we use a single GOT entry for all symbols
4029 in read-only sections, but trade sequences such as:
4031 sethi #gothi(label), gr#
4032 setlo #gotlo(label), gr#
4037 ld @(gr15,#got12(_gp)), gr#
4038 sethi #gprelhi(label), gr##
4039 setlo #gprello(label), gr##
4042 We may often be able to share gr# for multiple
4043 computations of GPREL addresses, and we may often fold
4044 the final add into the pair of registers of a load or
4045 store instruction, so it's often profitable. Even when
4046 optimizing for size, we're trading a GOT entry for an
4047 additional instruction, which trades GOT space
4048 (read-write) for code size (read-only, shareable), as
4049 long as the symbol is not used in more than two different
4052 With -fpie/-fpic, we'd be trading a single load for a
4053 sequence of 4 instructions, because the offset of the
4054 label can't be assumed to be addressable with 12 bits, so
4055 we don't do this. */
4056 if (TARGET_GPREL_RO)
4057 unspec = R_FRV_GPREL12;
4059 unspec = R_FRV_GOT12;
4062 base_regno = PIC_REGNO;
4067 if (frv_const_unspec_p (src, &old_unspec))
4070 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4073 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4074 emit_move_insn (dest, src);
4079 sym = XEXP (sym, 0);
4080 if (GET_CODE (sym) == PLUS
4081 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4082 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4083 sym = XEXP (sym, 0);
4084 if (GET_CODE (sym) == SYMBOL_REF)
4086 else if (GET_CODE (sym) == LABEL_REF)
4089 goto handle_whatever;
4097 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4101 src = frv_legitimize_tls_address (src, model);
4102 emit_move_insn (dest, src);
4106 if (SYMBOL_REF_FUNCTION_P (sym))
4108 if (frv_local_funcdesc_p (sym))
4109 unspec = R_FRV_FUNCDESC_GOTOFF12;
4111 unspec = R_FRV_FUNCDESC_GOT12;
4115 if (CONSTANT_POOL_ADDRESS_P (sym))
4116 switch (GET_CODE (get_pool_constant (sym)))
4123 unspec = R_FRV_GOTOFF12;
4128 if (TARGET_GPREL_RO)
4129 unspec = R_FRV_GPREL12;
4131 unspec = R_FRV_GOT12;
4134 else if (SYMBOL_REF_LOCAL_P (sym)
4135 && !SYMBOL_REF_EXTERNAL_P (sym)
4136 && SYMBOL_REF_DECL (sym)
4137 && (!DECL_P (SYMBOL_REF_DECL (sym))
4138 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4140 tree decl = SYMBOL_REF_DECL (sym);
4141 tree init = TREE_CODE (decl) == VAR_DECL
4142 ? DECL_INITIAL (decl)
4143 : TREE_CODE (decl) == CONSTRUCTOR
4146 bool named_section, readonly;
4148 if (init && init != error_mark_node)
4149 reloc = compute_reloc_for_constant (init);
4151 named_section = TREE_CODE (decl) == VAR_DECL
4152 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4153 readonly = decl_readonly_section (decl, reloc);
4156 unspec = R_FRV_GOT12;
4158 unspec = R_FRV_GOTOFF12;
4159 else if (readonly && TARGET_GPREL_RO)
4160 unspec = R_FRV_GPREL12;
4162 unspec = R_FRV_GOT12;
4165 unspec = R_FRV_GOT12;
4169 else if (SYMBOL_REF_SMALL_P (sym))
4170 base_regno = SDA_BASE_REG;
4173 base_regno = PIC_REGNO;
4178 if (base_regno >= 0)
4180 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4181 emit_insn (gen_symGOTOFF2reg (dest, src,
4182 gen_rtx_REG (Pmode, base_regno),
4183 GEN_INT (R_FRV_GPREL12)));
4185 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4186 gen_rtx_REG (Pmode, base_regno),
4187 GEN_INT (R_FRV_GPREL12)));
4188 if (base_regno == PIC_REGNO)
4189 crtl->uses_pic_offset_table = TRUE;
4197 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4198 new uses of it once reload has begun. */
4199 gcc_assert (!reload_in_progress && !reload_completed);
4203 case R_FRV_GOTOFF12:
4204 if (!frv_small_data_reloc_p (sym, unspec))
4205 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4208 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4211 if (!frv_small_data_reloc_p (sym, unspec))
4212 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4215 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4217 case R_FRV_FUNCDESC_GOTOFF12:
4219 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4222 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4226 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4229 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4233 crtl->uses_pic_offset_table = TRUE;
4242 /* Return a string to output a single word move. */
4245 output_move_single (rtx operands[], rtx insn)
4247 rtx dest = operands[0];
4248 rtx src = operands[1];
4250 if (GET_CODE (dest) == REG)
4252 int dest_regno = REGNO (dest);
4253 enum machine_mode mode = GET_MODE (dest);
4255 if (GPR_P (dest_regno))
4257 if (GET_CODE (src) == REG)
4259 /* gpr <- some sort of register */
4260 int src_regno = REGNO (src);
4262 if (GPR_P (src_regno))
4263 return "mov %1, %0";
4265 else if (FPR_P (src_regno))
4266 return "movfg %1, %0";
4268 else if (SPR_P (src_regno))
4269 return "movsg %1, %0";
4272 else if (GET_CODE (src) == MEM)
4281 return "ldsb%I1%U1 %M1,%0";
4284 return "ldsh%I1%U1 %M1,%0";
4288 return "ld%I1%U1 %M1, %0";
4292 else if (GET_CODE (src) == CONST_INT
4293 || GET_CODE (src) == CONST_DOUBLE)
4295 /* gpr <- integer/floating constant */
4296 HOST_WIDE_INT value;
4298 if (GET_CODE (src) == CONST_INT)
4299 value = INTVAL (src);
4301 else if (mode == SFmode)
4306 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4307 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4312 value = CONST_DOUBLE_LOW (src);
4314 if (IN_RANGE_P (value, -32768, 32767))
4315 return "setlos %1, %0";
4320 else if (GET_CODE (src) == SYMBOL_REF
4321 || GET_CODE (src) == LABEL_REF
4322 || GET_CODE (src) == CONST)
4328 else if (FPR_P (dest_regno))
4330 if (GET_CODE (src) == REG)
4332 /* fpr <- some sort of register */
4333 int src_regno = REGNO (src);
4335 if (GPR_P (src_regno))
4336 return "movgf %1, %0";
4338 else if (FPR_P (src_regno))
4340 if (TARGET_HARD_FLOAT)
4341 return "fmovs %1, %0";
4343 return "mor %1, %1, %0";
4347 else if (GET_CODE (src) == MEM)
4356 return "ldbf%I1%U1 %M1,%0";
4359 return "ldhf%I1%U1 %M1,%0";
4363 return "ldf%I1%U1 %M1, %0";
4367 else if (ZERO_P (src))
4368 return "movgf %., %0";
4371 else if (SPR_P (dest_regno))
4373 if (GET_CODE (src) == REG)
4375 /* spr <- some sort of register */
4376 int src_regno = REGNO (src);
4378 if (GPR_P (src_regno))
4379 return "movgs %1, %0";
4381 else if (ZERO_P (src))
4382 return "movgs %., %0";
4386 else if (GET_CODE (dest) == MEM)
4388 if (GET_CODE (src) == REG)
4390 int src_regno = REGNO (src);
4391 enum machine_mode mode = GET_MODE (dest);
4393 if (GPR_P (src_regno))
4401 return "stb%I0%U0 %1, %M0";
4404 return "sth%I0%U0 %1, %M0";
4408 return "st%I0%U0 %1, %M0";
4412 else if (FPR_P (src_regno))
4420 return "stbf%I0%U0 %1, %M0";
4423 return "sthf%I0%U0 %1, %M0";
4427 return "stf%I0%U0 %1, %M0";
4432 else if (ZERO_P (src))
4434 switch (GET_MODE (dest))
4440 return "stb%I0%U0 %., %M0";
4443 return "sth%I0%U0 %., %M0";
4447 return "st%I0%U0 %., %M0";
4452 fatal_insn ("bad output_move_single operand", insn);
4457 /* Return a string to output a double word move. */
4460 output_move_double (rtx operands[], rtx insn)
4462 rtx dest = operands[0];
4463 rtx src = operands[1];
4464 enum machine_mode mode = GET_MODE (dest);
4466 if (GET_CODE (dest) == REG)
4468 int dest_regno = REGNO (dest);
4470 if (GPR_P (dest_regno))
4472 if (GET_CODE (src) == REG)
4474 /* gpr <- some sort of register */
4475 int src_regno = REGNO (src);
4477 if (GPR_P (src_regno))
4480 else if (FPR_P (src_regno))
4482 if (((dest_regno - GPR_FIRST) & 1) == 0
4483 && ((src_regno - FPR_FIRST) & 1) == 0)
4484 return "movfgd %1, %0";
4490 else if (GET_CODE (src) == MEM)
4493 if (dbl_memory_one_insn_operand (src, mode))
4494 return "ldd%I1%U1 %M1, %0";
4499 else if (GET_CODE (src) == CONST_INT
4500 || GET_CODE (src) == CONST_DOUBLE)
4504 else if (FPR_P (dest_regno))
4506 if (GET_CODE (src) == REG)
4508 /* fpr <- some sort of register */
4509 int src_regno = REGNO (src);
4511 if (GPR_P (src_regno))
4513 if (((dest_regno - FPR_FIRST) & 1) == 0
4514 && ((src_regno - GPR_FIRST) & 1) == 0)
4515 return "movgfd %1, %0";
4520 else if (FPR_P (src_regno))
4523 && ((dest_regno - FPR_FIRST) & 1) == 0
4524 && ((src_regno - FPR_FIRST) & 1) == 0)
4525 return "fmovd %1, %0";
4531 else if (GET_CODE (src) == MEM)
4534 if (dbl_memory_one_insn_operand (src, mode))
4535 return "lddf%I1%U1 %M1, %0";
4540 else if (ZERO_P (src))
4545 else if (GET_CODE (dest) == MEM)
4547 if (GET_CODE (src) == REG)
4549 int src_regno = REGNO (src);
4551 if (GPR_P (src_regno))
4553 if (((src_regno - GPR_FIRST) & 1) == 0
4554 && dbl_memory_one_insn_operand (dest, mode))
4555 return "std%I0%U0 %1, %M0";
4560 if (FPR_P (src_regno))
4562 if (((src_regno - FPR_FIRST) & 1) == 0
4563 && dbl_memory_one_insn_operand (dest, mode))
4564 return "stdf%I0%U0 %1, %M0";
4570 else if (ZERO_P (src))
4572 if (dbl_memory_one_insn_operand (dest, mode))
4573 return "std%I0%U0 %., %M0";
4579 fatal_insn ("bad output_move_double operand", insn);
4584 /* Return a string to output a single word conditional move.
4585 Operand0 -- EQ/NE of ccr register and 0
4586 Operand1 -- CCR register
4587 Operand2 -- destination
4588 Operand3 -- source */
4591 output_condmove_single (rtx operands[], rtx insn)
4593 rtx dest = operands[2];
4594 rtx src = operands[3];
4596 if (GET_CODE (dest) == REG)
4598 int dest_regno = REGNO (dest);
4599 enum machine_mode mode = GET_MODE (dest);
4601 if (GPR_P (dest_regno))
4603 if (GET_CODE (src) == REG)
4605 /* gpr <- some sort of register */
4606 int src_regno = REGNO (src);
4608 if (GPR_P (src_regno))
4609 return "cmov %z3, %2, %1, %e0";
4611 else if (FPR_P (src_regno))
4612 return "cmovfg %3, %2, %1, %e0";
4615 else if (GET_CODE (src) == MEM)
4624 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4627 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4631 return "cld%I3%U3 %M3, %2, %1, %e0";
4635 else if (ZERO_P (src))
4636 return "cmov %., %2, %1, %e0";
4639 else if (FPR_P (dest_regno))
4641 if (GET_CODE (src) == REG)
4643 /* fpr <- some sort of register */
4644 int src_regno = REGNO (src);
4646 if (GPR_P (src_regno))
4647 return "cmovgf %3, %2, %1, %e0";
4649 else if (FPR_P (src_regno))
4651 if (TARGET_HARD_FLOAT)
4652 return "cfmovs %3,%2,%1,%e0";
4654 return "cmor %3, %3, %2, %1, %e0";
4658 else if (GET_CODE (src) == MEM)
4661 if (mode == SImode || mode == SFmode)
4662 return "cldf%I3%U3 %M3, %2, %1, %e0";
4665 else if (ZERO_P (src))
4666 return "cmovgf %., %2, %1, %e0";
4670 else if (GET_CODE (dest) == MEM)
4672 if (GET_CODE (src) == REG)
4674 int src_regno = REGNO (src);
4675 enum machine_mode mode = GET_MODE (dest);
4677 if (GPR_P (src_regno))
4685 return "cstb%I2%U2 %3, %M2, %1, %e0";
4688 return "csth%I2%U2 %3, %M2, %1, %e0";
4692 return "cst%I2%U2 %3, %M2, %1, %e0";
4696 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4697 return "cstf%I2%U2 %3, %M2, %1, %e0";
4700 else if (ZERO_P (src))
4702 enum machine_mode mode = GET_MODE (dest);
4709 return "cstb%I2%U2 %., %M2, %1, %e0";
4712 return "csth%I2%U2 %., %M2, %1, %e0";
4716 return "cst%I2%U2 %., %M2, %1, %e0";
4721 fatal_insn ("bad output_condmove_single operand", insn);
4726 /* Emit the appropriate code to do a comparison, returning the register the
4727 comparison was done it. */
4730 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4732 enum machine_mode cc_mode;
4735 /* Floating point doesn't have comparison against a constant. */
4736 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4737 op1 = force_reg (GET_MODE (op0), op1);
4739 /* Possibly disable using anything but a fixed register in order to work
4740 around cse moving comparisons past function calls. */
4741 cc_mode = SELECT_CC_MODE (test, op0, op1);
4742 cc_reg = ((TARGET_ALLOC_CC)
4743 ? gen_reg_rtx (cc_mode)
4744 : gen_rtx_REG (cc_mode,
4745 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4747 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4748 gen_rtx_COMPARE (cc_mode, op0, op1)));
4754 /* Emit code for a conditional branch.
4755 XXX: I originally wanted to add a clobber of a CCR register to use in
4756 conditional execution, but that confuses the rest of the compiler. */
4759 frv_emit_cond_branch (rtx operands[])
4764 enum rtx_code test = GET_CODE (operands[0]);
4765 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4766 enum machine_mode cc_mode = GET_MODE (cc_reg);
4768 /* Branches generate:
4770 (if_then_else (<test>, <cc_reg>, (const_int 0))
4771 (label_ref <branch_label>)
4773 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4774 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4775 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4776 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4781 /* Emit code to set a gpr to 1/0 based on a comparison. */
4784 frv_emit_scc (rtx operands[])
4790 enum rtx_code test = GET_CODE (operands[1]);
4791 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4793 /* SCC instructions generate:
4794 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4795 (clobber (<ccr_reg>))]) */
4796 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4797 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4799 cr_reg = ((TARGET_ALLOC_CC)
4800 ? gen_reg_rtx (CC_CCRmode)
4801 : gen_rtx_REG (CC_CCRmode,
4802 ((GET_MODE (cc_reg) == CC_FPmode)
4806 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4807 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4812 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4813 the separate insns. */
4816 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4822 /* Set the appropriate CCR bit. */
4823 emit_insn (gen_rtx_SET (VOIDmode,
4825 gen_rtx_fmt_ee (GET_CODE (test),
4830 /* Move the value into the destination. */
4831 emit_move_insn (dest, GEN_INT (value));
4833 /* Move 0 into the destination if the test failed */
4834 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4835 gen_rtx_EQ (GET_MODE (cr_reg),
4838 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4840 /* Finish up, return sequence. */
4847 /* Emit the code for a conditional move, return TRUE if we could do the
4851 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4858 enum rtx_code test = GET_CODE (test_rtx);
4859 rtx cc_reg = frv_emit_comparison (test,
4860 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4861 enum machine_mode cc_mode = GET_MODE (cc_reg);
4863 /* Conditional move instructions generate:
4864 (parallel [(set <target>
4865 (if_then_else (<test> <cc_reg> (const_int 0))
4868 (clobber (<ccr_reg>))]) */
4870 /* Handle various cases of conditional move involving two constants. */
4871 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4873 HOST_WIDE_INT value1 = INTVAL (src1);
4874 HOST_WIDE_INT value2 = INTVAL (src2);
4876 /* Having 0 as one of the constants can be done by loading the other
4877 constant, and optionally moving in gr0. */
4878 if (value1 == 0 || value2 == 0)
4881 /* If the first value is within an addi range and also the difference
4882 between the two fits in an addi's range, load up the difference, then
4883 conditionally move in 0, and then unconditionally add the first
4885 else if (IN_RANGE_P (value1, -2048, 2047)
4886 && IN_RANGE_P (value2 - value1, -2048, 2047))
4889 /* If neither condition holds, just force the constant into a
4893 src1 = force_reg (GET_MODE (dest), src1);
4894 src2 = force_reg (GET_MODE (dest), src2);
4898 /* If one value is a register, insure the other value is either 0 or a
4902 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4903 src1 = force_reg (GET_MODE (dest), src1);
4905 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4906 src2 = force_reg (GET_MODE (dest), src2);
4909 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4910 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4912 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4914 cr_reg = ((TARGET_ALLOC_CC)
4915 ? gen_reg_rtx (CC_CCRmode)
4916 : gen_rtx_REG (CC_CCRmode,
4917 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4919 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4920 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4925 /* Split a conditional move into constituent parts, returning a SEQUENCE
4926 containing all of the insns. */
4929 frv_split_cond_move (rtx operands[])
4931 rtx dest = operands[0];
4932 rtx test = operands[1];
4933 rtx cc_reg = operands[2];
4934 rtx src1 = operands[3];
4935 rtx src2 = operands[4];
4936 rtx cr_reg = operands[5];
4938 enum machine_mode cr_mode = GET_MODE (cr_reg);
4942 /* Set the appropriate CCR bit. */
4943 emit_insn (gen_rtx_SET (VOIDmode,
4945 gen_rtx_fmt_ee (GET_CODE (test),
4950 /* Handle various cases of conditional move involving two constants. */
4951 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4953 HOST_WIDE_INT value1 = INTVAL (src1);
4954 HOST_WIDE_INT value2 = INTVAL (src2);
4956 /* Having 0 as one of the constants can be done by loading the other
4957 constant, and optionally moving in gr0. */
4960 emit_move_insn (dest, src2);
4961 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4962 gen_rtx_NE (cr_mode, cr_reg,
4964 gen_rtx_SET (VOIDmode, dest, src1)));
4967 else if (value2 == 0)
4969 emit_move_insn (dest, src1);
4970 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4971 gen_rtx_EQ (cr_mode, cr_reg,
4973 gen_rtx_SET (VOIDmode, dest, src2)));
4976 /* If the first value is within an addi range and also the difference
4977 between the two fits in an addi's range, load up the difference, then
4978 conditionally move in 0, and then unconditionally add the first
4980 else if (IN_RANGE_P (value1, -2048, 2047)
4981 && IN_RANGE_P (value2 - value1, -2048, 2047))
4983 rtx dest_si = ((GET_MODE (dest) == SImode)
4985 : gen_rtx_SUBREG (SImode, dest, 0));
4987 emit_move_insn (dest_si, GEN_INT (value2 - value1));
4988 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4989 gen_rtx_NE (cr_mode, cr_reg,
4991 gen_rtx_SET (VOIDmode, dest_si,
4993 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5001 /* Emit the conditional move for the test being true if needed. */
5002 if (! rtx_equal_p (dest, src1))
5003 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5004 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5005 gen_rtx_SET (VOIDmode, dest, src1)));
5007 /* Emit the conditional move for the test being false if needed. */
5008 if (! rtx_equal_p (dest, src2))
5009 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5010 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5011 gen_rtx_SET (VOIDmode, dest, src2)));
5014 /* Finish up, return sequence. */
5021 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5022 memory location that is not known to be dword-aligned. */
5024 frv_split_double_load (rtx dest, rtx source)
5026 int regno = REGNO (dest);
5027 rtx dest1 = gen_highpart (SImode, dest);
5028 rtx dest2 = gen_lowpart (SImode, dest);
5029 rtx address = XEXP (source, 0);
5031 /* If the address is pre-modified, load the lower-numbered register
5032 first, then load the other register using an integer offset from
5033 the modified base register. This order should always be safe,
5034 since the pre-modification cannot affect the same registers as the
5037 The situation for other loads is more complicated. Loading one
5038 of the registers could affect the value of ADDRESS, so we must
5039 be careful which order we do them in. */
5040 if (GET_CODE (address) == PRE_MODIFY
5041 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5043 /* It is safe to load the lower-numbered register first. */
5044 emit_move_insn (dest1, change_address (source, SImode, NULL));
5045 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5049 /* ADDRESS is not pre-modified and the address depends on the
5050 lower-numbered register. Load the higher-numbered register
5052 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5053 emit_move_insn (dest1, change_address (source, SImode, NULL));
5057 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5058 and SOURCE is either a double register or the constant zero. */
5060 frv_split_double_store (rtx dest, rtx source)
5062 rtx dest1 = change_address (dest, SImode, NULL);
5063 rtx dest2 = frv_index_memory (dest, SImode, 1);
5064 if (ZERO_P (source))
5066 emit_move_insn (dest1, CONST0_RTX (SImode));
5067 emit_move_insn (dest2, CONST0_RTX (SImode));
5071 emit_move_insn (dest1, gen_highpart (SImode, source));
5072 emit_move_insn (dest2, gen_lowpart (SImode, source));
5077 /* Split a min/max operation returning a SEQUENCE containing all of the
5081 frv_split_minmax (rtx operands[])
5083 rtx dest = operands[0];
5084 rtx minmax = operands[1];
5085 rtx src1 = operands[2];
5086 rtx src2 = operands[3];
5087 rtx cc_reg = operands[4];
5088 rtx cr_reg = operands[5];
5090 enum rtx_code test_code;
5091 enum machine_mode cr_mode = GET_MODE (cr_reg);
5095 /* Figure out which test to use. */
5096 switch (GET_CODE (minmax))
5101 case SMIN: test_code = LT; break;
5102 case SMAX: test_code = GT; break;
5103 case UMIN: test_code = LTU; break;
5104 case UMAX: test_code = GTU; break;
5107 /* Issue the compare instruction. */
5108 emit_insn (gen_rtx_SET (VOIDmode,
5110 gen_rtx_COMPARE (GET_MODE (cc_reg),
5113 /* Set the appropriate CCR bit. */
5114 emit_insn (gen_rtx_SET (VOIDmode,
5116 gen_rtx_fmt_ee (test_code,
5121 /* If are taking the min/max of a nonzero constant, load that first, and
5122 then do a conditional move of the other value. */
5123 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5125 gcc_assert (!rtx_equal_p (dest, src1));
5127 emit_move_insn (dest, src2);
5128 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5129 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5130 gen_rtx_SET (VOIDmode, dest, src1)));
5133 /* Otherwise, do each half of the move. */
5136 /* Emit the conditional move for the test being true if needed. */
5137 if (! rtx_equal_p (dest, src1))
5138 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5139 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5140 gen_rtx_SET (VOIDmode, dest, src1)));
5142 /* Emit the conditional move for the test being false if needed. */
5143 if (! rtx_equal_p (dest, src2))
5144 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5145 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5146 gen_rtx_SET (VOIDmode, dest, src2)));
5149 /* Finish up, return sequence. */
5156 /* Split an integer abs operation returning a SEQUENCE containing all of the
5160 frv_split_abs (rtx operands[])
5162 rtx dest = operands[0];
5163 rtx src = operands[1];
5164 rtx cc_reg = operands[2];
5165 rtx cr_reg = operands[3];
5170 /* Issue the compare < 0 instruction. */
5171 emit_insn (gen_rtx_SET (VOIDmode,
5173 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5175 /* Set the appropriate CCR bit. */
5176 emit_insn (gen_rtx_SET (VOIDmode,
5178 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5180 /* Emit the conditional negate if the value is negative. */
5181 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5182 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5183 gen_negsi2 (dest, src)));
5185 /* Emit the conditional move for the test being false if needed. */
5186 if (! rtx_equal_p (dest, src))
5187 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5188 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5189 gen_rtx_SET (VOIDmode, dest, src)));
5191 /* Finish up, return sequence. */
5198 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5199 register used in an insn. */
5202 frv_clear_registers_used (rtx *ptr, void *data)
5204 if (GET_CODE (*ptr) == REG)
5206 int regno = REGNO (*ptr);
5207 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5209 if (regno < FIRST_PSEUDO_REGISTER)
5211 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5213 while (regno < reg_max)
5215 CLEAR_HARD_REG_BIT (*p_regs, regno);
5225 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5227 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5228 initialize the static storage. */
5230 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5232 frv_ifcvt.added_insns_list = NULL_RTX;
5233 frv_ifcvt.cur_scratch_regs = 0;
5234 frv_ifcvt.num_nested_cond_exec = 0;
5235 frv_ifcvt.cr_reg = NULL_RTX;
5236 frv_ifcvt.nested_cc_reg = NULL_RTX;
5237 frv_ifcvt.extra_int_cr = NULL_RTX;
5238 frv_ifcvt.extra_fp_cr = NULL_RTX;
5239 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5243 /* Internal function to add a potential insn to the list of insns to be inserted
5244 if the conditional execution conversion is successful. */
5247 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5249 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5251 link->jump = before_p; /* Mark to add this before or after insn. */
5252 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5253 frv_ifcvt.added_insns_list);
5255 if (TARGET_DEBUG_COND_EXEC)
5258 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5259 (before_p) ? "before" : "after",
5260 (int)INSN_UID (insn));
5262 debug_rtx (pattern);
5267 /* A C expression to modify the code described by the conditional if
5268 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5269 FALSE_EXPR for converting if-then and if-then-else code to conditional
5270 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5271 tests cannot be converted. */
5274 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5276 basic_block test_bb = ce_info->test_bb; /* test basic block */
5277 basic_block then_bb = ce_info->then_bb; /* THEN */
5278 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5279 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5280 rtx true_expr = *p_true;
5284 enum machine_mode mode = GET_MODE (true_expr);
5288 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5290 rtx sub_cond_exec_reg;
5292 enum rtx_code code_true;
5293 enum rtx_code code_false;
5294 enum reg_class cc_class;
5295 enum reg_class cr_class;
5298 reg_set_iterator rsi;
5300 /* Make sure we are only dealing with hard registers. Also honor the
5301 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5303 if (!reload_completed || !TARGET_COND_EXEC
5304 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5307 /* Figure out which registers we can allocate for our own purposes. Only
5308 consider registers that are not preserved across function calls and are
5309 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5310 if we did not need to use them in reloading other registers. */
5311 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5312 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5313 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5314 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5315 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5317 /* If this is a nested IF, we need to discover whether the CC registers that
5318 are set/used inside of the block are used anywhere else. If not, we can
5319 change them to be the CC register that is paired with the CR register that
5320 controls the outermost IF block. */
5321 if (ce_info->pass > 1)
5323 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5324 for (j = CC_FIRST; j <= CC_LAST; j++)
5325 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5327 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5331 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5335 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5338 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5342 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5343 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5345 frv_ifcvt.added_insns_list = NULL_RTX;
5346 frv_ifcvt.cur_scratch_regs = 0;
5348 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5349 * sizeof (basic_block));
5355 /* Remove anything live at the beginning of the join block from being
5356 available for allocation. */
5357 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5359 if (regno < FIRST_PSEUDO_REGISTER)
5360 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5364 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5366 if (ce_info->num_multiple_test_blocks)
5368 basic_block multiple_test_bb = ce_info->last_test_bb;
5370 while (multiple_test_bb != test_bb)
5372 bb[num_bb++] = multiple_test_bb;
5373 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5377 /* Add in the THEN and ELSE blocks to be scanned. */
5378 bb[num_bb++] = then_bb;
5380 bb[num_bb++] = else_bb;
5382 sub_cond_exec_reg = NULL_RTX;
5383 frv_ifcvt.num_nested_cond_exec = 0;
5385 /* Scan all of the blocks for registers that must not be allocated. */
5386 for (j = 0; j < num_bb; j++)
5388 rtx last_insn = BB_END (bb[j]);
5389 rtx insn = BB_HEAD (bb[j]);
5393 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5394 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5396 (int) INSN_UID (BB_HEAD (bb[j])),
5397 (int) INSN_UID (BB_END (bb[j])));
5399 /* Anything live at the beginning of the block is obviously unavailable
5401 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5403 if (regno < FIRST_PSEUDO_REGISTER)
5404 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5407 /* Loop through the insns in the block. */
5410 /* Mark any new registers that are created as being unavailable for
5411 allocation. Also see if the CC register used in nested IFs can be
5417 int skip_nested_if = FALSE;
5419 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5420 (void *)&tmp_reg->regs);
5422 pattern = PATTERN (insn);
5423 if (GET_CODE (pattern) == COND_EXEC)
5425 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5427 if (reg != sub_cond_exec_reg)
5429 sub_cond_exec_reg = reg;
5430 frv_ifcvt.num_nested_cond_exec++;
5434 set = single_set_pattern (pattern);
5437 rtx dest = SET_DEST (set);
5438 rtx src = SET_SRC (set);
5440 if (GET_CODE (dest) == REG)
5442 int regno = REGNO (dest);
5443 enum rtx_code src_code = GET_CODE (src);
5445 if (CC_P (regno) && src_code == COMPARE)
5446 skip_nested_if = TRUE;
5448 else if (CR_P (regno)
5449 && (src_code == IF_THEN_ELSE
5450 || COMPARISON_P (src)))
5451 skip_nested_if = TRUE;
5455 if (! skip_nested_if)
5456 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5457 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5460 if (insn == last_insn)
5463 insn = NEXT_INSN (insn);
5467 /* If this is a nested if, rewrite the CC registers that are available to
5468 include the ones that can be rewritten, to increase the chance of being
5469 able to allocate a paired CC/CR register combination. */
5470 if (ce_info->pass > 1)
5472 for (j = CC_FIRST; j <= CC_LAST; j++)
5473 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5474 SET_HARD_REG_BIT (tmp_reg->regs, j);
5476 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5482 fprintf (dump_file, "Available GPRs: ");
5484 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5485 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5487 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5488 if (++num_gprs > GPR_TEMP_NUM+2)
5492 fprintf (dump_file, "%s\nAvailable CRs: ",
5493 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5495 for (j = CR_FIRST; j <= CR_LAST; j++)
5496 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5497 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5499 fputs ("\n", dump_file);
5501 if (ce_info->pass > 1)
5503 fprintf (dump_file, "Modifiable CCs: ");
5504 for (j = CC_FIRST; j <= CC_LAST; j++)
5505 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5506 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5508 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5509 frv_ifcvt.num_nested_cond_exec);
5513 /* Allocate the appropriate temporary condition code register. Try to
5514 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5515 that conditional cmp's can be done. */
5516 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5518 cr_class = ICR_REGS;
5519 cc_class = ICC_REGS;
5520 cc_first = ICC_FIRST;
5523 else if (mode == CC_FPmode)
5525 cr_class = FCR_REGS;
5526 cc_class = FCC_REGS;
5527 cc_first = FCC_FIRST;
5532 cc_first = cc_last = 0;
5533 cr_class = cc_class = NO_REGS;
5536 cc = XEXP (true_expr, 0);
5537 nested_cc = cr = NULL_RTX;
5538 if (cc_class != NO_REGS)
5540 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5541 so we can execute a csubcc/caddcc/cfcmps instruction. */
5544 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5546 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5548 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5549 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5551 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5552 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5555 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5556 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5566 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5573 "Will use %s for conditional execution, %s for nested comparisons\n",
5574 reg_names[ REGNO (cr)],
5575 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5577 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5578 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5579 bit being true. We don't do this for floating point, because of NaNs. */
5580 code = GET_CODE (true_expr);
5581 if (GET_MODE (cc) != CC_FPmode)
5583 code = reverse_condition (code);
5593 check_insn = gen_rtx_SET (VOIDmode, cr,
5594 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5596 /* Record the check insn to be inserted later. */
5597 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5599 /* Update the tests. */
5600 frv_ifcvt.cr_reg = cr;
5601 frv_ifcvt.nested_cc_reg = nested_cc;
5602 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5603 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5606 /* Fail, don't do this conditional execution. */
5609 *p_false = NULL_RTX;
5611 fprintf (dump_file, "Disabling this conditional execution.\n");
5617 /* A C expression to modify the code described by the conditional if
5618 information CE_INFO, for the basic block BB, possibly updating the tests in
5619 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5620 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5621 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5623 /* p_true and p_false are given expressions of the form:
5625 (and (eq:CC_CCR (reg:CC_CCR)
5631 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5636 rtx old_true = XEXP (*p_true, 0);
5637 rtx old_false = XEXP (*p_false, 0);
5638 rtx true_expr = XEXP (*p_true, 1);
5639 rtx false_expr = XEXP (*p_false, 1);
5642 rtx cr = XEXP (old_true, 0);
5644 rtx new_cr = NULL_RTX;
5645 rtx *p_new_cr = (rtx *)0;
5649 enum reg_class cr_class;
5650 enum machine_mode mode = GET_MODE (true_expr);
5651 rtx (*logical_func)(rtx, rtx, rtx);
5653 if (TARGET_DEBUG_COND_EXEC)
5656 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5657 ce_info->and_and_p ? "&&" : "||");
5659 debug_rtx (*p_true);
5661 fputs ("\nfalse insn:\n", stderr);
5662 debug_rtx (*p_false);
5665 if (!TARGET_MULTI_CE)
5668 if (GET_CODE (cr) != REG)
5671 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5673 cr_class = ICR_REGS;
5674 p_new_cr = &frv_ifcvt.extra_int_cr;
5676 else if (mode == CC_FPmode)
5678 cr_class = FCR_REGS;
5679 p_new_cr = &frv_ifcvt.extra_fp_cr;
5684 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5685 more &&/|| tests. */
5689 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5690 CC_CCRmode, TRUE, TRUE);
5695 if (ce_info->and_and_p)
5697 old_test = old_false;
5698 test_expr = true_expr;
5699 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5700 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5701 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5705 old_test = old_false;
5706 test_expr = false_expr;
5707 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5708 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5709 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5712 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5713 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5715 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5717 /* Now add the conditional check insn. */
5718 cc = XEXP (test_expr, 0);
5719 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5720 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5722 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5724 /* Add the new check insn to the list of check insns that need to be
5726 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5728 if (TARGET_DEBUG_COND_EXEC)
5730 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5733 debug_rtx (*p_true);
5735 fputs ("\nfalse insn:\n", stderr);
5736 debug_rtx (*p_false);
5742 *p_true = *p_false = NULL_RTX;
5744 /* If we allocated a CR register, release it. */
5747 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5748 *p_new_cr = NULL_RTX;
5751 if (TARGET_DEBUG_COND_EXEC)
5752 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5758 /* Return a register which will be loaded with a value if an IF block is
5759 converted to conditional execution. This is used to rewrite instructions
5760 that use constants to ones that just use registers. */
5763 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5765 int num_alloc = frv_ifcvt.cur_scratch_regs;
5769 /* We know gr0 == 0, so replace any errant uses. */
5770 if (value == const0_rtx)
5771 return gen_rtx_REG (SImode, GPR_FIRST);
5773 /* First search all registers currently loaded to see if we have an
5774 applicable constant. */
5775 if (CONSTANT_P (value)
5776 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5778 for (i = 0; i < num_alloc; i++)
5780 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5781 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5785 /* Have we exhausted the number of registers available? */
5786 if (num_alloc >= GPR_TEMP_NUM)
5789 fprintf (dump_file, "Too many temporary registers allocated\n");
5794 /* Allocate the new register. */
5795 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5799 fputs ("Could not find a scratch register\n", dump_file);
5804 frv_ifcvt.cur_scratch_regs++;
5805 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5809 if (GET_CODE (value) == CONST_INT)
5810 fprintf (dump_file, "Register %s will hold %ld\n",
5811 reg_names[ REGNO (reg)], (long)INTVAL (value));
5813 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5814 fprintf (dump_file, "Register %s will hold LR\n",
5815 reg_names[ REGNO (reg)]);
5818 fprintf (dump_file, "Register %s will hold a saved value\n",
5819 reg_names[ REGNO (reg)]);
5826 /* Update a MEM used in conditional code that might contain an offset to put
5827 the offset into a scratch register, so that the conditional load/store
5828 operations can be used. This function returns the original pointer if the
5829 MEM is valid to use in conditional code, NULL if we can't load up the offset
5830 into a temporary register, or the new MEM if we were successful. */
5833 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5835 rtx addr = XEXP (mem, 0);
5837 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5839 if (GET_CODE (addr) == PLUS)
5841 rtx addr_op0 = XEXP (addr, 0);
5842 rtx addr_op1 = XEXP (addr, 1);
5844 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5846 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5850 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5857 else if (CONSTANT_P (addr))
5858 addr = frv_ifcvt_load_value (addr, insn);
5863 if (addr == NULL_RTX)
5866 else if (XEXP (mem, 0) != addr)
5867 return change_address (mem, mode, addr);
5874 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5875 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5878 single_set_pattern (rtx pattern)
5883 if (GET_CODE (pattern) == COND_EXEC)
5884 pattern = COND_EXEC_CODE (pattern);
5886 if (GET_CODE (pattern) == SET)
5889 else if (GET_CODE (pattern) == PARALLEL)
5891 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5893 rtx sub = XVECEXP (pattern, 0, i);
5895 switch (GET_CODE (sub))
5919 /* A C expression to modify the code described by the conditional if
5920 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5921 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5922 insn cannot be converted to be executed conditionally. */
5925 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5929 rtx orig_ce_pattern = pattern;
5935 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5937 test = COND_EXEC_TEST (pattern);
5938 if (GET_CODE (test) == AND)
5940 rtx cr = frv_ifcvt.cr_reg;
5943 op0 = XEXP (test, 0);
5944 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5947 op1 = XEXP (test, 1);
5948 test_reg = XEXP (op1, 0);
5949 if (GET_CODE (test_reg) != REG)
5952 /* Is this the first nested if block in this sequence? If so, generate
5953 an andcr or andncr. */
5954 if (! frv_ifcvt.last_nested_if_cr)
5958 frv_ifcvt.last_nested_if_cr = test_reg;
5959 if (GET_CODE (op0) == NE)
5960 and_op = gen_andcr (test_reg, cr, test_reg);
5962 and_op = gen_andncr (test_reg, cr, test_reg);
5964 frv_ifcvt_add_insn (and_op, insn, TRUE);
5967 /* If this isn't the first statement in the nested if sequence, see if we
5968 are dealing with the same register. */
5969 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5972 COND_EXEC_TEST (pattern) = test = op1;
5975 /* If this isn't a nested if, reset state variables. */
5978 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5981 set = single_set_pattern (pattern);
5984 rtx dest = SET_DEST (set);
5985 rtx src = SET_SRC (set);
5986 enum machine_mode mode = GET_MODE (dest);
5988 /* Check for normal binary operators. */
5989 if (mode == SImode && ARITHMETIC_P (src))
5991 op0 = XEXP (src, 0);
5992 op1 = XEXP (src, 1);
5994 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
5996 op1 = frv_ifcvt_load_value (op1, insn);
5998 COND_EXEC_CODE (pattern)
5999 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6007 /* For multiply by a constant, we need to handle the sign extending
6008 correctly. Add a USE of the value after the multiply to prevent flow
6009 from cratering because only one register out of the two were used. */
6010 else if (mode == DImode && GET_CODE (src) == MULT)
6012 op0 = XEXP (src, 0);
6013 op1 = XEXP (src, 1);
6014 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6016 op1 = frv_ifcvt_load_value (op1, insn);
6019 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6020 COND_EXEC_CODE (pattern)
6021 = gen_rtx_SET (VOIDmode, dest,
6022 gen_rtx_MULT (DImode, op0, op1));
6028 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6031 /* If we are just loading a constant created for a nested conditional
6032 execution statement, just load the constant without any conditional
6033 execution, since we know that the constant will not interfere with any
6035 else if (frv_ifcvt.scratch_insns_bitmap
6036 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6038 && REG_P (SET_DEST (set))
6039 /* We must not unconditionally set a scratch reg chosen
6040 for a nested if-converted block if its incoming
6041 value from the TEST block (or the result of the THEN
6042 branch) could/should propagate to the JOIN block.
6043 It suffices to test whether the register is live at
6044 the JOIN point: if it's live there, we can infer
6045 that we set it in the former JOIN block of the
6046 nested if-converted block (otherwise it wouldn't
6047 have been available as a scratch register), and it
6048 is either propagated through or set in the other
6049 conditional block. It's probably not worth trying
6050 to catch the latter case, and it could actually
6051 limit scheduling of the combined block quite
6054 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6055 REGNO (SET_DEST (set))))
6056 /* Similarly, we must not unconditionally set a reg
6057 used as scratch in the THEN branch if the same reg
6058 is live in the ELSE branch. */
6059 && (! ce_info->else_bb
6060 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6061 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6062 REGNO (SET_DEST (set))))))
6065 else if (mode == QImode || mode == HImode || mode == SImode
6068 int changed_p = FALSE;
6070 /* Check for just loading up a constant */
6071 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6073 src = frv_ifcvt_load_value (src, insn);
6080 /* See if we need to fix up stores */
6081 if (GET_CODE (dest) == MEM)
6083 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6088 else if (new_mem != dest)
6095 /* See if we need to fix up loads */
6096 if (GET_CODE (src) == MEM)
6098 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6103 else if (new_mem != src)
6110 /* If either src or destination changed, redo SET. */
6112 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6115 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6116 rewriting the CC register to be the same as the paired CC/CR register
6118 else if (mode == CC_CCRmode && COMPARISON_P (src))
6120 int regno = REGNO (XEXP (src, 0));
6123 if (ce_info->pass > 1
6124 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6125 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6127 src = gen_rtx_fmt_ee (GET_CODE (src),
6129 frv_ifcvt.nested_cc_reg,
6133 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6134 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6137 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6138 else if (ce_info->pass > 1
6139 && GET_CODE (dest) == REG
6140 && CC_P (REGNO (dest))
6141 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6142 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6144 && GET_CODE (src) == COMPARE)
6146 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6147 COND_EXEC_CODE (pattern)
6148 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6152 if (TARGET_DEBUG_COND_EXEC)
6154 rtx orig_pattern = PATTERN (insn);
6156 PATTERN (insn) = pattern;
6158 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6162 PATTERN (insn) = orig_pattern;
6168 if (TARGET_DEBUG_COND_EXEC)
6170 rtx orig_pattern = PATTERN (insn);
6172 PATTERN (insn) = orig_ce_pattern;
6174 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6178 PATTERN (insn) = orig_pattern;
6185 /* A C expression to perform any final machine dependent modifications in
6186 converting code to conditional execution in the code described by the
6187 conditional if information CE_INFO. */
6190 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6194 rtx p = frv_ifcvt.added_insns_list;
6197 /* Loop inserting the check insns. The last check insn is the first test,
6198 and is the appropriate place to insert constants. */
6203 rtx check_and_insert_insns = XEXP (p, 0);
6206 check_insn = XEXP (check_and_insert_insns, 0);
6207 existing_insn = XEXP (check_and_insert_insns, 1);
6210 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6211 the existing insn, otherwise it is to be inserted AFTER. */
6212 if (check_and_insert_insns->jump)
6214 emit_insn_before (check_insn, existing_insn);
6215 check_and_insert_insns->jump = 0;
6218 emit_insn_after (check_insn, existing_insn);
6220 free_EXPR_LIST_node (check_and_insert_insns);
6221 free_EXPR_LIST_node (old_p);
6223 while (p != NULL_RTX);
6225 /* Load up any constants needed into temp gprs */
6226 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6228 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6229 if (! frv_ifcvt.scratch_insns_bitmap)
6230 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6231 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6232 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6235 frv_ifcvt.added_insns_list = NULL_RTX;
6236 frv_ifcvt.cur_scratch_regs = 0;
6240 /* A C expression to cancel any machine dependent modifications in converting
6241 code to conditional execution in the code described by the conditional if
6242 information CE_INFO. */
6245 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6248 rtx p = frv_ifcvt.added_insns_list;
6250 /* Loop freeing up the EXPR_LIST's allocated. */
6251 while (p != NULL_RTX)
6253 rtx check_and_jump = XEXP (p, 0);
6257 free_EXPR_LIST_node (check_and_jump);
6258 free_EXPR_LIST_node (old_p);
6261 /* Release any temporary gprs allocated. */
6262 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6263 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6265 frv_ifcvt.added_insns_list = NULL_RTX;
6266 frv_ifcvt.cur_scratch_regs = 0;
6270 /* A C expression for the size in bytes of the trampoline, as an integer.
6274 setlo #0, <static_chain>
6276 sethi #0, <static_chain>
6277 jmpl @(gr0,<jmp_reg>) */
6280 frv_trampoline_size (void)
6283 /* Allocate room for the function descriptor and the lddi
6286 return 5 /* instructions */ * 4 /* instruction size. */;
6290 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6291 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6292 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6293 should be passed to the function when it is called.
6298 setlo #0, <static_chain>
6300 sethi #0, <static_chain>
6301 jmpl @(gr0,<jmp_reg>) */
6304 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
6306 rtx sc_reg = force_reg (Pmode, static_chain);
6308 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6311 GEN_INT (frv_trampoline_size ()), SImode,
6317 /* Many machines have some registers that cannot be copied directly to or from
6318 memory or even from other types of registers. An example is the `MQ'
6319 register, which on most machines, can only be copied to or from general
6320 registers, but not memory. Some machines allow copying all registers to and
6321 from memory, but require a scratch register for stores to some memory
6322 locations (e.g., those with symbolic address on the RT, and those with
6323 certain symbolic address on the SPARC when compiling PIC). In some cases,
6324 both an intermediate and a scratch register are required.
6326 You should define these macros to indicate to the reload phase that it may
6327 need to allocate at least one register for a reload in addition to the
6328 register to contain the data. Specifically, if copying X to a register
6329 RCLASS in MODE requires an intermediate register, you should define
6330 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6331 whose registers can be used as intermediate registers or scratch registers.
6333 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6334 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6335 largest register class required. If the requirements for input and output
6336 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6337 instead of defining both macros identically.
6339 The values returned by these macros are often `GENERAL_REGS'. Return
6340 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6341 to or from a register of RCLASS in MODE without requiring a scratch register.
6342 Do not define this macro if it would always return `NO_REGS'.
6344 If a scratch register is required (either with or without an intermediate
6345 register), you should define patterns for `reload_inM' or `reload_outM', as
6346 required.. These patterns, which will normally be implemented with a
6347 `define_expand', should be similar to the `movM' patterns, except that
6348 operand 2 is the scratch register.
6350 Define constraints for the reload register and scratch register that contain
6351 a single register class. If the original reload register (whose class is
6352 RCLASS) can meet the constraint given in the pattern, the value returned by
6353 these macros is used for the class of the scratch register. Otherwise, two
6354 additional reload registers are required. Their classes are obtained from
6355 the constraints in the insn pattern.
6357 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6358 either be in a hard register or in memory. Use `true_regnum' to find out;
6359 it will return -1 if the pseudo is in memory and the hard register number if
6360 it is in a register.
6362 These macros should not be used in the case where a particular class of
6363 registers can only be copied to memory and not to another class of
6364 registers. In that case, secondary reload registers are not needed and
6365 would not be helpful. Instead, a stack location must be used to perform the
6366 copy and the `movM' pattern should use memory as an intermediate storage.
6367 This case often occurs between floating-point and general registers. */
6370 frv_secondary_reload_class (enum reg_class rclass,
6371 enum machine_mode mode ATTRIBUTE_UNUSED,
6382 /* Accumulators/Accumulator guard registers need to go through floating
6388 if (x && GET_CODE (x) == REG)
6390 int regno = REGNO (x);
6392 if (ACC_P (regno) || ACCG_P (regno))
6397 /* Nonzero constants should be loaded into an FPR through a GPR. */
6401 if (x && CONSTANT_P (x) && !ZERO_P (x))
6407 /* All of these types need gpr registers. */
6419 /* The accumulators need fpr registers. */
6431 /* This hook exists to catch the case where secondary_reload_class() is
6432 called from init_reg_autoinc() in regclass.c - before the reload optabs
6433 have been initialised. */
6436 frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
6437 enum machine_mode reload_mode,
6438 secondary_reload_info * sri)
6440 enum reg_class rclass = NO_REGS;
6442 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6444 sri->icode = sri->prev_sri->t_icode;
6448 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6450 if (rclass != NO_REGS)
6452 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
6453 : reload_out_optab[(int) reload_mode]);
6456 /* This happens when then the reload_[in|out]_optabs have
6457 not been initialised. */
6458 sri->t_icode = CODE_FOR_nothing;
6463 /* Fall back to the default secondary reload handler. */
6464 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6468 /* A C expression whose value is nonzero if pseudos that have been assigned to
6469 registers of class RCLASS would likely be spilled because registers of RCLASS
6470 are needed for spill registers.
6472 The default value of this macro returns 1 if RCLASS has exactly one register
6473 and zero otherwise. On most machines, this default should be used. Only
6474 define this macro to some other expression if pseudo allocated by
6475 `local-alloc.c' end up in memory because their hard registers were needed
6476 for spill registers. If this macro returns nonzero for those classes, those
6477 pseudos will only be allocated by `global.c', which knows how to reallocate
6478 the pseudo to another register. If there would not be another register
6479 available for reallocation, you should not change the definition of this
6480 macro since the only effect of such a definition would be to slow down
6481 register allocation. */
6484 frv_class_likely_spilled_p (enum reg_class rclass)
6494 case FDPIC_FPTR_REGS:
6516 /* An expression for the alignment of a structure field FIELD if the
6517 alignment computed in the usual way is COMPUTED. GCC uses this
6518 value instead of the value in `BIGGEST_ALIGNMENT' or
6519 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6521 /* The definition type of the bit field data is either char, short, long or
6522 long long. The maximum bit size is the number of bits of its own type.
6524 The bit field data is assigned to a storage unit that has an adequate size
6525 for bit field data retention and is located at the smallest address.
6527 Consecutive bit field data are packed at consecutive bits having the same
6528 storage unit, with regard to the type, beginning with the MSB and continuing
6531 If a field to be assigned lies over a bit field type boundary, its
6532 assignment is completed by aligning it with a boundary suitable for the
6535 When a bit field having a bit length of 0 is declared, it is forcibly
6536 assigned to the next storage unit.
6549 &x 00000000 00000000 00000000 00000000
6552 &x+4 00000000 00000000 00000000 00000000
6555 &x+8 00000000 00000000 00000000 00000000
6558 &x+12 00000000 00000000 00000000 00000000
6564 frv_adjust_field_align (tree field, int computed)
6566 /* Make sure that the bitfield is not wider than the type. */
6567 if (DECL_BIT_FIELD (field)
6568 && !DECL_ARTIFICIAL (field))
6570 tree parent = DECL_CONTEXT (field);
6571 tree prev = NULL_TREE;
6574 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6576 if (TREE_CODE (cur) != FIELD_DECL)
6584 /* If this isn't a :0 field and if the previous element is a bitfield
6585 also, see if the type is different, if so, we will need to align the
6586 bit-field to the next boundary. */
6588 && ! DECL_PACKED (field)
6589 && ! integer_zerop (DECL_SIZE (field))
6590 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6592 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6593 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6594 computed = (prev_align > cur_align) ? prev_align : cur_align;
6602 /* A C expression that is nonzero if it is permissible to store a value of mode
6603 MODE in hard register number REGNO (or in several registers starting with
6604 that one). For a machine where all registers are equivalent, a suitable
6607 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6609 It is not necessary for this macro to check for the numbers of fixed
6610 registers, because the allocation mechanism considers them to be always
6613 On some machines, double-precision values must be kept in even/odd register
6614 pairs. The way to implement that is to define this macro to reject odd
6615 register numbers for such modes.
6617 The minimum requirement for a mode to be OK in a register is that the
6618 `movMODE' instruction pattern support moves between the register and any
6619 other hard register for which the mode is OK; and that moving a value into
6620 the register and back out not alter it.
6622 Since the same instruction used to move `SImode' will work for all narrower
6623 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6624 to distinguish between these modes, provided you define patterns `movhi',
6625 etc., to take advantage of this. This is useful because of the interaction
6626 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6627 all integer modes to be tieable.
6629 Many machines have special registers for floating point arithmetic. Often
6630 people assume that floating point machine modes are allowed only in floating
6631 point registers. This is not true. Any registers that can hold integers
6632 can safely *hold* a floating point machine mode, whether or not floating
6633 arithmetic can be done on it in those registers. Integer move instructions
6634 can be used to move the values.
6636 On some machines, though, the converse is true: fixed-point machine modes
6637 may not go in floating registers. This is true if the floating registers
6638 normalize any value stored in them, because storing a non-floating value
6639 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6640 fixed-point machine modes in floating registers. But if the floating
6641 registers do not automatically normalize, if you can store any bit pattern
6642 in one and retrieve it unchanged without a trap, then any machine mode may
6643 go in a floating register, so you can define this macro to say so.
6645 The primary significance of special floating registers is rather that they
6646 are the registers acceptable in floating point arithmetic instructions.
6647 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6648 writing the proper constraints for those instructions.
6650 On some machines, the floating registers are especially slow to access, so
6651 that it is better to store a value in a stack frame than in such a register
6652 if floating point arithmetic is not being done. As long as the floating
6653 registers are not in class `GENERAL_REGS', they will not be used unless some
6654 pattern's constraint asks for one. */
6657 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6667 return ICC_P (regno) || GPR_P (regno);
6670 return CR_P (regno) || GPR_P (regno);
6673 return FCC_P (regno) || GPR_P (regno);
6679 /* Set BASE to the first register in REGNO's class. Set MASK to the
6680 bits that must be clear in (REGNO - BASE) for the register to be
6682 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6686 /* ACCGs store one byte. Two-byte quantities must start in
6687 even-numbered registers, four-byte ones in registers whose
6688 numbers are divisible by four, and so on. */
6690 mask = GET_MODE_SIZE (mode) - 1;
6694 /* The other registers store one word. */
6695 if (GPR_P (regno) || regno == AP_FIRST)
6698 else if (FPR_P (regno))
6701 else if (ACC_P (regno))
6704 else if (SPR_P (regno))
6705 return mode == SImode;
6707 /* Fill in the table. */
6711 /* Anything smaller than an SI is OK in any word-sized register. */
6712 if (GET_MODE_SIZE (mode) < 4)
6715 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6717 return (((regno - base) & mask) == 0);
6724 /* A C expression for the number of consecutive hard registers, starting at
6725 register number REGNO, required to hold a value of mode MODE.
6727 On a machine where all registers are exactly one word, a suitable definition
6730 #define HARD_REGNO_NREGS(REGNO, MODE) \
6731 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6732 / UNITS_PER_WORD)) */
6734 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6735 that we can build the appropriate instructions to properly reload the
6736 values. Also, make the byte-sized accumulator guards use one guard
6740 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6743 return GET_MODE_SIZE (mode);
6745 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6749 /* A C expression for the maximum number of consecutive registers of
6750 class RCLASS needed to hold a value of mode MODE.
6752 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6753 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6754 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6756 This macro helps control the handling of multiple-word values in
6759 This declaration is required. */
6762 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6764 if (rclass == ACCG_REGS)
6765 /* An N-byte value requires N accumulator guards. */
6766 return GET_MODE_SIZE (mode);
6768 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6772 /* A C expression that is nonzero if X is a legitimate constant for an
6773 immediate operand on the target machine. You can assume that X satisfies
6774 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6775 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6778 frv_legitimate_constant_p (rtx x)
6780 enum machine_mode mode = GET_MODE (x);
6782 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6783 means that the move expanders will be expected to deal with most
6784 kinds of constant, regardless of what we return here.
6786 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6787 a constant can be entered into reg_equiv_constant[]. If we return true,
6788 reload can create new instances of the constant whenever it likes.
6790 The idea is therefore to accept as many constants as possible (to give
6791 reload more freedom) while rejecting constants that can only be created
6792 at certain times. In particular, anything with a symbolic component will
6793 require use of the pseudo FDPIC register, which is only available before
6796 return LEGITIMATE_PIC_OPERAND_P (x);
6798 /* All of the integer constants are ok. */
6799 if (GET_CODE (x) != CONST_DOUBLE)
6802 /* double integer constants are ok. */
6803 if (mode == VOIDmode || mode == DImode)
6806 /* 0 is always ok. */
6807 if (x == CONST0_RTX (mode))
6810 /* If floating point is just emulated, allow any constant, since it will be
6811 constructed in the GPRs. */
6812 if (!TARGET_HAS_FPRS)
6815 if (mode == DFmode && !TARGET_DOUBLE)
6818 /* Otherwise store the constant away and do a load. */
6822 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6823 CC_NZ for comparisons against zero in which a single Z or N flag test
6824 is enough, CC_UNS for other unsigned comparisons, and CC for other
6825 signed comparisons. */
6828 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6830 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6839 return y == const0_rtx ? CC_NZmode : CCmode;
6845 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6852 /* A C expression for the cost of moving data from a register in class FROM to
6853 one in class TO. The classes are expressed using the enumeration values
6854 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6855 interpreted relative to that.
6857 It is not required that the cost always equal 2 when FROM is the same as TO;
6858 on some machines it is expensive to move between registers if they are not
6861 If reload sees an insn consisting of a single `set' between two hard
6862 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6863 value of 2, reload does not check to ensure that the constraints of the insn
6864 are met. Setting a cost of other than 2 will allow reload to verify that
6865 the constraints are met. You should do this if the `movM' pattern's
6866 constraints do not allow such copying. */
6868 #define HIGH_COST 40
6869 #define MEDIUM_COST 3
6873 frv_register_move_cost (enum reg_class from, enum reg_class to)
6957 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6958 use ".picptr" to generate safe relocations for PIC code. We also
6959 need a fixup entry for aligned (non-debugging) code. */
6962 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6964 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6966 if (GET_CODE (value) == CONST
6967 || GET_CODE (value) == SYMBOL_REF
6968 || GET_CODE (value) == LABEL_REF)
6970 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6971 && SYMBOL_REF_FUNCTION_P (value))
6973 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6974 output_addr_const (asm_out_file, value);
6975 fputs (")\n", asm_out_file);
6978 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6979 && frv_function_symbol_referenced_p (value))
6981 if (aligned_p && !TARGET_FDPIC)
6983 static int label_num = 0;
6987 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
6988 p = (* targetm.strip_name_encoding) (buf);
6990 fprintf (asm_out_file, "%s:\n", p);
6991 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
6992 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
6993 fprintf (asm_out_file, "\t.previous\n");
6995 assemble_integer_with_op ("\t.picptr\t", value);
7000 /* We've set the unaligned SI op to NULL, so we always have to
7001 handle the unaligned case here. */
7002 assemble_integer_with_op ("\t.4byte\t", value);
7006 return default_assemble_integer (value, size, aligned_p);
7009 /* Function to set up the backend function structure. */
7011 static struct machine_function *
7012 frv_init_machine_status (void)
7014 return GGC_CNEW (struct machine_function);
7017 /* Implement TARGET_SCHED_ISSUE_RATE. */
7020 frv_issue_rate (void)
7025 switch (frv_cpu_type)
7029 case FRV_CPU_SIMPLE:
7037 case FRV_CPU_GENERIC:
7039 case FRV_CPU_TOMCAT:
7047 /* A for_each_rtx callback. If X refers to an accumulator, return
7048 ACC_GROUP_ODD if the bit 2 of the register number is set and
7049 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7053 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7057 if (ACC_P (REGNO (*x)))
7058 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7059 if (ACCG_P (REGNO (*x)))
7060 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7065 /* Return the value of INSN's acc_group attribute. */
7068 frv_acc_group (rtx insn)
7070 /* This distinction only applies to the FR550 packing constraints. */
7071 if (frv_cpu_type != FRV_CPU_FR550)
7072 return ACC_GROUP_NONE;
7073 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7076 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7077 INSN will try to claim first. Since this value depends only on the
7078 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7081 frv_insn_unit (rtx insn)
7083 enum attr_type type;
7085 type = get_attr_type (insn);
7086 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7088 /* We haven't seen this type of instruction before. */
7092 /* Issue the instruction on its own to see which unit it prefers. */
7093 state = alloca (state_size ());
7094 state_reset (state);
7095 state_transition (state, insn);
7097 /* Find out which unit was taken. */
7098 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7099 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7102 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7104 frv_type_to_unit[type] = unit;
7106 return frv_type_to_unit[type];
7109 /* Return true if INSN issues to a branch unit. */
7112 frv_issues_to_branch_unit_p (rtx insn)
7114 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7117 /* The current state of the packing pass, implemented by frv_pack_insns. */
7119 /* The state of the pipeline DFA. */
7122 /* Which hardware registers are set within the current packet,
7123 and the conditions under which they are set. */
7124 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7126 /* The memory locations that have been modified so far in this
7127 packet. MEM is the memref and COND is the regstate_t condition
7128 under which it is set. */
7134 /* The number of valid entries in MEMS. The value is larger than
7135 ARRAY_SIZE (mems) if there were too many mems to record. */
7136 unsigned int num_mems;
7138 /* The maximum number of instructions that can be packed together. */
7139 unsigned int issue_rate;
7141 /* The instructions in the packet, partitioned into groups. */
7142 struct frv_packet_group {
7143 /* How many instructions in the packet belong to this group. */
7144 unsigned int num_insns;
7146 /* A list of the instructions that belong to this group, in the order
7147 they appear in the rtl stream. */
7148 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7150 /* The contents of INSNS after they have been sorted into the correct
7151 assembly-language order. Element X issues to unit X. The list may
7152 contain extra nops. */
7153 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7155 /* The member of frv_nops[] to use in sorted[]. */
7157 } groups[NUM_GROUPS];
7159 /* The instructions that make up the current packet. */
7160 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7161 unsigned int num_insns;
7164 /* Return the regstate_t flags for the given COND_EXEC condition.
7165 Abort if the condition isn't in the right form. */
7168 frv_cond_flags (rtx cond)
7170 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7171 && GET_CODE (XEXP (cond, 0)) == REG
7172 && CR_P (REGNO (XEXP (cond, 0)))
7173 && XEXP (cond, 1) == const0_rtx);
7174 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7175 | (GET_CODE (cond) == NE
7177 : REGSTATE_IF_FALSE));
7181 /* Return true if something accessed under condition COND2 can
7182 conflict with something written under condition COND1. */
7185 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7187 /* If either reference was unconditional, we have a conflict. */
7188 if ((cond1 & REGSTATE_IF_EITHER) == 0
7189 || (cond2 & REGSTATE_IF_EITHER) == 0)
7192 /* The references might conflict if they were controlled by
7194 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7197 /* They definitely conflict if they are controlled by the
7199 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7206 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7207 the current packet. DATA points to a regstate_t that describes the
7208 condition under which *X might be set or used. */
7211 frv_registers_conflict_p_1 (rtx *x, void *data)
7213 unsigned int regno, i;
7216 cond = *(regstate_t *) data;
7218 if (GET_CODE (*x) == REG)
7219 FOR_EACH_REGNO (regno, *x)
7220 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7221 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7224 if (GET_CODE (*x) == MEM)
7226 /* If we ran out of memory slots, assume a conflict. */
7227 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7230 /* Check for output or true dependencies with earlier MEMs. */
7231 for (i = 0; i < frv_packet.num_mems; i++)
7232 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7234 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7238 if (output_dependence (frv_packet.mems[i].mem, *x))
7243 /* The return values of calls aren't significant: they describe
7244 the effect of the call as a whole, not of the insn itself. */
7245 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7247 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7252 /* Check subexpressions. */
7257 /* Return true if something in X might depend on an instruction
7258 in the current packet. */
7261 frv_registers_conflict_p (rtx x)
7266 if (GET_CODE (x) == COND_EXEC)
7268 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7271 flags |= frv_cond_flags (XEXP (x, 0));
7274 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7278 /* A note_stores callback. DATA points to the regstate_t condition
7279 under which X is modified. Update FRV_PACKET accordingly. */
7282 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7286 if (GET_CODE (x) == REG)
7287 FOR_EACH_REGNO (regno, x)
7288 frv_packet.regstate[regno] |= *(regstate_t *) data;
7290 if (GET_CODE (x) == MEM)
7292 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7294 frv_packet.mems[frv_packet.num_mems].mem = x;
7295 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7297 frv_packet.num_mems++;
7302 /* Update the register state information for an instruction whose
7306 frv_registers_update (rtx x)
7310 flags = REGSTATE_MODIFIED;
7311 if (GET_CODE (x) == COND_EXEC)
7313 flags |= frv_cond_flags (XEXP (x, 0));
7316 note_stores (x, frv_registers_update_1, &flags);
7320 /* Initialize frv_packet for the start of a new packet. */
7323 frv_start_packet (void)
7325 enum frv_insn_group group;
7327 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7328 frv_packet.num_mems = 0;
7329 frv_packet.num_insns = 0;
7330 for (group = 0; group < NUM_GROUPS; group++)
7331 frv_packet.groups[group].num_insns = 0;
7335 /* Likewise for the start of a new basic block. */
7338 frv_start_packet_block (void)
7340 state_reset (frv_packet.dfa_state);
7341 frv_start_packet ();
7345 /* Finish the current packet, if any, and start a new one. Call
7346 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7349 frv_finish_packet (void (*handle_packet) (void))
7351 if (frv_packet.num_insns > 0)
7354 state_transition (frv_packet.dfa_state, 0);
7355 frv_start_packet ();
7360 /* Return true if INSN can be added to the current packet. Update
7361 the DFA state on success. */
7364 frv_pack_insn_p (rtx insn)
7366 /* See if the packet is already as long as it can be. */
7367 if (frv_packet.num_insns == frv_packet.issue_rate)
7370 /* If the scheduler thought that an instruction should start a packet,
7371 it's usually a good idea to believe it. It knows much more about
7372 the latencies than we do.
7374 There are some exceptions though:
7376 - Conditional instructions are scheduled on the assumption that
7377 they will be executed. This is usually a good thing, since it
7378 tends to avoid unnecessary stalls in the conditional code.
7379 But we want to pack conditional instructions as tightly as
7380 possible, in order to optimize the case where they aren't
7383 - The scheduler will always put branches on their own, even
7384 if there's no real dependency.
7386 - There's no point putting a call in its own packet unless
7388 if (frv_packet.num_insns > 0
7389 && GET_CODE (insn) == INSN
7390 && GET_MODE (insn) == TImode
7391 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7394 /* Check for register conflicts. Don't do this for setlo since any
7395 conflict will be with the partnering sethi, with which it can
7397 if (get_attr_type (insn) != TYPE_SETLO)
7398 if (frv_registers_conflict_p (PATTERN (insn)))
7401 return state_transition (frv_packet.dfa_state, insn) < 0;
7405 /* Add instruction INSN to the current packet. */
7408 frv_add_insn_to_packet (rtx insn)
7410 struct frv_packet_group *packet_group;
7412 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7413 packet_group->insns[packet_group->num_insns++] = insn;
7414 frv_packet.insns[frv_packet.num_insns++] = insn;
7416 frv_registers_update (PATTERN (insn));
7420 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7421 packet ends in a branch or call, insert the nop before it, otherwise
7425 frv_insert_nop_in_packet (rtx insn)
7427 struct frv_packet_group *packet_group;
7430 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7431 last = frv_packet.insns[frv_packet.num_insns - 1];
7432 if (GET_CODE (last) != INSN)
7434 insn = emit_insn_before (PATTERN (insn), last);
7435 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7436 frv_packet.insns[frv_packet.num_insns++] = last;
7440 insn = emit_insn_after (PATTERN (insn), last);
7441 frv_packet.insns[frv_packet.num_insns++] = insn;
7443 packet_group->insns[packet_group->num_insns++] = insn;
7447 /* If packing is enabled, divide the instructions into packets and
7448 return true. Call HANDLE_PACKET for each complete packet. */
7451 frv_for_each_packet (void (*handle_packet) (void))
7453 rtx insn, next_insn;
7455 frv_packet.issue_rate = frv_issue_rate ();
7457 /* Early exit if we don't want to pack insns. */
7459 || !flag_schedule_insns_after_reload
7460 || !TARGET_VLIW_BRANCH
7461 || frv_packet.issue_rate == 1)
7464 /* Set up the initial packing state. */
7466 frv_packet.dfa_state = alloca (state_size ());
7468 frv_start_packet_block ();
7469 for (insn = get_insns (); insn != 0; insn = next_insn)
7474 code = GET_CODE (insn);
7475 next_insn = NEXT_INSN (insn);
7477 if (code == CODE_LABEL)
7479 frv_finish_packet (handle_packet);
7480 frv_start_packet_block ();
7484 switch (GET_CODE (PATTERN (insn)))
7493 /* Calls mustn't be packed on a TOMCAT. */
7494 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7495 frv_finish_packet (handle_packet);
7497 /* Since the last instruction in a packet determines the EH
7498 region, any exception-throwing instruction must come at
7499 the end of reordered packet. Insns that issue to a
7500 branch unit are bound to come last; for others it's
7501 too hard to predict. */
7502 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7503 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7504 frv_finish_packet (handle_packet);
7506 /* Finish the current packet if we can't add INSN to it.
7507 Simulate cycles until INSN is ready to issue. */
7508 if (!frv_pack_insn_p (insn))
7510 frv_finish_packet (handle_packet);
7511 while (!frv_pack_insn_p (insn))
7512 state_transition (frv_packet.dfa_state, 0);
7515 /* Add the instruction to the packet. */
7516 frv_add_insn_to_packet (insn);
7518 /* Calls and jumps end a packet, as do insns that throw
7520 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7521 frv_finish_packet (handle_packet);
7525 frv_finish_packet (handle_packet);
7530 /* Subroutine of frv_sort_insn_group. We are trying to sort
7531 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7532 language order. We have already picked a new position for
7533 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7534 These instructions will occupy elements [0, LOWER_SLOT) and
7535 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7536 the DFA state after issuing these instructions.
7538 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7539 of the unused instructions. Return true if one such permutation gives
7540 a valid ordering, leaving the successful permutation in sorted[].
7541 Do not modify sorted[] until a valid permutation is found. */
7544 frv_sort_insn_group_1 (enum frv_insn_group group,
7545 unsigned int lower_slot, unsigned int upper_slot,
7546 unsigned int issued, unsigned int num_insns,
7549 struct frv_packet_group *packet_group;
7555 /* Early success if we've filled all the slots. */
7556 if (lower_slot == upper_slot)
7559 packet_group = &frv_packet.groups[group];
7560 dfa_size = state_size ();
7561 test_state = alloca (dfa_size);
7563 /* Try issuing each unused instruction. */
7564 for (i = num_insns - 1; i + 1 != 0; i--)
7565 if (~issued & (1 << i))
7567 insn = packet_group->sorted[i];
7568 memcpy (test_state, state, dfa_size);
7569 if (state_transition (test_state, insn) < 0
7570 && cpu_unit_reservation_p (test_state,
7571 NTH_UNIT (group, upper_slot - 1))
7572 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7573 issued | (1 << i), num_insns,
7576 packet_group->sorted[upper_slot - 1] = insn;
7584 /* Compare two instructions by their frv_insn_unit. */
7587 frv_compare_insns (const void *first, const void *second)
7589 const rtx *const insn1 = (rtx const *) first,
7590 *const insn2 = (rtx const *) second;
7591 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7594 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7595 and sort it into assembly language order. See frv.md for a description of
7599 frv_sort_insn_group (enum frv_insn_group group)
7601 struct frv_packet_group *packet_group;
7602 unsigned int first, i, nop, max_unit, num_slots;
7603 state_t state, test_state;
7606 packet_group = &frv_packet.groups[group];
7608 /* Assume no nop is needed. */
7609 packet_group->nop = 0;
7611 if (packet_group->num_insns == 0)
7614 /* Copy insns[] to sorted[]. */
7615 memcpy (packet_group->sorted, packet_group->insns,
7616 sizeof (rtx) * packet_group->num_insns);
7618 /* Sort sorted[] by the unit that each insn tries to take first. */
7619 if (packet_group->num_insns > 1)
7620 qsort (packet_group->sorted, packet_group->num_insns,
7621 sizeof (rtx), frv_compare_insns);
7623 /* That's always enough for branch and control insns. */
7624 if (group == GROUP_B || group == GROUP_C)
7627 dfa_size = state_size ();
7628 state = alloca (dfa_size);
7629 test_state = alloca (dfa_size);
7631 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7632 consecutively and such that the DFA takes unit X when sorted[X]
7633 is added. Set STATE to the new DFA state. */
7634 state_reset (test_state);
7635 for (first = 0; first < packet_group->num_insns; first++)
7637 memcpy (state, test_state, dfa_size);
7638 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7639 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7643 /* If all the instructions issued in ascending order, we're done. */
7644 if (first == packet_group->num_insns)
7647 /* Add nops to the end of sorted[] and try each permutation until
7648 we find one that works. */
7649 for (nop = 0; nop < frv_num_nops; nop++)
7651 max_unit = frv_insn_unit (frv_nops[nop]);
7652 if (frv_unit_groups[max_unit] == group)
7654 packet_group->nop = frv_nops[nop];
7655 num_slots = UNIT_NUMBER (max_unit) + 1;
7656 for (i = packet_group->num_insns; i < num_slots; i++)
7657 packet_group->sorted[i] = frv_nops[nop];
7658 if (frv_sort_insn_group_1 (group, first, num_slots,
7659 (1 << first) - 1, num_slots, state))
7666 /* Sort the current packet into assembly-language order. Set packing
7667 flags as appropriate. */
7670 frv_reorder_packet (void)
7672 unsigned int cursor[NUM_GROUPS];
7673 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7674 unsigned int unit, to, from;
7675 enum frv_insn_group group;
7676 struct frv_packet_group *packet_group;
7678 /* First sort each group individually. */
7679 for (group = 0; group < NUM_GROUPS; group++)
7682 frv_sort_insn_group (group);
7685 /* Go through the unit template and try add an instruction from
7686 that unit's group. */
7688 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7690 group = frv_unit_groups[unit];
7691 packet_group = &frv_packet.groups[group];
7692 if (cursor[group] < packet_group->num_insns)
7694 /* frv_reorg should have added nops for us. */
7695 gcc_assert (packet_group->sorted[cursor[group]]
7696 != packet_group->nop);
7697 insns[to++] = packet_group->sorted[cursor[group]++];
7701 gcc_assert (to == frv_packet.num_insns);
7703 /* Clear the last instruction's packing flag, thus marking the end of
7704 a packet. Reorder the other instructions relative to it. */
7705 CLEAR_PACKING_FLAG (insns[to - 1]);
7706 for (from = 0; from < to - 1; from++)
7708 remove_insn (insns[from]);
7709 add_insn_before (insns[from], insns[to - 1], NULL);
7710 SET_PACKING_FLAG (insns[from]);
7715 /* Divide instructions into packets. Reorder the contents of each
7716 packet so that they are in the correct assembly-language order.
7718 Since this pass can change the raw meaning of the rtl stream, it must
7719 only be called at the last minute, just before the instructions are
7723 frv_pack_insns (void)
7725 if (frv_for_each_packet (frv_reorder_packet))
7726 frv_insn_packing_flag = 0;
7728 frv_insn_packing_flag = -1;
7731 /* See whether we need to add nops to group GROUP in order to
7732 make a valid packet. */
7735 frv_fill_unused_units (enum frv_insn_group group)
7737 unsigned int non_nops, nops, i;
7738 struct frv_packet_group *packet_group;
7740 packet_group = &frv_packet.groups[group];
7742 /* Sort the instructions into assembly-language order.
7743 Use nops to fill slots that are otherwise unused. */
7744 frv_sort_insn_group (group);
7746 /* See how many nops are needed before the final useful instruction. */
7748 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7749 while (packet_group->sorted[i++] == packet_group->nop)
7752 /* Insert that many nops into the instruction stream. */
7754 frv_insert_nop_in_packet (packet_group->nop);
7757 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7760 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7762 if (io1->const_address != 0 && io2->const_address != 0)
7763 return io1->const_address == io2->const_address;
7765 if (io1->var_address != 0 && io2->var_address != 0)
7766 return rtx_equal_p (io1->var_address, io2->var_address);
7771 /* Return true if operations IO1 and IO2 are guaranteed to complete
7775 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7777 /* The order of writes is always preserved. */
7778 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7781 /* The order of reads isn't preserved. */
7782 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7785 /* One operation is a write and the other is (or could be) a read.
7786 The order is only guaranteed if the accesses are to the same
7788 return frv_same_doubleword_p (io1, io2);
7791 /* Generalize I/O operation X so that it covers both X and Y. */
7794 frv_io_union (struct frv_io *x, const struct frv_io *y)
7796 if (x->type != y->type)
7797 x->type = FRV_IO_UNKNOWN;
7798 if (!frv_same_doubleword_p (x, y))
7800 x->const_address = 0;
7805 /* Fill IO with information about the load or store associated with
7806 membar instruction INSN. */
7809 frv_extract_membar (struct frv_io *io, rtx insn)
7811 extract_insn (insn);
7812 io->type = INTVAL (recog_data.operand[2]);
7813 io->const_address = INTVAL (recog_data.operand[1]);
7814 io->var_address = XEXP (recog_data.operand[0], 0);
7817 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7818 if X is a register and *DATA depends on X. */
7821 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7823 rtx *other = (rtx *) data;
7825 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7829 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7830 Remove every modified register from the set. */
7833 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7835 HARD_REG_SET *set = (HARD_REG_SET *) data;
7839 FOR_EACH_REGNO (regno, x)
7840 CLEAR_HARD_REG_BIT (*set, regno);
7843 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7844 Add every register in *X to the set. */
7847 frv_io_handle_use_1 (rtx *x, void *data)
7849 HARD_REG_SET *set = (HARD_REG_SET *) data;
7853 FOR_EACH_REGNO (regno, *x)
7854 SET_HARD_REG_BIT (*set, regno);
7859 /* A note_stores callback that applies frv_io_handle_use_1 to an
7860 entire rhs value. */
7863 frv_io_handle_use (rtx *x, void *data)
7865 for_each_rtx (x, frv_io_handle_use_1, data);
7868 /* Go through block BB looking for membars to remove. There are two
7869 cases where intra-block analysis is enough:
7871 - a membar is redundant if it occurs between two consecutive I/O
7872 operations and if those operations are guaranteed to complete
7875 - a membar for a __builtin_read is redundant if the result is
7876 used before the next I/O operation is issued.
7878 If the last membar in the block could not be removed, and there
7879 are guaranteed to be no I/O operations between that membar and
7880 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7883 Describe the block's first I/O operation in *NEXT_IO. Describe
7884 an unknown operation if the block doesn't do any I/O. */
7887 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7890 HARD_REG_SET used_regs;
7891 rtx next_membar, set, insn;
7894 /* NEXT_IO is the next I/O operation to be performed after the current
7895 instruction. It starts off as being an unknown operation. */
7896 memset (next_io, 0, sizeof (*next_io));
7898 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7899 next_is_end_p = true;
7901 /* If the current instruction is a __builtin_read or __builtin_write,
7902 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7903 is null if the membar has already been deleted.
7905 Note that the initialization here should only be needed to
7906 suppress warnings. */
7909 /* USED_REGS is the set of registers that are used before the
7910 next I/O instruction. */
7911 CLEAR_HARD_REG_SET (used_regs);
7913 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7914 if (GET_CODE (insn) == CALL_INSN)
7916 /* We can't predict what a call will do to volatile memory. */
7917 memset (next_io, 0, sizeof (struct frv_io));
7918 next_is_end_p = false;
7919 CLEAR_HARD_REG_SET (used_regs);
7921 else if (INSN_P (insn))
7922 switch (recog_memoized (insn))
7924 case CODE_FOR_optional_membar_qi:
7925 case CODE_FOR_optional_membar_hi:
7926 case CODE_FOR_optional_membar_si:
7927 case CODE_FOR_optional_membar_di:
7931 /* Local information isn't enough to decide whether this
7932 membar is needed. Stash it away for later. */
7933 *last_membar = insn;
7934 frv_extract_membar (next_io, insn);
7935 next_is_end_p = false;
7939 /* Check whether the I/O operation before INSN could be
7940 reordered with one described by NEXT_IO. If it can't,
7941 INSN will not be needed. */
7942 struct frv_io prev_io;
7944 frv_extract_membar (&prev_io, insn);
7945 if (frv_io_fixed_order_p (&prev_io, next_io))
7949 ";; [Local] Removing membar %d since order"
7950 " of accesses is guaranteed\n",
7951 INSN_UID (next_membar));
7953 insn = NEXT_INSN (insn);
7954 delete_insn (next_membar);
7962 /* Invalidate NEXT_IO's address if it depends on something that
7963 is clobbered by INSN. */
7964 if (next_io->var_address)
7965 note_stores (PATTERN (insn), frv_io_check_address,
7966 &next_io->var_address);
7968 /* If the next membar is associated with a __builtin_read,
7969 see if INSN reads from that address. If it does, and if
7970 the destination register is used before the next I/O access,
7971 there is no need for the membar. */
7972 set = PATTERN (insn);
7973 if (next_io->type == FRV_IO_READ
7974 && next_io->var_address != 0
7976 && GET_CODE (set) == SET
7977 && GET_CODE (SET_DEST (set)) == REG
7978 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
7982 src = SET_SRC (set);
7983 if (GET_CODE (src) == ZERO_EXTEND)
7984 src = XEXP (src, 0);
7986 if (GET_CODE (src) == MEM
7987 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
7991 ";; [Local] Removing membar %d since the target"
7992 " of %d is used before the I/O operation\n",
7993 INSN_UID (next_membar), INSN_UID (insn));
7995 if (next_membar == *last_membar)
7998 delete_insn (next_membar);
8003 /* If INSN has volatile references, forget about any registers
8004 that are used after it. Otherwise forget about uses that
8005 are (or might be) defined by INSN. */
8006 if (volatile_refs_p (PATTERN (insn)))
8007 CLEAR_HARD_REG_SET (used_regs);
8009 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8011 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8016 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8017 FIRST_IO[X] describes the first operation performed by basic block X. */
8020 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8023 struct frv_io this_io, next_io;
8027 /* We need to keep the membar if there is an edge to the exit block. */
8028 FOR_EACH_EDGE (succ, ei, bb->succs)
8029 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8030 if (succ->dest == EXIT_BLOCK_PTR)
8033 /* Work out the union of all successor blocks. */
8034 ei = ei_start (bb->succs);
8035 ei_cond (ei, &succ);
8036 /* next_io = first_io[bb->succ->dest->index]; */
8037 next_io = first_io[succ->dest->index];
8038 ei = ei_start (bb->succs);
8039 if (ei_cond (ei, &succ))
8041 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8042 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8043 frv_io_union (&next_io, &first_io[succ->dest->index]);
8048 frv_extract_membar (&this_io, membar);
8049 if (frv_io_fixed_order_p (&this_io, &next_io))
8053 ";; [Global] Removing membar %d since order of accesses"
8054 " is guaranteed\n", INSN_UID (membar));
8056 delete_insn (membar);
8060 /* Remove redundant membars from the current function. */
8063 frv_optimize_membar (void)
8066 struct frv_io *first_io;
8069 compute_bb_for_insn ();
8070 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8071 last_membar = XCNEWVEC (rtx, last_basic_block);
8074 frv_optimize_membar_local (bb, &first_io[bb->index],
8075 &last_membar[bb->index]);
8078 if (last_membar[bb->index] != 0)
8079 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8085 /* Used by frv_reorg to keep track of the current packet's address. */
8086 static unsigned int frv_packet_address;
8088 /* If the current packet falls through to a label, try to pad the packet
8089 with nops in order to fit the label's alignment requirements. */
8092 frv_align_label (void)
8094 unsigned int alignment, target, nop;
8095 rtx x, last, barrier, label;
8097 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8098 maximum alignment of that packet, LABEL to the last label between
8099 the packets, and BARRIER to the last barrier. */
8100 last = frv_packet.insns[frv_packet.num_insns - 1];
8101 label = barrier = 0;
8103 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8107 unsigned int subalign = 1 << label_to_alignment (x);
8108 alignment = MAX (alignment, subalign);
8115 /* If -malign-labels, and the packet falls through to an unaligned
8116 label, try introducing a nop to align that label to 8 bytes. */
8117 if (TARGET_ALIGN_LABELS
8120 && frv_packet.num_insns < frv_packet.issue_rate)
8121 alignment = MAX (alignment, 8);
8123 /* Advance the address to the end of the current packet. */
8124 frv_packet_address += frv_packet.num_insns * 4;
8126 /* Work out the target address, after alignment. */
8127 target = (frv_packet_address + alignment - 1) & -alignment;
8129 /* If the packet falls through to the label, try to find an efficient
8130 padding sequence. */
8133 /* First try adding nops to the current packet. */
8134 for (nop = 0; nop < frv_num_nops; nop++)
8135 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8137 frv_insert_nop_in_packet (frv_nops[nop]);
8138 frv_packet_address += 4;
8141 /* If we still haven't reached the target, add some new packets that
8142 contain only nops. If there are two types of nop, insert an
8143 alternating sequence of frv_nops[0] and frv_nops[1], which will
8144 lead to packets like:
8151 etc. Just emit frv_nops[0] if that's the only nop we have. */
8152 last = frv_packet.insns[frv_packet.num_insns - 1];
8154 while (frv_packet_address < target)
8156 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8157 frv_packet_address += 4;
8158 if (frv_num_nops > 1)
8163 frv_packet_address = target;
8166 /* Subroutine of frv_reorg, called after each packet has been constructed
8170 frv_reorg_packet (void)
8172 frv_fill_unused_units (GROUP_I);
8173 frv_fill_unused_units (GROUP_FM);
8177 /* Add an instruction with pattern NOP to frv_nops[]. */
8180 frv_register_nop (rtx nop)
8182 nop = make_insn_raw (nop);
8183 NEXT_INSN (nop) = 0;
8184 PREV_INSN (nop) = 0;
8185 frv_nops[frv_num_nops++] = nop;
8188 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8189 into packets and check whether we need to insert nops in order to
8190 fulfill the processor's issue requirements. Also, if the user has
8191 requested a certain alignment for a label, try to meet that alignment
8192 by inserting nops in the previous packet. */
8197 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8198 frv_optimize_membar ();
8201 frv_register_nop (gen_nop ());
8203 frv_register_nop (gen_mnop ());
8204 if (TARGET_HARD_FLOAT)
8205 frv_register_nop (gen_fnop ());
8207 /* Estimate the length of each branch. Although this may change after
8208 we've inserted nops, it will only do so in big functions. */
8209 shorten_branches (get_insns ());
8211 frv_packet_address = 0;
8212 frv_for_each_packet (frv_reorg_packet);
8215 #define def_builtin(name, type, code) \
8216 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8218 struct builtin_description
8220 enum insn_code icode;
8222 enum frv_builtins code;
8223 enum rtx_code comparison;
8227 /* Media intrinsics that take a single, constant argument. */
8229 static struct builtin_description bdesc_set[] =
8231 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8234 /* Media intrinsics that take just one argument. */
8236 static struct builtin_description bdesc_1arg[] =
8238 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8239 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8240 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8241 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8242 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8243 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8246 /* Media intrinsics that take two arguments. */
8248 static struct builtin_description bdesc_2arg[] =
8250 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8251 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8252 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8253 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8254 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8255 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8256 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8257 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8258 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8259 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8260 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8261 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8262 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8263 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8264 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8265 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8266 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8267 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8268 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8269 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8270 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8271 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8272 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8273 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8274 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8275 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8276 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8279 /* Integer intrinsics that take two arguments and have no return value. */
8281 static struct builtin_description bdesc_int_void2arg[] =
8283 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8284 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8285 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8288 static struct builtin_description bdesc_prefetches[] =
8290 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8291 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8294 /* Media intrinsics that take two arguments, the first being an ACC number. */
8296 static struct builtin_description bdesc_cut[] =
8298 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8299 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8300 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8303 /* Two-argument media intrinsics with an immediate second argument. */
8305 static struct builtin_description bdesc_2argimm[] =
8307 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8308 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8309 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8310 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8311 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8312 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8313 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8314 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8315 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8316 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8317 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8318 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8319 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8320 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8321 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8322 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8323 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8326 /* Media intrinsics that take two arguments and return void, the first argument
8327 being a pointer to 4 words in memory. */
8329 static struct builtin_description bdesc_void2arg[] =
8331 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8332 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8335 /* Media intrinsics that take three arguments, the first being a const_int that
8336 denotes an accumulator, and that return void. */
8338 static struct builtin_description bdesc_void3arg[] =
8340 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8341 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8342 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8343 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8344 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8345 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8346 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8347 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8348 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8349 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8350 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8351 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8352 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8353 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8354 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8355 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8356 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8357 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8358 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8359 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8360 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8361 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8362 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8363 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8364 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8367 /* Media intrinsics that take two accumulator numbers as argument and
8370 static struct builtin_description bdesc_voidacc[] =
8372 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8373 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8374 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8375 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8376 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8377 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8380 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8381 a normal move and the ICODE is for the membar. */
8383 static struct builtin_description bdesc_loads[] =
8385 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8386 FRV_BUILTIN_READ8, 0, 0 },
8387 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8388 FRV_BUILTIN_READ16, 0, 0 },
8389 { CODE_FOR_optional_membar_si, "__builtin_read32",
8390 FRV_BUILTIN_READ32, 0, 0 },
8391 { CODE_FOR_optional_membar_di, "__builtin_read64",
8392 FRV_BUILTIN_READ64, 0, 0 }
8395 /* Likewise stores. */
8397 static struct builtin_description bdesc_stores[] =
8399 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8400 FRV_BUILTIN_WRITE8, 0, 0 },
8401 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8402 FRV_BUILTIN_WRITE16, 0, 0 },
8403 { CODE_FOR_optional_membar_si, "__builtin_write32",
8404 FRV_BUILTIN_WRITE32, 0, 0 },
8405 { CODE_FOR_optional_membar_di, "__builtin_write64",
8406 FRV_BUILTIN_WRITE64, 0, 0 },
8409 /* Initialize media builtins. */
8412 frv_init_builtins (void)
8414 tree endlink = void_list_node;
8415 tree accumulator = integer_type_node;
8416 tree integer = integer_type_node;
8417 tree voidt = void_type_node;
8418 tree uhalf = short_unsigned_type_node;
8419 tree sword1 = long_integer_type_node;
8420 tree uword1 = long_unsigned_type_node;
8421 tree sword2 = long_long_integer_type_node;
8422 tree uword2 = long_long_unsigned_type_node;
8423 tree uword4 = build_pointer_type (uword1);
8424 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8425 tree ubyte = unsigned_char_type_node;
8426 tree iacc = integer_type_node;
8428 #define UNARY(RET, T1) \
8429 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8431 #define BINARY(RET, T1, T2) \
8432 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8433 tree_cons (NULL_TREE, T2, endlink)))
8435 #define TRINARY(RET, T1, T2, T3) \
8436 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8437 tree_cons (NULL_TREE, T2, \
8438 tree_cons (NULL_TREE, T3, endlink))))
8440 #define QUAD(RET, T1, T2, T3, T4) \
8441 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8442 tree_cons (NULL_TREE, T2, \
8443 tree_cons (NULL_TREE, T3, \
8444 tree_cons (NULL_TREE, T4, endlink)))))
8446 tree void_ftype_void = build_function_type (voidt, endlink);
8448 tree void_ftype_acc = UNARY (voidt, accumulator);
8449 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8450 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8451 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8452 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8453 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8454 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8455 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8456 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8458 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8459 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8460 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8461 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8462 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8463 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8464 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8465 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8466 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8467 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8468 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8470 tree sw1_ftype_int = UNARY (sword1, integer);
8471 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8472 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8474 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8475 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8476 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8477 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8478 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8479 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8481 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8482 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8483 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8484 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8485 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8486 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8487 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8488 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8489 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8490 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8491 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8492 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8493 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8494 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8495 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8496 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8497 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8499 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8500 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8501 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8502 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8503 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8504 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8505 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8506 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8507 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8508 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8509 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8510 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8511 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8512 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8513 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8514 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8515 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8516 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8517 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8518 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8519 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8520 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8521 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8522 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8523 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8524 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8525 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8526 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8527 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8528 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8529 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8530 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8531 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8532 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8533 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8534 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8535 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8536 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8537 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8538 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8539 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8540 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8541 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8542 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8543 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8544 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8545 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8546 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8547 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8548 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8549 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8550 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8551 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8552 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8553 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8554 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8555 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8556 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8557 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8558 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8559 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8560 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8561 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8562 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8563 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8564 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8565 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8566 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8567 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8568 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8569 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8570 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8571 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8572 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8573 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8574 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8575 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8576 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8577 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8578 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8579 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8580 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8581 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8582 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8583 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8584 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8585 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8586 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8587 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8588 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8589 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8590 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8591 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8592 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8593 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8594 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8595 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8596 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8597 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8598 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8599 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8600 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8601 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8602 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8603 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8604 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8605 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8606 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8608 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8609 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8610 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8611 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8619 /* Set the names for various arithmetic operations according to the
8622 frv_init_libfuncs (void)
8624 set_optab_libfunc (smod_optab, SImode, "__modi");
8625 set_optab_libfunc (umod_optab, SImode, "__umodi");
8627 set_optab_libfunc (add_optab, DImode, "__addll");
8628 set_optab_libfunc (sub_optab, DImode, "__subll");
8629 set_optab_libfunc (smul_optab, DImode, "__mulll");
8630 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8631 set_optab_libfunc (smod_optab, DImode, "__modll");
8632 set_optab_libfunc (umod_optab, DImode, "__umodll");
8633 set_optab_libfunc (and_optab, DImode, "__andll");
8634 set_optab_libfunc (ior_optab, DImode, "__orll");
8635 set_optab_libfunc (xor_optab, DImode, "__xorll");
8636 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8638 set_optab_libfunc (add_optab, SFmode, "__addf");
8639 set_optab_libfunc (sub_optab, SFmode, "__subf");
8640 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8641 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8643 set_optab_libfunc (add_optab, DFmode, "__addd");
8644 set_optab_libfunc (sub_optab, DFmode, "__subd");
8645 set_optab_libfunc (smul_optab, DFmode, "__muld");
8646 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8648 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8649 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8651 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8652 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8653 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8654 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8656 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8657 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8658 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8659 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8661 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8662 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8663 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8664 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8667 /* Convert an integer constant to an accumulator register. ICODE is the
8668 code of the target instruction, OPNUM is the number of the
8669 accumulator operand and OPVAL is the constant integer. Try both
8670 ACC and ACCG registers; only report an error if neither fit the
8674 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8679 /* ACCs and ACCGs are implicit global registers if media intrinsics
8680 are being used. We set up this lazily to avoid creating lots of
8681 unnecessary call_insn rtl in non-media code. */
8682 for (i = 0; i <= ACC_MASK; i++)
8683 if ((i & ACC_MASK) == i)
8684 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8686 if (GET_CODE (opval) != CONST_INT)
8688 error ("accumulator is not a constant integer");
8691 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8693 error ("accumulator number is out of bounds");
8697 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8698 ACC_FIRST + INTVAL (opval));
8699 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8700 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8702 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8704 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8710 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8713 static enum machine_mode
8714 frv_matching_accg_mode (enum machine_mode mode)
8732 /* Given that a __builtin_read or __builtin_write function is accessing
8733 address ADDRESS, return the value that should be used as operand 1
8737 frv_io_address_cookie (rtx address)
8739 return (GET_CODE (address) == CONST_INT
8740 ? GEN_INT (INTVAL (address) / 8 * 8)
8744 /* Return the accumulator guard that should be paired with accumulator
8745 register ACC. The mode of the returned register is in the same
8746 class as ACC, but is four times smaller. */
8749 frv_matching_accg_for_acc (rtx acc)
8751 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8752 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8755 /* Read the requested argument from the call EXP given by INDEX.
8756 Return the value as an rtx. */
8759 frv_read_argument (tree exp, unsigned int index)
8761 return expand_expr (CALL_EXPR_ARG (exp, index),
8762 NULL_RTX, VOIDmode, 0);
8765 /* Like frv_read_argument, but interpret the argument as the number
8766 of an IACC register and return a (reg:MODE ...) rtx for it. */
8769 frv_read_iacc_argument (enum machine_mode mode, tree call,
8775 op = frv_read_argument (call, index);
8776 if (GET_CODE (op) != CONST_INT
8778 || INTVAL (op) > IACC_LAST - IACC_FIRST
8779 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8781 error ("invalid IACC argument");
8785 /* IACCs are implicit global registers. We set up this lazily to
8786 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8788 regno = INTVAL (op) + IACC_FIRST;
8789 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8790 global_regs[regno + i] = 1;
8792 return gen_rtx_REG (mode, regno);
8795 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8796 The instruction should require a constant operand of some sort. The
8797 function prints an error if OPVAL is not valid. */
8800 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8802 if (GET_CODE (opval) != CONST_INT)
8804 error ("%qs expects a constant argument", insn_data[icode].name);
8807 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8809 error ("constant argument out of range for %qs", insn_data[icode].name);
8815 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8816 if it's not null, has the right mode, and satisfies operand 0's
8820 frv_legitimize_target (enum insn_code icode, rtx target)
8822 enum machine_mode mode = insn_data[icode].operand[0].mode;
8825 || GET_MODE (target) != mode
8826 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8827 return gen_reg_rtx (mode);
8832 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8833 check whether ARG satisfies the operand's constraints. If it doesn't,
8834 copy ARG to a temporary register and return that. Otherwise return ARG
8838 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8840 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8842 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8845 return copy_to_mode_reg (mode, arg);
8848 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8851 frv_volatile_memref (enum machine_mode mode, rtx arg)
8855 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8856 MEM_VOLATILE_P (mem) = 1;
8860 /* Expand builtins that take a single, constant argument. At the moment,
8861 only MHDSETS falls into this category. */
8864 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8867 rtx op0 = frv_read_argument (call, 0);
8869 if (! frv_check_constant_argument (icode, 1, op0))
8872 target = frv_legitimize_target (icode, target);
8873 pat = GEN_FCN (icode) (target, op0);
8881 /* Expand builtins that take one operand. */
8884 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8887 rtx op0 = frv_read_argument (call, 0);
8889 target = frv_legitimize_target (icode, target);
8890 op0 = frv_legitimize_argument (icode, 1, op0);
8891 pat = GEN_FCN (icode) (target, op0);
8899 /* Expand builtins that take two operands. */
8902 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8905 rtx op0 = frv_read_argument (call, 0);
8906 rtx op1 = frv_read_argument (call, 1);
8908 target = frv_legitimize_target (icode, target);
8909 op0 = frv_legitimize_argument (icode, 1, op0);
8910 op1 = frv_legitimize_argument (icode, 2, op1);
8911 pat = GEN_FCN (icode) (target, op0, op1);
8919 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8923 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8926 rtx op0 = frv_read_argument (call, 0);
8927 rtx op1 = frv_read_argument (call, 1);
8930 target = frv_legitimize_target (icode, target);
8931 op0 = frv_int_to_acc (icode, 1, op0);
8935 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8937 if (! frv_check_constant_argument (icode, 2, op1))
8941 op1 = frv_legitimize_argument (icode, 2, op1);
8943 op2 = frv_matching_accg_for_acc (op0);
8944 pat = GEN_FCN (icode) (target, op0, op1, op2);
8952 /* Expand builtins that take two operands and the second is immediate. */
8955 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8958 rtx op0 = frv_read_argument (call, 0);
8959 rtx op1 = frv_read_argument (call, 1);
8961 if (! frv_check_constant_argument (icode, 2, op1))
8964 target = frv_legitimize_target (icode, target);
8965 op0 = frv_legitimize_argument (icode, 1, op0);
8966 pat = GEN_FCN (icode) (target, op0, op1);
8974 /* Expand builtins that take two operands, the first operand being a pointer to
8975 ints and return void. */
8978 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
8981 rtx op0 = frv_read_argument (call, 0);
8982 rtx op1 = frv_read_argument (call, 1);
8983 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8986 if (GET_CODE (op0) != MEM)
8990 if (! offsettable_address_p (0, mode0, op0))
8992 reg = gen_reg_rtx (Pmode);
8993 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
8996 op0 = gen_rtx_MEM (SImode, reg);
8999 addr = XEXP (op0, 0);
9000 if (! offsettable_address_p (0, mode0, addr))
9001 addr = copy_to_mode_reg (Pmode, op0);
9003 op0 = change_address (op0, V4SImode, addr);
9004 op1 = frv_legitimize_argument (icode, 1, op1);
9005 pat = GEN_FCN (icode) (op0, op1);
9013 /* Expand builtins that take two long operands and return void. */
9016 frv_expand_int_void2arg (enum insn_code icode, tree call)
9019 rtx op0 = frv_read_argument (call, 0);
9020 rtx op1 = frv_read_argument (call, 1);
9022 op0 = frv_legitimize_argument (icode, 1, op0);
9023 op1 = frv_legitimize_argument (icode, 1, op1);
9024 pat = GEN_FCN (icode) (op0, op1);
9032 /* Expand prefetch builtins. These take a single address as argument. */
9035 frv_expand_prefetches (enum insn_code icode, tree call)
9038 rtx op0 = frv_read_argument (call, 0);
9040 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9048 /* Expand builtins that take three operands and return void. The first
9049 argument must be a constant that describes a pair or quad accumulators. A
9050 fourth argument is created that is the accumulator guard register that
9051 corresponds to the accumulator. */
9054 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9057 rtx op0 = frv_read_argument (call, 0);
9058 rtx op1 = frv_read_argument (call, 1);
9059 rtx op2 = frv_read_argument (call, 2);
9062 op0 = frv_int_to_acc (icode, 0, op0);
9066 op1 = frv_legitimize_argument (icode, 1, op1);
9067 op2 = frv_legitimize_argument (icode, 2, op2);
9068 op3 = frv_matching_accg_for_acc (op0);
9069 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9077 /* Expand builtins that perform accumulator-to-accumulator operations.
9078 These builtins take two accumulator numbers as argument and return
9082 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9085 rtx op0 = frv_read_argument (call, 0);
9086 rtx op1 = frv_read_argument (call, 1);
9090 op0 = frv_int_to_acc (icode, 0, op0);
9094 op1 = frv_int_to_acc (icode, 1, op1);
9098 op2 = frv_matching_accg_for_acc (op0);
9099 op3 = frv_matching_accg_for_acc (op1);
9100 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9108 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9109 membar and TARGET_MODE is the mode that the loaded value should have. */
9112 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9113 tree call, rtx target)
9115 rtx op0 = frv_read_argument (call, 0);
9116 rtx cookie = frv_io_address_cookie (op0);
9118 if (target == 0 || !REG_P (target))
9119 target = gen_reg_rtx (target_mode);
9120 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9121 convert_move (target, op0, 1);
9122 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9123 cfun->machine->has_membar_p = 1;
9127 /* Likewise __builtin_write* functions. */
9130 frv_expand_store_builtin (enum insn_code icode, tree call)
9132 rtx op0 = frv_read_argument (call, 0);
9133 rtx op1 = frv_read_argument (call, 1);
9134 rtx cookie = frv_io_address_cookie (op0);
9136 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9137 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9138 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9139 cfun->machine->has_membar_p = 1;
9143 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9144 each argument forms one word of the two double-word input registers.
9145 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9146 to put the return value. */
9149 frv_expand_mdpackh_builtin (tree call, rtx target)
9151 enum insn_code icode = CODE_FOR_mdpackh;
9153 rtx arg1 = frv_read_argument (call, 0);
9154 rtx arg2 = frv_read_argument (call, 1);
9155 rtx arg3 = frv_read_argument (call, 2);
9156 rtx arg4 = frv_read_argument (call, 3);
9158 target = frv_legitimize_target (icode, target);
9159 op0 = gen_reg_rtx (DImode);
9160 op1 = gen_reg_rtx (DImode);
9162 /* The high half of each word is not explicitly initialized, so indicate
9163 that the input operands are not live before this point. */
9167 /* Move each argument into the low half of its associated input word. */
9168 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9169 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9170 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9171 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9173 pat = GEN_FCN (icode) (target, op0, op1);
9181 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9182 number as argument. */
9185 frv_expand_mclracc_builtin (tree call)
9187 enum insn_code icode = CODE_FOR_mclracc;
9189 rtx op0 = frv_read_argument (call, 0);
9191 op0 = frv_int_to_acc (icode, 0, op0);
9195 pat = GEN_FCN (icode) (op0);
9202 /* Expand builtins that take no arguments. */
9205 frv_expand_noargs_builtin (enum insn_code icode)
9207 rtx pat = GEN_FCN (icode) (const0_rtx);
9214 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9215 number or accumulator guard number as argument and return an SI integer. */
9218 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9221 rtx target = gen_reg_rtx (SImode);
9222 rtx op0 = frv_read_argument (call, 0);
9224 op0 = frv_int_to_acc (icode, 1, op0);
9228 pat = GEN_FCN (icode) (target, op0);
9236 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9237 accumulator guard as their first argument and an SImode value as their
9241 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9244 rtx op0 = frv_read_argument (call, 0);
9245 rtx op1 = frv_read_argument (call, 1);
9247 op0 = frv_int_to_acc (icode, 0, op0);
9251 op1 = frv_legitimize_argument (icode, 1, op1);
9252 pat = GEN_FCN (icode) (op0, op1);
9259 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9260 to move DImode values into and out of IACC0. */
9263 frv_split_iacc_move (rtx dest, rtx src)
9265 enum machine_mode inner;
9268 inner = GET_MODE (dest);
9269 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9270 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9271 simplify_gen_subreg (SImode, src, inner, i));
9274 /* Expand builtins. */
9277 frv_expand_builtin (tree exp,
9279 rtx subtarget ATTRIBUTE_UNUSED,
9280 enum machine_mode mode ATTRIBUTE_UNUSED,
9281 int ignore ATTRIBUTE_UNUSED)
9283 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9284 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9286 struct builtin_description *d;
9288 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9290 error ("media functions are not available unless -mmedia is used");
9296 case FRV_BUILTIN_MCOP1:
9297 case FRV_BUILTIN_MCOP2:
9298 case FRV_BUILTIN_MDUNPACKH:
9299 case FRV_BUILTIN_MBTOHE:
9300 if (! TARGET_MEDIA_REV1)
9302 error ("this media function is only available on the fr500");
9307 case FRV_BUILTIN_MQXMACHS:
9308 case FRV_BUILTIN_MQXMACXHS:
9309 case FRV_BUILTIN_MQMACXHS:
9310 case FRV_BUILTIN_MADDACCS:
9311 case FRV_BUILTIN_MSUBACCS:
9312 case FRV_BUILTIN_MASACCS:
9313 case FRV_BUILTIN_MDADDACCS:
9314 case FRV_BUILTIN_MDSUBACCS:
9315 case FRV_BUILTIN_MDASACCS:
9316 case FRV_BUILTIN_MABSHS:
9317 case FRV_BUILTIN_MDROTLI:
9318 case FRV_BUILTIN_MCPLHI:
9319 case FRV_BUILTIN_MCPLI:
9320 case FRV_BUILTIN_MDCUTSSI:
9321 case FRV_BUILTIN_MQSATHS:
9322 case FRV_BUILTIN_MHSETLOS:
9323 case FRV_BUILTIN_MHSETLOH:
9324 case FRV_BUILTIN_MHSETHIS:
9325 case FRV_BUILTIN_MHSETHIH:
9326 case FRV_BUILTIN_MHDSETS:
9327 case FRV_BUILTIN_MHDSETH:
9328 if (! TARGET_MEDIA_REV2)
9330 error ("this media function is only available on the fr400"
9336 case FRV_BUILTIN_SMASS:
9337 case FRV_BUILTIN_SMSSS:
9338 case FRV_BUILTIN_SMU:
9339 case FRV_BUILTIN_ADDSS:
9340 case FRV_BUILTIN_SUBSS:
9341 case FRV_BUILTIN_SLASS:
9342 case FRV_BUILTIN_SCUTSS:
9343 case FRV_BUILTIN_IACCreadll:
9344 case FRV_BUILTIN_IACCreadl:
9345 case FRV_BUILTIN_IACCsetll:
9346 case FRV_BUILTIN_IACCsetl:
9347 if (!TARGET_FR405_BUILTINS)
9349 error ("this builtin function is only available"
9350 " on the fr405 and fr450");
9355 case FRV_BUILTIN_PREFETCH:
9356 if (!TARGET_FR500_FR550_BUILTINS)
9358 error ("this builtin function is only available on the fr500"
9364 case FRV_BUILTIN_MQLCLRHS:
9365 case FRV_BUILTIN_MQLMTHS:
9366 case FRV_BUILTIN_MQSLLHI:
9367 case FRV_BUILTIN_MQSRAHI:
9368 if (!TARGET_MEDIA_FR450)
9370 error ("this builtin function is only available on the fr450");
9379 /* Expand unique builtins. */
9383 case FRV_BUILTIN_MTRAP:
9384 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9386 case FRV_BUILTIN_MCLRACC:
9387 return frv_expand_mclracc_builtin (exp);
9389 case FRV_BUILTIN_MCLRACCA:
9391 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9393 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9395 case FRV_BUILTIN_MRDACC:
9396 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9398 case FRV_BUILTIN_MRDACCG:
9399 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9401 case FRV_BUILTIN_MWTACC:
9402 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9404 case FRV_BUILTIN_MWTACCG:
9405 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9407 case FRV_BUILTIN_MDPACKH:
9408 return frv_expand_mdpackh_builtin (exp, target);
9410 case FRV_BUILTIN_IACCreadll:
9412 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9413 if (target == 0 || !REG_P (target))
9414 target = gen_reg_rtx (DImode);
9415 frv_split_iacc_move (target, src);
9419 case FRV_BUILTIN_IACCreadl:
9420 return frv_read_iacc_argument (SImode, exp, 0);
9422 case FRV_BUILTIN_IACCsetll:
9424 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9425 rtx src = frv_read_argument (exp, 1);
9426 frv_split_iacc_move (dest, force_reg (DImode, src));
9430 case FRV_BUILTIN_IACCsetl:
9432 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9433 rtx src = frv_read_argument (exp, 1);
9434 emit_move_insn (dest, force_reg (SImode, src));
9442 /* Expand groups of builtins. */
9444 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9445 if (d->code == fcode)
9446 return frv_expand_set_builtin (d->icode, exp, target);
9448 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9449 if (d->code == fcode)
9450 return frv_expand_unop_builtin (d->icode, exp, target);
9452 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9453 if (d->code == fcode)
9454 return frv_expand_binop_builtin (d->icode, exp, target);
9456 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9457 if (d->code == fcode)
9458 return frv_expand_cut_builtin (d->icode, exp, target);
9460 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9461 if (d->code == fcode)
9462 return frv_expand_binopimm_builtin (d->icode, exp, target);
9464 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9465 if (d->code == fcode)
9466 return frv_expand_voidbinop_builtin (d->icode, exp);
9468 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9469 if (d->code == fcode)
9470 return frv_expand_voidtriop_builtin (d->icode, exp);
9472 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9473 if (d->code == fcode)
9474 return frv_expand_voidaccop_builtin (d->icode, exp);
9476 for (i = 0, d = bdesc_int_void2arg;
9477 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9478 if (d->code == fcode)
9479 return frv_expand_int_void2arg (d->icode, exp);
9481 for (i = 0, d = bdesc_prefetches;
9482 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9483 if (d->code == fcode)
9484 return frv_expand_prefetches (d->icode, exp);
9486 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9487 if (d->code == fcode)
9488 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9491 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9492 if (d->code == fcode)
9493 return frv_expand_store_builtin (d->icode, exp);
9499 frv_in_small_data_p (const_tree decl)
9502 const_tree section_name;
9504 /* Don't apply the -G flag to internal compiler structures. We
9505 should leave such structures in the main data section, partly
9506 for efficiency and partly because the size of some of them
9507 (such as C++ typeinfos) is not known until later. */
9508 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9511 /* If we already know which section the decl should be in, see if
9512 it's a small data section. */
9513 section_name = DECL_SECTION_NAME (decl);
9516 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9517 if (frv_string_begins_with (section_name, ".sdata"))
9519 if (frv_string_begins_with (section_name, ".sbss"))
9524 size = int_size_in_bytes (TREE_TYPE (decl));
9525 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9532 frv_rtx_costs (rtx x,
9533 int code ATTRIBUTE_UNUSED,
9534 int outer_code ATTRIBUTE_UNUSED,
9536 bool speed ATTRIBUTE_UNUSED)
9538 if (outer_code == MEM)
9540 /* Don't differentiate between memory addresses. All the ones
9541 we accept have equal cost. */
9542 *total = COSTS_N_INSNS (0);
9549 /* Make 12-bit integers really cheap. */
9550 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9561 *total = COSTS_N_INSNS (2);
9575 if (GET_MODE (x) == SImode)
9576 *total = COSTS_N_INSNS (1);
9577 else if (GET_MODE (x) == DImode)
9578 *total = COSTS_N_INSNS (2);
9580 *total = COSTS_N_INSNS (3);
9584 if (GET_MODE (x) == SImode)
9585 *total = COSTS_N_INSNS (2);
9587 *total = COSTS_N_INSNS (6); /* guess */
9594 *total = COSTS_N_INSNS (18);
9598 *total = COSTS_N_INSNS (3);
9607 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9609 switch_to_section (ctors_section);
9610 assemble_align (POINTER_SIZE);
9613 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9618 assemble_integer_with_op ("\t.picptr\t", symbol);
9622 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9624 switch_to_section (dtors_section);
9625 assemble_align (POINTER_SIZE);
9628 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9633 assemble_integer_with_op ("\t.picptr\t", symbol);
9636 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9639 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9640 int incoming ATTRIBUTE_UNUSED)
9642 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9645 #define TLS_BIAS (2048 - 16)
9647 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9648 We need to emit DTP-relative relocations. */
9651 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9653 gcc_assert (size == 4);
9654 fputs ("\t.picptr\ttlsmoff(", file);
9655 /* We want the unbiased TLS offset, so add the bias to the
9656 expression, such that the implicit biasing cancels out. */
9657 output_addr_const (file, plus_constant (x, TLS_BIAS));