1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
268 static int frv_default_flags_for_cpu (void);
269 static int frv_string_begins_with (const_tree, const char *);
270 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
271 static void frv_print_operand (FILE *, rtx, int);
272 static void frv_print_operand_address (FILE *, rtx);
273 static bool frv_print_operand_punct_valid_p (unsigned char code);
274 static void frv_print_operand_memory_reference_reg
276 static void frv_print_operand_memory_reference (FILE *, rtx, int);
277 static int frv_print_operand_jump_hint (rtx);
278 static const char *comparison_string (enum rtx_code, rtx);
279 static rtx frv_function_value (const_tree, const_tree,
281 static rtx frv_libcall_value (enum machine_mode,
283 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
284 static rtx single_set_pattern (rtx);
285 static int frv_function_contains_far_jump (void);
286 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
290 static rtx frv_frame_offset_rtx (int);
291 static rtx frv_frame_mem (enum machine_mode, rtx, int);
292 static rtx frv_dwarf_store (rtx, int);
293 static void frv_frame_insn (rtx, rtx);
294 static void frv_frame_access (frv_frame_accessor_t*,
296 static void frv_frame_access_multi (frv_frame_accessor_t*,
298 static void frv_frame_access_standard_regs (enum frv_stack_op,
300 static struct machine_function *frv_init_machine_status (void);
301 static rtx frv_int_to_acc (enum insn_code, int, rtx);
302 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
303 static rtx frv_read_argument (tree, unsigned int);
304 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
305 static int frv_check_constant_argument (enum insn_code, int, rtx);
306 static rtx frv_legitimize_target (enum insn_code, rtx);
307 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
308 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
309 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
310 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
312 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
313 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
314 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
315 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
316 static rtx frv_expand_int_void2arg (enum insn_code, tree);
317 static rtx frv_expand_prefetches (enum insn_code, tree);
318 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
319 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
320 static rtx frv_expand_mclracc_builtin (tree);
321 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
322 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
323 static rtx frv_expand_noargs_builtin (enum insn_code);
324 static void frv_split_iacc_move (rtx, rtx);
325 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
326 static int frv_clear_registers_used (rtx *, void *);
327 static void frv_ifcvt_add_insn (rtx, rtx, int);
328 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
329 static rtx frv_ifcvt_load_value (rtx, rtx);
330 static int frv_acc_group_1 (rtx *, void *);
331 static unsigned int frv_insn_unit (rtx);
332 static bool frv_issues_to_branch_unit_p (rtx);
333 static int frv_cond_flags (rtx);
334 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
335 static int frv_registers_conflict_p_1 (rtx *, void *);
336 static bool frv_registers_conflict_p (rtx);
337 static void frv_registers_update_1 (rtx, const_rtx, void *);
338 static void frv_registers_update (rtx);
339 static void frv_start_packet (void);
340 static void frv_start_packet_block (void);
341 static void frv_finish_packet (void (*) (void));
342 static bool frv_pack_insn_p (rtx);
343 static void frv_add_insn_to_packet (rtx);
344 static void frv_insert_nop_in_packet (rtx);
345 static bool frv_for_each_packet (void (*) (void));
346 static bool frv_sort_insn_group_1 (enum frv_insn_group,
347 unsigned int, unsigned int,
348 unsigned int, unsigned int,
350 static int frv_compare_insns (const void *, const void *);
351 static void frv_sort_insn_group (enum frv_insn_group);
352 static void frv_reorder_packet (void);
353 static void frv_fill_unused_units (enum frv_insn_group);
354 static void frv_align_label (void);
355 static void frv_reorg_packet (void);
356 static void frv_register_nop (rtx);
357 static void frv_reorg (void);
358 static void frv_pack_insns (void);
359 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
360 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
361 static bool frv_assemble_integer (rtx, unsigned, int);
362 static void frv_init_builtins (void);
363 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
364 static void frv_init_libfuncs (void);
365 static bool frv_in_small_data_p (const_tree);
366 static void frv_asm_output_mi_thunk
367 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
368 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
371 static rtx frv_expand_builtin_saveregs (void);
372 static void frv_expand_builtin_va_start (tree, rtx);
373 static bool frv_rtx_costs (rtx, int, int, int*, bool);
374 static int frv_register_move_cost (enum machine_mode,
375 reg_class_t, reg_class_t);
376 static int frv_memory_move_cost (enum machine_mode,
378 static void frv_asm_out_constructor (rtx, int);
379 static void frv_asm_out_destructor (rtx, int);
380 static bool frv_function_symbol_referenced_p (rtx);
381 static bool frv_cannot_force_const_mem (rtx);
382 static const char *unspec_got_name (int);
383 static void frv_output_const_unspec (FILE *,
384 const struct frv_unspec *);
385 static bool frv_function_ok_for_sibcall (tree, tree);
386 static rtx frv_struct_value_rtx (tree, int);
387 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
388 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
390 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
392 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
394 secondary_reload_info *);
395 static bool frv_frame_pointer_required (void);
396 static bool frv_can_eliminate (const int, const int);
397 static void frv_trampoline_init (rtx, tree, rtx);
398 static bool frv_class_likely_spilled_p (reg_class_t);
400 /* Allow us to easily change the default for -malloc-cc. */
401 #ifndef DEFAULT_NO_ALLOC_CC
402 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
404 #define MASK_DEFAULT_ALLOC_CC 0
407 /* Initialize the GCC target structure. */
408 #undef TARGET_PRINT_OPERAND
409 #define TARGET_PRINT_OPERAND frv_print_operand
410 #undef TARGET_PRINT_OPERAND_ADDRESS
411 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
412 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
413 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
414 #undef TARGET_ASM_FUNCTION_PROLOGUE
415 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
416 #undef TARGET_ASM_FUNCTION_EPILOGUE
417 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
418 #undef TARGET_ASM_INTEGER
419 #define TARGET_ASM_INTEGER frv_assemble_integer
420 #undef TARGET_DEFAULT_TARGET_FLAGS
421 #define TARGET_DEFAULT_TARGET_FLAGS \
422 (MASK_DEFAULT_ALLOC_CC \
429 #undef TARGET_HANDLE_OPTION
430 #define TARGET_HANDLE_OPTION frv_handle_option
431 #undef TARGET_INIT_BUILTINS
432 #define TARGET_INIT_BUILTINS frv_init_builtins
433 #undef TARGET_EXPAND_BUILTIN
434 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
435 #undef TARGET_INIT_LIBFUNCS
436 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
437 #undef TARGET_IN_SMALL_DATA_P
438 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
439 #undef TARGET_REGISTER_MOVE_COST
440 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
441 #undef TARGET_MEMORY_MOVE_COST
442 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
443 #undef TARGET_RTX_COSTS
444 #define TARGET_RTX_COSTS frv_rtx_costs
445 #undef TARGET_ASM_CONSTRUCTOR
446 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
447 #undef TARGET_ASM_DESTRUCTOR
448 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
450 #undef TARGET_ASM_OUTPUT_MI_THUNK
451 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
452 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
453 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
455 #undef TARGET_SCHED_ISSUE_RATE
456 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
458 #undef TARGET_LEGITIMIZE_ADDRESS
459 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
461 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
462 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
463 #undef TARGET_CANNOT_FORCE_CONST_MEM
464 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
466 #undef TARGET_HAVE_TLS
467 #define TARGET_HAVE_TLS HAVE_AS_TLS
469 #undef TARGET_STRUCT_VALUE_RTX
470 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
471 #undef TARGET_MUST_PASS_IN_STACK
472 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
473 #undef TARGET_PASS_BY_REFERENCE
474 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
475 #undef TARGET_ARG_PARTIAL_BYTES
476 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
478 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
479 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
480 #undef TARGET_SETUP_INCOMING_VARARGS
481 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
482 #undef TARGET_MACHINE_DEPENDENT_REORG
483 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
485 #undef TARGET_EXPAND_BUILTIN_VA_START
486 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
489 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
490 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
493 #undef TARGET_CLASS_LIKELY_SPILLED_P
494 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
496 #undef TARGET_SECONDARY_RELOAD
497 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
499 #undef TARGET_LEGITIMATE_ADDRESS_P
500 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
502 #undef TARGET_FRAME_POINTER_REQUIRED
503 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
505 #undef TARGET_CAN_ELIMINATE
506 #define TARGET_CAN_ELIMINATE frv_can_eliminate
508 #undef TARGET_TRAMPOLINE_INIT
509 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
511 #undef TARGET_FUNCTION_VALUE
512 #define TARGET_FUNCTION_VALUE frv_function_value
513 #undef TARGET_LIBCALL_VALUE
514 #define TARGET_LIBCALL_VALUE frv_libcall_value
516 struct gcc_target targetm = TARGET_INITIALIZER;
518 #define FRV_SYMBOL_REF_TLS_P(RTX) \
519 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
522 /* Any function call that satisfies the machine-independent
523 requirements is eligible on FR-V. */
526 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
527 tree exp ATTRIBUTE_UNUSED)
532 /* Return true if SYMBOL is a small data symbol and relocation RELOC
533 can be used to access it directly in a load or store. */
535 static FRV_INLINE bool
536 frv_small_data_reloc_p (rtx symbol, int reloc)
538 return (GET_CODE (symbol) == SYMBOL_REF
539 && SYMBOL_REF_SMALL_P (symbol)
540 && (!TARGET_FDPIC || flag_pic == 1)
541 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
544 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
548 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
550 if (GET_CODE (x) == CONST)
554 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
556 unspec->offset += INTVAL (XEXP (x, 1));
559 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
561 unspec->symbol = XVECEXP (x, 0, 0);
562 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
564 if (unspec->offset == 0)
567 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
568 && unspec->offset > 0
569 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
576 /* Decide whether we can force certain constants to memory. If we
577 decide we can't, the caller should be able to cope with it in
580 We never allow constants to be forced into memory for TARGET_FDPIC.
581 This is necessary for several reasons:
583 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
584 target-independent code will try to force them into the constant
585 pool, thus leading to infinite recursion.
587 2. We can never introduce new constant pool references during reload.
588 Any such reference would require use of the pseudo FDPIC register.
590 3. We can't represent a constant added to a function pointer (which is
591 not the same as a pointer to a function+constant).
593 4. In many cases, it's more efficient to calculate the constant in-line. */
596 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
601 /* Implement TARGET_HANDLE_OPTION. */
604 frv_handle_option (size_t code, const char *arg, int value)
609 g_switch_value = value;
614 if (strcmp (arg, "simple") == 0)
615 frv_cpu_type = FRV_CPU_SIMPLE;
616 else if (strcmp (arg, "tomcat") == 0)
617 frv_cpu_type = FRV_CPU_TOMCAT;
618 else if (strcmp (arg, "fr550") == 0)
619 frv_cpu_type = FRV_CPU_FR550;
620 else if (strcmp (arg, "fr500") == 0)
621 frv_cpu_type = FRV_CPU_FR500;
622 else if (strcmp (arg, "fr450") == 0)
623 frv_cpu_type = FRV_CPU_FR450;
624 else if (strcmp (arg, "fr405") == 0)
625 frv_cpu_type = FRV_CPU_FR405;
626 else if (strcmp (arg, "fr400") == 0)
627 frv_cpu_type = FRV_CPU_FR400;
628 else if (strcmp (arg, "fr300") == 0)
629 frv_cpu_type = FRV_CPU_FR300;
630 else if (strcmp (arg, "frv") == 0)
631 frv_cpu_type = FRV_CPU_GENERIC;
642 frv_default_flags_for_cpu (void)
644 switch (frv_cpu_type)
646 case FRV_CPU_GENERIC:
647 return MASK_DEFAULT_FRV;
650 return MASK_DEFAULT_FR550;
654 return MASK_DEFAULT_FR500;
657 return MASK_DEFAULT_FR450;
661 return MASK_DEFAULT_FR400;
665 return MASK_DEFAULT_SIMPLE;
672 /* Sometimes certain combinations of command options do not make
673 sense on a particular target machine. You can define a macro
674 `OVERRIDE_OPTIONS' to take account of this. This macro, if
675 defined, is executed once just after all the command options have
678 Don't use this macro to turn on various extra optimizations for
679 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
682 frv_override_options (void)
687 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
689 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
690 linker about linking pic and non-pic code. */
693 if (!flag_pic) /* -fPIC */
696 if (! g_switch_set) /* -G0 */
703 /* A C expression whose value is a register class containing hard
704 register REGNO. In general there is more than one such class;
705 choose a class which is "minimal", meaning that no smaller class
706 also contains the register. */
708 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
710 enum reg_class rclass;
714 int gpr_reg = regno - GPR_FIRST;
716 if (gpr_reg == GR8_REG)
719 else if (gpr_reg == GR9_REG)
722 else if (gpr_reg == GR14_REG)
723 rclass = FDPIC_FPTR_REGS;
725 else if (gpr_reg == FDPIC_REGNO)
728 else if ((gpr_reg & 3) == 0)
731 else if ((gpr_reg & 1) == 0)
738 else if (FPR_P (regno))
740 int fpr_reg = regno - GPR_FIRST;
741 if ((fpr_reg & 3) == 0)
742 rclass = QUAD_FPR_REGS;
744 else if ((fpr_reg & 1) == 0)
751 else if (regno == LR_REGNO)
754 else if (regno == LCR_REGNO)
757 else if (ICC_P (regno))
760 else if (FCC_P (regno))
763 else if (ICR_P (regno))
766 else if (FCR_P (regno))
769 else if (ACC_P (regno))
771 int r = regno - ACC_FIRST;
773 rclass = QUAD_ACC_REGS;
774 else if ((r & 1) == 0)
775 rclass = EVEN_ACC_REGS;
780 else if (ACCG_P (regno))
786 regno_reg_class[regno] = rclass;
789 /* Check for small data option */
791 g_switch_value = SDATA_DEFAULT_SIZE;
793 /* A C expression which defines the machine-dependent operand
794 constraint letters for register classes. If CHAR is such a
795 letter, the value should be the register class corresponding to
796 it. Otherwise, the value should be `NO_REGS'. The register
797 letter `r', corresponding to class `GENERAL_REGS', will not be
798 passed to this macro; you do not need to handle it.
800 The following letters are unavailable, due to being used as
805 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
806 'Q', 'R', 'S', 'T', 'U'
808 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
810 for (i = 0; i < 256; i++)
811 reg_class_from_letter[i] = NO_REGS;
813 reg_class_from_letter['a'] = ACC_REGS;
814 reg_class_from_letter['b'] = EVEN_ACC_REGS;
815 reg_class_from_letter['c'] = CC_REGS;
816 reg_class_from_letter['d'] = GPR_REGS;
817 reg_class_from_letter['e'] = EVEN_REGS;
818 reg_class_from_letter['f'] = FPR_REGS;
819 reg_class_from_letter['h'] = FEVEN_REGS;
820 reg_class_from_letter['l'] = LR_REG;
821 reg_class_from_letter['q'] = QUAD_REGS;
822 reg_class_from_letter['t'] = ICC_REGS;
823 reg_class_from_letter['u'] = FCC_REGS;
824 reg_class_from_letter['v'] = ICR_REGS;
825 reg_class_from_letter['w'] = FCR_REGS;
826 reg_class_from_letter['x'] = QUAD_FPR_REGS;
827 reg_class_from_letter['y'] = LCR_REG;
828 reg_class_from_letter['z'] = SPR_REGS;
829 reg_class_from_letter['A'] = QUAD_ACC_REGS;
830 reg_class_from_letter['B'] = ACCG_REGS;
831 reg_class_from_letter['C'] = CR_REGS;
832 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
833 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
835 /* There is no single unaligned SI op for PIC code. Sometimes we
836 need to use ".4byte" and sometimes we need to use ".picptr".
837 See frv_assemble_integer for details. */
838 if (flag_pic || TARGET_FDPIC)
839 targetm.asm_out.unaligned_op.si = 0;
841 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
842 target_flags |= MASK_LINKED_FP;
844 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
845 target_flags |= MASK_OPTIMIZE_MEMBAR;
847 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
848 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
850 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
851 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
853 init_machine_status = frv_init_machine_status;
857 /* Some machines may desire to change what optimizations are performed for
858 various optimization levels. This macro, if defined, is executed once just
859 after the optimization level is determined and before the remainder of the
860 command options have been parsed. Values set in this macro are used as the
861 default values for the other command line options.
863 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
864 `-O' is specified, and 0 if neither is specified.
866 SIZE is nonzero if `-Os' is specified, 0 otherwise.
868 You should not use this macro to change options that are not
869 machine-specific. These should uniformly selected by the same optimization
870 level on all supported machines. Use this macro to enable machine-specific
873 *Do not examine `write_symbols' in this macro!* The debugging options are
874 *not supposed to alter the generated code. */
876 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
877 scheduling pass at the current time. */
879 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
883 #ifdef DISABLE_SCHED2
884 flag_schedule_insns_after_reload = 0;
893 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
896 frv_string_begins_with (const_tree name, const char *prefix)
898 const int prefix_len = strlen (prefix);
900 /* Remember: NAME's length includes the null terminator. */
901 return (TREE_STRING_LENGTH (name) > prefix_len
902 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
905 /* Zero or more C statements that may conditionally modify two variables
906 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
907 been initialized from the two preceding macros.
909 This is necessary in case the fixed or call-clobbered registers depend on
912 You need not define this macro if it has no work to do.
914 If the usage of an entire class of registers depends on the target flags,
915 you may indicate this to GCC by using this macro to modify `fixed_regs' and
916 `call_used_regs' to 1 for each of the registers in the classes which should
917 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
918 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
920 (However, if this class is not included in `GENERAL_REGS' and all of the
921 insn patterns whose constraints permit this class are controlled by target
922 switches, then GCC will automatically avoid using these registers when the
923 target switches are opposed to them.) */
926 frv_conditional_register_usage (void)
930 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
931 fixed_regs[i] = call_used_regs[i] = 1;
933 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
934 fixed_regs[i] = call_used_regs[i] = 1;
936 /* Reserve the registers used for conditional execution. At present, we need
937 1 ICC and 1 ICR register. */
938 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
939 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
943 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
944 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
945 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
946 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
950 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
951 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
954 /* If -fpic, SDA_BASE_REG is the PIC register. */
955 if (g_switch_value == 0 && !flag_pic)
956 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
959 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
965 * Compute the stack frame layout
968 * +---------------+-----------------------+-----------------------+
969 * |Register |type |caller-save/callee-save|
970 * +---------------+-----------------------+-----------------------+
971 * |GR0 |Zero register | - |
972 * |GR1 |Stack pointer(SP) | - |
973 * |GR2 |Frame pointer(FP) | - |
974 * |GR3 |Hidden parameter | caller save |
975 * |GR4-GR7 | - | caller save |
976 * |GR8-GR13 |Argument register | caller save |
977 * |GR14-GR15 | - | caller save |
978 * |GR16-GR31 | - | callee save |
979 * |GR32-GR47 | - | caller save |
980 * |GR48-GR63 | - | callee save |
981 * |FR0-FR15 | - | caller save |
982 * |FR16-FR31 | - | callee save |
983 * |FR32-FR47 | - | caller save |
984 * |FR48-FR63 | - | callee save |
985 * +---------------+-----------------------+-----------------------+
989 * SP-> |-----------------------------------|
991 * |-----------------------------------|
992 * | Register save area |
993 * |-----------------------------------|
994 * | Local variable save area |
995 * FP-> |-----------------------------------|
997 * |-----------------------------------|
998 * | Hidden parameter save area |
999 * |-----------------------------------|
1000 * | Return address(LR) storage area |
1001 * |-----------------------------------|
1002 * | Padding for alignment |
1003 * |-----------------------------------|
1004 * | Register argument area |
1005 * OLD SP-> |-----------------------------------|
1006 * | Parameter area |
1007 * |-----------------------------------|
1010 * Argument area/Parameter area:
1012 * When a function is called, this area is used for argument transfer. When
1013 * the argument is set up by the caller function, this area is referred to as
1014 * the argument area. When the argument is referenced by the callee function,
1015 * this area is referred to as the parameter area. The area is allocated when
1016 * all arguments cannot be placed on the argument register at the time of
1017 * argument transfer.
1019 * Register save area:
1021 * This is a register save area that must be guaranteed for the caller
1022 * function. This area is not secured when the register save operation is not
1025 * Local variable save area:
1027 * This is the area for local variables and temporary variables.
1031 * This area stores the FP value of the caller function.
1033 * Hidden parameter save area:
1035 * This area stores the start address of the return value storage
1036 * area for a struct/union return function.
1037 * When a struct/union is used as the return value, the caller
1038 * function stores the return value storage area start address in
1039 * register GR3 and passes it to the caller function.
1040 * The callee function interprets the address stored in the GR3
1041 * as the return value storage area start address.
1042 * When register GR3 needs to be saved into memory, the callee
1043 * function saves it in the hidden parameter save area. This
1044 * area is not secured when the save operation is not needed.
1046 * Return address(LR) storage area:
1048 * This area saves the LR. The LR stores the address of a return to the caller
1049 * function for the purpose of function calling.
1051 * Argument register area:
1053 * This area saves the argument register. This area is not secured when the
1054 * save operation is not needed.
1058 * Arguments, the count of which equals the count of argument registers (6
1059 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1060 * function. When a struct/union return function is called, the return value
1061 * area address is stored in register GR3. Arguments not placed in the
1062 * argument registers will be stored in the stack argument area for transfer
1063 * purposes. When an 8-byte type argument is to be delivered using registers,
1064 * it is divided into two and placed in two registers for transfer. When
1065 * argument registers must be saved to memory, the callee function secures an
1066 * argument register save area in the stack. In this case, a continuous
1067 * argument register save area must be established in the parameter area. The
1068 * argument register save area must be allocated as needed to cover the size of
1069 * the argument register to be saved. If the function has a variable count of
1070 * arguments, it saves all argument registers in the argument register save
1073 * Argument Extension Format:
1075 * When an argument is to be stored in the stack, its type is converted to an
1076 * extended type in accordance with the individual argument type. The argument
1077 * is freed by the caller function after the return from the callee function is
1080 * +-----------------------+---------------+------------------------+
1081 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1082 * +-----------------------+---------------+------------------------+
1084 * |signed char |int | 4 |
1085 * |unsigned char |int | 4 |
1086 * |[signed] short int |int | 4 |
1087 * |unsigned short int |int | 4 |
1088 * |[signed] int |No extension | 4 |
1089 * |unsigned int |No extension | 4 |
1090 * |[signed] long int |No extension | 4 |
1091 * |unsigned long int |No extension | 4 |
1092 * |[signed] long long int |No extension | 8 |
1093 * |unsigned long long int |No extension | 8 |
1094 * |float |double | 8 |
1095 * |double |No extension | 8 |
1096 * |long double |No extension | 8 |
1097 * |pointer |No extension | 4 |
1098 * |struct/union |- | 4 (*1) |
1099 * +-----------------------+---------------+------------------------+
1101 * When a struct/union is to be delivered as an argument, the caller copies it
1102 * to the local variable area and delivers the address of that area.
1106 * +-------------------------------+----------------------+
1107 * |Return Value Type |Return Value Interface|
1108 * +-------------------------------+----------------------+
1110 * |[signed|unsigned] char |GR8 |
1111 * |[signed|unsigned] short int |GR8 |
1112 * |[signed|unsigned] int |GR8 |
1113 * |[signed|unsigned] long int |GR8 |
1115 * |[signed|unsigned] long long int|GR8 & GR9 |
1117 * |double |GR8 & GR9 |
1118 * |long double |GR8 & GR9 |
1119 * |struct/union |(*1) |
1120 * +-------------------------------+----------------------+
1122 * When a struct/union is used as the return value, the caller function stores
1123 * the start address of the return value storage area into GR3 and then passes
1124 * it to the callee function. The callee function interprets GR3 as the start
1125 * address of the return value storage area. When this address needs to be
1126 * saved in memory, the callee function secures the hidden parameter save area
1127 * and saves the address in that area.
1131 frv_stack_info (void)
1133 static frv_stack_t info, zero_info;
1134 frv_stack_t *info_ptr = &info;
1135 tree fndecl = current_function_decl;
1143 /* If we've already calculated the values and reload is complete,
1145 if (frv_stack_cache)
1146 return frv_stack_cache;
1148 /* Zero all fields. */
1151 /* Set up the register range information. */
1152 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1153 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1154 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1155 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1157 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1158 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1159 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1160 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1162 info_ptr->regs[STACK_REGS_LR].name = "lr";
1163 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1164 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1165 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1167 info_ptr->regs[STACK_REGS_CC].name = "cc";
1168 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1169 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1170 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1172 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1173 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1174 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1176 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1177 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1178 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1179 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1180 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1182 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1183 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1184 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1185 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1187 info_ptr->regs[STACK_REGS_FP].name = "fp";
1188 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1189 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1190 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1192 /* Determine if this is a stdarg function. If so, allocate space to store
1199 /* Find the last argument, and see if it is __builtin_va_alist. */
1200 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1202 next_arg = DECL_CHAIN (cur_arg);
1203 if (next_arg == (tree)0)
1205 if (DECL_NAME (cur_arg)
1206 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1214 /* Iterate over all of the register ranges. */
1215 for (range = 0; range < STACK_REGS_MAX; range++)
1217 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1218 int first = reg_ptr->first;
1219 int last = reg_ptr->last;
1221 int size_2words = 0;
1224 /* Calculate which registers need to be saved & save area size. */
1228 for (regno = first; regno <= last; regno++)
1230 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1231 || (crtl->calls_eh_return
1232 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1233 || (!TARGET_FDPIC && flag_pic
1234 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1236 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1237 size_1word += UNITS_PER_WORD;
1242 /* Calculate whether we need to create a frame after everything else
1243 has been processed. */
1248 if (df_regs_ever_live_p (LR_REGNO)
1250 /* This is set for __builtin_return_address, etc. */
1251 || cfun->machine->frame_needed
1252 || (TARGET_LINKED_FP && frame_pointer_needed)
1253 || (!TARGET_FDPIC && flag_pic
1254 && crtl->uses_pic_offset_table))
1256 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1257 size_1word += UNITS_PER_WORD;
1261 case STACK_REGS_STDARG:
1264 /* If this is a stdarg function with a non varardic
1265 argument split between registers and the stack,
1266 adjust the saved registers downward. */
1267 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1270 for (regno = first; regno <= last; regno++)
1272 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1273 size_1word += UNITS_PER_WORD;
1276 info_ptr->stdarg_size = size_1word;
1280 case STACK_REGS_STRUCT:
1281 if (cfun->returns_struct)
1283 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1284 size_1word += UNITS_PER_WORD;
1292 /* If this is a field, it only takes one word. */
1293 if (reg_ptr->field_p)
1294 size_1word = UNITS_PER_WORD;
1296 /* Determine which register pairs can be saved together. */
1297 else if (reg_ptr->dword_p && TARGET_DWORD)
1299 for (regno = first; regno < last; regno += 2)
1301 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1303 size_2words += 2 * UNITS_PER_WORD;
1304 size_1word -= 2 * UNITS_PER_WORD;
1305 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1306 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1311 reg_ptr->size_1word = size_1word;
1312 reg_ptr->size_2words = size_2words;
1314 if (! reg_ptr->special_p)
1316 info_ptr->regs_size_1word += size_1word;
1317 info_ptr->regs_size_2words += size_2words;
1322 /* Set up the sizes of each each field in the frame body, making the sizes
1323 of each be divisible by the size of a dword if dword operations might
1324 be used, or the size of a word otherwise. */
1325 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1327 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1328 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1329 + info_ptr->regs_size_1word,
1331 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1333 info_ptr->pretend_size = crtl->args.pretend_args_size;
1335 /* Work out the size of the frame, excluding the header. Both the frame
1336 body and register parameter area will be dword-aligned. */
1337 info_ptr->total_size
1338 = (ADDR_ALIGN (info_ptr->parameter_size
1339 + info_ptr->regs_size
1340 + info_ptr->vars_size,
1342 + ADDR_ALIGN (info_ptr->pretend_size
1343 + info_ptr->stdarg_size,
1344 2 * UNITS_PER_WORD));
1346 /* See if we need to create a frame at all, if so add header area. */
1347 if (info_ptr->total_size > 0
1348 || frame_pointer_needed
1349 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1350 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1352 offset = info_ptr->parameter_size;
1353 info_ptr->header_size = 4 * UNITS_PER_WORD;
1354 info_ptr->total_size += 4 * UNITS_PER_WORD;
1356 /* Calculate the offsets to save normal register pairs. */
1357 for (range = 0; range < STACK_REGS_MAX; range++)
1359 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1360 if (! reg_ptr->special_p)
1362 int first = reg_ptr->first;
1363 int last = reg_ptr->last;
1366 for (regno = first; regno <= last; regno++)
1367 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1368 && regno != FRAME_POINTER_REGNUM
1369 && (regno < FIRST_ARG_REGNUM
1370 || regno > LAST_ARG_REGNUM))
1372 info_ptr->reg_offset[regno] = offset;
1373 offset += 2 * UNITS_PER_WORD;
1378 /* Calculate the offsets to save normal single registers. */
1379 for (range = 0; range < STACK_REGS_MAX; range++)
1381 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1382 if (! reg_ptr->special_p)
1384 int first = reg_ptr->first;
1385 int last = reg_ptr->last;
1388 for (regno = first; regno <= last; regno++)
1389 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1390 && regno != FRAME_POINTER_REGNUM
1391 && (regno < FIRST_ARG_REGNUM
1392 || regno > LAST_ARG_REGNUM))
1394 info_ptr->reg_offset[regno] = offset;
1395 offset += UNITS_PER_WORD;
1400 /* Calculate the offset to save the local variables at. */
1401 offset = ADDR_ALIGN (offset, alignment);
1402 if (info_ptr->vars_size)
1404 info_ptr->vars_offset = offset;
1405 offset += info_ptr->vars_size;
1408 /* Align header to a dword-boundary. */
1409 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1411 /* Calculate the offsets in the fixed frame. */
1412 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1413 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1414 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1416 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1417 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1418 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1420 if (cfun->returns_struct)
1422 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1423 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1424 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1427 /* Calculate the offsets to store the arguments passed in registers
1428 for stdarg functions. The register pairs are first and the single
1429 register if any is last. The register save area starts on a
1431 if (info_ptr->stdarg_size)
1433 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1434 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1437 /* Skip the header. */
1438 offset += 4 * UNITS_PER_WORD;
1439 for (regno = first; regno <= last; regno++)
1441 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1443 info_ptr->reg_offset[regno] = offset;
1444 offset += 2 * UNITS_PER_WORD;
1446 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1448 info_ptr->reg_offset[regno] = offset;
1449 offset += UNITS_PER_WORD;
1455 if (reload_completed)
1456 frv_stack_cache = info_ptr;
1462 /* Print the information about the frv stack offsets, etc. when debugging. */
1465 frv_debug_stack (frv_stack_t *info)
1470 info = frv_stack_info ();
1472 fprintf (stderr, "\nStack information for function %s:\n",
1473 ((current_function_decl && DECL_NAME (current_function_decl))
1474 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1477 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1478 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1479 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1480 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1481 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1483 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1484 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1485 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1486 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1488 for (range = 0; range < STACK_REGS_MAX; range++)
1490 frv_stack_regs_t *regs = &(info->regs[range]);
1491 if ((regs->size_1word + regs->size_2words) > 0)
1493 int first = regs->first;
1494 int last = regs->last;
1497 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1498 regs->name, regs->size_1word + regs->size_2words,
1499 regs->size_1word, regs->size_2words);
1501 for (regno = first; regno <= last; regno++)
1503 if (info->save_p[regno] == REG_SAVE_1WORD)
1504 fprintf (stderr, " %s (%d)", reg_names[regno],
1505 info->reg_offset[regno]);
1507 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1508 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1509 reg_names[regno+1], info->reg_offset[regno]);
1512 fputc ('\n', stderr);
1522 /* Used during final to control the packing of insns. The value is
1523 1 if the current instruction should be packed with the next one,
1524 0 if it shouldn't or -1 if packing is disabled altogether. */
1526 static int frv_insn_packing_flag;
1528 /* True if the current function contains a far jump. */
1531 frv_function_contains_far_jump (void)
1533 rtx insn = get_insns ();
1535 && !(GET_CODE (insn) == JUMP_INSN
1536 /* Ignore tablejump patterns. */
1537 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1538 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1539 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1540 insn = NEXT_INSN (insn);
1541 return (insn != NULL);
1544 /* For the FRV, this function makes sure that a function with far jumps
1545 will return correctly. It also does the VLIW packing. */
1548 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1550 /* If no frame was created, check whether the function uses a call
1551 instruction to implement a far jump. If so, save the link in gr3 and
1552 replace all returns to LR with returns to GR3. GR3 is used because it
1553 is call-clobbered, because is not available to the register allocator,
1554 and because all functions that take a hidden argument pointer will have
1556 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1560 /* Just to check that the above comment is true. */
1561 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1563 /* Generate the instruction that saves the link register. */
1564 fprintf (file, "\tmovsg lr,gr3\n");
1566 /* Replace the LR with GR3 in *return_internal patterns. The insn
1567 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1568 simply emit a different assembly directive because bralr and jmpl
1569 execute in different units. */
1570 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1571 if (GET_CODE (insn) == JUMP_INSN)
1573 rtx pattern = PATTERN (insn);
1574 if (GET_CODE (pattern) == PARALLEL
1575 && XVECLEN (pattern, 0) >= 2
1576 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1577 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1579 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1580 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1581 SET_REGNO (address, GPR_FIRST + 3);
1588 /* Allow the garbage collector to free the nops created by frv_reorg. */
1589 memset (frv_nops, 0, sizeof (frv_nops));
1593 /* Return the next available temporary register in a given class. */
1596 frv_alloc_temp_reg (
1597 frv_tmp_reg_t *info, /* which registers are available */
1598 enum reg_class rclass, /* register class desired */
1599 enum machine_mode mode, /* mode to allocate register with */
1600 int mark_as_used, /* register not available after allocation */
1601 int no_abort) /* return NULL instead of aborting */
1603 int regno = info->next_reg[ (int)rclass ];
1604 int orig_regno = regno;
1605 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1610 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1611 && TEST_HARD_REG_BIT (info->regs, regno))
1614 if (++regno >= FIRST_PSEUDO_REGISTER)
1616 if (regno == orig_regno)
1618 gcc_assert (no_abort);
1623 nr = HARD_REGNO_NREGS (regno, mode);
1624 info->next_reg[ (int)rclass ] = regno + nr;
1627 for (i = 0; i < nr; i++)
1628 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1630 return gen_rtx_REG (mode, regno);
1634 /* Return an rtx with the value OFFSET, which will either be a register or a
1635 signed 12-bit integer. It can be used as the second operand in an "add"
1636 instruction, or as the index in a load or store.
1638 The function returns a constant rtx if OFFSET is small enough, otherwise
1639 it loads the constant into register OFFSET_REGNO and returns that. */
1641 frv_frame_offset_rtx (int offset)
1643 rtx offset_rtx = GEN_INT (offset);
1644 if (IN_RANGE_P (offset, -2048, 2047))
1648 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1649 if (IN_RANGE_P (offset, -32768, 32767))
1650 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1653 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1654 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1660 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1661 prologue and epilogue uses such expressions to access the stack. */
1663 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1665 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1667 frv_frame_offset_rtx (offset)));
1670 /* Generate a frame-related expression:
1672 (set REG (mem (plus (sp) (const_int OFFSET)))).
1674 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1675 instructions. Marking the expressions as frame-related is superfluous if
1676 the note contains just a single set. But if the note contains a PARALLEL
1677 or SEQUENCE that has several sets, each set must be individually marked
1678 as frame-related. */
1680 frv_dwarf_store (rtx reg, int offset)
1682 rtx set = gen_rtx_SET (VOIDmode,
1683 gen_rtx_MEM (GET_MODE (reg),
1684 plus_constant (stack_pointer_rtx,
1687 RTX_FRAME_RELATED_P (set) = 1;
1691 /* Emit a frame-related instruction whose pattern is PATTERN. The
1692 instruction is the last in a sequence that cumulatively performs the
1693 operation described by DWARF_PATTERN. The instruction is marked as
1694 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1697 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1699 rtx insn = emit_insn (pattern);
1700 RTX_FRAME_RELATED_P (insn) = 1;
1701 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1706 /* Emit instructions that transfer REG to or from the memory location (sp +
1707 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1708 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1709 function to store registers and only the epilogue uses it to load them.
1711 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1712 The generated instruction will use BASE as its base register. BASE may
1713 simply be the stack pointer, but if several accesses are being made to a
1714 region far away from the stack pointer, it may be more efficient to set
1715 up a temporary instead.
1717 Store instructions will be frame-related and will be annotated with the
1718 overall effect of the store. Load instructions will be followed by a
1719 (use) to prevent later optimizations from zapping them.
1721 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1722 as a temporary in such cases. */
1724 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1726 enum machine_mode mode = GET_MODE (reg);
1727 rtx mem = frv_frame_mem (mode,
1729 stack_offset - accessor->base_offset);
1731 if (accessor->op == FRV_LOAD)
1733 if (SPR_P (REGNO (reg)))
1735 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1736 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1737 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1741 /* We cannot use reg+reg addressing for DImode access. */
1743 && GET_CODE (XEXP (mem, 0)) == PLUS
1744 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1745 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1747 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1748 rtx insn = emit_move_insn (temp,
1749 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1750 XEXP (XEXP (mem, 0), 1)));
1751 mem = gen_rtx_MEM (DImode, temp);
1753 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1759 if (SPR_P (REGNO (reg)))
1761 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1762 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1763 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1764 frv_dwarf_store (reg, stack_offset));
1766 else if (mode == DImode)
1768 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1769 with a separate save for each register. */
1770 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1771 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1772 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1773 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1775 /* Also we cannot use reg+reg addressing. */
1776 if (GET_CODE (XEXP (mem, 0)) == PLUS
1777 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1778 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1780 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1781 rtx insn = emit_move_insn (temp,
1782 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1783 XEXP (XEXP (mem, 0), 1)));
1784 mem = gen_rtx_MEM (DImode, temp);
1787 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1788 gen_rtx_PARALLEL (VOIDmode,
1789 gen_rtvec (2, set1, set2)));
1792 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1793 frv_dwarf_store (reg, stack_offset));
1797 /* A function that uses frv_frame_access to transfer a group of registers to
1798 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1799 is the stack information generated by frv_stack_info, and REG_SET is the
1800 number of the register set to transfer. */
1802 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1806 frv_stack_regs_t *regs_info;
1809 regs_info = &info->regs[reg_set];
1810 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1811 if (info->save_p[regno])
1812 frv_frame_access (accessor,
1813 info->save_p[regno] == REG_SAVE_2WORDS
1814 ? gen_rtx_REG (DImode, regno)
1815 : gen_rtx_REG (SImode, regno),
1816 info->reg_offset[regno]);
1819 /* Save or restore callee-saved registers that are kept outside the frame
1820 header. The function saves the registers if OP is FRV_STORE and restores
1821 them if OP is FRV_LOAD. INFO is the stack information generated by
1824 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1826 frv_frame_accessor_t accessor;
1829 accessor.base = stack_pointer_rtx;
1830 accessor.base_offset = 0;
1831 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1832 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1833 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1837 /* Called after register allocation to add any instructions needed for the
1838 prologue. Using a prologue insn is favored compared to putting all of the
1839 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1840 it allows the scheduler to intermix instructions with the saves of
1841 the caller saved registers. In some cases, it might be necessary
1842 to emit a barrier instruction as the last insn to prevent such
1845 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1846 so that the debug info generation code can handle them properly. */
1848 frv_expand_prologue (void)
1850 frv_stack_t *info = frv_stack_info ();
1851 rtx sp = stack_pointer_rtx;
1852 rtx fp = frame_pointer_rtx;
1853 frv_frame_accessor_t accessor;
1855 if (TARGET_DEBUG_STACK)
1856 frv_debug_stack (info);
1858 if (info->total_size == 0)
1861 /* We're interested in three areas of the frame here:
1863 A: the register save area
1865 C: the header after B
1867 If the frame pointer isn't used, we'll have to set up A, B and C
1868 using the stack pointer. If the frame pointer is used, we'll access
1872 B: set up using sp or a temporary (see below)
1875 We set up B using the stack pointer if the frame is small enough.
1876 Otherwise, it's more efficient to copy the old stack pointer into a
1877 temporary and use that.
1879 Note that it's important to make sure the prologue and epilogue use the
1880 same registers to access A and C, since doing otherwise will confuse
1881 the aliasing code. */
1883 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1884 isn't used, the same method will serve for C. */
1885 accessor.op = FRV_STORE;
1886 if (frame_pointer_needed && info->total_size > 2048)
1890 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1891 accessor.base_offset = info->total_size;
1892 insn = emit_insn (gen_movsi (accessor.base, sp));
1896 accessor.base = stack_pointer_rtx;
1897 accessor.base_offset = 0;
1900 /* Allocate the stack space. */
1902 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1903 rtx dwarf_offset = GEN_INT (-info->total_size);
1905 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1908 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1911 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1912 and point the new one to that location. */
1913 if (frame_pointer_needed)
1915 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1917 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1918 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1920 rtx asm_src = plus_constant (accessor.base,
1921 fp_offset - accessor.base_offset);
1922 rtx dwarf_src = plus_constant (sp, fp_offset);
1924 /* Store the old frame pointer at (sp + FP_OFFSET). */
1925 frv_frame_access (&accessor, fp, fp_offset);
1927 /* Set up the new frame pointer. */
1928 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1929 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1931 /* Access region C from the frame pointer. */
1933 accessor.base_offset = fp_offset;
1936 /* Set up region C. */
1937 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1938 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1939 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1941 /* Set up region A. */
1942 frv_frame_access_standard_regs (FRV_STORE, info);
1944 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1945 scheduler from moving loads before the stores saving the registers. */
1946 if (info->stdarg_size > 0)
1947 emit_insn (gen_blockage ());
1949 /* Set up pic register/small data register for this function. */
1950 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1951 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1952 gen_rtx_REG (Pmode, LR_REGNO),
1953 gen_rtx_REG (SImode, OFFSET_REGNO)));
1957 /* Under frv, all of the work is done via frv_expand_epilogue, but
1958 this function provides a convenient place to do cleanup. */
1961 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1962 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1964 frv_stack_cache = (frv_stack_t *)0;
1966 /* Zap last used registers for conditional execution. */
1967 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1969 /* Release the bitmap of created insns. */
1970 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1974 /* Called after register allocation to add any instructions needed for the
1975 epilogue. Using an epilogue insn is favored compared to putting all of the
1976 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1977 it allows the scheduler to intermix instructions with the saves of
1978 the caller saved registers. In some cases, it might be necessary
1979 to emit a barrier instruction as the last insn to prevent such
1983 frv_expand_epilogue (bool emit_return)
1985 frv_stack_t *info = frv_stack_info ();
1986 rtx fp = frame_pointer_rtx;
1987 rtx sp = stack_pointer_rtx;
1991 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1993 /* Restore the stack pointer to its original value if alloca or the like
1995 if (! current_function_sp_is_unchanging)
1996 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1998 /* Restore the callee-saved registers that were used in this function. */
1999 frv_frame_access_standard_regs (FRV_LOAD, info);
2001 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
2002 no return instruction should be emitted. */
2003 if (info->save_p[LR_REGNO])
2008 /* Use the same method to access the link register's slot as we did in
2009 the prologue. In other words, use the frame pointer if available,
2010 otherwise use the stack pointer.
2012 LR_OFFSET is the offset of the link register's slot from the start
2013 of the frame and MEM is a memory rtx for it. */
2014 lr_offset = info->reg_offset[LR_REGNO];
2015 if (frame_pointer_needed)
2016 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
2018 mem = frv_frame_mem (Pmode, sp, lr_offset);
2020 /* Load the old link register into a GPR. */
2021 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
2022 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
2025 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
2027 /* Restore the old frame pointer. Emit a USE afterwards to make sure
2028 the load is preserved. */
2029 if (frame_pointer_needed)
2031 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
2035 /* Deallocate the stack frame. */
2036 if (info->total_size != 0)
2038 rtx offset = frv_frame_offset_rtx (info->total_size);
2039 emit_insn (gen_stack_adjust (sp, sp, offset));
2042 /* If this function uses eh_return, add the final stack adjustment now. */
2043 if (crtl->calls_eh_return)
2044 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2047 emit_jump_insn (gen_epilogue_return (return_addr));
2050 rtx lr = return_addr;
2052 if (REGNO (return_addr) != LR_REGNO)
2054 lr = gen_rtx_REG (Pmode, LR_REGNO);
2055 emit_move_insn (lr, return_addr);
2063 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2066 frv_asm_output_mi_thunk (FILE *file,
2067 tree thunk_fndecl ATTRIBUTE_UNUSED,
2068 HOST_WIDE_INT delta,
2069 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2072 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2073 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2074 const char *name_jmp = reg_names[JUMP_REGNO];
2075 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2077 /* Do the add using an addi if possible. */
2078 if (IN_RANGE_P (delta, -2048, 2047))
2079 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2082 const char *const name_add = reg_names[TEMP_REGNO];
2083 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2084 parallel, delta, name_add);
2085 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2087 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2092 const char *name_pic = reg_names[FDPIC_REGNO];
2093 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2097 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2098 assemble_name (file, name_func);
2099 fprintf (file, "),%s\n", name_jmp);
2101 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2102 assemble_name (file, name_func);
2103 fprintf (file, "),%s\n", name_jmp);
2105 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2109 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2110 assemble_name (file, name_func);
2111 fprintf (file, "\t)), %s\n", name_jmp);
2116 fprintf (file, "\tsethi%s #hi(", parallel);
2117 assemble_name (file, name_func);
2118 fprintf (file, "),%s\n", name_jmp);
2120 fprintf (file, "\tsetlo #lo(");
2121 assemble_name (file, name_func);
2122 fprintf (file, "),%s\n", name_jmp);
2126 /* Use JUMP_REGNO as a temporary PIC register. */
2127 const char *name_lr = reg_names[LR_REGNO];
2128 const char *name_gppic = name_jmp;
2129 const char *name_tmp = reg_names[TEMP_REGNO];
2131 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2132 fprintf (file, "\tcall 1f\n");
2133 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2134 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2135 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2136 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2137 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2139 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2140 assemble_name (file, name_func);
2141 fprintf (file, "),%s\n", name_tmp);
2143 fprintf (file, "\tsetlo #gprello(");
2144 assemble_name (file, name_func);
2145 fprintf (file, "),%s\n", name_tmp);
2147 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2150 /* Jump to the function address. */
2151 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2156 /* On frv, create a frame whenever we need to create stack. */
2159 frv_frame_pointer_required (void)
2161 /* If we forgoing the usual linkage requirements, we only need
2162 a frame pointer if the stack pointer might change. */
2163 if (!TARGET_LINKED_FP)
2164 return !current_function_sp_is_unchanging;
2166 if (! current_function_is_leaf)
2169 if (get_frame_size () != 0)
2175 if (!current_function_sp_is_unchanging)
2178 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2184 if (cfun->machine->frame_needed)
2191 /* Worker function for TARGET_CAN_ELIMINATE. */
2194 frv_can_eliminate (const int from, const int to)
2196 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2197 ? ! frame_pointer_needed
2201 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2202 initial difference between the specified pair of registers. This macro must
2203 be defined if `ELIMINABLE_REGS' is defined. */
2205 /* See frv_stack_info for more details on the frv stack frame. */
2208 frv_initial_elimination_offset (int from, int to)
2210 frv_stack_t *info = frv_stack_info ();
2213 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2214 ret = info->total_size - info->pretend_size;
2216 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2217 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2219 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2220 ret = (info->total_size
2221 - info->reg_offset[FRAME_POINTER_REGNUM]
2222 - info->pretend_size);
2227 if (TARGET_DEBUG_STACK)
2228 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2229 reg_names [from], reg_names[to], ret);
2235 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2238 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2239 enum machine_mode mode,
2240 tree type ATTRIBUTE_UNUSED,
2244 if (TARGET_DEBUG_ARG)
2246 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2247 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2251 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2254 frv_expand_builtin_saveregs (void)
2256 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2258 if (TARGET_DEBUG_ARG)
2259 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2262 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2266 /* Expand __builtin_va_start to do the va_start macro. */
2269 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2272 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2274 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2275 GEN_INT (UNITS_PER_WORD * num));
2277 if (TARGET_DEBUG_ARG)
2279 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2280 crtl->args.info, num);
2282 debug_rtx (nextarg);
2285 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2286 fold_convert (TREE_TYPE (valist),
2287 make_tree (sizetype, nextarg)));
2288 TREE_SIDE_EFFECTS (t) = 1;
2290 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2294 /* Expand a block move operation, and return 1 if successful. Return 0
2295 if we should let the compiler generate normal code.
2297 operands[0] is the destination
2298 operands[1] is the source
2299 operands[2] is the length
2300 operands[3] is the alignment */
2302 /* Maximum number of loads to do before doing the stores */
2303 #ifndef MAX_MOVE_REG
2304 #define MAX_MOVE_REG 4
2307 /* Maximum number of total loads to do. */
2308 #ifndef TOTAL_MOVE_REG
2309 #define TOTAL_MOVE_REG 8
2313 frv_expand_block_move (rtx operands[])
2315 rtx orig_dest = operands[0];
2316 rtx orig_src = operands[1];
2317 rtx bytes_rtx = operands[2];
2318 rtx align_rtx = operands[3];
2319 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2332 rtx stores[MAX_MOVE_REG];
2334 enum machine_mode mode;
2336 /* If this is not a fixed size move, just call memcpy. */
2340 /* This should be a fixed size alignment. */
2341 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2343 align = INTVAL (align_rtx);
2345 /* Anything to move? */
2346 bytes = INTVAL (bytes_rtx);
2350 /* Don't support real large moves. */
2351 if (bytes > TOTAL_MOVE_REG*align)
2354 /* Move the address into scratch registers. */
2355 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2356 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2358 num_reg = offset = 0;
2359 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2361 /* Calculate the correct offset for src/dest. */
2365 dest_addr = dest_reg;
2369 src_addr = plus_constant (src_reg, offset);
2370 dest_addr = plus_constant (dest_reg, offset);
2373 /* Generate the appropriate load and store, saving the stores
2375 if (bytes >= 4 && align >= 4)
2377 else if (bytes >= 2 && align >= 2)
2382 move_bytes = GET_MODE_SIZE (mode);
2383 tmp_reg = gen_reg_rtx (mode);
2384 src_mem = change_address (orig_src, mode, src_addr);
2385 dest_mem = change_address (orig_dest, mode, dest_addr);
2386 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2387 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2389 if (num_reg >= MAX_MOVE_REG)
2391 for (i = 0; i < num_reg; i++)
2392 emit_insn (stores[i]);
2397 for (i = 0; i < num_reg; i++)
2398 emit_insn (stores[i]);
2404 /* Expand a block clear operation, and return 1 if successful. Return 0
2405 if we should let the compiler generate normal code.
2407 operands[0] is the destination
2408 operands[1] is the length
2409 operands[3] is the alignment */
2412 frv_expand_block_clear (rtx operands[])
2414 rtx orig_dest = operands[0];
2415 rtx bytes_rtx = operands[1];
2416 rtx align_rtx = operands[3];
2417 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2426 enum machine_mode mode;
2428 /* If this is not a fixed size move, just call memcpy. */
2432 /* This should be a fixed size alignment. */
2433 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2435 align = INTVAL (align_rtx);
2437 /* Anything to move? */
2438 bytes = INTVAL (bytes_rtx);
2442 /* Don't support real large clears. */
2443 if (bytes > TOTAL_MOVE_REG*align)
2446 /* Move the address into a scratch register. */
2447 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2449 num_reg = offset = 0;
2450 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2452 /* Calculate the correct offset for src/dest. */
2453 dest_addr = ((offset == 0)
2455 : plus_constant (dest_reg, offset));
2457 /* Generate the appropriate store of gr0. */
2458 if (bytes >= 4 && align >= 4)
2460 else if (bytes >= 2 && align >= 2)
2465 clear_bytes = GET_MODE_SIZE (mode);
2466 dest_mem = change_address (orig_dest, mode, dest_addr);
2467 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2474 /* The following variable is used to output modifiers of assembler
2475 code of the current output insn. */
2477 static rtx *frv_insn_operands;
2479 /* The following function is used to add assembler insn code suffix .p
2480 if it is necessary. */
2483 frv_asm_output_opcode (FILE *f, const char *ptr)
2487 if (frv_insn_packing_flag <= 0)
2490 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2493 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2494 || (*ptr >= 'A' && *ptr <= 'Z')))
2496 int letter = *ptr++;
2499 frv_print_operand (f, frv_insn_operands [c], letter);
2500 while ((c = *ptr) >= '0' && c <= '9')
2512 /* Set up the packing bit for the current output insn. Note that this
2513 function is not called for asm insns. */
2516 frv_final_prescan_insn (rtx insn, rtx *opvec,
2517 int noperands ATTRIBUTE_UNUSED)
2521 if (frv_insn_packing_flag >= 0)
2523 frv_insn_operands = opvec;
2524 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2526 else if (recog_memoized (insn) >= 0
2527 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2528 /* Packing optimizations have been disabled, but INSN can only
2529 be issued in M1. Insert an mnop in M0. */
2530 fprintf (asm_out_file, "\tmnop.p\n");
2536 /* A C expression whose value is RTL representing the address in a stack frame
2537 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2538 an RTL expression for the address of the stack frame itself.
2540 If you don't define this macro, the default is to return the value of
2541 FRAMEADDR--that is, the stack frame address is also the address of the stack
2542 word that points to the previous frame. */
2544 /* The default is correct, but we need to make sure the frame gets created. */
2546 frv_dynamic_chain_address (rtx frame)
2548 cfun->machine->frame_needed = 1;
2553 /* A C expression whose value is RTL representing the value of the return
2554 address for the frame COUNT steps up from the current frame, after the
2555 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2556 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2559 The value of the expression must always be the correct address when COUNT is
2560 zero, but may be `NULL_RTX' if there is not way to determine the return
2561 address of other frames. */
2564 frv_return_addr_rtx (int count, rtx frame)
2568 cfun->machine->frame_needed = 1;
2569 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2572 /* Given a memory reference MEMREF, interpret the referenced memory as
2573 an array of MODE values, and return a reference to the element
2574 specified by INDEX. Assume that any pre-modification implicit in
2575 MEMREF has already happened.
2577 MEMREF must be a legitimate operand for modes larger than SImode.
2578 frv_legitimate_address_p forbids register+register addresses, which
2579 this function cannot handle. */
2581 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2583 rtx base = XEXP (memref, 0);
2584 if (GET_CODE (base) == PRE_MODIFY)
2585 base = XEXP (base, 0);
2586 return change_address (memref, mode,
2587 plus_constant (base, index * GET_MODE_SIZE (mode)));
2591 /* Print a memory address as an operand to reference that memory location. */
2593 frv_print_operand_address (FILE * stream, rtx x)
2595 if (GET_CODE (x) == MEM)
2598 switch (GET_CODE (x))
2601 fputs (reg_names [ REGNO (x)], stream);
2605 fprintf (stream, "%ld", (long) INTVAL (x));
2609 assemble_name (stream, XSTR (x, 0));
2614 output_addr_const (stream, x);
2618 /* Poorly constructed asm statements can trigger this alternative.
2619 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2620 frv_print_operand_memory_reference (stream, x, 0);
2627 fatal_insn ("bad insn to frv_print_operand_address:", x);
2632 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2634 int regno = true_regnum (x);
2636 fputs (reg_names[regno], stream);
2638 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2641 /* Print a memory reference suitable for the ld/st instructions. */
2644 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2646 struct frv_unspec unspec;
2650 switch (GET_CODE (x))
2657 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2659 x1 = XEXP (XEXP (x, 1), 1);
2669 if (GET_CODE (x0) == CONST_INT)
2677 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2686 else if (GET_CODE (x1) != CONST_INT)
2687 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2690 fputs ("@(", stream);
2692 fputs (reg_names[GPR_R0], stream);
2693 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2694 frv_print_operand_memory_reference_reg (stream, x0);
2696 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2698 fputs (",", stream);
2700 fputs (reg_names [GPR_R0], stream);
2704 switch (GET_CODE (x1))
2708 frv_print_operand_memory_reference_reg (stream, x1);
2712 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2716 if (!frv_const_unspec_p (x1, &unspec))
2717 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2718 frv_output_const_unspec (stream, &unspec);
2722 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2726 fputs (")", stream);
2730 /* Return 2 for likely branches and 0 for non-likely branches */
2732 #define FRV_JUMP_LIKELY 2
2733 #define FRV_JUMP_NOT_LIKELY 0
2736 frv_print_operand_jump_hint (rtx insn)
2741 HOST_WIDE_INT prob = -1;
2742 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2744 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2746 /* Assume any non-conditional jump is likely. */
2747 if (! any_condjump_p (insn))
2748 ret = FRV_JUMP_LIKELY;
2752 labelref = condjump_label (insn);
2755 rtx label = XEXP (labelref, 0);
2756 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2761 note = find_reg_note (insn, REG_BR_PROB, 0);
2763 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2767 prob = INTVAL (XEXP (note, 0));
2768 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2770 : FRV_JUMP_NOT_LIKELY);
2782 case UNKNOWN: direction = "unknown jump direction"; break;
2783 case BACKWARD: direction = "jump backward"; break;
2784 case FORWARD: direction = "jump forward"; break;
2788 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2789 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2790 (long)INSN_UID (insn), direction, (long)prob,
2791 (long)REG_BR_PROB_BASE, ret);
2799 /* Return the comparison operator to use for CODE given that the ICC
2803 comparison_string (enum rtx_code code, rtx op0)
2805 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2808 default: output_operand_lossage ("bad condition code");
2809 case EQ: return "eq";
2810 case NE: return "ne";
2811 case LT: return is_nz_p ? "n" : "lt";
2812 case LE: return "le";
2813 case GT: return "gt";
2814 case GE: return is_nz_p ? "p" : "ge";
2815 case LTU: return is_nz_p ? "no" : "c";
2816 case LEU: return is_nz_p ? "eq" : "ls";
2817 case GTU: return is_nz_p ? "ne" : "hi";
2818 case GEU: return is_nz_p ? "ra" : "nc";
2822 /* Print an operand to an assembler instruction.
2824 `%' followed by a letter and a digit says to output an operand in an
2825 alternate fashion. Four letters have standard, built-in meanings
2826 described below. The hook `TARGET_PRINT_OPERAND' can define
2827 additional letters with nonstandard meanings.
2829 `%cDIGIT' can be used to substitute an operand that is a constant value
2830 without the syntax that normally indicates an immediate operand.
2832 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2835 `%aDIGIT' can be used to substitute an operand as if it were a memory
2836 reference, with the actual operand treated as the address. This may be
2837 useful when outputting a "load address" instruction, because often the
2838 assembler syntax for such an instruction requires you to write the operand
2839 as if it were a memory reference.
2841 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2843 `%=' outputs a number which is unique to each instruction in the entire
2844 compilation. This is useful for making local labels to be referred to more
2845 than once in a single template that generates multiple assembler
2848 `%' followed by a punctuation character specifies a substitution that
2849 does not use an operand. Only one case is standard: `%%' outputs a
2850 `%' into the assembler code. Other nonstandard cases can be defined
2851 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2852 punctuation characters are valid with the
2853 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2856 frv_print_operand (FILE * file, rtx x, int code)
2858 struct frv_unspec unspec;
2859 HOST_WIDE_INT value;
2862 if (code != 0 && !ISALPHA (code))
2865 else if (GET_CODE (x) == CONST_INT)
2868 else if (GET_CODE (x) == CONST_DOUBLE)
2870 if (GET_MODE (x) == SFmode)
2875 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2876 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2880 else if (GET_MODE (x) == VOIDmode)
2881 value = CONST_DOUBLE_LOW (x);
2884 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2895 fputs (reg_names[GPR_R0], file);
2899 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2903 /* Output small data area base register (gr16). */
2904 fputs (reg_names[SDA_BASE_REG], file);
2908 /* Output pic register (gr17). */
2909 fputs (reg_names[PIC_REGNO], file);
2913 /* Output the temporary integer CCR register. */
2914 fputs (reg_names[ICR_TEMP], file);
2918 /* Output the temporary integer CC register. */
2919 fputs (reg_names[ICC_TEMP], file);
2922 /* case 'a': print an address. */
2925 /* Print appropriate test for integer branch false operation. */
2926 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2927 XEXP (x, 0)), file);
2931 /* Print appropriate test for integer branch true operation. */
2932 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2936 /* Print 1 for a NE and 0 for an EQ to give the final argument
2937 for a conditional instruction. */
2938 if (GET_CODE (x) == NE)
2941 else if (GET_CODE (x) == EQ)
2945 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2949 /* Print appropriate test for floating point branch false operation. */
2950 switch (GET_CODE (x))
2953 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2955 case EQ: fputs ("ne", file); break;
2956 case NE: fputs ("eq", file); break;
2957 case LT: fputs ("uge", file); break;
2958 case LE: fputs ("ug", file); break;
2959 case GT: fputs ("ule", file); break;
2960 case GE: fputs ("ul", file); break;
2965 /* Print appropriate test for floating point branch true operation. */
2966 switch (GET_CODE (x))
2969 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2971 case EQ: fputs ("eq", file); break;
2972 case NE: fputs ("ne", file); break;
2973 case LT: fputs ("lt", file); break;
2974 case LE: fputs ("le", file); break;
2975 case GT: fputs ("gt", file); break;
2976 case GE: fputs ("ge", file); break;
2981 /* Print appropriate GOT function. */
2982 if (GET_CODE (x) != CONST_INT)
2983 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2984 fputs (unspec_got_name (INTVAL (x)), file);
2988 /* Print 'i' if the operand is a constant, or is a memory reference that
2990 if (GET_CODE (x) == MEM)
2991 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2992 ? XEXP (XEXP (x, 0), 1)
2994 else if (GET_CODE (x) == PLUS)
2997 switch (GET_CODE (x))
3011 /* For jump instructions, print 'i' if the operand is a constant or
3012 is an expression that adds a constant. */
3013 if (GET_CODE (x) == CONST_INT)
3018 if (GET_CODE (x) == CONST_INT
3019 || (GET_CODE (x) == PLUS
3020 && (GET_CODE (XEXP (x, 1)) == CONST_INT
3021 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
3027 /* Print the lower register of a double word register pair */
3028 if (GET_CODE (x) == REG)
3029 fputs (reg_names[ REGNO (x)+1 ], file);
3031 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
3034 /* case 'l': print a LABEL_REF. */
3038 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
3039 for the second word of double memory operations. */
3040 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3041 switch (GET_CODE (x))
3044 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3047 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3055 frv_print_operand_memory_reference (file, x, offset);
3061 /* Print the opcode of a command. */
3062 switch (GET_CODE (x))
3065 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3067 case PLUS: fputs ("add", file); break;
3068 case MINUS: fputs ("sub", file); break;
3069 case AND: fputs ("and", file); break;
3070 case IOR: fputs ("or", file); break;
3071 case XOR: fputs ("xor", file); break;
3072 case ASHIFT: fputs ("sll", file); break;
3073 case ASHIFTRT: fputs ("sra", file); break;
3074 case LSHIFTRT: fputs ("srl", file); break;
3078 /* case 'n': negate and print a constant int. */
3081 /* Print PIC label using operand as the number. */
3082 if (GET_CODE (x) != CONST_INT)
3083 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3085 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3089 /* Print 'u' if the operand is a update load/store. */
3090 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3095 /* If value is 0, print gr0, otherwise it must be a register. */
3096 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3097 fputs (reg_names[GPR_R0], file);
3099 else if (GET_CODE (x) == REG)
3100 fputs (reg_names [REGNO (x)], file);
3103 fatal_insn ("bad insn in frv_print_operand, z case", x);
3107 /* Print constant in hex. */
3108 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3110 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3117 if (GET_CODE (x) == REG)
3118 fputs (reg_names [REGNO (x)], file);
3120 else if (GET_CODE (x) == CONST_INT
3121 || GET_CODE (x) == CONST_DOUBLE)
3122 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3124 else if (frv_const_unspec_p (x, &unspec))
3125 frv_output_const_unspec (file, &unspec);
3127 else if (GET_CODE (x) == MEM)
3128 frv_print_operand_address (file, XEXP (x, 0));
3130 else if (CONSTANT_ADDRESS_P (x))
3131 frv_print_operand_address (file, x);
3134 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3139 fatal_insn ("frv_print_operand: unknown code", x);
3147 frv_print_operand_punct_valid_p (unsigned char code)
3149 return (code == '.' || code == '#' || code == '@' || code == '~'
3150 || code == '*' || code == '&');
3154 /* A C statement (sans semicolon) for initializing the variable CUM for the
3155 state at the beginning of the argument list. The variable has type
3156 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3157 of the function which will receive the args, or 0 if the args are to a
3158 compiler support library function. The value of INDIRECT is nonzero when
3159 processing an indirect call, for example a call through a function pointer.
3160 The value of INDIRECT is zero for a call to an explicitly named function, a
3161 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3162 arguments for the function being compiled.
3164 When processing a call to a compiler support library function, LIBNAME
3165 identifies which one. It is a `symbol_ref' rtx which contains the name of
3166 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3167 being processed. Thus, each time this macro is called, either LIBNAME or
3168 FNTYPE is nonzero, but never both of them at once. */
3171 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3177 *cum = FIRST_ARG_REGNUM;
3179 if (TARGET_DEBUG_ARG)
3181 fprintf (stderr, "\ninit_cumulative_args:");
3182 if (!fndecl && fntype)
3183 fputs (" indirect", stderr);
3186 fputs (" incoming", stderr);
3190 tree ret_type = TREE_TYPE (fntype);
3191 fprintf (stderr, " return=%s,",
3192 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3195 if (libname && GET_CODE (libname) == SYMBOL_REF)
3196 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3198 if (cfun->returns_struct)
3199 fprintf (stderr, " return-struct");
3201 putc ('\n', stderr);
3206 /* Return true if we should pass an argument on the stack rather than
3210 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3212 if (mode == BLKmode)
3216 return AGGREGATE_TYPE_P (type);
3219 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3220 argument with the specified mode and type. If it is not defined,
3221 `PARM_BOUNDARY' is used for all arguments. */
3224 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3225 tree type ATTRIBUTE_UNUSED)
3227 return BITS_PER_WORD;
3231 frv_function_arg (CUMULATIVE_ARGS *cum,
3232 enum machine_mode mode,
3233 tree type ATTRIBUTE_UNUSED,
3235 int incoming ATTRIBUTE_UNUSED)
3237 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3242 /* Return a marker for use in the call instruction. */
3243 if (xmode == VOIDmode)
3249 else if (arg_num <= LAST_ARG_REGNUM)
3251 ret = gen_rtx_REG (xmode, arg_num);
3252 debstr = reg_names[arg_num];
3261 if (TARGET_DEBUG_ARG)
3263 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3264 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3270 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3271 advance past an argument in the argument list. The values MODE, TYPE and
3272 NAMED describe that argument. Once this is done, the variable CUM is
3273 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3275 This macro need not do anything if the argument in question was passed on
3276 the stack. The compiler knows how to track the amount of stack space used
3277 for arguments without any special help. */
3280 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3281 enum machine_mode mode,
3282 tree type ATTRIBUTE_UNUSED,
3285 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3286 int bytes = GET_MODE_SIZE (xmode);
3287 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3290 *cum = arg_num + words;
3292 if (TARGET_DEBUG_ARG)
3294 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3295 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3299 /* A C expression for the number of words, at the beginning of an argument,
3300 must be put in registers. The value must be zero for arguments that are
3301 passed entirely in registers or that are entirely pushed on the stack.
3303 On some machines, certain arguments must be passed partially in registers
3304 and partially in memory. On these machines, typically the first N words of
3305 arguments are passed in registers, and the rest on the stack. If a
3306 multi-word argument (a `double' or a structure) crosses that boundary, its
3307 first few words must be passed in registers and the rest must be pushed.
3308 This macro tells the compiler when this occurs, and how many of the words
3309 should go in registers.
3311 `FUNCTION_ARG' for these arguments should return the first register to be
3312 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3313 the called function. */
3316 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3317 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3319 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3320 int bytes = GET_MODE_SIZE (xmode);
3321 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3325 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3326 ? LAST_ARG_REGNUM - arg_num + 1
3328 ret *= UNITS_PER_WORD;
3330 if (TARGET_DEBUG_ARG && ret)
3331 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3337 /* Implements TARGET_FUNCTION_VALUE. */
3340 frv_function_value (const_tree valtype,
3341 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3342 bool outgoing ATTRIBUTE_UNUSED)
3344 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3348 /* Implements TARGET_LIBCALL_VALUE. */
3351 frv_libcall_value (enum machine_mode mode,
3352 const_rtx fun ATTRIBUTE_UNUSED)
3354 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3358 /* Implements FUNCTION_VALUE_REGNO_P. */
3361 frv_function_value_regno_p (const unsigned int regno)
3363 return (regno == RETURN_VALUE_REGNUM);
3366 /* Return true if a register is ok to use as a base or index register. */
3368 static FRV_INLINE int
3369 frv_regno_ok_for_base_p (int regno, int strict_p)
3375 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3377 if (regno == ARG_POINTER_REGNUM)
3380 return (regno >= FIRST_PSEUDO_REGISTER);
3384 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3385 RTX) is a legitimate memory address on the target machine for a memory
3386 operand of mode MODE.
3388 It usually pays to define several simpler macros to serve as subroutines for
3389 this one. Otherwise it may be too complicated to understand.
3391 This macro must exist in two variants: a strict variant and a non-strict
3392 one. The strict variant is used in the reload pass. It must be defined so
3393 that any pseudo-register that has not been allocated a hard register is
3394 considered a memory reference. In contexts where some kind of register is
3395 required, a pseudo-register with no hard register must be rejected.
3397 The non-strict variant is used in other passes. It must be defined to
3398 accept all pseudo-registers in every context where some kind of register is
3401 Compiler source files that want to use the strict variant of this macro
3402 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3403 conditional to define the strict variant in that case and the non-strict
3406 Normally, constant addresses which are the sum of a `symbol_ref' and an
3407 integer are stored inside a `const' RTX to mark them as constant.
3408 Therefore, there is no need to recognize such sums specifically as
3409 legitimate addresses. Normally you would simply recognize any `const' as
3412 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3413 constant sums that are not marked with `const'. It assumes that a
3414 naked `plus' indicates indexing. If so, then you *must* reject such
3415 naked constant sums as illegitimate addresses, so that none of them
3416 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3419 frv_legitimate_address_p_1 (enum machine_mode mode,
3423 int allow_double_reg_p)
3427 HOST_WIDE_INT value;
3430 if (FRV_SYMBOL_REF_TLS_P (x))
3433 switch (GET_CODE (x))
3440 if (GET_CODE (x) != REG)
3446 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3452 if (GET_CODE (x0) != REG
3453 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3454 || GET_CODE (x1) != PLUS
3455 || ! rtx_equal_p (x0, XEXP (x1, 0))
3456 || GET_CODE (XEXP (x1, 1)) != REG
3457 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3464 /* 12-bit immediate */
3469 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3471 /* If we can't use load/store double operations, make sure we can
3472 address the second word. */
3473 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3474 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3483 if (GET_CODE (x0) == SUBREG)
3484 x0 = SUBREG_REG (x0);
3486 if (GET_CODE (x0) != REG)
3489 regno0 = REGNO (x0);
3490 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3493 switch (GET_CODE (x1))
3499 x1 = SUBREG_REG (x1);
3500 if (GET_CODE (x1) != REG)
3506 /* Do not allow reg+reg addressing for modes > 1 word if we
3507 can't depend on having move double instructions. */
3508 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3511 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3515 /* 12-bit immediate */
3520 value = INTVAL (x1);
3521 ret = IN_RANGE_P (value, -2048, 2047);
3523 /* If we can't use load/store double operations, make sure we can
3524 address the second word. */
3525 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3526 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3531 if (!condexec_p && got12_operand (x1, VOIDmode))
3539 if (TARGET_DEBUG_ADDR)
3541 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3542 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3543 (condexec_p) ? ", inside conditional code" : "");
3551 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3553 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3556 /* Given an ADDR, generate code to inline the PLT. */
3558 gen_inlined_tls_plt (rtx addr)
3561 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3564 dest = gen_reg_rtx (DImode);
3571 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3572 calll #gettlsoff(ADDR)@(gr8, gr0)
3574 emit_insn (gen_tls_lddi (dest, addr, picreg));
3581 sethi.p #gottlsdeschi(ADDR), gr8
3582 setlo #gottlsdesclo(ADDR), gr8
3583 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3584 calll #gettlsoff(ADDR)@(gr8, gr0)
3586 rtx reguse = gen_reg_rtx (Pmode);
3587 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3588 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3591 retval = gen_reg_rtx (Pmode);
3592 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3596 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3597 the destination address. */
3599 gen_tlsmoff (rtx addr, rtx reg)
3601 rtx dest = gen_reg_rtx (Pmode);
3605 /* sethi.p #tlsmoffhi(x), grA
3606 setlo #tlsmofflo(x), grA
3608 dest = gen_reg_rtx (Pmode);
3609 emit_insn (gen_tlsoff_hilo (dest, addr,
3610 GEN_INT (R_FRV_TLSMOFFHI)));
3611 dest = gen_rtx_PLUS (Pmode, dest, reg);
3615 /* addi grB, #tlsmoff12(x), grC
3617 ld/st @(grB, #tlsmoff12(x)), grC
3619 dest = gen_reg_rtx (Pmode);
3620 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3621 GEN_INT (R_FRV_TLSMOFF12)));
3626 /* Generate code for a TLS address. */
3628 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3630 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3631 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3635 case TLS_MODEL_INITIAL_EXEC:
3639 ldi @(gr15, #gottlsoff12(x)), gr5
3641 dest = gen_reg_rtx (Pmode);
3642 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3643 dest = gen_rtx_PLUS (Pmode, tp, dest);
3647 /* -fPIC or anything else.
3649 sethi.p #gottlsoffhi(x), gr14
3650 setlo #gottlsofflo(x), gr14
3651 ld #tlsoff(x)@(gr15, gr14), gr9
3653 rtx tmp = gen_reg_rtx (Pmode);
3654 dest = gen_reg_rtx (Pmode);
3655 emit_insn (gen_tlsoff_hilo (tmp, addr,
3656 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3658 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3659 dest = gen_rtx_PLUS (Pmode, tp, dest);
3662 case TLS_MODEL_LOCAL_DYNAMIC:
3666 if (TARGET_INLINE_PLT)
3667 retval = gen_inlined_tls_plt (GEN_INT (0));
3670 /* call #gettlsoff(0) */
3671 retval = gen_reg_rtx (Pmode);
3672 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3675 reg = gen_reg_rtx (Pmode);
3676 emit_insn (gen_rtx_SET (VOIDmode, reg,
3677 gen_rtx_PLUS (Pmode,
3680 dest = gen_tlsmoff (addr, reg);
3683 dest = gen_reg_rtx (Pmode);
3684 emit_insn (gen_tlsoff_hilo (dest, addr,
3685 GEN_INT (R_FRV_TLSMOFFHI)));
3686 dest = gen_rtx_PLUS (Pmode, dest, reg);
3690 case TLS_MODEL_LOCAL_EXEC:
3691 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3693 case TLS_MODEL_GLOBAL_DYNAMIC:
3697 if (TARGET_INLINE_PLT)
3698 retval = gen_inlined_tls_plt (addr);
3701 /* call #gettlsoff(x) */
3702 retval = gen_reg_rtx (Pmode);
3703 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3705 dest = gen_rtx_PLUS (Pmode, retval, tp);
3716 frv_legitimize_address (rtx x,
3717 rtx oldx ATTRIBUTE_UNUSED,
3718 enum machine_mode mode ATTRIBUTE_UNUSED)
3720 if (GET_CODE (x) == SYMBOL_REF)
3722 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3724 return frv_legitimize_tls_address (x, model);
3730 /* Test whether a local function descriptor is canonical, i.e.,
3731 whether we can use FUNCDESC_GOTOFF to compute the address of the
3735 frv_local_funcdesc_p (rtx fnx)
3738 enum symbol_visibility vis;
3741 if (! SYMBOL_REF_LOCAL_P (fnx))
3744 fn = SYMBOL_REF_DECL (fnx);
3749 vis = DECL_VISIBILITY (fn);
3751 if (vis == VISIBILITY_PROTECTED)
3752 /* Private function descriptors for protected functions are not
3753 canonical. Temporarily change the visibility to global. */
3754 vis = VISIBILITY_DEFAULT;
3755 else if (flag_shlib)
3756 /* If we're already compiling for a shared library (that, unlike
3757 executables, can't assume that the existence of a definition
3758 implies local binding), we can skip the re-testing. */
3761 ret = default_binds_local_p_1 (fn, flag_pic);
3763 DECL_VISIBILITY (fn) = vis;
3768 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3772 frv_gen_GPsym2reg (rtx dest, rtx src)
3774 tree gp = get_identifier ("_gp");
3775 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3777 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3781 unspec_got_name (int i)
3785 case R_FRV_GOT12: return "got12";
3786 case R_FRV_GOTHI: return "gothi";
3787 case R_FRV_GOTLO: return "gotlo";
3788 case R_FRV_FUNCDESC: return "funcdesc";
3789 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3790 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3791 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3792 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3793 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3794 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3795 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3796 case R_FRV_GOTOFF12: return "gotoff12";
3797 case R_FRV_GOTOFFHI: return "gotoffhi";
3798 case R_FRV_GOTOFFLO: return "gotofflo";
3799 case R_FRV_GPREL12: return "gprel12";
3800 case R_FRV_GPRELHI: return "gprelhi";
3801 case R_FRV_GPRELLO: return "gprello";
3802 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3803 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3804 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3805 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3806 case R_FRV_TLSMOFF12: return "tlsmoff12";
3807 case R_FRV_TLSDESCHI: return "tlsdeschi";
3808 case R_FRV_TLSDESCLO: return "tlsdesclo";
3809 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3810 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3811 default: gcc_unreachable ();
3815 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3816 is added inside the relocation operator. */
3819 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3821 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3822 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3823 fputs (")", stream);
3826 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3827 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3828 otherwise return ORIG_X. */
3831 frv_find_base_term (rtx x)
3833 struct frv_unspec unspec;
3835 if (frv_const_unspec_p (x, &unspec)
3836 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3837 return plus_constant (unspec.symbol, unspec.offset);
3842 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3843 the operand is used by a predicated instruction. */
3846 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3848 return ((GET_MODE (op) == mode || mode == VOIDmode)
3849 && GET_CODE (op) == MEM
3850 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3851 reload_completed, condexec_p, FALSE));
3855 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3857 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3858 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3864 rvrtx = operands[0];
3868 addr = XEXP (operands[0], 0);
3870 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3871 any calls that would involve a PLT, but can't tell, since we
3872 don't know whether an extern function is going to be provided by
3873 a separate translation unit or imported from a separate module.
3874 When compiling for shared libraries, if the function has default
3875 visibility, we assume it's overridable, so we inline the PLT, but
3876 for executables, we don't really have a way to make a good
3877 decision: a function is as likely to be imported from a shared
3878 library as it is to be defined in the executable itself. We
3879 assume executables will get global functions defined locally,
3880 whereas shared libraries will have them potentially overridden,
3881 so we only inline PLTs when compiling for shared libraries.
3883 In order to mark a function as local to a shared library, any
3884 non-default visibility attribute suffices. Unfortunately,
3885 there's no simple way to tag a function declaration as ``in a
3886 different module'', which we could then use to trigger PLT
3887 inlining on executables. There's -minline-plt, but it affects
3888 all external functions, so one would have to also mark function
3889 declarations available in the same module with non-default
3890 visibility, which is advantageous in itself. */
3891 if (GET_CODE (addr) == SYMBOL_REF
3892 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3896 dest = gen_reg_rtx (SImode);
3898 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3899 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3901 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3902 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3904 crtl->uses_pic_offset_table = TRUE;
3907 else if (GET_CODE (addr) == SYMBOL_REF)
3909 /* These are always either local, or handled through a local
3912 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3913 operands[2], picreg, lr);
3915 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3919 else if (! ldd_address_operand (addr, Pmode))
3920 addr = force_reg (Pmode, addr);
3922 picreg = gen_reg_rtx (DImode);
3923 emit_insn (gen_movdi_ldd (picreg, addr));
3925 if (sibcall && ret_value)
3926 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3928 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3930 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3932 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3936 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3937 process these separately from any offsets, such that we add any
3938 offsets to the function descriptor (the actual pointer), not to the
3939 function address. */
3942 frv_function_symbol_referenced_p (rtx x)
3948 if (GET_CODE (x) == SYMBOL_REF)
3949 return SYMBOL_REF_FUNCTION_P (x);
3951 length = GET_RTX_LENGTH (GET_CODE (x));
3952 format = GET_RTX_FORMAT (GET_CODE (x));
3954 for (j = 0; j < length; ++j)
3959 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3965 if (XVEC (x, j) != 0)
3968 for (k = 0; k < XVECLEN (x, j); ++k)
3969 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3975 /* Nothing to do. */
3983 /* Return true if the memory operand is one that can be conditionally
3987 condexec_memory_operand (rtx op, enum machine_mode mode)
3989 enum machine_mode op_mode = GET_MODE (op);
3992 if (mode != VOIDmode && op_mode != mode)
4007 if (GET_CODE (op) != MEM)
4010 addr = XEXP (op, 0);
4011 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
4014 /* Return true if the bare return instruction can be used outside of the
4015 epilog code. For frv, we only do it if there was no stack allocation. */
4018 direct_return_p (void)
4022 if (!reload_completed)
4025 info = frv_stack_info ();
4026 return (info->total_size == 0);
4031 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
4033 if (GET_CODE (src) == SYMBOL_REF)
4035 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
4037 src = frv_legitimize_tls_address (src, model);
4043 if (frv_emit_movsi (dest, src))
4052 if (!reload_in_progress
4053 && !reload_completed
4054 && !register_operand (dest, mode)
4055 && !reg_or_0_operand (src, mode))
4056 src = copy_to_mode_reg (mode, src);
4063 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4066 /* Emit code to handle a MOVSI, adding in the small data register or pic
4067 register if needed to load up addresses. Return TRUE if the appropriate
4068 instructions are emitted. */
4071 frv_emit_movsi (rtx dest, rtx src)
4073 int base_regno = -1;
4076 struct frv_unspec old_unspec;
4078 if (!reload_in_progress
4079 && !reload_completed
4080 && !register_operand (dest, SImode)
4081 && (!reg_or_0_operand (src, SImode)
4082 /* Virtual registers will almost always be replaced by an
4083 add instruction, so expose this to CSE by copying to
4084 an intermediate register. */
4085 || (GET_CODE (src) == REG
4086 && IN_RANGE_P (REGNO (src),
4087 FIRST_VIRTUAL_REGISTER,
4088 LAST_VIRTUAL_REGISTER))))
4090 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4094 /* Explicitly add in the PIC or small data register if needed. */
4095 switch (GET_CODE (src))
4104 /* Using GPREL12, we use a single GOT entry for all symbols
4105 in read-only sections, but trade sequences such as:
4107 sethi #gothi(label), gr#
4108 setlo #gotlo(label), gr#
4113 ld @(gr15,#got12(_gp)), gr#
4114 sethi #gprelhi(label), gr##
4115 setlo #gprello(label), gr##
4118 We may often be able to share gr# for multiple
4119 computations of GPREL addresses, and we may often fold
4120 the final add into the pair of registers of a load or
4121 store instruction, so it's often profitable. Even when
4122 optimizing for size, we're trading a GOT entry for an
4123 additional instruction, which trades GOT space
4124 (read-write) for code size (read-only, shareable), as
4125 long as the symbol is not used in more than two different
4128 With -fpie/-fpic, we'd be trading a single load for a
4129 sequence of 4 instructions, because the offset of the
4130 label can't be assumed to be addressable with 12 bits, so
4131 we don't do this. */
4132 if (TARGET_GPREL_RO)
4133 unspec = R_FRV_GPREL12;
4135 unspec = R_FRV_GOT12;
4138 base_regno = PIC_REGNO;
4143 if (frv_const_unspec_p (src, &old_unspec))
4146 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4149 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4150 emit_move_insn (dest, src);
4155 sym = XEXP (sym, 0);
4156 if (GET_CODE (sym) == PLUS
4157 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4158 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4159 sym = XEXP (sym, 0);
4160 if (GET_CODE (sym) == SYMBOL_REF)
4162 else if (GET_CODE (sym) == LABEL_REF)
4165 goto handle_whatever;
4173 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4177 src = frv_legitimize_tls_address (src, model);
4178 emit_move_insn (dest, src);
4182 if (SYMBOL_REF_FUNCTION_P (sym))
4184 if (frv_local_funcdesc_p (sym))
4185 unspec = R_FRV_FUNCDESC_GOTOFF12;
4187 unspec = R_FRV_FUNCDESC_GOT12;
4191 if (CONSTANT_POOL_ADDRESS_P (sym))
4192 switch (GET_CODE (get_pool_constant (sym)))
4199 unspec = R_FRV_GOTOFF12;
4204 if (TARGET_GPREL_RO)
4205 unspec = R_FRV_GPREL12;
4207 unspec = R_FRV_GOT12;
4210 else if (SYMBOL_REF_LOCAL_P (sym)
4211 && !SYMBOL_REF_EXTERNAL_P (sym)
4212 && SYMBOL_REF_DECL (sym)
4213 && (!DECL_P (SYMBOL_REF_DECL (sym))
4214 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4216 tree decl = SYMBOL_REF_DECL (sym);
4217 tree init = TREE_CODE (decl) == VAR_DECL
4218 ? DECL_INITIAL (decl)
4219 : TREE_CODE (decl) == CONSTRUCTOR
4222 bool named_section, readonly;
4224 if (init && init != error_mark_node)
4225 reloc = compute_reloc_for_constant (init);
4227 named_section = TREE_CODE (decl) == VAR_DECL
4228 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4229 readonly = decl_readonly_section (decl, reloc);
4232 unspec = R_FRV_GOT12;
4234 unspec = R_FRV_GOTOFF12;
4235 else if (readonly && TARGET_GPREL_RO)
4236 unspec = R_FRV_GPREL12;
4238 unspec = R_FRV_GOT12;
4241 unspec = R_FRV_GOT12;
4245 else if (SYMBOL_REF_SMALL_P (sym))
4246 base_regno = SDA_BASE_REG;
4249 base_regno = PIC_REGNO;
4254 if (base_regno >= 0)
4256 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4257 emit_insn (gen_symGOTOFF2reg (dest, src,
4258 gen_rtx_REG (Pmode, base_regno),
4259 GEN_INT (R_FRV_GPREL12)));
4261 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4262 gen_rtx_REG (Pmode, base_regno),
4263 GEN_INT (R_FRV_GPREL12)));
4264 if (base_regno == PIC_REGNO)
4265 crtl->uses_pic_offset_table = TRUE;
4273 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4274 new uses of it once reload has begun. */
4275 gcc_assert (!reload_in_progress && !reload_completed);
4279 case R_FRV_GOTOFF12:
4280 if (!frv_small_data_reloc_p (sym, unspec))
4281 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4284 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4287 if (!frv_small_data_reloc_p (sym, unspec))
4288 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4291 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4293 case R_FRV_FUNCDESC_GOTOFF12:
4295 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4298 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4302 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4305 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4309 crtl->uses_pic_offset_table = TRUE;
4318 /* Return a string to output a single word move. */
4321 output_move_single (rtx operands[], rtx insn)
4323 rtx dest = operands[0];
4324 rtx src = operands[1];
4326 if (GET_CODE (dest) == REG)
4328 int dest_regno = REGNO (dest);
4329 enum machine_mode mode = GET_MODE (dest);
4331 if (GPR_P (dest_regno))
4333 if (GET_CODE (src) == REG)
4335 /* gpr <- some sort of register */
4336 int src_regno = REGNO (src);
4338 if (GPR_P (src_regno))
4339 return "mov %1, %0";
4341 else if (FPR_P (src_regno))
4342 return "movfg %1, %0";
4344 else if (SPR_P (src_regno))
4345 return "movsg %1, %0";
4348 else if (GET_CODE (src) == MEM)
4357 return "ldsb%I1%U1 %M1,%0";
4360 return "ldsh%I1%U1 %M1,%0";
4364 return "ld%I1%U1 %M1, %0";
4368 else if (GET_CODE (src) == CONST_INT
4369 || GET_CODE (src) == CONST_DOUBLE)
4371 /* gpr <- integer/floating constant */
4372 HOST_WIDE_INT value;
4374 if (GET_CODE (src) == CONST_INT)
4375 value = INTVAL (src);
4377 else if (mode == SFmode)
4382 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4383 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4388 value = CONST_DOUBLE_LOW (src);
4390 if (IN_RANGE_P (value, -32768, 32767))
4391 return "setlos %1, %0";
4396 else if (GET_CODE (src) == SYMBOL_REF
4397 || GET_CODE (src) == LABEL_REF
4398 || GET_CODE (src) == CONST)
4404 else if (FPR_P (dest_regno))
4406 if (GET_CODE (src) == REG)
4408 /* fpr <- some sort of register */
4409 int src_regno = REGNO (src);
4411 if (GPR_P (src_regno))
4412 return "movgf %1, %0";
4414 else if (FPR_P (src_regno))
4416 if (TARGET_HARD_FLOAT)
4417 return "fmovs %1, %0";
4419 return "mor %1, %1, %0";
4423 else if (GET_CODE (src) == MEM)
4432 return "ldbf%I1%U1 %M1,%0";
4435 return "ldhf%I1%U1 %M1,%0";
4439 return "ldf%I1%U1 %M1, %0";
4443 else if (ZERO_P (src))
4444 return "movgf %., %0";
4447 else if (SPR_P (dest_regno))
4449 if (GET_CODE (src) == REG)
4451 /* spr <- some sort of register */
4452 int src_regno = REGNO (src);
4454 if (GPR_P (src_regno))
4455 return "movgs %1, %0";
4457 else if (ZERO_P (src))
4458 return "movgs %., %0";
4462 else if (GET_CODE (dest) == MEM)
4464 if (GET_CODE (src) == REG)
4466 int src_regno = REGNO (src);
4467 enum machine_mode mode = GET_MODE (dest);
4469 if (GPR_P (src_regno))
4477 return "stb%I0%U0 %1, %M0";
4480 return "sth%I0%U0 %1, %M0";
4484 return "st%I0%U0 %1, %M0";
4488 else if (FPR_P (src_regno))
4496 return "stbf%I0%U0 %1, %M0";
4499 return "sthf%I0%U0 %1, %M0";
4503 return "stf%I0%U0 %1, %M0";
4508 else if (ZERO_P (src))
4510 switch (GET_MODE (dest))
4516 return "stb%I0%U0 %., %M0";
4519 return "sth%I0%U0 %., %M0";
4523 return "st%I0%U0 %., %M0";
4528 fatal_insn ("bad output_move_single operand", insn);
4533 /* Return a string to output a double word move. */
4536 output_move_double (rtx operands[], rtx insn)
4538 rtx dest = operands[0];
4539 rtx src = operands[1];
4540 enum machine_mode mode = GET_MODE (dest);
4542 if (GET_CODE (dest) == REG)
4544 int dest_regno = REGNO (dest);
4546 if (GPR_P (dest_regno))
4548 if (GET_CODE (src) == REG)
4550 /* gpr <- some sort of register */
4551 int src_regno = REGNO (src);
4553 if (GPR_P (src_regno))
4556 else if (FPR_P (src_regno))
4558 if (((dest_regno - GPR_FIRST) & 1) == 0
4559 && ((src_regno - FPR_FIRST) & 1) == 0)
4560 return "movfgd %1, %0";
4566 else if (GET_CODE (src) == MEM)
4569 if (dbl_memory_one_insn_operand (src, mode))
4570 return "ldd%I1%U1 %M1, %0";
4575 else if (GET_CODE (src) == CONST_INT
4576 || GET_CODE (src) == CONST_DOUBLE)
4580 else if (FPR_P (dest_regno))
4582 if (GET_CODE (src) == REG)
4584 /* fpr <- some sort of register */
4585 int src_regno = REGNO (src);
4587 if (GPR_P (src_regno))
4589 if (((dest_regno - FPR_FIRST) & 1) == 0
4590 && ((src_regno - GPR_FIRST) & 1) == 0)
4591 return "movgfd %1, %0";
4596 else if (FPR_P (src_regno))
4599 && ((dest_regno - FPR_FIRST) & 1) == 0
4600 && ((src_regno - FPR_FIRST) & 1) == 0)
4601 return "fmovd %1, %0";
4607 else if (GET_CODE (src) == MEM)
4610 if (dbl_memory_one_insn_operand (src, mode))
4611 return "lddf%I1%U1 %M1, %0";
4616 else if (ZERO_P (src))
4621 else if (GET_CODE (dest) == MEM)
4623 if (GET_CODE (src) == REG)
4625 int src_regno = REGNO (src);
4627 if (GPR_P (src_regno))
4629 if (((src_regno - GPR_FIRST) & 1) == 0
4630 && dbl_memory_one_insn_operand (dest, mode))
4631 return "std%I0%U0 %1, %M0";
4636 if (FPR_P (src_regno))
4638 if (((src_regno - FPR_FIRST) & 1) == 0
4639 && dbl_memory_one_insn_operand (dest, mode))
4640 return "stdf%I0%U0 %1, %M0";
4646 else if (ZERO_P (src))
4648 if (dbl_memory_one_insn_operand (dest, mode))
4649 return "std%I0%U0 %., %M0";
4655 fatal_insn ("bad output_move_double operand", insn);
4660 /* Return a string to output a single word conditional move.
4661 Operand0 -- EQ/NE of ccr register and 0
4662 Operand1 -- CCR register
4663 Operand2 -- destination
4664 Operand3 -- source */
4667 output_condmove_single (rtx operands[], rtx insn)
4669 rtx dest = operands[2];
4670 rtx src = operands[3];
4672 if (GET_CODE (dest) == REG)
4674 int dest_regno = REGNO (dest);
4675 enum machine_mode mode = GET_MODE (dest);
4677 if (GPR_P (dest_regno))
4679 if (GET_CODE (src) == REG)
4681 /* gpr <- some sort of register */
4682 int src_regno = REGNO (src);
4684 if (GPR_P (src_regno))
4685 return "cmov %z3, %2, %1, %e0";
4687 else if (FPR_P (src_regno))
4688 return "cmovfg %3, %2, %1, %e0";
4691 else if (GET_CODE (src) == MEM)
4700 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4703 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4707 return "cld%I3%U3 %M3, %2, %1, %e0";
4711 else if (ZERO_P (src))
4712 return "cmov %., %2, %1, %e0";
4715 else if (FPR_P (dest_regno))
4717 if (GET_CODE (src) == REG)
4719 /* fpr <- some sort of register */
4720 int src_regno = REGNO (src);
4722 if (GPR_P (src_regno))
4723 return "cmovgf %3, %2, %1, %e0";
4725 else if (FPR_P (src_regno))
4727 if (TARGET_HARD_FLOAT)
4728 return "cfmovs %3,%2,%1,%e0";
4730 return "cmor %3, %3, %2, %1, %e0";
4734 else if (GET_CODE (src) == MEM)
4737 if (mode == SImode || mode == SFmode)
4738 return "cldf%I3%U3 %M3, %2, %1, %e0";
4741 else if (ZERO_P (src))
4742 return "cmovgf %., %2, %1, %e0";
4746 else if (GET_CODE (dest) == MEM)
4748 if (GET_CODE (src) == REG)
4750 int src_regno = REGNO (src);
4751 enum machine_mode mode = GET_MODE (dest);
4753 if (GPR_P (src_regno))
4761 return "cstb%I2%U2 %3, %M2, %1, %e0";
4764 return "csth%I2%U2 %3, %M2, %1, %e0";
4768 return "cst%I2%U2 %3, %M2, %1, %e0";
4772 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4773 return "cstf%I2%U2 %3, %M2, %1, %e0";
4776 else if (ZERO_P (src))
4778 enum machine_mode mode = GET_MODE (dest);
4785 return "cstb%I2%U2 %., %M2, %1, %e0";
4788 return "csth%I2%U2 %., %M2, %1, %e0";
4792 return "cst%I2%U2 %., %M2, %1, %e0";
4797 fatal_insn ("bad output_condmove_single operand", insn);
4802 /* Emit the appropriate code to do a comparison, returning the register the
4803 comparison was done it. */
4806 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4808 enum machine_mode cc_mode;
4811 /* Floating point doesn't have comparison against a constant. */
4812 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4813 op1 = force_reg (GET_MODE (op0), op1);
4815 /* Possibly disable using anything but a fixed register in order to work
4816 around cse moving comparisons past function calls. */
4817 cc_mode = SELECT_CC_MODE (test, op0, op1);
4818 cc_reg = ((TARGET_ALLOC_CC)
4819 ? gen_reg_rtx (cc_mode)
4820 : gen_rtx_REG (cc_mode,
4821 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4823 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4824 gen_rtx_COMPARE (cc_mode, op0, op1)));
4830 /* Emit code for a conditional branch.
4831 XXX: I originally wanted to add a clobber of a CCR register to use in
4832 conditional execution, but that confuses the rest of the compiler. */
4835 frv_emit_cond_branch (rtx operands[])
4840 enum rtx_code test = GET_CODE (operands[0]);
4841 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4842 enum machine_mode cc_mode = GET_MODE (cc_reg);
4844 /* Branches generate:
4846 (if_then_else (<test>, <cc_reg>, (const_int 0))
4847 (label_ref <branch_label>)
4849 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4850 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4851 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4852 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4857 /* Emit code to set a gpr to 1/0 based on a comparison. */
4860 frv_emit_scc (rtx operands[])
4866 enum rtx_code test = GET_CODE (operands[1]);
4867 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4869 /* SCC instructions generate:
4870 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4871 (clobber (<ccr_reg>))]) */
4872 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4873 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4875 cr_reg = ((TARGET_ALLOC_CC)
4876 ? gen_reg_rtx (CC_CCRmode)
4877 : gen_rtx_REG (CC_CCRmode,
4878 ((GET_MODE (cc_reg) == CC_FPmode)
4882 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4883 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4888 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4889 the separate insns. */
4892 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4898 /* Set the appropriate CCR bit. */
4899 emit_insn (gen_rtx_SET (VOIDmode,
4901 gen_rtx_fmt_ee (GET_CODE (test),
4906 /* Move the value into the destination. */
4907 emit_move_insn (dest, GEN_INT (value));
4909 /* Move 0 into the destination if the test failed */
4910 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4911 gen_rtx_EQ (GET_MODE (cr_reg),
4914 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4916 /* Finish up, return sequence. */
4923 /* Emit the code for a conditional move, return TRUE if we could do the
4927 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4934 enum rtx_code test = GET_CODE (test_rtx);
4935 rtx cc_reg = frv_emit_comparison (test,
4936 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4937 enum machine_mode cc_mode = GET_MODE (cc_reg);
4939 /* Conditional move instructions generate:
4940 (parallel [(set <target>
4941 (if_then_else (<test> <cc_reg> (const_int 0))
4944 (clobber (<ccr_reg>))]) */
4946 /* Handle various cases of conditional move involving two constants. */
4947 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4949 HOST_WIDE_INT value1 = INTVAL (src1);
4950 HOST_WIDE_INT value2 = INTVAL (src2);
4952 /* Having 0 as one of the constants can be done by loading the other
4953 constant, and optionally moving in gr0. */
4954 if (value1 == 0 || value2 == 0)
4957 /* If the first value is within an addi range and also the difference
4958 between the two fits in an addi's range, load up the difference, then
4959 conditionally move in 0, and then unconditionally add the first
4961 else if (IN_RANGE_P (value1, -2048, 2047)
4962 && IN_RANGE_P (value2 - value1, -2048, 2047))
4965 /* If neither condition holds, just force the constant into a
4969 src1 = force_reg (GET_MODE (dest), src1);
4970 src2 = force_reg (GET_MODE (dest), src2);
4974 /* If one value is a register, insure the other value is either 0 or a
4978 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4979 src1 = force_reg (GET_MODE (dest), src1);
4981 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4982 src2 = force_reg (GET_MODE (dest), src2);
4985 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4986 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4988 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4990 cr_reg = ((TARGET_ALLOC_CC)
4991 ? gen_reg_rtx (CC_CCRmode)
4992 : gen_rtx_REG (CC_CCRmode,
4993 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4995 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4996 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
5001 /* Split a conditional move into constituent parts, returning a SEQUENCE
5002 containing all of the insns. */
5005 frv_split_cond_move (rtx operands[])
5007 rtx dest = operands[0];
5008 rtx test = operands[1];
5009 rtx cc_reg = operands[2];
5010 rtx src1 = operands[3];
5011 rtx src2 = operands[4];
5012 rtx cr_reg = operands[5];
5014 enum machine_mode cr_mode = GET_MODE (cr_reg);
5018 /* Set the appropriate CCR bit. */
5019 emit_insn (gen_rtx_SET (VOIDmode,
5021 gen_rtx_fmt_ee (GET_CODE (test),
5026 /* Handle various cases of conditional move involving two constants. */
5027 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
5029 HOST_WIDE_INT value1 = INTVAL (src1);
5030 HOST_WIDE_INT value2 = INTVAL (src2);
5032 /* Having 0 as one of the constants can be done by loading the other
5033 constant, and optionally moving in gr0. */
5036 emit_move_insn (dest, src2);
5037 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5038 gen_rtx_NE (cr_mode, cr_reg,
5040 gen_rtx_SET (VOIDmode, dest, src1)));
5043 else if (value2 == 0)
5045 emit_move_insn (dest, src1);
5046 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5047 gen_rtx_EQ (cr_mode, cr_reg,
5049 gen_rtx_SET (VOIDmode, dest, src2)));
5052 /* If the first value is within an addi range and also the difference
5053 between the two fits in an addi's range, load up the difference, then
5054 conditionally move in 0, and then unconditionally add the first
5056 else if (IN_RANGE_P (value1, -2048, 2047)
5057 && IN_RANGE_P (value2 - value1, -2048, 2047))
5059 rtx dest_si = ((GET_MODE (dest) == SImode)
5061 : gen_rtx_SUBREG (SImode, dest, 0));
5063 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5064 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5065 gen_rtx_NE (cr_mode, cr_reg,
5067 gen_rtx_SET (VOIDmode, dest_si,
5069 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5077 /* Emit the conditional move for the test being true if needed. */
5078 if (! rtx_equal_p (dest, src1))
5079 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5080 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5081 gen_rtx_SET (VOIDmode, dest, src1)));
5083 /* Emit the conditional move for the test being false if needed. */
5084 if (! rtx_equal_p (dest, src2))
5085 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5086 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5087 gen_rtx_SET (VOIDmode, dest, src2)));
5090 /* Finish up, return sequence. */
5097 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5098 memory location that is not known to be dword-aligned. */
5100 frv_split_double_load (rtx dest, rtx source)
5102 int regno = REGNO (dest);
5103 rtx dest1 = gen_highpart (SImode, dest);
5104 rtx dest2 = gen_lowpart (SImode, dest);
5105 rtx address = XEXP (source, 0);
5107 /* If the address is pre-modified, load the lower-numbered register
5108 first, then load the other register using an integer offset from
5109 the modified base register. This order should always be safe,
5110 since the pre-modification cannot affect the same registers as the
5113 The situation for other loads is more complicated. Loading one
5114 of the registers could affect the value of ADDRESS, so we must
5115 be careful which order we do them in. */
5116 if (GET_CODE (address) == PRE_MODIFY
5117 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5119 /* It is safe to load the lower-numbered register first. */
5120 emit_move_insn (dest1, change_address (source, SImode, NULL));
5121 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5125 /* ADDRESS is not pre-modified and the address depends on the
5126 lower-numbered register. Load the higher-numbered register
5128 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5129 emit_move_insn (dest1, change_address (source, SImode, NULL));
5133 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5134 and SOURCE is either a double register or the constant zero. */
5136 frv_split_double_store (rtx dest, rtx source)
5138 rtx dest1 = change_address (dest, SImode, NULL);
5139 rtx dest2 = frv_index_memory (dest, SImode, 1);
5140 if (ZERO_P (source))
5142 emit_move_insn (dest1, CONST0_RTX (SImode));
5143 emit_move_insn (dest2, CONST0_RTX (SImode));
5147 emit_move_insn (dest1, gen_highpart (SImode, source));
5148 emit_move_insn (dest2, gen_lowpart (SImode, source));
5153 /* Split a min/max operation returning a SEQUENCE containing all of the
5157 frv_split_minmax (rtx operands[])
5159 rtx dest = operands[0];
5160 rtx minmax = operands[1];
5161 rtx src1 = operands[2];
5162 rtx src2 = operands[3];
5163 rtx cc_reg = operands[4];
5164 rtx cr_reg = operands[5];
5166 enum rtx_code test_code;
5167 enum machine_mode cr_mode = GET_MODE (cr_reg);
5171 /* Figure out which test to use. */
5172 switch (GET_CODE (minmax))
5177 case SMIN: test_code = LT; break;
5178 case SMAX: test_code = GT; break;
5179 case UMIN: test_code = LTU; break;
5180 case UMAX: test_code = GTU; break;
5183 /* Issue the compare instruction. */
5184 emit_insn (gen_rtx_SET (VOIDmode,
5186 gen_rtx_COMPARE (GET_MODE (cc_reg),
5189 /* Set the appropriate CCR bit. */
5190 emit_insn (gen_rtx_SET (VOIDmode,
5192 gen_rtx_fmt_ee (test_code,
5197 /* If are taking the min/max of a nonzero constant, load that first, and
5198 then do a conditional move of the other value. */
5199 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5201 gcc_assert (!rtx_equal_p (dest, src1));
5203 emit_move_insn (dest, src2);
5204 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5205 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5206 gen_rtx_SET (VOIDmode, dest, src1)));
5209 /* Otherwise, do each half of the move. */
5212 /* Emit the conditional move for the test being true if needed. */
5213 if (! rtx_equal_p (dest, src1))
5214 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5215 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5216 gen_rtx_SET (VOIDmode, dest, src1)));
5218 /* Emit the conditional move for the test being false if needed. */
5219 if (! rtx_equal_p (dest, src2))
5220 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5221 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5222 gen_rtx_SET (VOIDmode, dest, src2)));
5225 /* Finish up, return sequence. */
5232 /* Split an integer abs operation returning a SEQUENCE containing all of the
5236 frv_split_abs (rtx operands[])
5238 rtx dest = operands[0];
5239 rtx src = operands[1];
5240 rtx cc_reg = operands[2];
5241 rtx cr_reg = operands[3];
5246 /* Issue the compare < 0 instruction. */
5247 emit_insn (gen_rtx_SET (VOIDmode,
5249 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5251 /* Set the appropriate CCR bit. */
5252 emit_insn (gen_rtx_SET (VOIDmode,
5254 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5256 /* Emit the conditional negate if the value is negative. */
5257 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5258 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5259 gen_negsi2 (dest, src)));
5261 /* Emit the conditional move for the test being false if needed. */
5262 if (! rtx_equal_p (dest, src))
5263 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5264 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5265 gen_rtx_SET (VOIDmode, dest, src)));
5267 /* Finish up, return sequence. */
5274 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5275 register used in an insn. */
5278 frv_clear_registers_used (rtx *ptr, void *data)
5280 if (GET_CODE (*ptr) == REG)
5282 int regno = REGNO (*ptr);
5283 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5285 if (regno < FIRST_PSEUDO_REGISTER)
5287 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5289 while (regno < reg_max)
5291 CLEAR_HARD_REG_BIT (*p_regs, regno);
5301 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5303 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5304 initialize the static storage. */
5306 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5308 frv_ifcvt.added_insns_list = NULL_RTX;
5309 frv_ifcvt.cur_scratch_regs = 0;
5310 frv_ifcvt.num_nested_cond_exec = 0;
5311 frv_ifcvt.cr_reg = NULL_RTX;
5312 frv_ifcvt.nested_cc_reg = NULL_RTX;
5313 frv_ifcvt.extra_int_cr = NULL_RTX;
5314 frv_ifcvt.extra_fp_cr = NULL_RTX;
5315 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5319 /* Internal function to add a potential insn to the list of insns to be inserted
5320 if the conditional execution conversion is successful. */
5323 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5325 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5327 link->jump = before_p; /* Mark to add this before or after insn. */
5328 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5329 frv_ifcvt.added_insns_list);
5331 if (TARGET_DEBUG_COND_EXEC)
5334 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5335 (before_p) ? "before" : "after",
5336 (int)INSN_UID (insn));
5338 debug_rtx (pattern);
5343 /* A C expression to modify the code described by the conditional if
5344 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5345 FALSE_EXPR for converting if-then and if-then-else code to conditional
5346 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5347 tests cannot be converted. */
5350 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5352 basic_block test_bb = ce_info->test_bb; /* test basic block */
5353 basic_block then_bb = ce_info->then_bb; /* THEN */
5354 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5355 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5356 rtx true_expr = *p_true;
5360 enum machine_mode mode = GET_MODE (true_expr);
5364 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5366 rtx sub_cond_exec_reg;
5368 enum rtx_code code_true;
5369 enum rtx_code code_false;
5370 enum reg_class cc_class;
5371 enum reg_class cr_class;
5374 reg_set_iterator rsi;
5376 /* Make sure we are only dealing with hard registers. Also honor the
5377 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5379 if (!reload_completed || !TARGET_COND_EXEC
5380 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5383 /* Figure out which registers we can allocate for our own purposes. Only
5384 consider registers that are not preserved across function calls and are
5385 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5386 if we did not need to use them in reloading other registers. */
5387 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5388 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5389 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5390 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5391 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5393 /* If this is a nested IF, we need to discover whether the CC registers that
5394 are set/used inside of the block are used anywhere else. If not, we can
5395 change them to be the CC register that is paired with the CR register that
5396 controls the outermost IF block. */
5397 if (ce_info->pass > 1)
5399 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5400 for (j = CC_FIRST; j <= CC_LAST; j++)
5401 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5403 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5407 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5411 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5414 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5418 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5419 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5421 frv_ifcvt.added_insns_list = NULL_RTX;
5422 frv_ifcvt.cur_scratch_regs = 0;
5424 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5425 * sizeof (basic_block));
5431 /* Remove anything live at the beginning of the join block from being
5432 available for allocation. */
5433 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5435 if (regno < FIRST_PSEUDO_REGISTER)
5436 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5440 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5442 if (ce_info->num_multiple_test_blocks)
5444 basic_block multiple_test_bb = ce_info->last_test_bb;
5446 while (multiple_test_bb != test_bb)
5448 bb[num_bb++] = multiple_test_bb;
5449 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5453 /* Add in the THEN and ELSE blocks to be scanned. */
5454 bb[num_bb++] = then_bb;
5456 bb[num_bb++] = else_bb;
5458 sub_cond_exec_reg = NULL_RTX;
5459 frv_ifcvt.num_nested_cond_exec = 0;
5461 /* Scan all of the blocks for registers that must not be allocated. */
5462 for (j = 0; j < num_bb; j++)
5464 rtx last_insn = BB_END (bb[j]);
5465 rtx insn = BB_HEAD (bb[j]);
5469 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5470 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5472 (int) INSN_UID (BB_HEAD (bb[j])),
5473 (int) INSN_UID (BB_END (bb[j])));
5475 /* Anything live at the beginning of the block is obviously unavailable
5477 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5479 if (regno < FIRST_PSEUDO_REGISTER)
5480 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5483 /* Loop through the insns in the block. */
5486 /* Mark any new registers that are created as being unavailable for
5487 allocation. Also see if the CC register used in nested IFs can be
5493 int skip_nested_if = FALSE;
5495 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5496 (void *)&tmp_reg->regs);
5498 pattern = PATTERN (insn);
5499 if (GET_CODE (pattern) == COND_EXEC)
5501 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5503 if (reg != sub_cond_exec_reg)
5505 sub_cond_exec_reg = reg;
5506 frv_ifcvt.num_nested_cond_exec++;
5510 set = single_set_pattern (pattern);
5513 rtx dest = SET_DEST (set);
5514 rtx src = SET_SRC (set);
5516 if (GET_CODE (dest) == REG)
5518 int regno = REGNO (dest);
5519 enum rtx_code src_code = GET_CODE (src);
5521 if (CC_P (regno) && src_code == COMPARE)
5522 skip_nested_if = TRUE;
5524 else if (CR_P (regno)
5525 && (src_code == IF_THEN_ELSE
5526 || COMPARISON_P (src)))
5527 skip_nested_if = TRUE;
5531 if (! skip_nested_if)
5532 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5533 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5536 if (insn == last_insn)
5539 insn = NEXT_INSN (insn);
5543 /* If this is a nested if, rewrite the CC registers that are available to
5544 include the ones that can be rewritten, to increase the chance of being
5545 able to allocate a paired CC/CR register combination. */
5546 if (ce_info->pass > 1)
5548 for (j = CC_FIRST; j <= CC_LAST; j++)
5549 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5550 SET_HARD_REG_BIT (tmp_reg->regs, j);
5552 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5558 fprintf (dump_file, "Available GPRs: ");
5560 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5561 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5563 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5564 if (++num_gprs > GPR_TEMP_NUM+2)
5568 fprintf (dump_file, "%s\nAvailable CRs: ",
5569 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5571 for (j = CR_FIRST; j <= CR_LAST; j++)
5572 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5573 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5575 fputs ("\n", dump_file);
5577 if (ce_info->pass > 1)
5579 fprintf (dump_file, "Modifiable CCs: ");
5580 for (j = CC_FIRST; j <= CC_LAST; j++)
5581 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5582 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5584 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5585 frv_ifcvt.num_nested_cond_exec);
5589 /* Allocate the appropriate temporary condition code register. Try to
5590 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5591 that conditional cmp's can be done. */
5592 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5594 cr_class = ICR_REGS;
5595 cc_class = ICC_REGS;
5596 cc_first = ICC_FIRST;
5599 else if (mode == CC_FPmode)
5601 cr_class = FCR_REGS;
5602 cc_class = FCC_REGS;
5603 cc_first = FCC_FIRST;
5608 cc_first = cc_last = 0;
5609 cr_class = cc_class = NO_REGS;
5612 cc = XEXP (true_expr, 0);
5613 nested_cc = cr = NULL_RTX;
5614 if (cc_class != NO_REGS)
5616 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5617 so we can execute a csubcc/caddcc/cfcmps instruction. */
5620 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5622 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5624 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5625 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5627 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5628 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5631 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5632 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5642 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5649 "Will use %s for conditional execution, %s for nested comparisons\n",
5650 reg_names[ REGNO (cr)],
5651 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5653 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5654 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5655 bit being true. We don't do this for floating point, because of NaNs. */
5656 code = GET_CODE (true_expr);
5657 if (GET_MODE (cc) != CC_FPmode)
5659 code = reverse_condition (code);
5669 check_insn = gen_rtx_SET (VOIDmode, cr,
5670 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5672 /* Record the check insn to be inserted later. */
5673 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5675 /* Update the tests. */
5676 frv_ifcvt.cr_reg = cr;
5677 frv_ifcvt.nested_cc_reg = nested_cc;
5678 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5679 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5682 /* Fail, don't do this conditional execution. */
5685 *p_false = NULL_RTX;
5687 fprintf (dump_file, "Disabling this conditional execution.\n");
5693 /* A C expression to modify the code described by the conditional if
5694 information CE_INFO, for the basic block BB, possibly updating the tests in
5695 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5696 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5697 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5699 /* p_true and p_false are given expressions of the form:
5701 (and (eq:CC_CCR (reg:CC_CCR)
5707 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5712 rtx old_true = XEXP (*p_true, 0);
5713 rtx old_false = XEXP (*p_false, 0);
5714 rtx true_expr = XEXP (*p_true, 1);
5715 rtx false_expr = XEXP (*p_false, 1);
5718 rtx cr = XEXP (old_true, 0);
5720 rtx new_cr = NULL_RTX;
5721 rtx *p_new_cr = (rtx *)0;
5725 enum reg_class cr_class;
5726 enum machine_mode mode = GET_MODE (true_expr);
5727 rtx (*logical_func)(rtx, rtx, rtx);
5729 if (TARGET_DEBUG_COND_EXEC)
5732 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5733 ce_info->and_and_p ? "&&" : "||");
5735 debug_rtx (*p_true);
5737 fputs ("\nfalse insn:\n", stderr);
5738 debug_rtx (*p_false);
5741 if (!TARGET_MULTI_CE)
5744 if (GET_CODE (cr) != REG)
5747 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5749 cr_class = ICR_REGS;
5750 p_new_cr = &frv_ifcvt.extra_int_cr;
5752 else if (mode == CC_FPmode)
5754 cr_class = FCR_REGS;
5755 p_new_cr = &frv_ifcvt.extra_fp_cr;
5760 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5761 more &&/|| tests. */
5765 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5766 CC_CCRmode, TRUE, TRUE);
5771 if (ce_info->and_and_p)
5773 old_test = old_false;
5774 test_expr = true_expr;
5775 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5776 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5777 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5781 old_test = old_false;
5782 test_expr = false_expr;
5783 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5784 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5785 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5788 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5789 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5791 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5793 /* Now add the conditional check insn. */
5794 cc = XEXP (test_expr, 0);
5795 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5796 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5798 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5800 /* Add the new check insn to the list of check insns that need to be
5802 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5804 if (TARGET_DEBUG_COND_EXEC)
5806 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5809 debug_rtx (*p_true);
5811 fputs ("\nfalse insn:\n", stderr);
5812 debug_rtx (*p_false);
5818 *p_true = *p_false = NULL_RTX;
5820 /* If we allocated a CR register, release it. */
5823 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5824 *p_new_cr = NULL_RTX;
5827 if (TARGET_DEBUG_COND_EXEC)
5828 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5834 /* Return a register which will be loaded with a value if an IF block is
5835 converted to conditional execution. This is used to rewrite instructions
5836 that use constants to ones that just use registers. */
5839 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5841 int num_alloc = frv_ifcvt.cur_scratch_regs;
5845 /* We know gr0 == 0, so replace any errant uses. */
5846 if (value == const0_rtx)
5847 return gen_rtx_REG (SImode, GPR_FIRST);
5849 /* First search all registers currently loaded to see if we have an
5850 applicable constant. */
5851 if (CONSTANT_P (value)
5852 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5854 for (i = 0; i < num_alloc; i++)
5856 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5857 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5861 /* Have we exhausted the number of registers available? */
5862 if (num_alloc >= GPR_TEMP_NUM)
5865 fprintf (dump_file, "Too many temporary registers allocated\n");
5870 /* Allocate the new register. */
5871 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5875 fputs ("Could not find a scratch register\n", dump_file);
5880 frv_ifcvt.cur_scratch_regs++;
5881 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5885 if (GET_CODE (value) == CONST_INT)
5886 fprintf (dump_file, "Register %s will hold %ld\n",
5887 reg_names[ REGNO (reg)], (long)INTVAL (value));
5889 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5890 fprintf (dump_file, "Register %s will hold LR\n",
5891 reg_names[ REGNO (reg)]);
5894 fprintf (dump_file, "Register %s will hold a saved value\n",
5895 reg_names[ REGNO (reg)]);
5902 /* Update a MEM used in conditional code that might contain an offset to put
5903 the offset into a scratch register, so that the conditional load/store
5904 operations can be used. This function returns the original pointer if the
5905 MEM is valid to use in conditional code, NULL if we can't load up the offset
5906 into a temporary register, or the new MEM if we were successful. */
5909 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5911 rtx addr = XEXP (mem, 0);
5913 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5915 if (GET_CODE (addr) == PLUS)
5917 rtx addr_op0 = XEXP (addr, 0);
5918 rtx addr_op1 = XEXP (addr, 1);
5920 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5922 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5926 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5933 else if (CONSTANT_P (addr))
5934 addr = frv_ifcvt_load_value (addr, insn);
5939 if (addr == NULL_RTX)
5942 else if (XEXP (mem, 0) != addr)
5943 return change_address (mem, mode, addr);
5950 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5951 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5954 single_set_pattern (rtx pattern)
5959 if (GET_CODE (pattern) == COND_EXEC)
5960 pattern = COND_EXEC_CODE (pattern);
5962 if (GET_CODE (pattern) == SET)
5965 else if (GET_CODE (pattern) == PARALLEL)
5967 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5969 rtx sub = XVECEXP (pattern, 0, i);
5971 switch (GET_CODE (sub))
5995 /* A C expression to modify the code described by the conditional if
5996 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5997 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5998 insn cannot be converted to be executed conditionally. */
6001 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
6005 rtx orig_ce_pattern = pattern;
6011 gcc_assert (GET_CODE (pattern) == COND_EXEC);
6013 test = COND_EXEC_TEST (pattern);
6014 if (GET_CODE (test) == AND)
6016 rtx cr = frv_ifcvt.cr_reg;
6019 op0 = XEXP (test, 0);
6020 if (! rtx_equal_p (cr, XEXP (op0, 0)))
6023 op1 = XEXP (test, 1);
6024 test_reg = XEXP (op1, 0);
6025 if (GET_CODE (test_reg) != REG)
6028 /* Is this the first nested if block in this sequence? If so, generate
6029 an andcr or andncr. */
6030 if (! frv_ifcvt.last_nested_if_cr)
6034 frv_ifcvt.last_nested_if_cr = test_reg;
6035 if (GET_CODE (op0) == NE)
6036 and_op = gen_andcr (test_reg, cr, test_reg);
6038 and_op = gen_andncr (test_reg, cr, test_reg);
6040 frv_ifcvt_add_insn (and_op, insn, TRUE);
6043 /* If this isn't the first statement in the nested if sequence, see if we
6044 are dealing with the same register. */
6045 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6048 COND_EXEC_TEST (pattern) = test = op1;
6051 /* If this isn't a nested if, reset state variables. */
6054 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6057 set = single_set_pattern (pattern);
6060 rtx dest = SET_DEST (set);
6061 rtx src = SET_SRC (set);
6062 enum machine_mode mode = GET_MODE (dest);
6064 /* Check for normal binary operators. */
6065 if (mode == SImode && ARITHMETIC_P (src))
6067 op0 = XEXP (src, 0);
6068 op1 = XEXP (src, 1);
6070 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6072 op1 = frv_ifcvt_load_value (op1, insn);
6074 COND_EXEC_CODE (pattern)
6075 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6083 /* For multiply by a constant, we need to handle the sign extending
6084 correctly. Add a USE of the value after the multiply to prevent flow
6085 from cratering because only one register out of the two were used. */
6086 else if (mode == DImode && GET_CODE (src) == MULT)
6088 op0 = XEXP (src, 0);
6089 op1 = XEXP (src, 1);
6090 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6092 op1 = frv_ifcvt_load_value (op1, insn);
6095 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6096 COND_EXEC_CODE (pattern)
6097 = gen_rtx_SET (VOIDmode, dest,
6098 gen_rtx_MULT (DImode, op0, op1));
6104 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6107 /* If we are just loading a constant created for a nested conditional
6108 execution statement, just load the constant without any conditional
6109 execution, since we know that the constant will not interfere with any
6111 else if (frv_ifcvt.scratch_insns_bitmap
6112 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6114 && REG_P (SET_DEST (set))
6115 /* We must not unconditionally set a scratch reg chosen
6116 for a nested if-converted block if its incoming
6117 value from the TEST block (or the result of the THEN
6118 branch) could/should propagate to the JOIN block.
6119 It suffices to test whether the register is live at
6120 the JOIN point: if it's live there, we can infer
6121 that we set it in the former JOIN block of the
6122 nested if-converted block (otherwise it wouldn't
6123 have been available as a scratch register), and it
6124 is either propagated through or set in the other
6125 conditional block. It's probably not worth trying
6126 to catch the latter case, and it could actually
6127 limit scheduling of the combined block quite
6130 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6131 REGNO (SET_DEST (set))))
6132 /* Similarly, we must not unconditionally set a reg
6133 used as scratch in the THEN branch if the same reg
6134 is live in the ELSE branch. */
6135 && (! ce_info->else_bb
6136 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6137 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6138 REGNO (SET_DEST (set))))))
6141 else if (mode == QImode || mode == HImode || mode == SImode
6144 int changed_p = FALSE;
6146 /* Check for just loading up a constant */
6147 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6149 src = frv_ifcvt_load_value (src, insn);
6156 /* See if we need to fix up stores */
6157 if (GET_CODE (dest) == MEM)
6159 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6164 else if (new_mem != dest)
6171 /* See if we need to fix up loads */
6172 if (GET_CODE (src) == MEM)
6174 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6179 else if (new_mem != src)
6186 /* If either src or destination changed, redo SET. */
6188 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6191 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6192 rewriting the CC register to be the same as the paired CC/CR register
6194 else if (mode == CC_CCRmode && COMPARISON_P (src))
6196 int regno = REGNO (XEXP (src, 0));
6199 if (ce_info->pass > 1
6200 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6201 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6203 src = gen_rtx_fmt_ee (GET_CODE (src),
6205 frv_ifcvt.nested_cc_reg,
6209 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6210 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6213 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6214 else if (ce_info->pass > 1
6215 && GET_CODE (dest) == REG
6216 && CC_P (REGNO (dest))
6217 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6218 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6220 && GET_CODE (src) == COMPARE)
6222 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6223 COND_EXEC_CODE (pattern)
6224 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6228 if (TARGET_DEBUG_COND_EXEC)
6230 rtx orig_pattern = PATTERN (insn);
6232 PATTERN (insn) = pattern;
6234 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6238 PATTERN (insn) = orig_pattern;
6244 if (TARGET_DEBUG_COND_EXEC)
6246 rtx orig_pattern = PATTERN (insn);
6248 PATTERN (insn) = orig_ce_pattern;
6250 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6254 PATTERN (insn) = orig_pattern;
6261 /* A C expression to perform any final machine dependent modifications in
6262 converting code to conditional execution in the code described by the
6263 conditional if information CE_INFO. */
6266 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6270 rtx p = frv_ifcvt.added_insns_list;
6273 /* Loop inserting the check insns. The last check insn is the first test,
6274 and is the appropriate place to insert constants. */
6279 rtx check_and_insert_insns = XEXP (p, 0);
6282 check_insn = XEXP (check_and_insert_insns, 0);
6283 existing_insn = XEXP (check_and_insert_insns, 1);
6286 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6287 the existing insn, otherwise it is to be inserted AFTER. */
6288 if (check_and_insert_insns->jump)
6290 emit_insn_before (check_insn, existing_insn);
6291 check_and_insert_insns->jump = 0;
6294 emit_insn_after (check_insn, existing_insn);
6296 free_EXPR_LIST_node (check_and_insert_insns);
6297 free_EXPR_LIST_node (old_p);
6299 while (p != NULL_RTX);
6301 /* Load up any constants needed into temp gprs */
6302 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6304 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6305 if (! frv_ifcvt.scratch_insns_bitmap)
6306 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6307 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6308 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6311 frv_ifcvt.added_insns_list = NULL_RTX;
6312 frv_ifcvt.cur_scratch_regs = 0;
6316 /* A C expression to cancel any machine dependent modifications in converting
6317 code to conditional execution in the code described by the conditional if
6318 information CE_INFO. */
6321 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6324 rtx p = frv_ifcvt.added_insns_list;
6326 /* Loop freeing up the EXPR_LIST's allocated. */
6327 while (p != NULL_RTX)
6329 rtx check_and_jump = XEXP (p, 0);
6333 free_EXPR_LIST_node (check_and_jump);
6334 free_EXPR_LIST_node (old_p);
6337 /* Release any temporary gprs allocated. */
6338 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6339 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6341 frv_ifcvt.added_insns_list = NULL_RTX;
6342 frv_ifcvt.cur_scratch_regs = 0;
6346 /* A C expression for the size in bytes of the trampoline, as an integer.
6350 setlo #0, <static_chain>
6352 sethi #0, <static_chain>
6353 jmpl @(gr0,<jmp_reg>) */
6356 frv_trampoline_size (void)
6359 /* Allocate room for the function descriptor and the lddi
6362 return 5 /* instructions */ * 4 /* instruction size. */;
6366 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6367 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6368 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6369 should be passed to the function when it is called.
6374 setlo #0, <static_chain>
6376 sethi #0, <static_chain>
6377 jmpl @(gr0,<jmp_reg>) */
6380 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6382 rtx addr = XEXP (m_tramp, 0);
6383 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6384 rtx sc_reg = force_reg (Pmode, static_chain);
6386 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6389 GEN_INT (frv_trampoline_size ()), SImode,
6395 /* Many machines have some registers that cannot be copied directly to or from
6396 memory or even from other types of registers. An example is the `MQ'
6397 register, which on most machines, can only be copied to or from general
6398 registers, but not memory. Some machines allow copying all registers to and
6399 from memory, but require a scratch register for stores to some memory
6400 locations (e.g., those with symbolic address on the RT, and those with
6401 certain symbolic address on the SPARC when compiling PIC). In some cases,
6402 both an intermediate and a scratch register are required.
6404 You should define these macros to indicate to the reload phase that it may
6405 need to allocate at least one register for a reload in addition to the
6406 register to contain the data. Specifically, if copying X to a register
6407 RCLASS in MODE requires an intermediate register, you should define
6408 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6409 whose registers can be used as intermediate registers or scratch registers.
6411 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6412 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6413 largest register class required. If the requirements for input and output
6414 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6415 instead of defining both macros identically.
6417 The values returned by these macros are often `GENERAL_REGS'. Return
6418 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6419 to or from a register of RCLASS in MODE without requiring a scratch register.
6420 Do not define this macro if it would always return `NO_REGS'.
6422 If a scratch register is required (either with or without an intermediate
6423 register), you should define patterns for `reload_inM' or `reload_outM', as
6424 required.. These patterns, which will normally be implemented with a
6425 `define_expand', should be similar to the `movM' patterns, except that
6426 operand 2 is the scratch register.
6428 Define constraints for the reload register and scratch register that contain
6429 a single register class. If the original reload register (whose class is
6430 RCLASS) can meet the constraint given in the pattern, the value returned by
6431 these macros is used for the class of the scratch register. Otherwise, two
6432 additional reload registers are required. Their classes are obtained from
6433 the constraints in the insn pattern.
6435 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6436 either be in a hard register or in memory. Use `true_regnum' to find out;
6437 it will return -1 if the pseudo is in memory and the hard register number if
6438 it is in a register.
6440 These macros should not be used in the case where a particular class of
6441 registers can only be copied to memory and not to another class of
6442 registers. In that case, secondary reload registers are not needed and
6443 would not be helpful. Instead, a stack location must be used to perform the
6444 copy and the `movM' pattern should use memory as an intermediate storage.
6445 This case often occurs between floating-point and general registers. */
6448 frv_secondary_reload_class (enum reg_class rclass,
6449 enum machine_mode mode ATTRIBUTE_UNUSED,
6460 /* Accumulators/Accumulator guard registers need to go through floating
6466 if (x && GET_CODE (x) == REG)
6468 int regno = REGNO (x);
6470 if (ACC_P (regno) || ACCG_P (regno))
6475 /* Nonzero constants should be loaded into an FPR through a GPR. */
6479 if (x && CONSTANT_P (x) && !ZERO_P (x))
6485 /* All of these types need gpr registers. */
6497 /* The accumulators need fpr registers. */
6509 /* This hook exists to catch the case where secondary_reload_class() is
6510 called from init_reg_autoinc() in regclass.c - before the reload optabs
6511 have been initialised. */
6514 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6515 enum machine_mode reload_mode,
6516 secondary_reload_info * sri)
6518 enum reg_class rclass = NO_REGS;
6519 enum reg_class reload_class = (enum reg_class) reload_class_i;
6521 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6523 sri->icode = sri->prev_sri->t_icode;
6527 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6529 if (rclass != NO_REGS)
6531 enum insn_code icode
6532 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6536 /* This happens when then the reload_[in|out]_optabs have
6537 not been initialised. */
6538 sri->t_icode = CODE_FOR_nothing;
6543 /* Fall back to the default secondary reload handler. */
6544 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6548 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6551 frv_class_likely_spilled_p (reg_class_t rclass)
6561 case FDPIC_FPTR_REGS:
6583 /* An expression for the alignment of a structure field FIELD if the
6584 alignment computed in the usual way is COMPUTED. GCC uses this
6585 value instead of the value in `BIGGEST_ALIGNMENT' or
6586 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6588 /* The definition type of the bit field data is either char, short, long or
6589 long long. The maximum bit size is the number of bits of its own type.
6591 The bit field data is assigned to a storage unit that has an adequate size
6592 for bit field data retention and is located at the smallest address.
6594 Consecutive bit field data are packed at consecutive bits having the same
6595 storage unit, with regard to the type, beginning with the MSB and continuing
6598 If a field to be assigned lies over a bit field type boundary, its
6599 assignment is completed by aligning it with a boundary suitable for the
6602 When a bit field having a bit length of 0 is declared, it is forcibly
6603 assigned to the next storage unit.
6616 &x 00000000 00000000 00000000 00000000
6619 &x+4 00000000 00000000 00000000 00000000
6622 &x+8 00000000 00000000 00000000 00000000
6625 &x+12 00000000 00000000 00000000 00000000
6631 frv_adjust_field_align (tree field, int computed)
6633 /* Make sure that the bitfield is not wider than the type. */
6634 if (DECL_BIT_FIELD (field)
6635 && !DECL_ARTIFICIAL (field))
6637 tree parent = DECL_CONTEXT (field);
6638 tree prev = NULL_TREE;
6641 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6643 if (TREE_CODE (cur) != FIELD_DECL)
6651 /* If this isn't a :0 field and if the previous element is a bitfield
6652 also, see if the type is different, if so, we will need to align the
6653 bit-field to the next boundary. */
6655 && ! DECL_PACKED (field)
6656 && ! integer_zerop (DECL_SIZE (field))
6657 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6659 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6660 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6661 computed = (prev_align > cur_align) ? prev_align : cur_align;
6669 /* A C expression that is nonzero if it is permissible to store a value of mode
6670 MODE in hard register number REGNO (or in several registers starting with
6671 that one). For a machine where all registers are equivalent, a suitable
6674 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6676 It is not necessary for this macro to check for the numbers of fixed
6677 registers, because the allocation mechanism considers them to be always
6680 On some machines, double-precision values must be kept in even/odd register
6681 pairs. The way to implement that is to define this macro to reject odd
6682 register numbers for such modes.
6684 The minimum requirement for a mode to be OK in a register is that the
6685 `movMODE' instruction pattern support moves between the register and any
6686 other hard register for which the mode is OK; and that moving a value into
6687 the register and back out not alter it.
6689 Since the same instruction used to move `SImode' will work for all narrower
6690 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6691 to distinguish between these modes, provided you define patterns `movhi',
6692 etc., to take advantage of this. This is useful because of the interaction
6693 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6694 all integer modes to be tieable.
6696 Many machines have special registers for floating point arithmetic. Often
6697 people assume that floating point machine modes are allowed only in floating
6698 point registers. This is not true. Any registers that can hold integers
6699 can safely *hold* a floating point machine mode, whether or not floating
6700 arithmetic can be done on it in those registers. Integer move instructions
6701 can be used to move the values.
6703 On some machines, though, the converse is true: fixed-point machine modes
6704 may not go in floating registers. This is true if the floating registers
6705 normalize any value stored in them, because storing a non-floating value
6706 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6707 fixed-point machine modes in floating registers. But if the floating
6708 registers do not automatically normalize, if you can store any bit pattern
6709 in one and retrieve it unchanged without a trap, then any machine mode may
6710 go in a floating register, so you can define this macro to say so.
6712 The primary significance of special floating registers is rather that they
6713 are the registers acceptable in floating point arithmetic instructions.
6714 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6715 writing the proper constraints for those instructions.
6717 On some machines, the floating registers are especially slow to access, so
6718 that it is better to store a value in a stack frame than in such a register
6719 if floating point arithmetic is not being done. As long as the floating
6720 registers are not in class `GENERAL_REGS', they will not be used unless some
6721 pattern's constraint asks for one. */
6724 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6734 return ICC_P (regno) || GPR_P (regno);
6737 return CR_P (regno) || GPR_P (regno);
6740 return FCC_P (regno) || GPR_P (regno);
6746 /* Set BASE to the first register in REGNO's class. Set MASK to the
6747 bits that must be clear in (REGNO - BASE) for the register to be
6749 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6753 /* ACCGs store one byte. Two-byte quantities must start in
6754 even-numbered registers, four-byte ones in registers whose
6755 numbers are divisible by four, and so on. */
6757 mask = GET_MODE_SIZE (mode) - 1;
6761 /* The other registers store one word. */
6762 if (GPR_P (regno) || regno == AP_FIRST)
6765 else if (FPR_P (regno))
6768 else if (ACC_P (regno))
6771 else if (SPR_P (regno))
6772 return mode == SImode;
6774 /* Fill in the table. */
6778 /* Anything smaller than an SI is OK in any word-sized register. */
6779 if (GET_MODE_SIZE (mode) < 4)
6782 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6784 return (((regno - base) & mask) == 0);
6791 /* A C expression for the number of consecutive hard registers, starting at
6792 register number REGNO, required to hold a value of mode MODE.
6794 On a machine where all registers are exactly one word, a suitable definition
6797 #define HARD_REGNO_NREGS(REGNO, MODE) \
6798 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6799 / UNITS_PER_WORD)) */
6801 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6802 that we can build the appropriate instructions to properly reload the
6803 values. Also, make the byte-sized accumulator guards use one guard
6807 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6810 return GET_MODE_SIZE (mode);
6812 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6816 /* A C expression for the maximum number of consecutive registers of
6817 class RCLASS needed to hold a value of mode MODE.
6819 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6820 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6821 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6823 This macro helps control the handling of multiple-word values in
6826 This declaration is required. */
6829 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6831 if (rclass == ACCG_REGS)
6832 /* An N-byte value requires N accumulator guards. */
6833 return GET_MODE_SIZE (mode);
6835 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6839 /* A C expression that is nonzero if X is a legitimate constant for an
6840 immediate operand on the target machine. You can assume that X satisfies
6841 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6842 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6845 frv_legitimate_constant_p (rtx x)
6847 enum machine_mode mode = GET_MODE (x);
6849 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6850 means that the move expanders will be expected to deal with most
6851 kinds of constant, regardless of what we return here.
6853 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6854 a constant can be entered into reg_equiv_constant[]. If we return true,
6855 reload can create new instances of the constant whenever it likes.
6857 The idea is therefore to accept as many constants as possible (to give
6858 reload more freedom) while rejecting constants that can only be created
6859 at certain times. In particular, anything with a symbolic component will
6860 require use of the pseudo FDPIC register, which is only available before
6863 return LEGITIMATE_PIC_OPERAND_P (x);
6865 /* All of the integer constants are ok. */
6866 if (GET_CODE (x) != CONST_DOUBLE)
6869 /* double integer constants are ok. */
6870 if (mode == VOIDmode || mode == DImode)
6873 /* 0 is always ok. */
6874 if (x == CONST0_RTX (mode))
6877 /* If floating point is just emulated, allow any constant, since it will be
6878 constructed in the GPRs. */
6879 if (!TARGET_HAS_FPRS)
6882 if (mode == DFmode && !TARGET_DOUBLE)
6885 /* Otherwise store the constant away and do a load. */
6889 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6890 CC_NZ for comparisons against zero in which a single Z or N flag test
6891 is enough, CC_UNS for other unsigned comparisons, and CC for other
6892 signed comparisons. */
6895 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6897 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6906 return y == const0_rtx ? CC_NZmode : CCmode;
6912 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6920 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6922 #define HIGH_COST 40
6923 #define MEDIUM_COST 3
6927 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6928 reg_class_t from, reg_class_t to)
7012 /* Worker function for TARGET_MEMORY_MOVE_COST. */
7015 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
7016 reg_class_t rclass ATTRIBUTE_UNUSED,
7017 bool in ATTRIBUTE_UNUSED)
7023 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7024 use ".picptr" to generate safe relocations for PIC code. We also
7025 need a fixup entry for aligned (non-debugging) code. */
7028 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
7030 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
7032 if (GET_CODE (value) == CONST
7033 || GET_CODE (value) == SYMBOL_REF
7034 || GET_CODE (value) == LABEL_REF)
7036 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
7037 && SYMBOL_REF_FUNCTION_P (value))
7039 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
7040 output_addr_const (asm_out_file, value);
7041 fputs (")\n", asm_out_file);
7044 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7045 && frv_function_symbol_referenced_p (value))
7047 if (aligned_p && !TARGET_FDPIC)
7049 static int label_num = 0;
7053 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7054 p = (* targetm.strip_name_encoding) (buf);
7056 fprintf (asm_out_file, "%s:\n", p);
7057 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7058 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7059 fprintf (asm_out_file, "\t.previous\n");
7061 assemble_integer_with_op ("\t.picptr\t", value);
7066 /* We've set the unaligned SI op to NULL, so we always have to
7067 handle the unaligned case here. */
7068 assemble_integer_with_op ("\t.4byte\t", value);
7072 return default_assemble_integer (value, size, aligned_p);
7075 /* Function to set up the backend function structure. */
7077 static struct machine_function *
7078 frv_init_machine_status (void)
7080 return ggc_alloc_cleared_machine_function ();
7083 /* Implement TARGET_SCHED_ISSUE_RATE. */
7086 frv_issue_rate (void)
7091 switch (frv_cpu_type)
7095 case FRV_CPU_SIMPLE:
7103 case FRV_CPU_GENERIC:
7105 case FRV_CPU_TOMCAT:
7113 /* A for_each_rtx callback. If X refers to an accumulator, return
7114 ACC_GROUP_ODD if the bit 2 of the register number is set and
7115 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7119 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7123 if (ACC_P (REGNO (*x)))
7124 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7125 if (ACCG_P (REGNO (*x)))
7126 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7131 /* Return the value of INSN's acc_group attribute. */
7134 frv_acc_group (rtx insn)
7136 /* This distinction only applies to the FR550 packing constraints. */
7137 if (frv_cpu_type != FRV_CPU_FR550)
7138 return ACC_GROUP_NONE;
7139 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7142 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7143 INSN will try to claim first. Since this value depends only on the
7144 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7147 frv_insn_unit (rtx insn)
7149 enum attr_type type;
7151 type = get_attr_type (insn);
7152 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7154 /* We haven't seen this type of instruction before. */
7158 /* Issue the instruction on its own to see which unit it prefers. */
7159 state = alloca (state_size ());
7160 state_reset (state);
7161 state_transition (state, insn);
7163 /* Find out which unit was taken. */
7164 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7165 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7168 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7170 frv_type_to_unit[type] = unit;
7172 return frv_type_to_unit[type];
7175 /* Return true if INSN issues to a branch unit. */
7178 frv_issues_to_branch_unit_p (rtx insn)
7180 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7183 /* The current state of the packing pass, implemented by frv_pack_insns. */
7185 /* The state of the pipeline DFA. */
7188 /* Which hardware registers are set within the current packet,
7189 and the conditions under which they are set. */
7190 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7192 /* The memory locations that have been modified so far in this
7193 packet. MEM is the memref and COND is the regstate_t condition
7194 under which it is set. */
7200 /* The number of valid entries in MEMS. The value is larger than
7201 ARRAY_SIZE (mems) if there were too many mems to record. */
7202 unsigned int num_mems;
7204 /* The maximum number of instructions that can be packed together. */
7205 unsigned int issue_rate;
7207 /* The instructions in the packet, partitioned into groups. */
7208 struct frv_packet_group {
7209 /* How many instructions in the packet belong to this group. */
7210 unsigned int num_insns;
7212 /* A list of the instructions that belong to this group, in the order
7213 they appear in the rtl stream. */
7214 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7216 /* The contents of INSNS after they have been sorted into the correct
7217 assembly-language order. Element X issues to unit X. The list may
7218 contain extra nops. */
7219 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7221 /* The member of frv_nops[] to use in sorted[]. */
7223 } groups[NUM_GROUPS];
7225 /* The instructions that make up the current packet. */
7226 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7227 unsigned int num_insns;
7230 /* Return the regstate_t flags for the given COND_EXEC condition.
7231 Abort if the condition isn't in the right form. */
7234 frv_cond_flags (rtx cond)
7236 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7237 && GET_CODE (XEXP (cond, 0)) == REG
7238 && CR_P (REGNO (XEXP (cond, 0)))
7239 && XEXP (cond, 1) == const0_rtx);
7240 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7241 | (GET_CODE (cond) == NE
7243 : REGSTATE_IF_FALSE));
7247 /* Return true if something accessed under condition COND2 can
7248 conflict with something written under condition COND1. */
7251 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7253 /* If either reference was unconditional, we have a conflict. */
7254 if ((cond1 & REGSTATE_IF_EITHER) == 0
7255 || (cond2 & REGSTATE_IF_EITHER) == 0)
7258 /* The references might conflict if they were controlled by
7260 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7263 /* They definitely conflict if they are controlled by the
7265 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7272 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7273 the current packet. DATA points to a regstate_t that describes the
7274 condition under which *X might be set or used. */
7277 frv_registers_conflict_p_1 (rtx *x, void *data)
7279 unsigned int regno, i;
7282 cond = *(regstate_t *) data;
7284 if (GET_CODE (*x) == REG)
7285 FOR_EACH_REGNO (regno, *x)
7286 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7287 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7290 if (GET_CODE (*x) == MEM)
7292 /* If we ran out of memory slots, assume a conflict. */
7293 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7296 /* Check for output or true dependencies with earlier MEMs. */
7297 for (i = 0; i < frv_packet.num_mems; i++)
7298 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7300 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7304 if (output_dependence (frv_packet.mems[i].mem, *x))
7309 /* The return values of calls aren't significant: they describe
7310 the effect of the call as a whole, not of the insn itself. */
7311 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7313 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7318 /* Check subexpressions. */
7323 /* Return true if something in X might depend on an instruction
7324 in the current packet. */
7327 frv_registers_conflict_p (rtx x)
7332 if (GET_CODE (x) == COND_EXEC)
7334 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7337 flags |= frv_cond_flags (XEXP (x, 0));
7340 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7344 /* A note_stores callback. DATA points to the regstate_t condition
7345 under which X is modified. Update FRV_PACKET accordingly. */
7348 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7352 if (GET_CODE (x) == REG)
7353 FOR_EACH_REGNO (regno, x)
7354 frv_packet.regstate[regno] |= *(regstate_t *) data;
7356 if (GET_CODE (x) == MEM)
7358 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7360 frv_packet.mems[frv_packet.num_mems].mem = x;
7361 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7363 frv_packet.num_mems++;
7368 /* Update the register state information for an instruction whose
7372 frv_registers_update (rtx x)
7376 flags = REGSTATE_MODIFIED;
7377 if (GET_CODE (x) == COND_EXEC)
7379 flags |= frv_cond_flags (XEXP (x, 0));
7382 note_stores (x, frv_registers_update_1, &flags);
7386 /* Initialize frv_packet for the start of a new packet. */
7389 frv_start_packet (void)
7391 enum frv_insn_group group;
7393 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7394 frv_packet.num_mems = 0;
7395 frv_packet.num_insns = 0;
7396 for (group = 0; group < NUM_GROUPS; group++)
7397 frv_packet.groups[group].num_insns = 0;
7401 /* Likewise for the start of a new basic block. */
7404 frv_start_packet_block (void)
7406 state_reset (frv_packet.dfa_state);
7407 frv_start_packet ();
7411 /* Finish the current packet, if any, and start a new one. Call
7412 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7415 frv_finish_packet (void (*handle_packet) (void))
7417 if (frv_packet.num_insns > 0)
7420 state_transition (frv_packet.dfa_state, 0);
7421 frv_start_packet ();
7426 /* Return true if INSN can be added to the current packet. Update
7427 the DFA state on success. */
7430 frv_pack_insn_p (rtx insn)
7432 /* See if the packet is already as long as it can be. */
7433 if (frv_packet.num_insns == frv_packet.issue_rate)
7436 /* If the scheduler thought that an instruction should start a packet,
7437 it's usually a good idea to believe it. It knows much more about
7438 the latencies than we do.
7440 There are some exceptions though:
7442 - Conditional instructions are scheduled on the assumption that
7443 they will be executed. This is usually a good thing, since it
7444 tends to avoid unnecessary stalls in the conditional code.
7445 But we want to pack conditional instructions as tightly as
7446 possible, in order to optimize the case where they aren't
7449 - The scheduler will always put branches on their own, even
7450 if there's no real dependency.
7452 - There's no point putting a call in its own packet unless
7454 if (frv_packet.num_insns > 0
7455 && GET_CODE (insn) == INSN
7456 && GET_MODE (insn) == TImode
7457 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7460 /* Check for register conflicts. Don't do this for setlo since any
7461 conflict will be with the partnering sethi, with which it can
7463 if (get_attr_type (insn) != TYPE_SETLO)
7464 if (frv_registers_conflict_p (PATTERN (insn)))
7467 return state_transition (frv_packet.dfa_state, insn) < 0;
7471 /* Add instruction INSN to the current packet. */
7474 frv_add_insn_to_packet (rtx insn)
7476 struct frv_packet_group *packet_group;
7478 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7479 packet_group->insns[packet_group->num_insns++] = insn;
7480 frv_packet.insns[frv_packet.num_insns++] = insn;
7482 frv_registers_update (PATTERN (insn));
7486 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7487 packet ends in a branch or call, insert the nop before it, otherwise
7491 frv_insert_nop_in_packet (rtx insn)
7493 struct frv_packet_group *packet_group;
7496 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7497 last = frv_packet.insns[frv_packet.num_insns - 1];
7498 if (GET_CODE (last) != INSN)
7500 insn = emit_insn_before (PATTERN (insn), last);
7501 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7502 frv_packet.insns[frv_packet.num_insns++] = last;
7506 insn = emit_insn_after (PATTERN (insn), last);
7507 frv_packet.insns[frv_packet.num_insns++] = insn;
7509 packet_group->insns[packet_group->num_insns++] = insn;
7513 /* If packing is enabled, divide the instructions into packets and
7514 return true. Call HANDLE_PACKET for each complete packet. */
7517 frv_for_each_packet (void (*handle_packet) (void))
7519 rtx insn, next_insn;
7521 frv_packet.issue_rate = frv_issue_rate ();
7523 /* Early exit if we don't want to pack insns. */
7525 || !flag_schedule_insns_after_reload
7526 || !TARGET_VLIW_BRANCH
7527 || frv_packet.issue_rate == 1)
7530 /* Set up the initial packing state. */
7532 frv_packet.dfa_state = alloca (state_size ());
7534 frv_start_packet_block ();
7535 for (insn = get_insns (); insn != 0; insn = next_insn)
7540 code = GET_CODE (insn);
7541 next_insn = NEXT_INSN (insn);
7543 if (code == CODE_LABEL)
7545 frv_finish_packet (handle_packet);
7546 frv_start_packet_block ();
7550 switch (GET_CODE (PATTERN (insn)))
7559 /* Calls mustn't be packed on a TOMCAT. */
7560 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7561 frv_finish_packet (handle_packet);
7563 /* Since the last instruction in a packet determines the EH
7564 region, any exception-throwing instruction must come at
7565 the end of reordered packet. Insns that issue to a
7566 branch unit are bound to come last; for others it's
7567 too hard to predict. */
7568 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7569 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7570 frv_finish_packet (handle_packet);
7572 /* Finish the current packet if we can't add INSN to it.
7573 Simulate cycles until INSN is ready to issue. */
7574 if (!frv_pack_insn_p (insn))
7576 frv_finish_packet (handle_packet);
7577 while (!frv_pack_insn_p (insn))
7578 state_transition (frv_packet.dfa_state, 0);
7581 /* Add the instruction to the packet. */
7582 frv_add_insn_to_packet (insn);
7584 /* Calls and jumps end a packet, as do insns that throw
7586 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7587 frv_finish_packet (handle_packet);
7591 frv_finish_packet (handle_packet);
7596 /* Subroutine of frv_sort_insn_group. We are trying to sort
7597 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7598 language order. We have already picked a new position for
7599 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7600 These instructions will occupy elements [0, LOWER_SLOT) and
7601 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7602 the DFA state after issuing these instructions.
7604 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7605 of the unused instructions. Return true if one such permutation gives
7606 a valid ordering, leaving the successful permutation in sorted[].
7607 Do not modify sorted[] until a valid permutation is found. */
7610 frv_sort_insn_group_1 (enum frv_insn_group group,
7611 unsigned int lower_slot, unsigned int upper_slot,
7612 unsigned int issued, unsigned int num_insns,
7615 struct frv_packet_group *packet_group;
7621 /* Early success if we've filled all the slots. */
7622 if (lower_slot == upper_slot)
7625 packet_group = &frv_packet.groups[group];
7626 dfa_size = state_size ();
7627 test_state = alloca (dfa_size);
7629 /* Try issuing each unused instruction. */
7630 for (i = num_insns - 1; i + 1 != 0; i--)
7631 if (~issued & (1 << i))
7633 insn = packet_group->sorted[i];
7634 memcpy (test_state, state, dfa_size);
7635 if (state_transition (test_state, insn) < 0
7636 && cpu_unit_reservation_p (test_state,
7637 NTH_UNIT (group, upper_slot - 1))
7638 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7639 issued | (1 << i), num_insns,
7642 packet_group->sorted[upper_slot - 1] = insn;
7650 /* Compare two instructions by their frv_insn_unit. */
7653 frv_compare_insns (const void *first, const void *second)
7655 const rtx *const insn1 = (rtx const *) first,
7656 *const insn2 = (rtx const *) second;
7657 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7660 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7661 and sort it into assembly language order. See frv.md for a description of
7665 frv_sort_insn_group (enum frv_insn_group group)
7667 struct frv_packet_group *packet_group;
7668 unsigned int first, i, nop, max_unit, num_slots;
7669 state_t state, test_state;
7672 packet_group = &frv_packet.groups[group];
7674 /* Assume no nop is needed. */
7675 packet_group->nop = 0;
7677 if (packet_group->num_insns == 0)
7680 /* Copy insns[] to sorted[]. */
7681 memcpy (packet_group->sorted, packet_group->insns,
7682 sizeof (rtx) * packet_group->num_insns);
7684 /* Sort sorted[] by the unit that each insn tries to take first. */
7685 if (packet_group->num_insns > 1)
7686 qsort (packet_group->sorted, packet_group->num_insns,
7687 sizeof (rtx), frv_compare_insns);
7689 /* That's always enough for branch and control insns. */
7690 if (group == GROUP_B || group == GROUP_C)
7693 dfa_size = state_size ();
7694 state = alloca (dfa_size);
7695 test_state = alloca (dfa_size);
7697 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7698 consecutively and such that the DFA takes unit X when sorted[X]
7699 is added. Set STATE to the new DFA state. */
7700 state_reset (test_state);
7701 for (first = 0; first < packet_group->num_insns; first++)
7703 memcpy (state, test_state, dfa_size);
7704 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7705 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7709 /* If all the instructions issued in ascending order, we're done. */
7710 if (first == packet_group->num_insns)
7713 /* Add nops to the end of sorted[] and try each permutation until
7714 we find one that works. */
7715 for (nop = 0; nop < frv_num_nops; nop++)
7717 max_unit = frv_insn_unit (frv_nops[nop]);
7718 if (frv_unit_groups[max_unit] == group)
7720 packet_group->nop = frv_nops[nop];
7721 num_slots = UNIT_NUMBER (max_unit) + 1;
7722 for (i = packet_group->num_insns; i < num_slots; i++)
7723 packet_group->sorted[i] = frv_nops[nop];
7724 if (frv_sort_insn_group_1 (group, first, num_slots,
7725 (1 << first) - 1, num_slots, state))
7732 /* Sort the current packet into assembly-language order. Set packing
7733 flags as appropriate. */
7736 frv_reorder_packet (void)
7738 unsigned int cursor[NUM_GROUPS];
7739 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7740 unsigned int unit, to, from;
7741 enum frv_insn_group group;
7742 struct frv_packet_group *packet_group;
7744 /* First sort each group individually. */
7745 for (group = 0; group < NUM_GROUPS; group++)
7748 frv_sort_insn_group (group);
7751 /* Go through the unit template and try add an instruction from
7752 that unit's group. */
7754 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7756 group = frv_unit_groups[unit];
7757 packet_group = &frv_packet.groups[group];
7758 if (cursor[group] < packet_group->num_insns)
7760 /* frv_reorg should have added nops for us. */
7761 gcc_assert (packet_group->sorted[cursor[group]]
7762 != packet_group->nop);
7763 insns[to++] = packet_group->sorted[cursor[group]++];
7767 gcc_assert (to == frv_packet.num_insns);
7769 /* Clear the last instruction's packing flag, thus marking the end of
7770 a packet. Reorder the other instructions relative to it. */
7771 CLEAR_PACKING_FLAG (insns[to - 1]);
7772 for (from = 0; from < to - 1; from++)
7774 remove_insn (insns[from]);
7775 add_insn_before (insns[from], insns[to - 1], NULL);
7776 SET_PACKING_FLAG (insns[from]);
7781 /* Divide instructions into packets. Reorder the contents of each
7782 packet so that they are in the correct assembly-language order.
7784 Since this pass can change the raw meaning of the rtl stream, it must
7785 only be called at the last minute, just before the instructions are
7789 frv_pack_insns (void)
7791 if (frv_for_each_packet (frv_reorder_packet))
7792 frv_insn_packing_flag = 0;
7794 frv_insn_packing_flag = -1;
7797 /* See whether we need to add nops to group GROUP in order to
7798 make a valid packet. */
7801 frv_fill_unused_units (enum frv_insn_group group)
7803 unsigned int non_nops, nops, i;
7804 struct frv_packet_group *packet_group;
7806 packet_group = &frv_packet.groups[group];
7808 /* Sort the instructions into assembly-language order.
7809 Use nops to fill slots that are otherwise unused. */
7810 frv_sort_insn_group (group);
7812 /* See how many nops are needed before the final useful instruction. */
7814 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7815 while (packet_group->sorted[i++] == packet_group->nop)
7818 /* Insert that many nops into the instruction stream. */
7820 frv_insert_nop_in_packet (packet_group->nop);
7823 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7826 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7828 if (io1->const_address != 0 && io2->const_address != 0)
7829 return io1->const_address == io2->const_address;
7831 if (io1->var_address != 0 && io2->var_address != 0)
7832 return rtx_equal_p (io1->var_address, io2->var_address);
7837 /* Return true if operations IO1 and IO2 are guaranteed to complete
7841 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7843 /* The order of writes is always preserved. */
7844 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7847 /* The order of reads isn't preserved. */
7848 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7851 /* One operation is a write and the other is (or could be) a read.
7852 The order is only guaranteed if the accesses are to the same
7854 return frv_same_doubleword_p (io1, io2);
7857 /* Generalize I/O operation X so that it covers both X and Y. */
7860 frv_io_union (struct frv_io *x, const struct frv_io *y)
7862 if (x->type != y->type)
7863 x->type = FRV_IO_UNKNOWN;
7864 if (!frv_same_doubleword_p (x, y))
7866 x->const_address = 0;
7871 /* Fill IO with information about the load or store associated with
7872 membar instruction INSN. */
7875 frv_extract_membar (struct frv_io *io, rtx insn)
7877 extract_insn (insn);
7878 io->type = INTVAL (recog_data.operand[2]);
7879 io->const_address = INTVAL (recog_data.operand[1]);
7880 io->var_address = XEXP (recog_data.operand[0], 0);
7883 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7884 if X is a register and *DATA depends on X. */
7887 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7889 rtx *other = (rtx *) data;
7891 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7895 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7896 Remove every modified register from the set. */
7899 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7901 HARD_REG_SET *set = (HARD_REG_SET *) data;
7905 FOR_EACH_REGNO (regno, x)
7906 CLEAR_HARD_REG_BIT (*set, regno);
7909 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7910 Add every register in *X to the set. */
7913 frv_io_handle_use_1 (rtx *x, void *data)
7915 HARD_REG_SET *set = (HARD_REG_SET *) data;
7919 FOR_EACH_REGNO (regno, *x)
7920 SET_HARD_REG_BIT (*set, regno);
7925 /* A note_stores callback that applies frv_io_handle_use_1 to an
7926 entire rhs value. */
7929 frv_io_handle_use (rtx *x, void *data)
7931 for_each_rtx (x, frv_io_handle_use_1, data);
7934 /* Go through block BB looking for membars to remove. There are two
7935 cases where intra-block analysis is enough:
7937 - a membar is redundant if it occurs between two consecutive I/O
7938 operations and if those operations are guaranteed to complete
7941 - a membar for a __builtin_read is redundant if the result is
7942 used before the next I/O operation is issued.
7944 If the last membar in the block could not be removed, and there
7945 are guaranteed to be no I/O operations between that membar and
7946 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7949 Describe the block's first I/O operation in *NEXT_IO. Describe
7950 an unknown operation if the block doesn't do any I/O. */
7953 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7956 HARD_REG_SET used_regs;
7957 rtx next_membar, set, insn;
7960 /* NEXT_IO is the next I/O operation to be performed after the current
7961 instruction. It starts off as being an unknown operation. */
7962 memset (next_io, 0, sizeof (*next_io));
7964 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7965 next_is_end_p = true;
7967 /* If the current instruction is a __builtin_read or __builtin_write,
7968 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7969 is null if the membar has already been deleted.
7971 Note that the initialization here should only be needed to
7972 suppress warnings. */
7975 /* USED_REGS is the set of registers that are used before the
7976 next I/O instruction. */
7977 CLEAR_HARD_REG_SET (used_regs);
7979 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7980 if (GET_CODE (insn) == CALL_INSN)
7982 /* We can't predict what a call will do to volatile memory. */
7983 memset (next_io, 0, sizeof (struct frv_io));
7984 next_is_end_p = false;
7985 CLEAR_HARD_REG_SET (used_regs);
7987 else if (INSN_P (insn))
7988 switch (recog_memoized (insn))
7990 case CODE_FOR_optional_membar_qi:
7991 case CODE_FOR_optional_membar_hi:
7992 case CODE_FOR_optional_membar_si:
7993 case CODE_FOR_optional_membar_di:
7997 /* Local information isn't enough to decide whether this
7998 membar is needed. Stash it away for later. */
7999 *last_membar = insn;
8000 frv_extract_membar (next_io, insn);
8001 next_is_end_p = false;
8005 /* Check whether the I/O operation before INSN could be
8006 reordered with one described by NEXT_IO. If it can't,
8007 INSN will not be needed. */
8008 struct frv_io prev_io;
8010 frv_extract_membar (&prev_io, insn);
8011 if (frv_io_fixed_order_p (&prev_io, next_io))
8015 ";; [Local] Removing membar %d since order"
8016 " of accesses is guaranteed\n",
8017 INSN_UID (next_membar));
8019 insn = NEXT_INSN (insn);
8020 delete_insn (next_membar);
8028 /* Invalidate NEXT_IO's address if it depends on something that
8029 is clobbered by INSN. */
8030 if (next_io->var_address)
8031 note_stores (PATTERN (insn), frv_io_check_address,
8032 &next_io->var_address);
8034 /* If the next membar is associated with a __builtin_read,
8035 see if INSN reads from that address. If it does, and if
8036 the destination register is used before the next I/O access,
8037 there is no need for the membar. */
8038 set = PATTERN (insn);
8039 if (next_io->type == FRV_IO_READ
8040 && next_io->var_address != 0
8042 && GET_CODE (set) == SET
8043 && GET_CODE (SET_DEST (set)) == REG
8044 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8048 src = SET_SRC (set);
8049 if (GET_CODE (src) == ZERO_EXTEND)
8050 src = XEXP (src, 0);
8052 if (GET_CODE (src) == MEM
8053 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8057 ";; [Local] Removing membar %d since the target"
8058 " of %d is used before the I/O operation\n",
8059 INSN_UID (next_membar), INSN_UID (insn));
8061 if (next_membar == *last_membar)
8064 delete_insn (next_membar);
8069 /* If INSN has volatile references, forget about any registers
8070 that are used after it. Otherwise forget about uses that
8071 are (or might be) defined by INSN. */
8072 if (volatile_refs_p (PATTERN (insn)))
8073 CLEAR_HARD_REG_SET (used_regs);
8075 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8077 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8082 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8083 FIRST_IO[X] describes the first operation performed by basic block X. */
8086 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8089 struct frv_io this_io, next_io;
8093 /* We need to keep the membar if there is an edge to the exit block. */
8094 FOR_EACH_EDGE (succ, ei, bb->succs)
8095 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8096 if (succ->dest == EXIT_BLOCK_PTR)
8099 /* Work out the union of all successor blocks. */
8100 ei = ei_start (bb->succs);
8101 ei_cond (ei, &succ);
8102 /* next_io = first_io[bb->succ->dest->index]; */
8103 next_io = first_io[succ->dest->index];
8104 ei = ei_start (bb->succs);
8105 if (ei_cond (ei, &succ))
8107 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8108 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8109 frv_io_union (&next_io, &first_io[succ->dest->index]);
8114 frv_extract_membar (&this_io, membar);
8115 if (frv_io_fixed_order_p (&this_io, &next_io))
8119 ";; [Global] Removing membar %d since order of accesses"
8120 " is guaranteed\n", INSN_UID (membar));
8122 delete_insn (membar);
8126 /* Remove redundant membars from the current function. */
8129 frv_optimize_membar (void)
8132 struct frv_io *first_io;
8135 compute_bb_for_insn ();
8136 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8137 last_membar = XCNEWVEC (rtx, last_basic_block);
8140 frv_optimize_membar_local (bb, &first_io[bb->index],
8141 &last_membar[bb->index]);
8144 if (last_membar[bb->index] != 0)
8145 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8151 /* Used by frv_reorg to keep track of the current packet's address. */
8152 static unsigned int frv_packet_address;
8154 /* If the current packet falls through to a label, try to pad the packet
8155 with nops in order to fit the label's alignment requirements. */
8158 frv_align_label (void)
8160 unsigned int alignment, target, nop;
8161 rtx x, last, barrier, label;
8163 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8164 maximum alignment of that packet, LABEL to the last label between
8165 the packets, and BARRIER to the last barrier. */
8166 last = frv_packet.insns[frv_packet.num_insns - 1];
8167 label = barrier = 0;
8169 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8173 unsigned int subalign = 1 << label_to_alignment (x);
8174 alignment = MAX (alignment, subalign);
8181 /* If -malign-labels, and the packet falls through to an unaligned
8182 label, try introducing a nop to align that label to 8 bytes. */
8183 if (TARGET_ALIGN_LABELS
8186 && frv_packet.num_insns < frv_packet.issue_rate)
8187 alignment = MAX (alignment, 8);
8189 /* Advance the address to the end of the current packet. */
8190 frv_packet_address += frv_packet.num_insns * 4;
8192 /* Work out the target address, after alignment. */
8193 target = (frv_packet_address + alignment - 1) & -alignment;
8195 /* If the packet falls through to the label, try to find an efficient
8196 padding sequence. */
8199 /* First try adding nops to the current packet. */
8200 for (nop = 0; nop < frv_num_nops; nop++)
8201 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8203 frv_insert_nop_in_packet (frv_nops[nop]);
8204 frv_packet_address += 4;
8207 /* If we still haven't reached the target, add some new packets that
8208 contain only nops. If there are two types of nop, insert an
8209 alternating sequence of frv_nops[0] and frv_nops[1], which will
8210 lead to packets like:
8217 etc. Just emit frv_nops[0] if that's the only nop we have. */
8218 last = frv_packet.insns[frv_packet.num_insns - 1];
8220 while (frv_packet_address < target)
8222 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8223 frv_packet_address += 4;
8224 if (frv_num_nops > 1)
8229 frv_packet_address = target;
8232 /* Subroutine of frv_reorg, called after each packet has been constructed
8236 frv_reorg_packet (void)
8238 frv_fill_unused_units (GROUP_I);
8239 frv_fill_unused_units (GROUP_FM);
8243 /* Add an instruction with pattern NOP to frv_nops[]. */
8246 frv_register_nop (rtx nop)
8248 nop = make_insn_raw (nop);
8249 NEXT_INSN (nop) = 0;
8250 PREV_INSN (nop) = 0;
8251 frv_nops[frv_num_nops++] = nop;
8254 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8255 into packets and check whether we need to insert nops in order to
8256 fulfill the processor's issue requirements. Also, if the user has
8257 requested a certain alignment for a label, try to meet that alignment
8258 by inserting nops in the previous packet. */
8263 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8264 frv_optimize_membar ();
8267 frv_register_nop (gen_nop ());
8269 frv_register_nop (gen_mnop ());
8270 if (TARGET_HARD_FLOAT)
8271 frv_register_nop (gen_fnop ());
8273 /* Estimate the length of each branch. Although this may change after
8274 we've inserted nops, it will only do so in big functions. */
8275 shorten_branches (get_insns ());
8277 frv_packet_address = 0;
8278 frv_for_each_packet (frv_reorg_packet);
8281 #define def_builtin(name, type, code) \
8282 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8284 struct builtin_description
8286 enum insn_code icode;
8288 enum frv_builtins code;
8289 enum rtx_code comparison;
8293 /* Media intrinsics that take a single, constant argument. */
8295 static struct builtin_description bdesc_set[] =
8297 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8300 /* Media intrinsics that take just one argument. */
8302 static struct builtin_description bdesc_1arg[] =
8304 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8305 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8306 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8307 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8308 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8309 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8312 /* Media intrinsics that take two arguments. */
8314 static struct builtin_description bdesc_2arg[] =
8316 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8317 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8318 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8319 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8320 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8321 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8322 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8323 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8324 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8325 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8326 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8327 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8328 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8329 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8330 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8331 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8332 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8333 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8334 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8335 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8336 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8337 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8338 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8339 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8340 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8341 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8342 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8345 /* Integer intrinsics that take two arguments and have no return value. */
8347 static struct builtin_description bdesc_int_void2arg[] =
8349 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8350 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8351 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8354 static struct builtin_description bdesc_prefetches[] =
8356 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8357 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8360 /* Media intrinsics that take two arguments, the first being an ACC number. */
8362 static struct builtin_description bdesc_cut[] =
8364 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8365 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8366 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8369 /* Two-argument media intrinsics with an immediate second argument. */
8371 static struct builtin_description bdesc_2argimm[] =
8373 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8374 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8375 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8376 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8377 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8378 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8379 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8380 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8381 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8382 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8383 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8384 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8385 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8386 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8387 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8388 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8389 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8392 /* Media intrinsics that take two arguments and return void, the first argument
8393 being a pointer to 4 words in memory. */
8395 static struct builtin_description bdesc_void2arg[] =
8397 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8398 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8401 /* Media intrinsics that take three arguments, the first being a const_int that
8402 denotes an accumulator, and that return void. */
8404 static struct builtin_description bdesc_void3arg[] =
8406 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8407 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8408 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8409 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8410 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8411 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8412 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8413 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8414 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8415 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8416 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8417 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8418 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8419 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8420 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8421 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8422 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8423 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8424 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8425 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8426 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8427 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8428 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8429 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8430 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8433 /* Media intrinsics that take two accumulator numbers as argument and
8436 static struct builtin_description bdesc_voidacc[] =
8438 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8439 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8440 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8441 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8442 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8443 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8446 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8447 a normal move and the ICODE is for the membar. */
8449 static struct builtin_description bdesc_loads[] =
8451 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8452 FRV_BUILTIN_READ8, 0, 0 },
8453 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8454 FRV_BUILTIN_READ16, 0, 0 },
8455 { CODE_FOR_optional_membar_si, "__builtin_read32",
8456 FRV_BUILTIN_READ32, 0, 0 },
8457 { CODE_FOR_optional_membar_di, "__builtin_read64",
8458 FRV_BUILTIN_READ64, 0, 0 }
8461 /* Likewise stores. */
8463 static struct builtin_description bdesc_stores[] =
8465 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8466 FRV_BUILTIN_WRITE8, 0, 0 },
8467 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8468 FRV_BUILTIN_WRITE16, 0, 0 },
8469 { CODE_FOR_optional_membar_si, "__builtin_write32",
8470 FRV_BUILTIN_WRITE32, 0, 0 },
8471 { CODE_FOR_optional_membar_di, "__builtin_write64",
8472 FRV_BUILTIN_WRITE64, 0, 0 },
8475 /* Initialize media builtins. */
8478 frv_init_builtins (void)
8480 tree endlink = void_list_node;
8481 tree accumulator = integer_type_node;
8482 tree integer = integer_type_node;
8483 tree voidt = void_type_node;
8484 tree uhalf = short_unsigned_type_node;
8485 tree sword1 = long_integer_type_node;
8486 tree uword1 = long_unsigned_type_node;
8487 tree sword2 = long_long_integer_type_node;
8488 tree uword2 = long_long_unsigned_type_node;
8489 tree uword4 = build_pointer_type (uword1);
8490 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8491 tree ubyte = unsigned_char_type_node;
8492 tree iacc = integer_type_node;
8494 #define UNARY(RET, T1) \
8495 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8497 #define BINARY(RET, T1, T2) \
8498 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8499 tree_cons (NULL_TREE, T2, endlink)))
8501 #define TRINARY(RET, T1, T2, T3) \
8502 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8503 tree_cons (NULL_TREE, T2, \
8504 tree_cons (NULL_TREE, T3, endlink))))
8506 #define QUAD(RET, T1, T2, T3, T4) \
8507 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8508 tree_cons (NULL_TREE, T2, \
8509 tree_cons (NULL_TREE, T3, \
8510 tree_cons (NULL_TREE, T4, endlink)))))
8512 tree void_ftype_void = build_function_type (voidt, endlink);
8514 tree void_ftype_acc = UNARY (voidt, accumulator);
8515 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8516 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8517 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8518 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8519 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8520 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8521 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8522 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8524 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8525 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8526 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8527 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8528 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8529 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8530 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8531 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8532 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8533 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8534 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8536 tree sw1_ftype_int = UNARY (sword1, integer);
8537 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8538 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8540 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8541 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8542 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8543 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8544 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8545 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8547 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8548 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8549 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8550 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8551 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8552 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8553 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8554 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8555 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8556 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8557 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8558 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8559 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8560 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8561 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8562 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8563 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8565 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8566 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8567 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8568 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8569 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8570 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8571 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8572 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8573 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8574 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8575 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8576 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8577 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8578 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8579 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8580 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8581 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8582 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8583 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8584 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8585 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8586 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8587 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8588 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8589 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8590 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8591 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8592 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8593 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8594 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8595 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8596 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8597 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8598 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8599 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8600 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8601 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8602 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8603 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8604 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8605 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8606 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8607 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8608 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8609 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8610 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8611 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8612 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8613 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8614 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8615 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8616 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8617 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8618 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8619 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8620 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8621 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8622 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8623 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8624 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8625 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8626 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8627 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8628 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8629 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8630 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8631 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8632 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8633 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8634 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8635 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8636 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8637 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8638 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8639 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8640 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8641 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8642 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8643 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8644 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8645 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8646 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8647 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8648 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8649 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8650 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8651 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8652 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8653 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8654 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8655 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8656 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8657 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8658 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8659 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8660 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8661 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8662 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8663 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8664 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8665 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8666 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8667 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8668 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8669 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8670 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8671 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8672 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8674 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8675 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8676 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8677 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8685 /* Set the names for various arithmetic operations according to the
8688 frv_init_libfuncs (void)
8690 set_optab_libfunc (smod_optab, SImode, "__modi");
8691 set_optab_libfunc (umod_optab, SImode, "__umodi");
8693 set_optab_libfunc (add_optab, DImode, "__addll");
8694 set_optab_libfunc (sub_optab, DImode, "__subll");
8695 set_optab_libfunc (smul_optab, DImode, "__mulll");
8696 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8697 set_optab_libfunc (smod_optab, DImode, "__modll");
8698 set_optab_libfunc (umod_optab, DImode, "__umodll");
8699 set_optab_libfunc (and_optab, DImode, "__andll");
8700 set_optab_libfunc (ior_optab, DImode, "__orll");
8701 set_optab_libfunc (xor_optab, DImode, "__xorll");
8702 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8704 set_optab_libfunc (add_optab, SFmode, "__addf");
8705 set_optab_libfunc (sub_optab, SFmode, "__subf");
8706 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8707 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8709 set_optab_libfunc (add_optab, DFmode, "__addd");
8710 set_optab_libfunc (sub_optab, DFmode, "__subd");
8711 set_optab_libfunc (smul_optab, DFmode, "__muld");
8712 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8714 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8715 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8717 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8718 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8719 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8720 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8722 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8723 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8724 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8725 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8727 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8728 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8729 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8730 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8733 /* Convert an integer constant to an accumulator register. ICODE is the
8734 code of the target instruction, OPNUM is the number of the
8735 accumulator operand and OPVAL is the constant integer. Try both
8736 ACC and ACCG registers; only report an error if neither fit the
8740 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8745 /* ACCs and ACCGs are implicit global registers if media intrinsics
8746 are being used. We set up this lazily to avoid creating lots of
8747 unnecessary call_insn rtl in non-media code. */
8748 for (i = 0; i <= ACC_MASK; i++)
8749 if ((i & ACC_MASK) == i)
8750 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8752 if (GET_CODE (opval) != CONST_INT)
8754 error ("accumulator is not a constant integer");
8757 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8759 error ("accumulator number is out of bounds");
8763 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8764 ACC_FIRST + INTVAL (opval));
8765 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8766 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8768 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8770 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8776 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8779 static enum machine_mode
8780 frv_matching_accg_mode (enum machine_mode mode)
8798 /* Given that a __builtin_read or __builtin_write function is accessing
8799 address ADDRESS, return the value that should be used as operand 1
8803 frv_io_address_cookie (rtx address)
8805 return (GET_CODE (address) == CONST_INT
8806 ? GEN_INT (INTVAL (address) / 8 * 8)
8810 /* Return the accumulator guard that should be paired with accumulator
8811 register ACC. The mode of the returned register is in the same
8812 class as ACC, but is four times smaller. */
8815 frv_matching_accg_for_acc (rtx acc)
8817 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8818 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8821 /* Read the requested argument from the call EXP given by INDEX.
8822 Return the value as an rtx. */
8825 frv_read_argument (tree exp, unsigned int index)
8827 return expand_expr (CALL_EXPR_ARG (exp, index),
8828 NULL_RTX, VOIDmode, 0);
8831 /* Like frv_read_argument, but interpret the argument as the number
8832 of an IACC register and return a (reg:MODE ...) rtx for it. */
8835 frv_read_iacc_argument (enum machine_mode mode, tree call,
8841 op = frv_read_argument (call, index);
8842 if (GET_CODE (op) != CONST_INT
8844 || INTVAL (op) > IACC_LAST - IACC_FIRST
8845 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8847 error ("invalid IACC argument");
8851 /* IACCs are implicit global registers. We set up this lazily to
8852 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8854 regno = INTVAL (op) + IACC_FIRST;
8855 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8856 global_regs[regno + i] = 1;
8858 return gen_rtx_REG (mode, regno);
8861 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8862 The instruction should require a constant operand of some sort. The
8863 function prints an error if OPVAL is not valid. */
8866 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8868 if (GET_CODE (opval) != CONST_INT)
8870 error ("%qs expects a constant argument", insn_data[icode].name);
8873 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8875 error ("constant argument out of range for %qs", insn_data[icode].name);
8881 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8882 if it's not null, has the right mode, and satisfies operand 0's
8886 frv_legitimize_target (enum insn_code icode, rtx target)
8888 enum machine_mode mode = insn_data[icode].operand[0].mode;
8891 || GET_MODE (target) != mode
8892 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8893 return gen_reg_rtx (mode);
8898 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8899 check whether ARG satisfies the operand's constraints. If it doesn't,
8900 copy ARG to a temporary register and return that. Otherwise return ARG
8904 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8906 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8908 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8911 return copy_to_mode_reg (mode, arg);
8914 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8917 frv_volatile_memref (enum machine_mode mode, rtx arg)
8921 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8922 MEM_VOLATILE_P (mem) = 1;
8926 /* Expand builtins that take a single, constant argument. At the moment,
8927 only MHDSETS falls into this category. */
8930 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8933 rtx op0 = frv_read_argument (call, 0);
8935 if (! frv_check_constant_argument (icode, 1, op0))
8938 target = frv_legitimize_target (icode, target);
8939 pat = GEN_FCN (icode) (target, op0);
8947 /* Expand builtins that take one operand. */
8950 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8953 rtx op0 = frv_read_argument (call, 0);
8955 target = frv_legitimize_target (icode, target);
8956 op0 = frv_legitimize_argument (icode, 1, op0);
8957 pat = GEN_FCN (icode) (target, op0);
8965 /* Expand builtins that take two operands. */
8968 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8971 rtx op0 = frv_read_argument (call, 0);
8972 rtx op1 = frv_read_argument (call, 1);
8974 target = frv_legitimize_target (icode, target);
8975 op0 = frv_legitimize_argument (icode, 1, op0);
8976 op1 = frv_legitimize_argument (icode, 2, op1);
8977 pat = GEN_FCN (icode) (target, op0, op1);
8985 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8989 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8992 rtx op0 = frv_read_argument (call, 0);
8993 rtx op1 = frv_read_argument (call, 1);
8996 target = frv_legitimize_target (icode, target);
8997 op0 = frv_int_to_acc (icode, 1, op0);
9001 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9003 if (! frv_check_constant_argument (icode, 2, op1))
9007 op1 = frv_legitimize_argument (icode, 2, op1);
9009 op2 = frv_matching_accg_for_acc (op0);
9010 pat = GEN_FCN (icode) (target, op0, op1, op2);
9018 /* Expand builtins that take two operands and the second is immediate. */
9021 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
9024 rtx op0 = frv_read_argument (call, 0);
9025 rtx op1 = frv_read_argument (call, 1);
9027 if (! frv_check_constant_argument (icode, 2, op1))
9030 target = frv_legitimize_target (icode, target);
9031 op0 = frv_legitimize_argument (icode, 1, op0);
9032 pat = GEN_FCN (icode) (target, op0, op1);
9040 /* Expand builtins that take two operands, the first operand being a pointer to
9041 ints and return void. */
9044 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9047 rtx op0 = frv_read_argument (call, 0);
9048 rtx op1 = frv_read_argument (call, 1);
9049 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9052 if (GET_CODE (op0) != MEM)
9056 if (! offsettable_address_p (0, mode0, op0))
9058 reg = gen_reg_rtx (Pmode);
9059 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9062 op0 = gen_rtx_MEM (SImode, reg);
9065 addr = XEXP (op0, 0);
9066 if (! offsettable_address_p (0, mode0, addr))
9067 addr = copy_to_mode_reg (Pmode, op0);
9069 op0 = change_address (op0, V4SImode, addr);
9070 op1 = frv_legitimize_argument (icode, 1, op1);
9071 pat = GEN_FCN (icode) (op0, op1);
9079 /* Expand builtins that take two long operands and return void. */
9082 frv_expand_int_void2arg (enum insn_code icode, tree call)
9085 rtx op0 = frv_read_argument (call, 0);
9086 rtx op1 = frv_read_argument (call, 1);
9088 op0 = frv_legitimize_argument (icode, 1, op0);
9089 op1 = frv_legitimize_argument (icode, 1, op1);
9090 pat = GEN_FCN (icode) (op0, op1);
9098 /* Expand prefetch builtins. These take a single address as argument. */
9101 frv_expand_prefetches (enum insn_code icode, tree call)
9104 rtx op0 = frv_read_argument (call, 0);
9106 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9114 /* Expand builtins that take three operands and return void. The first
9115 argument must be a constant that describes a pair or quad accumulators. A
9116 fourth argument is created that is the accumulator guard register that
9117 corresponds to the accumulator. */
9120 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9123 rtx op0 = frv_read_argument (call, 0);
9124 rtx op1 = frv_read_argument (call, 1);
9125 rtx op2 = frv_read_argument (call, 2);
9128 op0 = frv_int_to_acc (icode, 0, op0);
9132 op1 = frv_legitimize_argument (icode, 1, op1);
9133 op2 = frv_legitimize_argument (icode, 2, op2);
9134 op3 = frv_matching_accg_for_acc (op0);
9135 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9143 /* Expand builtins that perform accumulator-to-accumulator operations.
9144 These builtins take two accumulator numbers as argument and return
9148 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9151 rtx op0 = frv_read_argument (call, 0);
9152 rtx op1 = frv_read_argument (call, 1);
9156 op0 = frv_int_to_acc (icode, 0, op0);
9160 op1 = frv_int_to_acc (icode, 1, op1);
9164 op2 = frv_matching_accg_for_acc (op0);
9165 op3 = frv_matching_accg_for_acc (op1);
9166 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9174 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9175 membar and TARGET_MODE is the mode that the loaded value should have. */
9178 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9179 tree call, rtx target)
9181 rtx op0 = frv_read_argument (call, 0);
9182 rtx cookie = frv_io_address_cookie (op0);
9184 if (target == 0 || !REG_P (target))
9185 target = gen_reg_rtx (target_mode);
9186 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9187 convert_move (target, op0, 1);
9188 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9189 cfun->machine->has_membar_p = 1;
9193 /* Likewise __builtin_write* functions. */
9196 frv_expand_store_builtin (enum insn_code icode, tree call)
9198 rtx op0 = frv_read_argument (call, 0);
9199 rtx op1 = frv_read_argument (call, 1);
9200 rtx cookie = frv_io_address_cookie (op0);
9202 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9203 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9204 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9205 cfun->machine->has_membar_p = 1;
9209 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9210 each argument forms one word of the two double-word input registers.
9211 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9212 to put the return value. */
9215 frv_expand_mdpackh_builtin (tree call, rtx target)
9217 enum insn_code icode = CODE_FOR_mdpackh;
9219 rtx arg1 = frv_read_argument (call, 0);
9220 rtx arg2 = frv_read_argument (call, 1);
9221 rtx arg3 = frv_read_argument (call, 2);
9222 rtx arg4 = frv_read_argument (call, 3);
9224 target = frv_legitimize_target (icode, target);
9225 op0 = gen_reg_rtx (DImode);
9226 op1 = gen_reg_rtx (DImode);
9228 /* The high half of each word is not explicitly initialized, so indicate
9229 that the input operands are not live before this point. */
9233 /* Move each argument into the low half of its associated input word. */
9234 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9235 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9236 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9237 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9239 pat = GEN_FCN (icode) (target, op0, op1);
9247 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9248 number as argument. */
9251 frv_expand_mclracc_builtin (tree call)
9253 enum insn_code icode = CODE_FOR_mclracc;
9255 rtx op0 = frv_read_argument (call, 0);
9257 op0 = frv_int_to_acc (icode, 0, op0);
9261 pat = GEN_FCN (icode) (op0);
9268 /* Expand builtins that take no arguments. */
9271 frv_expand_noargs_builtin (enum insn_code icode)
9273 rtx pat = GEN_FCN (icode) (const0_rtx);
9280 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9281 number or accumulator guard number as argument and return an SI integer. */
9284 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9287 rtx target = gen_reg_rtx (SImode);
9288 rtx op0 = frv_read_argument (call, 0);
9290 op0 = frv_int_to_acc (icode, 1, op0);
9294 pat = GEN_FCN (icode) (target, op0);
9302 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9303 accumulator guard as their first argument and an SImode value as their
9307 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9310 rtx op0 = frv_read_argument (call, 0);
9311 rtx op1 = frv_read_argument (call, 1);
9313 op0 = frv_int_to_acc (icode, 0, op0);
9317 op1 = frv_legitimize_argument (icode, 1, op1);
9318 pat = GEN_FCN (icode) (op0, op1);
9325 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9326 to move DImode values into and out of IACC0. */
9329 frv_split_iacc_move (rtx dest, rtx src)
9331 enum machine_mode inner;
9334 inner = GET_MODE (dest);
9335 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9336 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9337 simplify_gen_subreg (SImode, src, inner, i));
9340 /* Expand builtins. */
9343 frv_expand_builtin (tree exp,
9345 rtx subtarget ATTRIBUTE_UNUSED,
9346 enum machine_mode mode ATTRIBUTE_UNUSED,
9347 int ignore ATTRIBUTE_UNUSED)
9349 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9350 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9352 struct builtin_description *d;
9354 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9356 error ("media functions are not available unless -mmedia is used");
9362 case FRV_BUILTIN_MCOP1:
9363 case FRV_BUILTIN_MCOP2:
9364 case FRV_BUILTIN_MDUNPACKH:
9365 case FRV_BUILTIN_MBTOHE:
9366 if (! TARGET_MEDIA_REV1)
9368 error ("this media function is only available on the fr500");
9373 case FRV_BUILTIN_MQXMACHS:
9374 case FRV_BUILTIN_MQXMACXHS:
9375 case FRV_BUILTIN_MQMACXHS:
9376 case FRV_BUILTIN_MADDACCS:
9377 case FRV_BUILTIN_MSUBACCS:
9378 case FRV_BUILTIN_MASACCS:
9379 case FRV_BUILTIN_MDADDACCS:
9380 case FRV_BUILTIN_MDSUBACCS:
9381 case FRV_BUILTIN_MDASACCS:
9382 case FRV_BUILTIN_MABSHS:
9383 case FRV_BUILTIN_MDROTLI:
9384 case FRV_BUILTIN_MCPLHI:
9385 case FRV_BUILTIN_MCPLI:
9386 case FRV_BUILTIN_MDCUTSSI:
9387 case FRV_BUILTIN_MQSATHS:
9388 case FRV_BUILTIN_MHSETLOS:
9389 case FRV_BUILTIN_MHSETLOH:
9390 case FRV_BUILTIN_MHSETHIS:
9391 case FRV_BUILTIN_MHSETHIH:
9392 case FRV_BUILTIN_MHDSETS:
9393 case FRV_BUILTIN_MHDSETH:
9394 if (! TARGET_MEDIA_REV2)
9396 error ("this media function is only available on the fr400"
9402 case FRV_BUILTIN_SMASS:
9403 case FRV_BUILTIN_SMSSS:
9404 case FRV_BUILTIN_SMU:
9405 case FRV_BUILTIN_ADDSS:
9406 case FRV_BUILTIN_SUBSS:
9407 case FRV_BUILTIN_SLASS:
9408 case FRV_BUILTIN_SCUTSS:
9409 case FRV_BUILTIN_IACCreadll:
9410 case FRV_BUILTIN_IACCreadl:
9411 case FRV_BUILTIN_IACCsetll:
9412 case FRV_BUILTIN_IACCsetl:
9413 if (!TARGET_FR405_BUILTINS)
9415 error ("this builtin function is only available"
9416 " on the fr405 and fr450");
9421 case FRV_BUILTIN_PREFETCH:
9422 if (!TARGET_FR500_FR550_BUILTINS)
9424 error ("this builtin function is only available on the fr500"
9430 case FRV_BUILTIN_MQLCLRHS:
9431 case FRV_BUILTIN_MQLMTHS:
9432 case FRV_BUILTIN_MQSLLHI:
9433 case FRV_BUILTIN_MQSRAHI:
9434 if (!TARGET_MEDIA_FR450)
9436 error ("this builtin function is only available on the fr450");
9445 /* Expand unique builtins. */
9449 case FRV_BUILTIN_MTRAP:
9450 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9452 case FRV_BUILTIN_MCLRACC:
9453 return frv_expand_mclracc_builtin (exp);
9455 case FRV_BUILTIN_MCLRACCA:
9457 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9459 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9461 case FRV_BUILTIN_MRDACC:
9462 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9464 case FRV_BUILTIN_MRDACCG:
9465 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9467 case FRV_BUILTIN_MWTACC:
9468 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9470 case FRV_BUILTIN_MWTACCG:
9471 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9473 case FRV_BUILTIN_MDPACKH:
9474 return frv_expand_mdpackh_builtin (exp, target);
9476 case FRV_BUILTIN_IACCreadll:
9478 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9479 if (target == 0 || !REG_P (target))
9480 target = gen_reg_rtx (DImode);
9481 frv_split_iacc_move (target, src);
9485 case FRV_BUILTIN_IACCreadl:
9486 return frv_read_iacc_argument (SImode, exp, 0);
9488 case FRV_BUILTIN_IACCsetll:
9490 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9491 rtx src = frv_read_argument (exp, 1);
9492 frv_split_iacc_move (dest, force_reg (DImode, src));
9496 case FRV_BUILTIN_IACCsetl:
9498 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9499 rtx src = frv_read_argument (exp, 1);
9500 emit_move_insn (dest, force_reg (SImode, src));
9508 /* Expand groups of builtins. */
9510 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9511 if (d->code == fcode)
9512 return frv_expand_set_builtin (d->icode, exp, target);
9514 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9515 if (d->code == fcode)
9516 return frv_expand_unop_builtin (d->icode, exp, target);
9518 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9519 if (d->code == fcode)
9520 return frv_expand_binop_builtin (d->icode, exp, target);
9522 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9523 if (d->code == fcode)
9524 return frv_expand_cut_builtin (d->icode, exp, target);
9526 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9527 if (d->code == fcode)
9528 return frv_expand_binopimm_builtin (d->icode, exp, target);
9530 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9531 if (d->code == fcode)
9532 return frv_expand_voidbinop_builtin (d->icode, exp);
9534 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9535 if (d->code == fcode)
9536 return frv_expand_voidtriop_builtin (d->icode, exp);
9538 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9539 if (d->code == fcode)
9540 return frv_expand_voidaccop_builtin (d->icode, exp);
9542 for (i = 0, d = bdesc_int_void2arg;
9543 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9544 if (d->code == fcode)
9545 return frv_expand_int_void2arg (d->icode, exp);
9547 for (i = 0, d = bdesc_prefetches;
9548 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9549 if (d->code == fcode)
9550 return frv_expand_prefetches (d->icode, exp);
9552 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9553 if (d->code == fcode)
9554 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9557 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9558 if (d->code == fcode)
9559 return frv_expand_store_builtin (d->icode, exp);
9565 frv_in_small_data_p (const_tree decl)
9568 const_tree section_name;
9570 /* Don't apply the -G flag to internal compiler structures. We
9571 should leave such structures in the main data section, partly
9572 for efficiency and partly because the size of some of them
9573 (such as C++ typeinfos) is not known until later. */
9574 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9577 /* If we already know which section the decl should be in, see if
9578 it's a small data section. */
9579 section_name = DECL_SECTION_NAME (decl);
9582 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9583 if (frv_string_begins_with (section_name, ".sdata"))
9585 if (frv_string_begins_with (section_name, ".sbss"))
9590 size = int_size_in_bytes (TREE_TYPE (decl));
9591 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9598 frv_rtx_costs (rtx x,
9599 int code ATTRIBUTE_UNUSED,
9600 int outer_code ATTRIBUTE_UNUSED,
9602 bool speed ATTRIBUTE_UNUSED)
9604 if (outer_code == MEM)
9606 /* Don't differentiate between memory addresses. All the ones
9607 we accept have equal cost. */
9608 *total = COSTS_N_INSNS (0);
9615 /* Make 12-bit integers really cheap. */
9616 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9627 *total = COSTS_N_INSNS (2);
9641 if (GET_MODE (x) == SImode)
9642 *total = COSTS_N_INSNS (1);
9643 else if (GET_MODE (x) == DImode)
9644 *total = COSTS_N_INSNS (2);
9646 *total = COSTS_N_INSNS (3);
9650 if (GET_MODE (x) == SImode)
9651 *total = COSTS_N_INSNS (2);
9653 *total = COSTS_N_INSNS (6); /* guess */
9660 *total = COSTS_N_INSNS (18);
9664 *total = COSTS_N_INSNS (3);
9673 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9675 switch_to_section (ctors_section);
9676 assemble_align (POINTER_SIZE);
9679 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9684 assemble_integer_with_op ("\t.picptr\t", symbol);
9688 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9690 switch_to_section (dtors_section);
9691 assemble_align (POINTER_SIZE);
9694 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9699 assemble_integer_with_op ("\t.picptr\t", symbol);
9702 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9705 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9706 int incoming ATTRIBUTE_UNUSED)
9708 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9711 #define TLS_BIAS (2048 - 16)
9713 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9714 We need to emit DTP-relative relocations. */
9717 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9719 gcc_assert (size == 4);
9720 fputs ("\t.picptr\ttlsmoff(", file);
9721 /* We want the unbiased TLS offset, so add the bias to the
9722 expression, such that the implicit biasing cancels out. */
9723 output_addr_const (file, plus_constant (x, TLS_BIAS));