1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static void frv_option_override (void);
268 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
269 static int frv_default_flags_for_cpu (void);
270 static int frv_string_begins_with (const_tree, const char *);
271 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
272 static void frv_print_operand (FILE *, rtx, int);
273 static void frv_print_operand_address (FILE *, rtx);
274 static bool frv_print_operand_punct_valid_p (unsigned char code);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static const char *comparison_string (enum rtx_code, rtx);
280 static rtx frv_function_value (const_tree, const_tree,
282 static rtx frv_libcall_value (enum machine_mode,
284 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
285 static rtx single_set_pattern (rtx);
286 static int frv_function_contains_far_jump (void);
287 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
291 static rtx frv_frame_offset_rtx (int);
292 static rtx frv_frame_mem (enum machine_mode, rtx, int);
293 static rtx frv_dwarf_store (rtx, int);
294 static void frv_frame_insn (rtx, rtx);
295 static void frv_frame_access (frv_frame_accessor_t*,
297 static void frv_frame_access_multi (frv_frame_accessor_t*,
299 static void frv_frame_access_standard_regs (enum frv_stack_op,
301 static struct machine_function *frv_init_machine_status (void);
302 static rtx frv_int_to_acc (enum insn_code, int, rtx);
303 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
304 static rtx frv_read_argument (tree, unsigned int);
305 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
306 static int frv_check_constant_argument (enum insn_code, int, rtx);
307 static rtx frv_legitimize_target (enum insn_code, rtx);
308 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
309 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
310 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
311 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
312 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
313 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
314 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
315 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
316 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
317 static rtx frv_expand_int_void2arg (enum insn_code, tree);
318 static rtx frv_expand_prefetches (enum insn_code, tree);
319 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
320 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
321 static rtx frv_expand_mclracc_builtin (tree);
322 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
323 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
324 static rtx frv_expand_noargs_builtin (enum insn_code);
325 static void frv_split_iacc_move (rtx, rtx);
326 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
327 static int frv_clear_registers_used (rtx *, void *);
328 static void frv_ifcvt_add_insn (rtx, rtx, int);
329 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
330 static rtx frv_ifcvt_load_value (rtx, rtx);
331 static int frv_acc_group_1 (rtx *, void *);
332 static unsigned int frv_insn_unit (rtx);
333 static bool frv_issues_to_branch_unit_p (rtx);
334 static int frv_cond_flags (rtx);
335 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
336 static int frv_registers_conflict_p_1 (rtx *, void *);
337 static bool frv_registers_conflict_p (rtx);
338 static void frv_registers_update_1 (rtx, const_rtx, void *);
339 static void frv_registers_update (rtx);
340 static void frv_start_packet (void);
341 static void frv_start_packet_block (void);
342 static void frv_finish_packet (void (*) (void));
343 static bool frv_pack_insn_p (rtx);
344 static void frv_add_insn_to_packet (rtx);
345 static void frv_insert_nop_in_packet (rtx);
346 static bool frv_for_each_packet (void (*) (void));
347 static bool frv_sort_insn_group_1 (enum frv_insn_group,
348 unsigned int, unsigned int,
349 unsigned int, unsigned int,
351 static int frv_compare_insns (const void *, const void *);
352 static void frv_sort_insn_group (enum frv_insn_group);
353 static void frv_reorder_packet (void);
354 static void frv_fill_unused_units (enum frv_insn_group);
355 static void frv_align_label (void);
356 static void frv_reorg_packet (void);
357 static void frv_register_nop (rtx);
358 static void frv_reorg (void);
359 static void frv_pack_insns (void);
360 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
361 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
362 static bool frv_assemble_integer (rtx, unsigned, int);
363 static void frv_init_builtins (void);
364 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
365 static void frv_init_libfuncs (void);
366 static bool frv_in_small_data_p (const_tree);
367 static void frv_asm_output_mi_thunk
368 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
369 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
372 static rtx frv_expand_builtin_saveregs (void);
373 static void frv_expand_builtin_va_start (tree, rtx);
374 static bool frv_rtx_costs (rtx, int, int, int*, bool);
375 static int frv_register_move_cost (enum machine_mode,
376 reg_class_t, reg_class_t);
377 static int frv_memory_move_cost (enum machine_mode,
379 static void frv_asm_out_constructor (rtx, int);
380 static void frv_asm_out_destructor (rtx, int);
381 static bool frv_function_symbol_referenced_p (rtx);
382 static bool frv_cannot_force_const_mem (rtx);
383 static const char *unspec_got_name (int);
384 static void frv_output_const_unspec (FILE *,
385 const struct frv_unspec *);
386 static bool frv_function_ok_for_sibcall (tree, tree);
387 static rtx frv_struct_value_rtx (tree, int);
388 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
389 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
391 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
393 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
395 secondary_reload_info *);
396 static bool frv_frame_pointer_required (void);
397 static bool frv_can_eliminate (const int, const int);
398 static void frv_trampoline_init (rtx, tree, rtx);
399 static bool frv_class_likely_spilled_p (reg_class_t);
401 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
402 static const struct default_options frv_option_optimization_table[] =
404 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
405 { OPT_LEVELS_NONE, 0, NULL, 0 }
408 /* Allow us to easily change the default for -malloc-cc. */
409 #ifndef DEFAULT_NO_ALLOC_CC
410 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
412 #define MASK_DEFAULT_ALLOC_CC 0
415 /* Initialize the GCC target structure. */
416 #undef TARGET_PRINT_OPERAND
417 #define TARGET_PRINT_OPERAND frv_print_operand
418 #undef TARGET_PRINT_OPERAND_ADDRESS
419 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
420 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
421 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
422 #undef TARGET_ASM_FUNCTION_PROLOGUE
423 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
424 #undef TARGET_ASM_FUNCTION_EPILOGUE
425 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
426 #undef TARGET_ASM_INTEGER
427 #define TARGET_ASM_INTEGER frv_assemble_integer
428 #undef TARGET_DEFAULT_TARGET_FLAGS
429 #define TARGET_DEFAULT_TARGET_FLAGS \
430 (MASK_DEFAULT_ALLOC_CC \
437 #undef TARGET_HANDLE_OPTION
438 #define TARGET_HANDLE_OPTION frv_handle_option
439 #undef TARGET_OPTION_OVERRIDE
440 #define TARGET_OPTION_OVERRIDE frv_option_override
441 #undef TARGET_OPTION_OPTIMIZATION_TABLE
442 #define TARGET_OPTION_OPTIMIZATION_TABLE frv_option_optimization_table
443 #undef TARGET_INIT_BUILTINS
444 #define TARGET_INIT_BUILTINS frv_init_builtins
445 #undef TARGET_EXPAND_BUILTIN
446 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
447 #undef TARGET_INIT_LIBFUNCS
448 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
449 #undef TARGET_IN_SMALL_DATA_P
450 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
451 #undef TARGET_REGISTER_MOVE_COST
452 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
453 #undef TARGET_MEMORY_MOVE_COST
454 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
455 #undef TARGET_RTX_COSTS
456 #define TARGET_RTX_COSTS frv_rtx_costs
457 #undef TARGET_ASM_CONSTRUCTOR
458 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
459 #undef TARGET_ASM_DESTRUCTOR
460 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
462 #undef TARGET_ASM_OUTPUT_MI_THUNK
463 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
464 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
465 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
467 #undef TARGET_SCHED_ISSUE_RATE
468 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
470 #undef TARGET_LEGITIMIZE_ADDRESS
471 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
473 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
474 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
475 #undef TARGET_CANNOT_FORCE_CONST_MEM
476 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
478 #undef TARGET_HAVE_TLS
479 #define TARGET_HAVE_TLS HAVE_AS_TLS
481 #undef TARGET_STRUCT_VALUE_RTX
482 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
483 #undef TARGET_MUST_PASS_IN_STACK
484 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
485 #undef TARGET_PASS_BY_REFERENCE
486 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
487 #undef TARGET_ARG_PARTIAL_BYTES
488 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
490 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
491 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
492 #undef TARGET_SETUP_INCOMING_VARARGS
493 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
494 #undef TARGET_MACHINE_DEPENDENT_REORG
495 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
497 #undef TARGET_EXPAND_BUILTIN_VA_START
498 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
501 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
502 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
505 #undef TARGET_CLASS_LIKELY_SPILLED_P
506 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
508 #undef TARGET_SECONDARY_RELOAD
509 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
511 #undef TARGET_LEGITIMATE_ADDRESS_P
512 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
514 #undef TARGET_FRAME_POINTER_REQUIRED
515 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
517 #undef TARGET_CAN_ELIMINATE
518 #define TARGET_CAN_ELIMINATE frv_can_eliminate
520 #undef TARGET_TRAMPOLINE_INIT
521 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
523 #undef TARGET_FUNCTION_VALUE
524 #define TARGET_FUNCTION_VALUE frv_function_value
525 #undef TARGET_LIBCALL_VALUE
526 #define TARGET_LIBCALL_VALUE frv_libcall_value
528 struct gcc_target targetm = TARGET_INITIALIZER;
530 #define FRV_SYMBOL_REF_TLS_P(RTX) \
531 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
534 /* Any function call that satisfies the machine-independent
535 requirements is eligible on FR-V. */
538 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
539 tree exp ATTRIBUTE_UNUSED)
544 /* Return true if SYMBOL is a small data symbol and relocation RELOC
545 can be used to access it directly in a load or store. */
547 static FRV_INLINE bool
548 frv_small_data_reloc_p (rtx symbol, int reloc)
550 return (GET_CODE (symbol) == SYMBOL_REF
551 && SYMBOL_REF_SMALL_P (symbol)
552 && (!TARGET_FDPIC || flag_pic == 1)
553 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
556 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
560 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
562 if (GET_CODE (x) == CONST)
566 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
568 unspec->offset += INTVAL (XEXP (x, 1));
571 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
573 unspec->symbol = XVECEXP (x, 0, 0);
574 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
576 if (unspec->offset == 0)
579 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
580 && unspec->offset > 0
581 && unspec->offset < g_switch_value)
588 /* Decide whether we can force certain constants to memory. If we
589 decide we can't, the caller should be able to cope with it in
592 We never allow constants to be forced into memory for TARGET_FDPIC.
593 This is necessary for several reasons:
595 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
596 target-independent code will try to force them into the constant
597 pool, thus leading to infinite recursion.
599 2. We can never introduce new constant pool references during reload.
600 Any such reference would require use of the pseudo FDPIC register.
602 3. We can't represent a constant added to a function pointer (which is
603 not the same as a pointer to a function+constant).
605 4. In many cases, it's more efficient to calculate the constant in-line. */
608 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
613 /* Implement TARGET_HANDLE_OPTION. */
616 frv_handle_option (size_t code, const char *arg, int value)
621 if (strcmp (arg, "simple") == 0)
622 frv_cpu_type = FRV_CPU_SIMPLE;
623 else if (strcmp (arg, "tomcat") == 0)
624 frv_cpu_type = FRV_CPU_TOMCAT;
625 else if (strcmp (arg, "fr550") == 0)
626 frv_cpu_type = FRV_CPU_FR550;
627 else if (strcmp (arg, "fr500") == 0)
628 frv_cpu_type = FRV_CPU_FR500;
629 else if (strcmp (arg, "fr450") == 0)
630 frv_cpu_type = FRV_CPU_FR450;
631 else if (strcmp (arg, "fr405") == 0)
632 frv_cpu_type = FRV_CPU_FR405;
633 else if (strcmp (arg, "fr400") == 0)
634 frv_cpu_type = FRV_CPU_FR400;
635 else if (strcmp (arg, "fr300") == 0)
636 frv_cpu_type = FRV_CPU_FR300;
637 else if (strcmp (arg, "frv") == 0)
638 frv_cpu_type = FRV_CPU_GENERIC;
649 frv_default_flags_for_cpu (void)
651 switch (frv_cpu_type)
653 case FRV_CPU_GENERIC:
654 return MASK_DEFAULT_FRV;
657 return MASK_DEFAULT_FR550;
661 return MASK_DEFAULT_FR500;
664 return MASK_DEFAULT_FR450;
668 return MASK_DEFAULT_FR400;
672 return MASK_DEFAULT_SIMPLE;
679 /* Implement TARGET_OPTION_OVERRIDE. */
682 frv_option_override (void)
687 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
689 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
690 linker about linking pic and non-pic code. */
693 if (!flag_pic) /* -fPIC */
696 if (!global_options_set.x_g_switch_value) /* -G0 */
702 /* A C expression whose value is a register class containing hard
703 register REGNO. In general there is more than one such class;
704 choose a class which is "minimal", meaning that no smaller class
705 also contains the register. */
707 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
709 enum reg_class rclass;
713 int gpr_reg = regno - GPR_FIRST;
715 if (gpr_reg == GR8_REG)
718 else if (gpr_reg == GR9_REG)
721 else if (gpr_reg == GR14_REG)
722 rclass = FDPIC_FPTR_REGS;
724 else if (gpr_reg == FDPIC_REGNO)
727 else if ((gpr_reg & 3) == 0)
730 else if ((gpr_reg & 1) == 0)
737 else if (FPR_P (regno))
739 int fpr_reg = regno - GPR_FIRST;
740 if ((fpr_reg & 3) == 0)
741 rclass = QUAD_FPR_REGS;
743 else if ((fpr_reg & 1) == 0)
750 else if (regno == LR_REGNO)
753 else if (regno == LCR_REGNO)
756 else if (ICC_P (regno))
759 else if (FCC_P (regno))
762 else if (ICR_P (regno))
765 else if (FCR_P (regno))
768 else if (ACC_P (regno))
770 int r = regno - ACC_FIRST;
772 rclass = QUAD_ACC_REGS;
773 else if ((r & 1) == 0)
774 rclass = EVEN_ACC_REGS;
779 else if (ACCG_P (regno))
785 regno_reg_class[regno] = rclass;
788 /* Check for small data option */
789 if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC)
790 g_switch_value = SDATA_DEFAULT_SIZE;
792 /* A C expression which defines the machine-dependent operand
793 constraint letters for register classes. If CHAR is such a
794 letter, the value should be the register class corresponding to
795 it. Otherwise, the value should be `NO_REGS'. The register
796 letter `r', corresponding to class `GENERAL_REGS', will not be
797 passed to this macro; you do not need to handle it.
799 The following letters are unavailable, due to being used as
804 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
805 'Q', 'R', 'S', 'T', 'U'
807 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
809 for (i = 0; i < 256; i++)
810 reg_class_from_letter[i] = NO_REGS;
812 reg_class_from_letter['a'] = ACC_REGS;
813 reg_class_from_letter['b'] = EVEN_ACC_REGS;
814 reg_class_from_letter['c'] = CC_REGS;
815 reg_class_from_letter['d'] = GPR_REGS;
816 reg_class_from_letter['e'] = EVEN_REGS;
817 reg_class_from_letter['f'] = FPR_REGS;
818 reg_class_from_letter['h'] = FEVEN_REGS;
819 reg_class_from_letter['l'] = LR_REG;
820 reg_class_from_letter['q'] = QUAD_REGS;
821 reg_class_from_letter['t'] = ICC_REGS;
822 reg_class_from_letter['u'] = FCC_REGS;
823 reg_class_from_letter['v'] = ICR_REGS;
824 reg_class_from_letter['w'] = FCR_REGS;
825 reg_class_from_letter['x'] = QUAD_FPR_REGS;
826 reg_class_from_letter['y'] = LCR_REG;
827 reg_class_from_letter['z'] = SPR_REGS;
828 reg_class_from_letter['A'] = QUAD_ACC_REGS;
829 reg_class_from_letter['B'] = ACCG_REGS;
830 reg_class_from_letter['C'] = CR_REGS;
831 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
832 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
834 /* There is no single unaligned SI op for PIC code. Sometimes we
835 need to use ".4byte" and sometimes we need to use ".picptr".
836 See frv_assemble_integer for details. */
837 if (flag_pic || TARGET_FDPIC)
838 targetm.asm_out.unaligned_op.si = 0;
840 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
841 target_flags |= MASK_LINKED_FP;
843 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
844 target_flags |= MASK_OPTIMIZE_MEMBAR;
846 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
847 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
849 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
850 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
852 init_machine_status = frv_init_machine_status;
856 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
859 frv_string_begins_with (const_tree name, const char *prefix)
861 const int prefix_len = strlen (prefix);
863 /* Remember: NAME's length includes the null terminator. */
864 return (TREE_STRING_LENGTH (name) > prefix_len
865 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
868 /* Zero or more C statements that may conditionally modify two variables
869 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
870 been initialized from the two preceding macros.
872 This is necessary in case the fixed or call-clobbered registers depend on
875 You need not define this macro if it has no work to do.
877 If the usage of an entire class of registers depends on the target flags,
878 you may indicate this to GCC by using this macro to modify `fixed_regs' and
879 `call_used_regs' to 1 for each of the registers in the classes which should
880 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
881 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
883 (However, if this class is not included in `GENERAL_REGS' and all of the
884 insn patterns whose constraints permit this class are controlled by target
885 switches, then GCC will automatically avoid using these registers when the
886 target switches are opposed to them.) */
889 frv_conditional_register_usage (void)
893 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
894 fixed_regs[i] = call_used_regs[i] = 1;
896 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
897 fixed_regs[i] = call_used_regs[i] = 1;
899 /* Reserve the registers used for conditional execution. At present, we need
900 1 ICC and 1 ICR register. */
901 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
902 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
906 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
907 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
908 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
909 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
913 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
914 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
917 /* If -fpic, SDA_BASE_REG is the PIC register. */
918 if (g_switch_value == 0 && !flag_pic)
919 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
922 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
928 * Compute the stack frame layout
931 * +---------------+-----------------------+-----------------------+
932 * |Register |type |caller-save/callee-save|
933 * +---------------+-----------------------+-----------------------+
934 * |GR0 |Zero register | - |
935 * |GR1 |Stack pointer(SP) | - |
936 * |GR2 |Frame pointer(FP) | - |
937 * |GR3 |Hidden parameter | caller save |
938 * |GR4-GR7 | - | caller save |
939 * |GR8-GR13 |Argument register | caller save |
940 * |GR14-GR15 | - | caller save |
941 * |GR16-GR31 | - | callee save |
942 * |GR32-GR47 | - | caller save |
943 * |GR48-GR63 | - | callee save |
944 * |FR0-FR15 | - | caller save |
945 * |FR16-FR31 | - | callee save |
946 * |FR32-FR47 | - | caller save |
947 * |FR48-FR63 | - | callee save |
948 * +---------------+-----------------------+-----------------------+
952 * SP-> |-----------------------------------|
954 * |-----------------------------------|
955 * | Register save area |
956 * |-----------------------------------|
957 * | Local variable save area |
958 * FP-> |-----------------------------------|
960 * |-----------------------------------|
961 * | Hidden parameter save area |
962 * |-----------------------------------|
963 * | Return address(LR) storage area |
964 * |-----------------------------------|
965 * | Padding for alignment |
966 * |-----------------------------------|
967 * | Register argument area |
968 * OLD SP-> |-----------------------------------|
970 * |-----------------------------------|
973 * Argument area/Parameter area:
975 * When a function is called, this area is used for argument transfer. When
976 * the argument is set up by the caller function, this area is referred to as
977 * the argument area. When the argument is referenced by the callee function,
978 * this area is referred to as the parameter area. The area is allocated when
979 * all arguments cannot be placed on the argument register at the time of
982 * Register save area:
984 * This is a register save area that must be guaranteed for the caller
985 * function. This area is not secured when the register save operation is not
988 * Local variable save area:
990 * This is the area for local variables and temporary variables.
994 * This area stores the FP value of the caller function.
996 * Hidden parameter save area:
998 * This area stores the start address of the return value storage
999 * area for a struct/union return function.
1000 * When a struct/union is used as the return value, the caller
1001 * function stores the return value storage area start address in
1002 * register GR3 and passes it to the caller function.
1003 * The callee function interprets the address stored in the GR3
1004 * as the return value storage area start address.
1005 * When register GR3 needs to be saved into memory, the callee
1006 * function saves it in the hidden parameter save area. This
1007 * area is not secured when the save operation is not needed.
1009 * Return address(LR) storage area:
1011 * This area saves the LR. The LR stores the address of a return to the caller
1012 * function for the purpose of function calling.
1014 * Argument register area:
1016 * This area saves the argument register. This area is not secured when the
1017 * save operation is not needed.
1021 * Arguments, the count of which equals the count of argument registers (6
1022 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1023 * function. When a struct/union return function is called, the return value
1024 * area address is stored in register GR3. Arguments not placed in the
1025 * argument registers will be stored in the stack argument area for transfer
1026 * purposes. When an 8-byte type argument is to be delivered using registers,
1027 * it is divided into two and placed in two registers for transfer. When
1028 * argument registers must be saved to memory, the callee function secures an
1029 * argument register save area in the stack. In this case, a continuous
1030 * argument register save area must be established in the parameter area. The
1031 * argument register save area must be allocated as needed to cover the size of
1032 * the argument register to be saved. If the function has a variable count of
1033 * arguments, it saves all argument registers in the argument register save
1036 * Argument Extension Format:
1038 * When an argument is to be stored in the stack, its type is converted to an
1039 * extended type in accordance with the individual argument type. The argument
1040 * is freed by the caller function after the return from the callee function is
1043 * +-----------------------+---------------+------------------------+
1044 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1045 * +-----------------------+---------------+------------------------+
1047 * |signed char |int | 4 |
1048 * |unsigned char |int | 4 |
1049 * |[signed] short int |int | 4 |
1050 * |unsigned short int |int | 4 |
1051 * |[signed] int |No extension | 4 |
1052 * |unsigned int |No extension | 4 |
1053 * |[signed] long int |No extension | 4 |
1054 * |unsigned long int |No extension | 4 |
1055 * |[signed] long long int |No extension | 8 |
1056 * |unsigned long long int |No extension | 8 |
1057 * |float |double | 8 |
1058 * |double |No extension | 8 |
1059 * |long double |No extension | 8 |
1060 * |pointer |No extension | 4 |
1061 * |struct/union |- | 4 (*1) |
1062 * +-----------------------+---------------+------------------------+
1064 * When a struct/union is to be delivered as an argument, the caller copies it
1065 * to the local variable area and delivers the address of that area.
1069 * +-------------------------------+----------------------+
1070 * |Return Value Type |Return Value Interface|
1071 * +-------------------------------+----------------------+
1073 * |[signed|unsigned] char |GR8 |
1074 * |[signed|unsigned] short int |GR8 |
1075 * |[signed|unsigned] int |GR8 |
1076 * |[signed|unsigned] long int |GR8 |
1078 * |[signed|unsigned] long long int|GR8 & GR9 |
1080 * |double |GR8 & GR9 |
1081 * |long double |GR8 & GR9 |
1082 * |struct/union |(*1) |
1083 * +-------------------------------+----------------------+
1085 * When a struct/union is used as the return value, the caller function stores
1086 * the start address of the return value storage area into GR3 and then passes
1087 * it to the callee function. The callee function interprets GR3 as the start
1088 * address of the return value storage area. When this address needs to be
1089 * saved in memory, the callee function secures the hidden parameter save area
1090 * and saves the address in that area.
1094 frv_stack_info (void)
1096 static frv_stack_t info, zero_info;
1097 frv_stack_t *info_ptr = &info;
1098 tree fndecl = current_function_decl;
1106 /* If we've already calculated the values and reload is complete,
1108 if (frv_stack_cache)
1109 return frv_stack_cache;
1111 /* Zero all fields. */
1114 /* Set up the register range information. */
1115 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1116 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1117 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1118 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1120 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1121 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1122 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1123 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1125 info_ptr->regs[STACK_REGS_LR].name = "lr";
1126 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1127 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1128 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1130 info_ptr->regs[STACK_REGS_CC].name = "cc";
1131 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1132 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1133 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1135 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1136 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1137 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1139 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1140 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1141 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1142 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1143 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1145 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1146 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1147 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1148 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1150 info_ptr->regs[STACK_REGS_FP].name = "fp";
1151 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1152 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1153 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1155 /* Determine if this is a stdarg function. If so, allocate space to store
1162 /* Find the last argument, and see if it is __builtin_va_alist. */
1163 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1165 next_arg = DECL_CHAIN (cur_arg);
1166 if (next_arg == (tree)0)
1168 if (DECL_NAME (cur_arg)
1169 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1177 /* Iterate over all of the register ranges. */
1178 for (range = 0; range < STACK_REGS_MAX; range++)
1180 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1181 int first = reg_ptr->first;
1182 int last = reg_ptr->last;
1184 int size_2words = 0;
1187 /* Calculate which registers need to be saved & save area size. */
1191 for (regno = first; regno <= last; regno++)
1193 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1194 || (crtl->calls_eh_return
1195 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1196 || (!TARGET_FDPIC && flag_pic
1197 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1199 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1200 size_1word += UNITS_PER_WORD;
1205 /* Calculate whether we need to create a frame after everything else
1206 has been processed. */
1211 if (df_regs_ever_live_p (LR_REGNO)
1213 /* This is set for __builtin_return_address, etc. */
1214 || cfun->machine->frame_needed
1215 || (TARGET_LINKED_FP && frame_pointer_needed)
1216 || (!TARGET_FDPIC && flag_pic
1217 && crtl->uses_pic_offset_table))
1219 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1220 size_1word += UNITS_PER_WORD;
1224 case STACK_REGS_STDARG:
1227 /* If this is a stdarg function with a non varardic
1228 argument split between registers and the stack,
1229 adjust the saved registers downward. */
1230 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1233 for (regno = first; regno <= last; regno++)
1235 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1236 size_1word += UNITS_PER_WORD;
1239 info_ptr->stdarg_size = size_1word;
1243 case STACK_REGS_STRUCT:
1244 if (cfun->returns_struct)
1246 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1247 size_1word += UNITS_PER_WORD;
1255 /* If this is a field, it only takes one word. */
1256 if (reg_ptr->field_p)
1257 size_1word = UNITS_PER_WORD;
1259 /* Determine which register pairs can be saved together. */
1260 else if (reg_ptr->dword_p && TARGET_DWORD)
1262 for (regno = first; regno < last; regno += 2)
1264 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1266 size_2words += 2 * UNITS_PER_WORD;
1267 size_1word -= 2 * UNITS_PER_WORD;
1268 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1269 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1274 reg_ptr->size_1word = size_1word;
1275 reg_ptr->size_2words = size_2words;
1277 if (! reg_ptr->special_p)
1279 info_ptr->regs_size_1word += size_1word;
1280 info_ptr->regs_size_2words += size_2words;
1285 /* Set up the sizes of each each field in the frame body, making the sizes
1286 of each be divisible by the size of a dword if dword operations might
1287 be used, or the size of a word otherwise. */
1288 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1290 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1291 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1292 + info_ptr->regs_size_1word,
1294 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1296 info_ptr->pretend_size = crtl->args.pretend_args_size;
1298 /* Work out the size of the frame, excluding the header. Both the frame
1299 body and register parameter area will be dword-aligned. */
1300 info_ptr->total_size
1301 = (ADDR_ALIGN (info_ptr->parameter_size
1302 + info_ptr->regs_size
1303 + info_ptr->vars_size,
1305 + ADDR_ALIGN (info_ptr->pretend_size
1306 + info_ptr->stdarg_size,
1307 2 * UNITS_PER_WORD));
1309 /* See if we need to create a frame at all, if so add header area. */
1310 if (info_ptr->total_size > 0
1311 || frame_pointer_needed
1312 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1313 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1315 offset = info_ptr->parameter_size;
1316 info_ptr->header_size = 4 * UNITS_PER_WORD;
1317 info_ptr->total_size += 4 * UNITS_PER_WORD;
1319 /* Calculate the offsets to save normal register pairs. */
1320 for (range = 0; range < STACK_REGS_MAX; range++)
1322 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1323 if (! reg_ptr->special_p)
1325 int first = reg_ptr->first;
1326 int last = reg_ptr->last;
1329 for (regno = first; regno <= last; regno++)
1330 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1331 && regno != FRAME_POINTER_REGNUM
1332 && (regno < FIRST_ARG_REGNUM
1333 || regno > LAST_ARG_REGNUM))
1335 info_ptr->reg_offset[regno] = offset;
1336 offset += 2 * UNITS_PER_WORD;
1341 /* Calculate the offsets to save normal single registers. */
1342 for (range = 0; range < STACK_REGS_MAX; range++)
1344 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1345 if (! reg_ptr->special_p)
1347 int first = reg_ptr->first;
1348 int last = reg_ptr->last;
1351 for (regno = first; regno <= last; regno++)
1352 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1353 && regno != FRAME_POINTER_REGNUM
1354 && (regno < FIRST_ARG_REGNUM
1355 || regno > LAST_ARG_REGNUM))
1357 info_ptr->reg_offset[regno] = offset;
1358 offset += UNITS_PER_WORD;
1363 /* Calculate the offset to save the local variables at. */
1364 offset = ADDR_ALIGN (offset, alignment);
1365 if (info_ptr->vars_size)
1367 info_ptr->vars_offset = offset;
1368 offset += info_ptr->vars_size;
1371 /* Align header to a dword-boundary. */
1372 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1374 /* Calculate the offsets in the fixed frame. */
1375 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1376 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1377 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1379 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1380 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1381 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1383 if (cfun->returns_struct)
1385 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1386 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1387 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1390 /* Calculate the offsets to store the arguments passed in registers
1391 for stdarg functions. The register pairs are first and the single
1392 register if any is last. The register save area starts on a
1394 if (info_ptr->stdarg_size)
1396 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1397 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1400 /* Skip the header. */
1401 offset += 4 * UNITS_PER_WORD;
1402 for (regno = first; regno <= last; regno++)
1404 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1406 info_ptr->reg_offset[regno] = offset;
1407 offset += 2 * UNITS_PER_WORD;
1409 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1411 info_ptr->reg_offset[regno] = offset;
1412 offset += UNITS_PER_WORD;
1418 if (reload_completed)
1419 frv_stack_cache = info_ptr;
1425 /* Print the information about the frv stack offsets, etc. when debugging. */
1428 frv_debug_stack (frv_stack_t *info)
1433 info = frv_stack_info ();
1435 fprintf (stderr, "\nStack information for function %s:\n",
1436 ((current_function_decl && DECL_NAME (current_function_decl))
1437 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1440 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1441 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1442 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1443 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1444 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1446 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1447 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1448 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1449 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1451 for (range = 0; range < STACK_REGS_MAX; range++)
1453 frv_stack_regs_t *regs = &(info->regs[range]);
1454 if ((regs->size_1word + regs->size_2words) > 0)
1456 int first = regs->first;
1457 int last = regs->last;
1460 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1461 regs->name, regs->size_1word + regs->size_2words,
1462 regs->size_1word, regs->size_2words);
1464 for (regno = first; regno <= last; regno++)
1466 if (info->save_p[regno] == REG_SAVE_1WORD)
1467 fprintf (stderr, " %s (%d)", reg_names[regno],
1468 info->reg_offset[regno]);
1470 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1471 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1472 reg_names[regno+1], info->reg_offset[regno]);
1475 fputc ('\n', stderr);
1485 /* Used during final to control the packing of insns. The value is
1486 1 if the current instruction should be packed with the next one,
1487 0 if it shouldn't or -1 if packing is disabled altogether. */
1489 static int frv_insn_packing_flag;
1491 /* True if the current function contains a far jump. */
1494 frv_function_contains_far_jump (void)
1496 rtx insn = get_insns ();
1498 && !(GET_CODE (insn) == JUMP_INSN
1499 /* Ignore tablejump patterns. */
1500 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1501 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1502 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1503 insn = NEXT_INSN (insn);
1504 return (insn != NULL);
1507 /* For the FRV, this function makes sure that a function with far jumps
1508 will return correctly. It also does the VLIW packing. */
1511 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1513 /* If no frame was created, check whether the function uses a call
1514 instruction to implement a far jump. If so, save the link in gr3 and
1515 replace all returns to LR with returns to GR3. GR3 is used because it
1516 is call-clobbered, because is not available to the register allocator,
1517 and because all functions that take a hidden argument pointer will have
1519 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1523 /* Just to check that the above comment is true. */
1524 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1526 /* Generate the instruction that saves the link register. */
1527 fprintf (file, "\tmovsg lr,gr3\n");
1529 /* Replace the LR with GR3 in *return_internal patterns. The insn
1530 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1531 simply emit a different assembly directive because bralr and jmpl
1532 execute in different units. */
1533 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1534 if (GET_CODE (insn) == JUMP_INSN)
1536 rtx pattern = PATTERN (insn);
1537 if (GET_CODE (pattern) == PARALLEL
1538 && XVECLEN (pattern, 0) >= 2
1539 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1540 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1542 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1543 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1544 SET_REGNO (address, GPR_FIRST + 3);
1551 /* Allow the garbage collector to free the nops created by frv_reorg. */
1552 memset (frv_nops, 0, sizeof (frv_nops));
1556 /* Return the next available temporary register in a given class. */
1559 frv_alloc_temp_reg (
1560 frv_tmp_reg_t *info, /* which registers are available */
1561 enum reg_class rclass, /* register class desired */
1562 enum machine_mode mode, /* mode to allocate register with */
1563 int mark_as_used, /* register not available after allocation */
1564 int no_abort) /* return NULL instead of aborting */
1566 int regno = info->next_reg[ (int)rclass ];
1567 int orig_regno = regno;
1568 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1573 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1574 && TEST_HARD_REG_BIT (info->regs, regno))
1577 if (++regno >= FIRST_PSEUDO_REGISTER)
1579 if (regno == orig_regno)
1581 gcc_assert (no_abort);
1586 nr = HARD_REGNO_NREGS (regno, mode);
1587 info->next_reg[ (int)rclass ] = regno + nr;
1590 for (i = 0; i < nr; i++)
1591 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1593 return gen_rtx_REG (mode, regno);
1597 /* Return an rtx with the value OFFSET, which will either be a register or a
1598 signed 12-bit integer. It can be used as the second operand in an "add"
1599 instruction, or as the index in a load or store.
1601 The function returns a constant rtx if OFFSET is small enough, otherwise
1602 it loads the constant into register OFFSET_REGNO and returns that. */
1604 frv_frame_offset_rtx (int offset)
1606 rtx offset_rtx = GEN_INT (offset);
1607 if (IN_RANGE_P (offset, -2048, 2047))
1611 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1612 if (IN_RANGE_P (offset, -32768, 32767))
1613 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1616 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1617 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1623 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1624 prologue and epilogue uses such expressions to access the stack. */
1626 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1628 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1630 frv_frame_offset_rtx (offset)));
1633 /* Generate a frame-related expression:
1635 (set REG (mem (plus (sp) (const_int OFFSET)))).
1637 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1638 instructions. Marking the expressions as frame-related is superfluous if
1639 the note contains just a single set. But if the note contains a PARALLEL
1640 or SEQUENCE that has several sets, each set must be individually marked
1641 as frame-related. */
1643 frv_dwarf_store (rtx reg, int offset)
1645 rtx set = gen_rtx_SET (VOIDmode,
1646 gen_rtx_MEM (GET_MODE (reg),
1647 plus_constant (stack_pointer_rtx,
1650 RTX_FRAME_RELATED_P (set) = 1;
1654 /* Emit a frame-related instruction whose pattern is PATTERN. The
1655 instruction is the last in a sequence that cumulatively performs the
1656 operation described by DWARF_PATTERN. The instruction is marked as
1657 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1660 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1662 rtx insn = emit_insn (pattern);
1663 RTX_FRAME_RELATED_P (insn) = 1;
1664 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1669 /* Emit instructions that transfer REG to or from the memory location (sp +
1670 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1671 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1672 function to store registers and only the epilogue uses it to load them.
1674 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1675 The generated instruction will use BASE as its base register. BASE may
1676 simply be the stack pointer, but if several accesses are being made to a
1677 region far away from the stack pointer, it may be more efficient to set
1678 up a temporary instead.
1680 Store instructions will be frame-related and will be annotated with the
1681 overall effect of the store. Load instructions will be followed by a
1682 (use) to prevent later optimizations from zapping them.
1684 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1685 as a temporary in such cases. */
1687 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1689 enum machine_mode mode = GET_MODE (reg);
1690 rtx mem = frv_frame_mem (mode,
1692 stack_offset - accessor->base_offset);
1694 if (accessor->op == FRV_LOAD)
1696 if (SPR_P (REGNO (reg)))
1698 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1699 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1700 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1704 /* We cannot use reg+reg addressing for DImode access. */
1706 && GET_CODE (XEXP (mem, 0)) == PLUS
1707 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1708 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1710 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1711 rtx insn = emit_move_insn (temp,
1712 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1713 XEXP (XEXP (mem, 0), 1)));
1714 mem = gen_rtx_MEM (DImode, temp);
1716 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1722 if (SPR_P (REGNO (reg)))
1724 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1725 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1726 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1727 frv_dwarf_store (reg, stack_offset));
1729 else if (mode == DImode)
1731 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1732 with a separate save for each register. */
1733 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1734 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1735 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1736 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1738 /* Also we cannot use reg+reg addressing. */
1739 if (GET_CODE (XEXP (mem, 0)) == PLUS
1740 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1741 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1743 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1744 rtx insn = emit_move_insn (temp,
1745 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1746 XEXP (XEXP (mem, 0), 1)));
1747 mem = gen_rtx_MEM (DImode, temp);
1750 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1751 gen_rtx_PARALLEL (VOIDmode,
1752 gen_rtvec (2, set1, set2)));
1755 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1756 frv_dwarf_store (reg, stack_offset));
1760 /* A function that uses frv_frame_access to transfer a group of registers to
1761 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1762 is the stack information generated by frv_stack_info, and REG_SET is the
1763 number of the register set to transfer. */
1765 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1769 frv_stack_regs_t *regs_info;
1772 regs_info = &info->regs[reg_set];
1773 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1774 if (info->save_p[regno])
1775 frv_frame_access (accessor,
1776 info->save_p[regno] == REG_SAVE_2WORDS
1777 ? gen_rtx_REG (DImode, regno)
1778 : gen_rtx_REG (SImode, regno),
1779 info->reg_offset[regno]);
1782 /* Save or restore callee-saved registers that are kept outside the frame
1783 header. The function saves the registers if OP is FRV_STORE and restores
1784 them if OP is FRV_LOAD. INFO is the stack information generated by
1787 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1789 frv_frame_accessor_t accessor;
1792 accessor.base = stack_pointer_rtx;
1793 accessor.base_offset = 0;
1794 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1795 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1796 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1800 /* Called after register allocation to add any instructions needed for the
1801 prologue. Using a prologue insn is favored compared to putting all of the
1802 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1803 it allows the scheduler to intermix instructions with the saves of
1804 the caller saved registers. In some cases, it might be necessary
1805 to emit a barrier instruction as the last insn to prevent such
1808 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1809 so that the debug info generation code can handle them properly. */
1811 frv_expand_prologue (void)
1813 frv_stack_t *info = frv_stack_info ();
1814 rtx sp = stack_pointer_rtx;
1815 rtx fp = frame_pointer_rtx;
1816 frv_frame_accessor_t accessor;
1818 if (TARGET_DEBUG_STACK)
1819 frv_debug_stack (info);
1821 if (info->total_size == 0)
1824 /* We're interested in three areas of the frame here:
1826 A: the register save area
1828 C: the header after B
1830 If the frame pointer isn't used, we'll have to set up A, B and C
1831 using the stack pointer. If the frame pointer is used, we'll access
1835 B: set up using sp or a temporary (see below)
1838 We set up B using the stack pointer if the frame is small enough.
1839 Otherwise, it's more efficient to copy the old stack pointer into a
1840 temporary and use that.
1842 Note that it's important to make sure the prologue and epilogue use the
1843 same registers to access A and C, since doing otherwise will confuse
1844 the aliasing code. */
1846 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1847 isn't used, the same method will serve for C. */
1848 accessor.op = FRV_STORE;
1849 if (frame_pointer_needed && info->total_size > 2048)
1853 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1854 accessor.base_offset = info->total_size;
1855 insn = emit_insn (gen_movsi (accessor.base, sp));
1859 accessor.base = stack_pointer_rtx;
1860 accessor.base_offset = 0;
1863 /* Allocate the stack space. */
1865 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1866 rtx dwarf_offset = GEN_INT (-info->total_size);
1868 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1871 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1874 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1875 and point the new one to that location. */
1876 if (frame_pointer_needed)
1878 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1880 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1881 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1883 rtx asm_src = plus_constant (accessor.base,
1884 fp_offset - accessor.base_offset);
1885 rtx dwarf_src = plus_constant (sp, fp_offset);
1887 /* Store the old frame pointer at (sp + FP_OFFSET). */
1888 frv_frame_access (&accessor, fp, fp_offset);
1890 /* Set up the new frame pointer. */
1891 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1892 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1894 /* Access region C from the frame pointer. */
1896 accessor.base_offset = fp_offset;
1899 /* Set up region C. */
1900 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1901 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1902 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1904 /* Set up region A. */
1905 frv_frame_access_standard_regs (FRV_STORE, info);
1907 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1908 scheduler from moving loads before the stores saving the registers. */
1909 if (info->stdarg_size > 0)
1910 emit_insn (gen_blockage ());
1912 /* Set up pic register/small data register for this function. */
1913 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1914 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1915 gen_rtx_REG (Pmode, LR_REGNO),
1916 gen_rtx_REG (SImode, OFFSET_REGNO)));
1920 /* Under frv, all of the work is done via frv_expand_epilogue, but
1921 this function provides a convenient place to do cleanup. */
1924 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1925 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1927 frv_stack_cache = (frv_stack_t *)0;
1929 /* Zap last used registers for conditional execution. */
1930 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1932 /* Release the bitmap of created insns. */
1933 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1937 /* Called after register allocation to add any instructions needed for the
1938 epilogue. Using an epilogue insn is favored compared to putting all of the
1939 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1940 it allows the scheduler to intermix instructions with the saves of
1941 the caller saved registers. In some cases, it might be necessary
1942 to emit a barrier instruction as the last insn to prevent such
1946 frv_expand_epilogue (bool emit_return)
1948 frv_stack_t *info = frv_stack_info ();
1949 rtx fp = frame_pointer_rtx;
1950 rtx sp = stack_pointer_rtx;
1954 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1956 /* Restore the stack pointer to its original value if alloca or the like
1958 if (! current_function_sp_is_unchanging)
1959 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1961 /* Restore the callee-saved registers that were used in this function. */
1962 frv_frame_access_standard_regs (FRV_LOAD, info);
1964 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1965 no return instruction should be emitted. */
1966 if (info->save_p[LR_REGNO])
1971 /* Use the same method to access the link register's slot as we did in
1972 the prologue. In other words, use the frame pointer if available,
1973 otherwise use the stack pointer.
1975 LR_OFFSET is the offset of the link register's slot from the start
1976 of the frame and MEM is a memory rtx for it. */
1977 lr_offset = info->reg_offset[LR_REGNO];
1978 if (frame_pointer_needed)
1979 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1981 mem = frv_frame_mem (Pmode, sp, lr_offset);
1983 /* Load the old link register into a GPR. */
1984 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1985 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1988 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1990 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1991 the load is preserved. */
1992 if (frame_pointer_needed)
1994 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1998 /* Deallocate the stack frame. */
1999 if (info->total_size != 0)
2001 rtx offset = frv_frame_offset_rtx (info->total_size);
2002 emit_insn (gen_stack_adjust (sp, sp, offset));
2005 /* If this function uses eh_return, add the final stack adjustment now. */
2006 if (crtl->calls_eh_return)
2007 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2010 emit_jump_insn (gen_epilogue_return (return_addr));
2013 rtx lr = return_addr;
2015 if (REGNO (return_addr) != LR_REGNO)
2017 lr = gen_rtx_REG (Pmode, LR_REGNO);
2018 emit_move_insn (lr, return_addr);
2026 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2029 frv_asm_output_mi_thunk (FILE *file,
2030 tree thunk_fndecl ATTRIBUTE_UNUSED,
2031 HOST_WIDE_INT delta,
2032 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2035 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2036 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2037 const char *name_jmp = reg_names[JUMP_REGNO];
2038 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2040 /* Do the add using an addi if possible. */
2041 if (IN_RANGE_P (delta, -2048, 2047))
2042 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2045 const char *const name_add = reg_names[TEMP_REGNO];
2046 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2047 parallel, delta, name_add);
2048 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2050 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2055 const char *name_pic = reg_names[FDPIC_REGNO];
2056 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2060 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2061 assemble_name (file, name_func);
2062 fprintf (file, "),%s\n", name_jmp);
2064 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2065 assemble_name (file, name_func);
2066 fprintf (file, "),%s\n", name_jmp);
2068 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2072 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2073 assemble_name (file, name_func);
2074 fprintf (file, "\t)), %s\n", name_jmp);
2079 fprintf (file, "\tsethi%s #hi(", parallel);
2080 assemble_name (file, name_func);
2081 fprintf (file, "),%s\n", name_jmp);
2083 fprintf (file, "\tsetlo #lo(");
2084 assemble_name (file, name_func);
2085 fprintf (file, "),%s\n", name_jmp);
2089 /* Use JUMP_REGNO as a temporary PIC register. */
2090 const char *name_lr = reg_names[LR_REGNO];
2091 const char *name_gppic = name_jmp;
2092 const char *name_tmp = reg_names[TEMP_REGNO];
2094 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2095 fprintf (file, "\tcall 1f\n");
2096 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2097 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2098 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2099 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2100 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2102 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2103 assemble_name (file, name_func);
2104 fprintf (file, "),%s\n", name_tmp);
2106 fprintf (file, "\tsetlo #gprello(");
2107 assemble_name (file, name_func);
2108 fprintf (file, "),%s\n", name_tmp);
2110 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2113 /* Jump to the function address. */
2114 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2119 /* On frv, create a frame whenever we need to create stack. */
2122 frv_frame_pointer_required (void)
2124 /* If we forgoing the usual linkage requirements, we only need
2125 a frame pointer if the stack pointer might change. */
2126 if (!TARGET_LINKED_FP)
2127 return !current_function_sp_is_unchanging;
2129 if (! current_function_is_leaf)
2132 if (get_frame_size () != 0)
2138 if (!current_function_sp_is_unchanging)
2141 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2147 if (cfun->machine->frame_needed)
2154 /* Worker function for TARGET_CAN_ELIMINATE. */
2157 frv_can_eliminate (const int from, const int to)
2159 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2160 ? ! frame_pointer_needed
2164 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2165 initial difference between the specified pair of registers. This macro must
2166 be defined if `ELIMINABLE_REGS' is defined. */
2168 /* See frv_stack_info for more details on the frv stack frame. */
2171 frv_initial_elimination_offset (int from, int to)
2173 frv_stack_t *info = frv_stack_info ();
2176 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2177 ret = info->total_size - info->pretend_size;
2179 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2180 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2182 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2183 ret = (info->total_size
2184 - info->reg_offset[FRAME_POINTER_REGNUM]
2185 - info->pretend_size);
2190 if (TARGET_DEBUG_STACK)
2191 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2192 reg_names [from], reg_names[to], ret);
2198 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2201 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2202 enum machine_mode mode,
2203 tree type ATTRIBUTE_UNUSED,
2207 if (TARGET_DEBUG_ARG)
2209 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2210 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2214 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2217 frv_expand_builtin_saveregs (void)
2219 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2221 if (TARGET_DEBUG_ARG)
2222 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2225 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2229 /* Expand __builtin_va_start to do the va_start macro. */
2232 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2235 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2237 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2238 GEN_INT (UNITS_PER_WORD * num));
2240 if (TARGET_DEBUG_ARG)
2242 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2243 crtl->args.info, num);
2245 debug_rtx (nextarg);
2248 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2249 fold_convert (TREE_TYPE (valist),
2250 make_tree (sizetype, nextarg)));
2251 TREE_SIDE_EFFECTS (t) = 1;
2253 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2257 /* Expand a block move operation, and return 1 if successful. Return 0
2258 if we should let the compiler generate normal code.
2260 operands[0] is the destination
2261 operands[1] is the source
2262 operands[2] is the length
2263 operands[3] is the alignment */
2265 /* Maximum number of loads to do before doing the stores */
2266 #ifndef MAX_MOVE_REG
2267 #define MAX_MOVE_REG 4
2270 /* Maximum number of total loads to do. */
2271 #ifndef TOTAL_MOVE_REG
2272 #define TOTAL_MOVE_REG 8
2276 frv_expand_block_move (rtx operands[])
2278 rtx orig_dest = operands[0];
2279 rtx orig_src = operands[1];
2280 rtx bytes_rtx = operands[2];
2281 rtx align_rtx = operands[3];
2282 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2295 rtx stores[MAX_MOVE_REG];
2297 enum machine_mode mode;
2299 /* If this is not a fixed size move, just call memcpy. */
2303 /* This should be a fixed size alignment. */
2304 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2306 align = INTVAL (align_rtx);
2308 /* Anything to move? */
2309 bytes = INTVAL (bytes_rtx);
2313 /* Don't support real large moves. */
2314 if (bytes > TOTAL_MOVE_REG*align)
2317 /* Move the address into scratch registers. */
2318 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2319 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2321 num_reg = offset = 0;
2322 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2324 /* Calculate the correct offset for src/dest. */
2328 dest_addr = dest_reg;
2332 src_addr = plus_constant (src_reg, offset);
2333 dest_addr = plus_constant (dest_reg, offset);
2336 /* Generate the appropriate load and store, saving the stores
2338 if (bytes >= 4 && align >= 4)
2340 else if (bytes >= 2 && align >= 2)
2345 move_bytes = GET_MODE_SIZE (mode);
2346 tmp_reg = gen_reg_rtx (mode);
2347 src_mem = change_address (orig_src, mode, src_addr);
2348 dest_mem = change_address (orig_dest, mode, dest_addr);
2349 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2350 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2352 if (num_reg >= MAX_MOVE_REG)
2354 for (i = 0; i < num_reg; i++)
2355 emit_insn (stores[i]);
2360 for (i = 0; i < num_reg; i++)
2361 emit_insn (stores[i]);
2367 /* Expand a block clear operation, and return 1 if successful. Return 0
2368 if we should let the compiler generate normal code.
2370 operands[0] is the destination
2371 operands[1] is the length
2372 operands[3] is the alignment */
2375 frv_expand_block_clear (rtx operands[])
2377 rtx orig_dest = operands[0];
2378 rtx bytes_rtx = operands[1];
2379 rtx align_rtx = operands[3];
2380 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2389 enum machine_mode mode;
2391 /* If this is not a fixed size move, just call memcpy. */
2395 /* This should be a fixed size alignment. */
2396 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2398 align = INTVAL (align_rtx);
2400 /* Anything to move? */
2401 bytes = INTVAL (bytes_rtx);
2405 /* Don't support real large clears. */
2406 if (bytes > TOTAL_MOVE_REG*align)
2409 /* Move the address into a scratch register. */
2410 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2412 num_reg = offset = 0;
2413 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2415 /* Calculate the correct offset for src/dest. */
2416 dest_addr = ((offset == 0)
2418 : plus_constant (dest_reg, offset));
2420 /* Generate the appropriate store of gr0. */
2421 if (bytes >= 4 && align >= 4)
2423 else if (bytes >= 2 && align >= 2)
2428 clear_bytes = GET_MODE_SIZE (mode);
2429 dest_mem = change_address (orig_dest, mode, dest_addr);
2430 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2437 /* The following variable is used to output modifiers of assembler
2438 code of the current output insn. */
2440 static rtx *frv_insn_operands;
2442 /* The following function is used to add assembler insn code suffix .p
2443 if it is necessary. */
2446 frv_asm_output_opcode (FILE *f, const char *ptr)
2450 if (frv_insn_packing_flag <= 0)
2453 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2456 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2457 || (*ptr >= 'A' && *ptr <= 'Z')))
2459 int letter = *ptr++;
2462 frv_print_operand (f, frv_insn_operands [c], letter);
2463 while ((c = *ptr) >= '0' && c <= '9')
2475 /* Set up the packing bit for the current output insn. Note that this
2476 function is not called for asm insns. */
2479 frv_final_prescan_insn (rtx insn, rtx *opvec,
2480 int noperands ATTRIBUTE_UNUSED)
2484 if (frv_insn_packing_flag >= 0)
2486 frv_insn_operands = opvec;
2487 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2489 else if (recog_memoized (insn) >= 0
2490 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2491 /* Packing optimizations have been disabled, but INSN can only
2492 be issued in M1. Insert an mnop in M0. */
2493 fprintf (asm_out_file, "\tmnop.p\n");
2499 /* A C expression whose value is RTL representing the address in a stack frame
2500 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2501 an RTL expression for the address of the stack frame itself.
2503 If you don't define this macro, the default is to return the value of
2504 FRAMEADDR--that is, the stack frame address is also the address of the stack
2505 word that points to the previous frame. */
2507 /* The default is correct, but we need to make sure the frame gets created. */
2509 frv_dynamic_chain_address (rtx frame)
2511 cfun->machine->frame_needed = 1;
2516 /* A C expression whose value is RTL representing the value of the return
2517 address for the frame COUNT steps up from the current frame, after the
2518 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2519 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2522 The value of the expression must always be the correct address when COUNT is
2523 zero, but may be `NULL_RTX' if there is not way to determine the return
2524 address of other frames. */
2527 frv_return_addr_rtx (int count, rtx frame)
2531 cfun->machine->frame_needed = 1;
2532 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2535 /* Given a memory reference MEMREF, interpret the referenced memory as
2536 an array of MODE values, and return a reference to the element
2537 specified by INDEX. Assume that any pre-modification implicit in
2538 MEMREF has already happened.
2540 MEMREF must be a legitimate operand for modes larger than SImode.
2541 frv_legitimate_address_p forbids register+register addresses, which
2542 this function cannot handle. */
2544 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2546 rtx base = XEXP (memref, 0);
2547 if (GET_CODE (base) == PRE_MODIFY)
2548 base = XEXP (base, 0);
2549 return change_address (memref, mode,
2550 plus_constant (base, index * GET_MODE_SIZE (mode)));
2554 /* Print a memory address as an operand to reference that memory location. */
2556 frv_print_operand_address (FILE * stream, rtx x)
2558 if (GET_CODE (x) == MEM)
2561 switch (GET_CODE (x))
2564 fputs (reg_names [ REGNO (x)], stream);
2568 fprintf (stream, "%ld", (long) INTVAL (x));
2572 assemble_name (stream, XSTR (x, 0));
2577 output_addr_const (stream, x);
2581 /* Poorly constructed asm statements can trigger this alternative.
2582 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2583 frv_print_operand_memory_reference (stream, x, 0);
2590 fatal_insn ("bad insn to frv_print_operand_address:", x);
2595 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2597 int regno = true_regnum (x);
2599 fputs (reg_names[regno], stream);
2601 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2604 /* Print a memory reference suitable for the ld/st instructions. */
2607 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2609 struct frv_unspec unspec;
2613 switch (GET_CODE (x))
2620 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2622 x1 = XEXP (XEXP (x, 1), 1);
2632 if (GET_CODE (x0) == CONST_INT)
2640 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2649 else if (GET_CODE (x1) != CONST_INT)
2650 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2653 fputs ("@(", stream);
2655 fputs (reg_names[GPR_R0], stream);
2656 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2657 frv_print_operand_memory_reference_reg (stream, x0);
2659 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2661 fputs (",", stream);
2663 fputs (reg_names [GPR_R0], stream);
2667 switch (GET_CODE (x1))
2671 frv_print_operand_memory_reference_reg (stream, x1);
2675 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2679 if (!frv_const_unspec_p (x1, &unspec))
2680 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2681 frv_output_const_unspec (stream, &unspec);
2685 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2689 fputs (")", stream);
2693 /* Return 2 for likely branches and 0 for non-likely branches */
2695 #define FRV_JUMP_LIKELY 2
2696 #define FRV_JUMP_NOT_LIKELY 0
2699 frv_print_operand_jump_hint (rtx insn)
2704 HOST_WIDE_INT prob = -1;
2705 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2707 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2709 /* Assume any non-conditional jump is likely. */
2710 if (! any_condjump_p (insn))
2711 ret = FRV_JUMP_LIKELY;
2715 labelref = condjump_label (insn);
2718 rtx label = XEXP (labelref, 0);
2719 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2724 note = find_reg_note (insn, REG_BR_PROB, 0);
2726 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2730 prob = INTVAL (XEXP (note, 0));
2731 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2733 : FRV_JUMP_NOT_LIKELY);
2745 case UNKNOWN: direction = "unknown jump direction"; break;
2746 case BACKWARD: direction = "jump backward"; break;
2747 case FORWARD: direction = "jump forward"; break;
2751 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2752 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2753 (long)INSN_UID (insn), direction, (long)prob,
2754 (long)REG_BR_PROB_BASE, ret);
2762 /* Return the comparison operator to use for CODE given that the ICC
2766 comparison_string (enum rtx_code code, rtx op0)
2768 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2771 default: output_operand_lossage ("bad condition code");
2772 case EQ: return "eq";
2773 case NE: return "ne";
2774 case LT: return is_nz_p ? "n" : "lt";
2775 case LE: return "le";
2776 case GT: return "gt";
2777 case GE: return is_nz_p ? "p" : "ge";
2778 case LTU: return is_nz_p ? "no" : "c";
2779 case LEU: return is_nz_p ? "eq" : "ls";
2780 case GTU: return is_nz_p ? "ne" : "hi";
2781 case GEU: return is_nz_p ? "ra" : "nc";
2785 /* Print an operand to an assembler instruction.
2787 `%' followed by a letter and a digit says to output an operand in an
2788 alternate fashion. Four letters have standard, built-in meanings
2789 described below. The hook `TARGET_PRINT_OPERAND' can define
2790 additional letters with nonstandard meanings.
2792 `%cDIGIT' can be used to substitute an operand that is a constant value
2793 without the syntax that normally indicates an immediate operand.
2795 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2798 `%aDIGIT' can be used to substitute an operand as if it were a memory
2799 reference, with the actual operand treated as the address. This may be
2800 useful when outputting a "load address" instruction, because often the
2801 assembler syntax for such an instruction requires you to write the operand
2802 as if it were a memory reference.
2804 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2806 `%=' outputs a number which is unique to each instruction in the entire
2807 compilation. This is useful for making local labels to be referred to more
2808 than once in a single template that generates multiple assembler
2811 `%' followed by a punctuation character specifies a substitution that
2812 does not use an operand. Only one case is standard: `%%' outputs a
2813 `%' into the assembler code. Other nonstandard cases can be defined
2814 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2815 punctuation characters are valid with the
2816 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2819 frv_print_operand (FILE * file, rtx x, int code)
2821 struct frv_unspec unspec;
2822 HOST_WIDE_INT value;
2825 if (code != 0 && !ISALPHA (code))
2828 else if (GET_CODE (x) == CONST_INT)
2831 else if (GET_CODE (x) == CONST_DOUBLE)
2833 if (GET_MODE (x) == SFmode)
2838 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2839 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2843 else if (GET_MODE (x) == VOIDmode)
2844 value = CONST_DOUBLE_LOW (x);
2847 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2858 fputs (reg_names[GPR_R0], file);
2862 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2866 /* Output small data area base register (gr16). */
2867 fputs (reg_names[SDA_BASE_REG], file);
2871 /* Output pic register (gr17). */
2872 fputs (reg_names[PIC_REGNO], file);
2876 /* Output the temporary integer CCR register. */
2877 fputs (reg_names[ICR_TEMP], file);
2881 /* Output the temporary integer CC register. */
2882 fputs (reg_names[ICC_TEMP], file);
2885 /* case 'a': print an address. */
2888 /* Print appropriate test for integer branch false operation. */
2889 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2890 XEXP (x, 0)), file);
2894 /* Print appropriate test for integer branch true operation. */
2895 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2899 /* Print 1 for a NE and 0 for an EQ to give the final argument
2900 for a conditional instruction. */
2901 if (GET_CODE (x) == NE)
2904 else if (GET_CODE (x) == EQ)
2908 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2912 /* Print appropriate test for floating point branch false operation. */
2913 switch (GET_CODE (x))
2916 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2918 case EQ: fputs ("ne", file); break;
2919 case NE: fputs ("eq", file); break;
2920 case LT: fputs ("uge", file); break;
2921 case LE: fputs ("ug", file); break;
2922 case GT: fputs ("ule", file); break;
2923 case GE: fputs ("ul", file); break;
2928 /* Print appropriate test for floating point branch true operation. */
2929 switch (GET_CODE (x))
2932 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2934 case EQ: fputs ("eq", file); break;
2935 case NE: fputs ("ne", file); break;
2936 case LT: fputs ("lt", file); break;
2937 case LE: fputs ("le", file); break;
2938 case GT: fputs ("gt", file); break;
2939 case GE: fputs ("ge", file); break;
2944 /* Print appropriate GOT function. */
2945 if (GET_CODE (x) != CONST_INT)
2946 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2947 fputs (unspec_got_name (INTVAL (x)), file);
2951 /* Print 'i' if the operand is a constant, or is a memory reference that
2953 if (GET_CODE (x) == MEM)
2954 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2955 ? XEXP (XEXP (x, 0), 1)
2957 else if (GET_CODE (x) == PLUS)
2960 switch (GET_CODE (x))
2974 /* For jump instructions, print 'i' if the operand is a constant or
2975 is an expression that adds a constant. */
2976 if (GET_CODE (x) == CONST_INT)
2981 if (GET_CODE (x) == CONST_INT
2982 || (GET_CODE (x) == PLUS
2983 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2984 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2990 /* Print the lower register of a double word register pair */
2991 if (GET_CODE (x) == REG)
2992 fputs (reg_names[ REGNO (x)+1 ], file);
2994 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2997 /* case 'l': print a LABEL_REF. */
3001 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
3002 for the second word of double memory operations. */
3003 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3004 switch (GET_CODE (x))
3007 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3010 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3018 frv_print_operand_memory_reference (file, x, offset);
3024 /* Print the opcode of a command. */
3025 switch (GET_CODE (x))
3028 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3030 case PLUS: fputs ("add", file); break;
3031 case MINUS: fputs ("sub", file); break;
3032 case AND: fputs ("and", file); break;
3033 case IOR: fputs ("or", file); break;
3034 case XOR: fputs ("xor", file); break;
3035 case ASHIFT: fputs ("sll", file); break;
3036 case ASHIFTRT: fputs ("sra", file); break;
3037 case LSHIFTRT: fputs ("srl", file); break;
3041 /* case 'n': negate and print a constant int. */
3044 /* Print PIC label using operand as the number. */
3045 if (GET_CODE (x) != CONST_INT)
3046 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3048 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3052 /* Print 'u' if the operand is a update load/store. */
3053 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3058 /* If value is 0, print gr0, otherwise it must be a register. */
3059 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3060 fputs (reg_names[GPR_R0], file);
3062 else if (GET_CODE (x) == REG)
3063 fputs (reg_names [REGNO (x)], file);
3066 fatal_insn ("bad insn in frv_print_operand, z case", x);
3070 /* Print constant in hex. */
3071 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3073 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3080 if (GET_CODE (x) == REG)
3081 fputs (reg_names [REGNO (x)], file);
3083 else if (GET_CODE (x) == CONST_INT
3084 || GET_CODE (x) == CONST_DOUBLE)
3085 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3087 else if (frv_const_unspec_p (x, &unspec))
3088 frv_output_const_unspec (file, &unspec);
3090 else if (GET_CODE (x) == MEM)
3091 frv_print_operand_address (file, XEXP (x, 0));
3093 else if (CONSTANT_ADDRESS_P (x))
3094 frv_print_operand_address (file, x);
3097 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3102 fatal_insn ("frv_print_operand: unknown code", x);
3110 frv_print_operand_punct_valid_p (unsigned char code)
3112 return (code == '.' || code == '#' || code == '@' || code == '~'
3113 || code == '*' || code == '&');
3117 /* A C statement (sans semicolon) for initializing the variable CUM for the
3118 state at the beginning of the argument list. The variable has type
3119 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3120 of the function which will receive the args, or 0 if the args are to a
3121 compiler support library function. The value of INDIRECT is nonzero when
3122 processing an indirect call, for example a call through a function pointer.
3123 The value of INDIRECT is zero for a call to an explicitly named function, a
3124 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3125 arguments for the function being compiled.
3127 When processing a call to a compiler support library function, LIBNAME
3128 identifies which one. It is a `symbol_ref' rtx which contains the name of
3129 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3130 being processed. Thus, each time this macro is called, either LIBNAME or
3131 FNTYPE is nonzero, but never both of them at once. */
3134 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3140 *cum = FIRST_ARG_REGNUM;
3142 if (TARGET_DEBUG_ARG)
3144 fprintf (stderr, "\ninit_cumulative_args:");
3145 if (!fndecl && fntype)
3146 fputs (" indirect", stderr);
3149 fputs (" incoming", stderr);
3153 tree ret_type = TREE_TYPE (fntype);
3154 fprintf (stderr, " return=%s,",
3155 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3158 if (libname && GET_CODE (libname) == SYMBOL_REF)
3159 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3161 if (cfun->returns_struct)
3162 fprintf (stderr, " return-struct");
3164 putc ('\n', stderr);
3169 /* Return true if we should pass an argument on the stack rather than
3173 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3175 if (mode == BLKmode)
3179 return AGGREGATE_TYPE_P (type);
3182 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3183 argument with the specified mode and type. If it is not defined,
3184 `PARM_BOUNDARY' is used for all arguments. */
3187 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3188 tree type ATTRIBUTE_UNUSED)
3190 return BITS_PER_WORD;
3194 frv_function_arg (CUMULATIVE_ARGS *cum,
3195 enum machine_mode mode,
3196 tree type ATTRIBUTE_UNUSED,
3198 int incoming ATTRIBUTE_UNUSED)
3200 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3205 /* Return a marker for use in the call instruction. */
3206 if (xmode == VOIDmode)
3212 else if (arg_num <= LAST_ARG_REGNUM)
3214 ret = gen_rtx_REG (xmode, arg_num);
3215 debstr = reg_names[arg_num];
3224 if (TARGET_DEBUG_ARG)
3226 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3227 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3233 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3234 advance past an argument in the argument list. The values MODE, TYPE and
3235 NAMED describe that argument. Once this is done, the variable CUM is
3236 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3238 This macro need not do anything if the argument in question was passed on
3239 the stack. The compiler knows how to track the amount of stack space used
3240 for arguments without any special help. */
3243 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3244 enum machine_mode mode,
3245 tree type ATTRIBUTE_UNUSED,
3248 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3249 int bytes = GET_MODE_SIZE (xmode);
3250 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3253 *cum = arg_num + words;
3255 if (TARGET_DEBUG_ARG)
3257 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3258 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3262 /* A C expression for the number of words, at the beginning of an argument,
3263 must be put in registers. The value must be zero for arguments that are
3264 passed entirely in registers or that are entirely pushed on the stack.
3266 On some machines, certain arguments must be passed partially in registers
3267 and partially in memory. On these machines, typically the first N words of
3268 arguments are passed in registers, and the rest on the stack. If a
3269 multi-word argument (a `double' or a structure) crosses that boundary, its
3270 first few words must be passed in registers and the rest must be pushed.
3271 This macro tells the compiler when this occurs, and how many of the words
3272 should go in registers.
3274 `FUNCTION_ARG' for these arguments should return the first register to be
3275 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3276 the called function. */
3279 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3280 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3282 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3283 int bytes = GET_MODE_SIZE (xmode);
3284 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3288 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3289 ? LAST_ARG_REGNUM - arg_num + 1
3291 ret *= UNITS_PER_WORD;
3293 if (TARGET_DEBUG_ARG && ret)
3294 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3300 /* Implements TARGET_FUNCTION_VALUE. */
3303 frv_function_value (const_tree valtype,
3304 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3305 bool outgoing ATTRIBUTE_UNUSED)
3307 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3311 /* Implements TARGET_LIBCALL_VALUE. */
3314 frv_libcall_value (enum machine_mode mode,
3315 const_rtx fun ATTRIBUTE_UNUSED)
3317 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3321 /* Implements FUNCTION_VALUE_REGNO_P. */
3324 frv_function_value_regno_p (const unsigned int regno)
3326 return (regno == RETURN_VALUE_REGNUM);
3329 /* Return true if a register is ok to use as a base or index register. */
3331 static FRV_INLINE int
3332 frv_regno_ok_for_base_p (int regno, int strict_p)
3338 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3340 if (regno == ARG_POINTER_REGNUM)
3343 return (regno >= FIRST_PSEUDO_REGISTER);
3347 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3348 RTX) is a legitimate memory address on the target machine for a memory
3349 operand of mode MODE.
3351 It usually pays to define several simpler macros to serve as subroutines for
3352 this one. Otherwise it may be too complicated to understand.
3354 This macro must exist in two variants: a strict variant and a non-strict
3355 one. The strict variant is used in the reload pass. It must be defined so
3356 that any pseudo-register that has not been allocated a hard register is
3357 considered a memory reference. In contexts where some kind of register is
3358 required, a pseudo-register with no hard register must be rejected.
3360 The non-strict variant is used in other passes. It must be defined to
3361 accept all pseudo-registers in every context where some kind of register is
3364 Compiler source files that want to use the strict variant of this macro
3365 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3366 conditional to define the strict variant in that case and the non-strict
3369 Normally, constant addresses which are the sum of a `symbol_ref' and an
3370 integer are stored inside a `const' RTX to mark them as constant.
3371 Therefore, there is no need to recognize such sums specifically as
3372 legitimate addresses. Normally you would simply recognize any `const' as
3375 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3376 constant sums that are not marked with `const'. It assumes that a
3377 naked `plus' indicates indexing. If so, then you *must* reject such
3378 naked constant sums as illegitimate addresses, so that none of them
3379 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3382 frv_legitimate_address_p_1 (enum machine_mode mode,
3386 int allow_double_reg_p)
3390 HOST_WIDE_INT value;
3393 if (FRV_SYMBOL_REF_TLS_P (x))
3396 switch (GET_CODE (x))
3403 if (GET_CODE (x) != REG)
3409 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3415 if (GET_CODE (x0) != REG
3416 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3417 || GET_CODE (x1) != PLUS
3418 || ! rtx_equal_p (x0, XEXP (x1, 0))
3419 || GET_CODE (XEXP (x1, 1)) != REG
3420 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3427 /* 12-bit immediate */
3432 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3434 /* If we can't use load/store double operations, make sure we can
3435 address the second word. */
3436 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3437 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3446 if (GET_CODE (x0) == SUBREG)
3447 x0 = SUBREG_REG (x0);
3449 if (GET_CODE (x0) != REG)
3452 regno0 = REGNO (x0);
3453 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3456 switch (GET_CODE (x1))
3462 x1 = SUBREG_REG (x1);
3463 if (GET_CODE (x1) != REG)
3469 /* Do not allow reg+reg addressing for modes > 1 word if we
3470 can't depend on having move double instructions. */
3471 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3474 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3478 /* 12-bit immediate */
3483 value = INTVAL (x1);
3484 ret = IN_RANGE_P (value, -2048, 2047);
3486 /* If we can't use load/store double operations, make sure we can
3487 address the second word. */
3488 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3489 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3494 if (!condexec_p && got12_operand (x1, VOIDmode))
3502 if (TARGET_DEBUG_ADDR)
3504 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3505 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3506 (condexec_p) ? ", inside conditional code" : "");
3514 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3516 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3519 /* Given an ADDR, generate code to inline the PLT. */
3521 gen_inlined_tls_plt (rtx addr)
3524 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3527 dest = gen_reg_rtx (DImode);
3534 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3535 calll #gettlsoff(ADDR)@(gr8, gr0)
3537 emit_insn (gen_tls_lddi (dest, addr, picreg));
3544 sethi.p #gottlsdeschi(ADDR), gr8
3545 setlo #gottlsdesclo(ADDR), gr8
3546 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3547 calll #gettlsoff(ADDR)@(gr8, gr0)
3549 rtx reguse = gen_reg_rtx (Pmode);
3550 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3551 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3554 retval = gen_reg_rtx (Pmode);
3555 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3559 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3560 the destination address. */
3562 gen_tlsmoff (rtx addr, rtx reg)
3564 rtx dest = gen_reg_rtx (Pmode);
3568 /* sethi.p #tlsmoffhi(x), grA
3569 setlo #tlsmofflo(x), grA
3571 dest = gen_reg_rtx (Pmode);
3572 emit_insn (gen_tlsoff_hilo (dest, addr,
3573 GEN_INT (R_FRV_TLSMOFFHI)));
3574 dest = gen_rtx_PLUS (Pmode, dest, reg);
3578 /* addi grB, #tlsmoff12(x), grC
3580 ld/st @(grB, #tlsmoff12(x)), grC
3582 dest = gen_reg_rtx (Pmode);
3583 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3584 GEN_INT (R_FRV_TLSMOFF12)));
3589 /* Generate code for a TLS address. */
3591 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3593 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3594 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3598 case TLS_MODEL_INITIAL_EXEC:
3602 ldi @(gr15, #gottlsoff12(x)), gr5
3604 dest = gen_reg_rtx (Pmode);
3605 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3606 dest = gen_rtx_PLUS (Pmode, tp, dest);
3610 /* -fPIC or anything else.
3612 sethi.p #gottlsoffhi(x), gr14
3613 setlo #gottlsofflo(x), gr14
3614 ld #tlsoff(x)@(gr15, gr14), gr9
3616 rtx tmp = gen_reg_rtx (Pmode);
3617 dest = gen_reg_rtx (Pmode);
3618 emit_insn (gen_tlsoff_hilo (tmp, addr,
3619 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3621 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3622 dest = gen_rtx_PLUS (Pmode, tp, dest);
3625 case TLS_MODEL_LOCAL_DYNAMIC:
3629 if (TARGET_INLINE_PLT)
3630 retval = gen_inlined_tls_plt (GEN_INT (0));
3633 /* call #gettlsoff(0) */
3634 retval = gen_reg_rtx (Pmode);
3635 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3638 reg = gen_reg_rtx (Pmode);
3639 emit_insn (gen_rtx_SET (VOIDmode, reg,
3640 gen_rtx_PLUS (Pmode,
3643 dest = gen_tlsmoff (addr, reg);
3646 dest = gen_reg_rtx (Pmode);
3647 emit_insn (gen_tlsoff_hilo (dest, addr,
3648 GEN_INT (R_FRV_TLSMOFFHI)));
3649 dest = gen_rtx_PLUS (Pmode, dest, reg);
3653 case TLS_MODEL_LOCAL_EXEC:
3654 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3656 case TLS_MODEL_GLOBAL_DYNAMIC:
3660 if (TARGET_INLINE_PLT)
3661 retval = gen_inlined_tls_plt (addr);
3664 /* call #gettlsoff(x) */
3665 retval = gen_reg_rtx (Pmode);
3666 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3668 dest = gen_rtx_PLUS (Pmode, retval, tp);
3679 frv_legitimize_address (rtx x,
3680 rtx oldx ATTRIBUTE_UNUSED,
3681 enum machine_mode mode ATTRIBUTE_UNUSED)
3683 if (GET_CODE (x) == SYMBOL_REF)
3685 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3687 return frv_legitimize_tls_address (x, model);
3693 /* Test whether a local function descriptor is canonical, i.e.,
3694 whether we can use FUNCDESC_GOTOFF to compute the address of the
3698 frv_local_funcdesc_p (rtx fnx)
3701 enum symbol_visibility vis;
3704 if (! SYMBOL_REF_LOCAL_P (fnx))
3707 fn = SYMBOL_REF_DECL (fnx);
3712 vis = DECL_VISIBILITY (fn);
3714 if (vis == VISIBILITY_PROTECTED)
3715 /* Private function descriptors for protected functions are not
3716 canonical. Temporarily change the visibility to global. */
3717 vis = VISIBILITY_DEFAULT;
3718 else if (flag_shlib)
3719 /* If we're already compiling for a shared library (that, unlike
3720 executables, can't assume that the existence of a definition
3721 implies local binding), we can skip the re-testing. */
3724 ret = default_binds_local_p_1 (fn, flag_pic);
3726 DECL_VISIBILITY (fn) = vis;
3731 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3735 frv_gen_GPsym2reg (rtx dest, rtx src)
3737 tree gp = get_identifier ("_gp");
3738 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3740 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3744 unspec_got_name (int i)
3748 case R_FRV_GOT12: return "got12";
3749 case R_FRV_GOTHI: return "gothi";
3750 case R_FRV_GOTLO: return "gotlo";
3751 case R_FRV_FUNCDESC: return "funcdesc";
3752 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3753 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3754 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3755 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3756 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3757 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3758 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3759 case R_FRV_GOTOFF12: return "gotoff12";
3760 case R_FRV_GOTOFFHI: return "gotoffhi";
3761 case R_FRV_GOTOFFLO: return "gotofflo";
3762 case R_FRV_GPREL12: return "gprel12";
3763 case R_FRV_GPRELHI: return "gprelhi";
3764 case R_FRV_GPRELLO: return "gprello";
3765 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3766 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3767 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3768 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3769 case R_FRV_TLSMOFF12: return "tlsmoff12";
3770 case R_FRV_TLSDESCHI: return "tlsdeschi";
3771 case R_FRV_TLSDESCLO: return "tlsdesclo";
3772 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3773 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3774 default: gcc_unreachable ();
3778 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3779 is added inside the relocation operator. */
3782 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3784 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3785 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3786 fputs (")", stream);
3789 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3790 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3791 otherwise return ORIG_X. */
3794 frv_find_base_term (rtx x)
3796 struct frv_unspec unspec;
3798 if (frv_const_unspec_p (x, &unspec)
3799 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3800 return plus_constant (unspec.symbol, unspec.offset);
3805 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3806 the operand is used by a predicated instruction. */
3809 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3811 return ((GET_MODE (op) == mode || mode == VOIDmode)
3812 && GET_CODE (op) == MEM
3813 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3814 reload_completed, condexec_p, FALSE));
3818 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3820 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3821 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3827 rvrtx = operands[0];
3831 addr = XEXP (operands[0], 0);
3833 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3834 any calls that would involve a PLT, but can't tell, since we
3835 don't know whether an extern function is going to be provided by
3836 a separate translation unit or imported from a separate module.
3837 When compiling for shared libraries, if the function has default
3838 visibility, we assume it's overridable, so we inline the PLT, but
3839 for executables, we don't really have a way to make a good
3840 decision: a function is as likely to be imported from a shared
3841 library as it is to be defined in the executable itself. We
3842 assume executables will get global functions defined locally,
3843 whereas shared libraries will have them potentially overridden,
3844 so we only inline PLTs when compiling for shared libraries.
3846 In order to mark a function as local to a shared library, any
3847 non-default visibility attribute suffices. Unfortunately,
3848 there's no simple way to tag a function declaration as ``in a
3849 different module'', which we could then use to trigger PLT
3850 inlining on executables. There's -minline-plt, but it affects
3851 all external functions, so one would have to also mark function
3852 declarations available in the same module with non-default
3853 visibility, which is advantageous in itself. */
3854 if (GET_CODE (addr) == SYMBOL_REF
3855 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3859 dest = gen_reg_rtx (SImode);
3861 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3862 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3864 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3865 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3867 crtl->uses_pic_offset_table = TRUE;
3870 else if (GET_CODE (addr) == SYMBOL_REF)
3872 /* These are always either local, or handled through a local
3875 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3876 operands[2], picreg, lr);
3878 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3882 else if (! ldd_address_operand (addr, Pmode))
3883 addr = force_reg (Pmode, addr);
3885 picreg = gen_reg_rtx (DImode);
3886 emit_insn (gen_movdi_ldd (picreg, addr));
3888 if (sibcall && ret_value)
3889 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3891 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3893 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3895 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3899 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3900 process these separately from any offsets, such that we add any
3901 offsets to the function descriptor (the actual pointer), not to the
3902 function address. */
3905 frv_function_symbol_referenced_p (rtx x)
3911 if (GET_CODE (x) == SYMBOL_REF)
3912 return SYMBOL_REF_FUNCTION_P (x);
3914 length = GET_RTX_LENGTH (GET_CODE (x));
3915 format = GET_RTX_FORMAT (GET_CODE (x));
3917 for (j = 0; j < length; ++j)
3922 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3928 if (XVEC (x, j) != 0)
3931 for (k = 0; k < XVECLEN (x, j); ++k)
3932 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3938 /* Nothing to do. */
3946 /* Return true if the memory operand is one that can be conditionally
3950 condexec_memory_operand (rtx op, enum machine_mode mode)
3952 enum machine_mode op_mode = GET_MODE (op);
3955 if (mode != VOIDmode && op_mode != mode)
3970 if (GET_CODE (op) != MEM)
3973 addr = XEXP (op, 0);
3974 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3977 /* Return true if the bare return instruction can be used outside of the
3978 epilog code. For frv, we only do it if there was no stack allocation. */
3981 direct_return_p (void)
3985 if (!reload_completed)
3988 info = frv_stack_info ();
3989 return (info->total_size == 0);
3994 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3996 if (GET_CODE (src) == SYMBOL_REF)
3998 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
4000 src = frv_legitimize_tls_address (src, model);
4006 if (frv_emit_movsi (dest, src))
4015 if (!reload_in_progress
4016 && !reload_completed
4017 && !register_operand (dest, mode)
4018 && !reg_or_0_operand (src, mode))
4019 src = copy_to_mode_reg (mode, src);
4026 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4029 /* Emit code to handle a MOVSI, adding in the small data register or pic
4030 register if needed to load up addresses. Return TRUE if the appropriate
4031 instructions are emitted. */
4034 frv_emit_movsi (rtx dest, rtx src)
4036 int base_regno = -1;
4039 struct frv_unspec old_unspec;
4041 if (!reload_in_progress
4042 && !reload_completed
4043 && !register_operand (dest, SImode)
4044 && (!reg_or_0_operand (src, SImode)
4045 /* Virtual registers will almost always be replaced by an
4046 add instruction, so expose this to CSE by copying to
4047 an intermediate register. */
4048 || (GET_CODE (src) == REG
4049 && IN_RANGE_P (REGNO (src),
4050 FIRST_VIRTUAL_REGISTER,
4051 LAST_VIRTUAL_POINTER_REGISTER))))
4053 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4057 /* Explicitly add in the PIC or small data register if needed. */
4058 switch (GET_CODE (src))
4067 /* Using GPREL12, we use a single GOT entry for all symbols
4068 in read-only sections, but trade sequences such as:
4070 sethi #gothi(label), gr#
4071 setlo #gotlo(label), gr#
4076 ld @(gr15,#got12(_gp)), gr#
4077 sethi #gprelhi(label), gr##
4078 setlo #gprello(label), gr##
4081 We may often be able to share gr# for multiple
4082 computations of GPREL addresses, and we may often fold
4083 the final add into the pair of registers of a load or
4084 store instruction, so it's often profitable. Even when
4085 optimizing for size, we're trading a GOT entry for an
4086 additional instruction, which trades GOT space
4087 (read-write) for code size (read-only, shareable), as
4088 long as the symbol is not used in more than two different
4091 With -fpie/-fpic, we'd be trading a single load for a
4092 sequence of 4 instructions, because the offset of the
4093 label can't be assumed to be addressable with 12 bits, so
4094 we don't do this. */
4095 if (TARGET_GPREL_RO)
4096 unspec = R_FRV_GPREL12;
4098 unspec = R_FRV_GOT12;
4101 base_regno = PIC_REGNO;
4106 if (frv_const_unspec_p (src, &old_unspec))
4109 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4112 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4113 emit_move_insn (dest, src);
4118 sym = XEXP (sym, 0);
4119 if (GET_CODE (sym) == PLUS
4120 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4121 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4122 sym = XEXP (sym, 0);
4123 if (GET_CODE (sym) == SYMBOL_REF)
4125 else if (GET_CODE (sym) == LABEL_REF)
4128 goto handle_whatever;
4136 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4140 src = frv_legitimize_tls_address (src, model);
4141 emit_move_insn (dest, src);
4145 if (SYMBOL_REF_FUNCTION_P (sym))
4147 if (frv_local_funcdesc_p (sym))
4148 unspec = R_FRV_FUNCDESC_GOTOFF12;
4150 unspec = R_FRV_FUNCDESC_GOT12;
4154 if (CONSTANT_POOL_ADDRESS_P (sym))
4155 switch (GET_CODE (get_pool_constant (sym)))
4162 unspec = R_FRV_GOTOFF12;
4167 if (TARGET_GPREL_RO)
4168 unspec = R_FRV_GPREL12;
4170 unspec = R_FRV_GOT12;
4173 else if (SYMBOL_REF_LOCAL_P (sym)
4174 && !SYMBOL_REF_EXTERNAL_P (sym)
4175 && SYMBOL_REF_DECL (sym)
4176 && (!DECL_P (SYMBOL_REF_DECL (sym))
4177 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4179 tree decl = SYMBOL_REF_DECL (sym);
4180 tree init = TREE_CODE (decl) == VAR_DECL
4181 ? DECL_INITIAL (decl)
4182 : TREE_CODE (decl) == CONSTRUCTOR
4185 bool named_section, readonly;
4187 if (init && init != error_mark_node)
4188 reloc = compute_reloc_for_constant (init);
4190 named_section = TREE_CODE (decl) == VAR_DECL
4191 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4192 readonly = decl_readonly_section (decl, reloc);
4195 unspec = R_FRV_GOT12;
4197 unspec = R_FRV_GOTOFF12;
4198 else if (readonly && TARGET_GPREL_RO)
4199 unspec = R_FRV_GPREL12;
4201 unspec = R_FRV_GOT12;
4204 unspec = R_FRV_GOT12;
4208 else if (SYMBOL_REF_SMALL_P (sym))
4209 base_regno = SDA_BASE_REG;
4212 base_regno = PIC_REGNO;
4217 if (base_regno >= 0)
4219 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4220 emit_insn (gen_symGOTOFF2reg (dest, src,
4221 gen_rtx_REG (Pmode, base_regno),
4222 GEN_INT (R_FRV_GPREL12)));
4224 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4225 gen_rtx_REG (Pmode, base_regno),
4226 GEN_INT (R_FRV_GPREL12)));
4227 if (base_regno == PIC_REGNO)
4228 crtl->uses_pic_offset_table = TRUE;
4236 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4237 new uses of it once reload has begun. */
4238 gcc_assert (!reload_in_progress && !reload_completed);
4242 case R_FRV_GOTOFF12:
4243 if (!frv_small_data_reloc_p (sym, unspec))
4244 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4247 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4250 if (!frv_small_data_reloc_p (sym, unspec))
4251 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4254 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4256 case R_FRV_FUNCDESC_GOTOFF12:
4258 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4261 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4265 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4268 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4272 crtl->uses_pic_offset_table = TRUE;
4281 /* Return a string to output a single word move. */
4284 output_move_single (rtx operands[], rtx insn)
4286 rtx dest = operands[0];
4287 rtx src = operands[1];
4289 if (GET_CODE (dest) == REG)
4291 int dest_regno = REGNO (dest);
4292 enum machine_mode mode = GET_MODE (dest);
4294 if (GPR_P (dest_regno))
4296 if (GET_CODE (src) == REG)
4298 /* gpr <- some sort of register */
4299 int src_regno = REGNO (src);
4301 if (GPR_P (src_regno))
4302 return "mov %1, %0";
4304 else if (FPR_P (src_regno))
4305 return "movfg %1, %0";
4307 else if (SPR_P (src_regno))
4308 return "movsg %1, %0";
4311 else if (GET_CODE (src) == MEM)
4320 return "ldsb%I1%U1 %M1,%0";
4323 return "ldsh%I1%U1 %M1,%0";
4327 return "ld%I1%U1 %M1, %0";
4331 else if (GET_CODE (src) == CONST_INT
4332 || GET_CODE (src) == CONST_DOUBLE)
4334 /* gpr <- integer/floating constant */
4335 HOST_WIDE_INT value;
4337 if (GET_CODE (src) == CONST_INT)
4338 value = INTVAL (src);
4340 else if (mode == SFmode)
4345 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4346 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4351 value = CONST_DOUBLE_LOW (src);
4353 if (IN_RANGE_P (value, -32768, 32767))
4354 return "setlos %1, %0";
4359 else if (GET_CODE (src) == SYMBOL_REF
4360 || GET_CODE (src) == LABEL_REF
4361 || GET_CODE (src) == CONST)
4367 else if (FPR_P (dest_regno))
4369 if (GET_CODE (src) == REG)
4371 /* fpr <- some sort of register */
4372 int src_regno = REGNO (src);
4374 if (GPR_P (src_regno))
4375 return "movgf %1, %0";
4377 else if (FPR_P (src_regno))
4379 if (TARGET_HARD_FLOAT)
4380 return "fmovs %1, %0";
4382 return "mor %1, %1, %0";
4386 else if (GET_CODE (src) == MEM)
4395 return "ldbf%I1%U1 %M1,%0";
4398 return "ldhf%I1%U1 %M1,%0";
4402 return "ldf%I1%U1 %M1, %0";
4406 else if (ZERO_P (src))
4407 return "movgf %., %0";
4410 else if (SPR_P (dest_regno))
4412 if (GET_CODE (src) == REG)
4414 /* spr <- some sort of register */
4415 int src_regno = REGNO (src);
4417 if (GPR_P (src_regno))
4418 return "movgs %1, %0";
4420 else if (ZERO_P (src))
4421 return "movgs %., %0";
4425 else if (GET_CODE (dest) == MEM)
4427 if (GET_CODE (src) == REG)
4429 int src_regno = REGNO (src);
4430 enum machine_mode mode = GET_MODE (dest);
4432 if (GPR_P (src_regno))
4440 return "stb%I0%U0 %1, %M0";
4443 return "sth%I0%U0 %1, %M0";
4447 return "st%I0%U0 %1, %M0";
4451 else if (FPR_P (src_regno))
4459 return "stbf%I0%U0 %1, %M0";
4462 return "sthf%I0%U0 %1, %M0";
4466 return "stf%I0%U0 %1, %M0";
4471 else if (ZERO_P (src))
4473 switch (GET_MODE (dest))
4479 return "stb%I0%U0 %., %M0";
4482 return "sth%I0%U0 %., %M0";
4486 return "st%I0%U0 %., %M0";
4491 fatal_insn ("bad output_move_single operand", insn);
4496 /* Return a string to output a double word move. */
4499 output_move_double (rtx operands[], rtx insn)
4501 rtx dest = operands[0];
4502 rtx src = operands[1];
4503 enum machine_mode mode = GET_MODE (dest);
4505 if (GET_CODE (dest) == REG)
4507 int dest_regno = REGNO (dest);
4509 if (GPR_P (dest_regno))
4511 if (GET_CODE (src) == REG)
4513 /* gpr <- some sort of register */
4514 int src_regno = REGNO (src);
4516 if (GPR_P (src_regno))
4519 else if (FPR_P (src_regno))
4521 if (((dest_regno - GPR_FIRST) & 1) == 0
4522 && ((src_regno - FPR_FIRST) & 1) == 0)
4523 return "movfgd %1, %0";
4529 else if (GET_CODE (src) == MEM)
4532 if (dbl_memory_one_insn_operand (src, mode))
4533 return "ldd%I1%U1 %M1, %0";
4538 else if (GET_CODE (src) == CONST_INT
4539 || GET_CODE (src) == CONST_DOUBLE)
4543 else if (FPR_P (dest_regno))
4545 if (GET_CODE (src) == REG)
4547 /* fpr <- some sort of register */
4548 int src_regno = REGNO (src);
4550 if (GPR_P (src_regno))
4552 if (((dest_regno - FPR_FIRST) & 1) == 0
4553 && ((src_regno - GPR_FIRST) & 1) == 0)
4554 return "movgfd %1, %0";
4559 else if (FPR_P (src_regno))
4562 && ((dest_regno - FPR_FIRST) & 1) == 0
4563 && ((src_regno - FPR_FIRST) & 1) == 0)
4564 return "fmovd %1, %0";
4570 else if (GET_CODE (src) == MEM)
4573 if (dbl_memory_one_insn_operand (src, mode))
4574 return "lddf%I1%U1 %M1, %0";
4579 else if (ZERO_P (src))
4584 else if (GET_CODE (dest) == MEM)
4586 if (GET_CODE (src) == REG)
4588 int src_regno = REGNO (src);
4590 if (GPR_P (src_regno))
4592 if (((src_regno - GPR_FIRST) & 1) == 0
4593 && dbl_memory_one_insn_operand (dest, mode))
4594 return "std%I0%U0 %1, %M0";
4599 if (FPR_P (src_regno))
4601 if (((src_regno - FPR_FIRST) & 1) == 0
4602 && dbl_memory_one_insn_operand (dest, mode))
4603 return "stdf%I0%U0 %1, %M0";
4609 else if (ZERO_P (src))
4611 if (dbl_memory_one_insn_operand (dest, mode))
4612 return "std%I0%U0 %., %M0";
4618 fatal_insn ("bad output_move_double operand", insn);
4623 /* Return a string to output a single word conditional move.
4624 Operand0 -- EQ/NE of ccr register and 0
4625 Operand1 -- CCR register
4626 Operand2 -- destination
4627 Operand3 -- source */
4630 output_condmove_single (rtx operands[], rtx insn)
4632 rtx dest = operands[2];
4633 rtx src = operands[3];
4635 if (GET_CODE (dest) == REG)
4637 int dest_regno = REGNO (dest);
4638 enum machine_mode mode = GET_MODE (dest);
4640 if (GPR_P (dest_regno))
4642 if (GET_CODE (src) == REG)
4644 /* gpr <- some sort of register */
4645 int src_regno = REGNO (src);
4647 if (GPR_P (src_regno))
4648 return "cmov %z3, %2, %1, %e0";
4650 else if (FPR_P (src_regno))
4651 return "cmovfg %3, %2, %1, %e0";
4654 else if (GET_CODE (src) == MEM)
4663 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4666 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4670 return "cld%I3%U3 %M3, %2, %1, %e0";
4674 else if (ZERO_P (src))
4675 return "cmov %., %2, %1, %e0";
4678 else if (FPR_P (dest_regno))
4680 if (GET_CODE (src) == REG)
4682 /* fpr <- some sort of register */
4683 int src_regno = REGNO (src);
4685 if (GPR_P (src_regno))
4686 return "cmovgf %3, %2, %1, %e0";
4688 else if (FPR_P (src_regno))
4690 if (TARGET_HARD_FLOAT)
4691 return "cfmovs %3,%2,%1,%e0";
4693 return "cmor %3, %3, %2, %1, %e0";
4697 else if (GET_CODE (src) == MEM)
4700 if (mode == SImode || mode == SFmode)
4701 return "cldf%I3%U3 %M3, %2, %1, %e0";
4704 else if (ZERO_P (src))
4705 return "cmovgf %., %2, %1, %e0";
4709 else if (GET_CODE (dest) == MEM)
4711 if (GET_CODE (src) == REG)
4713 int src_regno = REGNO (src);
4714 enum machine_mode mode = GET_MODE (dest);
4716 if (GPR_P (src_regno))
4724 return "cstb%I2%U2 %3, %M2, %1, %e0";
4727 return "csth%I2%U2 %3, %M2, %1, %e0";
4731 return "cst%I2%U2 %3, %M2, %1, %e0";
4735 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4736 return "cstf%I2%U2 %3, %M2, %1, %e0";
4739 else if (ZERO_P (src))
4741 enum machine_mode mode = GET_MODE (dest);
4748 return "cstb%I2%U2 %., %M2, %1, %e0";
4751 return "csth%I2%U2 %., %M2, %1, %e0";
4755 return "cst%I2%U2 %., %M2, %1, %e0";
4760 fatal_insn ("bad output_condmove_single operand", insn);
4765 /* Emit the appropriate code to do a comparison, returning the register the
4766 comparison was done it. */
4769 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4771 enum machine_mode cc_mode;
4774 /* Floating point doesn't have comparison against a constant. */
4775 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4776 op1 = force_reg (GET_MODE (op0), op1);
4778 /* Possibly disable using anything but a fixed register in order to work
4779 around cse moving comparisons past function calls. */
4780 cc_mode = SELECT_CC_MODE (test, op0, op1);
4781 cc_reg = ((TARGET_ALLOC_CC)
4782 ? gen_reg_rtx (cc_mode)
4783 : gen_rtx_REG (cc_mode,
4784 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4786 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4787 gen_rtx_COMPARE (cc_mode, op0, op1)));
4793 /* Emit code for a conditional branch.
4794 XXX: I originally wanted to add a clobber of a CCR register to use in
4795 conditional execution, but that confuses the rest of the compiler. */
4798 frv_emit_cond_branch (rtx operands[])
4803 enum rtx_code test = GET_CODE (operands[0]);
4804 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4805 enum machine_mode cc_mode = GET_MODE (cc_reg);
4807 /* Branches generate:
4809 (if_then_else (<test>, <cc_reg>, (const_int 0))
4810 (label_ref <branch_label>)
4812 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4813 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4814 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4815 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4820 /* Emit code to set a gpr to 1/0 based on a comparison. */
4823 frv_emit_scc (rtx operands[])
4829 enum rtx_code test = GET_CODE (operands[1]);
4830 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4832 /* SCC instructions generate:
4833 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4834 (clobber (<ccr_reg>))]) */
4835 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4836 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4838 cr_reg = ((TARGET_ALLOC_CC)
4839 ? gen_reg_rtx (CC_CCRmode)
4840 : gen_rtx_REG (CC_CCRmode,
4841 ((GET_MODE (cc_reg) == CC_FPmode)
4845 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4846 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4851 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4852 the separate insns. */
4855 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4861 /* Set the appropriate CCR bit. */
4862 emit_insn (gen_rtx_SET (VOIDmode,
4864 gen_rtx_fmt_ee (GET_CODE (test),
4869 /* Move the value into the destination. */
4870 emit_move_insn (dest, GEN_INT (value));
4872 /* Move 0 into the destination if the test failed */
4873 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4874 gen_rtx_EQ (GET_MODE (cr_reg),
4877 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4879 /* Finish up, return sequence. */
4886 /* Emit the code for a conditional move, return TRUE if we could do the
4890 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4897 enum rtx_code test = GET_CODE (test_rtx);
4898 rtx cc_reg = frv_emit_comparison (test,
4899 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4900 enum machine_mode cc_mode = GET_MODE (cc_reg);
4902 /* Conditional move instructions generate:
4903 (parallel [(set <target>
4904 (if_then_else (<test> <cc_reg> (const_int 0))
4907 (clobber (<ccr_reg>))]) */
4909 /* Handle various cases of conditional move involving two constants. */
4910 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4912 HOST_WIDE_INT value1 = INTVAL (src1);
4913 HOST_WIDE_INT value2 = INTVAL (src2);
4915 /* Having 0 as one of the constants can be done by loading the other
4916 constant, and optionally moving in gr0. */
4917 if (value1 == 0 || value2 == 0)
4920 /* If the first value is within an addi range and also the difference
4921 between the two fits in an addi's range, load up the difference, then
4922 conditionally move in 0, and then unconditionally add the first
4924 else if (IN_RANGE_P (value1, -2048, 2047)
4925 && IN_RANGE_P (value2 - value1, -2048, 2047))
4928 /* If neither condition holds, just force the constant into a
4932 src1 = force_reg (GET_MODE (dest), src1);
4933 src2 = force_reg (GET_MODE (dest), src2);
4937 /* If one value is a register, insure the other value is either 0 or a
4941 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4942 src1 = force_reg (GET_MODE (dest), src1);
4944 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4945 src2 = force_reg (GET_MODE (dest), src2);
4948 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4949 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4951 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4953 cr_reg = ((TARGET_ALLOC_CC)
4954 ? gen_reg_rtx (CC_CCRmode)
4955 : gen_rtx_REG (CC_CCRmode,
4956 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4958 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4959 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4964 /* Split a conditional move into constituent parts, returning a SEQUENCE
4965 containing all of the insns. */
4968 frv_split_cond_move (rtx operands[])
4970 rtx dest = operands[0];
4971 rtx test = operands[1];
4972 rtx cc_reg = operands[2];
4973 rtx src1 = operands[3];
4974 rtx src2 = operands[4];
4975 rtx cr_reg = operands[5];
4977 enum machine_mode cr_mode = GET_MODE (cr_reg);
4981 /* Set the appropriate CCR bit. */
4982 emit_insn (gen_rtx_SET (VOIDmode,
4984 gen_rtx_fmt_ee (GET_CODE (test),
4989 /* Handle various cases of conditional move involving two constants. */
4990 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4992 HOST_WIDE_INT value1 = INTVAL (src1);
4993 HOST_WIDE_INT value2 = INTVAL (src2);
4995 /* Having 0 as one of the constants can be done by loading the other
4996 constant, and optionally moving in gr0. */
4999 emit_move_insn (dest, src2);
5000 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5001 gen_rtx_NE (cr_mode, cr_reg,
5003 gen_rtx_SET (VOIDmode, dest, src1)));
5006 else if (value2 == 0)
5008 emit_move_insn (dest, src1);
5009 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5010 gen_rtx_EQ (cr_mode, cr_reg,
5012 gen_rtx_SET (VOIDmode, dest, src2)));
5015 /* If the first value is within an addi range and also the difference
5016 between the two fits in an addi's range, load up the difference, then
5017 conditionally move in 0, and then unconditionally add the first
5019 else if (IN_RANGE_P (value1, -2048, 2047)
5020 && IN_RANGE_P (value2 - value1, -2048, 2047))
5022 rtx dest_si = ((GET_MODE (dest) == SImode)
5024 : gen_rtx_SUBREG (SImode, dest, 0));
5026 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5027 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5028 gen_rtx_NE (cr_mode, cr_reg,
5030 gen_rtx_SET (VOIDmode, dest_si,
5032 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5040 /* Emit the conditional move for the test being true if needed. */
5041 if (! rtx_equal_p (dest, src1))
5042 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5043 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5044 gen_rtx_SET (VOIDmode, dest, src1)));
5046 /* Emit the conditional move for the test being false if needed. */
5047 if (! rtx_equal_p (dest, src2))
5048 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5049 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5050 gen_rtx_SET (VOIDmode, dest, src2)));
5053 /* Finish up, return sequence. */
5060 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5061 memory location that is not known to be dword-aligned. */
5063 frv_split_double_load (rtx dest, rtx source)
5065 int regno = REGNO (dest);
5066 rtx dest1 = gen_highpart (SImode, dest);
5067 rtx dest2 = gen_lowpart (SImode, dest);
5068 rtx address = XEXP (source, 0);
5070 /* If the address is pre-modified, load the lower-numbered register
5071 first, then load the other register using an integer offset from
5072 the modified base register. This order should always be safe,
5073 since the pre-modification cannot affect the same registers as the
5076 The situation for other loads is more complicated. Loading one
5077 of the registers could affect the value of ADDRESS, so we must
5078 be careful which order we do them in. */
5079 if (GET_CODE (address) == PRE_MODIFY
5080 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5082 /* It is safe to load the lower-numbered register first. */
5083 emit_move_insn (dest1, change_address (source, SImode, NULL));
5084 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5088 /* ADDRESS is not pre-modified and the address depends on the
5089 lower-numbered register. Load the higher-numbered register
5091 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5092 emit_move_insn (dest1, change_address (source, SImode, NULL));
5096 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5097 and SOURCE is either a double register or the constant zero. */
5099 frv_split_double_store (rtx dest, rtx source)
5101 rtx dest1 = change_address (dest, SImode, NULL);
5102 rtx dest2 = frv_index_memory (dest, SImode, 1);
5103 if (ZERO_P (source))
5105 emit_move_insn (dest1, CONST0_RTX (SImode));
5106 emit_move_insn (dest2, CONST0_RTX (SImode));
5110 emit_move_insn (dest1, gen_highpart (SImode, source));
5111 emit_move_insn (dest2, gen_lowpart (SImode, source));
5116 /* Split a min/max operation returning a SEQUENCE containing all of the
5120 frv_split_minmax (rtx operands[])
5122 rtx dest = operands[0];
5123 rtx minmax = operands[1];
5124 rtx src1 = operands[2];
5125 rtx src2 = operands[3];
5126 rtx cc_reg = operands[4];
5127 rtx cr_reg = operands[5];
5129 enum rtx_code test_code;
5130 enum machine_mode cr_mode = GET_MODE (cr_reg);
5134 /* Figure out which test to use. */
5135 switch (GET_CODE (minmax))
5140 case SMIN: test_code = LT; break;
5141 case SMAX: test_code = GT; break;
5142 case UMIN: test_code = LTU; break;
5143 case UMAX: test_code = GTU; break;
5146 /* Issue the compare instruction. */
5147 emit_insn (gen_rtx_SET (VOIDmode,
5149 gen_rtx_COMPARE (GET_MODE (cc_reg),
5152 /* Set the appropriate CCR bit. */
5153 emit_insn (gen_rtx_SET (VOIDmode,
5155 gen_rtx_fmt_ee (test_code,
5160 /* If are taking the min/max of a nonzero constant, load that first, and
5161 then do a conditional move of the other value. */
5162 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5164 gcc_assert (!rtx_equal_p (dest, src1));
5166 emit_move_insn (dest, src2);
5167 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5168 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5169 gen_rtx_SET (VOIDmode, dest, src1)));
5172 /* Otherwise, do each half of the move. */
5175 /* Emit the conditional move for the test being true if needed. */
5176 if (! rtx_equal_p (dest, src1))
5177 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5178 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5179 gen_rtx_SET (VOIDmode, dest, src1)));
5181 /* Emit the conditional move for the test being false if needed. */
5182 if (! rtx_equal_p (dest, src2))
5183 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5184 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5185 gen_rtx_SET (VOIDmode, dest, src2)));
5188 /* Finish up, return sequence. */
5195 /* Split an integer abs operation returning a SEQUENCE containing all of the
5199 frv_split_abs (rtx operands[])
5201 rtx dest = operands[0];
5202 rtx src = operands[1];
5203 rtx cc_reg = operands[2];
5204 rtx cr_reg = operands[3];
5209 /* Issue the compare < 0 instruction. */
5210 emit_insn (gen_rtx_SET (VOIDmode,
5212 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5214 /* Set the appropriate CCR bit. */
5215 emit_insn (gen_rtx_SET (VOIDmode,
5217 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5219 /* Emit the conditional negate if the value is negative. */
5220 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5221 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5222 gen_negsi2 (dest, src)));
5224 /* Emit the conditional move for the test being false if needed. */
5225 if (! rtx_equal_p (dest, src))
5226 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5227 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5228 gen_rtx_SET (VOIDmode, dest, src)));
5230 /* Finish up, return sequence. */
5237 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5238 register used in an insn. */
5241 frv_clear_registers_used (rtx *ptr, void *data)
5243 if (GET_CODE (*ptr) == REG)
5245 int regno = REGNO (*ptr);
5246 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5248 if (regno < FIRST_PSEUDO_REGISTER)
5250 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5252 while (regno < reg_max)
5254 CLEAR_HARD_REG_BIT (*p_regs, regno);
5264 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5266 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5267 initialize the static storage. */
5269 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5271 frv_ifcvt.added_insns_list = NULL_RTX;
5272 frv_ifcvt.cur_scratch_regs = 0;
5273 frv_ifcvt.num_nested_cond_exec = 0;
5274 frv_ifcvt.cr_reg = NULL_RTX;
5275 frv_ifcvt.nested_cc_reg = NULL_RTX;
5276 frv_ifcvt.extra_int_cr = NULL_RTX;
5277 frv_ifcvt.extra_fp_cr = NULL_RTX;
5278 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5282 /* Internal function to add a potential insn to the list of insns to be inserted
5283 if the conditional execution conversion is successful. */
5286 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5288 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5290 link->jump = before_p; /* Mark to add this before or after insn. */
5291 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5292 frv_ifcvt.added_insns_list);
5294 if (TARGET_DEBUG_COND_EXEC)
5297 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5298 (before_p) ? "before" : "after",
5299 (int)INSN_UID (insn));
5301 debug_rtx (pattern);
5306 /* A C expression to modify the code described by the conditional if
5307 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5308 FALSE_EXPR for converting if-then and if-then-else code to conditional
5309 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5310 tests cannot be converted. */
5313 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5315 basic_block test_bb = ce_info->test_bb; /* test basic block */
5316 basic_block then_bb = ce_info->then_bb; /* THEN */
5317 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5318 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5319 rtx true_expr = *p_true;
5323 enum machine_mode mode = GET_MODE (true_expr);
5327 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5329 rtx sub_cond_exec_reg;
5331 enum rtx_code code_true;
5332 enum rtx_code code_false;
5333 enum reg_class cc_class;
5334 enum reg_class cr_class;
5337 reg_set_iterator rsi;
5339 /* Make sure we are only dealing with hard registers. Also honor the
5340 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5342 if (!reload_completed || !TARGET_COND_EXEC
5343 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5346 /* Figure out which registers we can allocate for our own purposes. Only
5347 consider registers that are not preserved across function calls and are
5348 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5349 if we did not need to use them in reloading other registers. */
5350 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5351 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5352 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5353 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5354 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5356 /* If this is a nested IF, we need to discover whether the CC registers that
5357 are set/used inside of the block are used anywhere else. If not, we can
5358 change them to be the CC register that is paired with the CR register that
5359 controls the outermost IF block. */
5360 if (ce_info->pass > 1)
5362 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5363 for (j = CC_FIRST; j <= CC_LAST; j++)
5364 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5366 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5370 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5374 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5377 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5381 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5382 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5384 frv_ifcvt.added_insns_list = NULL_RTX;
5385 frv_ifcvt.cur_scratch_regs = 0;
5387 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5388 * sizeof (basic_block));
5394 /* Remove anything live at the beginning of the join block from being
5395 available for allocation. */
5396 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5398 if (regno < FIRST_PSEUDO_REGISTER)
5399 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5403 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5405 if (ce_info->num_multiple_test_blocks)
5407 basic_block multiple_test_bb = ce_info->last_test_bb;
5409 while (multiple_test_bb != test_bb)
5411 bb[num_bb++] = multiple_test_bb;
5412 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5416 /* Add in the THEN and ELSE blocks to be scanned. */
5417 bb[num_bb++] = then_bb;
5419 bb[num_bb++] = else_bb;
5421 sub_cond_exec_reg = NULL_RTX;
5422 frv_ifcvt.num_nested_cond_exec = 0;
5424 /* Scan all of the blocks for registers that must not be allocated. */
5425 for (j = 0; j < num_bb; j++)
5427 rtx last_insn = BB_END (bb[j]);
5428 rtx insn = BB_HEAD (bb[j]);
5432 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5433 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5435 (int) INSN_UID (BB_HEAD (bb[j])),
5436 (int) INSN_UID (BB_END (bb[j])));
5438 /* Anything live at the beginning of the block is obviously unavailable
5440 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5442 if (regno < FIRST_PSEUDO_REGISTER)
5443 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5446 /* Loop through the insns in the block. */
5449 /* Mark any new registers that are created as being unavailable for
5450 allocation. Also see if the CC register used in nested IFs can be
5456 int skip_nested_if = FALSE;
5458 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5459 (void *)&tmp_reg->regs);
5461 pattern = PATTERN (insn);
5462 if (GET_CODE (pattern) == COND_EXEC)
5464 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5466 if (reg != sub_cond_exec_reg)
5468 sub_cond_exec_reg = reg;
5469 frv_ifcvt.num_nested_cond_exec++;
5473 set = single_set_pattern (pattern);
5476 rtx dest = SET_DEST (set);
5477 rtx src = SET_SRC (set);
5479 if (GET_CODE (dest) == REG)
5481 int regno = REGNO (dest);
5482 enum rtx_code src_code = GET_CODE (src);
5484 if (CC_P (regno) && src_code == COMPARE)
5485 skip_nested_if = TRUE;
5487 else if (CR_P (regno)
5488 && (src_code == IF_THEN_ELSE
5489 || COMPARISON_P (src)))
5490 skip_nested_if = TRUE;
5494 if (! skip_nested_if)
5495 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5496 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5499 if (insn == last_insn)
5502 insn = NEXT_INSN (insn);
5506 /* If this is a nested if, rewrite the CC registers that are available to
5507 include the ones that can be rewritten, to increase the chance of being
5508 able to allocate a paired CC/CR register combination. */
5509 if (ce_info->pass > 1)
5511 for (j = CC_FIRST; j <= CC_LAST; j++)
5512 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5513 SET_HARD_REG_BIT (tmp_reg->regs, j);
5515 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5521 fprintf (dump_file, "Available GPRs: ");
5523 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5524 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5526 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5527 if (++num_gprs > GPR_TEMP_NUM+2)
5531 fprintf (dump_file, "%s\nAvailable CRs: ",
5532 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5534 for (j = CR_FIRST; j <= CR_LAST; j++)
5535 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5536 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5538 fputs ("\n", dump_file);
5540 if (ce_info->pass > 1)
5542 fprintf (dump_file, "Modifiable CCs: ");
5543 for (j = CC_FIRST; j <= CC_LAST; j++)
5544 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5545 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5547 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5548 frv_ifcvt.num_nested_cond_exec);
5552 /* Allocate the appropriate temporary condition code register. Try to
5553 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5554 that conditional cmp's can be done. */
5555 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5557 cr_class = ICR_REGS;
5558 cc_class = ICC_REGS;
5559 cc_first = ICC_FIRST;
5562 else if (mode == CC_FPmode)
5564 cr_class = FCR_REGS;
5565 cc_class = FCC_REGS;
5566 cc_first = FCC_FIRST;
5571 cc_first = cc_last = 0;
5572 cr_class = cc_class = NO_REGS;
5575 cc = XEXP (true_expr, 0);
5576 nested_cc = cr = NULL_RTX;
5577 if (cc_class != NO_REGS)
5579 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5580 so we can execute a csubcc/caddcc/cfcmps instruction. */
5583 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5585 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5587 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5588 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5590 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5591 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5594 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5595 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5605 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5612 "Will use %s for conditional execution, %s for nested comparisons\n",
5613 reg_names[ REGNO (cr)],
5614 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5616 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5617 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5618 bit being true. We don't do this for floating point, because of NaNs. */
5619 code = GET_CODE (true_expr);
5620 if (GET_MODE (cc) != CC_FPmode)
5622 code = reverse_condition (code);
5632 check_insn = gen_rtx_SET (VOIDmode, cr,
5633 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5635 /* Record the check insn to be inserted later. */
5636 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5638 /* Update the tests. */
5639 frv_ifcvt.cr_reg = cr;
5640 frv_ifcvt.nested_cc_reg = nested_cc;
5641 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5642 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5645 /* Fail, don't do this conditional execution. */
5648 *p_false = NULL_RTX;
5650 fprintf (dump_file, "Disabling this conditional execution.\n");
5656 /* A C expression to modify the code described by the conditional if
5657 information CE_INFO, for the basic block BB, possibly updating the tests in
5658 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5659 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5660 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5662 /* p_true and p_false are given expressions of the form:
5664 (and (eq:CC_CCR (reg:CC_CCR)
5670 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5675 rtx old_true = XEXP (*p_true, 0);
5676 rtx old_false = XEXP (*p_false, 0);
5677 rtx true_expr = XEXP (*p_true, 1);
5678 rtx false_expr = XEXP (*p_false, 1);
5681 rtx cr = XEXP (old_true, 0);
5683 rtx new_cr = NULL_RTX;
5684 rtx *p_new_cr = (rtx *)0;
5688 enum reg_class cr_class;
5689 enum machine_mode mode = GET_MODE (true_expr);
5690 rtx (*logical_func)(rtx, rtx, rtx);
5692 if (TARGET_DEBUG_COND_EXEC)
5695 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5696 ce_info->and_and_p ? "&&" : "||");
5698 debug_rtx (*p_true);
5700 fputs ("\nfalse insn:\n", stderr);
5701 debug_rtx (*p_false);
5704 if (!TARGET_MULTI_CE)
5707 if (GET_CODE (cr) != REG)
5710 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5712 cr_class = ICR_REGS;
5713 p_new_cr = &frv_ifcvt.extra_int_cr;
5715 else if (mode == CC_FPmode)
5717 cr_class = FCR_REGS;
5718 p_new_cr = &frv_ifcvt.extra_fp_cr;
5723 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5724 more &&/|| tests. */
5728 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5729 CC_CCRmode, TRUE, TRUE);
5734 if (ce_info->and_and_p)
5736 old_test = old_false;
5737 test_expr = true_expr;
5738 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5739 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5740 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5744 old_test = old_false;
5745 test_expr = false_expr;
5746 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5747 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5748 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5751 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5752 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5754 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5756 /* Now add the conditional check insn. */
5757 cc = XEXP (test_expr, 0);
5758 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5759 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5761 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5763 /* Add the new check insn to the list of check insns that need to be
5765 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5767 if (TARGET_DEBUG_COND_EXEC)
5769 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5772 debug_rtx (*p_true);
5774 fputs ("\nfalse insn:\n", stderr);
5775 debug_rtx (*p_false);
5781 *p_true = *p_false = NULL_RTX;
5783 /* If we allocated a CR register, release it. */
5786 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5787 *p_new_cr = NULL_RTX;
5790 if (TARGET_DEBUG_COND_EXEC)
5791 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5797 /* Return a register which will be loaded with a value if an IF block is
5798 converted to conditional execution. This is used to rewrite instructions
5799 that use constants to ones that just use registers. */
5802 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5804 int num_alloc = frv_ifcvt.cur_scratch_regs;
5808 /* We know gr0 == 0, so replace any errant uses. */
5809 if (value == const0_rtx)
5810 return gen_rtx_REG (SImode, GPR_FIRST);
5812 /* First search all registers currently loaded to see if we have an
5813 applicable constant. */
5814 if (CONSTANT_P (value)
5815 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5817 for (i = 0; i < num_alloc; i++)
5819 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5820 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5824 /* Have we exhausted the number of registers available? */
5825 if (num_alloc >= GPR_TEMP_NUM)
5828 fprintf (dump_file, "Too many temporary registers allocated\n");
5833 /* Allocate the new register. */
5834 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5838 fputs ("Could not find a scratch register\n", dump_file);
5843 frv_ifcvt.cur_scratch_regs++;
5844 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5848 if (GET_CODE (value) == CONST_INT)
5849 fprintf (dump_file, "Register %s will hold %ld\n",
5850 reg_names[ REGNO (reg)], (long)INTVAL (value));
5852 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5853 fprintf (dump_file, "Register %s will hold LR\n",
5854 reg_names[ REGNO (reg)]);
5857 fprintf (dump_file, "Register %s will hold a saved value\n",
5858 reg_names[ REGNO (reg)]);
5865 /* Update a MEM used in conditional code that might contain an offset to put
5866 the offset into a scratch register, so that the conditional load/store
5867 operations can be used. This function returns the original pointer if the
5868 MEM is valid to use in conditional code, NULL if we can't load up the offset
5869 into a temporary register, or the new MEM if we were successful. */
5872 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5874 rtx addr = XEXP (mem, 0);
5876 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5878 if (GET_CODE (addr) == PLUS)
5880 rtx addr_op0 = XEXP (addr, 0);
5881 rtx addr_op1 = XEXP (addr, 1);
5883 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5885 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5889 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5896 else if (CONSTANT_P (addr))
5897 addr = frv_ifcvt_load_value (addr, insn);
5902 if (addr == NULL_RTX)
5905 else if (XEXP (mem, 0) != addr)
5906 return change_address (mem, mode, addr);
5913 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5914 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5917 single_set_pattern (rtx pattern)
5922 if (GET_CODE (pattern) == COND_EXEC)
5923 pattern = COND_EXEC_CODE (pattern);
5925 if (GET_CODE (pattern) == SET)
5928 else if (GET_CODE (pattern) == PARALLEL)
5930 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5932 rtx sub = XVECEXP (pattern, 0, i);
5934 switch (GET_CODE (sub))
5958 /* A C expression to modify the code described by the conditional if
5959 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5960 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5961 insn cannot be converted to be executed conditionally. */
5964 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5968 rtx orig_ce_pattern = pattern;
5974 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5976 test = COND_EXEC_TEST (pattern);
5977 if (GET_CODE (test) == AND)
5979 rtx cr = frv_ifcvt.cr_reg;
5982 op0 = XEXP (test, 0);
5983 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5986 op1 = XEXP (test, 1);
5987 test_reg = XEXP (op1, 0);
5988 if (GET_CODE (test_reg) != REG)
5991 /* Is this the first nested if block in this sequence? If so, generate
5992 an andcr or andncr. */
5993 if (! frv_ifcvt.last_nested_if_cr)
5997 frv_ifcvt.last_nested_if_cr = test_reg;
5998 if (GET_CODE (op0) == NE)
5999 and_op = gen_andcr (test_reg, cr, test_reg);
6001 and_op = gen_andncr (test_reg, cr, test_reg);
6003 frv_ifcvt_add_insn (and_op, insn, TRUE);
6006 /* If this isn't the first statement in the nested if sequence, see if we
6007 are dealing with the same register. */
6008 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6011 COND_EXEC_TEST (pattern) = test = op1;
6014 /* If this isn't a nested if, reset state variables. */
6017 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6020 set = single_set_pattern (pattern);
6023 rtx dest = SET_DEST (set);
6024 rtx src = SET_SRC (set);
6025 enum machine_mode mode = GET_MODE (dest);
6027 /* Check for normal binary operators. */
6028 if (mode == SImode && ARITHMETIC_P (src))
6030 op0 = XEXP (src, 0);
6031 op1 = XEXP (src, 1);
6033 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6035 op1 = frv_ifcvt_load_value (op1, insn);
6037 COND_EXEC_CODE (pattern)
6038 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6046 /* For multiply by a constant, we need to handle the sign extending
6047 correctly. Add a USE of the value after the multiply to prevent flow
6048 from cratering because only one register out of the two were used. */
6049 else if (mode == DImode && GET_CODE (src) == MULT)
6051 op0 = XEXP (src, 0);
6052 op1 = XEXP (src, 1);
6053 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6055 op1 = frv_ifcvt_load_value (op1, insn);
6058 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6059 COND_EXEC_CODE (pattern)
6060 = gen_rtx_SET (VOIDmode, dest,
6061 gen_rtx_MULT (DImode, op0, op1));
6067 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6070 /* If we are just loading a constant created for a nested conditional
6071 execution statement, just load the constant without any conditional
6072 execution, since we know that the constant will not interfere with any
6074 else if (frv_ifcvt.scratch_insns_bitmap
6075 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6077 && REG_P (SET_DEST (set))
6078 /* We must not unconditionally set a scratch reg chosen
6079 for a nested if-converted block if its incoming
6080 value from the TEST block (or the result of the THEN
6081 branch) could/should propagate to the JOIN block.
6082 It suffices to test whether the register is live at
6083 the JOIN point: if it's live there, we can infer
6084 that we set it in the former JOIN block of the
6085 nested if-converted block (otherwise it wouldn't
6086 have been available as a scratch register), and it
6087 is either propagated through or set in the other
6088 conditional block. It's probably not worth trying
6089 to catch the latter case, and it could actually
6090 limit scheduling of the combined block quite
6093 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6094 REGNO (SET_DEST (set))))
6095 /* Similarly, we must not unconditionally set a reg
6096 used as scratch in the THEN branch if the same reg
6097 is live in the ELSE branch. */
6098 && (! ce_info->else_bb
6099 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6100 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6101 REGNO (SET_DEST (set))))))
6104 else if (mode == QImode || mode == HImode || mode == SImode
6107 int changed_p = FALSE;
6109 /* Check for just loading up a constant */
6110 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6112 src = frv_ifcvt_load_value (src, insn);
6119 /* See if we need to fix up stores */
6120 if (GET_CODE (dest) == MEM)
6122 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6127 else if (new_mem != dest)
6134 /* See if we need to fix up loads */
6135 if (GET_CODE (src) == MEM)
6137 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6142 else if (new_mem != src)
6149 /* If either src or destination changed, redo SET. */
6151 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6154 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6155 rewriting the CC register to be the same as the paired CC/CR register
6157 else if (mode == CC_CCRmode && COMPARISON_P (src))
6159 int regno = REGNO (XEXP (src, 0));
6162 if (ce_info->pass > 1
6163 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6164 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6166 src = gen_rtx_fmt_ee (GET_CODE (src),
6168 frv_ifcvt.nested_cc_reg,
6172 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6173 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6176 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6177 else if (ce_info->pass > 1
6178 && GET_CODE (dest) == REG
6179 && CC_P (REGNO (dest))
6180 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6181 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6183 && GET_CODE (src) == COMPARE)
6185 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6186 COND_EXEC_CODE (pattern)
6187 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6191 if (TARGET_DEBUG_COND_EXEC)
6193 rtx orig_pattern = PATTERN (insn);
6195 PATTERN (insn) = pattern;
6197 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6201 PATTERN (insn) = orig_pattern;
6207 if (TARGET_DEBUG_COND_EXEC)
6209 rtx orig_pattern = PATTERN (insn);
6211 PATTERN (insn) = orig_ce_pattern;
6213 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6217 PATTERN (insn) = orig_pattern;
6224 /* A C expression to perform any final machine dependent modifications in
6225 converting code to conditional execution in the code described by the
6226 conditional if information CE_INFO. */
6229 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6233 rtx p = frv_ifcvt.added_insns_list;
6236 /* Loop inserting the check insns. The last check insn is the first test,
6237 and is the appropriate place to insert constants. */
6242 rtx check_and_insert_insns = XEXP (p, 0);
6245 check_insn = XEXP (check_and_insert_insns, 0);
6246 existing_insn = XEXP (check_and_insert_insns, 1);
6249 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6250 the existing insn, otherwise it is to be inserted AFTER. */
6251 if (check_and_insert_insns->jump)
6253 emit_insn_before (check_insn, existing_insn);
6254 check_and_insert_insns->jump = 0;
6257 emit_insn_after (check_insn, existing_insn);
6259 free_EXPR_LIST_node (check_and_insert_insns);
6260 free_EXPR_LIST_node (old_p);
6262 while (p != NULL_RTX);
6264 /* Load up any constants needed into temp gprs */
6265 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6267 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6268 if (! frv_ifcvt.scratch_insns_bitmap)
6269 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6270 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6271 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6274 frv_ifcvt.added_insns_list = NULL_RTX;
6275 frv_ifcvt.cur_scratch_regs = 0;
6279 /* A C expression to cancel any machine dependent modifications in converting
6280 code to conditional execution in the code described by the conditional if
6281 information CE_INFO. */
6284 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6287 rtx p = frv_ifcvt.added_insns_list;
6289 /* Loop freeing up the EXPR_LIST's allocated. */
6290 while (p != NULL_RTX)
6292 rtx check_and_jump = XEXP (p, 0);
6296 free_EXPR_LIST_node (check_and_jump);
6297 free_EXPR_LIST_node (old_p);
6300 /* Release any temporary gprs allocated. */
6301 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6302 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6304 frv_ifcvt.added_insns_list = NULL_RTX;
6305 frv_ifcvt.cur_scratch_regs = 0;
6309 /* A C expression for the size in bytes of the trampoline, as an integer.
6313 setlo #0, <static_chain>
6315 sethi #0, <static_chain>
6316 jmpl @(gr0,<jmp_reg>) */
6319 frv_trampoline_size (void)
6322 /* Allocate room for the function descriptor and the lddi
6325 return 5 /* instructions */ * 4 /* instruction size. */;
6329 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6330 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6331 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6332 should be passed to the function when it is called.
6337 setlo #0, <static_chain>
6339 sethi #0, <static_chain>
6340 jmpl @(gr0,<jmp_reg>) */
6343 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6345 rtx addr = XEXP (m_tramp, 0);
6346 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6347 rtx sc_reg = force_reg (Pmode, static_chain);
6349 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6352 GEN_INT (frv_trampoline_size ()), SImode,
6358 /* Many machines have some registers that cannot be copied directly to or from
6359 memory or even from other types of registers. An example is the `MQ'
6360 register, which on most machines, can only be copied to or from general
6361 registers, but not memory. Some machines allow copying all registers to and
6362 from memory, but require a scratch register for stores to some memory
6363 locations (e.g., those with symbolic address on the RT, and those with
6364 certain symbolic address on the SPARC when compiling PIC). In some cases,
6365 both an intermediate and a scratch register are required.
6367 You should define these macros to indicate to the reload phase that it may
6368 need to allocate at least one register for a reload in addition to the
6369 register to contain the data. Specifically, if copying X to a register
6370 RCLASS in MODE requires an intermediate register, you should define
6371 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6372 whose registers can be used as intermediate registers or scratch registers.
6374 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6375 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6376 largest register class required. If the requirements for input and output
6377 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6378 instead of defining both macros identically.
6380 The values returned by these macros are often `GENERAL_REGS'. Return
6381 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6382 to or from a register of RCLASS in MODE without requiring a scratch register.
6383 Do not define this macro if it would always return `NO_REGS'.
6385 If a scratch register is required (either with or without an intermediate
6386 register), you should define patterns for `reload_inM' or `reload_outM', as
6387 required.. These patterns, which will normally be implemented with a
6388 `define_expand', should be similar to the `movM' patterns, except that
6389 operand 2 is the scratch register.
6391 Define constraints for the reload register and scratch register that contain
6392 a single register class. If the original reload register (whose class is
6393 RCLASS) can meet the constraint given in the pattern, the value returned by
6394 these macros is used for the class of the scratch register. Otherwise, two
6395 additional reload registers are required. Their classes are obtained from
6396 the constraints in the insn pattern.
6398 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6399 either be in a hard register or in memory. Use `true_regnum' to find out;
6400 it will return -1 if the pseudo is in memory and the hard register number if
6401 it is in a register.
6403 These macros should not be used in the case where a particular class of
6404 registers can only be copied to memory and not to another class of
6405 registers. In that case, secondary reload registers are not needed and
6406 would not be helpful. Instead, a stack location must be used to perform the
6407 copy and the `movM' pattern should use memory as an intermediate storage.
6408 This case often occurs between floating-point and general registers. */
6411 frv_secondary_reload_class (enum reg_class rclass,
6412 enum machine_mode mode ATTRIBUTE_UNUSED,
6423 /* Accumulators/Accumulator guard registers need to go through floating
6429 if (x && GET_CODE (x) == REG)
6431 int regno = REGNO (x);
6433 if (ACC_P (regno) || ACCG_P (regno))
6438 /* Nonzero constants should be loaded into an FPR through a GPR. */
6442 if (x && CONSTANT_P (x) && !ZERO_P (x))
6448 /* All of these types need gpr registers. */
6460 /* The accumulators need fpr registers. */
6472 /* This hook exists to catch the case where secondary_reload_class() is
6473 called from init_reg_autoinc() in regclass.c - before the reload optabs
6474 have been initialised. */
6477 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6478 enum machine_mode reload_mode,
6479 secondary_reload_info * sri)
6481 enum reg_class rclass = NO_REGS;
6482 enum reg_class reload_class = (enum reg_class) reload_class_i;
6484 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6486 sri->icode = sri->prev_sri->t_icode;
6490 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6492 if (rclass != NO_REGS)
6494 enum insn_code icode
6495 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6499 /* This happens when then the reload_[in|out]_optabs have
6500 not been initialised. */
6501 sri->t_icode = CODE_FOR_nothing;
6506 /* Fall back to the default secondary reload handler. */
6507 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6511 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6514 frv_class_likely_spilled_p (reg_class_t rclass)
6524 case FDPIC_FPTR_REGS:
6546 /* An expression for the alignment of a structure field FIELD if the
6547 alignment computed in the usual way is COMPUTED. GCC uses this
6548 value instead of the value in `BIGGEST_ALIGNMENT' or
6549 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6551 /* The definition type of the bit field data is either char, short, long or
6552 long long. The maximum bit size is the number of bits of its own type.
6554 The bit field data is assigned to a storage unit that has an adequate size
6555 for bit field data retention and is located at the smallest address.
6557 Consecutive bit field data are packed at consecutive bits having the same
6558 storage unit, with regard to the type, beginning with the MSB and continuing
6561 If a field to be assigned lies over a bit field type boundary, its
6562 assignment is completed by aligning it with a boundary suitable for the
6565 When a bit field having a bit length of 0 is declared, it is forcibly
6566 assigned to the next storage unit.
6579 &x 00000000 00000000 00000000 00000000
6582 &x+4 00000000 00000000 00000000 00000000
6585 &x+8 00000000 00000000 00000000 00000000
6588 &x+12 00000000 00000000 00000000 00000000
6594 frv_adjust_field_align (tree field, int computed)
6596 /* Make sure that the bitfield is not wider than the type. */
6597 if (DECL_BIT_FIELD (field)
6598 && !DECL_ARTIFICIAL (field))
6600 tree parent = DECL_CONTEXT (field);
6601 tree prev = NULL_TREE;
6604 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6606 if (TREE_CODE (cur) != FIELD_DECL)
6614 /* If this isn't a :0 field and if the previous element is a bitfield
6615 also, see if the type is different, if so, we will need to align the
6616 bit-field to the next boundary. */
6618 && ! DECL_PACKED (field)
6619 && ! integer_zerop (DECL_SIZE (field))
6620 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6622 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6623 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6624 computed = (prev_align > cur_align) ? prev_align : cur_align;
6632 /* A C expression that is nonzero if it is permissible to store a value of mode
6633 MODE in hard register number REGNO (or in several registers starting with
6634 that one). For a machine where all registers are equivalent, a suitable
6637 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6639 It is not necessary for this macro to check for the numbers of fixed
6640 registers, because the allocation mechanism considers them to be always
6643 On some machines, double-precision values must be kept in even/odd register
6644 pairs. The way to implement that is to define this macro to reject odd
6645 register numbers for such modes.
6647 The minimum requirement for a mode to be OK in a register is that the
6648 `movMODE' instruction pattern support moves between the register and any
6649 other hard register for which the mode is OK; and that moving a value into
6650 the register and back out not alter it.
6652 Since the same instruction used to move `SImode' will work for all narrower
6653 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6654 to distinguish between these modes, provided you define patterns `movhi',
6655 etc., to take advantage of this. This is useful because of the interaction
6656 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6657 all integer modes to be tieable.
6659 Many machines have special registers for floating point arithmetic. Often
6660 people assume that floating point machine modes are allowed only in floating
6661 point registers. This is not true. Any registers that can hold integers
6662 can safely *hold* a floating point machine mode, whether or not floating
6663 arithmetic can be done on it in those registers. Integer move instructions
6664 can be used to move the values.
6666 On some machines, though, the converse is true: fixed-point machine modes
6667 may not go in floating registers. This is true if the floating registers
6668 normalize any value stored in them, because storing a non-floating value
6669 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6670 fixed-point machine modes in floating registers. But if the floating
6671 registers do not automatically normalize, if you can store any bit pattern
6672 in one and retrieve it unchanged without a trap, then any machine mode may
6673 go in a floating register, so you can define this macro to say so.
6675 The primary significance of special floating registers is rather that they
6676 are the registers acceptable in floating point arithmetic instructions.
6677 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6678 writing the proper constraints for those instructions.
6680 On some machines, the floating registers are especially slow to access, so
6681 that it is better to store a value in a stack frame than in such a register
6682 if floating point arithmetic is not being done. As long as the floating
6683 registers are not in class `GENERAL_REGS', they will not be used unless some
6684 pattern's constraint asks for one. */
6687 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6697 return ICC_P (regno) || GPR_P (regno);
6700 return CR_P (regno) || GPR_P (regno);
6703 return FCC_P (regno) || GPR_P (regno);
6709 /* Set BASE to the first register in REGNO's class. Set MASK to the
6710 bits that must be clear in (REGNO - BASE) for the register to be
6712 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6716 /* ACCGs store one byte. Two-byte quantities must start in
6717 even-numbered registers, four-byte ones in registers whose
6718 numbers are divisible by four, and so on. */
6720 mask = GET_MODE_SIZE (mode) - 1;
6724 /* The other registers store one word. */
6725 if (GPR_P (regno) || regno == AP_FIRST)
6728 else if (FPR_P (regno))
6731 else if (ACC_P (regno))
6734 else if (SPR_P (regno))
6735 return mode == SImode;
6737 /* Fill in the table. */
6741 /* Anything smaller than an SI is OK in any word-sized register. */
6742 if (GET_MODE_SIZE (mode) < 4)
6745 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6747 return (((regno - base) & mask) == 0);
6754 /* A C expression for the number of consecutive hard registers, starting at
6755 register number REGNO, required to hold a value of mode MODE.
6757 On a machine where all registers are exactly one word, a suitable definition
6760 #define HARD_REGNO_NREGS(REGNO, MODE) \
6761 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6762 / UNITS_PER_WORD)) */
6764 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6765 that we can build the appropriate instructions to properly reload the
6766 values. Also, make the byte-sized accumulator guards use one guard
6770 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6773 return GET_MODE_SIZE (mode);
6775 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6779 /* A C expression for the maximum number of consecutive registers of
6780 class RCLASS needed to hold a value of mode MODE.
6782 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6783 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6784 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6786 This macro helps control the handling of multiple-word values in
6789 This declaration is required. */
6792 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6794 if (rclass == ACCG_REGS)
6795 /* An N-byte value requires N accumulator guards. */
6796 return GET_MODE_SIZE (mode);
6798 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6802 /* A C expression that is nonzero if X is a legitimate constant for an
6803 immediate operand on the target machine. You can assume that X satisfies
6804 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6805 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6808 frv_legitimate_constant_p (rtx x)
6810 enum machine_mode mode = GET_MODE (x);
6812 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6813 means that the move expanders will be expected to deal with most
6814 kinds of constant, regardless of what we return here.
6816 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6817 a constant can be entered into reg_equiv_constant[]. If we return true,
6818 reload can create new instances of the constant whenever it likes.
6820 The idea is therefore to accept as many constants as possible (to give
6821 reload more freedom) while rejecting constants that can only be created
6822 at certain times. In particular, anything with a symbolic component will
6823 require use of the pseudo FDPIC register, which is only available before
6826 return LEGITIMATE_PIC_OPERAND_P (x);
6828 /* All of the integer constants are ok. */
6829 if (GET_CODE (x) != CONST_DOUBLE)
6832 /* double integer constants are ok. */
6833 if (mode == VOIDmode || mode == DImode)
6836 /* 0 is always ok. */
6837 if (x == CONST0_RTX (mode))
6840 /* If floating point is just emulated, allow any constant, since it will be
6841 constructed in the GPRs. */
6842 if (!TARGET_HAS_FPRS)
6845 if (mode == DFmode && !TARGET_DOUBLE)
6848 /* Otherwise store the constant away and do a load. */
6852 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6853 CC_NZ for comparisons against zero in which a single Z or N flag test
6854 is enough, CC_UNS for other unsigned comparisons, and CC for other
6855 signed comparisons. */
6858 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6860 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6869 return y == const0_rtx ? CC_NZmode : CCmode;
6875 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6883 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6885 #define HIGH_COST 40
6886 #define MEDIUM_COST 3
6890 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6891 reg_class_t from, reg_class_t to)
6975 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6978 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6979 reg_class_t rclass ATTRIBUTE_UNUSED,
6980 bool in ATTRIBUTE_UNUSED)
6986 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6987 use ".picptr" to generate safe relocations for PIC code. We also
6988 need a fixup entry for aligned (non-debugging) code. */
6991 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6993 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6995 if (GET_CODE (value) == CONST
6996 || GET_CODE (value) == SYMBOL_REF
6997 || GET_CODE (value) == LABEL_REF)
6999 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
7000 && SYMBOL_REF_FUNCTION_P (value))
7002 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
7003 output_addr_const (asm_out_file, value);
7004 fputs (")\n", asm_out_file);
7007 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7008 && frv_function_symbol_referenced_p (value))
7010 if (aligned_p && !TARGET_FDPIC)
7012 static int label_num = 0;
7016 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7017 p = (* targetm.strip_name_encoding) (buf);
7019 fprintf (asm_out_file, "%s:\n", p);
7020 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7021 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7022 fprintf (asm_out_file, "\t.previous\n");
7024 assemble_integer_with_op ("\t.picptr\t", value);
7029 /* We've set the unaligned SI op to NULL, so we always have to
7030 handle the unaligned case here. */
7031 assemble_integer_with_op ("\t.4byte\t", value);
7035 return default_assemble_integer (value, size, aligned_p);
7038 /* Function to set up the backend function structure. */
7040 static struct machine_function *
7041 frv_init_machine_status (void)
7043 return ggc_alloc_cleared_machine_function ();
7046 /* Implement TARGET_SCHED_ISSUE_RATE. */
7049 frv_issue_rate (void)
7054 switch (frv_cpu_type)
7058 case FRV_CPU_SIMPLE:
7066 case FRV_CPU_GENERIC:
7068 case FRV_CPU_TOMCAT:
7076 /* A for_each_rtx callback. If X refers to an accumulator, return
7077 ACC_GROUP_ODD if the bit 2 of the register number is set and
7078 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7082 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7086 if (ACC_P (REGNO (*x)))
7087 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7088 if (ACCG_P (REGNO (*x)))
7089 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7094 /* Return the value of INSN's acc_group attribute. */
7097 frv_acc_group (rtx insn)
7099 /* This distinction only applies to the FR550 packing constraints. */
7100 if (frv_cpu_type != FRV_CPU_FR550)
7101 return ACC_GROUP_NONE;
7102 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7105 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7106 INSN will try to claim first. Since this value depends only on the
7107 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7110 frv_insn_unit (rtx insn)
7112 enum attr_type type;
7114 type = get_attr_type (insn);
7115 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7117 /* We haven't seen this type of instruction before. */
7121 /* Issue the instruction on its own to see which unit it prefers. */
7122 state = alloca (state_size ());
7123 state_reset (state);
7124 state_transition (state, insn);
7126 /* Find out which unit was taken. */
7127 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7128 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7131 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7133 frv_type_to_unit[type] = unit;
7135 return frv_type_to_unit[type];
7138 /* Return true if INSN issues to a branch unit. */
7141 frv_issues_to_branch_unit_p (rtx insn)
7143 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7146 /* The current state of the packing pass, implemented by frv_pack_insns. */
7148 /* The state of the pipeline DFA. */
7151 /* Which hardware registers are set within the current packet,
7152 and the conditions under which they are set. */
7153 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7155 /* The memory locations that have been modified so far in this
7156 packet. MEM is the memref and COND is the regstate_t condition
7157 under which it is set. */
7163 /* The number of valid entries in MEMS. The value is larger than
7164 ARRAY_SIZE (mems) if there were too many mems to record. */
7165 unsigned int num_mems;
7167 /* The maximum number of instructions that can be packed together. */
7168 unsigned int issue_rate;
7170 /* The instructions in the packet, partitioned into groups. */
7171 struct frv_packet_group {
7172 /* How many instructions in the packet belong to this group. */
7173 unsigned int num_insns;
7175 /* A list of the instructions that belong to this group, in the order
7176 they appear in the rtl stream. */
7177 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7179 /* The contents of INSNS after they have been sorted into the correct
7180 assembly-language order. Element X issues to unit X. The list may
7181 contain extra nops. */
7182 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7184 /* The member of frv_nops[] to use in sorted[]. */
7186 } groups[NUM_GROUPS];
7188 /* The instructions that make up the current packet. */
7189 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7190 unsigned int num_insns;
7193 /* Return the regstate_t flags for the given COND_EXEC condition.
7194 Abort if the condition isn't in the right form. */
7197 frv_cond_flags (rtx cond)
7199 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7200 && GET_CODE (XEXP (cond, 0)) == REG
7201 && CR_P (REGNO (XEXP (cond, 0)))
7202 && XEXP (cond, 1) == const0_rtx);
7203 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7204 | (GET_CODE (cond) == NE
7206 : REGSTATE_IF_FALSE));
7210 /* Return true if something accessed under condition COND2 can
7211 conflict with something written under condition COND1. */
7214 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7216 /* If either reference was unconditional, we have a conflict. */
7217 if ((cond1 & REGSTATE_IF_EITHER) == 0
7218 || (cond2 & REGSTATE_IF_EITHER) == 0)
7221 /* The references might conflict if they were controlled by
7223 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7226 /* They definitely conflict if they are controlled by the
7228 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7235 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7236 the current packet. DATA points to a regstate_t that describes the
7237 condition under which *X might be set or used. */
7240 frv_registers_conflict_p_1 (rtx *x, void *data)
7242 unsigned int regno, i;
7245 cond = *(regstate_t *) data;
7247 if (GET_CODE (*x) == REG)
7248 FOR_EACH_REGNO (regno, *x)
7249 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7250 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7253 if (GET_CODE (*x) == MEM)
7255 /* If we ran out of memory slots, assume a conflict. */
7256 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7259 /* Check for output or true dependencies with earlier MEMs. */
7260 for (i = 0; i < frv_packet.num_mems; i++)
7261 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7263 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7267 if (output_dependence (frv_packet.mems[i].mem, *x))
7272 /* The return values of calls aren't significant: they describe
7273 the effect of the call as a whole, not of the insn itself. */
7274 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7276 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7281 /* Check subexpressions. */
7286 /* Return true if something in X might depend on an instruction
7287 in the current packet. */
7290 frv_registers_conflict_p (rtx x)
7295 if (GET_CODE (x) == COND_EXEC)
7297 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7300 flags |= frv_cond_flags (XEXP (x, 0));
7303 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7307 /* A note_stores callback. DATA points to the regstate_t condition
7308 under which X is modified. Update FRV_PACKET accordingly. */
7311 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7315 if (GET_CODE (x) == REG)
7316 FOR_EACH_REGNO (regno, x)
7317 frv_packet.regstate[regno] |= *(regstate_t *) data;
7319 if (GET_CODE (x) == MEM)
7321 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7323 frv_packet.mems[frv_packet.num_mems].mem = x;
7324 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7326 frv_packet.num_mems++;
7331 /* Update the register state information for an instruction whose
7335 frv_registers_update (rtx x)
7339 flags = REGSTATE_MODIFIED;
7340 if (GET_CODE (x) == COND_EXEC)
7342 flags |= frv_cond_flags (XEXP (x, 0));
7345 note_stores (x, frv_registers_update_1, &flags);
7349 /* Initialize frv_packet for the start of a new packet. */
7352 frv_start_packet (void)
7354 enum frv_insn_group group;
7356 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7357 frv_packet.num_mems = 0;
7358 frv_packet.num_insns = 0;
7359 for (group = 0; group < NUM_GROUPS; group++)
7360 frv_packet.groups[group].num_insns = 0;
7364 /* Likewise for the start of a new basic block. */
7367 frv_start_packet_block (void)
7369 state_reset (frv_packet.dfa_state);
7370 frv_start_packet ();
7374 /* Finish the current packet, if any, and start a new one. Call
7375 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7378 frv_finish_packet (void (*handle_packet) (void))
7380 if (frv_packet.num_insns > 0)
7383 state_transition (frv_packet.dfa_state, 0);
7384 frv_start_packet ();
7389 /* Return true if INSN can be added to the current packet. Update
7390 the DFA state on success. */
7393 frv_pack_insn_p (rtx insn)
7395 /* See if the packet is already as long as it can be. */
7396 if (frv_packet.num_insns == frv_packet.issue_rate)
7399 /* If the scheduler thought that an instruction should start a packet,
7400 it's usually a good idea to believe it. It knows much more about
7401 the latencies than we do.
7403 There are some exceptions though:
7405 - Conditional instructions are scheduled on the assumption that
7406 they will be executed. This is usually a good thing, since it
7407 tends to avoid unnecessary stalls in the conditional code.
7408 But we want to pack conditional instructions as tightly as
7409 possible, in order to optimize the case where they aren't
7412 - The scheduler will always put branches on their own, even
7413 if there's no real dependency.
7415 - There's no point putting a call in its own packet unless
7417 if (frv_packet.num_insns > 0
7418 && GET_CODE (insn) == INSN
7419 && GET_MODE (insn) == TImode
7420 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7423 /* Check for register conflicts. Don't do this for setlo since any
7424 conflict will be with the partnering sethi, with which it can
7426 if (get_attr_type (insn) != TYPE_SETLO)
7427 if (frv_registers_conflict_p (PATTERN (insn)))
7430 return state_transition (frv_packet.dfa_state, insn) < 0;
7434 /* Add instruction INSN to the current packet. */
7437 frv_add_insn_to_packet (rtx insn)
7439 struct frv_packet_group *packet_group;
7441 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7442 packet_group->insns[packet_group->num_insns++] = insn;
7443 frv_packet.insns[frv_packet.num_insns++] = insn;
7445 frv_registers_update (PATTERN (insn));
7449 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7450 packet ends in a branch or call, insert the nop before it, otherwise
7454 frv_insert_nop_in_packet (rtx insn)
7456 struct frv_packet_group *packet_group;
7459 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7460 last = frv_packet.insns[frv_packet.num_insns - 1];
7461 if (GET_CODE (last) != INSN)
7463 insn = emit_insn_before (PATTERN (insn), last);
7464 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7465 frv_packet.insns[frv_packet.num_insns++] = last;
7469 insn = emit_insn_after (PATTERN (insn), last);
7470 frv_packet.insns[frv_packet.num_insns++] = insn;
7472 packet_group->insns[packet_group->num_insns++] = insn;
7476 /* If packing is enabled, divide the instructions into packets and
7477 return true. Call HANDLE_PACKET for each complete packet. */
7480 frv_for_each_packet (void (*handle_packet) (void))
7482 rtx insn, next_insn;
7484 frv_packet.issue_rate = frv_issue_rate ();
7486 /* Early exit if we don't want to pack insns. */
7488 || !flag_schedule_insns_after_reload
7489 || !TARGET_VLIW_BRANCH
7490 || frv_packet.issue_rate == 1)
7493 /* Set up the initial packing state. */
7495 frv_packet.dfa_state = alloca (state_size ());
7497 frv_start_packet_block ();
7498 for (insn = get_insns (); insn != 0; insn = next_insn)
7503 code = GET_CODE (insn);
7504 next_insn = NEXT_INSN (insn);
7506 if (code == CODE_LABEL)
7508 frv_finish_packet (handle_packet);
7509 frv_start_packet_block ();
7513 switch (GET_CODE (PATTERN (insn)))
7522 /* Calls mustn't be packed on a TOMCAT. */
7523 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7524 frv_finish_packet (handle_packet);
7526 /* Since the last instruction in a packet determines the EH
7527 region, any exception-throwing instruction must come at
7528 the end of reordered packet. Insns that issue to a
7529 branch unit are bound to come last; for others it's
7530 too hard to predict. */
7531 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7532 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7533 frv_finish_packet (handle_packet);
7535 /* Finish the current packet if we can't add INSN to it.
7536 Simulate cycles until INSN is ready to issue. */
7537 if (!frv_pack_insn_p (insn))
7539 frv_finish_packet (handle_packet);
7540 while (!frv_pack_insn_p (insn))
7541 state_transition (frv_packet.dfa_state, 0);
7544 /* Add the instruction to the packet. */
7545 frv_add_insn_to_packet (insn);
7547 /* Calls and jumps end a packet, as do insns that throw
7549 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7550 frv_finish_packet (handle_packet);
7554 frv_finish_packet (handle_packet);
7559 /* Subroutine of frv_sort_insn_group. We are trying to sort
7560 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7561 language order. We have already picked a new position for
7562 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7563 These instructions will occupy elements [0, LOWER_SLOT) and
7564 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7565 the DFA state after issuing these instructions.
7567 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7568 of the unused instructions. Return true if one such permutation gives
7569 a valid ordering, leaving the successful permutation in sorted[].
7570 Do not modify sorted[] until a valid permutation is found. */
7573 frv_sort_insn_group_1 (enum frv_insn_group group,
7574 unsigned int lower_slot, unsigned int upper_slot,
7575 unsigned int issued, unsigned int num_insns,
7578 struct frv_packet_group *packet_group;
7584 /* Early success if we've filled all the slots. */
7585 if (lower_slot == upper_slot)
7588 packet_group = &frv_packet.groups[group];
7589 dfa_size = state_size ();
7590 test_state = alloca (dfa_size);
7592 /* Try issuing each unused instruction. */
7593 for (i = num_insns - 1; i + 1 != 0; i--)
7594 if (~issued & (1 << i))
7596 insn = packet_group->sorted[i];
7597 memcpy (test_state, state, dfa_size);
7598 if (state_transition (test_state, insn) < 0
7599 && cpu_unit_reservation_p (test_state,
7600 NTH_UNIT (group, upper_slot - 1))
7601 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7602 issued | (1 << i), num_insns,
7605 packet_group->sorted[upper_slot - 1] = insn;
7613 /* Compare two instructions by their frv_insn_unit. */
7616 frv_compare_insns (const void *first, const void *second)
7618 const rtx *const insn1 = (rtx const *) first,
7619 *const insn2 = (rtx const *) second;
7620 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7623 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7624 and sort it into assembly language order. See frv.md for a description of
7628 frv_sort_insn_group (enum frv_insn_group group)
7630 struct frv_packet_group *packet_group;
7631 unsigned int first, i, nop, max_unit, num_slots;
7632 state_t state, test_state;
7635 packet_group = &frv_packet.groups[group];
7637 /* Assume no nop is needed. */
7638 packet_group->nop = 0;
7640 if (packet_group->num_insns == 0)
7643 /* Copy insns[] to sorted[]. */
7644 memcpy (packet_group->sorted, packet_group->insns,
7645 sizeof (rtx) * packet_group->num_insns);
7647 /* Sort sorted[] by the unit that each insn tries to take first. */
7648 if (packet_group->num_insns > 1)
7649 qsort (packet_group->sorted, packet_group->num_insns,
7650 sizeof (rtx), frv_compare_insns);
7652 /* That's always enough for branch and control insns. */
7653 if (group == GROUP_B || group == GROUP_C)
7656 dfa_size = state_size ();
7657 state = alloca (dfa_size);
7658 test_state = alloca (dfa_size);
7660 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7661 consecutively and such that the DFA takes unit X when sorted[X]
7662 is added. Set STATE to the new DFA state. */
7663 state_reset (test_state);
7664 for (first = 0; first < packet_group->num_insns; first++)
7666 memcpy (state, test_state, dfa_size);
7667 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7668 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7672 /* If all the instructions issued in ascending order, we're done. */
7673 if (first == packet_group->num_insns)
7676 /* Add nops to the end of sorted[] and try each permutation until
7677 we find one that works. */
7678 for (nop = 0; nop < frv_num_nops; nop++)
7680 max_unit = frv_insn_unit (frv_nops[nop]);
7681 if (frv_unit_groups[max_unit] == group)
7683 packet_group->nop = frv_nops[nop];
7684 num_slots = UNIT_NUMBER (max_unit) + 1;
7685 for (i = packet_group->num_insns; i < num_slots; i++)
7686 packet_group->sorted[i] = frv_nops[nop];
7687 if (frv_sort_insn_group_1 (group, first, num_slots,
7688 (1 << first) - 1, num_slots, state))
7695 /* Sort the current packet into assembly-language order. Set packing
7696 flags as appropriate. */
7699 frv_reorder_packet (void)
7701 unsigned int cursor[NUM_GROUPS];
7702 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7703 unsigned int unit, to, from;
7704 enum frv_insn_group group;
7705 struct frv_packet_group *packet_group;
7707 /* First sort each group individually. */
7708 for (group = 0; group < NUM_GROUPS; group++)
7711 frv_sort_insn_group (group);
7714 /* Go through the unit template and try add an instruction from
7715 that unit's group. */
7717 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7719 group = frv_unit_groups[unit];
7720 packet_group = &frv_packet.groups[group];
7721 if (cursor[group] < packet_group->num_insns)
7723 /* frv_reorg should have added nops for us. */
7724 gcc_assert (packet_group->sorted[cursor[group]]
7725 != packet_group->nop);
7726 insns[to++] = packet_group->sorted[cursor[group]++];
7730 gcc_assert (to == frv_packet.num_insns);
7732 /* Clear the last instruction's packing flag, thus marking the end of
7733 a packet. Reorder the other instructions relative to it. */
7734 CLEAR_PACKING_FLAG (insns[to - 1]);
7735 for (from = 0; from < to - 1; from++)
7737 remove_insn (insns[from]);
7738 add_insn_before (insns[from], insns[to - 1], NULL);
7739 SET_PACKING_FLAG (insns[from]);
7744 /* Divide instructions into packets. Reorder the contents of each
7745 packet so that they are in the correct assembly-language order.
7747 Since this pass can change the raw meaning of the rtl stream, it must
7748 only be called at the last minute, just before the instructions are
7752 frv_pack_insns (void)
7754 if (frv_for_each_packet (frv_reorder_packet))
7755 frv_insn_packing_flag = 0;
7757 frv_insn_packing_flag = -1;
7760 /* See whether we need to add nops to group GROUP in order to
7761 make a valid packet. */
7764 frv_fill_unused_units (enum frv_insn_group group)
7766 unsigned int non_nops, nops, i;
7767 struct frv_packet_group *packet_group;
7769 packet_group = &frv_packet.groups[group];
7771 /* Sort the instructions into assembly-language order.
7772 Use nops to fill slots that are otherwise unused. */
7773 frv_sort_insn_group (group);
7775 /* See how many nops are needed before the final useful instruction. */
7777 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7778 while (packet_group->sorted[i++] == packet_group->nop)
7781 /* Insert that many nops into the instruction stream. */
7783 frv_insert_nop_in_packet (packet_group->nop);
7786 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7789 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7791 if (io1->const_address != 0 && io2->const_address != 0)
7792 return io1->const_address == io2->const_address;
7794 if (io1->var_address != 0 && io2->var_address != 0)
7795 return rtx_equal_p (io1->var_address, io2->var_address);
7800 /* Return true if operations IO1 and IO2 are guaranteed to complete
7804 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7806 /* The order of writes is always preserved. */
7807 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7810 /* The order of reads isn't preserved. */
7811 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7814 /* One operation is a write and the other is (or could be) a read.
7815 The order is only guaranteed if the accesses are to the same
7817 return frv_same_doubleword_p (io1, io2);
7820 /* Generalize I/O operation X so that it covers both X and Y. */
7823 frv_io_union (struct frv_io *x, const struct frv_io *y)
7825 if (x->type != y->type)
7826 x->type = FRV_IO_UNKNOWN;
7827 if (!frv_same_doubleword_p (x, y))
7829 x->const_address = 0;
7834 /* Fill IO with information about the load or store associated with
7835 membar instruction INSN. */
7838 frv_extract_membar (struct frv_io *io, rtx insn)
7840 extract_insn (insn);
7841 io->type = INTVAL (recog_data.operand[2]);
7842 io->const_address = INTVAL (recog_data.operand[1]);
7843 io->var_address = XEXP (recog_data.operand[0], 0);
7846 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7847 if X is a register and *DATA depends on X. */
7850 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7852 rtx *other = (rtx *) data;
7854 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7858 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7859 Remove every modified register from the set. */
7862 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7864 HARD_REG_SET *set = (HARD_REG_SET *) data;
7868 FOR_EACH_REGNO (regno, x)
7869 CLEAR_HARD_REG_BIT (*set, regno);
7872 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7873 Add every register in *X to the set. */
7876 frv_io_handle_use_1 (rtx *x, void *data)
7878 HARD_REG_SET *set = (HARD_REG_SET *) data;
7882 FOR_EACH_REGNO (regno, *x)
7883 SET_HARD_REG_BIT (*set, regno);
7888 /* A note_stores callback that applies frv_io_handle_use_1 to an
7889 entire rhs value. */
7892 frv_io_handle_use (rtx *x, void *data)
7894 for_each_rtx (x, frv_io_handle_use_1, data);
7897 /* Go through block BB looking for membars to remove. There are two
7898 cases where intra-block analysis is enough:
7900 - a membar is redundant if it occurs between two consecutive I/O
7901 operations and if those operations are guaranteed to complete
7904 - a membar for a __builtin_read is redundant if the result is
7905 used before the next I/O operation is issued.
7907 If the last membar in the block could not be removed, and there
7908 are guaranteed to be no I/O operations between that membar and
7909 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7912 Describe the block's first I/O operation in *NEXT_IO. Describe
7913 an unknown operation if the block doesn't do any I/O. */
7916 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7919 HARD_REG_SET used_regs;
7920 rtx next_membar, set, insn;
7923 /* NEXT_IO is the next I/O operation to be performed after the current
7924 instruction. It starts off as being an unknown operation. */
7925 memset (next_io, 0, sizeof (*next_io));
7927 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7928 next_is_end_p = true;
7930 /* If the current instruction is a __builtin_read or __builtin_write,
7931 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7932 is null if the membar has already been deleted.
7934 Note that the initialization here should only be needed to
7935 suppress warnings. */
7938 /* USED_REGS is the set of registers that are used before the
7939 next I/O instruction. */
7940 CLEAR_HARD_REG_SET (used_regs);
7942 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7943 if (GET_CODE (insn) == CALL_INSN)
7945 /* We can't predict what a call will do to volatile memory. */
7946 memset (next_io, 0, sizeof (struct frv_io));
7947 next_is_end_p = false;
7948 CLEAR_HARD_REG_SET (used_regs);
7950 else if (INSN_P (insn))
7951 switch (recog_memoized (insn))
7953 case CODE_FOR_optional_membar_qi:
7954 case CODE_FOR_optional_membar_hi:
7955 case CODE_FOR_optional_membar_si:
7956 case CODE_FOR_optional_membar_di:
7960 /* Local information isn't enough to decide whether this
7961 membar is needed. Stash it away for later. */
7962 *last_membar = insn;
7963 frv_extract_membar (next_io, insn);
7964 next_is_end_p = false;
7968 /* Check whether the I/O operation before INSN could be
7969 reordered with one described by NEXT_IO. If it can't,
7970 INSN will not be needed. */
7971 struct frv_io prev_io;
7973 frv_extract_membar (&prev_io, insn);
7974 if (frv_io_fixed_order_p (&prev_io, next_io))
7978 ";; [Local] Removing membar %d since order"
7979 " of accesses is guaranteed\n",
7980 INSN_UID (next_membar));
7982 insn = NEXT_INSN (insn);
7983 delete_insn (next_membar);
7991 /* Invalidate NEXT_IO's address if it depends on something that
7992 is clobbered by INSN. */
7993 if (next_io->var_address)
7994 note_stores (PATTERN (insn), frv_io_check_address,
7995 &next_io->var_address);
7997 /* If the next membar is associated with a __builtin_read,
7998 see if INSN reads from that address. If it does, and if
7999 the destination register is used before the next I/O access,
8000 there is no need for the membar. */
8001 set = PATTERN (insn);
8002 if (next_io->type == FRV_IO_READ
8003 && next_io->var_address != 0
8005 && GET_CODE (set) == SET
8006 && GET_CODE (SET_DEST (set)) == REG
8007 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8011 src = SET_SRC (set);
8012 if (GET_CODE (src) == ZERO_EXTEND)
8013 src = XEXP (src, 0);
8015 if (GET_CODE (src) == MEM
8016 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8020 ";; [Local] Removing membar %d since the target"
8021 " of %d is used before the I/O operation\n",
8022 INSN_UID (next_membar), INSN_UID (insn));
8024 if (next_membar == *last_membar)
8027 delete_insn (next_membar);
8032 /* If INSN has volatile references, forget about any registers
8033 that are used after it. Otherwise forget about uses that
8034 are (or might be) defined by INSN. */
8035 if (volatile_refs_p (PATTERN (insn)))
8036 CLEAR_HARD_REG_SET (used_regs);
8038 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8040 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8045 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8046 FIRST_IO[X] describes the first operation performed by basic block X. */
8049 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8052 struct frv_io this_io, next_io;
8056 /* We need to keep the membar if there is an edge to the exit block. */
8057 FOR_EACH_EDGE (succ, ei, bb->succs)
8058 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8059 if (succ->dest == EXIT_BLOCK_PTR)
8062 /* Work out the union of all successor blocks. */
8063 ei = ei_start (bb->succs);
8064 ei_cond (ei, &succ);
8065 /* next_io = first_io[bb->succ->dest->index]; */
8066 next_io = first_io[succ->dest->index];
8067 ei = ei_start (bb->succs);
8068 if (ei_cond (ei, &succ))
8070 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8071 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8072 frv_io_union (&next_io, &first_io[succ->dest->index]);
8077 frv_extract_membar (&this_io, membar);
8078 if (frv_io_fixed_order_p (&this_io, &next_io))
8082 ";; [Global] Removing membar %d since order of accesses"
8083 " is guaranteed\n", INSN_UID (membar));
8085 delete_insn (membar);
8089 /* Remove redundant membars from the current function. */
8092 frv_optimize_membar (void)
8095 struct frv_io *first_io;
8098 compute_bb_for_insn ();
8099 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8100 last_membar = XCNEWVEC (rtx, last_basic_block);
8103 frv_optimize_membar_local (bb, &first_io[bb->index],
8104 &last_membar[bb->index]);
8107 if (last_membar[bb->index] != 0)
8108 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8114 /* Used by frv_reorg to keep track of the current packet's address. */
8115 static unsigned int frv_packet_address;
8117 /* If the current packet falls through to a label, try to pad the packet
8118 with nops in order to fit the label's alignment requirements. */
8121 frv_align_label (void)
8123 unsigned int alignment, target, nop;
8124 rtx x, last, barrier, label;
8126 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8127 maximum alignment of that packet, LABEL to the last label between
8128 the packets, and BARRIER to the last barrier. */
8129 last = frv_packet.insns[frv_packet.num_insns - 1];
8130 label = barrier = 0;
8132 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8136 unsigned int subalign = 1 << label_to_alignment (x);
8137 alignment = MAX (alignment, subalign);
8144 /* If -malign-labels, and the packet falls through to an unaligned
8145 label, try introducing a nop to align that label to 8 bytes. */
8146 if (TARGET_ALIGN_LABELS
8149 && frv_packet.num_insns < frv_packet.issue_rate)
8150 alignment = MAX (alignment, 8);
8152 /* Advance the address to the end of the current packet. */
8153 frv_packet_address += frv_packet.num_insns * 4;
8155 /* Work out the target address, after alignment. */
8156 target = (frv_packet_address + alignment - 1) & -alignment;
8158 /* If the packet falls through to the label, try to find an efficient
8159 padding sequence. */
8162 /* First try adding nops to the current packet. */
8163 for (nop = 0; nop < frv_num_nops; nop++)
8164 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8166 frv_insert_nop_in_packet (frv_nops[nop]);
8167 frv_packet_address += 4;
8170 /* If we still haven't reached the target, add some new packets that
8171 contain only nops. If there are two types of nop, insert an
8172 alternating sequence of frv_nops[0] and frv_nops[1], which will
8173 lead to packets like:
8180 etc. Just emit frv_nops[0] if that's the only nop we have. */
8181 last = frv_packet.insns[frv_packet.num_insns - 1];
8183 while (frv_packet_address < target)
8185 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8186 frv_packet_address += 4;
8187 if (frv_num_nops > 1)
8192 frv_packet_address = target;
8195 /* Subroutine of frv_reorg, called after each packet has been constructed
8199 frv_reorg_packet (void)
8201 frv_fill_unused_units (GROUP_I);
8202 frv_fill_unused_units (GROUP_FM);
8206 /* Add an instruction with pattern NOP to frv_nops[]. */
8209 frv_register_nop (rtx nop)
8211 nop = make_insn_raw (nop);
8212 NEXT_INSN (nop) = 0;
8213 PREV_INSN (nop) = 0;
8214 frv_nops[frv_num_nops++] = nop;
8217 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8218 into packets and check whether we need to insert nops in order to
8219 fulfill the processor's issue requirements. Also, if the user has
8220 requested a certain alignment for a label, try to meet that alignment
8221 by inserting nops in the previous packet. */
8226 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8227 frv_optimize_membar ();
8230 frv_register_nop (gen_nop ());
8232 frv_register_nop (gen_mnop ());
8233 if (TARGET_HARD_FLOAT)
8234 frv_register_nop (gen_fnop ());
8236 /* Estimate the length of each branch. Although this may change after
8237 we've inserted nops, it will only do so in big functions. */
8238 shorten_branches (get_insns ());
8240 frv_packet_address = 0;
8241 frv_for_each_packet (frv_reorg_packet);
8244 #define def_builtin(name, type, code) \
8245 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8247 struct builtin_description
8249 enum insn_code icode;
8251 enum frv_builtins code;
8252 enum rtx_code comparison;
8256 /* Media intrinsics that take a single, constant argument. */
8258 static struct builtin_description bdesc_set[] =
8260 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8263 /* Media intrinsics that take just one argument. */
8265 static struct builtin_description bdesc_1arg[] =
8267 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8268 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8269 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8270 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8271 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8272 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8275 /* Media intrinsics that take two arguments. */
8277 static struct builtin_description bdesc_2arg[] =
8279 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8280 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8281 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8282 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8283 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8284 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8285 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8286 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8287 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8288 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8289 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8290 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8291 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8292 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8293 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8294 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8295 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8296 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8297 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8298 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8299 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8300 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8301 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8302 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8303 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8304 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8305 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8308 /* Integer intrinsics that take two arguments and have no return value. */
8310 static struct builtin_description bdesc_int_void2arg[] =
8312 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8313 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8314 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8317 static struct builtin_description bdesc_prefetches[] =
8319 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8320 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8323 /* Media intrinsics that take two arguments, the first being an ACC number. */
8325 static struct builtin_description bdesc_cut[] =
8327 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8328 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8329 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8332 /* Two-argument media intrinsics with an immediate second argument. */
8334 static struct builtin_description bdesc_2argimm[] =
8336 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8337 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8338 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8339 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8340 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8341 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8342 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8343 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8344 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8345 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8346 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8347 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8348 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8349 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8350 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8351 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8352 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8355 /* Media intrinsics that take two arguments and return void, the first argument
8356 being a pointer to 4 words in memory. */
8358 static struct builtin_description bdesc_void2arg[] =
8360 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8361 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8364 /* Media intrinsics that take three arguments, the first being a const_int that
8365 denotes an accumulator, and that return void. */
8367 static struct builtin_description bdesc_void3arg[] =
8369 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8370 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8371 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8372 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8373 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8374 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8375 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8376 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8377 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8378 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8379 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8380 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8381 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8382 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8383 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8384 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8385 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8386 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8387 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8388 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8389 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8390 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8391 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8392 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8393 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8396 /* Media intrinsics that take two accumulator numbers as argument and
8399 static struct builtin_description bdesc_voidacc[] =
8401 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8402 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8403 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8404 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8405 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8406 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8409 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8410 a normal move and the ICODE is for the membar. */
8412 static struct builtin_description bdesc_loads[] =
8414 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8415 FRV_BUILTIN_READ8, 0, 0 },
8416 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8417 FRV_BUILTIN_READ16, 0, 0 },
8418 { CODE_FOR_optional_membar_si, "__builtin_read32",
8419 FRV_BUILTIN_READ32, 0, 0 },
8420 { CODE_FOR_optional_membar_di, "__builtin_read64",
8421 FRV_BUILTIN_READ64, 0, 0 }
8424 /* Likewise stores. */
8426 static struct builtin_description bdesc_stores[] =
8428 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8429 FRV_BUILTIN_WRITE8, 0, 0 },
8430 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8431 FRV_BUILTIN_WRITE16, 0, 0 },
8432 { CODE_FOR_optional_membar_si, "__builtin_write32",
8433 FRV_BUILTIN_WRITE32, 0, 0 },
8434 { CODE_FOR_optional_membar_di, "__builtin_write64",
8435 FRV_BUILTIN_WRITE64, 0, 0 },
8438 /* Initialize media builtins. */
8441 frv_init_builtins (void)
8443 tree endlink = void_list_node;
8444 tree accumulator = integer_type_node;
8445 tree integer = integer_type_node;
8446 tree voidt = void_type_node;
8447 tree uhalf = short_unsigned_type_node;
8448 tree sword1 = long_integer_type_node;
8449 tree uword1 = long_unsigned_type_node;
8450 tree sword2 = long_long_integer_type_node;
8451 tree uword2 = long_long_unsigned_type_node;
8452 tree uword4 = build_pointer_type (uword1);
8453 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8454 tree ubyte = unsigned_char_type_node;
8455 tree iacc = integer_type_node;
8457 #define UNARY(RET, T1) \
8458 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8460 #define BINARY(RET, T1, T2) \
8461 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8462 tree_cons (NULL_TREE, T2, endlink)))
8464 #define TRINARY(RET, T1, T2, T3) \
8465 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8466 tree_cons (NULL_TREE, T2, \
8467 tree_cons (NULL_TREE, T3, endlink))))
8469 #define QUAD(RET, T1, T2, T3, T4) \
8470 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8471 tree_cons (NULL_TREE, T2, \
8472 tree_cons (NULL_TREE, T3, \
8473 tree_cons (NULL_TREE, T4, endlink)))))
8475 tree void_ftype_void = build_function_type (voidt, endlink);
8477 tree void_ftype_acc = UNARY (voidt, accumulator);
8478 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8479 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8480 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8481 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8482 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8483 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8484 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8485 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8487 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8488 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8489 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8490 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8491 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8492 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8493 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8494 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8495 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8496 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8497 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8499 tree sw1_ftype_int = UNARY (sword1, integer);
8500 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8501 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8503 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8504 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8505 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8506 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8507 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8508 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8510 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8511 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8512 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8513 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8514 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8515 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8516 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8517 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8518 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8519 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8520 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8521 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8522 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8523 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8524 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8525 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8526 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8528 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8529 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8530 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8531 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8532 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8533 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8534 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8535 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8536 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8537 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8538 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8539 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8540 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8541 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8542 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8543 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8544 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8545 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8546 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8547 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8548 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8549 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8550 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8551 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8552 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8553 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8554 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8555 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8556 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8557 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8558 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8559 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8560 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8561 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8562 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8563 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8564 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8565 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8566 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8567 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8568 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8569 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8570 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8571 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8572 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8573 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8574 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8575 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8576 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8577 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8578 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8579 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8580 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8581 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8582 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8583 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8584 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8585 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8586 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8587 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8588 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8589 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8590 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8591 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8592 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8593 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8594 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8595 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8596 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8597 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8598 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8599 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8600 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8601 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8602 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8603 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8604 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8605 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8606 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8607 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8608 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8609 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8610 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8611 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8612 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8613 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8614 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8615 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8616 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8617 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8618 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8619 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8620 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8621 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8622 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8623 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8624 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8625 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8626 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8627 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8628 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8629 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8630 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8631 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8632 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8633 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8634 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8635 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8637 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8638 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8639 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8640 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8648 /* Set the names for various arithmetic operations according to the
8651 frv_init_libfuncs (void)
8653 set_optab_libfunc (smod_optab, SImode, "__modi");
8654 set_optab_libfunc (umod_optab, SImode, "__umodi");
8656 set_optab_libfunc (add_optab, DImode, "__addll");
8657 set_optab_libfunc (sub_optab, DImode, "__subll");
8658 set_optab_libfunc (smul_optab, DImode, "__mulll");
8659 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8660 set_optab_libfunc (smod_optab, DImode, "__modll");
8661 set_optab_libfunc (umod_optab, DImode, "__umodll");
8662 set_optab_libfunc (and_optab, DImode, "__andll");
8663 set_optab_libfunc (ior_optab, DImode, "__orll");
8664 set_optab_libfunc (xor_optab, DImode, "__xorll");
8665 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8667 set_optab_libfunc (add_optab, SFmode, "__addf");
8668 set_optab_libfunc (sub_optab, SFmode, "__subf");
8669 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8670 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8672 set_optab_libfunc (add_optab, DFmode, "__addd");
8673 set_optab_libfunc (sub_optab, DFmode, "__subd");
8674 set_optab_libfunc (smul_optab, DFmode, "__muld");
8675 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8677 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8678 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8680 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8681 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8682 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8683 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8685 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8686 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8687 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8688 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8690 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8691 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8692 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8693 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8696 /* Convert an integer constant to an accumulator register. ICODE is the
8697 code of the target instruction, OPNUM is the number of the
8698 accumulator operand and OPVAL is the constant integer. Try both
8699 ACC and ACCG registers; only report an error if neither fit the
8703 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8708 /* ACCs and ACCGs are implicit global registers if media intrinsics
8709 are being used. We set up this lazily to avoid creating lots of
8710 unnecessary call_insn rtl in non-media code. */
8711 for (i = 0; i <= ACC_MASK; i++)
8712 if ((i & ACC_MASK) == i)
8713 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8715 if (GET_CODE (opval) != CONST_INT)
8717 error ("accumulator is not a constant integer");
8720 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8722 error ("accumulator number is out of bounds");
8726 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8727 ACC_FIRST + INTVAL (opval));
8728 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8729 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8731 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8733 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8739 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8742 static enum machine_mode
8743 frv_matching_accg_mode (enum machine_mode mode)
8761 /* Given that a __builtin_read or __builtin_write function is accessing
8762 address ADDRESS, return the value that should be used as operand 1
8766 frv_io_address_cookie (rtx address)
8768 return (GET_CODE (address) == CONST_INT
8769 ? GEN_INT (INTVAL (address) / 8 * 8)
8773 /* Return the accumulator guard that should be paired with accumulator
8774 register ACC. The mode of the returned register is in the same
8775 class as ACC, but is four times smaller. */
8778 frv_matching_accg_for_acc (rtx acc)
8780 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8781 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8784 /* Read the requested argument from the call EXP given by INDEX.
8785 Return the value as an rtx. */
8788 frv_read_argument (tree exp, unsigned int index)
8790 return expand_expr (CALL_EXPR_ARG (exp, index),
8791 NULL_RTX, VOIDmode, 0);
8794 /* Like frv_read_argument, but interpret the argument as the number
8795 of an IACC register and return a (reg:MODE ...) rtx for it. */
8798 frv_read_iacc_argument (enum machine_mode mode, tree call,
8804 op = frv_read_argument (call, index);
8805 if (GET_CODE (op) != CONST_INT
8807 || INTVAL (op) > IACC_LAST - IACC_FIRST
8808 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8810 error ("invalid IACC argument");
8814 /* IACCs are implicit global registers. We set up this lazily to
8815 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8817 regno = INTVAL (op) + IACC_FIRST;
8818 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8819 global_regs[regno + i] = 1;
8821 return gen_rtx_REG (mode, regno);
8824 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8825 The instruction should require a constant operand of some sort. The
8826 function prints an error if OPVAL is not valid. */
8829 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8831 if (GET_CODE (opval) != CONST_INT)
8833 error ("%qs expects a constant argument", insn_data[icode].name);
8836 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8838 error ("constant argument out of range for %qs", insn_data[icode].name);
8844 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8845 if it's not null, has the right mode, and satisfies operand 0's
8849 frv_legitimize_target (enum insn_code icode, rtx target)
8851 enum machine_mode mode = insn_data[icode].operand[0].mode;
8854 || GET_MODE (target) != mode
8855 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8856 return gen_reg_rtx (mode);
8861 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8862 check whether ARG satisfies the operand's constraints. If it doesn't,
8863 copy ARG to a temporary register and return that. Otherwise return ARG
8867 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8869 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8871 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8874 return copy_to_mode_reg (mode, arg);
8877 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8880 frv_volatile_memref (enum machine_mode mode, rtx arg)
8884 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8885 MEM_VOLATILE_P (mem) = 1;
8889 /* Expand builtins that take a single, constant argument. At the moment,
8890 only MHDSETS falls into this category. */
8893 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8896 rtx op0 = frv_read_argument (call, 0);
8898 if (! frv_check_constant_argument (icode, 1, op0))
8901 target = frv_legitimize_target (icode, target);
8902 pat = GEN_FCN (icode) (target, op0);
8910 /* Expand builtins that take one operand. */
8913 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8916 rtx op0 = frv_read_argument (call, 0);
8918 target = frv_legitimize_target (icode, target);
8919 op0 = frv_legitimize_argument (icode, 1, op0);
8920 pat = GEN_FCN (icode) (target, op0);
8928 /* Expand builtins that take two operands. */
8931 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8934 rtx op0 = frv_read_argument (call, 0);
8935 rtx op1 = frv_read_argument (call, 1);
8937 target = frv_legitimize_target (icode, target);
8938 op0 = frv_legitimize_argument (icode, 1, op0);
8939 op1 = frv_legitimize_argument (icode, 2, op1);
8940 pat = GEN_FCN (icode) (target, op0, op1);
8948 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8952 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8955 rtx op0 = frv_read_argument (call, 0);
8956 rtx op1 = frv_read_argument (call, 1);
8959 target = frv_legitimize_target (icode, target);
8960 op0 = frv_int_to_acc (icode, 1, op0);
8964 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8966 if (! frv_check_constant_argument (icode, 2, op1))
8970 op1 = frv_legitimize_argument (icode, 2, op1);
8972 op2 = frv_matching_accg_for_acc (op0);
8973 pat = GEN_FCN (icode) (target, op0, op1, op2);
8981 /* Expand builtins that take two operands and the second is immediate. */
8984 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8987 rtx op0 = frv_read_argument (call, 0);
8988 rtx op1 = frv_read_argument (call, 1);
8990 if (! frv_check_constant_argument (icode, 2, op1))
8993 target = frv_legitimize_target (icode, target);
8994 op0 = frv_legitimize_argument (icode, 1, op0);
8995 pat = GEN_FCN (icode) (target, op0, op1);
9003 /* Expand builtins that take two operands, the first operand being a pointer to
9004 ints and return void. */
9007 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9010 rtx op0 = frv_read_argument (call, 0);
9011 rtx op1 = frv_read_argument (call, 1);
9012 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9015 if (GET_CODE (op0) != MEM)
9019 if (! offsettable_address_p (0, mode0, op0))
9021 reg = gen_reg_rtx (Pmode);
9022 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9025 op0 = gen_rtx_MEM (SImode, reg);
9028 addr = XEXP (op0, 0);
9029 if (! offsettable_address_p (0, mode0, addr))
9030 addr = copy_to_mode_reg (Pmode, op0);
9032 op0 = change_address (op0, V4SImode, addr);
9033 op1 = frv_legitimize_argument (icode, 1, op1);
9034 pat = GEN_FCN (icode) (op0, op1);
9042 /* Expand builtins that take two long operands and return void. */
9045 frv_expand_int_void2arg (enum insn_code icode, tree call)
9048 rtx op0 = frv_read_argument (call, 0);
9049 rtx op1 = frv_read_argument (call, 1);
9051 op0 = frv_legitimize_argument (icode, 1, op0);
9052 op1 = frv_legitimize_argument (icode, 1, op1);
9053 pat = GEN_FCN (icode) (op0, op1);
9061 /* Expand prefetch builtins. These take a single address as argument. */
9064 frv_expand_prefetches (enum insn_code icode, tree call)
9067 rtx op0 = frv_read_argument (call, 0);
9069 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9077 /* Expand builtins that take three operands and return void. The first
9078 argument must be a constant that describes a pair or quad accumulators. A
9079 fourth argument is created that is the accumulator guard register that
9080 corresponds to the accumulator. */
9083 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9086 rtx op0 = frv_read_argument (call, 0);
9087 rtx op1 = frv_read_argument (call, 1);
9088 rtx op2 = frv_read_argument (call, 2);
9091 op0 = frv_int_to_acc (icode, 0, op0);
9095 op1 = frv_legitimize_argument (icode, 1, op1);
9096 op2 = frv_legitimize_argument (icode, 2, op2);
9097 op3 = frv_matching_accg_for_acc (op0);
9098 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9106 /* Expand builtins that perform accumulator-to-accumulator operations.
9107 These builtins take two accumulator numbers as argument and return
9111 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9114 rtx op0 = frv_read_argument (call, 0);
9115 rtx op1 = frv_read_argument (call, 1);
9119 op0 = frv_int_to_acc (icode, 0, op0);
9123 op1 = frv_int_to_acc (icode, 1, op1);
9127 op2 = frv_matching_accg_for_acc (op0);
9128 op3 = frv_matching_accg_for_acc (op1);
9129 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9137 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9138 membar and TARGET_MODE is the mode that the loaded value should have. */
9141 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9142 tree call, rtx target)
9144 rtx op0 = frv_read_argument (call, 0);
9145 rtx cookie = frv_io_address_cookie (op0);
9147 if (target == 0 || !REG_P (target))
9148 target = gen_reg_rtx (target_mode);
9149 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9150 convert_move (target, op0, 1);
9151 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9152 cfun->machine->has_membar_p = 1;
9156 /* Likewise __builtin_write* functions. */
9159 frv_expand_store_builtin (enum insn_code icode, tree call)
9161 rtx op0 = frv_read_argument (call, 0);
9162 rtx op1 = frv_read_argument (call, 1);
9163 rtx cookie = frv_io_address_cookie (op0);
9165 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9166 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9167 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9168 cfun->machine->has_membar_p = 1;
9172 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9173 each argument forms one word of the two double-word input registers.
9174 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9175 to put the return value. */
9178 frv_expand_mdpackh_builtin (tree call, rtx target)
9180 enum insn_code icode = CODE_FOR_mdpackh;
9182 rtx arg1 = frv_read_argument (call, 0);
9183 rtx arg2 = frv_read_argument (call, 1);
9184 rtx arg3 = frv_read_argument (call, 2);
9185 rtx arg4 = frv_read_argument (call, 3);
9187 target = frv_legitimize_target (icode, target);
9188 op0 = gen_reg_rtx (DImode);
9189 op1 = gen_reg_rtx (DImode);
9191 /* The high half of each word is not explicitly initialized, so indicate
9192 that the input operands are not live before this point. */
9196 /* Move each argument into the low half of its associated input word. */
9197 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9198 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9199 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9200 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9202 pat = GEN_FCN (icode) (target, op0, op1);
9210 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9211 number as argument. */
9214 frv_expand_mclracc_builtin (tree call)
9216 enum insn_code icode = CODE_FOR_mclracc;
9218 rtx op0 = frv_read_argument (call, 0);
9220 op0 = frv_int_to_acc (icode, 0, op0);
9224 pat = GEN_FCN (icode) (op0);
9231 /* Expand builtins that take no arguments. */
9234 frv_expand_noargs_builtin (enum insn_code icode)
9236 rtx pat = GEN_FCN (icode) (const0_rtx);
9243 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9244 number or accumulator guard number as argument and return an SI integer. */
9247 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9250 rtx target = gen_reg_rtx (SImode);
9251 rtx op0 = frv_read_argument (call, 0);
9253 op0 = frv_int_to_acc (icode, 1, op0);
9257 pat = GEN_FCN (icode) (target, op0);
9265 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9266 accumulator guard as their first argument and an SImode value as their
9270 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9273 rtx op0 = frv_read_argument (call, 0);
9274 rtx op1 = frv_read_argument (call, 1);
9276 op0 = frv_int_to_acc (icode, 0, op0);
9280 op1 = frv_legitimize_argument (icode, 1, op1);
9281 pat = GEN_FCN (icode) (op0, op1);
9288 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9289 to move DImode values into and out of IACC0. */
9292 frv_split_iacc_move (rtx dest, rtx src)
9294 enum machine_mode inner;
9297 inner = GET_MODE (dest);
9298 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9299 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9300 simplify_gen_subreg (SImode, src, inner, i));
9303 /* Expand builtins. */
9306 frv_expand_builtin (tree exp,
9308 rtx subtarget ATTRIBUTE_UNUSED,
9309 enum machine_mode mode ATTRIBUTE_UNUSED,
9310 int ignore ATTRIBUTE_UNUSED)
9312 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9313 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9315 struct builtin_description *d;
9317 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9319 error ("media functions are not available unless -mmedia is used");
9325 case FRV_BUILTIN_MCOP1:
9326 case FRV_BUILTIN_MCOP2:
9327 case FRV_BUILTIN_MDUNPACKH:
9328 case FRV_BUILTIN_MBTOHE:
9329 if (! TARGET_MEDIA_REV1)
9331 error ("this media function is only available on the fr500");
9336 case FRV_BUILTIN_MQXMACHS:
9337 case FRV_BUILTIN_MQXMACXHS:
9338 case FRV_BUILTIN_MQMACXHS:
9339 case FRV_BUILTIN_MADDACCS:
9340 case FRV_BUILTIN_MSUBACCS:
9341 case FRV_BUILTIN_MASACCS:
9342 case FRV_BUILTIN_MDADDACCS:
9343 case FRV_BUILTIN_MDSUBACCS:
9344 case FRV_BUILTIN_MDASACCS:
9345 case FRV_BUILTIN_MABSHS:
9346 case FRV_BUILTIN_MDROTLI:
9347 case FRV_BUILTIN_MCPLHI:
9348 case FRV_BUILTIN_MCPLI:
9349 case FRV_BUILTIN_MDCUTSSI:
9350 case FRV_BUILTIN_MQSATHS:
9351 case FRV_BUILTIN_MHSETLOS:
9352 case FRV_BUILTIN_MHSETLOH:
9353 case FRV_BUILTIN_MHSETHIS:
9354 case FRV_BUILTIN_MHSETHIH:
9355 case FRV_BUILTIN_MHDSETS:
9356 case FRV_BUILTIN_MHDSETH:
9357 if (! TARGET_MEDIA_REV2)
9359 error ("this media function is only available on the fr400"
9365 case FRV_BUILTIN_SMASS:
9366 case FRV_BUILTIN_SMSSS:
9367 case FRV_BUILTIN_SMU:
9368 case FRV_BUILTIN_ADDSS:
9369 case FRV_BUILTIN_SUBSS:
9370 case FRV_BUILTIN_SLASS:
9371 case FRV_BUILTIN_SCUTSS:
9372 case FRV_BUILTIN_IACCreadll:
9373 case FRV_BUILTIN_IACCreadl:
9374 case FRV_BUILTIN_IACCsetll:
9375 case FRV_BUILTIN_IACCsetl:
9376 if (!TARGET_FR405_BUILTINS)
9378 error ("this builtin function is only available"
9379 " on the fr405 and fr450");
9384 case FRV_BUILTIN_PREFETCH:
9385 if (!TARGET_FR500_FR550_BUILTINS)
9387 error ("this builtin function is only available on the fr500"
9393 case FRV_BUILTIN_MQLCLRHS:
9394 case FRV_BUILTIN_MQLMTHS:
9395 case FRV_BUILTIN_MQSLLHI:
9396 case FRV_BUILTIN_MQSRAHI:
9397 if (!TARGET_MEDIA_FR450)
9399 error ("this builtin function is only available on the fr450");
9408 /* Expand unique builtins. */
9412 case FRV_BUILTIN_MTRAP:
9413 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9415 case FRV_BUILTIN_MCLRACC:
9416 return frv_expand_mclracc_builtin (exp);
9418 case FRV_BUILTIN_MCLRACCA:
9420 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9422 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9424 case FRV_BUILTIN_MRDACC:
9425 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9427 case FRV_BUILTIN_MRDACCG:
9428 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9430 case FRV_BUILTIN_MWTACC:
9431 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9433 case FRV_BUILTIN_MWTACCG:
9434 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9436 case FRV_BUILTIN_MDPACKH:
9437 return frv_expand_mdpackh_builtin (exp, target);
9439 case FRV_BUILTIN_IACCreadll:
9441 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9442 if (target == 0 || !REG_P (target))
9443 target = gen_reg_rtx (DImode);
9444 frv_split_iacc_move (target, src);
9448 case FRV_BUILTIN_IACCreadl:
9449 return frv_read_iacc_argument (SImode, exp, 0);
9451 case FRV_BUILTIN_IACCsetll:
9453 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9454 rtx src = frv_read_argument (exp, 1);
9455 frv_split_iacc_move (dest, force_reg (DImode, src));
9459 case FRV_BUILTIN_IACCsetl:
9461 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9462 rtx src = frv_read_argument (exp, 1);
9463 emit_move_insn (dest, force_reg (SImode, src));
9471 /* Expand groups of builtins. */
9473 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9474 if (d->code == fcode)
9475 return frv_expand_set_builtin (d->icode, exp, target);
9477 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9478 if (d->code == fcode)
9479 return frv_expand_unop_builtin (d->icode, exp, target);
9481 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9482 if (d->code == fcode)
9483 return frv_expand_binop_builtin (d->icode, exp, target);
9485 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9486 if (d->code == fcode)
9487 return frv_expand_cut_builtin (d->icode, exp, target);
9489 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9490 if (d->code == fcode)
9491 return frv_expand_binopimm_builtin (d->icode, exp, target);
9493 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9494 if (d->code == fcode)
9495 return frv_expand_voidbinop_builtin (d->icode, exp);
9497 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9498 if (d->code == fcode)
9499 return frv_expand_voidtriop_builtin (d->icode, exp);
9501 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9502 if (d->code == fcode)
9503 return frv_expand_voidaccop_builtin (d->icode, exp);
9505 for (i = 0, d = bdesc_int_void2arg;
9506 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9507 if (d->code == fcode)
9508 return frv_expand_int_void2arg (d->icode, exp);
9510 for (i = 0, d = bdesc_prefetches;
9511 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9512 if (d->code == fcode)
9513 return frv_expand_prefetches (d->icode, exp);
9515 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9516 if (d->code == fcode)
9517 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9520 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9521 if (d->code == fcode)
9522 return frv_expand_store_builtin (d->icode, exp);
9528 frv_in_small_data_p (const_tree decl)
9531 const_tree section_name;
9533 /* Don't apply the -G flag to internal compiler structures. We
9534 should leave such structures in the main data section, partly
9535 for efficiency and partly because the size of some of them
9536 (such as C++ typeinfos) is not known until later. */
9537 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9540 /* If we already know which section the decl should be in, see if
9541 it's a small data section. */
9542 section_name = DECL_SECTION_NAME (decl);
9545 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9546 if (frv_string_begins_with (section_name, ".sdata"))
9548 if (frv_string_begins_with (section_name, ".sbss"))
9553 size = int_size_in_bytes (TREE_TYPE (decl));
9554 if (size > 0 && size <= g_switch_value)
9561 frv_rtx_costs (rtx x,
9562 int code ATTRIBUTE_UNUSED,
9563 int outer_code ATTRIBUTE_UNUSED,
9565 bool speed ATTRIBUTE_UNUSED)
9567 if (outer_code == MEM)
9569 /* Don't differentiate between memory addresses. All the ones
9570 we accept have equal cost. */
9571 *total = COSTS_N_INSNS (0);
9578 /* Make 12-bit integers really cheap. */
9579 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9590 *total = COSTS_N_INSNS (2);
9604 if (GET_MODE (x) == SImode)
9605 *total = COSTS_N_INSNS (1);
9606 else if (GET_MODE (x) == DImode)
9607 *total = COSTS_N_INSNS (2);
9609 *total = COSTS_N_INSNS (3);
9613 if (GET_MODE (x) == SImode)
9614 *total = COSTS_N_INSNS (2);
9616 *total = COSTS_N_INSNS (6); /* guess */
9623 *total = COSTS_N_INSNS (18);
9627 *total = COSTS_N_INSNS (3);
9636 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9638 switch_to_section (ctors_section);
9639 assemble_align (POINTER_SIZE);
9642 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9647 assemble_integer_with_op ("\t.picptr\t", symbol);
9651 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9653 switch_to_section (dtors_section);
9654 assemble_align (POINTER_SIZE);
9657 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9662 assemble_integer_with_op ("\t.picptr\t", symbol);
9665 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9668 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9669 int incoming ATTRIBUTE_UNUSED)
9671 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9674 #define TLS_BIAS (2048 - 16)
9676 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9677 We need to emit DTP-relative relocations. */
9680 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9682 gcc_assert (size == 4);
9683 fputs ("\t.picptr\ttlsmoff(", file);
9684 /* We want the unbiased TLS offset, so add the bias to the
9685 expression, such that the implicit biasing cancels out. */
9686 output_addr_const (file, plus_constant (x, TLS_BIAS));