1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
48 #include "target-def.h"
49 #include "targhooks.h"
50 #include "integrate.h"
51 #include "langhooks.h"
55 #define FRV_INLINE inline
58 /* The maximum number of distinct NOP patterns. There are three:
59 nop, fnop and mnop. */
60 #define NUM_NOP_PATTERNS 3
62 /* Classification of instructions and units: integer, floating-point/media,
63 branch and control. */
64 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
66 /* The DFA names of the units, in packet order. */
67 static const char *const frv_unit_names[] =
77 /* The classification of each unit in frv_unit_names[]. */
78 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
88 /* Return the DFA unit code associated with the Nth unit of integer
89 or floating-point group GROUP, */
90 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
92 /* Return the number of integer or floating-point unit UNIT
93 (1 for I1, 2 for F2, etc.). */
94 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
96 /* The DFA unit number for each unit in frv_unit_names[]. */
97 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
99 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
100 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
101 no instruction of type T has been seen. */
102 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
104 /* An array of dummy nop INSNs, one for each type of nop that the
106 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
108 /* The number of nop instructions in frv_nops[]. */
109 static unsigned int frv_num_nops;
111 /* Information about one __builtin_read or __builtin_write access, or
112 the combination of several such accesses. The most general value
113 is all-zeros (an unknown access to an unknown address). */
115 /* The type of access. FRV_IO_UNKNOWN means the access can be either
116 a read or a write. */
117 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
119 /* The constant address being accessed, or zero if not known. */
120 HOST_WIDE_INT const_address;
122 /* The run-time address, as used in operand 0 of the membar pattern. */
126 /* Return true if instruction INSN should be packed with the following
128 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
130 /* Set the value of PACKING_FLAG_P(INSN). */
131 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
132 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
134 /* Loop with REG set to each hard register in rtx X. */
135 #define FOR_EACH_REGNO(REG, X) \
136 for (REG = REGNO (X); \
137 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
140 /* This structure contains machine specific function data. */
141 struct GTY(()) machine_function
143 /* True if we have created an rtx that relies on the stack frame. */
146 /* True if this function contains at least one __builtin_{read,write}*. */
150 /* Temporary register allocation support structure. */
151 typedef struct frv_tmp_reg_struct
153 HARD_REG_SET regs; /* possible registers to allocate */
154 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
158 /* Register state information for VLIW re-packing phase. */
159 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
160 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
161 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
162 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
164 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
166 typedef unsigned char regstate_t;
168 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
176 /* Information required by frv_frame_access. */
179 /* This field is FRV_LOAD if registers are to be loaded from the stack and
180 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
181 the move is being done by the prologue code while FRV_LOAD implies it
182 is being done by the epilogue. */
183 enum frv_stack_op op;
185 /* The base register to use when accessing the stack. This may be the
186 frame pointer, stack pointer, or a temporary. The choice of register
187 depends on which part of the frame is being accessed and how big the
191 /* The offset of BASE from the bottom of the current frame, in bytes. */
193 } frv_frame_accessor_t;
195 /* Conditional execution support gathered together in one structure. */
198 /* Linked list of insns to add if the conditional execution conversion was
199 successful. Each link points to an EXPR_LIST which points to the pattern
200 of the insn to add, and the insn to be inserted before. */
201 rtx added_insns_list;
203 /* Identify which registers are safe to allocate for if conversions to
204 conditional execution. We keep the last allocated register in the
205 register classes between COND_EXEC statements. This will mean we allocate
206 different registers for each different COND_EXEC group if we can. This
207 might allow the scheduler to intermix two different COND_EXEC sections. */
208 frv_tmp_reg_t tmp_reg;
210 /* For nested IFs, identify which CC registers are used outside of setting
211 via a compare isnsn, and using via a check insn. This will allow us to
212 know if we can rewrite the register to use a different register that will
213 be paired with the CR register controlling the nested IF-THEN blocks. */
214 HARD_REG_SET nested_cc_ok_rewrite;
216 /* Temporary registers allocated to hold constants during conditional
218 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
220 /* Current number of temp registers available. */
221 int cur_scratch_regs;
223 /* Number of nested conditional execution blocks. */
224 int num_nested_cond_exec;
226 /* Map of insns that set up constants in scratch registers. */
227 bitmap scratch_insns_bitmap;
229 /* Conditional execution test register (CC0..CC7). */
232 /* Conditional execution compare register that is paired with cr_reg, so that
233 nested compares can be done. The csubcc and caddcc instructions don't
234 have enough bits to specify both a CC register to be set and a CR register
235 to do the test on, so the same bit number is used for both. Needless to
236 say, this is rather inconvenient for GCC. */
239 /* Extra CR registers used for &&, ||. */
243 /* Previous CR used in nested if, to make sure we are dealing with the same
244 nested if as the previous statement. */
245 rtx last_nested_if_cr;
249 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
251 /* Map register number to smallest register class. */
252 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
254 /* Map class letter into register class. */
255 enum reg_class reg_class_from_letter[256];
257 /* Cached value of frv_stack_info. */
258 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
261 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
263 /* Forward references */
265 static bool frv_handle_option (size_t, const char *, int);
266 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
267 static int frv_default_flags_for_cpu (void);
268 static int frv_string_begins_with (const_tree, const char *);
269 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
270 static void frv_print_operand_memory_reference_reg
272 static void frv_print_operand_memory_reference (FILE *, rtx, int);
273 static int frv_print_operand_jump_hint (rtx);
274 static const char *comparison_string (enum rtx_code, rtx);
275 static rtx frv_function_value (const_tree, const_tree,
277 static rtx frv_libcall_value (enum machine_mode,
279 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
280 static rtx single_set_pattern (rtx);
281 static int frv_function_contains_far_jump (void);
282 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
286 static rtx frv_frame_offset_rtx (int);
287 static rtx frv_frame_mem (enum machine_mode, rtx, int);
288 static rtx frv_dwarf_store (rtx, int);
289 static void frv_frame_insn (rtx, rtx);
290 static void frv_frame_access (frv_frame_accessor_t*,
292 static void frv_frame_access_multi (frv_frame_accessor_t*,
294 static void frv_frame_access_standard_regs (enum frv_stack_op,
296 static struct machine_function *frv_init_machine_status (void);
297 static rtx frv_int_to_acc (enum insn_code, int, rtx);
298 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
299 static rtx frv_read_argument (tree, unsigned int);
300 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
301 static int frv_check_constant_argument (enum insn_code, int, rtx);
302 static rtx frv_legitimize_target (enum insn_code, rtx);
303 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
304 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
305 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
306 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
309 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
312 static rtx frv_expand_int_void2arg (enum insn_code, tree);
313 static rtx frv_expand_prefetches (enum insn_code, tree);
314 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
315 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
316 static rtx frv_expand_mclracc_builtin (tree);
317 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
318 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
319 static rtx frv_expand_noargs_builtin (enum insn_code);
320 static void frv_split_iacc_move (rtx, rtx);
321 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
322 static int frv_clear_registers_used (rtx *, void *);
323 static void frv_ifcvt_add_insn (rtx, rtx, int);
324 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
325 static rtx frv_ifcvt_load_value (rtx, rtx);
326 static int frv_acc_group_1 (rtx *, void *);
327 static unsigned int frv_insn_unit (rtx);
328 static bool frv_issues_to_branch_unit_p (rtx);
329 static int frv_cond_flags (rtx);
330 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
331 static int frv_registers_conflict_p_1 (rtx *, void *);
332 static bool frv_registers_conflict_p (rtx);
333 static void frv_registers_update_1 (rtx, const_rtx, void *);
334 static void frv_registers_update (rtx);
335 static void frv_start_packet (void);
336 static void frv_start_packet_block (void);
337 static void frv_finish_packet (void (*) (void));
338 static bool frv_pack_insn_p (rtx);
339 static void frv_add_insn_to_packet (rtx);
340 static void frv_insert_nop_in_packet (rtx);
341 static bool frv_for_each_packet (void (*) (void));
342 static bool frv_sort_insn_group_1 (enum frv_insn_group,
343 unsigned int, unsigned int,
344 unsigned int, unsigned int,
346 static int frv_compare_insns (const void *, const void *);
347 static void frv_sort_insn_group (enum frv_insn_group);
348 static void frv_reorder_packet (void);
349 static void frv_fill_unused_units (enum frv_insn_group);
350 static void frv_align_label (void);
351 static void frv_reorg_packet (void);
352 static void frv_register_nop (rtx);
353 static void frv_reorg (void);
354 static void frv_pack_insns (void);
355 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
356 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
357 static bool frv_assemble_integer (rtx, unsigned, int);
358 static void frv_init_builtins (void);
359 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
360 static void frv_init_libfuncs (void);
361 static bool frv_in_small_data_p (const_tree);
362 static void frv_asm_output_mi_thunk
363 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
364 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
367 static rtx frv_expand_builtin_saveregs (void);
368 static void frv_expand_builtin_va_start (tree, rtx);
369 static bool frv_rtx_costs (rtx, int, int, int*, bool);
370 static void frv_asm_out_constructor (rtx, int);
371 static void frv_asm_out_destructor (rtx, int);
372 static bool frv_function_symbol_referenced_p (rtx);
373 static bool frv_cannot_force_const_mem (rtx);
374 static const char *unspec_got_name (int);
375 static void frv_output_const_unspec (FILE *,
376 const struct frv_unspec *);
377 static bool frv_function_ok_for_sibcall (tree, tree);
378 static rtx frv_struct_value_rtx (tree, int);
379 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
380 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
382 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
384 static bool frv_secondary_reload (bool, rtx, enum reg_class,
386 secondary_reload_info *);
387 static bool frv_frame_pointer_required (void);
388 static bool frv_can_eliminate (const int, const int);
389 static void frv_trampoline_init (rtx, tree, rtx);
391 /* Allow us to easily change the default for -malloc-cc. */
392 #ifndef DEFAULT_NO_ALLOC_CC
393 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
395 #define MASK_DEFAULT_ALLOC_CC 0
398 /* Initialize the GCC target structure. */
399 #undef TARGET_ASM_FUNCTION_PROLOGUE
400 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
401 #undef TARGET_ASM_FUNCTION_EPILOGUE
402 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
403 #undef TARGET_ASM_INTEGER
404 #define TARGET_ASM_INTEGER frv_assemble_integer
405 #undef TARGET_DEFAULT_TARGET_FLAGS
406 #define TARGET_DEFAULT_TARGET_FLAGS \
407 (MASK_DEFAULT_ALLOC_CC \
414 #undef TARGET_HANDLE_OPTION
415 #define TARGET_HANDLE_OPTION frv_handle_option
416 #undef TARGET_INIT_BUILTINS
417 #define TARGET_INIT_BUILTINS frv_init_builtins
418 #undef TARGET_EXPAND_BUILTIN
419 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
420 #undef TARGET_INIT_LIBFUNCS
421 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
422 #undef TARGET_IN_SMALL_DATA_P
423 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
424 #undef TARGET_RTX_COSTS
425 #define TARGET_RTX_COSTS frv_rtx_costs
426 #undef TARGET_ASM_CONSTRUCTOR
427 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
428 #undef TARGET_ASM_DESTRUCTOR
429 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
431 #undef TARGET_ASM_OUTPUT_MI_THUNK
432 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
433 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
434 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
436 #undef TARGET_SCHED_ISSUE_RATE
437 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
439 #undef TARGET_LEGITIMIZE_ADDRESS
440 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
442 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
443 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
444 #undef TARGET_CANNOT_FORCE_CONST_MEM
445 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
447 #undef TARGET_HAVE_TLS
448 #define TARGET_HAVE_TLS HAVE_AS_TLS
450 #undef TARGET_STRUCT_VALUE_RTX
451 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
452 #undef TARGET_MUST_PASS_IN_STACK
453 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
454 #undef TARGET_PASS_BY_REFERENCE
455 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
456 #undef TARGET_ARG_PARTIAL_BYTES
457 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
459 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
460 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
461 #undef TARGET_SETUP_INCOMING_VARARGS
462 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
463 #undef TARGET_MACHINE_DEPENDENT_REORG
464 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
466 #undef TARGET_EXPAND_BUILTIN_VA_START
467 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
470 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
471 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
474 #undef TARGET_SECONDARY_RELOAD
475 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
477 #undef TARGET_LEGITIMATE_ADDRESS_P
478 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
480 #undef TARGET_FRAME_POINTER_REQUIRED
481 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
483 #undef TARGET_CAN_ELIMINATE
484 #define TARGET_CAN_ELIMINATE frv_can_eliminate
486 #undef TARGET_TRAMPOLINE_INIT
487 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
489 #undef TARGET_FUNCTION_VALUE
490 #define TARGET_FUNCTION_VALUE frv_function_value
491 #undef TARGET_LIBCALL_VALUE
492 #define TARGET_LIBCALL_VALUE frv_libcall_value
494 struct gcc_target targetm = TARGET_INITIALIZER;
496 #define FRV_SYMBOL_REF_TLS_P(RTX) \
497 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
500 /* Any function call that satisfies the machine-independent
501 requirements is eligible on FR-V. */
504 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
505 tree exp ATTRIBUTE_UNUSED)
510 /* Return true if SYMBOL is a small data symbol and relocation RELOC
511 can be used to access it directly in a load or store. */
513 static FRV_INLINE bool
514 frv_small_data_reloc_p (rtx symbol, int reloc)
516 return (GET_CODE (symbol) == SYMBOL_REF
517 && SYMBOL_REF_SMALL_P (symbol)
518 && (!TARGET_FDPIC || flag_pic == 1)
519 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
522 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
526 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
528 if (GET_CODE (x) == CONST)
532 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
534 unspec->offset += INTVAL (XEXP (x, 1));
537 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
539 unspec->symbol = XVECEXP (x, 0, 0);
540 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
542 if (unspec->offset == 0)
545 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
546 && unspec->offset > 0
547 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
554 /* Decide whether we can force certain constants to memory. If we
555 decide we can't, the caller should be able to cope with it in
558 We never allow constants to be forced into memory for TARGET_FDPIC.
559 This is necessary for several reasons:
561 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
562 target-independent code will try to force them into the constant
563 pool, thus leading to infinite recursion.
565 2. We can never introduce new constant pool references during reload.
566 Any such reference would require use of the pseudo FDPIC register.
568 3. We can't represent a constant added to a function pointer (which is
569 not the same as a pointer to a function+constant).
571 4. In many cases, it's more efficient to calculate the constant in-line. */
574 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
579 /* Implement TARGET_HANDLE_OPTION. */
582 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
587 if (strcmp (arg, "simple") == 0)
588 frv_cpu_type = FRV_CPU_SIMPLE;
589 else if (strcmp (arg, "tomcat") == 0)
590 frv_cpu_type = FRV_CPU_TOMCAT;
591 else if (strcmp (arg, "fr550") == 0)
592 frv_cpu_type = FRV_CPU_FR550;
593 else if (strcmp (arg, "fr500") == 0)
594 frv_cpu_type = FRV_CPU_FR500;
595 else if (strcmp (arg, "fr450") == 0)
596 frv_cpu_type = FRV_CPU_FR450;
597 else if (strcmp (arg, "fr405") == 0)
598 frv_cpu_type = FRV_CPU_FR405;
599 else if (strcmp (arg, "fr400") == 0)
600 frv_cpu_type = FRV_CPU_FR400;
601 else if (strcmp (arg, "fr300") == 0)
602 frv_cpu_type = FRV_CPU_FR300;
603 else if (strcmp (arg, "frv") == 0)
604 frv_cpu_type = FRV_CPU_GENERIC;
615 frv_default_flags_for_cpu (void)
617 switch (frv_cpu_type)
619 case FRV_CPU_GENERIC:
620 return MASK_DEFAULT_FRV;
623 return MASK_DEFAULT_FR550;
627 return MASK_DEFAULT_FR500;
630 return MASK_DEFAULT_FR450;
634 return MASK_DEFAULT_FR400;
638 return MASK_DEFAULT_SIMPLE;
645 /* Sometimes certain combinations of command options do not make
646 sense on a particular target machine. You can define a macro
647 `OVERRIDE_OPTIONS' to take account of this. This macro, if
648 defined, is executed once just after all the command options have
651 Don't use this macro to turn on various extra optimizations for
652 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
655 frv_override_options (void)
660 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
662 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
663 linker about linking pic and non-pic code. */
666 if (!flag_pic) /* -fPIC */
669 if (! g_switch_set) /* -G0 */
676 /* A C expression whose value is a register class containing hard
677 register REGNO. In general there is more than one such class;
678 choose a class which is "minimal", meaning that no smaller class
679 also contains the register. */
681 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
683 enum reg_class rclass;
687 int gpr_reg = regno - GPR_FIRST;
689 if (gpr_reg == GR8_REG)
692 else if (gpr_reg == GR9_REG)
695 else if (gpr_reg == GR14_REG)
696 rclass = FDPIC_FPTR_REGS;
698 else if (gpr_reg == FDPIC_REGNO)
701 else if ((gpr_reg & 3) == 0)
704 else if ((gpr_reg & 1) == 0)
711 else if (FPR_P (regno))
713 int fpr_reg = regno - GPR_FIRST;
714 if ((fpr_reg & 3) == 0)
715 rclass = QUAD_FPR_REGS;
717 else if ((fpr_reg & 1) == 0)
724 else if (regno == LR_REGNO)
727 else if (regno == LCR_REGNO)
730 else if (ICC_P (regno))
733 else if (FCC_P (regno))
736 else if (ICR_P (regno))
739 else if (FCR_P (regno))
742 else if (ACC_P (regno))
744 int r = regno - ACC_FIRST;
746 rclass = QUAD_ACC_REGS;
747 else if ((r & 1) == 0)
748 rclass = EVEN_ACC_REGS;
753 else if (ACCG_P (regno))
759 regno_reg_class[regno] = rclass;
762 /* Check for small data option */
764 g_switch_value = SDATA_DEFAULT_SIZE;
766 /* A C expression which defines the machine-dependent operand
767 constraint letters for register classes. If CHAR is such a
768 letter, the value should be the register class corresponding to
769 it. Otherwise, the value should be `NO_REGS'. The register
770 letter `r', corresponding to class `GENERAL_REGS', will not be
771 passed to this macro; you do not need to handle it.
773 The following letters are unavailable, due to being used as
778 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
779 'Q', 'R', 'S', 'T', 'U'
781 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
783 for (i = 0; i < 256; i++)
784 reg_class_from_letter[i] = NO_REGS;
786 reg_class_from_letter['a'] = ACC_REGS;
787 reg_class_from_letter['b'] = EVEN_ACC_REGS;
788 reg_class_from_letter['c'] = CC_REGS;
789 reg_class_from_letter['d'] = GPR_REGS;
790 reg_class_from_letter['e'] = EVEN_REGS;
791 reg_class_from_letter['f'] = FPR_REGS;
792 reg_class_from_letter['h'] = FEVEN_REGS;
793 reg_class_from_letter['l'] = LR_REG;
794 reg_class_from_letter['q'] = QUAD_REGS;
795 reg_class_from_letter['t'] = ICC_REGS;
796 reg_class_from_letter['u'] = FCC_REGS;
797 reg_class_from_letter['v'] = ICR_REGS;
798 reg_class_from_letter['w'] = FCR_REGS;
799 reg_class_from_letter['x'] = QUAD_FPR_REGS;
800 reg_class_from_letter['y'] = LCR_REG;
801 reg_class_from_letter['z'] = SPR_REGS;
802 reg_class_from_letter['A'] = QUAD_ACC_REGS;
803 reg_class_from_letter['B'] = ACCG_REGS;
804 reg_class_from_letter['C'] = CR_REGS;
805 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
806 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
808 /* There is no single unaligned SI op for PIC code. Sometimes we
809 need to use ".4byte" and sometimes we need to use ".picptr".
810 See frv_assemble_integer for details. */
811 if (flag_pic || TARGET_FDPIC)
812 targetm.asm_out.unaligned_op.si = 0;
814 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
815 target_flags |= MASK_LINKED_FP;
817 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
818 target_flags |= MASK_OPTIMIZE_MEMBAR;
820 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
821 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
823 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
824 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
826 init_machine_status = frv_init_machine_status;
830 /* Some machines may desire to change what optimizations are performed for
831 various optimization levels. This macro, if defined, is executed once just
832 after the optimization level is determined and before the remainder of the
833 command options have been parsed. Values set in this macro are used as the
834 default values for the other command line options.
836 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
837 `-O' is specified, and 0 if neither is specified.
839 SIZE is nonzero if `-Os' is specified, 0 otherwise.
841 You should not use this macro to change options that are not
842 machine-specific. These should uniformly selected by the same optimization
843 level on all supported machines. Use this macro to enable machine-specific
846 *Do not examine `write_symbols' in this macro!* The debugging options are
847 *not supposed to alter the generated code. */
849 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
850 scheduling pass at the current time. */
852 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
856 #ifdef DISABLE_SCHED2
857 flag_schedule_insns_after_reload = 0;
866 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
869 frv_string_begins_with (const_tree name, const char *prefix)
871 const int prefix_len = strlen (prefix);
873 /* Remember: NAME's length includes the null terminator. */
874 return (TREE_STRING_LENGTH (name) > prefix_len
875 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
878 /* Zero or more C statements that may conditionally modify two variables
879 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
880 been initialized from the two preceding macros.
882 This is necessary in case the fixed or call-clobbered registers depend on
885 You need not define this macro if it has no work to do.
887 If the usage of an entire class of registers depends on the target flags,
888 you may indicate this to GCC by using this macro to modify `fixed_regs' and
889 `call_used_regs' to 1 for each of the registers in the classes which should
890 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
891 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
893 (However, if this class is not included in `GENERAL_REGS' and all of the
894 insn patterns whose constraints permit this class are controlled by target
895 switches, then GCC will automatically avoid using these registers when the
896 target switches are opposed to them.) */
899 frv_conditional_register_usage (void)
903 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
904 fixed_regs[i] = call_used_regs[i] = 1;
906 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
907 fixed_regs[i] = call_used_regs[i] = 1;
909 /* Reserve the registers used for conditional execution. At present, we need
910 1 ICC and 1 ICR register. */
911 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
912 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
916 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
917 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
918 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
919 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
923 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
924 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
927 /* If -fpic, SDA_BASE_REG is the PIC register. */
928 if (g_switch_value == 0 && !flag_pic)
929 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
932 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
938 * Compute the stack frame layout
941 * +---------------+-----------------------+-----------------------+
942 * |Register |type |caller-save/callee-save|
943 * +---------------+-----------------------+-----------------------+
944 * |GR0 |Zero register | - |
945 * |GR1 |Stack pointer(SP) | - |
946 * |GR2 |Frame pointer(FP) | - |
947 * |GR3 |Hidden parameter | caller save |
948 * |GR4-GR7 | - | caller save |
949 * |GR8-GR13 |Argument register | caller save |
950 * |GR14-GR15 | - | caller save |
951 * |GR16-GR31 | - | callee save |
952 * |GR32-GR47 | - | caller save |
953 * |GR48-GR63 | - | callee save |
954 * |FR0-FR15 | - | caller save |
955 * |FR16-FR31 | - | callee save |
956 * |FR32-FR47 | - | caller save |
957 * |FR48-FR63 | - | callee save |
958 * +---------------+-----------------------+-----------------------+
962 * SP-> |-----------------------------------|
964 * |-----------------------------------|
965 * | Register save area |
966 * |-----------------------------------|
967 * | Local variable save area |
968 * FP-> |-----------------------------------|
970 * |-----------------------------------|
971 * | Hidden parameter save area |
972 * |-----------------------------------|
973 * | Return address(LR) storage area |
974 * |-----------------------------------|
975 * | Padding for alignment |
976 * |-----------------------------------|
977 * | Register argument area |
978 * OLD SP-> |-----------------------------------|
980 * |-----------------------------------|
983 * Argument area/Parameter area:
985 * When a function is called, this area is used for argument transfer. When
986 * the argument is set up by the caller function, this area is referred to as
987 * the argument area. When the argument is referenced by the callee function,
988 * this area is referred to as the parameter area. The area is allocated when
989 * all arguments cannot be placed on the argument register at the time of
992 * Register save area:
994 * This is a register save area that must be guaranteed for the caller
995 * function. This area is not secured when the register save operation is not
998 * Local variable save area:
1000 * This is the area for local variables and temporary variables.
1004 * This area stores the FP value of the caller function.
1006 * Hidden parameter save area:
1008 * This area stores the start address of the return value storage
1009 * area for a struct/union return function.
1010 * When a struct/union is used as the return value, the caller
1011 * function stores the return value storage area start address in
1012 * register GR3 and passes it to the caller function.
1013 * The callee function interprets the address stored in the GR3
1014 * as the return value storage area start address.
1015 * When register GR3 needs to be saved into memory, the callee
1016 * function saves it in the hidden parameter save area. This
1017 * area is not secured when the save operation is not needed.
1019 * Return address(LR) storage area:
1021 * This area saves the LR. The LR stores the address of a return to the caller
1022 * function for the purpose of function calling.
1024 * Argument register area:
1026 * This area saves the argument register. This area is not secured when the
1027 * save operation is not needed.
1031 * Arguments, the count of which equals the count of argument registers (6
1032 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1033 * function. When a struct/union return function is called, the return value
1034 * area address is stored in register GR3. Arguments not placed in the
1035 * argument registers will be stored in the stack argument area for transfer
1036 * purposes. When an 8-byte type argument is to be delivered using registers,
1037 * it is divided into two and placed in two registers for transfer. When
1038 * argument registers must be saved to memory, the callee function secures an
1039 * argument register save area in the stack. In this case, a continuous
1040 * argument register save area must be established in the parameter area. The
1041 * argument register save area must be allocated as needed to cover the size of
1042 * the argument register to be saved. If the function has a variable count of
1043 * arguments, it saves all argument registers in the argument register save
1046 * Argument Extension Format:
1048 * When an argument is to be stored in the stack, its type is converted to an
1049 * extended type in accordance with the individual argument type. The argument
1050 * is freed by the caller function after the return from the callee function is
1053 * +-----------------------+---------------+------------------------+
1054 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1055 * +-----------------------+---------------+------------------------+
1057 * |signed char |int | 4 |
1058 * |unsigned char |int | 4 |
1059 * |[signed] short int |int | 4 |
1060 * |unsigned short int |int | 4 |
1061 * |[signed] int |No extension | 4 |
1062 * |unsigned int |No extension | 4 |
1063 * |[signed] long int |No extension | 4 |
1064 * |unsigned long int |No extension | 4 |
1065 * |[signed] long long int |No extension | 8 |
1066 * |unsigned long long int |No extension | 8 |
1067 * |float |double | 8 |
1068 * |double |No extension | 8 |
1069 * |long double |No extension | 8 |
1070 * |pointer |No extension | 4 |
1071 * |struct/union |- | 4 (*1) |
1072 * +-----------------------+---------------+------------------------+
1074 * When a struct/union is to be delivered as an argument, the caller copies it
1075 * to the local variable area and delivers the address of that area.
1079 * +-------------------------------+----------------------+
1080 * |Return Value Type |Return Value Interface|
1081 * +-------------------------------+----------------------+
1083 * |[signed|unsigned] char |GR8 |
1084 * |[signed|unsigned] short int |GR8 |
1085 * |[signed|unsigned] int |GR8 |
1086 * |[signed|unsigned] long int |GR8 |
1088 * |[signed|unsigned] long long int|GR8 & GR9 |
1090 * |double |GR8 & GR9 |
1091 * |long double |GR8 & GR9 |
1092 * |struct/union |(*1) |
1093 * +-------------------------------+----------------------+
1095 * When a struct/union is used as the return value, the caller function stores
1096 * the start address of the return value storage area into GR3 and then passes
1097 * it to the callee function. The callee function interprets GR3 as the start
1098 * address of the return value storage area. When this address needs to be
1099 * saved in memory, the callee function secures the hidden parameter save area
1100 * and saves the address in that area.
1104 frv_stack_info (void)
1106 static frv_stack_t info, zero_info;
1107 frv_stack_t *info_ptr = &info;
1108 tree fndecl = current_function_decl;
1116 /* If we've already calculated the values and reload is complete,
1118 if (frv_stack_cache)
1119 return frv_stack_cache;
1121 /* Zero all fields. */
1124 /* Set up the register range information. */
1125 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1126 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1127 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1128 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1130 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1131 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1132 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1133 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1135 info_ptr->regs[STACK_REGS_LR].name = "lr";
1136 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1137 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1138 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1140 info_ptr->regs[STACK_REGS_CC].name = "cc";
1141 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1142 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1143 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1145 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1146 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1147 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1149 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1150 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1151 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1152 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1153 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1155 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1156 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1157 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1158 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1160 info_ptr->regs[STACK_REGS_FP].name = "fp";
1161 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1162 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1163 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1165 /* Determine if this is a stdarg function. If so, allocate space to store
1172 /* Find the last argument, and see if it is __builtin_va_alist. */
1173 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1175 next_arg = TREE_CHAIN (cur_arg);
1176 if (next_arg == (tree)0)
1178 if (DECL_NAME (cur_arg)
1179 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1187 /* Iterate over all of the register ranges. */
1188 for (range = 0; range < STACK_REGS_MAX; range++)
1190 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1191 int first = reg_ptr->first;
1192 int last = reg_ptr->last;
1194 int size_2words = 0;
1197 /* Calculate which registers need to be saved & save area size. */
1201 for (regno = first; regno <= last; regno++)
1203 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1204 || (crtl->calls_eh_return
1205 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1206 || (!TARGET_FDPIC && flag_pic
1207 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1209 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1210 size_1word += UNITS_PER_WORD;
1215 /* Calculate whether we need to create a frame after everything else
1216 has been processed. */
1221 if (df_regs_ever_live_p (LR_REGNO)
1223 /* This is set for __builtin_return_address, etc. */
1224 || cfun->machine->frame_needed
1225 || (TARGET_LINKED_FP && frame_pointer_needed)
1226 || (!TARGET_FDPIC && flag_pic
1227 && crtl->uses_pic_offset_table))
1229 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1230 size_1word += UNITS_PER_WORD;
1234 case STACK_REGS_STDARG:
1237 /* If this is a stdarg function with a non varardic
1238 argument split between registers and the stack,
1239 adjust the saved registers downward. */
1240 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1243 for (regno = first; regno <= last; regno++)
1245 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1246 size_1word += UNITS_PER_WORD;
1249 info_ptr->stdarg_size = size_1word;
1253 case STACK_REGS_STRUCT:
1254 if (cfun->returns_struct)
1256 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1257 size_1word += UNITS_PER_WORD;
1265 /* If this is a field, it only takes one word. */
1266 if (reg_ptr->field_p)
1267 size_1word = UNITS_PER_WORD;
1269 /* Determine which register pairs can be saved together. */
1270 else if (reg_ptr->dword_p && TARGET_DWORD)
1272 for (regno = first; regno < last; regno += 2)
1274 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1276 size_2words += 2 * UNITS_PER_WORD;
1277 size_1word -= 2 * UNITS_PER_WORD;
1278 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1279 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1284 reg_ptr->size_1word = size_1word;
1285 reg_ptr->size_2words = size_2words;
1287 if (! reg_ptr->special_p)
1289 info_ptr->regs_size_1word += size_1word;
1290 info_ptr->regs_size_2words += size_2words;
1295 /* Set up the sizes of each each field in the frame body, making the sizes
1296 of each be divisible by the size of a dword if dword operations might
1297 be used, or the size of a word otherwise. */
1298 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1300 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1301 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1302 + info_ptr->regs_size_1word,
1304 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1306 info_ptr->pretend_size = crtl->args.pretend_args_size;
1308 /* Work out the size of the frame, excluding the header. Both the frame
1309 body and register parameter area will be dword-aligned. */
1310 info_ptr->total_size
1311 = (ADDR_ALIGN (info_ptr->parameter_size
1312 + info_ptr->regs_size
1313 + info_ptr->vars_size,
1315 + ADDR_ALIGN (info_ptr->pretend_size
1316 + info_ptr->stdarg_size,
1317 2 * UNITS_PER_WORD));
1319 /* See if we need to create a frame at all, if so add header area. */
1320 if (info_ptr->total_size > 0
1321 || frame_pointer_needed
1322 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1323 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1325 offset = info_ptr->parameter_size;
1326 info_ptr->header_size = 4 * UNITS_PER_WORD;
1327 info_ptr->total_size += 4 * UNITS_PER_WORD;
1329 /* Calculate the offsets to save normal register pairs. */
1330 for (range = 0; range < STACK_REGS_MAX; range++)
1332 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1333 if (! reg_ptr->special_p)
1335 int first = reg_ptr->first;
1336 int last = reg_ptr->last;
1339 for (regno = first; regno <= last; regno++)
1340 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1341 && regno != FRAME_POINTER_REGNUM
1342 && (regno < FIRST_ARG_REGNUM
1343 || regno > LAST_ARG_REGNUM))
1345 info_ptr->reg_offset[regno] = offset;
1346 offset += 2 * UNITS_PER_WORD;
1351 /* Calculate the offsets to save normal single registers. */
1352 for (range = 0; range < STACK_REGS_MAX; range++)
1354 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1355 if (! reg_ptr->special_p)
1357 int first = reg_ptr->first;
1358 int last = reg_ptr->last;
1361 for (regno = first; regno <= last; regno++)
1362 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1363 && regno != FRAME_POINTER_REGNUM
1364 && (regno < FIRST_ARG_REGNUM
1365 || regno > LAST_ARG_REGNUM))
1367 info_ptr->reg_offset[regno] = offset;
1368 offset += UNITS_PER_WORD;
1373 /* Calculate the offset to save the local variables at. */
1374 offset = ADDR_ALIGN (offset, alignment);
1375 if (info_ptr->vars_size)
1377 info_ptr->vars_offset = offset;
1378 offset += info_ptr->vars_size;
1381 /* Align header to a dword-boundary. */
1382 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1384 /* Calculate the offsets in the fixed frame. */
1385 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1386 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1387 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1389 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1390 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1391 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1393 if (cfun->returns_struct)
1395 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1396 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1397 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1400 /* Calculate the offsets to store the arguments passed in registers
1401 for stdarg functions. The register pairs are first and the single
1402 register if any is last. The register save area starts on a
1404 if (info_ptr->stdarg_size)
1406 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1407 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1410 /* Skip the header. */
1411 offset += 4 * UNITS_PER_WORD;
1412 for (regno = first; regno <= last; regno++)
1414 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1416 info_ptr->reg_offset[regno] = offset;
1417 offset += 2 * UNITS_PER_WORD;
1419 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1421 info_ptr->reg_offset[regno] = offset;
1422 offset += UNITS_PER_WORD;
1428 if (reload_completed)
1429 frv_stack_cache = info_ptr;
1435 /* Print the information about the frv stack offsets, etc. when debugging. */
1438 frv_debug_stack (frv_stack_t *info)
1443 info = frv_stack_info ();
1445 fprintf (stderr, "\nStack information for function %s:\n",
1446 ((current_function_decl && DECL_NAME (current_function_decl))
1447 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1450 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1451 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1452 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1453 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1454 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1456 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1457 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1458 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1459 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1461 for (range = 0; range < STACK_REGS_MAX; range++)
1463 frv_stack_regs_t *regs = &(info->regs[range]);
1464 if ((regs->size_1word + regs->size_2words) > 0)
1466 int first = regs->first;
1467 int last = regs->last;
1470 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1471 regs->name, regs->size_1word + regs->size_2words,
1472 regs->size_1word, regs->size_2words);
1474 for (regno = first; regno <= last; regno++)
1476 if (info->save_p[regno] == REG_SAVE_1WORD)
1477 fprintf (stderr, " %s (%d)", reg_names[regno],
1478 info->reg_offset[regno]);
1480 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1481 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1482 reg_names[regno+1], info->reg_offset[regno]);
1485 fputc ('\n', stderr);
1495 /* Used during final to control the packing of insns. The value is
1496 1 if the current instruction should be packed with the next one,
1497 0 if it shouldn't or -1 if packing is disabled altogether. */
1499 static int frv_insn_packing_flag;
1501 /* True if the current function contains a far jump. */
1504 frv_function_contains_far_jump (void)
1506 rtx insn = get_insns ();
1508 && !(GET_CODE (insn) == JUMP_INSN
1509 /* Ignore tablejump patterns. */
1510 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1511 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1512 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1513 insn = NEXT_INSN (insn);
1514 return (insn != NULL);
1517 /* For the FRV, this function makes sure that a function with far jumps
1518 will return correctly. It also does the VLIW packing. */
1521 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1523 /* If no frame was created, check whether the function uses a call
1524 instruction to implement a far jump. If so, save the link in gr3 and
1525 replace all returns to LR with returns to GR3. GR3 is used because it
1526 is call-clobbered, because is not available to the register allocator,
1527 and because all functions that take a hidden argument pointer will have
1529 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1533 /* Just to check that the above comment is true. */
1534 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1536 /* Generate the instruction that saves the link register. */
1537 fprintf (file, "\tmovsg lr,gr3\n");
1539 /* Replace the LR with GR3 in *return_internal patterns. The insn
1540 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1541 simply emit a different assembly directive because bralr and jmpl
1542 execute in different units. */
1543 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1544 if (GET_CODE (insn) == JUMP_INSN)
1546 rtx pattern = PATTERN (insn);
1547 if (GET_CODE (pattern) == PARALLEL
1548 && XVECLEN (pattern, 0) >= 2
1549 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1550 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1552 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1553 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1554 SET_REGNO (address, GPR_FIRST + 3);
1561 /* Allow the garbage collector to free the nops created by frv_reorg. */
1562 memset (frv_nops, 0, sizeof (frv_nops));
1566 /* Return the next available temporary register in a given class. */
1569 frv_alloc_temp_reg (
1570 frv_tmp_reg_t *info, /* which registers are available */
1571 enum reg_class rclass, /* register class desired */
1572 enum machine_mode mode, /* mode to allocate register with */
1573 int mark_as_used, /* register not available after allocation */
1574 int no_abort) /* return NULL instead of aborting */
1576 int regno = info->next_reg[ (int)rclass ];
1577 int orig_regno = regno;
1578 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1583 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1584 && TEST_HARD_REG_BIT (info->regs, regno))
1587 if (++regno >= FIRST_PSEUDO_REGISTER)
1589 if (regno == orig_regno)
1591 gcc_assert (no_abort);
1596 nr = HARD_REGNO_NREGS (regno, mode);
1597 info->next_reg[ (int)rclass ] = regno + nr;
1600 for (i = 0; i < nr; i++)
1601 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1603 return gen_rtx_REG (mode, regno);
1607 /* Return an rtx with the value OFFSET, which will either be a register or a
1608 signed 12-bit integer. It can be used as the second operand in an "add"
1609 instruction, or as the index in a load or store.
1611 The function returns a constant rtx if OFFSET is small enough, otherwise
1612 it loads the constant into register OFFSET_REGNO and returns that. */
1614 frv_frame_offset_rtx (int offset)
1616 rtx offset_rtx = GEN_INT (offset);
1617 if (IN_RANGE_P (offset, -2048, 2047))
1621 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1622 if (IN_RANGE_P (offset, -32768, 32767))
1623 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1626 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1627 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1633 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1634 prologue and epilogue uses such expressions to access the stack. */
1636 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1638 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1640 frv_frame_offset_rtx (offset)));
1643 /* Generate a frame-related expression:
1645 (set REG (mem (plus (sp) (const_int OFFSET)))).
1647 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1648 instructions. Marking the expressions as frame-related is superfluous if
1649 the note contains just a single set. But if the note contains a PARALLEL
1650 or SEQUENCE that has several sets, each set must be individually marked
1651 as frame-related. */
1653 frv_dwarf_store (rtx reg, int offset)
1655 rtx set = gen_rtx_SET (VOIDmode,
1656 gen_rtx_MEM (GET_MODE (reg),
1657 plus_constant (stack_pointer_rtx,
1660 RTX_FRAME_RELATED_P (set) = 1;
1664 /* Emit a frame-related instruction whose pattern is PATTERN. The
1665 instruction is the last in a sequence that cumulatively performs the
1666 operation described by DWARF_PATTERN. The instruction is marked as
1667 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1670 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1672 rtx insn = emit_insn (pattern);
1673 RTX_FRAME_RELATED_P (insn) = 1;
1674 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1679 /* Emit instructions that transfer REG to or from the memory location (sp +
1680 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1681 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1682 function to store registers and only the epilogue uses it to load them.
1684 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1685 The generated instruction will use BASE as its base register. BASE may
1686 simply be the stack pointer, but if several accesses are being made to a
1687 region far away from the stack pointer, it may be more efficient to set
1688 up a temporary instead.
1690 Store instructions will be frame-related and will be annotated with the
1691 overall effect of the store. Load instructions will be followed by a
1692 (use) to prevent later optimizations from zapping them.
1694 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1695 as a temporary in such cases. */
1697 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1699 enum machine_mode mode = GET_MODE (reg);
1700 rtx mem = frv_frame_mem (mode,
1702 stack_offset - accessor->base_offset);
1704 if (accessor->op == FRV_LOAD)
1706 if (SPR_P (REGNO (reg)))
1708 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1709 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1710 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1714 /* We cannot use reg+reg addressing for DImode access. */
1716 && GET_CODE (XEXP (mem, 0)) == PLUS
1717 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1718 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1720 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1721 rtx insn = emit_move_insn (temp,
1722 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1723 XEXP (XEXP (mem, 0), 1)));
1724 mem = gen_rtx_MEM (DImode, temp);
1726 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1732 if (SPR_P (REGNO (reg)))
1734 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1735 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1736 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1737 frv_dwarf_store (reg, stack_offset));
1739 else if (mode == DImode)
1741 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1742 with a separate save for each register. */
1743 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1744 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1745 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1746 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1748 /* Also we cannot use reg+reg addressing. */
1749 if (GET_CODE (XEXP (mem, 0)) == PLUS
1750 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1751 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1753 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1754 rtx insn = emit_move_insn (temp,
1755 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1756 XEXP (XEXP (mem, 0), 1)));
1757 mem = gen_rtx_MEM (DImode, temp);
1760 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1761 gen_rtx_PARALLEL (VOIDmode,
1762 gen_rtvec (2, set1, set2)));
1765 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1766 frv_dwarf_store (reg, stack_offset));
1770 /* A function that uses frv_frame_access to transfer a group of registers to
1771 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1772 is the stack information generated by frv_stack_info, and REG_SET is the
1773 number of the register set to transfer. */
1775 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1779 frv_stack_regs_t *regs_info;
1782 regs_info = &info->regs[reg_set];
1783 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1784 if (info->save_p[regno])
1785 frv_frame_access (accessor,
1786 info->save_p[regno] == REG_SAVE_2WORDS
1787 ? gen_rtx_REG (DImode, regno)
1788 : gen_rtx_REG (SImode, regno),
1789 info->reg_offset[regno]);
1792 /* Save or restore callee-saved registers that are kept outside the frame
1793 header. The function saves the registers if OP is FRV_STORE and restores
1794 them if OP is FRV_LOAD. INFO is the stack information generated by
1797 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1799 frv_frame_accessor_t accessor;
1802 accessor.base = stack_pointer_rtx;
1803 accessor.base_offset = 0;
1804 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1805 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1806 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1810 /* Called after register allocation to add any instructions needed for the
1811 prologue. Using a prologue insn is favored compared to putting all of the
1812 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1813 it allows the scheduler to intermix instructions with the saves of
1814 the caller saved registers. In some cases, it might be necessary
1815 to emit a barrier instruction as the last insn to prevent such
1818 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1819 so that the debug info generation code can handle them properly. */
1821 frv_expand_prologue (void)
1823 frv_stack_t *info = frv_stack_info ();
1824 rtx sp = stack_pointer_rtx;
1825 rtx fp = frame_pointer_rtx;
1826 frv_frame_accessor_t accessor;
1828 if (TARGET_DEBUG_STACK)
1829 frv_debug_stack (info);
1831 if (info->total_size == 0)
1834 /* We're interested in three areas of the frame here:
1836 A: the register save area
1838 C: the header after B
1840 If the frame pointer isn't used, we'll have to set up A, B and C
1841 using the stack pointer. If the frame pointer is used, we'll access
1845 B: set up using sp or a temporary (see below)
1848 We set up B using the stack pointer if the frame is small enough.
1849 Otherwise, it's more efficient to copy the old stack pointer into a
1850 temporary and use that.
1852 Note that it's important to make sure the prologue and epilogue use the
1853 same registers to access A and C, since doing otherwise will confuse
1854 the aliasing code. */
1856 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1857 isn't used, the same method will serve for C. */
1858 accessor.op = FRV_STORE;
1859 if (frame_pointer_needed && info->total_size > 2048)
1863 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1864 accessor.base_offset = info->total_size;
1865 insn = emit_insn (gen_movsi (accessor.base, sp));
1869 accessor.base = stack_pointer_rtx;
1870 accessor.base_offset = 0;
1873 /* Allocate the stack space. */
1875 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1876 rtx dwarf_offset = GEN_INT (-info->total_size);
1878 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1881 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1884 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1885 and point the new one to that location. */
1886 if (frame_pointer_needed)
1888 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1890 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1891 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1893 rtx asm_src = plus_constant (accessor.base,
1894 fp_offset - accessor.base_offset);
1895 rtx dwarf_src = plus_constant (sp, fp_offset);
1897 /* Store the old frame pointer at (sp + FP_OFFSET). */
1898 frv_frame_access (&accessor, fp, fp_offset);
1900 /* Set up the new frame pointer. */
1901 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1902 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1904 /* Access region C from the frame pointer. */
1906 accessor.base_offset = fp_offset;
1909 /* Set up region C. */
1910 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1911 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1912 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1914 /* Set up region A. */
1915 frv_frame_access_standard_regs (FRV_STORE, info);
1917 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1918 scheduler from moving loads before the stores saving the registers. */
1919 if (info->stdarg_size > 0)
1920 emit_insn (gen_blockage ());
1922 /* Set up pic register/small data register for this function. */
1923 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1924 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1925 gen_rtx_REG (Pmode, LR_REGNO),
1926 gen_rtx_REG (SImode, OFFSET_REGNO)));
1930 /* Under frv, all of the work is done via frv_expand_epilogue, but
1931 this function provides a convenient place to do cleanup. */
1934 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1935 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1937 frv_stack_cache = (frv_stack_t *)0;
1939 /* Zap last used registers for conditional execution. */
1940 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1942 /* Release the bitmap of created insns. */
1943 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1947 /* Called after register allocation to add any instructions needed for the
1948 epilogue. Using an epilogue insn is favored compared to putting all of the
1949 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1950 it allows the scheduler to intermix instructions with the saves of
1951 the caller saved registers. In some cases, it might be necessary
1952 to emit a barrier instruction as the last insn to prevent such
1956 frv_expand_epilogue (bool emit_return)
1958 frv_stack_t *info = frv_stack_info ();
1959 rtx fp = frame_pointer_rtx;
1960 rtx sp = stack_pointer_rtx;
1964 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1966 /* Restore the stack pointer to its original value if alloca or the like
1968 if (! current_function_sp_is_unchanging)
1969 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1971 /* Restore the callee-saved registers that were used in this function. */
1972 frv_frame_access_standard_regs (FRV_LOAD, info);
1974 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1975 no return instruction should be emitted. */
1976 if (info->save_p[LR_REGNO])
1981 /* Use the same method to access the link register's slot as we did in
1982 the prologue. In other words, use the frame pointer if available,
1983 otherwise use the stack pointer.
1985 LR_OFFSET is the offset of the link register's slot from the start
1986 of the frame and MEM is a memory rtx for it. */
1987 lr_offset = info->reg_offset[LR_REGNO];
1988 if (frame_pointer_needed)
1989 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1991 mem = frv_frame_mem (Pmode, sp, lr_offset);
1993 /* Load the old link register into a GPR. */
1994 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1995 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1998 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
2000 /* Restore the old frame pointer. Emit a USE afterwards to make sure
2001 the load is preserved. */
2002 if (frame_pointer_needed)
2004 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
2008 /* Deallocate the stack frame. */
2009 if (info->total_size != 0)
2011 rtx offset = frv_frame_offset_rtx (info->total_size);
2012 emit_insn (gen_stack_adjust (sp, sp, offset));
2015 /* If this function uses eh_return, add the final stack adjustment now. */
2016 if (crtl->calls_eh_return)
2017 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2020 emit_jump_insn (gen_epilogue_return (return_addr));
2023 rtx lr = return_addr;
2025 if (REGNO (return_addr) != LR_REGNO)
2027 lr = gen_rtx_REG (Pmode, LR_REGNO);
2028 emit_move_insn (lr, return_addr);
2036 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2039 frv_asm_output_mi_thunk (FILE *file,
2040 tree thunk_fndecl ATTRIBUTE_UNUSED,
2041 HOST_WIDE_INT delta,
2042 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2045 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2046 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2047 const char *name_jmp = reg_names[JUMP_REGNO];
2048 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2050 /* Do the add using an addi if possible. */
2051 if (IN_RANGE_P (delta, -2048, 2047))
2052 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2055 const char *const name_add = reg_names[TEMP_REGNO];
2056 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2057 parallel, delta, name_add);
2058 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2060 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2065 const char *name_pic = reg_names[FDPIC_REGNO];
2066 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2070 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2071 assemble_name (file, name_func);
2072 fprintf (file, "),%s\n", name_jmp);
2074 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2075 assemble_name (file, name_func);
2076 fprintf (file, "),%s\n", name_jmp);
2078 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2082 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2083 assemble_name (file, name_func);
2084 fprintf (file, "\t)), %s\n", name_jmp);
2089 fprintf (file, "\tsethi%s #hi(", parallel);
2090 assemble_name (file, name_func);
2091 fprintf (file, "),%s\n", name_jmp);
2093 fprintf (file, "\tsetlo #lo(");
2094 assemble_name (file, name_func);
2095 fprintf (file, "),%s\n", name_jmp);
2099 /* Use JUMP_REGNO as a temporary PIC register. */
2100 const char *name_lr = reg_names[LR_REGNO];
2101 const char *name_gppic = name_jmp;
2102 const char *name_tmp = reg_names[TEMP_REGNO];
2104 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2105 fprintf (file, "\tcall 1f\n");
2106 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2107 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2108 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2109 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2110 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2112 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2113 assemble_name (file, name_func);
2114 fprintf (file, "),%s\n", name_tmp);
2116 fprintf (file, "\tsetlo #gprello(");
2117 assemble_name (file, name_func);
2118 fprintf (file, "),%s\n", name_tmp);
2120 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2123 /* Jump to the function address. */
2124 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2129 /* On frv, create a frame whenever we need to create stack. */
2132 frv_frame_pointer_required (void)
2134 /* If we forgoing the usual linkage requirements, we only need
2135 a frame pointer if the stack pointer might change. */
2136 if (!TARGET_LINKED_FP)
2137 return !current_function_sp_is_unchanging;
2139 if (! current_function_is_leaf)
2142 if (get_frame_size () != 0)
2148 if (!current_function_sp_is_unchanging)
2151 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2157 if (cfun->machine->frame_needed)
2164 /* Worker function for TARGET_CAN_ELIMINATE. */
2167 frv_can_eliminate (const int from, const int to)
2169 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2170 ? ! frame_pointer_needed
2174 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2175 initial difference between the specified pair of registers. This macro must
2176 be defined if `ELIMINABLE_REGS' is defined. */
2178 /* See frv_stack_info for more details on the frv stack frame. */
2181 frv_initial_elimination_offset (int from, int to)
2183 frv_stack_t *info = frv_stack_info ();
2186 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2187 ret = info->total_size - info->pretend_size;
2189 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2190 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2192 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2193 ret = (info->total_size
2194 - info->reg_offset[FRAME_POINTER_REGNUM]
2195 - info->pretend_size);
2200 if (TARGET_DEBUG_STACK)
2201 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2202 reg_names [from], reg_names[to], ret);
2208 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2211 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2212 enum machine_mode mode,
2213 tree type ATTRIBUTE_UNUSED,
2217 if (TARGET_DEBUG_ARG)
2219 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2220 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2224 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2227 frv_expand_builtin_saveregs (void)
2229 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2231 if (TARGET_DEBUG_ARG)
2232 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2235 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2239 /* Expand __builtin_va_start to do the va_start macro. */
2242 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2245 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2247 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2248 GEN_INT (UNITS_PER_WORD * num));
2250 if (TARGET_DEBUG_ARG)
2252 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2253 crtl->args.info, num);
2255 debug_rtx (nextarg);
2258 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2259 fold_convert (TREE_TYPE (valist),
2260 make_tree (sizetype, nextarg)));
2261 TREE_SIDE_EFFECTS (t) = 1;
2263 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2267 /* Expand a block move operation, and return 1 if successful. Return 0
2268 if we should let the compiler generate normal code.
2270 operands[0] is the destination
2271 operands[1] is the source
2272 operands[2] is the length
2273 operands[3] is the alignment */
2275 /* Maximum number of loads to do before doing the stores */
2276 #ifndef MAX_MOVE_REG
2277 #define MAX_MOVE_REG 4
2280 /* Maximum number of total loads to do. */
2281 #ifndef TOTAL_MOVE_REG
2282 #define TOTAL_MOVE_REG 8
2286 frv_expand_block_move (rtx operands[])
2288 rtx orig_dest = operands[0];
2289 rtx orig_src = operands[1];
2290 rtx bytes_rtx = operands[2];
2291 rtx align_rtx = operands[3];
2292 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2305 rtx stores[MAX_MOVE_REG];
2307 enum machine_mode mode;
2309 /* If this is not a fixed size move, just call memcpy. */
2313 /* This should be a fixed size alignment. */
2314 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2316 align = INTVAL (align_rtx);
2318 /* Anything to move? */
2319 bytes = INTVAL (bytes_rtx);
2323 /* Don't support real large moves. */
2324 if (bytes > TOTAL_MOVE_REG*align)
2327 /* Move the address into scratch registers. */
2328 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2329 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2331 num_reg = offset = 0;
2332 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2334 /* Calculate the correct offset for src/dest. */
2338 dest_addr = dest_reg;
2342 src_addr = plus_constant (src_reg, offset);
2343 dest_addr = plus_constant (dest_reg, offset);
2346 /* Generate the appropriate load and store, saving the stores
2348 if (bytes >= 4 && align >= 4)
2350 else if (bytes >= 2 && align >= 2)
2355 move_bytes = GET_MODE_SIZE (mode);
2356 tmp_reg = gen_reg_rtx (mode);
2357 src_mem = change_address (orig_src, mode, src_addr);
2358 dest_mem = change_address (orig_dest, mode, dest_addr);
2359 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2360 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2362 if (num_reg >= MAX_MOVE_REG)
2364 for (i = 0; i < num_reg; i++)
2365 emit_insn (stores[i]);
2370 for (i = 0; i < num_reg; i++)
2371 emit_insn (stores[i]);
2377 /* Expand a block clear operation, and return 1 if successful. Return 0
2378 if we should let the compiler generate normal code.
2380 operands[0] is the destination
2381 operands[1] is the length
2382 operands[3] is the alignment */
2385 frv_expand_block_clear (rtx operands[])
2387 rtx orig_dest = operands[0];
2388 rtx bytes_rtx = operands[1];
2389 rtx align_rtx = operands[3];
2390 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2399 enum machine_mode mode;
2401 /* If this is not a fixed size move, just call memcpy. */
2405 /* This should be a fixed size alignment. */
2406 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2408 align = INTVAL (align_rtx);
2410 /* Anything to move? */
2411 bytes = INTVAL (bytes_rtx);
2415 /* Don't support real large clears. */
2416 if (bytes > TOTAL_MOVE_REG*align)
2419 /* Move the address into a scratch register. */
2420 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2422 num_reg = offset = 0;
2423 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2425 /* Calculate the correct offset for src/dest. */
2426 dest_addr = ((offset == 0)
2428 : plus_constant (dest_reg, offset));
2430 /* Generate the appropriate store of gr0. */
2431 if (bytes >= 4 && align >= 4)
2433 else if (bytes >= 2 && align >= 2)
2438 clear_bytes = GET_MODE_SIZE (mode);
2439 dest_mem = change_address (orig_dest, mode, dest_addr);
2440 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2447 /* The following variable is used to output modifiers of assembler
2448 code of the current output insn. */
2450 static rtx *frv_insn_operands;
2452 /* The following function is used to add assembler insn code suffix .p
2453 if it is necessary. */
2456 frv_asm_output_opcode (FILE *f, const char *ptr)
2460 if (frv_insn_packing_flag <= 0)
2463 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2466 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2467 || (*ptr >= 'A' && *ptr <= 'Z')))
2469 int letter = *ptr++;
2472 frv_print_operand (f, frv_insn_operands [c], letter);
2473 while ((c = *ptr) >= '0' && c <= '9')
2485 /* Set up the packing bit for the current output insn. Note that this
2486 function is not called for asm insns. */
2489 frv_final_prescan_insn (rtx insn, rtx *opvec,
2490 int noperands ATTRIBUTE_UNUSED)
2494 if (frv_insn_packing_flag >= 0)
2496 frv_insn_operands = opvec;
2497 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2499 else if (recog_memoized (insn) >= 0
2500 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2501 /* Packing optimizations have been disabled, but INSN can only
2502 be issued in M1. Insert an mnop in M0. */
2503 fprintf (asm_out_file, "\tmnop.p\n");
2509 /* A C expression whose value is RTL representing the address in a stack frame
2510 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2511 an RTL expression for the address of the stack frame itself.
2513 If you don't define this macro, the default is to return the value of
2514 FRAMEADDR--that is, the stack frame address is also the address of the stack
2515 word that points to the previous frame. */
2517 /* The default is correct, but we need to make sure the frame gets created. */
2519 frv_dynamic_chain_address (rtx frame)
2521 cfun->machine->frame_needed = 1;
2526 /* A C expression whose value is RTL representing the value of the return
2527 address for the frame COUNT steps up from the current frame, after the
2528 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2529 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2532 The value of the expression must always be the correct address when COUNT is
2533 zero, but may be `NULL_RTX' if there is not way to determine the return
2534 address of other frames. */
2537 frv_return_addr_rtx (int count, rtx frame)
2541 cfun->machine->frame_needed = 1;
2542 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2545 /* Given a memory reference MEMREF, interpret the referenced memory as
2546 an array of MODE values, and return a reference to the element
2547 specified by INDEX. Assume that any pre-modification implicit in
2548 MEMREF has already happened.
2550 MEMREF must be a legitimate operand for modes larger than SImode.
2551 frv_legitimate_address_p forbids register+register addresses, which
2552 this function cannot handle. */
2554 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2556 rtx base = XEXP (memref, 0);
2557 if (GET_CODE (base) == PRE_MODIFY)
2558 base = XEXP (base, 0);
2559 return change_address (memref, mode,
2560 plus_constant (base, index * GET_MODE_SIZE (mode)));
2564 /* Print a memory address as an operand to reference that memory location. */
2566 frv_print_operand_address (FILE * stream, rtx x)
2568 if (GET_CODE (x) == MEM)
2571 switch (GET_CODE (x))
2574 fputs (reg_names [ REGNO (x)], stream);
2578 fprintf (stream, "%ld", (long) INTVAL (x));
2582 assemble_name (stream, XSTR (x, 0));
2587 output_addr_const (stream, x);
2591 /* Poorly constructed asm statements can trigger this alternative.
2592 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2593 frv_print_operand_memory_reference (stream, x, 0);
2600 fatal_insn ("bad insn to frv_print_operand_address:", x);
2605 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2607 int regno = true_regnum (x);
2609 fputs (reg_names[regno], stream);
2611 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2614 /* Print a memory reference suitable for the ld/st instructions. */
2617 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2619 struct frv_unspec unspec;
2623 switch (GET_CODE (x))
2630 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2632 x1 = XEXP (XEXP (x, 1), 1);
2642 if (GET_CODE (x0) == CONST_INT)
2650 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2659 else if (GET_CODE (x1) != CONST_INT)
2660 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2663 fputs ("@(", stream);
2665 fputs (reg_names[GPR_R0], stream);
2666 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2667 frv_print_operand_memory_reference_reg (stream, x0);
2669 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2671 fputs (",", stream);
2673 fputs (reg_names [GPR_R0], stream);
2677 switch (GET_CODE (x1))
2681 frv_print_operand_memory_reference_reg (stream, x1);
2685 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2689 if (!frv_const_unspec_p (x1, &unspec))
2690 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2691 frv_output_const_unspec (stream, &unspec);
2695 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2699 fputs (")", stream);
2703 /* Return 2 for likely branches and 0 for non-likely branches */
2705 #define FRV_JUMP_LIKELY 2
2706 #define FRV_JUMP_NOT_LIKELY 0
2709 frv_print_operand_jump_hint (rtx insn)
2714 HOST_WIDE_INT prob = -1;
2715 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2717 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2719 /* Assume any non-conditional jump is likely. */
2720 if (! any_condjump_p (insn))
2721 ret = FRV_JUMP_LIKELY;
2725 labelref = condjump_label (insn);
2728 rtx label = XEXP (labelref, 0);
2729 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2734 note = find_reg_note (insn, REG_BR_PROB, 0);
2736 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2740 prob = INTVAL (XEXP (note, 0));
2741 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2743 : FRV_JUMP_NOT_LIKELY);
2755 case UNKNOWN: direction = "unknown jump direction"; break;
2756 case BACKWARD: direction = "jump backward"; break;
2757 case FORWARD: direction = "jump forward"; break;
2761 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2762 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2763 (long)INSN_UID (insn), direction, (long)prob,
2764 (long)REG_BR_PROB_BASE, ret);
2772 /* Return the comparison operator to use for CODE given that the ICC
2776 comparison_string (enum rtx_code code, rtx op0)
2778 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2781 default: output_operand_lossage ("bad condition code");
2782 case EQ: return "eq";
2783 case NE: return "ne";
2784 case LT: return is_nz_p ? "n" : "lt";
2785 case LE: return "le";
2786 case GT: return "gt";
2787 case GE: return is_nz_p ? "p" : "ge";
2788 case LTU: return is_nz_p ? "no" : "c";
2789 case LEU: return is_nz_p ? "eq" : "ls";
2790 case GTU: return is_nz_p ? "ne" : "hi";
2791 case GEU: return is_nz_p ? "ra" : "nc";
2795 /* Print an operand to an assembler instruction.
2797 `%' followed by a letter and a digit says to output an operand in an
2798 alternate fashion. Four letters have standard, built-in meanings described
2799 below. The machine description macro `PRINT_OPERAND' can define additional
2800 letters with nonstandard meanings.
2802 `%cDIGIT' can be used to substitute an operand that is a constant value
2803 without the syntax that normally indicates an immediate operand.
2805 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2808 `%aDIGIT' can be used to substitute an operand as if it were a memory
2809 reference, with the actual operand treated as the address. This may be
2810 useful when outputting a "load address" instruction, because often the
2811 assembler syntax for such an instruction requires you to write the operand
2812 as if it were a memory reference.
2814 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2816 `%=' outputs a number which is unique to each instruction in the entire
2817 compilation. This is useful for making local labels to be referred to more
2818 than once in a single template that generates multiple assembler
2821 `%' followed by a punctuation character specifies a substitution that does
2822 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2823 assembler code. Other nonstandard cases can be defined in the
2824 `PRINT_OPERAND' macro. You must also define which punctuation characters
2825 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2828 frv_print_operand (FILE * file, rtx x, int code)
2830 struct frv_unspec unspec;
2831 HOST_WIDE_INT value;
2834 if (code != 0 && !ISALPHA (code))
2837 else if (GET_CODE (x) == CONST_INT)
2840 else if (GET_CODE (x) == CONST_DOUBLE)
2842 if (GET_MODE (x) == SFmode)
2847 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2848 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2852 else if (GET_MODE (x) == VOIDmode)
2853 value = CONST_DOUBLE_LOW (x);
2856 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2867 fputs (reg_names[GPR_R0], file);
2871 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2875 /* Output small data area base register (gr16). */
2876 fputs (reg_names[SDA_BASE_REG], file);
2880 /* Output pic register (gr17). */
2881 fputs (reg_names[PIC_REGNO], file);
2885 /* Output the temporary integer CCR register. */
2886 fputs (reg_names[ICR_TEMP], file);
2890 /* Output the temporary integer CC register. */
2891 fputs (reg_names[ICC_TEMP], file);
2894 /* case 'a': print an address. */
2897 /* Print appropriate test for integer branch false operation. */
2898 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2899 XEXP (x, 0)), file);
2903 /* Print appropriate test for integer branch true operation. */
2904 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2908 /* Print 1 for a NE and 0 for an EQ to give the final argument
2909 for a conditional instruction. */
2910 if (GET_CODE (x) == NE)
2913 else if (GET_CODE (x) == EQ)
2917 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2921 /* Print appropriate test for floating point branch false operation. */
2922 switch (GET_CODE (x))
2925 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2927 case EQ: fputs ("ne", file); break;
2928 case NE: fputs ("eq", file); break;
2929 case LT: fputs ("uge", file); break;
2930 case LE: fputs ("ug", file); break;
2931 case GT: fputs ("ule", file); break;
2932 case GE: fputs ("ul", file); break;
2937 /* Print appropriate test for floating point branch true operation. */
2938 switch (GET_CODE (x))
2941 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2943 case EQ: fputs ("eq", file); break;
2944 case NE: fputs ("ne", file); break;
2945 case LT: fputs ("lt", file); break;
2946 case LE: fputs ("le", file); break;
2947 case GT: fputs ("gt", file); break;
2948 case GE: fputs ("ge", file); break;
2953 /* Print appropriate GOT function. */
2954 if (GET_CODE (x) != CONST_INT)
2955 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2956 fputs (unspec_got_name (INTVAL (x)), file);
2960 /* Print 'i' if the operand is a constant, or is a memory reference that
2962 if (GET_CODE (x) == MEM)
2963 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2964 ? XEXP (XEXP (x, 0), 1)
2966 else if (GET_CODE (x) == PLUS)
2969 switch (GET_CODE (x))
2983 /* For jump instructions, print 'i' if the operand is a constant or
2984 is an expression that adds a constant. */
2985 if (GET_CODE (x) == CONST_INT)
2990 if (GET_CODE (x) == CONST_INT
2991 || (GET_CODE (x) == PLUS
2992 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2993 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2999 /* Print the lower register of a double word register pair */
3000 if (GET_CODE (x) == REG)
3001 fputs (reg_names[ REGNO (x)+1 ], file);
3003 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
3006 /* case 'l': print a LABEL_REF. */
3010 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
3011 for the second word of double memory operations. */
3012 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3013 switch (GET_CODE (x))
3016 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3019 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3027 frv_print_operand_memory_reference (file, x, offset);
3033 /* Print the opcode of a command. */
3034 switch (GET_CODE (x))
3037 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3039 case PLUS: fputs ("add", file); break;
3040 case MINUS: fputs ("sub", file); break;
3041 case AND: fputs ("and", file); break;
3042 case IOR: fputs ("or", file); break;
3043 case XOR: fputs ("xor", file); break;
3044 case ASHIFT: fputs ("sll", file); break;
3045 case ASHIFTRT: fputs ("sra", file); break;
3046 case LSHIFTRT: fputs ("srl", file); break;
3050 /* case 'n': negate and print a constant int. */
3053 /* Print PIC label using operand as the number. */
3054 if (GET_CODE (x) != CONST_INT)
3055 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3057 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3061 /* Print 'u' if the operand is a update load/store. */
3062 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3067 /* If value is 0, print gr0, otherwise it must be a register. */
3068 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3069 fputs (reg_names[GPR_R0], file);
3071 else if (GET_CODE (x) == REG)
3072 fputs (reg_names [REGNO (x)], file);
3075 fatal_insn ("bad insn in frv_print_operand, z case", x);
3079 /* Print constant in hex. */
3080 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3082 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3089 if (GET_CODE (x) == REG)
3090 fputs (reg_names [REGNO (x)], file);
3092 else if (GET_CODE (x) == CONST_INT
3093 || GET_CODE (x) == CONST_DOUBLE)
3094 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3096 else if (frv_const_unspec_p (x, &unspec))
3097 frv_output_const_unspec (file, &unspec);
3099 else if (GET_CODE (x) == MEM)
3100 frv_print_operand_address (file, XEXP (x, 0));
3102 else if (CONSTANT_ADDRESS_P (x))
3103 frv_print_operand_address (file, x);
3106 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3111 fatal_insn ("frv_print_operand: unknown code", x);
3119 /* A C statement (sans semicolon) for initializing the variable CUM for the
3120 state at the beginning of the argument list. The variable has type
3121 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3122 of the function which will receive the args, or 0 if the args are to a
3123 compiler support library function. The value of INDIRECT is nonzero when
3124 processing an indirect call, for example a call through a function pointer.
3125 The value of INDIRECT is zero for a call to an explicitly named function, a
3126 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3127 arguments for the function being compiled.
3129 When processing a call to a compiler support library function, LIBNAME
3130 identifies which one. It is a `symbol_ref' rtx which contains the name of
3131 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3132 being processed. Thus, each time this macro is called, either LIBNAME or
3133 FNTYPE is nonzero, but never both of them at once. */
3136 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3142 *cum = FIRST_ARG_REGNUM;
3144 if (TARGET_DEBUG_ARG)
3146 fprintf (stderr, "\ninit_cumulative_args:");
3147 if (!fndecl && fntype)
3148 fputs (" indirect", stderr);
3151 fputs (" incoming", stderr);
3155 tree ret_type = TREE_TYPE (fntype);
3156 fprintf (stderr, " return=%s,",
3157 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3160 if (libname && GET_CODE (libname) == SYMBOL_REF)
3161 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3163 if (cfun->returns_struct)
3164 fprintf (stderr, " return-struct");
3166 putc ('\n', stderr);
3171 /* Return true if we should pass an argument on the stack rather than
3175 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3177 if (mode == BLKmode)
3181 return AGGREGATE_TYPE_P (type);
3184 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3185 argument with the specified mode and type. If it is not defined,
3186 `PARM_BOUNDARY' is used for all arguments. */
3189 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3190 tree type ATTRIBUTE_UNUSED)
3192 return BITS_PER_WORD;
3196 frv_function_arg (CUMULATIVE_ARGS *cum,
3197 enum machine_mode mode,
3198 tree type ATTRIBUTE_UNUSED,
3200 int incoming ATTRIBUTE_UNUSED)
3202 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3207 /* Return a marker for use in the call instruction. */
3208 if (xmode == VOIDmode)
3214 else if (arg_num <= LAST_ARG_REGNUM)
3216 ret = gen_rtx_REG (xmode, arg_num);
3217 debstr = reg_names[arg_num];
3226 if (TARGET_DEBUG_ARG)
3228 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3229 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3235 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3236 advance past an argument in the argument list. The values MODE, TYPE and
3237 NAMED describe that argument. Once this is done, the variable CUM is
3238 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3240 This macro need not do anything if the argument in question was passed on
3241 the stack. The compiler knows how to track the amount of stack space used
3242 for arguments without any special help. */
3245 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3246 enum machine_mode mode,
3247 tree type ATTRIBUTE_UNUSED,
3250 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3251 int bytes = GET_MODE_SIZE (xmode);
3252 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3255 *cum = arg_num + words;
3257 if (TARGET_DEBUG_ARG)
3259 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3260 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3264 /* A C expression for the number of words, at the beginning of an argument,
3265 must be put in registers. The value must be zero for arguments that are
3266 passed entirely in registers or that are entirely pushed on the stack.
3268 On some machines, certain arguments must be passed partially in registers
3269 and partially in memory. On these machines, typically the first N words of
3270 arguments are passed in registers, and the rest on the stack. If a
3271 multi-word argument (a `double' or a structure) crosses that boundary, its
3272 first few words must be passed in registers and the rest must be pushed.
3273 This macro tells the compiler when this occurs, and how many of the words
3274 should go in registers.
3276 `FUNCTION_ARG' for these arguments should return the first register to be
3277 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3278 the called function. */
3281 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3282 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3284 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3285 int bytes = GET_MODE_SIZE (xmode);
3286 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3290 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3291 ? LAST_ARG_REGNUM - arg_num + 1
3293 ret *= UNITS_PER_WORD;
3295 if (TARGET_DEBUG_ARG && ret)
3296 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3302 /* Implements TARGET_FUNCTION_VALUE. */
3305 frv_function_value (const_tree valtype,
3306 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3307 bool outgoing ATTRIBUTE_UNUSED)
3309 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3313 /* Implements TARGET_LIBCALL_VALUE. */
3316 frv_libcall_value (enum machine_mode mode,
3317 const_rtx fun ATTRIBUTE_UNUSED)
3319 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3323 /* Implements FUNCTION_VALUE_REGNO_P. */
3326 frv_function_value_regno_p (const unsigned int regno)
3328 return (regno == RETURN_VALUE_REGNUM);
3331 /* Return true if a register is ok to use as a base or index register. */
3333 static FRV_INLINE int
3334 frv_regno_ok_for_base_p (int regno, int strict_p)
3340 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3342 if (regno == ARG_POINTER_REGNUM)
3345 return (regno >= FIRST_PSEUDO_REGISTER);
3349 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3350 RTX) is a legitimate memory address on the target machine for a memory
3351 operand of mode MODE.
3353 It usually pays to define several simpler macros to serve as subroutines for
3354 this one. Otherwise it may be too complicated to understand.
3356 This macro must exist in two variants: a strict variant and a non-strict
3357 one. The strict variant is used in the reload pass. It must be defined so
3358 that any pseudo-register that has not been allocated a hard register is
3359 considered a memory reference. In contexts where some kind of register is
3360 required, a pseudo-register with no hard register must be rejected.
3362 The non-strict variant is used in other passes. It must be defined to
3363 accept all pseudo-registers in every context where some kind of register is
3366 Compiler source files that want to use the strict variant of this macro
3367 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3368 conditional to define the strict variant in that case and the non-strict
3371 Normally, constant addresses which are the sum of a `symbol_ref' and an
3372 integer are stored inside a `const' RTX to mark them as constant.
3373 Therefore, there is no need to recognize such sums specifically as
3374 legitimate addresses. Normally you would simply recognize any `const' as
3377 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3378 are not marked with `const'. It assumes that a naked `plus' indicates
3379 indexing. If so, then you *must* reject such naked constant sums as
3380 illegitimate addresses, so that none of them will be given to
3381 `PRINT_OPERAND_ADDRESS'. */
3384 frv_legitimate_address_p_1 (enum machine_mode mode,
3388 int allow_double_reg_p)
3392 HOST_WIDE_INT value;
3395 if (FRV_SYMBOL_REF_TLS_P (x))
3398 switch (GET_CODE (x))
3405 if (GET_CODE (x) != REG)
3411 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3417 if (GET_CODE (x0) != REG
3418 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3419 || GET_CODE (x1) != PLUS
3420 || ! rtx_equal_p (x0, XEXP (x1, 0))
3421 || GET_CODE (XEXP (x1, 1)) != REG
3422 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3429 /* 12-bit immediate */
3434 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3436 /* If we can't use load/store double operations, make sure we can
3437 address the second word. */
3438 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3439 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3448 if (GET_CODE (x0) == SUBREG)
3449 x0 = SUBREG_REG (x0);
3451 if (GET_CODE (x0) != REG)
3454 regno0 = REGNO (x0);
3455 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3458 switch (GET_CODE (x1))
3464 x1 = SUBREG_REG (x1);
3465 if (GET_CODE (x1) != REG)
3471 /* Do not allow reg+reg addressing for modes > 1 word if we
3472 can't depend on having move double instructions. */
3473 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3476 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3480 /* 12-bit immediate */
3485 value = INTVAL (x1);
3486 ret = IN_RANGE_P (value, -2048, 2047);
3488 /* If we can't use load/store double operations, make sure we can
3489 address the second word. */
3490 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3491 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3496 if (!condexec_p && got12_operand (x1, VOIDmode))
3504 if (TARGET_DEBUG_ADDR)
3506 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3507 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3508 (condexec_p) ? ", inside conditional code" : "");
3516 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3518 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3521 /* Given an ADDR, generate code to inline the PLT. */
3523 gen_inlined_tls_plt (rtx addr)
3526 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3529 dest = gen_reg_rtx (DImode);
3536 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3537 calll #gettlsoff(ADDR)@(gr8, gr0)
3539 emit_insn (gen_tls_lddi (dest, addr, picreg));
3546 sethi.p #gottlsdeschi(ADDR), gr8
3547 setlo #gottlsdesclo(ADDR), gr8
3548 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3549 calll #gettlsoff(ADDR)@(gr8, gr0)
3551 rtx reguse = gen_reg_rtx (Pmode);
3552 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3553 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3556 retval = gen_reg_rtx (Pmode);
3557 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3561 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3562 the destination address. */
3564 gen_tlsmoff (rtx addr, rtx reg)
3566 rtx dest = gen_reg_rtx (Pmode);
3570 /* sethi.p #tlsmoffhi(x), grA
3571 setlo #tlsmofflo(x), grA
3573 dest = gen_reg_rtx (Pmode);
3574 emit_insn (gen_tlsoff_hilo (dest, addr,
3575 GEN_INT (R_FRV_TLSMOFFHI)));
3576 dest = gen_rtx_PLUS (Pmode, dest, reg);
3580 /* addi grB, #tlsmoff12(x), grC
3582 ld/st @(grB, #tlsmoff12(x)), grC
3584 dest = gen_reg_rtx (Pmode);
3585 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3586 GEN_INT (R_FRV_TLSMOFF12)));
3591 /* Generate code for a TLS address. */
3593 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3595 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3596 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3600 case TLS_MODEL_INITIAL_EXEC:
3604 ldi @(gr15, #gottlsoff12(x)), gr5
3606 dest = gen_reg_rtx (Pmode);
3607 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3608 dest = gen_rtx_PLUS (Pmode, tp, dest);
3612 /* -fPIC or anything else.
3614 sethi.p #gottlsoffhi(x), gr14
3615 setlo #gottlsofflo(x), gr14
3616 ld #tlsoff(x)@(gr15, gr14), gr9
3618 rtx tmp = gen_reg_rtx (Pmode);
3619 dest = gen_reg_rtx (Pmode);
3620 emit_insn (gen_tlsoff_hilo (tmp, addr,
3621 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3623 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3624 dest = gen_rtx_PLUS (Pmode, tp, dest);
3627 case TLS_MODEL_LOCAL_DYNAMIC:
3631 if (TARGET_INLINE_PLT)
3632 retval = gen_inlined_tls_plt (GEN_INT (0));
3635 /* call #gettlsoff(0) */
3636 retval = gen_reg_rtx (Pmode);
3637 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3640 reg = gen_reg_rtx (Pmode);
3641 emit_insn (gen_rtx_SET (VOIDmode, reg,
3642 gen_rtx_PLUS (Pmode,
3645 dest = gen_tlsmoff (addr, reg);
3648 dest = gen_reg_rtx (Pmode);
3649 emit_insn (gen_tlsoff_hilo (dest, addr,
3650 GEN_INT (R_FRV_TLSMOFFHI)));
3651 dest = gen_rtx_PLUS (Pmode, dest, reg);
3655 case TLS_MODEL_LOCAL_EXEC:
3656 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3658 case TLS_MODEL_GLOBAL_DYNAMIC:
3662 if (TARGET_INLINE_PLT)
3663 retval = gen_inlined_tls_plt (addr);
3666 /* call #gettlsoff(x) */
3667 retval = gen_reg_rtx (Pmode);
3668 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3670 dest = gen_rtx_PLUS (Pmode, retval, tp);
3681 frv_legitimize_address (rtx x,
3682 rtx oldx ATTRIBUTE_UNUSED,
3683 enum machine_mode mode ATTRIBUTE_UNUSED)
3685 if (GET_CODE (x) == SYMBOL_REF)
3687 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3689 return frv_legitimize_tls_address (x, model);
3695 /* Test whether a local function descriptor is canonical, i.e.,
3696 whether we can use FUNCDESC_GOTOFF to compute the address of the
3700 frv_local_funcdesc_p (rtx fnx)
3703 enum symbol_visibility vis;
3706 if (! SYMBOL_REF_LOCAL_P (fnx))
3709 fn = SYMBOL_REF_DECL (fnx);
3714 vis = DECL_VISIBILITY (fn);
3716 if (vis == VISIBILITY_PROTECTED)
3717 /* Private function descriptors for protected functions are not
3718 canonical. Temporarily change the visibility to global. */
3719 vis = VISIBILITY_DEFAULT;
3720 else if (flag_shlib)
3721 /* If we're already compiling for a shared library (that, unlike
3722 executables, can't assume that the existence of a definition
3723 implies local binding), we can skip the re-testing. */
3726 ret = default_binds_local_p_1 (fn, flag_pic);
3728 DECL_VISIBILITY (fn) = vis;
3733 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3737 frv_gen_GPsym2reg (rtx dest, rtx src)
3739 tree gp = get_identifier ("_gp");
3740 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3742 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3746 unspec_got_name (int i)
3750 case R_FRV_GOT12: return "got12";
3751 case R_FRV_GOTHI: return "gothi";
3752 case R_FRV_GOTLO: return "gotlo";
3753 case R_FRV_FUNCDESC: return "funcdesc";
3754 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3755 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3756 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3757 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3758 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3759 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3760 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3761 case R_FRV_GOTOFF12: return "gotoff12";
3762 case R_FRV_GOTOFFHI: return "gotoffhi";
3763 case R_FRV_GOTOFFLO: return "gotofflo";
3764 case R_FRV_GPREL12: return "gprel12";
3765 case R_FRV_GPRELHI: return "gprelhi";
3766 case R_FRV_GPRELLO: return "gprello";
3767 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3768 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3769 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3770 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3771 case R_FRV_TLSMOFF12: return "tlsmoff12";
3772 case R_FRV_TLSDESCHI: return "tlsdeschi";
3773 case R_FRV_TLSDESCLO: return "tlsdesclo";
3774 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3775 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3776 default: gcc_unreachable ();
3780 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3781 is added inside the relocation operator. */
3784 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3786 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3787 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3788 fputs (")", stream);
3791 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3792 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3793 otherwise return ORIG_X. */
3796 frv_find_base_term (rtx x)
3798 struct frv_unspec unspec;
3800 if (frv_const_unspec_p (x, &unspec)
3801 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3802 return plus_constant (unspec.symbol, unspec.offset);
3807 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3808 the operand is used by a predicated instruction. */
3811 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3813 return ((GET_MODE (op) == mode || mode == VOIDmode)
3814 && GET_CODE (op) == MEM
3815 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3816 reload_completed, condexec_p, FALSE));
3820 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3822 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3823 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3829 rvrtx = operands[0];
3833 addr = XEXP (operands[0], 0);
3835 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3836 any calls that would involve a PLT, but can't tell, since we
3837 don't know whether an extern function is going to be provided by
3838 a separate translation unit or imported from a separate module.
3839 When compiling for shared libraries, if the function has default
3840 visibility, we assume it's overridable, so we inline the PLT, but
3841 for executables, we don't really have a way to make a good
3842 decision: a function is as likely to be imported from a shared
3843 library as it is to be defined in the executable itself. We
3844 assume executables will get global functions defined locally,
3845 whereas shared libraries will have them potentially overridden,
3846 so we only inline PLTs when compiling for shared libraries.
3848 In order to mark a function as local to a shared library, any
3849 non-default visibility attribute suffices. Unfortunately,
3850 there's no simple way to tag a function declaration as ``in a
3851 different module'', which we could then use to trigger PLT
3852 inlining on executables. There's -minline-plt, but it affects
3853 all external functions, so one would have to also mark function
3854 declarations available in the same module with non-default
3855 visibility, which is advantageous in itself. */
3856 if (GET_CODE (addr) == SYMBOL_REF
3857 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3861 dest = gen_reg_rtx (SImode);
3863 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3864 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3866 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3867 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3869 crtl->uses_pic_offset_table = TRUE;
3872 else if (GET_CODE (addr) == SYMBOL_REF)
3874 /* These are always either local, or handled through a local
3877 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3878 operands[2], picreg, lr);
3880 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3884 else if (! ldd_address_operand (addr, Pmode))
3885 addr = force_reg (Pmode, addr);
3887 picreg = gen_reg_rtx (DImode);
3888 emit_insn (gen_movdi_ldd (picreg, addr));
3890 if (sibcall && ret_value)
3891 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3893 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3895 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3897 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3901 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3902 process these separately from any offsets, such that we add any
3903 offsets to the function descriptor (the actual pointer), not to the
3904 function address. */
3907 frv_function_symbol_referenced_p (rtx x)
3913 if (GET_CODE (x) == SYMBOL_REF)
3914 return SYMBOL_REF_FUNCTION_P (x);
3916 length = GET_RTX_LENGTH (GET_CODE (x));
3917 format = GET_RTX_FORMAT (GET_CODE (x));
3919 for (j = 0; j < length; ++j)
3924 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3930 if (XVEC (x, j) != 0)
3933 for (k = 0; k < XVECLEN (x, j); ++k)
3934 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3940 /* Nothing to do. */
3948 /* Return true if the memory operand is one that can be conditionally
3952 condexec_memory_operand (rtx op, enum machine_mode mode)
3954 enum machine_mode op_mode = GET_MODE (op);
3957 if (mode != VOIDmode && op_mode != mode)
3972 if (GET_CODE (op) != MEM)
3975 addr = XEXP (op, 0);
3976 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3979 /* Return true if the bare return instruction can be used outside of the
3980 epilog code. For frv, we only do it if there was no stack allocation. */
3983 direct_return_p (void)
3987 if (!reload_completed)
3990 info = frv_stack_info ();
3991 return (info->total_size == 0);
3996 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3998 if (GET_CODE (src) == SYMBOL_REF)
4000 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
4002 src = frv_legitimize_tls_address (src, model);
4008 if (frv_emit_movsi (dest, src))
4017 if (!reload_in_progress
4018 && !reload_completed
4019 && !register_operand (dest, mode)
4020 && !reg_or_0_operand (src, mode))
4021 src = copy_to_mode_reg (mode, src);
4028 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4031 /* Emit code to handle a MOVSI, adding in the small data register or pic
4032 register if needed to load up addresses. Return TRUE if the appropriate
4033 instructions are emitted. */
4036 frv_emit_movsi (rtx dest, rtx src)
4038 int base_regno = -1;
4041 struct frv_unspec old_unspec;
4043 if (!reload_in_progress
4044 && !reload_completed
4045 && !register_operand (dest, SImode)
4046 && (!reg_or_0_operand (src, SImode)
4047 /* Virtual registers will almost always be replaced by an
4048 add instruction, so expose this to CSE by copying to
4049 an intermediate register. */
4050 || (GET_CODE (src) == REG
4051 && IN_RANGE_P (REGNO (src),
4052 FIRST_VIRTUAL_REGISTER,
4053 LAST_VIRTUAL_REGISTER))))
4055 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4059 /* Explicitly add in the PIC or small data register if needed. */
4060 switch (GET_CODE (src))
4069 /* Using GPREL12, we use a single GOT entry for all symbols
4070 in read-only sections, but trade sequences such as:
4072 sethi #gothi(label), gr#
4073 setlo #gotlo(label), gr#
4078 ld @(gr15,#got12(_gp)), gr#
4079 sethi #gprelhi(label), gr##
4080 setlo #gprello(label), gr##
4083 We may often be able to share gr# for multiple
4084 computations of GPREL addresses, and we may often fold
4085 the final add into the pair of registers of a load or
4086 store instruction, so it's often profitable. Even when
4087 optimizing for size, we're trading a GOT entry for an
4088 additional instruction, which trades GOT space
4089 (read-write) for code size (read-only, shareable), as
4090 long as the symbol is not used in more than two different
4093 With -fpie/-fpic, we'd be trading a single load for a
4094 sequence of 4 instructions, because the offset of the
4095 label can't be assumed to be addressable with 12 bits, so
4096 we don't do this. */
4097 if (TARGET_GPREL_RO)
4098 unspec = R_FRV_GPREL12;
4100 unspec = R_FRV_GOT12;
4103 base_regno = PIC_REGNO;
4108 if (frv_const_unspec_p (src, &old_unspec))
4111 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4114 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4115 emit_move_insn (dest, src);
4120 sym = XEXP (sym, 0);
4121 if (GET_CODE (sym) == PLUS
4122 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4123 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4124 sym = XEXP (sym, 0);
4125 if (GET_CODE (sym) == SYMBOL_REF)
4127 else if (GET_CODE (sym) == LABEL_REF)
4130 goto handle_whatever;
4138 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4142 src = frv_legitimize_tls_address (src, model);
4143 emit_move_insn (dest, src);
4147 if (SYMBOL_REF_FUNCTION_P (sym))
4149 if (frv_local_funcdesc_p (sym))
4150 unspec = R_FRV_FUNCDESC_GOTOFF12;
4152 unspec = R_FRV_FUNCDESC_GOT12;
4156 if (CONSTANT_POOL_ADDRESS_P (sym))
4157 switch (GET_CODE (get_pool_constant (sym)))
4164 unspec = R_FRV_GOTOFF12;
4169 if (TARGET_GPREL_RO)
4170 unspec = R_FRV_GPREL12;
4172 unspec = R_FRV_GOT12;
4175 else if (SYMBOL_REF_LOCAL_P (sym)
4176 && !SYMBOL_REF_EXTERNAL_P (sym)
4177 && SYMBOL_REF_DECL (sym)
4178 && (!DECL_P (SYMBOL_REF_DECL (sym))
4179 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4181 tree decl = SYMBOL_REF_DECL (sym);
4182 tree init = TREE_CODE (decl) == VAR_DECL
4183 ? DECL_INITIAL (decl)
4184 : TREE_CODE (decl) == CONSTRUCTOR
4187 bool named_section, readonly;
4189 if (init && init != error_mark_node)
4190 reloc = compute_reloc_for_constant (init);
4192 named_section = TREE_CODE (decl) == VAR_DECL
4193 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4194 readonly = decl_readonly_section (decl, reloc);
4197 unspec = R_FRV_GOT12;
4199 unspec = R_FRV_GOTOFF12;
4200 else if (readonly && TARGET_GPREL_RO)
4201 unspec = R_FRV_GPREL12;
4203 unspec = R_FRV_GOT12;
4206 unspec = R_FRV_GOT12;
4210 else if (SYMBOL_REF_SMALL_P (sym))
4211 base_regno = SDA_BASE_REG;
4214 base_regno = PIC_REGNO;
4219 if (base_regno >= 0)
4221 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4222 emit_insn (gen_symGOTOFF2reg (dest, src,
4223 gen_rtx_REG (Pmode, base_regno),
4224 GEN_INT (R_FRV_GPREL12)));
4226 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4227 gen_rtx_REG (Pmode, base_regno),
4228 GEN_INT (R_FRV_GPREL12)));
4229 if (base_regno == PIC_REGNO)
4230 crtl->uses_pic_offset_table = TRUE;
4238 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4239 new uses of it once reload has begun. */
4240 gcc_assert (!reload_in_progress && !reload_completed);
4244 case R_FRV_GOTOFF12:
4245 if (!frv_small_data_reloc_p (sym, unspec))
4246 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4249 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4252 if (!frv_small_data_reloc_p (sym, unspec))
4253 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4256 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4258 case R_FRV_FUNCDESC_GOTOFF12:
4260 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4263 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4267 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4270 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4274 crtl->uses_pic_offset_table = TRUE;
4283 /* Return a string to output a single word move. */
4286 output_move_single (rtx operands[], rtx insn)
4288 rtx dest = operands[0];
4289 rtx src = operands[1];
4291 if (GET_CODE (dest) == REG)
4293 int dest_regno = REGNO (dest);
4294 enum machine_mode mode = GET_MODE (dest);
4296 if (GPR_P (dest_regno))
4298 if (GET_CODE (src) == REG)
4300 /* gpr <- some sort of register */
4301 int src_regno = REGNO (src);
4303 if (GPR_P (src_regno))
4304 return "mov %1, %0";
4306 else if (FPR_P (src_regno))
4307 return "movfg %1, %0";
4309 else if (SPR_P (src_regno))
4310 return "movsg %1, %0";
4313 else if (GET_CODE (src) == MEM)
4322 return "ldsb%I1%U1 %M1,%0";
4325 return "ldsh%I1%U1 %M1,%0";
4329 return "ld%I1%U1 %M1, %0";
4333 else if (GET_CODE (src) == CONST_INT
4334 || GET_CODE (src) == CONST_DOUBLE)
4336 /* gpr <- integer/floating constant */
4337 HOST_WIDE_INT value;
4339 if (GET_CODE (src) == CONST_INT)
4340 value = INTVAL (src);
4342 else if (mode == SFmode)
4347 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4348 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4353 value = CONST_DOUBLE_LOW (src);
4355 if (IN_RANGE_P (value, -32768, 32767))
4356 return "setlos %1, %0";
4361 else if (GET_CODE (src) == SYMBOL_REF
4362 || GET_CODE (src) == LABEL_REF
4363 || GET_CODE (src) == CONST)
4369 else if (FPR_P (dest_regno))
4371 if (GET_CODE (src) == REG)
4373 /* fpr <- some sort of register */
4374 int src_regno = REGNO (src);
4376 if (GPR_P (src_regno))
4377 return "movgf %1, %0";
4379 else if (FPR_P (src_regno))
4381 if (TARGET_HARD_FLOAT)
4382 return "fmovs %1, %0";
4384 return "mor %1, %1, %0";
4388 else if (GET_CODE (src) == MEM)
4397 return "ldbf%I1%U1 %M1,%0";
4400 return "ldhf%I1%U1 %M1,%0";
4404 return "ldf%I1%U1 %M1, %0";
4408 else if (ZERO_P (src))
4409 return "movgf %., %0";
4412 else if (SPR_P (dest_regno))
4414 if (GET_CODE (src) == REG)
4416 /* spr <- some sort of register */
4417 int src_regno = REGNO (src);
4419 if (GPR_P (src_regno))
4420 return "movgs %1, %0";
4422 else if (ZERO_P (src))
4423 return "movgs %., %0";
4427 else if (GET_CODE (dest) == MEM)
4429 if (GET_CODE (src) == REG)
4431 int src_regno = REGNO (src);
4432 enum machine_mode mode = GET_MODE (dest);
4434 if (GPR_P (src_regno))
4442 return "stb%I0%U0 %1, %M0";
4445 return "sth%I0%U0 %1, %M0";
4449 return "st%I0%U0 %1, %M0";
4453 else if (FPR_P (src_regno))
4461 return "stbf%I0%U0 %1, %M0";
4464 return "sthf%I0%U0 %1, %M0";
4468 return "stf%I0%U0 %1, %M0";
4473 else if (ZERO_P (src))
4475 switch (GET_MODE (dest))
4481 return "stb%I0%U0 %., %M0";
4484 return "sth%I0%U0 %., %M0";
4488 return "st%I0%U0 %., %M0";
4493 fatal_insn ("bad output_move_single operand", insn);
4498 /* Return a string to output a double word move. */
4501 output_move_double (rtx operands[], rtx insn)
4503 rtx dest = operands[0];
4504 rtx src = operands[1];
4505 enum machine_mode mode = GET_MODE (dest);
4507 if (GET_CODE (dest) == REG)
4509 int dest_regno = REGNO (dest);
4511 if (GPR_P (dest_regno))
4513 if (GET_CODE (src) == REG)
4515 /* gpr <- some sort of register */
4516 int src_regno = REGNO (src);
4518 if (GPR_P (src_regno))
4521 else if (FPR_P (src_regno))
4523 if (((dest_regno - GPR_FIRST) & 1) == 0
4524 && ((src_regno - FPR_FIRST) & 1) == 0)
4525 return "movfgd %1, %0";
4531 else if (GET_CODE (src) == MEM)
4534 if (dbl_memory_one_insn_operand (src, mode))
4535 return "ldd%I1%U1 %M1, %0";
4540 else if (GET_CODE (src) == CONST_INT
4541 || GET_CODE (src) == CONST_DOUBLE)
4545 else if (FPR_P (dest_regno))
4547 if (GET_CODE (src) == REG)
4549 /* fpr <- some sort of register */
4550 int src_regno = REGNO (src);
4552 if (GPR_P (src_regno))
4554 if (((dest_regno - FPR_FIRST) & 1) == 0
4555 && ((src_regno - GPR_FIRST) & 1) == 0)
4556 return "movgfd %1, %0";
4561 else if (FPR_P (src_regno))
4564 && ((dest_regno - FPR_FIRST) & 1) == 0
4565 && ((src_regno - FPR_FIRST) & 1) == 0)
4566 return "fmovd %1, %0";
4572 else if (GET_CODE (src) == MEM)
4575 if (dbl_memory_one_insn_operand (src, mode))
4576 return "lddf%I1%U1 %M1, %0";
4581 else if (ZERO_P (src))
4586 else if (GET_CODE (dest) == MEM)
4588 if (GET_CODE (src) == REG)
4590 int src_regno = REGNO (src);
4592 if (GPR_P (src_regno))
4594 if (((src_regno - GPR_FIRST) & 1) == 0
4595 && dbl_memory_one_insn_operand (dest, mode))
4596 return "std%I0%U0 %1, %M0";
4601 if (FPR_P (src_regno))
4603 if (((src_regno - FPR_FIRST) & 1) == 0
4604 && dbl_memory_one_insn_operand (dest, mode))
4605 return "stdf%I0%U0 %1, %M0";
4611 else if (ZERO_P (src))
4613 if (dbl_memory_one_insn_operand (dest, mode))
4614 return "std%I0%U0 %., %M0";
4620 fatal_insn ("bad output_move_double operand", insn);
4625 /* Return a string to output a single word conditional move.
4626 Operand0 -- EQ/NE of ccr register and 0
4627 Operand1 -- CCR register
4628 Operand2 -- destination
4629 Operand3 -- source */
4632 output_condmove_single (rtx operands[], rtx insn)
4634 rtx dest = operands[2];
4635 rtx src = operands[3];
4637 if (GET_CODE (dest) == REG)
4639 int dest_regno = REGNO (dest);
4640 enum machine_mode mode = GET_MODE (dest);
4642 if (GPR_P (dest_regno))
4644 if (GET_CODE (src) == REG)
4646 /* gpr <- some sort of register */
4647 int src_regno = REGNO (src);
4649 if (GPR_P (src_regno))
4650 return "cmov %z3, %2, %1, %e0";
4652 else if (FPR_P (src_regno))
4653 return "cmovfg %3, %2, %1, %e0";
4656 else if (GET_CODE (src) == MEM)
4665 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4668 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4672 return "cld%I3%U3 %M3, %2, %1, %e0";
4676 else if (ZERO_P (src))
4677 return "cmov %., %2, %1, %e0";
4680 else if (FPR_P (dest_regno))
4682 if (GET_CODE (src) == REG)
4684 /* fpr <- some sort of register */
4685 int src_regno = REGNO (src);
4687 if (GPR_P (src_regno))
4688 return "cmovgf %3, %2, %1, %e0";
4690 else if (FPR_P (src_regno))
4692 if (TARGET_HARD_FLOAT)
4693 return "cfmovs %3,%2,%1,%e0";
4695 return "cmor %3, %3, %2, %1, %e0";
4699 else if (GET_CODE (src) == MEM)
4702 if (mode == SImode || mode == SFmode)
4703 return "cldf%I3%U3 %M3, %2, %1, %e0";
4706 else if (ZERO_P (src))
4707 return "cmovgf %., %2, %1, %e0";
4711 else if (GET_CODE (dest) == MEM)
4713 if (GET_CODE (src) == REG)
4715 int src_regno = REGNO (src);
4716 enum machine_mode mode = GET_MODE (dest);
4718 if (GPR_P (src_regno))
4726 return "cstb%I2%U2 %3, %M2, %1, %e0";
4729 return "csth%I2%U2 %3, %M2, %1, %e0";
4733 return "cst%I2%U2 %3, %M2, %1, %e0";
4737 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4738 return "cstf%I2%U2 %3, %M2, %1, %e0";
4741 else if (ZERO_P (src))
4743 enum machine_mode mode = GET_MODE (dest);
4750 return "cstb%I2%U2 %., %M2, %1, %e0";
4753 return "csth%I2%U2 %., %M2, %1, %e0";
4757 return "cst%I2%U2 %., %M2, %1, %e0";
4762 fatal_insn ("bad output_condmove_single operand", insn);
4767 /* Emit the appropriate code to do a comparison, returning the register the
4768 comparison was done it. */
4771 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4773 enum machine_mode cc_mode;
4776 /* Floating point doesn't have comparison against a constant. */
4777 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4778 op1 = force_reg (GET_MODE (op0), op1);
4780 /* Possibly disable using anything but a fixed register in order to work
4781 around cse moving comparisons past function calls. */
4782 cc_mode = SELECT_CC_MODE (test, op0, op1);
4783 cc_reg = ((TARGET_ALLOC_CC)
4784 ? gen_reg_rtx (cc_mode)
4785 : gen_rtx_REG (cc_mode,
4786 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4788 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4789 gen_rtx_COMPARE (cc_mode, op0, op1)));
4795 /* Emit code for a conditional branch.
4796 XXX: I originally wanted to add a clobber of a CCR register to use in
4797 conditional execution, but that confuses the rest of the compiler. */
4800 frv_emit_cond_branch (rtx operands[])
4805 enum rtx_code test = GET_CODE (operands[0]);
4806 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4807 enum machine_mode cc_mode = GET_MODE (cc_reg);
4809 /* Branches generate:
4811 (if_then_else (<test>, <cc_reg>, (const_int 0))
4812 (label_ref <branch_label>)
4814 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4815 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4816 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4817 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4822 /* Emit code to set a gpr to 1/0 based on a comparison. */
4825 frv_emit_scc (rtx operands[])
4831 enum rtx_code test = GET_CODE (operands[1]);
4832 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4834 /* SCC instructions generate:
4835 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4836 (clobber (<ccr_reg>))]) */
4837 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4838 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4840 cr_reg = ((TARGET_ALLOC_CC)
4841 ? gen_reg_rtx (CC_CCRmode)
4842 : gen_rtx_REG (CC_CCRmode,
4843 ((GET_MODE (cc_reg) == CC_FPmode)
4847 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4848 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4853 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4854 the separate insns. */
4857 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4863 /* Set the appropriate CCR bit. */
4864 emit_insn (gen_rtx_SET (VOIDmode,
4866 gen_rtx_fmt_ee (GET_CODE (test),
4871 /* Move the value into the destination. */
4872 emit_move_insn (dest, GEN_INT (value));
4874 /* Move 0 into the destination if the test failed */
4875 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4876 gen_rtx_EQ (GET_MODE (cr_reg),
4879 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4881 /* Finish up, return sequence. */
4888 /* Emit the code for a conditional move, return TRUE if we could do the
4892 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4899 enum rtx_code test = GET_CODE (test_rtx);
4900 rtx cc_reg = frv_emit_comparison (test,
4901 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4902 enum machine_mode cc_mode = GET_MODE (cc_reg);
4904 /* Conditional move instructions generate:
4905 (parallel [(set <target>
4906 (if_then_else (<test> <cc_reg> (const_int 0))
4909 (clobber (<ccr_reg>))]) */
4911 /* Handle various cases of conditional move involving two constants. */
4912 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4914 HOST_WIDE_INT value1 = INTVAL (src1);
4915 HOST_WIDE_INT value2 = INTVAL (src2);
4917 /* Having 0 as one of the constants can be done by loading the other
4918 constant, and optionally moving in gr0. */
4919 if (value1 == 0 || value2 == 0)
4922 /* If the first value is within an addi range and also the difference
4923 between the two fits in an addi's range, load up the difference, then
4924 conditionally move in 0, and then unconditionally add the first
4926 else if (IN_RANGE_P (value1, -2048, 2047)
4927 && IN_RANGE_P (value2 - value1, -2048, 2047))
4930 /* If neither condition holds, just force the constant into a
4934 src1 = force_reg (GET_MODE (dest), src1);
4935 src2 = force_reg (GET_MODE (dest), src2);
4939 /* If one value is a register, insure the other value is either 0 or a
4943 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4944 src1 = force_reg (GET_MODE (dest), src1);
4946 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4947 src2 = force_reg (GET_MODE (dest), src2);
4950 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4951 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4953 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4955 cr_reg = ((TARGET_ALLOC_CC)
4956 ? gen_reg_rtx (CC_CCRmode)
4957 : gen_rtx_REG (CC_CCRmode,
4958 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4960 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4961 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4966 /* Split a conditional move into constituent parts, returning a SEQUENCE
4967 containing all of the insns. */
4970 frv_split_cond_move (rtx operands[])
4972 rtx dest = operands[0];
4973 rtx test = operands[1];
4974 rtx cc_reg = operands[2];
4975 rtx src1 = operands[3];
4976 rtx src2 = operands[4];
4977 rtx cr_reg = operands[5];
4979 enum machine_mode cr_mode = GET_MODE (cr_reg);
4983 /* Set the appropriate CCR bit. */
4984 emit_insn (gen_rtx_SET (VOIDmode,
4986 gen_rtx_fmt_ee (GET_CODE (test),
4991 /* Handle various cases of conditional move involving two constants. */
4992 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4994 HOST_WIDE_INT value1 = INTVAL (src1);
4995 HOST_WIDE_INT value2 = INTVAL (src2);
4997 /* Having 0 as one of the constants can be done by loading the other
4998 constant, and optionally moving in gr0. */
5001 emit_move_insn (dest, src2);
5002 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5003 gen_rtx_NE (cr_mode, cr_reg,
5005 gen_rtx_SET (VOIDmode, dest, src1)));
5008 else if (value2 == 0)
5010 emit_move_insn (dest, src1);
5011 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5012 gen_rtx_EQ (cr_mode, cr_reg,
5014 gen_rtx_SET (VOIDmode, dest, src2)));
5017 /* If the first value is within an addi range and also the difference
5018 between the two fits in an addi's range, load up the difference, then
5019 conditionally move in 0, and then unconditionally add the first
5021 else if (IN_RANGE_P (value1, -2048, 2047)
5022 && IN_RANGE_P (value2 - value1, -2048, 2047))
5024 rtx dest_si = ((GET_MODE (dest) == SImode)
5026 : gen_rtx_SUBREG (SImode, dest, 0));
5028 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5029 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5030 gen_rtx_NE (cr_mode, cr_reg,
5032 gen_rtx_SET (VOIDmode, dest_si,
5034 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5042 /* Emit the conditional move for the test being true if needed. */
5043 if (! rtx_equal_p (dest, src1))
5044 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5045 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5046 gen_rtx_SET (VOIDmode, dest, src1)));
5048 /* Emit the conditional move for the test being false if needed. */
5049 if (! rtx_equal_p (dest, src2))
5050 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5051 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5052 gen_rtx_SET (VOIDmode, dest, src2)));
5055 /* Finish up, return sequence. */
5062 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5063 memory location that is not known to be dword-aligned. */
5065 frv_split_double_load (rtx dest, rtx source)
5067 int regno = REGNO (dest);
5068 rtx dest1 = gen_highpart (SImode, dest);
5069 rtx dest2 = gen_lowpart (SImode, dest);
5070 rtx address = XEXP (source, 0);
5072 /* If the address is pre-modified, load the lower-numbered register
5073 first, then load the other register using an integer offset from
5074 the modified base register. This order should always be safe,
5075 since the pre-modification cannot affect the same registers as the
5078 The situation for other loads is more complicated. Loading one
5079 of the registers could affect the value of ADDRESS, so we must
5080 be careful which order we do them in. */
5081 if (GET_CODE (address) == PRE_MODIFY
5082 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5084 /* It is safe to load the lower-numbered register first. */
5085 emit_move_insn (dest1, change_address (source, SImode, NULL));
5086 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5090 /* ADDRESS is not pre-modified and the address depends on the
5091 lower-numbered register. Load the higher-numbered register
5093 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5094 emit_move_insn (dest1, change_address (source, SImode, NULL));
5098 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5099 and SOURCE is either a double register or the constant zero. */
5101 frv_split_double_store (rtx dest, rtx source)
5103 rtx dest1 = change_address (dest, SImode, NULL);
5104 rtx dest2 = frv_index_memory (dest, SImode, 1);
5105 if (ZERO_P (source))
5107 emit_move_insn (dest1, CONST0_RTX (SImode));
5108 emit_move_insn (dest2, CONST0_RTX (SImode));
5112 emit_move_insn (dest1, gen_highpart (SImode, source));
5113 emit_move_insn (dest2, gen_lowpart (SImode, source));
5118 /* Split a min/max operation returning a SEQUENCE containing all of the
5122 frv_split_minmax (rtx operands[])
5124 rtx dest = operands[0];
5125 rtx minmax = operands[1];
5126 rtx src1 = operands[2];
5127 rtx src2 = operands[3];
5128 rtx cc_reg = operands[4];
5129 rtx cr_reg = operands[5];
5131 enum rtx_code test_code;
5132 enum machine_mode cr_mode = GET_MODE (cr_reg);
5136 /* Figure out which test to use. */
5137 switch (GET_CODE (minmax))
5142 case SMIN: test_code = LT; break;
5143 case SMAX: test_code = GT; break;
5144 case UMIN: test_code = LTU; break;
5145 case UMAX: test_code = GTU; break;
5148 /* Issue the compare instruction. */
5149 emit_insn (gen_rtx_SET (VOIDmode,
5151 gen_rtx_COMPARE (GET_MODE (cc_reg),
5154 /* Set the appropriate CCR bit. */
5155 emit_insn (gen_rtx_SET (VOIDmode,
5157 gen_rtx_fmt_ee (test_code,
5162 /* If are taking the min/max of a nonzero constant, load that first, and
5163 then do a conditional move of the other value. */
5164 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5166 gcc_assert (!rtx_equal_p (dest, src1));
5168 emit_move_insn (dest, src2);
5169 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5170 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5171 gen_rtx_SET (VOIDmode, dest, src1)));
5174 /* Otherwise, do each half of the move. */
5177 /* Emit the conditional move for the test being true if needed. */
5178 if (! rtx_equal_p (dest, src1))
5179 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5180 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5181 gen_rtx_SET (VOIDmode, dest, src1)));
5183 /* Emit the conditional move for the test being false if needed. */
5184 if (! rtx_equal_p (dest, src2))
5185 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5186 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5187 gen_rtx_SET (VOIDmode, dest, src2)));
5190 /* Finish up, return sequence. */
5197 /* Split an integer abs operation returning a SEQUENCE containing all of the
5201 frv_split_abs (rtx operands[])
5203 rtx dest = operands[0];
5204 rtx src = operands[1];
5205 rtx cc_reg = operands[2];
5206 rtx cr_reg = operands[3];
5211 /* Issue the compare < 0 instruction. */
5212 emit_insn (gen_rtx_SET (VOIDmode,
5214 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5216 /* Set the appropriate CCR bit. */
5217 emit_insn (gen_rtx_SET (VOIDmode,
5219 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5221 /* Emit the conditional negate if the value is negative. */
5222 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5223 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5224 gen_negsi2 (dest, src)));
5226 /* Emit the conditional move for the test being false if needed. */
5227 if (! rtx_equal_p (dest, src))
5228 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5229 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5230 gen_rtx_SET (VOIDmode, dest, src)));
5232 /* Finish up, return sequence. */
5239 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5240 register used in an insn. */
5243 frv_clear_registers_used (rtx *ptr, void *data)
5245 if (GET_CODE (*ptr) == REG)
5247 int regno = REGNO (*ptr);
5248 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5250 if (regno < FIRST_PSEUDO_REGISTER)
5252 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5254 while (regno < reg_max)
5256 CLEAR_HARD_REG_BIT (*p_regs, regno);
5266 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5268 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5269 initialize the static storage. */
5271 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5273 frv_ifcvt.added_insns_list = NULL_RTX;
5274 frv_ifcvt.cur_scratch_regs = 0;
5275 frv_ifcvt.num_nested_cond_exec = 0;
5276 frv_ifcvt.cr_reg = NULL_RTX;
5277 frv_ifcvt.nested_cc_reg = NULL_RTX;
5278 frv_ifcvt.extra_int_cr = NULL_RTX;
5279 frv_ifcvt.extra_fp_cr = NULL_RTX;
5280 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5284 /* Internal function to add a potential insn to the list of insns to be inserted
5285 if the conditional execution conversion is successful. */
5288 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5290 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5292 link->jump = before_p; /* Mark to add this before or after insn. */
5293 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5294 frv_ifcvt.added_insns_list);
5296 if (TARGET_DEBUG_COND_EXEC)
5299 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5300 (before_p) ? "before" : "after",
5301 (int)INSN_UID (insn));
5303 debug_rtx (pattern);
5308 /* A C expression to modify the code described by the conditional if
5309 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5310 FALSE_EXPR for converting if-then and if-then-else code to conditional
5311 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5312 tests cannot be converted. */
5315 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5317 basic_block test_bb = ce_info->test_bb; /* test basic block */
5318 basic_block then_bb = ce_info->then_bb; /* THEN */
5319 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5320 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5321 rtx true_expr = *p_true;
5325 enum machine_mode mode = GET_MODE (true_expr);
5329 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5331 rtx sub_cond_exec_reg;
5333 enum rtx_code code_true;
5334 enum rtx_code code_false;
5335 enum reg_class cc_class;
5336 enum reg_class cr_class;
5339 reg_set_iterator rsi;
5341 /* Make sure we are only dealing with hard registers. Also honor the
5342 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5344 if (!reload_completed || !TARGET_COND_EXEC
5345 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5348 /* Figure out which registers we can allocate for our own purposes. Only
5349 consider registers that are not preserved across function calls and are
5350 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5351 if we did not need to use them in reloading other registers. */
5352 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5353 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5354 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5355 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5356 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5358 /* If this is a nested IF, we need to discover whether the CC registers that
5359 are set/used inside of the block are used anywhere else. If not, we can
5360 change them to be the CC register that is paired with the CR register that
5361 controls the outermost IF block. */
5362 if (ce_info->pass > 1)
5364 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5365 for (j = CC_FIRST; j <= CC_LAST; j++)
5366 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5368 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5372 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5376 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5379 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5383 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5384 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5386 frv_ifcvt.added_insns_list = NULL_RTX;
5387 frv_ifcvt.cur_scratch_regs = 0;
5389 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5390 * sizeof (basic_block));
5396 /* Remove anything live at the beginning of the join block from being
5397 available for allocation. */
5398 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5400 if (regno < FIRST_PSEUDO_REGISTER)
5401 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5405 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5407 if (ce_info->num_multiple_test_blocks)
5409 basic_block multiple_test_bb = ce_info->last_test_bb;
5411 while (multiple_test_bb != test_bb)
5413 bb[num_bb++] = multiple_test_bb;
5414 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5418 /* Add in the THEN and ELSE blocks to be scanned. */
5419 bb[num_bb++] = then_bb;
5421 bb[num_bb++] = else_bb;
5423 sub_cond_exec_reg = NULL_RTX;
5424 frv_ifcvt.num_nested_cond_exec = 0;
5426 /* Scan all of the blocks for registers that must not be allocated. */
5427 for (j = 0; j < num_bb; j++)
5429 rtx last_insn = BB_END (bb[j]);
5430 rtx insn = BB_HEAD (bb[j]);
5434 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5435 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5437 (int) INSN_UID (BB_HEAD (bb[j])),
5438 (int) INSN_UID (BB_END (bb[j])));
5440 /* Anything live at the beginning of the block is obviously unavailable
5442 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5444 if (regno < FIRST_PSEUDO_REGISTER)
5445 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5448 /* Loop through the insns in the block. */
5451 /* Mark any new registers that are created as being unavailable for
5452 allocation. Also see if the CC register used in nested IFs can be
5458 int skip_nested_if = FALSE;
5460 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5461 (void *)&tmp_reg->regs);
5463 pattern = PATTERN (insn);
5464 if (GET_CODE (pattern) == COND_EXEC)
5466 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5468 if (reg != sub_cond_exec_reg)
5470 sub_cond_exec_reg = reg;
5471 frv_ifcvt.num_nested_cond_exec++;
5475 set = single_set_pattern (pattern);
5478 rtx dest = SET_DEST (set);
5479 rtx src = SET_SRC (set);
5481 if (GET_CODE (dest) == REG)
5483 int regno = REGNO (dest);
5484 enum rtx_code src_code = GET_CODE (src);
5486 if (CC_P (regno) && src_code == COMPARE)
5487 skip_nested_if = TRUE;
5489 else if (CR_P (regno)
5490 && (src_code == IF_THEN_ELSE
5491 || COMPARISON_P (src)))
5492 skip_nested_if = TRUE;
5496 if (! skip_nested_if)
5497 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5498 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5501 if (insn == last_insn)
5504 insn = NEXT_INSN (insn);
5508 /* If this is a nested if, rewrite the CC registers that are available to
5509 include the ones that can be rewritten, to increase the chance of being
5510 able to allocate a paired CC/CR register combination. */
5511 if (ce_info->pass > 1)
5513 for (j = CC_FIRST; j <= CC_LAST; j++)
5514 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5515 SET_HARD_REG_BIT (tmp_reg->regs, j);
5517 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5523 fprintf (dump_file, "Available GPRs: ");
5525 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5526 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5528 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5529 if (++num_gprs > GPR_TEMP_NUM+2)
5533 fprintf (dump_file, "%s\nAvailable CRs: ",
5534 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5536 for (j = CR_FIRST; j <= CR_LAST; j++)
5537 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5538 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5540 fputs ("\n", dump_file);
5542 if (ce_info->pass > 1)
5544 fprintf (dump_file, "Modifiable CCs: ");
5545 for (j = CC_FIRST; j <= CC_LAST; j++)
5546 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5547 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5549 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5550 frv_ifcvt.num_nested_cond_exec);
5554 /* Allocate the appropriate temporary condition code register. Try to
5555 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5556 that conditional cmp's can be done. */
5557 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5559 cr_class = ICR_REGS;
5560 cc_class = ICC_REGS;
5561 cc_first = ICC_FIRST;
5564 else if (mode == CC_FPmode)
5566 cr_class = FCR_REGS;
5567 cc_class = FCC_REGS;
5568 cc_first = FCC_FIRST;
5573 cc_first = cc_last = 0;
5574 cr_class = cc_class = NO_REGS;
5577 cc = XEXP (true_expr, 0);
5578 nested_cc = cr = NULL_RTX;
5579 if (cc_class != NO_REGS)
5581 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5582 so we can execute a csubcc/caddcc/cfcmps instruction. */
5585 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5587 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5589 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5590 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5592 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5593 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5596 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5597 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5607 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5614 "Will use %s for conditional execution, %s for nested comparisons\n",
5615 reg_names[ REGNO (cr)],
5616 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5618 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5619 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5620 bit being true. We don't do this for floating point, because of NaNs. */
5621 code = GET_CODE (true_expr);
5622 if (GET_MODE (cc) != CC_FPmode)
5624 code = reverse_condition (code);
5634 check_insn = gen_rtx_SET (VOIDmode, cr,
5635 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5637 /* Record the check insn to be inserted later. */
5638 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5640 /* Update the tests. */
5641 frv_ifcvt.cr_reg = cr;
5642 frv_ifcvt.nested_cc_reg = nested_cc;
5643 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5644 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5647 /* Fail, don't do this conditional execution. */
5650 *p_false = NULL_RTX;
5652 fprintf (dump_file, "Disabling this conditional execution.\n");
5658 /* A C expression to modify the code described by the conditional if
5659 information CE_INFO, for the basic block BB, possibly updating the tests in
5660 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5661 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5662 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5664 /* p_true and p_false are given expressions of the form:
5666 (and (eq:CC_CCR (reg:CC_CCR)
5672 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5677 rtx old_true = XEXP (*p_true, 0);
5678 rtx old_false = XEXP (*p_false, 0);
5679 rtx true_expr = XEXP (*p_true, 1);
5680 rtx false_expr = XEXP (*p_false, 1);
5683 rtx cr = XEXP (old_true, 0);
5685 rtx new_cr = NULL_RTX;
5686 rtx *p_new_cr = (rtx *)0;
5690 enum reg_class cr_class;
5691 enum machine_mode mode = GET_MODE (true_expr);
5692 rtx (*logical_func)(rtx, rtx, rtx);
5694 if (TARGET_DEBUG_COND_EXEC)
5697 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5698 ce_info->and_and_p ? "&&" : "||");
5700 debug_rtx (*p_true);
5702 fputs ("\nfalse insn:\n", stderr);
5703 debug_rtx (*p_false);
5706 if (!TARGET_MULTI_CE)
5709 if (GET_CODE (cr) != REG)
5712 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5714 cr_class = ICR_REGS;
5715 p_new_cr = &frv_ifcvt.extra_int_cr;
5717 else if (mode == CC_FPmode)
5719 cr_class = FCR_REGS;
5720 p_new_cr = &frv_ifcvt.extra_fp_cr;
5725 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5726 more &&/|| tests. */
5730 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5731 CC_CCRmode, TRUE, TRUE);
5736 if (ce_info->and_and_p)
5738 old_test = old_false;
5739 test_expr = true_expr;
5740 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5741 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5742 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5746 old_test = old_false;
5747 test_expr = false_expr;
5748 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5749 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5750 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5753 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5754 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5756 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5758 /* Now add the conditional check insn. */
5759 cc = XEXP (test_expr, 0);
5760 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5761 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5763 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5765 /* Add the new check insn to the list of check insns that need to be
5767 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5769 if (TARGET_DEBUG_COND_EXEC)
5771 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5774 debug_rtx (*p_true);
5776 fputs ("\nfalse insn:\n", stderr);
5777 debug_rtx (*p_false);
5783 *p_true = *p_false = NULL_RTX;
5785 /* If we allocated a CR register, release it. */
5788 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5789 *p_new_cr = NULL_RTX;
5792 if (TARGET_DEBUG_COND_EXEC)
5793 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5799 /* Return a register which will be loaded with a value if an IF block is
5800 converted to conditional execution. This is used to rewrite instructions
5801 that use constants to ones that just use registers. */
5804 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5806 int num_alloc = frv_ifcvt.cur_scratch_regs;
5810 /* We know gr0 == 0, so replace any errant uses. */
5811 if (value == const0_rtx)
5812 return gen_rtx_REG (SImode, GPR_FIRST);
5814 /* First search all registers currently loaded to see if we have an
5815 applicable constant. */
5816 if (CONSTANT_P (value)
5817 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5819 for (i = 0; i < num_alloc; i++)
5821 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5822 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5826 /* Have we exhausted the number of registers available? */
5827 if (num_alloc >= GPR_TEMP_NUM)
5830 fprintf (dump_file, "Too many temporary registers allocated\n");
5835 /* Allocate the new register. */
5836 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5840 fputs ("Could not find a scratch register\n", dump_file);
5845 frv_ifcvt.cur_scratch_regs++;
5846 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5850 if (GET_CODE (value) == CONST_INT)
5851 fprintf (dump_file, "Register %s will hold %ld\n",
5852 reg_names[ REGNO (reg)], (long)INTVAL (value));
5854 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5855 fprintf (dump_file, "Register %s will hold LR\n",
5856 reg_names[ REGNO (reg)]);
5859 fprintf (dump_file, "Register %s will hold a saved value\n",
5860 reg_names[ REGNO (reg)]);
5867 /* Update a MEM used in conditional code that might contain an offset to put
5868 the offset into a scratch register, so that the conditional load/store
5869 operations can be used. This function returns the original pointer if the
5870 MEM is valid to use in conditional code, NULL if we can't load up the offset
5871 into a temporary register, or the new MEM if we were successful. */
5874 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5876 rtx addr = XEXP (mem, 0);
5878 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5880 if (GET_CODE (addr) == PLUS)
5882 rtx addr_op0 = XEXP (addr, 0);
5883 rtx addr_op1 = XEXP (addr, 1);
5885 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5887 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5891 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5898 else if (CONSTANT_P (addr))
5899 addr = frv_ifcvt_load_value (addr, insn);
5904 if (addr == NULL_RTX)
5907 else if (XEXP (mem, 0) != addr)
5908 return change_address (mem, mode, addr);
5915 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5916 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5919 single_set_pattern (rtx pattern)
5924 if (GET_CODE (pattern) == COND_EXEC)
5925 pattern = COND_EXEC_CODE (pattern);
5927 if (GET_CODE (pattern) == SET)
5930 else if (GET_CODE (pattern) == PARALLEL)
5932 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5934 rtx sub = XVECEXP (pattern, 0, i);
5936 switch (GET_CODE (sub))
5960 /* A C expression to modify the code described by the conditional if
5961 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5962 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5963 insn cannot be converted to be executed conditionally. */
5966 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5970 rtx orig_ce_pattern = pattern;
5976 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5978 test = COND_EXEC_TEST (pattern);
5979 if (GET_CODE (test) == AND)
5981 rtx cr = frv_ifcvt.cr_reg;
5984 op0 = XEXP (test, 0);
5985 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5988 op1 = XEXP (test, 1);
5989 test_reg = XEXP (op1, 0);
5990 if (GET_CODE (test_reg) != REG)
5993 /* Is this the first nested if block in this sequence? If so, generate
5994 an andcr or andncr. */
5995 if (! frv_ifcvt.last_nested_if_cr)
5999 frv_ifcvt.last_nested_if_cr = test_reg;
6000 if (GET_CODE (op0) == NE)
6001 and_op = gen_andcr (test_reg, cr, test_reg);
6003 and_op = gen_andncr (test_reg, cr, test_reg);
6005 frv_ifcvt_add_insn (and_op, insn, TRUE);
6008 /* If this isn't the first statement in the nested if sequence, see if we
6009 are dealing with the same register. */
6010 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6013 COND_EXEC_TEST (pattern) = test = op1;
6016 /* If this isn't a nested if, reset state variables. */
6019 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6022 set = single_set_pattern (pattern);
6025 rtx dest = SET_DEST (set);
6026 rtx src = SET_SRC (set);
6027 enum machine_mode mode = GET_MODE (dest);
6029 /* Check for normal binary operators. */
6030 if (mode == SImode && ARITHMETIC_P (src))
6032 op0 = XEXP (src, 0);
6033 op1 = XEXP (src, 1);
6035 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6037 op1 = frv_ifcvt_load_value (op1, insn);
6039 COND_EXEC_CODE (pattern)
6040 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6048 /* For multiply by a constant, we need to handle the sign extending
6049 correctly. Add a USE of the value after the multiply to prevent flow
6050 from cratering because only one register out of the two were used. */
6051 else if (mode == DImode && GET_CODE (src) == MULT)
6053 op0 = XEXP (src, 0);
6054 op1 = XEXP (src, 1);
6055 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6057 op1 = frv_ifcvt_load_value (op1, insn);
6060 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6061 COND_EXEC_CODE (pattern)
6062 = gen_rtx_SET (VOIDmode, dest,
6063 gen_rtx_MULT (DImode, op0, op1));
6069 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6072 /* If we are just loading a constant created for a nested conditional
6073 execution statement, just load the constant without any conditional
6074 execution, since we know that the constant will not interfere with any
6076 else if (frv_ifcvt.scratch_insns_bitmap
6077 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6079 && REG_P (SET_DEST (set))
6080 /* We must not unconditionally set a scratch reg chosen
6081 for a nested if-converted block if its incoming
6082 value from the TEST block (or the result of the THEN
6083 branch) could/should propagate to the JOIN block.
6084 It suffices to test whether the register is live at
6085 the JOIN point: if it's live there, we can infer
6086 that we set it in the former JOIN block of the
6087 nested if-converted block (otherwise it wouldn't
6088 have been available as a scratch register), and it
6089 is either propagated through or set in the other
6090 conditional block. It's probably not worth trying
6091 to catch the latter case, and it could actually
6092 limit scheduling of the combined block quite
6095 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6096 REGNO (SET_DEST (set))))
6097 /* Similarly, we must not unconditionally set a reg
6098 used as scratch in the THEN branch if the same reg
6099 is live in the ELSE branch. */
6100 && (! ce_info->else_bb
6101 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6102 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6103 REGNO (SET_DEST (set))))))
6106 else if (mode == QImode || mode == HImode || mode == SImode
6109 int changed_p = FALSE;
6111 /* Check for just loading up a constant */
6112 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6114 src = frv_ifcvt_load_value (src, insn);
6121 /* See if we need to fix up stores */
6122 if (GET_CODE (dest) == MEM)
6124 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6129 else if (new_mem != dest)
6136 /* See if we need to fix up loads */
6137 if (GET_CODE (src) == MEM)
6139 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6144 else if (new_mem != src)
6151 /* If either src or destination changed, redo SET. */
6153 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6156 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6157 rewriting the CC register to be the same as the paired CC/CR register
6159 else if (mode == CC_CCRmode && COMPARISON_P (src))
6161 int regno = REGNO (XEXP (src, 0));
6164 if (ce_info->pass > 1
6165 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6166 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6168 src = gen_rtx_fmt_ee (GET_CODE (src),
6170 frv_ifcvt.nested_cc_reg,
6174 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6175 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6178 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6179 else if (ce_info->pass > 1
6180 && GET_CODE (dest) == REG
6181 && CC_P (REGNO (dest))
6182 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6183 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6185 && GET_CODE (src) == COMPARE)
6187 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6188 COND_EXEC_CODE (pattern)
6189 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6193 if (TARGET_DEBUG_COND_EXEC)
6195 rtx orig_pattern = PATTERN (insn);
6197 PATTERN (insn) = pattern;
6199 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6203 PATTERN (insn) = orig_pattern;
6209 if (TARGET_DEBUG_COND_EXEC)
6211 rtx orig_pattern = PATTERN (insn);
6213 PATTERN (insn) = orig_ce_pattern;
6215 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6219 PATTERN (insn) = orig_pattern;
6226 /* A C expression to perform any final machine dependent modifications in
6227 converting code to conditional execution in the code described by the
6228 conditional if information CE_INFO. */
6231 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6235 rtx p = frv_ifcvt.added_insns_list;
6238 /* Loop inserting the check insns. The last check insn is the first test,
6239 and is the appropriate place to insert constants. */
6244 rtx check_and_insert_insns = XEXP (p, 0);
6247 check_insn = XEXP (check_and_insert_insns, 0);
6248 existing_insn = XEXP (check_and_insert_insns, 1);
6251 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6252 the existing insn, otherwise it is to be inserted AFTER. */
6253 if (check_and_insert_insns->jump)
6255 emit_insn_before (check_insn, existing_insn);
6256 check_and_insert_insns->jump = 0;
6259 emit_insn_after (check_insn, existing_insn);
6261 free_EXPR_LIST_node (check_and_insert_insns);
6262 free_EXPR_LIST_node (old_p);
6264 while (p != NULL_RTX);
6266 /* Load up any constants needed into temp gprs */
6267 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6269 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6270 if (! frv_ifcvt.scratch_insns_bitmap)
6271 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6272 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6273 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6276 frv_ifcvt.added_insns_list = NULL_RTX;
6277 frv_ifcvt.cur_scratch_regs = 0;
6281 /* A C expression to cancel any machine dependent modifications in converting
6282 code to conditional execution in the code described by the conditional if
6283 information CE_INFO. */
6286 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6289 rtx p = frv_ifcvt.added_insns_list;
6291 /* Loop freeing up the EXPR_LIST's allocated. */
6292 while (p != NULL_RTX)
6294 rtx check_and_jump = XEXP (p, 0);
6298 free_EXPR_LIST_node (check_and_jump);
6299 free_EXPR_LIST_node (old_p);
6302 /* Release any temporary gprs allocated. */
6303 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6304 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6306 frv_ifcvt.added_insns_list = NULL_RTX;
6307 frv_ifcvt.cur_scratch_regs = 0;
6311 /* A C expression for the size in bytes of the trampoline, as an integer.
6315 setlo #0, <static_chain>
6317 sethi #0, <static_chain>
6318 jmpl @(gr0,<jmp_reg>) */
6321 frv_trampoline_size (void)
6324 /* Allocate room for the function descriptor and the lddi
6327 return 5 /* instructions */ * 4 /* instruction size. */;
6331 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6332 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6333 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6334 should be passed to the function when it is called.
6339 setlo #0, <static_chain>
6341 sethi #0, <static_chain>
6342 jmpl @(gr0,<jmp_reg>) */
6345 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6347 rtx addr = XEXP (m_tramp, 0);
6348 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6349 rtx sc_reg = force_reg (Pmode, static_chain);
6351 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6354 GEN_INT (frv_trampoline_size ()), SImode,
6360 /* Many machines have some registers that cannot be copied directly to or from
6361 memory or even from other types of registers. An example is the `MQ'
6362 register, which on most machines, can only be copied to or from general
6363 registers, but not memory. Some machines allow copying all registers to and
6364 from memory, but require a scratch register for stores to some memory
6365 locations (e.g., those with symbolic address on the RT, and those with
6366 certain symbolic address on the SPARC when compiling PIC). In some cases,
6367 both an intermediate and a scratch register are required.
6369 You should define these macros to indicate to the reload phase that it may
6370 need to allocate at least one register for a reload in addition to the
6371 register to contain the data. Specifically, if copying X to a register
6372 RCLASS in MODE requires an intermediate register, you should define
6373 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6374 whose registers can be used as intermediate registers or scratch registers.
6376 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6377 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6378 largest register class required. If the requirements for input and output
6379 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6380 instead of defining both macros identically.
6382 The values returned by these macros are often `GENERAL_REGS'. Return
6383 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6384 to or from a register of RCLASS in MODE without requiring a scratch register.
6385 Do not define this macro if it would always return `NO_REGS'.
6387 If a scratch register is required (either with or without an intermediate
6388 register), you should define patterns for `reload_inM' or `reload_outM', as
6389 required.. These patterns, which will normally be implemented with a
6390 `define_expand', should be similar to the `movM' patterns, except that
6391 operand 2 is the scratch register.
6393 Define constraints for the reload register and scratch register that contain
6394 a single register class. If the original reload register (whose class is
6395 RCLASS) can meet the constraint given in the pattern, the value returned by
6396 these macros is used for the class of the scratch register. Otherwise, two
6397 additional reload registers are required. Their classes are obtained from
6398 the constraints in the insn pattern.
6400 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6401 either be in a hard register or in memory. Use `true_regnum' to find out;
6402 it will return -1 if the pseudo is in memory and the hard register number if
6403 it is in a register.
6405 These macros should not be used in the case where a particular class of
6406 registers can only be copied to memory and not to another class of
6407 registers. In that case, secondary reload registers are not needed and
6408 would not be helpful. Instead, a stack location must be used to perform the
6409 copy and the `movM' pattern should use memory as an intermediate storage.
6410 This case often occurs between floating-point and general registers. */
6413 frv_secondary_reload_class (enum reg_class rclass,
6414 enum machine_mode mode ATTRIBUTE_UNUSED,
6425 /* Accumulators/Accumulator guard registers need to go through floating
6431 if (x && GET_CODE (x) == REG)
6433 int regno = REGNO (x);
6435 if (ACC_P (regno) || ACCG_P (regno))
6440 /* Nonzero constants should be loaded into an FPR through a GPR. */
6444 if (x && CONSTANT_P (x) && !ZERO_P (x))
6450 /* All of these types need gpr registers. */
6462 /* The accumulators need fpr registers. */
6474 /* This hook exists to catch the case where secondary_reload_class() is
6475 called from init_reg_autoinc() in regclass.c - before the reload optabs
6476 have been initialised. */
6479 frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
6480 enum machine_mode reload_mode,
6481 secondary_reload_info * sri)
6483 enum reg_class rclass = NO_REGS;
6485 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6487 sri->icode = sri->prev_sri->t_icode;
6491 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6493 if (rclass != NO_REGS)
6495 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
6496 : reload_out_optab[(int) reload_mode]);
6499 /* This happens when then the reload_[in|out]_optabs have
6500 not been initialised. */
6501 sri->t_icode = CODE_FOR_nothing;
6506 /* Fall back to the default secondary reload handler. */
6507 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6511 /* A C expression whose value is nonzero if pseudos that have been assigned to
6512 registers of class RCLASS would likely be spilled because registers of RCLASS
6513 are needed for spill registers.
6515 The default value of this macro returns 1 if RCLASS has exactly one register
6516 and zero otherwise. On most machines, this default should be used. Only
6517 define this macro to some other expression if pseudo allocated by
6518 `local-alloc.c' end up in memory because their hard registers were needed
6519 for spill registers. If this macro returns nonzero for those classes, those
6520 pseudos will only be allocated by `global.c', which knows how to reallocate
6521 the pseudo to another register. If there would not be another register
6522 available for reallocation, you should not change the definition of this
6523 macro since the only effect of such a definition would be to slow down
6524 register allocation. */
6527 frv_class_likely_spilled_p (enum reg_class rclass)
6537 case FDPIC_FPTR_REGS:
6559 /* An expression for the alignment of a structure field FIELD if the
6560 alignment computed in the usual way is COMPUTED. GCC uses this
6561 value instead of the value in `BIGGEST_ALIGNMENT' or
6562 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6564 /* The definition type of the bit field data is either char, short, long or
6565 long long. The maximum bit size is the number of bits of its own type.
6567 The bit field data is assigned to a storage unit that has an adequate size
6568 for bit field data retention and is located at the smallest address.
6570 Consecutive bit field data are packed at consecutive bits having the same
6571 storage unit, with regard to the type, beginning with the MSB and continuing
6574 If a field to be assigned lies over a bit field type boundary, its
6575 assignment is completed by aligning it with a boundary suitable for the
6578 When a bit field having a bit length of 0 is declared, it is forcibly
6579 assigned to the next storage unit.
6592 &x 00000000 00000000 00000000 00000000
6595 &x+4 00000000 00000000 00000000 00000000
6598 &x+8 00000000 00000000 00000000 00000000
6601 &x+12 00000000 00000000 00000000 00000000
6607 frv_adjust_field_align (tree field, int computed)
6609 /* Make sure that the bitfield is not wider than the type. */
6610 if (DECL_BIT_FIELD (field)
6611 && !DECL_ARTIFICIAL (field))
6613 tree parent = DECL_CONTEXT (field);
6614 tree prev = NULL_TREE;
6617 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6619 if (TREE_CODE (cur) != FIELD_DECL)
6627 /* If this isn't a :0 field and if the previous element is a bitfield
6628 also, see if the type is different, if so, we will need to align the
6629 bit-field to the next boundary. */
6631 && ! DECL_PACKED (field)
6632 && ! integer_zerop (DECL_SIZE (field))
6633 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6635 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6636 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6637 computed = (prev_align > cur_align) ? prev_align : cur_align;
6645 /* A C expression that is nonzero if it is permissible to store a value of mode
6646 MODE in hard register number REGNO (or in several registers starting with
6647 that one). For a machine where all registers are equivalent, a suitable
6650 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6652 It is not necessary for this macro to check for the numbers of fixed
6653 registers, because the allocation mechanism considers them to be always
6656 On some machines, double-precision values must be kept in even/odd register
6657 pairs. The way to implement that is to define this macro to reject odd
6658 register numbers for such modes.
6660 The minimum requirement for a mode to be OK in a register is that the
6661 `movMODE' instruction pattern support moves between the register and any
6662 other hard register for which the mode is OK; and that moving a value into
6663 the register and back out not alter it.
6665 Since the same instruction used to move `SImode' will work for all narrower
6666 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6667 to distinguish between these modes, provided you define patterns `movhi',
6668 etc., to take advantage of this. This is useful because of the interaction
6669 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6670 all integer modes to be tieable.
6672 Many machines have special registers for floating point arithmetic. Often
6673 people assume that floating point machine modes are allowed only in floating
6674 point registers. This is not true. Any registers that can hold integers
6675 can safely *hold* a floating point machine mode, whether or not floating
6676 arithmetic can be done on it in those registers. Integer move instructions
6677 can be used to move the values.
6679 On some machines, though, the converse is true: fixed-point machine modes
6680 may not go in floating registers. This is true if the floating registers
6681 normalize any value stored in them, because storing a non-floating value
6682 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6683 fixed-point machine modes in floating registers. But if the floating
6684 registers do not automatically normalize, if you can store any bit pattern
6685 in one and retrieve it unchanged without a trap, then any machine mode may
6686 go in a floating register, so you can define this macro to say so.
6688 The primary significance of special floating registers is rather that they
6689 are the registers acceptable in floating point arithmetic instructions.
6690 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6691 writing the proper constraints for those instructions.
6693 On some machines, the floating registers are especially slow to access, so
6694 that it is better to store a value in a stack frame than in such a register
6695 if floating point arithmetic is not being done. As long as the floating
6696 registers are not in class `GENERAL_REGS', they will not be used unless some
6697 pattern's constraint asks for one. */
6700 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6710 return ICC_P (regno) || GPR_P (regno);
6713 return CR_P (regno) || GPR_P (regno);
6716 return FCC_P (regno) || GPR_P (regno);
6722 /* Set BASE to the first register in REGNO's class. Set MASK to the
6723 bits that must be clear in (REGNO - BASE) for the register to be
6725 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6729 /* ACCGs store one byte. Two-byte quantities must start in
6730 even-numbered registers, four-byte ones in registers whose
6731 numbers are divisible by four, and so on. */
6733 mask = GET_MODE_SIZE (mode) - 1;
6737 /* The other registers store one word. */
6738 if (GPR_P (regno) || regno == AP_FIRST)
6741 else if (FPR_P (regno))
6744 else if (ACC_P (regno))
6747 else if (SPR_P (regno))
6748 return mode == SImode;
6750 /* Fill in the table. */
6754 /* Anything smaller than an SI is OK in any word-sized register. */
6755 if (GET_MODE_SIZE (mode) < 4)
6758 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6760 return (((regno - base) & mask) == 0);
6767 /* A C expression for the number of consecutive hard registers, starting at
6768 register number REGNO, required to hold a value of mode MODE.
6770 On a machine where all registers are exactly one word, a suitable definition
6773 #define HARD_REGNO_NREGS(REGNO, MODE) \
6774 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6775 / UNITS_PER_WORD)) */
6777 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6778 that we can build the appropriate instructions to properly reload the
6779 values. Also, make the byte-sized accumulator guards use one guard
6783 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6786 return GET_MODE_SIZE (mode);
6788 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6792 /* A C expression for the maximum number of consecutive registers of
6793 class RCLASS needed to hold a value of mode MODE.
6795 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6796 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6797 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6799 This macro helps control the handling of multiple-word values in
6802 This declaration is required. */
6805 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6807 if (rclass == ACCG_REGS)
6808 /* An N-byte value requires N accumulator guards. */
6809 return GET_MODE_SIZE (mode);
6811 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6815 /* A C expression that is nonzero if X is a legitimate constant for an
6816 immediate operand on the target machine. You can assume that X satisfies
6817 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6818 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6821 frv_legitimate_constant_p (rtx x)
6823 enum machine_mode mode = GET_MODE (x);
6825 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6826 means that the move expanders will be expected to deal with most
6827 kinds of constant, regardless of what we return here.
6829 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6830 a constant can be entered into reg_equiv_constant[]. If we return true,
6831 reload can create new instances of the constant whenever it likes.
6833 The idea is therefore to accept as many constants as possible (to give
6834 reload more freedom) while rejecting constants that can only be created
6835 at certain times. In particular, anything with a symbolic component will
6836 require use of the pseudo FDPIC register, which is only available before
6839 return LEGITIMATE_PIC_OPERAND_P (x);
6841 /* All of the integer constants are ok. */
6842 if (GET_CODE (x) != CONST_DOUBLE)
6845 /* double integer constants are ok. */
6846 if (mode == VOIDmode || mode == DImode)
6849 /* 0 is always ok. */
6850 if (x == CONST0_RTX (mode))
6853 /* If floating point is just emulated, allow any constant, since it will be
6854 constructed in the GPRs. */
6855 if (!TARGET_HAS_FPRS)
6858 if (mode == DFmode && !TARGET_DOUBLE)
6861 /* Otherwise store the constant away and do a load. */
6865 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6866 CC_NZ for comparisons against zero in which a single Z or N flag test
6867 is enough, CC_UNS for other unsigned comparisons, and CC for other
6868 signed comparisons. */
6871 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6873 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6882 return y == const0_rtx ? CC_NZmode : CCmode;
6888 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6895 /* A C expression for the cost of moving data from a register in class FROM to
6896 one in class TO. The classes are expressed using the enumeration values
6897 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6898 interpreted relative to that.
6900 It is not required that the cost always equal 2 when FROM is the same as TO;
6901 on some machines it is expensive to move between registers if they are not
6904 If reload sees an insn consisting of a single `set' between two hard
6905 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6906 value of 2, reload does not check to ensure that the constraints of the insn
6907 are met. Setting a cost of other than 2 will allow reload to verify that
6908 the constraints are met. You should do this if the `movM' pattern's
6909 constraints do not allow such copying. */
6911 #define HIGH_COST 40
6912 #define MEDIUM_COST 3
6916 frv_register_move_cost (enum reg_class from, enum reg_class to)
7000 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7001 use ".picptr" to generate safe relocations for PIC code. We also
7002 need a fixup entry for aligned (non-debugging) code. */
7005 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
7007 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
7009 if (GET_CODE (value) == CONST
7010 || GET_CODE (value) == SYMBOL_REF
7011 || GET_CODE (value) == LABEL_REF)
7013 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
7014 && SYMBOL_REF_FUNCTION_P (value))
7016 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
7017 output_addr_const (asm_out_file, value);
7018 fputs (")\n", asm_out_file);
7021 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7022 && frv_function_symbol_referenced_p (value))
7024 if (aligned_p && !TARGET_FDPIC)
7026 static int label_num = 0;
7030 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7031 p = (* targetm.strip_name_encoding) (buf);
7033 fprintf (asm_out_file, "%s:\n", p);
7034 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7035 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7036 fprintf (asm_out_file, "\t.previous\n");
7038 assemble_integer_with_op ("\t.picptr\t", value);
7043 /* We've set the unaligned SI op to NULL, so we always have to
7044 handle the unaligned case here. */
7045 assemble_integer_with_op ("\t.4byte\t", value);
7049 return default_assemble_integer (value, size, aligned_p);
7052 /* Function to set up the backend function structure. */
7054 static struct machine_function *
7055 frv_init_machine_status (void)
7057 return GGC_CNEW (struct machine_function);
7060 /* Implement TARGET_SCHED_ISSUE_RATE. */
7063 frv_issue_rate (void)
7068 switch (frv_cpu_type)
7072 case FRV_CPU_SIMPLE:
7080 case FRV_CPU_GENERIC:
7082 case FRV_CPU_TOMCAT:
7090 /* A for_each_rtx callback. If X refers to an accumulator, return
7091 ACC_GROUP_ODD if the bit 2 of the register number is set and
7092 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7096 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7100 if (ACC_P (REGNO (*x)))
7101 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7102 if (ACCG_P (REGNO (*x)))
7103 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7108 /* Return the value of INSN's acc_group attribute. */
7111 frv_acc_group (rtx insn)
7113 /* This distinction only applies to the FR550 packing constraints. */
7114 if (frv_cpu_type != FRV_CPU_FR550)
7115 return ACC_GROUP_NONE;
7116 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7119 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7120 INSN will try to claim first. Since this value depends only on the
7121 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7124 frv_insn_unit (rtx insn)
7126 enum attr_type type;
7128 type = get_attr_type (insn);
7129 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7131 /* We haven't seen this type of instruction before. */
7135 /* Issue the instruction on its own to see which unit it prefers. */
7136 state = alloca (state_size ());
7137 state_reset (state);
7138 state_transition (state, insn);
7140 /* Find out which unit was taken. */
7141 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7142 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7145 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7147 frv_type_to_unit[type] = unit;
7149 return frv_type_to_unit[type];
7152 /* Return true if INSN issues to a branch unit. */
7155 frv_issues_to_branch_unit_p (rtx insn)
7157 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7160 /* The current state of the packing pass, implemented by frv_pack_insns. */
7162 /* The state of the pipeline DFA. */
7165 /* Which hardware registers are set within the current packet,
7166 and the conditions under which they are set. */
7167 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7169 /* The memory locations that have been modified so far in this
7170 packet. MEM is the memref and COND is the regstate_t condition
7171 under which it is set. */
7177 /* The number of valid entries in MEMS. The value is larger than
7178 ARRAY_SIZE (mems) if there were too many mems to record. */
7179 unsigned int num_mems;
7181 /* The maximum number of instructions that can be packed together. */
7182 unsigned int issue_rate;
7184 /* The instructions in the packet, partitioned into groups. */
7185 struct frv_packet_group {
7186 /* How many instructions in the packet belong to this group. */
7187 unsigned int num_insns;
7189 /* A list of the instructions that belong to this group, in the order
7190 they appear in the rtl stream. */
7191 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7193 /* The contents of INSNS after they have been sorted into the correct
7194 assembly-language order. Element X issues to unit X. The list may
7195 contain extra nops. */
7196 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7198 /* The member of frv_nops[] to use in sorted[]. */
7200 } groups[NUM_GROUPS];
7202 /* The instructions that make up the current packet. */
7203 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7204 unsigned int num_insns;
7207 /* Return the regstate_t flags for the given COND_EXEC condition.
7208 Abort if the condition isn't in the right form. */
7211 frv_cond_flags (rtx cond)
7213 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7214 && GET_CODE (XEXP (cond, 0)) == REG
7215 && CR_P (REGNO (XEXP (cond, 0)))
7216 && XEXP (cond, 1) == const0_rtx);
7217 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7218 | (GET_CODE (cond) == NE
7220 : REGSTATE_IF_FALSE));
7224 /* Return true if something accessed under condition COND2 can
7225 conflict with something written under condition COND1. */
7228 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7230 /* If either reference was unconditional, we have a conflict. */
7231 if ((cond1 & REGSTATE_IF_EITHER) == 0
7232 || (cond2 & REGSTATE_IF_EITHER) == 0)
7235 /* The references might conflict if they were controlled by
7237 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7240 /* They definitely conflict if they are controlled by the
7242 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7249 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7250 the current packet. DATA points to a regstate_t that describes the
7251 condition under which *X might be set or used. */
7254 frv_registers_conflict_p_1 (rtx *x, void *data)
7256 unsigned int regno, i;
7259 cond = *(regstate_t *) data;
7261 if (GET_CODE (*x) == REG)
7262 FOR_EACH_REGNO (regno, *x)
7263 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7264 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7267 if (GET_CODE (*x) == MEM)
7269 /* If we ran out of memory slots, assume a conflict. */
7270 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7273 /* Check for output or true dependencies with earlier MEMs. */
7274 for (i = 0; i < frv_packet.num_mems; i++)
7275 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7277 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7281 if (output_dependence (frv_packet.mems[i].mem, *x))
7286 /* The return values of calls aren't significant: they describe
7287 the effect of the call as a whole, not of the insn itself. */
7288 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7290 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7295 /* Check subexpressions. */
7300 /* Return true if something in X might depend on an instruction
7301 in the current packet. */
7304 frv_registers_conflict_p (rtx x)
7309 if (GET_CODE (x) == COND_EXEC)
7311 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7314 flags |= frv_cond_flags (XEXP (x, 0));
7317 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7321 /* A note_stores callback. DATA points to the regstate_t condition
7322 under which X is modified. Update FRV_PACKET accordingly. */
7325 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7329 if (GET_CODE (x) == REG)
7330 FOR_EACH_REGNO (regno, x)
7331 frv_packet.regstate[regno] |= *(regstate_t *) data;
7333 if (GET_CODE (x) == MEM)
7335 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7337 frv_packet.mems[frv_packet.num_mems].mem = x;
7338 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7340 frv_packet.num_mems++;
7345 /* Update the register state information for an instruction whose
7349 frv_registers_update (rtx x)
7353 flags = REGSTATE_MODIFIED;
7354 if (GET_CODE (x) == COND_EXEC)
7356 flags |= frv_cond_flags (XEXP (x, 0));
7359 note_stores (x, frv_registers_update_1, &flags);
7363 /* Initialize frv_packet for the start of a new packet. */
7366 frv_start_packet (void)
7368 enum frv_insn_group group;
7370 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7371 frv_packet.num_mems = 0;
7372 frv_packet.num_insns = 0;
7373 for (group = 0; group < NUM_GROUPS; group++)
7374 frv_packet.groups[group].num_insns = 0;
7378 /* Likewise for the start of a new basic block. */
7381 frv_start_packet_block (void)
7383 state_reset (frv_packet.dfa_state);
7384 frv_start_packet ();
7388 /* Finish the current packet, if any, and start a new one. Call
7389 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7392 frv_finish_packet (void (*handle_packet) (void))
7394 if (frv_packet.num_insns > 0)
7397 state_transition (frv_packet.dfa_state, 0);
7398 frv_start_packet ();
7403 /* Return true if INSN can be added to the current packet. Update
7404 the DFA state on success. */
7407 frv_pack_insn_p (rtx insn)
7409 /* See if the packet is already as long as it can be. */
7410 if (frv_packet.num_insns == frv_packet.issue_rate)
7413 /* If the scheduler thought that an instruction should start a packet,
7414 it's usually a good idea to believe it. It knows much more about
7415 the latencies than we do.
7417 There are some exceptions though:
7419 - Conditional instructions are scheduled on the assumption that
7420 they will be executed. This is usually a good thing, since it
7421 tends to avoid unnecessary stalls in the conditional code.
7422 But we want to pack conditional instructions as tightly as
7423 possible, in order to optimize the case where they aren't
7426 - The scheduler will always put branches on their own, even
7427 if there's no real dependency.
7429 - There's no point putting a call in its own packet unless
7431 if (frv_packet.num_insns > 0
7432 && GET_CODE (insn) == INSN
7433 && GET_MODE (insn) == TImode
7434 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7437 /* Check for register conflicts. Don't do this for setlo since any
7438 conflict will be with the partnering sethi, with which it can
7440 if (get_attr_type (insn) != TYPE_SETLO)
7441 if (frv_registers_conflict_p (PATTERN (insn)))
7444 return state_transition (frv_packet.dfa_state, insn) < 0;
7448 /* Add instruction INSN to the current packet. */
7451 frv_add_insn_to_packet (rtx insn)
7453 struct frv_packet_group *packet_group;
7455 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7456 packet_group->insns[packet_group->num_insns++] = insn;
7457 frv_packet.insns[frv_packet.num_insns++] = insn;
7459 frv_registers_update (PATTERN (insn));
7463 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7464 packet ends in a branch or call, insert the nop before it, otherwise
7468 frv_insert_nop_in_packet (rtx insn)
7470 struct frv_packet_group *packet_group;
7473 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7474 last = frv_packet.insns[frv_packet.num_insns - 1];
7475 if (GET_CODE (last) != INSN)
7477 insn = emit_insn_before (PATTERN (insn), last);
7478 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7479 frv_packet.insns[frv_packet.num_insns++] = last;
7483 insn = emit_insn_after (PATTERN (insn), last);
7484 frv_packet.insns[frv_packet.num_insns++] = insn;
7486 packet_group->insns[packet_group->num_insns++] = insn;
7490 /* If packing is enabled, divide the instructions into packets and
7491 return true. Call HANDLE_PACKET for each complete packet. */
7494 frv_for_each_packet (void (*handle_packet) (void))
7496 rtx insn, next_insn;
7498 frv_packet.issue_rate = frv_issue_rate ();
7500 /* Early exit if we don't want to pack insns. */
7502 || !flag_schedule_insns_after_reload
7503 || !TARGET_VLIW_BRANCH
7504 || frv_packet.issue_rate == 1)
7507 /* Set up the initial packing state. */
7509 frv_packet.dfa_state = alloca (state_size ());
7511 frv_start_packet_block ();
7512 for (insn = get_insns (); insn != 0; insn = next_insn)
7517 code = GET_CODE (insn);
7518 next_insn = NEXT_INSN (insn);
7520 if (code == CODE_LABEL)
7522 frv_finish_packet (handle_packet);
7523 frv_start_packet_block ();
7527 switch (GET_CODE (PATTERN (insn)))
7536 /* Calls mustn't be packed on a TOMCAT. */
7537 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7538 frv_finish_packet (handle_packet);
7540 /* Since the last instruction in a packet determines the EH
7541 region, any exception-throwing instruction must come at
7542 the end of reordered packet. Insns that issue to a
7543 branch unit are bound to come last; for others it's
7544 too hard to predict. */
7545 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7546 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7547 frv_finish_packet (handle_packet);
7549 /* Finish the current packet if we can't add INSN to it.
7550 Simulate cycles until INSN is ready to issue. */
7551 if (!frv_pack_insn_p (insn))
7553 frv_finish_packet (handle_packet);
7554 while (!frv_pack_insn_p (insn))
7555 state_transition (frv_packet.dfa_state, 0);
7558 /* Add the instruction to the packet. */
7559 frv_add_insn_to_packet (insn);
7561 /* Calls and jumps end a packet, as do insns that throw
7563 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7564 frv_finish_packet (handle_packet);
7568 frv_finish_packet (handle_packet);
7573 /* Subroutine of frv_sort_insn_group. We are trying to sort
7574 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7575 language order. We have already picked a new position for
7576 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7577 These instructions will occupy elements [0, LOWER_SLOT) and
7578 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7579 the DFA state after issuing these instructions.
7581 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7582 of the unused instructions. Return true if one such permutation gives
7583 a valid ordering, leaving the successful permutation in sorted[].
7584 Do not modify sorted[] until a valid permutation is found. */
7587 frv_sort_insn_group_1 (enum frv_insn_group group,
7588 unsigned int lower_slot, unsigned int upper_slot,
7589 unsigned int issued, unsigned int num_insns,
7592 struct frv_packet_group *packet_group;
7598 /* Early success if we've filled all the slots. */
7599 if (lower_slot == upper_slot)
7602 packet_group = &frv_packet.groups[group];
7603 dfa_size = state_size ();
7604 test_state = alloca (dfa_size);
7606 /* Try issuing each unused instruction. */
7607 for (i = num_insns - 1; i + 1 != 0; i--)
7608 if (~issued & (1 << i))
7610 insn = packet_group->sorted[i];
7611 memcpy (test_state, state, dfa_size);
7612 if (state_transition (test_state, insn) < 0
7613 && cpu_unit_reservation_p (test_state,
7614 NTH_UNIT (group, upper_slot - 1))
7615 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7616 issued | (1 << i), num_insns,
7619 packet_group->sorted[upper_slot - 1] = insn;
7627 /* Compare two instructions by their frv_insn_unit. */
7630 frv_compare_insns (const void *first, const void *second)
7632 const rtx *const insn1 = (rtx const *) first,
7633 *const insn2 = (rtx const *) second;
7634 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7637 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7638 and sort it into assembly language order. See frv.md for a description of
7642 frv_sort_insn_group (enum frv_insn_group group)
7644 struct frv_packet_group *packet_group;
7645 unsigned int first, i, nop, max_unit, num_slots;
7646 state_t state, test_state;
7649 packet_group = &frv_packet.groups[group];
7651 /* Assume no nop is needed. */
7652 packet_group->nop = 0;
7654 if (packet_group->num_insns == 0)
7657 /* Copy insns[] to sorted[]. */
7658 memcpy (packet_group->sorted, packet_group->insns,
7659 sizeof (rtx) * packet_group->num_insns);
7661 /* Sort sorted[] by the unit that each insn tries to take first. */
7662 if (packet_group->num_insns > 1)
7663 qsort (packet_group->sorted, packet_group->num_insns,
7664 sizeof (rtx), frv_compare_insns);
7666 /* That's always enough for branch and control insns. */
7667 if (group == GROUP_B || group == GROUP_C)
7670 dfa_size = state_size ();
7671 state = alloca (dfa_size);
7672 test_state = alloca (dfa_size);
7674 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7675 consecutively and such that the DFA takes unit X when sorted[X]
7676 is added. Set STATE to the new DFA state. */
7677 state_reset (test_state);
7678 for (first = 0; first < packet_group->num_insns; first++)
7680 memcpy (state, test_state, dfa_size);
7681 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7682 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7686 /* If all the instructions issued in ascending order, we're done. */
7687 if (first == packet_group->num_insns)
7690 /* Add nops to the end of sorted[] and try each permutation until
7691 we find one that works. */
7692 for (nop = 0; nop < frv_num_nops; nop++)
7694 max_unit = frv_insn_unit (frv_nops[nop]);
7695 if (frv_unit_groups[max_unit] == group)
7697 packet_group->nop = frv_nops[nop];
7698 num_slots = UNIT_NUMBER (max_unit) + 1;
7699 for (i = packet_group->num_insns; i < num_slots; i++)
7700 packet_group->sorted[i] = frv_nops[nop];
7701 if (frv_sort_insn_group_1 (group, first, num_slots,
7702 (1 << first) - 1, num_slots, state))
7709 /* Sort the current packet into assembly-language order. Set packing
7710 flags as appropriate. */
7713 frv_reorder_packet (void)
7715 unsigned int cursor[NUM_GROUPS];
7716 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7717 unsigned int unit, to, from;
7718 enum frv_insn_group group;
7719 struct frv_packet_group *packet_group;
7721 /* First sort each group individually. */
7722 for (group = 0; group < NUM_GROUPS; group++)
7725 frv_sort_insn_group (group);
7728 /* Go through the unit template and try add an instruction from
7729 that unit's group. */
7731 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7733 group = frv_unit_groups[unit];
7734 packet_group = &frv_packet.groups[group];
7735 if (cursor[group] < packet_group->num_insns)
7737 /* frv_reorg should have added nops for us. */
7738 gcc_assert (packet_group->sorted[cursor[group]]
7739 != packet_group->nop);
7740 insns[to++] = packet_group->sorted[cursor[group]++];
7744 gcc_assert (to == frv_packet.num_insns);
7746 /* Clear the last instruction's packing flag, thus marking the end of
7747 a packet. Reorder the other instructions relative to it. */
7748 CLEAR_PACKING_FLAG (insns[to - 1]);
7749 for (from = 0; from < to - 1; from++)
7751 remove_insn (insns[from]);
7752 add_insn_before (insns[from], insns[to - 1], NULL);
7753 SET_PACKING_FLAG (insns[from]);
7758 /* Divide instructions into packets. Reorder the contents of each
7759 packet so that they are in the correct assembly-language order.
7761 Since this pass can change the raw meaning of the rtl stream, it must
7762 only be called at the last minute, just before the instructions are
7766 frv_pack_insns (void)
7768 if (frv_for_each_packet (frv_reorder_packet))
7769 frv_insn_packing_flag = 0;
7771 frv_insn_packing_flag = -1;
7774 /* See whether we need to add nops to group GROUP in order to
7775 make a valid packet. */
7778 frv_fill_unused_units (enum frv_insn_group group)
7780 unsigned int non_nops, nops, i;
7781 struct frv_packet_group *packet_group;
7783 packet_group = &frv_packet.groups[group];
7785 /* Sort the instructions into assembly-language order.
7786 Use nops to fill slots that are otherwise unused. */
7787 frv_sort_insn_group (group);
7789 /* See how many nops are needed before the final useful instruction. */
7791 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7792 while (packet_group->sorted[i++] == packet_group->nop)
7795 /* Insert that many nops into the instruction stream. */
7797 frv_insert_nop_in_packet (packet_group->nop);
7800 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7803 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7805 if (io1->const_address != 0 && io2->const_address != 0)
7806 return io1->const_address == io2->const_address;
7808 if (io1->var_address != 0 && io2->var_address != 0)
7809 return rtx_equal_p (io1->var_address, io2->var_address);
7814 /* Return true if operations IO1 and IO2 are guaranteed to complete
7818 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7820 /* The order of writes is always preserved. */
7821 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7824 /* The order of reads isn't preserved. */
7825 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7828 /* One operation is a write and the other is (or could be) a read.
7829 The order is only guaranteed if the accesses are to the same
7831 return frv_same_doubleword_p (io1, io2);
7834 /* Generalize I/O operation X so that it covers both X and Y. */
7837 frv_io_union (struct frv_io *x, const struct frv_io *y)
7839 if (x->type != y->type)
7840 x->type = FRV_IO_UNKNOWN;
7841 if (!frv_same_doubleword_p (x, y))
7843 x->const_address = 0;
7848 /* Fill IO with information about the load or store associated with
7849 membar instruction INSN. */
7852 frv_extract_membar (struct frv_io *io, rtx insn)
7854 extract_insn (insn);
7855 io->type = INTVAL (recog_data.operand[2]);
7856 io->const_address = INTVAL (recog_data.operand[1]);
7857 io->var_address = XEXP (recog_data.operand[0], 0);
7860 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7861 if X is a register and *DATA depends on X. */
7864 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7866 rtx *other = (rtx *) data;
7868 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7872 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7873 Remove every modified register from the set. */
7876 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7878 HARD_REG_SET *set = (HARD_REG_SET *) data;
7882 FOR_EACH_REGNO (regno, x)
7883 CLEAR_HARD_REG_BIT (*set, regno);
7886 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7887 Add every register in *X to the set. */
7890 frv_io_handle_use_1 (rtx *x, void *data)
7892 HARD_REG_SET *set = (HARD_REG_SET *) data;
7896 FOR_EACH_REGNO (regno, *x)
7897 SET_HARD_REG_BIT (*set, regno);
7902 /* A note_stores callback that applies frv_io_handle_use_1 to an
7903 entire rhs value. */
7906 frv_io_handle_use (rtx *x, void *data)
7908 for_each_rtx (x, frv_io_handle_use_1, data);
7911 /* Go through block BB looking for membars to remove. There are two
7912 cases where intra-block analysis is enough:
7914 - a membar is redundant if it occurs between two consecutive I/O
7915 operations and if those operations are guaranteed to complete
7918 - a membar for a __builtin_read is redundant if the result is
7919 used before the next I/O operation is issued.
7921 If the last membar in the block could not be removed, and there
7922 are guaranteed to be no I/O operations between that membar and
7923 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7926 Describe the block's first I/O operation in *NEXT_IO. Describe
7927 an unknown operation if the block doesn't do any I/O. */
7930 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7933 HARD_REG_SET used_regs;
7934 rtx next_membar, set, insn;
7937 /* NEXT_IO is the next I/O operation to be performed after the current
7938 instruction. It starts off as being an unknown operation. */
7939 memset (next_io, 0, sizeof (*next_io));
7941 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7942 next_is_end_p = true;
7944 /* If the current instruction is a __builtin_read or __builtin_write,
7945 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7946 is null if the membar has already been deleted.
7948 Note that the initialization here should only be needed to
7949 suppress warnings. */
7952 /* USED_REGS is the set of registers that are used before the
7953 next I/O instruction. */
7954 CLEAR_HARD_REG_SET (used_regs);
7956 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7957 if (GET_CODE (insn) == CALL_INSN)
7959 /* We can't predict what a call will do to volatile memory. */
7960 memset (next_io, 0, sizeof (struct frv_io));
7961 next_is_end_p = false;
7962 CLEAR_HARD_REG_SET (used_regs);
7964 else if (INSN_P (insn))
7965 switch (recog_memoized (insn))
7967 case CODE_FOR_optional_membar_qi:
7968 case CODE_FOR_optional_membar_hi:
7969 case CODE_FOR_optional_membar_si:
7970 case CODE_FOR_optional_membar_di:
7974 /* Local information isn't enough to decide whether this
7975 membar is needed. Stash it away for later. */
7976 *last_membar = insn;
7977 frv_extract_membar (next_io, insn);
7978 next_is_end_p = false;
7982 /* Check whether the I/O operation before INSN could be
7983 reordered with one described by NEXT_IO. If it can't,
7984 INSN will not be needed. */
7985 struct frv_io prev_io;
7987 frv_extract_membar (&prev_io, insn);
7988 if (frv_io_fixed_order_p (&prev_io, next_io))
7992 ";; [Local] Removing membar %d since order"
7993 " of accesses is guaranteed\n",
7994 INSN_UID (next_membar));
7996 insn = NEXT_INSN (insn);
7997 delete_insn (next_membar);
8005 /* Invalidate NEXT_IO's address if it depends on something that
8006 is clobbered by INSN. */
8007 if (next_io->var_address)
8008 note_stores (PATTERN (insn), frv_io_check_address,
8009 &next_io->var_address);
8011 /* If the next membar is associated with a __builtin_read,
8012 see if INSN reads from that address. If it does, and if
8013 the destination register is used before the next I/O access,
8014 there is no need for the membar. */
8015 set = PATTERN (insn);
8016 if (next_io->type == FRV_IO_READ
8017 && next_io->var_address != 0
8019 && GET_CODE (set) == SET
8020 && GET_CODE (SET_DEST (set)) == REG
8021 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8025 src = SET_SRC (set);
8026 if (GET_CODE (src) == ZERO_EXTEND)
8027 src = XEXP (src, 0);
8029 if (GET_CODE (src) == MEM
8030 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8034 ";; [Local] Removing membar %d since the target"
8035 " of %d is used before the I/O operation\n",
8036 INSN_UID (next_membar), INSN_UID (insn));
8038 if (next_membar == *last_membar)
8041 delete_insn (next_membar);
8046 /* If INSN has volatile references, forget about any registers
8047 that are used after it. Otherwise forget about uses that
8048 are (or might be) defined by INSN. */
8049 if (volatile_refs_p (PATTERN (insn)))
8050 CLEAR_HARD_REG_SET (used_regs);
8052 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8054 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8059 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8060 FIRST_IO[X] describes the first operation performed by basic block X. */
8063 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8066 struct frv_io this_io, next_io;
8070 /* We need to keep the membar if there is an edge to the exit block. */
8071 FOR_EACH_EDGE (succ, ei, bb->succs)
8072 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8073 if (succ->dest == EXIT_BLOCK_PTR)
8076 /* Work out the union of all successor blocks. */
8077 ei = ei_start (bb->succs);
8078 ei_cond (ei, &succ);
8079 /* next_io = first_io[bb->succ->dest->index]; */
8080 next_io = first_io[succ->dest->index];
8081 ei = ei_start (bb->succs);
8082 if (ei_cond (ei, &succ))
8084 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8085 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8086 frv_io_union (&next_io, &first_io[succ->dest->index]);
8091 frv_extract_membar (&this_io, membar);
8092 if (frv_io_fixed_order_p (&this_io, &next_io))
8096 ";; [Global] Removing membar %d since order of accesses"
8097 " is guaranteed\n", INSN_UID (membar));
8099 delete_insn (membar);
8103 /* Remove redundant membars from the current function. */
8106 frv_optimize_membar (void)
8109 struct frv_io *first_io;
8112 compute_bb_for_insn ();
8113 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8114 last_membar = XCNEWVEC (rtx, last_basic_block);
8117 frv_optimize_membar_local (bb, &first_io[bb->index],
8118 &last_membar[bb->index]);
8121 if (last_membar[bb->index] != 0)
8122 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8128 /* Used by frv_reorg to keep track of the current packet's address. */
8129 static unsigned int frv_packet_address;
8131 /* If the current packet falls through to a label, try to pad the packet
8132 with nops in order to fit the label's alignment requirements. */
8135 frv_align_label (void)
8137 unsigned int alignment, target, nop;
8138 rtx x, last, barrier, label;
8140 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8141 maximum alignment of that packet, LABEL to the last label between
8142 the packets, and BARRIER to the last barrier. */
8143 last = frv_packet.insns[frv_packet.num_insns - 1];
8144 label = barrier = 0;
8146 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8150 unsigned int subalign = 1 << label_to_alignment (x);
8151 alignment = MAX (alignment, subalign);
8158 /* If -malign-labels, and the packet falls through to an unaligned
8159 label, try introducing a nop to align that label to 8 bytes. */
8160 if (TARGET_ALIGN_LABELS
8163 && frv_packet.num_insns < frv_packet.issue_rate)
8164 alignment = MAX (alignment, 8);
8166 /* Advance the address to the end of the current packet. */
8167 frv_packet_address += frv_packet.num_insns * 4;
8169 /* Work out the target address, after alignment. */
8170 target = (frv_packet_address + alignment - 1) & -alignment;
8172 /* If the packet falls through to the label, try to find an efficient
8173 padding sequence. */
8176 /* First try adding nops to the current packet. */
8177 for (nop = 0; nop < frv_num_nops; nop++)
8178 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8180 frv_insert_nop_in_packet (frv_nops[nop]);
8181 frv_packet_address += 4;
8184 /* If we still haven't reached the target, add some new packets that
8185 contain only nops. If there are two types of nop, insert an
8186 alternating sequence of frv_nops[0] and frv_nops[1], which will
8187 lead to packets like:
8194 etc. Just emit frv_nops[0] if that's the only nop we have. */
8195 last = frv_packet.insns[frv_packet.num_insns - 1];
8197 while (frv_packet_address < target)
8199 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8200 frv_packet_address += 4;
8201 if (frv_num_nops > 1)
8206 frv_packet_address = target;
8209 /* Subroutine of frv_reorg, called after each packet has been constructed
8213 frv_reorg_packet (void)
8215 frv_fill_unused_units (GROUP_I);
8216 frv_fill_unused_units (GROUP_FM);
8220 /* Add an instruction with pattern NOP to frv_nops[]. */
8223 frv_register_nop (rtx nop)
8225 nop = make_insn_raw (nop);
8226 NEXT_INSN (nop) = 0;
8227 PREV_INSN (nop) = 0;
8228 frv_nops[frv_num_nops++] = nop;
8231 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8232 into packets and check whether we need to insert nops in order to
8233 fulfill the processor's issue requirements. Also, if the user has
8234 requested a certain alignment for a label, try to meet that alignment
8235 by inserting nops in the previous packet. */
8240 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8241 frv_optimize_membar ();
8244 frv_register_nop (gen_nop ());
8246 frv_register_nop (gen_mnop ());
8247 if (TARGET_HARD_FLOAT)
8248 frv_register_nop (gen_fnop ());
8250 /* Estimate the length of each branch. Although this may change after
8251 we've inserted nops, it will only do so in big functions. */
8252 shorten_branches (get_insns ());
8254 frv_packet_address = 0;
8255 frv_for_each_packet (frv_reorg_packet);
8258 #define def_builtin(name, type, code) \
8259 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8261 struct builtin_description
8263 enum insn_code icode;
8265 enum frv_builtins code;
8266 enum rtx_code comparison;
8270 /* Media intrinsics that take a single, constant argument. */
8272 static struct builtin_description bdesc_set[] =
8274 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8277 /* Media intrinsics that take just one argument. */
8279 static struct builtin_description bdesc_1arg[] =
8281 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8282 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8283 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8284 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8285 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8286 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8289 /* Media intrinsics that take two arguments. */
8291 static struct builtin_description bdesc_2arg[] =
8293 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8294 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8295 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8296 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8297 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8298 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8299 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8300 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8301 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8302 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8303 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8304 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8305 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8306 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8307 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8308 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8309 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8310 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8311 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8312 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8313 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8314 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8315 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8316 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8317 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8318 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8319 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8322 /* Integer intrinsics that take two arguments and have no return value. */
8324 static struct builtin_description bdesc_int_void2arg[] =
8326 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8327 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8328 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8331 static struct builtin_description bdesc_prefetches[] =
8333 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8334 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8337 /* Media intrinsics that take two arguments, the first being an ACC number. */
8339 static struct builtin_description bdesc_cut[] =
8341 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8342 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8343 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8346 /* Two-argument media intrinsics with an immediate second argument. */
8348 static struct builtin_description bdesc_2argimm[] =
8350 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8351 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8352 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8353 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8354 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8355 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8356 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8357 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8358 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8359 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8360 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8361 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8362 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8363 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8364 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8365 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8366 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8369 /* Media intrinsics that take two arguments and return void, the first argument
8370 being a pointer to 4 words in memory. */
8372 static struct builtin_description bdesc_void2arg[] =
8374 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8375 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8378 /* Media intrinsics that take three arguments, the first being a const_int that
8379 denotes an accumulator, and that return void. */
8381 static struct builtin_description bdesc_void3arg[] =
8383 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8384 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8385 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8386 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8387 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8388 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8389 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8390 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8391 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8392 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8393 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8394 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8395 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8396 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8397 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8398 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8399 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8400 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8401 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8402 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8403 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8404 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8405 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8406 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8407 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8410 /* Media intrinsics that take two accumulator numbers as argument and
8413 static struct builtin_description bdesc_voidacc[] =
8415 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8416 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8417 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8418 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8419 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8420 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8423 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8424 a normal move and the ICODE is for the membar. */
8426 static struct builtin_description bdesc_loads[] =
8428 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8429 FRV_BUILTIN_READ8, 0, 0 },
8430 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8431 FRV_BUILTIN_READ16, 0, 0 },
8432 { CODE_FOR_optional_membar_si, "__builtin_read32",
8433 FRV_BUILTIN_READ32, 0, 0 },
8434 { CODE_FOR_optional_membar_di, "__builtin_read64",
8435 FRV_BUILTIN_READ64, 0, 0 }
8438 /* Likewise stores. */
8440 static struct builtin_description bdesc_stores[] =
8442 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8443 FRV_BUILTIN_WRITE8, 0, 0 },
8444 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8445 FRV_BUILTIN_WRITE16, 0, 0 },
8446 { CODE_FOR_optional_membar_si, "__builtin_write32",
8447 FRV_BUILTIN_WRITE32, 0, 0 },
8448 { CODE_FOR_optional_membar_di, "__builtin_write64",
8449 FRV_BUILTIN_WRITE64, 0, 0 },
8452 /* Initialize media builtins. */
8455 frv_init_builtins (void)
8457 tree endlink = void_list_node;
8458 tree accumulator = integer_type_node;
8459 tree integer = integer_type_node;
8460 tree voidt = void_type_node;
8461 tree uhalf = short_unsigned_type_node;
8462 tree sword1 = long_integer_type_node;
8463 tree uword1 = long_unsigned_type_node;
8464 tree sword2 = long_long_integer_type_node;
8465 tree uword2 = long_long_unsigned_type_node;
8466 tree uword4 = build_pointer_type (uword1);
8467 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8468 tree ubyte = unsigned_char_type_node;
8469 tree iacc = integer_type_node;
8471 #define UNARY(RET, T1) \
8472 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8474 #define BINARY(RET, T1, T2) \
8475 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8476 tree_cons (NULL_TREE, T2, endlink)))
8478 #define TRINARY(RET, T1, T2, T3) \
8479 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8480 tree_cons (NULL_TREE, T2, \
8481 tree_cons (NULL_TREE, T3, endlink))))
8483 #define QUAD(RET, T1, T2, T3, T4) \
8484 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8485 tree_cons (NULL_TREE, T2, \
8486 tree_cons (NULL_TREE, T3, \
8487 tree_cons (NULL_TREE, T4, endlink)))))
8489 tree void_ftype_void = build_function_type (voidt, endlink);
8491 tree void_ftype_acc = UNARY (voidt, accumulator);
8492 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8493 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8494 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8495 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8496 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8497 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8498 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8499 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8501 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8502 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8503 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8504 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8505 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8506 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8507 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8508 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8509 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8510 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8511 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8513 tree sw1_ftype_int = UNARY (sword1, integer);
8514 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8515 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8517 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8518 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8519 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8520 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8521 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8522 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8524 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8525 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8526 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8527 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8528 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8529 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8530 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8531 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8532 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8533 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8534 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8535 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8536 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8537 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8538 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8539 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8540 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8542 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8543 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8544 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8545 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8546 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8547 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8548 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8549 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8550 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8551 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8552 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8553 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8554 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8555 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8556 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8557 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8558 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8559 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8560 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8561 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8562 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8563 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8564 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8565 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8566 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8567 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8568 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8569 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8570 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8571 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8572 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8573 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8574 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8575 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8576 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8577 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8578 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8579 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8580 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8581 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8582 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8583 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8584 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8585 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8586 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8587 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8588 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8589 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8590 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8591 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8592 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8593 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8594 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8595 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8596 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8597 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8598 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8599 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8600 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8601 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8602 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8603 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8604 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8605 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8606 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8607 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8608 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8609 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8610 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8611 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8612 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8613 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8614 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8615 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8616 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8617 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8618 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8619 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8620 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8621 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8622 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8623 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8624 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8625 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8626 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8627 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8628 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8629 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8630 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8631 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8632 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8633 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8634 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8635 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8636 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8637 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8638 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8639 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8640 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8641 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8642 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8643 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8644 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8645 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8646 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8647 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8648 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8649 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8651 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8652 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8653 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8654 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8662 /* Set the names for various arithmetic operations according to the
8665 frv_init_libfuncs (void)
8667 set_optab_libfunc (smod_optab, SImode, "__modi");
8668 set_optab_libfunc (umod_optab, SImode, "__umodi");
8670 set_optab_libfunc (add_optab, DImode, "__addll");
8671 set_optab_libfunc (sub_optab, DImode, "__subll");
8672 set_optab_libfunc (smul_optab, DImode, "__mulll");
8673 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8674 set_optab_libfunc (smod_optab, DImode, "__modll");
8675 set_optab_libfunc (umod_optab, DImode, "__umodll");
8676 set_optab_libfunc (and_optab, DImode, "__andll");
8677 set_optab_libfunc (ior_optab, DImode, "__orll");
8678 set_optab_libfunc (xor_optab, DImode, "__xorll");
8679 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8681 set_optab_libfunc (add_optab, SFmode, "__addf");
8682 set_optab_libfunc (sub_optab, SFmode, "__subf");
8683 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8684 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8686 set_optab_libfunc (add_optab, DFmode, "__addd");
8687 set_optab_libfunc (sub_optab, DFmode, "__subd");
8688 set_optab_libfunc (smul_optab, DFmode, "__muld");
8689 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8691 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8692 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8694 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8695 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8696 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8697 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8699 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8700 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8701 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8702 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8704 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8705 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8706 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8707 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8710 /* Convert an integer constant to an accumulator register. ICODE is the
8711 code of the target instruction, OPNUM is the number of the
8712 accumulator operand and OPVAL is the constant integer. Try both
8713 ACC and ACCG registers; only report an error if neither fit the
8717 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8722 /* ACCs and ACCGs are implicit global registers if media intrinsics
8723 are being used. We set up this lazily to avoid creating lots of
8724 unnecessary call_insn rtl in non-media code. */
8725 for (i = 0; i <= ACC_MASK; i++)
8726 if ((i & ACC_MASK) == i)
8727 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8729 if (GET_CODE (opval) != CONST_INT)
8731 error ("accumulator is not a constant integer");
8734 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8736 error ("accumulator number is out of bounds");
8740 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8741 ACC_FIRST + INTVAL (opval));
8742 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8743 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8745 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8747 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8753 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8756 static enum machine_mode
8757 frv_matching_accg_mode (enum machine_mode mode)
8775 /* Given that a __builtin_read or __builtin_write function is accessing
8776 address ADDRESS, return the value that should be used as operand 1
8780 frv_io_address_cookie (rtx address)
8782 return (GET_CODE (address) == CONST_INT
8783 ? GEN_INT (INTVAL (address) / 8 * 8)
8787 /* Return the accumulator guard that should be paired with accumulator
8788 register ACC. The mode of the returned register is in the same
8789 class as ACC, but is four times smaller. */
8792 frv_matching_accg_for_acc (rtx acc)
8794 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8795 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8798 /* Read the requested argument from the call EXP given by INDEX.
8799 Return the value as an rtx. */
8802 frv_read_argument (tree exp, unsigned int index)
8804 return expand_expr (CALL_EXPR_ARG (exp, index),
8805 NULL_RTX, VOIDmode, 0);
8808 /* Like frv_read_argument, but interpret the argument as the number
8809 of an IACC register and return a (reg:MODE ...) rtx for it. */
8812 frv_read_iacc_argument (enum machine_mode mode, tree call,
8818 op = frv_read_argument (call, index);
8819 if (GET_CODE (op) != CONST_INT
8821 || INTVAL (op) > IACC_LAST - IACC_FIRST
8822 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8824 error ("invalid IACC argument");
8828 /* IACCs are implicit global registers. We set up this lazily to
8829 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8831 regno = INTVAL (op) + IACC_FIRST;
8832 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8833 global_regs[regno + i] = 1;
8835 return gen_rtx_REG (mode, regno);
8838 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8839 The instruction should require a constant operand of some sort. The
8840 function prints an error if OPVAL is not valid. */
8843 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8845 if (GET_CODE (opval) != CONST_INT)
8847 error ("%qs expects a constant argument", insn_data[icode].name);
8850 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8852 error ("constant argument out of range for %qs", insn_data[icode].name);
8858 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8859 if it's not null, has the right mode, and satisfies operand 0's
8863 frv_legitimize_target (enum insn_code icode, rtx target)
8865 enum machine_mode mode = insn_data[icode].operand[0].mode;
8868 || GET_MODE (target) != mode
8869 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8870 return gen_reg_rtx (mode);
8875 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8876 check whether ARG satisfies the operand's constraints. If it doesn't,
8877 copy ARG to a temporary register and return that. Otherwise return ARG
8881 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8883 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8885 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8888 return copy_to_mode_reg (mode, arg);
8891 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8894 frv_volatile_memref (enum machine_mode mode, rtx arg)
8898 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8899 MEM_VOLATILE_P (mem) = 1;
8903 /* Expand builtins that take a single, constant argument. At the moment,
8904 only MHDSETS falls into this category. */
8907 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8910 rtx op0 = frv_read_argument (call, 0);
8912 if (! frv_check_constant_argument (icode, 1, op0))
8915 target = frv_legitimize_target (icode, target);
8916 pat = GEN_FCN (icode) (target, op0);
8924 /* Expand builtins that take one operand. */
8927 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8930 rtx op0 = frv_read_argument (call, 0);
8932 target = frv_legitimize_target (icode, target);
8933 op0 = frv_legitimize_argument (icode, 1, op0);
8934 pat = GEN_FCN (icode) (target, op0);
8942 /* Expand builtins that take two operands. */
8945 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8948 rtx op0 = frv_read_argument (call, 0);
8949 rtx op1 = frv_read_argument (call, 1);
8951 target = frv_legitimize_target (icode, target);
8952 op0 = frv_legitimize_argument (icode, 1, op0);
8953 op1 = frv_legitimize_argument (icode, 2, op1);
8954 pat = GEN_FCN (icode) (target, op0, op1);
8962 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8966 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8969 rtx op0 = frv_read_argument (call, 0);
8970 rtx op1 = frv_read_argument (call, 1);
8973 target = frv_legitimize_target (icode, target);
8974 op0 = frv_int_to_acc (icode, 1, op0);
8978 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8980 if (! frv_check_constant_argument (icode, 2, op1))
8984 op1 = frv_legitimize_argument (icode, 2, op1);
8986 op2 = frv_matching_accg_for_acc (op0);
8987 pat = GEN_FCN (icode) (target, op0, op1, op2);
8995 /* Expand builtins that take two operands and the second is immediate. */
8998 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
9001 rtx op0 = frv_read_argument (call, 0);
9002 rtx op1 = frv_read_argument (call, 1);
9004 if (! frv_check_constant_argument (icode, 2, op1))
9007 target = frv_legitimize_target (icode, target);
9008 op0 = frv_legitimize_argument (icode, 1, op0);
9009 pat = GEN_FCN (icode) (target, op0, op1);
9017 /* Expand builtins that take two operands, the first operand being a pointer to
9018 ints and return void. */
9021 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9024 rtx op0 = frv_read_argument (call, 0);
9025 rtx op1 = frv_read_argument (call, 1);
9026 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9029 if (GET_CODE (op0) != MEM)
9033 if (! offsettable_address_p (0, mode0, op0))
9035 reg = gen_reg_rtx (Pmode);
9036 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9039 op0 = gen_rtx_MEM (SImode, reg);
9042 addr = XEXP (op0, 0);
9043 if (! offsettable_address_p (0, mode0, addr))
9044 addr = copy_to_mode_reg (Pmode, op0);
9046 op0 = change_address (op0, V4SImode, addr);
9047 op1 = frv_legitimize_argument (icode, 1, op1);
9048 pat = GEN_FCN (icode) (op0, op1);
9056 /* Expand builtins that take two long operands and return void. */
9059 frv_expand_int_void2arg (enum insn_code icode, tree call)
9062 rtx op0 = frv_read_argument (call, 0);
9063 rtx op1 = frv_read_argument (call, 1);
9065 op0 = frv_legitimize_argument (icode, 1, op0);
9066 op1 = frv_legitimize_argument (icode, 1, op1);
9067 pat = GEN_FCN (icode) (op0, op1);
9075 /* Expand prefetch builtins. These take a single address as argument. */
9078 frv_expand_prefetches (enum insn_code icode, tree call)
9081 rtx op0 = frv_read_argument (call, 0);
9083 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9091 /* Expand builtins that take three operands and return void. The first
9092 argument must be a constant that describes a pair or quad accumulators. A
9093 fourth argument is created that is the accumulator guard register that
9094 corresponds to the accumulator. */
9097 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9100 rtx op0 = frv_read_argument (call, 0);
9101 rtx op1 = frv_read_argument (call, 1);
9102 rtx op2 = frv_read_argument (call, 2);
9105 op0 = frv_int_to_acc (icode, 0, op0);
9109 op1 = frv_legitimize_argument (icode, 1, op1);
9110 op2 = frv_legitimize_argument (icode, 2, op2);
9111 op3 = frv_matching_accg_for_acc (op0);
9112 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9120 /* Expand builtins that perform accumulator-to-accumulator operations.
9121 These builtins take two accumulator numbers as argument and return
9125 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9128 rtx op0 = frv_read_argument (call, 0);
9129 rtx op1 = frv_read_argument (call, 1);
9133 op0 = frv_int_to_acc (icode, 0, op0);
9137 op1 = frv_int_to_acc (icode, 1, op1);
9141 op2 = frv_matching_accg_for_acc (op0);
9142 op3 = frv_matching_accg_for_acc (op1);
9143 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9151 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9152 membar and TARGET_MODE is the mode that the loaded value should have. */
9155 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9156 tree call, rtx target)
9158 rtx op0 = frv_read_argument (call, 0);
9159 rtx cookie = frv_io_address_cookie (op0);
9161 if (target == 0 || !REG_P (target))
9162 target = gen_reg_rtx (target_mode);
9163 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9164 convert_move (target, op0, 1);
9165 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9166 cfun->machine->has_membar_p = 1;
9170 /* Likewise __builtin_write* functions. */
9173 frv_expand_store_builtin (enum insn_code icode, tree call)
9175 rtx op0 = frv_read_argument (call, 0);
9176 rtx op1 = frv_read_argument (call, 1);
9177 rtx cookie = frv_io_address_cookie (op0);
9179 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9180 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9181 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9182 cfun->machine->has_membar_p = 1;
9186 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9187 each argument forms one word of the two double-word input registers.
9188 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9189 to put the return value. */
9192 frv_expand_mdpackh_builtin (tree call, rtx target)
9194 enum insn_code icode = CODE_FOR_mdpackh;
9196 rtx arg1 = frv_read_argument (call, 0);
9197 rtx arg2 = frv_read_argument (call, 1);
9198 rtx arg3 = frv_read_argument (call, 2);
9199 rtx arg4 = frv_read_argument (call, 3);
9201 target = frv_legitimize_target (icode, target);
9202 op0 = gen_reg_rtx (DImode);
9203 op1 = gen_reg_rtx (DImode);
9205 /* The high half of each word is not explicitly initialized, so indicate
9206 that the input operands are not live before this point. */
9210 /* Move each argument into the low half of its associated input word. */
9211 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9212 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9213 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9214 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9216 pat = GEN_FCN (icode) (target, op0, op1);
9224 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9225 number as argument. */
9228 frv_expand_mclracc_builtin (tree call)
9230 enum insn_code icode = CODE_FOR_mclracc;
9232 rtx op0 = frv_read_argument (call, 0);
9234 op0 = frv_int_to_acc (icode, 0, op0);
9238 pat = GEN_FCN (icode) (op0);
9245 /* Expand builtins that take no arguments. */
9248 frv_expand_noargs_builtin (enum insn_code icode)
9250 rtx pat = GEN_FCN (icode) (const0_rtx);
9257 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9258 number or accumulator guard number as argument and return an SI integer. */
9261 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9264 rtx target = gen_reg_rtx (SImode);
9265 rtx op0 = frv_read_argument (call, 0);
9267 op0 = frv_int_to_acc (icode, 1, op0);
9271 pat = GEN_FCN (icode) (target, op0);
9279 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9280 accumulator guard as their first argument and an SImode value as their
9284 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9287 rtx op0 = frv_read_argument (call, 0);
9288 rtx op1 = frv_read_argument (call, 1);
9290 op0 = frv_int_to_acc (icode, 0, op0);
9294 op1 = frv_legitimize_argument (icode, 1, op1);
9295 pat = GEN_FCN (icode) (op0, op1);
9302 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9303 to move DImode values into and out of IACC0. */
9306 frv_split_iacc_move (rtx dest, rtx src)
9308 enum machine_mode inner;
9311 inner = GET_MODE (dest);
9312 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9313 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9314 simplify_gen_subreg (SImode, src, inner, i));
9317 /* Expand builtins. */
9320 frv_expand_builtin (tree exp,
9322 rtx subtarget ATTRIBUTE_UNUSED,
9323 enum machine_mode mode ATTRIBUTE_UNUSED,
9324 int ignore ATTRIBUTE_UNUSED)
9326 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9327 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9329 struct builtin_description *d;
9331 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9333 error ("media functions are not available unless -mmedia is used");
9339 case FRV_BUILTIN_MCOP1:
9340 case FRV_BUILTIN_MCOP2:
9341 case FRV_BUILTIN_MDUNPACKH:
9342 case FRV_BUILTIN_MBTOHE:
9343 if (! TARGET_MEDIA_REV1)
9345 error ("this media function is only available on the fr500");
9350 case FRV_BUILTIN_MQXMACHS:
9351 case FRV_BUILTIN_MQXMACXHS:
9352 case FRV_BUILTIN_MQMACXHS:
9353 case FRV_BUILTIN_MADDACCS:
9354 case FRV_BUILTIN_MSUBACCS:
9355 case FRV_BUILTIN_MASACCS:
9356 case FRV_BUILTIN_MDADDACCS:
9357 case FRV_BUILTIN_MDSUBACCS:
9358 case FRV_BUILTIN_MDASACCS:
9359 case FRV_BUILTIN_MABSHS:
9360 case FRV_BUILTIN_MDROTLI:
9361 case FRV_BUILTIN_MCPLHI:
9362 case FRV_BUILTIN_MCPLI:
9363 case FRV_BUILTIN_MDCUTSSI:
9364 case FRV_BUILTIN_MQSATHS:
9365 case FRV_BUILTIN_MHSETLOS:
9366 case FRV_BUILTIN_MHSETLOH:
9367 case FRV_BUILTIN_MHSETHIS:
9368 case FRV_BUILTIN_MHSETHIH:
9369 case FRV_BUILTIN_MHDSETS:
9370 case FRV_BUILTIN_MHDSETH:
9371 if (! TARGET_MEDIA_REV2)
9373 error ("this media function is only available on the fr400"
9379 case FRV_BUILTIN_SMASS:
9380 case FRV_BUILTIN_SMSSS:
9381 case FRV_BUILTIN_SMU:
9382 case FRV_BUILTIN_ADDSS:
9383 case FRV_BUILTIN_SUBSS:
9384 case FRV_BUILTIN_SLASS:
9385 case FRV_BUILTIN_SCUTSS:
9386 case FRV_BUILTIN_IACCreadll:
9387 case FRV_BUILTIN_IACCreadl:
9388 case FRV_BUILTIN_IACCsetll:
9389 case FRV_BUILTIN_IACCsetl:
9390 if (!TARGET_FR405_BUILTINS)
9392 error ("this builtin function is only available"
9393 " on the fr405 and fr450");
9398 case FRV_BUILTIN_PREFETCH:
9399 if (!TARGET_FR500_FR550_BUILTINS)
9401 error ("this builtin function is only available on the fr500"
9407 case FRV_BUILTIN_MQLCLRHS:
9408 case FRV_BUILTIN_MQLMTHS:
9409 case FRV_BUILTIN_MQSLLHI:
9410 case FRV_BUILTIN_MQSRAHI:
9411 if (!TARGET_MEDIA_FR450)
9413 error ("this builtin function is only available on the fr450");
9422 /* Expand unique builtins. */
9426 case FRV_BUILTIN_MTRAP:
9427 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9429 case FRV_BUILTIN_MCLRACC:
9430 return frv_expand_mclracc_builtin (exp);
9432 case FRV_BUILTIN_MCLRACCA:
9434 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9436 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9438 case FRV_BUILTIN_MRDACC:
9439 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9441 case FRV_BUILTIN_MRDACCG:
9442 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9444 case FRV_BUILTIN_MWTACC:
9445 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9447 case FRV_BUILTIN_MWTACCG:
9448 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9450 case FRV_BUILTIN_MDPACKH:
9451 return frv_expand_mdpackh_builtin (exp, target);
9453 case FRV_BUILTIN_IACCreadll:
9455 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9456 if (target == 0 || !REG_P (target))
9457 target = gen_reg_rtx (DImode);
9458 frv_split_iacc_move (target, src);
9462 case FRV_BUILTIN_IACCreadl:
9463 return frv_read_iacc_argument (SImode, exp, 0);
9465 case FRV_BUILTIN_IACCsetll:
9467 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9468 rtx src = frv_read_argument (exp, 1);
9469 frv_split_iacc_move (dest, force_reg (DImode, src));
9473 case FRV_BUILTIN_IACCsetl:
9475 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9476 rtx src = frv_read_argument (exp, 1);
9477 emit_move_insn (dest, force_reg (SImode, src));
9485 /* Expand groups of builtins. */
9487 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9488 if (d->code == fcode)
9489 return frv_expand_set_builtin (d->icode, exp, target);
9491 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9492 if (d->code == fcode)
9493 return frv_expand_unop_builtin (d->icode, exp, target);
9495 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9496 if (d->code == fcode)
9497 return frv_expand_binop_builtin (d->icode, exp, target);
9499 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9500 if (d->code == fcode)
9501 return frv_expand_cut_builtin (d->icode, exp, target);
9503 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9504 if (d->code == fcode)
9505 return frv_expand_binopimm_builtin (d->icode, exp, target);
9507 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9508 if (d->code == fcode)
9509 return frv_expand_voidbinop_builtin (d->icode, exp);
9511 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9512 if (d->code == fcode)
9513 return frv_expand_voidtriop_builtin (d->icode, exp);
9515 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9516 if (d->code == fcode)
9517 return frv_expand_voidaccop_builtin (d->icode, exp);
9519 for (i = 0, d = bdesc_int_void2arg;
9520 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9521 if (d->code == fcode)
9522 return frv_expand_int_void2arg (d->icode, exp);
9524 for (i = 0, d = bdesc_prefetches;
9525 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9526 if (d->code == fcode)
9527 return frv_expand_prefetches (d->icode, exp);
9529 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9530 if (d->code == fcode)
9531 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9534 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9535 if (d->code == fcode)
9536 return frv_expand_store_builtin (d->icode, exp);
9542 frv_in_small_data_p (const_tree decl)
9545 const_tree section_name;
9547 /* Don't apply the -G flag to internal compiler structures. We
9548 should leave such structures in the main data section, partly
9549 for efficiency and partly because the size of some of them
9550 (such as C++ typeinfos) is not known until later. */
9551 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9554 /* If we already know which section the decl should be in, see if
9555 it's a small data section. */
9556 section_name = DECL_SECTION_NAME (decl);
9559 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9560 if (frv_string_begins_with (section_name, ".sdata"))
9562 if (frv_string_begins_with (section_name, ".sbss"))
9567 size = int_size_in_bytes (TREE_TYPE (decl));
9568 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9575 frv_rtx_costs (rtx x,
9576 int code ATTRIBUTE_UNUSED,
9577 int outer_code ATTRIBUTE_UNUSED,
9579 bool speed ATTRIBUTE_UNUSED)
9581 if (outer_code == MEM)
9583 /* Don't differentiate between memory addresses. All the ones
9584 we accept have equal cost. */
9585 *total = COSTS_N_INSNS (0);
9592 /* Make 12-bit integers really cheap. */
9593 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9604 *total = COSTS_N_INSNS (2);
9618 if (GET_MODE (x) == SImode)
9619 *total = COSTS_N_INSNS (1);
9620 else if (GET_MODE (x) == DImode)
9621 *total = COSTS_N_INSNS (2);
9623 *total = COSTS_N_INSNS (3);
9627 if (GET_MODE (x) == SImode)
9628 *total = COSTS_N_INSNS (2);
9630 *total = COSTS_N_INSNS (6); /* guess */
9637 *total = COSTS_N_INSNS (18);
9641 *total = COSTS_N_INSNS (3);
9650 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9652 switch_to_section (ctors_section);
9653 assemble_align (POINTER_SIZE);
9656 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9661 assemble_integer_with_op ("\t.picptr\t", symbol);
9665 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9667 switch_to_section (dtors_section);
9668 assemble_align (POINTER_SIZE);
9671 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9676 assemble_integer_with_op ("\t.picptr\t", symbol);
9679 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9682 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9683 int incoming ATTRIBUTE_UNUSED)
9685 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9688 #define TLS_BIAS (2048 - 16)
9690 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9691 We need to emit DTP-relative relocations. */
9694 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9696 gcc_assert (size == 4);
9697 fputs ("\t.picptr\ttlsmoff(", file);
9698 /* We want the unbiased TLS offset, so add the bias to the
9699 expression, such that the implicit biasing cancels out. */
9700 output_addr_const (file, plus_constant (x, TLS_BIAS));