1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "basic-block.h"
48 #include "target-def.h"
49 #include "targhooks.h"
50 #include "integrate.h"
51 #include "langhooks.h"
55 #define FRV_INLINE inline
58 /* The maximum number of distinct NOP patterns. There are three:
59 nop, fnop and mnop. */
60 #define NUM_NOP_PATTERNS 3
62 /* Classification of instructions and units: integer, floating-point/media,
63 branch and control. */
64 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
66 /* The DFA names of the units, in packet order. */
67 static const char *const frv_unit_names[] =
77 /* The classification of each unit in frv_unit_names[]. */
78 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
88 /* Return the DFA unit code associated with the Nth unit of integer
89 or floating-point group GROUP, */
90 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
92 /* Return the number of integer or floating-point unit UNIT
93 (1 for I1, 2 for F2, etc.). */
94 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
96 /* The DFA unit number for each unit in frv_unit_names[]. */
97 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
99 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
100 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
101 no instruction of type T has been seen. */
102 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
104 /* An array of dummy nop INSNs, one for each type of nop that the
106 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
108 /* The number of nop instructions in frv_nops[]. */
109 static unsigned int frv_num_nops;
111 /* The type of access. FRV_IO_UNKNOWN means the access can be either
112 a read or a write. */
113 enum frv_io_type { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE };
115 /* Information about one __builtin_read or __builtin_write access, or
116 the combination of several such accesses. The most general value
117 is all-zeros (an unknown access to an unknown address). */
119 enum frv_io_type type;
121 /* The constant address being accessed, or zero if not known. */
122 HOST_WIDE_INT const_address;
124 /* The run-time address, as used in operand 0 of the membar pattern. */
128 /* Return true if instruction INSN should be packed with the following
130 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
132 /* Set the value of PACKING_FLAG_P(INSN). */
133 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
134 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
136 /* Loop with REG set to each hard register in rtx X. */
137 #define FOR_EACH_REGNO(REG, X) \
138 for (REG = REGNO (X); \
139 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
142 /* This structure contains machine specific function data. */
143 struct GTY(()) machine_function
145 /* True if we have created an rtx that relies on the stack frame. */
148 /* True if this function contains at least one __builtin_{read,write}*. */
152 /* Temporary register allocation support structure. */
153 typedef struct frv_tmp_reg_struct
155 HARD_REG_SET regs; /* possible registers to allocate */
156 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
160 /* Register state information for VLIW re-packing phase. */
161 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
162 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
163 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
164 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
166 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
168 typedef unsigned char regstate_t;
170 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
178 /* Information required by frv_frame_access. */
181 /* This field is FRV_LOAD if registers are to be loaded from the stack and
182 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
183 the move is being done by the prologue code while FRV_LOAD implies it
184 is being done by the epilogue. */
185 enum frv_stack_op op;
187 /* The base register to use when accessing the stack. This may be the
188 frame pointer, stack pointer, or a temporary. The choice of register
189 depends on which part of the frame is being accessed and how big the
193 /* The offset of BASE from the bottom of the current frame, in bytes. */
195 } frv_frame_accessor_t;
197 /* Conditional execution support gathered together in one structure. */
200 /* Linked list of insns to add if the conditional execution conversion was
201 successful. Each link points to an EXPR_LIST which points to the pattern
202 of the insn to add, and the insn to be inserted before. */
203 rtx added_insns_list;
205 /* Identify which registers are safe to allocate for if conversions to
206 conditional execution. We keep the last allocated register in the
207 register classes between COND_EXEC statements. This will mean we allocate
208 different registers for each different COND_EXEC group if we can. This
209 might allow the scheduler to intermix two different COND_EXEC sections. */
210 frv_tmp_reg_t tmp_reg;
212 /* For nested IFs, identify which CC registers are used outside of setting
213 via a compare isnsn, and using via a check insn. This will allow us to
214 know if we can rewrite the register to use a different register that will
215 be paired with the CR register controlling the nested IF-THEN blocks. */
216 HARD_REG_SET nested_cc_ok_rewrite;
218 /* Temporary registers allocated to hold constants during conditional
220 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
222 /* Current number of temp registers available. */
223 int cur_scratch_regs;
225 /* Number of nested conditional execution blocks. */
226 int num_nested_cond_exec;
228 /* Map of insns that set up constants in scratch registers. */
229 bitmap scratch_insns_bitmap;
231 /* Conditional execution test register (CC0..CC7). */
234 /* Conditional execution compare register that is paired with cr_reg, so that
235 nested compares can be done. The csubcc and caddcc instructions don't
236 have enough bits to specify both a CC register to be set and a CR register
237 to do the test on, so the same bit number is used for both. Needless to
238 say, this is rather inconvenient for GCC. */
241 /* Extra CR registers used for &&, ||. */
245 /* Previous CR used in nested if, to make sure we are dealing with the same
246 nested if as the previous statement. */
247 rtx last_nested_if_cr;
251 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
253 /* Map register number to smallest register class. */
254 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
256 /* Map class letter into register class. */
257 enum reg_class reg_class_from_letter[256];
259 /* Cached value of frv_stack_info. */
260 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
263 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
265 /* Forward references */
267 static bool frv_handle_option (size_t, const char *, int);
268 static void frv_option_override (void);
269 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
270 static int frv_default_flags_for_cpu (void);
271 static int frv_string_begins_with (const_tree, const char *);
272 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
273 static void frv_print_operand (FILE *, rtx, int);
274 static void frv_print_operand_address (FILE *, rtx);
275 static bool frv_print_operand_punct_valid_p (unsigned char code);
276 static void frv_print_operand_memory_reference_reg
278 static void frv_print_operand_memory_reference (FILE *, rtx, int);
279 static int frv_print_operand_jump_hint (rtx);
280 static const char *comparison_string (enum rtx_code, rtx);
281 static rtx frv_function_value (const_tree, const_tree,
283 static rtx frv_libcall_value (enum machine_mode,
285 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
286 static rtx single_set_pattern (rtx);
287 static int frv_function_contains_far_jump (void);
288 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
292 static rtx frv_frame_offset_rtx (int);
293 static rtx frv_frame_mem (enum machine_mode, rtx, int);
294 static rtx frv_dwarf_store (rtx, int);
295 static void frv_frame_insn (rtx, rtx);
296 static void frv_frame_access (frv_frame_accessor_t*,
298 static void frv_frame_access_multi (frv_frame_accessor_t*,
300 static void frv_frame_access_standard_regs (enum frv_stack_op,
302 static struct machine_function *frv_init_machine_status (void);
303 static rtx frv_int_to_acc (enum insn_code, int, rtx);
304 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
305 static rtx frv_read_argument (tree, unsigned int);
306 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
307 static int frv_check_constant_argument (enum insn_code, int, rtx);
308 static rtx frv_legitimize_target (enum insn_code, rtx);
309 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
310 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
311 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
312 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
313 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
314 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
315 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
316 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
317 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
318 static rtx frv_expand_int_void2arg (enum insn_code, tree);
319 static rtx frv_expand_prefetches (enum insn_code, tree);
320 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
321 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
322 static rtx frv_expand_mclracc_builtin (tree);
323 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
324 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
325 static rtx frv_expand_noargs_builtin (enum insn_code);
326 static void frv_split_iacc_move (rtx, rtx);
327 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
328 static int frv_clear_registers_used (rtx *, void *);
329 static void frv_ifcvt_add_insn (rtx, rtx, int);
330 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
331 static rtx frv_ifcvt_load_value (rtx, rtx);
332 static int frv_acc_group_1 (rtx *, void *);
333 static unsigned int frv_insn_unit (rtx);
334 static bool frv_issues_to_branch_unit_p (rtx);
335 static int frv_cond_flags (rtx);
336 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
337 static int frv_registers_conflict_p_1 (rtx *, void *);
338 static bool frv_registers_conflict_p (rtx);
339 static void frv_registers_update_1 (rtx, const_rtx, void *);
340 static void frv_registers_update (rtx);
341 static void frv_start_packet (void);
342 static void frv_start_packet_block (void);
343 static void frv_finish_packet (void (*) (void));
344 static bool frv_pack_insn_p (rtx);
345 static void frv_add_insn_to_packet (rtx);
346 static void frv_insert_nop_in_packet (rtx);
347 static bool frv_for_each_packet (void (*) (void));
348 static bool frv_sort_insn_group_1 (enum frv_insn_group,
349 unsigned int, unsigned int,
350 unsigned int, unsigned int,
352 static int frv_compare_insns (const void *, const void *);
353 static void frv_sort_insn_group (enum frv_insn_group);
354 static void frv_reorder_packet (void);
355 static void frv_fill_unused_units (enum frv_insn_group);
356 static void frv_align_label (void);
357 static void frv_reorg_packet (void);
358 static void frv_register_nop (rtx);
359 static void frv_reorg (void);
360 static void frv_pack_insns (void);
361 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
362 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
363 static bool frv_assemble_integer (rtx, unsigned, int);
364 static void frv_init_builtins (void);
365 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
366 static void frv_init_libfuncs (void);
367 static bool frv_in_small_data_p (const_tree);
368 static void frv_asm_output_mi_thunk
369 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
370 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
373 static rtx frv_expand_builtin_saveregs (void);
374 static void frv_expand_builtin_va_start (tree, rtx);
375 static bool frv_rtx_costs (rtx, int, int, int*, bool);
376 static int frv_register_move_cost (enum machine_mode,
377 reg_class_t, reg_class_t);
378 static int frv_memory_move_cost (enum machine_mode,
380 static void frv_asm_out_constructor (rtx, int);
381 static void frv_asm_out_destructor (rtx, int);
382 static bool frv_function_symbol_referenced_p (rtx);
383 static bool frv_cannot_force_const_mem (rtx);
384 static const char *unspec_got_name (int);
385 static void frv_output_const_unspec (FILE *,
386 const struct frv_unspec *);
387 static bool frv_function_ok_for_sibcall (tree, tree);
388 static rtx frv_struct_value_rtx (tree, int);
389 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
390 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
392 static rtx frv_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
394 static rtx frv_function_incoming_arg (CUMULATIVE_ARGS *, enum machine_mode,
396 static void frv_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
398 static unsigned int frv_function_arg_boundary (enum machine_mode,
400 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
402 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
404 secondary_reload_info *);
405 static bool frv_frame_pointer_required (void);
406 static bool frv_can_eliminate (const int, const int);
407 static void frv_conditional_register_usage (void);
408 static void frv_trampoline_init (rtx, tree, rtx);
409 static bool frv_class_likely_spilled_p (reg_class_t);
411 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
412 static const struct default_options frv_option_optimization_table[] =
414 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
415 { OPT_LEVELS_NONE, 0, NULL, 0 }
418 /* Allow us to easily change the default for -malloc-cc. */
419 #ifndef DEFAULT_NO_ALLOC_CC
420 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
422 #define MASK_DEFAULT_ALLOC_CC 0
425 /* Initialize the GCC target structure. */
426 #undef TARGET_PRINT_OPERAND
427 #define TARGET_PRINT_OPERAND frv_print_operand
428 #undef TARGET_PRINT_OPERAND_ADDRESS
429 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
430 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
431 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
432 #undef TARGET_ASM_FUNCTION_PROLOGUE
433 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
434 #undef TARGET_ASM_FUNCTION_EPILOGUE
435 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
436 #undef TARGET_ASM_INTEGER
437 #define TARGET_ASM_INTEGER frv_assemble_integer
438 #undef TARGET_DEFAULT_TARGET_FLAGS
439 #define TARGET_DEFAULT_TARGET_FLAGS \
440 (MASK_DEFAULT_ALLOC_CC \
447 #undef TARGET_HANDLE_OPTION
448 #define TARGET_HANDLE_OPTION frv_handle_option
449 #undef TARGET_OPTION_OVERRIDE
450 #define TARGET_OPTION_OVERRIDE frv_option_override
451 #undef TARGET_OPTION_OPTIMIZATION_TABLE
452 #define TARGET_OPTION_OPTIMIZATION_TABLE frv_option_optimization_table
453 #undef TARGET_INIT_BUILTINS
454 #define TARGET_INIT_BUILTINS frv_init_builtins
455 #undef TARGET_EXPAND_BUILTIN
456 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
457 #undef TARGET_INIT_LIBFUNCS
458 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
459 #undef TARGET_IN_SMALL_DATA_P
460 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
461 #undef TARGET_REGISTER_MOVE_COST
462 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
463 #undef TARGET_MEMORY_MOVE_COST
464 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
465 #undef TARGET_RTX_COSTS
466 #define TARGET_RTX_COSTS frv_rtx_costs
467 #undef TARGET_ASM_CONSTRUCTOR
468 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
469 #undef TARGET_ASM_DESTRUCTOR
470 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
472 #undef TARGET_ASM_OUTPUT_MI_THUNK
473 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
474 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
475 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
477 #undef TARGET_SCHED_ISSUE_RATE
478 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
480 #undef TARGET_LEGITIMIZE_ADDRESS
481 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
483 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
484 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
485 #undef TARGET_CANNOT_FORCE_CONST_MEM
486 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
488 #undef TARGET_HAVE_TLS
489 #define TARGET_HAVE_TLS HAVE_AS_TLS
491 #undef TARGET_STRUCT_VALUE_RTX
492 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
493 #undef TARGET_MUST_PASS_IN_STACK
494 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
495 #undef TARGET_PASS_BY_REFERENCE
496 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
497 #undef TARGET_ARG_PARTIAL_BYTES
498 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
499 #undef TARGET_FUNCTION_ARG
500 #define TARGET_FUNCTION_ARG frv_function_arg
501 #undef TARGET_FUNCTION_INCOMING_ARG
502 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
503 #undef TARGET_FUNCTION_ARG_ADVANCE
504 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
505 #undef TARGET_FUNCTION_ARG_BOUNDARY
506 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
508 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
509 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
510 #undef TARGET_SETUP_INCOMING_VARARGS
511 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
512 #undef TARGET_MACHINE_DEPENDENT_REORG
513 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
515 #undef TARGET_EXPAND_BUILTIN_VA_START
516 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
519 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
520 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
523 #undef TARGET_CLASS_LIKELY_SPILLED_P
524 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
526 #undef TARGET_SECONDARY_RELOAD
527 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
529 #undef TARGET_LEGITIMATE_ADDRESS_P
530 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
532 #undef TARGET_FRAME_POINTER_REQUIRED
533 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
535 #undef TARGET_CAN_ELIMINATE
536 #define TARGET_CAN_ELIMINATE frv_can_eliminate
538 #undef TARGET_CONDITIONAL_REGISTER_USAGE
539 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
541 #undef TARGET_TRAMPOLINE_INIT
542 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
544 #undef TARGET_FUNCTION_VALUE
545 #define TARGET_FUNCTION_VALUE frv_function_value
546 #undef TARGET_LIBCALL_VALUE
547 #define TARGET_LIBCALL_VALUE frv_libcall_value
549 struct gcc_target targetm = TARGET_INITIALIZER;
551 #define FRV_SYMBOL_REF_TLS_P(RTX) \
552 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
555 /* Any function call that satisfies the machine-independent
556 requirements is eligible on FR-V. */
559 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
560 tree exp ATTRIBUTE_UNUSED)
565 /* Return true if SYMBOL is a small data symbol and relocation RELOC
566 can be used to access it directly in a load or store. */
568 static FRV_INLINE bool
569 frv_small_data_reloc_p (rtx symbol, int reloc)
571 return (GET_CODE (symbol) == SYMBOL_REF
572 && SYMBOL_REF_SMALL_P (symbol)
573 && (!TARGET_FDPIC || flag_pic == 1)
574 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
577 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
581 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
583 if (GET_CODE (x) == CONST)
587 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
589 unspec->offset += INTVAL (XEXP (x, 1));
592 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
594 unspec->symbol = XVECEXP (x, 0, 0);
595 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
597 if (unspec->offset == 0)
600 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
601 && unspec->offset > 0
602 && unspec->offset < g_switch_value)
609 /* Decide whether we can force certain constants to memory. If we
610 decide we can't, the caller should be able to cope with it in
613 We never allow constants to be forced into memory for TARGET_FDPIC.
614 This is necessary for several reasons:
616 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
617 target-independent code will try to force them into the constant
618 pool, thus leading to infinite recursion.
620 2. We can never introduce new constant pool references during reload.
621 Any such reference would require use of the pseudo FDPIC register.
623 3. We can't represent a constant added to a function pointer (which is
624 not the same as a pointer to a function+constant).
626 4. In many cases, it's more efficient to calculate the constant in-line. */
629 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
634 /* Implement TARGET_HANDLE_OPTION. */
637 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
642 if (strcmp (arg, "simple") == 0)
643 frv_cpu_type = FRV_CPU_SIMPLE;
644 else if (strcmp (arg, "tomcat") == 0)
645 frv_cpu_type = FRV_CPU_TOMCAT;
646 else if (strcmp (arg, "fr550") == 0)
647 frv_cpu_type = FRV_CPU_FR550;
648 else if (strcmp (arg, "fr500") == 0)
649 frv_cpu_type = FRV_CPU_FR500;
650 else if (strcmp (arg, "fr450") == 0)
651 frv_cpu_type = FRV_CPU_FR450;
652 else if (strcmp (arg, "fr405") == 0)
653 frv_cpu_type = FRV_CPU_FR405;
654 else if (strcmp (arg, "fr400") == 0)
655 frv_cpu_type = FRV_CPU_FR400;
656 else if (strcmp (arg, "fr300") == 0)
657 frv_cpu_type = FRV_CPU_FR300;
658 else if (strcmp (arg, "frv") == 0)
659 frv_cpu_type = FRV_CPU_GENERIC;
670 frv_default_flags_for_cpu (void)
672 switch (frv_cpu_type)
674 case FRV_CPU_GENERIC:
675 return MASK_DEFAULT_FRV;
678 return MASK_DEFAULT_FR550;
682 return MASK_DEFAULT_FR500;
685 return MASK_DEFAULT_FR450;
689 return MASK_DEFAULT_FR400;
693 return MASK_DEFAULT_SIMPLE;
700 /* Implement TARGET_OPTION_OVERRIDE. */
703 frv_option_override (void)
708 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
710 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
711 linker about linking pic and non-pic code. */
714 if (!flag_pic) /* -fPIC */
717 if (!global_options_set.x_g_switch_value) /* -G0 */
723 /* A C expression whose value is a register class containing hard
724 register REGNO. In general there is more than one such class;
725 choose a class which is "minimal", meaning that no smaller class
726 also contains the register. */
728 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
730 enum reg_class rclass;
734 int gpr_reg = regno - GPR_FIRST;
736 if (gpr_reg == GR8_REG)
739 else if (gpr_reg == GR9_REG)
742 else if (gpr_reg == GR14_REG)
743 rclass = FDPIC_FPTR_REGS;
745 else if (gpr_reg == FDPIC_REGNO)
748 else if ((gpr_reg & 3) == 0)
751 else if ((gpr_reg & 1) == 0)
758 else if (FPR_P (regno))
760 int fpr_reg = regno - GPR_FIRST;
761 if ((fpr_reg & 3) == 0)
762 rclass = QUAD_FPR_REGS;
764 else if ((fpr_reg & 1) == 0)
771 else if (regno == LR_REGNO)
774 else if (regno == LCR_REGNO)
777 else if (ICC_P (regno))
780 else if (FCC_P (regno))
783 else if (ICR_P (regno))
786 else if (FCR_P (regno))
789 else if (ACC_P (regno))
791 int r = regno - ACC_FIRST;
793 rclass = QUAD_ACC_REGS;
794 else if ((r & 1) == 0)
795 rclass = EVEN_ACC_REGS;
800 else if (ACCG_P (regno))
806 regno_reg_class[regno] = rclass;
809 /* Check for small data option */
810 if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC)
811 g_switch_value = SDATA_DEFAULT_SIZE;
813 /* A C expression which defines the machine-dependent operand
814 constraint letters for register classes. If CHAR is such a
815 letter, the value should be the register class corresponding to
816 it. Otherwise, the value should be `NO_REGS'. The register
817 letter `r', corresponding to class `GENERAL_REGS', will not be
818 passed to this macro; you do not need to handle it.
820 The following letters are unavailable, due to being used as
825 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
826 'Q', 'R', 'S', 'T', 'U'
828 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
830 for (i = 0; i < 256; i++)
831 reg_class_from_letter[i] = NO_REGS;
833 reg_class_from_letter['a'] = ACC_REGS;
834 reg_class_from_letter['b'] = EVEN_ACC_REGS;
835 reg_class_from_letter['c'] = CC_REGS;
836 reg_class_from_letter['d'] = GPR_REGS;
837 reg_class_from_letter['e'] = EVEN_REGS;
838 reg_class_from_letter['f'] = FPR_REGS;
839 reg_class_from_letter['h'] = FEVEN_REGS;
840 reg_class_from_letter['l'] = LR_REG;
841 reg_class_from_letter['q'] = QUAD_REGS;
842 reg_class_from_letter['t'] = ICC_REGS;
843 reg_class_from_letter['u'] = FCC_REGS;
844 reg_class_from_letter['v'] = ICR_REGS;
845 reg_class_from_letter['w'] = FCR_REGS;
846 reg_class_from_letter['x'] = QUAD_FPR_REGS;
847 reg_class_from_letter['y'] = LCR_REG;
848 reg_class_from_letter['z'] = SPR_REGS;
849 reg_class_from_letter['A'] = QUAD_ACC_REGS;
850 reg_class_from_letter['B'] = ACCG_REGS;
851 reg_class_from_letter['C'] = CR_REGS;
852 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
853 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
855 /* There is no single unaligned SI op for PIC code. Sometimes we
856 need to use ".4byte" and sometimes we need to use ".picptr".
857 See frv_assemble_integer for details. */
858 if (flag_pic || TARGET_FDPIC)
859 targetm.asm_out.unaligned_op.si = 0;
861 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
862 target_flags |= MASK_LINKED_FP;
864 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
865 target_flags |= MASK_OPTIMIZE_MEMBAR;
867 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
868 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
870 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
871 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
873 init_machine_status = frv_init_machine_status;
877 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
880 frv_string_begins_with (const_tree name, const char *prefix)
882 const int prefix_len = strlen (prefix);
884 /* Remember: NAME's length includes the null terminator. */
885 return (TREE_STRING_LENGTH (name) > prefix_len
886 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
889 /* Zero or more C statements that may conditionally modify two variables
890 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
891 been initialized from the two preceding macros.
893 This is necessary in case the fixed or call-clobbered registers depend on
896 You need not define this macro if it has no work to do.
898 If the usage of an entire class of registers depends on the target flags,
899 you may indicate this to GCC by using this macro to modify `fixed_regs' and
900 `call_used_regs' to 1 for each of the registers in the classes which should
901 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
902 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
904 (However, if this class is not included in `GENERAL_REGS' and all of the
905 insn patterns whose constraints permit this class are controlled by target
906 switches, then GCC will automatically avoid using these registers when the
907 target switches are opposed to them.) */
910 frv_conditional_register_usage (void)
914 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
915 fixed_regs[i] = call_used_regs[i] = 1;
917 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
918 fixed_regs[i] = call_used_regs[i] = 1;
920 /* Reserve the registers used for conditional execution. At present, we need
921 1 ICC and 1 ICR register. */
922 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
923 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
927 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
928 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
929 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
930 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
934 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
935 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
938 /* If -fpic, SDA_BASE_REG is the PIC register. */
939 if (g_switch_value == 0 && !flag_pic)
940 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
943 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
949 * Compute the stack frame layout
952 * +---------------+-----------------------+-----------------------+
953 * |Register |type |caller-save/callee-save|
954 * +---------------+-----------------------+-----------------------+
955 * |GR0 |Zero register | - |
956 * |GR1 |Stack pointer(SP) | - |
957 * |GR2 |Frame pointer(FP) | - |
958 * |GR3 |Hidden parameter | caller save |
959 * |GR4-GR7 | - | caller save |
960 * |GR8-GR13 |Argument register | caller save |
961 * |GR14-GR15 | - | caller save |
962 * |GR16-GR31 | - | callee save |
963 * |GR32-GR47 | - | caller save |
964 * |GR48-GR63 | - | callee save |
965 * |FR0-FR15 | - | caller save |
966 * |FR16-FR31 | - | callee save |
967 * |FR32-FR47 | - | caller save |
968 * |FR48-FR63 | - | callee save |
969 * +---------------+-----------------------+-----------------------+
973 * SP-> |-----------------------------------|
975 * |-----------------------------------|
976 * | Register save area |
977 * |-----------------------------------|
978 * | Local variable save area |
979 * FP-> |-----------------------------------|
981 * |-----------------------------------|
982 * | Hidden parameter save area |
983 * |-----------------------------------|
984 * | Return address(LR) storage area |
985 * |-----------------------------------|
986 * | Padding for alignment |
987 * |-----------------------------------|
988 * | Register argument area |
989 * OLD SP-> |-----------------------------------|
991 * |-----------------------------------|
994 * Argument area/Parameter area:
996 * When a function is called, this area is used for argument transfer. When
997 * the argument is set up by the caller function, this area is referred to as
998 * the argument area. When the argument is referenced by the callee function,
999 * this area is referred to as the parameter area. The area is allocated when
1000 * all arguments cannot be placed on the argument register at the time of
1001 * argument transfer.
1003 * Register save area:
1005 * This is a register save area that must be guaranteed for the caller
1006 * function. This area is not secured when the register save operation is not
1009 * Local variable save area:
1011 * This is the area for local variables and temporary variables.
1015 * This area stores the FP value of the caller function.
1017 * Hidden parameter save area:
1019 * This area stores the start address of the return value storage
1020 * area for a struct/union return function.
1021 * When a struct/union is used as the return value, the caller
1022 * function stores the return value storage area start address in
1023 * register GR3 and passes it to the caller function.
1024 * The callee function interprets the address stored in the GR3
1025 * as the return value storage area start address.
1026 * When register GR3 needs to be saved into memory, the callee
1027 * function saves it in the hidden parameter save area. This
1028 * area is not secured when the save operation is not needed.
1030 * Return address(LR) storage area:
1032 * This area saves the LR. The LR stores the address of a return to the caller
1033 * function for the purpose of function calling.
1035 * Argument register area:
1037 * This area saves the argument register. This area is not secured when the
1038 * save operation is not needed.
1042 * Arguments, the count of which equals the count of argument registers (6
1043 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1044 * function. When a struct/union return function is called, the return value
1045 * area address is stored in register GR3. Arguments not placed in the
1046 * argument registers will be stored in the stack argument area for transfer
1047 * purposes. When an 8-byte type argument is to be delivered using registers,
1048 * it is divided into two and placed in two registers for transfer. When
1049 * argument registers must be saved to memory, the callee function secures an
1050 * argument register save area in the stack. In this case, a continuous
1051 * argument register save area must be established in the parameter area. The
1052 * argument register save area must be allocated as needed to cover the size of
1053 * the argument register to be saved. If the function has a variable count of
1054 * arguments, it saves all argument registers in the argument register save
1057 * Argument Extension Format:
1059 * When an argument is to be stored in the stack, its type is converted to an
1060 * extended type in accordance with the individual argument type. The argument
1061 * is freed by the caller function after the return from the callee function is
1064 * +-----------------------+---------------+------------------------+
1065 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1066 * +-----------------------+---------------+------------------------+
1068 * |signed char |int | 4 |
1069 * |unsigned char |int | 4 |
1070 * |[signed] short int |int | 4 |
1071 * |unsigned short int |int | 4 |
1072 * |[signed] int |No extension | 4 |
1073 * |unsigned int |No extension | 4 |
1074 * |[signed] long int |No extension | 4 |
1075 * |unsigned long int |No extension | 4 |
1076 * |[signed] long long int |No extension | 8 |
1077 * |unsigned long long int |No extension | 8 |
1078 * |float |double | 8 |
1079 * |double |No extension | 8 |
1080 * |long double |No extension | 8 |
1081 * |pointer |No extension | 4 |
1082 * |struct/union |- | 4 (*1) |
1083 * +-----------------------+---------------+------------------------+
1085 * When a struct/union is to be delivered as an argument, the caller copies it
1086 * to the local variable area and delivers the address of that area.
1090 * +-------------------------------+----------------------+
1091 * |Return Value Type |Return Value Interface|
1092 * +-------------------------------+----------------------+
1094 * |[signed|unsigned] char |GR8 |
1095 * |[signed|unsigned] short int |GR8 |
1096 * |[signed|unsigned] int |GR8 |
1097 * |[signed|unsigned] long int |GR8 |
1099 * |[signed|unsigned] long long int|GR8 & GR9 |
1101 * |double |GR8 & GR9 |
1102 * |long double |GR8 & GR9 |
1103 * |struct/union |(*1) |
1104 * +-------------------------------+----------------------+
1106 * When a struct/union is used as the return value, the caller function stores
1107 * the start address of the return value storage area into GR3 and then passes
1108 * it to the callee function. The callee function interprets GR3 as the start
1109 * address of the return value storage area. When this address needs to be
1110 * saved in memory, the callee function secures the hidden parameter save area
1111 * and saves the address in that area.
1115 frv_stack_info (void)
1117 static frv_stack_t info, zero_info;
1118 frv_stack_t *info_ptr = &info;
1119 tree fndecl = current_function_decl;
1127 /* If we've already calculated the values and reload is complete,
1129 if (frv_stack_cache)
1130 return frv_stack_cache;
1132 /* Zero all fields. */
1135 /* Set up the register range information. */
1136 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1137 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1138 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1139 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1141 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1142 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1143 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1144 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1146 info_ptr->regs[STACK_REGS_LR].name = "lr";
1147 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1148 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1149 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1151 info_ptr->regs[STACK_REGS_CC].name = "cc";
1152 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1153 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1154 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1156 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1157 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1158 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1160 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1161 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1162 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1163 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1164 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1166 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1167 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1168 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1169 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1171 info_ptr->regs[STACK_REGS_FP].name = "fp";
1172 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1173 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1174 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1176 /* Determine if this is a stdarg function. If so, allocate space to store
1183 /* Find the last argument, and see if it is __builtin_va_alist. */
1184 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1186 next_arg = DECL_CHAIN (cur_arg);
1187 if (next_arg == (tree)0)
1189 if (DECL_NAME (cur_arg)
1190 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1198 /* Iterate over all of the register ranges. */
1199 for (range = 0; range < STACK_REGS_MAX; range++)
1201 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1202 int first = reg_ptr->first;
1203 int last = reg_ptr->last;
1205 int size_2words = 0;
1208 /* Calculate which registers need to be saved & save area size. */
1212 for (regno = first; regno <= last; regno++)
1214 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1215 || (crtl->calls_eh_return
1216 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1217 || (!TARGET_FDPIC && flag_pic
1218 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1220 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1221 size_1word += UNITS_PER_WORD;
1226 /* Calculate whether we need to create a frame after everything else
1227 has been processed. */
1232 if (df_regs_ever_live_p (LR_REGNO)
1234 /* This is set for __builtin_return_address, etc. */
1235 || cfun->machine->frame_needed
1236 || (TARGET_LINKED_FP && frame_pointer_needed)
1237 || (!TARGET_FDPIC && flag_pic
1238 && crtl->uses_pic_offset_table))
1240 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1241 size_1word += UNITS_PER_WORD;
1245 case STACK_REGS_STDARG:
1248 /* If this is a stdarg function with a non varardic
1249 argument split between registers and the stack,
1250 adjust the saved registers downward. */
1251 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1254 for (regno = first; regno <= last; regno++)
1256 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1257 size_1word += UNITS_PER_WORD;
1260 info_ptr->stdarg_size = size_1word;
1264 case STACK_REGS_STRUCT:
1265 if (cfun->returns_struct)
1267 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1268 size_1word += UNITS_PER_WORD;
1276 /* If this is a field, it only takes one word. */
1277 if (reg_ptr->field_p)
1278 size_1word = UNITS_PER_WORD;
1280 /* Determine which register pairs can be saved together. */
1281 else if (reg_ptr->dword_p && TARGET_DWORD)
1283 for (regno = first; regno < last; regno += 2)
1285 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1287 size_2words += 2 * UNITS_PER_WORD;
1288 size_1word -= 2 * UNITS_PER_WORD;
1289 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1290 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1295 reg_ptr->size_1word = size_1word;
1296 reg_ptr->size_2words = size_2words;
1298 if (! reg_ptr->special_p)
1300 info_ptr->regs_size_1word += size_1word;
1301 info_ptr->regs_size_2words += size_2words;
1306 /* Set up the sizes of each each field in the frame body, making the sizes
1307 of each be divisible by the size of a dword if dword operations might
1308 be used, or the size of a word otherwise. */
1309 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1311 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1312 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1313 + info_ptr->regs_size_1word,
1315 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1317 info_ptr->pretend_size = crtl->args.pretend_args_size;
1319 /* Work out the size of the frame, excluding the header. Both the frame
1320 body and register parameter area will be dword-aligned. */
1321 info_ptr->total_size
1322 = (ADDR_ALIGN (info_ptr->parameter_size
1323 + info_ptr->regs_size
1324 + info_ptr->vars_size,
1326 + ADDR_ALIGN (info_ptr->pretend_size
1327 + info_ptr->stdarg_size,
1328 2 * UNITS_PER_WORD));
1330 /* See if we need to create a frame at all, if so add header area. */
1331 if (info_ptr->total_size > 0
1332 || frame_pointer_needed
1333 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1334 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1336 offset = info_ptr->parameter_size;
1337 info_ptr->header_size = 4 * UNITS_PER_WORD;
1338 info_ptr->total_size += 4 * UNITS_PER_WORD;
1340 /* Calculate the offsets to save normal register pairs. */
1341 for (range = 0; range < STACK_REGS_MAX; range++)
1343 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1344 if (! reg_ptr->special_p)
1346 int first = reg_ptr->first;
1347 int last = reg_ptr->last;
1350 for (regno = first; regno <= last; regno++)
1351 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1352 && regno != FRAME_POINTER_REGNUM
1353 && (regno < FIRST_ARG_REGNUM
1354 || regno > LAST_ARG_REGNUM))
1356 info_ptr->reg_offset[regno] = offset;
1357 offset += 2 * UNITS_PER_WORD;
1362 /* Calculate the offsets to save normal single registers. */
1363 for (range = 0; range < STACK_REGS_MAX; range++)
1365 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1366 if (! reg_ptr->special_p)
1368 int first = reg_ptr->first;
1369 int last = reg_ptr->last;
1372 for (regno = first; regno <= last; regno++)
1373 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1374 && regno != FRAME_POINTER_REGNUM
1375 && (regno < FIRST_ARG_REGNUM
1376 || regno > LAST_ARG_REGNUM))
1378 info_ptr->reg_offset[regno] = offset;
1379 offset += UNITS_PER_WORD;
1384 /* Calculate the offset to save the local variables at. */
1385 offset = ADDR_ALIGN (offset, alignment);
1386 if (info_ptr->vars_size)
1388 info_ptr->vars_offset = offset;
1389 offset += info_ptr->vars_size;
1392 /* Align header to a dword-boundary. */
1393 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1395 /* Calculate the offsets in the fixed frame. */
1396 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1397 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1398 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1400 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1401 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1402 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1404 if (cfun->returns_struct)
1406 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1407 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1408 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1411 /* Calculate the offsets to store the arguments passed in registers
1412 for stdarg functions. The register pairs are first and the single
1413 register if any is last. The register save area starts on a
1415 if (info_ptr->stdarg_size)
1417 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1418 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1421 /* Skip the header. */
1422 offset += 4 * UNITS_PER_WORD;
1423 for (regno = first; regno <= last; regno++)
1425 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1427 info_ptr->reg_offset[regno] = offset;
1428 offset += 2 * UNITS_PER_WORD;
1430 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1432 info_ptr->reg_offset[regno] = offset;
1433 offset += UNITS_PER_WORD;
1439 if (reload_completed)
1440 frv_stack_cache = info_ptr;
1446 /* Print the information about the frv stack offsets, etc. when debugging. */
1449 frv_debug_stack (frv_stack_t *info)
1454 info = frv_stack_info ();
1456 fprintf (stderr, "\nStack information for function %s:\n",
1457 ((current_function_decl && DECL_NAME (current_function_decl))
1458 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1461 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1462 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1463 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1464 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1465 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1467 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1468 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1469 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1470 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1472 for (range = 0; range < STACK_REGS_MAX; range++)
1474 frv_stack_regs_t *regs = &(info->regs[range]);
1475 if ((regs->size_1word + regs->size_2words) > 0)
1477 int first = regs->first;
1478 int last = regs->last;
1481 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1482 regs->name, regs->size_1word + regs->size_2words,
1483 regs->size_1word, regs->size_2words);
1485 for (regno = first; regno <= last; regno++)
1487 if (info->save_p[regno] == REG_SAVE_1WORD)
1488 fprintf (stderr, " %s (%d)", reg_names[regno],
1489 info->reg_offset[regno]);
1491 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1492 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1493 reg_names[regno+1], info->reg_offset[regno]);
1496 fputc ('\n', stderr);
1506 /* Used during final to control the packing of insns. The value is
1507 1 if the current instruction should be packed with the next one,
1508 0 if it shouldn't or -1 if packing is disabled altogether. */
1510 static int frv_insn_packing_flag;
1512 /* True if the current function contains a far jump. */
1515 frv_function_contains_far_jump (void)
1517 rtx insn = get_insns ();
1519 && !(GET_CODE (insn) == JUMP_INSN
1520 /* Ignore tablejump patterns. */
1521 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1522 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1523 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1524 insn = NEXT_INSN (insn);
1525 return (insn != NULL);
1528 /* For the FRV, this function makes sure that a function with far jumps
1529 will return correctly. It also does the VLIW packing. */
1532 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1534 /* If no frame was created, check whether the function uses a call
1535 instruction to implement a far jump. If so, save the link in gr3 and
1536 replace all returns to LR with returns to GR3. GR3 is used because it
1537 is call-clobbered, because is not available to the register allocator,
1538 and because all functions that take a hidden argument pointer will have
1540 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1544 /* Just to check that the above comment is true. */
1545 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1547 /* Generate the instruction that saves the link register. */
1548 fprintf (file, "\tmovsg lr,gr3\n");
1550 /* Replace the LR with GR3 in *return_internal patterns. The insn
1551 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1552 simply emit a different assembly directive because bralr and jmpl
1553 execute in different units. */
1554 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1555 if (GET_CODE (insn) == JUMP_INSN)
1557 rtx pattern = PATTERN (insn);
1558 if (GET_CODE (pattern) == PARALLEL
1559 && XVECLEN (pattern, 0) >= 2
1560 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1561 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1563 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1564 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1565 SET_REGNO (address, GPR_FIRST + 3);
1572 /* Allow the garbage collector to free the nops created by frv_reorg. */
1573 memset (frv_nops, 0, sizeof (frv_nops));
1577 /* Return the next available temporary register in a given class. */
1580 frv_alloc_temp_reg (
1581 frv_tmp_reg_t *info, /* which registers are available */
1582 enum reg_class rclass, /* register class desired */
1583 enum machine_mode mode, /* mode to allocate register with */
1584 int mark_as_used, /* register not available after allocation */
1585 int no_abort) /* return NULL instead of aborting */
1587 int regno = info->next_reg[ (int)rclass ];
1588 int orig_regno = regno;
1589 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1594 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1595 && TEST_HARD_REG_BIT (info->regs, regno))
1598 if (++regno >= FIRST_PSEUDO_REGISTER)
1600 if (regno == orig_regno)
1602 gcc_assert (no_abort);
1607 nr = HARD_REGNO_NREGS (regno, mode);
1608 info->next_reg[ (int)rclass ] = regno + nr;
1611 for (i = 0; i < nr; i++)
1612 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1614 return gen_rtx_REG (mode, regno);
1618 /* Return an rtx with the value OFFSET, which will either be a register or a
1619 signed 12-bit integer. It can be used as the second operand in an "add"
1620 instruction, or as the index in a load or store.
1622 The function returns a constant rtx if OFFSET is small enough, otherwise
1623 it loads the constant into register OFFSET_REGNO and returns that. */
1625 frv_frame_offset_rtx (int offset)
1627 rtx offset_rtx = GEN_INT (offset);
1628 if (IN_RANGE_P (offset, -2048, 2047))
1632 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1633 if (IN_RANGE_P (offset, -32768, 32767))
1634 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1637 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1638 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1644 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1645 prologue and epilogue uses such expressions to access the stack. */
1647 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1649 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1651 frv_frame_offset_rtx (offset)));
1654 /* Generate a frame-related expression:
1656 (set REG (mem (plus (sp) (const_int OFFSET)))).
1658 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1659 instructions. Marking the expressions as frame-related is superfluous if
1660 the note contains just a single set. But if the note contains a PARALLEL
1661 or SEQUENCE that has several sets, each set must be individually marked
1662 as frame-related. */
1664 frv_dwarf_store (rtx reg, int offset)
1666 rtx set = gen_rtx_SET (VOIDmode,
1667 gen_rtx_MEM (GET_MODE (reg),
1668 plus_constant (stack_pointer_rtx,
1671 RTX_FRAME_RELATED_P (set) = 1;
1675 /* Emit a frame-related instruction whose pattern is PATTERN. The
1676 instruction is the last in a sequence that cumulatively performs the
1677 operation described by DWARF_PATTERN. The instruction is marked as
1678 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1681 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1683 rtx insn = emit_insn (pattern);
1684 RTX_FRAME_RELATED_P (insn) = 1;
1685 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1690 /* Emit instructions that transfer REG to or from the memory location (sp +
1691 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1692 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1693 function to store registers and only the epilogue uses it to load them.
1695 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1696 The generated instruction will use BASE as its base register. BASE may
1697 simply be the stack pointer, but if several accesses are being made to a
1698 region far away from the stack pointer, it may be more efficient to set
1699 up a temporary instead.
1701 Store instructions will be frame-related and will be annotated with the
1702 overall effect of the store. Load instructions will be followed by a
1703 (use) to prevent later optimizations from zapping them.
1705 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1706 as a temporary in such cases. */
1708 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1710 enum machine_mode mode = GET_MODE (reg);
1711 rtx mem = frv_frame_mem (mode,
1713 stack_offset - accessor->base_offset);
1715 if (accessor->op == FRV_LOAD)
1717 if (SPR_P (REGNO (reg)))
1719 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1720 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1721 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1725 /* We cannot use reg+reg addressing for DImode access. */
1727 && GET_CODE (XEXP (mem, 0)) == PLUS
1728 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1729 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1731 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1733 emit_move_insn (temp,
1734 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1735 XEXP (XEXP (mem, 0), 1)));
1736 mem = gen_rtx_MEM (DImode, temp);
1738 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1744 if (SPR_P (REGNO (reg)))
1746 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1747 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1748 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1749 frv_dwarf_store (reg, stack_offset));
1751 else if (mode == DImode)
1753 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1754 with a separate save for each register. */
1755 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1756 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1757 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1758 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1760 /* Also we cannot use reg+reg addressing. */
1761 if (GET_CODE (XEXP (mem, 0)) == PLUS
1762 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1763 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1765 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1766 emit_move_insn (temp,
1767 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1768 XEXP (XEXP (mem, 0), 1)));
1769 mem = gen_rtx_MEM (DImode, temp);
1772 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1773 gen_rtx_PARALLEL (VOIDmode,
1774 gen_rtvec (2, set1, set2)));
1777 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1778 frv_dwarf_store (reg, stack_offset));
1782 /* A function that uses frv_frame_access to transfer a group of registers to
1783 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1784 is the stack information generated by frv_stack_info, and REG_SET is the
1785 number of the register set to transfer. */
1787 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1791 frv_stack_regs_t *regs_info;
1794 regs_info = &info->regs[reg_set];
1795 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1796 if (info->save_p[regno])
1797 frv_frame_access (accessor,
1798 info->save_p[regno] == REG_SAVE_2WORDS
1799 ? gen_rtx_REG (DImode, regno)
1800 : gen_rtx_REG (SImode, regno),
1801 info->reg_offset[regno]);
1804 /* Save or restore callee-saved registers that are kept outside the frame
1805 header. The function saves the registers if OP is FRV_STORE and restores
1806 them if OP is FRV_LOAD. INFO is the stack information generated by
1809 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1811 frv_frame_accessor_t accessor;
1814 accessor.base = stack_pointer_rtx;
1815 accessor.base_offset = 0;
1816 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1817 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1818 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1822 /* Called after register allocation to add any instructions needed for the
1823 prologue. Using a prologue insn is favored compared to putting all of the
1824 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1825 it allows the scheduler to intermix instructions with the saves of
1826 the caller saved registers. In some cases, it might be necessary
1827 to emit a barrier instruction as the last insn to prevent such
1830 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1831 so that the debug info generation code can handle them properly. */
1833 frv_expand_prologue (void)
1835 frv_stack_t *info = frv_stack_info ();
1836 rtx sp = stack_pointer_rtx;
1837 rtx fp = frame_pointer_rtx;
1838 frv_frame_accessor_t accessor;
1840 if (TARGET_DEBUG_STACK)
1841 frv_debug_stack (info);
1843 if (info->total_size == 0)
1846 /* We're interested in three areas of the frame here:
1848 A: the register save area
1850 C: the header after B
1852 If the frame pointer isn't used, we'll have to set up A, B and C
1853 using the stack pointer. If the frame pointer is used, we'll access
1857 B: set up using sp or a temporary (see below)
1860 We set up B using the stack pointer if the frame is small enough.
1861 Otherwise, it's more efficient to copy the old stack pointer into a
1862 temporary and use that.
1864 Note that it's important to make sure the prologue and epilogue use the
1865 same registers to access A and C, since doing otherwise will confuse
1866 the aliasing code. */
1868 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1869 isn't used, the same method will serve for C. */
1870 accessor.op = FRV_STORE;
1871 if (frame_pointer_needed && info->total_size > 2048)
1873 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1874 accessor.base_offset = info->total_size;
1875 emit_insn (gen_movsi (accessor.base, sp));
1879 accessor.base = stack_pointer_rtx;
1880 accessor.base_offset = 0;
1883 /* Allocate the stack space. */
1885 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1886 rtx dwarf_offset = GEN_INT (-info->total_size);
1888 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1891 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1894 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1895 and point the new one to that location. */
1896 if (frame_pointer_needed)
1898 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1900 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1901 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1903 rtx asm_src = plus_constant (accessor.base,
1904 fp_offset - accessor.base_offset);
1905 rtx dwarf_src = plus_constant (sp, fp_offset);
1907 /* Store the old frame pointer at (sp + FP_OFFSET). */
1908 frv_frame_access (&accessor, fp, fp_offset);
1910 /* Set up the new frame pointer. */
1911 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1912 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1914 /* Access region C from the frame pointer. */
1916 accessor.base_offset = fp_offset;
1919 /* Set up region C. */
1920 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1921 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1922 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1924 /* Set up region A. */
1925 frv_frame_access_standard_regs (FRV_STORE, info);
1927 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1928 scheduler from moving loads before the stores saving the registers. */
1929 if (info->stdarg_size > 0)
1930 emit_insn (gen_blockage ());
1932 /* Set up pic register/small data register for this function. */
1933 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1934 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1935 gen_rtx_REG (Pmode, LR_REGNO),
1936 gen_rtx_REG (SImode, OFFSET_REGNO)));
1940 /* Under frv, all of the work is done via frv_expand_epilogue, but
1941 this function provides a convenient place to do cleanup. */
1944 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1945 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1947 frv_stack_cache = (frv_stack_t *)0;
1949 /* Zap last used registers for conditional execution. */
1950 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1952 /* Release the bitmap of created insns. */
1953 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1957 /* Called after register allocation to add any instructions needed for the
1958 epilogue. Using an epilogue insn is favored compared to putting all of the
1959 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1960 it allows the scheduler to intermix instructions with the saves of
1961 the caller saved registers. In some cases, it might be necessary
1962 to emit a barrier instruction as the last insn to prevent such
1966 frv_expand_epilogue (bool emit_return)
1968 frv_stack_t *info = frv_stack_info ();
1969 rtx fp = frame_pointer_rtx;
1970 rtx sp = stack_pointer_rtx;
1974 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1976 /* Restore the stack pointer to its original value if alloca or the like
1978 if (! current_function_sp_is_unchanging)
1979 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1981 /* Restore the callee-saved registers that were used in this function. */
1982 frv_frame_access_standard_regs (FRV_LOAD, info);
1984 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1985 no return instruction should be emitted. */
1986 if (info->save_p[LR_REGNO])
1991 /* Use the same method to access the link register's slot as we did in
1992 the prologue. In other words, use the frame pointer if available,
1993 otherwise use the stack pointer.
1995 LR_OFFSET is the offset of the link register's slot from the start
1996 of the frame and MEM is a memory rtx for it. */
1997 lr_offset = info->reg_offset[LR_REGNO];
1998 if (frame_pointer_needed)
1999 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
2001 mem = frv_frame_mem (Pmode, sp, lr_offset);
2003 /* Load the old link register into a GPR. */
2004 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
2005 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
2008 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
2010 /* Restore the old frame pointer. Emit a USE afterwards to make sure
2011 the load is preserved. */
2012 if (frame_pointer_needed)
2014 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
2018 /* Deallocate the stack frame. */
2019 if (info->total_size != 0)
2021 rtx offset = frv_frame_offset_rtx (info->total_size);
2022 emit_insn (gen_stack_adjust (sp, sp, offset));
2025 /* If this function uses eh_return, add the final stack adjustment now. */
2026 if (crtl->calls_eh_return)
2027 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2030 emit_jump_insn (gen_epilogue_return (return_addr));
2033 rtx lr = return_addr;
2035 if (REGNO (return_addr) != LR_REGNO)
2037 lr = gen_rtx_REG (Pmode, LR_REGNO);
2038 emit_move_insn (lr, return_addr);
2046 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2049 frv_asm_output_mi_thunk (FILE *file,
2050 tree thunk_fndecl ATTRIBUTE_UNUSED,
2051 HOST_WIDE_INT delta,
2052 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2055 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2056 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2057 const char *name_jmp = reg_names[JUMP_REGNO];
2058 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2060 /* Do the add using an addi if possible. */
2061 if (IN_RANGE_P (delta, -2048, 2047))
2062 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2065 const char *const name_add = reg_names[TEMP_REGNO];
2066 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2067 parallel, delta, name_add);
2068 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2070 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2075 const char *name_pic = reg_names[FDPIC_REGNO];
2076 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2080 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2081 assemble_name (file, name_func);
2082 fprintf (file, "),%s\n", name_jmp);
2084 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2085 assemble_name (file, name_func);
2086 fprintf (file, "),%s\n", name_jmp);
2088 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2092 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2093 assemble_name (file, name_func);
2094 fprintf (file, "\t)), %s\n", name_jmp);
2099 fprintf (file, "\tsethi%s #hi(", parallel);
2100 assemble_name (file, name_func);
2101 fprintf (file, "),%s\n", name_jmp);
2103 fprintf (file, "\tsetlo #lo(");
2104 assemble_name (file, name_func);
2105 fprintf (file, "),%s\n", name_jmp);
2109 /* Use JUMP_REGNO as a temporary PIC register. */
2110 const char *name_lr = reg_names[LR_REGNO];
2111 const char *name_gppic = name_jmp;
2112 const char *name_tmp = reg_names[TEMP_REGNO];
2114 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2115 fprintf (file, "\tcall 1f\n");
2116 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2117 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2118 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2119 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2120 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2122 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2123 assemble_name (file, name_func);
2124 fprintf (file, "),%s\n", name_tmp);
2126 fprintf (file, "\tsetlo #gprello(");
2127 assemble_name (file, name_func);
2128 fprintf (file, "),%s\n", name_tmp);
2130 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2133 /* Jump to the function address. */
2134 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2139 /* On frv, create a frame whenever we need to create stack. */
2142 frv_frame_pointer_required (void)
2144 /* If we forgoing the usual linkage requirements, we only need
2145 a frame pointer if the stack pointer might change. */
2146 if (!TARGET_LINKED_FP)
2147 return !current_function_sp_is_unchanging;
2149 if (! current_function_is_leaf)
2152 if (get_frame_size () != 0)
2158 if (!current_function_sp_is_unchanging)
2161 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2167 if (cfun->machine->frame_needed)
2174 /* Worker function for TARGET_CAN_ELIMINATE. */
2177 frv_can_eliminate (const int from, const int to)
2179 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2180 ? ! frame_pointer_needed
2184 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2185 initial difference between the specified pair of registers. This macro must
2186 be defined if `ELIMINABLE_REGS' is defined. */
2188 /* See frv_stack_info for more details on the frv stack frame. */
2191 frv_initial_elimination_offset (int from, int to)
2193 frv_stack_t *info = frv_stack_info ();
2196 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2197 ret = info->total_size - info->pretend_size;
2199 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2200 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2202 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2203 ret = (info->total_size
2204 - info->reg_offset[FRAME_POINTER_REGNUM]
2205 - info->pretend_size);
2210 if (TARGET_DEBUG_STACK)
2211 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2212 reg_names [from], reg_names[to], ret);
2218 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2221 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2222 enum machine_mode mode,
2223 tree type ATTRIBUTE_UNUSED,
2227 if (TARGET_DEBUG_ARG)
2229 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2230 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2234 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2237 frv_expand_builtin_saveregs (void)
2239 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2241 if (TARGET_DEBUG_ARG)
2242 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2245 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2249 /* Expand __builtin_va_start to do the va_start macro. */
2252 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2255 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2257 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2258 GEN_INT (UNITS_PER_WORD * num));
2260 if (TARGET_DEBUG_ARG)
2262 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2263 crtl->args.info, num);
2265 debug_rtx (nextarg);
2268 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2269 fold_convert (TREE_TYPE (valist),
2270 make_tree (sizetype, nextarg)));
2271 TREE_SIDE_EFFECTS (t) = 1;
2273 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2277 /* Expand a block move operation, and return 1 if successful. Return 0
2278 if we should let the compiler generate normal code.
2280 operands[0] is the destination
2281 operands[1] is the source
2282 operands[2] is the length
2283 operands[3] is the alignment */
2285 /* Maximum number of loads to do before doing the stores */
2286 #ifndef MAX_MOVE_REG
2287 #define MAX_MOVE_REG 4
2290 /* Maximum number of total loads to do. */
2291 #ifndef TOTAL_MOVE_REG
2292 #define TOTAL_MOVE_REG 8
2296 frv_expand_block_move (rtx operands[])
2298 rtx orig_dest = operands[0];
2299 rtx orig_src = operands[1];
2300 rtx bytes_rtx = operands[2];
2301 rtx align_rtx = operands[3];
2302 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2315 rtx stores[MAX_MOVE_REG];
2317 enum machine_mode mode;
2319 /* If this is not a fixed size move, just call memcpy. */
2323 /* This should be a fixed size alignment. */
2324 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2326 align = INTVAL (align_rtx);
2328 /* Anything to move? */
2329 bytes = INTVAL (bytes_rtx);
2333 /* Don't support real large moves. */
2334 if (bytes > TOTAL_MOVE_REG*align)
2337 /* Move the address into scratch registers. */
2338 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2339 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2341 num_reg = offset = 0;
2342 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2344 /* Calculate the correct offset for src/dest. */
2348 dest_addr = dest_reg;
2352 src_addr = plus_constant (src_reg, offset);
2353 dest_addr = plus_constant (dest_reg, offset);
2356 /* Generate the appropriate load and store, saving the stores
2358 if (bytes >= 4 && align >= 4)
2360 else if (bytes >= 2 && align >= 2)
2365 move_bytes = GET_MODE_SIZE (mode);
2366 tmp_reg = gen_reg_rtx (mode);
2367 src_mem = change_address (orig_src, mode, src_addr);
2368 dest_mem = change_address (orig_dest, mode, dest_addr);
2369 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2370 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2372 if (num_reg >= MAX_MOVE_REG)
2374 for (i = 0; i < num_reg; i++)
2375 emit_insn (stores[i]);
2380 for (i = 0; i < num_reg; i++)
2381 emit_insn (stores[i]);
2387 /* Expand a block clear operation, and return 1 if successful. Return 0
2388 if we should let the compiler generate normal code.
2390 operands[0] is the destination
2391 operands[1] is the length
2392 operands[3] is the alignment */
2395 frv_expand_block_clear (rtx operands[])
2397 rtx orig_dest = operands[0];
2398 rtx bytes_rtx = operands[1];
2399 rtx align_rtx = operands[3];
2400 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2408 enum machine_mode mode;
2410 /* If this is not a fixed size move, just call memcpy. */
2414 /* This should be a fixed size alignment. */
2415 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2417 align = INTVAL (align_rtx);
2419 /* Anything to move? */
2420 bytes = INTVAL (bytes_rtx);
2424 /* Don't support real large clears. */
2425 if (bytes > TOTAL_MOVE_REG*align)
2428 /* Move the address into a scratch register. */
2429 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2432 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2434 /* Calculate the correct offset for src/dest. */
2435 dest_addr = ((offset == 0)
2437 : plus_constant (dest_reg, offset));
2439 /* Generate the appropriate store of gr0. */
2440 if (bytes >= 4 && align >= 4)
2442 else if (bytes >= 2 && align >= 2)
2447 clear_bytes = GET_MODE_SIZE (mode);
2448 dest_mem = change_address (orig_dest, mode, dest_addr);
2449 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2456 /* The following variable is used to output modifiers of assembler
2457 code of the current output insn. */
2459 static rtx *frv_insn_operands;
2461 /* The following function is used to add assembler insn code suffix .p
2462 if it is necessary. */
2465 frv_asm_output_opcode (FILE *f, const char *ptr)
2469 if (frv_insn_packing_flag <= 0)
2472 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2475 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2476 || (*ptr >= 'A' && *ptr <= 'Z')))
2478 int letter = *ptr++;
2481 frv_print_operand (f, frv_insn_operands [c], letter);
2482 while ((c = *ptr) >= '0' && c <= '9')
2494 /* Set up the packing bit for the current output insn. Note that this
2495 function is not called for asm insns. */
2498 frv_final_prescan_insn (rtx insn, rtx *opvec,
2499 int noperands ATTRIBUTE_UNUSED)
2503 if (frv_insn_packing_flag >= 0)
2505 frv_insn_operands = opvec;
2506 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2508 else if (recog_memoized (insn) >= 0
2509 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2510 /* Packing optimizations have been disabled, but INSN can only
2511 be issued in M1. Insert an mnop in M0. */
2512 fprintf (asm_out_file, "\tmnop.p\n");
2518 /* A C expression whose value is RTL representing the address in a stack frame
2519 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2520 an RTL expression for the address of the stack frame itself.
2522 If you don't define this macro, the default is to return the value of
2523 FRAMEADDR--that is, the stack frame address is also the address of the stack
2524 word that points to the previous frame. */
2526 /* The default is correct, but we need to make sure the frame gets created. */
2528 frv_dynamic_chain_address (rtx frame)
2530 cfun->machine->frame_needed = 1;
2535 /* A C expression whose value is RTL representing the value of the return
2536 address for the frame COUNT steps up from the current frame, after the
2537 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2538 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2541 The value of the expression must always be the correct address when COUNT is
2542 zero, but may be `NULL_RTX' if there is not way to determine the return
2543 address of other frames. */
2546 frv_return_addr_rtx (int count, rtx frame)
2550 cfun->machine->frame_needed = 1;
2551 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2554 /* Given a memory reference MEMREF, interpret the referenced memory as
2555 an array of MODE values, and return a reference to the element
2556 specified by INDEX. Assume that any pre-modification implicit in
2557 MEMREF has already happened.
2559 MEMREF must be a legitimate operand for modes larger than SImode.
2560 frv_legitimate_address_p forbids register+register addresses, which
2561 this function cannot handle. */
2563 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2565 rtx base = XEXP (memref, 0);
2566 if (GET_CODE (base) == PRE_MODIFY)
2567 base = XEXP (base, 0);
2568 return change_address (memref, mode,
2569 plus_constant (base, index * GET_MODE_SIZE (mode)));
2573 /* Print a memory address as an operand to reference that memory location. */
2575 frv_print_operand_address (FILE * stream, rtx x)
2577 if (GET_CODE (x) == MEM)
2580 switch (GET_CODE (x))
2583 fputs (reg_names [ REGNO (x)], stream);
2587 fprintf (stream, "%ld", (long) INTVAL (x));
2591 assemble_name (stream, XSTR (x, 0));
2596 output_addr_const (stream, x);
2600 /* Poorly constructed asm statements can trigger this alternative.
2601 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2602 frv_print_operand_memory_reference (stream, x, 0);
2609 fatal_insn ("bad insn to frv_print_operand_address:", x);
2614 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2616 int regno = true_regnum (x);
2618 fputs (reg_names[regno], stream);
2620 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2623 /* Print a memory reference suitable for the ld/st instructions. */
2626 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2628 struct frv_unspec unspec;
2632 switch (GET_CODE (x))
2639 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2641 x1 = XEXP (XEXP (x, 1), 1);
2651 if (GET_CODE (x0) == CONST_INT)
2659 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2668 else if (GET_CODE (x1) != CONST_INT)
2669 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2672 fputs ("@(", stream);
2674 fputs (reg_names[GPR_R0], stream);
2675 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2676 frv_print_operand_memory_reference_reg (stream, x0);
2678 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2680 fputs (",", stream);
2682 fputs (reg_names [GPR_R0], stream);
2686 switch (GET_CODE (x1))
2690 frv_print_operand_memory_reference_reg (stream, x1);
2694 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2698 if (!frv_const_unspec_p (x1, &unspec))
2699 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2700 frv_output_const_unspec (stream, &unspec);
2704 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2708 fputs (")", stream);
2712 /* Return 2 for likely branches and 0 for non-likely branches */
2714 #define FRV_JUMP_LIKELY 2
2715 #define FRV_JUMP_NOT_LIKELY 0
2718 frv_print_operand_jump_hint (rtx insn)
2723 HOST_WIDE_INT prob = -1;
2724 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2726 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2728 /* Assume any non-conditional jump is likely. */
2729 if (! any_condjump_p (insn))
2730 ret = FRV_JUMP_LIKELY;
2734 labelref = condjump_label (insn);
2737 rtx label = XEXP (labelref, 0);
2738 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2743 note = find_reg_note (insn, REG_BR_PROB, 0);
2745 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2749 prob = INTVAL (XEXP (note, 0));
2750 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2752 : FRV_JUMP_NOT_LIKELY);
2764 case UNKNOWN: direction = "unknown jump direction"; break;
2765 case BACKWARD: direction = "jump backward"; break;
2766 case FORWARD: direction = "jump forward"; break;
2770 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2771 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2772 (long)INSN_UID (insn), direction, (long)prob,
2773 (long)REG_BR_PROB_BASE, ret);
2781 /* Return the comparison operator to use for CODE given that the ICC
2785 comparison_string (enum rtx_code code, rtx op0)
2787 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2790 default: output_operand_lossage ("bad condition code");
2791 case EQ: return "eq";
2792 case NE: return "ne";
2793 case LT: return is_nz_p ? "n" : "lt";
2794 case LE: return "le";
2795 case GT: return "gt";
2796 case GE: return is_nz_p ? "p" : "ge";
2797 case LTU: return is_nz_p ? "no" : "c";
2798 case LEU: return is_nz_p ? "eq" : "ls";
2799 case GTU: return is_nz_p ? "ne" : "hi";
2800 case GEU: return is_nz_p ? "ra" : "nc";
2804 /* Print an operand to an assembler instruction.
2806 `%' followed by a letter and a digit says to output an operand in an
2807 alternate fashion. Four letters have standard, built-in meanings
2808 described below. The hook `TARGET_PRINT_OPERAND' can define
2809 additional letters with nonstandard meanings.
2811 `%cDIGIT' can be used to substitute an operand that is a constant value
2812 without the syntax that normally indicates an immediate operand.
2814 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2817 `%aDIGIT' can be used to substitute an operand as if it were a memory
2818 reference, with the actual operand treated as the address. This may be
2819 useful when outputting a "load address" instruction, because often the
2820 assembler syntax for such an instruction requires you to write the operand
2821 as if it were a memory reference.
2823 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2825 `%=' outputs a number which is unique to each instruction in the entire
2826 compilation. This is useful for making local labels to be referred to more
2827 than once in a single template that generates multiple assembler
2830 `%' followed by a punctuation character specifies a substitution that
2831 does not use an operand. Only one case is standard: `%%' outputs a
2832 `%' into the assembler code. Other nonstandard cases can be defined
2833 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2834 punctuation characters are valid with the
2835 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2838 frv_print_operand (FILE * file, rtx x, int code)
2840 struct frv_unspec unspec;
2841 HOST_WIDE_INT value;
2844 if (code != 0 && !ISALPHA (code))
2847 else if (GET_CODE (x) == CONST_INT)
2850 else if (GET_CODE (x) == CONST_DOUBLE)
2852 if (GET_MODE (x) == SFmode)
2857 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2858 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2862 else if (GET_MODE (x) == VOIDmode)
2863 value = CONST_DOUBLE_LOW (x);
2866 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2877 fputs (reg_names[GPR_R0], file);
2881 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2885 /* Output small data area base register (gr16). */
2886 fputs (reg_names[SDA_BASE_REG], file);
2890 /* Output pic register (gr17). */
2891 fputs (reg_names[PIC_REGNO], file);
2895 /* Output the temporary integer CCR register. */
2896 fputs (reg_names[ICR_TEMP], file);
2900 /* Output the temporary integer CC register. */
2901 fputs (reg_names[ICC_TEMP], file);
2904 /* case 'a': print an address. */
2907 /* Print appropriate test for integer branch false operation. */
2908 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2909 XEXP (x, 0)), file);
2913 /* Print appropriate test for integer branch true operation. */
2914 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2918 /* Print 1 for a NE and 0 for an EQ to give the final argument
2919 for a conditional instruction. */
2920 if (GET_CODE (x) == NE)
2923 else if (GET_CODE (x) == EQ)
2927 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2931 /* Print appropriate test for floating point branch false operation. */
2932 switch (GET_CODE (x))
2935 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2937 case EQ: fputs ("ne", file); break;
2938 case NE: fputs ("eq", file); break;
2939 case LT: fputs ("uge", file); break;
2940 case LE: fputs ("ug", file); break;
2941 case GT: fputs ("ule", file); break;
2942 case GE: fputs ("ul", file); break;
2947 /* Print appropriate test for floating point branch true operation. */
2948 switch (GET_CODE (x))
2951 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2953 case EQ: fputs ("eq", file); break;
2954 case NE: fputs ("ne", file); break;
2955 case LT: fputs ("lt", file); break;
2956 case LE: fputs ("le", file); break;
2957 case GT: fputs ("gt", file); break;
2958 case GE: fputs ("ge", file); break;
2963 /* Print appropriate GOT function. */
2964 if (GET_CODE (x) != CONST_INT)
2965 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2966 fputs (unspec_got_name (INTVAL (x)), file);
2970 /* Print 'i' if the operand is a constant, or is a memory reference that
2972 if (GET_CODE (x) == MEM)
2973 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2974 ? XEXP (XEXP (x, 0), 1)
2976 else if (GET_CODE (x) == PLUS)
2979 switch (GET_CODE (x))
2993 /* For jump instructions, print 'i' if the operand is a constant or
2994 is an expression that adds a constant. */
2995 if (GET_CODE (x) == CONST_INT)
3000 if (GET_CODE (x) == CONST_INT
3001 || (GET_CODE (x) == PLUS
3002 && (GET_CODE (XEXP (x, 1)) == CONST_INT
3003 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
3009 /* Print the lower register of a double word register pair */
3010 if (GET_CODE (x) == REG)
3011 fputs (reg_names[ REGNO (x)+1 ], file);
3013 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
3016 /* case 'l': print a LABEL_REF. */
3020 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
3021 for the second word of double memory operations. */
3022 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3023 switch (GET_CODE (x))
3026 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3029 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3037 frv_print_operand_memory_reference (file, x, offset);
3043 /* Print the opcode of a command. */
3044 switch (GET_CODE (x))
3047 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3049 case PLUS: fputs ("add", file); break;
3050 case MINUS: fputs ("sub", file); break;
3051 case AND: fputs ("and", file); break;
3052 case IOR: fputs ("or", file); break;
3053 case XOR: fputs ("xor", file); break;
3054 case ASHIFT: fputs ("sll", file); break;
3055 case ASHIFTRT: fputs ("sra", file); break;
3056 case LSHIFTRT: fputs ("srl", file); break;
3060 /* case 'n': negate and print a constant int. */
3063 /* Print PIC label using operand as the number. */
3064 if (GET_CODE (x) != CONST_INT)
3065 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3067 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3071 /* Print 'u' if the operand is a update load/store. */
3072 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3077 /* If value is 0, print gr0, otherwise it must be a register. */
3078 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3079 fputs (reg_names[GPR_R0], file);
3081 else if (GET_CODE (x) == REG)
3082 fputs (reg_names [REGNO (x)], file);
3085 fatal_insn ("bad insn in frv_print_operand, z case", x);
3089 /* Print constant in hex. */
3090 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3092 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3099 if (GET_CODE (x) == REG)
3100 fputs (reg_names [REGNO (x)], file);
3102 else if (GET_CODE (x) == CONST_INT
3103 || GET_CODE (x) == CONST_DOUBLE)
3104 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3106 else if (frv_const_unspec_p (x, &unspec))
3107 frv_output_const_unspec (file, &unspec);
3109 else if (GET_CODE (x) == MEM)
3110 frv_print_operand_address (file, XEXP (x, 0));
3112 else if (CONSTANT_ADDRESS_P (x))
3113 frv_print_operand_address (file, x);
3116 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3121 fatal_insn ("frv_print_operand: unknown code", x);
3129 frv_print_operand_punct_valid_p (unsigned char code)
3131 return (code == '.' || code == '#' || code == '@' || code == '~'
3132 || code == '*' || code == '&');
3136 /* A C statement (sans semicolon) for initializing the variable CUM for the
3137 state at the beginning of the argument list. The variable has type
3138 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3139 of the function which will receive the args, or 0 if the args are to a
3140 compiler support library function. The value of INDIRECT is nonzero when
3141 processing an indirect call, for example a call through a function pointer.
3142 The value of INDIRECT is zero for a call to an explicitly named function, a
3143 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3144 arguments for the function being compiled.
3146 When processing a call to a compiler support library function, LIBNAME
3147 identifies which one. It is a `symbol_ref' rtx which contains the name of
3148 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3149 being processed. Thus, each time this macro is called, either LIBNAME or
3150 FNTYPE is nonzero, but never both of them at once. */
3153 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3159 *cum = FIRST_ARG_REGNUM;
3161 if (TARGET_DEBUG_ARG)
3163 fprintf (stderr, "\ninit_cumulative_args:");
3164 if (!fndecl && fntype)
3165 fputs (" indirect", stderr);
3168 fputs (" incoming", stderr);
3172 tree ret_type = TREE_TYPE (fntype);
3173 fprintf (stderr, " return=%s,",
3174 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3177 if (libname && GET_CODE (libname) == SYMBOL_REF)
3178 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3180 if (cfun->returns_struct)
3181 fprintf (stderr, " return-struct");
3183 putc ('\n', stderr);
3188 /* Return true if we should pass an argument on the stack rather than
3192 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3194 if (mode == BLKmode)
3198 return AGGREGATE_TYPE_P (type);
3201 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3202 argument with the specified mode and type. If it is not defined,
3203 `PARM_BOUNDARY' is used for all arguments. */
3206 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3207 const_tree type ATTRIBUTE_UNUSED)
3209 return BITS_PER_WORD;
3213 frv_function_arg_1 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3214 const_tree type ATTRIBUTE_UNUSED, bool named,
3215 bool incoming ATTRIBUTE_UNUSED)
3217 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3222 /* Return a marker for use in the call instruction. */
3223 if (xmode == VOIDmode)
3229 else if (arg_num <= LAST_ARG_REGNUM)
3231 ret = gen_rtx_REG (xmode, arg_num);
3232 debstr = reg_names[arg_num];
3241 if (TARGET_DEBUG_ARG)
3243 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3244 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3250 frv_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3251 const_tree type, bool named)
3253 return frv_function_arg_1 (cum, mode, type, named, false);
3257 frv_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3258 const_tree type, bool named)
3260 return frv_function_arg_1 (cum, mode, type, named, true);
3264 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3265 advance past an argument in the argument list. The values MODE, TYPE and
3266 NAMED describe that argument. Once this is done, the variable CUM is
3267 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3269 This macro need not do anything if the argument in question was passed on
3270 the stack. The compiler knows how to track the amount of stack space used
3271 for arguments without any special help. */
3274 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3275 enum machine_mode mode,
3276 const_tree type ATTRIBUTE_UNUSED,
3279 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3280 int bytes = GET_MODE_SIZE (xmode);
3281 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3284 *cum = arg_num + words;
3286 if (TARGET_DEBUG_ARG)
3288 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3289 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3293 /* A C expression for the number of words, at the beginning of an argument,
3294 must be put in registers. The value must be zero for arguments that are
3295 passed entirely in registers or that are entirely pushed on the stack.
3297 On some machines, certain arguments must be passed partially in registers
3298 and partially in memory. On these machines, typically the first N words of
3299 arguments are passed in registers, and the rest on the stack. If a
3300 multi-word argument (a `double' or a structure) crosses that boundary, its
3301 first few words must be passed in registers and the rest must be pushed.
3302 This macro tells the compiler when this occurs, and how many of the words
3303 should go in registers.
3305 `FUNCTION_ARG' for these arguments should return the first register to be
3306 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3307 the called function. */
3310 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3311 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3313 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3314 int bytes = GET_MODE_SIZE (xmode);
3315 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3319 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3320 ? LAST_ARG_REGNUM - arg_num + 1
3322 ret *= UNITS_PER_WORD;
3324 if (TARGET_DEBUG_ARG && ret)
3325 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3331 /* Implements TARGET_FUNCTION_VALUE. */
3334 frv_function_value (const_tree valtype,
3335 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3336 bool outgoing ATTRIBUTE_UNUSED)
3338 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3342 /* Implements TARGET_LIBCALL_VALUE. */
3345 frv_libcall_value (enum machine_mode mode,
3346 const_rtx fun ATTRIBUTE_UNUSED)
3348 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3352 /* Implements FUNCTION_VALUE_REGNO_P. */
3355 frv_function_value_regno_p (const unsigned int regno)
3357 return (regno == RETURN_VALUE_REGNUM);
3360 /* Return true if a register is ok to use as a base or index register. */
3362 static FRV_INLINE int
3363 frv_regno_ok_for_base_p (int regno, int strict_p)
3369 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3371 if (regno == ARG_POINTER_REGNUM)
3374 return (regno >= FIRST_PSEUDO_REGISTER);
3378 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3379 RTX) is a legitimate memory address on the target machine for a memory
3380 operand of mode MODE.
3382 It usually pays to define several simpler macros to serve as subroutines for
3383 this one. Otherwise it may be too complicated to understand.
3385 This macro must exist in two variants: a strict variant and a non-strict
3386 one. The strict variant is used in the reload pass. It must be defined so
3387 that any pseudo-register that has not been allocated a hard register is
3388 considered a memory reference. In contexts where some kind of register is
3389 required, a pseudo-register with no hard register must be rejected.
3391 The non-strict variant is used in other passes. It must be defined to
3392 accept all pseudo-registers in every context where some kind of register is
3395 Compiler source files that want to use the strict variant of this macro
3396 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3397 conditional to define the strict variant in that case and the non-strict
3400 Normally, constant addresses which are the sum of a `symbol_ref' and an
3401 integer are stored inside a `const' RTX to mark them as constant.
3402 Therefore, there is no need to recognize such sums specifically as
3403 legitimate addresses. Normally you would simply recognize any `const' as
3406 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3407 constant sums that are not marked with `const'. It assumes that a
3408 naked `plus' indicates indexing. If so, then you *must* reject such
3409 naked constant sums as illegitimate addresses, so that none of them
3410 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3413 frv_legitimate_address_p_1 (enum machine_mode mode,
3417 int allow_double_reg_p)
3421 HOST_WIDE_INT value;
3424 if (FRV_SYMBOL_REF_TLS_P (x))
3427 switch (GET_CODE (x))
3434 if (GET_CODE (x) != REG)
3440 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3446 if (GET_CODE (x0) != REG
3447 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3448 || GET_CODE (x1) != PLUS
3449 || ! rtx_equal_p (x0, XEXP (x1, 0))
3450 || GET_CODE (XEXP (x1, 1)) != REG
3451 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3458 /* 12-bit immediate */
3463 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3465 /* If we can't use load/store double operations, make sure we can
3466 address the second word. */
3467 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3468 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3477 if (GET_CODE (x0) == SUBREG)
3478 x0 = SUBREG_REG (x0);
3480 if (GET_CODE (x0) != REG)
3483 regno0 = REGNO (x0);
3484 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3487 switch (GET_CODE (x1))
3493 x1 = SUBREG_REG (x1);
3494 if (GET_CODE (x1) != REG)
3500 /* Do not allow reg+reg addressing for modes > 1 word if we
3501 can't depend on having move double instructions. */
3502 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3505 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3509 /* 12-bit immediate */
3514 value = INTVAL (x1);
3515 ret = IN_RANGE_P (value, -2048, 2047);
3517 /* If we can't use load/store double operations, make sure we can
3518 address the second word. */
3519 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3520 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3525 if (!condexec_p && got12_operand (x1, VOIDmode))
3533 if (TARGET_DEBUG_ADDR)
3535 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3536 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3537 (condexec_p) ? ", inside conditional code" : "");
3545 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3547 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3550 /* Given an ADDR, generate code to inline the PLT. */
3552 gen_inlined_tls_plt (rtx addr)
3555 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3558 dest = gen_reg_rtx (DImode);
3565 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3566 calll #gettlsoff(ADDR)@(gr8, gr0)
3568 emit_insn (gen_tls_lddi (dest, addr, picreg));
3575 sethi.p #gottlsdeschi(ADDR), gr8
3576 setlo #gottlsdesclo(ADDR), gr8
3577 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3578 calll #gettlsoff(ADDR)@(gr8, gr0)
3580 rtx reguse = gen_reg_rtx (Pmode);
3581 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3582 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3585 retval = gen_reg_rtx (Pmode);
3586 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3590 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3591 the destination address. */
3593 gen_tlsmoff (rtx addr, rtx reg)
3595 rtx dest = gen_reg_rtx (Pmode);
3599 /* sethi.p #tlsmoffhi(x), grA
3600 setlo #tlsmofflo(x), grA
3602 dest = gen_reg_rtx (Pmode);
3603 emit_insn (gen_tlsoff_hilo (dest, addr,
3604 GEN_INT (R_FRV_TLSMOFFHI)));
3605 dest = gen_rtx_PLUS (Pmode, dest, reg);
3609 /* addi grB, #tlsmoff12(x), grC
3611 ld/st @(grB, #tlsmoff12(x)), grC
3613 dest = gen_reg_rtx (Pmode);
3614 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3615 GEN_INT (R_FRV_TLSMOFF12)));
3620 /* Generate code for a TLS address. */
3622 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3624 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3625 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3629 case TLS_MODEL_INITIAL_EXEC:
3633 ldi @(gr15, #gottlsoff12(x)), gr5
3635 dest = gen_reg_rtx (Pmode);
3636 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3637 dest = gen_rtx_PLUS (Pmode, tp, dest);
3641 /* -fPIC or anything else.
3643 sethi.p #gottlsoffhi(x), gr14
3644 setlo #gottlsofflo(x), gr14
3645 ld #tlsoff(x)@(gr15, gr14), gr9
3647 rtx tmp = gen_reg_rtx (Pmode);
3648 dest = gen_reg_rtx (Pmode);
3649 emit_insn (gen_tlsoff_hilo (tmp, addr,
3650 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3652 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3653 dest = gen_rtx_PLUS (Pmode, tp, dest);
3656 case TLS_MODEL_LOCAL_DYNAMIC:
3660 if (TARGET_INLINE_PLT)
3661 retval = gen_inlined_tls_plt (GEN_INT (0));
3664 /* call #gettlsoff(0) */
3665 retval = gen_reg_rtx (Pmode);
3666 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3669 reg = gen_reg_rtx (Pmode);
3670 emit_insn (gen_rtx_SET (VOIDmode, reg,
3671 gen_rtx_PLUS (Pmode,
3674 dest = gen_tlsmoff (addr, reg);
3677 dest = gen_reg_rtx (Pmode);
3678 emit_insn (gen_tlsoff_hilo (dest, addr,
3679 GEN_INT (R_FRV_TLSMOFFHI)));
3680 dest = gen_rtx_PLUS (Pmode, dest, reg);
3684 case TLS_MODEL_LOCAL_EXEC:
3685 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3687 case TLS_MODEL_GLOBAL_DYNAMIC:
3691 if (TARGET_INLINE_PLT)
3692 retval = gen_inlined_tls_plt (addr);
3695 /* call #gettlsoff(x) */
3696 retval = gen_reg_rtx (Pmode);
3697 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3699 dest = gen_rtx_PLUS (Pmode, retval, tp);
3710 frv_legitimize_address (rtx x,
3711 rtx oldx ATTRIBUTE_UNUSED,
3712 enum machine_mode mode ATTRIBUTE_UNUSED)
3714 if (GET_CODE (x) == SYMBOL_REF)
3716 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3718 return frv_legitimize_tls_address (x, model);
3724 /* Test whether a local function descriptor is canonical, i.e.,
3725 whether we can use FUNCDESC_GOTOFF to compute the address of the
3729 frv_local_funcdesc_p (rtx fnx)
3732 enum symbol_visibility vis;
3735 if (! SYMBOL_REF_LOCAL_P (fnx))
3738 fn = SYMBOL_REF_DECL (fnx);
3743 vis = DECL_VISIBILITY (fn);
3745 if (vis == VISIBILITY_PROTECTED)
3746 /* Private function descriptors for protected functions are not
3747 canonical. Temporarily change the visibility to global. */
3748 vis = VISIBILITY_DEFAULT;
3749 else if (flag_shlib)
3750 /* If we're already compiling for a shared library (that, unlike
3751 executables, can't assume that the existence of a definition
3752 implies local binding), we can skip the re-testing. */
3755 ret = default_binds_local_p_1 (fn, flag_pic);
3757 DECL_VISIBILITY (fn) = vis;
3762 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3766 frv_gen_GPsym2reg (rtx dest, rtx src)
3768 tree gp = get_identifier ("_gp");
3769 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3771 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3775 unspec_got_name (int i)
3779 case R_FRV_GOT12: return "got12";
3780 case R_FRV_GOTHI: return "gothi";
3781 case R_FRV_GOTLO: return "gotlo";
3782 case R_FRV_FUNCDESC: return "funcdesc";
3783 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3784 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3785 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3786 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3787 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3788 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3789 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3790 case R_FRV_GOTOFF12: return "gotoff12";
3791 case R_FRV_GOTOFFHI: return "gotoffhi";
3792 case R_FRV_GOTOFFLO: return "gotofflo";
3793 case R_FRV_GPREL12: return "gprel12";
3794 case R_FRV_GPRELHI: return "gprelhi";
3795 case R_FRV_GPRELLO: return "gprello";
3796 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3797 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3798 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3799 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3800 case R_FRV_TLSMOFF12: return "tlsmoff12";
3801 case R_FRV_TLSDESCHI: return "tlsdeschi";
3802 case R_FRV_TLSDESCLO: return "tlsdesclo";
3803 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3804 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3805 default: gcc_unreachable ();
3809 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3810 is added inside the relocation operator. */
3813 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3815 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3816 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3817 fputs (")", stream);
3820 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3821 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3822 otherwise return ORIG_X. */
3825 frv_find_base_term (rtx x)
3827 struct frv_unspec unspec;
3829 if (frv_const_unspec_p (x, &unspec)
3830 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3831 return plus_constant (unspec.symbol, unspec.offset);
3836 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3837 the operand is used by a predicated instruction. */
3840 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3842 return ((GET_MODE (op) == mode || mode == VOIDmode)
3843 && GET_CODE (op) == MEM
3844 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3845 reload_completed, condexec_p, FALSE));
3849 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3851 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3852 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3858 rvrtx = operands[0];
3862 addr = XEXP (operands[0], 0);
3864 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3865 any calls that would involve a PLT, but can't tell, since we
3866 don't know whether an extern function is going to be provided by
3867 a separate translation unit or imported from a separate module.
3868 When compiling for shared libraries, if the function has default
3869 visibility, we assume it's overridable, so we inline the PLT, but
3870 for executables, we don't really have a way to make a good
3871 decision: a function is as likely to be imported from a shared
3872 library as it is to be defined in the executable itself. We
3873 assume executables will get global functions defined locally,
3874 whereas shared libraries will have them potentially overridden,
3875 so we only inline PLTs when compiling for shared libraries.
3877 In order to mark a function as local to a shared library, any
3878 non-default visibility attribute suffices. Unfortunately,
3879 there's no simple way to tag a function declaration as ``in a
3880 different module'', which we could then use to trigger PLT
3881 inlining on executables. There's -minline-plt, but it affects
3882 all external functions, so one would have to also mark function
3883 declarations available in the same module with non-default
3884 visibility, which is advantageous in itself. */
3885 if (GET_CODE (addr) == SYMBOL_REF
3886 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3890 dest = gen_reg_rtx (SImode);
3892 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3893 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3895 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3896 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3898 crtl->uses_pic_offset_table = TRUE;
3901 else if (GET_CODE (addr) == SYMBOL_REF)
3903 /* These are always either local, or handled through a local
3906 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3907 operands[2], picreg, lr);
3909 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3913 else if (! ldd_address_operand (addr, Pmode))
3914 addr = force_reg (Pmode, addr);
3916 picreg = gen_reg_rtx (DImode);
3917 emit_insn (gen_movdi_ldd (picreg, addr));
3919 if (sibcall && ret_value)
3920 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3922 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3924 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3926 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3930 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3931 process these separately from any offsets, such that we add any
3932 offsets to the function descriptor (the actual pointer), not to the
3933 function address. */
3936 frv_function_symbol_referenced_p (rtx x)
3942 if (GET_CODE (x) == SYMBOL_REF)
3943 return SYMBOL_REF_FUNCTION_P (x);
3945 length = GET_RTX_LENGTH (GET_CODE (x));
3946 format = GET_RTX_FORMAT (GET_CODE (x));
3948 for (j = 0; j < length; ++j)
3953 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3959 if (XVEC (x, j) != 0)
3962 for (k = 0; k < XVECLEN (x, j); ++k)
3963 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3969 /* Nothing to do. */
3977 /* Return true if the memory operand is one that can be conditionally
3981 condexec_memory_operand (rtx op, enum machine_mode mode)
3983 enum machine_mode op_mode = GET_MODE (op);
3986 if (mode != VOIDmode && op_mode != mode)
4001 if (GET_CODE (op) != MEM)
4004 addr = XEXP (op, 0);
4005 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
4008 /* Return true if the bare return instruction can be used outside of the
4009 epilog code. For frv, we only do it if there was no stack allocation. */
4012 direct_return_p (void)
4016 if (!reload_completed)
4019 info = frv_stack_info ();
4020 return (info->total_size == 0);
4025 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
4027 if (GET_CODE (src) == SYMBOL_REF)
4029 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
4031 src = frv_legitimize_tls_address (src, model);
4037 if (frv_emit_movsi (dest, src))
4046 if (!reload_in_progress
4047 && !reload_completed
4048 && !register_operand (dest, mode)
4049 && !reg_or_0_operand (src, mode))
4050 src = copy_to_mode_reg (mode, src);
4057 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4060 /* Emit code to handle a MOVSI, adding in the small data register or pic
4061 register if needed to load up addresses. Return TRUE if the appropriate
4062 instructions are emitted. */
4065 frv_emit_movsi (rtx dest, rtx src)
4067 int base_regno = -1;
4070 struct frv_unspec old_unspec;
4072 if (!reload_in_progress
4073 && !reload_completed
4074 && !register_operand (dest, SImode)
4075 && (!reg_or_0_operand (src, SImode)
4076 /* Virtual registers will almost always be replaced by an
4077 add instruction, so expose this to CSE by copying to
4078 an intermediate register. */
4079 || (GET_CODE (src) == REG
4080 && IN_RANGE_P (REGNO (src),
4081 FIRST_VIRTUAL_REGISTER,
4082 LAST_VIRTUAL_POINTER_REGISTER))))
4084 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4088 /* Explicitly add in the PIC or small data register if needed. */
4089 switch (GET_CODE (src))
4098 /* Using GPREL12, we use a single GOT entry for all symbols
4099 in read-only sections, but trade sequences such as:
4101 sethi #gothi(label), gr#
4102 setlo #gotlo(label), gr#
4107 ld @(gr15,#got12(_gp)), gr#
4108 sethi #gprelhi(label), gr##
4109 setlo #gprello(label), gr##
4112 We may often be able to share gr# for multiple
4113 computations of GPREL addresses, and we may often fold
4114 the final add into the pair of registers of a load or
4115 store instruction, so it's often profitable. Even when
4116 optimizing for size, we're trading a GOT entry for an
4117 additional instruction, which trades GOT space
4118 (read-write) for code size (read-only, shareable), as
4119 long as the symbol is not used in more than two different
4122 With -fpie/-fpic, we'd be trading a single load for a
4123 sequence of 4 instructions, because the offset of the
4124 label can't be assumed to be addressable with 12 bits, so
4125 we don't do this. */
4126 if (TARGET_GPREL_RO)
4127 unspec = R_FRV_GPREL12;
4129 unspec = R_FRV_GOT12;
4132 base_regno = PIC_REGNO;
4137 if (frv_const_unspec_p (src, &old_unspec))
4140 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4143 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4144 emit_move_insn (dest, src);
4149 sym = XEXP (sym, 0);
4150 if (GET_CODE (sym) == PLUS
4151 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4152 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4153 sym = XEXP (sym, 0);
4154 if (GET_CODE (sym) == SYMBOL_REF)
4156 else if (GET_CODE (sym) == LABEL_REF)
4159 goto handle_whatever;
4167 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4171 src = frv_legitimize_tls_address (src, model);
4172 emit_move_insn (dest, src);
4176 if (SYMBOL_REF_FUNCTION_P (sym))
4178 if (frv_local_funcdesc_p (sym))
4179 unspec = R_FRV_FUNCDESC_GOTOFF12;
4181 unspec = R_FRV_FUNCDESC_GOT12;
4185 if (CONSTANT_POOL_ADDRESS_P (sym))
4186 switch (GET_CODE (get_pool_constant (sym)))
4193 unspec = R_FRV_GOTOFF12;
4198 if (TARGET_GPREL_RO)
4199 unspec = R_FRV_GPREL12;
4201 unspec = R_FRV_GOT12;
4204 else if (SYMBOL_REF_LOCAL_P (sym)
4205 && !SYMBOL_REF_EXTERNAL_P (sym)
4206 && SYMBOL_REF_DECL (sym)
4207 && (!DECL_P (SYMBOL_REF_DECL (sym))
4208 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4210 tree decl = SYMBOL_REF_DECL (sym);
4211 tree init = TREE_CODE (decl) == VAR_DECL
4212 ? DECL_INITIAL (decl)
4213 : TREE_CODE (decl) == CONSTRUCTOR
4216 bool named_section, readonly;
4218 if (init && init != error_mark_node)
4219 reloc = compute_reloc_for_constant (init);
4221 named_section = TREE_CODE (decl) == VAR_DECL
4222 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4223 readonly = decl_readonly_section (decl, reloc);
4226 unspec = R_FRV_GOT12;
4228 unspec = R_FRV_GOTOFF12;
4229 else if (readonly && TARGET_GPREL_RO)
4230 unspec = R_FRV_GPREL12;
4232 unspec = R_FRV_GOT12;
4235 unspec = R_FRV_GOT12;
4239 else if (SYMBOL_REF_SMALL_P (sym))
4240 base_regno = SDA_BASE_REG;
4243 base_regno = PIC_REGNO;
4248 if (base_regno >= 0)
4250 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4251 emit_insn (gen_symGOTOFF2reg (dest, src,
4252 gen_rtx_REG (Pmode, base_regno),
4253 GEN_INT (R_FRV_GPREL12)));
4255 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4256 gen_rtx_REG (Pmode, base_regno),
4257 GEN_INT (R_FRV_GPREL12)));
4258 if (base_regno == PIC_REGNO)
4259 crtl->uses_pic_offset_table = TRUE;
4267 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4268 new uses of it once reload has begun. */
4269 gcc_assert (!reload_in_progress && !reload_completed);
4273 case R_FRV_GOTOFF12:
4274 if (!frv_small_data_reloc_p (sym, unspec))
4275 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4278 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4281 if (!frv_small_data_reloc_p (sym, unspec))
4282 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4285 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4287 case R_FRV_FUNCDESC_GOTOFF12:
4289 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4292 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4296 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4299 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4303 crtl->uses_pic_offset_table = TRUE;
4312 /* Return a string to output a single word move. */
4315 output_move_single (rtx operands[], rtx insn)
4317 rtx dest = operands[0];
4318 rtx src = operands[1];
4320 if (GET_CODE (dest) == REG)
4322 int dest_regno = REGNO (dest);
4323 enum machine_mode mode = GET_MODE (dest);
4325 if (GPR_P (dest_regno))
4327 if (GET_CODE (src) == REG)
4329 /* gpr <- some sort of register */
4330 int src_regno = REGNO (src);
4332 if (GPR_P (src_regno))
4333 return "mov %1, %0";
4335 else if (FPR_P (src_regno))
4336 return "movfg %1, %0";
4338 else if (SPR_P (src_regno))
4339 return "movsg %1, %0";
4342 else if (GET_CODE (src) == MEM)
4351 return "ldsb%I1%U1 %M1,%0";
4354 return "ldsh%I1%U1 %M1,%0";
4358 return "ld%I1%U1 %M1, %0";
4362 else if (GET_CODE (src) == CONST_INT
4363 || GET_CODE (src) == CONST_DOUBLE)
4365 /* gpr <- integer/floating constant */
4366 HOST_WIDE_INT value;
4368 if (GET_CODE (src) == CONST_INT)
4369 value = INTVAL (src);
4371 else if (mode == SFmode)
4376 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4377 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4382 value = CONST_DOUBLE_LOW (src);
4384 if (IN_RANGE_P (value, -32768, 32767))
4385 return "setlos %1, %0";
4390 else if (GET_CODE (src) == SYMBOL_REF
4391 || GET_CODE (src) == LABEL_REF
4392 || GET_CODE (src) == CONST)
4398 else if (FPR_P (dest_regno))
4400 if (GET_CODE (src) == REG)
4402 /* fpr <- some sort of register */
4403 int src_regno = REGNO (src);
4405 if (GPR_P (src_regno))
4406 return "movgf %1, %0";
4408 else if (FPR_P (src_regno))
4410 if (TARGET_HARD_FLOAT)
4411 return "fmovs %1, %0";
4413 return "mor %1, %1, %0";
4417 else if (GET_CODE (src) == MEM)
4426 return "ldbf%I1%U1 %M1,%0";
4429 return "ldhf%I1%U1 %M1,%0";
4433 return "ldf%I1%U1 %M1, %0";
4437 else if (ZERO_P (src))
4438 return "movgf %., %0";
4441 else if (SPR_P (dest_regno))
4443 if (GET_CODE (src) == REG)
4445 /* spr <- some sort of register */
4446 int src_regno = REGNO (src);
4448 if (GPR_P (src_regno))
4449 return "movgs %1, %0";
4451 else if (ZERO_P (src))
4452 return "movgs %., %0";
4456 else if (GET_CODE (dest) == MEM)
4458 if (GET_CODE (src) == REG)
4460 int src_regno = REGNO (src);
4461 enum machine_mode mode = GET_MODE (dest);
4463 if (GPR_P (src_regno))
4471 return "stb%I0%U0 %1, %M0";
4474 return "sth%I0%U0 %1, %M0";
4478 return "st%I0%U0 %1, %M0";
4482 else if (FPR_P (src_regno))
4490 return "stbf%I0%U0 %1, %M0";
4493 return "sthf%I0%U0 %1, %M0";
4497 return "stf%I0%U0 %1, %M0";
4502 else if (ZERO_P (src))
4504 switch (GET_MODE (dest))
4510 return "stb%I0%U0 %., %M0";
4513 return "sth%I0%U0 %., %M0";
4517 return "st%I0%U0 %., %M0";
4522 fatal_insn ("bad output_move_single operand", insn);
4527 /* Return a string to output a double word move. */
4530 output_move_double (rtx operands[], rtx insn)
4532 rtx dest = operands[0];
4533 rtx src = operands[1];
4534 enum machine_mode mode = GET_MODE (dest);
4536 if (GET_CODE (dest) == REG)
4538 int dest_regno = REGNO (dest);
4540 if (GPR_P (dest_regno))
4542 if (GET_CODE (src) == REG)
4544 /* gpr <- some sort of register */
4545 int src_regno = REGNO (src);
4547 if (GPR_P (src_regno))
4550 else if (FPR_P (src_regno))
4552 if (((dest_regno - GPR_FIRST) & 1) == 0
4553 && ((src_regno - FPR_FIRST) & 1) == 0)
4554 return "movfgd %1, %0";
4560 else if (GET_CODE (src) == MEM)
4563 if (dbl_memory_one_insn_operand (src, mode))
4564 return "ldd%I1%U1 %M1, %0";
4569 else if (GET_CODE (src) == CONST_INT
4570 || GET_CODE (src) == CONST_DOUBLE)
4574 else if (FPR_P (dest_regno))
4576 if (GET_CODE (src) == REG)
4578 /* fpr <- some sort of register */
4579 int src_regno = REGNO (src);
4581 if (GPR_P (src_regno))
4583 if (((dest_regno - FPR_FIRST) & 1) == 0
4584 && ((src_regno - GPR_FIRST) & 1) == 0)
4585 return "movgfd %1, %0";
4590 else if (FPR_P (src_regno))
4593 && ((dest_regno - FPR_FIRST) & 1) == 0
4594 && ((src_regno - FPR_FIRST) & 1) == 0)
4595 return "fmovd %1, %0";
4601 else if (GET_CODE (src) == MEM)
4604 if (dbl_memory_one_insn_operand (src, mode))
4605 return "lddf%I1%U1 %M1, %0";
4610 else if (ZERO_P (src))
4615 else if (GET_CODE (dest) == MEM)
4617 if (GET_CODE (src) == REG)
4619 int src_regno = REGNO (src);
4621 if (GPR_P (src_regno))
4623 if (((src_regno - GPR_FIRST) & 1) == 0
4624 && dbl_memory_one_insn_operand (dest, mode))
4625 return "std%I0%U0 %1, %M0";
4630 if (FPR_P (src_regno))
4632 if (((src_regno - FPR_FIRST) & 1) == 0
4633 && dbl_memory_one_insn_operand (dest, mode))
4634 return "stdf%I0%U0 %1, %M0";
4640 else if (ZERO_P (src))
4642 if (dbl_memory_one_insn_operand (dest, mode))
4643 return "std%I0%U0 %., %M0";
4649 fatal_insn ("bad output_move_double operand", insn);
4654 /* Return a string to output a single word conditional move.
4655 Operand0 -- EQ/NE of ccr register and 0
4656 Operand1 -- CCR register
4657 Operand2 -- destination
4658 Operand3 -- source */
4661 output_condmove_single (rtx operands[], rtx insn)
4663 rtx dest = operands[2];
4664 rtx src = operands[3];
4666 if (GET_CODE (dest) == REG)
4668 int dest_regno = REGNO (dest);
4669 enum machine_mode mode = GET_MODE (dest);
4671 if (GPR_P (dest_regno))
4673 if (GET_CODE (src) == REG)
4675 /* gpr <- some sort of register */
4676 int src_regno = REGNO (src);
4678 if (GPR_P (src_regno))
4679 return "cmov %z3, %2, %1, %e0";
4681 else if (FPR_P (src_regno))
4682 return "cmovfg %3, %2, %1, %e0";
4685 else if (GET_CODE (src) == MEM)
4694 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4697 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4701 return "cld%I3%U3 %M3, %2, %1, %e0";
4705 else if (ZERO_P (src))
4706 return "cmov %., %2, %1, %e0";
4709 else if (FPR_P (dest_regno))
4711 if (GET_CODE (src) == REG)
4713 /* fpr <- some sort of register */
4714 int src_regno = REGNO (src);
4716 if (GPR_P (src_regno))
4717 return "cmovgf %3, %2, %1, %e0";
4719 else if (FPR_P (src_regno))
4721 if (TARGET_HARD_FLOAT)
4722 return "cfmovs %3,%2,%1,%e0";
4724 return "cmor %3, %3, %2, %1, %e0";
4728 else if (GET_CODE (src) == MEM)
4731 if (mode == SImode || mode == SFmode)
4732 return "cldf%I3%U3 %M3, %2, %1, %e0";
4735 else if (ZERO_P (src))
4736 return "cmovgf %., %2, %1, %e0";
4740 else if (GET_CODE (dest) == MEM)
4742 if (GET_CODE (src) == REG)
4744 int src_regno = REGNO (src);
4745 enum machine_mode mode = GET_MODE (dest);
4747 if (GPR_P (src_regno))
4755 return "cstb%I2%U2 %3, %M2, %1, %e0";
4758 return "csth%I2%U2 %3, %M2, %1, %e0";
4762 return "cst%I2%U2 %3, %M2, %1, %e0";
4766 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4767 return "cstf%I2%U2 %3, %M2, %1, %e0";
4770 else if (ZERO_P (src))
4772 enum machine_mode mode = GET_MODE (dest);
4779 return "cstb%I2%U2 %., %M2, %1, %e0";
4782 return "csth%I2%U2 %., %M2, %1, %e0";
4786 return "cst%I2%U2 %., %M2, %1, %e0";
4791 fatal_insn ("bad output_condmove_single operand", insn);
4796 /* Emit the appropriate code to do a comparison, returning the register the
4797 comparison was done it. */
4800 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4802 enum machine_mode cc_mode;
4805 /* Floating point doesn't have comparison against a constant. */
4806 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4807 op1 = force_reg (GET_MODE (op0), op1);
4809 /* Possibly disable using anything but a fixed register in order to work
4810 around cse moving comparisons past function calls. */
4811 cc_mode = SELECT_CC_MODE (test, op0, op1);
4812 cc_reg = ((TARGET_ALLOC_CC)
4813 ? gen_reg_rtx (cc_mode)
4814 : gen_rtx_REG (cc_mode,
4815 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4817 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4818 gen_rtx_COMPARE (cc_mode, op0, op1)));
4824 /* Emit code for a conditional branch.
4825 XXX: I originally wanted to add a clobber of a CCR register to use in
4826 conditional execution, but that confuses the rest of the compiler. */
4829 frv_emit_cond_branch (rtx operands[])
4834 enum rtx_code test = GET_CODE (operands[0]);
4835 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4836 enum machine_mode cc_mode = GET_MODE (cc_reg);
4838 /* Branches generate:
4840 (if_then_else (<test>, <cc_reg>, (const_int 0))
4841 (label_ref <branch_label>)
4843 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4844 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4845 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4846 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4851 /* Emit code to set a gpr to 1/0 based on a comparison. */
4854 frv_emit_scc (rtx operands[])
4860 enum rtx_code test = GET_CODE (operands[1]);
4861 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4863 /* SCC instructions generate:
4864 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4865 (clobber (<ccr_reg>))]) */
4866 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4867 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4869 cr_reg = ((TARGET_ALLOC_CC)
4870 ? gen_reg_rtx (CC_CCRmode)
4871 : gen_rtx_REG (CC_CCRmode,
4872 ((GET_MODE (cc_reg) == CC_FPmode)
4876 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4877 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4882 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4883 the separate insns. */
4886 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4892 /* Set the appropriate CCR bit. */
4893 emit_insn (gen_rtx_SET (VOIDmode,
4895 gen_rtx_fmt_ee (GET_CODE (test),
4900 /* Move the value into the destination. */
4901 emit_move_insn (dest, GEN_INT (value));
4903 /* Move 0 into the destination if the test failed */
4904 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4905 gen_rtx_EQ (GET_MODE (cr_reg),
4908 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4910 /* Finish up, return sequence. */
4917 /* Emit the code for a conditional move, return TRUE if we could do the
4921 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4928 enum rtx_code test = GET_CODE (test_rtx);
4929 rtx cc_reg = frv_emit_comparison (test,
4930 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4931 enum machine_mode cc_mode = GET_MODE (cc_reg);
4933 /* Conditional move instructions generate:
4934 (parallel [(set <target>
4935 (if_then_else (<test> <cc_reg> (const_int 0))
4938 (clobber (<ccr_reg>))]) */
4940 /* Handle various cases of conditional move involving two constants. */
4941 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4943 HOST_WIDE_INT value1 = INTVAL (src1);
4944 HOST_WIDE_INT value2 = INTVAL (src2);
4946 /* Having 0 as one of the constants can be done by loading the other
4947 constant, and optionally moving in gr0. */
4948 if (value1 == 0 || value2 == 0)
4951 /* If the first value is within an addi range and also the difference
4952 between the two fits in an addi's range, load up the difference, then
4953 conditionally move in 0, and then unconditionally add the first
4955 else if (IN_RANGE_P (value1, -2048, 2047)
4956 && IN_RANGE_P (value2 - value1, -2048, 2047))
4959 /* If neither condition holds, just force the constant into a
4963 src1 = force_reg (GET_MODE (dest), src1);
4964 src2 = force_reg (GET_MODE (dest), src2);
4968 /* If one value is a register, insure the other value is either 0 or a
4972 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4973 src1 = force_reg (GET_MODE (dest), src1);
4975 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4976 src2 = force_reg (GET_MODE (dest), src2);
4979 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4980 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4982 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4984 cr_reg = ((TARGET_ALLOC_CC)
4985 ? gen_reg_rtx (CC_CCRmode)
4986 : gen_rtx_REG (CC_CCRmode,
4987 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4989 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4990 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4995 /* Split a conditional move into constituent parts, returning a SEQUENCE
4996 containing all of the insns. */
4999 frv_split_cond_move (rtx operands[])
5001 rtx dest = operands[0];
5002 rtx test = operands[1];
5003 rtx cc_reg = operands[2];
5004 rtx src1 = operands[3];
5005 rtx src2 = operands[4];
5006 rtx cr_reg = operands[5];
5008 enum machine_mode cr_mode = GET_MODE (cr_reg);
5012 /* Set the appropriate CCR bit. */
5013 emit_insn (gen_rtx_SET (VOIDmode,
5015 gen_rtx_fmt_ee (GET_CODE (test),
5020 /* Handle various cases of conditional move involving two constants. */
5021 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
5023 HOST_WIDE_INT value1 = INTVAL (src1);
5024 HOST_WIDE_INT value2 = INTVAL (src2);
5026 /* Having 0 as one of the constants can be done by loading the other
5027 constant, and optionally moving in gr0. */
5030 emit_move_insn (dest, src2);
5031 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5032 gen_rtx_NE (cr_mode, cr_reg,
5034 gen_rtx_SET (VOIDmode, dest, src1)));
5037 else if (value2 == 0)
5039 emit_move_insn (dest, src1);
5040 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5041 gen_rtx_EQ (cr_mode, cr_reg,
5043 gen_rtx_SET (VOIDmode, dest, src2)));
5046 /* If the first value is within an addi range and also the difference
5047 between the two fits in an addi's range, load up the difference, then
5048 conditionally move in 0, and then unconditionally add the first
5050 else if (IN_RANGE_P (value1, -2048, 2047)
5051 && IN_RANGE_P (value2 - value1, -2048, 2047))
5053 rtx dest_si = ((GET_MODE (dest) == SImode)
5055 : gen_rtx_SUBREG (SImode, dest, 0));
5057 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5058 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5059 gen_rtx_NE (cr_mode, cr_reg,
5061 gen_rtx_SET (VOIDmode, dest_si,
5063 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5071 /* Emit the conditional move for the test being true if needed. */
5072 if (! rtx_equal_p (dest, src1))
5073 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5074 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5075 gen_rtx_SET (VOIDmode, dest, src1)));
5077 /* Emit the conditional move for the test being false if needed. */
5078 if (! rtx_equal_p (dest, src2))
5079 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5080 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5081 gen_rtx_SET (VOIDmode, dest, src2)));
5084 /* Finish up, return sequence. */
5091 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5092 memory location that is not known to be dword-aligned. */
5094 frv_split_double_load (rtx dest, rtx source)
5096 int regno = REGNO (dest);
5097 rtx dest1 = gen_highpart (SImode, dest);
5098 rtx dest2 = gen_lowpart (SImode, dest);
5099 rtx address = XEXP (source, 0);
5101 /* If the address is pre-modified, load the lower-numbered register
5102 first, then load the other register using an integer offset from
5103 the modified base register. This order should always be safe,
5104 since the pre-modification cannot affect the same registers as the
5107 The situation for other loads is more complicated. Loading one
5108 of the registers could affect the value of ADDRESS, so we must
5109 be careful which order we do them in. */
5110 if (GET_CODE (address) == PRE_MODIFY
5111 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5113 /* It is safe to load the lower-numbered register first. */
5114 emit_move_insn (dest1, change_address (source, SImode, NULL));
5115 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5119 /* ADDRESS is not pre-modified and the address depends on the
5120 lower-numbered register. Load the higher-numbered register
5122 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5123 emit_move_insn (dest1, change_address (source, SImode, NULL));
5127 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5128 and SOURCE is either a double register or the constant zero. */
5130 frv_split_double_store (rtx dest, rtx source)
5132 rtx dest1 = change_address (dest, SImode, NULL);
5133 rtx dest2 = frv_index_memory (dest, SImode, 1);
5134 if (ZERO_P (source))
5136 emit_move_insn (dest1, CONST0_RTX (SImode));
5137 emit_move_insn (dest2, CONST0_RTX (SImode));
5141 emit_move_insn (dest1, gen_highpart (SImode, source));
5142 emit_move_insn (dest2, gen_lowpart (SImode, source));
5147 /* Split a min/max operation returning a SEQUENCE containing all of the
5151 frv_split_minmax (rtx operands[])
5153 rtx dest = operands[0];
5154 rtx minmax = operands[1];
5155 rtx src1 = operands[2];
5156 rtx src2 = operands[3];
5157 rtx cc_reg = operands[4];
5158 rtx cr_reg = operands[5];
5160 enum rtx_code test_code;
5161 enum machine_mode cr_mode = GET_MODE (cr_reg);
5165 /* Figure out which test to use. */
5166 switch (GET_CODE (minmax))
5171 case SMIN: test_code = LT; break;
5172 case SMAX: test_code = GT; break;
5173 case UMIN: test_code = LTU; break;
5174 case UMAX: test_code = GTU; break;
5177 /* Issue the compare instruction. */
5178 emit_insn (gen_rtx_SET (VOIDmode,
5180 gen_rtx_COMPARE (GET_MODE (cc_reg),
5183 /* Set the appropriate CCR bit. */
5184 emit_insn (gen_rtx_SET (VOIDmode,
5186 gen_rtx_fmt_ee (test_code,
5191 /* If are taking the min/max of a nonzero constant, load that first, and
5192 then do a conditional move of the other value. */
5193 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5195 gcc_assert (!rtx_equal_p (dest, src1));
5197 emit_move_insn (dest, src2);
5198 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5199 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5200 gen_rtx_SET (VOIDmode, dest, src1)));
5203 /* Otherwise, do each half of the move. */
5206 /* Emit the conditional move for the test being true if needed. */
5207 if (! rtx_equal_p (dest, src1))
5208 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5209 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5210 gen_rtx_SET (VOIDmode, dest, src1)));
5212 /* Emit the conditional move for the test being false if needed. */
5213 if (! rtx_equal_p (dest, src2))
5214 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5215 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5216 gen_rtx_SET (VOIDmode, dest, src2)));
5219 /* Finish up, return sequence. */
5226 /* Split an integer abs operation returning a SEQUENCE containing all of the
5230 frv_split_abs (rtx operands[])
5232 rtx dest = operands[0];
5233 rtx src = operands[1];
5234 rtx cc_reg = operands[2];
5235 rtx cr_reg = operands[3];
5240 /* Issue the compare < 0 instruction. */
5241 emit_insn (gen_rtx_SET (VOIDmode,
5243 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5245 /* Set the appropriate CCR bit. */
5246 emit_insn (gen_rtx_SET (VOIDmode,
5248 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5250 /* Emit the conditional negate if the value is negative. */
5251 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5252 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5253 gen_negsi2 (dest, src)));
5255 /* Emit the conditional move for the test being false if needed. */
5256 if (! rtx_equal_p (dest, src))
5257 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5258 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5259 gen_rtx_SET (VOIDmode, dest, src)));
5261 /* Finish up, return sequence. */
5268 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5269 register used in an insn. */
5272 frv_clear_registers_used (rtx *ptr, void *data)
5274 if (GET_CODE (*ptr) == REG)
5276 int regno = REGNO (*ptr);
5277 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5279 if (regno < FIRST_PSEUDO_REGISTER)
5281 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5283 while (regno < reg_max)
5285 CLEAR_HARD_REG_BIT (*p_regs, regno);
5295 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5297 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5298 initialize the static storage. */
5300 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5302 frv_ifcvt.added_insns_list = NULL_RTX;
5303 frv_ifcvt.cur_scratch_regs = 0;
5304 frv_ifcvt.num_nested_cond_exec = 0;
5305 frv_ifcvt.cr_reg = NULL_RTX;
5306 frv_ifcvt.nested_cc_reg = NULL_RTX;
5307 frv_ifcvt.extra_int_cr = NULL_RTX;
5308 frv_ifcvt.extra_fp_cr = NULL_RTX;
5309 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5313 /* Internal function to add a potential insn to the list of insns to be inserted
5314 if the conditional execution conversion is successful. */
5317 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5319 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5321 link->jump = before_p; /* Mark to add this before or after insn. */
5322 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5323 frv_ifcvt.added_insns_list);
5325 if (TARGET_DEBUG_COND_EXEC)
5328 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5329 (before_p) ? "before" : "after",
5330 (int)INSN_UID (insn));
5332 debug_rtx (pattern);
5337 /* A C expression to modify the code described by the conditional if
5338 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5339 FALSE_EXPR for converting if-then and if-then-else code to conditional
5340 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5341 tests cannot be converted. */
5344 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5346 basic_block test_bb = ce_info->test_bb; /* test basic block */
5347 basic_block then_bb = ce_info->then_bb; /* THEN */
5348 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5349 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5350 rtx true_expr = *p_true;
5354 enum machine_mode mode = GET_MODE (true_expr);
5358 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5360 rtx sub_cond_exec_reg;
5362 enum rtx_code code_true;
5363 enum rtx_code code_false;
5364 enum reg_class cc_class;
5365 enum reg_class cr_class;
5368 reg_set_iterator rsi;
5370 /* Make sure we are only dealing with hard registers. Also honor the
5371 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5373 if (!reload_completed || !TARGET_COND_EXEC
5374 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5377 /* Figure out which registers we can allocate for our own purposes. Only
5378 consider registers that are not preserved across function calls and are
5379 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5380 if we did not need to use them in reloading other registers. */
5381 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5382 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5383 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5384 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5385 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5387 /* If this is a nested IF, we need to discover whether the CC registers that
5388 are set/used inside of the block are used anywhere else. If not, we can
5389 change them to be the CC register that is paired with the CR register that
5390 controls the outermost IF block. */
5391 if (ce_info->pass > 1)
5393 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5394 for (j = CC_FIRST; j <= CC_LAST; j++)
5395 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5397 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5401 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5405 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5408 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5412 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5413 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5415 frv_ifcvt.added_insns_list = NULL_RTX;
5416 frv_ifcvt.cur_scratch_regs = 0;
5418 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5419 * sizeof (basic_block));
5425 /* Remove anything live at the beginning of the join block from being
5426 available for allocation. */
5427 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5429 if (regno < FIRST_PSEUDO_REGISTER)
5430 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5434 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5436 if (ce_info->num_multiple_test_blocks)
5438 basic_block multiple_test_bb = ce_info->last_test_bb;
5440 while (multiple_test_bb != test_bb)
5442 bb[num_bb++] = multiple_test_bb;
5443 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5447 /* Add in the THEN and ELSE blocks to be scanned. */
5448 bb[num_bb++] = then_bb;
5450 bb[num_bb++] = else_bb;
5452 sub_cond_exec_reg = NULL_RTX;
5453 frv_ifcvt.num_nested_cond_exec = 0;
5455 /* Scan all of the blocks for registers that must not be allocated. */
5456 for (j = 0; j < num_bb; j++)
5458 rtx last_insn = BB_END (bb[j]);
5459 rtx insn = BB_HEAD (bb[j]);
5463 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5464 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5466 (int) INSN_UID (BB_HEAD (bb[j])),
5467 (int) INSN_UID (BB_END (bb[j])));
5469 /* Anything live at the beginning of the block is obviously unavailable
5471 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5473 if (regno < FIRST_PSEUDO_REGISTER)
5474 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5477 /* Loop through the insns in the block. */
5480 /* Mark any new registers that are created as being unavailable for
5481 allocation. Also see if the CC register used in nested IFs can be
5487 int skip_nested_if = FALSE;
5489 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5490 (void *)&tmp_reg->regs);
5492 pattern = PATTERN (insn);
5493 if (GET_CODE (pattern) == COND_EXEC)
5495 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5497 if (reg != sub_cond_exec_reg)
5499 sub_cond_exec_reg = reg;
5500 frv_ifcvt.num_nested_cond_exec++;
5504 set = single_set_pattern (pattern);
5507 rtx dest = SET_DEST (set);
5508 rtx src = SET_SRC (set);
5510 if (GET_CODE (dest) == REG)
5512 int regno = REGNO (dest);
5513 enum rtx_code src_code = GET_CODE (src);
5515 if (CC_P (regno) && src_code == COMPARE)
5516 skip_nested_if = TRUE;
5518 else if (CR_P (regno)
5519 && (src_code == IF_THEN_ELSE
5520 || COMPARISON_P (src)))
5521 skip_nested_if = TRUE;
5525 if (! skip_nested_if)
5526 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5527 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5530 if (insn == last_insn)
5533 insn = NEXT_INSN (insn);
5537 /* If this is a nested if, rewrite the CC registers that are available to
5538 include the ones that can be rewritten, to increase the chance of being
5539 able to allocate a paired CC/CR register combination. */
5540 if (ce_info->pass > 1)
5542 for (j = CC_FIRST; j <= CC_LAST; j++)
5543 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5544 SET_HARD_REG_BIT (tmp_reg->regs, j);
5546 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5552 fprintf (dump_file, "Available GPRs: ");
5554 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5555 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5557 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5558 if (++num_gprs > GPR_TEMP_NUM+2)
5562 fprintf (dump_file, "%s\nAvailable CRs: ",
5563 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5565 for (j = CR_FIRST; j <= CR_LAST; j++)
5566 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5567 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5569 fputs ("\n", dump_file);
5571 if (ce_info->pass > 1)
5573 fprintf (dump_file, "Modifiable CCs: ");
5574 for (j = CC_FIRST; j <= CC_LAST; j++)
5575 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5576 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5578 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5579 frv_ifcvt.num_nested_cond_exec);
5583 /* Allocate the appropriate temporary condition code register. Try to
5584 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5585 that conditional cmp's can be done. */
5586 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5588 cr_class = ICR_REGS;
5589 cc_class = ICC_REGS;
5590 cc_first = ICC_FIRST;
5593 else if (mode == CC_FPmode)
5595 cr_class = FCR_REGS;
5596 cc_class = FCC_REGS;
5597 cc_first = FCC_FIRST;
5602 cc_first = cc_last = 0;
5603 cr_class = cc_class = NO_REGS;
5606 cc = XEXP (true_expr, 0);
5607 nested_cc = cr = NULL_RTX;
5608 if (cc_class != NO_REGS)
5610 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5611 so we can execute a csubcc/caddcc/cfcmps instruction. */
5614 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5616 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5618 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5619 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5621 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5622 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5625 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5626 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5636 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5643 "Will use %s for conditional execution, %s for nested comparisons\n",
5644 reg_names[ REGNO (cr)],
5645 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5647 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5648 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5649 bit being true. We don't do this for floating point, because of NaNs. */
5650 code = GET_CODE (true_expr);
5651 if (GET_MODE (cc) != CC_FPmode)
5653 code = reverse_condition (code);
5663 check_insn = gen_rtx_SET (VOIDmode, cr,
5664 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5666 /* Record the check insn to be inserted later. */
5667 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5669 /* Update the tests. */
5670 frv_ifcvt.cr_reg = cr;
5671 frv_ifcvt.nested_cc_reg = nested_cc;
5672 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5673 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5676 /* Fail, don't do this conditional execution. */
5679 *p_false = NULL_RTX;
5681 fprintf (dump_file, "Disabling this conditional execution.\n");
5687 /* A C expression to modify the code described by the conditional if
5688 information CE_INFO, for the basic block BB, possibly updating the tests in
5689 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5690 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5691 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5693 /* p_true and p_false are given expressions of the form:
5695 (and (eq:CC_CCR (reg:CC_CCR)
5701 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5706 rtx old_true = XEXP (*p_true, 0);
5707 rtx old_false = XEXP (*p_false, 0);
5708 rtx true_expr = XEXP (*p_true, 1);
5709 rtx false_expr = XEXP (*p_false, 1);
5712 rtx cr = XEXP (old_true, 0);
5714 rtx new_cr = NULL_RTX;
5715 rtx *p_new_cr = (rtx *)0;
5719 enum reg_class cr_class;
5720 enum machine_mode mode = GET_MODE (true_expr);
5721 rtx (*logical_func)(rtx, rtx, rtx);
5723 if (TARGET_DEBUG_COND_EXEC)
5726 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5727 ce_info->and_and_p ? "&&" : "||");
5729 debug_rtx (*p_true);
5731 fputs ("\nfalse insn:\n", stderr);
5732 debug_rtx (*p_false);
5735 if (!TARGET_MULTI_CE)
5738 if (GET_CODE (cr) != REG)
5741 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5743 cr_class = ICR_REGS;
5744 p_new_cr = &frv_ifcvt.extra_int_cr;
5746 else if (mode == CC_FPmode)
5748 cr_class = FCR_REGS;
5749 p_new_cr = &frv_ifcvt.extra_fp_cr;
5754 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5755 more &&/|| tests. */
5759 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5760 CC_CCRmode, TRUE, TRUE);
5765 if (ce_info->and_and_p)
5767 old_test = old_false;
5768 test_expr = true_expr;
5769 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5770 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5771 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5775 old_test = old_false;
5776 test_expr = false_expr;
5777 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5778 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5779 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5782 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5783 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5785 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5787 /* Now add the conditional check insn. */
5788 cc = XEXP (test_expr, 0);
5789 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5790 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5792 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5794 /* Add the new check insn to the list of check insns that need to be
5796 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5798 if (TARGET_DEBUG_COND_EXEC)
5800 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5803 debug_rtx (*p_true);
5805 fputs ("\nfalse insn:\n", stderr);
5806 debug_rtx (*p_false);
5812 *p_true = *p_false = NULL_RTX;
5814 /* If we allocated a CR register, release it. */
5817 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5818 *p_new_cr = NULL_RTX;
5821 if (TARGET_DEBUG_COND_EXEC)
5822 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5828 /* Return a register which will be loaded with a value if an IF block is
5829 converted to conditional execution. This is used to rewrite instructions
5830 that use constants to ones that just use registers. */
5833 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5835 int num_alloc = frv_ifcvt.cur_scratch_regs;
5839 /* We know gr0 == 0, so replace any errant uses. */
5840 if (value == const0_rtx)
5841 return gen_rtx_REG (SImode, GPR_FIRST);
5843 /* First search all registers currently loaded to see if we have an
5844 applicable constant. */
5845 if (CONSTANT_P (value)
5846 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5848 for (i = 0; i < num_alloc; i++)
5850 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5851 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5855 /* Have we exhausted the number of registers available? */
5856 if (num_alloc >= GPR_TEMP_NUM)
5859 fprintf (dump_file, "Too many temporary registers allocated\n");
5864 /* Allocate the new register. */
5865 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5869 fputs ("Could not find a scratch register\n", dump_file);
5874 frv_ifcvt.cur_scratch_regs++;
5875 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5879 if (GET_CODE (value) == CONST_INT)
5880 fprintf (dump_file, "Register %s will hold %ld\n",
5881 reg_names[ REGNO (reg)], (long)INTVAL (value));
5883 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5884 fprintf (dump_file, "Register %s will hold LR\n",
5885 reg_names[ REGNO (reg)]);
5888 fprintf (dump_file, "Register %s will hold a saved value\n",
5889 reg_names[ REGNO (reg)]);
5896 /* Update a MEM used in conditional code that might contain an offset to put
5897 the offset into a scratch register, so that the conditional load/store
5898 operations can be used. This function returns the original pointer if the
5899 MEM is valid to use in conditional code, NULL if we can't load up the offset
5900 into a temporary register, or the new MEM if we were successful. */
5903 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5905 rtx addr = XEXP (mem, 0);
5907 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5909 if (GET_CODE (addr) == PLUS)
5911 rtx addr_op0 = XEXP (addr, 0);
5912 rtx addr_op1 = XEXP (addr, 1);
5914 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5916 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5920 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5927 else if (CONSTANT_P (addr))
5928 addr = frv_ifcvt_load_value (addr, insn);
5933 if (addr == NULL_RTX)
5936 else if (XEXP (mem, 0) != addr)
5937 return change_address (mem, mode, addr);
5944 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5945 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5948 single_set_pattern (rtx pattern)
5953 if (GET_CODE (pattern) == COND_EXEC)
5954 pattern = COND_EXEC_CODE (pattern);
5956 if (GET_CODE (pattern) == SET)
5959 else if (GET_CODE (pattern) == PARALLEL)
5961 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5963 rtx sub = XVECEXP (pattern, 0, i);
5965 switch (GET_CODE (sub))
5989 /* A C expression to modify the code described by the conditional if
5990 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5991 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5992 insn cannot be converted to be executed conditionally. */
5995 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5999 rtx orig_ce_pattern = pattern;
6005 gcc_assert (GET_CODE (pattern) == COND_EXEC);
6007 test = COND_EXEC_TEST (pattern);
6008 if (GET_CODE (test) == AND)
6010 rtx cr = frv_ifcvt.cr_reg;
6013 op0 = XEXP (test, 0);
6014 if (! rtx_equal_p (cr, XEXP (op0, 0)))
6017 op1 = XEXP (test, 1);
6018 test_reg = XEXP (op1, 0);
6019 if (GET_CODE (test_reg) != REG)
6022 /* Is this the first nested if block in this sequence? If so, generate
6023 an andcr or andncr. */
6024 if (! frv_ifcvt.last_nested_if_cr)
6028 frv_ifcvt.last_nested_if_cr = test_reg;
6029 if (GET_CODE (op0) == NE)
6030 and_op = gen_andcr (test_reg, cr, test_reg);
6032 and_op = gen_andncr (test_reg, cr, test_reg);
6034 frv_ifcvt_add_insn (and_op, insn, TRUE);
6037 /* If this isn't the first statement in the nested if sequence, see if we
6038 are dealing with the same register. */
6039 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6042 COND_EXEC_TEST (pattern) = test = op1;
6045 /* If this isn't a nested if, reset state variables. */
6048 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6051 set = single_set_pattern (pattern);
6054 rtx dest = SET_DEST (set);
6055 rtx src = SET_SRC (set);
6056 enum machine_mode mode = GET_MODE (dest);
6058 /* Check for normal binary operators. */
6059 if (mode == SImode && ARITHMETIC_P (src))
6061 op0 = XEXP (src, 0);
6062 op1 = XEXP (src, 1);
6064 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6066 op1 = frv_ifcvt_load_value (op1, insn);
6068 COND_EXEC_CODE (pattern)
6069 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6077 /* For multiply by a constant, we need to handle the sign extending
6078 correctly. Add a USE of the value after the multiply to prevent flow
6079 from cratering because only one register out of the two were used. */
6080 else if (mode == DImode && GET_CODE (src) == MULT)
6082 op0 = XEXP (src, 0);
6083 op1 = XEXP (src, 1);
6084 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6086 op1 = frv_ifcvt_load_value (op1, insn);
6089 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6090 COND_EXEC_CODE (pattern)
6091 = gen_rtx_SET (VOIDmode, dest,
6092 gen_rtx_MULT (DImode, op0, op1));
6098 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6101 /* If we are just loading a constant created for a nested conditional
6102 execution statement, just load the constant without any conditional
6103 execution, since we know that the constant will not interfere with any
6105 else if (frv_ifcvt.scratch_insns_bitmap
6106 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6108 && REG_P (SET_DEST (set))
6109 /* We must not unconditionally set a scratch reg chosen
6110 for a nested if-converted block if its incoming
6111 value from the TEST block (or the result of the THEN
6112 branch) could/should propagate to the JOIN block.
6113 It suffices to test whether the register is live at
6114 the JOIN point: if it's live there, we can infer
6115 that we set it in the former JOIN block of the
6116 nested if-converted block (otherwise it wouldn't
6117 have been available as a scratch register), and it
6118 is either propagated through or set in the other
6119 conditional block. It's probably not worth trying
6120 to catch the latter case, and it could actually
6121 limit scheduling of the combined block quite
6124 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6125 REGNO (SET_DEST (set))))
6126 /* Similarly, we must not unconditionally set a reg
6127 used as scratch in the THEN branch if the same reg
6128 is live in the ELSE branch. */
6129 && (! ce_info->else_bb
6130 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6131 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6132 REGNO (SET_DEST (set))))))
6135 else if (mode == QImode || mode == HImode || mode == SImode
6138 int changed_p = FALSE;
6140 /* Check for just loading up a constant */
6141 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6143 src = frv_ifcvt_load_value (src, insn);
6150 /* See if we need to fix up stores */
6151 if (GET_CODE (dest) == MEM)
6153 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6158 else if (new_mem != dest)
6165 /* See if we need to fix up loads */
6166 if (GET_CODE (src) == MEM)
6168 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6173 else if (new_mem != src)
6180 /* If either src or destination changed, redo SET. */
6182 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6185 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6186 rewriting the CC register to be the same as the paired CC/CR register
6188 else if (mode == CC_CCRmode && COMPARISON_P (src))
6190 int regno = REGNO (XEXP (src, 0));
6193 if (ce_info->pass > 1
6194 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6195 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6197 src = gen_rtx_fmt_ee (GET_CODE (src),
6199 frv_ifcvt.nested_cc_reg,
6203 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6204 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6207 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6208 else if (ce_info->pass > 1
6209 && GET_CODE (dest) == REG
6210 && CC_P (REGNO (dest))
6211 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6212 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6214 && GET_CODE (src) == COMPARE)
6216 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6217 COND_EXEC_CODE (pattern)
6218 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6222 if (TARGET_DEBUG_COND_EXEC)
6224 rtx orig_pattern = PATTERN (insn);
6226 PATTERN (insn) = pattern;
6228 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6232 PATTERN (insn) = orig_pattern;
6238 if (TARGET_DEBUG_COND_EXEC)
6240 rtx orig_pattern = PATTERN (insn);
6242 PATTERN (insn) = orig_ce_pattern;
6244 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6248 PATTERN (insn) = orig_pattern;
6255 /* A C expression to perform any final machine dependent modifications in
6256 converting code to conditional execution in the code described by the
6257 conditional if information CE_INFO. */
6260 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6264 rtx p = frv_ifcvt.added_insns_list;
6267 /* Loop inserting the check insns. The last check insn is the first test,
6268 and is the appropriate place to insert constants. */
6273 rtx check_and_insert_insns = XEXP (p, 0);
6276 check_insn = XEXP (check_and_insert_insns, 0);
6277 existing_insn = XEXP (check_and_insert_insns, 1);
6280 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6281 the existing insn, otherwise it is to be inserted AFTER. */
6282 if (check_and_insert_insns->jump)
6284 emit_insn_before (check_insn, existing_insn);
6285 check_and_insert_insns->jump = 0;
6288 emit_insn_after (check_insn, existing_insn);
6290 free_EXPR_LIST_node (check_and_insert_insns);
6291 free_EXPR_LIST_node (old_p);
6293 while (p != NULL_RTX);
6295 /* Load up any constants needed into temp gprs */
6296 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6298 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6299 if (! frv_ifcvt.scratch_insns_bitmap)
6300 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6301 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6302 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6305 frv_ifcvt.added_insns_list = NULL_RTX;
6306 frv_ifcvt.cur_scratch_regs = 0;
6310 /* A C expression to cancel any machine dependent modifications in converting
6311 code to conditional execution in the code described by the conditional if
6312 information CE_INFO. */
6315 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6318 rtx p = frv_ifcvt.added_insns_list;
6320 /* Loop freeing up the EXPR_LIST's allocated. */
6321 while (p != NULL_RTX)
6323 rtx check_and_jump = XEXP (p, 0);
6327 free_EXPR_LIST_node (check_and_jump);
6328 free_EXPR_LIST_node (old_p);
6331 /* Release any temporary gprs allocated. */
6332 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6333 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6335 frv_ifcvt.added_insns_list = NULL_RTX;
6336 frv_ifcvt.cur_scratch_regs = 0;
6340 /* A C expression for the size in bytes of the trampoline, as an integer.
6344 setlo #0, <static_chain>
6346 sethi #0, <static_chain>
6347 jmpl @(gr0,<jmp_reg>) */
6350 frv_trampoline_size (void)
6353 /* Allocate room for the function descriptor and the lddi
6356 return 5 /* instructions */ * 4 /* instruction size. */;
6360 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6361 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6362 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6363 should be passed to the function when it is called.
6368 setlo #0, <static_chain>
6370 sethi #0, <static_chain>
6371 jmpl @(gr0,<jmp_reg>) */
6374 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6376 rtx addr = XEXP (m_tramp, 0);
6377 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6378 rtx sc_reg = force_reg (Pmode, static_chain);
6380 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6381 LCT_NORMAL, VOIDmode, 4,
6383 GEN_INT (frv_trampoline_size ()), SImode,
6389 /* Many machines have some registers that cannot be copied directly to or from
6390 memory or even from other types of registers. An example is the `MQ'
6391 register, which on most machines, can only be copied to or from general
6392 registers, but not memory. Some machines allow copying all registers to and
6393 from memory, but require a scratch register for stores to some memory
6394 locations (e.g., those with symbolic address on the RT, and those with
6395 certain symbolic address on the SPARC when compiling PIC). In some cases,
6396 both an intermediate and a scratch register are required.
6398 You should define these macros to indicate to the reload phase that it may
6399 need to allocate at least one register for a reload in addition to the
6400 register to contain the data. Specifically, if copying X to a register
6401 RCLASS in MODE requires an intermediate register, you should define
6402 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6403 whose registers can be used as intermediate registers or scratch registers.
6405 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6406 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6407 largest register class required. If the requirements for input and output
6408 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6409 instead of defining both macros identically.
6411 The values returned by these macros are often `GENERAL_REGS'. Return
6412 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6413 to or from a register of RCLASS in MODE without requiring a scratch register.
6414 Do not define this macro if it would always return `NO_REGS'.
6416 If a scratch register is required (either with or without an intermediate
6417 register), you should define patterns for `reload_inM' or `reload_outM', as
6418 required.. These patterns, which will normally be implemented with a
6419 `define_expand', should be similar to the `movM' patterns, except that
6420 operand 2 is the scratch register.
6422 Define constraints for the reload register and scratch register that contain
6423 a single register class. If the original reload register (whose class is
6424 RCLASS) can meet the constraint given in the pattern, the value returned by
6425 these macros is used for the class of the scratch register. Otherwise, two
6426 additional reload registers are required. Their classes are obtained from
6427 the constraints in the insn pattern.
6429 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6430 either be in a hard register or in memory. Use `true_regnum' to find out;
6431 it will return -1 if the pseudo is in memory and the hard register number if
6432 it is in a register.
6434 These macros should not be used in the case where a particular class of
6435 registers can only be copied to memory and not to another class of
6436 registers. In that case, secondary reload registers are not needed and
6437 would not be helpful. Instead, a stack location must be used to perform the
6438 copy and the `movM' pattern should use memory as an intermediate storage.
6439 This case often occurs between floating-point and general registers. */
6442 frv_secondary_reload_class (enum reg_class rclass,
6443 enum machine_mode mode ATTRIBUTE_UNUSED,
6454 /* Accumulators/Accumulator guard registers need to go through floating
6460 if (x && GET_CODE (x) == REG)
6462 int regno = REGNO (x);
6464 if (ACC_P (regno) || ACCG_P (regno))
6469 /* Nonzero constants should be loaded into an FPR through a GPR. */
6473 if (x && CONSTANT_P (x) && !ZERO_P (x))
6479 /* All of these types need gpr registers. */
6491 /* The accumulators need fpr registers. */
6503 /* This hook exists to catch the case where secondary_reload_class() is
6504 called from init_reg_autoinc() in regclass.c - before the reload optabs
6505 have been initialised. */
6508 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6509 enum machine_mode reload_mode,
6510 secondary_reload_info * sri)
6512 enum reg_class rclass = NO_REGS;
6513 enum reg_class reload_class = (enum reg_class) reload_class_i;
6515 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6517 sri->icode = sri->prev_sri->t_icode;
6521 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6523 if (rclass != NO_REGS)
6525 enum insn_code icode
6526 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6530 /* This happens when then the reload_[in|out]_optabs have
6531 not been initialised. */
6532 sri->t_icode = CODE_FOR_nothing;
6537 /* Fall back to the default secondary reload handler. */
6538 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6542 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6545 frv_class_likely_spilled_p (reg_class_t rclass)
6555 case FDPIC_FPTR_REGS:
6577 /* An expression for the alignment of a structure field FIELD if the
6578 alignment computed in the usual way is COMPUTED. GCC uses this
6579 value instead of the value in `BIGGEST_ALIGNMENT' or
6580 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6582 /* The definition type of the bit field data is either char, short, long or
6583 long long. The maximum bit size is the number of bits of its own type.
6585 The bit field data is assigned to a storage unit that has an adequate size
6586 for bit field data retention and is located at the smallest address.
6588 Consecutive bit field data are packed at consecutive bits having the same
6589 storage unit, with regard to the type, beginning with the MSB and continuing
6592 If a field to be assigned lies over a bit field type boundary, its
6593 assignment is completed by aligning it with a boundary suitable for the
6596 When a bit field having a bit length of 0 is declared, it is forcibly
6597 assigned to the next storage unit.
6610 &x 00000000 00000000 00000000 00000000
6613 &x+4 00000000 00000000 00000000 00000000
6616 &x+8 00000000 00000000 00000000 00000000
6619 &x+12 00000000 00000000 00000000 00000000
6625 frv_adjust_field_align (tree field, int computed)
6627 /* Make sure that the bitfield is not wider than the type. */
6628 if (DECL_BIT_FIELD (field)
6629 && !DECL_ARTIFICIAL (field))
6631 tree parent = DECL_CONTEXT (field);
6632 tree prev = NULL_TREE;
6635 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6637 if (TREE_CODE (cur) != FIELD_DECL)
6645 /* If this isn't a :0 field and if the previous element is a bitfield
6646 also, see if the type is different, if so, we will need to align the
6647 bit-field to the next boundary. */
6649 && ! DECL_PACKED (field)
6650 && ! integer_zerop (DECL_SIZE (field))
6651 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6653 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6654 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6655 computed = (prev_align > cur_align) ? prev_align : cur_align;
6663 /* A C expression that is nonzero if it is permissible to store a value of mode
6664 MODE in hard register number REGNO (or in several registers starting with
6665 that one). For a machine where all registers are equivalent, a suitable
6668 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6670 It is not necessary for this macro to check for the numbers of fixed
6671 registers, because the allocation mechanism considers them to be always
6674 On some machines, double-precision values must be kept in even/odd register
6675 pairs. The way to implement that is to define this macro to reject odd
6676 register numbers for such modes.
6678 The minimum requirement for a mode to be OK in a register is that the
6679 `movMODE' instruction pattern support moves between the register and any
6680 other hard register for which the mode is OK; and that moving a value into
6681 the register and back out not alter it.
6683 Since the same instruction used to move `SImode' will work for all narrower
6684 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6685 to distinguish between these modes, provided you define patterns `movhi',
6686 etc., to take advantage of this. This is useful because of the interaction
6687 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6688 all integer modes to be tieable.
6690 Many machines have special registers for floating point arithmetic. Often
6691 people assume that floating point machine modes are allowed only in floating
6692 point registers. This is not true. Any registers that can hold integers
6693 can safely *hold* a floating point machine mode, whether or not floating
6694 arithmetic can be done on it in those registers. Integer move instructions
6695 can be used to move the values.
6697 On some machines, though, the converse is true: fixed-point machine modes
6698 may not go in floating registers. This is true if the floating registers
6699 normalize any value stored in them, because storing a non-floating value
6700 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6701 fixed-point machine modes in floating registers. But if the floating
6702 registers do not automatically normalize, if you can store any bit pattern
6703 in one and retrieve it unchanged without a trap, then any machine mode may
6704 go in a floating register, so you can define this macro to say so.
6706 The primary significance of special floating registers is rather that they
6707 are the registers acceptable in floating point arithmetic instructions.
6708 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6709 writing the proper constraints for those instructions.
6711 On some machines, the floating registers are especially slow to access, so
6712 that it is better to store a value in a stack frame than in such a register
6713 if floating point arithmetic is not being done. As long as the floating
6714 registers are not in class `GENERAL_REGS', they will not be used unless some
6715 pattern's constraint asks for one. */
6718 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6728 return ICC_P (regno) || GPR_P (regno);
6731 return CR_P (regno) || GPR_P (regno);
6734 return FCC_P (regno) || GPR_P (regno);
6740 /* Set BASE to the first register in REGNO's class. Set MASK to the
6741 bits that must be clear in (REGNO - BASE) for the register to be
6743 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6747 /* ACCGs store one byte. Two-byte quantities must start in
6748 even-numbered registers, four-byte ones in registers whose
6749 numbers are divisible by four, and so on. */
6751 mask = GET_MODE_SIZE (mode) - 1;
6755 /* The other registers store one word. */
6756 if (GPR_P (regno) || regno == AP_FIRST)
6759 else if (FPR_P (regno))
6762 else if (ACC_P (regno))
6765 else if (SPR_P (regno))
6766 return mode == SImode;
6768 /* Fill in the table. */
6772 /* Anything smaller than an SI is OK in any word-sized register. */
6773 if (GET_MODE_SIZE (mode) < 4)
6776 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6778 return (((regno - base) & mask) == 0);
6785 /* A C expression for the number of consecutive hard registers, starting at
6786 register number REGNO, required to hold a value of mode MODE.
6788 On a machine where all registers are exactly one word, a suitable definition
6791 #define HARD_REGNO_NREGS(REGNO, MODE) \
6792 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6793 / UNITS_PER_WORD)) */
6795 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6796 that we can build the appropriate instructions to properly reload the
6797 values. Also, make the byte-sized accumulator guards use one guard
6801 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6804 return GET_MODE_SIZE (mode);
6806 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6810 /* A C expression for the maximum number of consecutive registers of
6811 class RCLASS needed to hold a value of mode MODE.
6813 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6814 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6815 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6817 This macro helps control the handling of multiple-word values in
6820 This declaration is required. */
6823 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6825 if (rclass == ACCG_REGS)
6826 /* An N-byte value requires N accumulator guards. */
6827 return GET_MODE_SIZE (mode);
6829 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6833 /* A C expression that is nonzero if X is a legitimate constant for an
6834 immediate operand on the target machine. You can assume that X satisfies
6835 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6836 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6839 frv_legitimate_constant_p (rtx x)
6841 enum machine_mode mode = GET_MODE (x);
6843 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6844 means that the move expanders will be expected to deal with most
6845 kinds of constant, regardless of what we return here.
6847 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6848 a constant can be entered into reg_equiv_constant[]. If we return true,
6849 reload can create new instances of the constant whenever it likes.
6851 The idea is therefore to accept as many constants as possible (to give
6852 reload more freedom) while rejecting constants that can only be created
6853 at certain times. In particular, anything with a symbolic component will
6854 require use of the pseudo FDPIC register, which is only available before
6857 return LEGITIMATE_PIC_OPERAND_P (x);
6859 /* All of the integer constants are ok. */
6860 if (GET_CODE (x) != CONST_DOUBLE)
6863 /* double integer constants are ok. */
6864 if (mode == VOIDmode || mode == DImode)
6867 /* 0 is always ok. */
6868 if (x == CONST0_RTX (mode))
6871 /* If floating point is just emulated, allow any constant, since it will be
6872 constructed in the GPRs. */
6873 if (!TARGET_HAS_FPRS)
6876 if (mode == DFmode && !TARGET_DOUBLE)
6879 /* Otherwise store the constant away and do a load. */
6883 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6884 CC_NZ for comparisons against zero in which a single Z or N flag test
6885 is enough, CC_UNS for other unsigned comparisons, and CC for other
6886 signed comparisons. */
6889 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6891 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6900 return y == const0_rtx ? CC_NZmode : CCmode;
6906 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6914 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6916 #define HIGH_COST 40
6917 #define MEDIUM_COST 3
6921 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6922 reg_class_t from, reg_class_t to)
7006 /* Worker function for TARGET_MEMORY_MOVE_COST. */
7009 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
7010 reg_class_t rclass ATTRIBUTE_UNUSED,
7011 bool in ATTRIBUTE_UNUSED)
7017 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7018 use ".picptr" to generate safe relocations for PIC code. We also
7019 need a fixup entry for aligned (non-debugging) code. */
7022 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
7024 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
7026 if (GET_CODE (value) == CONST
7027 || GET_CODE (value) == SYMBOL_REF
7028 || GET_CODE (value) == LABEL_REF)
7030 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
7031 && SYMBOL_REF_FUNCTION_P (value))
7033 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
7034 output_addr_const (asm_out_file, value);
7035 fputs (")\n", asm_out_file);
7038 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7039 && frv_function_symbol_referenced_p (value))
7041 if (aligned_p && !TARGET_FDPIC)
7043 static int label_num = 0;
7047 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7048 p = (* targetm.strip_name_encoding) (buf);
7050 fprintf (asm_out_file, "%s:\n", p);
7051 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7052 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7053 fprintf (asm_out_file, "\t.previous\n");
7055 assemble_integer_with_op ("\t.picptr\t", value);
7060 /* We've set the unaligned SI op to NULL, so we always have to
7061 handle the unaligned case here. */
7062 assemble_integer_with_op ("\t.4byte\t", value);
7066 return default_assemble_integer (value, size, aligned_p);
7069 /* Function to set up the backend function structure. */
7071 static struct machine_function *
7072 frv_init_machine_status (void)
7074 return ggc_alloc_cleared_machine_function ();
7077 /* Implement TARGET_SCHED_ISSUE_RATE. */
7080 frv_issue_rate (void)
7085 switch (frv_cpu_type)
7089 case FRV_CPU_SIMPLE:
7097 case FRV_CPU_GENERIC:
7099 case FRV_CPU_TOMCAT:
7107 /* A for_each_rtx callback. If X refers to an accumulator, return
7108 ACC_GROUP_ODD if the bit 2 of the register number is set and
7109 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7113 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7117 if (ACC_P (REGNO (*x)))
7118 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7119 if (ACCG_P (REGNO (*x)))
7120 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7125 /* Return the value of INSN's acc_group attribute. */
7128 frv_acc_group (rtx insn)
7130 /* This distinction only applies to the FR550 packing constraints. */
7131 if (frv_cpu_type != FRV_CPU_FR550)
7132 return ACC_GROUP_NONE;
7133 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7136 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7137 INSN will try to claim first. Since this value depends only on the
7138 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7141 frv_insn_unit (rtx insn)
7143 enum attr_type type;
7145 type = get_attr_type (insn);
7146 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7148 /* We haven't seen this type of instruction before. */
7152 /* Issue the instruction on its own to see which unit it prefers. */
7153 state = alloca (state_size ());
7154 state_reset (state);
7155 state_transition (state, insn);
7157 /* Find out which unit was taken. */
7158 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7159 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7162 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7164 frv_type_to_unit[type] = unit;
7166 return frv_type_to_unit[type];
7169 /* Return true if INSN issues to a branch unit. */
7172 frv_issues_to_branch_unit_p (rtx insn)
7174 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7177 /* The instructions in the packet, partitioned into groups. */
7178 struct frv_packet_group {
7179 /* How many instructions in the packet belong to this group. */
7180 unsigned int num_insns;
7182 /* A list of the instructions that belong to this group, in the order
7183 they appear in the rtl stream. */
7184 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7186 /* The contents of INSNS after they have been sorted into the correct
7187 assembly-language order. Element X issues to unit X. The list may
7188 contain extra nops. */
7189 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7191 /* The member of frv_nops[] to use in sorted[]. */
7195 /* The current state of the packing pass, implemented by frv_pack_insns. */
7197 /* The state of the pipeline DFA. */
7200 /* Which hardware registers are set within the current packet,
7201 and the conditions under which they are set. */
7202 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7204 /* The memory locations that have been modified so far in this
7205 packet. MEM is the memref and COND is the regstate_t condition
7206 under which it is set. */
7212 /* The number of valid entries in MEMS. The value is larger than
7213 ARRAY_SIZE (mems) if there were too many mems to record. */
7214 unsigned int num_mems;
7216 /* The maximum number of instructions that can be packed together. */
7217 unsigned int issue_rate;
7219 /* The instructions in the packet, partitioned into groups. */
7220 struct frv_packet_group groups[NUM_GROUPS];
7222 /* The instructions that make up the current packet. */
7223 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7224 unsigned int num_insns;
7227 /* Return the regstate_t flags for the given COND_EXEC condition.
7228 Abort if the condition isn't in the right form. */
7231 frv_cond_flags (rtx cond)
7233 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7234 && GET_CODE (XEXP (cond, 0)) == REG
7235 && CR_P (REGNO (XEXP (cond, 0)))
7236 && XEXP (cond, 1) == const0_rtx);
7237 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7238 | (GET_CODE (cond) == NE
7240 : REGSTATE_IF_FALSE));
7244 /* Return true if something accessed under condition COND2 can
7245 conflict with something written under condition COND1. */
7248 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7250 /* If either reference was unconditional, we have a conflict. */
7251 if ((cond1 & REGSTATE_IF_EITHER) == 0
7252 || (cond2 & REGSTATE_IF_EITHER) == 0)
7255 /* The references might conflict if they were controlled by
7257 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7260 /* They definitely conflict if they are controlled by the
7262 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7269 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7270 the current packet. DATA points to a regstate_t that describes the
7271 condition under which *X might be set or used. */
7274 frv_registers_conflict_p_1 (rtx *x, void *data)
7276 unsigned int regno, i;
7279 cond = *(regstate_t *) data;
7281 if (GET_CODE (*x) == REG)
7282 FOR_EACH_REGNO (regno, *x)
7283 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7284 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7287 if (GET_CODE (*x) == MEM)
7289 /* If we ran out of memory slots, assume a conflict. */
7290 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7293 /* Check for output or true dependencies with earlier MEMs. */
7294 for (i = 0; i < frv_packet.num_mems; i++)
7295 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7297 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7301 if (output_dependence (frv_packet.mems[i].mem, *x))
7306 /* The return values of calls aren't significant: they describe
7307 the effect of the call as a whole, not of the insn itself. */
7308 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7310 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7315 /* Check subexpressions. */
7320 /* Return true if something in X might depend on an instruction
7321 in the current packet. */
7324 frv_registers_conflict_p (rtx x)
7329 if (GET_CODE (x) == COND_EXEC)
7331 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7334 flags |= frv_cond_flags (XEXP (x, 0));
7337 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7341 /* A note_stores callback. DATA points to the regstate_t condition
7342 under which X is modified. Update FRV_PACKET accordingly. */
7345 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7349 if (GET_CODE (x) == REG)
7350 FOR_EACH_REGNO (regno, x)
7351 frv_packet.regstate[regno] |= *(regstate_t *) data;
7353 if (GET_CODE (x) == MEM)
7355 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7357 frv_packet.mems[frv_packet.num_mems].mem = x;
7358 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7360 frv_packet.num_mems++;
7365 /* Update the register state information for an instruction whose
7369 frv_registers_update (rtx x)
7373 flags = REGSTATE_MODIFIED;
7374 if (GET_CODE (x) == COND_EXEC)
7376 flags |= frv_cond_flags (XEXP (x, 0));
7379 note_stores (x, frv_registers_update_1, &flags);
7383 /* Initialize frv_packet for the start of a new packet. */
7386 frv_start_packet (void)
7388 enum frv_insn_group group;
7390 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7391 frv_packet.num_mems = 0;
7392 frv_packet.num_insns = 0;
7393 for (group = GROUP_I; group < NUM_GROUPS;
7394 group = (enum frv_insn_group) (group + 1))
7395 frv_packet.groups[group].num_insns = 0;
7399 /* Likewise for the start of a new basic block. */
7402 frv_start_packet_block (void)
7404 state_reset (frv_packet.dfa_state);
7405 frv_start_packet ();
7409 /* Finish the current packet, if any, and start a new one. Call
7410 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7413 frv_finish_packet (void (*handle_packet) (void))
7415 if (frv_packet.num_insns > 0)
7418 state_transition (frv_packet.dfa_state, 0);
7419 frv_start_packet ();
7424 /* Return true if INSN can be added to the current packet. Update
7425 the DFA state on success. */
7428 frv_pack_insn_p (rtx insn)
7430 /* See if the packet is already as long as it can be. */
7431 if (frv_packet.num_insns == frv_packet.issue_rate)
7434 /* If the scheduler thought that an instruction should start a packet,
7435 it's usually a good idea to believe it. It knows much more about
7436 the latencies than we do.
7438 There are some exceptions though:
7440 - Conditional instructions are scheduled on the assumption that
7441 they will be executed. This is usually a good thing, since it
7442 tends to avoid unnecessary stalls in the conditional code.
7443 But we want to pack conditional instructions as tightly as
7444 possible, in order to optimize the case where they aren't
7447 - The scheduler will always put branches on their own, even
7448 if there's no real dependency.
7450 - There's no point putting a call in its own packet unless
7452 if (frv_packet.num_insns > 0
7453 && GET_CODE (insn) == INSN
7454 && GET_MODE (insn) == TImode
7455 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7458 /* Check for register conflicts. Don't do this for setlo since any
7459 conflict will be with the partnering sethi, with which it can
7461 if (get_attr_type (insn) != TYPE_SETLO)
7462 if (frv_registers_conflict_p (PATTERN (insn)))
7465 return state_transition (frv_packet.dfa_state, insn) < 0;
7469 /* Add instruction INSN to the current packet. */
7472 frv_add_insn_to_packet (rtx insn)
7474 struct frv_packet_group *packet_group;
7476 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7477 packet_group->insns[packet_group->num_insns++] = insn;
7478 frv_packet.insns[frv_packet.num_insns++] = insn;
7480 frv_registers_update (PATTERN (insn));
7484 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7485 packet ends in a branch or call, insert the nop before it, otherwise
7489 frv_insert_nop_in_packet (rtx insn)
7491 struct frv_packet_group *packet_group;
7494 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7495 last = frv_packet.insns[frv_packet.num_insns - 1];
7496 if (GET_CODE (last) != INSN)
7498 insn = emit_insn_before (PATTERN (insn), last);
7499 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7500 frv_packet.insns[frv_packet.num_insns++] = last;
7504 insn = emit_insn_after (PATTERN (insn), last);
7505 frv_packet.insns[frv_packet.num_insns++] = insn;
7507 packet_group->insns[packet_group->num_insns++] = insn;
7511 /* If packing is enabled, divide the instructions into packets and
7512 return true. Call HANDLE_PACKET for each complete packet. */
7515 frv_for_each_packet (void (*handle_packet) (void))
7517 rtx insn, next_insn;
7519 frv_packet.issue_rate = frv_issue_rate ();
7521 /* Early exit if we don't want to pack insns. */
7523 || !flag_schedule_insns_after_reload
7524 || !TARGET_VLIW_BRANCH
7525 || frv_packet.issue_rate == 1)
7528 /* Set up the initial packing state. */
7530 frv_packet.dfa_state = alloca (state_size ());
7532 frv_start_packet_block ();
7533 for (insn = get_insns (); insn != 0; insn = next_insn)
7538 code = GET_CODE (insn);
7539 next_insn = NEXT_INSN (insn);
7541 if (code == CODE_LABEL)
7543 frv_finish_packet (handle_packet);
7544 frv_start_packet_block ();
7548 switch (GET_CODE (PATTERN (insn)))
7557 /* Calls mustn't be packed on a TOMCAT. */
7558 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7559 frv_finish_packet (handle_packet);
7561 /* Since the last instruction in a packet determines the EH
7562 region, any exception-throwing instruction must come at
7563 the end of reordered packet. Insns that issue to a
7564 branch unit are bound to come last; for others it's
7565 too hard to predict. */
7566 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7567 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7568 frv_finish_packet (handle_packet);
7570 /* Finish the current packet if we can't add INSN to it.
7571 Simulate cycles until INSN is ready to issue. */
7572 if (!frv_pack_insn_p (insn))
7574 frv_finish_packet (handle_packet);
7575 while (!frv_pack_insn_p (insn))
7576 state_transition (frv_packet.dfa_state, 0);
7579 /* Add the instruction to the packet. */
7580 frv_add_insn_to_packet (insn);
7582 /* Calls and jumps end a packet, as do insns that throw
7584 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7585 frv_finish_packet (handle_packet);
7589 frv_finish_packet (handle_packet);
7594 /* Subroutine of frv_sort_insn_group. We are trying to sort
7595 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7596 language order. We have already picked a new position for
7597 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7598 These instructions will occupy elements [0, LOWER_SLOT) and
7599 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7600 the DFA state after issuing these instructions.
7602 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7603 of the unused instructions. Return true if one such permutation gives
7604 a valid ordering, leaving the successful permutation in sorted[].
7605 Do not modify sorted[] until a valid permutation is found. */
7608 frv_sort_insn_group_1 (enum frv_insn_group group,
7609 unsigned int lower_slot, unsigned int upper_slot,
7610 unsigned int issued, unsigned int num_insns,
7613 struct frv_packet_group *packet_group;
7619 /* Early success if we've filled all the slots. */
7620 if (lower_slot == upper_slot)
7623 packet_group = &frv_packet.groups[group];
7624 dfa_size = state_size ();
7625 test_state = alloca (dfa_size);
7627 /* Try issuing each unused instruction. */
7628 for (i = num_insns - 1; i + 1 != 0; i--)
7629 if (~issued & (1 << i))
7631 insn = packet_group->sorted[i];
7632 memcpy (test_state, state, dfa_size);
7633 if (state_transition (test_state, insn) < 0
7634 && cpu_unit_reservation_p (test_state,
7635 NTH_UNIT (group, upper_slot - 1))
7636 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7637 issued | (1 << i), num_insns,
7640 packet_group->sorted[upper_slot - 1] = insn;
7648 /* Compare two instructions by their frv_insn_unit. */
7651 frv_compare_insns (const void *first, const void *second)
7653 const rtx *const insn1 = (rtx const *) first,
7654 *const insn2 = (rtx const *) second;
7655 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7658 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7659 and sort it into assembly language order. See frv.md for a description of
7663 frv_sort_insn_group (enum frv_insn_group group)
7665 struct frv_packet_group *packet_group;
7666 unsigned int first, i, nop, max_unit, num_slots;
7667 state_t state, test_state;
7670 packet_group = &frv_packet.groups[group];
7672 /* Assume no nop is needed. */
7673 packet_group->nop = 0;
7675 if (packet_group->num_insns == 0)
7678 /* Copy insns[] to sorted[]. */
7679 memcpy (packet_group->sorted, packet_group->insns,
7680 sizeof (rtx) * packet_group->num_insns);
7682 /* Sort sorted[] by the unit that each insn tries to take first. */
7683 if (packet_group->num_insns > 1)
7684 qsort (packet_group->sorted, packet_group->num_insns,
7685 sizeof (rtx), frv_compare_insns);
7687 /* That's always enough for branch and control insns. */
7688 if (group == GROUP_B || group == GROUP_C)
7691 dfa_size = state_size ();
7692 state = alloca (dfa_size);
7693 test_state = alloca (dfa_size);
7695 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7696 consecutively and such that the DFA takes unit X when sorted[X]
7697 is added. Set STATE to the new DFA state. */
7698 state_reset (test_state);
7699 for (first = 0; first < packet_group->num_insns; first++)
7701 memcpy (state, test_state, dfa_size);
7702 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7703 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7707 /* If all the instructions issued in ascending order, we're done. */
7708 if (first == packet_group->num_insns)
7711 /* Add nops to the end of sorted[] and try each permutation until
7712 we find one that works. */
7713 for (nop = 0; nop < frv_num_nops; nop++)
7715 max_unit = frv_insn_unit (frv_nops[nop]);
7716 if (frv_unit_groups[max_unit] == group)
7718 packet_group->nop = frv_nops[nop];
7719 num_slots = UNIT_NUMBER (max_unit) + 1;
7720 for (i = packet_group->num_insns; i < num_slots; i++)
7721 packet_group->sorted[i] = frv_nops[nop];
7722 if (frv_sort_insn_group_1 (group, first, num_slots,
7723 (1 << first) - 1, num_slots, state))
7730 /* Sort the current packet into assembly-language order. Set packing
7731 flags as appropriate. */
7734 frv_reorder_packet (void)
7736 unsigned int cursor[NUM_GROUPS];
7737 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7738 unsigned int unit, to, from;
7739 enum frv_insn_group group;
7740 struct frv_packet_group *packet_group;
7742 /* First sort each group individually. */
7743 for (group = GROUP_I; group < NUM_GROUPS;
7744 group = (enum frv_insn_group) (group + 1))
7747 frv_sort_insn_group (group);
7750 /* Go through the unit template and try add an instruction from
7751 that unit's group. */
7753 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7755 group = frv_unit_groups[unit];
7756 packet_group = &frv_packet.groups[group];
7757 if (cursor[group] < packet_group->num_insns)
7759 /* frv_reorg should have added nops for us. */
7760 gcc_assert (packet_group->sorted[cursor[group]]
7761 != packet_group->nop);
7762 insns[to++] = packet_group->sorted[cursor[group]++];
7766 gcc_assert (to == frv_packet.num_insns);
7768 /* Clear the last instruction's packing flag, thus marking the end of
7769 a packet. Reorder the other instructions relative to it. */
7770 CLEAR_PACKING_FLAG (insns[to - 1]);
7771 for (from = 0; from < to - 1; from++)
7773 remove_insn (insns[from]);
7774 add_insn_before (insns[from], insns[to - 1], NULL);
7775 SET_PACKING_FLAG (insns[from]);
7780 /* Divide instructions into packets. Reorder the contents of each
7781 packet so that they are in the correct assembly-language order.
7783 Since this pass can change the raw meaning of the rtl stream, it must
7784 only be called at the last minute, just before the instructions are
7788 frv_pack_insns (void)
7790 if (frv_for_each_packet (frv_reorder_packet))
7791 frv_insn_packing_flag = 0;
7793 frv_insn_packing_flag = -1;
7796 /* See whether we need to add nops to group GROUP in order to
7797 make a valid packet. */
7800 frv_fill_unused_units (enum frv_insn_group group)
7802 unsigned int non_nops, nops, i;
7803 struct frv_packet_group *packet_group;
7805 packet_group = &frv_packet.groups[group];
7807 /* Sort the instructions into assembly-language order.
7808 Use nops to fill slots that are otherwise unused. */
7809 frv_sort_insn_group (group);
7811 /* See how many nops are needed before the final useful instruction. */
7813 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7814 while (packet_group->sorted[i++] == packet_group->nop)
7817 /* Insert that many nops into the instruction stream. */
7819 frv_insert_nop_in_packet (packet_group->nop);
7822 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7825 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7827 if (io1->const_address != 0 && io2->const_address != 0)
7828 return io1->const_address == io2->const_address;
7830 if (io1->var_address != 0 && io2->var_address != 0)
7831 return rtx_equal_p (io1->var_address, io2->var_address);
7836 /* Return true if operations IO1 and IO2 are guaranteed to complete
7840 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7842 /* The order of writes is always preserved. */
7843 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7846 /* The order of reads isn't preserved. */
7847 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7850 /* One operation is a write and the other is (or could be) a read.
7851 The order is only guaranteed if the accesses are to the same
7853 return frv_same_doubleword_p (io1, io2);
7856 /* Generalize I/O operation X so that it covers both X and Y. */
7859 frv_io_union (struct frv_io *x, const struct frv_io *y)
7861 if (x->type != y->type)
7862 x->type = FRV_IO_UNKNOWN;
7863 if (!frv_same_doubleword_p (x, y))
7865 x->const_address = 0;
7870 /* Fill IO with information about the load or store associated with
7871 membar instruction INSN. */
7874 frv_extract_membar (struct frv_io *io, rtx insn)
7876 extract_insn (insn);
7877 io->type = (enum frv_io_type) INTVAL (recog_data.operand[2]);
7878 io->const_address = INTVAL (recog_data.operand[1]);
7879 io->var_address = XEXP (recog_data.operand[0], 0);
7882 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7883 if X is a register and *DATA depends on X. */
7886 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7888 rtx *other = (rtx *) data;
7890 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7894 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7895 Remove every modified register from the set. */
7898 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7900 HARD_REG_SET *set = (HARD_REG_SET *) data;
7904 FOR_EACH_REGNO (regno, x)
7905 CLEAR_HARD_REG_BIT (*set, regno);
7908 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7909 Add every register in *X to the set. */
7912 frv_io_handle_use_1 (rtx *x, void *data)
7914 HARD_REG_SET *set = (HARD_REG_SET *) data;
7918 FOR_EACH_REGNO (regno, *x)
7919 SET_HARD_REG_BIT (*set, regno);
7924 /* A note_stores callback that applies frv_io_handle_use_1 to an
7925 entire rhs value. */
7928 frv_io_handle_use (rtx *x, void *data)
7930 for_each_rtx (x, frv_io_handle_use_1, data);
7933 /* Go through block BB looking for membars to remove. There are two
7934 cases where intra-block analysis is enough:
7936 - a membar is redundant if it occurs between two consecutive I/O
7937 operations and if those operations are guaranteed to complete
7940 - a membar for a __builtin_read is redundant if the result is
7941 used before the next I/O operation is issued.
7943 If the last membar in the block could not be removed, and there
7944 are guaranteed to be no I/O operations between that membar and
7945 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7948 Describe the block's first I/O operation in *NEXT_IO. Describe
7949 an unknown operation if the block doesn't do any I/O. */
7952 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7955 HARD_REG_SET used_regs;
7956 rtx next_membar, set, insn;
7959 /* NEXT_IO is the next I/O operation to be performed after the current
7960 instruction. It starts off as being an unknown operation. */
7961 memset (next_io, 0, sizeof (*next_io));
7963 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7964 next_is_end_p = true;
7966 /* If the current instruction is a __builtin_read or __builtin_write,
7967 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7968 is null if the membar has already been deleted.
7970 Note that the initialization here should only be needed to
7971 suppress warnings. */
7974 /* USED_REGS is the set of registers that are used before the
7975 next I/O instruction. */
7976 CLEAR_HARD_REG_SET (used_regs);
7978 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7979 if (GET_CODE (insn) == CALL_INSN)
7981 /* We can't predict what a call will do to volatile memory. */
7982 memset (next_io, 0, sizeof (struct frv_io));
7983 next_is_end_p = false;
7984 CLEAR_HARD_REG_SET (used_regs);
7986 else if (INSN_P (insn))
7987 switch (recog_memoized (insn))
7989 case CODE_FOR_optional_membar_qi:
7990 case CODE_FOR_optional_membar_hi:
7991 case CODE_FOR_optional_membar_si:
7992 case CODE_FOR_optional_membar_di:
7996 /* Local information isn't enough to decide whether this
7997 membar is needed. Stash it away for later. */
7998 *last_membar = insn;
7999 frv_extract_membar (next_io, insn);
8000 next_is_end_p = false;
8004 /* Check whether the I/O operation before INSN could be
8005 reordered with one described by NEXT_IO. If it can't,
8006 INSN will not be needed. */
8007 struct frv_io prev_io;
8009 frv_extract_membar (&prev_io, insn);
8010 if (frv_io_fixed_order_p (&prev_io, next_io))
8014 ";; [Local] Removing membar %d since order"
8015 " of accesses is guaranteed\n",
8016 INSN_UID (next_membar));
8018 insn = NEXT_INSN (insn);
8019 delete_insn (next_membar);
8027 /* Invalidate NEXT_IO's address if it depends on something that
8028 is clobbered by INSN. */
8029 if (next_io->var_address)
8030 note_stores (PATTERN (insn), frv_io_check_address,
8031 &next_io->var_address);
8033 /* If the next membar is associated with a __builtin_read,
8034 see if INSN reads from that address. If it does, and if
8035 the destination register is used before the next I/O access,
8036 there is no need for the membar. */
8037 set = PATTERN (insn);
8038 if (next_io->type == FRV_IO_READ
8039 && next_io->var_address != 0
8041 && GET_CODE (set) == SET
8042 && GET_CODE (SET_DEST (set)) == REG
8043 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8047 src = SET_SRC (set);
8048 if (GET_CODE (src) == ZERO_EXTEND)
8049 src = XEXP (src, 0);
8051 if (GET_CODE (src) == MEM
8052 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8056 ";; [Local] Removing membar %d since the target"
8057 " of %d is used before the I/O operation\n",
8058 INSN_UID (next_membar), INSN_UID (insn));
8060 if (next_membar == *last_membar)
8063 delete_insn (next_membar);
8068 /* If INSN has volatile references, forget about any registers
8069 that are used after it. Otherwise forget about uses that
8070 are (or might be) defined by INSN. */
8071 if (volatile_refs_p (PATTERN (insn)))
8072 CLEAR_HARD_REG_SET (used_regs);
8074 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8076 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8081 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8082 FIRST_IO[X] describes the first operation performed by basic block X. */
8085 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8088 struct frv_io this_io, next_io;
8092 /* We need to keep the membar if there is an edge to the exit block. */
8093 FOR_EACH_EDGE (succ, ei, bb->succs)
8094 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8095 if (succ->dest == EXIT_BLOCK_PTR)
8098 /* Work out the union of all successor blocks. */
8099 ei = ei_start (bb->succs);
8100 ei_cond (ei, &succ);
8101 /* next_io = first_io[bb->succ->dest->index]; */
8102 next_io = first_io[succ->dest->index];
8103 ei = ei_start (bb->succs);
8104 if (ei_cond (ei, &succ))
8106 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8107 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8108 frv_io_union (&next_io, &first_io[succ->dest->index]);
8113 frv_extract_membar (&this_io, membar);
8114 if (frv_io_fixed_order_p (&this_io, &next_io))
8118 ";; [Global] Removing membar %d since order of accesses"
8119 " is guaranteed\n", INSN_UID (membar));
8121 delete_insn (membar);
8125 /* Remove redundant membars from the current function. */
8128 frv_optimize_membar (void)
8131 struct frv_io *first_io;
8134 compute_bb_for_insn ();
8135 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8136 last_membar = XCNEWVEC (rtx, last_basic_block);
8139 frv_optimize_membar_local (bb, &first_io[bb->index],
8140 &last_membar[bb->index]);
8143 if (last_membar[bb->index] != 0)
8144 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8150 /* Used by frv_reorg to keep track of the current packet's address. */
8151 static unsigned int frv_packet_address;
8153 /* If the current packet falls through to a label, try to pad the packet
8154 with nops in order to fit the label's alignment requirements. */
8157 frv_align_label (void)
8159 unsigned int alignment, target, nop;
8160 rtx x, last, barrier, label;
8162 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8163 maximum alignment of that packet, LABEL to the last label between
8164 the packets, and BARRIER to the last barrier. */
8165 last = frv_packet.insns[frv_packet.num_insns - 1];
8166 label = barrier = 0;
8168 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8172 unsigned int subalign = 1 << label_to_alignment (x);
8173 alignment = MAX (alignment, subalign);
8180 /* If -malign-labels, and the packet falls through to an unaligned
8181 label, try introducing a nop to align that label to 8 bytes. */
8182 if (TARGET_ALIGN_LABELS
8185 && frv_packet.num_insns < frv_packet.issue_rate)
8186 alignment = MAX (alignment, 8);
8188 /* Advance the address to the end of the current packet. */
8189 frv_packet_address += frv_packet.num_insns * 4;
8191 /* Work out the target address, after alignment. */
8192 target = (frv_packet_address + alignment - 1) & -alignment;
8194 /* If the packet falls through to the label, try to find an efficient
8195 padding sequence. */
8198 /* First try adding nops to the current packet. */
8199 for (nop = 0; nop < frv_num_nops; nop++)
8200 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8202 frv_insert_nop_in_packet (frv_nops[nop]);
8203 frv_packet_address += 4;
8206 /* If we still haven't reached the target, add some new packets that
8207 contain only nops. If there are two types of nop, insert an
8208 alternating sequence of frv_nops[0] and frv_nops[1], which will
8209 lead to packets like:
8216 etc. Just emit frv_nops[0] if that's the only nop we have. */
8217 last = frv_packet.insns[frv_packet.num_insns - 1];
8219 while (frv_packet_address < target)
8221 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8222 frv_packet_address += 4;
8223 if (frv_num_nops > 1)
8228 frv_packet_address = target;
8231 /* Subroutine of frv_reorg, called after each packet has been constructed
8235 frv_reorg_packet (void)
8237 frv_fill_unused_units (GROUP_I);
8238 frv_fill_unused_units (GROUP_FM);
8242 /* Add an instruction with pattern NOP to frv_nops[]. */
8245 frv_register_nop (rtx nop)
8247 nop = make_insn_raw (nop);
8248 NEXT_INSN (nop) = 0;
8249 PREV_INSN (nop) = 0;
8250 frv_nops[frv_num_nops++] = nop;
8253 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8254 into packets and check whether we need to insert nops in order to
8255 fulfill the processor's issue requirements. Also, if the user has
8256 requested a certain alignment for a label, try to meet that alignment
8257 by inserting nops in the previous packet. */
8262 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8263 frv_optimize_membar ();
8266 frv_register_nop (gen_nop ());
8268 frv_register_nop (gen_mnop ());
8269 if (TARGET_HARD_FLOAT)
8270 frv_register_nop (gen_fnop ());
8272 /* Estimate the length of each branch. Although this may change after
8273 we've inserted nops, it will only do so in big functions. */
8274 shorten_branches (get_insns ());
8276 frv_packet_address = 0;
8277 frv_for_each_packet (frv_reorg_packet);
8280 #define def_builtin(name, type, code) \
8281 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8283 struct builtin_description
8285 enum insn_code icode;
8287 enum frv_builtins code;
8288 enum rtx_code comparison;
8292 /* Media intrinsics that take a single, constant argument. */
8294 static struct builtin_description bdesc_set[] =
8296 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, UNKNOWN, 0 }
8299 /* Media intrinsics that take just one argument. */
8301 static struct builtin_description bdesc_1arg[] =
8303 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, UNKNOWN, 0 },
8304 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, UNKNOWN, 0 },
8305 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, UNKNOWN, 0 },
8306 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, UNKNOWN, 0},
8307 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, UNKNOWN, 0 },
8308 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, UNKNOWN, 0 }
8311 /* Media intrinsics that take two arguments. */
8313 static struct builtin_description bdesc_2arg[] =
8315 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, UNKNOWN, 0},
8316 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, UNKNOWN, 0},
8317 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, UNKNOWN, 0},
8318 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, UNKNOWN, 0},
8319 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, UNKNOWN, 0},
8320 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, UNKNOWN, 0},
8321 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, UNKNOWN, 0},
8322 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, UNKNOWN, 0},
8323 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, UNKNOWN, 0},
8324 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, UNKNOWN, 0},
8325 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, UNKNOWN, 0},
8326 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, UNKNOWN, 0},
8327 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, UNKNOWN, 0},
8328 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, UNKNOWN, 0},
8329 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, UNKNOWN, 0},
8330 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, UNKNOWN, 0},
8331 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, UNKNOWN, 0},
8332 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, UNKNOWN, 0},
8333 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, UNKNOWN, 0},
8334 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, UNKNOWN, 0},
8335 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, UNKNOWN, 0},
8336 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, UNKNOWN, 0},
8337 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, UNKNOWN, 0},
8338 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, UNKNOWN, 0},
8339 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, UNKNOWN, 0},
8340 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, UNKNOWN, 0},
8341 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, UNKNOWN, 0}
8344 /* Integer intrinsics that take two arguments and have no return value. */
8346 static struct builtin_description bdesc_int_void2arg[] =
8348 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, UNKNOWN, 0},
8349 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, UNKNOWN, 0},
8350 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, UNKNOWN, 0}
8353 static struct builtin_description bdesc_prefetches[] =
8355 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, UNKNOWN,
8357 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, UNKNOWN, 0}
8360 /* Media intrinsics that take two arguments, the first being an ACC number. */
8362 static struct builtin_description bdesc_cut[] =
8364 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, UNKNOWN, 0},
8365 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, UNKNOWN, 0},
8366 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, UNKNOWN, 0}
8369 /* Two-argument media intrinsics with an immediate second argument. */
8371 static struct builtin_description bdesc_2argimm[] =
8373 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, UNKNOWN, 0},
8374 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, UNKNOWN, 0},
8375 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, UNKNOWN, 0},
8376 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, UNKNOWN, 0},
8377 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, UNKNOWN, 0},
8378 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, UNKNOWN, 0},
8379 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, UNKNOWN, 0},
8380 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, UNKNOWN, 0},
8381 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, UNKNOWN, 0},
8382 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, UNKNOWN, 0},
8383 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, UNKNOWN, 0},
8384 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, UNKNOWN, 0},
8385 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, UNKNOWN, 0},
8386 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, UNKNOWN, 0},
8387 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, UNKNOWN, 0},
8388 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, UNKNOWN, 0},
8389 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, UNKNOWN, 0}
8392 /* Media intrinsics that take two arguments and return void, the first argument
8393 being a pointer to 4 words in memory. */
8395 static struct builtin_description bdesc_void2arg[] =
8397 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, UNKNOWN, 0},
8398 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, UNKNOWN, 0},
8401 /* Media intrinsics that take three arguments, the first being a const_int that
8402 denotes an accumulator, and that return void. */
8404 static struct builtin_description bdesc_void3arg[] =
8406 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, UNKNOWN, 0},
8407 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, UNKNOWN, 0},
8408 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, UNKNOWN, 0},
8409 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, UNKNOWN, 0},
8410 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, UNKNOWN, 0},
8411 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, UNKNOWN, 0},
8412 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, UNKNOWN, 0},
8413 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, UNKNOWN, 0},
8414 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, UNKNOWN, 0},
8415 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, UNKNOWN, 0},
8416 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, UNKNOWN, 0},
8417 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, UNKNOWN, 0},
8418 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, UNKNOWN, 0},
8419 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, UNKNOWN, 0},
8420 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, UNKNOWN, 0},
8421 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, UNKNOWN, 0},
8422 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, UNKNOWN, 0},
8423 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, UNKNOWN, 0},
8424 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, UNKNOWN, 0},
8425 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, UNKNOWN, 0},
8426 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, UNKNOWN, 0},
8427 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, UNKNOWN, 0},
8428 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, UNKNOWN, 0},
8429 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, UNKNOWN, 0},
8430 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, UNKNOWN, 0}
8433 /* Media intrinsics that take two accumulator numbers as argument and
8436 static struct builtin_description bdesc_voidacc[] =
8438 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, UNKNOWN, 0},
8439 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, UNKNOWN, 0},
8440 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, UNKNOWN, 0},
8441 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, UNKNOWN, 0},
8442 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, UNKNOWN, 0},
8443 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, UNKNOWN, 0}
8446 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8447 a normal move and the ICODE is for the membar. */
8449 static struct builtin_description bdesc_loads[] =
8451 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8452 FRV_BUILTIN_READ8, UNKNOWN, 0},
8453 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8454 FRV_BUILTIN_READ16, UNKNOWN, 0},
8455 { CODE_FOR_optional_membar_si, "__builtin_read32",
8456 FRV_BUILTIN_READ32, UNKNOWN, 0},
8457 { CODE_FOR_optional_membar_di, "__builtin_read64",
8458 FRV_BUILTIN_READ64, UNKNOWN, 0}
8461 /* Likewise stores. */
8463 static struct builtin_description bdesc_stores[] =
8465 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8466 FRV_BUILTIN_WRITE8, UNKNOWN, 0},
8467 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8468 FRV_BUILTIN_WRITE16, UNKNOWN, 0},
8469 { CODE_FOR_optional_membar_si, "__builtin_write32",
8470 FRV_BUILTIN_WRITE32, UNKNOWN, 0},
8471 { CODE_FOR_optional_membar_di, "__builtin_write64",
8472 FRV_BUILTIN_WRITE64, UNKNOWN, 0},
8475 /* Initialize media builtins. */
8478 frv_init_builtins (void)
8480 tree endlink = void_list_node;
8481 tree accumulator = integer_type_node;
8482 tree integer = integer_type_node;
8483 tree voidt = void_type_node;
8484 tree uhalf = short_unsigned_type_node;
8485 tree sword1 = long_integer_type_node;
8486 tree uword1 = long_unsigned_type_node;
8487 tree sword2 = long_long_integer_type_node;
8488 tree uword2 = long_long_unsigned_type_node;
8489 tree uword4 = build_pointer_type (uword1);
8490 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8491 tree ubyte = unsigned_char_type_node;
8492 tree iacc = integer_type_node;
8494 #define UNARY(RET, T1) \
8495 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8497 #define BINARY(RET, T1, T2) \
8498 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8499 tree_cons (NULL_TREE, T2, endlink)))
8501 #define TRINARY(RET, T1, T2, T3) \
8502 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8503 tree_cons (NULL_TREE, T2, \
8504 tree_cons (NULL_TREE, T3, endlink))))
8506 #define QUAD(RET, T1, T2, T3, T4) \
8507 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8508 tree_cons (NULL_TREE, T2, \
8509 tree_cons (NULL_TREE, T3, \
8510 tree_cons (NULL_TREE, T4, endlink)))))
8512 tree void_ftype_void = build_function_type (voidt, endlink);
8514 tree void_ftype_acc = UNARY (voidt, accumulator);
8515 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8516 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8517 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8518 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8519 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8520 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8521 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8522 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8524 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8525 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8526 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8527 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8528 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8529 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8530 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8531 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8532 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8533 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8534 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8536 tree sw1_ftype_int = UNARY (sword1, integer);
8537 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8538 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8540 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8541 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8542 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8543 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8544 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8545 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8547 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8548 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8549 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8550 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8551 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8552 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8553 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8554 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8555 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8556 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8557 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8558 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8559 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8560 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8561 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8562 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8563 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8565 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8566 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8567 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8568 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8569 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8570 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8571 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8572 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8573 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8574 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8575 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8576 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8577 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8578 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8579 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8580 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8581 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8582 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8583 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8584 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8585 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8586 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8587 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8588 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8589 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8590 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8591 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8592 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8593 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8594 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8595 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8596 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8597 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8598 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8599 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8600 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8601 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8602 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8603 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8604 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8605 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8606 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8607 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8608 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8609 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8610 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8611 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8612 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8613 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8614 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8615 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8616 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8617 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8618 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8619 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8620 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8621 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8622 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8623 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8624 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8625 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8626 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8627 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8628 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8629 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8630 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8631 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8632 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8633 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8634 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8635 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8636 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8637 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8638 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8639 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8640 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8641 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8642 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8643 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8644 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8645 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8646 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8647 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8648 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8649 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8650 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8651 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8652 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8653 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8654 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8655 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8656 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8657 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8658 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8659 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8660 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8661 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8662 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8663 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8664 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8665 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8666 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8667 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8668 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8669 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8670 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8671 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8672 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8674 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8675 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8676 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8677 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8685 /* Set the names for various arithmetic operations according to the
8688 frv_init_libfuncs (void)
8690 set_optab_libfunc (smod_optab, SImode, "__modi");
8691 set_optab_libfunc (umod_optab, SImode, "__umodi");
8693 set_optab_libfunc (add_optab, DImode, "__addll");
8694 set_optab_libfunc (sub_optab, DImode, "__subll");
8695 set_optab_libfunc (smul_optab, DImode, "__mulll");
8696 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8697 set_optab_libfunc (smod_optab, DImode, "__modll");
8698 set_optab_libfunc (umod_optab, DImode, "__umodll");
8699 set_optab_libfunc (and_optab, DImode, "__andll");
8700 set_optab_libfunc (ior_optab, DImode, "__orll");
8701 set_optab_libfunc (xor_optab, DImode, "__xorll");
8702 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8704 set_optab_libfunc (add_optab, SFmode, "__addf");
8705 set_optab_libfunc (sub_optab, SFmode, "__subf");
8706 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8707 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8709 set_optab_libfunc (add_optab, DFmode, "__addd");
8710 set_optab_libfunc (sub_optab, DFmode, "__subd");
8711 set_optab_libfunc (smul_optab, DFmode, "__muld");
8712 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8714 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8715 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8717 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8718 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8719 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8720 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8722 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8723 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8724 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8725 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8727 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8728 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8729 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8730 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8733 /* Convert an integer constant to an accumulator register. ICODE is the
8734 code of the target instruction, OPNUM is the number of the
8735 accumulator operand and OPVAL is the constant integer. Try both
8736 ACC and ACCG registers; only report an error if neither fit the
8740 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8745 /* ACCs and ACCGs are implicit global registers if media intrinsics
8746 are being used. We set up this lazily to avoid creating lots of
8747 unnecessary call_insn rtl in non-media code. */
8748 for (i = 0; i <= ACC_MASK; i++)
8749 if ((i & ACC_MASK) == i)
8750 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8752 if (GET_CODE (opval) != CONST_INT)
8754 error ("accumulator is not a constant integer");
8757 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8759 error ("accumulator number is out of bounds");
8763 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8764 ACC_FIRST + INTVAL (opval));
8765 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8766 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8768 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8770 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8776 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8779 static enum machine_mode
8780 frv_matching_accg_mode (enum machine_mode mode)
8798 /* Given that a __builtin_read or __builtin_write function is accessing
8799 address ADDRESS, return the value that should be used as operand 1
8803 frv_io_address_cookie (rtx address)
8805 return (GET_CODE (address) == CONST_INT
8806 ? GEN_INT (INTVAL (address) / 8 * 8)
8810 /* Return the accumulator guard that should be paired with accumulator
8811 register ACC. The mode of the returned register is in the same
8812 class as ACC, but is four times smaller. */
8815 frv_matching_accg_for_acc (rtx acc)
8817 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8818 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8821 /* Read the requested argument from the call EXP given by INDEX.
8822 Return the value as an rtx. */
8825 frv_read_argument (tree exp, unsigned int index)
8827 return expand_normal (CALL_EXPR_ARG (exp, index));
8830 /* Like frv_read_argument, but interpret the argument as the number
8831 of an IACC register and return a (reg:MODE ...) rtx for it. */
8834 frv_read_iacc_argument (enum machine_mode mode, tree call,
8840 op = frv_read_argument (call, index);
8841 if (GET_CODE (op) != CONST_INT
8843 || INTVAL (op) > IACC_LAST - IACC_FIRST
8844 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8846 error ("invalid IACC argument");
8850 /* IACCs are implicit global registers. We set up this lazily to
8851 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8853 regno = INTVAL (op) + IACC_FIRST;
8854 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8855 global_regs[regno + i] = 1;
8857 return gen_rtx_REG (mode, regno);
8860 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8861 The instruction should require a constant operand of some sort. The
8862 function prints an error if OPVAL is not valid. */
8865 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8867 if (GET_CODE (opval) != CONST_INT)
8869 error ("%qs expects a constant argument", insn_data[icode].name);
8872 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8874 error ("constant argument out of range for %qs", insn_data[icode].name);
8880 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8881 if it's not null, has the right mode, and satisfies operand 0's
8885 frv_legitimize_target (enum insn_code icode, rtx target)
8887 enum machine_mode mode = insn_data[icode].operand[0].mode;
8890 || GET_MODE (target) != mode
8891 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8892 return gen_reg_rtx (mode);
8897 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8898 check whether ARG satisfies the operand's constraints. If it doesn't,
8899 copy ARG to a temporary register and return that. Otherwise return ARG
8903 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8905 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8907 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8910 return copy_to_mode_reg (mode, arg);
8913 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8916 frv_volatile_memref (enum machine_mode mode, rtx arg)
8920 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8921 MEM_VOLATILE_P (mem) = 1;
8925 /* Expand builtins that take a single, constant argument. At the moment,
8926 only MHDSETS falls into this category. */
8929 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8932 rtx op0 = frv_read_argument (call, 0);
8934 if (! frv_check_constant_argument (icode, 1, op0))
8937 target = frv_legitimize_target (icode, target);
8938 pat = GEN_FCN (icode) (target, op0);
8946 /* Expand builtins that take one operand. */
8949 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8952 rtx op0 = frv_read_argument (call, 0);
8954 target = frv_legitimize_target (icode, target);
8955 op0 = frv_legitimize_argument (icode, 1, op0);
8956 pat = GEN_FCN (icode) (target, op0);
8964 /* Expand builtins that take two operands. */
8967 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8970 rtx op0 = frv_read_argument (call, 0);
8971 rtx op1 = frv_read_argument (call, 1);
8973 target = frv_legitimize_target (icode, target);
8974 op0 = frv_legitimize_argument (icode, 1, op0);
8975 op1 = frv_legitimize_argument (icode, 2, op1);
8976 pat = GEN_FCN (icode) (target, op0, op1);
8984 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8988 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8991 rtx op0 = frv_read_argument (call, 0);
8992 rtx op1 = frv_read_argument (call, 1);
8995 target = frv_legitimize_target (icode, target);
8996 op0 = frv_int_to_acc (icode, 1, op0);
9000 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9002 if (! frv_check_constant_argument (icode, 2, op1))
9006 op1 = frv_legitimize_argument (icode, 2, op1);
9008 op2 = frv_matching_accg_for_acc (op0);
9009 pat = GEN_FCN (icode) (target, op0, op1, op2);
9017 /* Expand builtins that take two operands and the second is immediate. */
9020 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
9023 rtx op0 = frv_read_argument (call, 0);
9024 rtx op1 = frv_read_argument (call, 1);
9026 if (! frv_check_constant_argument (icode, 2, op1))
9029 target = frv_legitimize_target (icode, target);
9030 op0 = frv_legitimize_argument (icode, 1, op0);
9031 pat = GEN_FCN (icode) (target, op0, op1);
9039 /* Expand builtins that take two operands, the first operand being a pointer to
9040 ints and return void. */
9043 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9046 rtx op0 = frv_read_argument (call, 0);
9047 rtx op1 = frv_read_argument (call, 1);
9048 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9051 if (GET_CODE (op0) != MEM)
9055 if (! offsettable_address_p (0, mode0, op0))
9057 reg = gen_reg_rtx (Pmode);
9058 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9061 op0 = gen_rtx_MEM (SImode, reg);
9064 addr = XEXP (op0, 0);
9065 if (! offsettable_address_p (0, mode0, addr))
9066 addr = copy_to_mode_reg (Pmode, op0);
9068 op0 = change_address (op0, V4SImode, addr);
9069 op1 = frv_legitimize_argument (icode, 1, op1);
9070 pat = GEN_FCN (icode) (op0, op1);
9078 /* Expand builtins that take two long operands and return void. */
9081 frv_expand_int_void2arg (enum insn_code icode, tree call)
9084 rtx op0 = frv_read_argument (call, 0);
9085 rtx op1 = frv_read_argument (call, 1);
9087 op0 = frv_legitimize_argument (icode, 1, op0);
9088 op1 = frv_legitimize_argument (icode, 1, op1);
9089 pat = GEN_FCN (icode) (op0, op1);
9097 /* Expand prefetch builtins. These take a single address as argument. */
9100 frv_expand_prefetches (enum insn_code icode, tree call)
9103 rtx op0 = frv_read_argument (call, 0);
9105 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9113 /* Expand builtins that take three operands and return void. The first
9114 argument must be a constant that describes a pair or quad accumulators. A
9115 fourth argument is created that is the accumulator guard register that
9116 corresponds to the accumulator. */
9119 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9122 rtx op0 = frv_read_argument (call, 0);
9123 rtx op1 = frv_read_argument (call, 1);
9124 rtx op2 = frv_read_argument (call, 2);
9127 op0 = frv_int_to_acc (icode, 0, op0);
9131 op1 = frv_legitimize_argument (icode, 1, op1);
9132 op2 = frv_legitimize_argument (icode, 2, op2);
9133 op3 = frv_matching_accg_for_acc (op0);
9134 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9142 /* Expand builtins that perform accumulator-to-accumulator operations.
9143 These builtins take two accumulator numbers as argument and return
9147 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9150 rtx op0 = frv_read_argument (call, 0);
9151 rtx op1 = frv_read_argument (call, 1);
9155 op0 = frv_int_to_acc (icode, 0, op0);
9159 op1 = frv_int_to_acc (icode, 1, op1);
9163 op2 = frv_matching_accg_for_acc (op0);
9164 op3 = frv_matching_accg_for_acc (op1);
9165 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9173 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9174 membar and TARGET_MODE is the mode that the loaded value should have. */
9177 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9178 tree call, rtx target)
9180 rtx op0 = frv_read_argument (call, 0);
9181 rtx cookie = frv_io_address_cookie (op0);
9183 if (target == 0 || !REG_P (target))
9184 target = gen_reg_rtx (target_mode);
9185 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9186 convert_move (target, op0, 1);
9187 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9188 cfun->machine->has_membar_p = 1;
9192 /* Likewise __builtin_write* functions. */
9195 frv_expand_store_builtin (enum insn_code icode, tree call)
9197 rtx op0 = frv_read_argument (call, 0);
9198 rtx op1 = frv_read_argument (call, 1);
9199 rtx cookie = frv_io_address_cookie (op0);
9201 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9202 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9203 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9204 cfun->machine->has_membar_p = 1;
9208 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9209 each argument forms one word of the two double-word input registers.
9210 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9211 to put the return value. */
9214 frv_expand_mdpackh_builtin (tree call, rtx target)
9216 enum insn_code icode = CODE_FOR_mdpackh;
9218 rtx arg1 = frv_read_argument (call, 0);
9219 rtx arg2 = frv_read_argument (call, 1);
9220 rtx arg3 = frv_read_argument (call, 2);
9221 rtx arg4 = frv_read_argument (call, 3);
9223 target = frv_legitimize_target (icode, target);
9224 op0 = gen_reg_rtx (DImode);
9225 op1 = gen_reg_rtx (DImode);
9227 /* The high half of each word is not explicitly initialized, so indicate
9228 that the input operands are not live before this point. */
9232 /* Move each argument into the low half of its associated input word. */
9233 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9234 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9235 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9236 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9238 pat = GEN_FCN (icode) (target, op0, op1);
9246 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9247 number as argument. */
9250 frv_expand_mclracc_builtin (tree call)
9252 enum insn_code icode = CODE_FOR_mclracc;
9254 rtx op0 = frv_read_argument (call, 0);
9256 op0 = frv_int_to_acc (icode, 0, op0);
9260 pat = GEN_FCN (icode) (op0);
9267 /* Expand builtins that take no arguments. */
9270 frv_expand_noargs_builtin (enum insn_code icode)
9272 rtx pat = GEN_FCN (icode) (const0_rtx);
9279 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9280 number or accumulator guard number as argument and return an SI integer. */
9283 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9286 rtx target = gen_reg_rtx (SImode);
9287 rtx op0 = frv_read_argument (call, 0);
9289 op0 = frv_int_to_acc (icode, 1, op0);
9293 pat = GEN_FCN (icode) (target, op0);
9301 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9302 accumulator guard as their first argument and an SImode value as their
9306 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9309 rtx op0 = frv_read_argument (call, 0);
9310 rtx op1 = frv_read_argument (call, 1);
9312 op0 = frv_int_to_acc (icode, 0, op0);
9316 op1 = frv_legitimize_argument (icode, 1, op1);
9317 pat = GEN_FCN (icode) (op0, op1);
9324 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9325 to move DImode values into and out of IACC0. */
9328 frv_split_iacc_move (rtx dest, rtx src)
9330 enum machine_mode inner;
9333 inner = GET_MODE (dest);
9334 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9335 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9336 simplify_gen_subreg (SImode, src, inner, i));
9339 /* Expand builtins. */
9342 frv_expand_builtin (tree exp,
9344 rtx subtarget ATTRIBUTE_UNUSED,
9345 enum machine_mode mode ATTRIBUTE_UNUSED,
9346 int ignore ATTRIBUTE_UNUSED)
9348 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9349 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9351 struct builtin_description *d;
9353 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9355 error ("media functions are not available unless -mmedia is used");
9361 case FRV_BUILTIN_MCOP1:
9362 case FRV_BUILTIN_MCOP2:
9363 case FRV_BUILTIN_MDUNPACKH:
9364 case FRV_BUILTIN_MBTOHE:
9365 if (! TARGET_MEDIA_REV1)
9367 error ("this media function is only available on the fr500");
9372 case FRV_BUILTIN_MQXMACHS:
9373 case FRV_BUILTIN_MQXMACXHS:
9374 case FRV_BUILTIN_MQMACXHS:
9375 case FRV_BUILTIN_MADDACCS:
9376 case FRV_BUILTIN_MSUBACCS:
9377 case FRV_BUILTIN_MASACCS:
9378 case FRV_BUILTIN_MDADDACCS:
9379 case FRV_BUILTIN_MDSUBACCS:
9380 case FRV_BUILTIN_MDASACCS:
9381 case FRV_BUILTIN_MABSHS:
9382 case FRV_BUILTIN_MDROTLI:
9383 case FRV_BUILTIN_MCPLHI:
9384 case FRV_BUILTIN_MCPLI:
9385 case FRV_BUILTIN_MDCUTSSI:
9386 case FRV_BUILTIN_MQSATHS:
9387 case FRV_BUILTIN_MHSETLOS:
9388 case FRV_BUILTIN_MHSETLOH:
9389 case FRV_BUILTIN_MHSETHIS:
9390 case FRV_BUILTIN_MHSETHIH:
9391 case FRV_BUILTIN_MHDSETS:
9392 case FRV_BUILTIN_MHDSETH:
9393 if (! TARGET_MEDIA_REV2)
9395 error ("this media function is only available on the fr400"
9401 case FRV_BUILTIN_SMASS:
9402 case FRV_BUILTIN_SMSSS:
9403 case FRV_BUILTIN_SMU:
9404 case FRV_BUILTIN_ADDSS:
9405 case FRV_BUILTIN_SUBSS:
9406 case FRV_BUILTIN_SLASS:
9407 case FRV_BUILTIN_SCUTSS:
9408 case FRV_BUILTIN_IACCreadll:
9409 case FRV_BUILTIN_IACCreadl:
9410 case FRV_BUILTIN_IACCsetll:
9411 case FRV_BUILTIN_IACCsetl:
9412 if (!TARGET_FR405_BUILTINS)
9414 error ("this builtin function is only available"
9415 " on the fr405 and fr450");
9420 case FRV_BUILTIN_PREFETCH:
9421 if (!TARGET_FR500_FR550_BUILTINS)
9423 error ("this builtin function is only available on the fr500"
9429 case FRV_BUILTIN_MQLCLRHS:
9430 case FRV_BUILTIN_MQLMTHS:
9431 case FRV_BUILTIN_MQSLLHI:
9432 case FRV_BUILTIN_MQSRAHI:
9433 if (!TARGET_MEDIA_FR450)
9435 error ("this builtin function is only available on the fr450");
9444 /* Expand unique builtins. */
9448 case FRV_BUILTIN_MTRAP:
9449 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9451 case FRV_BUILTIN_MCLRACC:
9452 return frv_expand_mclracc_builtin (exp);
9454 case FRV_BUILTIN_MCLRACCA:
9456 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9458 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9460 case FRV_BUILTIN_MRDACC:
9461 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9463 case FRV_BUILTIN_MRDACCG:
9464 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9466 case FRV_BUILTIN_MWTACC:
9467 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9469 case FRV_BUILTIN_MWTACCG:
9470 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9472 case FRV_BUILTIN_MDPACKH:
9473 return frv_expand_mdpackh_builtin (exp, target);
9475 case FRV_BUILTIN_IACCreadll:
9477 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9478 if (target == 0 || !REG_P (target))
9479 target = gen_reg_rtx (DImode);
9480 frv_split_iacc_move (target, src);
9484 case FRV_BUILTIN_IACCreadl:
9485 return frv_read_iacc_argument (SImode, exp, 0);
9487 case FRV_BUILTIN_IACCsetll:
9489 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9490 rtx src = frv_read_argument (exp, 1);
9491 frv_split_iacc_move (dest, force_reg (DImode, src));
9495 case FRV_BUILTIN_IACCsetl:
9497 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9498 rtx src = frv_read_argument (exp, 1);
9499 emit_move_insn (dest, force_reg (SImode, src));
9507 /* Expand groups of builtins. */
9509 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9510 if (d->code == fcode)
9511 return frv_expand_set_builtin (d->icode, exp, target);
9513 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9514 if (d->code == fcode)
9515 return frv_expand_unop_builtin (d->icode, exp, target);
9517 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9518 if (d->code == fcode)
9519 return frv_expand_binop_builtin (d->icode, exp, target);
9521 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9522 if (d->code == fcode)
9523 return frv_expand_cut_builtin (d->icode, exp, target);
9525 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9526 if (d->code == fcode)
9527 return frv_expand_binopimm_builtin (d->icode, exp, target);
9529 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9530 if (d->code == fcode)
9531 return frv_expand_voidbinop_builtin (d->icode, exp);
9533 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9534 if (d->code == fcode)
9535 return frv_expand_voidtriop_builtin (d->icode, exp);
9537 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9538 if (d->code == fcode)
9539 return frv_expand_voidaccop_builtin (d->icode, exp);
9541 for (i = 0, d = bdesc_int_void2arg;
9542 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9543 if (d->code == fcode)
9544 return frv_expand_int_void2arg (d->icode, exp);
9546 for (i = 0, d = bdesc_prefetches;
9547 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9548 if (d->code == fcode)
9549 return frv_expand_prefetches (d->icode, exp);
9551 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9552 if (d->code == fcode)
9553 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9556 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9557 if (d->code == fcode)
9558 return frv_expand_store_builtin (d->icode, exp);
9564 frv_in_small_data_p (const_tree decl)
9567 const_tree section_name;
9569 /* Don't apply the -G flag to internal compiler structures. We
9570 should leave such structures in the main data section, partly
9571 for efficiency and partly because the size of some of them
9572 (such as C++ typeinfos) is not known until later. */
9573 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9576 /* If we already know which section the decl should be in, see if
9577 it's a small data section. */
9578 section_name = DECL_SECTION_NAME (decl);
9581 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9582 if (frv_string_begins_with (section_name, ".sdata"))
9584 if (frv_string_begins_with (section_name, ".sbss"))
9589 size = int_size_in_bytes (TREE_TYPE (decl));
9590 if (size > 0 && size <= g_switch_value)
9597 frv_rtx_costs (rtx x,
9598 int code ATTRIBUTE_UNUSED,
9599 int outer_code ATTRIBUTE_UNUSED,
9601 bool speed ATTRIBUTE_UNUSED)
9603 if (outer_code == MEM)
9605 /* Don't differentiate between memory addresses. All the ones
9606 we accept have equal cost. */
9607 *total = COSTS_N_INSNS (0);
9614 /* Make 12-bit integers really cheap. */
9615 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9626 *total = COSTS_N_INSNS (2);
9640 if (GET_MODE (x) == SImode)
9641 *total = COSTS_N_INSNS (1);
9642 else if (GET_MODE (x) == DImode)
9643 *total = COSTS_N_INSNS (2);
9645 *total = COSTS_N_INSNS (3);
9649 if (GET_MODE (x) == SImode)
9650 *total = COSTS_N_INSNS (2);
9652 *total = COSTS_N_INSNS (6); /* guess */
9659 *total = COSTS_N_INSNS (18);
9663 *total = COSTS_N_INSNS (3);
9672 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9674 switch_to_section (ctors_section);
9675 assemble_align (POINTER_SIZE);
9678 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9683 assemble_integer_with_op ("\t.picptr\t", symbol);
9687 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9689 switch_to_section (dtors_section);
9690 assemble_align (POINTER_SIZE);
9693 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9698 assemble_integer_with_op ("\t.picptr\t", symbol);
9701 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9704 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9705 int incoming ATTRIBUTE_UNUSED)
9707 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9710 #define TLS_BIAS (2048 - 16)
9712 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9713 We need to emit DTP-relative relocations. */
9716 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9718 gcc_assert (size == 4);
9719 fputs ("\t.picptr\ttlsmoff(", file);
9720 /* We want the unbiased TLS offset, so add the bias to the
9721 expression, such that the implicit biasing cancels out. */
9722 output_addr_const (file, plus_constant (x, TLS_BIAS));