1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
268 static int frv_default_flags_for_cpu (void);
269 static int frv_string_begins_with (const_tree, const char *);
270 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
271 static void frv_print_operand (FILE *, rtx, int);
272 static void frv_print_operand_address (FILE *, rtx);
273 static bool frv_print_operand_punct_valid_p (unsigned char code);
274 static void frv_print_operand_memory_reference_reg
276 static void frv_print_operand_memory_reference (FILE *, rtx, int);
277 static int frv_print_operand_jump_hint (rtx);
278 static const char *comparison_string (enum rtx_code, rtx);
279 static rtx frv_function_value (const_tree, const_tree,
281 static rtx frv_libcall_value (enum machine_mode,
283 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
284 static rtx single_set_pattern (rtx);
285 static int frv_function_contains_far_jump (void);
286 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
290 static rtx frv_frame_offset_rtx (int);
291 static rtx frv_frame_mem (enum machine_mode, rtx, int);
292 static rtx frv_dwarf_store (rtx, int);
293 static void frv_frame_insn (rtx, rtx);
294 static void frv_frame_access (frv_frame_accessor_t*,
296 static void frv_frame_access_multi (frv_frame_accessor_t*,
298 static void frv_frame_access_standard_regs (enum frv_stack_op,
300 static struct machine_function *frv_init_machine_status (void);
301 static rtx frv_int_to_acc (enum insn_code, int, rtx);
302 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
303 static rtx frv_read_argument (tree, unsigned int);
304 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
305 static int frv_check_constant_argument (enum insn_code, int, rtx);
306 static rtx frv_legitimize_target (enum insn_code, rtx);
307 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
308 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
309 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
310 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
312 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
313 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
314 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
315 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
316 static rtx frv_expand_int_void2arg (enum insn_code, tree);
317 static rtx frv_expand_prefetches (enum insn_code, tree);
318 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
319 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
320 static rtx frv_expand_mclracc_builtin (tree);
321 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
322 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
323 static rtx frv_expand_noargs_builtin (enum insn_code);
324 static void frv_split_iacc_move (rtx, rtx);
325 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
326 static int frv_clear_registers_used (rtx *, void *);
327 static void frv_ifcvt_add_insn (rtx, rtx, int);
328 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
329 static rtx frv_ifcvt_load_value (rtx, rtx);
330 static int frv_acc_group_1 (rtx *, void *);
331 static unsigned int frv_insn_unit (rtx);
332 static bool frv_issues_to_branch_unit_p (rtx);
333 static int frv_cond_flags (rtx);
334 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
335 static int frv_registers_conflict_p_1 (rtx *, void *);
336 static bool frv_registers_conflict_p (rtx);
337 static void frv_registers_update_1 (rtx, const_rtx, void *);
338 static void frv_registers_update (rtx);
339 static void frv_start_packet (void);
340 static void frv_start_packet_block (void);
341 static void frv_finish_packet (void (*) (void));
342 static bool frv_pack_insn_p (rtx);
343 static void frv_add_insn_to_packet (rtx);
344 static void frv_insert_nop_in_packet (rtx);
345 static bool frv_for_each_packet (void (*) (void));
346 static bool frv_sort_insn_group_1 (enum frv_insn_group,
347 unsigned int, unsigned int,
348 unsigned int, unsigned int,
350 static int frv_compare_insns (const void *, const void *);
351 static void frv_sort_insn_group (enum frv_insn_group);
352 static void frv_reorder_packet (void);
353 static void frv_fill_unused_units (enum frv_insn_group);
354 static void frv_align_label (void);
355 static void frv_reorg_packet (void);
356 static void frv_register_nop (rtx);
357 static void frv_reorg (void);
358 static void frv_pack_insns (void);
359 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
360 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
361 static bool frv_assemble_integer (rtx, unsigned, int);
362 static void frv_init_builtins (void);
363 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
364 static void frv_init_libfuncs (void);
365 static bool frv_in_small_data_p (const_tree);
366 static void frv_asm_output_mi_thunk
367 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
368 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
371 static rtx frv_expand_builtin_saveregs (void);
372 static void frv_expand_builtin_va_start (tree, rtx);
373 static bool frv_rtx_costs (rtx, int, int, int*, bool);
374 static void frv_asm_out_constructor (rtx, int);
375 static void frv_asm_out_destructor (rtx, int);
376 static bool frv_function_symbol_referenced_p (rtx);
377 static bool frv_cannot_force_const_mem (rtx);
378 static const char *unspec_got_name (int);
379 static void frv_output_const_unspec (FILE *,
380 const struct frv_unspec *);
381 static bool frv_function_ok_for_sibcall (tree, tree);
382 static rtx frv_struct_value_rtx (tree, int);
383 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
384 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
386 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
388 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
390 secondary_reload_info *);
391 static bool frv_frame_pointer_required (void);
392 static bool frv_can_eliminate (const int, const int);
393 static void frv_trampoline_init (rtx, tree, rtx);
394 static bool frv_class_likely_spilled_p (reg_class_t);
396 /* Allow us to easily change the default for -malloc-cc. */
397 #ifndef DEFAULT_NO_ALLOC_CC
398 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
400 #define MASK_DEFAULT_ALLOC_CC 0
403 /* Initialize the GCC target structure. */
404 #undef TARGET_PRINT_OPERAND
405 #define TARGET_PRINT_OPERAND frv_print_operand
406 #undef TARGET_PRINT_OPERAND_ADDRESS
407 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
408 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
409 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
410 #undef TARGET_ASM_FUNCTION_PROLOGUE
411 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
412 #undef TARGET_ASM_FUNCTION_EPILOGUE
413 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
414 #undef TARGET_ASM_INTEGER
415 #define TARGET_ASM_INTEGER frv_assemble_integer
416 #undef TARGET_DEFAULT_TARGET_FLAGS
417 #define TARGET_DEFAULT_TARGET_FLAGS \
418 (MASK_DEFAULT_ALLOC_CC \
425 #undef TARGET_HANDLE_OPTION
426 #define TARGET_HANDLE_OPTION frv_handle_option
427 #undef TARGET_INIT_BUILTINS
428 #define TARGET_INIT_BUILTINS frv_init_builtins
429 #undef TARGET_EXPAND_BUILTIN
430 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
431 #undef TARGET_INIT_LIBFUNCS
432 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
433 #undef TARGET_IN_SMALL_DATA_P
434 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
435 #undef TARGET_RTX_COSTS
436 #define TARGET_RTX_COSTS frv_rtx_costs
437 #undef TARGET_ASM_CONSTRUCTOR
438 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
439 #undef TARGET_ASM_DESTRUCTOR
440 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
442 #undef TARGET_ASM_OUTPUT_MI_THUNK
443 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
444 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
445 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
447 #undef TARGET_SCHED_ISSUE_RATE
448 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
450 #undef TARGET_LEGITIMIZE_ADDRESS
451 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
453 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
454 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
455 #undef TARGET_CANNOT_FORCE_CONST_MEM
456 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
458 #undef TARGET_HAVE_TLS
459 #define TARGET_HAVE_TLS HAVE_AS_TLS
461 #undef TARGET_STRUCT_VALUE_RTX
462 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
463 #undef TARGET_MUST_PASS_IN_STACK
464 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
465 #undef TARGET_PASS_BY_REFERENCE
466 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
467 #undef TARGET_ARG_PARTIAL_BYTES
468 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
470 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
471 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
472 #undef TARGET_SETUP_INCOMING_VARARGS
473 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
474 #undef TARGET_MACHINE_DEPENDENT_REORG
475 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
477 #undef TARGET_EXPAND_BUILTIN_VA_START
478 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
481 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
482 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
485 #undef TARGET_CLASS_LIKELY_SPILLED_P
486 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
488 #undef TARGET_SECONDARY_RELOAD
489 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
491 #undef TARGET_LEGITIMATE_ADDRESS_P
492 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
494 #undef TARGET_FRAME_POINTER_REQUIRED
495 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
497 #undef TARGET_CAN_ELIMINATE
498 #define TARGET_CAN_ELIMINATE frv_can_eliminate
500 #undef TARGET_TRAMPOLINE_INIT
501 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
503 #undef TARGET_FUNCTION_VALUE
504 #define TARGET_FUNCTION_VALUE frv_function_value
505 #undef TARGET_LIBCALL_VALUE
506 #define TARGET_LIBCALL_VALUE frv_libcall_value
508 struct gcc_target targetm = TARGET_INITIALIZER;
510 #define FRV_SYMBOL_REF_TLS_P(RTX) \
511 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
514 /* Any function call that satisfies the machine-independent
515 requirements is eligible on FR-V. */
518 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
519 tree exp ATTRIBUTE_UNUSED)
524 /* Return true if SYMBOL is a small data symbol and relocation RELOC
525 can be used to access it directly in a load or store. */
527 static FRV_INLINE bool
528 frv_small_data_reloc_p (rtx symbol, int reloc)
530 return (GET_CODE (symbol) == SYMBOL_REF
531 && SYMBOL_REF_SMALL_P (symbol)
532 && (!TARGET_FDPIC || flag_pic == 1)
533 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
536 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
540 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
542 if (GET_CODE (x) == CONST)
546 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
548 unspec->offset += INTVAL (XEXP (x, 1));
551 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
553 unspec->symbol = XVECEXP (x, 0, 0);
554 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
556 if (unspec->offset == 0)
559 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
560 && unspec->offset > 0
561 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
568 /* Decide whether we can force certain constants to memory. If we
569 decide we can't, the caller should be able to cope with it in
572 We never allow constants to be forced into memory for TARGET_FDPIC.
573 This is necessary for several reasons:
575 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
576 target-independent code will try to force them into the constant
577 pool, thus leading to infinite recursion.
579 2. We can never introduce new constant pool references during reload.
580 Any such reference would require use of the pseudo FDPIC register.
582 3. We can't represent a constant added to a function pointer (which is
583 not the same as a pointer to a function+constant).
585 4. In many cases, it's more efficient to calculate the constant in-line. */
588 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
593 /* Implement TARGET_HANDLE_OPTION. */
596 frv_handle_option (size_t code, const char *arg, int value)
601 g_switch_value = value;
606 if (strcmp (arg, "simple") == 0)
607 frv_cpu_type = FRV_CPU_SIMPLE;
608 else if (strcmp (arg, "tomcat") == 0)
609 frv_cpu_type = FRV_CPU_TOMCAT;
610 else if (strcmp (arg, "fr550") == 0)
611 frv_cpu_type = FRV_CPU_FR550;
612 else if (strcmp (arg, "fr500") == 0)
613 frv_cpu_type = FRV_CPU_FR500;
614 else if (strcmp (arg, "fr450") == 0)
615 frv_cpu_type = FRV_CPU_FR450;
616 else if (strcmp (arg, "fr405") == 0)
617 frv_cpu_type = FRV_CPU_FR405;
618 else if (strcmp (arg, "fr400") == 0)
619 frv_cpu_type = FRV_CPU_FR400;
620 else if (strcmp (arg, "fr300") == 0)
621 frv_cpu_type = FRV_CPU_FR300;
622 else if (strcmp (arg, "frv") == 0)
623 frv_cpu_type = FRV_CPU_GENERIC;
634 frv_default_flags_for_cpu (void)
636 switch (frv_cpu_type)
638 case FRV_CPU_GENERIC:
639 return MASK_DEFAULT_FRV;
642 return MASK_DEFAULT_FR550;
646 return MASK_DEFAULT_FR500;
649 return MASK_DEFAULT_FR450;
653 return MASK_DEFAULT_FR400;
657 return MASK_DEFAULT_SIMPLE;
664 /* Sometimes certain combinations of command options do not make
665 sense on a particular target machine. You can define a macro
666 `OVERRIDE_OPTIONS' to take account of this. This macro, if
667 defined, is executed once just after all the command options have
670 Don't use this macro to turn on various extra optimizations for
671 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
674 frv_override_options (void)
679 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
681 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
682 linker about linking pic and non-pic code. */
685 if (!flag_pic) /* -fPIC */
688 if (! g_switch_set) /* -G0 */
695 /* A C expression whose value is a register class containing hard
696 register REGNO. In general there is more than one such class;
697 choose a class which is "minimal", meaning that no smaller class
698 also contains the register. */
700 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
702 enum reg_class rclass;
706 int gpr_reg = regno - GPR_FIRST;
708 if (gpr_reg == GR8_REG)
711 else if (gpr_reg == GR9_REG)
714 else if (gpr_reg == GR14_REG)
715 rclass = FDPIC_FPTR_REGS;
717 else if (gpr_reg == FDPIC_REGNO)
720 else if ((gpr_reg & 3) == 0)
723 else if ((gpr_reg & 1) == 0)
730 else if (FPR_P (regno))
732 int fpr_reg = regno - GPR_FIRST;
733 if ((fpr_reg & 3) == 0)
734 rclass = QUAD_FPR_REGS;
736 else if ((fpr_reg & 1) == 0)
743 else if (regno == LR_REGNO)
746 else if (regno == LCR_REGNO)
749 else if (ICC_P (regno))
752 else if (FCC_P (regno))
755 else if (ICR_P (regno))
758 else if (FCR_P (regno))
761 else if (ACC_P (regno))
763 int r = regno - ACC_FIRST;
765 rclass = QUAD_ACC_REGS;
766 else if ((r & 1) == 0)
767 rclass = EVEN_ACC_REGS;
772 else if (ACCG_P (regno))
778 regno_reg_class[regno] = rclass;
781 /* Check for small data option */
783 g_switch_value = SDATA_DEFAULT_SIZE;
785 /* A C expression which defines the machine-dependent operand
786 constraint letters for register classes. If CHAR is such a
787 letter, the value should be the register class corresponding to
788 it. Otherwise, the value should be `NO_REGS'. The register
789 letter `r', corresponding to class `GENERAL_REGS', will not be
790 passed to this macro; you do not need to handle it.
792 The following letters are unavailable, due to being used as
797 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
798 'Q', 'R', 'S', 'T', 'U'
800 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
802 for (i = 0; i < 256; i++)
803 reg_class_from_letter[i] = NO_REGS;
805 reg_class_from_letter['a'] = ACC_REGS;
806 reg_class_from_letter['b'] = EVEN_ACC_REGS;
807 reg_class_from_letter['c'] = CC_REGS;
808 reg_class_from_letter['d'] = GPR_REGS;
809 reg_class_from_letter['e'] = EVEN_REGS;
810 reg_class_from_letter['f'] = FPR_REGS;
811 reg_class_from_letter['h'] = FEVEN_REGS;
812 reg_class_from_letter['l'] = LR_REG;
813 reg_class_from_letter['q'] = QUAD_REGS;
814 reg_class_from_letter['t'] = ICC_REGS;
815 reg_class_from_letter['u'] = FCC_REGS;
816 reg_class_from_letter['v'] = ICR_REGS;
817 reg_class_from_letter['w'] = FCR_REGS;
818 reg_class_from_letter['x'] = QUAD_FPR_REGS;
819 reg_class_from_letter['y'] = LCR_REG;
820 reg_class_from_letter['z'] = SPR_REGS;
821 reg_class_from_letter['A'] = QUAD_ACC_REGS;
822 reg_class_from_letter['B'] = ACCG_REGS;
823 reg_class_from_letter['C'] = CR_REGS;
824 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
825 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
827 /* There is no single unaligned SI op for PIC code. Sometimes we
828 need to use ".4byte" and sometimes we need to use ".picptr".
829 See frv_assemble_integer for details. */
830 if (flag_pic || TARGET_FDPIC)
831 targetm.asm_out.unaligned_op.si = 0;
833 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
834 target_flags |= MASK_LINKED_FP;
836 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
837 target_flags |= MASK_OPTIMIZE_MEMBAR;
839 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
840 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
842 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
843 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
845 init_machine_status = frv_init_machine_status;
849 /* Some machines may desire to change what optimizations are performed for
850 various optimization levels. This macro, if defined, is executed once just
851 after the optimization level is determined and before the remainder of the
852 command options have been parsed. Values set in this macro are used as the
853 default values for the other command line options.
855 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
856 `-O' is specified, and 0 if neither is specified.
858 SIZE is nonzero if `-Os' is specified, 0 otherwise.
860 You should not use this macro to change options that are not
861 machine-specific. These should uniformly selected by the same optimization
862 level on all supported machines. Use this macro to enable machine-specific
865 *Do not examine `write_symbols' in this macro!* The debugging options are
866 *not supposed to alter the generated code. */
868 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
869 scheduling pass at the current time. */
871 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
875 #ifdef DISABLE_SCHED2
876 flag_schedule_insns_after_reload = 0;
885 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
888 frv_string_begins_with (const_tree name, const char *prefix)
890 const int prefix_len = strlen (prefix);
892 /* Remember: NAME's length includes the null terminator. */
893 return (TREE_STRING_LENGTH (name) > prefix_len
894 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
897 /* Zero or more C statements that may conditionally modify two variables
898 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
899 been initialized from the two preceding macros.
901 This is necessary in case the fixed or call-clobbered registers depend on
904 You need not define this macro if it has no work to do.
906 If the usage of an entire class of registers depends on the target flags,
907 you may indicate this to GCC by using this macro to modify `fixed_regs' and
908 `call_used_regs' to 1 for each of the registers in the classes which should
909 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
910 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
912 (However, if this class is not included in `GENERAL_REGS' and all of the
913 insn patterns whose constraints permit this class are controlled by target
914 switches, then GCC will automatically avoid using these registers when the
915 target switches are opposed to them.) */
918 frv_conditional_register_usage (void)
922 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
923 fixed_regs[i] = call_used_regs[i] = 1;
925 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
926 fixed_regs[i] = call_used_regs[i] = 1;
928 /* Reserve the registers used for conditional execution. At present, we need
929 1 ICC and 1 ICR register. */
930 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
931 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
935 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
936 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
937 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
938 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
942 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
943 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
946 /* If -fpic, SDA_BASE_REG is the PIC register. */
947 if (g_switch_value == 0 && !flag_pic)
948 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
951 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
957 * Compute the stack frame layout
960 * +---------------+-----------------------+-----------------------+
961 * |Register |type |caller-save/callee-save|
962 * +---------------+-----------------------+-----------------------+
963 * |GR0 |Zero register | - |
964 * |GR1 |Stack pointer(SP) | - |
965 * |GR2 |Frame pointer(FP) | - |
966 * |GR3 |Hidden parameter | caller save |
967 * |GR4-GR7 | - | caller save |
968 * |GR8-GR13 |Argument register | caller save |
969 * |GR14-GR15 | - | caller save |
970 * |GR16-GR31 | - | callee save |
971 * |GR32-GR47 | - | caller save |
972 * |GR48-GR63 | - | callee save |
973 * |FR0-FR15 | - | caller save |
974 * |FR16-FR31 | - | callee save |
975 * |FR32-FR47 | - | caller save |
976 * |FR48-FR63 | - | callee save |
977 * +---------------+-----------------------+-----------------------+
981 * SP-> |-----------------------------------|
983 * |-----------------------------------|
984 * | Register save area |
985 * |-----------------------------------|
986 * | Local variable save area |
987 * FP-> |-----------------------------------|
989 * |-----------------------------------|
990 * | Hidden parameter save area |
991 * |-----------------------------------|
992 * | Return address(LR) storage area |
993 * |-----------------------------------|
994 * | Padding for alignment |
995 * |-----------------------------------|
996 * | Register argument area |
997 * OLD SP-> |-----------------------------------|
999 * |-----------------------------------|
1002 * Argument area/Parameter area:
1004 * When a function is called, this area is used for argument transfer. When
1005 * the argument is set up by the caller function, this area is referred to as
1006 * the argument area. When the argument is referenced by the callee function,
1007 * this area is referred to as the parameter area. The area is allocated when
1008 * all arguments cannot be placed on the argument register at the time of
1009 * argument transfer.
1011 * Register save area:
1013 * This is a register save area that must be guaranteed for the caller
1014 * function. This area is not secured when the register save operation is not
1017 * Local variable save area:
1019 * This is the area for local variables and temporary variables.
1023 * This area stores the FP value of the caller function.
1025 * Hidden parameter save area:
1027 * This area stores the start address of the return value storage
1028 * area for a struct/union return function.
1029 * When a struct/union is used as the return value, the caller
1030 * function stores the return value storage area start address in
1031 * register GR3 and passes it to the caller function.
1032 * The callee function interprets the address stored in the GR3
1033 * as the return value storage area start address.
1034 * When register GR3 needs to be saved into memory, the callee
1035 * function saves it in the hidden parameter save area. This
1036 * area is not secured when the save operation is not needed.
1038 * Return address(LR) storage area:
1040 * This area saves the LR. The LR stores the address of a return to the caller
1041 * function for the purpose of function calling.
1043 * Argument register area:
1045 * This area saves the argument register. This area is not secured when the
1046 * save operation is not needed.
1050 * Arguments, the count of which equals the count of argument registers (6
1051 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1052 * function. When a struct/union return function is called, the return value
1053 * area address is stored in register GR3. Arguments not placed in the
1054 * argument registers will be stored in the stack argument area for transfer
1055 * purposes. When an 8-byte type argument is to be delivered using registers,
1056 * it is divided into two and placed in two registers for transfer. When
1057 * argument registers must be saved to memory, the callee function secures an
1058 * argument register save area in the stack. In this case, a continuous
1059 * argument register save area must be established in the parameter area. The
1060 * argument register save area must be allocated as needed to cover the size of
1061 * the argument register to be saved. If the function has a variable count of
1062 * arguments, it saves all argument registers in the argument register save
1065 * Argument Extension Format:
1067 * When an argument is to be stored in the stack, its type is converted to an
1068 * extended type in accordance with the individual argument type. The argument
1069 * is freed by the caller function after the return from the callee function is
1072 * +-----------------------+---------------+------------------------+
1073 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1074 * +-----------------------+---------------+------------------------+
1076 * |signed char |int | 4 |
1077 * |unsigned char |int | 4 |
1078 * |[signed] short int |int | 4 |
1079 * |unsigned short int |int | 4 |
1080 * |[signed] int |No extension | 4 |
1081 * |unsigned int |No extension | 4 |
1082 * |[signed] long int |No extension | 4 |
1083 * |unsigned long int |No extension | 4 |
1084 * |[signed] long long int |No extension | 8 |
1085 * |unsigned long long int |No extension | 8 |
1086 * |float |double | 8 |
1087 * |double |No extension | 8 |
1088 * |long double |No extension | 8 |
1089 * |pointer |No extension | 4 |
1090 * |struct/union |- | 4 (*1) |
1091 * +-----------------------+---------------+------------------------+
1093 * When a struct/union is to be delivered as an argument, the caller copies it
1094 * to the local variable area and delivers the address of that area.
1098 * +-------------------------------+----------------------+
1099 * |Return Value Type |Return Value Interface|
1100 * +-------------------------------+----------------------+
1102 * |[signed|unsigned] char |GR8 |
1103 * |[signed|unsigned] short int |GR8 |
1104 * |[signed|unsigned] int |GR8 |
1105 * |[signed|unsigned] long int |GR8 |
1107 * |[signed|unsigned] long long int|GR8 & GR9 |
1109 * |double |GR8 & GR9 |
1110 * |long double |GR8 & GR9 |
1111 * |struct/union |(*1) |
1112 * +-------------------------------+----------------------+
1114 * When a struct/union is used as the return value, the caller function stores
1115 * the start address of the return value storage area into GR3 and then passes
1116 * it to the callee function. The callee function interprets GR3 as the start
1117 * address of the return value storage area. When this address needs to be
1118 * saved in memory, the callee function secures the hidden parameter save area
1119 * and saves the address in that area.
1123 frv_stack_info (void)
1125 static frv_stack_t info, zero_info;
1126 frv_stack_t *info_ptr = &info;
1127 tree fndecl = current_function_decl;
1135 /* If we've already calculated the values and reload is complete,
1137 if (frv_stack_cache)
1138 return frv_stack_cache;
1140 /* Zero all fields. */
1143 /* Set up the register range information. */
1144 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1145 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1146 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1147 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1149 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1150 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1151 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1152 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1154 info_ptr->regs[STACK_REGS_LR].name = "lr";
1155 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1156 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1157 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1159 info_ptr->regs[STACK_REGS_CC].name = "cc";
1160 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1161 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1162 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1164 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1165 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1166 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1168 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1169 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1170 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1171 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1172 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1174 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1175 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1176 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1177 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1179 info_ptr->regs[STACK_REGS_FP].name = "fp";
1180 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1181 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1182 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1184 /* Determine if this is a stdarg function. If so, allocate space to store
1191 /* Find the last argument, and see if it is __builtin_va_alist. */
1192 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1194 next_arg = DECL_CHAIN (cur_arg);
1195 if (next_arg == (tree)0)
1197 if (DECL_NAME (cur_arg)
1198 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1206 /* Iterate over all of the register ranges. */
1207 for (range = 0; range < STACK_REGS_MAX; range++)
1209 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1210 int first = reg_ptr->first;
1211 int last = reg_ptr->last;
1213 int size_2words = 0;
1216 /* Calculate which registers need to be saved & save area size. */
1220 for (regno = first; regno <= last; regno++)
1222 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1223 || (crtl->calls_eh_return
1224 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1225 || (!TARGET_FDPIC && flag_pic
1226 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1228 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1229 size_1word += UNITS_PER_WORD;
1234 /* Calculate whether we need to create a frame after everything else
1235 has been processed. */
1240 if (df_regs_ever_live_p (LR_REGNO)
1242 /* This is set for __builtin_return_address, etc. */
1243 || cfun->machine->frame_needed
1244 || (TARGET_LINKED_FP && frame_pointer_needed)
1245 || (!TARGET_FDPIC && flag_pic
1246 && crtl->uses_pic_offset_table))
1248 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1249 size_1word += UNITS_PER_WORD;
1253 case STACK_REGS_STDARG:
1256 /* If this is a stdarg function with a non varardic
1257 argument split between registers and the stack,
1258 adjust the saved registers downward. */
1259 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1262 for (regno = first; regno <= last; regno++)
1264 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1265 size_1word += UNITS_PER_WORD;
1268 info_ptr->stdarg_size = size_1word;
1272 case STACK_REGS_STRUCT:
1273 if (cfun->returns_struct)
1275 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1276 size_1word += UNITS_PER_WORD;
1284 /* If this is a field, it only takes one word. */
1285 if (reg_ptr->field_p)
1286 size_1word = UNITS_PER_WORD;
1288 /* Determine which register pairs can be saved together. */
1289 else if (reg_ptr->dword_p && TARGET_DWORD)
1291 for (regno = first; regno < last; regno += 2)
1293 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1295 size_2words += 2 * UNITS_PER_WORD;
1296 size_1word -= 2 * UNITS_PER_WORD;
1297 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1298 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1303 reg_ptr->size_1word = size_1word;
1304 reg_ptr->size_2words = size_2words;
1306 if (! reg_ptr->special_p)
1308 info_ptr->regs_size_1word += size_1word;
1309 info_ptr->regs_size_2words += size_2words;
1314 /* Set up the sizes of each each field in the frame body, making the sizes
1315 of each be divisible by the size of a dword if dword operations might
1316 be used, or the size of a word otherwise. */
1317 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1319 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1320 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1321 + info_ptr->regs_size_1word,
1323 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1325 info_ptr->pretend_size = crtl->args.pretend_args_size;
1327 /* Work out the size of the frame, excluding the header. Both the frame
1328 body and register parameter area will be dword-aligned. */
1329 info_ptr->total_size
1330 = (ADDR_ALIGN (info_ptr->parameter_size
1331 + info_ptr->regs_size
1332 + info_ptr->vars_size,
1334 + ADDR_ALIGN (info_ptr->pretend_size
1335 + info_ptr->stdarg_size,
1336 2 * UNITS_PER_WORD));
1338 /* See if we need to create a frame at all, if so add header area. */
1339 if (info_ptr->total_size > 0
1340 || frame_pointer_needed
1341 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1342 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1344 offset = info_ptr->parameter_size;
1345 info_ptr->header_size = 4 * UNITS_PER_WORD;
1346 info_ptr->total_size += 4 * UNITS_PER_WORD;
1348 /* Calculate the offsets to save normal register pairs. */
1349 for (range = 0; range < STACK_REGS_MAX; range++)
1351 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1352 if (! reg_ptr->special_p)
1354 int first = reg_ptr->first;
1355 int last = reg_ptr->last;
1358 for (regno = first; regno <= last; regno++)
1359 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1360 && regno != FRAME_POINTER_REGNUM
1361 && (regno < FIRST_ARG_REGNUM
1362 || regno > LAST_ARG_REGNUM))
1364 info_ptr->reg_offset[regno] = offset;
1365 offset += 2 * UNITS_PER_WORD;
1370 /* Calculate the offsets to save normal single registers. */
1371 for (range = 0; range < STACK_REGS_MAX; range++)
1373 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1374 if (! reg_ptr->special_p)
1376 int first = reg_ptr->first;
1377 int last = reg_ptr->last;
1380 for (regno = first; regno <= last; regno++)
1381 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1382 && regno != FRAME_POINTER_REGNUM
1383 && (regno < FIRST_ARG_REGNUM
1384 || regno > LAST_ARG_REGNUM))
1386 info_ptr->reg_offset[regno] = offset;
1387 offset += UNITS_PER_WORD;
1392 /* Calculate the offset to save the local variables at. */
1393 offset = ADDR_ALIGN (offset, alignment);
1394 if (info_ptr->vars_size)
1396 info_ptr->vars_offset = offset;
1397 offset += info_ptr->vars_size;
1400 /* Align header to a dword-boundary. */
1401 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1403 /* Calculate the offsets in the fixed frame. */
1404 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1405 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1406 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1408 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1409 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1410 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1412 if (cfun->returns_struct)
1414 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1415 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1416 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1419 /* Calculate the offsets to store the arguments passed in registers
1420 for stdarg functions. The register pairs are first and the single
1421 register if any is last. The register save area starts on a
1423 if (info_ptr->stdarg_size)
1425 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1426 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1429 /* Skip the header. */
1430 offset += 4 * UNITS_PER_WORD;
1431 for (regno = first; regno <= last; regno++)
1433 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1435 info_ptr->reg_offset[regno] = offset;
1436 offset += 2 * UNITS_PER_WORD;
1438 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1440 info_ptr->reg_offset[regno] = offset;
1441 offset += UNITS_PER_WORD;
1447 if (reload_completed)
1448 frv_stack_cache = info_ptr;
1454 /* Print the information about the frv stack offsets, etc. when debugging. */
1457 frv_debug_stack (frv_stack_t *info)
1462 info = frv_stack_info ();
1464 fprintf (stderr, "\nStack information for function %s:\n",
1465 ((current_function_decl && DECL_NAME (current_function_decl))
1466 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1469 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1470 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1471 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1472 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1473 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1475 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1476 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1477 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1478 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1480 for (range = 0; range < STACK_REGS_MAX; range++)
1482 frv_stack_regs_t *regs = &(info->regs[range]);
1483 if ((regs->size_1word + regs->size_2words) > 0)
1485 int first = regs->first;
1486 int last = regs->last;
1489 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1490 regs->name, regs->size_1word + regs->size_2words,
1491 regs->size_1word, regs->size_2words);
1493 for (regno = first; regno <= last; regno++)
1495 if (info->save_p[regno] == REG_SAVE_1WORD)
1496 fprintf (stderr, " %s (%d)", reg_names[regno],
1497 info->reg_offset[regno]);
1499 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1500 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1501 reg_names[regno+1], info->reg_offset[regno]);
1504 fputc ('\n', stderr);
1514 /* Used during final to control the packing of insns. The value is
1515 1 if the current instruction should be packed with the next one,
1516 0 if it shouldn't or -1 if packing is disabled altogether. */
1518 static int frv_insn_packing_flag;
1520 /* True if the current function contains a far jump. */
1523 frv_function_contains_far_jump (void)
1525 rtx insn = get_insns ();
1527 && !(GET_CODE (insn) == JUMP_INSN
1528 /* Ignore tablejump patterns. */
1529 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1530 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1531 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1532 insn = NEXT_INSN (insn);
1533 return (insn != NULL);
1536 /* For the FRV, this function makes sure that a function with far jumps
1537 will return correctly. It also does the VLIW packing. */
1540 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1542 /* If no frame was created, check whether the function uses a call
1543 instruction to implement a far jump. If so, save the link in gr3 and
1544 replace all returns to LR with returns to GR3. GR3 is used because it
1545 is call-clobbered, because is not available to the register allocator,
1546 and because all functions that take a hidden argument pointer will have
1548 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1552 /* Just to check that the above comment is true. */
1553 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1555 /* Generate the instruction that saves the link register. */
1556 fprintf (file, "\tmovsg lr,gr3\n");
1558 /* Replace the LR with GR3 in *return_internal patterns. The insn
1559 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1560 simply emit a different assembly directive because bralr and jmpl
1561 execute in different units. */
1562 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1563 if (GET_CODE (insn) == JUMP_INSN)
1565 rtx pattern = PATTERN (insn);
1566 if (GET_CODE (pattern) == PARALLEL
1567 && XVECLEN (pattern, 0) >= 2
1568 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1569 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1571 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1572 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1573 SET_REGNO (address, GPR_FIRST + 3);
1580 /* Allow the garbage collector to free the nops created by frv_reorg. */
1581 memset (frv_nops, 0, sizeof (frv_nops));
1585 /* Return the next available temporary register in a given class. */
1588 frv_alloc_temp_reg (
1589 frv_tmp_reg_t *info, /* which registers are available */
1590 enum reg_class rclass, /* register class desired */
1591 enum machine_mode mode, /* mode to allocate register with */
1592 int mark_as_used, /* register not available after allocation */
1593 int no_abort) /* return NULL instead of aborting */
1595 int regno = info->next_reg[ (int)rclass ];
1596 int orig_regno = regno;
1597 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1602 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1603 && TEST_HARD_REG_BIT (info->regs, regno))
1606 if (++regno >= FIRST_PSEUDO_REGISTER)
1608 if (regno == orig_regno)
1610 gcc_assert (no_abort);
1615 nr = HARD_REGNO_NREGS (regno, mode);
1616 info->next_reg[ (int)rclass ] = regno + nr;
1619 for (i = 0; i < nr; i++)
1620 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1622 return gen_rtx_REG (mode, regno);
1626 /* Return an rtx with the value OFFSET, which will either be a register or a
1627 signed 12-bit integer. It can be used as the second operand in an "add"
1628 instruction, or as the index in a load or store.
1630 The function returns a constant rtx if OFFSET is small enough, otherwise
1631 it loads the constant into register OFFSET_REGNO and returns that. */
1633 frv_frame_offset_rtx (int offset)
1635 rtx offset_rtx = GEN_INT (offset);
1636 if (IN_RANGE_P (offset, -2048, 2047))
1640 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1641 if (IN_RANGE_P (offset, -32768, 32767))
1642 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1645 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1646 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1652 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1653 prologue and epilogue uses such expressions to access the stack. */
1655 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1657 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1659 frv_frame_offset_rtx (offset)));
1662 /* Generate a frame-related expression:
1664 (set REG (mem (plus (sp) (const_int OFFSET)))).
1666 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1667 instructions. Marking the expressions as frame-related is superfluous if
1668 the note contains just a single set. But if the note contains a PARALLEL
1669 or SEQUENCE that has several sets, each set must be individually marked
1670 as frame-related. */
1672 frv_dwarf_store (rtx reg, int offset)
1674 rtx set = gen_rtx_SET (VOIDmode,
1675 gen_rtx_MEM (GET_MODE (reg),
1676 plus_constant (stack_pointer_rtx,
1679 RTX_FRAME_RELATED_P (set) = 1;
1683 /* Emit a frame-related instruction whose pattern is PATTERN. The
1684 instruction is the last in a sequence that cumulatively performs the
1685 operation described by DWARF_PATTERN. The instruction is marked as
1686 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1689 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1691 rtx insn = emit_insn (pattern);
1692 RTX_FRAME_RELATED_P (insn) = 1;
1693 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1698 /* Emit instructions that transfer REG to or from the memory location (sp +
1699 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1700 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1701 function to store registers and only the epilogue uses it to load them.
1703 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1704 The generated instruction will use BASE as its base register. BASE may
1705 simply be the stack pointer, but if several accesses are being made to a
1706 region far away from the stack pointer, it may be more efficient to set
1707 up a temporary instead.
1709 Store instructions will be frame-related and will be annotated with the
1710 overall effect of the store. Load instructions will be followed by a
1711 (use) to prevent later optimizations from zapping them.
1713 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1714 as a temporary in such cases. */
1716 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1718 enum machine_mode mode = GET_MODE (reg);
1719 rtx mem = frv_frame_mem (mode,
1721 stack_offset - accessor->base_offset);
1723 if (accessor->op == FRV_LOAD)
1725 if (SPR_P (REGNO (reg)))
1727 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1728 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1729 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1733 /* We cannot use reg+reg addressing for DImode access. */
1735 && GET_CODE (XEXP (mem, 0)) == PLUS
1736 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1737 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1739 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1740 rtx insn = emit_move_insn (temp,
1741 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1742 XEXP (XEXP (mem, 0), 1)));
1743 mem = gen_rtx_MEM (DImode, temp);
1745 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1751 if (SPR_P (REGNO (reg)))
1753 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1754 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1755 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1756 frv_dwarf_store (reg, stack_offset));
1758 else if (mode == DImode)
1760 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1761 with a separate save for each register. */
1762 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1763 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1764 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1765 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1767 /* Also we cannot use reg+reg addressing. */
1768 if (GET_CODE (XEXP (mem, 0)) == PLUS
1769 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1770 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1772 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1773 rtx insn = emit_move_insn (temp,
1774 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1775 XEXP (XEXP (mem, 0), 1)));
1776 mem = gen_rtx_MEM (DImode, temp);
1779 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1780 gen_rtx_PARALLEL (VOIDmode,
1781 gen_rtvec (2, set1, set2)));
1784 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1785 frv_dwarf_store (reg, stack_offset));
1789 /* A function that uses frv_frame_access to transfer a group of registers to
1790 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1791 is the stack information generated by frv_stack_info, and REG_SET is the
1792 number of the register set to transfer. */
1794 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1798 frv_stack_regs_t *regs_info;
1801 regs_info = &info->regs[reg_set];
1802 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1803 if (info->save_p[regno])
1804 frv_frame_access (accessor,
1805 info->save_p[regno] == REG_SAVE_2WORDS
1806 ? gen_rtx_REG (DImode, regno)
1807 : gen_rtx_REG (SImode, regno),
1808 info->reg_offset[regno]);
1811 /* Save or restore callee-saved registers that are kept outside the frame
1812 header. The function saves the registers if OP is FRV_STORE and restores
1813 them if OP is FRV_LOAD. INFO is the stack information generated by
1816 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1818 frv_frame_accessor_t accessor;
1821 accessor.base = stack_pointer_rtx;
1822 accessor.base_offset = 0;
1823 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1824 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1825 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1829 /* Called after register allocation to add any instructions needed for the
1830 prologue. Using a prologue insn is favored compared to putting all of the
1831 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1832 it allows the scheduler to intermix instructions with the saves of
1833 the caller saved registers. In some cases, it might be necessary
1834 to emit a barrier instruction as the last insn to prevent such
1837 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1838 so that the debug info generation code can handle them properly. */
1840 frv_expand_prologue (void)
1842 frv_stack_t *info = frv_stack_info ();
1843 rtx sp = stack_pointer_rtx;
1844 rtx fp = frame_pointer_rtx;
1845 frv_frame_accessor_t accessor;
1847 if (TARGET_DEBUG_STACK)
1848 frv_debug_stack (info);
1850 if (info->total_size == 0)
1853 /* We're interested in three areas of the frame here:
1855 A: the register save area
1857 C: the header after B
1859 If the frame pointer isn't used, we'll have to set up A, B and C
1860 using the stack pointer. If the frame pointer is used, we'll access
1864 B: set up using sp or a temporary (see below)
1867 We set up B using the stack pointer if the frame is small enough.
1868 Otherwise, it's more efficient to copy the old stack pointer into a
1869 temporary and use that.
1871 Note that it's important to make sure the prologue and epilogue use the
1872 same registers to access A and C, since doing otherwise will confuse
1873 the aliasing code. */
1875 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1876 isn't used, the same method will serve for C. */
1877 accessor.op = FRV_STORE;
1878 if (frame_pointer_needed && info->total_size > 2048)
1882 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1883 accessor.base_offset = info->total_size;
1884 insn = emit_insn (gen_movsi (accessor.base, sp));
1888 accessor.base = stack_pointer_rtx;
1889 accessor.base_offset = 0;
1892 /* Allocate the stack space. */
1894 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1895 rtx dwarf_offset = GEN_INT (-info->total_size);
1897 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1900 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1903 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1904 and point the new one to that location. */
1905 if (frame_pointer_needed)
1907 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1909 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1910 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1912 rtx asm_src = plus_constant (accessor.base,
1913 fp_offset - accessor.base_offset);
1914 rtx dwarf_src = plus_constant (sp, fp_offset);
1916 /* Store the old frame pointer at (sp + FP_OFFSET). */
1917 frv_frame_access (&accessor, fp, fp_offset);
1919 /* Set up the new frame pointer. */
1920 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1921 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1923 /* Access region C from the frame pointer. */
1925 accessor.base_offset = fp_offset;
1928 /* Set up region C. */
1929 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1930 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1931 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1933 /* Set up region A. */
1934 frv_frame_access_standard_regs (FRV_STORE, info);
1936 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1937 scheduler from moving loads before the stores saving the registers. */
1938 if (info->stdarg_size > 0)
1939 emit_insn (gen_blockage ());
1941 /* Set up pic register/small data register for this function. */
1942 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1943 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1944 gen_rtx_REG (Pmode, LR_REGNO),
1945 gen_rtx_REG (SImode, OFFSET_REGNO)));
1949 /* Under frv, all of the work is done via frv_expand_epilogue, but
1950 this function provides a convenient place to do cleanup. */
1953 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1954 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1956 frv_stack_cache = (frv_stack_t *)0;
1958 /* Zap last used registers for conditional execution. */
1959 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1961 /* Release the bitmap of created insns. */
1962 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1966 /* Called after register allocation to add any instructions needed for the
1967 epilogue. Using an epilogue insn is favored compared to putting all of the
1968 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1969 it allows the scheduler to intermix instructions with the saves of
1970 the caller saved registers. In some cases, it might be necessary
1971 to emit a barrier instruction as the last insn to prevent such
1975 frv_expand_epilogue (bool emit_return)
1977 frv_stack_t *info = frv_stack_info ();
1978 rtx fp = frame_pointer_rtx;
1979 rtx sp = stack_pointer_rtx;
1983 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1985 /* Restore the stack pointer to its original value if alloca or the like
1987 if (! current_function_sp_is_unchanging)
1988 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1990 /* Restore the callee-saved registers that were used in this function. */
1991 frv_frame_access_standard_regs (FRV_LOAD, info);
1993 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1994 no return instruction should be emitted. */
1995 if (info->save_p[LR_REGNO])
2000 /* Use the same method to access the link register's slot as we did in
2001 the prologue. In other words, use the frame pointer if available,
2002 otherwise use the stack pointer.
2004 LR_OFFSET is the offset of the link register's slot from the start
2005 of the frame and MEM is a memory rtx for it. */
2006 lr_offset = info->reg_offset[LR_REGNO];
2007 if (frame_pointer_needed)
2008 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
2010 mem = frv_frame_mem (Pmode, sp, lr_offset);
2012 /* Load the old link register into a GPR. */
2013 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
2014 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
2017 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
2019 /* Restore the old frame pointer. Emit a USE afterwards to make sure
2020 the load is preserved. */
2021 if (frame_pointer_needed)
2023 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
2027 /* Deallocate the stack frame. */
2028 if (info->total_size != 0)
2030 rtx offset = frv_frame_offset_rtx (info->total_size);
2031 emit_insn (gen_stack_adjust (sp, sp, offset));
2034 /* If this function uses eh_return, add the final stack adjustment now. */
2035 if (crtl->calls_eh_return)
2036 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2039 emit_jump_insn (gen_epilogue_return (return_addr));
2042 rtx lr = return_addr;
2044 if (REGNO (return_addr) != LR_REGNO)
2046 lr = gen_rtx_REG (Pmode, LR_REGNO);
2047 emit_move_insn (lr, return_addr);
2055 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2058 frv_asm_output_mi_thunk (FILE *file,
2059 tree thunk_fndecl ATTRIBUTE_UNUSED,
2060 HOST_WIDE_INT delta,
2061 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2064 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2065 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2066 const char *name_jmp = reg_names[JUMP_REGNO];
2067 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2069 /* Do the add using an addi if possible. */
2070 if (IN_RANGE_P (delta, -2048, 2047))
2071 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2074 const char *const name_add = reg_names[TEMP_REGNO];
2075 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2076 parallel, delta, name_add);
2077 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2079 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2084 const char *name_pic = reg_names[FDPIC_REGNO];
2085 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2089 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2090 assemble_name (file, name_func);
2091 fprintf (file, "),%s\n", name_jmp);
2093 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2094 assemble_name (file, name_func);
2095 fprintf (file, "),%s\n", name_jmp);
2097 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2101 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2102 assemble_name (file, name_func);
2103 fprintf (file, "\t)), %s\n", name_jmp);
2108 fprintf (file, "\tsethi%s #hi(", parallel);
2109 assemble_name (file, name_func);
2110 fprintf (file, "),%s\n", name_jmp);
2112 fprintf (file, "\tsetlo #lo(");
2113 assemble_name (file, name_func);
2114 fprintf (file, "),%s\n", name_jmp);
2118 /* Use JUMP_REGNO as a temporary PIC register. */
2119 const char *name_lr = reg_names[LR_REGNO];
2120 const char *name_gppic = name_jmp;
2121 const char *name_tmp = reg_names[TEMP_REGNO];
2123 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2124 fprintf (file, "\tcall 1f\n");
2125 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2126 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2127 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2128 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2129 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2131 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2132 assemble_name (file, name_func);
2133 fprintf (file, "),%s\n", name_tmp);
2135 fprintf (file, "\tsetlo #gprello(");
2136 assemble_name (file, name_func);
2137 fprintf (file, "),%s\n", name_tmp);
2139 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2142 /* Jump to the function address. */
2143 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2148 /* On frv, create a frame whenever we need to create stack. */
2151 frv_frame_pointer_required (void)
2153 /* If we forgoing the usual linkage requirements, we only need
2154 a frame pointer if the stack pointer might change. */
2155 if (!TARGET_LINKED_FP)
2156 return !current_function_sp_is_unchanging;
2158 if (! current_function_is_leaf)
2161 if (get_frame_size () != 0)
2167 if (!current_function_sp_is_unchanging)
2170 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2176 if (cfun->machine->frame_needed)
2183 /* Worker function for TARGET_CAN_ELIMINATE. */
2186 frv_can_eliminate (const int from, const int to)
2188 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2189 ? ! frame_pointer_needed
2193 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2194 initial difference between the specified pair of registers. This macro must
2195 be defined if `ELIMINABLE_REGS' is defined. */
2197 /* See frv_stack_info for more details on the frv stack frame. */
2200 frv_initial_elimination_offset (int from, int to)
2202 frv_stack_t *info = frv_stack_info ();
2205 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2206 ret = info->total_size - info->pretend_size;
2208 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2209 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2211 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2212 ret = (info->total_size
2213 - info->reg_offset[FRAME_POINTER_REGNUM]
2214 - info->pretend_size);
2219 if (TARGET_DEBUG_STACK)
2220 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2221 reg_names [from], reg_names[to], ret);
2227 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2230 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2231 enum machine_mode mode,
2232 tree type ATTRIBUTE_UNUSED,
2236 if (TARGET_DEBUG_ARG)
2238 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2239 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2243 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2246 frv_expand_builtin_saveregs (void)
2248 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2250 if (TARGET_DEBUG_ARG)
2251 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2254 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2258 /* Expand __builtin_va_start to do the va_start macro. */
2261 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2264 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2266 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2267 GEN_INT (UNITS_PER_WORD * num));
2269 if (TARGET_DEBUG_ARG)
2271 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2272 crtl->args.info, num);
2274 debug_rtx (nextarg);
2277 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2278 fold_convert (TREE_TYPE (valist),
2279 make_tree (sizetype, nextarg)));
2280 TREE_SIDE_EFFECTS (t) = 1;
2282 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2286 /* Expand a block move operation, and return 1 if successful. Return 0
2287 if we should let the compiler generate normal code.
2289 operands[0] is the destination
2290 operands[1] is the source
2291 operands[2] is the length
2292 operands[3] is the alignment */
2294 /* Maximum number of loads to do before doing the stores */
2295 #ifndef MAX_MOVE_REG
2296 #define MAX_MOVE_REG 4
2299 /* Maximum number of total loads to do. */
2300 #ifndef TOTAL_MOVE_REG
2301 #define TOTAL_MOVE_REG 8
2305 frv_expand_block_move (rtx operands[])
2307 rtx orig_dest = operands[0];
2308 rtx orig_src = operands[1];
2309 rtx bytes_rtx = operands[2];
2310 rtx align_rtx = operands[3];
2311 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2324 rtx stores[MAX_MOVE_REG];
2326 enum machine_mode mode;
2328 /* If this is not a fixed size move, just call memcpy. */
2332 /* This should be a fixed size alignment. */
2333 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2335 align = INTVAL (align_rtx);
2337 /* Anything to move? */
2338 bytes = INTVAL (bytes_rtx);
2342 /* Don't support real large moves. */
2343 if (bytes > TOTAL_MOVE_REG*align)
2346 /* Move the address into scratch registers. */
2347 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2348 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2350 num_reg = offset = 0;
2351 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2353 /* Calculate the correct offset for src/dest. */
2357 dest_addr = dest_reg;
2361 src_addr = plus_constant (src_reg, offset);
2362 dest_addr = plus_constant (dest_reg, offset);
2365 /* Generate the appropriate load and store, saving the stores
2367 if (bytes >= 4 && align >= 4)
2369 else if (bytes >= 2 && align >= 2)
2374 move_bytes = GET_MODE_SIZE (mode);
2375 tmp_reg = gen_reg_rtx (mode);
2376 src_mem = change_address (orig_src, mode, src_addr);
2377 dest_mem = change_address (orig_dest, mode, dest_addr);
2378 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2379 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2381 if (num_reg >= MAX_MOVE_REG)
2383 for (i = 0; i < num_reg; i++)
2384 emit_insn (stores[i]);
2389 for (i = 0; i < num_reg; i++)
2390 emit_insn (stores[i]);
2396 /* Expand a block clear operation, and return 1 if successful. Return 0
2397 if we should let the compiler generate normal code.
2399 operands[0] is the destination
2400 operands[1] is the length
2401 operands[3] is the alignment */
2404 frv_expand_block_clear (rtx operands[])
2406 rtx orig_dest = operands[0];
2407 rtx bytes_rtx = operands[1];
2408 rtx align_rtx = operands[3];
2409 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2418 enum machine_mode mode;
2420 /* If this is not a fixed size move, just call memcpy. */
2424 /* This should be a fixed size alignment. */
2425 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2427 align = INTVAL (align_rtx);
2429 /* Anything to move? */
2430 bytes = INTVAL (bytes_rtx);
2434 /* Don't support real large clears. */
2435 if (bytes > TOTAL_MOVE_REG*align)
2438 /* Move the address into a scratch register. */
2439 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2441 num_reg = offset = 0;
2442 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2444 /* Calculate the correct offset for src/dest. */
2445 dest_addr = ((offset == 0)
2447 : plus_constant (dest_reg, offset));
2449 /* Generate the appropriate store of gr0. */
2450 if (bytes >= 4 && align >= 4)
2452 else if (bytes >= 2 && align >= 2)
2457 clear_bytes = GET_MODE_SIZE (mode);
2458 dest_mem = change_address (orig_dest, mode, dest_addr);
2459 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2466 /* The following variable is used to output modifiers of assembler
2467 code of the current output insn. */
2469 static rtx *frv_insn_operands;
2471 /* The following function is used to add assembler insn code suffix .p
2472 if it is necessary. */
2475 frv_asm_output_opcode (FILE *f, const char *ptr)
2479 if (frv_insn_packing_flag <= 0)
2482 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2485 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2486 || (*ptr >= 'A' && *ptr <= 'Z')))
2488 int letter = *ptr++;
2491 frv_print_operand (f, frv_insn_operands [c], letter);
2492 while ((c = *ptr) >= '0' && c <= '9')
2504 /* Set up the packing bit for the current output insn. Note that this
2505 function is not called for asm insns. */
2508 frv_final_prescan_insn (rtx insn, rtx *opvec,
2509 int noperands ATTRIBUTE_UNUSED)
2513 if (frv_insn_packing_flag >= 0)
2515 frv_insn_operands = opvec;
2516 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2518 else if (recog_memoized (insn) >= 0
2519 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2520 /* Packing optimizations have been disabled, but INSN can only
2521 be issued in M1. Insert an mnop in M0. */
2522 fprintf (asm_out_file, "\tmnop.p\n");
2528 /* A C expression whose value is RTL representing the address in a stack frame
2529 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2530 an RTL expression for the address of the stack frame itself.
2532 If you don't define this macro, the default is to return the value of
2533 FRAMEADDR--that is, the stack frame address is also the address of the stack
2534 word that points to the previous frame. */
2536 /* The default is correct, but we need to make sure the frame gets created. */
2538 frv_dynamic_chain_address (rtx frame)
2540 cfun->machine->frame_needed = 1;
2545 /* A C expression whose value is RTL representing the value of the return
2546 address for the frame COUNT steps up from the current frame, after the
2547 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2548 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2551 The value of the expression must always be the correct address when COUNT is
2552 zero, but may be `NULL_RTX' if there is not way to determine the return
2553 address of other frames. */
2556 frv_return_addr_rtx (int count, rtx frame)
2560 cfun->machine->frame_needed = 1;
2561 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2564 /* Given a memory reference MEMREF, interpret the referenced memory as
2565 an array of MODE values, and return a reference to the element
2566 specified by INDEX. Assume that any pre-modification implicit in
2567 MEMREF has already happened.
2569 MEMREF must be a legitimate operand for modes larger than SImode.
2570 frv_legitimate_address_p forbids register+register addresses, which
2571 this function cannot handle. */
2573 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2575 rtx base = XEXP (memref, 0);
2576 if (GET_CODE (base) == PRE_MODIFY)
2577 base = XEXP (base, 0);
2578 return change_address (memref, mode,
2579 plus_constant (base, index * GET_MODE_SIZE (mode)));
2583 /* Print a memory address as an operand to reference that memory location. */
2585 frv_print_operand_address (FILE * stream, rtx x)
2587 if (GET_CODE (x) == MEM)
2590 switch (GET_CODE (x))
2593 fputs (reg_names [ REGNO (x)], stream);
2597 fprintf (stream, "%ld", (long) INTVAL (x));
2601 assemble_name (stream, XSTR (x, 0));
2606 output_addr_const (stream, x);
2610 /* Poorly constructed asm statements can trigger this alternative.
2611 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2612 frv_print_operand_memory_reference (stream, x, 0);
2619 fatal_insn ("bad insn to frv_print_operand_address:", x);
2624 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2626 int regno = true_regnum (x);
2628 fputs (reg_names[regno], stream);
2630 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2633 /* Print a memory reference suitable for the ld/st instructions. */
2636 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2638 struct frv_unspec unspec;
2642 switch (GET_CODE (x))
2649 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2651 x1 = XEXP (XEXP (x, 1), 1);
2661 if (GET_CODE (x0) == CONST_INT)
2669 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2678 else if (GET_CODE (x1) != CONST_INT)
2679 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2682 fputs ("@(", stream);
2684 fputs (reg_names[GPR_R0], stream);
2685 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2686 frv_print_operand_memory_reference_reg (stream, x0);
2688 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2690 fputs (",", stream);
2692 fputs (reg_names [GPR_R0], stream);
2696 switch (GET_CODE (x1))
2700 frv_print_operand_memory_reference_reg (stream, x1);
2704 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2708 if (!frv_const_unspec_p (x1, &unspec))
2709 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2710 frv_output_const_unspec (stream, &unspec);
2714 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2718 fputs (")", stream);
2722 /* Return 2 for likely branches and 0 for non-likely branches */
2724 #define FRV_JUMP_LIKELY 2
2725 #define FRV_JUMP_NOT_LIKELY 0
2728 frv_print_operand_jump_hint (rtx insn)
2733 HOST_WIDE_INT prob = -1;
2734 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2736 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2738 /* Assume any non-conditional jump is likely. */
2739 if (! any_condjump_p (insn))
2740 ret = FRV_JUMP_LIKELY;
2744 labelref = condjump_label (insn);
2747 rtx label = XEXP (labelref, 0);
2748 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2753 note = find_reg_note (insn, REG_BR_PROB, 0);
2755 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2759 prob = INTVAL (XEXP (note, 0));
2760 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2762 : FRV_JUMP_NOT_LIKELY);
2774 case UNKNOWN: direction = "unknown jump direction"; break;
2775 case BACKWARD: direction = "jump backward"; break;
2776 case FORWARD: direction = "jump forward"; break;
2780 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2781 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2782 (long)INSN_UID (insn), direction, (long)prob,
2783 (long)REG_BR_PROB_BASE, ret);
2791 /* Return the comparison operator to use for CODE given that the ICC
2795 comparison_string (enum rtx_code code, rtx op0)
2797 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2800 default: output_operand_lossage ("bad condition code");
2801 case EQ: return "eq";
2802 case NE: return "ne";
2803 case LT: return is_nz_p ? "n" : "lt";
2804 case LE: return "le";
2805 case GT: return "gt";
2806 case GE: return is_nz_p ? "p" : "ge";
2807 case LTU: return is_nz_p ? "no" : "c";
2808 case LEU: return is_nz_p ? "eq" : "ls";
2809 case GTU: return is_nz_p ? "ne" : "hi";
2810 case GEU: return is_nz_p ? "ra" : "nc";
2814 /* Print an operand to an assembler instruction.
2816 `%' followed by a letter and a digit says to output an operand in an
2817 alternate fashion. Four letters have standard, built-in meanings
2818 described below. The hook `TARGET_PRINT_OPERAND' can define
2819 additional letters with nonstandard meanings.
2821 `%cDIGIT' can be used to substitute an operand that is a constant value
2822 without the syntax that normally indicates an immediate operand.
2824 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2827 `%aDIGIT' can be used to substitute an operand as if it were a memory
2828 reference, with the actual operand treated as the address. This may be
2829 useful when outputting a "load address" instruction, because often the
2830 assembler syntax for such an instruction requires you to write the operand
2831 as if it were a memory reference.
2833 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2835 `%=' outputs a number which is unique to each instruction in the entire
2836 compilation. This is useful for making local labels to be referred to more
2837 than once in a single template that generates multiple assembler
2840 `%' followed by a punctuation character specifies a substitution that
2841 does not use an operand. Only one case is standard: `%%' outputs a
2842 `%' into the assembler code. Other nonstandard cases can be defined
2843 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2844 punctuation characters are valid with the
2845 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2848 frv_print_operand (FILE * file, rtx x, int code)
2850 struct frv_unspec unspec;
2851 HOST_WIDE_INT value;
2854 if (code != 0 && !ISALPHA (code))
2857 else if (GET_CODE (x) == CONST_INT)
2860 else if (GET_CODE (x) == CONST_DOUBLE)
2862 if (GET_MODE (x) == SFmode)
2867 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2868 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2872 else if (GET_MODE (x) == VOIDmode)
2873 value = CONST_DOUBLE_LOW (x);
2876 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2887 fputs (reg_names[GPR_R0], file);
2891 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2895 /* Output small data area base register (gr16). */
2896 fputs (reg_names[SDA_BASE_REG], file);
2900 /* Output pic register (gr17). */
2901 fputs (reg_names[PIC_REGNO], file);
2905 /* Output the temporary integer CCR register. */
2906 fputs (reg_names[ICR_TEMP], file);
2910 /* Output the temporary integer CC register. */
2911 fputs (reg_names[ICC_TEMP], file);
2914 /* case 'a': print an address. */
2917 /* Print appropriate test for integer branch false operation. */
2918 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2919 XEXP (x, 0)), file);
2923 /* Print appropriate test for integer branch true operation. */
2924 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2928 /* Print 1 for a NE and 0 for an EQ to give the final argument
2929 for a conditional instruction. */
2930 if (GET_CODE (x) == NE)
2933 else if (GET_CODE (x) == EQ)
2937 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2941 /* Print appropriate test for floating point branch false operation. */
2942 switch (GET_CODE (x))
2945 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2947 case EQ: fputs ("ne", file); break;
2948 case NE: fputs ("eq", file); break;
2949 case LT: fputs ("uge", file); break;
2950 case LE: fputs ("ug", file); break;
2951 case GT: fputs ("ule", file); break;
2952 case GE: fputs ("ul", file); break;
2957 /* Print appropriate test for floating point branch true operation. */
2958 switch (GET_CODE (x))
2961 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2963 case EQ: fputs ("eq", file); break;
2964 case NE: fputs ("ne", file); break;
2965 case LT: fputs ("lt", file); break;
2966 case LE: fputs ("le", file); break;
2967 case GT: fputs ("gt", file); break;
2968 case GE: fputs ("ge", file); break;
2973 /* Print appropriate GOT function. */
2974 if (GET_CODE (x) != CONST_INT)
2975 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2976 fputs (unspec_got_name (INTVAL (x)), file);
2980 /* Print 'i' if the operand is a constant, or is a memory reference that
2982 if (GET_CODE (x) == MEM)
2983 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2984 ? XEXP (XEXP (x, 0), 1)
2986 else if (GET_CODE (x) == PLUS)
2989 switch (GET_CODE (x))
3003 /* For jump instructions, print 'i' if the operand is a constant or
3004 is an expression that adds a constant. */
3005 if (GET_CODE (x) == CONST_INT)
3010 if (GET_CODE (x) == CONST_INT
3011 || (GET_CODE (x) == PLUS
3012 && (GET_CODE (XEXP (x, 1)) == CONST_INT
3013 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
3019 /* Print the lower register of a double word register pair */
3020 if (GET_CODE (x) == REG)
3021 fputs (reg_names[ REGNO (x)+1 ], file);
3023 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
3026 /* case 'l': print a LABEL_REF. */
3030 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
3031 for the second word of double memory operations. */
3032 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3033 switch (GET_CODE (x))
3036 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3039 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3047 frv_print_operand_memory_reference (file, x, offset);
3053 /* Print the opcode of a command. */
3054 switch (GET_CODE (x))
3057 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3059 case PLUS: fputs ("add", file); break;
3060 case MINUS: fputs ("sub", file); break;
3061 case AND: fputs ("and", file); break;
3062 case IOR: fputs ("or", file); break;
3063 case XOR: fputs ("xor", file); break;
3064 case ASHIFT: fputs ("sll", file); break;
3065 case ASHIFTRT: fputs ("sra", file); break;
3066 case LSHIFTRT: fputs ("srl", file); break;
3070 /* case 'n': negate and print a constant int. */
3073 /* Print PIC label using operand as the number. */
3074 if (GET_CODE (x) != CONST_INT)
3075 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3077 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3081 /* Print 'u' if the operand is a update load/store. */
3082 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3087 /* If value is 0, print gr0, otherwise it must be a register. */
3088 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3089 fputs (reg_names[GPR_R0], file);
3091 else if (GET_CODE (x) == REG)
3092 fputs (reg_names [REGNO (x)], file);
3095 fatal_insn ("bad insn in frv_print_operand, z case", x);
3099 /* Print constant in hex. */
3100 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3102 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3109 if (GET_CODE (x) == REG)
3110 fputs (reg_names [REGNO (x)], file);
3112 else if (GET_CODE (x) == CONST_INT
3113 || GET_CODE (x) == CONST_DOUBLE)
3114 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3116 else if (frv_const_unspec_p (x, &unspec))
3117 frv_output_const_unspec (file, &unspec);
3119 else if (GET_CODE (x) == MEM)
3120 frv_print_operand_address (file, XEXP (x, 0));
3122 else if (CONSTANT_ADDRESS_P (x))
3123 frv_print_operand_address (file, x);
3126 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3131 fatal_insn ("frv_print_operand: unknown code", x);
3139 frv_print_operand_punct_valid_p (unsigned char code)
3141 return (code == '.' || code == '#' || code == '@' || code == '~'
3142 || code == '*' || code == '&');
3146 /* A C statement (sans semicolon) for initializing the variable CUM for the
3147 state at the beginning of the argument list. The variable has type
3148 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3149 of the function which will receive the args, or 0 if the args are to a
3150 compiler support library function. The value of INDIRECT is nonzero when
3151 processing an indirect call, for example a call through a function pointer.
3152 The value of INDIRECT is zero for a call to an explicitly named function, a
3153 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3154 arguments for the function being compiled.
3156 When processing a call to a compiler support library function, LIBNAME
3157 identifies which one. It is a `symbol_ref' rtx which contains the name of
3158 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3159 being processed. Thus, each time this macro is called, either LIBNAME or
3160 FNTYPE is nonzero, but never both of them at once. */
3163 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3169 *cum = FIRST_ARG_REGNUM;
3171 if (TARGET_DEBUG_ARG)
3173 fprintf (stderr, "\ninit_cumulative_args:");
3174 if (!fndecl && fntype)
3175 fputs (" indirect", stderr);
3178 fputs (" incoming", stderr);
3182 tree ret_type = TREE_TYPE (fntype);
3183 fprintf (stderr, " return=%s,",
3184 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3187 if (libname && GET_CODE (libname) == SYMBOL_REF)
3188 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3190 if (cfun->returns_struct)
3191 fprintf (stderr, " return-struct");
3193 putc ('\n', stderr);
3198 /* Return true if we should pass an argument on the stack rather than
3202 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3204 if (mode == BLKmode)
3208 return AGGREGATE_TYPE_P (type);
3211 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3212 argument with the specified mode and type. If it is not defined,
3213 `PARM_BOUNDARY' is used for all arguments. */
3216 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3217 tree type ATTRIBUTE_UNUSED)
3219 return BITS_PER_WORD;
3223 frv_function_arg (CUMULATIVE_ARGS *cum,
3224 enum machine_mode mode,
3225 tree type ATTRIBUTE_UNUSED,
3227 int incoming ATTRIBUTE_UNUSED)
3229 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3234 /* Return a marker for use in the call instruction. */
3235 if (xmode == VOIDmode)
3241 else if (arg_num <= LAST_ARG_REGNUM)
3243 ret = gen_rtx_REG (xmode, arg_num);
3244 debstr = reg_names[arg_num];
3253 if (TARGET_DEBUG_ARG)
3255 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3256 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3262 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3263 advance past an argument in the argument list. The values MODE, TYPE and
3264 NAMED describe that argument. Once this is done, the variable CUM is
3265 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3267 This macro need not do anything if the argument in question was passed on
3268 the stack. The compiler knows how to track the amount of stack space used
3269 for arguments without any special help. */
3272 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3273 enum machine_mode mode,
3274 tree type ATTRIBUTE_UNUSED,
3277 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3278 int bytes = GET_MODE_SIZE (xmode);
3279 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3282 *cum = arg_num + words;
3284 if (TARGET_DEBUG_ARG)
3286 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3287 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3291 /* A C expression for the number of words, at the beginning of an argument,
3292 must be put in registers. The value must be zero for arguments that are
3293 passed entirely in registers or that are entirely pushed on the stack.
3295 On some machines, certain arguments must be passed partially in registers
3296 and partially in memory. On these machines, typically the first N words of
3297 arguments are passed in registers, and the rest on the stack. If a
3298 multi-word argument (a `double' or a structure) crosses that boundary, its
3299 first few words must be passed in registers and the rest must be pushed.
3300 This macro tells the compiler when this occurs, and how many of the words
3301 should go in registers.
3303 `FUNCTION_ARG' for these arguments should return the first register to be
3304 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3305 the called function. */
3308 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3309 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3311 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3312 int bytes = GET_MODE_SIZE (xmode);
3313 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3317 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3318 ? LAST_ARG_REGNUM - arg_num + 1
3320 ret *= UNITS_PER_WORD;
3322 if (TARGET_DEBUG_ARG && ret)
3323 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3329 /* Implements TARGET_FUNCTION_VALUE. */
3332 frv_function_value (const_tree valtype,
3333 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3334 bool outgoing ATTRIBUTE_UNUSED)
3336 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3340 /* Implements TARGET_LIBCALL_VALUE. */
3343 frv_libcall_value (enum machine_mode mode,
3344 const_rtx fun ATTRIBUTE_UNUSED)
3346 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3350 /* Implements FUNCTION_VALUE_REGNO_P. */
3353 frv_function_value_regno_p (const unsigned int regno)
3355 return (regno == RETURN_VALUE_REGNUM);
3358 /* Return true if a register is ok to use as a base or index register. */
3360 static FRV_INLINE int
3361 frv_regno_ok_for_base_p (int regno, int strict_p)
3367 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3369 if (regno == ARG_POINTER_REGNUM)
3372 return (regno >= FIRST_PSEUDO_REGISTER);
3376 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3377 RTX) is a legitimate memory address on the target machine for a memory
3378 operand of mode MODE.
3380 It usually pays to define several simpler macros to serve as subroutines for
3381 this one. Otherwise it may be too complicated to understand.
3383 This macro must exist in two variants: a strict variant and a non-strict
3384 one. The strict variant is used in the reload pass. It must be defined so
3385 that any pseudo-register that has not been allocated a hard register is
3386 considered a memory reference. In contexts where some kind of register is
3387 required, a pseudo-register with no hard register must be rejected.
3389 The non-strict variant is used in other passes. It must be defined to
3390 accept all pseudo-registers in every context where some kind of register is
3393 Compiler source files that want to use the strict variant of this macro
3394 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3395 conditional to define the strict variant in that case and the non-strict
3398 Normally, constant addresses which are the sum of a `symbol_ref' and an
3399 integer are stored inside a `const' RTX to mark them as constant.
3400 Therefore, there is no need to recognize such sums specifically as
3401 legitimate addresses. Normally you would simply recognize any `const' as
3404 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3405 constant sums that are not marked with `const'. It assumes that a
3406 naked `plus' indicates indexing. If so, then you *must* reject such
3407 naked constant sums as illegitimate addresses, so that none of them
3408 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3411 frv_legitimate_address_p_1 (enum machine_mode mode,
3415 int allow_double_reg_p)
3419 HOST_WIDE_INT value;
3422 if (FRV_SYMBOL_REF_TLS_P (x))
3425 switch (GET_CODE (x))
3432 if (GET_CODE (x) != REG)
3438 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3444 if (GET_CODE (x0) != REG
3445 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3446 || GET_CODE (x1) != PLUS
3447 || ! rtx_equal_p (x0, XEXP (x1, 0))
3448 || GET_CODE (XEXP (x1, 1)) != REG
3449 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3456 /* 12-bit immediate */
3461 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3463 /* If we can't use load/store double operations, make sure we can
3464 address the second word. */
3465 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3466 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3475 if (GET_CODE (x0) == SUBREG)
3476 x0 = SUBREG_REG (x0);
3478 if (GET_CODE (x0) != REG)
3481 regno0 = REGNO (x0);
3482 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3485 switch (GET_CODE (x1))
3491 x1 = SUBREG_REG (x1);
3492 if (GET_CODE (x1) != REG)
3498 /* Do not allow reg+reg addressing for modes > 1 word if we
3499 can't depend on having move double instructions. */
3500 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3503 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3507 /* 12-bit immediate */
3512 value = INTVAL (x1);
3513 ret = IN_RANGE_P (value, -2048, 2047);
3515 /* If we can't use load/store double operations, make sure we can
3516 address the second word. */
3517 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3518 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3523 if (!condexec_p && got12_operand (x1, VOIDmode))
3531 if (TARGET_DEBUG_ADDR)
3533 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3534 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3535 (condexec_p) ? ", inside conditional code" : "");
3543 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3545 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3548 /* Given an ADDR, generate code to inline the PLT. */
3550 gen_inlined_tls_plt (rtx addr)
3553 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3556 dest = gen_reg_rtx (DImode);
3563 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3564 calll #gettlsoff(ADDR)@(gr8, gr0)
3566 emit_insn (gen_tls_lddi (dest, addr, picreg));
3573 sethi.p #gottlsdeschi(ADDR), gr8
3574 setlo #gottlsdesclo(ADDR), gr8
3575 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3576 calll #gettlsoff(ADDR)@(gr8, gr0)
3578 rtx reguse = gen_reg_rtx (Pmode);
3579 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3580 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3583 retval = gen_reg_rtx (Pmode);
3584 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3588 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3589 the destination address. */
3591 gen_tlsmoff (rtx addr, rtx reg)
3593 rtx dest = gen_reg_rtx (Pmode);
3597 /* sethi.p #tlsmoffhi(x), grA
3598 setlo #tlsmofflo(x), grA
3600 dest = gen_reg_rtx (Pmode);
3601 emit_insn (gen_tlsoff_hilo (dest, addr,
3602 GEN_INT (R_FRV_TLSMOFFHI)));
3603 dest = gen_rtx_PLUS (Pmode, dest, reg);
3607 /* addi grB, #tlsmoff12(x), grC
3609 ld/st @(grB, #tlsmoff12(x)), grC
3611 dest = gen_reg_rtx (Pmode);
3612 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3613 GEN_INT (R_FRV_TLSMOFF12)));
3618 /* Generate code for a TLS address. */
3620 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3622 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3623 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3627 case TLS_MODEL_INITIAL_EXEC:
3631 ldi @(gr15, #gottlsoff12(x)), gr5
3633 dest = gen_reg_rtx (Pmode);
3634 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3635 dest = gen_rtx_PLUS (Pmode, tp, dest);
3639 /* -fPIC or anything else.
3641 sethi.p #gottlsoffhi(x), gr14
3642 setlo #gottlsofflo(x), gr14
3643 ld #tlsoff(x)@(gr15, gr14), gr9
3645 rtx tmp = gen_reg_rtx (Pmode);
3646 dest = gen_reg_rtx (Pmode);
3647 emit_insn (gen_tlsoff_hilo (tmp, addr,
3648 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3650 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3651 dest = gen_rtx_PLUS (Pmode, tp, dest);
3654 case TLS_MODEL_LOCAL_DYNAMIC:
3658 if (TARGET_INLINE_PLT)
3659 retval = gen_inlined_tls_plt (GEN_INT (0));
3662 /* call #gettlsoff(0) */
3663 retval = gen_reg_rtx (Pmode);
3664 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3667 reg = gen_reg_rtx (Pmode);
3668 emit_insn (gen_rtx_SET (VOIDmode, reg,
3669 gen_rtx_PLUS (Pmode,
3672 dest = gen_tlsmoff (addr, reg);
3675 dest = gen_reg_rtx (Pmode);
3676 emit_insn (gen_tlsoff_hilo (dest, addr,
3677 GEN_INT (R_FRV_TLSMOFFHI)));
3678 dest = gen_rtx_PLUS (Pmode, dest, reg);
3682 case TLS_MODEL_LOCAL_EXEC:
3683 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3685 case TLS_MODEL_GLOBAL_DYNAMIC:
3689 if (TARGET_INLINE_PLT)
3690 retval = gen_inlined_tls_plt (addr);
3693 /* call #gettlsoff(x) */
3694 retval = gen_reg_rtx (Pmode);
3695 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3697 dest = gen_rtx_PLUS (Pmode, retval, tp);
3708 frv_legitimize_address (rtx x,
3709 rtx oldx ATTRIBUTE_UNUSED,
3710 enum machine_mode mode ATTRIBUTE_UNUSED)
3712 if (GET_CODE (x) == SYMBOL_REF)
3714 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3716 return frv_legitimize_tls_address (x, model);
3722 /* Test whether a local function descriptor is canonical, i.e.,
3723 whether we can use FUNCDESC_GOTOFF to compute the address of the
3727 frv_local_funcdesc_p (rtx fnx)
3730 enum symbol_visibility vis;
3733 if (! SYMBOL_REF_LOCAL_P (fnx))
3736 fn = SYMBOL_REF_DECL (fnx);
3741 vis = DECL_VISIBILITY (fn);
3743 if (vis == VISIBILITY_PROTECTED)
3744 /* Private function descriptors for protected functions are not
3745 canonical. Temporarily change the visibility to global. */
3746 vis = VISIBILITY_DEFAULT;
3747 else if (flag_shlib)
3748 /* If we're already compiling for a shared library (that, unlike
3749 executables, can't assume that the existence of a definition
3750 implies local binding), we can skip the re-testing. */
3753 ret = default_binds_local_p_1 (fn, flag_pic);
3755 DECL_VISIBILITY (fn) = vis;
3760 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3764 frv_gen_GPsym2reg (rtx dest, rtx src)
3766 tree gp = get_identifier ("_gp");
3767 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3769 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3773 unspec_got_name (int i)
3777 case R_FRV_GOT12: return "got12";
3778 case R_FRV_GOTHI: return "gothi";
3779 case R_FRV_GOTLO: return "gotlo";
3780 case R_FRV_FUNCDESC: return "funcdesc";
3781 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3782 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3783 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3784 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3785 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3786 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3787 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3788 case R_FRV_GOTOFF12: return "gotoff12";
3789 case R_FRV_GOTOFFHI: return "gotoffhi";
3790 case R_FRV_GOTOFFLO: return "gotofflo";
3791 case R_FRV_GPREL12: return "gprel12";
3792 case R_FRV_GPRELHI: return "gprelhi";
3793 case R_FRV_GPRELLO: return "gprello";
3794 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3795 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3796 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3797 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3798 case R_FRV_TLSMOFF12: return "tlsmoff12";
3799 case R_FRV_TLSDESCHI: return "tlsdeschi";
3800 case R_FRV_TLSDESCLO: return "tlsdesclo";
3801 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3802 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3803 default: gcc_unreachable ();
3807 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3808 is added inside the relocation operator. */
3811 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3813 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3814 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3815 fputs (")", stream);
3818 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3819 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3820 otherwise return ORIG_X. */
3823 frv_find_base_term (rtx x)
3825 struct frv_unspec unspec;
3827 if (frv_const_unspec_p (x, &unspec)
3828 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3829 return plus_constant (unspec.symbol, unspec.offset);
3834 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3835 the operand is used by a predicated instruction. */
3838 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3840 return ((GET_MODE (op) == mode || mode == VOIDmode)
3841 && GET_CODE (op) == MEM
3842 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3843 reload_completed, condexec_p, FALSE));
3847 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3849 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3850 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3856 rvrtx = operands[0];
3860 addr = XEXP (operands[0], 0);
3862 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3863 any calls that would involve a PLT, but can't tell, since we
3864 don't know whether an extern function is going to be provided by
3865 a separate translation unit or imported from a separate module.
3866 When compiling for shared libraries, if the function has default
3867 visibility, we assume it's overridable, so we inline the PLT, but
3868 for executables, we don't really have a way to make a good
3869 decision: a function is as likely to be imported from a shared
3870 library as it is to be defined in the executable itself. We
3871 assume executables will get global functions defined locally,
3872 whereas shared libraries will have them potentially overridden,
3873 so we only inline PLTs when compiling for shared libraries.
3875 In order to mark a function as local to a shared library, any
3876 non-default visibility attribute suffices. Unfortunately,
3877 there's no simple way to tag a function declaration as ``in a
3878 different module'', which we could then use to trigger PLT
3879 inlining on executables. There's -minline-plt, but it affects
3880 all external functions, so one would have to also mark function
3881 declarations available in the same module with non-default
3882 visibility, which is advantageous in itself. */
3883 if (GET_CODE (addr) == SYMBOL_REF
3884 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3888 dest = gen_reg_rtx (SImode);
3890 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3891 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3893 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3894 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3896 crtl->uses_pic_offset_table = TRUE;
3899 else if (GET_CODE (addr) == SYMBOL_REF)
3901 /* These are always either local, or handled through a local
3904 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3905 operands[2], picreg, lr);
3907 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3911 else if (! ldd_address_operand (addr, Pmode))
3912 addr = force_reg (Pmode, addr);
3914 picreg = gen_reg_rtx (DImode);
3915 emit_insn (gen_movdi_ldd (picreg, addr));
3917 if (sibcall && ret_value)
3918 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3920 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3922 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3924 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3928 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3929 process these separately from any offsets, such that we add any
3930 offsets to the function descriptor (the actual pointer), not to the
3931 function address. */
3934 frv_function_symbol_referenced_p (rtx x)
3940 if (GET_CODE (x) == SYMBOL_REF)
3941 return SYMBOL_REF_FUNCTION_P (x);
3943 length = GET_RTX_LENGTH (GET_CODE (x));
3944 format = GET_RTX_FORMAT (GET_CODE (x));
3946 for (j = 0; j < length; ++j)
3951 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3957 if (XVEC (x, j) != 0)
3960 for (k = 0; k < XVECLEN (x, j); ++k)
3961 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3967 /* Nothing to do. */
3975 /* Return true if the memory operand is one that can be conditionally
3979 condexec_memory_operand (rtx op, enum machine_mode mode)
3981 enum machine_mode op_mode = GET_MODE (op);
3984 if (mode != VOIDmode && op_mode != mode)
3999 if (GET_CODE (op) != MEM)
4002 addr = XEXP (op, 0);
4003 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
4006 /* Return true if the bare return instruction can be used outside of the
4007 epilog code. For frv, we only do it if there was no stack allocation. */
4010 direct_return_p (void)
4014 if (!reload_completed)
4017 info = frv_stack_info ();
4018 return (info->total_size == 0);
4023 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
4025 if (GET_CODE (src) == SYMBOL_REF)
4027 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
4029 src = frv_legitimize_tls_address (src, model);
4035 if (frv_emit_movsi (dest, src))
4044 if (!reload_in_progress
4045 && !reload_completed
4046 && !register_operand (dest, mode)
4047 && !reg_or_0_operand (src, mode))
4048 src = copy_to_mode_reg (mode, src);
4055 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4058 /* Emit code to handle a MOVSI, adding in the small data register or pic
4059 register if needed to load up addresses. Return TRUE if the appropriate
4060 instructions are emitted. */
4063 frv_emit_movsi (rtx dest, rtx src)
4065 int base_regno = -1;
4068 struct frv_unspec old_unspec;
4070 if (!reload_in_progress
4071 && !reload_completed
4072 && !register_operand (dest, SImode)
4073 && (!reg_or_0_operand (src, SImode)
4074 /* Virtual registers will almost always be replaced by an
4075 add instruction, so expose this to CSE by copying to
4076 an intermediate register. */
4077 || (GET_CODE (src) == REG
4078 && IN_RANGE_P (REGNO (src),
4079 FIRST_VIRTUAL_REGISTER,
4080 LAST_VIRTUAL_REGISTER))))
4082 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4086 /* Explicitly add in the PIC or small data register if needed. */
4087 switch (GET_CODE (src))
4096 /* Using GPREL12, we use a single GOT entry for all symbols
4097 in read-only sections, but trade sequences such as:
4099 sethi #gothi(label), gr#
4100 setlo #gotlo(label), gr#
4105 ld @(gr15,#got12(_gp)), gr#
4106 sethi #gprelhi(label), gr##
4107 setlo #gprello(label), gr##
4110 We may often be able to share gr# for multiple
4111 computations of GPREL addresses, and we may often fold
4112 the final add into the pair of registers of a load or
4113 store instruction, so it's often profitable. Even when
4114 optimizing for size, we're trading a GOT entry for an
4115 additional instruction, which trades GOT space
4116 (read-write) for code size (read-only, shareable), as
4117 long as the symbol is not used in more than two different
4120 With -fpie/-fpic, we'd be trading a single load for a
4121 sequence of 4 instructions, because the offset of the
4122 label can't be assumed to be addressable with 12 bits, so
4123 we don't do this. */
4124 if (TARGET_GPREL_RO)
4125 unspec = R_FRV_GPREL12;
4127 unspec = R_FRV_GOT12;
4130 base_regno = PIC_REGNO;
4135 if (frv_const_unspec_p (src, &old_unspec))
4138 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4141 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4142 emit_move_insn (dest, src);
4147 sym = XEXP (sym, 0);
4148 if (GET_CODE (sym) == PLUS
4149 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4150 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4151 sym = XEXP (sym, 0);
4152 if (GET_CODE (sym) == SYMBOL_REF)
4154 else if (GET_CODE (sym) == LABEL_REF)
4157 goto handle_whatever;
4165 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4169 src = frv_legitimize_tls_address (src, model);
4170 emit_move_insn (dest, src);
4174 if (SYMBOL_REF_FUNCTION_P (sym))
4176 if (frv_local_funcdesc_p (sym))
4177 unspec = R_FRV_FUNCDESC_GOTOFF12;
4179 unspec = R_FRV_FUNCDESC_GOT12;
4183 if (CONSTANT_POOL_ADDRESS_P (sym))
4184 switch (GET_CODE (get_pool_constant (sym)))
4191 unspec = R_FRV_GOTOFF12;
4196 if (TARGET_GPREL_RO)
4197 unspec = R_FRV_GPREL12;
4199 unspec = R_FRV_GOT12;
4202 else if (SYMBOL_REF_LOCAL_P (sym)
4203 && !SYMBOL_REF_EXTERNAL_P (sym)
4204 && SYMBOL_REF_DECL (sym)
4205 && (!DECL_P (SYMBOL_REF_DECL (sym))
4206 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4208 tree decl = SYMBOL_REF_DECL (sym);
4209 tree init = TREE_CODE (decl) == VAR_DECL
4210 ? DECL_INITIAL (decl)
4211 : TREE_CODE (decl) == CONSTRUCTOR
4214 bool named_section, readonly;
4216 if (init && init != error_mark_node)
4217 reloc = compute_reloc_for_constant (init);
4219 named_section = TREE_CODE (decl) == VAR_DECL
4220 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4221 readonly = decl_readonly_section (decl, reloc);
4224 unspec = R_FRV_GOT12;
4226 unspec = R_FRV_GOTOFF12;
4227 else if (readonly && TARGET_GPREL_RO)
4228 unspec = R_FRV_GPREL12;
4230 unspec = R_FRV_GOT12;
4233 unspec = R_FRV_GOT12;
4237 else if (SYMBOL_REF_SMALL_P (sym))
4238 base_regno = SDA_BASE_REG;
4241 base_regno = PIC_REGNO;
4246 if (base_regno >= 0)
4248 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4249 emit_insn (gen_symGOTOFF2reg (dest, src,
4250 gen_rtx_REG (Pmode, base_regno),
4251 GEN_INT (R_FRV_GPREL12)));
4253 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4254 gen_rtx_REG (Pmode, base_regno),
4255 GEN_INT (R_FRV_GPREL12)));
4256 if (base_regno == PIC_REGNO)
4257 crtl->uses_pic_offset_table = TRUE;
4265 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4266 new uses of it once reload has begun. */
4267 gcc_assert (!reload_in_progress && !reload_completed);
4271 case R_FRV_GOTOFF12:
4272 if (!frv_small_data_reloc_p (sym, unspec))
4273 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4276 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4279 if (!frv_small_data_reloc_p (sym, unspec))
4280 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4283 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4285 case R_FRV_FUNCDESC_GOTOFF12:
4287 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4290 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4294 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4297 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4301 crtl->uses_pic_offset_table = TRUE;
4310 /* Return a string to output a single word move. */
4313 output_move_single (rtx operands[], rtx insn)
4315 rtx dest = operands[0];
4316 rtx src = operands[1];
4318 if (GET_CODE (dest) == REG)
4320 int dest_regno = REGNO (dest);
4321 enum machine_mode mode = GET_MODE (dest);
4323 if (GPR_P (dest_regno))
4325 if (GET_CODE (src) == REG)
4327 /* gpr <- some sort of register */
4328 int src_regno = REGNO (src);
4330 if (GPR_P (src_regno))
4331 return "mov %1, %0";
4333 else if (FPR_P (src_regno))
4334 return "movfg %1, %0";
4336 else if (SPR_P (src_regno))
4337 return "movsg %1, %0";
4340 else if (GET_CODE (src) == MEM)
4349 return "ldsb%I1%U1 %M1,%0";
4352 return "ldsh%I1%U1 %M1,%0";
4356 return "ld%I1%U1 %M1, %0";
4360 else if (GET_CODE (src) == CONST_INT
4361 || GET_CODE (src) == CONST_DOUBLE)
4363 /* gpr <- integer/floating constant */
4364 HOST_WIDE_INT value;
4366 if (GET_CODE (src) == CONST_INT)
4367 value = INTVAL (src);
4369 else if (mode == SFmode)
4374 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4375 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4380 value = CONST_DOUBLE_LOW (src);
4382 if (IN_RANGE_P (value, -32768, 32767))
4383 return "setlos %1, %0";
4388 else if (GET_CODE (src) == SYMBOL_REF
4389 || GET_CODE (src) == LABEL_REF
4390 || GET_CODE (src) == CONST)
4396 else if (FPR_P (dest_regno))
4398 if (GET_CODE (src) == REG)
4400 /* fpr <- some sort of register */
4401 int src_regno = REGNO (src);
4403 if (GPR_P (src_regno))
4404 return "movgf %1, %0";
4406 else if (FPR_P (src_regno))
4408 if (TARGET_HARD_FLOAT)
4409 return "fmovs %1, %0";
4411 return "mor %1, %1, %0";
4415 else if (GET_CODE (src) == MEM)
4424 return "ldbf%I1%U1 %M1,%0";
4427 return "ldhf%I1%U1 %M1,%0";
4431 return "ldf%I1%U1 %M1, %0";
4435 else if (ZERO_P (src))
4436 return "movgf %., %0";
4439 else if (SPR_P (dest_regno))
4441 if (GET_CODE (src) == REG)
4443 /* spr <- some sort of register */
4444 int src_regno = REGNO (src);
4446 if (GPR_P (src_regno))
4447 return "movgs %1, %0";
4449 else if (ZERO_P (src))
4450 return "movgs %., %0";
4454 else if (GET_CODE (dest) == MEM)
4456 if (GET_CODE (src) == REG)
4458 int src_regno = REGNO (src);
4459 enum machine_mode mode = GET_MODE (dest);
4461 if (GPR_P (src_regno))
4469 return "stb%I0%U0 %1, %M0";
4472 return "sth%I0%U0 %1, %M0";
4476 return "st%I0%U0 %1, %M0";
4480 else if (FPR_P (src_regno))
4488 return "stbf%I0%U0 %1, %M0";
4491 return "sthf%I0%U0 %1, %M0";
4495 return "stf%I0%U0 %1, %M0";
4500 else if (ZERO_P (src))
4502 switch (GET_MODE (dest))
4508 return "stb%I0%U0 %., %M0";
4511 return "sth%I0%U0 %., %M0";
4515 return "st%I0%U0 %., %M0";
4520 fatal_insn ("bad output_move_single operand", insn);
4525 /* Return a string to output a double word move. */
4528 output_move_double (rtx operands[], rtx insn)
4530 rtx dest = operands[0];
4531 rtx src = operands[1];
4532 enum machine_mode mode = GET_MODE (dest);
4534 if (GET_CODE (dest) == REG)
4536 int dest_regno = REGNO (dest);
4538 if (GPR_P (dest_regno))
4540 if (GET_CODE (src) == REG)
4542 /* gpr <- some sort of register */
4543 int src_regno = REGNO (src);
4545 if (GPR_P (src_regno))
4548 else if (FPR_P (src_regno))
4550 if (((dest_regno - GPR_FIRST) & 1) == 0
4551 && ((src_regno - FPR_FIRST) & 1) == 0)
4552 return "movfgd %1, %0";
4558 else if (GET_CODE (src) == MEM)
4561 if (dbl_memory_one_insn_operand (src, mode))
4562 return "ldd%I1%U1 %M1, %0";
4567 else if (GET_CODE (src) == CONST_INT
4568 || GET_CODE (src) == CONST_DOUBLE)
4572 else if (FPR_P (dest_regno))
4574 if (GET_CODE (src) == REG)
4576 /* fpr <- some sort of register */
4577 int src_regno = REGNO (src);
4579 if (GPR_P (src_regno))
4581 if (((dest_regno - FPR_FIRST) & 1) == 0
4582 && ((src_regno - GPR_FIRST) & 1) == 0)
4583 return "movgfd %1, %0";
4588 else if (FPR_P (src_regno))
4591 && ((dest_regno - FPR_FIRST) & 1) == 0
4592 && ((src_regno - FPR_FIRST) & 1) == 0)
4593 return "fmovd %1, %0";
4599 else if (GET_CODE (src) == MEM)
4602 if (dbl_memory_one_insn_operand (src, mode))
4603 return "lddf%I1%U1 %M1, %0";
4608 else if (ZERO_P (src))
4613 else if (GET_CODE (dest) == MEM)
4615 if (GET_CODE (src) == REG)
4617 int src_regno = REGNO (src);
4619 if (GPR_P (src_regno))
4621 if (((src_regno - GPR_FIRST) & 1) == 0
4622 && dbl_memory_one_insn_operand (dest, mode))
4623 return "std%I0%U0 %1, %M0";
4628 if (FPR_P (src_regno))
4630 if (((src_regno - FPR_FIRST) & 1) == 0
4631 && dbl_memory_one_insn_operand (dest, mode))
4632 return "stdf%I0%U0 %1, %M0";
4638 else if (ZERO_P (src))
4640 if (dbl_memory_one_insn_operand (dest, mode))
4641 return "std%I0%U0 %., %M0";
4647 fatal_insn ("bad output_move_double operand", insn);
4652 /* Return a string to output a single word conditional move.
4653 Operand0 -- EQ/NE of ccr register and 0
4654 Operand1 -- CCR register
4655 Operand2 -- destination
4656 Operand3 -- source */
4659 output_condmove_single (rtx operands[], rtx insn)
4661 rtx dest = operands[2];
4662 rtx src = operands[3];
4664 if (GET_CODE (dest) == REG)
4666 int dest_regno = REGNO (dest);
4667 enum machine_mode mode = GET_MODE (dest);
4669 if (GPR_P (dest_regno))
4671 if (GET_CODE (src) == REG)
4673 /* gpr <- some sort of register */
4674 int src_regno = REGNO (src);
4676 if (GPR_P (src_regno))
4677 return "cmov %z3, %2, %1, %e0";
4679 else if (FPR_P (src_regno))
4680 return "cmovfg %3, %2, %1, %e0";
4683 else if (GET_CODE (src) == MEM)
4692 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4695 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4699 return "cld%I3%U3 %M3, %2, %1, %e0";
4703 else if (ZERO_P (src))
4704 return "cmov %., %2, %1, %e0";
4707 else if (FPR_P (dest_regno))
4709 if (GET_CODE (src) == REG)
4711 /* fpr <- some sort of register */
4712 int src_regno = REGNO (src);
4714 if (GPR_P (src_regno))
4715 return "cmovgf %3, %2, %1, %e0";
4717 else if (FPR_P (src_regno))
4719 if (TARGET_HARD_FLOAT)
4720 return "cfmovs %3,%2,%1,%e0";
4722 return "cmor %3, %3, %2, %1, %e0";
4726 else if (GET_CODE (src) == MEM)
4729 if (mode == SImode || mode == SFmode)
4730 return "cldf%I3%U3 %M3, %2, %1, %e0";
4733 else if (ZERO_P (src))
4734 return "cmovgf %., %2, %1, %e0";
4738 else if (GET_CODE (dest) == MEM)
4740 if (GET_CODE (src) == REG)
4742 int src_regno = REGNO (src);
4743 enum machine_mode mode = GET_MODE (dest);
4745 if (GPR_P (src_regno))
4753 return "cstb%I2%U2 %3, %M2, %1, %e0";
4756 return "csth%I2%U2 %3, %M2, %1, %e0";
4760 return "cst%I2%U2 %3, %M2, %1, %e0";
4764 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4765 return "cstf%I2%U2 %3, %M2, %1, %e0";
4768 else if (ZERO_P (src))
4770 enum machine_mode mode = GET_MODE (dest);
4777 return "cstb%I2%U2 %., %M2, %1, %e0";
4780 return "csth%I2%U2 %., %M2, %1, %e0";
4784 return "cst%I2%U2 %., %M2, %1, %e0";
4789 fatal_insn ("bad output_condmove_single operand", insn);
4794 /* Emit the appropriate code to do a comparison, returning the register the
4795 comparison was done it. */
4798 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4800 enum machine_mode cc_mode;
4803 /* Floating point doesn't have comparison against a constant. */
4804 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4805 op1 = force_reg (GET_MODE (op0), op1);
4807 /* Possibly disable using anything but a fixed register in order to work
4808 around cse moving comparisons past function calls. */
4809 cc_mode = SELECT_CC_MODE (test, op0, op1);
4810 cc_reg = ((TARGET_ALLOC_CC)
4811 ? gen_reg_rtx (cc_mode)
4812 : gen_rtx_REG (cc_mode,
4813 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4815 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4816 gen_rtx_COMPARE (cc_mode, op0, op1)));
4822 /* Emit code for a conditional branch.
4823 XXX: I originally wanted to add a clobber of a CCR register to use in
4824 conditional execution, but that confuses the rest of the compiler. */
4827 frv_emit_cond_branch (rtx operands[])
4832 enum rtx_code test = GET_CODE (operands[0]);
4833 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4834 enum machine_mode cc_mode = GET_MODE (cc_reg);
4836 /* Branches generate:
4838 (if_then_else (<test>, <cc_reg>, (const_int 0))
4839 (label_ref <branch_label>)
4841 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4842 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4843 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4844 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4849 /* Emit code to set a gpr to 1/0 based on a comparison. */
4852 frv_emit_scc (rtx operands[])
4858 enum rtx_code test = GET_CODE (operands[1]);
4859 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4861 /* SCC instructions generate:
4862 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4863 (clobber (<ccr_reg>))]) */
4864 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4865 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4867 cr_reg = ((TARGET_ALLOC_CC)
4868 ? gen_reg_rtx (CC_CCRmode)
4869 : gen_rtx_REG (CC_CCRmode,
4870 ((GET_MODE (cc_reg) == CC_FPmode)
4874 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4875 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4880 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4881 the separate insns. */
4884 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4890 /* Set the appropriate CCR bit. */
4891 emit_insn (gen_rtx_SET (VOIDmode,
4893 gen_rtx_fmt_ee (GET_CODE (test),
4898 /* Move the value into the destination. */
4899 emit_move_insn (dest, GEN_INT (value));
4901 /* Move 0 into the destination if the test failed */
4902 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4903 gen_rtx_EQ (GET_MODE (cr_reg),
4906 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4908 /* Finish up, return sequence. */
4915 /* Emit the code for a conditional move, return TRUE if we could do the
4919 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4926 enum rtx_code test = GET_CODE (test_rtx);
4927 rtx cc_reg = frv_emit_comparison (test,
4928 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4929 enum machine_mode cc_mode = GET_MODE (cc_reg);
4931 /* Conditional move instructions generate:
4932 (parallel [(set <target>
4933 (if_then_else (<test> <cc_reg> (const_int 0))
4936 (clobber (<ccr_reg>))]) */
4938 /* Handle various cases of conditional move involving two constants. */
4939 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4941 HOST_WIDE_INT value1 = INTVAL (src1);
4942 HOST_WIDE_INT value2 = INTVAL (src2);
4944 /* Having 0 as one of the constants can be done by loading the other
4945 constant, and optionally moving in gr0. */
4946 if (value1 == 0 || value2 == 0)
4949 /* If the first value is within an addi range and also the difference
4950 between the two fits in an addi's range, load up the difference, then
4951 conditionally move in 0, and then unconditionally add the first
4953 else if (IN_RANGE_P (value1, -2048, 2047)
4954 && IN_RANGE_P (value2 - value1, -2048, 2047))
4957 /* If neither condition holds, just force the constant into a
4961 src1 = force_reg (GET_MODE (dest), src1);
4962 src2 = force_reg (GET_MODE (dest), src2);
4966 /* If one value is a register, insure the other value is either 0 or a
4970 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4971 src1 = force_reg (GET_MODE (dest), src1);
4973 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4974 src2 = force_reg (GET_MODE (dest), src2);
4977 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4978 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4980 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4982 cr_reg = ((TARGET_ALLOC_CC)
4983 ? gen_reg_rtx (CC_CCRmode)
4984 : gen_rtx_REG (CC_CCRmode,
4985 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4987 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4988 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4993 /* Split a conditional move into constituent parts, returning a SEQUENCE
4994 containing all of the insns. */
4997 frv_split_cond_move (rtx operands[])
4999 rtx dest = operands[0];
5000 rtx test = operands[1];
5001 rtx cc_reg = operands[2];
5002 rtx src1 = operands[3];
5003 rtx src2 = operands[4];
5004 rtx cr_reg = operands[5];
5006 enum machine_mode cr_mode = GET_MODE (cr_reg);
5010 /* Set the appropriate CCR bit. */
5011 emit_insn (gen_rtx_SET (VOIDmode,
5013 gen_rtx_fmt_ee (GET_CODE (test),
5018 /* Handle various cases of conditional move involving two constants. */
5019 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
5021 HOST_WIDE_INT value1 = INTVAL (src1);
5022 HOST_WIDE_INT value2 = INTVAL (src2);
5024 /* Having 0 as one of the constants can be done by loading the other
5025 constant, and optionally moving in gr0. */
5028 emit_move_insn (dest, src2);
5029 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5030 gen_rtx_NE (cr_mode, cr_reg,
5032 gen_rtx_SET (VOIDmode, dest, src1)));
5035 else if (value2 == 0)
5037 emit_move_insn (dest, src1);
5038 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5039 gen_rtx_EQ (cr_mode, cr_reg,
5041 gen_rtx_SET (VOIDmode, dest, src2)));
5044 /* If the first value is within an addi range and also the difference
5045 between the two fits in an addi's range, load up the difference, then
5046 conditionally move in 0, and then unconditionally add the first
5048 else if (IN_RANGE_P (value1, -2048, 2047)
5049 && IN_RANGE_P (value2 - value1, -2048, 2047))
5051 rtx dest_si = ((GET_MODE (dest) == SImode)
5053 : gen_rtx_SUBREG (SImode, dest, 0));
5055 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5056 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5057 gen_rtx_NE (cr_mode, cr_reg,
5059 gen_rtx_SET (VOIDmode, dest_si,
5061 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5069 /* Emit the conditional move for the test being true if needed. */
5070 if (! rtx_equal_p (dest, src1))
5071 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5072 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5073 gen_rtx_SET (VOIDmode, dest, src1)));
5075 /* Emit the conditional move for the test being false if needed. */
5076 if (! rtx_equal_p (dest, src2))
5077 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5078 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5079 gen_rtx_SET (VOIDmode, dest, src2)));
5082 /* Finish up, return sequence. */
5089 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5090 memory location that is not known to be dword-aligned. */
5092 frv_split_double_load (rtx dest, rtx source)
5094 int regno = REGNO (dest);
5095 rtx dest1 = gen_highpart (SImode, dest);
5096 rtx dest2 = gen_lowpart (SImode, dest);
5097 rtx address = XEXP (source, 0);
5099 /* If the address is pre-modified, load the lower-numbered register
5100 first, then load the other register using an integer offset from
5101 the modified base register. This order should always be safe,
5102 since the pre-modification cannot affect the same registers as the
5105 The situation for other loads is more complicated. Loading one
5106 of the registers could affect the value of ADDRESS, so we must
5107 be careful which order we do them in. */
5108 if (GET_CODE (address) == PRE_MODIFY
5109 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5111 /* It is safe to load the lower-numbered register first. */
5112 emit_move_insn (dest1, change_address (source, SImode, NULL));
5113 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5117 /* ADDRESS is not pre-modified and the address depends on the
5118 lower-numbered register. Load the higher-numbered register
5120 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5121 emit_move_insn (dest1, change_address (source, SImode, NULL));
5125 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5126 and SOURCE is either a double register or the constant zero. */
5128 frv_split_double_store (rtx dest, rtx source)
5130 rtx dest1 = change_address (dest, SImode, NULL);
5131 rtx dest2 = frv_index_memory (dest, SImode, 1);
5132 if (ZERO_P (source))
5134 emit_move_insn (dest1, CONST0_RTX (SImode));
5135 emit_move_insn (dest2, CONST0_RTX (SImode));
5139 emit_move_insn (dest1, gen_highpart (SImode, source));
5140 emit_move_insn (dest2, gen_lowpart (SImode, source));
5145 /* Split a min/max operation returning a SEQUENCE containing all of the
5149 frv_split_minmax (rtx operands[])
5151 rtx dest = operands[0];
5152 rtx minmax = operands[1];
5153 rtx src1 = operands[2];
5154 rtx src2 = operands[3];
5155 rtx cc_reg = operands[4];
5156 rtx cr_reg = operands[5];
5158 enum rtx_code test_code;
5159 enum machine_mode cr_mode = GET_MODE (cr_reg);
5163 /* Figure out which test to use. */
5164 switch (GET_CODE (minmax))
5169 case SMIN: test_code = LT; break;
5170 case SMAX: test_code = GT; break;
5171 case UMIN: test_code = LTU; break;
5172 case UMAX: test_code = GTU; break;
5175 /* Issue the compare instruction. */
5176 emit_insn (gen_rtx_SET (VOIDmode,
5178 gen_rtx_COMPARE (GET_MODE (cc_reg),
5181 /* Set the appropriate CCR bit. */
5182 emit_insn (gen_rtx_SET (VOIDmode,
5184 gen_rtx_fmt_ee (test_code,
5189 /* If are taking the min/max of a nonzero constant, load that first, and
5190 then do a conditional move of the other value. */
5191 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5193 gcc_assert (!rtx_equal_p (dest, src1));
5195 emit_move_insn (dest, src2);
5196 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5197 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5198 gen_rtx_SET (VOIDmode, dest, src1)));
5201 /* Otherwise, do each half of the move. */
5204 /* Emit the conditional move for the test being true if needed. */
5205 if (! rtx_equal_p (dest, src1))
5206 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5207 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5208 gen_rtx_SET (VOIDmode, dest, src1)));
5210 /* Emit the conditional move for the test being false if needed. */
5211 if (! rtx_equal_p (dest, src2))
5212 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5213 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5214 gen_rtx_SET (VOIDmode, dest, src2)));
5217 /* Finish up, return sequence. */
5224 /* Split an integer abs operation returning a SEQUENCE containing all of the
5228 frv_split_abs (rtx operands[])
5230 rtx dest = operands[0];
5231 rtx src = operands[1];
5232 rtx cc_reg = operands[2];
5233 rtx cr_reg = operands[3];
5238 /* Issue the compare < 0 instruction. */
5239 emit_insn (gen_rtx_SET (VOIDmode,
5241 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5243 /* Set the appropriate CCR bit. */
5244 emit_insn (gen_rtx_SET (VOIDmode,
5246 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5248 /* Emit the conditional negate if the value is negative. */
5249 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5250 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5251 gen_negsi2 (dest, src)));
5253 /* Emit the conditional move for the test being false if needed. */
5254 if (! rtx_equal_p (dest, src))
5255 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5256 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5257 gen_rtx_SET (VOIDmode, dest, src)));
5259 /* Finish up, return sequence. */
5266 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5267 register used in an insn. */
5270 frv_clear_registers_used (rtx *ptr, void *data)
5272 if (GET_CODE (*ptr) == REG)
5274 int regno = REGNO (*ptr);
5275 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5277 if (regno < FIRST_PSEUDO_REGISTER)
5279 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5281 while (regno < reg_max)
5283 CLEAR_HARD_REG_BIT (*p_regs, regno);
5293 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5295 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5296 initialize the static storage. */
5298 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5300 frv_ifcvt.added_insns_list = NULL_RTX;
5301 frv_ifcvt.cur_scratch_regs = 0;
5302 frv_ifcvt.num_nested_cond_exec = 0;
5303 frv_ifcvt.cr_reg = NULL_RTX;
5304 frv_ifcvt.nested_cc_reg = NULL_RTX;
5305 frv_ifcvt.extra_int_cr = NULL_RTX;
5306 frv_ifcvt.extra_fp_cr = NULL_RTX;
5307 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5311 /* Internal function to add a potential insn to the list of insns to be inserted
5312 if the conditional execution conversion is successful. */
5315 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5317 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5319 link->jump = before_p; /* Mark to add this before or after insn. */
5320 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5321 frv_ifcvt.added_insns_list);
5323 if (TARGET_DEBUG_COND_EXEC)
5326 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5327 (before_p) ? "before" : "after",
5328 (int)INSN_UID (insn));
5330 debug_rtx (pattern);
5335 /* A C expression to modify the code described by the conditional if
5336 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5337 FALSE_EXPR for converting if-then and if-then-else code to conditional
5338 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5339 tests cannot be converted. */
5342 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5344 basic_block test_bb = ce_info->test_bb; /* test basic block */
5345 basic_block then_bb = ce_info->then_bb; /* THEN */
5346 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5347 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5348 rtx true_expr = *p_true;
5352 enum machine_mode mode = GET_MODE (true_expr);
5356 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5358 rtx sub_cond_exec_reg;
5360 enum rtx_code code_true;
5361 enum rtx_code code_false;
5362 enum reg_class cc_class;
5363 enum reg_class cr_class;
5366 reg_set_iterator rsi;
5368 /* Make sure we are only dealing with hard registers. Also honor the
5369 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5371 if (!reload_completed || !TARGET_COND_EXEC
5372 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5375 /* Figure out which registers we can allocate for our own purposes. Only
5376 consider registers that are not preserved across function calls and are
5377 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5378 if we did not need to use them in reloading other registers. */
5379 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5380 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5381 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5382 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5383 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5385 /* If this is a nested IF, we need to discover whether the CC registers that
5386 are set/used inside of the block are used anywhere else. If not, we can
5387 change them to be the CC register that is paired with the CR register that
5388 controls the outermost IF block. */
5389 if (ce_info->pass > 1)
5391 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5392 for (j = CC_FIRST; j <= CC_LAST; j++)
5393 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5395 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5399 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5403 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5406 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5410 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5411 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5413 frv_ifcvt.added_insns_list = NULL_RTX;
5414 frv_ifcvt.cur_scratch_regs = 0;
5416 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5417 * sizeof (basic_block));
5423 /* Remove anything live at the beginning of the join block from being
5424 available for allocation. */
5425 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5427 if (regno < FIRST_PSEUDO_REGISTER)
5428 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5432 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5434 if (ce_info->num_multiple_test_blocks)
5436 basic_block multiple_test_bb = ce_info->last_test_bb;
5438 while (multiple_test_bb != test_bb)
5440 bb[num_bb++] = multiple_test_bb;
5441 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5445 /* Add in the THEN and ELSE blocks to be scanned. */
5446 bb[num_bb++] = then_bb;
5448 bb[num_bb++] = else_bb;
5450 sub_cond_exec_reg = NULL_RTX;
5451 frv_ifcvt.num_nested_cond_exec = 0;
5453 /* Scan all of the blocks for registers that must not be allocated. */
5454 for (j = 0; j < num_bb; j++)
5456 rtx last_insn = BB_END (bb[j]);
5457 rtx insn = BB_HEAD (bb[j]);
5461 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5462 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5464 (int) INSN_UID (BB_HEAD (bb[j])),
5465 (int) INSN_UID (BB_END (bb[j])));
5467 /* Anything live at the beginning of the block is obviously unavailable
5469 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5471 if (regno < FIRST_PSEUDO_REGISTER)
5472 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5475 /* Loop through the insns in the block. */
5478 /* Mark any new registers that are created as being unavailable for
5479 allocation. Also see if the CC register used in nested IFs can be
5485 int skip_nested_if = FALSE;
5487 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5488 (void *)&tmp_reg->regs);
5490 pattern = PATTERN (insn);
5491 if (GET_CODE (pattern) == COND_EXEC)
5493 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5495 if (reg != sub_cond_exec_reg)
5497 sub_cond_exec_reg = reg;
5498 frv_ifcvt.num_nested_cond_exec++;
5502 set = single_set_pattern (pattern);
5505 rtx dest = SET_DEST (set);
5506 rtx src = SET_SRC (set);
5508 if (GET_CODE (dest) == REG)
5510 int regno = REGNO (dest);
5511 enum rtx_code src_code = GET_CODE (src);
5513 if (CC_P (regno) && src_code == COMPARE)
5514 skip_nested_if = TRUE;
5516 else if (CR_P (regno)
5517 && (src_code == IF_THEN_ELSE
5518 || COMPARISON_P (src)))
5519 skip_nested_if = TRUE;
5523 if (! skip_nested_if)
5524 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5525 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5528 if (insn == last_insn)
5531 insn = NEXT_INSN (insn);
5535 /* If this is a nested if, rewrite the CC registers that are available to
5536 include the ones that can be rewritten, to increase the chance of being
5537 able to allocate a paired CC/CR register combination. */
5538 if (ce_info->pass > 1)
5540 for (j = CC_FIRST; j <= CC_LAST; j++)
5541 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5542 SET_HARD_REG_BIT (tmp_reg->regs, j);
5544 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5550 fprintf (dump_file, "Available GPRs: ");
5552 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5553 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5555 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5556 if (++num_gprs > GPR_TEMP_NUM+2)
5560 fprintf (dump_file, "%s\nAvailable CRs: ",
5561 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5563 for (j = CR_FIRST; j <= CR_LAST; j++)
5564 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5565 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5567 fputs ("\n", dump_file);
5569 if (ce_info->pass > 1)
5571 fprintf (dump_file, "Modifiable CCs: ");
5572 for (j = CC_FIRST; j <= CC_LAST; j++)
5573 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5574 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5576 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5577 frv_ifcvt.num_nested_cond_exec);
5581 /* Allocate the appropriate temporary condition code register. Try to
5582 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5583 that conditional cmp's can be done. */
5584 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5586 cr_class = ICR_REGS;
5587 cc_class = ICC_REGS;
5588 cc_first = ICC_FIRST;
5591 else if (mode == CC_FPmode)
5593 cr_class = FCR_REGS;
5594 cc_class = FCC_REGS;
5595 cc_first = FCC_FIRST;
5600 cc_first = cc_last = 0;
5601 cr_class = cc_class = NO_REGS;
5604 cc = XEXP (true_expr, 0);
5605 nested_cc = cr = NULL_RTX;
5606 if (cc_class != NO_REGS)
5608 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5609 so we can execute a csubcc/caddcc/cfcmps instruction. */
5612 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5614 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5616 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5617 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5619 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5620 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5623 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5624 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5634 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5641 "Will use %s for conditional execution, %s for nested comparisons\n",
5642 reg_names[ REGNO (cr)],
5643 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5645 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5646 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5647 bit being true. We don't do this for floating point, because of NaNs. */
5648 code = GET_CODE (true_expr);
5649 if (GET_MODE (cc) != CC_FPmode)
5651 code = reverse_condition (code);
5661 check_insn = gen_rtx_SET (VOIDmode, cr,
5662 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5664 /* Record the check insn to be inserted later. */
5665 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5667 /* Update the tests. */
5668 frv_ifcvt.cr_reg = cr;
5669 frv_ifcvt.nested_cc_reg = nested_cc;
5670 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5671 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5674 /* Fail, don't do this conditional execution. */
5677 *p_false = NULL_RTX;
5679 fprintf (dump_file, "Disabling this conditional execution.\n");
5685 /* A C expression to modify the code described by the conditional if
5686 information CE_INFO, for the basic block BB, possibly updating the tests in
5687 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5688 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5689 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5691 /* p_true and p_false are given expressions of the form:
5693 (and (eq:CC_CCR (reg:CC_CCR)
5699 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5704 rtx old_true = XEXP (*p_true, 0);
5705 rtx old_false = XEXP (*p_false, 0);
5706 rtx true_expr = XEXP (*p_true, 1);
5707 rtx false_expr = XEXP (*p_false, 1);
5710 rtx cr = XEXP (old_true, 0);
5712 rtx new_cr = NULL_RTX;
5713 rtx *p_new_cr = (rtx *)0;
5717 enum reg_class cr_class;
5718 enum machine_mode mode = GET_MODE (true_expr);
5719 rtx (*logical_func)(rtx, rtx, rtx);
5721 if (TARGET_DEBUG_COND_EXEC)
5724 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5725 ce_info->and_and_p ? "&&" : "||");
5727 debug_rtx (*p_true);
5729 fputs ("\nfalse insn:\n", stderr);
5730 debug_rtx (*p_false);
5733 if (!TARGET_MULTI_CE)
5736 if (GET_CODE (cr) != REG)
5739 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5741 cr_class = ICR_REGS;
5742 p_new_cr = &frv_ifcvt.extra_int_cr;
5744 else if (mode == CC_FPmode)
5746 cr_class = FCR_REGS;
5747 p_new_cr = &frv_ifcvt.extra_fp_cr;
5752 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5753 more &&/|| tests. */
5757 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5758 CC_CCRmode, TRUE, TRUE);
5763 if (ce_info->and_and_p)
5765 old_test = old_false;
5766 test_expr = true_expr;
5767 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5768 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5769 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5773 old_test = old_false;
5774 test_expr = false_expr;
5775 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5776 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5777 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5780 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5781 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5783 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5785 /* Now add the conditional check insn. */
5786 cc = XEXP (test_expr, 0);
5787 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5788 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5790 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5792 /* Add the new check insn to the list of check insns that need to be
5794 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5796 if (TARGET_DEBUG_COND_EXEC)
5798 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5801 debug_rtx (*p_true);
5803 fputs ("\nfalse insn:\n", stderr);
5804 debug_rtx (*p_false);
5810 *p_true = *p_false = NULL_RTX;
5812 /* If we allocated a CR register, release it. */
5815 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5816 *p_new_cr = NULL_RTX;
5819 if (TARGET_DEBUG_COND_EXEC)
5820 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5826 /* Return a register which will be loaded with a value if an IF block is
5827 converted to conditional execution. This is used to rewrite instructions
5828 that use constants to ones that just use registers. */
5831 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5833 int num_alloc = frv_ifcvt.cur_scratch_regs;
5837 /* We know gr0 == 0, so replace any errant uses. */
5838 if (value == const0_rtx)
5839 return gen_rtx_REG (SImode, GPR_FIRST);
5841 /* First search all registers currently loaded to see if we have an
5842 applicable constant. */
5843 if (CONSTANT_P (value)
5844 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5846 for (i = 0; i < num_alloc; i++)
5848 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5849 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5853 /* Have we exhausted the number of registers available? */
5854 if (num_alloc >= GPR_TEMP_NUM)
5857 fprintf (dump_file, "Too many temporary registers allocated\n");
5862 /* Allocate the new register. */
5863 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5867 fputs ("Could not find a scratch register\n", dump_file);
5872 frv_ifcvt.cur_scratch_regs++;
5873 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5877 if (GET_CODE (value) == CONST_INT)
5878 fprintf (dump_file, "Register %s will hold %ld\n",
5879 reg_names[ REGNO (reg)], (long)INTVAL (value));
5881 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5882 fprintf (dump_file, "Register %s will hold LR\n",
5883 reg_names[ REGNO (reg)]);
5886 fprintf (dump_file, "Register %s will hold a saved value\n",
5887 reg_names[ REGNO (reg)]);
5894 /* Update a MEM used in conditional code that might contain an offset to put
5895 the offset into a scratch register, so that the conditional load/store
5896 operations can be used. This function returns the original pointer if the
5897 MEM is valid to use in conditional code, NULL if we can't load up the offset
5898 into a temporary register, or the new MEM if we were successful. */
5901 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5903 rtx addr = XEXP (mem, 0);
5905 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5907 if (GET_CODE (addr) == PLUS)
5909 rtx addr_op0 = XEXP (addr, 0);
5910 rtx addr_op1 = XEXP (addr, 1);
5912 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5914 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5918 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5925 else if (CONSTANT_P (addr))
5926 addr = frv_ifcvt_load_value (addr, insn);
5931 if (addr == NULL_RTX)
5934 else if (XEXP (mem, 0) != addr)
5935 return change_address (mem, mode, addr);
5942 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5943 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5946 single_set_pattern (rtx pattern)
5951 if (GET_CODE (pattern) == COND_EXEC)
5952 pattern = COND_EXEC_CODE (pattern);
5954 if (GET_CODE (pattern) == SET)
5957 else if (GET_CODE (pattern) == PARALLEL)
5959 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5961 rtx sub = XVECEXP (pattern, 0, i);
5963 switch (GET_CODE (sub))
5987 /* A C expression to modify the code described by the conditional if
5988 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5989 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5990 insn cannot be converted to be executed conditionally. */
5993 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5997 rtx orig_ce_pattern = pattern;
6003 gcc_assert (GET_CODE (pattern) == COND_EXEC);
6005 test = COND_EXEC_TEST (pattern);
6006 if (GET_CODE (test) == AND)
6008 rtx cr = frv_ifcvt.cr_reg;
6011 op0 = XEXP (test, 0);
6012 if (! rtx_equal_p (cr, XEXP (op0, 0)))
6015 op1 = XEXP (test, 1);
6016 test_reg = XEXP (op1, 0);
6017 if (GET_CODE (test_reg) != REG)
6020 /* Is this the first nested if block in this sequence? If so, generate
6021 an andcr or andncr. */
6022 if (! frv_ifcvt.last_nested_if_cr)
6026 frv_ifcvt.last_nested_if_cr = test_reg;
6027 if (GET_CODE (op0) == NE)
6028 and_op = gen_andcr (test_reg, cr, test_reg);
6030 and_op = gen_andncr (test_reg, cr, test_reg);
6032 frv_ifcvt_add_insn (and_op, insn, TRUE);
6035 /* If this isn't the first statement in the nested if sequence, see if we
6036 are dealing with the same register. */
6037 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6040 COND_EXEC_TEST (pattern) = test = op1;
6043 /* If this isn't a nested if, reset state variables. */
6046 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6049 set = single_set_pattern (pattern);
6052 rtx dest = SET_DEST (set);
6053 rtx src = SET_SRC (set);
6054 enum machine_mode mode = GET_MODE (dest);
6056 /* Check for normal binary operators. */
6057 if (mode == SImode && ARITHMETIC_P (src))
6059 op0 = XEXP (src, 0);
6060 op1 = XEXP (src, 1);
6062 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6064 op1 = frv_ifcvt_load_value (op1, insn);
6066 COND_EXEC_CODE (pattern)
6067 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6075 /* For multiply by a constant, we need to handle the sign extending
6076 correctly. Add a USE of the value after the multiply to prevent flow
6077 from cratering because only one register out of the two were used. */
6078 else if (mode == DImode && GET_CODE (src) == MULT)
6080 op0 = XEXP (src, 0);
6081 op1 = XEXP (src, 1);
6082 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6084 op1 = frv_ifcvt_load_value (op1, insn);
6087 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6088 COND_EXEC_CODE (pattern)
6089 = gen_rtx_SET (VOIDmode, dest,
6090 gen_rtx_MULT (DImode, op0, op1));
6096 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6099 /* If we are just loading a constant created for a nested conditional
6100 execution statement, just load the constant without any conditional
6101 execution, since we know that the constant will not interfere with any
6103 else if (frv_ifcvt.scratch_insns_bitmap
6104 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6106 && REG_P (SET_DEST (set))
6107 /* We must not unconditionally set a scratch reg chosen
6108 for a nested if-converted block if its incoming
6109 value from the TEST block (or the result of the THEN
6110 branch) could/should propagate to the JOIN block.
6111 It suffices to test whether the register is live at
6112 the JOIN point: if it's live there, we can infer
6113 that we set it in the former JOIN block of the
6114 nested if-converted block (otherwise it wouldn't
6115 have been available as a scratch register), and it
6116 is either propagated through or set in the other
6117 conditional block. It's probably not worth trying
6118 to catch the latter case, and it could actually
6119 limit scheduling of the combined block quite
6122 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6123 REGNO (SET_DEST (set))))
6124 /* Similarly, we must not unconditionally set a reg
6125 used as scratch in the THEN branch if the same reg
6126 is live in the ELSE branch. */
6127 && (! ce_info->else_bb
6128 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6129 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6130 REGNO (SET_DEST (set))))))
6133 else if (mode == QImode || mode == HImode || mode == SImode
6136 int changed_p = FALSE;
6138 /* Check for just loading up a constant */
6139 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6141 src = frv_ifcvt_load_value (src, insn);
6148 /* See if we need to fix up stores */
6149 if (GET_CODE (dest) == MEM)
6151 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6156 else if (new_mem != dest)
6163 /* See if we need to fix up loads */
6164 if (GET_CODE (src) == MEM)
6166 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6171 else if (new_mem != src)
6178 /* If either src or destination changed, redo SET. */
6180 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6183 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6184 rewriting the CC register to be the same as the paired CC/CR register
6186 else if (mode == CC_CCRmode && COMPARISON_P (src))
6188 int regno = REGNO (XEXP (src, 0));
6191 if (ce_info->pass > 1
6192 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6193 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6195 src = gen_rtx_fmt_ee (GET_CODE (src),
6197 frv_ifcvt.nested_cc_reg,
6201 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6202 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6205 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6206 else if (ce_info->pass > 1
6207 && GET_CODE (dest) == REG
6208 && CC_P (REGNO (dest))
6209 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6210 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6212 && GET_CODE (src) == COMPARE)
6214 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6215 COND_EXEC_CODE (pattern)
6216 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6220 if (TARGET_DEBUG_COND_EXEC)
6222 rtx orig_pattern = PATTERN (insn);
6224 PATTERN (insn) = pattern;
6226 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6230 PATTERN (insn) = orig_pattern;
6236 if (TARGET_DEBUG_COND_EXEC)
6238 rtx orig_pattern = PATTERN (insn);
6240 PATTERN (insn) = orig_ce_pattern;
6242 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6246 PATTERN (insn) = orig_pattern;
6253 /* A C expression to perform any final machine dependent modifications in
6254 converting code to conditional execution in the code described by the
6255 conditional if information CE_INFO. */
6258 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6262 rtx p = frv_ifcvt.added_insns_list;
6265 /* Loop inserting the check insns. The last check insn is the first test,
6266 and is the appropriate place to insert constants. */
6271 rtx check_and_insert_insns = XEXP (p, 0);
6274 check_insn = XEXP (check_and_insert_insns, 0);
6275 existing_insn = XEXP (check_and_insert_insns, 1);
6278 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6279 the existing insn, otherwise it is to be inserted AFTER. */
6280 if (check_and_insert_insns->jump)
6282 emit_insn_before (check_insn, existing_insn);
6283 check_and_insert_insns->jump = 0;
6286 emit_insn_after (check_insn, existing_insn);
6288 free_EXPR_LIST_node (check_and_insert_insns);
6289 free_EXPR_LIST_node (old_p);
6291 while (p != NULL_RTX);
6293 /* Load up any constants needed into temp gprs */
6294 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6296 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6297 if (! frv_ifcvt.scratch_insns_bitmap)
6298 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6299 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6300 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6303 frv_ifcvt.added_insns_list = NULL_RTX;
6304 frv_ifcvt.cur_scratch_regs = 0;
6308 /* A C expression to cancel any machine dependent modifications in converting
6309 code to conditional execution in the code described by the conditional if
6310 information CE_INFO. */
6313 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6316 rtx p = frv_ifcvt.added_insns_list;
6318 /* Loop freeing up the EXPR_LIST's allocated. */
6319 while (p != NULL_RTX)
6321 rtx check_and_jump = XEXP (p, 0);
6325 free_EXPR_LIST_node (check_and_jump);
6326 free_EXPR_LIST_node (old_p);
6329 /* Release any temporary gprs allocated. */
6330 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6331 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6333 frv_ifcvt.added_insns_list = NULL_RTX;
6334 frv_ifcvt.cur_scratch_regs = 0;
6338 /* A C expression for the size in bytes of the trampoline, as an integer.
6342 setlo #0, <static_chain>
6344 sethi #0, <static_chain>
6345 jmpl @(gr0,<jmp_reg>) */
6348 frv_trampoline_size (void)
6351 /* Allocate room for the function descriptor and the lddi
6354 return 5 /* instructions */ * 4 /* instruction size. */;
6358 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6359 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6360 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6361 should be passed to the function when it is called.
6366 setlo #0, <static_chain>
6368 sethi #0, <static_chain>
6369 jmpl @(gr0,<jmp_reg>) */
6372 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6374 rtx addr = XEXP (m_tramp, 0);
6375 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6376 rtx sc_reg = force_reg (Pmode, static_chain);
6378 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6381 GEN_INT (frv_trampoline_size ()), SImode,
6387 /* Many machines have some registers that cannot be copied directly to or from
6388 memory or even from other types of registers. An example is the `MQ'
6389 register, which on most machines, can only be copied to or from general
6390 registers, but not memory. Some machines allow copying all registers to and
6391 from memory, but require a scratch register for stores to some memory
6392 locations (e.g., those with symbolic address on the RT, and those with
6393 certain symbolic address on the SPARC when compiling PIC). In some cases,
6394 both an intermediate and a scratch register are required.
6396 You should define these macros to indicate to the reload phase that it may
6397 need to allocate at least one register for a reload in addition to the
6398 register to contain the data. Specifically, if copying X to a register
6399 RCLASS in MODE requires an intermediate register, you should define
6400 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6401 whose registers can be used as intermediate registers or scratch registers.
6403 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6404 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6405 largest register class required. If the requirements for input and output
6406 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6407 instead of defining both macros identically.
6409 The values returned by these macros are often `GENERAL_REGS'. Return
6410 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6411 to or from a register of RCLASS in MODE without requiring a scratch register.
6412 Do not define this macro if it would always return `NO_REGS'.
6414 If a scratch register is required (either with or without an intermediate
6415 register), you should define patterns for `reload_inM' or `reload_outM', as
6416 required.. These patterns, which will normally be implemented with a
6417 `define_expand', should be similar to the `movM' patterns, except that
6418 operand 2 is the scratch register.
6420 Define constraints for the reload register and scratch register that contain
6421 a single register class. If the original reload register (whose class is
6422 RCLASS) can meet the constraint given in the pattern, the value returned by
6423 these macros is used for the class of the scratch register. Otherwise, two
6424 additional reload registers are required. Their classes are obtained from
6425 the constraints in the insn pattern.
6427 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6428 either be in a hard register or in memory. Use `true_regnum' to find out;
6429 it will return -1 if the pseudo is in memory and the hard register number if
6430 it is in a register.
6432 These macros should not be used in the case where a particular class of
6433 registers can only be copied to memory and not to another class of
6434 registers. In that case, secondary reload registers are not needed and
6435 would not be helpful. Instead, a stack location must be used to perform the
6436 copy and the `movM' pattern should use memory as an intermediate storage.
6437 This case often occurs between floating-point and general registers. */
6440 frv_secondary_reload_class (enum reg_class rclass,
6441 enum machine_mode mode ATTRIBUTE_UNUSED,
6452 /* Accumulators/Accumulator guard registers need to go through floating
6458 if (x && GET_CODE (x) == REG)
6460 int regno = REGNO (x);
6462 if (ACC_P (regno) || ACCG_P (regno))
6467 /* Nonzero constants should be loaded into an FPR through a GPR. */
6471 if (x && CONSTANT_P (x) && !ZERO_P (x))
6477 /* All of these types need gpr registers. */
6489 /* The accumulators need fpr registers. */
6501 /* This hook exists to catch the case where secondary_reload_class() is
6502 called from init_reg_autoinc() in regclass.c - before the reload optabs
6503 have been initialised. */
6506 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6507 enum machine_mode reload_mode,
6508 secondary_reload_info * sri)
6510 enum reg_class rclass = NO_REGS;
6511 enum reg_class reload_class = (enum reg_class) reload_class_i;
6513 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6515 sri->icode = sri->prev_sri->t_icode;
6519 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6521 if (rclass != NO_REGS)
6523 enum insn_code icode
6524 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6528 /* This happens when then the reload_[in|out]_optabs have
6529 not been initialised. */
6530 sri->t_icode = CODE_FOR_nothing;
6535 /* Fall back to the default secondary reload handler. */
6536 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6540 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6543 frv_class_likely_spilled_p (reg_class_t rclass)
6553 case FDPIC_FPTR_REGS:
6575 /* An expression for the alignment of a structure field FIELD if the
6576 alignment computed in the usual way is COMPUTED. GCC uses this
6577 value instead of the value in `BIGGEST_ALIGNMENT' or
6578 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6580 /* The definition type of the bit field data is either char, short, long or
6581 long long. The maximum bit size is the number of bits of its own type.
6583 The bit field data is assigned to a storage unit that has an adequate size
6584 for bit field data retention and is located at the smallest address.
6586 Consecutive bit field data are packed at consecutive bits having the same
6587 storage unit, with regard to the type, beginning with the MSB and continuing
6590 If a field to be assigned lies over a bit field type boundary, its
6591 assignment is completed by aligning it with a boundary suitable for the
6594 When a bit field having a bit length of 0 is declared, it is forcibly
6595 assigned to the next storage unit.
6608 &x 00000000 00000000 00000000 00000000
6611 &x+4 00000000 00000000 00000000 00000000
6614 &x+8 00000000 00000000 00000000 00000000
6617 &x+12 00000000 00000000 00000000 00000000
6623 frv_adjust_field_align (tree field, int computed)
6625 /* Make sure that the bitfield is not wider than the type. */
6626 if (DECL_BIT_FIELD (field)
6627 && !DECL_ARTIFICIAL (field))
6629 tree parent = DECL_CONTEXT (field);
6630 tree prev = NULL_TREE;
6633 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6635 if (TREE_CODE (cur) != FIELD_DECL)
6643 /* If this isn't a :0 field and if the previous element is a bitfield
6644 also, see if the type is different, if so, we will need to align the
6645 bit-field to the next boundary. */
6647 && ! DECL_PACKED (field)
6648 && ! integer_zerop (DECL_SIZE (field))
6649 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6651 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6652 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6653 computed = (prev_align > cur_align) ? prev_align : cur_align;
6661 /* A C expression that is nonzero if it is permissible to store a value of mode
6662 MODE in hard register number REGNO (or in several registers starting with
6663 that one). For a machine where all registers are equivalent, a suitable
6666 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6668 It is not necessary for this macro to check for the numbers of fixed
6669 registers, because the allocation mechanism considers them to be always
6672 On some machines, double-precision values must be kept in even/odd register
6673 pairs. The way to implement that is to define this macro to reject odd
6674 register numbers for such modes.
6676 The minimum requirement for a mode to be OK in a register is that the
6677 `movMODE' instruction pattern support moves between the register and any
6678 other hard register for which the mode is OK; and that moving a value into
6679 the register and back out not alter it.
6681 Since the same instruction used to move `SImode' will work for all narrower
6682 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6683 to distinguish between these modes, provided you define patterns `movhi',
6684 etc., to take advantage of this. This is useful because of the interaction
6685 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6686 all integer modes to be tieable.
6688 Many machines have special registers for floating point arithmetic. Often
6689 people assume that floating point machine modes are allowed only in floating
6690 point registers. This is not true. Any registers that can hold integers
6691 can safely *hold* a floating point machine mode, whether or not floating
6692 arithmetic can be done on it in those registers. Integer move instructions
6693 can be used to move the values.
6695 On some machines, though, the converse is true: fixed-point machine modes
6696 may not go in floating registers. This is true if the floating registers
6697 normalize any value stored in them, because storing a non-floating value
6698 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6699 fixed-point machine modes in floating registers. But if the floating
6700 registers do not automatically normalize, if you can store any bit pattern
6701 in one and retrieve it unchanged without a trap, then any machine mode may
6702 go in a floating register, so you can define this macro to say so.
6704 The primary significance of special floating registers is rather that they
6705 are the registers acceptable in floating point arithmetic instructions.
6706 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6707 writing the proper constraints for those instructions.
6709 On some machines, the floating registers are especially slow to access, so
6710 that it is better to store a value in a stack frame than in such a register
6711 if floating point arithmetic is not being done. As long as the floating
6712 registers are not in class `GENERAL_REGS', they will not be used unless some
6713 pattern's constraint asks for one. */
6716 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6726 return ICC_P (regno) || GPR_P (regno);
6729 return CR_P (regno) || GPR_P (regno);
6732 return FCC_P (regno) || GPR_P (regno);
6738 /* Set BASE to the first register in REGNO's class. Set MASK to the
6739 bits that must be clear in (REGNO - BASE) for the register to be
6741 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6745 /* ACCGs store one byte. Two-byte quantities must start in
6746 even-numbered registers, four-byte ones in registers whose
6747 numbers are divisible by four, and so on. */
6749 mask = GET_MODE_SIZE (mode) - 1;
6753 /* The other registers store one word. */
6754 if (GPR_P (regno) || regno == AP_FIRST)
6757 else if (FPR_P (regno))
6760 else if (ACC_P (regno))
6763 else if (SPR_P (regno))
6764 return mode == SImode;
6766 /* Fill in the table. */
6770 /* Anything smaller than an SI is OK in any word-sized register. */
6771 if (GET_MODE_SIZE (mode) < 4)
6774 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6776 return (((regno - base) & mask) == 0);
6783 /* A C expression for the number of consecutive hard registers, starting at
6784 register number REGNO, required to hold a value of mode MODE.
6786 On a machine where all registers are exactly one word, a suitable definition
6789 #define HARD_REGNO_NREGS(REGNO, MODE) \
6790 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6791 / UNITS_PER_WORD)) */
6793 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6794 that we can build the appropriate instructions to properly reload the
6795 values. Also, make the byte-sized accumulator guards use one guard
6799 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6802 return GET_MODE_SIZE (mode);
6804 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6808 /* A C expression for the maximum number of consecutive registers of
6809 class RCLASS needed to hold a value of mode MODE.
6811 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6812 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6813 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6815 This macro helps control the handling of multiple-word values in
6818 This declaration is required. */
6821 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6823 if (rclass == ACCG_REGS)
6824 /* An N-byte value requires N accumulator guards. */
6825 return GET_MODE_SIZE (mode);
6827 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6831 /* A C expression that is nonzero if X is a legitimate constant for an
6832 immediate operand on the target machine. You can assume that X satisfies
6833 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6834 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6837 frv_legitimate_constant_p (rtx x)
6839 enum machine_mode mode = GET_MODE (x);
6841 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6842 means that the move expanders will be expected to deal with most
6843 kinds of constant, regardless of what we return here.
6845 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6846 a constant can be entered into reg_equiv_constant[]. If we return true,
6847 reload can create new instances of the constant whenever it likes.
6849 The idea is therefore to accept as many constants as possible (to give
6850 reload more freedom) while rejecting constants that can only be created
6851 at certain times. In particular, anything with a symbolic component will
6852 require use of the pseudo FDPIC register, which is only available before
6855 return LEGITIMATE_PIC_OPERAND_P (x);
6857 /* All of the integer constants are ok. */
6858 if (GET_CODE (x) != CONST_DOUBLE)
6861 /* double integer constants are ok. */
6862 if (mode == VOIDmode || mode == DImode)
6865 /* 0 is always ok. */
6866 if (x == CONST0_RTX (mode))
6869 /* If floating point is just emulated, allow any constant, since it will be
6870 constructed in the GPRs. */
6871 if (!TARGET_HAS_FPRS)
6874 if (mode == DFmode && !TARGET_DOUBLE)
6877 /* Otherwise store the constant away and do a load. */
6881 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6882 CC_NZ for comparisons against zero in which a single Z or N flag test
6883 is enough, CC_UNS for other unsigned comparisons, and CC for other
6884 signed comparisons. */
6887 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6889 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6898 return y == const0_rtx ? CC_NZmode : CCmode;
6904 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6911 /* A C expression for the cost of moving data from a register in class FROM to
6912 one in class TO. The classes are expressed using the enumeration values
6913 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6914 interpreted relative to that.
6916 It is not required that the cost always equal 2 when FROM is the same as TO;
6917 on some machines it is expensive to move between registers if they are not
6920 If reload sees an insn consisting of a single `set' between two hard
6921 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6922 value of 2, reload does not check to ensure that the constraints of the insn
6923 are met. Setting a cost of other than 2 will allow reload to verify that
6924 the constraints are met. You should do this if the `movM' pattern's
6925 constraints do not allow such copying. */
6927 #define HIGH_COST 40
6928 #define MEDIUM_COST 3
6932 frv_register_move_cost (enum reg_class from, enum reg_class to)
7016 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7017 use ".picptr" to generate safe relocations for PIC code. We also
7018 need a fixup entry for aligned (non-debugging) code. */
7021 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
7023 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
7025 if (GET_CODE (value) == CONST
7026 || GET_CODE (value) == SYMBOL_REF
7027 || GET_CODE (value) == LABEL_REF)
7029 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
7030 && SYMBOL_REF_FUNCTION_P (value))
7032 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
7033 output_addr_const (asm_out_file, value);
7034 fputs (")\n", asm_out_file);
7037 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7038 && frv_function_symbol_referenced_p (value))
7040 if (aligned_p && !TARGET_FDPIC)
7042 static int label_num = 0;
7046 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7047 p = (* targetm.strip_name_encoding) (buf);
7049 fprintf (asm_out_file, "%s:\n", p);
7050 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7051 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7052 fprintf (asm_out_file, "\t.previous\n");
7054 assemble_integer_with_op ("\t.picptr\t", value);
7059 /* We've set the unaligned SI op to NULL, so we always have to
7060 handle the unaligned case here. */
7061 assemble_integer_with_op ("\t.4byte\t", value);
7065 return default_assemble_integer (value, size, aligned_p);
7068 /* Function to set up the backend function structure. */
7070 static struct machine_function *
7071 frv_init_machine_status (void)
7073 return ggc_alloc_cleared_machine_function ();
7076 /* Implement TARGET_SCHED_ISSUE_RATE. */
7079 frv_issue_rate (void)
7084 switch (frv_cpu_type)
7088 case FRV_CPU_SIMPLE:
7096 case FRV_CPU_GENERIC:
7098 case FRV_CPU_TOMCAT:
7106 /* A for_each_rtx callback. If X refers to an accumulator, return
7107 ACC_GROUP_ODD if the bit 2 of the register number is set and
7108 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7112 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7116 if (ACC_P (REGNO (*x)))
7117 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7118 if (ACCG_P (REGNO (*x)))
7119 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7124 /* Return the value of INSN's acc_group attribute. */
7127 frv_acc_group (rtx insn)
7129 /* This distinction only applies to the FR550 packing constraints. */
7130 if (frv_cpu_type != FRV_CPU_FR550)
7131 return ACC_GROUP_NONE;
7132 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7135 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7136 INSN will try to claim first. Since this value depends only on the
7137 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7140 frv_insn_unit (rtx insn)
7142 enum attr_type type;
7144 type = get_attr_type (insn);
7145 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7147 /* We haven't seen this type of instruction before. */
7151 /* Issue the instruction on its own to see which unit it prefers. */
7152 state = alloca (state_size ());
7153 state_reset (state);
7154 state_transition (state, insn);
7156 /* Find out which unit was taken. */
7157 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7158 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7161 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7163 frv_type_to_unit[type] = unit;
7165 return frv_type_to_unit[type];
7168 /* Return true if INSN issues to a branch unit. */
7171 frv_issues_to_branch_unit_p (rtx insn)
7173 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7176 /* The current state of the packing pass, implemented by frv_pack_insns. */
7178 /* The state of the pipeline DFA. */
7181 /* Which hardware registers are set within the current packet,
7182 and the conditions under which they are set. */
7183 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7185 /* The memory locations that have been modified so far in this
7186 packet. MEM is the memref and COND is the regstate_t condition
7187 under which it is set. */
7193 /* The number of valid entries in MEMS. The value is larger than
7194 ARRAY_SIZE (mems) if there were too many mems to record. */
7195 unsigned int num_mems;
7197 /* The maximum number of instructions that can be packed together. */
7198 unsigned int issue_rate;
7200 /* The instructions in the packet, partitioned into groups. */
7201 struct frv_packet_group {
7202 /* How many instructions in the packet belong to this group. */
7203 unsigned int num_insns;
7205 /* A list of the instructions that belong to this group, in the order
7206 they appear in the rtl stream. */
7207 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7209 /* The contents of INSNS after they have been sorted into the correct
7210 assembly-language order. Element X issues to unit X. The list may
7211 contain extra nops. */
7212 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7214 /* The member of frv_nops[] to use in sorted[]. */
7216 } groups[NUM_GROUPS];
7218 /* The instructions that make up the current packet. */
7219 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7220 unsigned int num_insns;
7223 /* Return the regstate_t flags for the given COND_EXEC condition.
7224 Abort if the condition isn't in the right form. */
7227 frv_cond_flags (rtx cond)
7229 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7230 && GET_CODE (XEXP (cond, 0)) == REG
7231 && CR_P (REGNO (XEXP (cond, 0)))
7232 && XEXP (cond, 1) == const0_rtx);
7233 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7234 | (GET_CODE (cond) == NE
7236 : REGSTATE_IF_FALSE));
7240 /* Return true if something accessed under condition COND2 can
7241 conflict with something written under condition COND1. */
7244 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7246 /* If either reference was unconditional, we have a conflict. */
7247 if ((cond1 & REGSTATE_IF_EITHER) == 0
7248 || (cond2 & REGSTATE_IF_EITHER) == 0)
7251 /* The references might conflict if they were controlled by
7253 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7256 /* They definitely conflict if they are controlled by the
7258 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7265 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7266 the current packet. DATA points to a regstate_t that describes the
7267 condition under which *X might be set or used. */
7270 frv_registers_conflict_p_1 (rtx *x, void *data)
7272 unsigned int regno, i;
7275 cond = *(regstate_t *) data;
7277 if (GET_CODE (*x) == REG)
7278 FOR_EACH_REGNO (regno, *x)
7279 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7280 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7283 if (GET_CODE (*x) == MEM)
7285 /* If we ran out of memory slots, assume a conflict. */
7286 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7289 /* Check for output or true dependencies with earlier MEMs. */
7290 for (i = 0; i < frv_packet.num_mems; i++)
7291 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7293 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7297 if (output_dependence (frv_packet.mems[i].mem, *x))
7302 /* The return values of calls aren't significant: they describe
7303 the effect of the call as a whole, not of the insn itself. */
7304 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7306 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7311 /* Check subexpressions. */
7316 /* Return true if something in X might depend on an instruction
7317 in the current packet. */
7320 frv_registers_conflict_p (rtx x)
7325 if (GET_CODE (x) == COND_EXEC)
7327 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7330 flags |= frv_cond_flags (XEXP (x, 0));
7333 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7337 /* A note_stores callback. DATA points to the regstate_t condition
7338 under which X is modified. Update FRV_PACKET accordingly. */
7341 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7345 if (GET_CODE (x) == REG)
7346 FOR_EACH_REGNO (regno, x)
7347 frv_packet.regstate[regno] |= *(regstate_t *) data;
7349 if (GET_CODE (x) == MEM)
7351 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7353 frv_packet.mems[frv_packet.num_mems].mem = x;
7354 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7356 frv_packet.num_mems++;
7361 /* Update the register state information for an instruction whose
7365 frv_registers_update (rtx x)
7369 flags = REGSTATE_MODIFIED;
7370 if (GET_CODE (x) == COND_EXEC)
7372 flags |= frv_cond_flags (XEXP (x, 0));
7375 note_stores (x, frv_registers_update_1, &flags);
7379 /* Initialize frv_packet for the start of a new packet. */
7382 frv_start_packet (void)
7384 enum frv_insn_group group;
7386 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7387 frv_packet.num_mems = 0;
7388 frv_packet.num_insns = 0;
7389 for (group = 0; group < NUM_GROUPS; group++)
7390 frv_packet.groups[group].num_insns = 0;
7394 /* Likewise for the start of a new basic block. */
7397 frv_start_packet_block (void)
7399 state_reset (frv_packet.dfa_state);
7400 frv_start_packet ();
7404 /* Finish the current packet, if any, and start a new one. Call
7405 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7408 frv_finish_packet (void (*handle_packet) (void))
7410 if (frv_packet.num_insns > 0)
7413 state_transition (frv_packet.dfa_state, 0);
7414 frv_start_packet ();
7419 /* Return true if INSN can be added to the current packet. Update
7420 the DFA state on success. */
7423 frv_pack_insn_p (rtx insn)
7425 /* See if the packet is already as long as it can be. */
7426 if (frv_packet.num_insns == frv_packet.issue_rate)
7429 /* If the scheduler thought that an instruction should start a packet,
7430 it's usually a good idea to believe it. It knows much more about
7431 the latencies than we do.
7433 There are some exceptions though:
7435 - Conditional instructions are scheduled on the assumption that
7436 they will be executed. This is usually a good thing, since it
7437 tends to avoid unnecessary stalls in the conditional code.
7438 But we want to pack conditional instructions as tightly as
7439 possible, in order to optimize the case where they aren't
7442 - The scheduler will always put branches on their own, even
7443 if there's no real dependency.
7445 - There's no point putting a call in its own packet unless
7447 if (frv_packet.num_insns > 0
7448 && GET_CODE (insn) == INSN
7449 && GET_MODE (insn) == TImode
7450 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7453 /* Check for register conflicts. Don't do this for setlo since any
7454 conflict will be with the partnering sethi, with which it can
7456 if (get_attr_type (insn) != TYPE_SETLO)
7457 if (frv_registers_conflict_p (PATTERN (insn)))
7460 return state_transition (frv_packet.dfa_state, insn) < 0;
7464 /* Add instruction INSN to the current packet. */
7467 frv_add_insn_to_packet (rtx insn)
7469 struct frv_packet_group *packet_group;
7471 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7472 packet_group->insns[packet_group->num_insns++] = insn;
7473 frv_packet.insns[frv_packet.num_insns++] = insn;
7475 frv_registers_update (PATTERN (insn));
7479 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7480 packet ends in a branch or call, insert the nop before it, otherwise
7484 frv_insert_nop_in_packet (rtx insn)
7486 struct frv_packet_group *packet_group;
7489 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7490 last = frv_packet.insns[frv_packet.num_insns - 1];
7491 if (GET_CODE (last) != INSN)
7493 insn = emit_insn_before (PATTERN (insn), last);
7494 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7495 frv_packet.insns[frv_packet.num_insns++] = last;
7499 insn = emit_insn_after (PATTERN (insn), last);
7500 frv_packet.insns[frv_packet.num_insns++] = insn;
7502 packet_group->insns[packet_group->num_insns++] = insn;
7506 /* If packing is enabled, divide the instructions into packets and
7507 return true. Call HANDLE_PACKET for each complete packet. */
7510 frv_for_each_packet (void (*handle_packet) (void))
7512 rtx insn, next_insn;
7514 frv_packet.issue_rate = frv_issue_rate ();
7516 /* Early exit if we don't want to pack insns. */
7518 || !flag_schedule_insns_after_reload
7519 || !TARGET_VLIW_BRANCH
7520 || frv_packet.issue_rate == 1)
7523 /* Set up the initial packing state. */
7525 frv_packet.dfa_state = alloca (state_size ());
7527 frv_start_packet_block ();
7528 for (insn = get_insns (); insn != 0; insn = next_insn)
7533 code = GET_CODE (insn);
7534 next_insn = NEXT_INSN (insn);
7536 if (code == CODE_LABEL)
7538 frv_finish_packet (handle_packet);
7539 frv_start_packet_block ();
7543 switch (GET_CODE (PATTERN (insn)))
7552 /* Calls mustn't be packed on a TOMCAT. */
7553 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7554 frv_finish_packet (handle_packet);
7556 /* Since the last instruction in a packet determines the EH
7557 region, any exception-throwing instruction must come at
7558 the end of reordered packet. Insns that issue to a
7559 branch unit are bound to come last; for others it's
7560 too hard to predict. */
7561 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7562 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7563 frv_finish_packet (handle_packet);
7565 /* Finish the current packet if we can't add INSN to it.
7566 Simulate cycles until INSN is ready to issue. */
7567 if (!frv_pack_insn_p (insn))
7569 frv_finish_packet (handle_packet);
7570 while (!frv_pack_insn_p (insn))
7571 state_transition (frv_packet.dfa_state, 0);
7574 /* Add the instruction to the packet. */
7575 frv_add_insn_to_packet (insn);
7577 /* Calls and jumps end a packet, as do insns that throw
7579 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7580 frv_finish_packet (handle_packet);
7584 frv_finish_packet (handle_packet);
7589 /* Subroutine of frv_sort_insn_group. We are trying to sort
7590 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7591 language order. We have already picked a new position for
7592 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7593 These instructions will occupy elements [0, LOWER_SLOT) and
7594 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7595 the DFA state after issuing these instructions.
7597 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7598 of the unused instructions. Return true if one such permutation gives
7599 a valid ordering, leaving the successful permutation in sorted[].
7600 Do not modify sorted[] until a valid permutation is found. */
7603 frv_sort_insn_group_1 (enum frv_insn_group group,
7604 unsigned int lower_slot, unsigned int upper_slot,
7605 unsigned int issued, unsigned int num_insns,
7608 struct frv_packet_group *packet_group;
7614 /* Early success if we've filled all the slots. */
7615 if (lower_slot == upper_slot)
7618 packet_group = &frv_packet.groups[group];
7619 dfa_size = state_size ();
7620 test_state = alloca (dfa_size);
7622 /* Try issuing each unused instruction. */
7623 for (i = num_insns - 1; i + 1 != 0; i--)
7624 if (~issued & (1 << i))
7626 insn = packet_group->sorted[i];
7627 memcpy (test_state, state, dfa_size);
7628 if (state_transition (test_state, insn) < 0
7629 && cpu_unit_reservation_p (test_state,
7630 NTH_UNIT (group, upper_slot - 1))
7631 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7632 issued | (1 << i), num_insns,
7635 packet_group->sorted[upper_slot - 1] = insn;
7643 /* Compare two instructions by their frv_insn_unit. */
7646 frv_compare_insns (const void *first, const void *second)
7648 const rtx *const insn1 = (rtx const *) first,
7649 *const insn2 = (rtx const *) second;
7650 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7653 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7654 and sort it into assembly language order. See frv.md for a description of
7658 frv_sort_insn_group (enum frv_insn_group group)
7660 struct frv_packet_group *packet_group;
7661 unsigned int first, i, nop, max_unit, num_slots;
7662 state_t state, test_state;
7665 packet_group = &frv_packet.groups[group];
7667 /* Assume no nop is needed. */
7668 packet_group->nop = 0;
7670 if (packet_group->num_insns == 0)
7673 /* Copy insns[] to sorted[]. */
7674 memcpy (packet_group->sorted, packet_group->insns,
7675 sizeof (rtx) * packet_group->num_insns);
7677 /* Sort sorted[] by the unit that each insn tries to take first. */
7678 if (packet_group->num_insns > 1)
7679 qsort (packet_group->sorted, packet_group->num_insns,
7680 sizeof (rtx), frv_compare_insns);
7682 /* That's always enough for branch and control insns. */
7683 if (group == GROUP_B || group == GROUP_C)
7686 dfa_size = state_size ();
7687 state = alloca (dfa_size);
7688 test_state = alloca (dfa_size);
7690 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7691 consecutively and such that the DFA takes unit X when sorted[X]
7692 is added. Set STATE to the new DFA state. */
7693 state_reset (test_state);
7694 for (first = 0; first < packet_group->num_insns; first++)
7696 memcpy (state, test_state, dfa_size);
7697 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7698 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7702 /* If all the instructions issued in ascending order, we're done. */
7703 if (first == packet_group->num_insns)
7706 /* Add nops to the end of sorted[] and try each permutation until
7707 we find one that works. */
7708 for (nop = 0; nop < frv_num_nops; nop++)
7710 max_unit = frv_insn_unit (frv_nops[nop]);
7711 if (frv_unit_groups[max_unit] == group)
7713 packet_group->nop = frv_nops[nop];
7714 num_slots = UNIT_NUMBER (max_unit) + 1;
7715 for (i = packet_group->num_insns; i < num_slots; i++)
7716 packet_group->sorted[i] = frv_nops[nop];
7717 if (frv_sort_insn_group_1 (group, first, num_slots,
7718 (1 << first) - 1, num_slots, state))
7725 /* Sort the current packet into assembly-language order. Set packing
7726 flags as appropriate. */
7729 frv_reorder_packet (void)
7731 unsigned int cursor[NUM_GROUPS];
7732 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7733 unsigned int unit, to, from;
7734 enum frv_insn_group group;
7735 struct frv_packet_group *packet_group;
7737 /* First sort each group individually. */
7738 for (group = 0; group < NUM_GROUPS; group++)
7741 frv_sort_insn_group (group);
7744 /* Go through the unit template and try add an instruction from
7745 that unit's group. */
7747 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7749 group = frv_unit_groups[unit];
7750 packet_group = &frv_packet.groups[group];
7751 if (cursor[group] < packet_group->num_insns)
7753 /* frv_reorg should have added nops for us. */
7754 gcc_assert (packet_group->sorted[cursor[group]]
7755 != packet_group->nop);
7756 insns[to++] = packet_group->sorted[cursor[group]++];
7760 gcc_assert (to == frv_packet.num_insns);
7762 /* Clear the last instruction's packing flag, thus marking the end of
7763 a packet. Reorder the other instructions relative to it. */
7764 CLEAR_PACKING_FLAG (insns[to - 1]);
7765 for (from = 0; from < to - 1; from++)
7767 remove_insn (insns[from]);
7768 add_insn_before (insns[from], insns[to - 1], NULL);
7769 SET_PACKING_FLAG (insns[from]);
7774 /* Divide instructions into packets. Reorder the contents of each
7775 packet so that they are in the correct assembly-language order.
7777 Since this pass can change the raw meaning of the rtl stream, it must
7778 only be called at the last minute, just before the instructions are
7782 frv_pack_insns (void)
7784 if (frv_for_each_packet (frv_reorder_packet))
7785 frv_insn_packing_flag = 0;
7787 frv_insn_packing_flag = -1;
7790 /* See whether we need to add nops to group GROUP in order to
7791 make a valid packet. */
7794 frv_fill_unused_units (enum frv_insn_group group)
7796 unsigned int non_nops, nops, i;
7797 struct frv_packet_group *packet_group;
7799 packet_group = &frv_packet.groups[group];
7801 /* Sort the instructions into assembly-language order.
7802 Use nops to fill slots that are otherwise unused. */
7803 frv_sort_insn_group (group);
7805 /* See how many nops are needed before the final useful instruction. */
7807 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7808 while (packet_group->sorted[i++] == packet_group->nop)
7811 /* Insert that many nops into the instruction stream. */
7813 frv_insert_nop_in_packet (packet_group->nop);
7816 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7819 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7821 if (io1->const_address != 0 && io2->const_address != 0)
7822 return io1->const_address == io2->const_address;
7824 if (io1->var_address != 0 && io2->var_address != 0)
7825 return rtx_equal_p (io1->var_address, io2->var_address);
7830 /* Return true if operations IO1 and IO2 are guaranteed to complete
7834 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7836 /* The order of writes is always preserved. */
7837 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7840 /* The order of reads isn't preserved. */
7841 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7844 /* One operation is a write and the other is (or could be) a read.
7845 The order is only guaranteed if the accesses are to the same
7847 return frv_same_doubleword_p (io1, io2);
7850 /* Generalize I/O operation X so that it covers both X and Y. */
7853 frv_io_union (struct frv_io *x, const struct frv_io *y)
7855 if (x->type != y->type)
7856 x->type = FRV_IO_UNKNOWN;
7857 if (!frv_same_doubleword_p (x, y))
7859 x->const_address = 0;
7864 /* Fill IO with information about the load or store associated with
7865 membar instruction INSN. */
7868 frv_extract_membar (struct frv_io *io, rtx insn)
7870 extract_insn (insn);
7871 io->type = INTVAL (recog_data.operand[2]);
7872 io->const_address = INTVAL (recog_data.operand[1]);
7873 io->var_address = XEXP (recog_data.operand[0], 0);
7876 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7877 if X is a register and *DATA depends on X. */
7880 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7882 rtx *other = (rtx *) data;
7884 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7888 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7889 Remove every modified register from the set. */
7892 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7894 HARD_REG_SET *set = (HARD_REG_SET *) data;
7898 FOR_EACH_REGNO (regno, x)
7899 CLEAR_HARD_REG_BIT (*set, regno);
7902 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7903 Add every register in *X to the set. */
7906 frv_io_handle_use_1 (rtx *x, void *data)
7908 HARD_REG_SET *set = (HARD_REG_SET *) data;
7912 FOR_EACH_REGNO (regno, *x)
7913 SET_HARD_REG_BIT (*set, regno);
7918 /* A note_stores callback that applies frv_io_handle_use_1 to an
7919 entire rhs value. */
7922 frv_io_handle_use (rtx *x, void *data)
7924 for_each_rtx (x, frv_io_handle_use_1, data);
7927 /* Go through block BB looking for membars to remove. There are two
7928 cases where intra-block analysis is enough:
7930 - a membar is redundant if it occurs between two consecutive I/O
7931 operations and if those operations are guaranteed to complete
7934 - a membar for a __builtin_read is redundant if the result is
7935 used before the next I/O operation is issued.
7937 If the last membar in the block could not be removed, and there
7938 are guaranteed to be no I/O operations between that membar and
7939 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7942 Describe the block's first I/O operation in *NEXT_IO. Describe
7943 an unknown operation if the block doesn't do any I/O. */
7946 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7949 HARD_REG_SET used_regs;
7950 rtx next_membar, set, insn;
7953 /* NEXT_IO is the next I/O operation to be performed after the current
7954 instruction. It starts off as being an unknown operation. */
7955 memset (next_io, 0, sizeof (*next_io));
7957 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7958 next_is_end_p = true;
7960 /* If the current instruction is a __builtin_read or __builtin_write,
7961 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7962 is null if the membar has already been deleted.
7964 Note that the initialization here should only be needed to
7965 suppress warnings. */
7968 /* USED_REGS is the set of registers that are used before the
7969 next I/O instruction. */
7970 CLEAR_HARD_REG_SET (used_regs);
7972 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7973 if (GET_CODE (insn) == CALL_INSN)
7975 /* We can't predict what a call will do to volatile memory. */
7976 memset (next_io, 0, sizeof (struct frv_io));
7977 next_is_end_p = false;
7978 CLEAR_HARD_REG_SET (used_regs);
7980 else if (INSN_P (insn))
7981 switch (recog_memoized (insn))
7983 case CODE_FOR_optional_membar_qi:
7984 case CODE_FOR_optional_membar_hi:
7985 case CODE_FOR_optional_membar_si:
7986 case CODE_FOR_optional_membar_di:
7990 /* Local information isn't enough to decide whether this
7991 membar is needed. Stash it away for later. */
7992 *last_membar = insn;
7993 frv_extract_membar (next_io, insn);
7994 next_is_end_p = false;
7998 /* Check whether the I/O operation before INSN could be
7999 reordered with one described by NEXT_IO. If it can't,
8000 INSN will not be needed. */
8001 struct frv_io prev_io;
8003 frv_extract_membar (&prev_io, insn);
8004 if (frv_io_fixed_order_p (&prev_io, next_io))
8008 ";; [Local] Removing membar %d since order"
8009 " of accesses is guaranteed\n",
8010 INSN_UID (next_membar));
8012 insn = NEXT_INSN (insn);
8013 delete_insn (next_membar);
8021 /* Invalidate NEXT_IO's address if it depends on something that
8022 is clobbered by INSN. */
8023 if (next_io->var_address)
8024 note_stores (PATTERN (insn), frv_io_check_address,
8025 &next_io->var_address);
8027 /* If the next membar is associated with a __builtin_read,
8028 see if INSN reads from that address. If it does, and if
8029 the destination register is used before the next I/O access,
8030 there is no need for the membar. */
8031 set = PATTERN (insn);
8032 if (next_io->type == FRV_IO_READ
8033 && next_io->var_address != 0
8035 && GET_CODE (set) == SET
8036 && GET_CODE (SET_DEST (set)) == REG
8037 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8041 src = SET_SRC (set);
8042 if (GET_CODE (src) == ZERO_EXTEND)
8043 src = XEXP (src, 0);
8045 if (GET_CODE (src) == MEM
8046 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8050 ";; [Local] Removing membar %d since the target"
8051 " of %d is used before the I/O operation\n",
8052 INSN_UID (next_membar), INSN_UID (insn));
8054 if (next_membar == *last_membar)
8057 delete_insn (next_membar);
8062 /* If INSN has volatile references, forget about any registers
8063 that are used after it. Otherwise forget about uses that
8064 are (or might be) defined by INSN. */
8065 if (volatile_refs_p (PATTERN (insn)))
8066 CLEAR_HARD_REG_SET (used_regs);
8068 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8070 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8075 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8076 FIRST_IO[X] describes the first operation performed by basic block X. */
8079 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8082 struct frv_io this_io, next_io;
8086 /* We need to keep the membar if there is an edge to the exit block. */
8087 FOR_EACH_EDGE (succ, ei, bb->succs)
8088 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8089 if (succ->dest == EXIT_BLOCK_PTR)
8092 /* Work out the union of all successor blocks. */
8093 ei = ei_start (bb->succs);
8094 ei_cond (ei, &succ);
8095 /* next_io = first_io[bb->succ->dest->index]; */
8096 next_io = first_io[succ->dest->index];
8097 ei = ei_start (bb->succs);
8098 if (ei_cond (ei, &succ))
8100 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8101 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8102 frv_io_union (&next_io, &first_io[succ->dest->index]);
8107 frv_extract_membar (&this_io, membar);
8108 if (frv_io_fixed_order_p (&this_io, &next_io))
8112 ";; [Global] Removing membar %d since order of accesses"
8113 " is guaranteed\n", INSN_UID (membar));
8115 delete_insn (membar);
8119 /* Remove redundant membars from the current function. */
8122 frv_optimize_membar (void)
8125 struct frv_io *first_io;
8128 compute_bb_for_insn ();
8129 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8130 last_membar = XCNEWVEC (rtx, last_basic_block);
8133 frv_optimize_membar_local (bb, &first_io[bb->index],
8134 &last_membar[bb->index]);
8137 if (last_membar[bb->index] != 0)
8138 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8144 /* Used by frv_reorg to keep track of the current packet's address. */
8145 static unsigned int frv_packet_address;
8147 /* If the current packet falls through to a label, try to pad the packet
8148 with nops in order to fit the label's alignment requirements. */
8151 frv_align_label (void)
8153 unsigned int alignment, target, nop;
8154 rtx x, last, barrier, label;
8156 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8157 maximum alignment of that packet, LABEL to the last label between
8158 the packets, and BARRIER to the last barrier. */
8159 last = frv_packet.insns[frv_packet.num_insns - 1];
8160 label = barrier = 0;
8162 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8166 unsigned int subalign = 1 << label_to_alignment (x);
8167 alignment = MAX (alignment, subalign);
8174 /* If -malign-labels, and the packet falls through to an unaligned
8175 label, try introducing a nop to align that label to 8 bytes. */
8176 if (TARGET_ALIGN_LABELS
8179 && frv_packet.num_insns < frv_packet.issue_rate)
8180 alignment = MAX (alignment, 8);
8182 /* Advance the address to the end of the current packet. */
8183 frv_packet_address += frv_packet.num_insns * 4;
8185 /* Work out the target address, after alignment. */
8186 target = (frv_packet_address + alignment - 1) & -alignment;
8188 /* If the packet falls through to the label, try to find an efficient
8189 padding sequence. */
8192 /* First try adding nops to the current packet. */
8193 for (nop = 0; nop < frv_num_nops; nop++)
8194 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8196 frv_insert_nop_in_packet (frv_nops[nop]);
8197 frv_packet_address += 4;
8200 /* If we still haven't reached the target, add some new packets that
8201 contain only nops. If there are two types of nop, insert an
8202 alternating sequence of frv_nops[0] and frv_nops[1], which will
8203 lead to packets like:
8210 etc. Just emit frv_nops[0] if that's the only nop we have. */
8211 last = frv_packet.insns[frv_packet.num_insns - 1];
8213 while (frv_packet_address < target)
8215 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8216 frv_packet_address += 4;
8217 if (frv_num_nops > 1)
8222 frv_packet_address = target;
8225 /* Subroutine of frv_reorg, called after each packet has been constructed
8229 frv_reorg_packet (void)
8231 frv_fill_unused_units (GROUP_I);
8232 frv_fill_unused_units (GROUP_FM);
8236 /* Add an instruction with pattern NOP to frv_nops[]. */
8239 frv_register_nop (rtx nop)
8241 nop = make_insn_raw (nop);
8242 NEXT_INSN (nop) = 0;
8243 PREV_INSN (nop) = 0;
8244 frv_nops[frv_num_nops++] = nop;
8247 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8248 into packets and check whether we need to insert nops in order to
8249 fulfill the processor's issue requirements. Also, if the user has
8250 requested a certain alignment for a label, try to meet that alignment
8251 by inserting nops in the previous packet. */
8256 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8257 frv_optimize_membar ();
8260 frv_register_nop (gen_nop ());
8262 frv_register_nop (gen_mnop ());
8263 if (TARGET_HARD_FLOAT)
8264 frv_register_nop (gen_fnop ());
8266 /* Estimate the length of each branch. Although this may change after
8267 we've inserted nops, it will only do so in big functions. */
8268 shorten_branches (get_insns ());
8270 frv_packet_address = 0;
8271 frv_for_each_packet (frv_reorg_packet);
8274 #define def_builtin(name, type, code) \
8275 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8277 struct builtin_description
8279 enum insn_code icode;
8281 enum frv_builtins code;
8282 enum rtx_code comparison;
8286 /* Media intrinsics that take a single, constant argument. */
8288 static struct builtin_description bdesc_set[] =
8290 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8293 /* Media intrinsics that take just one argument. */
8295 static struct builtin_description bdesc_1arg[] =
8297 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8298 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8299 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8300 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8301 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8302 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8305 /* Media intrinsics that take two arguments. */
8307 static struct builtin_description bdesc_2arg[] =
8309 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8310 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8311 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8312 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8313 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8314 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8315 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8316 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8317 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8318 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8319 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8320 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8321 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8322 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8323 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8324 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8325 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8326 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8327 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8328 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8329 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8330 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8331 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8332 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8333 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8334 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8335 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8338 /* Integer intrinsics that take two arguments and have no return value. */
8340 static struct builtin_description bdesc_int_void2arg[] =
8342 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8343 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8344 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8347 static struct builtin_description bdesc_prefetches[] =
8349 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8350 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8353 /* Media intrinsics that take two arguments, the first being an ACC number. */
8355 static struct builtin_description bdesc_cut[] =
8357 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8358 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8359 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8362 /* Two-argument media intrinsics with an immediate second argument. */
8364 static struct builtin_description bdesc_2argimm[] =
8366 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8367 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8368 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8369 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8370 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8371 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8372 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8373 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8374 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8375 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8376 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8377 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8378 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8379 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8380 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8381 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8382 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8385 /* Media intrinsics that take two arguments and return void, the first argument
8386 being a pointer to 4 words in memory. */
8388 static struct builtin_description bdesc_void2arg[] =
8390 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8391 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8394 /* Media intrinsics that take three arguments, the first being a const_int that
8395 denotes an accumulator, and that return void. */
8397 static struct builtin_description bdesc_void3arg[] =
8399 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8400 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8401 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8402 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8403 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8404 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8405 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8406 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8407 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8408 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8409 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8410 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8411 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8412 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8413 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8414 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8415 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8416 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8417 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8418 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8419 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8420 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8421 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8422 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8423 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8426 /* Media intrinsics that take two accumulator numbers as argument and
8429 static struct builtin_description bdesc_voidacc[] =
8431 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8432 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8433 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8434 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8435 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8436 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8439 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8440 a normal move and the ICODE is for the membar. */
8442 static struct builtin_description bdesc_loads[] =
8444 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8445 FRV_BUILTIN_READ8, 0, 0 },
8446 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8447 FRV_BUILTIN_READ16, 0, 0 },
8448 { CODE_FOR_optional_membar_si, "__builtin_read32",
8449 FRV_BUILTIN_READ32, 0, 0 },
8450 { CODE_FOR_optional_membar_di, "__builtin_read64",
8451 FRV_BUILTIN_READ64, 0, 0 }
8454 /* Likewise stores. */
8456 static struct builtin_description bdesc_stores[] =
8458 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8459 FRV_BUILTIN_WRITE8, 0, 0 },
8460 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8461 FRV_BUILTIN_WRITE16, 0, 0 },
8462 { CODE_FOR_optional_membar_si, "__builtin_write32",
8463 FRV_BUILTIN_WRITE32, 0, 0 },
8464 { CODE_FOR_optional_membar_di, "__builtin_write64",
8465 FRV_BUILTIN_WRITE64, 0, 0 },
8468 /* Initialize media builtins. */
8471 frv_init_builtins (void)
8473 tree endlink = void_list_node;
8474 tree accumulator = integer_type_node;
8475 tree integer = integer_type_node;
8476 tree voidt = void_type_node;
8477 tree uhalf = short_unsigned_type_node;
8478 tree sword1 = long_integer_type_node;
8479 tree uword1 = long_unsigned_type_node;
8480 tree sword2 = long_long_integer_type_node;
8481 tree uword2 = long_long_unsigned_type_node;
8482 tree uword4 = build_pointer_type (uword1);
8483 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8484 tree ubyte = unsigned_char_type_node;
8485 tree iacc = integer_type_node;
8487 #define UNARY(RET, T1) \
8488 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8490 #define BINARY(RET, T1, T2) \
8491 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8492 tree_cons (NULL_TREE, T2, endlink)))
8494 #define TRINARY(RET, T1, T2, T3) \
8495 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8496 tree_cons (NULL_TREE, T2, \
8497 tree_cons (NULL_TREE, T3, endlink))))
8499 #define QUAD(RET, T1, T2, T3, T4) \
8500 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8501 tree_cons (NULL_TREE, T2, \
8502 tree_cons (NULL_TREE, T3, \
8503 tree_cons (NULL_TREE, T4, endlink)))))
8505 tree void_ftype_void = build_function_type (voidt, endlink);
8507 tree void_ftype_acc = UNARY (voidt, accumulator);
8508 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8509 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8510 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8511 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8512 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8513 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8514 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8515 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8517 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8518 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8519 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8520 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8521 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8522 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8523 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8524 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8525 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8526 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8527 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8529 tree sw1_ftype_int = UNARY (sword1, integer);
8530 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8531 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8533 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8534 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8535 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8536 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8537 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8538 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8540 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8541 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8542 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8543 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8544 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8545 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8546 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8547 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8548 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8549 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8550 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8551 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8552 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8553 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8554 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8555 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8556 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8558 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8559 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8560 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8561 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8562 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8563 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8564 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8565 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8566 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8567 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8568 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8569 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8570 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8571 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8572 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8573 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8574 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8575 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8576 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8577 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8578 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8579 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8580 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8581 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8582 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8583 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8584 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8585 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8586 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8587 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8588 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8589 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8590 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8591 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8592 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8593 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8594 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8595 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8596 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8597 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8598 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8599 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8600 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8601 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8602 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8603 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8604 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8605 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8606 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8607 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8608 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8609 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8610 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8611 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8612 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8613 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8614 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8615 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8616 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8617 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8618 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8619 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8620 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8621 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8622 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8623 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8624 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8625 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8626 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8627 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8628 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8629 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8630 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8631 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8632 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8633 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8634 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8635 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8636 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8637 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8638 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8639 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8640 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8641 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8642 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8643 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8644 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8645 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8646 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8647 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8648 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8649 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8650 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8651 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8652 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8653 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8654 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8655 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8656 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8657 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8658 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8659 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8660 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8661 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8662 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8663 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8664 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8665 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8667 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8668 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8669 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8670 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8678 /* Set the names for various arithmetic operations according to the
8681 frv_init_libfuncs (void)
8683 set_optab_libfunc (smod_optab, SImode, "__modi");
8684 set_optab_libfunc (umod_optab, SImode, "__umodi");
8686 set_optab_libfunc (add_optab, DImode, "__addll");
8687 set_optab_libfunc (sub_optab, DImode, "__subll");
8688 set_optab_libfunc (smul_optab, DImode, "__mulll");
8689 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8690 set_optab_libfunc (smod_optab, DImode, "__modll");
8691 set_optab_libfunc (umod_optab, DImode, "__umodll");
8692 set_optab_libfunc (and_optab, DImode, "__andll");
8693 set_optab_libfunc (ior_optab, DImode, "__orll");
8694 set_optab_libfunc (xor_optab, DImode, "__xorll");
8695 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8697 set_optab_libfunc (add_optab, SFmode, "__addf");
8698 set_optab_libfunc (sub_optab, SFmode, "__subf");
8699 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8700 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8702 set_optab_libfunc (add_optab, DFmode, "__addd");
8703 set_optab_libfunc (sub_optab, DFmode, "__subd");
8704 set_optab_libfunc (smul_optab, DFmode, "__muld");
8705 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8707 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8708 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8710 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8711 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8712 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8713 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8715 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8716 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8717 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8718 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8720 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8721 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8722 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8723 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8726 /* Convert an integer constant to an accumulator register. ICODE is the
8727 code of the target instruction, OPNUM is the number of the
8728 accumulator operand and OPVAL is the constant integer. Try both
8729 ACC and ACCG registers; only report an error if neither fit the
8733 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8738 /* ACCs and ACCGs are implicit global registers if media intrinsics
8739 are being used. We set up this lazily to avoid creating lots of
8740 unnecessary call_insn rtl in non-media code. */
8741 for (i = 0; i <= ACC_MASK; i++)
8742 if ((i & ACC_MASK) == i)
8743 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8745 if (GET_CODE (opval) != CONST_INT)
8747 error ("accumulator is not a constant integer");
8750 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8752 error ("accumulator number is out of bounds");
8756 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8757 ACC_FIRST + INTVAL (opval));
8758 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8759 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8761 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8763 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8769 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8772 static enum machine_mode
8773 frv_matching_accg_mode (enum machine_mode mode)
8791 /* Given that a __builtin_read or __builtin_write function is accessing
8792 address ADDRESS, return the value that should be used as operand 1
8796 frv_io_address_cookie (rtx address)
8798 return (GET_CODE (address) == CONST_INT
8799 ? GEN_INT (INTVAL (address) / 8 * 8)
8803 /* Return the accumulator guard that should be paired with accumulator
8804 register ACC. The mode of the returned register is in the same
8805 class as ACC, but is four times smaller. */
8808 frv_matching_accg_for_acc (rtx acc)
8810 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8811 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8814 /* Read the requested argument from the call EXP given by INDEX.
8815 Return the value as an rtx. */
8818 frv_read_argument (tree exp, unsigned int index)
8820 return expand_expr (CALL_EXPR_ARG (exp, index),
8821 NULL_RTX, VOIDmode, 0);
8824 /* Like frv_read_argument, but interpret the argument as the number
8825 of an IACC register and return a (reg:MODE ...) rtx for it. */
8828 frv_read_iacc_argument (enum machine_mode mode, tree call,
8834 op = frv_read_argument (call, index);
8835 if (GET_CODE (op) != CONST_INT
8837 || INTVAL (op) > IACC_LAST - IACC_FIRST
8838 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8840 error ("invalid IACC argument");
8844 /* IACCs are implicit global registers. We set up this lazily to
8845 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8847 regno = INTVAL (op) + IACC_FIRST;
8848 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8849 global_regs[regno + i] = 1;
8851 return gen_rtx_REG (mode, regno);
8854 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8855 The instruction should require a constant operand of some sort. The
8856 function prints an error if OPVAL is not valid. */
8859 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8861 if (GET_CODE (opval) != CONST_INT)
8863 error ("%qs expects a constant argument", insn_data[icode].name);
8866 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8868 error ("constant argument out of range for %qs", insn_data[icode].name);
8874 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8875 if it's not null, has the right mode, and satisfies operand 0's
8879 frv_legitimize_target (enum insn_code icode, rtx target)
8881 enum machine_mode mode = insn_data[icode].operand[0].mode;
8884 || GET_MODE (target) != mode
8885 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8886 return gen_reg_rtx (mode);
8891 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8892 check whether ARG satisfies the operand's constraints. If it doesn't,
8893 copy ARG to a temporary register and return that. Otherwise return ARG
8897 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8899 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8901 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8904 return copy_to_mode_reg (mode, arg);
8907 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8910 frv_volatile_memref (enum machine_mode mode, rtx arg)
8914 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8915 MEM_VOLATILE_P (mem) = 1;
8919 /* Expand builtins that take a single, constant argument. At the moment,
8920 only MHDSETS falls into this category. */
8923 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8926 rtx op0 = frv_read_argument (call, 0);
8928 if (! frv_check_constant_argument (icode, 1, op0))
8931 target = frv_legitimize_target (icode, target);
8932 pat = GEN_FCN (icode) (target, op0);
8940 /* Expand builtins that take one operand. */
8943 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8946 rtx op0 = frv_read_argument (call, 0);
8948 target = frv_legitimize_target (icode, target);
8949 op0 = frv_legitimize_argument (icode, 1, op0);
8950 pat = GEN_FCN (icode) (target, op0);
8958 /* Expand builtins that take two operands. */
8961 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8964 rtx op0 = frv_read_argument (call, 0);
8965 rtx op1 = frv_read_argument (call, 1);
8967 target = frv_legitimize_target (icode, target);
8968 op0 = frv_legitimize_argument (icode, 1, op0);
8969 op1 = frv_legitimize_argument (icode, 2, op1);
8970 pat = GEN_FCN (icode) (target, op0, op1);
8978 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8982 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8985 rtx op0 = frv_read_argument (call, 0);
8986 rtx op1 = frv_read_argument (call, 1);
8989 target = frv_legitimize_target (icode, target);
8990 op0 = frv_int_to_acc (icode, 1, op0);
8994 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8996 if (! frv_check_constant_argument (icode, 2, op1))
9000 op1 = frv_legitimize_argument (icode, 2, op1);
9002 op2 = frv_matching_accg_for_acc (op0);
9003 pat = GEN_FCN (icode) (target, op0, op1, op2);
9011 /* Expand builtins that take two operands and the second is immediate. */
9014 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
9017 rtx op0 = frv_read_argument (call, 0);
9018 rtx op1 = frv_read_argument (call, 1);
9020 if (! frv_check_constant_argument (icode, 2, op1))
9023 target = frv_legitimize_target (icode, target);
9024 op0 = frv_legitimize_argument (icode, 1, op0);
9025 pat = GEN_FCN (icode) (target, op0, op1);
9033 /* Expand builtins that take two operands, the first operand being a pointer to
9034 ints and return void. */
9037 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9040 rtx op0 = frv_read_argument (call, 0);
9041 rtx op1 = frv_read_argument (call, 1);
9042 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9045 if (GET_CODE (op0) != MEM)
9049 if (! offsettable_address_p (0, mode0, op0))
9051 reg = gen_reg_rtx (Pmode);
9052 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9055 op0 = gen_rtx_MEM (SImode, reg);
9058 addr = XEXP (op0, 0);
9059 if (! offsettable_address_p (0, mode0, addr))
9060 addr = copy_to_mode_reg (Pmode, op0);
9062 op0 = change_address (op0, V4SImode, addr);
9063 op1 = frv_legitimize_argument (icode, 1, op1);
9064 pat = GEN_FCN (icode) (op0, op1);
9072 /* Expand builtins that take two long operands and return void. */
9075 frv_expand_int_void2arg (enum insn_code icode, tree call)
9078 rtx op0 = frv_read_argument (call, 0);
9079 rtx op1 = frv_read_argument (call, 1);
9081 op0 = frv_legitimize_argument (icode, 1, op0);
9082 op1 = frv_legitimize_argument (icode, 1, op1);
9083 pat = GEN_FCN (icode) (op0, op1);
9091 /* Expand prefetch builtins. These take a single address as argument. */
9094 frv_expand_prefetches (enum insn_code icode, tree call)
9097 rtx op0 = frv_read_argument (call, 0);
9099 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9107 /* Expand builtins that take three operands and return void. The first
9108 argument must be a constant that describes a pair or quad accumulators. A
9109 fourth argument is created that is the accumulator guard register that
9110 corresponds to the accumulator. */
9113 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9116 rtx op0 = frv_read_argument (call, 0);
9117 rtx op1 = frv_read_argument (call, 1);
9118 rtx op2 = frv_read_argument (call, 2);
9121 op0 = frv_int_to_acc (icode, 0, op0);
9125 op1 = frv_legitimize_argument (icode, 1, op1);
9126 op2 = frv_legitimize_argument (icode, 2, op2);
9127 op3 = frv_matching_accg_for_acc (op0);
9128 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9136 /* Expand builtins that perform accumulator-to-accumulator operations.
9137 These builtins take two accumulator numbers as argument and return
9141 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9144 rtx op0 = frv_read_argument (call, 0);
9145 rtx op1 = frv_read_argument (call, 1);
9149 op0 = frv_int_to_acc (icode, 0, op0);
9153 op1 = frv_int_to_acc (icode, 1, op1);
9157 op2 = frv_matching_accg_for_acc (op0);
9158 op3 = frv_matching_accg_for_acc (op1);
9159 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9167 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9168 membar and TARGET_MODE is the mode that the loaded value should have. */
9171 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9172 tree call, rtx target)
9174 rtx op0 = frv_read_argument (call, 0);
9175 rtx cookie = frv_io_address_cookie (op0);
9177 if (target == 0 || !REG_P (target))
9178 target = gen_reg_rtx (target_mode);
9179 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9180 convert_move (target, op0, 1);
9181 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9182 cfun->machine->has_membar_p = 1;
9186 /* Likewise __builtin_write* functions. */
9189 frv_expand_store_builtin (enum insn_code icode, tree call)
9191 rtx op0 = frv_read_argument (call, 0);
9192 rtx op1 = frv_read_argument (call, 1);
9193 rtx cookie = frv_io_address_cookie (op0);
9195 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9196 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9197 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9198 cfun->machine->has_membar_p = 1;
9202 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9203 each argument forms one word of the two double-word input registers.
9204 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9205 to put the return value. */
9208 frv_expand_mdpackh_builtin (tree call, rtx target)
9210 enum insn_code icode = CODE_FOR_mdpackh;
9212 rtx arg1 = frv_read_argument (call, 0);
9213 rtx arg2 = frv_read_argument (call, 1);
9214 rtx arg3 = frv_read_argument (call, 2);
9215 rtx arg4 = frv_read_argument (call, 3);
9217 target = frv_legitimize_target (icode, target);
9218 op0 = gen_reg_rtx (DImode);
9219 op1 = gen_reg_rtx (DImode);
9221 /* The high half of each word is not explicitly initialized, so indicate
9222 that the input operands are not live before this point. */
9226 /* Move each argument into the low half of its associated input word. */
9227 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9228 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9229 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9230 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9232 pat = GEN_FCN (icode) (target, op0, op1);
9240 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9241 number as argument. */
9244 frv_expand_mclracc_builtin (tree call)
9246 enum insn_code icode = CODE_FOR_mclracc;
9248 rtx op0 = frv_read_argument (call, 0);
9250 op0 = frv_int_to_acc (icode, 0, op0);
9254 pat = GEN_FCN (icode) (op0);
9261 /* Expand builtins that take no arguments. */
9264 frv_expand_noargs_builtin (enum insn_code icode)
9266 rtx pat = GEN_FCN (icode) (const0_rtx);
9273 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9274 number or accumulator guard number as argument and return an SI integer. */
9277 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9280 rtx target = gen_reg_rtx (SImode);
9281 rtx op0 = frv_read_argument (call, 0);
9283 op0 = frv_int_to_acc (icode, 1, op0);
9287 pat = GEN_FCN (icode) (target, op0);
9295 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9296 accumulator guard as their first argument and an SImode value as their
9300 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9303 rtx op0 = frv_read_argument (call, 0);
9304 rtx op1 = frv_read_argument (call, 1);
9306 op0 = frv_int_to_acc (icode, 0, op0);
9310 op1 = frv_legitimize_argument (icode, 1, op1);
9311 pat = GEN_FCN (icode) (op0, op1);
9318 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9319 to move DImode values into and out of IACC0. */
9322 frv_split_iacc_move (rtx dest, rtx src)
9324 enum machine_mode inner;
9327 inner = GET_MODE (dest);
9328 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9329 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9330 simplify_gen_subreg (SImode, src, inner, i));
9333 /* Expand builtins. */
9336 frv_expand_builtin (tree exp,
9338 rtx subtarget ATTRIBUTE_UNUSED,
9339 enum machine_mode mode ATTRIBUTE_UNUSED,
9340 int ignore ATTRIBUTE_UNUSED)
9342 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9343 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9345 struct builtin_description *d;
9347 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9349 error ("media functions are not available unless -mmedia is used");
9355 case FRV_BUILTIN_MCOP1:
9356 case FRV_BUILTIN_MCOP2:
9357 case FRV_BUILTIN_MDUNPACKH:
9358 case FRV_BUILTIN_MBTOHE:
9359 if (! TARGET_MEDIA_REV1)
9361 error ("this media function is only available on the fr500");
9366 case FRV_BUILTIN_MQXMACHS:
9367 case FRV_BUILTIN_MQXMACXHS:
9368 case FRV_BUILTIN_MQMACXHS:
9369 case FRV_BUILTIN_MADDACCS:
9370 case FRV_BUILTIN_MSUBACCS:
9371 case FRV_BUILTIN_MASACCS:
9372 case FRV_BUILTIN_MDADDACCS:
9373 case FRV_BUILTIN_MDSUBACCS:
9374 case FRV_BUILTIN_MDASACCS:
9375 case FRV_BUILTIN_MABSHS:
9376 case FRV_BUILTIN_MDROTLI:
9377 case FRV_BUILTIN_MCPLHI:
9378 case FRV_BUILTIN_MCPLI:
9379 case FRV_BUILTIN_MDCUTSSI:
9380 case FRV_BUILTIN_MQSATHS:
9381 case FRV_BUILTIN_MHSETLOS:
9382 case FRV_BUILTIN_MHSETLOH:
9383 case FRV_BUILTIN_MHSETHIS:
9384 case FRV_BUILTIN_MHSETHIH:
9385 case FRV_BUILTIN_MHDSETS:
9386 case FRV_BUILTIN_MHDSETH:
9387 if (! TARGET_MEDIA_REV2)
9389 error ("this media function is only available on the fr400"
9395 case FRV_BUILTIN_SMASS:
9396 case FRV_BUILTIN_SMSSS:
9397 case FRV_BUILTIN_SMU:
9398 case FRV_BUILTIN_ADDSS:
9399 case FRV_BUILTIN_SUBSS:
9400 case FRV_BUILTIN_SLASS:
9401 case FRV_BUILTIN_SCUTSS:
9402 case FRV_BUILTIN_IACCreadll:
9403 case FRV_BUILTIN_IACCreadl:
9404 case FRV_BUILTIN_IACCsetll:
9405 case FRV_BUILTIN_IACCsetl:
9406 if (!TARGET_FR405_BUILTINS)
9408 error ("this builtin function is only available"
9409 " on the fr405 and fr450");
9414 case FRV_BUILTIN_PREFETCH:
9415 if (!TARGET_FR500_FR550_BUILTINS)
9417 error ("this builtin function is only available on the fr500"
9423 case FRV_BUILTIN_MQLCLRHS:
9424 case FRV_BUILTIN_MQLMTHS:
9425 case FRV_BUILTIN_MQSLLHI:
9426 case FRV_BUILTIN_MQSRAHI:
9427 if (!TARGET_MEDIA_FR450)
9429 error ("this builtin function is only available on the fr450");
9438 /* Expand unique builtins. */
9442 case FRV_BUILTIN_MTRAP:
9443 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9445 case FRV_BUILTIN_MCLRACC:
9446 return frv_expand_mclracc_builtin (exp);
9448 case FRV_BUILTIN_MCLRACCA:
9450 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9452 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9454 case FRV_BUILTIN_MRDACC:
9455 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9457 case FRV_BUILTIN_MRDACCG:
9458 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9460 case FRV_BUILTIN_MWTACC:
9461 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9463 case FRV_BUILTIN_MWTACCG:
9464 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9466 case FRV_BUILTIN_MDPACKH:
9467 return frv_expand_mdpackh_builtin (exp, target);
9469 case FRV_BUILTIN_IACCreadll:
9471 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9472 if (target == 0 || !REG_P (target))
9473 target = gen_reg_rtx (DImode);
9474 frv_split_iacc_move (target, src);
9478 case FRV_BUILTIN_IACCreadl:
9479 return frv_read_iacc_argument (SImode, exp, 0);
9481 case FRV_BUILTIN_IACCsetll:
9483 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9484 rtx src = frv_read_argument (exp, 1);
9485 frv_split_iacc_move (dest, force_reg (DImode, src));
9489 case FRV_BUILTIN_IACCsetl:
9491 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9492 rtx src = frv_read_argument (exp, 1);
9493 emit_move_insn (dest, force_reg (SImode, src));
9501 /* Expand groups of builtins. */
9503 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9504 if (d->code == fcode)
9505 return frv_expand_set_builtin (d->icode, exp, target);
9507 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9508 if (d->code == fcode)
9509 return frv_expand_unop_builtin (d->icode, exp, target);
9511 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9512 if (d->code == fcode)
9513 return frv_expand_binop_builtin (d->icode, exp, target);
9515 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9516 if (d->code == fcode)
9517 return frv_expand_cut_builtin (d->icode, exp, target);
9519 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9520 if (d->code == fcode)
9521 return frv_expand_binopimm_builtin (d->icode, exp, target);
9523 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9524 if (d->code == fcode)
9525 return frv_expand_voidbinop_builtin (d->icode, exp);
9527 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9528 if (d->code == fcode)
9529 return frv_expand_voidtriop_builtin (d->icode, exp);
9531 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9532 if (d->code == fcode)
9533 return frv_expand_voidaccop_builtin (d->icode, exp);
9535 for (i = 0, d = bdesc_int_void2arg;
9536 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9537 if (d->code == fcode)
9538 return frv_expand_int_void2arg (d->icode, exp);
9540 for (i = 0, d = bdesc_prefetches;
9541 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9542 if (d->code == fcode)
9543 return frv_expand_prefetches (d->icode, exp);
9545 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9546 if (d->code == fcode)
9547 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9550 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9551 if (d->code == fcode)
9552 return frv_expand_store_builtin (d->icode, exp);
9558 frv_in_small_data_p (const_tree decl)
9561 const_tree section_name;
9563 /* Don't apply the -G flag to internal compiler structures. We
9564 should leave such structures in the main data section, partly
9565 for efficiency and partly because the size of some of them
9566 (such as C++ typeinfos) is not known until later. */
9567 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9570 /* If we already know which section the decl should be in, see if
9571 it's a small data section. */
9572 section_name = DECL_SECTION_NAME (decl);
9575 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9576 if (frv_string_begins_with (section_name, ".sdata"))
9578 if (frv_string_begins_with (section_name, ".sbss"))
9583 size = int_size_in_bytes (TREE_TYPE (decl));
9584 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9591 frv_rtx_costs (rtx x,
9592 int code ATTRIBUTE_UNUSED,
9593 int outer_code ATTRIBUTE_UNUSED,
9595 bool speed ATTRIBUTE_UNUSED)
9597 if (outer_code == MEM)
9599 /* Don't differentiate between memory addresses. All the ones
9600 we accept have equal cost. */
9601 *total = COSTS_N_INSNS (0);
9608 /* Make 12-bit integers really cheap. */
9609 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9620 *total = COSTS_N_INSNS (2);
9634 if (GET_MODE (x) == SImode)
9635 *total = COSTS_N_INSNS (1);
9636 else if (GET_MODE (x) == DImode)
9637 *total = COSTS_N_INSNS (2);
9639 *total = COSTS_N_INSNS (3);
9643 if (GET_MODE (x) == SImode)
9644 *total = COSTS_N_INSNS (2);
9646 *total = COSTS_N_INSNS (6); /* guess */
9653 *total = COSTS_N_INSNS (18);
9657 *total = COSTS_N_INSNS (3);
9666 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9668 switch_to_section (ctors_section);
9669 assemble_align (POINTER_SIZE);
9672 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9677 assemble_integer_with_op ("\t.picptr\t", symbol);
9681 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9683 switch_to_section (dtors_section);
9684 assemble_align (POINTER_SIZE);
9687 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9692 assemble_integer_with_op ("\t.picptr\t", symbol);
9695 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9698 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9699 int incoming ATTRIBUTE_UNUSED)
9701 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9704 #define TLS_BIAS (2048 - 16)
9706 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9707 We need to emit DTP-relative relocations. */
9710 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9712 gcc_assert (size == 4);
9713 fputs ("\t.picptr\ttlsmoff(", file);
9714 /* We want the unbiased TLS offset, so add the bias to the
9715 expression, such that the implicit biasing cancels out. */
9716 output_addr_const (file, plus_constant (x, TLS_BIAS));