1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static int frv_default_flags_for_cpu (void);
268 static int frv_string_begins_with (const_tree, const char *);
269 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
270 static void frv_print_operand_memory_reference_reg
272 static void frv_print_operand_memory_reference (FILE *, rtx, int);
273 static int frv_print_operand_jump_hint (rtx);
274 static const char *comparison_string (enum rtx_code, rtx);
275 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
276 static rtx single_set_pattern (rtx);
277 static int frv_function_contains_far_jump (void);
278 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
282 static rtx frv_frame_offset_rtx (int);
283 static rtx frv_frame_mem (enum machine_mode, rtx, int);
284 static rtx frv_dwarf_store (rtx, int);
285 static void frv_frame_insn (rtx, rtx);
286 static void frv_frame_access (frv_frame_accessor_t*,
288 static void frv_frame_access_multi (frv_frame_accessor_t*,
290 static void frv_frame_access_standard_regs (enum frv_stack_op,
292 static struct machine_function *frv_init_machine_status (void);
293 static rtx frv_int_to_acc (enum insn_code, int, rtx);
294 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
295 static rtx frv_read_argument (tree, unsigned int);
296 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
297 static int frv_check_constant_argument (enum insn_code, int, rtx);
298 static rtx frv_legitimize_target (enum insn_code, rtx);
299 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
300 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
301 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
302 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
303 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
304 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
305 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
306 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
308 static rtx frv_expand_int_void2arg (enum insn_code, tree);
309 static rtx frv_expand_prefetches (enum insn_code, tree);
310 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
311 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
312 static rtx frv_expand_mclracc_builtin (tree);
313 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
314 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
315 static rtx frv_expand_noargs_builtin (enum insn_code);
316 static void frv_split_iacc_move (rtx, rtx);
317 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
318 static int frv_clear_registers_used (rtx *, void *);
319 static void frv_ifcvt_add_insn (rtx, rtx, int);
320 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
321 static rtx frv_ifcvt_load_value (rtx, rtx);
322 static int frv_acc_group_1 (rtx *, void *);
323 static unsigned int frv_insn_unit (rtx);
324 static bool frv_issues_to_branch_unit_p (rtx);
325 static int frv_cond_flags (rtx);
326 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
327 static int frv_registers_conflict_p_1 (rtx *, void *);
328 static bool frv_registers_conflict_p (rtx);
329 static void frv_registers_update_1 (rtx, const_rtx, void *);
330 static void frv_registers_update (rtx);
331 static void frv_start_packet (void);
332 static void frv_start_packet_block (void);
333 static void frv_finish_packet (void (*) (void));
334 static bool frv_pack_insn_p (rtx);
335 static void frv_add_insn_to_packet (rtx);
336 static void frv_insert_nop_in_packet (rtx);
337 static bool frv_for_each_packet (void (*) (void));
338 static bool frv_sort_insn_group_1 (enum frv_insn_group,
339 unsigned int, unsigned int,
340 unsigned int, unsigned int,
342 static int frv_compare_insns (const void *, const void *);
343 static void frv_sort_insn_group (enum frv_insn_group);
344 static void frv_reorder_packet (void);
345 static void frv_fill_unused_units (enum frv_insn_group);
346 static void frv_align_label (void);
347 static void frv_reorg_packet (void);
348 static void frv_register_nop (rtx);
349 static void frv_reorg (void);
350 static void frv_pack_insns (void);
351 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
352 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
353 static bool frv_assemble_integer (rtx, unsigned, int);
354 static void frv_init_builtins (void);
355 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
356 static void frv_init_libfuncs (void);
357 static bool frv_in_small_data_p (const_tree);
358 static void frv_asm_output_mi_thunk
359 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
360 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
363 static rtx frv_expand_builtin_saveregs (void);
364 static void frv_expand_builtin_va_start (tree, rtx);
365 static bool frv_rtx_costs (rtx, int, int, int*, bool);
366 static void frv_asm_out_constructor (rtx, int);
367 static void frv_asm_out_destructor (rtx, int);
368 static bool frv_function_symbol_referenced_p (rtx);
369 static bool frv_cannot_force_const_mem (rtx);
370 static const char *unspec_got_name (int);
371 static void frv_output_const_unspec (FILE *,
372 const struct frv_unspec *);
373 static bool frv_function_ok_for_sibcall (tree, tree);
374 static rtx frv_struct_value_rtx (tree, int);
375 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
376 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
378 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
380 static bool frv_secondary_reload (bool, rtx, enum reg_class,
382 secondary_reload_info *);
384 /* Allow us to easily change the default for -malloc-cc. */
385 #ifndef DEFAULT_NO_ALLOC_CC
386 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
388 #define MASK_DEFAULT_ALLOC_CC 0
391 /* Initialize the GCC target structure. */
392 #undef TARGET_ASM_FUNCTION_PROLOGUE
393 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
394 #undef TARGET_ASM_FUNCTION_EPILOGUE
395 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
396 #undef TARGET_ASM_INTEGER
397 #define TARGET_ASM_INTEGER frv_assemble_integer
398 #undef TARGET_DEFAULT_TARGET_FLAGS
399 #define TARGET_DEFAULT_TARGET_FLAGS \
400 (MASK_DEFAULT_ALLOC_CC \
407 #undef TARGET_HANDLE_OPTION
408 #define TARGET_HANDLE_OPTION frv_handle_option
409 #undef TARGET_INIT_BUILTINS
410 #define TARGET_INIT_BUILTINS frv_init_builtins
411 #undef TARGET_EXPAND_BUILTIN
412 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
413 #undef TARGET_INIT_LIBFUNCS
414 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
415 #undef TARGET_IN_SMALL_DATA_P
416 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
417 #undef TARGET_RTX_COSTS
418 #define TARGET_RTX_COSTS frv_rtx_costs
419 #undef TARGET_ASM_CONSTRUCTOR
420 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
421 #undef TARGET_ASM_DESTRUCTOR
422 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
424 #undef TARGET_ASM_OUTPUT_MI_THUNK
425 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
426 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
427 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
429 #undef TARGET_SCHED_ISSUE_RATE
430 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
432 #undef TARGET_LEGITIMIZE_ADDRESS
433 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
435 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
436 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
437 #undef TARGET_CANNOT_FORCE_CONST_MEM
438 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
440 #undef TARGET_HAVE_TLS
441 #define TARGET_HAVE_TLS HAVE_AS_TLS
443 #undef TARGET_STRUCT_VALUE_RTX
444 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
445 #undef TARGET_MUST_PASS_IN_STACK
446 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
447 #undef TARGET_PASS_BY_REFERENCE
448 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
449 #undef TARGET_ARG_PARTIAL_BYTES
450 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
452 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
453 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
454 #undef TARGET_SETUP_INCOMING_VARARGS
455 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
456 #undef TARGET_MACHINE_DEPENDENT_REORG
457 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
459 #undef TARGET_EXPAND_BUILTIN_VA_START
460 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
463 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
464 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
467 #undef TARGET_SECONDARY_RELOAD
468 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
470 struct gcc_target targetm = TARGET_INITIALIZER;
472 #define FRV_SYMBOL_REF_TLS_P(RTX) \
473 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
476 /* Any function call that satisfies the machine-independent
477 requirements is eligible on FR-V. */
480 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
481 tree exp ATTRIBUTE_UNUSED)
486 /* Return true if SYMBOL is a small data symbol and relocation RELOC
487 can be used to access it directly in a load or store. */
489 static FRV_INLINE bool
490 frv_small_data_reloc_p (rtx symbol, int reloc)
492 return (GET_CODE (symbol) == SYMBOL_REF
493 && SYMBOL_REF_SMALL_P (symbol)
494 && (!TARGET_FDPIC || flag_pic == 1)
495 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
498 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
502 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
504 if (GET_CODE (x) == CONST)
508 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
510 unspec->offset += INTVAL (XEXP (x, 1));
513 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
515 unspec->symbol = XVECEXP (x, 0, 0);
516 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
518 if (unspec->offset == 0)
521 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
522 && unspec->offset > 0
523 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
530 /* Decide whether we can force certain constants to memory. If we
531 decide we can't, the caller should be able to cope with it in
534 We never allow constants to be forced into memory for TARGET_FDPIC.
535 This is necessary for several reasons:
537 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
538 target-independent code will try to force them into the constant
539 pool, thus leading to infinite recursion.
541 2. We can never introduce new constant pool references during reload.
542 Any such reference would require use of the pseudo FDPIC register.
544 3. We can't represent a constant added to a function pointer (which is
545 not the same as a pointer to a function+constant).
547 4. In many cases, it's more efficient to calculate the constant in-line. */
550 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
555 /* Implement TARGET_HANDLE_OPTION. */
558 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
563 if (strcmp (arg, "simple") == 0)
564 frv_cpu_type = FRV_CPU_SIMPLE;
565 else if (strcmp (arg, "tomcat") == 0)
566 frv_cpu_type = FRV_CPU_TOMCAT;
567 else if (strcmp (arg, "fr550") == 0)
568 frv_cpu_type = FRV_CPU_FR550;
569 else if (strcmp (arg, "fr500") == 0)
570 frv_cpu_type = FRV_CPU_FR500;
571 else if (strcmp (arg, "fr450") == 0)
572 frv_cpu_type = FRV_CPU_FR450;
573 else if (strcmp (arg, "fr405") == 0)
574 frv_cpu_type = FRV_CPU_FR405;
575 else if (strcmp (arg, "fr400") == 0)
576 frv_cpu_type = FRV_CPU_FR400;
577 else if (strcmp (arg, "fr300") == 0)
578 frv_cpu_type = FRV_CPU_FR300;
579 else if (strcmp (arg, "frv") == 0)
580 frv_cpu_type = FRV_CPU_GENERIC;
591 frv_default_flags_for_cpu (void)
593 switch (frv_cpu_type)
595 case FRV_CPU_GENERIC:
596 return MASK_DEFAULT_FRV;
599 return MASK_DEFAULT_FR550;
603 return MASK_DEFAULT_FR500;
606 return MASK_DEFAULT_FR450;
610 return MASK_DEFAULT_FR400;
614 return MASK_DEFAULT_SIMPLE;
621 /* Sometimes certain combinations of command options do not make
622 sense on a particular target machine. You can define a macro
623 `OVERRIDE_OPTIONS' to take account of this. This macro, if
624 defined, is executed once just after all the command options have
627 Don't use this macro to turn on various extra optimizations for
628 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
631 frv_override_options (void)
636 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
638 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
639 linker about linking pic and non-pic code. */
642 if (!flag_pic) /* -fPIC */
645 if (! g_switch_set) /* -G0 */
652 /* A C expression whose value is a register class containing hard
653 register REGNO. In general there is more than one such class;
654 choose a class which is "minimal", meaning that no smaller class
655 also contains the register. */
657 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
659 enum reg_class rclass;
663 int gpr_reg = regno - GPR_FIRST;
665 if (gpr_reg == GR8_REG)
668 else if (gpr_reg == GR9_REG)
671 else if (gpr_reg == GR14_REG)
672 rclass = FDPIC_FPTR_REGS;
674 else if (gpr_reg == FDPIC_REGNO)
677 else if ((gpr_reg & 3) == 0)
680 else if ((gpr_reg & 1) == 0)
687 else if (FPR_P (regno))
689 int fpr_reg = regno - GPR_FIRST;
690 if ((fpr_reg & 3) == 0)
691 rclass = QUAD_FPR_REGS;
693 else if ((fpr_reg & 1) == 0)
700 else if (regno == LR_REGNO)
703 else if (regno == LCR_REGNO)
706 else if (ICC_P (regno))
709 else if (FCC_P (regno))
712 else if (ICR_P (regno))
715 else if (FCR_P (regno))
718 else if (ACC_P (regno))
720 int r = regno - ACC_FIRST;
722 rclass = QUAD_ACC_REGS;
723 else if ((r & 1) == 0)
724 rclass = EVEN_ACC_REGS;
729 else if (ACCG_P (regno))
735 regno_reg_class[regno] = rclass;
738 /* Check for small data option */
740 g_switch_value = SDATA_DEFAULT_SIZE;
742 /* A C expression which defines the machine-dependent operand
743 constraint letters for register classes. If CHAR is such a
744 letter, the value should be the register class corresponding to
745 it. Otherwise, the value should be `NO_REGS'. The register
746 letter `r', corresponding to class `GENERAL_REGS', will not be
747 passed to this macro; you do not need to handle it.
749 The following letters are unavailable, due to being used as
754 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
755 'Q', 'R', 'S', 'T', 'U'
757 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
759 for (i = 0; i < 256; i++)
760 reg_class_from_letter[i] = NO_REGS;
762 reg_class_from_letter['a'] = ACC_REGS;
763 reg_class_from_letter['b'] = EVEN_ACC_REGS;
764 reg_class_from_letter['c'] = CC_REGS;
765 reg_class_from_letter['d'] = GPR_REGS;
766 reg_class_from_letter['e'] = EVEN_REGS;
767 reg_class_from_letter['f'] = FPR_REGS;
768 reg_class_from_letter['h'] = FEVEN_REGS;
769 reg_class_from_letter['l'] = LR_REG;
770 reg_class_from_letter['q'] = QUAD_REGS;
771 reg_class_from_letter['t'] = ICC_REGS;
772 reg_class_from_letter['u'] = FCC_REGS;
773 reg_class_from_letter['v'] = ICR_REGS;
774 reg_class_from_letter['w'] = FCR_REGS;
775 reg_class_from_letter['x'] = QUAD_FPR_REGS;
776 reg_class_from_letter['y'] = LCR_REG;
777 reg_class_from_letter['z'] = SPR_REGS;
778 reg_class_from_letter['A'] = QUAD_ACC_REGS;
779 reg_class_from_letter['B'] = ACCG_REGS;
780 reg_class_from_letter['C'] = CR_REGS;
781 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
782 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
784 /* There is no single unaligned SI op for PIC code. Sometimes we
785 need to use ".4byte" and sometimes we need to use ".picptr".
786 See frv_assemble_integer for details. */
787 if (flag_pic || TARGET_FDPIC)
788 targetm.asm_out.unaligned_op.si = 0;
790 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
791 target_flags |= MASK_LINKED_FP;
793 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
794 target_flags |= MASK_OPTIMIZE_MEMBAR;
796 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
797 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
799 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
800 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
802 init_machine_status = frv_init_machine_status;
806 /* Some machines may desire to change what optimizations are performed for
807 various optimization levels. This macro, if defined, is executed once just
808 after the optimization level is determined and before the remainder of the
809 command options have been parsed. Values set in this macro are used as the
810 default values for the other command line options.
812 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
813 `-O' is specified, and 0 if neither is specified.
815 SIZE is nonzero if `-Os' is specified, 0 otherwise.
817 You should not use this macro to change options that are not
818 machine-specific. These should uniformly selected by the same optimization
819 level on all supported machines. Use this macro to enable machine-specific
822 *Do not examine `write_symbols' in this macro!* The debugging options are
823 *not supposed to alter the generated code. */
825 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
826 scheduling pass at the current time. */
828 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
832 #ifdef DISABLE_SCHED2
833 flag_schedule_insns_after_reload = 0;
842 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
845 frv_string_begins_with (const_tree name, const char *prefix)
847 const int prefix_len = strlen (prefix);
849 /* Remember: NAME's length includes the null terminator. */
850 return (TREE_STRING_LENGTH (name) > prefix_len
851 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
854 /* Zero or more C statements that may conditionally modify two variables
855 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
856 been initialized from the two preceding macros.
858 This is necessary in case the fixed or call-clobbered registers depend on
861 You need not define this macro if it has no work to do.
863 If the usage of an entire class of registers depends on the target flags,
864 you may indicate this to GCC by using this macro to modify `fixed_regs' and
865 `call_used_regs' to 1 for each of the registers in the classes which should
866 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
867 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
869 (However, if this class is not included in `GENERAL_REGS' and all of the
870 insn patterns whose constraints permit this class are controlled by target
871 switches, then GCC will automatically avoid using these registers when the
872 target switches are opposed to them.) */
875 frv_conditional_register_usage (void)
879 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
880 fixed_regs[i] = call_used_regs[i] = 1;
882 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
883 fixed_regs[i] = call_used_regs[i] = 1;
885 /* Reserve the registers used for conditional execution. At present, we need
886 1 ICC and 1 ICR register. */
887 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
888 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
892 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
893 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
894 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
895 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
899 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
900 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
903 /* If -fpic, SDA_BASE_REG is the PIC register. */
904 if (g_switch_value == 0 && !flag_pic)
905 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
908 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
914 * Compute the stack frame layout
917 * +---------------+-----------------------+-----------------------+
918 * |Register |type |caller-save/callee-save|
919 * +---------------+-----------------------+-----------------------+
920 * |GR0 |Zero register | - |
921 * |GR1 |Stack pointer(SP) | - |
922 * |GR2 |Frame pointer(FP) | - |
923 * |GR3 |Hidden parameter | caller save |
924 * |GR4-GR7 | - | caller save |
925 * |GR8-GR13 |Argument register | caller save |
926 * |GR14-GR15 | - | caller save |
927 * |GR16-GR31 | - | callee save |
928 * |GR32-GR47 | - | caller save |
929 * |GR48-GR63 | - | callee save |
930 * |FR0-FR15 | - | caller save |
931 * |FR16-FR31 | - | callee save |
932 * |FR32-FR47 | - | caller save |
933 * |FR48-FR63 | - | callee save |
934 * +---------------+-----------------------+-----------------------+
938 * SP-> |-----------------------------------|
940 * |-----------------------------------|
941 * | Register save area |
942 * |-----------------------------------|
943 * | Local variable save area |
944 * FP-> |-----------------------------------|
946 * |-----------------------------------|
947 * | Hidden parameter save area |
948 * |-----------------------------------|
949 * | Return address(LR) storage area |
950 * |-----------------------------------|
951 * | Padding for alignment |
952 * |-----------------------------------|
953 * | Register argument area |
954 * OLD SP-> |-----------------------------------|
956 * |-----------------------------------|
959 * Argument area/Parameter area:
961 * When a function is called, this area is used for argument transfer. When
962 * the argument is set up by the caller function, this area is referred to as
963 * the argument area. When the argument is referenced by the callee function,
964 * this area is referred to as the parameter area. The area is allocated when
965 * all arguments cannot be placed on the argument register at the time of
968 * Register save area:
970 * This is a register save area that must be guaranteed for the caller
971 * function. This area is not secured when the register save operation is not
974 * Local variable save area:
976 * This is the area for local variables and temporary variables.
980 * This area stores the FP value of the caller function.
982 * Hidden parameter save area:
984 * This area stores the start address of the return value storage
985 * area for a struct/union return function.
986 * When a struct/union is used as the return value, the caller
987 * function stores the return value storage area start address in
988 * register GR3 and passes it to the caller function.
989 * The callee function interprets the address stored in the GR3
990 * as the return value storage area start address.
991 * When register GR3 needs to be saved into memory, the callee
992 * function saves it in the hidden parameter save area. This
993 * area is not secured when the save operation is not needed.
995 * Return address(LR) storage area:
997 * This area saves the LR. The LR stores the address of a return to the caller
998 * function for the purpose of function calling.
1000 * Argument register area:
1002 * This area saves the argument register. This area is not secured when the
1003 * save operation is not needed.
1007 * Arguments, the count of which equals the count of argument registers (6
1008 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1009 * function. When a struct/union return function is called, the return value
1010 * area address is stored in register GR3. Arguments not placed in the
1011 * argument registers will be stored in the stack argument area for transfer
1012 * purposes. When an 8-byte type argument is to be delivered using registers,
1013 * it is divided into two and placed in two registers for transfer. When
1014 * argument registers must be saved to memory, the callee function secures an
1015 * argument register save area in the stack. In this case, a continuous
1016 * argument register save area must be established in the parameter area. The
1017 * argument register save area must be allocated as needed to cover the size of
1018 * the argument register to be saved. If the function has a variable count of
1019 * arguments, it saves all argument registers in the argument register save
1022 * Argument Extension Format:
1024 * When an argument is to be stored in the stack, its type is converted to an
1025 * extended type in accordance with the individual argument type. The argument
1026 * is freed by the caller function after the return from the callee function is
1029 * +-----------------------+---------------+------------------------+
1030 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1031 * +-----------------------+---------------+------------------------+
1033 * |signed char |int | 4 |
1034 * |unsigned char |int | 4 |
1035 * |[signed] short int |int | 4 |
1036 * |unsigned short int |int | 4 |
1037 * |[signed] int |No extension | 4 |
1038 * |unsigned int |No extension | 4 |
1039 * |[signed] long int |No extension | 4 |
1040 * |unsigned long int |No extension | 4 |
1041 * |[signed] long long int |No extension | 8 |
1042 * |unsigned long long int |No extension | 8 |
1043 * |float |double | 8 |
1044 * |double |No extension | 8 |
1045 * |long double |No extension | 8 |
1046 * |pointer |No extension | 4 |
1047 * |struct/union |- | 4 (*1) |
1048 * +-----------------------+---------------+------------------------+
1050 * When a struct/union is to be delivered as an argument, the caller copies it
1051 * to the local variable area and delivers the address of that area.
1055 * +-------------------------------+----------------------+
1056 * |Return Value Type |Return Value Interface|
1057 * +-------------------------------+----------------------+
1059 * |[signed|unsigned] char |GR8 |
1060 * |[signed|unsigned] short int |GR8 |
1061 * |[signed|unsigned] int |GR8 |
1062 * |[signed|unsigned] long int |GR8 |
1064 * |[signed|unsigned] long long int|GR8 & GR9 |
1066 * |double |GR8 & GR9 |
1067 * |long double |GR8 & GR9 |
1068 * |struct/union |(*1) |
1069 * +-------------------------------+----------------------+
1071 * When a struct/union is used as the return value, the caller function stores
1072 * the start address of the return value storage area into GR3 and then passes
1073 * it to the callee function. The callee function interprets GR3 as the start
1074 * address of the return value storage area. When this address needs to be
1075 * saved in memory, the callee function secures the hidden parameter save area
1076 * and saves the address in that area.
1080 frv_stack_info (void)
1082 static frv_stack_t info, zero_info;
1083 frv_stack_t *info_ptr = &info;
1084 tree fndecl = current_function_decl;
1092 /* If we've already calculated the values and reload is complete,
1094 if (frv_stack_cache)
1095 return frv_stack_cache;
1097 /* Zero all fields. */
1100 /* Set up the register range information. */
1101 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1102 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1103 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1104 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1106 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1107 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1108 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1109 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1111 info_ptr->regs[STACK_REGS_LR].name = "lr";
1112 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1113 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1114 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1116 info_ptr->regs[STACK_REGS_CC].name = "cc";
1117 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1118 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1119 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1121 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1122 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1123 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1125 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1126 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1127 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1128 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1129 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1131 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1132 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1133 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1134 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1136 info_ptr->regs[STACK_REGS_FP].name = "fp";
1137 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1138 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1139 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1141 /* Determine if this is a stdarg function. If so, allocate space to store
1148 /* Find the last argument, and see if it is __builtin_va_alist. */
1149 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1151 next_arg = TREE_CHAIN (cur_arg);
1152 if (next_arg == (tree)0)
1154 if (DECL_NAME (cur_arg)
1155 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1163 /* Iterate over all of the register ranges. */
1164 for (range = 0; range < STACK_REGS_MAX; range++)
1166 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1167 int first = reg_ptr->first;
1168 int last = reg_ptr->last;
1170 int size_2words = 0;
1173 /* Calculate which registers need to be saved & save area size. */
1177 for (regno = first; regno <= last; regno++)
1179 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1180 || (crtl->calls_eh_return
1181 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1182 || (!TARGET_FDPIC && flag_pic
1183 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1185 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1186 size_1word += UNITS_PER_WORD;
1191 /* Calculate whether we need to create a frame after everything else
1192 has been processed. */
1197 if (df_regs_ever_live_p (LR_REGNO)
1199 /* This is set for __builtin_return_address, etc. */
1200 || cfun->machine->frame_needed
1201 || (TARGET_LINKED_FP && frame_pointer_needed)
1202 || (!TARGET_FDPIC && flag_pic
1203 && crtl->uses_pic_offset_table))
1205 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1206 size_1word += UNITS_PER_WORD;
1210 case STACK_REGS_STDARG:
1213 /* If this is a stdarg function with a non varardic
1214 argument split between registers and the stack,
1215 adjust the saved registers downward. */
1216 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1219 for (regno = first; regno <= last; regno++)
1221 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1222 size_1word += UNITS_PER_WORD;
1225 info_ptr->stdarg_size = size_1word;
1229 case STACK_REGS_STRUCT:
1230 if (cfun->returns_struct)
1232 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1233 size_1word += UNITS_PER_WORD;
1241 /* If this is a field, it only takes one word. */
1242 if (reg_ptr->field_p)
1243 size_1word = UNITS_PER_WORD;
1245 /* Determine which register pairs can be saved together. */
1246 else if (reg_ptr->dword_p && TARGET_DWORD)
1248 for (regno = first; regno < last; regno += 2)
1250 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1252 size_2words += 2 * UNITS_PER_WORD;
1253 size_1word -= 2 * UNITS_PER_WORD;
1254 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1255 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1260 reg_ptr->size_1word = size_1word;
1261 reg_ptr->size_2words = size_2words;
1263 if (! reg_ptr->special_p)
1265 info_ptr->regs_size_1word += size_1word;
1266 info_ptr->regs_size_2words += size_2words;
1271 /* Set up the sizes of each each field in the frame body, making the sizes
1272 of each be divisible by the size of a dword if dword operations might
1273 be used, or the size of a word otherwise. */
1274 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1276 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1277 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1278 + info_ptr->regs_size_1word,
1280 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1282 info_ptr->pretend_size = crtl->args.pretend_args_size;
1284 /* Work out the size of the frame, excluding the header. Both the frame
1285 body and register parameter area will be dword-aligned. */
1286 info_ptr->total_size
1287 = (ADDR_ALIGN (info_ptr->parameter_size
1288 + info_ptr->regs_size
1289 + info_ptr->vars_size,
1291 + ADDR_ALIGN (info_ptr->pretend_size
1292 + info_ptr->stdarg_size,
1293 2 * UNITS_PER_WORD));
1295 /* See if we need to create a frame at all, if so add header area. */
1296 if (info_ptr->total_size > 0
1297 || frame_pointer_needed
1298 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1299 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1301 offset = info_ptr->parameter_size;
1302 info_ptr->header_size = 4 * UNITS_PER_WORD;
1303 info_ptr->total_size += 4 * UNITS_PER_WORD;
1305 /* Calculate the offsets to save normal register pairs. */
1306 for (range = 0; range < STACK_REGS_MAX; range++)
1308 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1309 if (! reg_ptr->special_p)
1311 int first = reg_ptr->first;
1312 int last = reg_ptr->last;
1315 for (regno = first; regno <= last; regno++)
1316 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1317 && regno != FRAME_POINTER_REGNUM
1318 && (regno < FIRST_ARG_REGNUM
1319 || regno > LAST_ARG_REGNUM))
1321 info_ptr->reg_offset[regno] = offset;
1322 offset += 2 * UNITS_PER_WORD;
1327 /* Calculate the offsets to save normal single registers. */
1328 for (range = 0; range < STACK_REGS_MAX; range++)
1330 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1331 if (! reg_ptr->special_p)
1333 int first = reg_ptr->first;
1334 int last = reg_ptr->last;
1337 for (regno = first; regno <= last; regno++)
1338 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1339 && regno != FRAME_POINTER_REGNUM
1340 && (regno < FIRST_ARG_REGNUM
1341 || regno > LAST_ARG_REGNUM))
1343 info_ptr->reg_offset[regno] = offset;
1344 offset += UNITS_PER_WORD;
1349 /* Calculate the offset to save the local variables at. */
1350 offset = ADDR_ALIGN (offset, alignment);
1351 if (info_ptr->vars_size)
1353 info_ptr->vars_offset = offset;
1354 offset += info_ptr->vars_size;
1357 /* Align header to a dword-boundary. */
1358 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1360 /* Calculate the offsets in the fixed frame. */
1361 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1362 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1363 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1365 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1366 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1367 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1369 if (cfun->returns_struct)
1371 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1372 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1373 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1376 /* Calculate the offsets to store the arguments passed in registers
1377 for stdarg functions. The register pairs are first and the single
1378 register if any is last. The register save area starts on a
1380 if (info_ptr->stdarg_size)
1382 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1383 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1386 /* Skip the header. */
1387 offset += 4 * UNITS_PER_WORD;
1388 for (regno = first; regno <= last; regno++)
1390 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1392 info_ptr->reg_offset[regno] = offset;
1393 offset += 2 * UNITS_PER_WORD;
1395 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1397 info_ptr->reg_offset[regno] = offset;
1398 offset += UNITS_PER_WORD;
1404 if (reload_completed)
1405 frv_stack_cache = info_ptr;
1411 /* Print the information about the frv stack offsets, etc. when debugging. */
1414 frv_debug_stack (frv_stack_t *info)
1419 info = frv_stack_info ();
1421 fprintf (stderr, "\nStack information for function %s:\n",
1422 ((current_function_decl && DECL_NAME (current_function_decl))
1423 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1426 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1427 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1428 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1429 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1430 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1432 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1433 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1434 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1435 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1437 for (range = 0; range < STACK_REGS_MAX; range++)
1439 frv_stack_regs_t *regs = &(info->regs[range]);
1440 if ((regs->size_1word + regs->size_2words) > 0)
1442 int first = regs->first;
1443 int last = regs->last;
1446 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1447 regs->name, regs->size_1word + regs->size_2words,
1448 regs->size_1word, regs->size_2words);
1450 for (regno = first; regno <= last; regno++)
1452 if (info->save_p[regno] == REG_SAVE_1WORD)
1453 fprintf (stderr, " %s (%d)", reg_names[regno],
1454 info->reg_offset[regno]);
1456 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1457 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1458 reg_names[regno+1], info->reg_offset[regno]);
1461 fputc ('\n', stderr);
1471 /* Used during final to control the packing of insns. The value is
1472 1 if the current instruction should be packed with the next one,
1473 0 if it shouldn't or -1 if packing is disabled altogether. */
1475 static int frv_insn_packing_flag;
1477 /* True if the current function contains a far jump. */
1480 frv_function_contains_far_jump (void)
1482 rtx insn = get_insns ();
1484 && !(GET_CODE (insn) == JUMP_INSN
1485 /* Ignore tablejump patterns. */
1486 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1487 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1488 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1489 insn = NEXT_INSN (insn);
1490 return (insn != NULL);
1493 /* For the FRV, this function makes sure that a function with far jumps
1494 will return correctly. It also does the VLIW packing. */
1497 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1499 /* If no frame was created, check whether the function uses a call
1500 instruction to implement a far jump. If so, save the link in gr3 and
1501 replace all returns to LR with returns to GR3. GR3 is used because it
1502 is call-clobbered, because is not available to the register allocator,
1503 and because all functions that take a hidden argument pointer will have
1505 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1509 /* Just to check that the above comment is true. */
1510 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1512 /* Generate the instruction that saves the link register. */
1513 fprintf (file, "\tmovsg lr,gr3\n");
1515 /* Replace the LR with GR3 in *return_internal patterns. The insn
1516 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1517 simply emit a different assembly directive because bralr and jmpl
1518 execute in different units. */
1519 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1520 if (GET_CODE (insn) == JUMP_INSN)
1522 rtx pattern = PATTERN (insn);
1523 if (GET_CODE (pattern) == PARALLEL
1524 && XVECLEN (pattern, 0) >= 2
1525 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1526 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1528 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1529 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1530 SET_REGNO (address, GPR_FIRST + 3);
1537 /* Allow the garbage collector to free the nops created by frv_reorg. */
1538 memset (frv_nops, 0, sizeof (frv_nops));
1542 /* Return the next available temporary register in a given class. */
1545 frv_alloc_temp_reg (
1546 frv_tmp_reg_t *info, /* which registers are available */
1547 enum reg_class rclass, /* register class desired */
1548 enum machine_mode mode, /* mode to allocate register with */
1549 int mark_as_used, /* register not available after allocation */
1550 int no_abort) /* return NULL instead of aborting */
1552 int regno = info->next_reg[ (int)rclass ];
1553 int orig_regno = regno;
1554 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1559 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1560 && TEST_HARD_REG_BIT (info->regs, regno))
1563 if (++regno >= FIRST_PSEUDO_REGISTER)
1565 if (regno == orig_regno)
1567 gcc_assert (no_abort);
1572 nr = HARD_REGNO_NREGS (regno, mode);
1573 info->next_reg[ (int)rclass ] = regno + nr;
1576 for (i = 0; i < nr; i++)
1577 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1579 return gen_rtx_REG (mode, regno);
1583 /* Return an rtx with the value OFFSET, which will either be a register or a
1584 signed 12-bit integer. It can be used as the second operand in an "add"
1585 instruction, or as the index in a load or store.
1587 The function returns a constant rtx if OFFSET is small enough, otherwise
1588 it loads the constant into register OFFSET_REGNO and returns that. */
1590 frv_frame_offset_rtx (int offset)
1592 rtx offset_rtx = GEN_INT (offset);
1593 if (IN_RANGE_P (offset, -2048, 2047))
1597 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1598 if (IN_RANGE_P (offset, -32768, 32767))
1599 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1602 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1603 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1609 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1610 prologue and epilogue uses such expressions to access the stack. */
1612 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1614 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1616 frv_frame_offset_rtx (offset)));
1619 /* Generate a frame-related expression:
1621 (set REG (mem (plus (sp) (const_int OFFSET)))).
1623 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1624 instructions. Marking the expressions as frame-related is superfluous if
1625 the note contains just a single set. But if the note contains a PARALLEL
1626 or SEQUENCE that has several sets, each set must be individually marked
1627 as frame-related. */
1629 frv_dwarf_store (rtx reg, int offset)
1631 rtx set = gen_rtx_SET (VOIDmode,
1632 gen_rtx_MEM (GET_MODE (reg),
1633 plus_constant (stack_pointer_rtx,
1636 RTX_FRAME_RELATED_P (set) = 1;
1640 /* Emit a frame-related instruction whose pattern is PATTERN. The
1641 instruction is the last in a sequence that cumulatively performs the
1642 operation described by DWARF_PATTERN. The instruction is marked as
1643 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1646 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1648 rtx insn = emit_insn (pattern);
1649 RTX_FRAME_RELATED_P (insn) = 1;
1650 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1655 /* Emit instructions that transfer REG to or from the memory location (sp +
1656 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1657 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1658 function to store registers and only the epilogue uses it to load them.
1660 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1661 The generated instruction will use BASE as its base register. BASE may
1662 simply be the stack pointer, but if several accesses are being made to a
1663 region far away from the stack pointer, it may be more efficient to set
1664 up a temporary instead.
1666 Store instructions will be frame-related and will be annotated with the
1667 overall effect of the store. Load instructions will be followed by a
1668 (use) to prevent later optimizations from zapping them.
1670 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1671 as a temporary in such cases. */
1673 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1675 enum machine_mode mode = GET_MODE (reg);
1676 rtx mem = frv_frame_mem (mode,
1678 stack_offset - accessor->base_offset);
1680 if (accessor->op == FRV_LOAD)
1682 if (SPR_P (REGNO (reg)))
1684 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1685 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1686 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1690 /* We cannot use reg+reg addressing for DImode access. */
1692 && GET_CODE (XEXP (mem, 0)) == PLUS
1693 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1694 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1696 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1697 rtx insn = emit_move_insn (temp,
1698 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1699 XEXP (XEXP (mem, 0), 1)));
1700 mem = gen_rtx_MEM (DImode, temp);
1702 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1708 if (SPR_P (REGNO (reg)))
1710 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1711 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1712 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1713 frv_dwarf_store (reg, stack_offset));
1715 else if (mode == DImode)
1717 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1718 with a separate save for each register. */
1719 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1720 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1721 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1722 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1724 /* Also we cannot use reg+reg addressing. */
1725 if (GET_CODE (XEXP (mem, 0)) == PLUS
1726 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1727 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1729 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1730 rtx insn = emit_move_insn (temp,
1731 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1732 XEXP (XEXP (mem, 0), 1)));
1733 mem = gen_rtx_MEM (DImode, temp);
1736 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1737 gen_rtx_PARALLEL (VOIDmode,
1738 gen_rtvec (2, set1, set2)));
1741 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1742 frv_dwarf_store (reg, stack_offset));
1746 /* A function that uses frv_frame_access to transfer a group of registers to
1747 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1748 is the stack information generated by frv_stack_info, and REG_SET is the
1749 number of the register set to transfer. */
1751 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1755 frv_stack_regs_t *regs_info;
1758 regs_info = &info->regs[reg_set];
1759 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1760 if (info->save_p[regno])
1761 frv_frame_access (accessor,
1762 info->save_p[regno] == REG_SAVE_2WORDS
1763 ? gen_rtx_REG (DImode, regno)
1764 : gen_rtx_REG (SImode, regno),
1765 info->reg_offset[regno]);
1768 /* Save or restore callee-saved registers that are kept outside the frame
1769 header. The function saves the registers if OP is FRV_STORE and restores
1770 them if OP is FRV_LOAD. INFO is the stack information generated by
1773 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1775 frv_frame_accessor_t accessor;
1778 accessor.base = stack_pointer_rtx;
1779 accessor.base_offset = 0;
1780 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1781 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1782 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1786 /* Called after register allocation to add any instructions needed for the
1787 prologue. Using a prologue insn is favored compared to putting all of the
1788 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1789 it allows the scheduler to intermix instructions with the saves of
1790 the caller saved registers. In some cases, it might be necessary
1791 to emit a barrier instruction as the last insn to prevent such
1794 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1795 so that the debug info generation code can handle them properly. */
1797 frv_expand_prologue (void)
1799 frv_stack_t *info = frv_stack_info ();
1800 rtx sp = stack_pointer_rtx;
1801 rtx fp = frame_pointer_rtx;
1802 frv_frame_accessor_t accessor;
1804 if (TARGET_DEBUG_STACK)
1805 frv_debug_stack (info);
1807 if (info->total_size == 0)
1810 /* We're interested in three areas of the frame here:
1812 A: the register save area
1814 C: the header after B
1816 If the frame pointer isn't used, we'll have to set up A, B and C
1817 using the stack pointer. If the frame pointer is used, we'll access
1821 B: set up using sp or a temporary (see below)
1824 We set up B using the stack pointer if the frame is small enough.
1825 Otherwise, it's more efficient to copy the old stack pointer into a
1826 temporary and use that.
1828 Note that it's important to make sure the prologue and epilogue use the
1829 same registers to access A and C, since doing otherwise will confuse
1830 the aliasing code. */
1832 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1833 isn't used, the same method will serve for C. */
1834 accessor.op = FRV_STORE;
1835 if (frame_pointer_needed && info->total_size > 2048)
1839 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1840 accessor.base_offset = info->total_size;
1841 insn = emit_insn (gen_movsi (accessor.base, sp));
1845 accessor.base = stack_pointer_rtx;
1846 accessor.base_offset = 0;
1849 /* Allocate the stack space. */
1851 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1852 rtx dwarf_offset = GEN_INT (-info->total_size);
1854 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1857 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1860 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1861 and point the new one to that location. */
1862 if (frame_pointer_needed)
1864 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1866 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1867 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1869 rtx asm_src = plus_constant (accessor.base,
1870 fp_offset - accessor.base_offset);
1871 rtx dwarf_src = plus_constant (sp, fp_offset);
1873 /* Store the old frame pointer at (sp + FP_OFFSET). */
1874 frv_frame_access (&accessor, fp, fp_offset);
1876 /* Set up the new frame pointer. */
1877 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1878 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1880 /* Access region C from the frame pointer. */
1882 accessor.base_offset = fp_offset;
1885 /* Set up region C. */
1886 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1887 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1888 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1890 /* Set up region A. */
1891 frv_frame_access_standard_regs (FRV_STORE, info);
1893 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1894 scheduler from moving loads before the stores saving the registers. */
1895 if (info->stdarg_size > 0)
1896 emit_insn (gen_blockage ());
1898 /* Set up pic register/small data register for this function. */
1899 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1900 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1901 gen_rtx_REG (Pmode, LR_REGNO),
1902 gen_rtx_REG (SImode, OFFSET_REGNO)));
1906 /* Under frv, all of the work is done via frv_expand_epilogue, but
1907 this function provides a convenient place to do cleanup. */
1910 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1911 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1913 frv_stack_cache = (frv_stack_t *)0;
1915 /* Zap last used registers for conditional execution. */
1916 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1918 /* Release the bitmap of created insns. */
1919 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1923 /* Called after register allocation to add any instructions needed for the
1924 epilogue. Using an epilogue insn is favored compared to putting all of the
1925 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1926 it allows the scheduler to intermix instructions with the saves of
1927 the caller saved registers. In some cases, it might be necessary
1928 to emit a barrier instruction as the last insn to prevent such
1932 frv_expand_epilogue (bool emit_return)
1934 frv_stack_t *info = frv_stack_info ();
1935 rtx fp = frame_pointer_rtx;
1936 rtx sp = stack_pointer_rtx;
1940 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1942 /* Restore the stack pointer to its original value if alloca or the like
1944 if (! current_function_sp_is_unchanging)
1945 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1947 /* Restore the callee-saved registers that were used in this function. */
1948 frv_frame_access_standard_regs (FRV_LOAD, info);
1950 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1951 no return instruction should be emitted. */
1952 if (info->save_p[LR_REGNO])
1957 /* Use the same method to access the link register's slot as we did in
1958 the prologue. In other words, use the frame pointer if available,
1959 otherwise use the stack pointer.
1961 LR_OFFSET is the offset of the link register's slot from the start
1962 of the frame and MEM is a memory rtx for it. */
1963 lr_offset = info->reg_offset[LR_REGNO];
1964 if (frame_pointer_needed)
1965 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1967 mem = frv_frame_mem (Pmode, sp, lr_offset);
1969 /* Load the old link register into a GPR. */
1970 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1971 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1974 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1976 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1977 the load is preserved. */
1978 if (frame_pointer_needed)
1980 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1984 /* Deallocate the stack frame. */
1985 if (info->total_size != 0)
1987 rtx offset = frv_frame_offset_rtx (info->total_size);
1988 emit_insn (gen_stack_adjust (sp, sp, offset));
1991 /* If this function uses eh_return, add the final stack adjustment now. */
1992 if (crtl->calls_eh_return)
1993 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1996 emit_jump_insn (gen_epilogue_return (return_addr));
1999 rtx lr = return_addr;
2001 if (REGNO (return_addr) != LR_REGNO)
2003 lr = gen_rtx_REG (Pmode, LR_REGNO);
2004 emit_move_insn (lr, return_addr);
2012 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2015 frv_asm_output_mi_thunk (FILE *file,
2016 tree thunk_fndecl ATTRIBUTE_UNUSED,
2017 HOST_WIDE_INT delta,
2018 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2021 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2022 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2023 const char *name_jmp = reg_names[JUMP_REGNO];
2024 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2026 /* Do the add using an addi if possible. */
2027 if (IN_RANGE_P (delta, -2048, 2047))
2028 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2031 const char *const name_add = reg_names[TEMP_REGNO];
2032 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2033 parallel, delta, name_add);
2034 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2036 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2041 const char *name_pic = reg_names[FDPIC_REGNO];
2042 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2046 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2047 assemble_name (file, name_func);
2048 fprintf (file, "),%s\n", name_jmp);
2050 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2051 assemble_name (file, name_func);
2052 fprintf (file, "),%s\n", name_jmp);
2054 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2058 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2059 assemble_name (file, name_func);
2060 fprintf (file, "\t)), %s\n", name_jmp);
2065 fprintf (file, "\tsethi%s #hi(", parallel);
2066 assemble_name (file, name_func);
2067 fprintf (file, "),%s\n", name_jmp);
2069 fprintf (file, "\tsetlo #lo(");
2070 assemble_name (file, name_func);
2071 fprintf (file, "),%s\n", name_jmp);
2075 /* Use JUMP_REGNO as a temporary PIC register. */
2076 const char *name_lr = reg_names[LR_REGNO];
2077 const char *name_gppic = name_jmp;
2078 const char *name_tmp = reg_names[TEMP_REGNO];
2080 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2081 fprintf (file, "\tcall 1f\n");
2082 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2083 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2084 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2085 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2086 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2088 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2089 assemble_name (file, name_func);
2090 fprintf (file, "),%s\n", name_tmp);
2092 fprintf (file, "\tsetlo #gprello(");
2093 assemble_name (file, name_func);
2094 fprintf (file, "),%s\n", name_tmp);
2096 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2099 /* Jump to the function address. */
2100 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2104 /* A C expression which is nonzero if a function must have and use a frame
2105 pointer. This expression is evaluated in the reload pass. If its value is
2106 nonzero the function will have a frame pointer.
2108 The expression can in principle examine the current function and decide
2109 according to the facts, but on most machines the constant 0 or the constant
2110 1 suffices. Use 0 when the machine allows code to be generated with no
2111 frame pointer, and doing so saves some time or space. Use 1 when there is
2112 no possible advantage to avoiding a frame pointer.
2114 In certain cases, the compiler does not know how to produce valid code
2115 without a frame pointer. The compiler recognizes those cases and
2116 automatically gives the function a frame pointer regardless of what
2117 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2119 In a function that does not require a frame pointer, the frame pointer
2120 register can be allocated for ordinary usage, unless you mark it as a fixed
2121 register. See `FIXED_REGISTERS' for more information. */
2123 /* On frv, create a frame whenever we need to create stack. */
2126 frv_frame_pointer_required (void)
2128 /* If we forgoing the usual linkage requirements, we only need
2129 a frame pointer if the stack pointer might change. */
2130 if (!TARGET_LINKED_FP)
2131 return !current_function_sp_is_unchanging;
2133 if (! current_function_is_leaf)
2136 if (get_frame_size () != 0)
2142 if (!current_function_sp_is_unchanging)
2145 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2151 if (cfun->machine->frame_needed)
2158 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2159 initial difference between the specified pair of registers. This macro must
2160 be defined if `ELIMINABLE_REGS' is defined. */
2162 /* See frv_stack_info for more details on the frv stack frame. */
2165 frv_initial_elimination_offset (int from, int to)
2167 frv_stack_t *info = frv_stack_info ();
2170 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2171 ret = info->total_size - info->pretend_size;
2173 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2174 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2176 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2177 ret = (info->total_size
2178 - info->reg_offset[FRAME_POINTER_REGNUM]
2179 - info->pretend_size);
2184 if (TARGET_DEBUG_STACK)
2185 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2186 reg_names [from], reg_names[to], ret);
2192 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2195 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2196 enum machine_mode mode,
2197 tree type ATTRIBUTE_UNUSED,
2201 if (TARGET_DEBUG_ARG)
2203 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2204 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2208 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2211 frv_expand_builtin_saveregs (void)
2213 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2215 if (TARGET_DEBUG_ARG)
2216 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2219 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2223 /* Expand __builtin_va_start to do the va_start macro. */
2226 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2229 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2231 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2232 GEN_INT (UNITS_PER_WORD * num));
2234 if (TARGET_DEBUG_ARG)
2236 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2237 crtl->args.info, num);
2239 debug_rtx (nextarg);
2242 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2243 fold_convert (TREE_TYPE (valist),
2244 make_tree (sizetype, nextarg)));
2245 TREE_SIDE_EFFECTS (t) = 1;
2247 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2251 /* Expand a block move operation, and return 1 if successful. Return 0
2252 if we should let the compiler generate normal code.
2254 operands[0] is the destination
2255 operands[1] is the source
2256 operands[2] is the length
2257 operands[3] is the alignment */
2259 /* Maximum number of loads to do before doing the stores */
2260 #ifndef MAX_MOVE_REG
2261 #define MAX_MOVE_REG 4
2264 /* Maximum number of total loads to do. */
2265 #ifndef TOTAL_MOVE_REG
2266 #define TOTAL_MOVE_REG 8
2270 frv_expand_block_move (rtx operands[])
2272 rtx orig_dest = operands[0];
2273 rtx orig_src = operands[1];
2274 rtx bytes_rtx = operands[2];
2275 rtx align_rtx = operands[3];
2276 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2289 rtx stores[MAX_MOVE_REG];
2291 enum machine_mode mode;
2293 /* If this is not a fixed size move, just call memcpy. */
2297 /* This should be a fixed size alignment. */
2298 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2300 align = INTVAL (align_rtx);
2302 /* Anything to move? */
2303 bytes = INTVAL (bytes_rtx);
2307 /* Don't support real large moves. */
2308 if (bytes > TOTAL_MOVE_REG*align)
2311 /* Move the address into scratch registers. */
2312 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2313 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2315 num_reg = offset = 0;
2316 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2318 /* Calculate the correct offset for src/dest. */
2322 dest_addr = dest_reg;
2326 src_addr = plus_constant (src_reg, offset);
2327 dest_addr = plus_constant (dest_reg, offset);
2330 /* Generate the appropriate load and store, saving the stores
2332 if (bytes >= 4 && align >= 4)
2334 else if (bytes >= 2 && align >= 2)
2339 move_bytes = GET_MODE_SIZE (mode);
2340 tmp_reg = gen_reg_rtx (mode);
2341 src_mem = change_address (orig_src, mode, src_addr);
2342 dest_mem = change_address (orig_dest, mode, dest_addr);
2343 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2344 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2346 if (num_reg >= MAX_MOVE_REG)
2348 for (i = 0; i < num_reg; i++)
2349 emit_insn (stores[i]);
2354 for (i = 0; i < num_reg; i++)
2355 emit_insn (stores[i]);
2361 /* Expand a block clear operation, and return 1 if successful. Return 0
2362 if we should let the compiler generate normal code.
2364 operands[0] is the destination
2365 operands[1] is the length
2366 operands[3] is the alignment */
2369 frv_expand_block_clear (rtx operands[])
2371 rtx orig_dest = operands[0];
2372 rtx bytes_rtx = operands[1];
2373 rtx align_rtx = operands[3];
2374 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2383 enum machine_mode mode;
2385 /* If this is not a fixed size move, just call memcpy. */
2389 /* This should be a fixed size alignment. */
2390 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2392 align = INTVAL (align_rtx);
2394 /* Anything to move? */
2395 bytes = INTVAL (bytes_rtx);
2399 /* Don't support real large clears. */
2400 if (bytes > TOTAL_MOVE_REG*align)
2403 /* Move the address into a scratch register. */
2404 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2406 num_reg = offset = 0;
2407 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2409 /* Calculate the correct offset for src/dest. */
2410 dest_addr = ((offset == 0)
2412 : plus_constant (dest_reg, offset));
2414 /* Generate the appropriate store of gr0. */
2415 if (bytes >= 4 && align >= 4)
2417 else if (bytes >= 2 && align >= 2)
2422 clear_bytes = GET_MODE_SIZE (mode);
2423 dest_mem = change_address (orig_dest, mode, dest_addr);
2424 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2431 /* The following variable is used to output modifiers of assembler
2432 code of the current output insn. */
2434 static rtx *frv_insn_operands;
2436 /* The following function is used to add assembler insn code suffix .p
2437 if it is necessary. */
2440 frv_asm_output_opcode (FILE *f, const char *ptr)
2444 if (frv_insn_packing_flag <= 0)
2447 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2450 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2451 || (*ptr >= 'A' && *ptr <= 'Z')))
2453 int letter = *ptr++;
2456 frv_print_operand (f, frv_insn_operands [c], letter);
2457 while ((c = *ptr) >= '0' && c <= '9')
2469 /* Set up the packing bit for the current output insn. Note that this
2470 function is not called for asm insns. */
2473 frv_final_prescan_insn (rtx insn, rtx *opvec,
2474 int noperands ATTRIBUTE_UNUSED)
2478 if (frv_insn_packing_flag >= 0)
2480 frv_insn_operands = opvec;
2481 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2483 else if (recog_memoized (insn) >= 0
2484 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2485 /* Packing optimizations have been disabled, but INSN can only
2486 be issued in M1. Insert an mnop in M0. */
2487 fprintf (asm_out_file, "\tmnop.p\n");
2493 /* A C expression whose value is RTL representing the address in a stack frame
2494 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2495 an RTL expression for the address of the stack frame itself.
2497 If you don't define this macro, the default is to return the value of
2498 FRAMEADDR--that is, the stack frame address is also the address of the stack
2499 word that points to the previous frame. */
2501 /* The default is correct, but we need to make sure the frame gets created. */
2503 frv_dynamic_chain_address (rtx frame)
2505 cfun->machine->frame_needed = 1;
2510 /* A C expression whose value is RTL representing the value of the return
2511 address for the frame COUNT steps up from the current frame, after the
2512 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2513 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2516 The value of the expression must always be the correct address when COUNT is
2517 zero, but may be `NULL_RTX' if there is not way to determine the return
2518 address of other frames. */
2521 frv_return_addr_rtx (int count, rtx frame)
2525 cfun->machine->frame_needed = 1;
2526 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2529 /* Given a memory reference MEMREF, interpret the referenced memory as
2530 an array of MODE values, and return a reference to the element
2531 specified by INDEX. Assume that any pre-modification implicit in
2532 MEMREF has already happened.
2534 MEMREF must be a legitimate operand for modes larger than SImode.
2535 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2536 this function cannot handle. */
2538 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2540 rtx base = XEXP (memref, 0);
2541 if (GET_CODE (base) == PRE_MODIFY)
2542 base = XEXP (base, 0);
2543 return change_address (memref, mode,
2544 plus_constant (base, index * GET_MODE_SIZE (mode)));
2548 /* Print a memory address as an operand to reference that memory location. */
2550 frv_print_operand_address (FILE * stream, rtx x)
2552 if (GET_CODE (x) == MEM)
2555 switch (GET_CODE (x))
2558 fputs (reg_names [ REGNO (x)], stream);
2562 fprintf (stream, "%ld", (long) INTVAL (x));
2566 assemble_name (stream, XSTR (x, 0));
2571 output_addr_const (stream, x);
2575 /* Poorly constructed asm statements can trigger this alternative.
2576 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2577 frv_print_operand_memory_reference (stream, x, 0);
2584 fatal_insn ("bad insn to frv_print_operand_address:", x);
2589 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2591 int regno = true_regnum (x);
2593 fputs (reg_names[regno], stream);
2595 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2598 /* Print a memory reference suitable for the ld/st instructions. */
2601 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2603 struct frv_unspec unspec;
2607 switch (GET_CODE (x))
2614 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2616 x1 = XEXP (XEXP (x, 1), 1);
2626 if (GET_CODE (x0) == CONST_INT)
2634 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2643 else if (GET_CODE (x1) != CONST_INT)
2644 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2647 fputs ("@(", stream);
2649 fputs (reg_names[GPR_R0], stream);
2650 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2651 frv_print_operand_memory_reference_reg (stream, x0);
2653 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2655 fputs (",", stream);
2657 fputs (reg_names [GPR_R0], stream);
2661 switch (GET_CODE (x1))
2665 frv_print_operand_memory_reference_reg (stream, x1);
2669 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2673 if (!frv_const_unspec_p (x1, &unspec))
2674 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2675 frv_output_const_unspec (stream, &unspec);
2679 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2683 fputs (")", stream);
2687 /* Return 2 for likely branches and 0 for non-likely branches */
2689 #define FRV_JUMP_LIKELY 2
2690 #define FRV_JUMP_NOT_LIKELY 0
2693 frv_print_operand_jump_hint (rtx insn)
2698 HOST_WIDE_INT prob = -1;
2699 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2701 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2703 /* Assume any non-conditional jump is likely. */
2704 if (! any_condjump_p (insn))
2705 ret = FRV_JUMP_LIKELY;
2709 labelref = condjump_label (insn);
2712 rtx label = XEXP (labelref, 0);
2713 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2718 note = find_reg_note (insn, REG_BR_PROB, 0);
2720 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2724 prob = INTVAL (XEXP (note, 0));
2725 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2727 : FRV_JUMP_NOT_LIKELY);
2739 case UNKNOWN: direction = "unknown jump direction"; break;
2740 case BACKWARD: direction = "jump backward"; break;
2741 case FORWARD: direction = "jump forward"; break;
2745 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2746 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2747 (long)INSN_UID (insn), direction, (long)prob,
2748 (long)REG_BR_PROB_BASE, ret);
2756 /* Return the comparison operator to use for CODE given that the ICC
2760 comparison_string (enum rtx_code code, rtx op0)
2762 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2765 default: output_operand_lossage ("bad condition code");
2766 case EQ: return "eq";
2767 case NE: return "ne";
2768 case LT: return is_nz_p ? "n" : "lt";
2769 case LE: return "le";
2770 case GT: return "gt";
2771 case GE: return is_nz_p ? "p" : "ge";
2772 case LTU: return is_nz_p ? "no" : "c";
2773 case LEU: return is_nz_p ? "eq" : "ls";
2774 case GTU: return is_nz_p ? "ne" : "hi";
2775 case GEU: return is_nz_p ? "ra" : "nc";
2779 /* Print an operand to an assembler instruction.
2781 `%' followed by a letter and a digit says to output an operand in an
2782 alternate fashion. Four letters have standard, built-in meanings described
2783 below. The machine description macro `PRINT_OPERAND' can define additional
2784 letters with nonstandard meanings.
2786 `%cDIGIT' can be used to substitute an operand that is a constant value
2787 without the syntax that normally indicates an immediate operand.
2789 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2792 `%aDIGIT' can be used to substitute an operand as if it were a memory
2793 reference, with the actual operand treated as the address. This may be
2794 useful when outputting a "load address" instruction, because often the
2795 assembler syntax for such an instruction requires you to write the operand
2796 as if it were a memory reference.
2798 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2800 `%=' outputs a number which is unique to each instruction in the entire
2801 compilation. This is useful for making local labels to be referred to more
2802 than once in a single template that generates multiple assembler
2805 `%' followed by a punctuation character specifies a substitution that does
2806 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2807 assembler code. Other nonstandard cases can be defined in the
2808 `PRINT_OPERAND' macro. You must also define which punctuation characters
2809 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2812 frv_print_operand (FILE * file, rtx x, int code)
2814 struct frv_unspec unspec;
2815 HOST_WIDE_INT value;
2818 if (code != 0 && !ISALPHA (code))
2821 else if (GET_CODE (x) == CONST_INT)
2824 else if (GET_CODE (x) == CONST_DOUBLE)
2826 if (GET_MODE (x) == SFmode)
2831 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2832 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2836 else if (GET_MODE (x) == VOIDmode)
2837 value = CONST_DOUBLE_LOW (x);
2840 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2851 fputs (reg_names[GPR_R0], file);
2855 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2859 /* Output small data area base register (gr16). */
2860 fputs (reg_names[SDA_BASE_REG], file);
2864 /* Output pic register (gr17). */
2865 fputs (reg_names[PIC_REGNO], file);
2869 /* Output the temporary integer CCR register. */
2870 fputs (reg_names[ICR_TEMP], file);
2874 /* Output the temporary integer CC register. */
2875 fputs (reg_names[ICC_TEMP], file);
2878 /* case 'a': print an address. */
2881 /* Print appropriate test for integer branch false operation. */
2882 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2883 XEXP (x, 0)), file);
2887 /* Print appropriate test for integer branch true operation. */
2888 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2892 /* Print 1 for a NE and 0 for an EQ to give the final argument
2893 for a conditional instruction. */
2894 if (GET_CODE (x) == NE)
2897 else if (GET_CODE (x) == EQ)
2901 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2905 /* Print appropriate test for floating point branch false operation. */
2906 switch (GET_CODE (x))
2909 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2911 case EQ: fputs ("ne", file); break;
2912 case NE: fputs ("eq", file); break;
2913 case LT: fputs ("uge", file); break;
2914 case LE: fputs ("ug", file); break;
2915 case GT: fputs ("ule", file); break;
2916 case GE: fputs ("ul", file); break;
2921 /* Print appropriate test for floating point branch true operation. */
2922 switch (GET_CODE (x))
2925 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2927 case EQ: fputs ("eq", file); break;
2928 case NE: fputs ("ne", file); break;
2929 case LT: fputs ("lt", file); break;
2930 case LE: fputs ("le", file); break;
2931 case GT: fputs ("gt", file); break;
2932 case GE: fputs ("ge", file); break;
2937 /* Print appropriate GOT function. */
2938 if (GET_CODE (x) != CONST_INT)
2939 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2940 fputs (unspec_got_name (INTVAL (x)), file);
2944 /* Print 'i' if the operand is a constant, or is a memory reference that
2946 if (GET_CODE (x) == MEM)
2947 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2948 ? XEXP (XEXP (x, 0), 1)
2950 else if (GET_CODE (x) == PLUS)
2953 switch (GET_CODE (x))
2967 /* For jump instructions, print 'i' if the operand is a constant or
2968 is an expression that adds a constant. */
2969 if (GET_CODE (x) == CONST_INT)
2974 if (GET_CODE (x) == CONST_INT
2975 || (GET_CODE (x) == PLUS
2976 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2977 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2983 /* Print the lower register of a double word register pair */
2984 if (GET_CODE (x) == REG)
2985 fputs (reg_names[ REGNO (x)+1 ], file);
2987 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
2990 /* case 'l': print a LABEL_REF. */
2994 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2995 for the second word of double memory operations. */
2996 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2997 switch (GET_CODE (x))
3000 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3003 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3011 frv_print_operand_memory_reference (file, x, offset);
3017 /* Print the opcode of a command. */
3018 switch (GET_CODE (x))
3021 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3023 case PLUS: fputs ("add", file); break;
3024 case MINUS: fputs ("sub", file); break;
3025 case AND: fputs ("and", file); break;
3026 case IOR: fputs ("or", file); break;
3027 case XOR: fputs ("xor", file); break;
3028 case ASHIFT: fputs ("sll", file); break;
3029 case ASHIFTRT: fputs ("sra", file); break;
3030 case LSHIFTRT: fputs ("srl", file); break;
3034 /* case 'n': negate and print a constant int. */
3037 /* Print PIC label using operand as the number. */
3038 if (GET_CODE (x) != CONST_INT)
3039 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3041 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3045 /* Print 'u' if the operand is a update load/store. */
3046 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3051 /* If value is 0, print gr0, otherwise it must be a register. */
3052 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3053 fputs (reg_names[GPR_R0], file);
3055 else if (GET_CODE (x) == REG)
3056 fputs (reg_names [REGNO (x)], file);
3059 fatal_insn ("bad insn in frv_print_operand, z case", x);
3063 /* Print constant in hex. */
3064 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3066 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3073 if (GET_CODE (x) == REG)
3074 fputs (reg_names [REGNO (x)], file);
3076 else if (GET_CODE (x) == CONST_INT
3077 || GET_CODE (x) == CONST_DOUBLE)
3078 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3080 else if (frv_const_unspec_p (x, &unspec))
3081 frv_output_const_unspec (file, &unspec);
3083 else if (GET_CODE (x) == MEM)
3084 frv_print_operand_address (file, XEXP (x, 0));
3086 else if (CONSTANT_ADDRESS_P (x))
3087 frv_print_operand_address (file, x);
3090 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3095 fatal_insn ("frv_print_operand: unknown code", x);
3103 /* A C statement (sans semicolon) for initializing the variable CUM for the
3104 state at the beginning of the argument list. The variable has type
3105 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3106 of the function which will receive the args, or 0 if the args are to a
3107 compiler support library function. The value of INDIRECT is nonzero when
3108 processing an indirect call, for example a call through a function pointer.
3109 The value of INDIRECT is zero for a call to an explicitly named function, a
3110 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3111 arguments for the function being compiled.
3113 When processing a call to a compiler support library function, LIBNAME
3114 identifies which one. It is a `symbol_ref' rtx which contains the name of
3115 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3116 being processed. Thus, each time this macro is called, either LIBNAME or
3117 FNTYPE is nonzero, but never both of them at once. */
3120 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3126 *cum = FIRST_ARG_REGNUM;
3128 if (TARGET_DEBUG_ARG)
3130 fprintf (stderr, "\ninit_cumulative_args:");
3131 if (!fndecl && fntype)
3132 fputs (" indirect", stderr);
3135 fputs (" incoming", stderr);
3139 tree ret_type = TREE_TYPE (fntype);
3140 fprintf (stderr, " return=%s,",
3141 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3144 if (libname && GET_CODE (libname) == SYMBOL_REF)
3145 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3147 if (cfun->returns_struct)
3148 fprintf (stderr, " return-struct");
3150 putc ('\n', stderr);
3155 /* Return true if we should pass an argument on the stack rather than
3159 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3161 if (mode == BLKmode)
3165 return AGGREGATE_TYPE_P (type);
3168 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3169 argument with the specified mode and type. If it is not defined,
3170 `PARM_BOUNDARY' is used for all arguments. */
3173 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3174 tree type ATTRIBUTE_UNUSED)
3176 return BITS_PER_WORD;
3180 frv_function_arg (CUMULATIVE_ARGS *cum,
3181 enum machine_mode mode,
3182 tree type ATTRIBUTE_UNUSED,
3184 int incoming ATTRIBUTE_UNUSED)
3186 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3191 /* Return a marker for use in the call instruction. */
3192 if (xmode == VOIDmode)
3198 else if (arg_num <= LAST_ARG_REGNUM)
3200 ret = gen_rtx_REG (xmode, arg_num);
3201 debstr = reg_names[arg_num];
3210 if (TARGET_DEBUG_ARG)
3212 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3213 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3219 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3220 advance past an argument in the argument list. The values MODE, TYPE and
3221 NAMED describe that argument. Once this is done, the variable CUM is
3222 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3224 This macro need not do anything if the argument in question was passed on
3225 the stack. The compiler knows how to track the amount of stack space used
3226 for arguments without any special help. */
3229 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3230 enum machine_mode mode,
3231 tree type ATTRIBUTE_UNUSED,
3234 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3235 int bytes = GET_MODE_SIZE (xmode);
3236 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3239 *cum = arg_num + words;
3241 if (TARGET_DEBUG_ARG)
3243 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3244 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3248 /* A C expression for the number of words, at the beginning of an argument,
3249 must be put in registers. The value must be zero for arguments that are
3250 passed entirely in registers or that are entirely pushed on the stack.
3252 On some machines, certain arguments must be passed partially in registers
3253 and partially in memory. On these machines, typically the first N words of
3254 arguments are passed in registers, and the rest on the stack. If a
3255 multi-word argument (a `double' or a structure) crosses that boundary, its
3256 first few words must be passed in registers and the rest must be pushed.
3257 This macro tells the compiler when this occurs, and how many of the words
3258 should go in registers.
3260 `FUNCTION_ARG' for these arguments should return the first register to be
3261 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3262 the called function. */
3265 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3266 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3268 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3269 int bytes = GET_MODE_SIZE (xmode);
3270 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3274 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3275 ? LAST_ARG_REGNUM - arg_num + 1
3277 ret *= UNITS_PER_WORD;
3279 if (TARGET_DEBUG_ARG && ret)
3280 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3286 /* Return true if a register is ok to use as a base or index register. */
3288 static FRV_INLINE int
3289 frv_regno_ok_for_base_p (int regno, int strict_p)
3295 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3297 if (regno == ARG_POINTER_REGNUM)
3300 return (regno >= FIRST_PSEUDO_REGISTER);
3304 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3305 RTX) is a legitimate memory address on the target machine for a memory
3306 operand of mode MODE.
3308 It usually pays to define several simpler macros to serve as subroutines for
3309 this one. Otherwise it may be too complicated to understand.
3311 This macro must exist in two variants: a strict variant and a non-strict
3312 one. The strict variant is used in the reload pass. It must be defined so
3313 that any pseudo-register that has not been allocated a hard register is
3314 considered a memory reference. In contexts where some kind of register is
3315 required, a pseudo-register with no hard register must be rejected.
3317 The non-strict variant is used in other passes. It must be defined to
3318 accept all pseudo-registers in every context where some kind of register is
3321 Compiler source files that want to use the strict variant of this macro
3322 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3323 conditional to define the strict variant in that case and the non-strict
3326 Subroutines to check for acceptable registers for various purposes (one for
3327 base registers, one for index registers, and so on) are typically among the
3328 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3329 subroutine macros need have two variants; the higher levels of macros may be
3330 the same whether strict or not.
3332 Normally, constant addresses which are the sum of a `symbol_ref' and an
3333 integer are stored inside a `const' RTX to mark them as constant.
3334 Therefore, there is no need to recognize such sums specifically as
3335 legitimate addresses. Normally you would simply recognize any `const' as
3338 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3339 are not marked with `const'. It assumes that a naked `plus' indicates
3340 indexing. If so, then you *must* reject such naked constant sums as
3341 illegitimate addresses, so that none of them will be given to
3342 `PRINT_OPERAND_ADDRESS'.
3344 On some machines, whether a symbolic address is legitimate depends on the
3345 section that the address refers to. On these machines, define the macro
3346 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3347 then check for it here. When you see a `const', you will have to look
3348 inside it to find the `symbol_ref' in order to determine the section.
3350 The best way to modify the name string is by adding text to the beginning,
3351 with suitable punctuation to prevent any ambiguity. Allocate the new name
3352 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3353 remove and decode the added text and output the name accordingly, and define
3354 `(* targetm.strip_name_encoding)' to access the original name string.
3356 You can check the information stored here into the `symbol_ref' in the
3357 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3358 `PRINT_OPERAND_ADDRESS'. */
3361 frv_legitimate_address_p (enum machine_mode mode,
3365 int allow_double_reg_p)
3369 HOST_WIDE_INT value;
3372 if (FRV_SYMBOL_REF_TLS_P (x))
3375 switch (GET_CODE (x))
3382 if (GET_CODE (x) != REG)
3388 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3394 if (GET_CODE (x0) != REG
3395 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3396 || GET_CODE (x1) != PLUS
3397 || ! rtx_equal_p (x0, XEXP (x1, 0))
3398 || GET_CODE (XEXP (x1, 1)) != REG
3399 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3406 /* 12-bit immediate */
3411 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3413 /* If we can't use load/store double operations, make sure we can
3414 address the second word. */
3415 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3416 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3425 if (GET_CODE (x0) == SUBREG)
3426 x0 = SUBREG_REG (x0);
3428 if (GET_CODE (x0) != REG)
3431 regno0 = REGNO (x0);
3432 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3435 switch (GET_CODE (x1))
3441 x1 = SUBREG_REG (x1);
3442 if (GET_CODE (x1) != REG)
3448 /* Do not allow reg+reg addressing for modes > 1 word if we
3449 can't depend on having move double instructions. */
3450 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3453 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3457 /* 12-bit immediate */
3462 value = INTVAL (x1);
3463 ret = IN_RANGE_P (value, -2048, 2047);
3465 /* If we can't use load/store double operations, make sure we can
3466 address the second word. */
3467 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3468 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3473 if (!condexec_p && got12_operand (x1, VOIDmode))
3481 if (TARGET_DEBUG_ADDR)
3483 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3484 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3485 (condexec_p) ? ", inside conditional code" : "");
3492 /* Given an ADDR, generate code to inline the PLT. */
3494 gen_inlined_tls_plt (rtx addr)
3497 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3500 dest = gen_reg_rtx (DImode);
3507 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3508 calll #gettlsoff(ADDR)@(gr8, gr0)
3510 emit_insn (gen_tls_lddi (dest, addr, picreg));
3517 sethi.p #gottlsdeschi(ADDR), gr8
3518 setlo #gottlsdesclo(ADDR), gr8
3519 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3520 calll #gettlsoff(ADDR)@(gr8, gr0)
3522 rtx reguse = gen_reg_rtx (Pmode);
3523 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3524 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3527 retval = gen_reg_rtx (Pmode);
3528 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3532 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3533 the destination address. */
3535 gen_tlsmoff (rtx addr, rtx reg)
3537 rtx dest = gen_reg_rtx (Pmode);
3541 /* sethi.p #tlsmoffhi(x), grA
3542 setlo #tlsmofflo(x), grA
3544 dest = gen_reg_rtx (Pmode);
3545 emit_insn (gen_tlsoff_hilo (dest, addr,
3546 GEN_INT (R_FRV_TLSMOFFHI)));
3547 dest = gen_rtx_PLUS (Pmode, dest, reg);
3551 /* addi grB, #tlsmoff12(x), grC
3553 ld/st @(grB, #tlsmoff12(x)), grC
3555 dest = gen_reg_rtx (Pmode);
3556 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3557 GEN_INT (R_FRV_TLSMOFF12)));
3562 /* Generate code for a TLS address. */
3564 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3566 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3567 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3571 case TLS_MODEL_INITIAL_EXEC:
3575 ldi @(gr15, #gottlsoff12(x)), gr5
3577 dest = gen_reg_rtx (Pmode);
3578 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3579 dest = gen_rtx_PLUS (Pmode, tp, dest);
3583 /* -fPIC or anything else.
3585 sethi.p #gottlsoffhi(x), gr14
3586 setlo #gottlsofflo(x), gr14
3587 ld #tlsoff(x)@(gr15, gr14), gr9
3589 rtx tmp = gen_reg_rtx (Pmode);
3590 dest = gen_reg_rtx (Pmode);
3591 emit_insn (gen_tlsoff_hilo (tmp, addr,
3592 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3594 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3595 dest = gen_rtx_PLUS (Pmode, tp, dest);
3598 case TLS_MODEL_LOCAL_DYNAMIC:
3602 if (TARGET_INLINE_PLT)
3603 retval = gen_inlined_tls_plt (GEN_INT (0));
3606 /* call #gettlsoff(0) */
3607 retval = gen_reg_rtx (Pmode);
3608 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3611 reg = gen_reg_rtx (Pmode);
3612 emit_insn (gen_rtx_SET (VOIDmode, reg,
3613 gen_rtx_PLUS (Pmode,
3616 dest = gen_tlsmoff (addr, reg);
3619 dest = gen_reg_rtx (Pmode);
3620 emit_insn (gen_tlsoff_hilo (dest, addr,
3621 GEN_INT (R_FRV_TLSMOFFHI)));
3622 dest = gen_rtx_PLUS (Pmode, dest, reg);
3626 case TLS_MODEL_LOCAL_EXEC:
3627 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3629 case TLS_MODEL_GLOBAL_DYNAMIC:
3633 if (TARGET_INLINE_PLT)
3634 retval = gen_inlined_tls_plt (addr);
3637 /* call #gettlsoff(x) */
3638 retval = gen_reg_rtx (Pmode);
3639 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3641 dest = gen_rtx_PLUS (Pmode, retval, tp);
3652 frv_legitimize_address (rtx x,
3653 rtx oldx ATTRIBUTE_UNUSED,
3654 enum machine_mode mode ATTRIBUTE_UNUSED)
3656 if (GET_CODE (x) == SYMBOL_REF)
3658 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3660 return frv_legitimize_tls_address (x, model);
3666 /* Test whether a local function descriptor is canonical, i.e.,
3667 whether we can use FUNCDESC_GOTOFF to compute the address of the
3671 frv_local_funcdesc_p (rtx fnx)
3674 enum symbol_visibility vis;
3677 if (! SYMBOL_REF_LOCAL_P (fnx))
3680 fn = SYMBOL_REF_DECL (fnx);
3685 vis = DECL_VISIBILITY (fn);
3687 if (vis == VISIBILITY_PROTECTED)
3688 /* Private function descriptors for protected functions are not
3689 canonical. Temporarily change the visibility to global. */
3690 vis = VISIBILITY_DEFAULT;
3691 else if (flag_shlib)
3692 /* If we're already compiling for a shared library (that, unlike
3693 executables, can't assume that the existence of a definition
3694 implies local binding), we can skip the re-testing. */
3697 ret = default_binds_local_p_1 (fn, flag_pic);
3699 DECL_VISIBILITY (fn) = vis;
3704 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3708 frv_gen_GPsym2reg (rtx dest, rtx src)
3710 tree gp = get_identifier ("_gp");
3711 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3713 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3717 unspec_got_name (int i)
3721 case R_FRV_GOT12: return "got12";
3722 case R_FRV_GOTHI: return "gothi";
3723 case R_FRV_GOTLO: return "gotlo";
3724 case R_FRV_FUNCDESC: return "funcdesc";
3725 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3726 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3727 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3728 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3729 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3730 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3731 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3732 case R_FRV_GOTOFF12: return "gotoff12";
3733 case R_FRV_GOTOFFHI: return "gotoffhi";
3734 case R_FRV_GOTOFFLO: return "gotofflo";
3735 case R_FRV_GPREL12: return "gprel12";
3736 case R_FRV_GPRELHI: return "gprelhi";
3737 case R_FRV_GPRELLO: return "gprello";
3738 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3739 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3740 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3741 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3742 case R_FRV_TLSMOFF12: return "tlsmoff12";
3743 case R_FRV_TLSDESCHI: return "tlsdeschi";
3744 case R_FRV_TLSDESCLO: return "tlsdesclo";
3745 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3746 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3747 default: gcc_unreachable ();
3751 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3752 is added inside the relocation operator. */
3755 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3757 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3758 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3759 fputs (")", stream);
3762 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3763 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3764 otherwise return ORIG_X. */
3767 frv_find_base_term (rtx x)
3769 struct frv_unspec unspec;
3771 if (frv_const_unspec_p (x, &unspec)
3772 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3773 return plus_constant (unspec.symbol, unspec.offset);
3778 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3779 the operand is used by a predicated instruction. */
3782 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3784 return ((GET_MODE (op) == mode || mode == VOIDmode)
3785 && GET_CODE (op) == MEM
3786 && frv_legitimate_address_p (mode, XEXP (op, 0),
3787 reload_completed, condexec_p, FALSE));
3791 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3793 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3794 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3800 rvrtx = operands[0];
3804 addr = XEXP (operands[0], 0);
3806 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3807 any calls that would involve a PLT, but can't tell, since we
3808 don't know whether an extern function is going to be provided by
3809 a separate translation unit or imported from a separate module.
3810 When compiling for shared libraries, if the function has default
3811 visibility, we assume it's overridable, so we inline the PLT, but
3812 for executables, we don't really have a way to make a good
3813 decision: a function is as likely to be imported from a shared
3814 library as it is to be defined in the executable itself. We
3815 assume executables will get global functions defined locally,
3816 whereas shared libraries will have them potentially overridden,
3817 so we only inline PLTs when compiling for shared libraries.
3819 In order to mark a function as local to a shared library, any
3820 non-default visibility attribute suffices. Unfortunately,
3821 there's no simple way to tag a function declaration as ``in a
3822 different module'', which we could then use to trigger PLT
3823 inlining on executables. There's -minline-plt, but it affects
3824 all external functions, so one would have to also mark function
3825 declarations available in the same module with non-default
3826 visibility, which is advantageous in itself. */
3827 if (GET_CODE (addr) == SYMBOL_REF
3828 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3832 dest = gen_reg_rtx (SImode);
3834 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3835 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3837 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3838 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3840 crtl->uses_pic_offset_table = TRUE;
3843 else if (GET_CODE (addr) == SYMBOL_REF)
3845 /* These are always either local, or handled through a local
3848 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3849 operands[2], picreg, lr);
3851 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3855 else if (! ldd_address_operand (addr, Pmode))
3856 addr = force_reg (Pmode, addr);
3858 picreg = gen_reg_rtx (DImode);
3859 emit_insn (gen_movdi_ldd (picreg, addr));
3861 if (sibcall && ret_value)
3862 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3864 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3866 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3868 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3872 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3873 process these separately from any offsets, such that we add any
3874 offsets to the function descriptor (the actual pointer), not to the
3875 function address. */
3878 frv_function_symbol_referenced_p (rtx x)
3884 if (GET_CODE (x) == SYMBOL_REF)
3885 return SYMBOL_REF_FUNCTION_P (x);
3887 length = GET_RTX_LENGTH (GET_CODE (x));
3888 format = GET_RTX_FORMAT (GET_CODE (x));
3890 for (j = 0; j < length; ++j)
3895 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3901 if (XVEC (x, j) != 0)
3904 for (k = 0; k < XVECLEN (x, j); ++k)
3905 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3911 /* Nothing to do. */
3919 /* Return true if the memory operand is one that can be conditionally
3923 condexec_memory_operand (rtx op, enum machine_mode mode)
3925 enum machine_mode op_mode = GET_MODE (op);
3928 if (mode != VOIDmode && op_mode != mode)
3943 if (GET_CODE (op) != MEM)
3946 addr = XEXP (op, 0);
3947 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
3950 /* Return true if the bare return instruction can be used outside of the
3951 epilog code. For frv, we only do it if there was no stack allocation. */
3954 direct_return_p (void)
3958 if (!reload_completed)
3961 info = frv_stack_info ();
3962 return (info->total_size == 0);
3967 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3969 if (GET_CODE (src) == SYMBOL_REF)
3971 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3973 src = frv_legitimize_tls_address (src, model);
3979 if (frv_emit_movsi (dest, src))
3988 if (!reload_in_progress
3989 && !reload_completed
3990 && !register_operand (dest, mode)
3991 && !reg_or_0_operand (src, mode))
3992 src = copy_to_mode_reg (mode, src);
3999 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4002 /* Emit code to handle a MOVSI, adding in the small data register or pic
4003 register if needed to load up addresses. Return TRUE if the appropriate
4004 instructions are emitted. */
4007 frv_emit_movsi (rtx dest, rtx src)
4009 int base_regno = -1;
4012 struct frv_unspec old_unspec;
4014 if (!reload_in_progress
4015 && !reload_completed
4016 && !register_operand (dest, SImode)
4017 && (!reg_or_0_operand (src, SImode)
4018 /* Virtual registers will almost always be replaced by an
4019 add instruction, so expose this to CSE by copying to
4020 an intermediate register. */
4021 || (GET_CODE (src) == REG
4022 && IN_RANGE_P (REGNO (src),
4023 FIRST_VIRTUAL_REGISTER,
4024 LAST_VIRTUAL_REGISTER))))
4026 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4030 /* Explicitly add in the PIC or small data register if needed. */
4031 switch (GET_CODE (src))
4040 /* Using GPREL12, we use a single GOT entry for all symbols
4041 in read-only sections, but trade sequences such as:
4043 sethi #gothi(label), gr#
4044 setlo #gotlo(label), gr#
4049 ld @(gr15,#got12(_gp)), gr#
4050 sethi #gprelhi(label), gr##
4051 setlo #gprello(label), gr##
4054 We may often be able to share gr# for multiple
4055 computations of GPREL addresses, and we may often fold
4056 the final add into the pair of registers of a load or
4057 store instruction, so it's often profitable. Even when
4058 optimizing for size, we're trading a GOT entry for an
4059 additional instruction, which trades GOT space
4060 (read-write) for code size (read-only, shareable), as
4061 long as the symbol is not used in more than two different
4064 With -fpie/-fpic, we'd be trading a single load for a
4065 sequence of 4 instructions, because the offset of the
4066 label can't be assumed to be addressable with 12 bits, so
4067 we don't do this. */
4068 if (TARGET_GPREL_RO)
4069 unspec = R_FRV_GPREL12;
4071 unspec = R_FRV_GOT12;
4074 base_regno = PIC_REGNO;
4079 if (frv_const_unspec_p (src, &old_unspec))
4082 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4085 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4086 emit_move_insn (dest, src);
4091 sym = XEXP (sym, 0);
4092 if (GET_CODE (sym) == PLUS
4093 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4094 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4095 sym = XEXP (sym, 0);
4096 if (GET_CODE (sym) == SYMBOL_REF)
4098 else if (GET_CODE (sym) == LABEL_REF)
4101 goto handle_whatever;
4109 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4113 src = frv_legitimize_tls_address (src, model);
4114 emit_move_insn (dest, src);
4118 if (SYMBOL_REF_FUNCTION_P (sym))
4120 if (frv_local_funcdesc_p (sym))
4121 unspec = R_FRV_FUNCDESC_GOTOFF12;
4123 unspec = R_FRV_FUNCDESC_GOT12;
4127 if (CONSTANT_POOL_ADDRESS_P (sym))
4128 switch (GET_CODE (get_pool_constant (sym)))
4135 unspec = R_FRV_GOTOFF12;
4140 if (TARGET_GPREL_RO)
4141 unspec = R_FRV_GPREL12;
4143 unspec = R_FRV_GOT12;
4146 else if (SYMBOL_REF_LOCAL_P (sym)
4147 && !SYMBOL_REF_EXTERNAL_P (sym)
4148 && SYMBOL_REF_DECL (sym)
4149 && (!DECL_P (SYMBOL_REF_DECL (sym))
4150 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4152 tree decl = SYMBOL_REF_DECL (sym);
4153 tree init = TREE_CODE (decl) == VAR_DECL
4154 ? DECL_INITIAL (decl)
4155 : TREE_CODE (decl) == CONSTRUCTOR
4158 bool named_section, readonly;
4160 if (init && init != error_mark_node)
4161 reloc = compute_reloc_for_constant (init);
4163 named_section = TREE_CODE (decl) == VAR_DECL
4164 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4165 readonly = decl_readonly_section (decl, reloc);
4168 unspec = R_FRV_GOT12;
4170 unspec = R_FRV_GOTOFF12;
4171 else if (readonly && TARGET_GPREL_RO)
4172 unspec = R_FRV_GPREL12;
4174 unspec = R_FRV_GOT12;
4177 unspec = R_FRV_GOT12;
4181 else if (SYMBOL_REF_SMALL_P (sym))
4182 base_regno = SDA_BASE_REG;
4185 base_regno = PIC_REGNO;
4190 if (base_regno >= 0)
4192 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4193 emit_insn (gen_symGOTOFF2reg (dest, src,
4194 gen_rtx_REG (Pmode, base_regno),
4195 GEN_INT (R_FRV_GPREL12)));
4197 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4198 gen_rtx_REG (Pmode, base_regno),
4199 GEN_INT (R_FRV_GPREL12)));
4200 if (base_regno == PIC_REGNO)
4201 crtl->uses_pic_offset_table = TRUE;
4209 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4210 new uses of it once reload has begun. */
4211 gcc_assert (!reload_in_progress && !reload_completed);
4215 case R_FRV_GOTOFF12:
4216 if (!frv_small_data_reloc_p (sym, unspec))
4217 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4220 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4223 if (!frv_small_data_reloc_p (sym, unspec))
4224 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4227 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4229 case R_FRV_FUNCDESC_GOTOFF12:
4231 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4234 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4238 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4241 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4245 crtl->uses_pic_offset_table = TRUE;
4254 /* Return a string to output a single word move. */
4257 output_move_single (rtx operands[], rtx insn)
4259 rtx dest = operands[0];
4260 rtx src = operands[1];
4262 if (GET_CODE (dest) == REG)
4264 int dest_regno = REGNO (dest);
4265 enum machine_mode mode = GET_MODE (dest);
4267 if (GPR_P (dest_regno))
4269 if (GET_CODE (src) == REG)
4271 /* gpr <- some sort of register */
4272 int src_regno = REGNO (src);
4274 if (GPR_P (src_regno))
4275 return "mov %1, %0";
4277 else if (FPR_P (src_regno))
4278 return "movfg %1, %0";
4280 else if (SPR_P (src_regno))
4281 return "movsg %1, %0";
4284 else if (GET_CODE (src) == MEM)
4293 return "ldsb%I1%U1 %M1,%0";
4296 return "ldsh%I1%U1 %M1,%0";
4300 return "ld%I1%U1 %M1, %0";
4304 else if (GET_CODE (src) == CONST_INT
4305 || GET_CODE (src) == CONST_DOUBLE)
4307 /* gpr <- integer/floating constant */
4308 HOST_WIDE_INT value;
4310 if (GET_CODE (src) == CONST_INT)
4311 value = INTVAL (src);
4313 else if (mode == SFmode)
4318 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4319 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4324 value = CONST_DOUBLE_LOW (src);
4326 if (IN_RANGE_P (value, -32768, 32767))
4327 return "setlos %1, %0";
4332 else if (GET_CODE (src) == SYMBOL_REF
4333 || GET_CODE (src) == LABEL_REF
4334 || GET_CODE (src) == CONST)
4340 else if (FPR_P (dest_regno))
4342 if (GET_CODE (src) == REG)
4344 /* fpr <- some sort of register */
4345 int src_regno = REGNO (src);
4347 if (GPR_P (src_regno))
4348 return "movgf %1, %0";
4350 else if (FPR_P (src_regno))
4352 if (TARGET_HARD_FLOAT)
4353 return "fmovs %1, %0";
4355 return "mor %1, %1, %0";
4359 else if (GET_CODE (src) == MEM)
4368 return "ldbf%I1%U1 %M1,%0";
4371 return "ldhf%I1%U1 %M1,%0";
4375 return "ldf%I1%U1 %M1, %0";
4379 else if (ZERO_P (src))
4380 return "movgf %., %0";
4383 else if (SPR_P (dest_regno))
4385 if (GET_CODE (src) == REG)
4387 /* spr <- some sort of register */
4388 int src_regno = REGNO (src);
4390 if (GPR_P (src_regno))
4391 return "movgs %1, %0";
4393 else if (ZERO_P (src))
4394 return "movgs %., %0";
4398 else if (GET_CODE (dest) == MEM)
4400 if (GET_CODE (src) == REG)
4402 int src_regno = REGNO (src);
4403 enum machine_mode mode = GET_MODE (dest);
4405 if (GPR_P (src_regno))
4413 return "stb%I0%U0 %1, %M0";
4416 return "sth%I0%U0 %1, %M0";
4420 return "st%I0%U0 %1, %M0";
4424 else if (FPR_P (src_regno))
4432 return "stbf%I0%U0 %1, %M0";
4435 return "sthf%I0%U0 %1, %M0";
4439 return "stf%I0%U0 %1, %M0";
4444 else if (ZERO_P (src))
4446 switch (GET_MODE (dest))
4452 return "stb%I0%U0 %., %M0";
4455 return "sth%I0%U0 %., %M0";
4459 return "st%I0%U0 %., %M0";
4464 fatal_insn ("bad output_move_single operand", insn);
4469 /* Return a string to output a double word move. */
4472 output_move_double (rtx operands[], rtx insn)
4474 rtx dest = operands[0];
4475 rtx src = operands[1];
4476 enum machine_mode mode = GET_MODE (dest);
4478 if (GET_CODE (dest) == REG)
4480 int dest_regno = REGNO (dest);
4482 if (GPR_P (dest_regno))
4484 if (GET_CODE (src) == REG)
4486 /* gpr <- some sort of register */
4487 int src_regno = REGNO (src);
4489 if (GPR_P (src_regno))
4492 else if (FPR_P (src_regno))
4494 if (((dest_regno - GPR_FIRST) & 1) == 0
4495 && ((src_regno - FPR_FIRST) & 1) == 0)
4496 return "movfgd %1, %0";
4502 else if (GET_CODE (src) == MEM)
4505 if (dbl_memory_one_insn_operand (src, mode))
4506 return "ldd%I1%U1 %M1, %0";
4511 else if (GET_CODE (src) == CONST_INT
4512 || GET_CODE (src) == CONST_DOUBLE)
4516 else if (FPR_P (dest_regno))
4518 if (GET_CODE (src) == REG)
4520 /* fpr <- some sort of register */
4521 int src_regno = REGNO (src);
4523 if (GPR_P (src_regno))
4525 if (((dest_regno - FPR_FIRST) & 1) == 0
4526 && ((src_regno - GPR_FIRST) & 1) == 0)
4527 return "movgfd %1, %0";
4532 else if (FPR_P (src_regno))
4535 && ((dest_regno - FPR_FIRST) & 1) == 0
4536 && ((src_regno - FPR_FIRST) & 1) == 0)
4537 return "fmovd %1, %0";
4543 else if (GET_CODE (src) == MEM)
4546 if (dbl_memory_one_insn_operand (src, mode))
4547 return "lddf%I1%U1 %M1, %0";
4552 else if (ZERO_P (src))
4557 else if (GET_CODE (dest) == MEM)
4559 if (GET_CODE (src) == REG)
4561 int src_regno = REGNO (src);
4563 if (GPR_P (src_regno))
4565 if (((src_regno - GPR_FIRST) & 1) == 0
4566 && dbl_memory_one_insn_operand (dest, mode))
4567 return "std%I0%U0 %1, %M0";
4572 if (FPR_P (src_regno))
4574 if (((src_regno - FPR_FIRST) & 1) == 0
4575 && dbl_memory_one_insn_operand (dest, mode))
4576 return "stdf%I0%U0 %1, %M0";
4582 else if (ZERO_P (src))
4584 if (dbl_memory_one_insn_operand (dest, mode))
4585 return "std%I0%U0 %., %M0";
4591 fatal_insn ("bad output_move_double operand", insn);
4596 /* Return a string to output a single word conditional move.
4597 Operand0 -- EQ/NE of ccr register and 0
4598 Operand1 -- CCR register
4599 Operand2 -- destination
4600 Operand3 -- source */
4603 output_condmove_single (rtx operands[], rtx insn)
4605 rtx dest = operands[2];
4606 rtx src = operands[3];
4608 if (GET_CODE (dest) == REG)
4610 int dest_regno = REGNO (dest);
4611 enum machine_mode mode = GET_MODE (dest);
4613 if (GPR_P (dest_regno))
4615 if (GET_CODE (src) == REG)
4617 /* gpr <- some sort of register */
4618 int src_regno = REGNO (src);
4620 if (GPR_P (src_regno))
4621 return "cmov %z3, %2, %1, %e0";
4623 else if (FPR_P (src_regno))
4624 return "cmovfg %3, %2, %1, %e0";
4627 else if (GET_CODE (src) == MEM)
4636 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4639 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4643 return "cld%I3%U3 %M3, %2, %1, %e0";
4647 else if (ZERO_P (src))
4648 return "cmov %., %2, %1, %e0";
4651 else if (FPR_P (dest_regno))
4653 if (GET_CODE (src) == REG)
4655 /* fpr <- some sort of register */
4656 int src_regno = REGNO (src);
4658 if (GPR_P (src_regno))
4659 return "cmovgf %3, %2, %1, %e0";
4661 else if (FPR_P (src_regno))
4663 if (TARGET_HARD_FLOAT)
4664 return "cfmovs %3,%2,%1,%e0";
4666 return "cmor %3, %3, %2, %1, %e0";
4670 else if (GET_CODE (src) == MEM)
4673 if (mode == SImode || mode == SFmode)
4674 return "cldf%I3%U3 %M3, %2, %1, %e0";
4677 else if (ZERO_P (src))
4678 return "cmovgf %., %2, %1, %e0";
4682 else if (GET_CODE (dest) == MEM)
4684 if (GET_CODE (src) == REG)
4686 int src_regno = REGNO (src);
4687 enum machine_mode mode = GET_MODE (dest);
4689 if (GPR_P (src_regno))
4697 return "cstb%I2%U2 %3, %M2, %1, %e0";
4700 return "csth%I2%U2 %3, %M2, %1, %e0";
4704 return "cst%I2%U2 %3, %M2, %1, %e0";
4708 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4709 return "cstf%I2%U2 %3, %M2, %1, %e0";
4712 else if (ZERO_P (src))
4714 enum machine_mode mode = GET_MODE (dest);
4721 return "cstb%I2%U2 %., %M2, %1, %e0";
4724 return "csth%I2%U2 %., %M2, %1, %e0";
4728 return "cst%I2%U2 %., %M2, %1, %e0";
4733 fatal_insn ("bad output_condmove_single operand", insn);
4738 /* Emit the appropriate code to do a comparison, returning the register the
4739 comparison was done it. */
4742 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4744 enum machine_mode cc_mode;
4747 /* Floating point doesn't have comparison against a constant. */
4748 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4749 op1 = force_reg (GET_MODE (op0), op1);
4751 /* Possibly disable using anything but a fixed register in order to work
4752 around cse moving comparisons past function calls. */
4753 cc_mode = SELECT_CC_MODE (test, op0, op1);
4754 cc_reg = ((TARGET_ALLOC_CC)
4755 ? gen_reg_rtx (cc_mode)
4756 : gen_rtx_REG (cc_mode,
4757 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4759 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4760 gen_rtx_COMPARE (cc_mode, op0, op1)));
4766 /* Emit code for a conditional branch.
4767 XXX: I originally wanted to add a clobber of a CCR register to use in
4768 conditional execution, but that confuses the rest of the compiler. */
4771 frv_emit_cond_branch (rtx operands[])
4776 enum rtx_code test = GET_CODE (operands[0]);
4777 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4778 enum machine_mode cc_mode = GET_MODE (cc_reg);
4780 /* Branches generate:
4782 (if_then_else (<test>, <cc_reg>, (const_int 0))
4783 (label_ref <branch_label>)
4785 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4786 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4787 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4788 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4793 /* Emit code to set a gpr to 1/0 based on a comparison. */
4796 frv_emit_scc (rtx operands[])
4802 enum rtx_code test = GET_CODE (operands[1]);
4803 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4805 /* SCC instructions generate:
4806 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4807 (clobber (<ccr_reg>))]) */
4808 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4809 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4811 cr_reg = ((TARGET_ALLOC_CC)
4812 ? gen_reg_rtx (CC_CCRmode)
4813 : gen_rtx_REG (CC_CCRmode,
4814 ((GET_MODE (cc_reg) == CC_FPmode)
4818 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4819 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4824 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4825 the separate insns. */
4828 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4834 /* Set the appropriate CCR bit. */
4835 emit_insn (gen_rtx_SET (VOIDmode,
4837 gen_rtx_fmt_ee (GET_CODE (test),
4842 /* Move the value into the destination. */
4843 emit_move_insn (dest, GEN_INT (value));
4845 /* Move 0 into the destination if the test failed */
4846 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4847 gen_rtx_EQ (GET_MODE (cr_reg),
4850 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4852 /* Finish up, return sequence. */
4859 /* Emit the code for a conditional move, return TRUE if we could do the
4863 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4870 enum rtx_code test = GET_CODE (test_rtx);
4871 rtx cc_reg = frv_emit_comparison (test,
4872 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4873 enum machine_mode cc_mode = GET_MODE (cc_reg);
4875 /* Conditional move instructions generate:
4876 (parallel [(set <target>
4877 (if_then_else (<test> <cc_reg> (const_int 0))
4880 (clobber (<ccr_reg>))]) */
4882 /* Handle various cases of conditional move involving two constants. */
4883 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4885 HOST_WIDE_INT value1 = INTVAL (src1);
4886 HOST_WIDE_INT value2 = INTVAL (src2);
4888 /* Having 0 as one of the constants can be done by loading the other
4889 constant, and optionally moving in gr0. */
4890 if (value1 == 0 || value2 == 0)
4893 /* If the first value is within an addi range and also the difference
4894 between the two fits in an addi's range, load up the difference, then
4895 conditionally move in 0, and then unconditionally add the first
4897 else if (IN_RANGE_P (value1, -2048, 2047)
4898 && IN_RANGE_P (value2 - value1, -2048, 2047))
4901 /* If neither condition holds, just force the constant into a
4905 src1 = force_reg (GET_MODE (dest), src1);
4906 src2 = force_reg (GET_MODE (dest), src2);
4910 /* If one value is a register, insure the other value is either 0 or a
4914 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4915 src1 = force_reg (GET_MODE (dest), src1);
4917 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4918 src2 = force_reg (GET_MODE (dest), src2);
4921 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4922 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4924 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4926 cr_reg = ((TARGET_ALLOC_CC)
4927 ? gen_reg_rtx (CC_CCRmode)
4928 : gen_rtx_REG (CC_CCRmode,
4929 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4931 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4932 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4937 /* Split a conditional move into constituent parts, returning a SEQUENCE
4938 containing all of the insns. */
4941 frv_split_cond_move (rtx operands[])
4943 rtx dest = operands[0];
4944 rtx test = operands[1];
4945 rtx cc_reg = operands[2];
4946 rtx src1 = operands[3];
4947 rtx src2 = operands[4];
4948 rtx cr_reg = operands[5];
4950 enum machine_mode cr_mode = GET_MODE (cr_reg);
4954 /* Set the appropriate CCR bit. */
4955 emit_insn (gen_rtx_SET (VOIDmode,
4957 gen_rtx_fmt_ee (GET_CODE (test),
4962 /* Handle various cases of conditional move involving two constants. */
4963 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4965 HOST_WIDE_INT value1 = INTVAL (src1);
4966 HOST_WIDE_INT value2 = INTVAL (src2);
4968 /* Having 0 as one of the constants can be done by loading the other
4969 constant, and optionally moving in gr0. */
4972 emit_move_insn (dest, src2);
4973 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4974 gen_rtx_NE (cr_mode, cr_reg,
4976 gen_rtx_SET (VOIDmode, dest, src1)));
4979 else if (value2 == 0)
4981 emit_move_insn (dest, src1);
4982 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4983 gen_rtx_EQ (cr_mode, cr_reg,
4985 gen_rtx_SET (VOIDmode, dest, src2)));
4988 /* If the first value is within an addi range and also the difference
4989 between the two fits in an addi's range, load up the difference, then
4990 conditionally move in 0, and then unconditionally add the first
4992 else if (IN_RANGE_P (value1, -2048, 2047)
4993 && IN_RANGE_P (value2 - value1, -2048, 2047))
4995 rtx dest_si = ((GET_MODE (dest) == SImode)
4997 : gen_rtx_SUBREG (SImode, dest, 0));
4999 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5000 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5001 gen_rtx_NE (cr_mode, cr_reg,
5003 gen_rtx_SET (VOIDmode, dest_si,
5005 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5013 /* Emit the conditional move for the test being true if needed. */
5014 if (! rtx_equal_p (dest, src1))
5015 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5016 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5017 gen_rtx_SET (VOIDmode, dest, src1)));
5019 /* Emit the conditional move for the test being false if needed. */
5020 if (! rtx_equal_p (dest, src2))
5021 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5022 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5023 gen_rtx_SET (VOIDmode, dest, src2)));
5026 /* Finish up, return sequence. */
5033 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5034 memory location that is not known to be dword-aligned. */
5036 frv_split_double_load (rtx dest, rtx source)
5038 int regno = REGNO (dest);
5039 rtx dest1 = gen_highpart (SImode, dest);
5040 rtx dest2 = gen_lowpart (SImode, dest);
5041 rtx address = XEXP (source, 0);
5043 /* If the address is pre-modified, load the lower-numbered register
5044 first, then load the other register using an integer offset from
5045 the modified base register. This order should always be safe,
5046 since the pre-modification cannot affect the same registers as the
5049 The situation for other loads is more complicated. Loading one
5050 of the registers could affect the value of ADDRESS, so we must
5051 be careful which order we do them in. */
5052 if (GET_CODE (address) == PRE_MODIFY
5053 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5055 /* It is safe to load the lower-numbered register first. */
5056 emit_move_insn (dest1, change_address (source, SImode, NULL));
5057 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5061 /* ADDRESS is not pre-modified and the address depends on the
5062 lower-numbered register. Load the higher-numbered register
5064 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5065 emit_move_insn (dest1, change_address (source, SImode, NULL));
5069 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5070 and SOURCE is either a double register or the constant zero. */
5072 frv_split_double_store (rtx dest, rtx source)
5074 rtx dest1 = change_address (dest, SImode, NULL);
5075 rtx dest2 = frv_index_memory (dest, SImode, 1);
5076 if (ZERO_P (source))
5078 emit_move_insn (dest1, CONST0_RTX (SImode));
5079 emit_move_insn (dest2, CONST0_RTX (SImode));
5083 emit_move_insn (dest1, gen_highpart (SImode, source));
5084 emit_move_insn (dest2, gen_lowpart (SImode, source));
5089 /* Split a min/max operation returning a SEQUENCE containing all of the
5093 frv_split_minmax (rtx operands[])
5095 rtx dest = operands[0];
5096 rtx minmax = operands[1];
5097 rtx src1 = operands[2];
5098 rtx src2 = operands[3];
5099 rtx cc_reg = operands[4];
5100 rtx cr_reg = operands[5];
5102 enum rtx_code test_code;
5103 enum machine_mode cr_mode = GET_MODE (cr_reg);
5107 /* Figure out which test to use. */
5108 switch (GET_CODE (minmax))
5113 case SMIN: test_code = LT; break;
5114 case SMAX: test_code = GT; break;
5115 case UMIN: test_code = LTU; break;
5116 case UMAX: test_code = GTU; break;
5119 /* Issue the compare instruction. */
5120 emit_insn (gen_rtx_SET (VOIDmode,
5122 gen_rtx_COMPARE (GET_MODE (cc_reg),
5125 /* Set the appropriate CCR bit. */
5126 emit_insn (gen_rtx_SET (VOIDmode,
5128 gen_rtx_fmt_ee (test_code,
5133 /* If are taking the min/max of a nonzero constant, load that first, and
5134 then do a conditional move of the other value. */
5135 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5137 gcc_assert (!rtx_equal_p (dest, src1));
5139 emit_move_insn (dest, src2);
5140 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5141 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5142 gen_rtx_SET (VOIDmode, dest, src1)));
5145 /* Otherwise, do each half of the move. */
5148 /* Emit the conditional move for the test being true if needed. */
5149 if (! rtx_equal_p (dest, src1))
5150 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5151 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5152 gen_rtx_SET (VOIDmode, dest, src1)));
5154 /* Emit the conditional move for the test being false if needed. */
5155 if (! rtx_equal_p (dest, src2))
5156 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5157 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5158 gen_rtx_SET (VOIDmode, dest, src2)));
5161 /* Finish up, return sequence. */
5168 /* Split an integer abs operation returning a SEQUENCE containing all of the
5172 frv_split_abs (rtx operands[])
5174 rtx dest = operands[0];
5175 rtx src = operands[1];
5176 rtx cc_reg = operands[2];
5177 rtx cr_reg = operands[3];
5182 /* Issue the compare < 0 instruction. */
5183 emit_insn (gen_rtx_SET (VOIDmode,
5185 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5187 /* Set the appropriate CCR bit. */
5188 emit_insn (gen_rtx_SET (VOIDmode,
5190 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5192 /* Emit the conditional negate if the value is negative. */
5193 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5194 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5195 gen_negsi2 (dest, src)));
5197 /* Emit the conditional move for the test being false if needed. */
5198 if (! rtx_equal_p (dest, src))
5199 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5200 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5201 gen_rtx_SET (VOIDmode, dest, src)));
5203 /* Finish up, return sequence. */
5210 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5211 register used in an insn. */
5214 frv_clear_registers_used (rtx *ptr, void *data)
5216 if (GET_CODE (*ptr) == REG)
5218 int regno = REGNO (*ptr);
5219 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5221 if (regno < FIRST_PSEUDO_REGISTER)
5223 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5225 while (regno < reg_max)
5227 CLEAR_HARD_REG_BIT (*p_regs, regno);
5237 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5239 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5240 initialize the static storage. */
5242 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5244 frv_ifcvt.added_insns_list = NULL_RTX;
5245 frv_ifcvt.cur_scratch_regs = 0;
5246 frv_ifcvt.num_nested_cond_exec = 0;
5247 frv_ifcvt.cr_reg = NULL_RTX;
5248 frv_ifcvt.nested_cc_reg = NULL_RTX;
5249 frv_ifcvt.extra_int_cr = NULL_RTX;
5250 frv_ifcvt.extra_fp_cr = NULL_RTX;
5251 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5255 /* Internal function to add a potential insn to the list of insns to be inserted
5256 if the conditional execution conversion is successful. */
5259 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5261 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5263 link->jump = before_p; /* Mark to add this before or after insn. */
5264 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5265 frv_ifcvt.added_insns_list);
5267 if (TARGET_DEBUG_COND_EXEC)
5270 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5271 (before_p) ? "before" : "after",
5272 (int)INSN_UID (insn));
5274 debug_rtx (pattern);
5279 /* A C expression to modify the code described by the conditional if
5280 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5281 FALSE_EXPR for converting if-then and if-then-else code to conditional
5282 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5283 tests cannot be converted. */
5286 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5288 basic_block test_bb = ce_info->test_bb; /* test basic block */
5289 basic_block then_bb = ce_info->then_bb; /* THEN */
5290 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5291 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5292 rtx true_expr = *p_true;
5296 enum machine_mode mode = GET_MODE (true_expr);
5300 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5302 rtx sub_cond_exec_reg;
5304 enum rtx_code code_true;
5305 enum rtx_code code_false;
5306 enum reg_class cc_class;
5307 enum reg_class cr_class;
5310 reg_set_iterator rsi;
5312 /* Make sure we are only dealing with hard registers. Also honor the
5313 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5315 if (!reload_completed || !TARGET_COND_EXEC
5316 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5319 /* Figure out which registers we can allocate for our own purposes. Only
5320 consider registers that are not preserved across function calls and are
5321 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5322 if we did not need to use them in reloading other registers. */
5323 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5324 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5325 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5326 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5327 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5329 /* If this is a nested IF, we need to discover whether the CC registers that
5330 are set/used inside of the block are used anywhere else. If not, we can
5331 change them to be the CC register that is paired with the CR register that
5332 controls the outermost IF block. */
5333 if (ce_info->pass > 1)
5335 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5336 for (j = CC_FIRST; j <= CC_LAST; j++)
5337 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5339 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5343 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5347 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5350 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5354 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5355 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5357 frv_ifcvt.added_insns_list = NULL_RTX;
5358 frv_ifcvt.cur_scratch_regs = 0;
5360 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5361 * sizeof (basic_block));
5367 /* Remove anything live at the beginning of the join block from being
5368 available for allocation. */
5369 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5371 if (regno < FIRST_PSEUDO_REGISTER)
5372 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5376 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5378 if (ce_info->num_multiple_test_blocks)
5380 basic_block multiple_test_bb = ce_info->last_test_bb;
5382 while (multiple_test_bb != test_bb)
5384 bb[num_bb++] = multiple_test_bb;
5385 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5389 /* Add in the THEN and ELSE blocks to be scanned. */
5390 bb[num_bb++] = then_bb;
5392 bb[num_bb++] = else_bb;
5394 sub_cond_exec_reg = NULL_RTX;
5395 frv_ifcvt.num_nested_cond_exec = 0;
5397 /* Scan all of the blocks for registers that must not be allocated. */
5398 for (j = 0; j < num_bb; j++)
5400 rtx last_insn = BB_END (bb[j]);
5401 rtx insn = BB_HEAD (bb[j]);
5405 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5406 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5408 (int) INSN_UID (BB_HEAD (bb[j])),
5409 (int) INSN_UID (BB_END (bb[j])));
5411 /* Anything live at the beginning of the block is obviously unavailable
5413 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5415 if (regno < FIRST_PSEUDO_REGISTER)
5416 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5419 /* Loop through the insns in the block. */
5422 /* Mark any new registers that are created as being unavailable for
5423 allocation. Also see if the CC register used in nested IFs can be
5429 int skip_nested_if = FALSE;
5431 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5432 (void *)&tmp_reg->regs);
5434 pattern = PATTERN (insn);
5435 if (GET_CODE (pattern) == COND_EXEC)
5437 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5439 if (reg != sub_cond_exec_reg)
5441 sub_cond_exec_reg = reg;
5442 frv_ifcvt.num_nested_cond_exec++;
5446 set = single_set_pattern (pattern);
5449 rtx dest = SET_DEST (set);
5450 rtx src = SET_SRC (set);
5452 if (GET_CODE (dest) == REG)
5454 int regno = REGNO (dest);
5455 enum rtx_code src_code = GET_CODE (src);
5457 if (CC_P (regno) && src_code == COMPARE)
5458 skip_nested_if = TRUE;
5460 else if (CR_P (regno)
5461 && (src_code == IF_THEN_ELSE
5462 || COMPARISON_P (src)))
5463 skip_nested_if = TRUE;
5467 if (! skip_nested_if)
5468 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5469 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5472 if (insn == last_insn)
5475 insn = NEXT_INSN (insn);
5479 /* If this is a nested if, rewrite the CC registers that are available to
5480 include the ones that can be rewritten, to increase the chance of being
5481 able to allocate a paired CC/CR register combination. */
5482 if (ce_info->pass > 1)
5484 for (j = CC_FIRST; j <= CC_LAST; j++)
5485 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5486 SET_HARD_REG_BIT (tmp_reg->regs, j);
5488 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5494 fprintf (dump_file, "Available GPRs: ");
5496 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5497 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5499 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5500 if (++num_gprs > GPR_TEMP_NUM+2)
5504 fprintf (dump_file, "%s\nAvailable CRs: ",
5505 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5507 for (j = CR_FIRST; j <= CR_LAST; j++)
5508 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5509 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5511 fputs ("\n", dump_file);
5513 if (ce_info->pass > 1)
5515 fprintf (dump_file, "Modifiable CCs: ");
5516 for (j = CC_FIRST; j <= CC_LAST; j++)
5517 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5518 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5520 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5521 frv_ifcvt.num_nested_cond_exec);
5525 /* Allocate the appropriate temporary condition code register. Try to
5526 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5527 that conditional cmp's can be done. */
5528 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5530 cr_class = ICR_REGS;
5531 cc_class = ICC_REGS;
5532 cc_first = ICC_FIRST;
5535 else if (mode == CC_FPmode)
5537 cr_class = FCR_REGS;
5538 cc_class = FCC_REGS;
5539 cc_first = FCC_FIRST;
5544 cc_first = cc_last = 0;
5545 cr_class = cc_class = NO_REGS;
5548 cc = XEXP (true_expr, 0);
5549 nested_cc = cr = NULL_RTX;
5550 if (cc_class != NO_REGS)
5552 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5553 so we can execute a csubcc/caddcc/cfcmps instruction. */
5556 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5558 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5560 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5561 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5563 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5564 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5567 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5568 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5578 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5585 "Will use %s for conditional execution, %s for nested comparisons\n",
5586 reg_names[ REGNO (cr)],
5587 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5589 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5590 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5591 bit being true. We don't do this for floating point, because of NaNs. */
5592 code = GET_CODE (true_expr);
5593 if (GET_MODE (cc) != CC_FPmode)
5595 code = reverse_condition (code);
5605 check_insn = gen_rtx_SET (VOIDmode, cr,
5606 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5608 /* Record the check insn to be inserted later. */
5609 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5611 /* Update the tests. */
5612 frv_ifcvt.cr_reg = cr;
5613 frv_ifcvt.nested_cc_reg = nested_cc;
5614 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5615 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5618 /* Fail, don't do this conditional execution. */
5621 *p_false = NULL_RTX;
5623 fprintf (dump_file, "Disabling this conditional execution.\n");
5629 /* A C expression to modify the code described by the conditional if
5630 information CE_INFO, for the basic block BB, possibly updating the tests in
5631 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5632 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5633 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5635 /* p_true and p_false are given expressions of the form:
5637 (and (eq:CC_CCR (reg:CC_CCR)
5643 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5648 rtx old_true = XEXP (*p_true, 0);
5649 rtx old_false = XEXP (*p_false, 0);
5650 rtx true_expr = XEXP (*p_true, 1);
5651 rtx false_expr = XEXP (*p_false, 1);
5654 rtx cr = XEXP (old_true, 0);
5656 rtx new_cr = NULL_RTX;
5657 rtx *p_new_cr = (rtx *)0;
5661 enum reg_class cr_class;
5662 enum machine_mode mode = GET_MODE (true_expr);
5663 rtx (*logical_func)(rtx, rtx, rtx);
5665 if (TARGET_DEBUG_COND_EXEC)
5668 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5669 ce_info->and_and_p ? "&&" : "||");
5671 debug_rtx (*p_true);
5673 fputs ("\nfalse insn:\n", stderr);
5674 debug_rtx (*p_false);
5677 if (!TARGET_MULTI_CE)
5680 if (GET_CODE (cr) != REG)
5683 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5685 cr_class = ICR_REGS;
5686 p_new_cr = &frv_ifcvt.extra_int_cr;
5688 else if (mode == CC_FPmode)
5690 cr_class = FCR_REGS;
5691 p_new_cr = &frv_ifcvt.extra_fp_cr;
5696 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5697 more &&/|| tests. */
5701 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5702 CC_CCRmode, TRUE, TRUE);
5707 if (ce_info->and_and_p)
5709 old_test = old_false;
5710 test_expr = true_expr;
5711 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5712 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5713 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5717 old_test = old_false;
5718 test_expr = false_expr;
5719 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5720 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5721 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5724 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5725 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5727 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5729 /* Now add the conditional check insn. */
5730 cc = XEXP (test_expr, 0);
5731 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5732 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5734 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5736 /* Add the new check insn to the list of check insns that need to be
5738 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5740 if (TARGET_DEBUG_COND_EXEC)
5742 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5745 debug_rtx (*p_true);
5747 fputs ("\nfalse insn:\n", stderr);
5748 debug_rtx (*p_false);
5754 *p_true = *p_false = NULL_RTX;
5756 /* If we allocated a CR register, release it. */
5759 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5760 *p_new_cr = NULL_RTX;
5763 if (TARGET_DEBUG_COND_EXEC)
5764 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5770 /* Return a register which will be loaded with a value if an IF block is
5771 converted to conditional execution. This is used to rewrite instructions
5772 that use constants to ones that just use registers. */
5775 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5777 int num_alloc = frv_ifcvt.cur_scratch_regs;
5781 /* We know gr0 == 0, so replace any errant uses. */
5782 if (value == const0_rtx)
5783 return gen_rtx_REG (SImode, GPR_FIRST);
5785 /* First search all registers currently loaded to see if we have an
5786 applicable constant. */
5787 if (CONSTANT_P (value)
5788 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5790 for (i = 0; i < num_alloc; i++)
5792 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5793 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5797 /* Have we exhausted the number of registers available? */
5798 if (num_alloc >= GPR_TEMP_NUM)
5801 fprintf (dump_file, "Too many temporary registers allocated\n");
5806 /* Allocate the new register. */
5807 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5811 fputs ("Could not find a scratch register\n", dump_file);
5816 frv_ifcvt.cur_scratch_regs++;
5817 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5821 if (GET_CODE (value) == CONST_INT)
5822 fprintf (dump_file, "Register %s will hold %ld\n",
5823 reg_names[ REGNO (reg)], (long)INTVAL (value));
5825 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5826 fprintf (dump_file, "Register %s will hold LR\n",
5827 reg_names[ REGNO (reg)]);
5830 fprintf (dump_file, "Register %s will hold a saved value\n",
5831 reg_names[ REGNO (reg)]);
5838 /* Update a MEM used in conditional code that might contain an offset to put
5839 the offset into a scratch register, so that the conditional load/store
5840 operations can be used. This function returns the original pointer if the
5841 MEM is valid to use in conditional code, NULL if we can't load up the offset
5842 into a temporary register, or the new MEM if we were successful. */
5845 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5847 rtx addr = XEXP (mem, 0);
5849 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
5851 if (GET_CODE (addr) == PLUS)
5853 rtx addr_op0 = XEXP (addr, 0);
5854 rtx addr_op1 = XEXP (addr, 1);
5856 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5858 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5862 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5869 else if (CONSTANT_P (addr))
5870 addr = frv_ifcvt_load_value (addr, insn);
5875 if (addr == NULL_RTX)
5878 else if (XEXP (mem, 0) != addr)
5879 return change_address (mem, mode, addr);
5886 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5887 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5890 single_set_pattern (rtx pattern)
5895 if (GET_CODE (pattern) == COND_EXEC)
5896 pattern = COND_EXEC_CODE (pattern);
5898 if (GET_CODE (pattern) == SET)
5901 else if (GET_CODE (pattern) == PARALLEL)
5903 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5905 rtx sub = XVECEXP (pattern, 0, i);
5907 switch (GET_CODE (sub))
5931 /* A C expression to modify the code described by the conditional if
5932 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5933 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5934 insn cannot be converted to be executed conditionally. */
5937 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5941 rtx orig_ce_pattern = pattern;
5947 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5949 test = COND_EXEC_TEST (pattern);
5950 if (GET_CODE (test) == AND)
5952 rtx cr = frv_ifcvt.cr_reg;
5955 op0 = XEXP (test, 0);
5956 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5959 op1 = XEXP (test, 1);
5960 test_reg = XEXP (op1, 0);
5961 if (GET_CODE (test_reg) != REG)
5964 /* Is this the first nested if block in this sequence? If so, generate
5965 an andcr or andncr. */
5966 if (! frv_ifcvt.last_nested_if_cr)
5970 frv_ifcvt.last_nested_if_cr = test_reg;
5971 if (GET_CODE (op0) == NE)
5972 and_op = gen_andcr (test_reg, cr, test_reg);
5974 and_op = gen_andncr (test_reg, cr, test_reg);
5976 frv_ifcvt_add_insn (and_op, insn, TRUE);
5979 /* If this isn't the first statement in the nested if sequence, see if we
5980 are dealing with the same register. */
5981 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5984 COND_EXEC_TEST (pattern) = test = op1;
5987 /* If this isn't a nested if, reset state variables. */
5990 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5993 set = single_set_pattern (pattern);
5996 rtx dest = SET_DEST (set);
5997 rtx src = SET_SRC (set);
5998 enum machine_mode mode = GET_MODE (dest);
6000 /* Check for normal binary operators. */
6001 if (mode == SImode && ARITHMETIC_P (src))
6003 op0 = XEXP (src, 0);
6004 op1 = XEXP (src, 1);
6006 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6008 op1 = frv_ifcvt_load_value (op1, insn);
6010 COND_EXEC_CODE (pattern)
6011 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6019 /* For multiply by a constant, we need to handle the sign extending
6020 correctly. Add a USE of the value after the multiply to prevent flow
6021 from cratering because only one register out of the two were used. */
6022 else if (mode == DImode && GET_CODE (src) == MULT)
6024 op0 = XEXP (src, 0);
6025 op1 = XEXP (src, 1);
6026 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6028 op1 = frv_ifcvt_load_value (op1, insn);
6031 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6032 COND_EXEC_CODE (pattern)
6033 = gen_rtx_SET (VOIDmode, dest,
6034 gen_rtx_MULT (DImode, op0, op1));
6040 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6043 /* If we are just loading a constant created for a nested conditional
6044 execution statement, just load the constant without any conditional
6045 execution, since we know that the constant will not interfere with any
6047 else if (frv_ifcvt.scratch_insns_bitmap
6048 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6050 && REG_P (SET_DEST (set))
6051 /* We must not unconditionally set a scratch reg chosen
6052 for a nested if-converted block if its incoming
6053 value from the TEST block (or the result of the THEN
6054 branch) could/should propagate to the JOIN block.
6055 It suffices to test whether the register is live at
6056 the JOIN point: if it's live there, we can infer
6057 that we set it in the former JOIN block of the
6058 nested if-converted block (otherwise it wouldn't
6059 have been available as a scratch register), and it
6060 is either propagated through or set in the other
6061 conditional block. It's probably not worth trying
6062 to catch the latter case, and it could actually
6063 limit scheduling of the combined block quite
6066 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6067 REGNO (SET_DEST (set))))
6068 /* Similarly, we must not unconditionally set a reg
6069 used as scratch in the THEN branch if the same reg
6070 is live in the ELSE branch. */
6071 && (! ce_info->else_bb
6072 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6073 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6074 REGNO (SET_DEST (set))))))
6077 else if (mode == QImode || mode == HImode || mode == SImode
6080 int changed_p = FALSE;
6082 /* Check for just loading up a constant */
6083 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6085 src = frv_ifcvt_load_value (src, insn);
6092 /* See if we need to fix up stores */
6093 if (GET_CODE (dest) == MEM)
6095 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6100 else if (new_mem != dest)
6107 /* See if we need to fix up loads */
6108 if (GET_CODE (src) == MEM)
6110 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6115 else if (new_mem != src)
6122 /* If either src or destination changed, redo SET. */
6124 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6127 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6128 rewriting the CC register to be the same as the paired CC/CR register
6130 else if (mode == CC_CCRmode && COMPARISON_P (src))
6132 int regno = REGNO (XEXP (src, 0));
6135 if (ce_info->pass > 1
6136 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6137 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6139 src = gen_rtx_fmt_ee (GET_CODE (src),
6141 frv_ifcvt.nested_cc_reg,
6145 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6146 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6149 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6150 else if (ce_info->pass > 1
6151 && GET_CODE (dest) == REG
6152 && CC_P (REGNO (dest))
6153 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6154 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6156 && GET_CODE (src) == COMPARE)
6158 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6159 COND_EXEC_CODE (pattern)
6160 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6164 if (TARGET_DEBUG_COND_EXEC)
6166 rtx orig_pattern = PATTERN (insn);
6168 PATTERN (insn) = pattern;
6170 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6174 PATTERN (insn) = orig_pattern;
6180 if (TARGET_DEBUG_COND_EXEC)
6182 rtx orig_pattern = PATTERN (insn);
6184 PATTERN (insn) = orig_ce_pattern;
6186 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6190 PATTERN (insn) = orig_pattern;
6197 /* A C expression to perform any final machine dependent modifications in
6198 converting code to conditional execution in the code described by the
6199 conditional if information CE_INFO. */
6202 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6206 rtx p = frv_ifcvt.added_insns_list;
6209 /* Loop inserting the check insns. The last check insn is the first test,
6210 and is the appropriate place to insert constants. */
6215 rtx check_and_insert_insns = XEXP (p, 0);
6218 check_insn = XEXP (check_and_insert_insns, 0);
6219 existing_insn = XEXP (check_and_insert_insns, 1);
6222 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6223 the existing insn, otherwise it is to be inserted AFTER. */
6224 if (check_and_insert_insns->jump)
6226 emit_insn_before (check_insn, existing_insn);
6227 check_and_insert_insns->jump = 0;
6230 emit_insn_after (check_insn, existing_insn);
6232 free_EXPR_LIST_node (check_and_insert_insns);
6233 free_EXPR_LIST_node (old_p);
6235 while (p != NULL_RTX);
6237 /* Load up any constants needed into temp gprs */
6238 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6240 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6241 if (! frv_ifcvt.scratch_insns_bitmap)
6242 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6243 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6244 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6247 frv_ifcvt.added_insns_list = NULL_RTX;
6248 frv_ifcvt.cur_scratch_regs = 0;
6252 /* A C expression to cancel any machine dependent modifications in converting
6253 code to conditional execution in the code described by the conditional if
6254 information CE_INFO. */
6257 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6260 rtx p = frv_ifcvt.added_insns_list;
6262 /* Loop freeing up the EXPR_LIST's allocated. */
6263 while (p != NULL_RTX)
6265 rtx check_and_jump = XEXP (p, 0);
6269 free_EXPR_LIST_node (check_and_jump);
6270 free_EXPR_LIST_node (old_p);
6273 /* Release any temporary gprs allocated. */
6274 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6275 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6277 frv_ifcvt.added_insns_list = NULL_RTX;
6278 frv_ifcvt.cur_scratch_regs = 0;
6282 /* A C expression for the size in bytes of the trampoline, as an integer.
6286 setlo #0, <static_chain>
6288 sethi #0, <static_chain>
6289 jmpl @(gr0,<jmp_reg>) */
6292 frv_trampoline_size (void)
6295 /* Allocate room for the function descriptor and the lddi
6298 return 5 /* instructions */ * 4 /* instruction size. */;
6302 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6303 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6304 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6305 should be passed to the function when it is called.
6310 setlo #0, <static_chain>
6312 sethi #0, <static_chain>
6313 jmpl @(gr0,<jmp_reg>) */
6316 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
6318 rtx sc_reg = force_reg (Pmode, static_chain);
6320 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6323 GEN_INT (frv_trampoline_size ()), SImode,
6329 /* Many machines have some registers that cannot be copied directly to or from
6330 memory or even from other types of registers. An example is the `MQ'
6331 register, which on most machines, can only be copied to or from general
6332 registers, but not memory. Some machines allow copying all registers to and
6333 from memory, but require a scratch register for stores to some memory
6334 locations (e.g., those with symbolic address on the RT, and those with
6335 certain symbolic address on the SPARC when compiling PIC). In some cases,
6336 both an intermediate and a scratch register are required.
6338 You should define these macros to indicate to the reload phase that it may
6339 need to allocate at least one register for a reload in addition to the
6340 register to contain the data. Specifically, if copying X to a register
6341 RCLASS in MODE requires an intermediate register, you should define
6342 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6343 whose registers can be used as intermediate registers or scratch registers.
6345 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6346 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6347 largest register class required. If the requirements for input and output
6348 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6349 instead of defining both macros identically.
6351 The values returned by these macros are often `GENERAL_REGS'. Return
6352 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6353 to or from a register of RCLASS in MODE without requiring a scratch register.
6354 Do not define this macro if it would always return `NO_REGS'.
6356 If a scratch register is required (either with or without an intermediate
6357 register), you should define patterns for `reload_inM' or `reload_outM', as
6358 required.. These patterns, which will normally be implemented with a
6359 `define_expand', should be similar to the `movM' patterns, except that
6360 operand 2 is the scratch register.
6362 Define constraints for the reload register and scratch register that contain
6363 a single register class. If the original reload register (whose class is
6364 RCLASS) can meet the constraint given in the pattern, the value returned by
6365 these macros is used for the class of the scratch register. Otherwise, two
6366 additional reload registers are required. Their classes are obtained from
6367 the constraints in the insn pattern.
6369 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6370 either be in a hard register or in memory. Use `true_regnum' to find out;
6371 it will return -1 if the pseudo is in memory and the hard register number if
6372 it is in a register.
6374 These macros should not be used in the case where a particular class of
6375 registers can only be copied to memory and not to another class of
6376 registers. In that case, secondary reload registers are not needed and
6377 would not be helpful. Instead, a stack location must be used to perform the
6378 copy and the `movM' pattern should use memory as an intermediate storage.
6379 This case often occurs between floating-point and general registers. */
6382 frv_secondary_reload_class (enum reg_class rclass,
6383 enum machine_mode mode ATTRIBUTE_UNUSED,
6394 /* Accumulators/Accumulator guard registers need to go through floating
6400 if (x && GET_CODE (x) == REG)
6402 int regno = REGNO (x);
6404 if (ACC_P (regno) || ACCG_P (regno))
6409 /* Nonzero constants should be loaded into an FPR through a GPR. */
6413 if (x && CONSTANT_P (x) && !ZERO_P (x))
6419 /* All of these types need gpr registers. */
6431 /* The accumulators need fpr registers. */
6443 /* This hook exists to catch the case where secondary_reload_class() is
6444 called from init_reg_autoinc() in regclass.c - before the reload optabs
6445 have been initialised. */
6448 frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
6449 enum machine_mode reload_mode,
6450 secondary_reload_info * sri)
6452 enum reg_class rclass = NO_REGS;
6454 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6456 sri->icode = sri->prev_sri->t_icode;
6460 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6462 if (rclass != NO_REGS)
6464 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
6465 : reload_out_optab[(int) reload_mode]);
6468 /* This happens when then the reload_[in|out]_optabs have
6469 not been initialised. */
6470 sri->t_icode = CODE_FOR_nothing;
6475 /* Fall back to the default secondary reload handler. */
6476 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6480 /* A C expression whose value is nonzero if pseudos that have been assigned to
6481 registers of class RCLASS would likely be spilled because registers of RCLASS
6482 are needed for spill registers.
6484 The default value of this macro returns 1 if RCLASS has exactly one register
6485 and zero otherwise. On most machines, this default should be used. Only
6486 define this macro to some other expression if pseudo allocated by
6487 `local-alloc.c' end up in memory because their hard registers were needed
6488 for spill registers. If this macro returns nonzero for those classes, those
6489 pseudos will only be allocated by `global.c', which knows how to reallocate
6490 the pseudo to another register. If there would not be another register
6491 available for reallocation, you should not change the definition of this
6492 macro since the only effect of such a definition would be to slow down
6493 register allocation. */
6496 frv_class_likely_spilled_p (enum reg_class rclass)
6506 case FDPIC_FPTR_REGS:
6528 /* An expression for the alignment of a structure field FIELD if the
6529 alignment computed in the usual way is COMPUTED. GCC uses this
6530 value instead of the value in `BIGGEST_ALIGNMENT' or
6531 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6533 /* The definition type of the bit field data is either char, short, long or
6534 long long. The maximum bit size is the number of bits of its own type.
6536 The bit field data is assigned to a storage unit that has an adequate size
6537 for bit field data retention and is located at the smallest address.
6539 Consecutive bit field data are packed at consecutive bits having the same
6540 storage unit, with regard to the type, beginning with the MSB and continuing
6543 If a field to be assigned lies over a bit field type boundary, its
6544 assignment is completed by aligning it with a boundary suitable for the
6547 When a bit field having a bit length of 0 is declared, it is forcibly
6548 assigned to the next storage unit.
6561 &x 00000000 00000000 00000000 00000000
6564 &x+4 00000000 00000000 00000000 00000000
6567 &x+8 00000000 00000000 00000000 00000000
6570 &x+12 00000000 00000000 00000000 00000000
6576 frv_adjust_field_align (tree field, int computed)
6578 /* Make sure that the bitfield is not wider than the type. */
6579 if (DECL_BIT_FIELD (field)
6580 && !DECL_ARTIFICIAL (field))
6582 tree parent = DECL_CONTEXT (field);
6583 tree prev = NULL_TREE;
6586 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6588 if (TREE_CODE (cur) != FIELD_DECL)
6596 /* If this isn't a :0 field and if the previous element is a bitfield
6597 also, see if the type is different, if so, we will need to align the
6598 bit-field to the next boundary. */
6600 && ! DECL_PACKED (field)
6601 && ! integer_zerop (DECL_SIZE (field))
6602 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6604 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6605 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6606 computed = (prev_align > cur_align) ? prev_align : cur_align;
6614 /* A C expression that is nonzero if it is permissible to store a value of mode
6615 MODE in hard register number REGNO (or in several registers starting with
6616 that one). For a machine where all registers are equivalent, a suitable
6619 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6621 It is not necessary for this macro to check for the numbers of fixed
6622 registers, because the allocation mechanism considers them to be always
6625 On some machines, double-precision values must be kept in even/odd register
6626 pairs. The way to implement that is to define this macro to reject odd
6627 register numbers for such modes.
6629 The minimum requirement for a mode to be OK in a register is that the
6630 `movMODE' instruction pattern support moves between the register and any
6631 other hard register for which the mode is OK; and that moving a value into
6632 the register and back out not alter it.
6634 Since the same instruction used to move `SImode' will work for all narrower
6635 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6636 to distinguish between these modes, provided you define patterns `movhi',
6637 etc., to take advantage of this. This is useful because of the interaction
6638 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6639 all integer modes to be tieable.
6641 Many machines have special registers for floating point arithmetic. Often
6642 people assume that floating point machine modes are allowed only in floating
6643 point registers. This is not true. Any registers that can hold integers
6644 can safely *hold* a floating point machine mode, whether or not floating
6645 arithmetic can be done on it in those registers. Integer move instructions
6646 can be used to move the values.
6648 On some machines, though, the converse is true: fixed-point machine modes
6649 may not go in floating registers. This is true if the floating registers
6650 normalize any value stored in them, because storing a non-floating value
6651 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6652 fixed-point machine modes in floating registers. But if the floating
6653 registers do not automatically normalize, if you can store any bit pattern
6654 in one and retrieve it unchanged without a trap, then any machine mode may
6655 go in a floating register, so you can define this macro to say so.
6657 The primary significance of special floating registers is rather that they
6658 are the registers acceptable in floating point arithmetic instructions.
6659 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6660 writing the proper constraints for those instructions.
6662 On some machines, the floating registers are especially slow to access, so
6663 that it is better to store a value in a stack frame than in such a register
6664 if floating point arithmetic is not being done. As long as the floating
6665 registers are not in class `GENERAL_REGS', they will not be used unless some
6666 pattern's constraint asks for one. */
6669 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6679 return ICC_P (regno) || GPR_P (regno);
6682 return CR_P (regno) || GPR_P (regno);
6685 return FCC_P (regno) || GPR_P (regno);
6691 /* Set BASE to the first register in REGNO's class. Set MASK to the
6692 bits that must be clear in (REGNO - BASE) for the register to be
6694 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6698 /* ACCGs store one byte. Two-byte quantities must start in
6699 even-numbered registers, four-byte ones in registers whose
6700 numbers are divisible by four, and so on. */
6702 mask = GET_MODE_SIZE (mode) - 1;
6706 /* The other registers store one word. */
6707 if (GPR_P (regno) || regno == AP_FIRST)
6710 else if (FPR_P (regno))
6713 else if (ACC_P (regno))
6716 else if (SPR_P (regno))
6717 return mode == SImode;
6719 /* Fill in the table. */
6723 /* Anything smaller than an SI is OK in any word-sized register. */
6724 if (GET_MODE_SIZE (mode) < 4)
6727 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6729 return (((regno - base) & mask) == 0);
6736 /* A C expression for the number of consecutive hard registers, starting at
6737 register number REGNO, required to hold a value of mode MODE.
6739 On a machine where all registers are exactly one word, a suitable definition
6742 #define HARD_REGNO_NREGS(REGNO, MODE) \
6743 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6744 / UNITS_PER_WORD)) */
6746 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6747 that we can build the appropriate instructions to properly reload the
6748 values. Also, make the byte-sized accumulator guards use one guard
6752 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6755 return GET_MODE_SIZE (mode);
6757 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6761 /* A C expression for the maximum number of consecutive registers of
6762 class RCLASS needed to hold a value of mode MODE.
6764 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6765 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6766 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6768 This macro helps control the handling of multiple-word values in
6771 This declaration is required. */
6774 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6776 if (rclass == ACCG_REGS)
6777 /* An N-byte value requires N accumulator guards. */
6778 return GET_MODE_SIZE (mode);
6780 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6784 /* A C expression that is nonzero if X is a legitimate constant for an
6785 immediate operand on the target machine. You can assume that X satisfies
6786 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6787 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6790 frv_legitimate_constant_p (rtx x)
6792 enum machine_mode mode = GET_MODE (x);
6794 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6795 means that the move expanders will be expected to deal with most
6796 kinds of constant, regardless of what we return here.
6798 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6799 a constant can be entered into reg_equiv_constant[]. If we return true,
6800 reload can create new instances of the constant whenever it likes.
6802 The idea is therefore to accept as many constants as possible (to give
6803 reload more freedom) while rejecting constants that can only be created
6804 at certain times. In particular, anything with a symbolic component will
6805 require use of the pseudo FDPIC register, which is only available before
6808 return LEGITIMATE_PIC_OPERAND_P (x);
6810 /* All of the integer constants are ok. */
6811 if (GET_CODE (x) != CONST_DOUBLE)
6814 /* double integer constants are ok. */
6815 if (mode == VOIDmode || mode == DImode)
6818 /* 0 is always ok. */
6819 if (x == CONST0_RTX (mode))
6822 /* If floating point is just emulated, allow any constant, since it will be
6823 constructed in the GPRs. */
6824 if (!TARGET_HAS_FPRS)
6827 if (mode == DFmode && !TARGET_DOUBLE)
6830 /* Otherwise store the constant away and do a load. */
6834 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6835 CC_NZ for comparisons against zero in which a single Z or N flag test
6836 is enough, CC_UNS for other unsigned comparisons, and CC for other
6837 signed comparisons. */
6840 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6842 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6851 return y == const0_rtx ? CC_NZmode : CCmode;
6857 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6864 /* A C expression for the cost of moving data from a register in class FROM to
6865 one in class TO. The classes are expressed using the enumeration values
6866 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6867 interpreted relative to that.
6869 It is not required that the cost always equal 2 when FROM is the same as TO;
6870 on some machines it is expensive to move between registers if they are not
6873 If reload sees an insn consisting of a single `set' between two hard
6874 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6875 value of 2, reload does not check to ensure that the constraints of the insn
6876 are met. Setting a cost of other than 2 will allow reload to verify that
6877 the constraints are met. You should do this if the `movM' pattern's
6878 constraints do not allow such copying. */
6880 #define HIGH_COST 40
6881 #define MEDIUM_COST 3
6885 frv_register_move_cost (enum reg_class from, enum reg_class to)
6969 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6970 use ".picptr" to generate safe relocations for PIC code. We also
6971 need a fixup entry for aligned (non-debugging) code. */
6974 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6976 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6978 if (GET_CODE (value) == CONST
6979 || GET_CODE (value) == SYMBOL_REF
6980 || GET_CODE (value) == LABEL_REF)
6982 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6983 && SYMBOL_REF_FUNCTION_P (value))
6985 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6986 output_addr_const (asm_out_file, value);
6987 fputs (")\n", asm_out_file);
6990 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6991 && frv_function_symbol_referenced_p (value))
6993 if (aligned_p && !TARGET_FDPIC)
6995 static int label_num = 0;
6999 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7000 p = (* targetm.strip_name_encoding) (buf);
7002 fprintf (asm_out_file, "%s:\n", p);
7003 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7004 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7005 fprintf (asm_out_file, "\t.previous\n");
7007 assemble_integer_with_op ("\t.picptr\t", value);
7012 /* We've set the unaligned SI op to NULL, so we always have to
7013 handle the unaligned case here. */
7014 assemble_integer_with_op ("\t.4byte\t", value);
7018 return default_assemble_integer (value, size, aligned_p);
7021 /* Function to set up the backend function structure. */
7023 static struct machine_function *
7024 frv_init_machine_status (void)
7026 return GGC_CNEW (struct machine_function);
7029 /* Implement TARGET_SCHED_ISSUE_RATE. */
7032 frv_issue_rate (void)
7037 switch (frv_cpu_type)
7041 case FRV_CPU_SIMPLE:
7049 case FRV_CPU_GENERIC:
7051 case FRV_CPU_TOMCAT:
7059 /* A for_each_rtx callback. If X refers to an accumulator, return
7060 ACC_GROUP_ODD if the bit 2 of the register number is set and
7061 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7065 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7069 if (ACC_P (REGNO (*x)))
7070 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7071 if (ACCG_P (REGNO (*x)))
7072 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7077 /* Return the value of INSN's acc_group attribute. */
7080 frv_acc_group (rtx insn)
7082 /* This distinction only applies to the FR550 packing constraints. */
7083 if (frv_cpu_type != FRV_CPU_FR550)
7084 return ACC_GROUP_NONE;
7085 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7088 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7089 INSN will try to claim first. Since this value depends only on the
7090 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7093 frv_insn_unit (rtx insn)
7095 enum attr_type type;
7097 type = get_attr_type (insn);
7098 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7100 /* We haven't seen this type of instruction before. */
7104 /* Issue the instruction on its own to see which unit it prefers. */
7105 state = alloca (state_size ());
7106 state_reset (state);
7107 state_transition (state, insn);
7109 /* Find out which unit was taken. */
7110 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7111 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7114 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7116 frv_type_to_unit[type] = unit;
7118 return frv_type_to_unit[type];
7121 /* Return true if INSN issues to a branch unit. */
7124 frv_issues_to_branch_unit_p (rtx insn)
7126 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7129 /* The current state of the packing pass, implemented by frv_pack_insns. */
7131 /* The state of the pipeline DFA. */
7134 /* Which hardware registers are set within the current packet,
7135 and the conditions under which they are set. */
7136 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7138 /* The memory locations that have been modified so far in this
7139 packet. MEM is the memref and COND is the regstate_t condition
7140 under which it is set. */
7146 /* The number of valid entries in MEMS. The value is larger than
7147 ARRAY_SIZE (mems) if there were too many mems to record. */
7148 unsigned int num_mems;
7150 /* The maximum number of instructions that can be packed together. */
7151 unsigned int issue_rate;
7153 /* The instructions in the packet, partitioned into groups. */
7154 struct frv_packet_group {
7155 /* How many instructions in the packet belong to this group. */
7156 unsigned int num_insns;
7158 /* A list of the instructions that belong to this group, in the order
7159 they appear in the rtl stream. */
7160 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7162 /* The contents of INSNS after they have been sorted into the correct
7163 assembly-language order. Element X issues to unit X. The list may
7164 contain extra nops. */
7165 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7167 /* The member of frv_nops[] to use in sorted[]. */
7169 } groups[NUM_GROUPS];
7171 /* The instructions that make up the current packet. */
7172 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7173 unsigned int num_insns;
7176 /* Return the regstate_t flags for the given COND_EXEC condition.
7177 Abort if the condition isn't in the right form. */
7180 frv_cond_flags (rtx cond)
7182 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7183 && GET_CODE (XEXP (cond, 0)) == REG
7184 && CR_P (REGNO (XEXP (cond, 0)))
7185 && XEXP (cond, 1) == const0_rtx);
7186 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7187 | (GET_CODE (cond) == NE
7189 : REGSTATE_IF_FALSE));
7193 /* Return true if something accessed under condition COND2 can
7194 conflict with something written under condition COND1. */
7197 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7199 /* If either reference was unconditional, we have a conflict. */
7200 if ((cond1 & REGSTATE_IF_EITHER) == 0
7201 || (cond2 & REGSTATE_IF_EITHER) == 0)
7204 /* The references might conflict if they were controlled by
7206 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7209 /* They definitely conflict if they are controlled by the
7211 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7218 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7219 the current packet. DATA points to a regstate_t that describes the
7220 condition under which *X might be set or used. */
7223 frv_registers_conflict_p_1 (rtx *x, void *data)
7225 unsigned int regno, i;
7228 cond = *(regstate_t *) data;
7230 if (GET_CODE (*x) == REG)
7231 FOR_EACH_REGNO (regno, *x)
7232 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7233 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7236 if (GET_CODE (*x) == MEM)
7238 /* If we ran out of memory slots, assume a conflict. */
7239 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7242 /* Check for output or true dependencies with earlier MEMs. */
7243 for (i = 0; i < frv_packet.num_mems; i++)
7244 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7246 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7250 if (output_dependence (frv_packet.mems[i].mem, *x))
7255 /* The return values of calls aren't significant: they describe
7256 the effect of the call as a whole, not of the insn itself. */
7257 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7259 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7264 /* Check subexpressions. */
7269 /* Return true if something in X might depend on an instruction
7270 in the current packet. */
7273 frv_registers_conflict_p (rtx x)
7278 if (GET_CODE (x) == COND_EXEC)
7280 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7283 flags |= frv_cond_flags (XEXP (x, 0));
7286 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7290 /* A note_stores callback. DATA points to the regstate_t condition
7291 under which X is modified. Update FRV_PACKET accordingly. */
7294 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7298 if (GET_CODE (x) == REG)
7299 FOR_EACH_REGNO (regno, x)
7300 frv_packet.regstate[regno] |= *(regstate_t *) data;
7302 if (GET_CODE (x) == MEM)
7304 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7306 frv_packet.mems[frv_packet.num_mems].mem = x;
7307 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7309 frv_packet.num_mems++;
7314 /* Update the register state information for an instruction whose
7318 frv_registers_update (rtx x)
7322 flags = REGSTATE_MODIFIED;
7323 if (GET_CODE (x) == COND_EXEC)
7325 flags |= frv_cond_flags (XEXP (x, 0));
7328 note_stores (x, frv_registers_update_1, &flags);
7332 /* Initialize frv_packet for the start of a new packet. */
7335 frv_start_packet (void)
7337 enum frv_insn_group group;
7339 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7340 frv_packet.num_mems = 0;
7341 frv_packet.num_insns = 0;
7342 for (group = 0; group < NUM_GROUPS; group++)
7343 frv_packet.groups[group].num_insns = 0;
7347 /* Likewise for the start of a new basic block. */
7350 frv_start_packet_block (void)
7352 state_reset (frv_packet.dfa_state);
7353 frv_start_packet ();
7357 /* Finish the current packet, if any, and start a new one. Call
7358 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7361 frv_finish_packet (void (*handle_packet) (void))
7363 if (frv_packet.num_insns > 0)
7366 state_transition (frv_packet.dfa_state, 0);
7367 frv_start_packet ();
7372 /* Return true if INSN can be added to the current packet. Update
7373 the DFA state on success. */
7376 frv_pack_insn_p (rtx insn)
7378 /* See if the packet is already as long as it can be. */
7379 if (frv_packet.num_insns == frv_packet.issue_rate)
7382 /* If the scheduler thought that an instruction should start a packet,
7383 it's usually a good idea to believe it. It knows much more about
7384 the latencies than we do.
7386 There are some exceptions though:
7388 - Conditional instructions are scheduled on the assumption that
7389 they will be executed. This is usually a good thing, since it
7390 tends to avoid unnecessary stalls in the conditional code.
7391 But we want to pack conditional instructions as tightly as
7392 possible, in order to optimize the case where they aren't
7395 - The scheduler will always put branches on their own, even
7396 if there's no real dependency.
7398 - There's no point putting a call in its own packet unless
7400 if (frv_packet.num_insns > 0
7401 && GET_CODE (insn) == INSN
7402 && GET_MODE (insn) == TImode
7403 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7406 /* Check for register conflicts. Don't do this for setlo since any
7407 conflict will be with the partnering sethi, with which it can
7409 if (get_attr_type (insn) != TYPE_SETLO)
7410 if (frv_registers_conflict_p (PATTERN (insn)))
7413 return state_transition (frv_packet.dfa_state, insn) < 0;
7417 /* Add instruction INSN to the current packet. */
7420 frv_add_insn_to_packet (rtx insn)
7422 struct frv_packet_group *packet_group;
7424 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7425 packet_group->insns[packet_group->num_insns++] = insn;
7426 frv_packet.insns[frv_packet.num_insns++] = insn;
7428 frv_registers_update (PATTERN (insn));
7432 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7433 packet ends in a branch or call, insert the nop before it, otherwise
7437 frv_insert_nop_in_packet (rtx insn)
7439 struct frv_packet_group *packet_group;
7442 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7443 last = frv_packet.insns[frv_packet.num_insns - 1];
7444 if (GET_CODE (last) != INSN)
7446 insn = emit_insn_before (PATTERN (insn), last);
7447 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7448 frv_packet.insns[frv_packet.num_insns++] = last;
7452 insn = emit_insn_after (PATTERN (insn), last);
7453 frv_packet.insns[frv_packet.num_insns++] = insn;
7455 packet_group->insns[packet_group->num_insns++] = insn;
7459 /* If packing is enabled, divide the instructions into packets and
7460 return true. Call HANDLE_PACKET for each complete packet. */
7463 frv_for_each_packet (void (*handle_packet) (void))
7465 rtx insn, next_insn;
7467 frv_packet.issue_rate = frv_issue_rate ();
7469 /* Early exit if we don't want to pack insns. */
7471 || !flag_schedule_insns_after_reload
7472 || !TARGET_VLIW_BRANCH
7473 || frv_packet.issue_rate == 1)
7476 /* Set up the initial packing state. */
7478 frv_packet.dfa_state = alloca (state_size ());
7480 frv_start_packet_block ();
7481 for (insn = get_insns (); insn != 0; insn = next_insn)
7486 code = GET_CODE (insn);
7487 next_insn = NEXT_INSN (insn);
7489 if (code == CODE_LABEL)
7491 frv_finish_packet (handle_packet);
7492 frv_start_packet_block ();
7496 switch (GET_CODE (PATTERN (insn)))
7505 /* Calls mustn't be packed on a TOMCAT. */
7506 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7507 frv_finish_packet (handle_packet);
7509 /* Since the last instruction in a packet determines the EH
7510 region, any exception-throwing instruction must come at
7511 the end of reordered packet. Insns that issue to a
7512 branch unit are bound to come last; for others it's
7513 too hard to predict. */
7514 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7515 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7516 frv_finish_packet (handle_packet);
7518 /* Finish the current packet if we can't add INSN to it.
7519 Simulate cycles until INSN is ready to issue. */
7520 if (!frv_pack_insn_p (insn))
7522 frv_finish_packet (handle_packet);
7523 while (!frv_pack_insn_p (insn))
7524 state_transition (frv_packet.dfa_state, 0);
7527 /* Add the instruction to the packet. */
7528 frv_add_insn_to_packet (insn);
7530 /* Calls and jumps end a packet, as do insns that throw
7532 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7533 frv_finish_packet (handle_packet);
7537 frv_finish_packet (handle_packet);
7542 /* Subroutine of frv_sort_insn_group. We are trying to sort
7543 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7544 language order. We have already picked a new position for
7545 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7546 These instructions will occupy elements [0, LOWER_SLOT) and
7547 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7548 the DFA state after issuing these instructions.
7550 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7551 of the unused instructions. Return true if one such permutation gives
7552 a valid ordering, leaving the successful permutation in sorted[].
7553 Do not modify sorted[] until a valid permutation is found. */
7556 frv_sort_insn_group_1 (enum frv_insn_group group,
7557 unsigned int lower_slot, unsigned int upper_slot,
7558 unsigned int issued, unsigned int num_insns,
7561 struct frv_packet_group *packet_group;
7567 /* Early success if we've filled all the slots. */
7568 if (lower_slot == upper_slot)
7571 packet_group = &frv_packet.groups[group];
7572 dfa_size = state_size ();
7573 test_state = alloca (dfa_size);
7575 /* Try issuing each unused instruction. */
7576 for (i = num_insns - 1; i + 1 != 0; i--)
7577 if (~issued & (1 << i))
7579 insn = packet_group->sorted[i];
7580 memcpy (test_state, state, dfa_size);
7581 if (state_transition (test_state, insn) < 0
7582 && cpu_unit_reservation_p (test_state,
7583 NTH_UNIT (group, upper_slot - 1))
7584 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7585 issued | (1 << i), num_insns,
7588 packet_group->sorted[upper_slot - 1] = insn;
7596 /* Compare two instructions by their frv_insn_unit. */
7599 frv_compare_insns (const void *first, const void *second)
7601 const rtx *const insn1 = (rtx const *) first,
7602 *const insn2 = (rtx const *) second;
7603 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7606 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7607 and sort it into assembly language order. See frv.md for a description of
7611 frv_sort_insn_group (enum frv_insn_group group)
7613 struct frv_packet_group *packet_group;
7614 unsigned int first, i, nop, max_unit, num_slots;
7615 state_t state, test_state;
7618 packet_group = &frv_packet.groups[group];
7620 /* Assume no nop is needed. */
7621 packet_group->nop = 0;
7623 if (packet_group->num_insns == 0)
7626 /* Copy insns[] to sorted[]. */
7627 memcpy (packet_group->sorted, packet_group->insns,
7628 sizeof (rtx) * packet_group->num_insns);
7630 /* Sort sorted[] by the unit that each insn tries to take first. */
7631 if (packet_group->num_insns > 1)
7632 qsort (packet_group->sorted, packet_group->num_insns,
7633 sizeof (rtx), frv_compare_insns);
7635 /* That's always enough for branch and control insns. */
7636 if (group == GROUP_B || group == GROUP_C)
7639 dfa_size = state_size ();
7640 state = alloca (dfa_size);
7641 test_state = alloca (dfa_size);
7643 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7644 consecutively and such that the DFA takes unit X when sorted[X]
7645 is added. Set STATE to the new DFA state. */
7646 state_reset (test_state);
7647 for (first = 0; first < packet_group->num_insns; first++)
7649 memcpy (state, test_state, dfa_size);
7650 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7651 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7655 /* If all the instructions issued in ascending order, we're done. */
7656 if (first == packet_group->num_insns)
7659 /* Add nops to the end of sorted[] and try each permutation until
7660 we find one that works. */
7661 for (nop = 0; nop < frv_num_nops; nop++)
7663 max_unit = frv_insn_unit (frv_nops[nop]);
7664 if (frv_unit_groups[max_unit] == group)
7666 packet_group->nop = frv_nops[nop];
7667 num_slots = UNIT_NUMBER (max_unit) + 1;
7668 for (i = packet_group->num_insns; i < num_slots; i++)
7669 packet_group->sorted[i] = frv_nops[nop];
7670 if (frv_sort_insn_group_1 (group, first, num_slots,
7671 (1 << first) - 1, num_slots, state))
7678 /* Sort the current packet into assembly-language order. Set packing
7679 flags as appropriate. */
7682 frv_reorder_packet (void)
7684 unsigned int cursor[NUM_GROUPS];
7685 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7686 unsigned int unit, to, from;
7687 enum frv_insn_group group;
7688 struct frv_packet_group *packet_group;
7690 /* First sort each group individually. */
7691 for (group = 0; group < NUM_GROUPS; group++)
7694 frv_sort_insn_group (group);
7697 /* Go through the unit template and try add an instruction from
7698 that unit's group. */
7700 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7702 group = frv_unit_groups[unit];
7703 packet_group = &frv_packet.groups[group];
7704 if (cursor[group] < packet_group->num_insns)
7706 /* frv_reorg should have added nops for us. */
7707 gcc_assert (packet_group->sorted[cursor[group]]
7708 != packet_group->nop);
7709 insns[to++] = packet_group->sorted[cursor[group]++];
7713 gcc_assert (to == frv_packet.num_insns);
7715 /* Clear the last instruction's packing flag, thus marking the end of
7716 a packet. Reorder the other instructions relative to it. */
7717 CLEAR_PACKING_FLAG (insns[to - 1]);
7718 for (from = 0; from < to - 1; from++)
7720 remove_insn (insns[from]);
7721 add_insn_before (insns[from], insns[to - 1], NULL);
7722 SET_PACKING_FLAG (insns[from]);
7727 /* Divide instructions into packets. Reorder the contents of each
7728 packet so that they are in the correct assembly-language order.
7730 Since this pass can change the raw meaning of the rtl stream, it must
7731 only be called at the last minute, just before the instructions are
7735 frv_pack_insns (void)
7737 if (frv_for_each_packet (frv_reorder_packet))
7738 frv_insn_packing_flag = 0;
7740 frv_insn_packing_flag = -1;
7743 /* See whether we need to add nops to group GROUP in order to
7744 make a valid packet. */
7747 frv_fill_unused_units (enum frv_insn_group group)
7749 unsigned int non_nops, nops, i;
7750 struct frv_packet_group *packet_group;
7752 packet_group = &frv_packet.groups[group];
7754 /* Sort the instructions into assembly-language order.
7755 Use nops to fill slots that are otherwise unused. */
7756 frv_sort_insn_group (group);
7758 /* See how many nops are needed before the final useful instruction. */
7760 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7761 while (packet_group->sorted[i++] == packet_group->nop)
7764 /* Insert that many nops into the instruction stream. */
7766 frv_insert_nop_in_packet (packet_group->nop);
7769 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7772 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7774 if (io1->const_address != 0 && io2->const_address != 0)
7775 return io1->const_address == io2->const_address;
7777 if (io1->var_address != 0 && io2->var_address != 0)
7778 return rtx_equal_p (io1->var_address, io2->var_address);
7783 /* Return true if operations IO1 and IO2 are guaranteed to complete
7787 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7789 /* The order of writes is always preserved. */
7790 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7793 /* The order of reads isn't preserved. */
7794 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7797 /* One operation is a write and the other is (or could be) a read.
7798 The order is only guaranteed if the accesses are to the same
7800 return frv_same_doubleword_p (io1, io2);
7803 /* Generalize I/O operation X so that it covers both X and Y. */
7806 frv_io_union (struct frv_io *x, const struct frv_io *y)
7808 if (x->type != y->type)
7809 x->type = FRV_IO_UNKNOWN;
7810 if (!frv_same_doubleword_p (x, y))
7812 x->const_address = 0;
7817 /* Fill IO with information about the load or store associated with
7818 membar instruction INSN. */
7821 frv_extract_membar (struct frv_io *io, rtx insn)
7823 extract_insn (insn);
7824 io->type = INTVAL (recog_data.operand[2]);
7825 io->const_address = INTVAL (recog_data.operand[1]);
7826 io->var_address = XEXP (recog_data.operand[0], 0);
7829 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7830 if X is a register and *DATA depends on X. */
7833 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7835 rtx *other = (rtx *) data;
7837 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7841 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7842 Remove every modified register from the set. */
7845 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7847 HARD_REG_SET *set = (HARD_REG_SET *) data;
7851 FOR_EACH_REGNO (regno, x)
7852 CLEAR_HARD_REG_BIT (*set, regno);
7855 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7856 Add every register in *X to the set. */
7859 frv_io_handle_use_1 (rtx *x, void *data)
7861 HARD_REG_SET *set = (HARD_REG_SET *) data;
7865 FOR_EACH_REGNO (regno, *x)
7866 SET_HARD_REG_BIT (*set, regno);
7871 /* A note_stores callback that applies frv_io_handle_use_1 to an
7872 entire rhs value. */
7875 frv_io_handle_use (rtx *x, void *data)
7877 for_each_rtx (x, frv_io_handle_use_1, data);
7880 /* Go through block BB looking for membars to remove. There are two
7881 cases where intra-block analysis is enough:
7883 - a membar is redundant if it occurs between two consecutive I/O
7884 operations and if those operations are guaranteed to complete
7887 - a membar for a __builtin_read is redundant if the result is
7888 used before the next I/O operation is issued.
7890 If the last membar in the block could not be removed, and there
7891 are guaranteed to be no I/O operations between that membar and
7892 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7895 Describe the block's first I/O operation in *NEXT_IO. Describe
7896 an unknown operation if the block doesn't do any I/O. */
7899 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7902 HARD_REG_SET used_regs;
7903 rtx next_membar, set, insn;
7906 /* NEXT_IO is the next I/O operation to be performed after the current
7907 instruction. It starts off as being an unknown operation. */
7908 memset (next_io, 0, sizeof (*next_io));
7910 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7911 next_is_end_p = true;
7913 /* If the current instruction is a __builtin_read or __builtin_write,
7914 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7915 is null if the membar has already been deleted.
7917 Note that the initialization here should only be needed to
7918 suppress warnings. */
7921 /* USED_REGS is the set of registers that are used before the
7922 next I/O instruction. */
7923 CLEAR_HARD_REG_SET (used_regs);
7925 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7926 if (GET_CODE (insn) == CALL_INSN)
7928 /* We can't predict what a call will do to volatile memory. */
7929 memset (next_io, 0, sizeof (struct frv_io));
7930 next_is_end_p = false;
7931 CLEAR_HARD_REG_SET (used_regs);
7933 else if (INSN_P (insn))
7934 switch (recog_memoized (insn))
7936 case CODE_FOR_optional_membar_qi:
7937 case CODE_FOR_optional_membar_hi:
7938 case CODE_FOR_optional_membar_si:
7939 case CODE_FOR_optional_membar_di:
7943 /* Local information isn't enough to decide whether this
7944 membar is needed. Stash it away for later. */
7945 *last_membar = insn;
7946 frv_extract_membar (next_io, insn);
7947 next_is_end_p = false;
7951 /* Check whether the I/O operation before INSN could be
7952 reordered with one described by NEXT_IO. If it can't,
7953 INSN will not be needed. */
7954 struct frv_io prev_io;
7956 frv_extract_membar (&prev_io, insn);
7957 if (frv_io_fixed_order_p (&prev_io, next_io))
7961 ";; [Local] Removing membar %d since order"
7962 " of accesses is guaranteed\n",
7963 INSN_UID (next_membar));
7965 insn = NEXT_INSN (insn);
7966 delete_insn (next_membar);
7974 /* Invalidate NEXT_IO's address if it depends on something that
7975 is clobbered by INSN. */
7976 if (next_io->var_address)
7977 note_stores (PATTERN (insn), frv_io_check_address,
7978 &next_io->var_address);
7980 /* If the next membar is associated with a __builtin_read,
7981 see if INSN reads from that address. If it does, and if
7982 the destination register is used before the next I/O access,
7983 there is no need for the membar. */
7984 set = PATTERN (insn);
7985 if (next_io->type == FRV_IO_READ
7986 && next_io->var_address != 0
7988 && GET_CODE (set) == SET
7989 && GET_CODE (SET_DEST (set)) == REG
7990 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
7994 src = SET_SRC (set);
7995 if (GET_CODE (src) == ZERO_EXTEND)
7996 src = XEXP (src, 0);
7998 if (GET_CODE (src) == MEM
7999 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8003 ";; [Local] Removing membar %d since the target"
8004 " of %d is used before the I/O operation\n",
8005 INSN_UID (next_membar), INSN_UID (insn));
8007 if (next_membar == *last_membar)
8010 delete_insn (next_membar);
8015 /* If INSN has volatile references, forget about any registers
8016 that are used after it. Otherwise forget about uses that
8017 are (or might be) defined by INSN. */
8018 if (volatile_refs_p (PATTERN (insn)))
8019 CLEAR_HARD_REG_SET (used_regs);
8021 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8023 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8028 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8029 FIRST_IO[X] describes the first operation performed by basic block X. */
8032 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8035 struct frv_io this_io, next_io;
8039 /* We need to keep the membar if there is an edge to the exit block. */
8040 FOR_EACH_EDGE (succ, ei, bb->succs)
8041 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8042 if (succ->dest == EXIT_BLOCK_PTR)
8045 /* Work out the union of all successor blocks. */
8046 ei = ei_start (bb->succs);
8047 ei_cond (ei, &succ);
8048 /* next_io = first_io[bb->succ->dest->index]; */
8049 next_io = first_io[succ->dest->index];
8050 ei = ei_start (bb->succs);
8051 if (ei_cond (ei, &succ))
8053 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8054 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8055 frv_io_union (&next_io, &first_io[succ->dest->index]);
8060 frv_extract_membar (&this_io, membar);
8061 if (frv_io_fixed_order_p (&this_io, &next_io))
8065 ";; [Global] Removing membar %d since order of accesses"
8066 " is guaranteed\n", INSN_UID (membar));
8068 delete_insn (membar);
8072 /* Remove redundant membars from the current function. */
8075 frv_optimize_membar (void)
8078 struct frv_io *first_io;
8081 compute_bb_for_insn ();
8082 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8083 last_membar = XCNEWVEC (rtx, last_basic_block);
8086 frv_optimize_membar_local (bb, &first_io[bb->index],
8087 &last_membar[bb->index]);
8090 if (last_membar[bb->index] != 0)
8091 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8097 /* Used by frv_reorg to keep track of the current packet's address. */
8098 static unsigned int frv_packet_address;
8100 /* If the current packet falls through to a label, try to pad the packet
8101 with nops in order to fit the label's alignment requirements. */
8104 frv_align_label (void)
8106 unsigned int alignment, target, nop;
8107 rtx x, last, barrier, label;
8109 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8110 maximum alignment of that packet, LABEL to the last label between
8111 the packets, and BARRIER to the last barrier. */
8112 last = frv_packet.insns[frv_packet.num_insns - 1];
8113 label = barrier = 0;
8115 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8119 unsigned int subalign = 1 << label_to_alignment (x);
8120 alignment = MAX (alignment, subalign);
8127 /* If -malign-labels, and the packet falls through to an unaligned
8128 label, try introducing a nop to align that label to 8 bytes. */
8129 if (TARGET_ALIGN_LABELS
8132 && frv_packet.num_insns < frv_packet.issue_rate)
8133 alignment = MAX (alignment, 8);
8135 /* Advance the address to the end of the current packet. */
8136 frv_packet_address += frv_packet.num_insns * 4;
8138 /* Work out the target address, after alignment. */
8139 target = (frv_packet_address + alignment - 1) & -alignment;
8141 /* If the packet falls through to the label, try to find an efficient
8142 padding sequence. */
8145 /* First try adding nops to the current packet. */
8146 for (nop = 0; nop < frv_num_nops; nop++)
8147 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8149 frv_insert_nop_in_packet (frv_nops[nop]);
8150 frv_packet_address += 4;
8153 /* If we still haven't reached the target, add some new packets that
8154 contain only nops. If there are two types of nop, insert an
8155 alternating sequence of frv_nops[0] and frv_nops[1], which will
8156 lead to packets like:
8163 etc. Just emit frv_nops[0] if that's the only nop we have. */
8164 last = frv_packet.insns[frv_packet.num_insns - 1];
8166 while (frv_packet_address < target)
8168 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8169 frv_packet_address += 4;
8170 if (frv_num_nops > 1)
8175 frv_packet_address = target;
8178 /* Subroutine of frv_reorg, called after each packet has been constructed
8182 frv_reorg_packet (void)
8184 frv_fill_unused_units (GROUP_I);
8185 frv_fill_unused_units (GROUP_FM);
8189 /* Add an instruction with pattern NOP to frv_nops[]. */
8192 frv_register_nop (rtx nop)
8194 nop = make_insn_raw (nop);
8195 NEXT_INSN (nop) = 0;
8196 PREV_INSN (nop) = 0;
8197 frv_nops[frv_num_nops++] = nop;
8200 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8201 into packets and check whether we need to insert nops in order to
8202 fulfill the processor's issue requirements. Also, if the user has
8203 requested a certain alignment for a label, try to meet that alignment
8204 by inserting nops in the previous packet. */
8209 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8210 frv_optimize_membar ();
8213 frv_register_nop (gen_nop ());
8215 frv_register_nop (gen_mnop ());
8216 if (TARGET_HARD_FLOAT)
8217 frv_register_nop (gen_fnop ());
8219 /* Estimate the length of each branch. Although this may change after
8220 we've inserted nops, it will only do so in big functions. */
8221 shorten_branches (get_insns ());
8223 frv_packet_address = 0;
8224 frv_for_each_packet (frv_reorg_packet);
8227 #define def_builtin(name, type, code) \
8228 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8230 struct builtin_description
8232 enum insn_code icode;
8234 enum frv_builtins code;
8235 enum rtx_code comparison;
8239 /* Media intrinsics that take a single, constant argument. */
8241 static struct builtin_description bdesc_set[] =
8243 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8246 /* Media intrinsics that take just one argument. */
8248 static struct builtin_description bdesc_1arg[] =
8250 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8251 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8252 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8253 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8254 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8255 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8258 /* Media intrinsics that take two arguments. */
8260 static struct builtin_description bdesc_2arg[] =
8262 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8263 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8264 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8265 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8266 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8267 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8268 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8269 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8270 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8271 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8272 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8273 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8274 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8275 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8276 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8277 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8278 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8279 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8280 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8281 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8282 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8283 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8284 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8285 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8286 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8287 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8288 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8291 /* Integer intrinsics that take two arguments and have no return value. */
8293 static struct builtin_description bdesc_int_void2arg[] =
8295 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8296 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8297 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8300 static struct builtin_description bdesc_prefetches[] =
8302 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8303 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8306 /* Media intrinsics that take two arguments, the first being an ACC number. */
8308 static struct builtin_description bdesc_cut[] =
8310 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8311 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8312 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8315 /* Two-argument media intrinsics with an immediate second argument. */
8317 static struct builtin_description bdesc_2argimm[] =
8319 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8320 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8321 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8322 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8323 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8324 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8325 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8326 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8327 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8328 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8329 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8330 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8331 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8332 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8333 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8334 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8335 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8338 /* Media intrinsics that take two arguments and return void, the first argument
8339 being a pointer to 4 words in memory. */
8341 static struct builtin_description bdesc_void2arg[] =
8343 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8344 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8347 /* Media intrinsics that take three arguments, the first being a const_int that
8348 denotes an accumulator, and that return void. */
8350 static struct builtin_description bdesc_void3arg[] =
8352 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8353 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8354 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8355 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8356 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8357 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8358 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8359 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8360 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8361 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8362 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8363 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8364 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8365 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8366 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8367 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8368 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8369 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8370 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8371 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8372 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8373 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8374 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8375 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8376 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8379 /* Media intrinsics that take two accumulator numbers as argument and
8382 static struct builtin_description bdesc_voidacc[] =
8384 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8385 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8386 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8387 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8388 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8389 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8392 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8393 a normal move and the ICODE is for the membar. */
8395 static struct builtin_description bdesc_loads[] =
8397 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8398 FRV_BUILTIN_READ8, 0, 0 },
8399 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8400 FRV_BUILTIN_READ16, 0, 0 },
8401 { CODE_FOR_optional_membar_si, "__builtin_read32",
8402 FRV_BUILTIN_READ32, 0, 0 },
8403 { CODE_FOR_optional_membar_di, "__builtin_read64",
8404 FRV_BUILTIN_READ64, 0, 0 }
8407 /* Likewise stores. */
8409 static struct builtin_description bdesc_stores[] =
8411 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8412 FRV_BUILTIN_WRITE8, 0, 0 },
8413 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8414 FRV_BUILTIN_WRITE16, 0, 0 },
8415 { CODE_FOR_optional_membar_si, "__builtin_write32",
8416 FRV_BUILTIN_WRITE32, 0, 0 },
8417 { CODE_FOR_optional_membar_di, "__builtin_write64",
8418 FRV_BUILTIN_WRITE64, 0, 0 },
8421 /* Initialize media builtins. */
8424 frv_init_builtins (void)
8426 tree endlink = void_list_node;
8427 tree accumulator = integer_type_node;
8428 tree integer = integer_type_node;
8429 tree voidt = void_type_node;
8430 tree uhalf = short_unsigned_type_node;
8431 tree sword1 = long_integer_type_node;
8432 tree uword1 = long_unsigned_type_node;
8433 tree sword2 = long_long_integer_type_node;
8434 tree uword2 = long_long_unsigned_type_node;
8435 tree uword4 = build_pointer_type (uword1);
8436 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8437 tree ubyte = unsigned_char_type_node;
8438 tree iacc = integer_type_node;
8440 #define UNARY(RET, T1) \
8441 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8443 #define BINARY(RET, T1, T2) \
8444 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8445 tree_cons (NULL_TREE, T2, endlink)))
8447 #define TRINARY(RET, T1, T2, T3) \
8448 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8449 tree_cons (NULL_TREE, T2, \
8450 tree_cons (NULL_TREE, T3, endlink))))
8452 #define QUAD(RET, T1, T2, T3, T4) \
8453 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8454 tree_cons (NULL_TREE, T2, \
8455 tree_cons (NULL_TREE, T3, \
8456 tree_cons (NULL_TREE, T4, endlink)))))
8458 tree void_ftype_void = build_function_type (voidt, endlink);
8460 tree void_ftype_acc = UNARY (voidt, accumulator);
8461 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8462 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8463 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8464 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8465 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8466 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8467 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8468 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8470 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8471 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8472 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8473 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8474 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8475 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8476 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8477 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8478 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8479 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8480 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8482 tree sw1_ftype_int = UNARY (sword1, integer);
8483 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8484 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8486 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8487 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8488 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8489 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8490 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8491 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8493 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8494 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8495 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8496 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8497 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8498 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8499 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8500 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8501 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8502 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8503 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8504 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8505 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8506 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8507 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8508 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8509 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8511 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8512 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8513 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8514 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8515 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8516 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8517 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8518 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8519 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8520 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8521 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8522 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8523 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8524 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8525 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8526 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8527 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8528 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8529 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8530 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8531 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8532 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8533 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8534 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8535 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8536 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8537 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8538 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8539 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8540 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8541 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8542 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8543 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8544 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8545 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8546 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8547 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8548 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8549 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8550 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8551 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8552 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8553 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8554 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8555 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8556 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8557 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8558 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8559 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8560 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8561 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8562 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8563 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8564 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8565 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8566 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8567 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8568 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8569 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8570 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8571 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8572 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8573 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8574 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8575 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8576 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8577 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8578 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8579 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8580 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8581 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8582 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8583 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8584 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8585 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8586 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8587 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8588 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8589 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8590 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8591 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8592 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8593 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8594 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8595 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8596 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8597 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8598 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8599 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8600 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8601 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8602 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8603 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8604 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8605 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8606 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8607 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8608 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8609 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8610 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8611 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8612 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8613 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8614 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8615 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8616 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8617 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8618 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8620 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8621 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8622 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8623 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8631 /* Set the names for various arithmetic operations according to the
8634 frv_init_libfuncs (void)
8636 set_optab_libfunc (smod_optab, SImode, "__modi");
8637 set_optab_libfunc (umod_optab, SImode, "__umodi");
8639 set_optab_libfunc (add_optab, DImode, "__addll");
8640 set_optab_libfunc (sub_optab, DImode, "__subll");
8641 set_optab_libfunc (smul_optab, DImode, "__mulll");
8642 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8643 set_optab_libfunc (smod_optab, DImode, "__modll");
8644 set_optab_libfunc (umod_optab, DImode, "__umodll");
8645 set_optab_libfunc (and_optab, DImode, "__andll");
8646 set_optab_libfunc (ior_optab, DImode, "__orll");
8647 set_optab_libfunc (xor_optab, DImode, "__xorll");
8648 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8650 set_optab_libfunc (add_optab, SFmode, "__addf");
8651 set_optab_libfunc (sub_optab, SFmode, "__subf");
8652 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8653 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8655 set_optab_libfunc (add_optab, DFmode, "__addd");
8656 set_optab_libfunc (sub_optab, DFmode, "__subd");
8657 set_optab_libfunc (smul_optab, DFmode, "__muld");
8658 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8660 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8661 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8663 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8664 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8665 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8666 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8668 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8669 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8670 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8671 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8673 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8674 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8675 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8676 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8679 /* Convert an integer constant to an accumulator register. ICODE is the
8680 code of the target instruction, OPNUM is the number of the
8681 accumulator operand and OPVAL is the constant integer. Try both
8682 ACC and ACCG registers; only report an error if neither fit the
8686 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8691 /* ACCs and ACCGs are implicit global registers if media intrinsics
8692 are being used. We set up this lazily to avoid creating lots of
8693 unnecessary call_insn rtl in non-media code. */
8694 for (i = 0; i <= ACC_MASK; i++)
8695 if ((i & ACC_MASK) == i)
8696 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8698 if (GET_CODE (opval) != CONST_INT)
8700 error ("accumulator is not a constant integer");
8703 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8705 error ("accumulator number is out of bounds");
8709 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8710 ACC_FIRST + INTVAL (opval));
8711 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8712 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8714 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8716 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8722 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8725 static enum machine_mode
8726 frv_matching_accg_mode (enum machine_mode mode)
8744 /* Given that a __builtin_read or __builtin_write function is accessing
8745 address ADDRESS, return the value that should be used as operand 1
8749 frv_io_address_cookie (rtx address)
8751 return (GET_CODE (address) == CONST_INT
8752 ? GEN_INT (INTVAL (address) / 8 * 8)
8756 /* Return the accumulator guard that should be paired with accumulator
8757 register ACC. The mode of the returned register is in the same
8758 class as ACC, but is four times smaller. */
8761 frv_matching_accg_for_acc (rtx acc)
8763 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8764 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8767 /* Read the requested argument from the call EXP given by INDEX.
8768 Return the value as an rtx. */
8771 frv_read_argument (tree exp, unsigned int index)
8773 return expand_expr (CALL_EXPR_ARG (exp, index),
8774 NULL_RTX, VOIDmode, 0);
8777 /* Like frv_read_argument, but interpret the argument as the number
8778 of an IACC register and return a (reg:MODE ...) rtx for it. */
8781 frv_read_iacc_argument (enum machine_mode mode, tree call,
8787 op = frv_read_argument (call, index);
8788 if (GET_CODE (op) != CONST_INT
8790 || INTVAL (op) > IACC_LAST - IACC_FIRST
8791 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8793 error ("invalid IACC argument");
8797 /* IACCs are implicit global registers. We set up this lazily to
8798 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8800 regno = INTVAL (op) + IACC_FIRST;
8801 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8802 global_regs[regno + i] = 1;
8804 return gen_rtx_REG (mode, regno);
8807 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8808 The instruction should require a constant operand of some sort. The
8809 function prints an error if OPVAL is not valid. */
8812 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8814 if (GET_CODE (opval) != CONST_INT)
8816 error ("%qs expects a constant argument", insn_data[icode].name);
8819 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8821 error ("constant argument out of range for %qs", insn_data[icode].name);
8827 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8828 if it's not null, has the right mode, and satisfies operand 0's
8832 frv_legitimize_target (enum insn_code icode, rtx target)
8834 enum machine_mode mode = insn_data[icode].operand[0].mode;
8837 || GET_MODE (target) != mode
8838 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8839 return gen_reg_rtx (mode);
8844 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8845 check whether ARG satisfies the operand's constraints. If it doesn't,
8846 copy ARG to a temporary register and return that. Otherwise return ARG
8850 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8852 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8854 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8857 return copy_to_mode_reg (mode, arg);
8860 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8863 frv_volatile_memref (enum machine_mode mode, rtx arg)
8867 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8868 MEM_VOLATILE_P (mem) = 1;
8872 /* Expand builtins that take a single, constant argument. At the moment,
8873 only MHDSETS falls into this category. */
8876 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8879 rtx op0 = frv_read_argument (call, 0);
8881 if (! frv_check_constant_argument (icode, 1, op0))
8884 target = frv_legitimize_target (icode, target);
8885 pat = GEN_FCN (icode) (target, op0);
8893 /* Expand builtins that take one operand. */
8896 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8899 rtx op0 = frv_read_argument (call, 0);
8901 target = frv_legitimize_target (icode, target);
8902 op0 = frv_legitimize_argument (icode, 1, op0);
8903 pat = GEN_FCN (icode) (target, op0);
8911 /* Expand builtins that take two operands. */
8914 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8917 rtx op0 = frv_read_argument (call, 0);
8918 rtx op1 = frv_read_argument (call, 1);
8920 target = frv_legitimize_target (icode, target);
8921 op0 = frv_legitimize_argument (icode, 1, op0);
8922 op1 = frv_legitimize_argument (icode, 2, op1);
8923 pat = GEN_FCN (icode) (target, op0, op1);
8931 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8935 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8938 rtx op0 = frv_read_argument (call, 0);
8939 rtx op1 = frv_read_argument (call, 1);
8942 target = frv_legitimize_target (icode, target);
8943 op0 = frv_int_to_acc (icode, 1, op0);
8947 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8949 if (! frv_check_constant_argument (icode, 2, op1))
8953 op1 = frv_legitimize_argument (icode, 2, op1);
8955 op2 = frv_matching_accg_for_acc (op0);
8956 pat = GEN_FCN (icode) (target, op0, op1, op2);
8964 /* Expand builtins that take two operands and the second is immediate. */
8967 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
8970 rtx op0 = frv_read_argument (call, 0);
8971 rtx op1 = frv_read_argument (call, 1);
8973 if (! frv_check_constant_argument (icode, 2, op1))
8976 target = frv_legitimize_target (icode, target);
8977 op0 = frv_legitimize_argument (icode, 1, op0);
8978 pat = GEN_FCN (icode) (target, op0, op1);
8986 /* Expand builtins that take two operands, the first operand being a pointer to
8987 ints and return void. */
8990 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
8993 rtx op0 = frv_read_argument (call, 0);
8994 rtx op1 = frv_read_argument (call, 1);
8995 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8998 if (GET_CODE (op0) != MEM)
9002 if (! offsettable_address_p (0, mode0, op0))
9004 reg = gen_reg_rtx (Pmode);
9005 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9008 op0 = gen_rtx_MEM (SImode, reg);
9011 addr = XEXP (op0, 0);
9012 if (! offsettable_address_p (0, mode0, addr))
9013 addr = copy_to_mode_reg (Pmode, op0);
9015 op0 = change_address (op0, V4SImode, addr);
9016 op1 = frv_legitimize_argument (icode, 1, op1);
9017 pat = GEN_FCN (icode) (op0, op1);
9025 /* Expand builtins that take two long operands and return void. */
9028 frv_expand_int_void2arg (enum insn_code icode, tree call)
9031 rtx op0 = frv_read_argument (call, 0);
9032 rtx op1 = frv_read_argument (call, 1);
9034 op0 = frv_legitimize_argument (icode, 1, op0);
9035 op1 = frv_legitimize_argument (icode, 1, op1);
9036 pat = GEN_FCN (icode) (op0, op1);
9044 /* Expand prefetch builtins. These take a single address as argument. */
9047 frv_expand_prefetches (enum insn_code icode, tree call)
9050 rtx op0 = frv_read_argument (call, 0);
9052 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9060 /* Expand builtins that take three operands and return void. The first
9061 argument must be a constant that describes a pair or quad accumulators. A
9062 fourth argument is created that is the accumulator guard register that
9063 corresponds to the accumulator. */
9066 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9069 rtx op0 = frv_read_argument (call, 0);
9070 rtx op1 = frv_read_argument (call, 1);
9071 rtx op2 = frv_read_argument (call, 2);
9074 op0 = frv_int_to_acc (icode, 0, op0);
9078 op1 = frv_legitimize_argument (icode, 1, op1);
9079 op2 = frv_legitimize_argument (icode, 2, op2);
9080 op3 = frv_matching_accg_for_acc (op0);
9081 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9089 /* Expand builtins that perform accumulator-to-accumulator operations.
9090 These builtins take two accumulator numbers as argument and return
9094 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9097 rtx op0 = frv_read_argument (call, 0);
9098 rtx op1 = frv_read_argument (call, 1);
9102 op0 = frv_int_to_acc (icode, 0, op0);
9106 op1 = frv_int_to_acc (icode, 1, op1);
9110 op2 = frv_matching_accg_for_acc (op0);
9111 op3 = frv_matching_accg_for_acc (op1);
9112 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9120 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9121 membar and TARGET_MODE is the mode that the loaded value should have. */
9124 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9125 tree call, rtx target)
9127 rtx op0 = frv_read_argument (call, 0);
9128 rtx cookie = frv_io_address_cookie (op0);
9130 if (target == 0 || !REG_P (target))
9131 target = gen_reg_rtx (target_mode);
9132 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9133 convert_move (target, op0, 1);
9134 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9135 cfun->machine->has_membar_p = 1;
9139 /* Likewise __builtin_write* functions. */
9142 frv_expand_store_builtin (enum insn_code icode, tree call)
9144 rtx op0 = frv_read_argument (call, 0);
9145 rtx op1 = frv_read_argument (call, 1);
9146 rtx cookie = frv_io_address_cookie (op0);
9148 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9149 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9150 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9151 cfun->machine->has_membar_p = 1;
9155 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9156 each argument forms one word of the two double-word input registers.
9157 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9158 to put the return value. */
9161 frv_expand_mdpackh_builtin (tree call, rtx target)
9163 enum insn_code icode = CODE_FOR_mdpackh;
9165 rtx arg1 = frv_read_argument (call, 0);
9166 rtx arg2 = frv_read_argument (call, 1);
9167 rtx arg3 = frv_read_argument (call, 2);
9168 rtx arg4 = frv_read_argument (call, 3);
9170 target = frv_legitimize_target (icode, target);
9171 op0 = gen_reg_rtx (DImode);
9172 op1 = gen_reg_rtx (DImode);
9174 /* The high half of each word is not explicitly initialized, so indicate
9175 that the input operands are not live before this point. */
9179 /* Move each argument into the low half of its associated input word. */
9180 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9181 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9182 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9183 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9185 pat = GEN_FCN (icode) (target, op0, op1);
9193 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9194 number as argument. */
9197 frv_expand_mclracc_builtin (tree call)
9199 enum insn_code icode = CODE_FOR_mclracc;
9201 rtx op0 = frv_read_argument (call, 0);
9203 op0 = frv_int_to_acc (icode, 0, op0);
9207 pat = GEN_FCN (icode) (op0);
9214 /* Expand builtins that take no arguments. */
9217 frv_expand_noargs_builtin (enum insn_code icode)
9219 rtx pat = GEN_FCN (icode) (const0_rtx);
9226 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9227 number or accumulator guard number as argument and return an SI integer. */
9230 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9233 rtx target = gen_reg_rtx (SImode);
9234 rtx op0 = frv_read_argument (call, 0);
9236 op0 = frv_int_to_acc (icode, 1, op0);
9240 pat = GEN_FCN (icode) (target, op0);
9248 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9249 accumulator guard as their first argument and an SImode value as their
9253 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9256 rtx op0 = frv_read_argument (call, 0);
9257 rtx op1 = frv_read_argument (call, 1);
9259 op0 = frv_int_to_acc (icode, 0, op0);
9263 op1 = frv_legitimize_argument (icode, 1, op1);
9264 pat = GEN_FCN (icode) (op0, op1);
9271 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9272 to move DImode values into and out of IACC0. */
9275 frv_split_iacc_move (rtx dest, rtx src)
9277 enum machine_mode inner;
9280 inner = GET_MODE (dest);
9281 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9282 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9283 simplify_gen_subreg (SImode, src, inner, i));
9286 /* Expand builtins. */
9289 frv_expand_builtin (tree exp,
9291 rtx subtarget ATTRIBUTE_UNUSED,
9292 enum machine_mode mode ATTRIBUTE_UNUSED,
9293 int ignore ATTRIBUTE_UNUSED)
9295 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9296 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9298 struct builtin_description *d;
9300 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9302 error ("media functions are not available unless -mmedia is used");
9308 case FRV_BUILTIN_MCOP1:
9309 case FRV_BUILTIN_MCOP2:
9310 case FRV_BUILTIN_MDUNPACKH:
9311 case FRV_BUILTIN_MBTOHE:
9312 if (! TARGET_MEDIA_REV1)
9314 error ("this media function is only available on the fr500");
9319 case FRV_BUILTIN_MQXMACHS:
9320 case FRV_BUILTIN_MQXMACXHS:
9321 case FRV_BUILTIN_MQMACXHS:
9322 case FRV_BUILTIN_MADDACCS:
9323 case FRV_BUILTIN_MSUBACCS:
9324 case FRV_BUILTIN_MASACCS:
9325 case FRV_BUILTIN_MDADDACCS:
9326 case FRV_BUILTIN_MDSUBACCS:
9327 case FRV_BUILTIN_MDASACCS:
9328 case FRV_BUILTIN_MABSHS:
9329 case FRV_BUILTIN_MDROTLI:
9330 case FRV_BUILTIN_MCPLHI:
9331 case FRV_BUILTIN_MCPLI:
9332 case FRV_BUILTIN_MDCUTSSI:
9333 case FRV_BUILTIN_MQSATHS:
9334 case FRV_BUILTIN_MHSETLOS:
9335 case FRV_BUILTIN_MHSETLOH:
9336 case FRV_BUILTIN_MHSETHIS:
9337 case FRV_BUILTIN_MHSETHIH:
9338 case FRV_BUILTIN_MHDSETS:
9339 case FRV_BUILTIN_MHDSETH:
9340 if (! TARGET_MEDIA_REV2)
9342 error ("this media function is only available on the fr400"
9348 case FRV_BUILTIN_SMASS:
9349 case FRV_BUILTIN_SMSSS:
9350 case FRV_BUILTIN_SMU:
9351 case FRV_BUILTIN_ADDSS:
9352 case FRV_BUILTIN_SUBSS:
9353 case FRV_BUILTIN_SLASS:
9354 case FRV_BUILTIN_SCUTSS:
9355 case FRV_BUILTIN_IACCreadll:
9356 case FRV_BUILTIN_IACCreadl:
9357 case FRV_BUILTIN_IACCsetll:
9358 case FRV_BUILTIN_IACCsetl:
9359 if (!TARGET_FR405_BUILTINS)
9361 error ("this builtin function is only available"
9362 " on the fr405 and fr450");
9367 case FRV_BUILTIN_PREFETCH:
9368 if (!TARGET_FR500_FR550_BUILTINS)
9370 error ("this builtin function is only available on the fr500"
9376 case FRV_BUILTIN_MQLCLRHS:
9377 case FRV_BUILTIN_MQLMTHS:
9378 case FRV_BUILTIN_MQSLLHI:
9379 case FRV_BUILTIN_MQSRAHI:
9380 if (!TARGET_MEDIA_FR450)
9382 error ("this builtin function is only available on the fr450");
9391 /* Expand unique builtins. */
9395 case FRV_BUILTIN_MTRAP:
9396 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9398 case FRV_BUILTIN_MCLRACC:
9399 return frv_expand_mclracc_builtin (exp);
9401 case FRV_BUILTIN_MCLRACCA:
9403 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9405 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9407 case FRV_BUILTIN_MRDACC:
9408 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9410 case FRV_BUILTIN_MRDACCG:
9411 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9413 case FRV_BUILTIN_MWTACC:
9414 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9416 case FRV_BUILTIN_MWTACCG:
9417 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9419 case FRV_BUILTIN_MDPACKH:
9420 return frv_expand_mdpackh_builtin (exp, target);
9422 case FRV_BUILTIN_IACCreadll:
9424 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9425 if (target == 0 || !REG_P (target))
9426 target = gen_reg_rtx (DImode);
9427 frv_split_iacc_move (target, src);
9431 case FRV_BUILTIN_IACCreadl:
9432 return frv_read_iacc_argument (SImode, exp, 0);
9434 case FRV_BUILTIN_IACCsetll:
9436 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9437 rtx src = frv_read_argument (exp, 1);
9438 frv_split_iacc_move (dest, force_reg (DImode, src));
9442 case FRV_BUILTIN_IACCsetl:
9444 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9445 rtx src = frv_read_argument (exp, 1);
9446 emit_move_insn (dest, force_reg (SImode, src));
9454 /* Expand groups of builtins. */
9456 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9457 if (d->code == fcode)
9458 return frv_expand_set_builtin (d->icode, exp, target);
9460 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9461 if (d->code == fcode)
9462 return frv_expand_unop_builtin (d->icode, exp, target);
9464 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9465 if (d->code == fcode)
9466 return frv_expand_binop_builtin (d->icode, exp, target);
9468 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9469 if (d->code == fcode)
9470 return frv_expand_cut_builtin (d->icode, exp, target);
9472 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9473 if (d->code == fcode)
9474 return frv_expand_binopimm_builtin (d->icode, exp, target);
9476 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9477 if (d->code == fcode)
9478 return frv_expand_voidbinop_builtin (d->icode, exp);
9480 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9481 if (d->code == fcode)
9482 return frv_expand_voidtriop_builtin (d->icode, exp);
9484 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9485 if (d->code == fcode)
9486 return frv_expand_voidaccop_builtin (d->icode, exp);
9488 for (i = 0, d = bdesc_int_void2arg;
9489 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9490 if (d->code == fcode)
9491 return frv_expand_int_void2arg (d->icode, exp);
9493 for (i = 0, d = bdesc_prefetches;
9494 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9495 if (d->code == fcode)
9496 return frv_expand_prefetches (d->icode, exp);
9498 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9499 if (d->code == fcode)
9500 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9503 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9504 if (d->code == fcode)
9505 return frv_expand_store_builtin (d->icode, exp);
9511 frv_in_small_data_p (const_tree decl)
9514 const_tree section_name;
9516 /* Don't apply the -G flag to internal compiler structures. We
9517 should leave such structures in the main data section, partly
9518 for efficiency and partly because the size of some of them
9519 (such as C++ typeinfos) is not known until later. */
9520 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9523 /* If we already know which section the decl should be in, see if
9524 it's a small data section. */
9525 section_name = DECL_SECTION_NAME (decl);
9528 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9529 if (frv_string_begins_with (section_name, ".sdata"))
9531 if (frv_string_begins_with (section_name, ".sbss"))
9536 size = int_size_in_bytes (TREE_TYPE (decl));
9537 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9544 frv_rtx_costs (rtx x,
9545 int code ATTRIBUTE_UNUSED,
9546 int outer_code ATTRIBUTE_UNUSED,
9548 bool speed ATTRIBUTE_UNUSED)
9550 if (outer_code == MEM)
9552 /* Don't differentiate between memory addresses. All the ones
9553 we accept have equal cost. */
9554 *total = COSTS_N_INSNS (0);
9561 /* Make 12-bit integers really cheap. */
9562 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9573 *total = COSTS_N_INSNS (2);
9587 if (GET_MODE (x) == SImode)
9588 *total = COSTS_N_INSNS (1);
9589 else if (GET_MODE (x) == DImode)
9590 *total = COSTS_N_INSNS (2);
9592 *total = COSTS_N_INSNS (3);
9596 if (GET_MODE (x) == SImode)
9597 *total = COSTS_N_INSNS (2);
9599 *total = COSTS_N_INSNS (6); /* guess */
9606 *total = COSTS_N_INSNS (18);
9610 *total = COSTS_N_INSNS (3);
9619 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9621 switch_to_section (ctors_section);
9622 assemble_align (POINTER_SIZE);
9625 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9630 assemble_integer_with_op ("\t.picptr\t", symbol);
9634 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9636 switch_to_section (dtors_section);
9637 assemble_align (POINTER_SIZE);
9640 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9645 assemble_integer_with_op ("\t.picptr\t", symbol);
9648 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9651 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9652 int incoming ATTRIBUTE_UNUSED)
9654 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9657 #define TLS_BIAS (2048 - 16)
9659 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9660 We need to emit DTP-relative relocations. */
9663 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9665 gcc_assert (size == 4);
9666 fputs ("\t.picptr\ttlsmoff(", file);
9667 /* We want the unbiased TLS offset, so add the bias to the
9668 expression, such that the implicit biasing cancels out. */
9669 output_addr_const (file, plus_constant (x, TLS_BIAS));