1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Return true if instruction INSN should be packed with the following
114 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
116 /* Set the value of PACKING_FLAG_P(INSN). */
117 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
118 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
120 /* Loop with REG set to each hard register in rtx X. */
121 #define FOR_EACH_REGNO(REG, X) \
122 for (REG = REGNO (X); \
123 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
126 /* Information about a relocation unspec. SYMBOL is the relocation symbol
127 (a SYMBOL_REF or LABEL_REF), RELOC is the type of relocation and OFFSET
128 is the constant addend. */
132 HOST_WIDE_INT offset;
135 /* Temporary register allocation support structure. */
136 typedef struct frv_tmp_reg_struct
138 HARD_REG_SET regs; /* possible registers to allocate */
139 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
143 /* Register state information for VLIW re-packing phase. */
144 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
145 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
146 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
147 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
149 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
151 typedef unsigned char regstate_t;
153 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
161 /* Information required by frv_frame_access. */
164 /* This field is FRV_LOAD if registers are to be loaded from the stack and
165 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
166 the move is being done by the prologue code while FRV_LOAD implies it
167 is being done by the epilogue. */
168 enum frv_stack_op op;
170 /* The base register to use when accessing the stack. This may be the
171 frame pointer, stack pointer, or a temporary. The choice of register
172 depends on which part of the frame is being accessed and how big the
176 /* The offset of BASE from the bottom of the current frame, in bytes. */
178 } frv_frame_accessor_t;
180 /* Define the information needed to generate branch and scc insns. This is
181 stored from the compare operation. */
185 /* Conditional execution support gathered together in one structure. */
188 /* Linked list of insns to add if the conditional execution conversion was
189 successful. Each link points to an EXPR_LIST which points to the pattern
190 of the insn to add, and the insn to be inserted before. */
191 rtx added_insns_list;
193 /* Identify which registers are safe to allocate for if conversions to
194 conditional execution. We keep the last allocated register in the
195 register classes between COND_EXEC statements. This will mean we allocate
196 different registers for each different COND_EXEC group if we can. This
197 might allow the scheduler to intermix two different COND_EXEC sections. */
198 frv_tmp_reg_t tmp_reg;
200 /* For nested IFs, identify which CC registers are used outside of setting
201 via a compare isnsn, and using via a check insn. This will allow us to
202 know if we can rewrite the register to use a different register that will
203 be paired with the CR register controlling the nested IF-THEN blocks. */
204 HARD_REG_SET nested_cc_ok_rewrite;
206 /* Temporary registers allocated to hold constants during conditional
208 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
210 /* Current number of temp registers available. */
211 int cur_scratch_regs;
213 /* Number of nested conditional execution blocks. */
214 int num_nested_cond_exec;
216 /* Map of insns that set up constants in scratch registers. */
217 bitmap scratch_insns_bitmap;
219 /* Conditional execution test register (CC0..CC7). */
222 /* Conditional execution compare register that is paired with cr_reg, so that
223 nested compares can be done. The csubcc and caddcc instructions don't
224 have enough bits to specify both a CC register to be set and a CR register
225 to do the test on, so the same bit number is used for both. Needless to
226 say, this is rather inconvenient for GCC. */
229 /* Extra CR registers used for &&, ||. */
233 /* Previous CR used in nested if, to make sure we are dealing with the same
234 nested if as the previous statement. */
235 rtx last_nested_if_cr;
239 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
241 /* Map register number to smallest register class. */
242 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
244 /* Map class letter into register class. */
245 enum reg_class reg_class_from_letter[256];
247 /* Cached value of frv_stack_info. */
248 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
250 /* -mbranch-cost= support */
251 const char *frv_branch_cost_string;
252 int frv_branch_cost_int = DEFAULT_BRANCH_COST;
255 const char *frv_cpu_string; /* -mcpu= option */
256 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
258 /* -mcond-exec-insns= support */
259 const char *frv_condexec_insns_str; /* -mcond-exec-insns= option */
260 int frv_condexec_insns = DEFAULT_CONDEXEC_INSNS; /* value of -mcond-exec-insns*/
262 /* -mcond-exec-temps= support */
263 const char *frv_condexec_temps_str; /* -mcond-exec-temps= option */
264 int frv_condexec_temps = DEFAULT_CONDEXEC_TEMPS; /* value of -mcond-exec-temps*/
266 /* -msched-lookahead=n */
267 const char *frv_sched_lookahead_str; /* -msched-lookahead=n */
268 int frv_sched_lookahead = 4; /* -msched-lookahead=n */
270 /* Forward references */
271 static int frv_default_flags_for_cpu (void);
272 static int frv_string_begins_with (tree, const char *);
273 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
274 static FRV_INLINE bool frv_const_unspec_p (rtx, struct frv_unspec *);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static const char *comparison_string (enum rtx_code, rtx);
280 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
281 static rtx single_set_pattern (rtx);
282 static int frv_function_contains_far_jump (void);
283 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
287 static rtx frv_frame_offset_rtx (int);
288 static rtx frv_frame_mem (enum machine_mode, rtx, int);
289 static rtx frv_dwarf_store (rtx, int);
290 static void frv_frame_insn (rtx, rtx);
291 static void frv_frame_access (frv_frame_accessor_t*,
293 static void frv_frame_access_multi (frv_frame_accessor_t*,
295 static void frv_frame_access_standard_regs (enum frv_stack_op,
297 static struct machine_function *frv_init_machine_status (void);
298 static int frv_legitimate_memory_operand (rtx, enum machine_mode, int);
299 static rtx frv_int_to_acc (enum insn_code, int, rtx);
300 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
301 static rtx frv_read_argument (tree *);
302 static rtx frv_read_iacc_argument (enum machine_mode, tree *);
303 static int frv_check_constant_argument (enum insn_code, int, rtx);
304 static rtx frv_legitimize_target (enum insn_code, rtx);
305 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
306 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
307 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
308 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
309 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
312 static rtx frv_expand_int_void2arg (enum insn_code, tree);
313 static rtx frv_expand_prefetches (enum insn_code, tree);
314 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
315 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
316 static rtx frv_expand_mclracc_builtin (tree);
317 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
318 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
319 static rtx frv_expand_noargs_builtin (enum insn_code);
320 static void frv_split_iacc_move (rtx, rtx);
321 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
322 static int frv_clear_registers_used (rtx *, void *);
323 static void frv_ifcvt_add_insn (rtx, rtx, int);
324 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
325 static rtx frv_ifcvt_load_value (rtx, rtx);
326 static int frv_acc_group_1 (rtx *, void *);
327 static unsigned int frv_insn_unit (rtx);
328 static bool frv_issues_to_branch_unit_p (rtx);
329 static int frv_cond_flags (rtx);
330 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
331 static int frv_registers_conflict_p_1 (rtx *, void *);
332 static bool frv_registers_conflict_p (rtx);
333 static void frv_registers_update_1 (rtx, rtx, void *);
334 static void frv_registers_update (rtx);
335 static void frv_start_packet (void);
336 static void frv_start_packet_block (void);
337 static void frv_finish_packet (void (*) (void));
338 static bool frv_pack_insn_p (rtx);
339 static void frv_add_insn_to_packet (rtx);
340 static void frv_insert_nop_in_packet (rtx);
341 static bool frv_for_each_packet (void (*) (void));
342 static bool frv_sort_insn_group_1 (enum frv_insn_group,
343 unsigned int, unsigned int,
344 unsigned int, unsigned int,
346 static int frv_compare_insns (const void *, const void *);
347 static void frv_sort_insn_group (enum frv_insn_group);
348 static void frv_reorder_packet (void);
349 static void frv_fill_unused_units (enum frv_insn_group);
350 static void frv_align_label (void);
351 static void frv_reorg_packet (void);
352 static void frv_register_nop (rtx);
353 static void frv_reorg (void);
354 static void frv_pack_insns (void);
355 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
356 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
357 static bool frv_assemble_integer (rtx, unsigned, int);
358 static void frv_init_builtins (void);
359 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
360 static void frv_init_libfuncs (void);
361 static bool frv_in_small_data_p (tree);
362 static void frv_asm_output_mi_thunk
363 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
364 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
367 static rtx frv_expand_builtin_saveregs (void);
368 static bool frv_rtx_costs (rtx, int, int, int*);
369 static void frv_asm_out_constructor (rtx, int);
370 static void frv_asm_out_destructor (rtx, int);
371 static bool frv_function_symbol_referenced_p (rtx);
372 static bool frv_cannot_force_const_mem (rtx);
373 static const char *unspec_got_name (int);
374 static void frv_output_const_unspec (FILE *,
375 const struct frv_unspec *);
376 static bool frv_function_ok_for_sibcall (tree, tree);
377 static rtx frv_struct_value_rtx (tree, int);
378 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
380 /* Initialize the GCC target structure. */
381 #undef TARGET_ASM_FUNCTION_PROLOGUE
382 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
383 #undef TARGET_ASM_FUNCTION_EPILOGUE
384 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
385 #undef TARGET_ASM_INTEGER
386 #define TARGET_ASM_INTEGER frv_assemble_integer
387 #undef TARGET_INIT_BUILTINS
388 #define TARGET_INIT_BUILTINS frv_init_builtins
389 #undef TARGET_EXPAND_BUILTIN
390 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
391 #undef TARGET_INIT_LIBFUNCS
392 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
393 #undef TARGET_IN_SMALL_DATA_P
394 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
395 #undef TARGET_RTX_COSTS
396 #define TARGET_RTX_COSTS frv_rtx_costs
397 #undef TARGET_ASM_CONSTRUCTOR
398 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
399 #undef TARGET_ASM_DESTRUCTOR
400 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
402 #undef TARGET_ASM_OUTPUT_MI_THUNK
403 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
404 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
405 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
407 #undef TARGET_SCHED_ISSUE_RATE
408 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
410 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
411 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
412 #undef TARGET_CANNOT_FORCE_CONST_MEM
413 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
415 #undef TARGET_STRUCT_VALUE_RTX
416 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
417 #undef TARGET_MUST_PASS_IN_STACK
418 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
419 #undef TARGET_PASS_BY_REFERENCE
420 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
422 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
423 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
424 #undef TARGET_SETUP_INCOMING_VARARGS
425 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
426 #undef TARGET_MACHINE_DEPENDENT_REORG
427 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
429 struct gcc_target targetm = TARGET_INITIALIZER;
431 /* Any function call that satisfies the machine-independent
432 requirements is eligible on FR-V. */
435 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
436 tree exp ATTRIBUTE_UNUSED)
441 /* Return true if SYMBOL is a small data symbol and relocation RELOC
442 can be used to access it directly in a load or store. */
444 static FRV_INLINE bool
445 frv_small_data_reloc_p (rtx symbol, int reloc)
447 return (GET_CODE (symbol) == SYMBOL_REF
448 && SYMBOL_REF_SMALL_P (symbol)
449 && (!TARGET_FDPIC || flag_pic == 1)
450 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
453 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
456 static FRV_INLINE bool
457 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
459 if (GET_CODE (x) == CONST)
463 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
465 unspec->offset += INTVAL (XEXP (x, 1));
468 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
470 unspec->symbol = XVECEXP (x, 0, 0);
471 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
473 if (unspec->offset == 0)
476 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
477 && unspec->offset > 0
478 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
485 /* Decide whether we can force certain constants to memory. If we
486 decide we can't, the caller should be able to cope with it in
489 We never allow constants to be forced into memory for TARGET_FDPIC.
490 This is necessary for several reasons:
492 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
493 target-independent code will try to force them into the constant
494 pool, thus leading to infinite recursion.
496 2. We can never introduce new constant pool references during reload.
497 Any such reference would require use of the pseudo FDPIC register.
499 3. We can't represent a constant added to a function pointer (which is
500 not the same as a pointer to a function+constant).
502 4. In many cases, it's more efficient to calculate the constant in-line. */
505 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
511 frv_default_flags_for_cpu (void)
513 switch (frv_cpu_type)
515 case FRV_CPU_GENERIC:
516 return MASK_DEFAULT_FRV;
519 return MASK_DEFAULT_FR550;
523 return MASK_DEFAULT_FR500;
526 return MASK_DEFAULT_FR450;
530 return MASK_DEFAULT_FR400;
534 return MASK_DEFAULT_SIMPLE;
539 /* Sometimes certain combinations of command options do not make
540 sense on a particular target machine. You can define a macro
541 `OVERRIDE_OPTIONS' to take account of this. This macro, if
542 defined, is executed once just after all the command options have
545 Don't use this macro to turn on various extra optimizations for
546 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
549 frv_override_options (void)
554 /* Set the cpu type. */
557 if (strcmp (frv_cpu_string, "simple") == 0)
558 frv_cpu_type = FRV_CPU_SIMPLE;
560 else if (strcmp (frv_cpu_string, "tomcat") == 0)
561 frv_cpu_type = FRV_CPU_TOMCAT;
563 else if (strncmp (frv_cpu_string, "fr", sizeof ("fr")-1) != 0)
564 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
568 const char *p = frv_cpu_string + sizeof ("fr") - 1;
569 if (strcmp (p, "550") == 0)
570 frv_cpu_type = FRV_CPU_FR550;
572 else if (strcmp (p, "500") == 0)
573 frv_cpu_type = FRV_CPU_FR500;
575 else if (strcmp (p, "450") == 0)
576 frv_cpu_type = FRV_CPU_FR450;
578 else if (strcmp (p, "405") == 0)
579 frv_cpu_type = FRV_CPU_FR405;
581 else if (strcmp (p, "400") == 0)
582 frv_cpu_type = FRV_CPU_FR400;
584 else if (strcmp (p, "300") == 0)
585 frv_cpu_type = FRV_CPU_FR300;
587 else if (strcmp (p, "v") == 0)
588 frv_cpu_type = FRV_CPU_GENERIC;
591 error ("Unknown cpu: -mcpu=%s", frv_cpu_string);
595 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
597 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
598 linker about linking pic and non-pic code. */
601 if (!flag_pic) /* -fPIC */
604 if (! g_switch_set) /* -G0 */
611 /* Change the branch cost value. */
612 if (frv_branch_cost_string)
613 frv_branch_cost_int = atoi (frv_branch_cost_string);
615 /* Change the # of insns to be converted to conditional execution. */
616 if (frv_condexec_insns_str)
617 frv_condexec_insns = atoi (frv_condexec_insns_str);
619 /* Change # of temporary registers used to hold integer constants. */
620 if (frv_condexec_temps_str)
621 frv_condexec_temps = atoi (frv_condexec_temps_str);
623 /* Change scheduling look ahead. */
624 if (frv_sched_lookahead_str)
625 frv_sched_lookahead = atoi (frv_sched_lookahead_str);
627 /* A C expression whose value is a register class containing hard
628 register REGNO. In general there is more than one such class;
629 choose a class which is "minimal", meaning that no smaller class
630 also contains the register. */
632 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
634 enum reg_class class;
638 int gpr_reg = regno - GPR_FIRST;
639 if ((gpr_reg & 3) == 0)
642 else if ((gpr_reg & 1) == 0)
649 else if (FPR_P (regno))
651 int fpr_reg = regno - GPR_FIRST;
652 if ((fpr_reg & 3) == 0)
653 class = QUAD_FPR_REGS;
655 else if ((fpr_reg & 1) == 0)
662 else if (regno == LR_REGNO)
665 else if (regno == LCR_REGNO)
668 else if (ICC_P (regno))
671 else if (FCC_P (regno))
674 else if (ICR_P (regno))
677 else if (FCR_P (regno))
680 else if (ACC_P (regno))
682 int r = regno - ACC_FIRST;
684 class = QUAD_ACC_REGS;
685 else if ((r & 1) == 0)
686 class = EVEN_ACC_REGS;
691 else if (ACCG_P (regno))
697 regno_reg_class[regno] = class;
700 /* Check for small data option */
702 g_switch_value = SDATA_DEFAULT_SIZE;
704 /* A C expression which defines the machine-dependent operand
705 constraint letters for register classes. If CHAR is such a
706 letter, the value should be the register class corresponding to
707 it. Otherwise, the value should be `NO_REGS'. The register
708 letter `r', corresponding to class `GENERAL_REGS', will not be
709 passed to this macro; you do not need to handle it.
711 The following letters are unavailable, due to being used as
716 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
717 'Q', 'R', 'S', 'T', 'U'
719 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
721 for (i = 0; i < 256; i++)
722 reg_class_from_letter[i] = NO_REGS;
724 reg_class_from_letter['a'] = ACC_REGS;
725 reg_class_from_letter['b'] = EVEN_ACC_REGS;
726 reg_class_from_letter['c'] = CC_REGS;
727 reg_class_from_letter['d'] = GPR_REGS;
728 reg_class_from_letter['e'] = EVEN_REGS;
729 reg_class_from_letter['f'] = FPR_REGS;
730 reg_class_from_letter['h'] = FEVEN_REGS;
731 reg_class_from_letter['l'] = LR_REG;
732 reg_class_from_letter['q'] = QUAD_REGS;
733 reg_class_from_letter['t'] = ICC_REGS;
734 reg_class_from_letter['u'] = FCC_REGS;
735 reg_class_from_letter['v'] = ICR_REGS;
736 reg_class_from_letter['w'] = FCR_REGS;
737 reg_class_from_letter['x'] = QUAD_FPR_REGS;
738 reg_class_from_letter['y'] = LCR_REG;
739 reg_class_from_letter['z'] = SPR_REGS;
740 reg_class_from_letter['A'] = QUAD_ACC_REGS;
741 reg_class_from_letter['B'] = ACCG_REGS;
742 reg_class_from_letter['C'] = CR_REGS;
743 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
744 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
746 /* There is no single unaligned SI op for PIC code. Sometimes we
747 need to use ".4byte" and sometimes we need to use ".picptr".
748 See frv_assemble_integer for details. */
749 if (flag_pic || TARGET_FDPIC)
750 targetm.asm_out.unaligned_op.si = 0;
752 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
753 target_flags |= MASK_LINKED_FP;
755 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
756 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
758 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
759 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
761 init_machine_status = frv_init_machine_status;
765 /* Some machines may desire to change what optimizations are performed for
766 various optimization levels. This macro, if defined, is executed once just
767 after the optimization level is determined and before the remainder of the
768 command options have been parsed. Values set in this macro are used as the
769 default values for the other command line options.
771 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
772 `-O' is specified, and 0 if neither is specified.
774 SIZE is nonzero if `-Os' is specified, 0 otherwise.
776 You should not use this macro to change options that are not
777 machine-specific. These should uniformly selected by the same optimization
778 level on all supported machines. Use this macro to enable machbine-specific
781 *Do not examine `write_symbols' in this macro!* The debugging options are
782 *not supposed to alter the generated code. */
784 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
785 scheduling pass at the current time. */
787 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
791 #ifdef DISABLE_SCHED2
792 flag_schedule_insns_after_reload = 0;
801 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
804 frv_string_begins_with (tree name, const char *prefix)
806 int prefix_len = strlen (prefix);
808 /* Remember: NAME's length includes the null terminator. */
809 return (TREE_STRING_LENGTH (name) > prefix_len
810 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
813 /* Zero or more C statements that may conditionally modify two variables
814 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
815 been initialized from the two preceding macros.
817 This is necessary in case the fixed or call-clobbered registers depend on
820 You need not define this macro if it has no work to do.
822 If the usage of an entire class of registers depends on the target flags,
823 you may indicate this to GCC by using this macro to modify `fixed_regs' and
824 `call_used_regs' to 1 for each of the registers in the classes which should
825 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
826 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
828 (However, if this class is not included in `GENERAL_REGS' and all of the
829 insn patterns whose constraints permit this class are controlled by target
830 switches, then GCC will automatically avoid using these registers when the
831 target switches are opposed to them.) */
834 frv_conditional_register_usage (void)
838 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
839 fixed_regs[i] = call_used_regs[i] = 1;
841 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
842 fixed_regs[i] = call_used_regs[i] = 1;
844 /* Reserve the registers used for conditional execution. At present, we need
845 1 ICC and 1 ICR register. */
846 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
847 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
851 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
852 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
853 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
854 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
858 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
859 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
862 /* If -fpic, SDA_BASE_REG is the PIC register. */
863 if (g_switch_value == 0 && !flag_pic)
864 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
867 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
873 * Compute the stack frame layout
876 * +---------------+-----------------------+-----------------------+
877 * |Register |type |caller-save/callee-save|
878 * +---------------+-----------------------+-----------------------+
879 * |GR0 |Zero register | - |
880 * |GR1 |Stack pointer(SP) | - |
881 * |GR2 |Frame pointer(FP) | - |
882 * |GR3 |Hidden parameter | caller save |
883 * |GR4-GR7 | - | caller save |
884 * |GR8-GR13 |Argument register | caller save |
885 * |GR14-GR15 | - | caller save |
886 * |GR16-GR31 | - | callee save |
887 * |GR32-GR47 | - | caller save |
888 * |GR48-GR63 | - | callee save |
889 * |FR0-FR15 | - | caller save |
890 * |FR16-FR31 | - | callee save |
891 * |FR32-FR47 | - | caller save |
892 * |FR48-FR63 | - | callee save |
893 * +---------------+-----------------------+-----------------------+
897 * SP-> |-----------------------------------|
899 * |-----------------------------------|
900 * | Register save area |
901 * |-----------------------------------|
902 * | Local variable save area |
903 * FP-> |-----------------------------------|
905 * |-----------------------------------|
906 * | Hidden parameter save area |
907 * |-----------------------------------|
908 * | Return address(LR) storage area |
909 * |-----------------------------------|
910 * | Padding for alignment |
911 * |-----------------------------------|
912 * | Register argument area |
913 * OLD SP-> |-----------------------------------|
915 * |-----------------------------------|
918 * Argument area/Parameter area:
920 * When a function is called, this area is used for argument transfer. When
921 * the argument is set up by the caller function, this area is referred to as
922 * the argument area. When the argument is referenced by the callee function,
923 * this area is referred to as the parameter area. The area is allocated when
924 * all arguments cannot be placed on the argument register at the time of
927 * Register save area:
929 * This is a register save area that must be guaranteed for the caller
930 * function. This area is not secured when the register save operation is not
933 * Local variable save area:
935 * This is the area for local variables and temporary variables.
939 * This area stores the FP value of the caller function.
941 * Hidden parameter save area:
943 * This area stores the start address of the return value storage
944 * area for a struct/union return function.
945 * When a struct/union is used as the return value, the caller
946 * function stores the return value storage area start address in
947 * register GR3 and passes it to the caller function.
948 * The callee function interprets the address stored in the GR3
949 * as the return value storage area start address.
950 * When register GR3 needs to be saved into memory, the callee
951 * function saves it in the hidden parameter save area. This
952 * area is not secured when the save operation is not needed.
954 * Return address(LR) storage area:
956 * This area saves the LR. The LR stores the address of a return to the caller
957 * function for the purpose of function calling.
959 * Argument register area:
961 * This area saves the argument register. This area is not secured when the
962 * save operation is not needed.
966 * Arguments, the count of which equals the count of argument registers (6
967 * words), are positioned in registers GR8 to GR13 and delivered to the callee
968 * function. When a struct/union return function is called, the return value
969 * area address is stored in register GR3. Arguments not placed in the
970 * argument registers will be stored in the stack argument area for transfer
971 * purposes. When an 8-byte type argument is to be delivered using registers,
972 * it is divided into two and placed in two registers for transfer. When
973 * argument registers must be saved to memory, the callee function secures an
974 * argument register save area in the stack. In this case, a continuous
975 * argument register save area must be established in the parameter area. The
976 * argument register save area must be allocated as needed to cover the size of
977 * the argument register to be saved. If the function has a variable count of
978 * arguments, it saves all argument registers in the argument register save
981 * Argument Extension Format:
983 * When an argument is to be stored in the stack, its type is converted to an
984 * extended type in accordance with the individual argument type. The argument
985 * is freed by the caller function after the return from the callee function is
988 * +-----------------------+---------------+------------------------+
989 * | Argument Type |Extended Type |Stack Storage Size(byte)|
990 * +-----------------------+---------------+------------------------+
992 * |signed char |int | 4 |
993 * |unsigned char |int | 4 |
994 * |[signed] short int |int | 4 |
995 * |unsigned short int |int | 4 |
996 * |[signed] int |No extension | 4 |
997 * |unsigned int |No extension | 4 |
998 * |[signed] long int |No extension | 4 |
999 * |unsigned long int |No extension | 4 |
1000 * |[signed] long long int |No extension | 8 |
1001 * |unsigned long long int |No extension | 8 |
1002 * |float |double | 8 |
1003 * |double |No extension | 8 |
1004 * |long double |No extension | 8 |
1005 * |pointer |No extension | 4 |
1006 * |struct/union |- | 4 (*1) |
1007 * +-----------------------+---------------+------------------------+
1009 * When a struct/union is to be delivered as an argument, the caller copies it
1010 * to the local variable area and delivers the address of that area.
1014 * +-------------------------------+----------------------+
1015 * |Return Value Type |Return Value Interface|
1016 * +-------------------------------+----------------------+
1018 * |[signed|unsigned] char |GR8 |
1019 * |[signed|unsigned] short int |GR8 |
1020 * |[signed|unsigned] int |GR8 |
1021 * |[signed|unsigned] long int |GR8 |
1023 * |[signed|unsigned] long long int|GR8 & GR9 |
1025 * |double |GR8 & GR9 |
1026 * |long double |GR8 & GR9 |
1027 * |struct/union |(*1) |
1028 * +-------------------------------+----------------------+
1030 * When a struct/union is used as the return value, the caller function stores
1031 * the start address of the return value storage area into GR3 and then passes
1032 * it to the callee function. The callee function interprets GR3 as the start
1033 * address of the return value storage area. When this address needs to be
1034 * saved in memory, the callee function secures the hidden parameter save area
1035 * and saves the address in that area.
1039 frv_stack_info (void)
1041 static frv_stack_t info, zero_info;
1042 frv_stack_t *info_ptr = &info;
1043 tree fndecl = current_function_decl;
1051 /* If we've already calculated the values and reload is complete,
1053 if (frv_stack_cache)
1054 return frv_stack_cache;
1056 /* Zero all fields. */
1059 /* Set up the register range information. */
1060 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1061 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1062 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1063 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1065 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1066 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1067 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1068 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1070 info_ptr->regs[STACK_REGS_LR].name = "lr";
1071 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1072 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1073 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1075 info_ptr->regs[STACK_REGS_CC].name = "cc";
1076 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1077 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1078 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1080 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1081 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1082 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1084 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1085 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1086 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1087 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1088 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1090 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1091 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1092 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1093 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1095 info_ptr->regs[STACK_REGS_FP].name = "fp";
1096 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1097 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1098 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1100 /* Determine if this is a stdarg function. If so, allocate space to store
1107 /* Find the last argument, and see if it is __builtin_va_alist. */
1108 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1110 next_arg = TREE_CHAIN (cur_arg);
1111 if (next_arg == (tree)0)
1113 if (DECL_NAME (cur_arg)
1114 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1122 /* Iterate over all of the register ranges. */
1123 for (range = 0; range < STACK_REGS_MAX; range++)
1125 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1126 int first = reg_ptr->first;
1127 int last = reg_ptr->last;
1129 int size_2words = 0;
1132 /* Calculate which registers need to be saved & save area size. */
1136 for (regno = first; regno <= last; regno++)
1138 if ((regs_ever_live[regno] && !call_used_regs[regno])
1139 || (current_function_calls_eh_return
1140 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1141 || (!TARGET_FDPIC && flag_pic
1142 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1144 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1145 size_1word += UNITS_PER_WORD;
1150 /* Calculate whether we need to create a frame after everything else
1151 has been processed. */
1156 if (regs_ever_live[LR_REGNO]
1158 /* This is set for __builtin_return_address, etc. */
1159 || cfun->machine->frame_needed
1160 || (TARGET_LINKED_FP && frame_pointer_needed)
1161 || (!TARGET_FDPIC && flag_pic
1162 && cfun->uses_pic_offset_table))
1164 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1165 size_1word += UNITS_PER_WORD;
1169 case STACK_REGS_STDARG:
1172 /* If this is a stdarg function with a non varardic
1173 argument split between registers and the stack,
1174 adjust the saved registers downward. */
1175 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1178 for (regno = first; regno <= last; regno++)
1180 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1181 size_1word += UNITS_PER_WORD;
1184 info_ptr->stdarg_size = size_1word;
1188 case STACK_REGS_STRUCT:
1189 if (cfun->returns_struct)
1191 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1192 size_1word += UNITS_PER_WORD;
1200 /* If this is a field, it only takes one word. */
1201 if (reg_ptr->field_p)
1202 size_1word = UNITS_PER_WORD;
1204 /* Determine which register pairs can be saved together. */
1205 else if (reg_ptr->dword_p && TARGET_DWORD)
1207 for (regno = first; regno < last; regno += 2)
1209 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1211 size_2words += 2 * UNITS_PER_WORD;
1212 size_1word -= 2 * UNITS_PER_WORD;
1213 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1214 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1219 reg_ptr->size_1word = size_1word;
1220 reg_ptr->size_2words = size_2words;
1222 if (! reg_ptr->special_p)
1224 info_ptr->regs_size_1word += size_1word;
1225 info_ptr->regs_size_2words += size_2words;
1230 /* Set up the sizes of each each field in the frame body, making the sizes
1231 of each be divisible by the size of a dword if dword operations might
1232 be used, or the size of a word otherwise. */
1233 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1235 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1236 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1237 + info_ptr->regs_size_1word,
1239 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1241 info_ptr->pretend_size = cfun->pretend_args_size;
1243 /* Work out the size of the frame, excluding the header. Both the frame
1244 body and register parameter area will be dword-aligned. */
1245 info_ptr->total_size
1246 = (ADDR_ALIGN (info_ptr->parameter_size
1247 + info_ptr->regs_size
1248 + info_ptr->vars_size,
1250 + ADDR_ALIGN (info_ptr->pretend_size
1251 + info_ptr->stdarg_size,
1252 2 * UNITS_PER_WORD));
1254 /* See if we need to create a frame at all, if so add header area. */
1255 if (info_ptr->total_size > 0
1256 || frame_pointer_needed
1257 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1258 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1260 offset = info_ptr->parameter_size;
1261 info_ptr->header_size = 4 * UNITS_PER_WORD;
1262 info_ptr->total_size += 4 * UNITS_PER_WORD;
1264 /* Calculate the offsets to save normal register pairs. */
1265 for (range = 0; range < STACK_REGS_MAX; range++)
1267 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1268 if (! reg_ptr->special_p)
1270 int first = reg_ptr->first;
1271 int last = reg_ptr->last;
1274 for (regno = first; regno <= last; regno++)
1275 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1276 && regno != FRAME_POINTER_REGNUM
1277 && (regno < FIRST_ARG_REGNUM
1278 || regno > LAST_ARG_REGNUM))
1280 info_ptr->reg_offset[regno] = offset;
1281 offset += 2 * UNITS_PER_WORD;
1286 /* Calculate the offsets to save normal single registers. */
1287 for (range = 0; range < STACK_REGS_MAX; range++)
1289 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1290 if (! reg_ptr->special_p)
1292 int first = reg_ptr->first;
1293 int last = reg_ptr->last;
1296 for (regno = first; regno <= last; regno++)
1297 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1298 && regno != FRAME_POINTER_REGNUM
1299 && (regno < FIRST_ARG_REGNUM
1300 || regno > LAST_ARG_REGNUM))
1302 info_ptr->reg_offset[regno] = offset;
1303 offset += UNITS_PER_WORD;
1308 /* Calculate the offset to save the local variables at. */
1309 offset = ADDR_ALIGN (offset, alignment);
1310 if (info_ptr->vars_size)
1312 info_ptr->vars_offset = offset;
1313 offset += info_ptr->vars_size;
1316 /* Align header to a dword-boundary. */
1317 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1319 /* Calculate the offsets in the fixed frame. */
1320 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1321 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1322 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1324 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1325 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1326 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1328 if (cfun->returns_struct)
1330 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1331 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1332 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1335 /* Calculate the offsets to store the arguments passed in registers
1336 for stdarg functions. The register pairs are first and the single
1337 register if any is last. The register save area starts on a
1339 if (info_ptr->stdarg_size)
1341 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1342 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1345 /* Skip the header. */
1346 offset += 4 * UNITS_PER_WORD;
1347 for (regno = first; regno <= last; regno++)
1349 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1351 info_ptr->reg_offset[regno] = offset;
1352 offset += 2 * UNITS_PER_WORD;
1354 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1356 info_ptr->reg_offset[regno] = offset;
1357 offset += UNITS_PER_WORD;
1363 if (reload_completed)
1364 frv_stack_cache = info_ptr;
1370 /* Print the information about the frv stack offsets, etc. when debugging. */
1373 frv_debug_stack (frv_stack_t *info)
1378 info = frv_stack_info ();
1380 fprintf (stderr, "\nStack information for function %s:\n",
1381 ((current_function_decl && DECL_NAME (current_function_decl))
1382 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1385 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1386 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1387 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1388 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1389 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1391 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1392 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1393 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1394 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1396 for (range = 0; range < STACK_REGS_MAX; range++)
1398 frv_stack_regs_t *regs = &(info->regs[range]);
1399 if ((regs->size_1word + regs->size_2words) > 0)
1401 int first = regs->first;
1402 int last = regs->last;
1405 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1406 regs->name, regs->size_1word + regs->size_2words,
1407 regs->size_1word, regs->size_2words);
1409 for (regno = first; regno <= last; regno++)
1411 if (info->save_p[regno] == REG_SAVE_1WORD)
1412 fprintf (stderr, " %s (%d)", reg_names[regno],
1413 info->reg_offset[regno]);
1415 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1416 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1417 reg_names[regno+1], info->reg_offset[regno]);
1420 fputc ('\n', stderr);
1430 /* Used during final to control the packing of insns. The value is
1431 1 if the current instruction should be packed with the next one,
1432 0 if it shouldn't or -1 if packing is disabled altogether. */
1434 static int frv_insn_packing_flag;
1436 /* True if the current function contains a far jump. */
1439 frv_function_contains_far_jump (void)
1441 rtx insn = get_insns ();
1443 && !(GET_CODE (insn) == JUMP_INSN
1444 /* Ignore tablejump patterns. */
1445 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1446 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1447 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1448 insn = NEXT_INSN (insn);
1449 return (insn != NULL);
1452 /* For the FRV, this function makes sure that a function with far jumps
1453 will return correctly. It also does the VLIW packing. */
1456 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1458 /* If no frame was created, check whether the function uses a call
1459 instruction to implement a far jump. If so, save the link in gr3 and
1460 replace all returns to LR with returns to GR3. GR3 is used because it
1461 is call-clobbered, because is not available to the register allocator,
1462 and because all functions that take a hidden argument pointer will have
1464 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1468 /* Just to check that the above comment is true. */
1469 if (regs_ever_live[GPR_FIRST + 3])
1472 /* Generate the instruction that saves the link register. */
1473 fprintf (file, "\tmovsg lr,gr3\n");
1475 /* Replace the LR with GR3 in *return_internal patterns. The insn
1476 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1477 simply emit a different assembly directive because bralr and jmpl
1478 execute in different units. */
1479 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1480 if (GET_CODE (insn) == JUMP_INSN)
1482 rtx pattern = PATTERN (insn);
1483 if (GET_CODE (pattern) == PARALLEL
1484 && XVECLEN (pattern, 0) >= 2
1485 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1486 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1488 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1489 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1490 REGNO (address) = GPR_FIRST + 3;
1497 /* Allow the garbage collector to free the nops created by frv_reorg. */
1498 memset (frv_nops, 0, sizeof (frv_nops));
1502 /* Return the next available temporary register in a given class. */
1505 frv_alloc_temp_reg (
1506 frv_tmp_reg_t *info, /* which registers are available */
1507 enum reg_class class, /* register class desired */
1508 enum machine_mode mode, /* mode to allocate register with */
1509 int mark_as_used, /* register not available after allocation */
1510 int no_abort) /* return NULL instead of aborting */
1512 int regno = info->next_reg[ (int)class ];
1513 int orig_regno = regno;
1514 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1519 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1520 && TEST_HARD_REG_BIT (info->regs, regno))
1523 if (++regno >= FIRST_PSEUDO_REGISTER)
1525 if (regno == orig_regno)
1534 nr = HARD_REGNO_NREGS (regno, mode);
1535 info->next_reg[ (int)class ] = regno + nr;
1538 for (i = 0; i < nr; i++)
1539 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1541 return gen_rtx_REG (mode, regno);
1545 /* Return an rtx with the value OFFSET, which will either be a register or a
1546 signed 12-bit integer. It can be used as the second operand in an "add"
1547 instruction, or as the index in a load or store.
1549 The function returns a constant rtx if OFFSET is small enough, otherwise
1550 it loads the constant into register OFFSET_REGNO and returns that. */
1552 frv_frame_offset_rtx (int offset)
1554 rtx offset_rtx = GEN_INT (offset);
1555 if (IN_RANGE_P (offset, -2048, 2047))
1559 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1560 if (IN_RANGE_P (offset, -32768, 32767))
1561 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1564 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1565 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1571 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1572 prologue and epilogue uses such expressions to access the stack. */
1574 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1576 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1578 frv_frame_offset_rtx (offset)));
1581 /* Generate a frame-related expression:
1583 (set REG (mem (plus (sp) (const_int OFFSET)))).
1585 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1586 instructions. Marking the expressions as frame-related is superfluous if
1587 the note contains just a single set. But if the note contains a PARALLEL
1588 or SEQUENCE that has several sets, each set must be individually marked
1589 as frame-related. */
1591 frv_dwarf_store (rtx reg, int offset)
1593 rtx set = gen_rtx_SET (VOIDmode,
1594 gen_rtx_MEM (GET_MODE (reg),
1595 plus_constant (stack_pointer_rtx,
1598 RTX_FRAME_RELATED_P (set) = 1;
1602 /* Emit a frame-related instruction whose pattern is PATTERN. The
1603 instruction is the last in a sequence that cumulatively performs the
1604 operation described by DWARF_PATTERN. The instruction is marked as
1605 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1608 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1610 rtx insn = emit_insn (pattern);
1611 RTX_FRAME_RELATED_P (insn) = 1;
1612 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1617 /* Emit instructions that transfer REG to or from the memory location (sp +
1618 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1619 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1620 function to store registers and only the epilogue uses it to load them.
1622 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1623 The generated instruction will use BASE as its base register. BASE may
1624 simply be the stack pointer, but if several accesses are being made to a
1625 region far away from the stack pointer, it may be more efficient to set
1626 up a temporary instead.
1628 Store instructions will be frame-related and will be annotated with the
1629 overall effect of the store. Load instructions will be followed by a
1630 (use) to prevent later optimizations from zapping them.
1632 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1633 as a temporary in such cases. */
1635 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1637 enum machine_mode mode = GET_MODE (reg);
1638 rtx mem = frv_frame_mem (mode,
1640 stack_offset - accessor->base_offset);
1642 if (accessor->op == FRV_LOAD)
1644 if (SPR_P (REGNO (reg)))
1646 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1647 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1648 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1651 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1652 emit_insn (gen_rtx_USE (VOIDmode, reg));
1656 if (SPR_P (REGNO (reg)))
1658 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1659 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1660 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1661 frv_dwarf_store (reg, stack_offset));
1663 else if (GET_MODE (reg) == DImode)
1665 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1666 with a separate save for each register. */
1667 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1668 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1669 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1670 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1671 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1672 gen_rtx_PARALLEL (VOIDmode,
1673 gen_rtvec (2, set1, set2)));
1676 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1677 frv_dwarf_store (reg, stack_offset));
1681 /* A function that uses frv_frame_access to transfer a group of registers to
1682 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1683 is the stack information generated by frv_stack_info, and REG_SET is the
1684 number of the register set to transfer. */
1686 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1690 frv_stack_regs_t *regs_info;
1693 regs_info = &info->regs[reg_set];
1694 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1695 if (info->save_p[regno])
1696 frv_frame_access (accessor,
1697 info->save_p[regno] == REG_SAVE_2WORDS
1698 ? gen_rtx_REG (DImode, regno)
1699 : gen_rtx_REG (SImode, regno),
1700 info->reg_offset[regno]);
1703 /* Save or restore callee-saved registers that are kept outside the frame
1704 header. The function saves the registers if OP is FRV_STORE and restores
1705 them if OP is FRV_LOAD. INFO is the stack information generated by
1708 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1710 frv_frame_accessor_t accessor;
1713 accessor.base = stack_pointer_rtx;
1714 accessor.base_offset = 0;
1715 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1716 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1717 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1721 /* Called after register allocation to add any instructions needed for the
1722 prologue. Using a prologue insn is favored compared to putting all of the
1723 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1724 it allows the scheduler to intermix instructions with the saves of
1725 the caller saved registers. In some cases, it might be necessary
1726 to emit a barrier instruction as the last insn to prevent such
1729 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1730 so that the debug info generation code can handle them properly. */
1732 frv_expand_prologue (void)
1734 frv_stack_t *info = frv_stack_info ();
1735 rtx sp = stack_pointer_rtx;
1736 rtx fp = frame_pointer_rtx;
1737 frv_frame_accessor_t accessor;
1739 if (TARGET_DEBUG_STACK)
1740 frv_debug_stack (info);
1742 if (info->total_size == 0)
1745 /* We're interested in three areas of the frame here:
1747 A: the register save area
1749 C: the header after B
1751 If the frame pointer isn't used, we'll have to set up A, B and C
1752 using the stack pointer. If the frame pointer is used, we'll access
1756 B: set up using sp or a temporary (see below)
1759 We set up B using the stack pointer if the frame is small enough.
1760 Otherwise, it's more efficient to copy the old stack pointer into a
1761 temporary and use that.
1763 Note that it's important to make sure the prologue and epilogue use the
1764 same registers to access A and C, since doing otherwise will confuse
1765 the aliasing code. */
1767 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1768 isn't used, the same method will serve for C. */
1769 accessor.op = FRV_STORE;
1770 if (frame_pointer_needed && info->total_size > 2048)
1774 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1775 accessor.base_offset = info->total_size;
1776 insn = emit_insn (gen_movsi (accessor.base, sp));
1780 accessor.base = stack_pointer_rtx;
1781 accessor.base_offset = 0;
1784 /* Allocate the stack space. */
1786 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1787 rtx dwarf_offset = GEN_INT (-info->total_size);
1789 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1792 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1795 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1796 and point the new one to that location. */
1797 if (frame_pointer_needed)
1799 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1801 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1802 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1804 rtx asm_src = plus_constant (accessor.base,
1805 fp_offset - accessor.base_offset);
1806 rtx dwarf_src = plus_constant (sp, fp_offset);
1808 /* Store the old frame pointer at (sp + FP_OFFSET). */
1809 frv_frame_access (&accessor, fp, fp_offset);
1811 /* Set up the new frame pointer. */
1812 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1813 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1815 /* Access region C from the frame pointer. */
1817 accessor.base_offset = fp_offset;
1820 /* Set up region C. */
1821 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1822 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1823 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1825 /* Set up region A. */
1826 frv_frame_access_standard_regs (FRV_STORE, info);
1828 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1829 scheduler from moving loads before the stores saving the registers. */
1830 if (info->stdarg_size > 0)
1831 emit_insn (gen_blockage ());
1833 /* Set up pic register/small data register for this function. */
1834 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1835 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1836 gen_rtx_REG (Pmode, LR_REGNO),
1837 gen_rtx_REG (SImode, OFFSET_REGNO)));
1841 /* Under frv, all of the work is done via frv_expand_epilogue, but
1842 this function provides a convenient place to do cleanup. */
1845 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1846 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1848 frv_stack_cache = (frv_stack_t *)0;
1850 /* Zap last used registers for conditional execution. */
1851 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1853 /* Release the bitmap of created insns. */
1854 BITMAP_XFREE (frv_ifcvt.scratch_insns_bitmap);
1858 /* Called after register allocation to add any instructions needed for the
1859 epilogue. Using an epilogue insn is favored compared to putting all of the
1860 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1861 it allows the scheduler to intermix instructions with the saves of
1862 the caller saved registers. In some cases, it might be necessary
1863 to emit a barrier instruction as the last insn to prevent such
1867 frv_expand_epilogue (bool emit_return)
1869 frv_stack_t *info = frv_stack_info ();
1870 rtx fp = frame_pointer_rtx;
1871 rtx sp = stack_pointer_rtx;
1875 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1877 /* Restore the stack pointer to its original value if alloca or the like
1879 if (! current_function_sp_is_unchanging)
1880 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1882 /* Restore the callee-saved registers that were used in this function. */
1883 frv_frame_access_standard_regs (FRV_LOAD, info);
1885 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1886 no return instruction should be emitted. */
1887 if (info->save_p[LR_REGNO])
1892 /* Use the same method to access the link register's slot as we did in
1893 the prologue. In other words, use the frame pointer if available,
1894 otherwise use the stack pointer.
1896 LR_OFFSET is the offset of the link register's slot from the start
1897 of the frame and MEM is a memory rtx for it. */
1898 lr_offset = info->reg_offset[LR_REGNO];
1899 if (frame_pointer_needed)
1900 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1902 mem = frv_frame_mem (Pmode, sp, lr_offset);
1904 /* Load the old link register into a GPR. */
1905 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1906 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1909 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1911 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1912 the load is preserved. */
1913 if (frame_pointer_needed)
1915 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1916 emit_insn (gen_rtx_USE (VOIDmode, fp));
1919 /* Deallocate the stack frame. */
1920 if (info->total_size != 0)
1922 rtx offset = frv_frame_offset_rtx (info->total_size);
1923 emit_insn (gen_stack_adjust (sp, sp, offset));
1926 /* If this function uses eh_return, add the final stack adjustment now. */
1927 if (current_function_calls_eh_return)
1928 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1931 emit_jump_insn (gen_epilogue_return (return_addr));
1934 rtx lr = return_addr;
1936 if (REGNO (return_addr) != LR_REGNO)
1938 lr = gen_rtx_REG (Pmode, LR_REGNO);
1939 emit_move_insn (lr, return_addr);
1942 emit_insn (gen_rtx_USE (VOIDmode, lr));
1947 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1950 frv_asm_output_mi_thunk (FILE *file,
1951 tree thunk_fndecl ATTRIBUTE_UNUSED,
1952 HOST_WIDE_INT delta,
1953 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1956 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1957 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1958 const char *name_jmp = reg_names[JUMP_REGNO];
1959 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1961 /* Do the add using an addi if possible. */
1962 if (IN_RANGE_P (delta, -2048, 2047))
1963 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1966 const char *const name_add = reg_names[TEMP_REGNO];
1967 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1968 parallel, delta, name_add);
1969 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1971 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1976 const char *name_pic = reg_names[FDPIC_REGNO];
1977 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1981 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1982 assemble_name (file, name_func);
1983 fprintf (file, "),%s\n", name_jmp);
1985 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1986 assemble_name (file, name_func);
1987 fprintf (file, "),%s\n", name_jmp);
1989 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1993 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
1994 assemble_name (file, name_func);
1995 fprintf (file, "\t)), %s\n", name_jmp);
2000 fprintf (file, "\tsethi%s #hi(", parallel);
2001 assemble_name (file, name_func);
2002 fprintf (file, "),%s\n", name_jmp);
2004 fprintf (file, "\tsetlo #lo(");
2005 assemble_name (file, name_func);
2006 fprintf (file, "),%s\n", name_jmp);
2010 /* Use JUMP_REGNO as a temporary PIC register. */
2011 const char *name_lr = reg_names[LR_REGNO];
2012 const char *name_gppic = name_jmp;
2013 const char *name_tmp = reg_names[TEMP_REGNO];
2015 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2016 fprintf (file, "\tcall 1f\n");
2017 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2018 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2019 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2020 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2021 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2023 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2024 assemble_name (file, name_func);
2025 fprintf (file, "),%s\n", name_tmp);
2027 fprintf (file, "\tsetlo #gprello(");
2028 assemble_name (file, name_func);
2029 fprintf (file, "),%s\n", name_tmp);
2031 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2034 /* Jump to the function address. */
2035 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2039 /* A C expression which is nonzero if a function must have and use a frame
2040 pointer. This expression is evaluated in the reload pass. If its value is
2041 nonzero the function will have a frame pointer.
2043 The expression can in principle examine the current function and decide
2044 according to the facts, but on most machines the constant 0 or the constant
2045 1 suffices. Use 0 when the machine allows code to be generated with no
2046 frame pointer, and doing so saves some time or space. Use 1 when there is
2047 no possible advantage to avoiding a frame pointer.
2049 In certain cases, the compiler does not know how to produce valid code
2050 without a frame pointer. The compiler recognizes those cases and
2051 automatically gives the function a frame pointer regardless of what
2052 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2054 In a function that does not require a frame pointer, the frame pointer
2055 register can be allocated for ordinary usage, unless you mark it as a fixed
2056 register. See `FIXED_REGISTERS' for more information. */
2058 /* On frv, create a frame whenever we need to create stack. */
2061 frv_frame_pointer_required (void)
2063 /* If we forgoing the usual linkage requirements, we only need
2064 a frame pointer if the stack pointer might change. */
2065 if (!TARGET_LINKED_FP)
2066 return !current_function_sp_is_unchanging;
2068 if (! current_function_is_leaf)
2071 if (get_frame_size () != 0)
2077 if (!current_function_sp_is_unchanging)
2080 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
2086 if (cfun->machine->frame_needed)
2093 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2094 initial difference between the specified pair of registers. This macro must
2095 be defined if `ELIMINABLE_REGS' is defined. */
2097 /* See frv_stack_info for more details on the frv stack frame. */
2100 frv_initial_elimination_offset (int from, int to)
2102 frv_stack_t *info = frv_stack_info ();
2105 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2106 ret = info->total_size - info->pretend_size;
2108 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2109 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2111 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2112 ret = (info->total_size
2113 - info->reg_offset[FRAME_POINTER_REGNUM]
2114 - info->pretend_size);
2119 if (TARGET_DEBUG_STACK)
2120 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2121 reg_names [from], reg_names[to], ret);
2127 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2130 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2131 enum machine_mode mode,
2132 tree type ATTRIBUTE_UNUSED,
2136 if (TARGET_DEBUG_ARG)
2138 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2139 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2143 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2146 frv_expand_builtin_saveregs (void)
2148 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2150 if (TARGET_DEBUG_ARG)
2151 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2154 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2158 /* Expand __builtin_va_start to do the va_start macro. */
2161 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2164 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2166 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2167 GEN_INT (UNITS_PER_WORD * num));
2169 if (TARGET_DEBUG_ARG)
2171 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2172 cfun->args_info, num);
2174 debug_rtx (nextarg);
2177 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2178 make_tree (ptr_type_node, nextarg));
2179 TREE_SIDE_EFFECTS (t) = 1;
2181 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2185 /* Expand a block move operation, and return 1 if successful. Return 0
2186 if we should let the compiler generate normal code.
2188 operands[0] is the destination
2189 operands[1] is the source
2190 operands[2] is the length
2191 operands[3] is the alignment */
2193 /* Maximum number of loads to do before doing the stores */
2194 #ifndef MAX_MOVE_REG
2195 #define MAX_MOVE_REG 4
2198 /* Maximum number of total loads to do. */
2199 #ifndef TOTAL_MOVE_REG
2200 #define TOTAL_MOVE_REG 8
2204 frv_expand_block_move (rtx operands[])
2206 rtx orig_dest = operands[0];
2207 rtx orig_src = operands[1];
2208 rtx bytes_rtx = operands[2];
2209 rtx align_rtx = operands[3];
2210 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2223 rtx stores[MAX_MOVE_REG];
2225 enum machine_mode mode;
2227 /* If this is not a fixed size move, just call memcpy. */
2231 /* If this is not a fixed size alignment, abort. */
2232 if (GET_CODE (align_rtx) != CONST_INT)
2235 align = INTVAL (align_rtx);
2237 /* Anything to move? */
2238 bytes = INTVAL (bytes_rtx);
2242 /* Don't support real large moves. */
2243 if (bytes > TOTAL_MOVE_REG*align)
2246 /* Move the address into scratch registers. */
2247 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2248 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2250 num_reg = offset = 0;
2251 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2253 /* Calculate the correct offset for src/dest. */
2257 dest_addr = dest_reg;
2261 src_addr = plus_constant (src_reg, offset);
2262 dest_addr = plus_constant (dest_reg, offset);
2265 /* Generate the appropriate load and store, saving the stores
2267 if (bytes >= 4 && align >= 4)
2269 else if (bytes >= 2 && align >= 2)
2274 move_bytes = GET_MODE_SIZE (mode);
2275 tmp_reg = gen_reg_rtx (mode);
2276 src_mem = change_address (orig_src, mode, src_addr);
2277 dest_mem = change_address (orig_dest, mode, dest_addr);
2278 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2279 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2281 if (num_reg >= MAX_MOVE_REG)
2283 for (i = 0; i < num_reg; i++)
2284 emit_insn (stores[i]);
2289 for (i = 0; i < num_reg; i++)
2290 emit_insn (stores[i]);
2296 /* Expand a block clear operation, and return 1 if successful. Return 0
2297 if we should let the compiler generate normal code.
2299 operands[0] is the destination
2300 operands[1] is the length
2301 operands[2] is the alignment */
2304 frv_expand_block_clear (rtx operands[])
2306 rtx orig_dest = operands[0];
2307 rtx bytes_rtx = operands[1];
2308 rtx align_rtx = operands[2];
2309 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2318 enum machine_mode mode;
2320 /* If this is not a fixed size move, just call memcpy. */
2324 /* If this is not a fixed size alignment, abort. */
2325 if (GET_CODE (align_rtx) != CONST_INT)
2328 align = INTVAL (align_rtx);
2330 /* Anything to move? */
2331 bytes = INTVAL (bytes_rtx);
2335 /* Don't support real large clears. */
2336 if (bytes > TOTAL_MOVE_REG*align)
2339 /* Move the address into a scratch register. */
2340 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2342 num_reg = offset = 0;
2343 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2345 /* Calculate the correct offset for src/dest. */
2346 dest_addr = ((offset == 0)
2348 : plus_constant (dest_reg, offset));
2350 /* Generate the appropriate store of gr0. */
2351 if (bytes >= 4 && align >= 4)
2353 else if (bytes >= 2 && align >= 2)
2358 clear_bytes = GET_MODE_SIZE (mode);
2359 dest_mem = change_address (orig_dest, mode, dest_addr);
2360 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2367 /* The following variable is used to output modifiers of assembler
2368 code of the current output insn. */
2370 static rtx *frv_insn_operands;
2372 /* The following function is used to add assembler insn code suffix .p
2373 if it is necessary. */
2376 frv_asm_output_opcode (FILE *f, const char *ptr)
2380 if (frv_insn_packing_flag <= 0)
2383 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2386 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2387 || (*ptr >= 'A' && *ptr <= 'Z')))
2389 int letter = *ptr++;
2392 frv_print_operand (f, frv_insn_operands [c], letter);
2393 while ((c = *ptr) >= '0' && c <= '9')
2405 /* Set up the packing bit for the current output insn. Note that this
2406 function is not called for asm insns. */
2409 frv_final_prescan_insn (rtx insn, rtx *opvec,
2410 int noperands ATTRIBUTE_UNUSED)
2414 if (frv_insn_packing_flag >= 0)
2416 frv_insn_operands = opvec;
2417 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2419 else if (recog_memoized (insn) >= 0
2420 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2421 /* Packing optimizations have been disabled, but INSN can only
2422 be issued in M1. Insert an mnop in M0. */
2423 fprintf (asm_out_file, "\tmnop.p\n");
2429 /* A C expression whose value is RTL representing the address in a stack frame
2430 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2431 an RTL expression for the address of the stack frame itself.
2433 If you don't define this macro, the default is to return the value of
2434 FRAMEADDR--that is, the stack frame address is also the address of the stack
2435 word that points to the previous frame. */
2437 /* The default is correct, but we need to make sure the frame gets created. */
2439 frv_dynamic_chain_address (rtx frame)
2441 cfun->machine->frame_needed = 1;
2446 /* A C expression whose value is RTL representing the value of the return
2447 address for the frame COUNT steps up from the current frame, after the
2448 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2449 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2452 The value of the expression must always be the correct address when COUNT is
2453 zero, but may be `NULL_RTX' if there is not way to determine the return
2454 address of other frames. */
2457 frv_return_addr_rtx (int count, rtx frame)
2461 cfun->machine->frame_needed = 1;
2462 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2465 /* Given a memory reference MEMREF, interpret the referenced memory as
2466 an array of MODE values, and return a reference to the element
2467 specified by INDEX. Assume that any pre-modification implicit in
2468 MEMREF has already happened.
2470 MEMREF must be a legitimate operand for modes larger than SImode.
2471 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2472 this function cannot handle. */
2474 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2476 rtx base = XEXP (memref, 0);
2477 if (GET_CODE (base) == PRE_MODIFY)
2478 base = XEXP (base, 0);
2479 return change_address (memref, mode,
2480 plus_constant (base, index * GET_MODE_SIZE (mode)));
2484 /* Print a memory address as an operand to reference that memory location. */
2486 frv_print_operand_address (FILE * stream, rtx x)
2488 if (GET_CODE (x) == MEM)
2491 switch (GET_CODE (x))
2494 fputs (reg_names [ REGNO (x)], stream);
2498 fprintf (stream, "%ld", (long) INTVAL (x));
2502 assemble_name (stream, XSTR (x, 0));
2507 output_addr_const (stream, x);
2514 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2519 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2521 int regno = true_regnum (x);
2523 fputs (reg_names[regno], stream);
2525 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2528 /* Print a memory reference suitable for the ld/st instructions. */
2531 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2533 struct frv_unspec unspec;
2537 switch (GET_CODE (x))
2544 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2546 x1 = XEXP (XEXP (x, 1), 1);
2556 if (GET_CODE (x0) == CONST_INT)
2564 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2573 else if (GET_CODE (x1) != CONST_INT)
2574 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2577 fputs ("@(", stream);
2579 fputs (reg_names[GPR_R0], stream);
2580 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2581 frv_print_operand_memory_reference_reg (stream, x0);
2583 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2585 fputs (",", stream);
2587 fputs (reg_names [GPR_R0], stream);
2591 switch (GET_CODE (x1))
2595 frv_print_operand_memory_reference_reg (stream, x1);
2599 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2603 if (!frv_const_unspec_p (x1, &unspec))
2604 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2605 frv_output_const_unspec (stream, &unspec);
2609 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2613 fputs (")", stream);
2617 /* Return 2 for likely branches and 0 for non-likely branches */
2619 #define FRV_JUMP_LIKELY 2
2620 #define FRV_JUMP_NOT_LIKELY 0
2623 frv_print_operand_jump_hint (rtx insn)
2628 HOST_WIDE_INT prob = -1;
2629 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2631 if (GET_CODE (insn) != JUMP_INSN)
2634 /* Assume any non-conditional jump is likely. */
2635 if (! any_condjump_p (insn))
2636 ret = FRV_JUMP_LIKELY;
2640 labelref = condjump_label (insn);
2643 rtx label = XEXP (labelref, 0);
2644 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2649 note = find_reg_note (insn, REG_BR_PROB, 0);
2651 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2655 prob = INTVAL (XEXP (note, 0));
2656 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2658 : FRV_JUMP_NOT_LIKELY);
2670 case UNKNOWN: direction = "unknown jump direction"; break;
2671 case BACKWARD: direction = "jump backward"; break;
2672 case FORWARD: direction = "jump forward"; break;
2676 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2677 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2678 (long)INSN_UID (insn), direction, (long)prob,
2679 (long)REG_BR_PROB_BASE, ret);
2687 /* Return the comparison operator to use for CODE given that the ICC
2691 comparison_string (enum rtx_code code, rtx op0)
2693 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2696 default: output_operand_lossage ("bad condition code");
2697 case EQ: return "eq";
2698 case NE: return "ne";
2699 case LT: return is_nz_p ? "n" : "lt";
2700 case LE: return "le";
2701 case GT: return "gt";
2702 case GE: return is_nz_p ? "p" : "ge";
2703 case LTU: return is_nz_p ? "no" : "c";
2704 case LEU: return is_nz_p ? "eq" : "ls";
2705 case GTU: return is_nz_p ? "ne" : "hi";
2706 case GEU: return is_nz_p ? "ra" : "nc";
2710 /* Print an operand to an assembler instruction.
2712 `%' followed by a letter and a digit says to output an operand in an
2713 alternate fashion. Four letters have standard, built-in meanings described
2714 below. The machine description macro `PRINT_OPERAND' can define additional
2715 letters with nonstandard meanings.
2717 `%cDIGIT' can be used to substitute an operand that is a constant value
2718 without the syntax that normally indicates an immediate operand.
2720 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2723 `%aDIGIT' can be used to substitute an operand as if it were a memory
2724 reference, with the actual operand treated as the address. This may be
2725 useful when outputting a "load address" instruction, because often the
2726 assembler syntax for such an instruction requires you to write the operand
2727 as if it were a memory reference.
2729 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2731 `%=' outputs a number which is unique to each instruction in the entire
2732 compilation. This is useful for making local labels to be referred to more
2733 than once in a single template that generates multiple assembler
2736 `%' followed by a punctuation character specifies a substitution that does
2737 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2738 assembler code. Other nonstandard cases can be defined in the
2739 `PRINT_OPERAND' macro. You must also define which punctuation characters
2740 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2743 frv_print_operand (FILE * file, rtx x, int code)
2745 struct frv_unspec unspec;
2746 HOST_WIDE_INT value;
2749 if (code != 0 && !isalpha (code))
2752 else if (GET_CODE (x) == CONST_INT)
2755 else if (GET_CODE (x) == CONST_DOUBLE)
2757 if (GET_MODE (x) == SFmode)
2762 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2763 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2767 else if (GET_MODE (x) == VOIDmode)
2768 value = CONST_DOUBLE_LOW (x);
2771 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2782 fputs (reg_names[GPR_R0], file);
2786 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2790 /* Output small data area base register (gr16). */
2791 fputs (reg_names[SDA_BASE_REG], file);
2795 /* Output pic register (gr17). */
2796 fputs (reg_names[PIC_REGNO], file);
2800 /* Output the temporary integer CCR register. */
2801 fputs (reg_names[ICR_TEMP], file);
2805 /* Output the temporary integer CC register. */
2806 fputs (reg_names[ICC_TEMP], file);
2809 /* case 'a': print an address. */
2812 /* Print appropriate test for integer branch false operation. */
2813 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2814 XEXP (x, 0)), file);
2818 /* Print appropriate test for integer branch true operation. */
2819 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2823 /* Print 1 for a NE and 0 for an EQ to give the final argument
2824 for a conditional instruction. */
2825 if (GET_CODE (x) == NE)
2828 else if (GET_CODE (x) == EQ)
2832 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2836 /* Print appropriate test for floating point branch false operation. */
2837 switch (GET_CODE (x))
2840 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2842 case EQ: fputs ("ne", file); break;
2843 case NE: fputs ("eq", file); break;
2844 case LT: fputs ("uge", file); break;
2845 case LE: fputs ("ug", file); break;
2846 case GT: fputs ("ule", file); break;
2847 case GE: fputs ("ul", file); break;
2852 /* Print appropriate test for floating point branch true operation. */
2853 switch (GET_CODE (x))
2856 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2858 case EQ: fputs ("eq", file); break;
2859 case NE: fputs ("ne", file); break;
2860 case LT: fputs ("lt", file); break;
2861 case LE: fputs ("le", file); break;
2862 case GT: fputs ("gt", file); break;
2863 case GE: fputs ("ge", file); break;
2868 /* Print appropriate GOT function. */
2869 if (GET_CODE (x) != CONST_INT)
2870 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2871 fputs (unspec_got_name (INTVAL (x)), file);
2875 /* Print 'i' if the operand is a constant, or is a memory reference that
2877 if (GET_CODE (x) == MEM)
2878 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2879 ? XEXP (XEXP (x, 0), 1)
2881 else if (GET_CODE (x) == PLUS)
2884 switch (GET_CODE (x))
2898 /* For jump instructions, print 'i' if the operand is a constant or
2899 is an expression that adds a constant. */
2900 if (GET_CODE (x) == CONST_INT)
2905 if (GET_CODE (x) == CONST_INT
2906 || (GET_CODE (x) == PLUS
2907 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2908 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2914 /* Print the lower register of a double word register pair */
2915 if (GET_CODE (x) == REG)
2916 fputs (reg_names[ REGNO (x)+1 ], file);
2918 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2921 /* case 'l': print a LABEL_REF. */
2925 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2926 for the second word of double memory operations. */
2927 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2928 switch (GET_CODE (x))
2931 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2934 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2942 frv_print_operand_memory_reference (file, x, offset);
2948 /* Print the opcode of a command. */
2949 switch (GET_CODE (x))
2952 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2954 case PLUS: fputs ("add", file); break;
2955 case MINUS: fputs ("sub", file); break;
2956 case AND: fputs ("and", file); break;
2957 case IOR: fputs ("or", file); break;
2958 case XOR: fputs ("xor", file); break;
2959 case ASHIFT: fputs ("sll", file); break;
2960 case ASHIFTRT: fputs ("sra", file); break;
2961 case LSHIFTRT: fputs ("srl", file); break;
2965 /* case 'n': negate and print a constant int. */
2968 /* Print PIC label using operand as the number. */
2969 if (GET_CODE (x) != CONST_INT)
2970 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2972 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2976 /* Print 'u' if the operand is a update load/store. */
2977 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2982 /* If value is 0, print gr0, otherwise it must be a register. */
2983 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2984 fputs (reg_names[GPR_R0], file);
2986 else if (GET_CODE (x) == REG)
2987 fputs (reg_names [REGNO (x)], file);
2990 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2994 /* Print constant in hex. */
2995 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2997 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3004 if (GET_CODE (x) == REG)
3005 fputs (reg_names [REGNO (x)], file);
3007 else if (GET_CODE (x) == CONST_INT
3008 || GET_CODE (x) == CONST_DOUBLE)
3009 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3011 else if (frv_const_unspec_p (x, &unspec))
3012 frv_output_const_unspec (file, &unspec);
3014 else if (GET_CODE (x) == MEM)
3015 frv_print_operand_address (file, XEXP (x, 0));
3017 else if (CONSTANT_ADDRESS_P (x))
3018 frv_print_operand_address (file, x);
3021 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3026 fatal_insn ("frv_print_operand: unknown code", x);
3034 /* A C statement (sans semicolon) for initializing the variable CUM for the
3035 state at the beginning of the argument list. The variable has type
3036 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3037 of the function which will receive the args, or 0 if the args are to a
3038 compiler support library function. The value of INDIRECT is nonzero when
3039 processing an indirect call, for example a call through a function pointer.
3040 The value of INDIRECT is zero for a call to an explicitly named function, a
3041 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3042 arguments for the function being compiled.
3044 When processing a call to a compiler support library function, LIBNAME
3045 identifies which one. It is a `symbol_ref' rtx which contains the name of
3046 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3047 being processed. Thus, each time this macro is called, either LIBNAME or
3048 FNTYPE is nonzero, but never both of them at once. */
3051 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3057 *cum = FIRST_ARG_REGNUM;
3059 if (TARGET_DEBUG_ARG)
3061 fprintf (stderr, "\ninit_cumulative_args:");
3062 if (!fndecl && fntype)
3063 fputs (" indirect", stderr);
3066 fputs (" incoming", stderr);
3070 tree ret_type = TREE_TYPE (fntype);
3071 fprintf (stderr, " return=%s,",
3072 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3075 if (libname && GET_CODE (libname) == SYMBOL_REF)
3076 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3078 if (cfun->returns_struct)
3079 fprintf (stderr, " return-struct");
3081 putc ('\n', stderr);
3086 /* Return true if we should pass an argument on the stack rather than
3090 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3092 if (mode == BLKmode)
3096 return AGGREGATE_TYPE_P (type);
3099 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3100 argument with the specified mode and type. If it is not defined,
3101 `PARM_BOUNDARY' is used for all arguments. */
3104 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3105 tree type ATTRIBUTE_UNUSED)
3107 return BITS_PER_WORD;
3111 frv_function_arg (CUMULATIVE_ARGS *cum,
3112 enum machine_mode mode,
3113 tree type ATTRIBUTE_UNUSED,
3115 int incoming ATTRIBUTE_UNUSED)
3117 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3122 /* Return a marker for use in the call instruction. */
3123 if (xmode == VOIDmode)
3129 else if (arg_num <= LAST_ARG_REGNUM)
3131 ret = gen_rtx_REG (xmode, arg_num);
3132 debstr = reg_names[arg_num];
3141 if (TARGET_DEBUG_ARG)
3143 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3144 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3150 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3151 advance past an argument in the argument list. The values MODE, TYPE and
3152 NAMED describe that argument. Once this is done, the variable CUM is
3153 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3155 This macro need not do anything if the argument in question was passed on
3156 the stack. The compiler knows how to track the amount of stack space used
3157 for arguments without any special help. */
3160 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3161 enum machine_mode mode,
3162 tree type ATTRIBUTE_UNUSED,
3165 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3166 int bytes = GET_MODE_SIZE (xmode);
3167 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3170 *cum = arg_num + words;
3172 if (TARGET_DEBUG_ARG)
3174 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3175 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3179 /* A C expression for the number of words, at the beginning of an argument,
3180 must be put in registers. The value must be zero for arguments that are
3181 passed entirely in registers or that are entirely pushed on the stack.
3183 On some machines, certain arguments must be passed partially in registers
3184 and partially in memory. On these machines, typically the first N words of
3185 arguments are passed in registers, and the rest on the stack. If a
3186 multi-word argument (a `double' or a structure) crosses that boundary, its
3187 first few words must be passed in registers and the rest must be pushed.
3188 This macro tells the compiler when this occurs, and how many of the words
3189 should go in registers.
3191 `FUNCTION_ARG' for these arguments should return the first register to be
3192 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3193 the called function. */
3196 frv_function_arg_partial_nregs (CUMULATIVE_ARGS *cum,
3197 enum machine_mode mode,
3198 tree type ATTRIBUTE_UNUSED,
3199 int named ATTRIBUTE_UNUSED)
3201 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3202 int bytes = GET_MODE_SIZE (xmode);
3203 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3207 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3208 ? LAST_ARG_REGNUM - arg_num + 1
3211 if (TARGET_DEBUG_ARG && ret)
3212 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
3219 /* Return true if a register is ok to use as a base or index register. */
3221 static FRV_INLINE int
3222 frv_regno_ok_for_base_p (int regno, int strict_p)
3228 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3230 if (regno == ARG_POINTER_REGNUM)
3233 return (regno >= FIRST_PSEUDO_REGISTER);
3237 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3238 RTX) is a legitimate memory address on the target machine for a memory
3239 operand of mode MODE.
3241 It usually pays to define several simpler macros to serve as subroutines for
3242 this one. Otherwise it may be too complicated to understand.
3244 This macro must exist in two variants: a strict variant and a non-strict
3245 one. The strict variant is used in the reload pass. It must be defined so
3246 that any pseudo-register that has not been allocated a hard register is
3247 considered a memory reference. In contexts where some kind of register is
3248 required, a pseudo-register with no hard register must be rejected.
3250 The non-strict variant is used in other passes. It must be defined to
3251 accept all pseudo-registers in every context where some kind of register is
3254 Compiler source files that want to use the strict variant of this macro
3255 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3256 conditional to define the strict variant in that case and the non-strict
3259 Subroutines to check for acceptable registers for various purposes (one for
3260 base registers, one for index registers, and so on) are typically among the
3261 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3262 subroutine macros need have two variants; the higher levels of macros may be
3263 the same whether strict or not.
3265 Normally, constant addresses which are the sum of a `symbol_ref' and an
3266 integer are stored inside a `const' RTX to mark them as constant.
3267 Therefore, there is no need to recognize such sums specifically as
3268 legitimate addresses. Normally you would simply recognize any `const' as
3271 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3272 are not marked with `const'. It assumes that a naked `plus' indicates
3273 indexing. If so, then you *must* reject such naked constant sums as
3274 illegitimate addresses, so that none of them will be given to
3275 `PRINT_OPERAND_ADDRESS'.
3277 On some machines, whether a symbolic address is legitimate depends on the
3278 section that the address refers to. On these machines, define the macro
3279 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3280 then check for it here. When you see a `const', you will have to look
3281 inside it to find the `symbol_ref' in order to determine the section.
3283 The best way to modify the name string is by adding text to the beginning,
3284 with suitable punctuation to prevent any ambiguity. Allocate the new name
3285 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3286 remove and decode the added text and output the name accordingly, and define
3287 `(* targetm.strip_name_encoding)' to access the original name string.
3289 You can check the information stored here into the `symbol_ref' in the
3290 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3291 `PRINT_OPERAND_ADDRESS'. */
3294 frv_legitimate_address_p (enum machine_mode mode,
3298 int allow_double_reg_p)
3302 HOST_WIDE_INT value;
3305 switch (GET_CODE (x))
3312 if (GET_CODE (x) != REG)
3318 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3324 if (GET_CODE (x0) != REG
3325 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3326 || GET_CODE (x1) != PLUS
3327 || ! rtx_equal_p (x0, XEXP (x1, 0))
3328 || GET_CODE (XEXP (x1, 1)) != REG
3329 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3336 /* 12 bit immediate */
3341 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3343 /* If we can't use load/store double operations, make sure we can
3344 address the second word. */
3345 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3346 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3355 if (GET_CODE (x0) == SUBREG)
3356 x0 = SUBREG_REG (x0);
3358 if (GET_CODE (x0) != REG)
3361 regno0 = REGNO (x0);
3362 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3365 switch (GET_CODE (x1))
3371 x1 = SUBREG_REG (x1);
3372 if (GET_CODE (x1) != REG)
3378 /* Do not allow reg+reg addressing for modes > 1 word if we
3379 can't depend on having move double instructions. */
3380 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3383 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3387 /* 12 bit immediate */
3392 value = INTVAL (x1);
3393 ret = IN_RANGE_P (value, -2048, 2047);
3395 /* If we can't use load/store double operations, make sure we can
3396 address the second word. */
3397 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3398 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3403 if (!condexec_p && got12_operand (x1, VOIDmode))
3411 if (TARGET_DEBUG_ADDR)
3413 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3414 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3415 (condexec_p) ? ", inside conditional code" : "");
3423 frv_legitimize_address (rtx x ATTRIBUTE_UNUSED,
3424 rtx oldx ATTRIBUTE_UNUSED,
3425 enum machine_mode mode ATTRIBUTE_UNUSED)
3430 /* Test whether a local function descriptor is canonical, i.e.,
3431 whether we can use FUNCDESC_GOTOFF to compute the address of the
3435 frv_local_funcdesc_p (rtx fnx)
3438 enum symbol_visibility vis;
3441 if (! SYMBOL_REF_LOCAL_P (fnx))
3444 fn = SYMBOL_REF_DECL (fnx);
3449 vis = DECL_VISIBILITY (fn);
3451 if (vis == VISIBILITY_PROTECTED)
3452 /* Private function descriptors for protected functions are not
3453 canonical. Temporarily change the visibility to global. */
3454 vis = VISIBILITY_DEFAULT;
3455 else if (flag_shlib)
3456 /* If we're already compiling for a shared library (that, unlike
3457 executables, can't assume that the existence of a definition
3458 implies local binding), we can skip the re-testing. */
3461 ret = default_binds_local_p_1 (fn, flag_pic);
3463 DECL_VISIBILITY (fn) = vis;
3468 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3472 frv_gen_GPsym2reg (rtx dest, rtx src)
3474 tree gp = get_identifier ("_gp");
3475 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3477 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3481 unspec_got_name (int i)
3485 case R_FRV_GOT12: return "got12";
3486 case R_FRV_GOTHI: return "gothi";
3487 case R_FRV_GOTLO: return "gotlo";
3488 case R_FRV_FUNCDESC: return "funcdesc";
3489 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3490 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3491 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3492 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3493 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3494 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3495 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3496 case R_FRV_GOTOFF12: return "gotoff12";
3497 case R_FRV_GOTOFFHI: return "gotoffhi";
3498 case R_FRV_GOTOFFLO: return "gotofflo";
3499 case R_FRV_GPREL12: return "gprel12";
3500 case R_FRV_GPRELHI: return "gprelhi";
3501 case R_FRV_GPRELLO: return "gprello";
3506 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3507 is added inside the relocation operator. */
3510 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3512 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3513 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3514 fputs (")", stream);
3517 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3518 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3519 otherwise return ORIG_X. */
3522 frv_find_base_term (rtx x)
3524 struct frv_unspec unspec;
3526 if (frv_const_unspec_p (x, &unspec)
3527 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3528 return plus_constant (unspec.symbol, unspec.offset);
3533 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3534 the operand is used by a predicated instruction. */
3537 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3539 return ((GET_MODE (op) == mode || mode == VOIDmode)
3540 && GET_CODE (op) == MEM
3541 && frv_legitimate_address_p (mode, XEXP (op, 0),
3542 reload_completed, condexec_p, FALSE));
3546 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3548 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3549 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3555 rvrtx = operands[0];
3559 addr = XEXP (operands[0], 0);
3561 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3562 any calls that would involve a PLT, but can't tell, since we
3563 don't know whether an extern function is going to be provided by
3564 a separate translation unit or imported from a separate module.
3565 When compiling for shared libraries, if the function has default
3566 visibility, we assume it's overridable, so we inline the PLT, but
3567 for executables, we don't really have a way to make a good
3568 decision: a function is as likely to be imported from a shared
3569 library as it is to be defined in the executable itself. We
3570 assume executables will get global functions defined locally,
3571 whereas shared libraries will have them potentially overridden,
3572 so we only inline PLTs when compiling for shared libraries.
3574 In order to mark a function as local to a shared library, any
3575 non-default visibility attribute suffices. Unfortunately,
3576 there's no simple way to tag a function declaration as ``in a
3577 different module'', which we could then use to trigger PLT
3578 inlining on executables. There's -minline-plt, but it affects
3579 all external functions, so one would have to also mark function
3580 declarations available in the same module with non-default
3581 visibility, which is advantageous in itself. */
3582 if (GET_CODE (addr) == SYMBOL_REF
3583 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3587 dest = gen_reg_rtx (SImode);
3589 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3590 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3592 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3593 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3595 cfun->uses_pic_offset_table = TRUE;
3598 else if (GET_CODE (addr) == SYMBOL_REF)
3600 /* These are always either local, or handled through a local
3603 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3604 operands[2], picreg, lr);
3606 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3610 else if (! ldd_address_operand (addr, Pmode))
3611 addr = force_reg (Pmode, addr);
3613 picreg = gen_reg_rtx (DImode);
3614 emit_insn (gen_movdi_ldd (picreg, addr));
3616 if (sibcall && ret_value)
3617 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3619 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3621 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3623 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3627 /* An address operand that may use a pair of registers, an addressing
3628 mode that we reject in general. */
3631 ldd_address_operand (rtx x, enum machine_mode mode)
3633 if (GET_MODE (x) != mode && GET_MODE (x) != VOIDmode)
3636 return frv_legitimate_address_p (DImode, x, reload_completed, FALSE, TRUE);
3640 fdpic_fptr_operand (rtx op, enum machine_mode mode)
3642 if (GET_MODE (op) != mode && mode != VOIDmode)
3644 if (GET_CODE (op) != REG)
3646 if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
3651 /* Return 1 is OP is a memory operand, or will be turned into one by
3655 frv_load_operand (rtx op, enum machine_mode mode)
3657 if (GET_MODE (op) != mode && mode != VOIDmode)
3660 if (reload_in_progress)
3663 if (GET_CODE (tmp) == SUBREG)
3664 tmp = SUBREG_REG (tmp);
3665 if (GET_CODE (tmp) == REG
3666 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
3667 op = reg_equiv_memory_loc[REGNO (tmp)];
3670 return op && memory_operand (op, mode);
3674 /* Return 1 if operand is a GPR register or a FPR register. */
3677 gpr_or_fpr_operand (rtx op, enum machine_mode mode)
3681 if (GET_MODE (op) != mode && mode != VOIDmode)
3684 if (GET_CODE (op) == SUBREG)
3686 if (GET_CODE (SUBREG_REG (op)) != REG)
3687 return register_operand (op, mode);
3689 op = SUBREG_REG (op);
3692 if (GET_CODE (op) != REG)
3696 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3702 /* Return 1 if operand is a GPR register or 12 bit signed immediate. */
3705 gpr_or_int12_operand (rtx op, enum machine_mode mode)
3707 if (GET_CODE (op) == CONST_INT)
3708 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3710 if (got12_operand (op, mode))
3713 if (GET_MODE (op) != mode && mode != VOIDmode)
3716 if (GET_CODE (op) == SUBREG)
3718 if (GET_CODE (SUBREG_REG (op)) != REG)
3719 return register_operand (op, mode);
3721 op = SUBREG_REG (op);
3724 if (GET_CODE (op) != REG)
3727 return GPR_OR_PSEUDO_P (REGNO (op));
3730 /* Return 1 if operand is a GPR register, or a FPR register, or a 12 bit
3731 signed immediate. */
3734 gpr_fpr_or_int12_operand (rtx op, enum machine_mode mode)
3738 if (GET_CODE (op) == CONST_INT)
3739 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3741 if (GET_MODE (op) != mode && mode != VOIDmode)
3744 if (GET_CODE (op) == SUBREG)
3746 if (GET_CODE (SUBREG_REG (op)) != REG)
3747 return register_operand (op, mode);
3749 op = SUBREG_REG (op);
3752 if (GET_CODE (op) != REG)
3756 if (GPR_P (regno) || FPR_P (regno) || regno >= FIRST_PSEUDO_REGISTER)
3762 /* Return 1 if operand is a register or 6 bit signed immediate. */
3765 fpr_or_int6_operand (rtx op, enum machine_mode mode)
3767 if (GET_CODE (op) == CONST_INT)
3768 return IN_RANGE_P (INTVAL (op), -32, 31);
3770 if (GET_MODE (op) != mode && mode != VOIDmode)
3773 if (GET_CODE (op) == SUBREG)
3775 if (GET_CODE (SUBREG_REG (op)) != REG)
3776 return register_operand (op, mode);
3778 op = SUBREG_REG (op);
3781 if (GET_CODE (op) != REG)
3784 return FPR_OR_PSEUDO_P (REGNO (op));
3787 /* Return 1 if operand is a register or 10 bit signed immediate. */
3790 gpr_or_int10_operand (rtx op, enum machine_mode mode)
3792 if (GET_CODE (op) == CONST_INT)
3793 return IN_RANGE_P (INTVAL (op), -512, 511);
3795 if (GET_MODE (op) != mode && mode != VOIDmode)
3798 if (GET_CODE (op) == SUBREG)
3800 if (GET_CODE (SUBREG_REG (op)) != REG)
3801 return register_operand (op, mode);
3803 op = SUBREG_REG (op);
3806 if (GET_CODE (op) != REG)
3809 return GPR_OR_PSEUDO_P (REGNO (op));
3812 /* Return 1 if operand is a register or an integer immediate. */
3815 gpr_or_int_operand (rtx op, enum machine_mode mode)
3817 if (GET_CODE (op) == CONST_INT)
3820 if (GET_MODE (op) != mode && mode != VOIDmode)
3823 if (GET_CODE (op) == SUBREG)
3825 if (GET_CODE (SUBREG_REG (op)) != REG)
3826 return register_operand (op, mode);
3828 op = SUBREG_REG (op);
3831 if (GET_CODE (op) != REG)
3834 return GPR_OR_PSEUDO_P (REGNO (op));
3837 /* Return 1 if operand is a 12 bit signed immediate. */
3840 int12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3842 if (GET_CODE (op) != CONST_INT)
3845 return IN_RANGE_P (INTVAL (op), -2048, 2047);
3848 /* Return 1 if operand is a 6 bit signed immediate. */
3851 int6_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3853 if (GET_CODE (op) != CONST_INT)
3856 return IN_RANGE_P (INTVAL (op), -32, 31);
3859 /* Return 1 if operand is a 5 bit signed immediate. */
3862 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3864 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), -16, 15);
3867 /* Return 1 if operand is a 5 bit unsigned immediate. */
3870 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3872 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 31);
3875 /* Return 1 if operand is a 4 bit unsigned immediate. */
3878 uint4_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3880 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 15);
3883 /* Return 1 if operand is a 1 bit unsigned immediate (0 or 1). */
3886 uint1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3888 return GET_CODE (op) == CONST_INT && IN_RANGE_P (INTVAL (op), 0, 1);
3891 /* Return 1 if operand is an integer constant that takes 2 instructions
3892 to load up and can be split into sethi/setlo instructions.. */
3895 int_2word_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3897 HOST_WIDE_INT value;
3901 switch (GET_CODE (op))
3910 return (flag_pic == 0);
3913 if (flag_pic || TARGET_FDPIC)
3917 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
3919 return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
3925 /* small data references are already 1 word */
3926 return (flag_pic == 0) && (! SYMBOL_REF_SMALL_P (op));
3929 return ! IN_RANGE_P (INTVAL (op), -32768, 32767);
3932 if (GET_MODE (op) == SFmode)
3934 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
3935 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
3937 return ! IN_RANGE_P (value, -32768, 32767);
3939 else if (GET_MODE (op) == VOIDmode)
3941 value = CONST_DOUBLE_LOW (op);
3942 return ! IN_RANGE_P (value, -32768, 32767);
3950 /* Return 1 if operand is a 16 bit unsigned immediate. */
3953 uint16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3955 if (GET_CODE (op) != CONST_INT)
3958 return IN_RANGE_P (INTVAL (op), 0, 0xffff);
3961 /* Return 1 if operand is an integer constant with the bottom 16 bits
3965 upper_int16_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3967 if (GET_CODE (op) != CONST_INT)
3970 return ((INTVAL (op) & 0xffff) == 0);
3973 /* Return true if operand is a GPR register. */
3976 integer_register_operand (rtx op, enum machine_mode mode)
3978 if (GET_MODE (op) != mode && mode != VOIDmode)
3981 if (GET_CODE (op) == SUBREG)
3983 if (GET_CODE (SUBREG_REG (op)) != REG)
3984 return register_operand (op, mode);
3986 op = SUBREG_REG (op);
3989 if (GET_CODE (op) != REG)
3992 return GPR_OR_PSEUDO_P (REGNO (op));
3995 /* Return true if operand is a GPR register. Do not allow SUBREG's
3996 here, in order to prevent a combine bug. */
3999 gpr_no_subreg_operand (rtx op, enum machine_mode mode)
4001 if (GET_MODE (op) != mode && mode != VOIDmode)
4004 if (GET_CODE (op) != REG)
4007 return GPR_OR_PSEUDO_P (REGNO (op));
4010 /* Return true if operand is a FPR register. */
4013 fpr_operand (rtx op, enum machine_mode mode)
4015 if (GET_MODE (op) != mode && mode != VOIDmode)
4018 if (GET_CODE (op) == SUBREG)
4020 if (GET_CODE (SUBREG_REG (op)) != REG)
4021 return register_operand (op, mode);
4023 op = SUBREG_REG (op);
4026 if (GET_CODE (op) != REG)
4029 return FPR_OR_PSEUDO_P (REGNO (op));
4032 /* Return true if operand is an even GPR or FPR register. */
4035 even_reg_operand (rtx op, enum machine_mode mode)
4039 if (GET_MODE (op) != mode && mode != VOIDmode)
4042 if (GET_CODE (op) == SUBREG)
4044 if (GET_CODE (SUBREG_REG (op)) != REG)
4045 return register_operand (op, mode);
4047 op = SUBREG_REG (op);
4050 if (GET_CODE (op) != REG)
4054 if (regno >= FIRST_PSEUDO_REGISTER)
4058 return (((regno - GPR_FIRST) & 1) == 0);
4061 return (((regno - FPR_FIRST) & 1) == 0);
4066 /* Return true if operand is an odd GPR register. */
4069 odd_reg_operand (rtx op, enum machine_mode mode)
4073 if (GET_MODE (op) != mode && mode != VOIDmode)
4076 if (GET_CODE (op) == SUBREG)
4078 if (GET_CODE (SUBREG_REG (op)) != REG)
4079 return register_operand (op, mode);
4081 op = SUBREG_REG (op);
4084 if (GET_CODE (op) != REG)
4088 /* Assume that reload will give us an even register. */
4089 if (regno >= FIRST_PSEUDO_REGISTER)
4093 return (((regno - GPR_FIRST) & 1) != 0);
4096 return (((regno - FPR_FIRST) & 1) != 0);
4101 /* Return true if operand is an even GPR register. */
4104 even_gpr_operand (rtx op, enum machine_mode mode)
4108 if (GET_MODE (op) != mode && mode != VOIDmode)
4111 if (GET_CODE (op) == SUBREG)
4113 if (GET_CODE (SUBREG_REG (op)) != REG)
4114 return register_operand (op, mode);
4116 op = SUBREG_REG (op);
4119 if (GET_CODE (op) != REG)
4123 if (regno >= FIRST_PSEUDO_REGISTER)
4126 if (! GPR_P (regno))
4129 return (((regno - GPR_FIRST) & 1) == 0);
4132 /* Return true if operand is an odd GPR register. */
4135 odd_gpr_operand (rtx op, enum machine_mode mode)
4139 if (GET_MODE (op) != mode && mode != VOIDmode)
4142 if (GET_CODE (op) == SUBREG)
4144 if (GET_CODE (SUBREG_REG (op)) != REG)
4145 return register_operand (op, mode);
4147 op = SUBREG_REG (op);
4150 if (GET_CODE (op) != REG)
4154 /* Assume that reload will give us an even register. */
4155 if (regno >= FIRST_PSEUDO_REGISTER)
4158 if (! GPR_P (regno))
4161 return (((regno - GPR_FIRST) & 1) != 0);
4164 /* Return true if operand is a quad aligned FPR register. */
4167 quad_fpr_operand (rtx op, enum machine_mode mode)
4171 if (GET_MODE (op) != mode && mode != VOIDmode)
4174 if (GET_CODE (op) == SUBREG)
4176 if (GET_CODE (SUBREG_REG (op)) != REG)
4177 return register_operand (op, mode);
4179 op = SUBREG_REG (op);
4182 if (GET_CODE (op) != REG)
4186 if (regno >= FIRST_PSEUDO_REGISTER)
4189 if (! FPR_P (regno))
4192 return (((regno - FPR_FIRST) & 3) == 0);
4195 /* Return true if operand is an even FPR register. */
4198 even_fpr_operand (rtx op, enum machine_mode mode)
4202 if (GET_MODE (op) != mode && mode != VOIDmode)
4205 if (GET_CODE (op) == SUBREG)
4207 if (GET_CODE (SUBREG_REG (op)) != REG)
4208 return register_operand (op, mode);
4210 op = SUBREG_REG (op);
4213 if (GET_CODE (op) != REG)
4217 if (regno >= FIRST_PSEUDO_REGISTER)
4220 if (! FPR_P (regno))
4223 return (((regno - FPR_FIRST) & 1) == 0);
4226 /* Return true if operand is an odd FPR register. */
4229 odd_fpr_operand (rtx op, enum machine_mode mode)
4233 if (GET_MODE (op) != mode && mode != VOIDmode)
4236 if (GET_CODE (op) == SUBREG)
4238 if (GET_CODE (SUBREG_REG (op)) != REG)
4239 return register_operand (op, mode);
4241 op = SUBREG_REG (op);
4244 if (GET_CODE (op) != REG)
4248 /* Assume that reload will give us an even register. */
4249 if (regno >= FIRST_PSEUDO_REGISTER)
4252 if (! FPR_P (regno))
4255 return (((regno - FPR_FIRST) & 1) != 0);
4258 /* Return true if operand is a 2 word memory address that can be loaded in one
4259 instruction to load or store. We assume the stack and frame pointers are
4260 suitably aligned, and variables in the small data area. FIXME -- at some we
4261 should recognize other globals and statics. We can't assume that any old
4262 pointer is aligned, given that arguments could be passed on an odd word on
4263 the stack and the address taken and passed through to another function. */
4266 dbl_memory_one_insn_operand (rtx op, enum machine_mode mode)
4274 if (GET_CODE (op) != MEM)
4277 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4280 addr = XEXP (op, 0);
4281 if (GET_CODE (addr) == REG)
4284 else if (GET_CODE (addr) == PLUS)
4286 rtx addr0 = XEXP (addr, 0);
4287 rtx addr1 = XEXP (addr, 1);
4289 if (GET_CODE (addr0) != REG)
4292 if (got12_operand (addr1, VOIDmode))
4295 if (GET_CODE (addr1) != CONST_INT)
4298 if ((INTVAL (addr1) & 7) != 0)
4307 if (addr_reg == frame_pointer_rtx || addr_reg == stack_pointer_rtx)
4313 /* Return true if operand is a 2 word memory address that needs to
4314 use two instructions to load or store. */
4317 dbl_memory_two_insn_operand (rtx op, enum machine_mode mode)
4319 if (GET_CODE (op) != MEM)
4322 if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
4328 return ! dbl_memory_one_insn_operand (op, mode);
4331 /* Return true if operand is something that can be an output for a move
4335 move_destination_operand (rtx op, enum machine_mode mode)
4340 switch (GET_CODE (op))
4346 if (GET_MODE (op) != mode && mode != VOIDmode)
4349 subreg = SUBREG_REG (op);
4350 code = GET_CODE (subreg);
4352 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4353 reload_completed, FALSE, FALSE);
4355 return (code == REG);
4358 if (GET_MODE (op) != mode && mode != VOIDmode)
4364 return frv_legitimate_memory_operand (op, mode, FALSE);
4370 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
4371 process these separately from any offsets, such that we add any
4372 offsets to the function descriptor (the actual pointer), not to the
4373 function address. */
4376 frv_function_symbol_referenced_p (rtx x)
4382 if (GET_CODE (x) == SYMBOL_REF)
4383 return SYMBOL_REF_FUNCTION_P (x);
4385 length = GET_RTX_LENGTH (GET_CODE (x));
4386 format = GET_RTX_FORMAT (GET_CODE (x));
4388 for (j = 0; j < length; ++j)
4393 if (frv_function_symbol_referenced_p (XEXP (x, j)))
4399 if (XVEC (x, j) != 0)
4402 for (k = 0; k < XVECLEN (x, j); ++k)
4403 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
4409 /* Nothing to do. */
4417 /* Return true if operand is something that can be an input for a move
4421 move_source_operand (rtx op, enum machine_mode mode)
4426 switch (GET_CODE (op))
4433 return immediate_operand (op, mode);
4436 if (GET_MODE (op) != mode && mode != VOIDmode)
4439 subreg = SUBREG_REG (op);
4440 code = GET_CODE (subreg);
4442 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4443 reload_completed, FALSE, FALSE);
4445 return (code == REG);
4448 if (GET_MODE (op) != mode && mode != VOIDmode)
4454 return frv_legitimate_memory_operand (op, mode, FALSE);
4460 /* Return true if operand is something that can be an output for a conditional
4464 condexec_dest_operand (rtx op, enum machine_mode mode)
4469 switch (GET_CODE (op))
4475 if (GET_MODE (op) != mode && mode != VOIDmode)
4478 subreg = SUBREG_REG (op);
4479 code = GET_CODE (subreg);
4481 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4482 reload_completed, TRUE, FALSE);
4484 return (code == REG);
4487 if (GET_MODE (op) != mode && mode != VOIDmode)
4493 return frv_legitimate_memory_operand (op, mode, TRUE);
4499 /* Return true if operand is something that can be an input for a conditional
4503 condexec_source_operand (rtx op, enum machine_mode mode)
4508 switch (GET_CODE (op))
4518 if (GET_MODE (op) != mode && mode != VOIDmode)
4521 subreg = SUBREG_REG (op);
4522 code = GET_CODE (subreg);
4524 return frv_legitimate_address_p (mode, XEXP (subreg, 0),
4525 reload_completed, TRUE, FALSE);
4527 return (code == REG);
4530 if (GET_MODE (op) != mode && mode != VOIDmode)
4536 return frv_legitimate_memory_operand (op, mode, TRUE);
4542 /* Return true if operand is a register of any flavor or a 0 of the
4543 appropriate type. */
4546 reg_or_0_operand (rtx op, enum machine_mode mode)
4548 switch (GET_CODE (op))
4555 if (GET_MODE (op) != mode && mode != VOIDmode)
4558 return register_operand (op, mode);
4568 /* Return true if operand is the link register. */
4571 lr_operand (rtx op, enum machine_mode mode)
4573 if (GET_CODE (op) != REG)
4576 if (GET_MODE (op) != mode && mode != VOIDmode)
4579 if (REGNO (op) != LR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4585 /* Return true if operand is the uClinux PIC register. */
4588 fdpic_operand (rtx op, enum machine_mode mode)
4593 if (GET_CODE (op) != REG)
4596 if (GET_MODE (op) != mode && mode != VOIDmode)
4599 if (REGNO (op) != FDPIC_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
4606 got12_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4608 struct frv_unspec unspec;
4610 if (frv_const_unspec_p (op, &unspec))
4611 switch (unspec.reloc)
4614 case R_FRV_GOTOFF12:
4615 case R_FRV_FUNCDESC_GOT12:
4616 case R_FRV_FUNCDESC_GOTOFF12:
4623 /* Return true if OP is a valid const-unspec expression. */
4626 const_unspec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4628 struct frv_unspec unspec;
4630 return frv_const_unspec_p (op, &unspec);
4632 /* Return true if operand is a gpr register or a valid memory operation. */
4635 gpr_or_memory_operand (rtx op, enum machine_mode mode)
4637 return (integer_register_operand (op, mode)
4638 || frv_legitimate_memory_operand (op, mode, FALSE));
4641 /* Return true if operand is a fpr register or a valid memory operation. */
4644 fpr_or_memory_operand (rtx op, enum machine_mode mode)
4646 return (fpr_operand (op, mode)
4647 || frv_legitimate_memory_operand (op, mode, FALSE));
4650 /* Return true if operand is an icc register. */
4653 icc_operand (rtx op, enum machine_mode mode)
4657 if (GET_MODE (op) != mode && mode != VOIDmode)
4660 if (GET_CODE (op) != REG)
4664 return ICC_OR_PSEUDO_P (regno);
4667 /* Return true if operand is an fcc register. */
4670 fcc_operand (rtx op, enum machine_mode mode)
4674 if (GET_MODE (op) != mode && mode != VOIDmode)
4677 if (GET_CODE (op) != REG)
4681 return FCC_OR_PSEUDO_P (regno);
4684 /* Return true if operand is either an fcc or icc register. */
4687 cc_operand (rtx op, enum machine_mode mode)
4691 if (GET_MODE (op) != mode && mode != VOIDmode)
4694 if (GET_CODE (op) != REG)
4698 if (CC_OR_PSEUDO_P (regno))
4704 /* Return true if operand is an integer CCR register. */
4707 icr_operand (rtx op, enum machine_mode mode)
4711 if (GET_MODE (op) != mode && mode != VOIDmode)
4714 if (GET_CODE (op) != REG)
4718 return ICR_OR_PSEUDO_P (regno);
4721 /* Return true if operand is an fcc register. */
4724 fcr_operand (rtx op, enum machine_mode mode)
4728 if (GET_MODE (op) != mode && mode != VOIDmode)
4731 if (GET_CODE (op) != REG)
4735 return FCR_OR_PSEUDO_P (regno);
4738 /* Return true if operand is either an fcc or icc register. */
4741 cr_operand (rtx op, enum machine_mode mode)
4745 if (GET_MODE (op) != mode && mode != VOIDmode)
4748 if (GET_CODE (op) != REG)
4752 if (CR_OR_PSEUDO_P (regno))
4758 /* Return true if operand is a memory reference suitable for a call. */
4761 call_operand (rtx op, enum machine_mode mode)
4763 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4766 if (GET_CODE (op) == SYMBOL_REF)
4767 return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op);
4769 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4770 never occur anyway), but prevents reload from not handling the case
4771 properly of a call through a pointer on a function that calls
4772 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4773 return gpr_or_int12_operand (op, mode);
4776 /* Return true if operand is a memory reference suitable for a sibcall. */
4779 sibcall_operand (rtx op, enum machine_mode mode)
4781 if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
4784 /* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
4785 never occur anyway), but prevents reload from not handling the case
4786 properly of a call through a pointer on a function that calls
4787 vfork/setjmp, etc. due to the need to flush all of the registers to stack. */
4788 return gpr_or_int12_operand (op, mode);
4791 /* Return true if operator is a kind of relational operator. */
4794 relational_operator (rtx op, enum machine_mode mode)
4796 return (integer_relational_operator (op, mode)
4797 || float_relational_operator (op, mode));
4800 /* Return true if OP is a relational operator suitable for CCmode,
4801 CC_UNSmode or CC_NZmode. */
4804 integer_relational_operator (rtx op, enum machine_mode mode)
4806 if (mode != VOIDmode && mode != GET_MODE (op))
4809 /* The allowable relations depend on the mode of the ICC register. */
4810 switch (GET_CODE (op))
4819 return (GET_MODE (XEXP (op, 0)) == CC_NZmode
4820 || GET_MODE (XEXP (op, 0)) == CCmode);
4824 return GET_MODE (XEXP (op, 0)) == CCmode;
4830 return (GET_MODE (XEXP (op, 0)) == CC_NZmode
4831 || GET_MODE (XEXP (op, 0)) == CC_UNSmode);
4835 /* Return true if operator is a floating point relational operator. */
4838 float_relational_operator (rtx op, enum machine_mode mode)
4840 if (mode != VOIDmode && mode != GET_MODE (op))
4843 switch (GET_CODE (op))
4858 return GET_MODE (XEXP (op, 0)) == CC_FPmode;
4862 /* Return true if operator is EQ/NE of a conditional execution register. */
4865 ccr_eqne_operator (rtx op, enum machine_mode mode)
4867 enum machine_mode op_mode = GET_MODE (op);
4872 if (mode != VOIDmode && op_mode != mode)
4875 switch (GET_CODE (op))
4886 if (op1 != const0_rtx)
4890 if (GET_CODE (op0) != REG)
4893 regno = REGNO (op0);
4894 if (op_mode == CC_CCRmode && CR_OR_PSEUDO_P (regno))
4900 /* Return true if operator is a minimum or maximum operator (both signed and
4904 minmax_operator (rtx op, enum machine_mode mode)
4906 if (mode != VOIDmode && mode != GET_MODE (op))
4909 switch (GET_CODE (op))
4921 if (! integer_register_operand (XEXP (op, 0), mode))
4924 if (! gpr_or_int10_operand (XEXP (op, 1), mode))
4930 /* Return true if operator is an integer binary operator that can executed
4931 conditionally and takes 1 cycle. */
4934 condexec_si_binary_operator (rtx op, enum machine_mode mode)
4936 enum machine_mode op_mode = GET_MODE (op);
4938 if (mode != VOIDmode && op_mode != mode)
4941 switch (GET_CODE (op))
4958 /* Return true if operator is an integer binary operator that can be
4959 executed conditionally by a media instruction. */
4962 condexec_si_media_operator (rtx op, enum machine_mode mode)
4964 enum machine_mode op_mode = GET_MODE (op);
4966 if (mode != VOIDmode && op_mode != mode)
4969 switch (GET_CODE (op))
4981 /* Return true if operator is an integer division operator that can executed
4985 condexec_si_divide_operator (rtx op, enum machine_mode mode)
4987 enum machine_mode op_mode = GET_MODE (op);
4989 if (mode != VOIDmode && op_mode != mode)
4992 switch (GET_CODE (op))
5003 /* Return true if operator is an integer unary operator that can executed
5007 condexec_si_unary_operator (rtx op, enum machine_mode mode)
5009 enum machine_mode op_mode = GET_MODE (op);
5011 if (mode != VOIDmode && op_mode != mode)
5014 switch (GET_CODE (op))
5025 /* Return true if operator is a conversion-type expression that can be
5026 evaluated conditionally by floating-point instructions. */
5029 condexec_sf_conv_operator (rtx op, enum machine_mode mode)
5031 enum machine_mode op_mode = GET_MODE (op);
5033 if (mode != VOIDmode && op_mode != mode)
5036 switch (GET_CODE (op))
5047 /* Return true if operator is an addition or subtraction expression.
5048 Such expressions can be evaluated conditionally by floating-point
5052 condexec_sf_add_operator (rtx op, enum machine_mode mode)
5054 enum machine_mode op_mode = GET_MODE (op);
5056 if (mode != VOIDmode && op_mode != mode)
5059 switch (GET_CODE (op))
5070 /* Return true if the memory operand is one that can be conditionally
5074 condexec_memory_operand (rtx op, enum machine_mode mode)
5076 enum machine_mode op_mode = GET_MODE (op);
5079 if (mode != VOIDmode && op_mode != mode)
5094 if (GET_CODE (op) != MEM)
5097 addr = XEXP (op, 0);
5098 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
5101 /* Return true if OP is an integer binary operator that can be combined
5102 with a (set ... (compare:CC_NZ ...)) pattern. */
5105 intop_compare_operator (rtx op, enum machine_mode mode)
5107 if (mode != VOIDmode && GET_MODE (op) != mode)
5110 switch (GET_CODE (op))
5122 return GET_MODE (op) == SImode;
5126 /* Return 1 if operand is a valid ACC register number. */
5129 acc_operand (rtx op, enum machine_mode mode)
5131 return ((mode == VOIDmode || mode == GET_MODE (op))
5132 && REG_P (op) && ACC_P (REGNO (op))
5133 && ((REGNO (op) - ACC_FIRST) & ~ACC_MASK) == 0);
5136 /* Return 1 if operand is a valid even ACC register number. */
5139 even_acc_operand (rtx op, enum machine_mode mode)
5141 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 1) == 0;
5144 /* Return 1 if operand is zero or four. */
5147 quad_acc_operand (rtx op, enum machine_mode mode)
5149 return acc_operand (op, mode) && ((REGNO (op) - ACC_FIRST) & 3) == 0;
5152 /* Return 1 if operand is a valid ACCG register number. */
5155 accg_operand (rtx op, enum machine_mode mode)
5157 return ((mode == VOIDmode || mode == GET_MODE (op))
5158 && REG_P (op) && ACCG_P (REGNO (op))
5159 && ((REGNO (op) - ACCG_FIRST) & ~ACC_MASK) == 0);
5163 /* Return true if the bare return instruction can be used outside of the
5164 epilog code. For frv, we only do it if there was no stack allocation. */
5167 direct_return_p (void)
5171 if (!reload_completed)
5174 info = frv_stack_info ();
5175 return (info->total_size == 0);
5180 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
5185 if (frv_emit_movsi (dest, src))
5194 if (!reload_in_progress
5195 && !reload_completed
5196 && !register_operand (dest, mode)
5197 && !reg_or_0_operand (src, mode))
5198 src = copy_to_mode_reg (mode, src);
5205 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
5208 /* Emit code to handle a MOVSI, adding in the small data register or pic
5209 register if needed to load up addresses. Return TRUE if the appropriate
5210 instructions are emitted. */
5213 frv_emit_movsi (rtx dest, rtx src)
5215 int base_regno = -1;
5218 struct frv_unspec old_unspec;
5220 if (!reload_in_progress
5221 && !reload_completed
5222 && !register_operand (dest, SImode)
5223 && (!reg_or_0_operand (src, SImode)
5224 /* Virtual registers will almost always be replaced by an
5225 add instruction, so expose this to CSE by copying to
5226 an intermediate register. */
5227 || (GET_CODE (src) == REG
5228 && IN_RANGE_P (REGNO (src),
5229 FIRST_VIRTUAL_REGISTER,
5230 LAST_VIRTUAL_REGISTER))))
5232 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
5236 /* Explicitly add in the PIC or small data register if needed. */
5237 switch (GET_CODE (src))
5246 /* Using GPREL12, we use a single GOT entry for all symbols
5247 in read-only sections, but trade sequences such as:
5249 sethi #gothi(label), gr#
5250 setlo #gotlo(label), gr#
5255 ld @(gr15,#got12(_gp)), gr#
5256 sethi #gprelhi(label), gr##
5257 setlo #gprello(label), gr##
5260 We may often be able to share gr# for multiple
5261 computations of GPREL addresses, and we may often fold
5262 the final add into the pair of registers of a load or
5263 store instruction, so it's often profitable. Even when
5264 optimizing for size, we're trading a GOT entry for an
5265 additional instruction, which trades GOT space
5266 (read-write) for code size (read-only, shareable), as
5267 long as the symbol is not used in more than two different
5270 With -fpie/-fpic, we'd be trading a single load for a
5271 sequence of 4 instructions, because the offset of the
5272 label can't be assumed to be addressable with 12 bits, so
5273 we don't do this. */
5274 if (TARGET_GPREL_RO)
5275 unspec = R_FRV_GPREL12;
5277 unspec = R_FRV_GOT12;
5280 base_regno = PIC_REGNO;
5285 if (frv_const_unspec_p (src, &old_unspec))
5288 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
5291 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
5292 emit_move_insn (dest, src);
5297 sym = XEXP (sym, 0);
5298 if (GET_CODE (sym) == PLUS
5299 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
5300 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
5301 sym = XEXP (sym, 0);
5302 if (GET_CODE (sym) == SYMBOL_REF)
5304 else if (GET_CODE (sym) == LABEL_REF)
5307 goto handle_whatever;
5315 if (SYMBOL_REF_FUNCTION_P (sym))
5317 if (frv_local_funcdesc_p (sym))
5318 unspec = R_FRV_FUNCDESC_GOTOFF12;
5320 unspec = R_FRV_FUNCDESC_GOT12;
5324 if (CONSTANT_POOL_ADDRESS_P (sym))
5325 switch (GET_CODE (get_pool_constant (sym)))
5332 unspec = R_FRV_GOTOFF12;
5337 if (TARGET_GPREL_RO)
5338 unspec = R_FRV_GPREL12;
5340 unspec = R_FRV_GOT12;
5343 else if (SYMBOL_REF_LOCAL_P (sym)
5344 && !SYMBOL_REF_EXTERNAL_P (sym)
5345 && SYMBOL_REF_DECL (sym)
5346 && (!DECL_P (SYMBOL_REF_DECL (sym))
5347 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
5349 tree decl = SYMBOL_REF_DECL (sym);
5350 tree init = TREE_CODE (decl) == VAR_DECL
5351 ? DECL_INITIAL (decl)
5352 : TREE_CODE (decl) == CONSTRUCTOR
5355 bool named_section, readonly;
5357 if (init && init != error_mark_node)
5358 reloc = compute_reloc_for_constant (init);
5360 named_section = TREE_CODE (decl) == VAR_DECL
5361 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
5362 readonly = decl_readonly_section (decl, reloc);
5365 unspec = R_FRV_GOT12;
5367 unspec = R_FRV_GOTOFF12;
5368 else if (readonly && TARGET_GPREL_RO)
5369 unspec = R_FRV_GPREL12;
5371 unspec = R_FRV_GOT12;
5374 unspec = R_FRV_GOT12;
5378 else if (SYMBOL_REF_SMALL_P (sym))
5379 base_regno = SDA_BASE_REG;
5382 base_regno = PIC_REGNO;
5387 if (base_regno >= 0)
5389 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
5390 emit_insn (gen_symGOTOFF2reg (dest, src,
5391 gen_rtx_REG (Pmode, base_regno),
5392 GEN_INT (R_FRV_GPREL12)));
5394 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
5395 gen_rtx_REG (Pmode, base_regno),
5396 GEN_INT (R_FRV_GPREL12)));
5397 if (base_regno == PIC_REGNO)
5398 cfun->uses_pic_offset_table = TRUE;
5406 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
5407 new uses of it once reload has begun. */
5408 if (reload_in_progress || reload_completed)
5413 case R_FRV_GOTOFF12:
5414 if (!frv_small_data_reloc_p (sym, unspec))
5415 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5418 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5421 if (!frv_small_data_reloc_p (sym, unspec))
5422 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
5425 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5427 case R_FRV_FUNCDESC_GOTOFF12:
5429 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
5432 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5436 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
5439 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
5443 cfun->uses_pic_offset_table = TRUE;
5452 /* Return a string to output a single word move. */
5455 output_move_single (rtx operands[], rtx insn)
5457 rtx dest = operands[0];
5458 rtx src = operands[1];
5460 if (GET_CODE (dest) == REG)
5462 int dest_regno = REGNO (dest);
5463 enum machine_mode mode = GET_MODE (dest);
5465 if (GPR_P (dest_regno))
5467 if (GET_CODE (src) == REG)
5469 /* gpr <- some sort of register */
5470 int src_regno = REGNO (src);
5472 if (GPR_P (src_regno))
5473 return "mov %1, %0";
5475 else if (FPR_P (src_regno))
5476 return "movfg %1, %0";
5478 else if (SPR_P (src_regno))
5479 return "movsg %1, %0";
5482 else if (GET_CODE (src) == MEM)
5491 return "ldsb%I1%U1 %M1,%0";
5494 return "ldsh%I1%U1 %M1,%0";
5498 return "ld%I1%U1 %M1, %0";
5502 else if (GET_CODE (src) == CONST_INT
5503 || GET_CODE (src) == CONST_DOUBLE)
5505 /* gpr <- integer/floating constant */
5506 HOST_WIDE_INT value;
5508 if (GET_CODE (src) == CONST_INT)
5509 value = INTVAL (src);
5511 else if (mode == SFmode)
5516 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
5517 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5522 value = CONST_DOUBLE_LOW (src);
5524 if (IN_RANGE_P (value, -32768, 32767))
5525 return "setlos %1, %0";
5530 else if (GET_CODE (src) == SYMBOL_REF
5531 || GET_CODE (src) == LABEL_REF
5532 || GET_CODE (src) == CONST)
5538 else if (FPR_P (dest_regno))
5540 if (GET_CODE (src) == REG)
5542 /* fpr <- some sort of register */
5543 int src_regno = REGNO (src);
5545 if (GPR_P (src_regno))
5546 return "movgf %1, %0";
5548 else if (FPR_P (src_regno))
5550 if (TARGET_HARD_FLOAT)
5551 return "fmovs %1, %0";
5553 return "mor %1, %1, %0";
5557 else if (GET_CODE (src) == MEM)
5566 return "ldbf%I1%U1 %M1,%0";
5569 return "ldhf%I1%U1 %M1,%0";
5573 return "ldf%I1%U1 %M1, %0";
5577 else if (ZERO_P (src))
5578 return "movgf %., %0";
5581 else if (SPR_P (dest_regno))
5583 if (GET_CODE (src) == REG)
5585 /* spr <- some sort of register */
5586 int src_regno = REGNO (src);
5588 if (GPR_P (src_regno))
5589 return "movgs %1, %0";
5591 else if (ZERO_P (src))
5592 return "movgs %., %0";
5596 else if (GET_CODE (dest) == MEM)
5598 if (GET_CODE (src) == REG)
5600 int src_regno = REGNO (src);
5601 enum machine_mode mode = GET_MODE (dest);
5603 if (GPR_P (src_regno))
5611 return "stb%I0%U0 %1, %M0";
5614 return "sth%I0%U0 %1, %M0";
5618 return "st%I0%U0 %1, %M0";
5622 else if (FPR_P (src_regno))
5630 return "stbf%I0%U0 %1, %M0";
5633 return "sthf%I0%U0 %1, %M0";
5637 return "stf%I0%U0 %1, %M0";
5642 else if (ZERO_P (src))
5644 switch (GET_MODE (dest))
5650 return "stb%I0%U0 %., %M0";
5653 return "sth%I0%U0 %., %M0";
5657 return "st%I0%U0 %., %M0";
5662 fatal_insn ("Bad output_move_single operand", insn);
5667 /* Return a string to output a double word move. */
5670 output_move_double (rtx operands[], rtx insn)
5672 rtx dest = operands[0];
5673 rtx src = operands[1];
5674 enum machine_mode mode = GET_MODE (dest);
5676 if (GET_CODE (dest) == REG)
5678 int dest_regno = REGNO (dest);
5680 if (GPR_P (dest_regno))
5682 if (GET_CODE (src) == REG)
5684 /* gpr <- some sort of register */
5685 int src_regno = REGNO (src);
5687 if (GPR_P (src_regno))
5690 else if (FPR_P (src_regno))
5692 if (((dest_regno - GPR_FIRST) & 1) == 0
5693 && ((src_regno - FPR_FIRST) & 1) == 0)
5694 return "movfgd %1, %0";
5700 else if (GET_CODE (src) == MEM)
5703 if (dbl_memory_one_insn_operand (src, mode))
5704 return "ldd%I1%U1 %M1, %0";
5709 else if (GET_CODE (src) == CONST_INT
5710 || GET_CODE (src) == CONST_DOUBLE)
5714 else if (FPR_P (dest_regno))
5716 if (GET_CODE (src) == REG)
5718 /* fpr <- some sort of register */
5719 int src_regno = REGNO (src);
5721 if (GPR_P (src_regno))
5723 if (((dest_regno - FPR_FIRST) & 1) == 0
5724 && ((src_regno - GPR_FIRST) & 1) == 0)
5725 return "movgfd %1, %0";
5730 else if (FPR_P (src_regno))
5733 && ((dest_regno - FPR_FIRST) & 1) == 0
5734 && ((src_regno - FPR_FIRST) & 1) == 0)
5735 return "fmovd %1, %0";
5741 else if (GET_CODE (src) == MEM)
5744 if (dbl_memory_one_insn_operand (src, mode))
5745 return "lddf%I1%U1 %M1, %0";
5750 else if (ZERO_P (src))
5755 else if (GET_CODE (dest) == MEM)
5757 if (GET_CODE (src) == REG)
5759 int src_regno = REGNO (src);
5761 if (GPR_P (src_regno))
5763 if (((src_regno - GPR_FIRST) & 1) == 0
5764 && dbl_memory_one_insn_operand (dest, mode))
5765 return "std%I0%U0 %1, %M0";
5770 if (FPR_P (src_regno))
5772 if (((src_regno - FPR_FIRST) & 1) == 0
5773 && dbl_memory_one_insn_operand (dest, mode))
5774 return "stdf%I0%U0 %1, %M0";
5780 else if (ZERO_P (src))
5782 if (dbl_memory_one_insn_operand (dest, mode))
5783 return "std%I0%U0 %., %M0";
5789 fatal_insn ("Bad output_move_double operand", insn);
5794 /* Return a string to output a single word conditional move.
5795 Operand0 -- EQ/NE of ccr register and 0
5796 Operand1 -- CCR register
5797 Operand2 -- destination
5798 Operand3 -- source */
5801 output_condmove_single (rtx operands[], rtx insn)
5803 rtx dest = operands[2];
5804 rtx src = operands[3];
5806 if (GET_CODE (dest) == REG)
5808 int dest_regno = REGNO (dest);
5809 enum machine_mode mode = GET_MODE (dest);
5811 if (GPR_P (dest_regno))
5813 if (GET_CODE (src) == REG)
5815 /* gpr <- some sort of register */
5816 int src_regno = REGNO (src);
5818 if (GPR_P (src_regno))
5819 return "cmov %z3, %2, %1, %e0";
5821 else if (FPR_P (src_regno))
5822 return "cmovfg %3, %2, %1, %e0";
5825 else if (GET_CODE (src) == MEM)
5834 return "cldsb%I3%U3 %M3, %2, %1, %e0";
5837 return "cldsh%I3%U3 %M3, %2, %1, %e0";
5841 return "cld%I3%U3 %M3, %2, %1, %e0";
5845 else if (ZERO_P (src))
5846 return "cmov %., %2, %1, %e0";
5849 else if (FPR_P (dest_regno))
5851 if (GET_CODE (src) == REG)
5853 /* fpr <- some sort of register */
5854 int src_regno = REGNO (src);
5856 if (GPR_P (src_regno))
5857 return "cmovgf %3, %2, %1, %e0";
5859 else if (FPR_P (src_regno))
5861 if (TARGET_HARD_FLOAT)
5862 return "cfmovs %3,%2,%1,%e0";
5864 return "cmor %3, %3, %2, %1, %e0";
5868 else if (GET_CODE (src) == MEM)
5871 if (mode == SImode || mode == SFmode)
5872 return "cldf%I3%U3 %M3, %2, %1, %e0";
5875 else if (ZERO_P (src))
5876 return "cmovgf %., %2, %1, %e0";
5880 else if (GET_CODE (dest) == MEM)
5882 if (GET_CODE (src) == REG)
5884 int src_regno = REGNO (src);
5885 enum machine_mode mode = GET_MODE (dest);
5887 if (GPR_P (src_regno))
5895 return "cstb%I2%U2 %3, %M2, %1, %e0";
5898 return "csth%I2%U2 %3, %M2, %1, %e0";
5902 return "cst%I2%U2 %3, %M2, %1, %e0";
5906 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
5907 return "cstf%I2%U2 %3, %M2, %1, %e0";
5910 else if (ZERO_P (src))
5912 enum machine_mode mode = GET_MODE (dest);
5919 return "cstb%I2%U2 %., %M2, %1, %e0";
5922 return "csth%I2%U2 %., %M2, %1, %e0";
5926 return "cst%I2%U2 %., %M2, %1, %e0";
5931 fatal_insn ("Bad output_condmove_single operand", insn);
5936 /* Emit the appropriate code to do a comparison, returning the register the
5937 comparison was done it. */
5940 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
5942 enum machine_mode cc_mode;
5945 /* Floating point doesn't have comparison against a constant. */
5946 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
5947 op1 = force_reg (GET_MODE (op0), op1);
5949 /* Possibly disable using anything but a fixed register in order to work
5950 around cse moving comparisons past function calls. */
5951 cc_mode = SELECT_CC_MODE (test, op0, op1);
5952 cc_reg = ((TARGET_ALLOC_CC)
5953 ? gen_reg_rtx (cc_mode)
5954 : gen_rtx_REG (cc_mode,
5955 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
5957 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5958 gen_rtx_COMPARE (cc_mode, op0, op1)));
5964 /* Emit code for a conditional branch. The comparison operands were previously
5965 stored in frv_compare_op0 and frv_compare_op1.
5967 XXX: I originally wanted to add a clobber of a CCR register to use in
5968 conditional execution, but that confuses the rest of the compiler. */
5971 frv_emit_cond_branch (enum rtx_code test, rtx label)
5976 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
5977 enum machine_mode cc_mode = GET_MODE (cc_reg);
5979 /* Branches generate:
5981 (if_then_else (<test>, <cc_reg>, (const_int 0))
5982 (label_ref <branch_label>)
5984 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
5985 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
5986 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
5987 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
5992 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
5993 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
5996 frv_emit_scc (enum rtx_code test, rtx target)
6002 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6004 /* SCC instructions generate:
6005 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
6006 (clobber (<ccr_reg>))]) */
6007 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
6008 set = gen_rtx_SET (VOIDmode, target, test_rtx);
6010 cr_reg = ((TARGET_ALLOC_CC)
6011 ? gen_reg_rtx (CC_CCRmode)
6012 : gen_rtx_REG (CC_CCRmode,
6013 ((GET_MODE (cc_reg) == CC_FPmode)
6017 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6018 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
6023 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
6024 the separate insns. */
6027 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
6033 /* Set the appropriate CCR bit. */
6034 emit_insn (gen_rtx_SET (VOIDmode,
6036 gen_rtx_fmt_ee (GET_CODE (test),
6041 /* Move the value into the destination. */
6042 emit_move_insn (dest, GEN_INT (value));
6044 /* Move 0 into the destination if the test failed */
6045 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6046 gen_rtx_EQ (GET_MODE (cr_reg),
6049 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
6051 /* Finish up, return sequence. */
6058 /* Emit the code for a conditional move, return TRUE if we could do the
6062 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
6069 enum rtx_code test = GET_CODE (test_rtx);
6070 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
6071 enum machine_mode cc_mode = GET_MODE (cc_reg);
6073 /* Conditional move instructions generate:
6074 (parallel [(set <target>
6075 (if_then_else (<test> <cc_reg> (const_int 0))
6078 (clobber (<ccr_reg>))]) */
6080 /* Handle various cases of conditional move involving two constants. */
6081 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6083 HOST_WIDE_INT value1 = INTVAL (src1);
6084 HOST_WIDE_INT value2 = INTVAL (src2);
6086 /* Having 0 as one of the constants can be done by loading the other
6087 constant, and optionally moving in gr0. */
6088 if (value1 == 0 || value2 == 0)
6091 /* If the first value is within an addi range and also the difference
6092 between the two fits in an addi's range, load up the difference, then
6093 conditionally move in 0, and then unconditionally add the first
6095 else if (IN_RANGE_P (value1, -2048, 2047)
6096 && IN_RANGE_P (value2 - value1, -2048, 2047))
6099 /* If neither condition holds, just force the constant into a
6103 src1 = force_reg (GET_MODE (dest), src1);
6104 src2 = force_reg (GET_MODE (dest), src2);
6108 /* If one value is a register, insure the other value is either 0 or a
6112 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
6113 src1 = force_reg (GET_MODE (dest), src1);
6115 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6116 src2 = force_reg (GET_MODE (dest), src2);
6119 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
6120 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
6122 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
6124 cr_reg = ((TARGET_ALLOC_CC)
6125 ? gen_reg_rtx (CC_CCRmode)
6126 : gen_rtx_REG (CC_CCRmode,
6127 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
6129 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
6130 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
6135 /* Split a conditional move into constituent parts, returning a SEQUENCE
6136 containing all of the insns. */
6139 frv_split_cond_move (rtx operands[])
6141 rtx dest = operands[0];
6142 rtx test = operands[1];
6143 rtx cc_reg = operands[2];
6144 rtx src1 = operands[3];
6145 rtx src2 = operands[4];
6146 rtx cr_reg = operands[5];
6148 enum machine_mode cr_mode = GET_MODE (cr_reg);
6152 /* Set the appropriate CCR bit. */
6153 emit_insn (gen_rtx_SET (VOIDmode,
6155 gen_rtx_fmt_ee (GET_CODE (test),
6160 /* Handle various cases of conditional move involving two constants. */
6161 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
6163 HOST_WIDE_INT value1 = INTVAL (src1);
6164 HOST_WIDE_INT value2 = INTVAL (src2);
6166 /* Having 0 as one of the constants can be done by loading the other
6167 constant, and optionally moving in gr0. */
6170 emit_move_insn (dest, src2);
6171 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6172 gen_rtx_NE (cr_mode, cr_reg,
6174 gen_rtx_SET (VOIDmode, dest, src1)));
6177 else if (value2 == 0)
6179 emit_move_insn (dest, src1);
6180 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6181 gen_rtx_EQ (cr_mode, cr_reg,
6183 gen_rtx_SET (VOIDmode, dest, src2)));
6186 /* If the first value is within an addi range and also the difference
6187 between the two fits in an addi's range, load up the difference, then
6188 conditionally move in 0, and then unconditionally add the first
6190 else if (IN_RANGE_P (value1, -2048, 2047)
6191 && IN_RANGE_P (value2 - value1, -2048, 2047))
6193 rtx dest_si = ((GET_MODE (dest) == SImode)
6195 : gen_rtx_SUBREG (SImode, dest, 0));
6197 emit_move_insn (dest_si, GEN_INT (value2 - value1));
6198 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6199 gen_rtx_NE (cr_mode, cr_reg,
6201 gen_rtx_SET (VOIDmode, dest_si,
6203 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
6211 /* Emit the conditional move for the test being true if needed. */
6212 if (! rtx_equal_p (dest, src1))
6213 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6214 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6215 gen_rtx_SET (VOIDmode, dest, src1)));
6217 /* Emit the conditional move for the test being false if needed. */
6218 if (! rtx_equal_p (dest, src2))
6219 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6220 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6221 gen_rtx_SET (VOIDmode, dest, src2)));
6224 /* Finish up, return sequence. */
6231 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
6232 memory location that is not known to be dword-aligned. */
6234 frv_split_double_load (rtx dest, rtx source)
6236 int regno = REGNO (dest);
6237 rtx dest1 = gen_highpart (SImode, dest);
6238 rtx dest2 = gen_lowpart (SImode, dest);
6239 rtx address = XEXP (source, 0);
6241 /* If the address is pre-modified, load the lower-numbered register
6242 first, then load the other register using an integer offset from
6243 the modified base register. This order should always be safe,
6244 since the pre-modification cannot affect the same registers as the
6247 The situation for other loads is more complicated. Loading one
6248 of the registers could affect the value of ADDRESS, so we must
6249 be careful which order we do them in. */
6250 if (GET_CODE (address) == PRE_MODIFY
6251 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
6253 /* It is safe to load the lower-numbered register first. */
6254 emit_move_insn (dest1, change_address (source, SImode, NULL));
6255 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6259 /* ADDRESS is not pre-modified and the address depends on the
6260 lower-numbered register. Load the higher-numbered register
6262 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
6263 emit_move_insn (dest1, change_address (source, SImode, NULL));
6267 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
6268 and SOURCE is either a double register or the constant zero. */
6270 frv_split_double_store (rtx dest, rtx source)
6272 rtx dest1 = change_address (dest, SImode, NULL);
6273 rtx dest2 = frv_index_memory (dest, SImode, 1);
6274 if (ZERO_P (source))
6276 emit_move_insn (dest1, CONST0_RTX (SImode));
6277 emit_move_insn (dest2, CONST0_RTX (SImode));
6281 emit_move_insn (dest1, gen_highpart (SImode, source));
6282 emit_move_insn (dest2, gen_lowpart (SImode, source));
6287 /* Split a min/max operation returning a SEQUENCE containing all of the
6291 frv_split_minmax (rtx operands[])
6293 rtx dest = operands[0];
6294 rtx minmax = operands[1];
6295 rtx src1 = operands[2];
6296 rtx src2 = operands[3];
6297 rtx cc_reg = operands[4];
6298 rtx cr_reg = operands[5];
6300 enum rtx_code test_code;
6301 enum machine_mode cr_mode = GET_MODE (cr_reg);
6305 /* Figure out which test to use. */
6306 switch (GET_CODE (minmax))
6311 case SMIN: test_code = LT; break;
6312 case SMAX: test_code = GT; break;
6313 case UMIN: test_code = LTU; break;
6314 case UMAX: test_code = GTU; break;
6317 /* Issue the compare instruction. */
6318 emit_insn (gen_rtx_SET (VOIDmode,
6320 gen_rtx_COMPARE (GET_MODE (cc_reg),
6323 /* Set the appropriate CCR bit. */
6324 emit_insn (gen_rtx_SET (VOIDmode,
6326 gen_rtx_fmt_ee (test_code,
6331 /* If are taking the min/max of a nonzero constant, load that first, and
6332 then do a conditional move of the other value. */
6333 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
6335 if (rtx_equal_p (dest, src1))
6338 emit_move_insn (dest, src2);
6339 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6340 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6341 gen_rtx_SET (VOIDmode, dest, src1)));
6344 /* Otherwise, do each half of the move. */
6347 /* Emit the conditional move for the test being true if needed. */
6348 if (! rtx_equal_p (dest, src1))
6349 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6350 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
6351 gen_rtx_SET (VOIDmode, dest, src1)));
6353 /* Emit the conditional move for the test being false if needed. */
6354 if (! rtx_equal_p (dest, src2))
6355 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6356 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
6357 gen_rtx_SET (VOIDmode, dest, src2)));
6360 /* Finish up, return sequence. */
6367 /* Split an integer abs operation returning a SEQUENCE containing all of the
6371 frv_split_abs (rtx operands[])
6373 rtx dest = operands[0];
6374 rtx src = operands[1];
6375 rtx cc_reg = operands[2];
6376 rtx cr_reg = operands[3];
6381 /* Issue the compare < 0 instruction. */
6382 emit_insn (gen_rtx_SET (VOIDmode,
6384 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
6386 /* Set the appropriate CCR bit. */
6387 emit_insn (gen_rtx_SET (VOIDmode,
6389 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
6391 /* Emit the conditional negate if the value is negative. */
6392 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6393 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
6394 gen_negsi2 (dest, src)));
6396 /* Emit the conditional move for the test being false if needed. */
6397 if (! rtx_equal_p (dest, src))
6398 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
6399 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
6400 gen_rtx_SET (VOIDmode, dest, src)));
6402 /* Finish up, return sequence. */
6409 /* An internal function called by for_each_rtx to clear in a hard_reg set each
6410 register used in an insn. */
6413 frv_clear_registers_used (rtx *ptr, void *data)
6415 if (GET_CODE (*ptr) == REG)
6417 int regno = REGNO (*ptr);
6418 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
6420 if (regno < FIRST_PSEUDO_REGISTER)
6422 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
6424 while (regno < reg_max)
6426 CLEAR_HARD_REG_BIT (*p_regs, regno);
6436 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
6438 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
6439 initialize the static storage. */
6441 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6443 frv_ifcvt.added_insns_list = NULL_RTX;
6444 frv_ifcvt.cur_scratch_regs = 0;
6445 frv_ifcvt.num_nested_cond_exec = 0;
6446 frv_ifcvt.cr_reg = NULL_RTX;
6447 frv_ifcvt.nested_cc_reg = NULL_RTX;
6448 frv_ifcvt.extra_int_cr = NULL_RTX;
6449 frv_ifcvt.extra_fp_cr = NULL_RTX;
6450 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6454 /* Internal function to add a potential insn to the list of insns to be inserted
6455 if the conditional execution conversion is successful. */
6458 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
6460 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
6462 link->jump = before_p; /* Mark to add this before or after insn. */
6463 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
6464 frv_ifcvt.added_insns_list);
6466 if (TARGET_DEBUG_COND_EXEC)
6469 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
6470 (before_p) ? "before" : "after",
6471 (int)INSN_UID (insn));
6473 debug_rtx (pattern);
6478 /* A C expression to modify the code described by the conditional if
6479 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
6480 FALSE_EXPR for converting if-then and if-then-else code to conditional
6481 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
6482 tests cannot be converted. */
6485 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
6487 basic_block test_bb = ce_info->test_bb; /* test basic block */
6488 basic_block then_bb = ce_info->then_bb; /* THEN */
6489 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
6490 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
6491 rtx true_expr = *p_true;
6495 enum machine_mode mode = GET_MODE (true_expr);
6499 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
6501 rtx sub_cond_exec_reg;
6503 enum rtx_code code_true;
6504 enum rtx_code code_false;
6505 enum reg_class cc_class;
6506 enum reg_class cr_class;
6509 reg_set_iterator rsi;
6511 /* Make sure we are only dealing with hard registers. Also honor the
6512 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
6514 if (!reload_completed || TARGET_NO_COND_EXEC
6515 || (TARGET_NO_NESTED_CE && ce_info->pass > 1))
6518 /* Figure out which registers we can allocate for our own purposes. Only
6519 consider registers that are not preserved across function calls and are
6520 not fixed. However, allow the ICC/ICR temporary registers to be allocated
6521 if we did not need to use them in reloading other registers. */
6522 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
6523 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
6524 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
6525 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
6526 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
6528 /* If this is a nested IF, we need to discover whether the CC registers that
6529 are set/used inside of the block are used anywhere else. If not, we can
6530 change them to be the CC register that is paired with the CR register that
6531 controls the outermost IF block. */
6532 if (ce_info->pass > 1)
6534 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
6535 for (j = CC_FIRST; j <= CC_LAST; j++)
6536 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6538 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
6541 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
6544 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
6547 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
6551 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
6552 frv_ifcvt.scratch_regs[j] = NULL_RTX;
6554 frv_ifcvt.added_insns_list = NULL_RTX;
6555 frv_ifcvt.cur_scratch_regs = 0;
6557 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
6558 * sizeof (basic_block));
6564 /* Remove anything live at the beginning of the join block from being
6565 available for allocation. */
6566 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno, rsi)
6568 if (regno < FIRST_PSEUDO_REGISTER)
6569 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6573 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
6575 if (ce_info->num_multiple_test_blocks)
6577 basic_block multiple_test_bb = ce_info->last_test_bb;
6579 while (multiple_test_bb != test_bb)
6581 bb[num_bb++] = multiple_test_bb;
6582 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
6586 /* Add in the THEN and ELSE blocks to be scanned. */
6587 bb[num_bb++] = then_bb;
6589 bb[num_bb++] = else_bb;
6591 sub_cond_exec_reg = NULL_RTX;
6592 frv_ifcvt.num_nested_cond_exec = 0;
6594 /* Scan all of the blocks for registers that must not be allocated. */
6595 for (j = 0; j < num_bb; j++)
6597 rtx last_insn = BB_END (bb[j]);
6598 rtx insn = BB_HEAD (bb[j]);
6602 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
6603 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
6605 (int) INSN_UID (BB_HEAD (bb[j])),
6606 (int) INSN_UID (BB_END (bb[j])));
6608 /* Anything live at the beginning of the block is obviously unavailable
6610 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno, rsi)
6612 if (regno < FIRST_PSEUDO_REGISTER)
6613 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
6616 /* Loop through the insns in the block. */
6619 /* Mark any new registers that are created as being unavailable for
6620 allocation. Also see if the CC register used in nested IFs can be
6626 int skip_nested_if = FALSE;
6628 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6629 (void *)&tmp_reg->regs);
6631 pattern = PATTERN (insn);
6632 if (GET_CODE (pattern) == COND_EXEC)
6634 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
6636 if (reg != sub_cond_exec_reg)
6638 sub_cond_exec_reg = reg;
6639 frv_ifcvt.num_nested_cond_exec++;
6643 set = single_set_pattern (pattern);
6646 rtx dest = SET_DEST (set);
6647 rtx src = SET_SRC (set);
6649 if (GET_CODE (dest) == REG)
6651 int regno = REGNO (dest);
6652 enum rtx_code src_code = GET_CODE (src);
6654 if (CC_P (regno) && src_code == COMPARE)
6655 skip_nested_if = TRUE;
6657 else if (CR_P (regno)
6658 && (src_code == IF_THEN_ELSE
6659 || COMPARISON_P (src)))
6660 skip_nested_if = TRUE;
6664 if (! skip_nested_if)
6665 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
6666 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
6669 if (insn == last_insn)
6672 insn = NEXT_INSN (insn);
6676 /* If this is a nested if, rewrite the CC registers that are available to
6677 include the ones that can be rewritten, to increase the chance of being
6678 able to allocate a paired CC/CR register combination. */
6679 if (ce_info->pass > 1)
6681 for (j = CC_FIRST; j <= CC_LAST; j++)
6682 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
6683 SET_HARD_REG_BIT (tmp_reg->regs, j);
6685 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
6691 fprintf (dump_file, "Available GPRs: ");
6693 for (j = GPR_FIRST; j <= GPR_LAST; j++)
6694 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6696 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6697 if (++num_gprs > GPR_TEMP_NUM+2)
6701 fprintf (dump_file, "%s\nAvailable CRs: ",
6702 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
6704 for (j = CR_FIRST; j <= CR_LAST; j++)
6705 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6706 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6708 fputs ("\n", dump_file);
6710 if (ce_info->pass > 1)
6712 fprintf (dump_file, "Modifiable CCs: ");
6713 for (j = CC_FIRST; j <= CC_LAST; j++)
6714 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
6715 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
6717 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
6718 frv_ifcvt.num_nested_cond_exec);
6722 /* Allocate the appropriate temporary condition code register. Try to
6723 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
6724 that conditional cmp's can be done. */
6725 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
6727 cr_class = ICR_REGS;
6728 cc_class = ICC_REGS;
6729 cc_first = ICC_FIRST;
6732 else if (mode == CC_FPmode)
6734 cr_class = FCR_REGS;
6735 cc_class = FCC_REGS;
6736 cc_first = FCC_FIRST;
6741 cc_first = cc_last = 0;
6742 cr_class = cc_class = NO_REGS;
6745 cc = XEXP (true_expr, 0);
6746 nested_cc = cr = NULL_RTX;
6747 if (cc_class != NO_REGS)
6749 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
6750 so we can execute a csubcc/caddcc/cfcmps instruction. */
6753 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
6755 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
6757 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
6758 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
6760 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
6761 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
6764 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
6765 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
6775 fprintf (dump_file, "Could not allocate a CR temporary register\n");
6782 "Will use %s for conditional execution, %s for nested comparisons\n",
6783 reg_names[ REGNO (cr)],
6784 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
6786 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
6787 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
6788 bit being true. We don't do this for floating point, because of NaNs. */
6789 code = GET_CODE (true_expr);
6790 if (GET_MODE (cc) != CC_FPmode)
6792 code = reverse_condition (code);
6802 check_insn = gen_rtx_SET (VOIDmode, cr,
6803 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
6805 /* Record the check insn to be inserted later. */
6806 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
6808 /* Update the tests. */
6809 frv_ifcvt.cr_reg = cr;
6810 frv_ifcvt.nested_cc_reg = nested_cc;
6811 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
6812 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
6815 /* Fail, don't do this conditional execution. */
6818 *p_false = NULL_RTX;
6820 fprintf (dump_file, "Disabling this conditional execution.\n");
6826 /* A C expression to modify the code described by the conditional if
6827 information CE_INFO, for the basic block BB, possibly updating the tests in
6828 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
6829 if-then-else code to conditional instructions. Set either TRUE_EXPR or
6830 FALSE_EXPR to a null pointer if the tests cannot be converted. */
6832 /* p_true and p_false are given expressions of the form:
6834 (and (eq:CC_CCR (reg:CC_CCR)
6840 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
6845 rtx old_true = XEXP (*p_true, 0);
6846 rtx old_false = XEXP (*p_false, 0);
6847 rtx true_expr = XEXP (*p_true, 1);
6848 rtx false_expr = XEXP (*p_false, 1);
6851 rtx cr = XEXP (old_true, 0);
6853 rtx new_cr = NULL_RTX;
6854 rtx *p_new_cr = (rtx *)0;
6858 enum reg_class cr_class;
6859 enum machine_mode mode = GET_MODE (true_expr);
6860 rtx (*logical_func)(rtx, rtx, rtx);
6862 if (TARGET_DEBUG_COND_EXEC)
6865 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
6866 ce_info->and_and_p ? "&&" : "||");
6868 debug_rtx (*p_true);
6870 fputs ("\nfalse insn:\n", stderr);
6871 debug_rtx (*p_false);
6874 if (TARGET_NO_MULTI_CE)
6877 if (GET_CODE (cr) != REG)
6880 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
6882 cr_class = ICR_REGS;
6883 p_new_cr = &frv_ifcvt.extra_int_cr;
6885 else if (mode == CC_FPmode)
6887 cr_class = FCR_REGS;
6888 p_new_cr = &frv_ifcvt.extra_fp_cr;
6893 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
6894 more &&/|| tests. */
6898 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
6899 CC_CCRmode, TRUE, TRUE);
6904 if (ce_info->and_and_p)
6906 old_test = old_false;
6907 test_expr = true_expr;
6908 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
6909 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6910 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6914 old_test = old_false;
6915 test_expr = false_expr;
6916 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
6917 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
6918 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
6921 /* First add the andcr/andncr/orcr/orncr, which will be added after the
6922 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
6924 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
6926 /* Now add the conditional check insn. */
6927 cc = XEXP (test_expr, 0);
6928 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
6929 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
6931 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
6933 /* Add the new check insn to the list of check insns that need to be
6935 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
6937 if (TARGET_DEBUG_COND_EXEC)
6939 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
6942 debug_rtx (*p_true);
6944 fputs ("\nfalse insn:\n", stderr);
6945 debug_rtx (*p_false);
6951 *p_true = *p_false = NULL_RTX;
6953 /* If we allocated a CR register, release it. */
6956 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
6957 *p_new_cr = NULL_RTX;
6960 if (TARGET_DEBUG_COND_EXEC)
6961 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
6967 /* Return a register which will be loaded with a value if an IF block is
6968 converted to conditional execution. This is used to rewrite instructions
6969 that use constants to ones that just use registers. */
6972 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
6974 int num_alloc = frv_ifcvt.cur_scratch_regs;
6978 /* We know gr0 == 0, so replace any errant uses. */
6979 if (value == const0_rtx)
6980 return gen_rtx_REG (SImode, GPR_FIRST);
6982 /* First search all registers currently loaded to see if we have an
6983 applicable constant. */
6984 if (CONSTANT_P (value)
6985 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
6987 for (i = 0; i < num_alloc; i++)
6989 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
6990 return SET_DEST (frv_ifcvt.scratch_regs[i]);
6994 /* Have we exhausted the number of registers available? */
6995 if (num_alloc >= GPR_TEMP_NUM)
6998 fprintf (dump_file, "Too many temporary registers allocated\n");
7003 /* Allocate the new register. */
7004 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
7008 fputs ("Could not find a scratch register\n", dump_file);
7013 frv_ifcvt.cur_scratch_regs++;
7014 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
7018 if (GET_CODE (value) == CONST_INT)
7019 fprintf (dump_file, "Register %s will hold %ld\n",
7020 reg_names[ REGNO (reg)], (long)INTVAL (value));
7022 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
7023 fprintf (dump_file, "Register %s will hold LR\n",
7024 reg_names[ REGNO (reg)]);
7027 fprintf (dump_file, "Register %s will hold a saved value\n",
7028 reg_names[ REGNO (reg)]);
7035 /* Update a MEM used in conditional code that might contain an offset to put
7036 the offset into a scratch register, so that the conditional load/store
7037 operations can be used. This function returns the original pointer if the
7038 MEM is valid to use in conditional code, NULL if we can't load up the offset
7039 into a temporary register, or the new MEM if we were successful. */
7042 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
7044 rtx addr = XEXP (mem, 0);
7046 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
7048 if (GET_CODE (addr) == PLUS)
7050 rtx addr_op0 = XEXP (addr, 0);
7051 rtx addr_op1 = XEXP (addr, 1);
7053 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
7055 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
7059 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
7066 else if (CONSTANT_P (addr))
7067 addr = frv_ifcvt_load_value (addr, insn);
7072 if (addr == NULL_RTX)
7075 else if (XEXP (mem, 0) != addr)
7076 return change_address (mem, mode, addr);
7083 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
7084 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
7087 single_set_pattern (rtx pattern)
7092 if (GET_CODE (pattern) == COND_EXEC)
7093 pattern = COND_EXEC_CODE (pattern);
7095 if (GET_CODE (pattern) == SET)
7098 else if (GET_CODE (pattern) == PARALLEL)
7100 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
7102 rtx sub = XVECEXP (pattern, 0, i);
7104 switch (GET_CODE (sub))
7128 /* A C expression to modify the code described by the conditional if
7129 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
7130 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
7131 insn cannot be converted to be executed conditionally. */
7134 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
7138 rtx orig_ce_pattern = pattern;
7144 if (GET_CODE (pattern) != COND_EXEC)
7147 test = COND_EXEC_TEST (pattern);
7148 if (GET_CODE (test) == AND)
7150 rtx cr = frv_ifcvt.cr_reg;
7153 op0 = XEXP (test, 0);
7154 if (! rtx_equal_p (cr, XEXP (op0, 0)))
7157 op1 = XEXP (test, 1);
7158 test_reg = XEXP (op1, 0);
7159 if (GET_CODE (test_reg) != REG)
7162 /* Is this the first nested if block in this sequence? If so, generate
7163 an andcr or andncr. */
7164 if (! frv_ifcvt.last_nested_if_cr)
7168 frv_ifcvt.last_nested_if_cr = test_reg;
7169 if (GET_CODE (op0) == NE)
7170 and_op = gen_andcr (test_reg, cr, test_reg);
7172 and_op = gen_andncr (test_reg, cr, test_reg);
7174 frv_ifcvt_add_insn (and_op, insn, TRUE);
7177 /* If this isn't the first statement in the nested if sequence, see if we
7178 are dealing with the same register. */
7179 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
7182 COND_EXEC_TEST (pattern) = test = op1;
7185 /* If this isn't a nested if, reset state variables. */
7188 frv_ifcvt.last_nested_if_cr = NULL_RTX;
7191 set = single_set_pattern (pattern);
7194 rtx dest = SET_DEST (set);
7195 rtx src = SET_SRC (set);
7196 enum machine_mode mode = GET_MODE (dest);
7198 /* Check for normal binary operators. */
7199 if (mode == SImode && ARITHMETIC_P (src))
7201 op0 = XEXP (src, 0);
7202 op1 = XEXP (src, 1);
7204 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
7206 op1 = frv_ifcvt_load_value (op1, insn);
7208 COND_EXEC_CODE (pattern)
7209 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
7217 /* For multiply by a constant, we need to handle the sign extending
7218 correctly. Add a USE of the value after the multiply to prevent flow
7219 from cratering because only one register out of the two were used. */
7220 else if (mode == DImode && GET_CODE (src) == MULT)
7222 op0 = XEXP (src, 0);
7223 op1 = XEXP (src, 1);
7224 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
7226 op1 = frv_ifcvt_load_value (op1, insn);
7229 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
7230 COND_EXEC_CODE (pattern)
7231 = gen_rtx_SET (VOIDmode, dest,
7232 gen_rtx_MULT (DImode, op0, op1));
7238 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
7241 /* If we are just loading a constant created for a nested conditional
7242 execution statement, just load the constant without any conditional
7243 execution, since we know that the constant will not interfere with any
7245 else if (frv_ifcvt.scratch_insns_bitmap
7246 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
7248 && REG_P (SET_DEST (set))
7249 /* We must not unconditionally set a scratch reg chosen
7250 for a nested if-converted block if its incoming
7251 value from the TEST block (or the result of the THEN
7252 branch) could/should propagate to the JOIN block.
7253 It suffices to test whether the register is live at
7254 the JOIN point: if it's live there, we can infer
7255 that we set it in the former JOIN block of the
7256 nested if-converted block (otherwise it wouldn't
7257 have been available as a scratch register), and it
7258 is either propagated through or set in the other
7259 conditional block. It's probably not worth trying
7260 to catch the latter case, and it could actually
7261 limit scheduling of the combined block quite
7264 && ! (REGNO_REG_SET_P
7265 (ce_info->join_bb->global_live_at_start,
7266 REGNO (SET_DEST (set))))
7267 /* Similarly, we must not unconditionally set a reg
7268 used as scratch in the THEN branch if the same reg
7269 is live in the ELSE branch. */
7270 && (! ce_info->else_bb
7271 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
7272 || ! (REGNO_REG_SET_P
7273 (ce_info->else_bb->global_live_at_start,
7274 REGNO (SET_DEST (set))))))
7277 else if (mode == QImode || mode == HImode || mode == SImode
7280 int changed_p = FALSE;
7282 /* Check for just loading up a constant */
7283 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
7285 src = frv_ifcvt_load_value (src, insn);
7292 /* See if we need to fix up stores */
7293 if (GET_CODE (dest) == MEM)
7295 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
7300 else if (new_mem != dest)
7307 /* See if we need to fix up loads */
7308 if (GET_CODE (src) == MEM)
7310 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
7315 else if (new_mem != src)
7322 /* If either src or destination changed, redo SET. */
7324 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
7327 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
7328 rewriting the CC register to be the same as the paired CC/CR register
7330 else if (mode == CC_CCRmode && COMPARISON_P (src))
7332 int regno = REGNO (XEXP (src, 0));
7335 if (ce_info->pass > 1
7336 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
7337 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
7339 src = gen_rtx_fmt_ee (GET_CODE (src),
7341 frv_ifcvt.nested_cc_reg,
7345 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
7346 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
7349 /* Remap a nested compare instruction to use the paired CC/CR reg. */
7350 else if (ce_info->pass > 1
7351 && GET_CODE (dest) == REG
7352 && CC_P (REGNO (dest))
7353 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
7354 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
7356 && GET_CODE (src) == COMPARE)
7358 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
7359 COND_EXEC_CODE (pattern)
7360 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
7364 if (TARGET_DEBUG_COND_EXEC)
7366 rtx orig_pattern = PATTERN (insn);
7368 PATTERN (insn) = pattern;
7370 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
7374 PATTERN (insn) = orig_pattern;
7380 if (TARGET_DEBUG_COND_EXEC)
7382 rtx orig_pattern = PATTERN (insn);
7384 PATTERN (insn) = orig_ce_pattern;
7386 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
7390 PATTERN (insn) = orig_pattern;
7397 /* A C expression to perform any final machine dependent modifications in
7398 converting code to conditional execution in the code described by the
7399 conditional if information CE_INFO. */
7402 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7406 rtx p = frv_ifcvt.added_insns_list;
7409 /* Loop inserting the check insns. The last check insn is the first test,
7410 and is the appropriate place to insert constants. */
7416 rtx check_and_insert_insns = XEXP (p, 0);
7419 check_insn = XEXP (check_and_insert_insns, 0);
7420 existing_insn = XEXP (check_and_insert_insns, 1);
7423 /* The jump bit is used to say that the new insn is to be inserted BEFORE
7424 the existing insn, otherwise it is to be inserted AFTER. */
7425 if (check_and_insert_insns->jump)
7427 emit_insn_before (check_insn, existing_insn);
7428 check_and_insert_insns->jump = 0;
7431 emit_insn_after (check_insn, existing_insn);
7433 free_EXPR_LIST_node (check_and_insert_insns);
7434 free_EXPR_LIST_node (old_p);
7436 while (p != NULL_RTX);
7438 /* Load up any constants needed into temp gprs */
7439 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7441 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
7442 if (! frv_ifcvt.scratch_insns_bitmap)
7443 frv_ifcvt.scratch_insns_bitmap = BITMAP_XMALLOC ();
7444 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
7445 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7448 frv_ifcvt.added_insns_list = NULL_RTX;
7449 frv_ifcvt.cur_scratch_regs = 0;
7453 /* A C expression to cancel any machine dependent modifications in converting
7454 code to conditional execution in the code described by the conditional if
7455 information CE_INFO. */
7458 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
7461 rtx p = frv_ifcvt.added_insns_list;
7463 /* Loop freeing up the EXPR_LIST's allocated. */
7464 while (p != NULL_RTX)
7466 rtx check_and_jump = XEXP (p, 0);
7470 free_EXPR_LIST_node (check_and_jump);
7471 free_EXPR_LIST_node (old_p);
7474 /* Release any temporary gprs allocated. */
7475 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
7476 frv_ifcvt.scratch_regs[i] = NULL_RTX;
7478 frv_ifcvt.added_insns_list = NULL_RTX;
7479 frv_ifcvt.cur_scratch_regs = 0;
7483 /* A C expression for the size in bytes of the trampoline, as an integer.
7487 setlo #0, <static_chain>
7489 sethi #0, <static_chain>
7490 jmpl @(gr0,<jmp_reg>) */
7493 frv_trampoline_size (void)
7496 /* Allocate room for the function descriptor and the lddi
7499 return 5 /* instructions */ * 4 /* instruction size. */;
7503 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
7504 RTX for the address of the trampoline; FNADDR is an RTX for the address of
7505 the nested function; STATIC_CHAIN is an RTX for the static chain value that
7506 should be passed to the function when it is called.
7511 setlo #0, <static_chain>
7513 sethi #0, <static_chain>
7514 jmpl @(gr0,<jmp_reg>) */
7517 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
7519 rtx sc_reg = force_reg (Pmode, static_chain);
7521 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
7524 GEN_INT (frv_trampoline_size ()), SImode,
7530 /* Many machines have some registers that cannot be copied directly to or from
7531 memory or even from other types of registers. An example is the `MQ'
7532 register, which on most machines, can only be copied to or from general
7533 registers, but not memory. Some machines allow copying all registers to and
7534 from memory, but require a scratch register for stores to some memory
7535 locations (e.g., those with symbolic address on the RT, and those with
7536 certain symbolic address on the SPARC when compiling PIC). In some cases,
7537 both an intermediate and a scratch register are required.
7539 You should define these macros to indicate to the reload phase that it may
7540 need to allocate at least one register for a reload in addition to the
7541 register to contain the data. Specifically, if copying X to a register
7542 CLASS in MODE requires an intermediate register, you should define
7543 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
7544 whose registers can be used as intermediate registers or scratch registers.
7546 If copying a register CLASS in MODE to X requires an intermediate or scratch
7547 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
7548 largest register class required. If the requirements for input and output
7549 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
7550 instead of defining both macros identically.
7552 The values returned by these macros are often `GENERAL_REGS'. Return
7553 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
7554 to or from a register of CLASS in MODE without requiring a scratch register.
7555 Do not define this macro if it would always return `NO_REGS'.
7557 If a scratch register is required (either with or without an intermediate
7558 register), you should define patterns for `reload_inM' or `reload_outM', as
7559 required.. These patterns, which will normally be implemented with a
7560 `define_expand', should be similar to the `movM' patterns, except that
7561 operand 2 is the scratch register.
7563 Define constraints for the reload register and scratch register that contain
7564 a single register class. If the original reload register (whose class is
7565 CLASS) can meet the constraint given in the pattern, the value returned by
7566 these macros is used for the class of the scratch register. Otherwise, two
7567 additional reload registers are required. Their classes are obtained from
7568 the constraints in the insn pattern.
7570 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
7571 either be in a hard register or in memory. Use `true_regnum' to find out;
7572 it will return -1 if the pseudo is in memory and the hard register number if
7573 it is in a register.
7575 These macros should not be used in the case where a particular class of
7576 registers can only be copied to memory and not to another class of
7577 registers. In that case, secondary reload registers are not needed and
7578 would not be helpful. Instead, a stack location must be used to perform the
7579 copy and the `movM' pattern should use memory as an intermediate storage.
7580 This case often occurs between floating-point and general registers. */
7583 frv_secondary_reload_class (enum reg_class class,
7584 enum machine_mode mode ATTRIBUTE_UNUSED,
7586 int in_p ATTRIBUTE_UNUSED)
7596 /* Accumulators/Accumulator guard registers need to go through floating
7602 if (x && GET_CODE (x) == REG)
7604 int regno = REGNO (x);
7606 if (ACC_P (regno) || ACCG_P (regno))
7611 /* Nonzero constants should be loaded into an FPR through a GPR. */
7615 if (x && CONSTANT_P (x) && !ZERO_P (x))
7621 /* All of these types need gpr registers. */
7633 /* The accumulators need fpr registers */
7646 /* A C expression whose value is nonzero if pseudos that have been assigned to
7647 registers of class CLASS would likely be spilled because registers of CLASS
7648 are needed for spill registers.
7650 The default value of this macro returns 1 if CLASS has exactly one register
7651 and zero otherwise. On most machines, this default should be used. Only
7652 define this macro to some other expression if pseudo allocated by
7653 `local-alloc.c' end up in memory because their hard registers were needed
7654 for spill registers. If this macro returns nonzero for those classes, those
7655 pseudos will only be allocated by `global.c', which knows how to reallocate
7656 the pseudo to another register. If there would not be another register
7657 available for reallocation, you should not change the definition of this
7658 macro since the only effect of such a definition would be to slow down
7659 register allocation. */
7662 frv_class_likely_spilled_p (enum reg_class class)
7689 /* An expression for the alignment of a structure field FIELD if the
7690 alignment computed in the usual way is COMPUTED. GCC uses this
7691 value instead of the value in `BIGGEST_ALIGNMENT' or
7692 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
7694 /* The definition type of the bit field data is either char, short, long or
7695 long long. The maximum bit size is the number of bits of its own type.
7697 The bit field data is assigned to a storage unit that has an adequate size
7698 for bit field data retention and is located at the smallest address.
7700 Consecutive bit field data are packed at consecutive bits having the same
7701 storage unit, with regard to the type, beginning with the MSB and continuing
7704 If a field to be assigned lies over a bit field type boundary, its
7705 assignment is completed by aligning it with a boundary suitable for the
7708 When a bit field having a bit length of 0 is declared, it is forcibly
7709 assigned to the next storage unit.
7722 &x 00000000 00000000 00000000 00000000
7725 &x+4 00000000 00000000 00000000 00000000
7728 &x+8 00000000 00000000 00000000 00000000
7731 &x+12 00000000 00000000 00000000 00000000
7737 frv_adjust_field_align (tree field, int computed)
7739 /* Make sure that the bitfield is not wider than the type. */
7740 if (DECL_BIT_FIELD (field)
7741 && !DECL_ARTIFICIAL (field))
7743 tree parent = DECL_CONTEXT (field);
7744 tree prev = NULL_TREE;
7747 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
7749 if (TREE_CODE (cur) != FIELD_DECL)
7758 /* If this isn't a :0 field and if the previous element is a bitfield
7759 also, see if the type is different, if so, we will need to align the
7760 bit-field to the next boundary. */
7762 && ! DECL_PACKED (field)
7763 && ! integer_zerop (DECL_SIZE (field))
7764 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
7766 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
7767 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
7768 computed = (prev_align > cur_align) ? prev_align : cur_align;
7776 /* A C expression that is nonzero if it is permissible to store a value of mode
7777 MODE in hard register number REGNO (or in several registers starting with
7778 that one). For a machine where all registers are equivalent, a suitable
7781 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
7783 It is not necessary for this macro to check for the numbers of fixed
7784 registers, because the allocation mechanism considers them to be always
7787 On some machines, double-precision values must be kept in even/odd register
7788 pairs. The way to implement that is to define this macro to reject odd
7789 register numbers for such modes.
7791 The minimum requirement for a mode to be OK in a register is that the
7792 `movMODE' instruction pattern support moves between the register and any
7793 other hard register for which the mode is OK; and that moving a value into
7794 the register and back out not alter it.
7796 Since the same instruction used to move `SImode' will work for all narrower
7797 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
7798 to distinguish between these modes, provided you define patterns `movhi',
7799 etc., to take advantage of this. This is useful because of the interaction
7800 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
7801 all integer modes to be tieable.
7803 Many machines have special registers for floating point arithmetic. Often
7804 people assume that floating point machine modes are allowed only in floating
7805 point registers. This is not true. Any registers that can hold integers
7806 can safely *hold* a floating point machine mode, whether or not floating
7807 arithmetic can be done on it in those registers. Integer move instructions
7808 can be used to move the values.
7810 On some machines, though, the converse is true: fixed-point machine modes
7811 may not go in floating registers. This is true if the floating registers
7812 normalize any value stored in them, because storing a non-floating value
7813 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
7814 fixed-point machine modes in floating registers. But if the floating
7815 registers do not automatically normalize, if you can store any bit pattern
7816 in one and retrieve it unchanged without a trap, then any machine mode may
7817 go in a floating register, so you can define this macro to say so.
7819 The primary significance of special floating registers is rather that they
7820 are the registers acceptable in floating point arithmetic instructions.
7821 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
7822 writing the proper constraints for those instructions.
7824 On some machines, the floating registers are especially slow to access, so
7825 that it is better to store a value in a stack frame than in such a register
7826 if floating point arithmetic is not being done. As long as the floating
7827 registers are not in class `GENERAL_REGS', they will not be used unless some
7828 pattern's constraint asks for one. */
7831 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
7841 return ICC_P (regno) || GPR_P (regno);
7844 return CR_P (regno) || GPR_P (regno);
7847 return FCC_P (regno) || GPR_P (regno);
7853 /* Set BASE to the first register in REGNO's class. Set MASK to the
7854 bits that must be clear in (REGNO - BASE) for the register to be
7856 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
7860 /* ACCGs store one byte. Two-byte quantities must start in
7861 even-numbered registers, four-byte ones in registers whose
7862 numbers are divisible by four, and so on. */
7864 mask = GET_MODE_SIZE (mode) - 1;
7868 /* The other registers store one word. */
7869 if (GPR_P (regno) || regno == AP_FIRST)
7872 else if (FPR_P (regno))
7875 else if (ACC_P (regno))
7878 else if (SPR_P (regno))
7879 return mode == SImode;
7881 /* Fill in the table. */
7885 /* Anything smaller than an SI is OK in any word-sized register. */
7886 if (GET_MODE_SIZE (mode) < 4)
7889 mask = (GET_MODE_SIZE (mode) / 4) - 1;
7891 return (((regno - base) & mask) == 0);
7898 /* A C expression for the number of consecutive hard registers, starting at
7899 register number REGNO, required to hold a value of mode MODE.
7901 On a machine where all registers are exactly one word, a suitable definition
7904 #define HARD_REGNO_NREGS(REGNO, MODE) \
7905 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
7906 / UNITS_PER_WORD)) */
7908 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
7909 that we can build the appropriate instructions to properly reload the
7910 values. Also, make the byte-sized accumulator guards use one guard
7914 frv_hard_regno_nregs (int regno, enum machine_mode mode)
7917 return GET_MODE_SIZE (mode);
7919 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7923 /* A C expression for the maximum number of consecutive registers of
7924 class CLASS needed to hold a value of mode MODE.
7926 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
7927 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
7928 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
7930 This macro helps control the handling of multiple-word values in
7933 This declaration is required. */
7936 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
7938 if (class == ACCG_REGS)
7939 /* An N-byte value requires N accumulator guards. */
7940 return GET_MODE_SIZE (mode);
7942 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7946 /* A C expression that is nonzero if X is a legitimate constant for an
7947 immediate operand on the target machine. You can assume that X satisfies
7948 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
7949 definition for this macro on machines where anything `CONSTANT_P' is valid. */
7952 frv_legitimate_constant_p (rtx x)
7954 enum machine_mode mode = GET_MODE (x);
7956 /* frv_cannot_force_const_mem always returns true for FDPIC. This
7957 means that the move expanders will be expected to deal with most
7958 kinds of constant, regardless of what we return here.
7960 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
7961 a constant can be entered into reg_equiv_constant[]. If we return true,
7962 reload can create new instances of the constant whenever it likes.
7964 The idea is therefore to accept as many constants as possible (to give
7965 reload more freedom) while rejecting constants that can only be created
7966 at certain times. In particular, anything with a symbolic component will
7967 require use of the pseudo FDPIC register, which is only available before
7970 return LEGITIMATE_PIC_OPERAND_P (x);
7972 /* All of the integer constants are ok. */
7973 if (GET_CODE (x) != CONST_DOUBLE)
7976 /* double integer constants are ok. */
7977 if (mode == VOIDmode || mode == DImode)
7980 /* 0 is always ok. */
7981 if (x == CONST0_RTX (mode))
7984 /* If floating point is just emulated, allow any constant, since it will be
7985 constructed in the GPRs. */
7986 if (!TARGET_HAS_FPRS)
7989 if (mode == DFmode && !TARGET_DOUBLE)
7992 /* Otherwise store the constant away and do a load. */
7996 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
7997 CC_NZ for comparisons against zero in which a single Z or N flag test
7998 is enough, CC_UNS for other unsigned comparisons, and CC for other
7999 signed comparisons. */
8002 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
8004 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
8013 return y == const0_rtx ? CC_NZmode : CCmode;
8019 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
8026 /* A C expression for the cost of moving data from a register in class FROM to
8027 one in class TO. The classes are expressed using the enumeration values
8028 such as `GENERAL_REGS'. A value of 4 is the default; other values are
8029 interpreted relative to that.
8031 It is not required that the cost always equal 2 when FROM is the same as TO;
8032 on some machines it is expensive to move between registers if they are not
8035 If reload sees an insn consisting of a single `set' between two hard
8036 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
8037 value of 2, reload does not check to ensure that the constraints of the insn
8038 are met. Setting a cost of other than 2 will allow reload to verify that
8039 the constraints are met. You should do this if the `movM' pattern's
8040 constraints do not allow such copying. */
8042 #define HIGH_COST 40
8043 #define MEDIUM_COST 3
8047 frv_register_move_cost (enum reg_class from, enum reg_class to)
8131 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
8132 use ".picptr" to generate safe relocations for PIC code. We also
8133 need a fixup entry for aligned (non-debugging) code. */
8136 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
8138 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
8140 if (GET_CODE (value) == CONST
8141 || GET_CODE (value) == SYMBOL_REF
8142 || GET_CODE (value) == LABEL_REF)
8144 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
8145 && SYMBOL_REF_FUNCTION_P (value))
8147 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
8148 output_addr_const (asm_out_file, value);
8149 fputs (")\n", asm_out_file);
8152 else if (TARGET_FDPIC && GET_CODE (value) == CONST
8153 && frv_function_symbol_referenced_p (value))
8155 if (aligned_p && !TARGET_FDPIC)
8157 static int label_num = 0;
8161 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
8162 p = (* targetm.strip_name_encoding) (buf);
8164 fprintf (asm_out_file, "%s:\n", p);
8165 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
8166 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
8167 fprintf (asm_out_file, "\t.previous\n");
8169 assemble_integer_with_op ("\t.picptr\t", value);
8174 /* We've set the unaligned SI op to NULL, so we always have to
8175 handle the unaligned case here. */
8176 assemble_integer_with_op ("\t.4byte\t", value);
8180 return default_assemble_integer (value, size, aligned_p);
8183 /* Function to set up the backend function structure. */
8185 static struct machine_function *
8186 frv_init_machine_status (void)
8188 return ggc_alloc_cleared (sizeof (struct machine_function));
8191 /* Implement TARGET_SCHED_ISSUE_RATE. */
8194 frv_issue_rate (void)
8199 switch (frv_cpu_type)
8203 case FRV_CPU_SIMPLE:
8211 case FRV_CPU_GENERIC:
8213 case FRV_CPU_TOMCAT:
8221 /* A for_each_rtx callback. If X refers to an accumulator, return
8222 ACC_GROUP_ODD if the bit 2 of the register number is set and
8223 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
8227 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
8231 if (ACC_P (REGNO (*x)))
8232 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8233 if (ACCG_P (REGNO (*x)))
8234 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
8239 /* Return the value of INSN's acc_group attribute. */
8242 frv_acc_group (rtx insn)
8244 /* This distinction only applies to the FR550 packing constraints. */
8245 if (frv_cpu_type != FRV_CPU_FR550)
8246 return ACC_GROUP_NONE;
8247 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
8250 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
8251 INSN will try to claim first. Since this value depends only on the
8252 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
8255 frv_insn_unit (rtx insn)
8257 enum attr_type type;
8259 type = get_attr_type (insn);
8260 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
8262 /* We haven't seen this type of instruction before. */
8266 /* Issue the instruction on its own to see which unit it prefers. */
8267 state = alloca (state_size ());
8268 state_reset (state);
8269 state_transition (state, insn);
8271 /* Find out which unit was taken. */
8272 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
8273 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
8276 if (unit == ARRAY_SIZE (frv_unit_codes))
8279 frv_type_to_unit[type] = unit;
8281 return frv_type_to_unit[type];
8284 /* Return true if INSN issues to a branch unit. */
8287 frv_issues_to_branch_unit_p (rtx insn)
8289 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
8292 /* The current state of the packing pass, implemented by frv_pack_insns. */
8294 /* The state of the pipeline DFA. */
8297 /* Which hardware registers are set within the current packet,
8298 and the conditions under which they are set. */
8299 regstate_t regstate[FIRST_PSEUDO_REGISTER];
8301 /* The memory locations that have been modified so far in this
8302 packet. MEM is the memref and COND is the regstate_t condition
8303 under which it is set. */
8309 /* The number of valid entries in MEMS. The value is larger than
8310 ARRAY_SIZE (mems) if there were too many mems to record. */
8311 unsigned int num_mems;
8313 /* The maximum number of instructions that can be packed together. */
8314 unsigned int issue_rate;
8316 /* The instructions in the packet, partitioned into groups. */
8317 struct frv_packet_group {
8318 /* How many instructions in the packet belong to this group. */
8319 unsigned int num_insns;
8321 /* A list of the instructions that belong to this group, in the order
8322 they appear in the rtl stream. */
8323 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8325 /* The contents of INSNS after they have been sorted into the correct
8326 assembly-language order. Element X issues to unit X. The list may
8327 contain extra nops. */
8328 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
8330 /* The member of frv_nops[] to use in sorted[]. */
8332 } groups[NUM_GROUPS];
8334 /* The instructions that make up the current packet. */
8335 rtx insns[ARRAY_SIZE (frv_unit_codes)];
8336 unsigned int num_insns;
8339 /* Return the regstate_t flags for the given COND_EXEC condition.
8340 Abort if the condition isn't in the right form. */
8343 frv_cond_flags (rtx cond)
8345 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8346 && GET_CODE (XEXP (cond, 0)) == REG
8347 && CR_P (REGNO (XEXP (cond, 0)))
8348 && XEXP (cond, 1) == const0_rtx)
8349 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
8350 | (GET_CODE (cond) == NE
8352 : REGSTATE_IF_FALSE));
8357 /* Return true if something accessed under condition COND2 can
8358 conflict with something written under condition COND1. */
8361 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
8363 /* If either reference was unconditional, we have a conflict. */
8364 if ((cond1 & REGSTATE_IF_EITHER) == 0
8365 || (cond2 & REGSTATE_IF_EITHER) == 0)
8368 /* The references might conflict if they were controlled by
8370 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
8373 /* They definitely conflict if they are controlled by the
8375 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
8382 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
8383 the current packet. DATA points to a regstate_t that describes the
8384 condition under which *X might be set or used. */
8387 frv_registers_conflict_p_1 (rtx *x, void *data)
8389 unsigned int regno, i;
8392 cond = *(regstate_t *) data;
8394 if (GET_CODE (*x) == REG)
8395 FOR_EACH_REGNO (regno, *x)
8396 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
8397 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
8400 if (GET_CODE (*x) == MEM)
8402 /* If we ran out of memory slots, assume a conflict. */
8403 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
8406 /* Check for output or true dependencies with earlier MEMs. */
8407 for (i = 0; i < frv_packet.num_mems; i++)
8408 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
8410 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
8414 if (output_dependence (frv_packet.mems[i].mem, *x))
8419 /* The return values of calls aren't significant: they describe
8420 the effect of the call as a whole, not of the insn itself. */
8421 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
8423 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
8428 /* Check subexpressions. */
8433 /* Return true if something in X might depend on an instruction
8434 in the current packet. */
8437 frv_registers_conflict_p (rtx x)
8442 if (GET_CODE (x) == COND_EXEC)
8444 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
8447 flags |= frv_cond_flags (XEXP (x, 0));
8450 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
8454 /* A note_stores callback. DATA points to the regstate_t condition
8455 under which X is modified. Update FRV_PACKET accordingly. */
8458 frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8462 if (GET_CODE (x) == REG)
8463 FOR_EACH_REGNO (regno, x)
8464 frv_packet.regstate[regno] |= *(regstate_t *) data;
8466 if (GET_CODE (x) == MEM)
8468 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
8470 frv_packet.mems[frv_packet.num_mems].mem = x;
8471 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
8473 frv_packet.num_mems++;
8478 /* Update the register state information for an instruction whose
8482 frv_registers_update (rtx x)
8486 flags = REGSTATE_MODIFIED;
8487 if (GET_CODE (x) == COND_EXEC)
8489 flags |= frv_cond_flags (XEXP (x, 0));
8492 note_stores (x, frv_registers_update_1, &flags);
8496 /* Initialize frv_packet for the start of a new packet. */
8499 frv_start_packet (void)
8501 enum frv_insn_group group;
8503 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
8504 frv_packet.num_mems = 0;
8505 frv_packet.num_insns = 0;
8506 for (group = 0; group < NUM_GROUPS; group++)
8507 frv_packet.groups[group].num_insns = 0;
8511 /* Likewise for the start of a new basic block. */
8514 frv_start_packet_block (void)
8516 state_reset (frv_packet.dfa_state);
8517 frv_start_packet ();
8521 /* Finish the current packet, if any, and start a new one. Call
8522 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
8525 frv_finish_packet (void (*handle_packet) (void))
8527 if (frv_packet.num_insns > 0)
8530 state_transition (frv_packet.dfa_state, 0);
8531 frv_start_packet ();
8536 /* Return true if INSN can be added to the current packet. Update
8537 the DFA state on success. */
8540 frv_pack_insn_p (rtx insn)
8542 /* See if the packet is already as long as it can be. */
8543 if (frv_packet.num_insns == frv_packet.issue_rate)
8546 /* If the scheduler thought that an instruction should start a packet,
8547 it's usually a good idea to believe it. It knows much more about
8548 the latencies than we do.
8550 There are some exceptions though:
8552 - Conditional instructions are scheduled on the assumption that
8553 they will be executed. This is usually a good thing, since it
8554 tends to avoid unnecessary stalls in the conditional code.
8555 But we want to pack conditional instructions as tightly as
8556 possible, in order to optimize the case where they aren't
8559 - The scheduler will always put branches on their own, even
8560 if there's no real dependency.
8562 - There's no point putting a call in its own packet unless
8564 if (frv_packet.num_insns > 0
8565 && GET_CODE (insn) == INSN
8566 && GET_MODE (insn) == TImode
8567 && GET_CODE (PATTERN (insn)) != COND_EXEC)
8570 /* Check for register conflicts. Don't do this for setlo since any
8571 conflict will be with the partnering sethi, with which it can
8573 if (get_attr_type (insn) != TYPE_SETLO)
8574 if (frv_registers_conflict_p (PATTERN (insn)))
8577 return state_transition (frv_packet.dfa_state, insn) < 0;
8581 /* Add instruction INSN to the current packet. */
8584 frv_add_insn_to_packet (rtx insn)
8586 struct frv_packet_group *packet_group;
8588 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8589 packet_group->insns[packet_group->num_insns++] = insn;
8590 frv_packet.insns[frv_packet.num_insns++] = insn;
8592 frv_registers_update (PATTERN (insn));
8596 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
8597 packet ends in a branch or call, insert the nop before it, otherwise
8601 frv_insert_nop_in_packet (rtx insn)
8603 struct frv_packet_group *packet_group;
8606 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
8607 last = frv_packet.insns[frv_packet.num_insns - 1];
8608 if (GET_CODE (last) != INSN)
8610 insn = emit_insn_before (PATTERN (insn), last);
8611 frv_packet.insns[frv_packet.num_insns - 1] = insn;
8612 frv_packet.insns[frv_packet.num_insns++] = last;
8616 insn = emit_insn_after (PATTERN (insn), last);
8617 frv_packet.insns[frv_packet.num_insns++] = insn;
8619 packet_group->insns[packet_group->num_insns++] = insn;
8623 /* If packing is enabled, divide the instructions into packets and
8624 return true. Call HANDLE_PACKET for each complete packet. */
8627 frv_for_each_packet (void (*handle_packet) (void))
8629 rtx insn, next_insn;
8631 frv_packet.issue_rate = frv_issue_rate ();
8633 /* Early exit if we don't want to pack insns. */
8635 || !flag_schedule_insns_after_reload
8636 || TARGET_NO_VLIW_BRANCH
8637 || frv_packet.issue_rate == 1)
8640 /* Set up the initial packing state. */
8642 frv_packet.dfa_state = alloca (state_size ());
8644 frv_start_packet_block ();
8645 for (insn = get_insns (); insn != 0; insn = next_insn)
8650 code = GET_CODE (insn);
8651 next_insn = NEXT_INSN (insn);
8653 if (code == CODE_LABEL)
8655 frv_finish_packet (handle_packet);
8656 frv_start_packet_block ();
8660 switch (GET_CODE (PATTERN (insn)))
8669 /* Calls mustn't be packed on a TOMCAT. */
8670 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
8671 frv_finish_packet (handle_packet);
8673 /* Since the last instruction in a packet determines the EH
8674 region, any exception-throwing instruction must come at
8675 the end of reordered packet. Insns that issue to a
8676 branch unit are bound to come last; for others it's
8677 too hard to predict. */
8678 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
8679 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
8680 frv_finish_packet (handle_packet);
8682 /* Finish the current packet if we can't add INSN to it.
8683 Simulate cycles until INSN is ready to issue. */
8684 if (!frv_pack_insn_p (insn))
8686 frv_finish_packet (handle_packet);
8687 while (!frv_pack_insn_p (insn))
8688 state_transition (frv_packet.dfa_state, 0);
8691 /* Add the instruction to the packet. */
8692 frv_add_insn_to_packet (insn);
8694 /* Calls and jumps end a packet, as do insns that throw
8696 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
8697 frv_finish_packet (handle_packet);
8701 frv_finish_packet (handle_packet);
8706 /* Subroutine of frv_sort_insn_group. We are trying to sort
8707 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
8708 language order. We have already picked a new position for
8709 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
8710 These instructions will occupy elements [0, LOWER_SLOT) and
8711 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
8712 the DFA state after issuing these instructions.
8714 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
8715 of the unused instructions. Return true if one such permutation gives
8716 a valid ordering, leaving the successful permutation in sorted[].
8717 Do not modify sorted[] until a valid permutation is found. */
8720 frv_sort_insn_group_1 (enum frv_insn_group group,
8721 unsigned int lower_slot, unsigned int upper_slot,
8722 unsigned int issued, unsigned int num_insns,
8725 struct frv_packet_group *packet_group;
8731 /* Early success if we've filled all the slots. */
8732 if (lower_slot == upper_slot)
8735 packet_group = &frv_packet.groups[group];
8736 dfa_size = state_size ();
8737 test_state = alloca (dfa_size);
8739 /* Try issuing each unused instruction. */
8740 for (i = num_insns - 1; i + 1 != 0; i--)
8741 if (~issued & (1 << i))
8743 insn = packet_group->sorted[i];
8744 memcpy (test_state, state, dfa_size);
8745 if (state_transition (test_state, insn) < 0
8746 && cpu_unit_reservation_p (test_state,
8747 NTH_UNIT (group, upper_slot - 1))
8748 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
8749 issued | (1 << i), num_insns,
8752 packet_group->sorted[upper_slot - 1] = insn;
8760 /* Compare two instructions by their frv_insn_unit. */
8763 frv_compare_insns (const void *first, const void *second)
8765 const rtx *insn1 = first, *insn2 = second;
8766 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
8769 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
8770 and sort it into assembly language order. See frv.md for a description of
8774 frv_sort_insn_group (enum frv_insn_group group)
8776 struct frv_packet_group *packet_group;
8777 unsigned int first, i, nop, max_unit, num_slots;
8778 state_t state, test_state;
8781 packet_group = &frv_packet.groups[group];
8783 /* Assume no nop is needed. */
8784 packet_group->nop = 0;
8786 if (packet_group->num_insns == 0)
8789 /* Copy insns[] to sorted[]. */
8790 memcpy (packet_group->sorted, packet_group->insns,
8791 sizeof (rtx) * packet_group->num_insns);
8793 /* Sort sorted[] by the unit that each insn tries to take first. */
8794 if (packet_group->num_insns > 1)
8795 qsort (packet_group->sorted, packet_group->num_insns,
8796 sizeof (rtx), frv_compare_insns);
8798 /* That's always enough for branch and control insns. */
8799 if (group == GROUP_B || group == GROUP_C)
8802 dfa_size = state_size ();
8803 state = alloca (dfa_size);
8804 test_state = alloca (dfa_size);
8806 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
8807 consecutively and such that the DFA takes unit X when sorted[X]
8808 is added. Set STATE to the new DFA state. */
8809 state_reset (test_state);
8810 for (first = 0; first < packet_group->num_insns; first++)
8812 memcpy (state, test_state, dfa_size);
8813 if (state_transition (test_state, packet_group->sorted[first]) >= 0
8814 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
8818 /* If all the instructions issued in ascending order, we're done. */
8819 if (first == packet_group->num_insns)
8822 /* Add nops to the end of sorted[] and try each permutation until
8823 we find one that works. */
8824 for (nop = 0; nop < frv_num_nops; nop++)
8826 max_unit = frv_insn_unit (frv_nops[nop]);
8827 if (frv_unit_groups[max_unit] == group)
8829 packet_group->nop = frv_nops[nop];
8830 num_slots = UNIT_NUMBER (max_unit) + 1;
8831 for (i = packet_group->num_insns; i < num_slots; i++)
8832 packet_group->sorted[i] = frv_nops[nop];
8833 if (frv_sort_insn_group_1 (group, first, num_slots,
8834 (1 << first) - 1, num_slots, state))
8841 /* Sort the current packet into assembly-language order. Set packing
8842 flags as appropriate. */
8845 frv_reorder_packet (void)
8847 unsigned int cursor[NUM_GROUPS];
8848 rtx insns[ARRAY_SIZE (frv_unit_groups)];
8849 unsigned int unit, to, from;
8850 enum frv_insn_group group;
8851 struct frv_packet_group *packet_group;
8853 /* First sort each group individually. */
8854 for (group = 0; group < NUM_GROUPS; group++)
8857 frv_sort_insn_group (group);
8860 /* Go through the unit template and try add an instruction from
8861 that unit's group. */
8863 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
8865 group = frv_unit_groups[unit];
8866 packet_group = &frv_packet.groups[group];
8867 if (cursor[group] < packet_group->num_insns)
8869 /* frv_reorg should have added nops for us. */
8870 if (packet_group->sorted[cursor[group]] == packet_group->nop)
8872 insns[to++] = packet_group->sorted[cursor[group]++];
8876 if (to != frv_packet.num_insns)
8879 /* Clear the last instruction's packing flag, thus marking the end of
8880 a packet. Reorder the other instructions relative to it. */
8881 CLEAR_PACKING_FLAG (insns[to - 1]);
8882 for (from = 0; from < to - 1; from++)
8884 remove_insn (insns[from]);
8885 add_insn_before (insns[from], insns[to - 1]);
8886 SET_PACKING_FLAG (insns[from]);
8891 /* Divide instructions into packets. Reorder the contents of each
8892 packet so that they are in the correct assembly-language order.
8894 Since this pass can change the raw meaning of the rtl stream, it must
8895 only be called at the last minute, just before the instructions are
8899 frv_pack_insns (void)
8901 if (frv_for_each_packet (frv_reorder_packet))
8902 frv_insn_packing_flag = 0;
8904 frv_insn_packing_flag = -1;
8907 /* See whether we need to add nops to group GROUP in order to
8908 make a valid packet. */
8911 frv_fill_unused_units (enum frv_insn_group group)
8913 unsigned int non_nops, nops, i;
8914 struct frv_packet_group *packet_group;
8916 packet_group = &frv_packet.groups[group];
8918 /* Sort the instructions into assembly-language order.
8919 Use nops to fill slots that are otherwise unused. */
8920 frv_sort_insn_group (group);
8922 /* See how many nops are needed before the final useful instruction. */
8924 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
8925 while (packet_group->sorted[i++] == packet_group->nop)
8928 /* Insert that many nops into the instruction stream. */
8930 frv_insert_nop_in_packet (packet_group->nop);
8933 /* Used by frv_reorg to keep track of the current packet's address. */
8934 static unsigned int frv_packet_address;
8936 /* If the current packet falls through to a label, try to pad the packet
8937 with nops in order to fit the label's alignment requirements. */
8940 frv_align_label (void)
8942 unsigned int alignment, target, nop;
8943 rtx x, last, barrier, label;
8945 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8946 maximum alignment of that packet, LABEL to the last label between
8947 the packets, and BARRIER to the last barrier. */
8948 last = frv_packet.insns[frv_packet.num_insns - 1];
8949 label = barrier = 0;
8951 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8955 unsigned int subalign = 1 << label_to_alignment (x);
8956 alignment = MAX (alignment, subalign);
8963 /* If -malign-labels, and the packet falls through to an unaligned
8964 label, try introducing a nop to align that label to 8 bytes. */
8965 if (TARGET_ALIGN_LABELS
8968 && frv_packet.num_insns < frv_packet.issue_rate)
8969 alignment = MAX (alignment, 8);
8971 /* Advance the address to the end of the current packet. */
8972 frv_packet_address += frv_packet.num_insns * 4;
8974 /* Work out the target address, after alignment. */
8975 target = (frv_packet_address + alignment - 1) & -alignment;
8977 /* If the packet falls through to the label, try to find an efficient
8978 padding sequence. */
8981 /* First try adding nops to the current packet. */
8982 for (nop = 0; nop < frv_num_nops; nop++)
8983 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8985 frv_insert_nop_in_packet (frv_nops[nop]);
8986 frv_packet_address += 4;
8989 /* If we still haven't reached the target, add some new packets that
8990 contain only nops. If there are two types of nop, insert an
8991 alternating sequence of frv_nops[0] and frv_nops[1], which will
8992 lead to packets like:
8999 etc. Just emit frv_nops[0] if that's the only nop we have. */
9000 last = frv_packet.insns[frv_packet.num_insns - 1];
9002 while (frv_packet_address < target)
9004 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
9005 frv_packet_address += 4;
9006 if (frv_num_nops > 1)
9011 frv_packet_address = target;
9014 /* Subroutine of frv_reorg, called after each packet has been constructed
9018 frv_reorg_packet (void)
9020 frv_fill_unused_units (GROUP_I);
9021 frv_fill_unused_units (GROUP_FM);
9025 /* Add an instruction with pattern NOP to frv_nops[]. */
9028 frv_register_nop (rtx nop)
9030 nop = make_insn_raw (nop);
9031 NEXT_INSN (nop) = 0;
9032 PREV_INSN (nop) = 0;
9033 frv_nops[frv_num_nops++] = nop;
9036 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
9037 into packets and check whether we need to insert nops in order to
9038 fulfill the processor's issue requirements. Also, if the user has
9039 requested a certain alignment for a label, try to meet that alignment
9040 by inserting nops in the previous packet. */
9046 frv_register_nop (gen_nop ());
9048 frv_register_nop (gen_mnop ());
9049 if (TARGET_HARD_FLOAT)
9050 frv_register_nop (gen_fnop ());
9052 /* Estimate the length of each branch. Although this may change after
9053 we've inserted nops, it will only do so in big functions. */
9054 shorten_branches (get_insns ());
9056 frv_packet_address = 0;
9057 frv_for_each_packet (frv_reorg_packet);
9060 #define def_builtin(name, type, code) \
9061 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
9063 struct builtin_description
9065 enum insn_code icode;
9067 enum frv_builtins code;
9068 enum rtx_code comparison;
9072 /* Media intrinsics that take a single, constant argument. */
9074 static struct builtin_description bdesc_set[] =
9076 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
9079 /* Media intrinsics that take just one argument. */
9081 static struct builtin_description bdesc_1arg[] =
9083 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
9084 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
9085 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
9086 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
9087 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
9088 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
9091 /* Media intrinsics that take two arguments. */
9093 static struct builtin_description bdesc_2arg[] =
9095 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
9096 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
9097 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
9098 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
9099 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
9100 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
9101 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
9102 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
9103 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
9104 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
9105 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
9106 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
9107 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
9108 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
9109 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
9110 { CODE_FOR_mdpackh, "__MDPACKH", FRV_BUILTIN_MDPACKH, 0, 0 },
9111 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
9112 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
9113 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
9114 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
9115 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
9116 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
9117 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
9118 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
9119 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
9120 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
9121 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
9122 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
9125 /* Integer intrinsics that take two arguments and have no return value. */
9127 static struct builtin_description bdesc_int_void2arg[] =
9129 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
9130 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
9131 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
9134 static struct builtin_description bdesc_prefetches[] =
9136 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
9137 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
9140 /* Media intrinsics that take two arguments, the first being an ACC number. */
9142 static struct builtin_description bdesc_cut[] =
9144 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
9145 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
9146 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
9149 /* Two-argument media intrinsics with an immediate second argument. */
9151 static struct builtin_description bdesc_2argimm[] =
9153 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
9154 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
9155 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
9156 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
9157 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
9158 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
9159 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
9160 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
9161 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
9162 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
9163 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
9164 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
9165 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
9166 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
9167 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
9168 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
9169 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
9172 /* Media intrinsics that take two arguments and return void, the first argument
9173 being a pointer to 4 words in memory. */
9175 static struct builtin_description bdesc_void2arg[] =
9177 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
9178 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
9181 /* Media intrinsics that take three arguments, the first being a const_int that
9182 denotes an accumulator, and that return void. */
9184 static struct builtin_description bdesc_void3arg[] =
9186 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
9187 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
9188 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
9189 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
9190 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
9191 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
9192 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
9193 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
9194 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
9195 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
9196 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
9197 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
9198 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
9199 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
9200 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
9201 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
9202 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
9203 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
9204 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
9205 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
9206 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
9207 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
9208 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
9209 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
9210 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
9213 /* Media intrinsics that take two accumulator numbers as argument and
9216 static struct builtin_description bdesc_voidacc[] =
9218 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
9219 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
9220 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
9221 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
9222 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
9223 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
9226 /* Initialize media builtins. */
9229 frv_init_builtins (void)
9231 tree endlink = void_list_node;
9232 tree accumulator = integer_type_node;
9233 tree integer = integer_type_node;
9234 tree voidt = void_type_node;
9235 tree uhalf = short_unsigned_type_node;
9236 tree sword1 = long_integer_type_node;
9237 tree uword1 = long_unsigned_type_node;
9238 tree sword2 = long_long_integer_type_node;
9239 tree uword2 = long_long_unsigned_type_node;
9240 tree uword4 = build_pointer_type (uword1);
9241 tree iacc = integer_type_node;
9243 #define UNARY(RET, T1) \
9244 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
9246 #define BINARY(RET, T1, T2) \
9247 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9248 tree_cons (NULL_TREE, T2, endlink)))
9250 #define TRINARY(RET, T1, T2, T3) \
9251 build_function_type (RET, tree_cons (NULL_TREE, T1, \
9252 tree_cons (NULL_TREE, T2, \
9253 tree_cons (NULL_TREE, T3, endlink))))
9255 tree void_ftype_void = build_function_type (voidt, endlink);
9257 tree void_ftype_acc = UNARY (voidt, accumulator);
9258 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
9259 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
9260 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
9261 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
9262 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
9263 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
9264 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
9265 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
9267 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
9268 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
9269 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
9270 tree uw1_ftype_acc = UNARY (uword1, accumulator);
9271 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
9272 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
9273 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
9274 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
9275 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
9276 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
9277 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
9279 tree sw1_ftype_int = UNARY (sword1, integer);
9280 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
9281 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
9283 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
9284 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
9285 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
9286 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
9287 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
9289 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
9290 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
9291 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
9292 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
9293 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
9294 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
9295 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
9296 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
9297 tree sw2_ftype_iacc = UNARY (sword2, iacc);
9298 tree sw1_ftype_iacc = UNARY (sword1, iacc);
9299 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
9301 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
9302 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
9303 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
9304 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
9305 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
9306 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
9307 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
9308 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
9309 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
9310 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
9311 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
9312 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
9313 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
9314 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
9315 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
9316 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
9317 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
9318 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
9319 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
9320 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
9321 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
9322 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
9323 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
9324 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
9325 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
9326 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
9327 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
9328 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
9329 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
9330 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
9331 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
9332 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
9333 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
9334 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
9335 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
9336 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
9337 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
9338 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
9339 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
9340 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
9341 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
9342 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
9343 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
9344 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
9345 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
9346 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
9347 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
9348 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
9349 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
9350 def_builtin ("__MDPACKH", uw2_ftype_uw2_uw2, FRV_BUILTIN_MDPACKH);
9351 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
9352 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
9353 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
9354 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
9355 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
9356 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
9357 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
9358 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
9359 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
9360 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
9361 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
9362 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
9363 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
9364 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
9365 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
9366 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
9367 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
9368 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
9369 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
9370 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
9371 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
9372 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
9373 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
9374 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
9375 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
9376 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
9377 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
9378 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
9379 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
9380 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
9381 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
9382 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
9383 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
9384 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
9385 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
9386 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
9387 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
9388 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
9389 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
9390 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
9391 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
9392 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
9393 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
9394 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
9395 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
9396 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
9397 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
9398 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
9399 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
9400 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
9401 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
9402 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
9403 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
9404 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
9411 /* Set the names for various arithmetic operations according to the
9414 frv_init_libfuncs (void)
9416 set_optab_libfunc (smod_optab, SImode, "__modi");
9417 set_optab_libfunc (umod_optab, SImode, "__umodi");
9419 set_optab_libfunc (add_optab, DImode, "__addll");
9420 set_optab_libfunc (sub_optab, DImode, "__subll");
9421 set_optab_libfunc (smul_optab, DImode, "__mulll");
9422 set_optab_libfunc (sdiv_optab, DImode, "__divll");
9423 set_optab_libfunc (smod_optab, DImode, "__modll");
9424 set_optab_libfunc (umod_optab, DImode, "__umodll");
9425 set_optab_libfunc (and_optab, DImode, "__andll");
9426 set_optab_libfunc (ior_optab, DImode, "__orll");
9427 set_optab_libfunc (xor_optab, DImode, "__xorll");
9428 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
9430 set_optab_libfunc (add_optab, SFmode, "__addf");
9431 set_optab_libfunc (sub_optab, SFmode, "__subf");
9432 set_optab_libfunc (smul_optab, SFmode, "__mulf");
9433 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
9435 set_optab_libfunc (add_optab, DFmode, "__addd");
9436 set_optab_libfunc (sub_optab, DFmode, "__subd");
9437 set_optab_libfunc (smul_optab, DFmode, "__muld");
9438 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
9440 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
9441 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
9443 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
9444 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
9445 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
9446 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
9448 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
9449 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
9450 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
9451 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
9453 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
9454 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
9455 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
9456 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
9459 /* Convert an integer constant to an accumulator register. ICODE is the
9460 code of the target instruction, OPNUM is the number of the
9461 accumulator operand and OPVAL is the constant integer. Try both
9462 ACC and ACCG registers; only report an error if neither fit the
9466 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
9471 /* ACCs and ACCGs are implicity global registers if media intrinsics
9472 are being used. We set up this lazily to avoid creating lots of
9473 unnecessary call_insn rtl in non-media code. */
9474 for (i = 0; i <= ACC_MASK; i++)
9475 if ((i & ACC_MASK) == i)
9476 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
9478 if (GET_CODE (opval) != CONST_INT)
9480 error ("accumulator is not a constant integer");
9483 if ((INTVAL (opval) & ~ACC_MASK) != 0)
9485 error ("accumulator number is out of bounds");
9489 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
9490 ACC_FIRST + INTVAL (opval));
9491 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9492 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
9494 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
9496 error ("inappropriate accumulator for %qs", insn_data[icode].name);
9502 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
9505 static enum machine_mode
9506 frv_matching_accg_mode (enum machine_mode mode)
9524 /* Return the accumulator guard that should be paired with accumulator
9525 register ACC. The mode of the returned register is in the same
9526 class as ACC, but is four times smaller. */
9529 frv_matching_accg_for_acc (rtx acc)
9531 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
9532 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
9535 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
9536 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
9540 frv_read_argument (tree *arglistptr)
9542 tree next = TREE_VALUE (*arglistptr);
9543 *arglistptr = TREE_CHAIN (*arglistptr);
9544 return expand_expr (next, NULL_RTX, VOIDmode, 0);
9547 /* Like frv_read_argument, but interpret the argument as the number
9548 of an IACC register and return a (reg:MODE ...) rtx for it. */
9551 frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr)
9556 op = frv_read_argument (arglistptr);
9557 if (GET_CODE (op) != CONST_INT
9559 || INTVAL (op) > IACC_LAST - IACC_FIRST
9560 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
9562 error ("invalid IACC argument");
9566 /* IACCs are implicity global registers. We set up this lazily to
9567 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
9569 regno = INTVAL (op) + IACC_FIRST;
9570 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
9571 global_regs[regno + i] = 1;
9573 return gen_rtx_REG (mode, regno);
9576 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
9577 The instruction should require a constant operand of some sort. The
9578 function prints an error if OPVAL is not valid. */
9581 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
9583 if (GET_CODE (opval) != CONST_INT)
9585 error ("%qs expects a constant argument", insn_data[icode].name);
9588 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
9590 error ("constant argument out of range for %qs", insn_data[icode].name);
9596 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
9597 if it's not null, has the right mode, and satisfies operand 0's
9601 frv_legitimize_target (enum insn_code icode, rtx target)
9603 enum machine_mode mode = insn_data[icode].operand[0].mode;
9606 || GET_MODE (target) != mode
9607 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
9608 return gen_reg_rtx (mode);
9613 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
9614 check whether ARG satisfies the operand's constraints. If it doesn't,
9615 copy ARG to a temporary register and return that. Otherwise return ARG
9619 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
9621 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
9623 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
9626 return copy_to_mode_reg (mode, arg);
9629 /* Expand builtins that take a single, constant argument. At the moment,
9630 only MHDSETS falls into this category. */
9633 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
9636 rtx op0 = frv_read_argument (&arglist);
9638 if (! frv_check_constant_argument (icode, 1, op0))
9641 target = frv_legitimize_target (icode, target);
9642 pat = GEN_FCN (icode) (target, op0);
9650 /* Expand builtins that take one operand. */
9653 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
9656 rtx op0 = frv_read_argument (&arglist);
9658 target = frv_legitimize_target (icode, target);
9659 op0 = frv_legitimize_argument (icode, 1, op0);
9660 pat = GEN_FCN (icode) (target, op0);
9668 /* Expand builtins that take two operands. */
9671 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
9674 rtx op0 = frv_read_argument (&arglist);
9675 rtx op1 = frv_read_argument (&arglist);
9677 target = frv_legitimize_target (icode, target);
9678 op0 = frv_legitimize_argument (icode, 1, op0);
9679 op1 = frv_legitimize_argument (icode, 2, op1);
9680 pat = GEN_FCN (icode) (target, op0, op1);
9688 /* Expand cut-style builtins, which take two operands and an implicit ACCG
9692 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
9695 rtx op0 = frv_read_argument (&arglist);
9696 rtx op1 = frv_read_argument (&arglist);
9699 target = frv_legitimize_target (icode, target);
9700 op0 = frv_int_to_acc (icode, 1, op0);
9704 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
9706 if (! frv_check_constant_argument (icode, 2, op1))
9710 op1 = frv_legitimize_argument (icode, 2, op1);
9712 op2 = frv_matching_accg_for_acc (op0);
9713 pat = GEN_FCN (icode) (target, op0, op1, op2);
9721 /* Expand builtins that take two operands and the second is immediate. */
9724 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
9727 rtx op0 = frv_read_argument (&arglist);
9728 rtx op1 = frv_read_argument (&arglist);
9730 if (! frv_check_constant_argument (icode, 2, op1))
9733 target = frv_legitimize_target (icode, target);
9734 op0 = frv_legitimize_argument (icode, 1, op0);
9735 pat = GEN_FCN (icode) (target, op0, op1);
9743 /* Expand builtins that take two operands, the first operand being a pointer to
9744 ints and return void. */
9747 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
9750 rtx op0 = frv_read_argument (&arglist);
9751 rtx op1 = frv_read_argument (&arglist);
9752 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9755 if (GET_CODE (op0) != MEM)
9759 if (! offsettable_address_p (0, mode0, op0))
9761 reg = gen_reg_rtx (Pmode);
9762 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9765 op0 = gen_rtx_MEM (SImode, reg);
9768 addr = XEXP (op0, 0);
9769 if (! offsettable_address_p (0, mode0, addr))
9770 addr = copy_to_mode_reg (Pmode, op0);
9772 op0 = change_address (op0, V4SImode, addr);
9773 op1 = frv_legitimize_argument (icode, 1, op1);
9774 pat = GEN_FCN (icode) (op0, op1);
9782 /* Expand builtins that take two long operands and return void. */
9785 frv_expand_int_void2arg (enum insn_code icode, tree arglist)
9788 rtx op0 = frv_read_argument (&arglist);
9789 rtx op1 = frv_read_argument (&arglist);
9791 op0 = frv_legitimize_argument (icode, 1, op0);
9792 op1 = frv_legitimize_argument (icode, 1, op1);
9793 pat = GEN_FCN (icode) (op0, op1);
9801 /* Expand prefetch builtins. These take a single address as argument. */
9804 frv_expand_prefetches (enum insn_code icode, tree arglist)
9807 rtx op0 = frv_read_argument (&arglist);
9809 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9817 /* Expand builtins that take three operands and return void. The first
9818 argument must be a constant that describes a pair or quad accumulators. A
9819 fourth argument is created that is the accumulator guard register that
9820 corresponds to the accumulator. */
9823 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
9826 rtx op0 = frv_read_argument (&arglist);
9827 rtx op1 = frv_read_argument (&arglist);
9828 rtx op2 = frv_read_argument (&arglist);
9831 op0 = frv_int_to_acc (icode, 0, op0);
9835 op1 = frv_legitimize_argument (icode, 1, op1);
9836 op2 = frv_legitimize_argument (icode, 2, op2);
9837 op3 = frv_matching_accg_for_acc (op0);
9838 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9846 /* Expand builtins that perform accumulator-to-accumulator operations.
9847 These builtins take two accumulator numbers as argument and return
9851 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
9854 rtx op0 = frv_read_argument (&arglist);
9855 rtx op1 = frv_read_argument (&arglist);
9859 op0 = frv_int_to_acc (icode, 0, op0);
9863 op1 = frv_int_to_acc (icode, 1, op1);
9867 op2 = frv_matching_accg_for_acc (op0);
9868 op3 = frv_matching_accg_for_acc (op1);
9869 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9877 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9878 number as argument. */
9881 frv_expand_mclracc_builtin (tree arglist)
9883 enum insn_code icode = CODE_FOR_mclracc;
9885 rtx op0 = frv_read_argument (&arglist);
9887 op0 = frv_int_to_acc (icode, 0, op0);
9891 pat = GEN_FCN (icode) (op0);
9898 /* Expand builtins that take no arguments. */
9901 frv_expand_noargs_builtin (enum insn_code icode)
9903 rtx pat = GEN_FCN (icode) (const0_rtx);
9910 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9911 number or accumulator guard number as argument and return an SI integer. */
9914 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
9917 rtx target = gen_reg_rtx (SImode);
9918 rtx op0 = frv_read_argument (&arglist);
9920 op0 = frv_int_to_acc (icode, 1, op0);
9924 pat = GEN_FCN (icode) (target, op0);
9932 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9933 accumulator guard as their first argument and an SImode value as their
9937 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
9940 rtx op0 = frv_read_argument (&arglist);
9941 rtx op1 = frv_read_argument (&arglist);
9943 op0 = frv_int_to_acc (icode, 0, op0);
9947 op1 = frv_legitimize_argument (icode, 1, op1);
9948 pat = GEN_FCN (icode) (op0, op1);
9955 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9956 to move DImode values into and out of IACC0. */
9959 frv_split_iacc_move (rtx dest, rtx src)
9961 enum machine_mode inner;
9964 inner = GET_MODE (dest);
9965 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9966 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9967 simplify_gen_subreg (SImode, src, inner, i));
9970 /* Expand builtins. */
9973 frv_expand_builtin (tree exp,
9975 rtx subtarget ATTRIBUTE_UNUSED,
9976 enum machine_mode mode ATTRIBUTE_UNUSED,
9977 int ignore ATTRIBUTE_UNUSED)
9979 tree arglist = TREE_OPERAND (exp, 1);
9980 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9981 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9983 struct builtin_description *d;
9985 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9987 error ("media functions are not available unless -mmedia is used");
9993 case FRV_BUILTIN_MCOP1:
9994 case FRV_BUILTIN_MCOP2:
9995 case FRV_BUILTIN_MDUNPACKH:
9996 case FRV_BUILTIN_MBTOHE:
9997 if (! TARGET_MEDIA_REV1)
9999 error ("this media function is only available on the fr500");
10004 case FRV_BUILTIN_MQXMACHS:
10005 case FRV_BUILTIN_MQXMACXHS:
10006 case FRV_BUILTIN_MQMACXHS:
10007 case FRV_BUILTIN_MADDACCS:
10008 case FRV_BUILTIN_MSUBACCS:
10009 case FRV_BUILTIN_MASACCS:
10010 case FRV_BUILTIN_MDADDACCS:
10011 case FRV_BUILTIN_MDSUBACCS:
10012 case FRV_BUILTIN_MDASACCS:
10013 case FRV_BUILTIN_MABSHS:
10014 case FRV_BUILTIN_MDROTLI:
10015 case FRV_BUILTIN_MCPLHI:
10016 case FRV_BUILTIN_MCPLI:
10017 case FRV_BUILTIN_MDCUTSSI:
10018 case FRV_BUILTIN_MQSATHS:
10019 case FRV_BUILTIN_MHSETLOS:
10020 case FRV_BUILTIN_MHSETLOH:
10021 case FRV_BUILTIN_MHSETHIS:
10022 case FRV_BUILTIN_MHSETHIH:
10023 case FRV_BUILTIN_MHDSETS:
10024 case FRV_BUILTIN_MHDSETH:
10025 if (! TARGET_MEDIA_REV2)
10027 error ("this media function is only available on the fr400"
10033 case FRV_BUILTIN_SMASS:
10034 case FRV_BUILTIN_SMSSS:
10035 case FRV_BUILTIN_SMU:
10036 case FRV_BUILTIN_ADDSS:
10037 case FRV_BUILTIN_SUBSS:
10038 case FRV_BUILTIN_SLASS:
10039 case FRV_BUILTIN_SCUTSS:
10040 case FRV_BUILTIN_IACCreadll:
10041 case FRV_BUILTIN_IACCreadl:
10042 case FRV_BUILTIN_IACCsetll:
10043 case FRV_BUILTIN_IACCsetl:
10044 if (!TARGET_FR405_BUILTINS)
10046 error ("this builtin function is only available"
10047 " on the fr405 and fr450");
10052 case FRV_BUILTIN_PREFETCH:
10053 if (!TARGET_FR500_FR550_BUILTINS)
10055 error ("this builtin function is only available on the fr500"
10061 case FRV_BUILTIN_MQLCLRHS:
10062 case FRV_BUILTIN_MQLMTHS:
10063 case FRV_BUILTIN_MQSLLHI:
10064 case FRV_BUILTIN_MQSRAHI:
10065 if (!TARGET_MEDIA_FR450)
10067 error ("this builtin function is only available on the fr450");
10076 /* Expand unique builtins. */
10080 case FRV_BUILTIN_MTRAP:
10081 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
10083 case FRV_BUILTIN_MCLRACC:
10084 return frv_expand_mclracc_builtin (arglist);
10086 case FRV_BUILTIN_MCLRACCA:
10088 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
10090 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
10092 case FRV_BUILTIN_MRDACC:
10093 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
10095 case FRV_BUILTIN_MRDACCG:
10096 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
10098 case FRV_BUILTIN_MWTACC:
10099 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
10101 case FRV_BUILTIN_MWTACCG:
10102 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
10104 case FRV_BUILTIN_IACCreadll:
10106 rtx src = frv_read_iacc_argument (DImode, &arglist);
10107 if (target == 0 || !REG_P (target))
10108 target = gen_reg_rtx (DImode);
10109 frv_split_iacc_move (target, src);
10113 case FRV_BUILTIN_IACCreadl:
10114 return frv_read_iacc_argument (SImode, &arglist);
10116 case FRV_BUILTIN_IACCsetll:
10118 rtx dest = frv_read_iacc_argument (DImode, &arglist);
10119 rtx src = frv_read_argument (&arglist);
10120 frv_split_iacc_move (dest, force_reg (DImode, src));
10124 case FRV_BUILTIN_IACCsetl:
10126 rtx dest = frv_read_iacc_argument (SImode, &arglist);
10127 rtx src = frv_read_argument (&arglist);
10128 emit_move_insn (dest, force_reg (SImode, src));
10136 /* Expand groups of builtins. */
10138 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
10139 if (d->code == fcode)
10140 return frv_expand_set_builtin (d->icode, arglist, target);
10142 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10143 if (d->code == fcode)
10144 return frv_expand_unop_builtin (d->icode, arglist, target);
10146 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10147 if (d->code == fcode)
10148 return frv_expand_binop_builtin (d->icode, arglist, target);
10150 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
10151 if (d->code == fcode)
10152 return frv_expand_cut_builtin (d->icode, arglist, target);
10154 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
10155 if (d->code == fcode)
10156 return frv_expand_binopimm_builtin (d->icode, arglist, target);
10158 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
10159 if (d->code == fcode)
10160 return frv_expand_voidbinop_builtin (d->icode, arglist);
10162 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
10163 if (d->code == fcode)
10164 return frv_expand_voidtriop_builtin (d->icode, arglist);
10166 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
10167 if (d->code == fcode)
10168 return frv_expand_voidaccop_builtin (d->icode, arglist);
10170 for (i = 0, d = bdesc_int_void2arg;
10171 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
10172 if (d->code == fcode)
10173 return frv_expand_int_void2arg (d->icode, arglist);
10175 for (i = 0, d = bdesc_prefetches;
10176 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
10177 if (d->code == fcode)
10178 return frv_expand_prefetches (d->icode, arglist);
10184 frv_in_small_data_p (tree decl)
10186 HOST_WIDE_INT size;
10189 /* Don't apply the -G flag to internal compiler structures. We
10190 should leave such structures in the main data section, partly
10191 for efficiency and partly because the size of some of them
10192 (such as C++ typeinfos) is not known until later. */
10193 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
10196 /* If we already know which section the decl should be in, see if
10197 it's a small data section. */
10198 section_name = DECL_SECTION_NAME (decl);
10201 if (TREE_CODE (section_name) != STRING_CST)
10203 if (frv_string_begins_with (section_name, ".sdata"))
10205 if (frv_string_begins_with (section_name, ".sbss"))
10210 size = int_size_in_bytes (TREE_TYPE (decl));
10211 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
10218 frv_rtx_costs (rtx x,
10219 int code ATTRIBUTE_UNUSED,
10220 int outer_code ATTRIBUTE_UNUSED,
10223 if (outer_code == MEM)
10225 /* Don't differentiate between memory addresses. All the ones
10226 we accept have equal cost. */
10227 *total = COSTS_N_INSNS (0);
10234 /* Make 12 bit integers really cheap. */
10235 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
10240 /* Fall through. */
10246 *total = COSTS_N_INSNS (2);
10260 if (GET_MODE (x) == SImode)
10261 *total = COSTS_N_INSNS (1);
10262 else if (GET_MODE (x) == DImode)
10263 *total = COSTS_N_INSNS (2);
10265 *total = COSTS_N_INSNS (3);
10269 if (GET_MODE (x) == SImode)
10270 *total = COSTS_N_INSNS (2);
10272 *total = COSTS_N_INSNS (6); /* guess */
10279 *total = COSTS_N_INSNS (18);
10283 *total = COSTS_N_INSNS (3);
10292 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10295 assemble_align (POINTER_SIZE);
10298 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10302 assemble_integer_with_op ("\t.picptr\t", symbol);
10306 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10309 assemble_align (POINTER_SIZE);
10312 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
10316 assemble_integer_with_op ("\t.picptr\t", symbol);
10319 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10322 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
10323 int incoming ATTRIBUTE_UNUSED)
10325 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
10328 #include "gt-frv.h"