1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
48 #include "target-def.h"
49 #include "targhooks.h"
50 #include "integrate.h"
51 #include "langhooks.h"
55 #define FRV_INLINE inline
58 /* The maximum number of distinct NOP patterns. There are three:
59 nop, fnop and mnop. */
60 #define NUM_NOP_PATTERNS 3
62 /* Classification of instructions and units: integer, floating-point/media,
63 branch and control. */
64 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
66 /* The DFA names of the units, in packet order. */
67 static const char *const frv_unit_names[] =
77 /* The classification of each unit in frv_unit_names[]. */
78 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
88 /* Return the DFA unit code associated with the Nth unit of integer
89 or floating-point group GROUP, */
90 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
92 /* Return the number of integer or floating-point unit UNIT
93 (1 for I1, 2 for F2, etc.). */
94 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
96 /* The DFA unit number for each unit in frv_unit_names[]. */
97 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
99 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
100 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
101 no instruction of type T has been seen. */
102 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
104 /* An array of dummy nop INSNs, one for each type of nop that the
106 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
108 /* The number of nop instructions in frv_nops[]. */
109 static unsigned int frv_num_nops;
111 /* Information about one __builtin_read or __builtin_write access, or
112 the combination of several such accesses. The most general value
113 is all-zeros (an unknown access to an unknown address). */
115 /* The type of access. FRV_IO_UNKNOWN means the access can be either
116 a read or a write. */
117 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
119 /* The constant address being accessed, or zero if not known. */
120 HOST_WIDE_INT const_address;
122 /* The run-time address, as used in operand 0 of the membar pattern. */
126 /* Return true if instruction INSN should be packed with the following
128 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
130 /* Set the value of PACKING_FLAG_P(INSN). */
131 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
132 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
134 /* Loop with REG set to each hard register in rtx X. */
135 #define FOR_EACH_REGNO(REG, X) \
136 for (REG = REGNO (X); \
137 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
140 /* This structure contains machine specific function data. */
141 struct GTY(()) machine_function
143 /* True if we have created an rtx that relies on the stack frame. */
146 /* True if this function contains at least one __builtin_{read,write}*. */
150 /* Temporary register allocation support structure. */
151 typedef struct frv_tmp_reg_struct
153 HARD_REG_SET regs; /* possible registers to allocate */
154 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
158 /* Register state information for VLIW re-packing phase. */
159 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
160 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
161 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
162 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
164 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
166 typedef unsigned char regstate_t;
168 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
176 /* Information required by frv_frame_access. */
179 /* This field is FRV_LOAD if registers are to be loaded from the stack and
180 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
181 the move is being done by the prologue code while FRV_LOAD implies it
182 is being done by the epilogue. */
183 enum frv_stack_op op;
185 /* The base register to use when accessing the stack. This may be the
186 frame pointer, stack pointer, or a temporary. The choice of register
187 depends on which part of the frame is being accessed and how big the
191 /* The offset of BASE from the bottom of the current frame, in bytes. */
193 } frv_frame_accessor_t;
195 /* Conditional execution support gathered together in one structure. */
198 /* Linked list of insns to add if the conditional execution conversion was
199 successful. Each link points to an EXPR_LIST which points to the pattern
200 of the insn to add, and the insn to be inserted before. */
201 rtx added_insns_list;
203 /* Identify which registers are safe to allocate for if conversions to
204 conditional execution. We keep the last allocated register in the
205 register classes between COND_EXEC statements. This will mean we allocate
206 different registers for each different COND_EXEC group if we can. This
207 might allow the scheduler to intermix two different COND_EXEC sections. */
208 frv_tmp_reg_t tmp_reg;
210 /* For nested IFs, identify which CC registers are used outside of setting
211 via a compare isnsn, and using via a check insn. This will allow us to
212 know if we can rewrite the register to use a different register that will
213 be paired with the CR register controlling the nested IF-THEN blocks. */
214 HARD_REG_SET nested_cc_ok_rewrite;
216 /* Temporary registers allocated to hold constants during conditional
218 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
220 /* Current number of temp registers available. */
221 int cur_scratch_regs;
223 /* Number of nested conditional execution blocks. */
224 int num_nested_cond_exec;
226 /* Map of insns that set up constants in scratch registers. */
227 bitmap scratch_insns_bitmap;
229 /* Conditional execution test register (CC0..CC7). */
232 /* Conditional execution compare register that is paired with cr_reg, so that
233 nested compares can be done. The csubcc and caddcc instructions don't
234 have enough bits to specify both a CC register to be set and a CR register
235 to do the test on, so the same bit number is used for both. Needless to
236 say, this is rather inconvenient for GCC. */
239 /* Extra CR registers used for &&, ||. */
243 /* Previous CR used in nested if, to make sure we are dealing with the same
244 nested if as the previous statement. */
245 rtx last_nested_if_cr;
249 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
251 /* Map register number to smallest register class. */
252 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
254 /* Map class letter into register class. */
255 enum reg_class reg_class_from_letter[256];
257 /* Cached value of frv_stack_info. */
258 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
261 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
263 /* Forward references */
265 static bool frv_handle_option (size_t, const char *, int);
266 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
267 static int frv_default_flags_for_cpu (void);
268 static int frv_string_begins_with (const_tree, const char *);
269 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
270 static void frv_print_operand (FILE *, rtx, int);
271 static void frv_print_operand_address (FILE *, rtx);
272 static bool frv_print_operand_punct_valid_p (unsigned char code);
273 static void frv_print_operand_memory_reference_reg
275 static void frv_print_operand_memory_reference (FILE *, rtx, int);
276 static int frv_print_operand_jump_hint (rtx);
277 static const char *comparison_string (enum rtx_code, rtx);
278 static rtx frv_function_value (const_tree, const_tree,
280 static rtx frv_libcall_value (enum machine_mode,
282 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
283 static rtx single_set_pattern (rtx);
284 static int frv_function_contains_far_jump (void);
285 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
289 static rtx frv_frame_offset_rtx (int);
290 static rtx frv_frame_mem (enum machine_mode, rtx, int);
291 static rtx frv_dwarf_store (rtx, int);
292 static void frv_frame_insn (rtx, rtx);
293 static void frv_frame_access (frv_frame_accessor_t*,
295 static void frv_frame_access_multi (frv_frame_accessor_t*,
297 static void frv_frame_access_standard_regs (enum frv_stack_op,
299 static struct machine_function *frv_init_machine_status (void);
300 static rtx frv_int_to_acc (enum insn_code, int, rtx);
301 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
302 static rtx frv_read_argument (tree, unsigned int);
303 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
304 static int frv_check_constant_argument (enum insn_code, int, rtx);
305 static rtx frv_legitimize_target (enum insn_code, rtx);
306 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
307 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
308 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
309 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
310 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
311 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
312 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
313 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
314 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
315 static rtx frv_expand_int_void2arg (enum insn_code, tree);
316 static rtx frv_expand_prefetches (enum insn_code, tree);
317 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
318 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
319 static rtx frv_expand_mclracc_builtin (tree);
320 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
321 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
322 static rtx frv_expand_noargs_builtin (enum insn_code);
323 static void frv_split_iacc_move (rtx, rtx);
324 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
325 static int frv_clear_registers_used (rtx *, void *);
326 static void frv_ifcvt_add_insn (rtx, rtx, int);
327 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
328 static rtx frv_ifcvt_load_value (rtx, rtx);
329 static int frv_acc_group_1 (rtx *, void *);
330 static unsigned int frv_insn_unit (rtx);
331 static bool frv_issues_to_branch_unit_p (rtx);
332 static int frv_cond_flags (rtx);
333 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
334 static int frv_registers_conflict_p_1 (rtx *, void *);
335 static bool frv_registers_conflict_p (rtx);
336 static void frv_registers_update_1 (rtx, const_rtx, void *);
337 static void frv_registers_update (rtx);
338 static void frv_start_packet (void);
339 static void frv_start_packet_block (void);
340 static void frv_finish_packet (void (*) (void));
341 static bool frv_pack_insn_p (rtx);
342 static void frv_add_insn_to_packet (rtx);
343 static void frv_insert_nop_in_packet (rtx);
344 static bool frv_for_each_packet (void (*) (void));
345 static bool frv_sort_insn_group_1 (enum frv_insn_group,
346 unsigned int, unsigned int,
347 unsigned int, unsigned int,
349 static int frv_compare_insns (const void *, const void *);
350 static void frv_sort_insn_group (enum frv_insn_group);
351 static void frv_reorder_packet (void);
352 static void frv_fill_unused_units (enum frv_insn_group);
353 static void frv_align_label (void);
354 static void frv_reorg_packet (void);
355 static void frv_register_nop (rtx);
356 static void frv_reorg (void);
357 static void frv_pack_insns (void);
358 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
359 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
360 static bool frv_assemble_integer (rtx, unsigned, int);
361 static void frv_init_builtins (void);
362 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
363 static void frv_init_libfuncs (void);
364 static bool frv_in_small_data_p (const_tree);
365 static void frv_asm_output_mi_thunk
366 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
367 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
370 static rtx frv_expand_builtin_saveregs (void);
371 static void frv_expand_builtin_va_start (tree, rtx);
372 static bool frv_rtx_costs (rtx, int, int, int*, bool);
373 static void frv_asm_out_constructor (rtx, int);
374 static void frv_asm_out_destructor (rtx, int);
375 static bool frv_function_symbol_referenced_p (rtx);
376 static bool frv_cannot_force_const_mem (rtx);
377 static const char *unspec_got_name (int);
378 static void frv_output_const_unspec (FILE *,
379 const struct frv_unspec *);
380 static bool frv_function_ok_for_sibcall (tree, tree);
381 static rtx frv_struct_value_rtx (tree, int);
382 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
383 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
385 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
387 static bool frv_secondary_reload (bool, rtx, enum reg_class,
389 secondary_reload_info *);
390 static bool frv_frame_pointer_required (void);
391 static bool frv_can_eliminate (const int, const int);
392 static void frv_trampoline_init (rtx, tree, rtx);
394 /* Allow us to easily change the default for -malloc-cc. */
395 #ifndef DEFAULT_NO_ALLOC_CC
396 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
398 #define MASK_DEFAULT_ALLOC_CC 0
401 /* Initialize the GCC target structure. */
402 #undef TARGET_PRINT_OPERAND
403 #define TARGET_PRINT_OPERAND frv_print_operand
404 #undef TARGET_PRINT_OPERAND_ADDRESS
405 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
406 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
407 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
408 #undef TARGET_ASM_FUNCTION_PROLOGUE
409 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
410 #undef TARGET_ASM_FUNCTION_EPILOGUE
411 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
412 #undef TARGET_ASM_INTEGER
413 #define TARGET_ASM_INTEGER frv_assemble_integer
414 #undef TARGET_DEFAULT_TARGET_FLAGS
415 #define TARGET_DEFAULT_TARGET_FLAGS \
416 (MASK_DEFAULT_ALLOC_CC \
423 #undef TARGET_HANDLE_OPTION
424 #define TARGET_HANDLE_OPTION frv_handle_option
425 #undef TARGET_INIT_BUILTINS
426 #define TARGET_INIT_BUILTINS frv_init_builtins
427 #undef TARGET_EXPAND_BUILTIN
428 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
429 #undef TARGET_INIT_LIBFUNCS
430 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
431 #undef TARGET_IN_SMALL_DATA_P
432 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
433 #undef TARGET_RTX_COSTS
434 #define TARGET_RTX_COSTS frv_rtx_costs
435 #undef TARGET_ASM_CONSTRUCTOR
436 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
437 #undef TARGET_ASM_DESTRUCTOR
438 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
440 #undef TARGET_ASM_OUTPUT_MI_THUNK
441 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
442 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
443 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
445 #undef TARGET_SCHED_ISSUE_RATE
446 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
448 #undef TARGET_LEGITIMIZE_ADDRESS
449 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
451 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
452 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
453 #undef TARGET_CANNOT_FORCE_CONST_MEM
454 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
456 #undef TARGET_HAVE_TLS
457 #define TARGET_HAVE_TLS HAVE_AS_TLS
459 #undef TARGET_STRUCT_VALUE_RTX
460 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
461 #undef TARGET_MUST_PASS_IN_STACK
462 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
463 #undef TARGET_PASS_BY_REFERENCE
464 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
465 #undef TARGET_ARG_PARTIAL_BYTES
466 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
468 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
469 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
470 #undef TARGET_SETUP_INCOMING_VARARGS
471 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
472 #undef TARGET_MACHINE_DEPENDENT_REORG
473 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
475 #undef TARGET_EXPAND_BUILTIN_VA_START
476 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
479 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
480 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
483 #undef TARGET_SECONDARY_RELOAD
484 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
486 #undef TARGET_LEGITIMATE_ADDRESS_P
487 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
489 #undef TARGET_FRAME_POINTER_REQUIRED
490 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
492 #undef TARGET_CAN_ELIMINATE
493 #define TARGET_CAN_ELIMINATE frv_can_eliminate
495 #undef TARGET_TRAMPOLINE_INIT
496 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
498 #undef TARGET_FUNCTION_VALUE
499 #define TARGET_FUNCTION_VALUE frv_function_value
500 #undef TARGET_LIBCALL_VALUE
501 #define TARGET_LIBCALL_VALUE frv_libcall_value
503 struct gcc_target targetm = TARGET_INITIALIZER;
505 #define FRV_SYMBOL_REF_TLS_P(RTX) \
506 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
509 /* Any function call that satisfies the machine-independent
510 requirements is eligible on FR-V. */
513 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
514 tree exp ATTRIBUTE_UNUSED)
519 /* Return true if SYMBOL is a small data symbol and relocation RELOC
520 can be used to access it directly in a load or store. */
522 static FRV_INLINE bool
523 frv_small_data_reloc_p (rtx symbol, int reloc)
525 return (GET_CODE (symbol) == SYMBOL_REF
526 && SYMBOL_REF_SMALL_P (symbol)
527 && (!TARGET_FDPIC || flag_pic == 1)
528 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
531 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
535 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
537 if (GET_CODE (x) == CONST)
541 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
543 unspec->offset += INTVAL (XEXP (x, 1));
546 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
548 unspec->symbol = XVECEXP (x, 0, 0);
549 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
551 if (unspec->offset == 0)
554 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
555 && unspec->offset > 0
556 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
563 /* Decide whether we can force certain constants to memory. If we
564 decide we can't, the caller should be able to cope with it in
567 We never allow constants to be forced into memory for TARGET_FDPIC.
568 This is necessary for several reasons:
570 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
571 target-independent code will try to force them into the constant
572 pool, thus leading to infinite recursion.
574 2. We can never introduce new constant pool references during reload.
575 Any such reference would require use of the pseudo FDPIC register.
577 3. We can't represent a constant added to a function pointer (which is
578 not the same as a pointer to a function+constant).
580 4. In many cases, it's more efficient to calculate the constant in-line. */
583 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
588 /* Implement TARGET_HANDLE_OPTION. */
591 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
596 if (strcmp (arg, "simple") == 0)
597 frv_cpu_type = FRV_CPU_SIMPLE;
598 else if (strcmp (arg, "tomcat") == 0)
599 frv_cpu_type = FRV_CPU_TOMCAT;
600 else if (strcmp (arg, "fr550") == 0)
601 frv_cpu_type = FRV_CPU_FR550;
602 else if (strcmp (arg, "fr500") == 0)
603 frv_cpu_type = FRV_CPU_FR500;
604 else if (strcmp (arg, "fr450") == 0)
605 frv_cpu_type = FRV_CPU_FR450;
606 else if (strcmp (arg, "fr405") == 0)
607 frv_cpu_type = FRV_CPU_FR405;
608 else if (strcmp (arg, "fr400") == 0)
609 frv_cpu_type = FRV_CPU_FR400;
610 else if (strcmp (arg, "fr300") == 0)
611 frv_cpu_type = FRV_CPU_FR300;
612 else if (strcmp (arg, "frv") == 0)
613 frv_cpu_type = FRV_CPU_GENERIC;
624 frv_default_flags_for_cpu (void)
626 switch (frv_cpu_type)
628 case FRV_CPU_GENERIC:
629 return MASK_DEFAULT_FRV;
632 return MASK_DEFAULT_FR550;
636 return MASK_DEFAULT_FR500;
639 return MASK_DEFAULT_FR450;
643 return MASK_DEFAULT_FR400;
647 return MASK_DEFAULT_SIMPLE;
654 /* Sometimes certain combinations of command options do not make
655 sense on a particular target machine. You can define a macro
656 `OVERRIDE_OPTIONS' to take account of this. This macro, if
657 defined, is executed once just after all the command options have
660 Don't use this macro to turn on various extra optimizations for
661 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
664 frv_override_options (void)
669 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
671 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
672 linker about linking pic and non-pic code. */
675 if (!flag_pic) /* -fPIC */
678 if (! g_switch_set) /* -G0 */
685 /* A C expression whose value is a register class containing hard
686 register REGNO. In general there is more than one such class;
687 choose a class which is "minimal", meaning that no smaller class
688 also contains the register. */
690 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
692 enum reg_class rclass;
696 int gpr_reg = regno - GPR_FIRST;
698 if (gpr_reg == GR8_REG)
701 else if (gpr_reg == GR9_REG)
704 else if (gpr_reg == GR14_REG)
705 rclass = FDPIC_FPTR_REGS;
707 else if (gpr_reg == FDPIC_REGNO)
710 else if ((gpr_reg & 3) == 0)
713 else if ((gpr_reg & 1) == 0)
720 else if (FPR_P (regno))
722 int fpr_reg = regno - GPR_FIRST;
723 if ((fpr_reg & 3) == 0)
724 rclass = QUAD_FPR_REGS;
726 else if ((fpr_reg & 1) == 0)
733 else if (regno == LR_REGNO)
736 else if (regno == LCR_REGNO)
739 else if (ICC_P (regno))
742 else if (FCC_P (regno))
745 else if (ICR_P (regno))
748 else if (FCR_P (regno))
751 else if (ACC_P (regno))
753 int r = regno - ACC_FIRST;
755 rclass = QUAD_ACC_REGS;
756 else if ((r & 1) == 0)
757 rclass = EVEN_ACC_REGS;
762 else if (ACCG_P (regno))
768 regno_reg_class[regno] = rclass;
771 /* Check for small data option */
773 g_switch_value = SDATA_DEFAULT_SIZE;
775 /* A C expression which defines the machine-dependent operand
776 constraint letters for register classes. If CHAR is such a
777 letter, the value should be the register class corresponding to
778 it. Otherwise, the value should be `NO_REGS'. The register
779 letter `r', corresponding to class `GENERAL_REGS', will not be
780 passed to this macro; you do not need to handle it.
782 The following letters are unavailable, due to being used as
787 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
788 'Q', 'R', 'S', 'T', 'U'
790 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
792 for (i = 0; i < 256; i++)
793 reg_class_from_letter[i] = NO_REGS;
795 reg_class_from_letter['a'] = ACC_REGS;
796 reg_class_from_letter['b'] = EVEN_ACC_REGS;
797 reg_class_from_letter['c'] = CC_REGS;
798 reg_class_from_letter['d'] = GPR_REGS;
799 reg_class_from_letter['e'] = EVEN_REGS;
800 reg_class_from_letter['f'] = FPR_REGS;
801 reg_class_from_letter['h'] = FEVEN_REGS;
802 reg_class_from_letter['l'] = LR_REG;
803 reg_class_from_letter['q'] = QUAD_REGS;
804 reg_class_from_letter['t'] = ICC_REGS;
805 reg_class_from_letter['u'] = FCC_REGS;
806 reg_class_from_letter['v'] = ICR_REGS;
807 reg_class_from_letter['w'] = FCR_REGS;
808 reg_class_from_letter['x'] = QUAD_FPR_REGS;
809 reg_class_from_letter['y'] = LCR_REG;
810 reg_class_from_letter['z'] = SPR_REGS;
811 reg_class_from_letter['A'] = QUAD_ACC_REGS;
812 reg_class_from_letter['B'] = ACCG_REGS;
813 reg_class_from_letter['C'] = CR_REGS;
814 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
815 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
817 /* There is no single unaligned SI op for PIC code. Sometimes we
818 need to use ".4byte" and sometimes we need to use ".picptr".
819 See frv_assemble_integer for details. */
820 if (flag_pic || TARGET_FDPIC)
821 targetm.asm_out.unaligned_op.si = 0;
823 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
824 target_flags |= MASK_LINKED_FP;
826 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
827 target_flags |= MASK_OPTIMIZE_MEMBAR;
829 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
830 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
832 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
833 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
835 init_machine_status = frv_init_machine_status;
839 /* Some machines may desire to change what optimizations are performed for
840 various optimization levels. This macro, if defined, is executed once just
841 after the optimization level is determined and before the remainder of the
842 command options have been parsed. Values set in this macro are used as the
843 default values for the other command line options.
845 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
846 `-O' is specified, and 0 if neither is specified.
848 SIZE is nonzero if `-Os' is specified, 0 otherwise.
850 You should not use this macro to change options that are not
851 machine-specific. These should uniformly selected by the same optimization
852 level on all supported machines. Use this macro to enable machine-specific
855 *Do not examine `write_symbols' in this macro!* The debugging options are
856 *not supposed to alter the generated code. */
858 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
859 scheduling pass at the current time. */
861 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
865 #ifdef DISABLE_SCHED2
866 flag_schedule_insns_after_reload = 0;
875 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
878 frv_string_begins_with (const_tree name, const char *prefix)
880 const int prefix_len = strlen (prefix);
882 /* Remember: NAME's length includes the null terminator. */
883 return (TREE_STRING_LENGTH (name) > prefix_len
884 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
887 /* Zero or more C statements that may conditionally modify two variables
888 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
889 been initialized from the two preceding macros.
891 This is necessary in case the fixed or call-clobbered registers depend on
894 You need not define this macro if it has no work to do.
896 If the usage of an entire class of registers depends on the target flags,
897 you may indicate this to GCC by using this macro to modify `fixed_regs' and
898 `call_used_regs' to 1 for each of the registers in the classes which should
899 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
900 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
902 (However, if this class is not included in `GENERAL_REGS' and all of the
903 insn patterns whose constraints permit this class are controlled by target
904 switches, then GCC will automatically avoid using these registers when the
905 target switches are opposed to them.) */
908 frv_conditional_register_usage (void)
912 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
913 fixed_regs[i] = call_used_regs[i] = 1;
915 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
916 fixed_regs[i] = call_used_regs[i] = 1;
918 /* Reserve the registers used for conditional execution. At present, we need
919 1 ICC and 1 ICR register. */
920 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
921 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
925 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
926 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
927 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
928 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
932 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
933 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
936 /* If -fpic, SDA_BASE_REG is the PIC register. */
937 if (g_switch_value == 0 && !flag_pic)
938 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
941 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
947 * Compute the stack frame layout
950 * +---------------+-----------------------+-----------------------+
951 * |Register |type |caller-save/callee-save|
952 * +---------------+-----------------------+-----------------------+
953 * |GR0 |Zero register | - |
954 * |GR1 |Stack pointer(SP) | - |
955 * |GR2 |Frame pointer(FP) | - |
956 * |GR3 |Hidden parameter | caller save |
957 * |GR4-GR7 | - | caller save |
958 * |GR8-GR13 |Argument register | caller save |
959 * |GR14-GR15 | - | caller save |
960 * |GR16-GR31 | - | callee save |
961 * |GR32-GR47 | - | caller save |
962 * |GR48-GR63 | - | callee save |
963 * |FR0-FR15 | - | caller save |
964 * |FR16-FR31 | - | callee save |
965 * |FR32-FR47 | - | caller save |
966 * |FR48-FR63 | - | callee save |
967 * +---------------+-----------------------+-----------------------+
971 * SP-> |-----------------------------------|
973 * |-----------------------------------|
974 * | Register save area |
975 * |-----------------------------------|
976 * | Local variable save area |
977 * FP-> |-----------------------------------|
979 * |-----------------------------------|
980 * | Hidden parameter save area |
981 * |-----------------------------------|
982 * | Return address(LR) storage area |
983 * |-----------------------------------|
984 * | Padding for alignment |
985 * |-----------------------------------|
986 * | Register argument area |
987 * OLD SP-> |-----------------------------------|
989 * |-----------------------------------|
992 * Argument area/Parameter area:
994 * When a function is called, this area is used for argument transfer. When
995 * the argument is set up by the caller function, this area is referred to as
996 * the argument area. When the argument is referenced by the callee function,
997 * this area is referred to as the parameter area. The area is allocated when
998 * all arguments cannot be placed on the argument register at the time of
1001 * Register save area:
1003 * This is a register save area that must be guaranteed for the caller
1004 * function. This area is not secured when the register save operation is not
1007 * Local variable save area:
1009 * This is the area for local variables and temporary variables.
1013 * This area stores the FP value of the caller function.
1015 * Hidden parameter save area:
1017 * This area stores the start address of the return value storage
1018 * area for a struct/union return function.
1019 * When a struct/union is used as the return value, the caller
1020 * function stores the return value storage area start address in
1021 * register GR3 and passes it to the caller function.
1022 * The callee function interprets the address stored in the GR3
1023 * as the return value storage area start address.
1024 * When register GR3 needs to be saved into memory, the callee
1025 * function saves it in the hidden parameter save area. This
1026 * area is not secured when the save operation is not needed.
1028 * Return address(LR) storage area:
1030 * This area saves the LR. The LR stores the address of a return to the caller
1031 * function for the purpose of function calling.
1033 * Argument register area:
1035 * This area saves the argument register. This area is not secured when the
1036 * save operation is not needed.
1040 * Arguments, the count of which equals the count of argument registers (6
1041 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1042 * function. When a struct/union return function is called, the return value
1043 * area address is stored in register GR3. Arguments not placed in the
1044 * argument registers will be stored in the stack argument area for transfer
1045 * purposes. When an 8-byte type argument is to be delivered using registers,
1046 * it is divided into two and placed in two registers for transfer. When
1047 * argument registers must be saved to memory, the callee function secures an
1048 * argument register save area in the stack. In this case, a continuous
1049 * argument register save area must be established in the parameter area. The
1050 * argument register save area must be allocated as needed to cover the size of
1051 * the argument register to be saved. If the function has a variable count of
1052 * arguments, it saves all argument registers in the argument register save
1055 * Argument Extension Format:
1057 * When an argument is to be stored in the stack, its type is converted to an
1058 * extended type in accordance with the individual argument type. The argument
1059 * is freed by the caller function after the return from the callee function is
1062 * +-----------------------+---------------+------------------------+
1063 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1064 * +-----------------------+---------------+------------------------+
1066 * |signed char |int | 4 |
1067 * |unsigned char |int | 4 |
1068 * |[signed] short int |int | 4 |
1069 * |unsigned short int |int | 4 |
1070 * |[signed] int |No extension | 4 |
1071 * |unsigned int |No extension | 4 |
1072 * |[signed] long int |No extension | 4 |
1073 * |unsigned long int |No extension | 4 |
1074 * |[signed] long long int |No extension | 8 |
1075 * |unsigned long long int |No extension | 8 |
1076 * |float |double | 8 |
1077 * |double |No extension | 8 |
1078 * |long double |No extension | 8 |
1079 * |pointer |No extension | 4 |
1080 * |struct/union |- | 4 (*1) |
1081 * +-----------------------+---------------+------------------------+
1083 * When a struct/union is to be delivered as an argument, the caller copies it
1084 * to the local variable area and delivers the address of that area.
1088 * +-------------------------------+----------------------+
1089 * |Return Value Type |Return Value Interface|
1090 * +-------------------------------+----------------------+
1092 * |[signed|unsigned] char |GR8 |
1093 * |[signed|unsigned] short int |GR8 |
1094 * |[signed|unsigned] int |GR8 |
1095 * |[signed|unsigned] long int |GR8 |
1097 * |[signed|unsigned] long long int|GR8 & GR9 |
1099 * |double |GR8 & GR9 |
1100 * |long double |GR8 & GR9 |
1101 * |struct/union |(*1) |
1102 * +-------------------------------+----------------------+
1104 * When a struct/union is used as the return value, the caller function stores
1105 * the start address of the return value storage area into GR3 and then passes
1106 * it to the callee function. The callee function interprets GR3 as the start
1107 * address of the return value storage area. When this address needs to be
1108 * saved in memory, the callee function secures the hidden parameter save area
1109 * and saves the address in that area.
1113 frv_stack_info (void)
1115 static frv_stack_t info, zero_info;
1116 frv_stack_t *info_ptr = &info;
1117 tree fndecl = current_function_decl;
1125 /* If we've already calculated the values and reload is complete,
1127 if (frv_stack_cache)
1128 return frv_stack_cache;
1130 /* Zero all fields. */
1133 /* Set up the register range information. */
1134 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1135 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1136 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1137 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1139 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1140 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1141 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1142 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1144 info_ptr->regs[STACK_REGS_LR].name = "lr";
1145 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1146 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1147 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1149 info_ptr->regs[STACK_REGS_CC].name = "cc";
1150 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1151 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1152 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1154 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1155 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1156 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1158 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1159 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1160 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1161 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1162 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1164 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1165 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1166 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1167 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1169 info_ptr->regs[STACK_REGS_FP].name = "fp";
1170 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1171 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1172 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1174 /* Determine if this is a stdarg function. If so, allocate space to store
1181 /* Find the last argument, and see if it is __builtin_va_alist. */
1182 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1184 next_arg = TREE_CHAIN (cur_arg);
1185 if (next_arg == (tree)0)
1187 if (DECL_NAME (cur_arg)
1188 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1196 /* Iterate over all of the register ranges. */
1197 for (range = 0; range < STACK_REGS_MAX; range++)
1199 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1200 int first = reg_ptr->first;
1201 int last = reg_ptr->last;
1203 int size_2words = 0;
1206 /* Calculate which registers need to be saved & save area size. */
1210 for (regno = first; regno <= last; regno++)
1212 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1213 || (crtl->calls_eh_return
1214 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1215 || (!TARGET_FDPIC && flag_pic
1216 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1218 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1219 size_1word += UNITS_PER_WORD;
1224 /* Calculate whether we need to create a frame after everything else
1225 has been processed. */
1230 if (df_regs_ever_live_p (LR_REGNO)
1232 /* This is set for __builtin_return_address, etc. */
1233 || cfun->machine->frame_needed
1234 || (TARGET_LINKED_FP && frame_pointer_needed)
1235 || (!TARGET_FDPIC && flag_pic
1236 && crtl->uses_pic_offset_table))
1238 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1239 size_1word += UNITS_PER_WORD;
1243 case STACK_REGS_STDARG:
1246 /* If this is a stdarg function with a non varardic
1247 argument split between registers and the stack,
1248 adjust the saved registers downward. */
1249 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1252 for (regno = first; regno <= last; regno++)
1254 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1255 size_1word += UNITS_PER_WORD;
1258 info_ptr->stdarg_size = size_1word;
1262 case STACK_REGS_STRUCT:
1263 if (cfun->returns_struct)
1265 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1266 size_1word += UNITS_PER_WORD;
1274 /* If this is a field, it only takes one word. */
1275 if (reg_ptr->field_p)
1276 size_1word = UNITS_PER_WORD;
1278 /* Determine which register pairs can be saved together. */
1279 else if (reg_ptr->dword_p && TARGET_DWORD)
1281 for (regno = first; regno < last; regno += 2)
1283 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1285 size_2words += 2 * UNITS_PER_WORD;
1286 size_1word -= 2 * UNITS_PER_WORD;
1287 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1288 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1293 reg_ptr->size_1word = size_1word;
1294 reg_ptr->size_2words = size_2words;
1296 if (! reg_ptr->special_p)
1298 info_ptr->regs_size_1word += size_1word;
1299 info_ptr->regs_size_2words += size_2words;
1304 /* Set up the sizes of each each field in the frame body, making the sizes
1305 of each be divisible by the size of a dword if dword operations might
1306 be used, or the size of a word otherwise. */
1307 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1309 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1310 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1311 + info_ptr->regs_size_1word,
1313 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1315 info_ptr->pretend_size = crtl->args.pretend_args_size;
1317 /* Work out the size of the frame, excluding the header. Both the frame
1318 body and register parameter area will be dword-aligned. */
1319 info_ptr->total_size
1320 = (ADDR_ALIGN (info_ptr->parameter_size
1321 + info_ptr->regs_size
1322 + info_ptr->vars_size,
1324 + ADDR_ALIGN (info_ptr->pretend_size
1325 + info_ptr->stdarg_size,
1326 2 * UNITS_PER_WORD));
1328 /* See if we need to create a frame at all, if so add header area. */
1329 if (info_ptr->total_size > 0
1330 || frame_pointer_needed
1331 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1332 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1334 offset = info_ptr->parameter_size;
1335 info_ptr->header_size = 4 * UNITS_PER_WORD;
1336 info_ptr->total_size += 4 * UNITS_PER_WORD;
1338 /* Calculate the offsets to save normal register pairs. */
1339 for (range = 0; range < STACK_REGS_MAX; range++)
1341 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1342 if (! reg_ptr->special_p)
1344 int first = reg_ptr->first;
1345 int last = reg_ptr->last;
1348 for (regno = first; regno <= last; regno++)
1349 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1350 && regno != FRAME_POINTER_REGNUM
1351 && (regno < FIRST_ARG_REGNUM
1352 || regno > LAST_ARG_REGNUM))
1354 info_ptr->reg_offset[regno] = offset;
1355 offset += 2 * UNITS_PER_WORD;
1360 /* Calculate the offsets to save normal single registers. */
1361 for (range = 0; range < STACK_REGS_MAX; range++)
1363 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1364 if (! reg_ptr->special_p)
1366 int first = reg_ptr->first;
1367 int last = reg_ptr->last;
1370 for (regno = first; regno <= last; regno++)
1371 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1372 && regno != FRAME_POINTER_REGNUM
1373 && (regno < FIRST_ARG_REGNUM
1374 || regno > LAST_ARG_REGNUM))
1376 info_ptr->reg_offset[regno] = offset;
1377 offset += UNITS_PER_WORD;
1382 /* Calculate the offset to save the local variables at. */
1383 offset = ADDR_ALIGN (offset, alignment);
1384 if (info_ptr->vars_size)
1386 info_ptr->vars_offset = offset;
1387 offset += info_ptr->vars_size;
1390 /* Align header to a dword-boundary. */
1391 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1393 /* Calculate the offsets in the fixed frame. */
1394 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1395 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1396 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1398 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1399 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1400 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1402 if (cfun->returns_struct)
1404 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1405 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1406 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1409 /* Calculate the offsets to store the arguments passed in registers
1410 for stdarg functions. The register pairs are first and the single
1411 register if any is last. The register save area starts on a
1413 if (info_ptr->stdarg_size)
1415 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1416 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1419 /* Skip the header. */
1420 offset += 4 * UNITS_PER_WORD;
1421 for (regno = first; regno <= last; regno++)
1423 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1425 info_ptr->reg_offset[regno] = offset;
1426 offset += 2 * UNITS_PER_WORD;
1428 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1430 info_ptr->reg_offset[regno] = offset;
1431 offset += UNITS_PER_WORD;
1437 if (reload_completed)
1438 frv_stack_cache = info_ptr;
1444 /* Print the information about the frv stack offsets, etc. when debugging. */
1447 frv_debug_stack (frv_stack_t *info)
1452 info = frv_stack_info ();
1454 fprintf (stderr, "\nStack information for function %s:\n",
1455 ((current_function_decl && DECL_NAME (current_function_decl))
1456 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1459 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1460 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1461 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1462 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1463 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1465 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1466 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1467 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1468 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1470 for (range = 0; range < STACK_REGS_MAX; range++)
1472 frv_stack_regs_t *regs = &(info->regs[range]);
1473 if ((regs->size_1word + regs->size_2words) > 0)
1475 int first = regs->first;
1476 int last = regs->last;
1479 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1480 regs->name, regs->size_1word + regs->size_2words,
1481 regs->size_1word, regs->size_2words);
1483 for (regno = first; regno <= last; regno++)
1485 if (info->save_p[regno] == REG_SAVE_1WORD)
1486 fprintf (stderr, " %s (%d)", reg_names[regno],
1487 info->reg_offset[regno]);
1489 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1490 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1491 reg_names[regno+1], info->reg_offset[regno]);
1494 fputc ('\n', stderr);
1504 /* Used during final to control the packing of insns. The value is
1505 1 if the current instruction should be packed with the next one,
1506 0 if it shouldn't or -1 if packing is disabled altogether. */
1508 static int frv_insn_packing_flag;
1510 /* True if the current function contains a far jump. */
1513 frv_function_contains_far_jump (void)
1515 rtx insn = get_insns ();
1517 && !(GET_CODE (insn) == JUMP_INSN
1518 /* Ignore tablejump patterns. */
1519 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1520 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1521 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1522 insn = NEXT_INSN (insn);
1523 return (insn != NULL);
1526 /* For the FRV, this function makes sure that a function with far jumps
1527 will return correctly. It also does the VLIW packing. */
1530 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1532 /* If no frame was created, check whether the function uses a call
1533 instruction to implement a far jump. If so, save the link in gr3 and
1534 replace all returns to LR with returns to GR3. GR3 is used because it
1535 is call-clobbered, because is not available to the register allocator,
1536 and because all functions that take a hidden argument pointer will have
1538 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1542 /* Just to check that the above comment is true. */
1543 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1545 /* Generate the instruction that saves the link register. */
1546 fprintf (file, "\tmovsg lr,gr3\n");
1548 /* Replace the LR with GR3 in *return_internal patterns. The insn
1549 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1550 simply emit a different assembly directive because bralr and jmpl
1551 execute in different units. */
1552 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1553 if (GET_CODE (insn) == JUMP_INSN)
1555 rtx pattern = PATTERN (insn);
1556 if (GET_CODE (pattern) == PARALLEL
1557 && XVECLEN (pattern, 0) >= 2
1558 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1559 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1561 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1562 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1563 SET_REGNO (address, GPR_FIRST + 3);
1570 /* Allow the garbage collector to free the nops created by frv_reorg. */
1571 memset (frv_nops, 0, sizeof (frv_nops));
1575 /* Return the next available temporary register in a given class. */
1578 frv_alloc_temp_reg (
1579 frv_tmp_reg_t *info, /* which registers are available */
1580 enum reg_class rclass, /* register class desired */
1581 enum machine_mode mode, /* mode to allocate register with */
1582 int mark_as_used, /* register not available after allocation */
1583 int no_abort) /* return NULL instead of aborting */
1585 int regno = info->next_reg[ (int)rclass ];
1586 int orig_regno = regno;
1587 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1592 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1593 && TEST_HARD_REG_BIT (info->regs, regno))
1596 if (++regno >= FIRST_PSEUDO_REGISTER)
1598 if (regno == orig_regno)
1600 gcc_assert (no_abort);
1605 nr = HARD_REGNO_NREGS (regno, mode);
1606 info->next_reg[ (int)rclass ] = regno + nr;
1609 for (i = 0; i < nr; i++)
1610 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1612 return gen_rtx_REG (mode, regno);
1616 /* Return an rtx with the value OFFSET, which will either be a register or a
1617 signed 12-bit integer. It can be used as the second operand in an "add"
1618 instruction, or as the index in a load or store.
1620 The function returns a constant rtx if OFFSET is small enough, otherwise
1621 it loads the constant into register OFFSET_REGNO and returns that. */
1623 frv_frame_offset_rtx (int offset)
1625 rtx offset_rtx = GEN_INT (offset);
1626 if (IN_RANGE_P (offset, -2048, 2047))
1630 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1631 if (IN_RANGE_P (offset, -32768, 32767))
1632 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1635 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1636 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1642 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1643 prologue and epilogue uses such expressions to access the stack. */
1645 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1647 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1649 frv_frame_offset_rtx (offset)));
1652 /* Generate a frame-related expression:
1654 (set REG (mem (plus (sp) (const_int OFFSET)))).
1656 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1657 instructions. Marking the expressions as frame-related is superfluous if
1658 the note contains just a single set. But if the note contains a PARALLEL
1659 or SEQUENCE that has several sets, each set must be individually marked
1660 as frame-related. */
1662 frv_dwarf_store (rtx reg, int offset)
1664 rtx set = gen_rtx_SET (VOIDmode,
1665 gen_rtx_MEM (GET_MODE (reg),
1666 plus_constant (stack_pointer_rtx,
1669 RTX_FRAME_RELATED_P (set) = 1;
1673 /* Emit a frame-related instruction whose pattern is PATTERN. The
1674 instruction is the last in a sequence that cumulatively performs the
1675 operation described by DWARF_PATTERN. The instruction is marked as
1676 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1679 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1681 rtx insn = emit_insn (pattern);
1682 RTX_FRAME_RELATED_P (insn) = 1;
1683 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1688 /* Emit instructions that transfer REG to or from the memory location (sp +
1689 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1690 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1691 function to store registers and only the epilogue uses it to load them.
1693 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1694 The generated instruction will use BASE as its base register. BASE may
1695 simply be the stack pointer, but if several accesses are being made to a
1696 region far away from the stack pointer, it may be more efficient to set
1697 up a temporary instead.
1699 Store instructions will be frame-related and will be annotated with the
1700 overall effect of the store. Load instructions will be followed by a
1701 (use) to prevent later optimizations from zapping them.
1703 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1704 as a temporary in such cases. */
1706 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1708 enum machine_mode mode = GET_MODE (reg);
1709 rtx mem = frv_frame_mem (mode,
1711 stack_offset - accessor->base_offset);
1713 if (accessor->op == FRV_LOAD)
1715 if (SPR_P (REGNO (reg)))
1717 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1718 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1719 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1723 /* We cannot use reg+reg addressing for DImode access. */
1725 && GET_CODE (XEXP (mem, 0)) == PLUS
1726 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1727 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1729 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1730 rtx insn = emit_move_insn (temp,
1731 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1732 XEXP (XEXP (mem, 0), 1)));
1733 mem = gen_rtx_MEM (DImode, temp);
1735 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1741 if (SPR_P (REGNO (reg)))
1743 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1744 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1745 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1746 frv_dwarf_store (reg, stack_offset));
1748 else if (mode == DImode)
1750 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1751 with a separate save for each register. */
1752 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1753 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1754 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1755 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1757 /* Also we cannot use reg+reg addressing. */
1758 if (GET_CODE (XEXP (mem, 0)) == PLUS
1759 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1760 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1762 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1763 rtx insn = emit_move_insn (temp,
1764 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1765 XEXP (XEXP (mem, 0), 1)));
1766 mem = gen_rtx_MEM (DImode, temp);
1769 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1770 gen_rtx_PARALLEL (VOIDmode,
1771 gen_rtvec (2, set1, set2)));
1774 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1775 frv_dwarf_store (reg, stack_offset));
1779 /* A function that uses frv_frame_access to transfer a group of registers to
1780 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1781 is the stack information generated by frv_stack_info, and REG_SET is the
1782 number of the register set to transfer. */
1784 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1788 frv_stack_regs_t *regs_info;
1791 regs_info = &info->regs[reg_set];
1792 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1793 if (info->save_p[regno])
1794 frv_frame_access (accessor,
1795 info->save_p[regno] == REG_SAVE_2WORDS
1796 ? gen_rtx_REG (DImode, regno)
1797 : gen_rtx_REG (SImode, regno),
1798 info->reg_offset[regno]);
1801 /* Save or restore callee-saved registers that are kept outside the frame
1802 header. The function saves the registers if OP is FRV_STORE and restores
1803 them if OP is FRV_LOAD. INFO is the stack information generated by
1806 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1808 frv_frame_accessor_t accessor;
1811 accessor.base = stack_pointer_rtx;
1812 accessor.base_offset = 0;
1813 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1814 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1815 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1819 /* Called after register allocation to add any instructions needed for the
1820 prologue. Using a prologue insn is favored compared to putting all of the
1821 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1822 it allows the scheduler to intermix instructions with the saves of
1823 the caller saved registers. In some cases, it might be necessary
1824 to emit a barrier instruction as the last insn to prevent such
1827 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1828 so that the debug info generation code can handle them properly. */
1830 frv_expand_prologue (void)
1832 frv_stack_t *info = frv_stack_info ();
1833 rtx sp = stack_pointer_rtx;
1834 rtx fp = frame_pointer_rtx;
1835 frv_frame_accessor_t accessor;
1837 if (TARGET_DEBUG_STACK)
1838 frv_debug_stack (info);
1840 if (info->total_size == 0)
1843 /* We're interested in three areas of the frame here:
1845 A: the register save area
1847 C: the header after B
1849 If the frame pointer isn't used, we'll have to set up A, B and C
1850 using the stack pointer. If the frame pointer is used, we'll access
1854 B: set up using sp or a temporary (see below)
1857 We set up B using the stack pointer if the frame is small enough.
1858 Otherwise, it's more efficient to copy the old stack pointer into a
1859 temporary and use that.
1861 Note that it's important to make sure the prologue and epilogue use the
1862 same registers to access A and C, since doing otherwise will confuse
1863 the aliasing code. */
1865 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1866 isn't used, the same method will serve for C. */
1867 accessor.op = FRV_STORE;
1868 if (frame_pointer_needed && info->total_size > 2048)
1872 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1873 accessor.base_offset = info->total_size;
1874 insn = emit_insn (gen_movsi (accessor.base, sp));
1878 accessor.base = stack_pointer_rtx;
1879 accessor.base_offset = 0;
1882 /* Allocate the stack space. */
1884 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1885 rtx dwarf_offset = GEN_INT (-info->total_size);
1887 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1890 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1893 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1894 and point the new one to that location. */
1895 if (frame_pointer_needed)
1897 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1899 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1900 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1902 rtx asm_src = plus_constant (accessor.base,
1903 fp_offset - accessor.base_offset);
1904 rtx dwarf_src = plus_constant (sp, fp_offset);
1906 /* Store the old frame pointer at (sp + FP_OFFSET). */
1907 frv_frame_access (&accessor, fp, fp_offset);
1909 /* Set up the new frame pointer. */
1910 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1911 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1913 /* Access region C from the frame pointer. */
1915 accessor.base_offset = fp_offset;
1918 /* Set up region C. */
1919 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1920 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1921 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1923 /* Set up region A. */
1924 frv_frame_access_standard_regs (FRV_STORE, info);
1926 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1927 scheduler from moving loads before the stores saving the registers. */
1928 if (info->stdarg_size > 0)
1929 emit_insn (gen_blockage ());
1931 /* Set up pic register/small data register for this function. */
1932 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1933 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1934 gen_rtx_REG (Pmode, LR_REGNO),
1935 gen_rtx_REG (SImode, OFFSET_REGNO)));
1939 /* Under frv, all of the work is done via frv_expand_epilogue, but
1940 this function provides a convenient place to do cleanup. */
1943 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1944 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1946 frv_stack_cache = (frv_stack_t *)0;
1948 /* Zap last used registers for conditional execution. */
1949 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1951 /* Release the bitmap of created insns. */
1952 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1956 /* Called after register allocation to add any instructions needed for the
1957 epilogue. Using an epilogue insn is favored compared to putting all of the
1958 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1959 it allows the scheduler to intermix instructions with the saves of
1960 the caller saved registers. In some cases, it might be necessary
1961 to emit a barrier instruction as the last insn to prevent such
1965 frv_expand_epilogue (bool emit_return)
1967 frv_stack_t *info = frv_stack_info ();
1968 rtx fp = frame_pointer_rtx;
1969 rtx sp = stack_pointer_rtx;
1973 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1975 /* Restore the stack pointer to its original value if alloca or the like
1977 if (! current_function_sp_is_unchanging)
1978 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1980 /* Restore the callee-saved registers that were used in this function. */
1981 frv_frame_access_standard_regs (FRV_LOAD, info);
1983 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1984 no return instruction should be emitted. */
1985 if (info->save_p[LR_REGNO])
1990 /* Use the same method to access the link register's slot as we did in
1991 the prologue. In other words, use the frame pointer if available,
1992 otherwise use the stack pointer.
1994 LR_OFFSET is the offset of the link register's slot from the start
1995 of the frame and MEM is a memory rtx for it. */
1996 lr_offset = info->reg_offset[LR_REGNO];
1997 if (frame_pointer_needed)
1998 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
2000 mem = frv_frame_mem (Pmode, sp, lr_offset);
2002 /* Load the old link register into a GPR. */
2003 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
2004 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
2007 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
2009 /* Restore the old frame pointer. Emit a USE afterwards to make sure
2010 the load is preserved. */
2011 if (frame_pointer_needed)
2013 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
2017 /* Deallocate the stack frame. */
2018 if (info->total_size != 0)
2020 rtx offset = frv_frame_offset_rtx (info->total_size);
2021 emit_insn (gen_stack_adjust (sp, sp, offset));
2024 /* If this function uses eh_return, add the final stack adjustment now. */
2025 if (crtl->calls_eh_return)
2026 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2029 emit_jump_insn (gen_epilogue_return (return_addr));
2032 rtx lr = return_addr;
2034 if (REGNO (return_addr) != LR_REGNO)
2036 lr = gen_rtx_REG (Pmode, LR_REGNO);
2037 emit_move_insn (lr, return_addr);
2045 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2048 frv_asm_output_mi_thunk (FILE *file,
2049 tree thunk_fndecl ATTRIBUTE_UNUSED,
2050 HOST_WIDE_INT delta,
2051 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2054 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2055 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2056 const char *name_jmp = reg_names[JUMP_REGNO];
2057 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2059 /* Do the add using an addi if possible. */
2060 if (IN_RANGE_P (delta, -2048, 2047))
2061 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2064 const char *const name_add = reg_names[TEMP_REGNO];
2065 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2066 parallel, delta, name_add);
2067 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2069 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2074 const char *name_pic = reg_names[FDPIC_REGNO];
2075 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2079 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2080 assemble_name (file, name_func);
2081 fprintf (file, "),%s\n", name_jmp);
2083 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2084 assemble_name (file, name_func);
2085 fprintf (file, "),%s\n", name_jmp);
2087 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2091 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2092 assemble_name (file, name_func);
2093 fprintf (file, "\t)), %s\n", name_jmp);
2098 fprintf (file, "\tsethi%s #hi(", parallel);
2099 assemble_name (file, name_func);
2100 fprintf (file, "),%s\n", name_jmp);
2102 fprintf (file, "\tsetlo #lo(");
2103 assemble_name (file, name_func);
2104 fprintf (file, "),%s\n", name_jmp);
2108 /* Use JUMP_REGNO as a temporary PIC register. */
2109 const char *name_lr = reg_names[LR_REGNO];
2110 const char *name_gppic = name_jmp;
2111 const char *name_tmp = reg_names[TEMP_REGNO];
2113 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2114 fprintf (file, "\tcall 1f\n");
2115 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2116 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2117 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2118 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2119 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2121 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2122 assemble_name (file, name_func);
2123 fprintf (file, "),%s\n", name_tmp);
2125 fprintf (file, "\tsetlo #gprello(");
2126 assemble_name (file, name_func);
2127 fprintf (file, "),%s\n", name_tmp);
2129 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2132 /* Jump to the function address. */
2133 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2138 /* On frv, create a frame whenever we need to create stack. */
2141 frv_frame_pointer_required (void)
2143 /* If we forgoing the usual linkage requirements, we only need
2144 a frame pointer if the stack pointer might change. */
2145 if (!TARGET_LINKED_FP)
2146 return !current_function_sp_is_unchanging;
2148 if (! current_function_is_leaf)
2151 if (get_frame_size () != 0)
2157 if (!current_function_sp_is_unchanging)
2160 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2166 if (cfun->machine->frame_needed)
2173 /* Worker function for TARGET_CAN_ELIMINATE. */
2176 frv_can_eliminate (const int from, const int to)
2178 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2179 ? ! frame_pointer_needed
2183 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2184 initial difference between the specified pair of registers. This macro must
2185 be defined if `ELIMINABLE_REGS' is defined. */
2187 /* See frv_stack_info for more details on the frv stack frame. */
2190 frv_initial_elimination_offset (int from, int to)
2192 frv_stack_t *info = frv_stack_info ();
2195 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2196 ret = info->total_size - info->pretend_size;
2198 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2199 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2201 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2202 ret = (info->total_size
2203 - info->reg_offset[FRAME_POINTER_REGNUM]
2204 - info->pretend_size);
2209 if (TARGET_DEBUG_STACK)
2210 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2211 reg_names [from], reg_names[to], ret);
2217 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2220 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2221 enum machine_mode mode,
2222 tree type ATTRIBUTE_UNUSED,
2226 if (TARGET_DEBUG_ARG)
2228 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2229 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2233 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2236 frv_expand_builtin_saveregs (void)
2238 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2240 if (TARGET_DEBUG_ARG)
2241 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2244 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2248 /* Expand __builtin_va_start to do the va_start macro. */
2251 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2254 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2256 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2257 GEN_INT (UNITS_PER_WORD * num));
2259 if (TARGET_DEBUG_ARG)
2261 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2262 crtl->args.info, num);
2264 debug_rtx (nextarg);
2267 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2268 fold_convert (TREE_TYPE (valist),
2269 make_tree (sizetype, nextarg)));
2270 TREE_SIDE_EFFECTS (t) = 1;
2272 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2276 /* Expand a block move operation, and return 1 if successful. Return 0
2277 if we should let the compiler generate normal code.
2279 operands[0] is the destination
2280 operands[1] is the source
2281 operands[2] is the length
2282 operands[3] is the alignment */
2284 /* Maximum number of loads to do before doing the stores */
2285 #ifndef MAX_MOVE_REG
2286 #define MAX_MOVE_REG 4
2289 /* Maximum number of total loads to do. */
2290 #ifndef TOTAL_MOVE_REG
2291 #define TOTAL_MOVE_REG 8
2295 frv_expand_block_move (rtx operands[])
2297 rtx orig_dest = operands[0];
2298 rtx orig_src = operands[1];
2299 rtx bytes_rtx = operands[2];
2300 rtx align_rtx = operands[3];
2301 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2314 rtx stores[MAX_MOVE_REG];
2316 enum machine_mode mode;
2318 /* If this is not a fixed size move, just call memcpy. */
2322 /* This should be a fixed size alignment. */
2323 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2325 align = INTVAL (align_rtx);
2327 /* Anything to move? */
2328 bytes = INTVAL (bytes_rtx);
2332 /* Don't support real large moves. */
2333 if (bytes > TOTAL_MOVE_REG*align)
2336 /* Move the address into scratch registers. */
2337 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2338 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2340 num_reg = offset = 0;
2341 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2343 /* Calculate the correct offset for src/dest. */
2347 dest_addr = dest_reg;
2351 src_addr = plus_constant (src_reg, offset);
2352 dest_addr = plus_constant (dest_reg, offset);
2355 /* Generate the appropriate load and store, saving the stores
2357 if (bytes >= 4 && align >= 4)
2359 else if (bytes >= 2 && align >= 2)
2364 move_bytes = GET_MODE_SIZE (mode);
2365 tmp_reg = gen_reg_rtx (mode);
2366 src_mem = change_address (orig_src, mode, src_addr);
2367 dest_mem = change_address (orig_dest, mode, dest_addr);
2368 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2369 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2371 if (num_reg >= MAX_MOVE_REG)
2373 for (i = 0; i < num_reg; i++)
2374 emit_insn (stores[i]);
2379 for (i = 0; i < num_reg; i++)
2380 emit_insn (stores[i]);
2386 /* Expand a block clear operation, and return 1 if successful. Return 0
2387 if we should let the compiler generate normal code.
2389 operands[0] is the destination
2390 operands[1] is the length
2391 operands[3] is the alignment */
2394 frv_expand_block_clear (rtx operands[])
2396 rtx orig_dest = operands[0];
2397 rtx bytes_rtx = operands[1];
2398 rtx align_rtx = operands[3];
2399 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2408 enum machine_mode mode;
2410 /* If this is not a fixed size move, just call memcpy. */
2414 /* This should be a fixed size alignment. */
2415 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2417 align = INTVAL (align_rtx);
2419 /* Anything to move? */
2420 bytes = INTVAL (bytes_rtx);
2424 /* Don't support real large clears. */
2425 if (bytes > TOTAL_MOVE_REG*align)
2428 /* Move the address into a scratch register. */
2429 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2431 num_reg = offset = 0;
2432 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2434 /* Calculate the correct offset for src/dest. */
2435 dest_addr = ((offset == 0)
2437 : plus_constant (dest_reg, offset));
2439 /* Generate the appropriate store of gr0. */
2440 if (bytes >= 4 && align >= 4)
2442 else if (bytes >= 2 && align >= 2)
2447 clear_bytes = GET_MODE_SIZE (mode);
2448 dest_mem = change_address (orig_dest, mode, dest_addr);
2449 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2456 /* The following variable is used to output modifiers of assembler
2457 code of the current output insn. */
2459 static rtx *frv_insn_operands;
2461 /* The following function is used to add assembler insn code suffix .p
2462 if it is necessary. */
2465 frv_asm_output_opcode (FILE *f, const char *ptr)
2469 if (frv_insn_packing_flag <= 0)
2472 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2475 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2476 || (*ptr >= 'A' && *ptr <= 'Z')))
2478 int letter = *ptr++;
2481 frv_print_operand (f, frv_insn_operands [c], letter);
2482 while ((c = *ptr) >= '0' && c <= '9')
2494 /* Set up the packing bit for the current output insn. Note that this
2495 function is not called for asm insns. */
2498 frv_final_prescan_insn (rtx insn, rtx *opvec,
2499 int noperands ATTRIBUTE_UNUSED)
2503 if (frv_insn_packing_flag >= 0)
2505 frv_insn_operands = opvec;
2506 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2508 else if (recog_memoized (insn) >= 0
2509 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2510 /* Packing optimizations have been disabled, but INSN can only
2511 be issued in M1. Insert an mnop in M0. */
2512 fprintf (asm_out_file, "\tmnop.p\n");
2518 /* A C expression whose value is RTL representing the address in a stack frame
2519 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2520 an RTL expression for the address of the stack frame itself.
2522 If you don't define this macro, the default is to return the value of
2523 FRAMEADDR--that is, the stack frame address is also the address of the stack
2524 word that points to the previous frame. */
2526 /* The default is correct, but we need to make sure the frame gets created. */
2528 frv_dynamic_chain_address (rtx frame)
2530 cfun->machine->frame_needed = 1;
2535 /* A C expression whose value is RTL representing the value of the return
2536 address for the frame COUNT steps up from the current frame, after the
2537 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2538 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2541 The value of the expression must always be the correct address when COUNT is
2542 zero, but may be `NULL_RTX' if there is not way to determine the return
2543 address of other frames. */
2546 frv_return_addr_rtx (int count, rtx frame)
2550 cfun->machine->frame_needed = 1;
2551 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2554 /* Given a memory reference MEMREF, interpret the referenced memory as
2555 an array of MODE values, and return a reference to the element
2556 specified by INDEX. Assume that any pre-modification implicit in
2557 MEMREF has already happened.
2559 MEMREF must be a legitimate operand for modes larger than SImode.
2560 frv_legitimate_address_p forbids register+register addresses, which
2561 this function cannot handle. */
2563 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2565 rtx base = XEXP (memref, 0);
2566 if (GET_CODE (base) == PRE_MODIFY)
2567 base = XEXP (base, 0);
2568 return change_address (memref, mode,
2569 plus_constant (base, index * GET_MODE_SIZE (mode)));
2573 /* Print a memory address as an operand to reference that memory location. */
2575 frv_print_operand_address (FILE * stream, rtx x)
2577 if (GET_CODE (x) == MEM)
2580 switch (GET_CODE (x))
2583 fputs (reg_names [ REGNO (x)], stream);
2587 fprintf (stream, "%ld", (long) INTVAL (x));
2591 assemble_name (stream, XSTR (x, 0));
2596 output_addr_const (stream, x);
2600 /* Poorly constructed asm statements can trigger this alternative.
2601 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2602 frv_print_operand_memory_reference (stream, x, 0);
2609 fatal_insn ("bad insn to frv_print_operand_address:", x);
2614 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2616 int regno = true_regnum (x);
2618 fputs (reg_names[regno], stream);
2620 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2623 /* Print a memory reference suitable for the ld/st instructions. */
2626 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2628 struct frv_unspec unspec;
2632 switch (GET_CODE (x))
2639 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2641 x1 = XEXP (XEXP (x, 1), 1);
2651 if (GET_CODE (x0) == CONST_INT)
2659 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2668 else if (GET_CODE (x1) != CONST_INT)
2669 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2672 fputs ("@(", stream);
2674 fputs (reg_names[GPR_R0], stream);
2675 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2676 frv_print_operand_memory_reference_reg (stream, x0);
2678 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2680 fputs (",", stream);
2682 fputs (reg_names [GPR_R0], stream);
2686 switch (GET_CODE (x1))
2690 frv_print_operand_memory_reference_reg (stream, x1);
2694 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2698 if (!frv_const_unspec_p (x1, &unspec))
2699 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2700 frv_output_const_unspec (stream, &unspec);
2704 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2708 fputs (")", stream);
2712 /* Return 2 for likely branches and 0 for non-likely branches */
2714 #define FRV_JUMP_LIKELY 2
2715 #define FRV_JUMP_NOT_LIKELY 0
2718 frv_print_operand_jump_hint (rtx insn)
2723 HOST_WIDE_INT prob = -1;
2724 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2726 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2728 /* Assume any non-conditional jump is likely. */
2729 if (! any_condjump_p (insn))
2730 ret = FRV_JUMP_LIKELY;
2734 labelref = condjump_label (insn);
2737 rtx label = XEXP (labelref, 0);
2738 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2743 note = find_reg_note (insn, REG_BR_PROB, 0);
2745 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2749 prob = INTVAL (XEXP (note, 0));
2750 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2752 : FRV_JUMP_NOT_LIKELY);
2764 case UNKNOWN: direction = "unknown jump direction"; break;
2765 case BACKWARD: direction = "jump backward"; break;
2766 case FORWARD: direction = "jump forward"; break;
2770 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2771 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2772 (long)INSN_UID (insn), direction, (long)prob,
2773 (long)REG_BR_PROB_BASE, ret);
2781 /* Return the comparison operator to use for CODE given that the ICC
2785 comparison_string (enum rtx_code code, rtx op0)
2787 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2790 default: output_operand_lossage ("bad condition code");
2791 case EQ: return "eq";
2792 case NE: return "ne";
2793 case LT: return is_nz_p ? "n" : "lt";
2794 case LE: return "le";
2795 case GT: return "gt";
2796 case GE: return is_nz_p ? "p" : "ge";
2797 case LTU: return is_nz_p ? "no" : "c";
2798 case LEU: return is_nz_p ? "eq" : "ls";
2799 case GTU: return is_nz_p ? "ne" : "hi";
2800 case GEU: return is_nz_p ? "ra" : "nc";
2804 /* Print an operand to an assembler instruction.
2806 `%' followed by a letter and a digit says to output an operand in an
2807 alternate fashion. Four letters have standard, built-in meanings
2808 described below. The hook `TARGET_PRINT_OPERAND' can define
2809 additional letters with nonstandard meanings.
2811 `%cDIGIT' can be used to substitute an operand that is a constant value
2812 without the syntax that normally indicates an immediate operand.
2814 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2817 `%aDIGIT' can be used to substitute an operand as if it were a memory
2818 reference, with the actual operand treated as the address. This may be
2819 useful when outputting a "load address" instruction, because often the
2820 assembler syntax for such an instruction requires you to write the operand
2821 as if it were a memory reference.
2823 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2825 `%=' outputs a number which is unique to each instruction in the entire
2826 compilation. This is useful for making local labels to be referred to more
2827 than once in a single template that generates multiple assembler
2830 `%' followed by a punctuation character specifies a substitution that
2831 does not use an operand. Only one case is standard: `%%' outputs a
2832 `%' into the assembler code. Other nonstandard cases can be defined
2833 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2834 punctuation characters are valid with the
2835 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2838 frv_print_operand (FILE * file, rtx x, int code)
2840 struct frv_unspec unspec;
2841 HOST_WIDE_INT value;
2844 if (code != 0 && !ISALPHA (code))
2847 else if (GET_CODE (x) == CONST_INT)
2850 else if (GET_CODE (x) == CONST_DOUBLE)
2852 if (GET_MODE (x) == SFmode)
2857 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2858 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2862 else if (GET_MODE (x) == VOIDmode)
2863 value = CONST_DOUBLE_LOW (x);
2866 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2877 fputs (reg_names[GPR_R0], file);
2881 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2885 /* Output small data area base register (gr16). */
2886 fputs (reg_names[SDA_BASE_REG], file);
2890 /* Output pic register (gr17). */
2891 fputs (reg_names[PIC_REGNO], file);
2895 /* Output the temporary integer CCR register. */
2896 fputs (reg_names[ICR_TEMP], file);
2900 /* Output the temporary integer CC register. */
2901 fputs (reg_names[ICC_TEMP], file);
2904 /* case 'a': print an address. */
2907 /* Print appropriate test for integer branch false operation. */
2908 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2909 XEXP (x, 0)), file);
2913 /* Print appropriate test for integer branch true operation. */
2914 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2918 /* Print 1 for a NE and 0 for an EQ to give the final argument
2919 for a conditional instruction. */
2920 if (GET_CODE (x) == NE)
2923 else if (GET_CODE (x) == EQ)
2927 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2931 /* Print appropriate test for floating point branch false operation. */
2932 switch (GET_CODE (x))
2935 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2937 case EQ: fputs ("ne", file); break;
2938 case NE: fputs ("eq", file); break;
2939 case LT: fputs ("uge", file); break;
2940 case LE: fputs ("ug", file); break;
2941 case GT: fputs ("ule", file); break;
2942 case GE: fputs ("ul", file); break;
2947 /* Print appropriate test for floating point branch true operation. */
2948 switch (GET_CODE (x))
2951 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2953 case EQ: fputs ("eq", file); break;
2954 case NE: fputs ("ne", file); break;
2955 case LT: fputs ("lt", file); break;
2956 case LE: fputs ("le", file); break;
2957 case GT: fputs ("gt", file); break;
2958 case GE: fputs ("ge", file); break;
2963 /* Print appropriate GOT function. */
2964 if (GET_CODE (x) != CONST_INT)
2965 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2966 fputs (unspec_got_name (INTVAL (x)), file);
2970 /* Print 'i' if the operand is a constant, or is a memory reference that
2972 if (GET_CODE (x) == MEM)
2973 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2974 ? XEXP (XEXP (x, 0), 1)
2976 else if (GET_CODE (x) == PLUS)
2979 switch (GET_CODE (x))
2993 /* For jump instructions, print 'i' if the operand is a constant or
2994 is an expression that adds a constant. */
2995 if (GET_CODE (x) == CONST_INT)
3000 if (GET_CODE (x) == CONST_INT
3001 || (GET_CODE (x) == PLUS
3002 && (GET_CODE (XEXP (x, 1)) == CONST_INT
3003 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
3009 /* Print the lower register of a double word register pair */
3010 if (GET_CODE (x) == REG)
3011 fputs (reg_names[ REGNO (x)+1 ], file);
3013 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
3016 /* case 'l': print a LABEL_REF. */
3020 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
3021 for the second word of double memory operations. */
3022 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3023 switch (GET_CODE (x))
3026 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3029 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3037 frv_print_operand_memory_reference (file, x, offset);
3043 /* Print the opcode of a command. */
3044 switch (GET_CODE (x))
3047 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3049 case PLUS: fputs ("add", file); break;
3050 case MINUS: fputs ("sub", file); break;
3051 case AND: fputs ("and", file); break;
3052 case IOR: fputs ("or", file); break;
3053 case XOR: fputs ("xor", file); break;
3054 case ASHIFT: fputs ("sll", file); break;
3055 case ASHIFTRT: fputs ("sra", file); break;
3056 case LSHIFTRT: fputs ("srl", file); break;
3060 /* case 'n': negate and print a constant int. */
3063 /* Print PIC label using operand as the number. */
3064 if (GET_CODE (x) != CONST_INT)
3065 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3067 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3071 /* Print 'u' if the operand is a update load/store. */
3072 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3077 /* If value is 0, print gr0, otherwise it must be a register. */
3078 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3079 fputs (reg_names[GPR_R0], file);
3081 else if (GET_CODE (x) == REG)
3082 fputs (reg_names [REGNO (x)], file);
3085 fatal_insn ("bad insn in frv_print_operand, z case", x);
3089 /* Print constant in hex. */
3090 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3092 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3099 if (GET_CODE (x) == REG)
3100 fputs (reg_names [REGNO (x)], file);
3102 else if (GET_CODE (x) == CONST_INT
3103 || GET_CODE (x) == CONST_DOUBLE)
3104 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3106 else if (frv_const_unspec_p (x, &unspec))
3107 frv_output_const_unspec (file, &unspec);
3109 else if (GET_CODE (x) == MEM)
3110 frv_print_operand_address (file, XEXP (x, 0));
3112 else if (CONSTANT_ADDRESS_P (x))
3113 frv_print_operand_address (file, x);
3116 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3121 fatal_insn ("frv_print_operand: unknown code", x);
3129 frv_print_operand_punct_valid_p (unsigned char code)
3131 return (code == '.' || code == '#' || code == '@' || code == '~'
3132 || code == '*' || code == '&');
3136 /* A C statement (sans semicolon) for initializing the variable CUM for the
3137 state at the beginning of the argument list. The variable has type
3138 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3139 of the function which will receive the args, or 0 if the args are to a
3140 compiler support library function. The value of INDIRECT is nonzero when
3141 processing an indirect call, for example a call through a function pointer.
3142 The value of INDIRECT is zero for a call to an explicitly named function, a
3143 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3144 arguments for the function being compiled.
3146 When processing a call to a compiler support library function, LIBNAME
3147 identifies which one. It is a `symbol_ref' rtx which contains the name of
3148 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3149 being processed. Thus, each time this macro is called, either LIBNAME or
3150 FNTYPE is nonzero, but never both of them at once. */
3153 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3159 *cum = FIRST_ARG_REGNUM;
3161 if (TARGET_DEBUG_ARG)
3163 fprintf (stderr, "\ninit_cumulative_args:");
3164 if (!fndecl && fntype)
3165 fputs (" indirect", stderr);
3168 fputs (" incoming", stderr);
3172 tree ret_type = TREE_TYPE (fntype);
3173 fprintf (stderr, " return=%s,",
3174 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3177 if (libname && GET_CODE (libname) == SYMBOL_REF)
3178 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3180 if (cfun->returns_struct)
3181 fprintf (stderr, " return-struct");
3183 putc ('\n', stderr);
3188 /* Return true if we should pass an argument on the stack rather than
3192 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3194 if (mode == BLKmode)
3198 return AGGREGATE_TYPE_P (type);
3201 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3202 argument with the specified mode and type. If it is not defined,
3203 `PARM_BOUNDARY' is used for all arguments. */
3206 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3207 tree type ATTRIBUTE_UNUSED)
3209 return BITS_PER_WORD;
3213 frv_function_arg (CUMULATIVE_ARGS *cum,
3214 enum machine_mode mode,
3215 tree type ATTRIBUTE_UNUSED,
3217 int incoming ATTRIBUTE_UNUSED)
3219 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3224 /* Return a marker for use in the call instruction. */
3225 if (xmode == VOIDmode)
3231 else if (arg_num <= LAST_ARG_REGNUM)
3233 ret = gen_rtx_REG (xmode, arg_num);
3234 debstr = reg_names[arg_num];
3243 if (TARGET_DEBUG_ARG)
3245 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3246 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3252 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3253 advance past an argument in the argument list. The values MODE, TYPE and
3254 NAMED describe that argument. Once this is done, the variable CUM is
3255 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3257 This macro need not do anything if the argument in question was passed on
3258 the stack. The compiler knows how to track the amount of stack space used
3259 for arguments without any special help. */
3262 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3263 enum machine_mode mode,
3264 tree type ATTRIBUTE_UNUSED,
3267 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3268 int bytes = GET_MODE_SIZE (xmode);
3269 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3272 *cum = arg_num + words;
3274 if (TARGET_DEBUG_ARG)
3276 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3277 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3281 /* A C expression for the number of words, at the beginning of an argument,
3282 must be put in registers. The value must be zero for arguments that are
3283 passed entirely in registers or that are entirely pushed on the stack.
3285 On some machines, certain arguments must be passed partially in registers
3286 and partially in memory. On these machines, typically the first N words of
3287 arguments are passed in registers, and the rest on the stack. If a
3288 multi-word argument (a `double' or a structure) crosses that boundary, its
3289 first few words must be passed in registers and the rest must be pushed.
3290 This macro tells the compiler when this occurs, and how many of the words
3291 should go in registers.
3293 `FUNCTION_ARG' for these arguments should return the first register to be
3294 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3295 the called function. */
3298 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3299 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3301 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3302 int bytes = GET_MODE_SIZE (xmode);
3303 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3307 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3308 ? LAST_ARG_REGNUM - arg_num + 1
3310 ret *= UNITS_PER_WORD;
3312 if (TARGET_DEBUG_ARG && ret)
3313 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3319 /* Implements TARGET_FUNCTION_VALUE. */
3322 frv_function_value (const_tree valtype,
3323 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3324 bool outgoing ATTRIBUTE_UNUSED)
3326 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3330 /* Implements TARGET_LIBCALL_VALUE. */
3333 frv_libcall_value (enum machine_mode mode,
3334 const_rtx fun ATTRIBUTE_UNUSED)
3336 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3340 /* Implements FUNCTION_VALUE_REGNO_P. */
3343 frv_function_value_regno_p (const unsigned int regno)
3345 return (regno == RETURN_VALUE_REGNUM);
3348 /* Return true if a register is ok to use as a base or index register. */
3350 static FRV_INLINE int
3351 frv_regno_ok_for_base_p (int regno, int strict_p)
3357 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3359 if (regno == ARG_POINTER_REGNUM)
3362 return (regno >= FIRST_PSEUDO_REGISTER);
3366 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3367 RTX) is a legitimate memory address on the target machine for a memory
3368 operand of mode MODE.
3370 It usually pays to define several simpler macros to serve as subroutines for
3371 this one. Otherwise it may be too complicated to understand.
3373 This macro must exist in two variants: a strict variant and a non-strict
3374 one. The strict variant is used in the reload pass. It must be defined so
3375 that any pseudo-register that has not been allocated a hard register is
3376 considered a memory reference. In contexts where some kind of register is
3377 required, a pseudo-register with no hard register must be rejected.
3379 The non-strict variant is used in other passes. It must be defined to
3380 accept all pseudo-registers in every context where some kind of register is
3383 Compiler source files that want to use the strict variant of this macro
3384 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3385 conditional to define the strict variant in that case and the non-strict
3388 Normally, constant addresses which are the sum of a `symbol_ref' and an
3389 integer are stored inside a `const' RTX to mark them as constant.
3390 Therefore, there is no need to recognize such sums specifically as
3391 legitimate addresses. Normally you would simply recognize any `const' as
3394 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3395 constant sums that are not marked with `const'. It assumes that a
3396 naked `plus' indicates indexing. If so, then you *must* reject such
3397 naked constant sums as illegitimate addresses, so that none of them
3398 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3401 frv_legitimate_address_p_1 (enum machine_mode mode,
3405 int allow_double_reg_p)
3409 HOST_WIDE_INT value;
3412 if (FRV_SYMBOL_REF_TLS_P (x))
3415 switch (GET_CODE (x))
3422 if (GET_CODE (x) != REG)
3428 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3434 if (GET_CODE (x0) != REG
3435 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3436 || GET_CODE (x1) != PLUS
3437 || ! rtx_equal_p (x0, XEXP (x1, 0))
3438 || GET_CODE (XEXP (x1, 1)) != REG
3439 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3446 /* 12-bit immediate */
3451 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3453 /* If we can't use load/store double operations, make sure we can
3454 address the second word. */
3455 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3456 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3465 if (GET_CODE (x0) == SUBREG)
3466 x0 = SUBREG_REG (x0);
3468 if (GET_CODE (x0) != REG)
3471 regno0 = REGNO (x0);
3472 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3475 switch (GET_CODE (x1))
3481 x1 = SUBREG_REG (x1);
3482 if (GET_CODE (x1) != REG)
3488 /* Do not allow reg+reg addressing for modes > 1 word if we
3489 can't depend on having move double instructions. */
3490 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3493 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3497 /* 12-bit immediate */
3502 value = INTVAL (x1);
3503 ret = IN_RANGE_P (value, -2048, 2047);
3505 /* If we can't use load/store double operations, make sure we can
3506 address the second word. */
3507 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3508 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3513 if (!condexec_p && got12_operand (x1, VOIDmode))
3521 if (TARGET_DEBUG_ADDR)
3523 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3524 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3525 (condexec_p) ? ", inside conditional code" : "");
3533 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3535 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3538 /* Given an ADDR, generate code to inline the PLT. */
3540 gen_inlined_tls_plt (rtx addr)
3543 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3546 dest = gen_reg_rtx (DImode);
3553 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3554 calll #gettlsoff(ADDR)@(gr8, gr0)
3556 emit_insn (gen_tls_lddi (dest, addr, picreg));
3563 sethi.p #gottlsdeschi(ADDR), gr8
3564 setlo #gottlsdesclo(ADDR), gr8
3565 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3566 calll #gettlsoff(ADDR)@(gr8, gr0)
3568 rtx reguse = gen_reg_rtx (Pmode);
3569 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3570 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3573 retval = gen_reg_rtx (Pmode);
3574 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3578 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3579 the destination address. */
3581 gen_tlsmoff (rtx addr, rtx reg)
3583 rtx dest = gen_reg_rtx (Pmode);
3587 /* sethi.p #tlsmoffhi(x), grA
3588 setlo #tlsmofflo(x), grA
3590 dest = gen_reg_rtx (Pmode);
3591 emit_insn (gen_tlsoff_hilo (dest, addr,
3592 GEN_INT (R_FRV_TLSMOFFHI)));
3593 dest = gen_rtx_PLUS (Pmode, dest, reg);
3597 /* addi grB, #tlsmoff12(x), grC
3599 ld/st @(grB, #tlsmoff12(x)), grC
3601 dest = gen_reg_rtx (Pmode);
3602 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3603 GEN_INT (R_FRV_TLSMOFF12)));
3608 /* Generate code for a TLS address. */
3610 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3612 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3613 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3617 case TLS_MODEL_INITIAL_EXEC:
3621 ldi @(gr15, #gottlsoff12(x)), gr5
3623 dest = gen_reg_rtx (Pmode);
3624 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3625 dest = gen_rtx_PLUS (Pmode, tp, dest);
3629 /* -fPIC or anything else.
3631 sethi.p #gottlsoffhi(x), gr14
3632 setlo #gottlsofflo(x), gr14
3633 ld #tlsoff(x)@(gr15, gr14), gr9
3635 rtx tmp = gen_reg_rtx (Pmode);
3636 dest = gen_reg_rtx (Pmode);
3637 emit_insn (gen_tlsoff_hilo (tmp, addr,
3638 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3640 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3641 dest = gen_rtx_PLUS (Pmode, tp, dest);
3644 case TLS_MODEL_LOCAL_DYNAMIC:
3648 if (TARGET_INLINE_PLT)
3649 retval = gen_inlined_tls_plt (GEN_INT (0));
3652 /* call #gettlsoff(0) */
3653 retval = gen_reg_rtx (Pmode);
3654 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3657 reg = gen_reg_rtx (Pmode);
3658 emit_insn (gen_rtx_SET (VOIDmode, reg,
3659 gen_rtx_PLUS (Pmode,
3662 dest = gen_tlsmoff (addr, reg);
3665 dest = gen_reg_rtx (Pmode);
3666 emit_insn (gen_tlsoff_hilo (dest, addr,
3667 GEN_INT (R_FRV_TLSMOFFHI)));
3668 dest = gen_rtx_PLUS (Pmode, dest, reg);
3672 case TLS_MODEL_LOCAL_EXEC:
3673 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3675 case TLS_MODEL_GLOBAL_DYNAMIC:
3679 if (TARGET_INLINE_PLT)
3680 retval = gen_inlined_tls_plt (addr);
3683 /* call #gettlsoff(x) */
3684 retval = gen_reg_rtx (Pmode);
3685 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3687 dest = gen_rtx_PLUS (Pmode, retval, tp);
3698 frv_legitimize_address (rtx x,
3699 rtx oldx ATTRIBUTE_UNUSED,
3700 enum machine_mode mode ATTRIBUTE_UNUSED)
3702 if (GET_CODE (x) == SYMBOL_REF)
3704 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3706 return frv_legitimize_tls_address (x, model);
3712 /* Test whether a local function descriptor is canonical, i.e.,
3713 whether we can use FUNCDESC_GOTOFF to compute the address of the
3717 frv_local_funcdesc_p (rtx fnx)
3720 enum symbol_visibility vis;
3723 if (! SYMBOL_REF_LOCAL_P (fnx))
3726 fn = SYMBOL_REF_DECL (fnx);
3731 vis = DECL_VISIBILITY (fn);
3733 if (vis == VISIBILITY_PROTECTED)
3734 /* Private function descriptors for protected functions are not
3735 canonical. Temporarily change the visibility to global. */
3736 vis = VISIBILITY_DEFAULT;
3737 else if (flag_shlib)
3738 /* If we're already compiling for a shared library (that, unlike
3739 executables, can't assume that the existence of a definition
3740 implies local binding), we can skip the re-testing. */
3743 ret = default_binds_local_p_1 (fn, flag_pic);
3745 DECL_VISIBILITY (fn) = vis;
3750 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3754 frv_gen_GPsym2reg (rtx dest, rtx src)
3756 tree gp = get_identifier ("_gp");
3757 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3759 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3763 unspec_got_name (int i)
3767 case R_FRV_GOT12: return "got12";
3768 case R_FRV_GOTHI: return "gothi";
3769 case R_FRV_GOTLO: return "gotlo";
3770 case R_FRV_FUNCDESC: return "funcdesc";
3771 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3772 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3773 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3774 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3775 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3776 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3777 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3778 case R_FRV_GOTOFF12: return "gotoff12";
3779 case R_FRV_GOTOFFHI: return "gotoffhi";
3780 case R_FRV_GOTOFFLO: return "gotofflo";
3781 case R_FRV_GPREL12: return "gprel12";
3782 case R_FRV_GPRELHI: return "gprelhi";
3783 case R_FRV_GPRELLO: return "gprello";
3784 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3785 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3786 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3787 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3788 case R_FRV_TLSMOFF12: return "tlsmoff12";
3789 case R_FRV_TLSDESCHI: return "tlsdeschi";
3790 case R_FRV_TLSDESCLO: return "tlsdesclo";
3791 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3792 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3793 default: gcc_unreachable ();
3797 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3798 is added inside the relocation operator. */
3801 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3803 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3804 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3805 fputs (")", stream);
3808 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3809 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3810 otherwise return ORIG_X. */
3813 frv_find_base_term (rtx x)
3815 struct frv_unspec unspec;
3817 if (frv_const_unspec_p (x, &unspec)
3818 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3819 return plus_constant (unspec.symbol, unspec.offset);
3824 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3825 the operand is used by a predicated instruction. */
3828 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3830 return ((GET_MODE (op) == mode || mode == VOIDmode)
3831 && GET_CODE (op) == MEM
3832 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3833 reload_completed, condexec_p, FALSE));
3837 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3839 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3840 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3846 rvrtx = operands[0];
3850 addr = XEXP (operands[0], 0);
3852 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3853 any calls that would involve a PLT, but can't tell, since we
3854 don't know whether an extern function is going to be provided by
3855 a separate translation unit or imported from a separate module.
3856 When compiling for shared libraries, if the function has default
3857 visibility, we assume it's overridable, so we inline the PLT, but
3858 for executables, we don't really have a way to make a good
3859 decision: a function is as likely to be imported from a shared
3860 library as it is to be defined in the executable itself. We
3861 assume executables will get global functions defined locally,
3862 whereas shared libraries will have them potentially overridden,
3863 so we only inline PLTs when compiling for shared libraries.
3865 In order to mark a function as local to a shared library, any
3866 non-default visibility attribute suffices. Unfortunately,
3867 there's no simple way to tag a function declaration as ``in a
3868 different module'', which we could then use to trigger PLT
3869 inlining on executables. There's -minline-plt, but it affects
3870 all external functions, so one would have to also mark function
3871 declarations available in the same module with non-default
3872 visibility, which is advantageous in itself. */
3873 if (GET_CODE (addr) == SYMBOL_REF
3874 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3878 dest = gen_reg_rtx (SImode);
3880 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3881 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3883 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3884 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3886 crtl->uses_pic_offset_table = TRUE;
3889 else if (GET_CODE (addr) == SYMBOL_REF)
3891 /* These are always either local, or handled through a local
3894 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3895 operands[2], picreg, lr);
3897 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3901 else if (! ldd_address_operand (addr, Pmode))
3902 addr = force_reg (Pmode, addr);
3904 picreg = gen_reg_rtx (DImode);
3905 emit_insn (gen_movdi_ldd (picreg, addr));
3907 if (sibcall && ret_value)
3908 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3910 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3912 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3914 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3918 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3919 process these separately from any offsets, such that we add any
3920 offsets to the function descriptor (the actual pointer), not to the
3921 function address. */
3924 frv_function_symbol_referenced_p (rtx x)
3930 if (GET_CODE (x) == SYMBOL_REF)
3931 return SYMBOL_REF_FUNCTION_P (x);
3933 length = GET_RTX_LENGTH (GET_CODE (x));
3934 format = GET_RTX_FORMAT (GET_CODE (x));
3936 for (j = 0; j < length; ++j)
3941 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3947 if (XVEC (x, j) != 0)
3950 for (k = 0; k < XVECLEN (x, j); ++k)
3951 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3957 /* Nothing to do. */
3965 /* Return true if the memory operand is one that can be conditionally
3969 condexec_memory_operand (rtx op, enum machine_mode mode)
3971 enum machine_mode op_mode = GET_MODE (op);
3974 if (mode != VOIDmode && op_mode != mode)
3989 if (GET_CODE (op) != MEM)
3992 addr = XEXP (op, 0);
3993 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
3996 /* Return true if the bare return instruction can be used outside of the
3997 epilog code. For frv, we only do it if there was no stack allocation. */
4000 direct_return_p (void)
4004 if (!reload_completed)
4007 info = frv_stack_info ();
4008 return (info->total_size == 0);
4013 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
4015 if (GET_CODE (src) == SYMBOL_REF)
4017 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
4019 src = frv_legitimize_tls_address (src, model);
4025 if (frv_emit_movsi (dest, src))
4034 if (!reload_in_progress
4035 && !reload_completed
4036 && !register_operand (dest, mode)
4037 && !reg_or_0_operand (src, mode))
4038 src = copy_to_mode_reg (mode, src);
4045 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4048 /* Emit code to handle a MOVSI, adding in the small data register or pic
4049 register if needed to load up addresses. Return TRUE if the appropriate
4050 instructions are emitted. */
4053 frv_emit_movsi (rtx dest, rtx src)
4055 int base_regno = -1;
4058 struct frv_unspec old_unspec;
4060 if (!reload_in_progress
4061 && !reload_completed
4062 && !register_operand (dest, SImode)
4063 && (!reg_or_0_operand (src, SImode)
4064 /* Virtual registers will almost always be replaced by an
4065 add instruction, so expose this to CSE by copying to
4066 an intermediate register. */
4067 || (GET_CODE (src) == REG
4068 && IN_RANGE_P (REGNO (src),
4069 FIRST_VIRTUAL_REGISTER,
4070 LAST_VIRTUAL_REGISTER))))
4072 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4076 /* Explicitly add in the PIC or small data register if needed. */
4077 switch (GET_CODE (src))
4086 /* Using GPREL12, we use a single GOT entry for all symbols
4087 in read-only sections, but trade sequences such as:
4089 sethi #gothi(label), gr#
4090 setlo #gotlo(label), gr#
4095 ld @(gr15,#got12(_gp)), gr#
4096 sethi #gprelhi(label), gr##
4097 setlo #gprello(label), gr##
4100 We may often be able to share gr# for multiple
4101 computations of GPREL addresses, and we may often fold
4102 the final add into the pair of registers of a load or
4103 store instruction, so it's often profitable. Even when
4104 optimizing for size, we're trading a GOT entry for an
4105 additional instruction, which trades GOT space
4106 (read-write) for code size (read-only, shareable), as
4107 long as the symbol is not used in more than two different
4110 With -fpie/-fpic, we'd be trading a single load for a
4111 sequence of 4 instructions, because the offset of the
4112 label can't be assumed to be addressable with 12 bits, so
4113 we don't do this. */
4114 if (TARGET_GPREL_RO)
4115 unspec = R_FRV_GPREL12;
4117 unspec = R_FRV_GOT12;
4120 base_regno = PIC_REGNO;
4125 if (frv_const_unspec_p (src, &old_unspec))
4128 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4131 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4132 emit_move_insn (dest, src);
4137 sym = XEXP (sym, 0);
4138 if (GET_CODE (sym) == PLUS
4139 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4140 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4141 sym = XEXP (sym, 0);
4142 if (GET_CODE (sym) == SYMBOL_REF)
4144 else if (GET_CODE (sym) == LABEL_REF)
4147 goto handle_whatever;
4155 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4159 src = frv_legitimize_tls_address (src, model);
4160 emit_move_insn (dest, src);
4164 if (SYMBOL_REF_FUNCTION_P (sym))
4166 if (frv_local_funcdesc_p (sym))
4167 unspec = R_FRV_FUNCDESC_GOTOFF12;
4169 unspec = R_FRV_FUNCDESC_GOT12;
4173 if (CONSTANT_POOL_ADDRESS_P (sym))
4174 switch (GET_CODE (get_pool_constant (sym)))
4181 unspec = R_FRV_GOTOFF12;
4186 if (TARGET_GPREL_RO)
4187 unspec = R_FRV_GPREL12;
4189 unspec = R_FRV_GOT12;
4192 else if (SYMBOL_REF_LOCAL_P (sym)
4193 && !SYMBOL_REF_EXTERNAL_P (sym)
4194 && SYMBOL_REF_DECL (sym)
4195 && (!DECL_P (SYMBOL_REF_DECL (sym))
4196 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4198 tree decl = SYMBOL_REF_DECL (sym);
4199 tree init = TREE_CODE (decl) == VAR_DECL
4200 ? DECL_INITIAL (decl)
4201 : TREE_CODE (decl) == CONSTRUCTOR
4204 bool named_section, readonly;
4206 if (init && init != error_mark_node)
4207 reloc = compute_reloc_for_constant (init);
4209 named_section = TREE_CODE (decl) == VAR_DECL
4210 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4211 readonly = decl_readonly_section (decl, reloc);
4214 unspec = R_FRV_GOT12;
4216 unspec = R_FRV_GOTOFF12;
4217 else if (readonly && TARGET_GPREL_RO)
4218 unspec = R_FRV_GPREL12;
4220 unspec = R_FRV_GOT12;
4223 unspec = R_FRV_GOT12;
4227 else if (SYMBOL_REF_SMALL_P (sym))
4228 base_regno = SDA_BASE_REG;
4231 base_regno = PIC_REGNO;
4236 if (base_regno >= 0)
4238 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4239 emit_insn (gen_symGOTOFF2reg (dest, src,
4240 gen_rtx_REG (Pmode, base_regno),
4241 GEN_INT (R_FRV_GPREL12)));
4243 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4244 gen_rtx_REG (Pmode, base_regno),
4245 GEN_INT (R_FRV_GPREL12)));
4246 if (base_regno == PIC_REGNO)
4247 crtl->uses_pic_offset_table = TRUE;
4255 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4256 new uses of it once reload has begun. */
4257 gcc_assert (!reload_in_progress && !reload_completed);
4261 case R_FRV_GOTOFF12:
4262 if (!frv_small_data_reloc_p (sym, unspec))
4263 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4266 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4269 if (!frv_small_data_reloc_p (sym, unspec))
4270 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4273 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4275 case R_FRV_FUNCDESC_GOTOFF12:
4277 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4280 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4284 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4287 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4291 crtl->uses_pic_offset_table = TRUE;
4300 /* Return a string to output a single word move. */
4303 output_move_single (rtx operands[], rtx insn)
4305 rtx dest = operands[0];
4306 rtx src = operands[1];
4308 if (GET_CODE (dest) == REG)
4310 int dest_regno = REGNO (dest);
4311 enum machine_mode mode = GET_MODE (dest);
4313 if (GPR_P (dest_regno))
4315 if (GET_CODE (src) == REG)
4317 /* gpr <- some sort of register */
4318 int src_regno = REGNO (src);
4320 if (GPR_P (src_regno))
4321 return "mov %1, %0";
4323 else if (FPR_P (src_regno))
4324 return "movfg %1, %0";
4326 else if (SPR_P (src_regno))
4327 return "movsg %1, %0";
4330 else if (GET_CODE (src) == MEM)
4339 return "ldsb%I1%U1 %M1,%0";
4342 return "ldsh%I1%U1 %M1,%0";
4346 return "ld%I1%U1 %M1, %0";
4350 else if (GET_CODE (src) == CONST_INT
4351 || GET_CODE (src) == CONST_DOUBLE)
4353 /* gpr <- integer/floating constant */
4354 HOST_WIDE_INT value;
4356 if (GET_CODE (src) == CONST_INT)
4357 value = INTVAL (src);
4359 else if (mode == SFmode)
4364 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4365 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4370 value = CONST_DOUBLE_LOW (src);
4372 if (IN_RANGE_P (value, -32768, 32767))
4373 return "setlos %1, %0";
4378 else if (GET_CODE (src) == SYMBOL_REF
4379 || GET_CODE (src) == LABEL_REF
4380 || GET_CODE (src) == CONST)
4386 else if (FPR_P (dest_regno))
4388 if (GET_CODE (src) == REG)
4390 /* fpr <- some sort of register */
4391 int src_regno = REGNO (src);
4393 if (GPR_P (src_regno))
4394 return "movgf %1, %0";
4396 else if (FPR_P (src_regno))
4398 if (TARGET_HARD_FLOAT)
4399 return "fmovs %1, %0";
4401 return "mor %1, %1, %0";
4405 else if (GET_CODE (src) == MEM)
4414 return "ldbf%I1%U1 %M1,%0";
4417 return "ldhf%I1%U1 %M1,%0";
4421 return "ldf%I1%U1 %M1, %0";
4425 else if (ZERO_P (src))
4426 return "movgf %., %0";
4429 else if (SPR_P (dest_regno))
4431 if (GET_CODE (src) == REG)
4433 /* spr <- some sort of register */
4434 int src_regno = REGNO (src);
4436 if (GPR_P (src_regno))
4437 return "movgs %1, %0";
4439 else if (ZERO_P (src))
4440 return "movgs %., %0";
4444 else if (GET_CODE (dest) == MEM)
4446 if (GET_CODE (src) == REG)
4448 int src_regno = REGNO (src);
4449 enum machine_mode mode = GET_MODE (dest);
4451 if (GPR_P (src_regno))
4459 return "stb%I0%U0 %1, %M0";
4462 return "sth%I0%U0 %1, %M0";
4466 return "st%I0%U0 %1, %M0";
4470 else if (FPR_P (src_regno))
4478 return "stbf%I0%U0 %1, %M0";
4481 return "sthf%I0%U0 %1, %M0";
4485 return "stf%I0%U0 %1, %M0";
4490 else if (ZERO_P (src))
4492 switch (GET_MODE (dest))
4498 return "stb%I0%U0 %., %M0";
4501 return "sth%I0%U0 %., %M0";
4505 return "st%I0%U0 %., %M0";
4510 fatal_insn ("bad output_move_single operand", insn);
4515 /* Return a string to output a double word move. */
4518 output_move_double (rtx operands[], rtx insn)
4520 rtx dest = operands[0];
4521 rtx src = operands[1];
4522 enum machine_mode mode = GET_MODE (dest);
4524 if (GET_CODE (dest) == REG)
4526 int dest_regno = REGNO (dest);
4528 if (GPR_P (dest_regno))
4530 if (GET_CODE (src) == REG)
4532 /* gpr <- some sort of register */
4533 int src_regno = REGNO (src);
4535 if (GPR_P (src_regno))
4538 else if (FPR_P (src_regno))
4540 if (((dest_regno - GPR_FIRST) & 1) == 0
4541 && ((src_regno - FPR_FIRST) & 1) == 0)
4542 return "movfgd %1, %0";
4548 else if (GET_CODE (src) == MEM)
4551 if (dbl_memory_one_insn_operand (src, mode))
4552 return "ldd%I1%U1 %M1, %0";
4557 else if (GET_CODE (src) == CONST_INT
4558 || GET_CODE (src) == CONST_DOUBLE)
4562 else if (FPR_P (dest_regno))
4564 if (GET_CODE (src) == REG)
4566 /* fpr <- some sort of register */
4567 int src_regno = REGNO (src);
4569 if (GPR_P (src_regno))
4571 if (((dest_regno - FPR_FIRST) & 1) == 0
4572 && ((src_regno - GPR_FIRST) & 1) == 0)
4573 return "movgfd %1, %0";
4578 else if (FPR_P (src_regno))
4581 && ((dest_regno - FPR_FIRST) & 1) == 0
4582 && ((src_regno - FPR_FIRST) & 1) == 0)
4583 return "fmovd %1, %0";
4589 else if (GET_CODE (src) == MEM)
4592 if (dbl_memory_one_insn_operand (src, mode))
4593 return "lddf%I1%U1 %M1, %0";
4598 else if (ZERO_P (src))
4603 else if (GET_CODE (dest) == MEM)
4605 if (GET_CODE (src) == REG)
4607 int src_regno = REGNO (src);
4609 if (GPR_P (src_regno))
4611 if (((src_regno - GPR_FIRST) & 1) == 0
4612 && dbl_memory_one_insn_operand (dest, mode))
4613 return "std%I0%U0 %1, %M0";
4618 if (FPR_P (src_regno))
4620 if (((src_regno - FPR_FIRST) & 1) == 0
4621 && dbl_memory_one_insn_operand (dest, mode))
4622 return "stdf%I0%U0 %1, %M0";
4628 else if (ZERO_P (src))
4630 if (dbl_memory_one_insn_operand (dest, mode))
4631 return "std%I0%U0 %., %M0";
4637 fatal_insn ("bad output_move_double operand", insn);
4642 /* Return a string to output a single word conditional move.
4643 Operand0 -- EQ/NE of ccr register and 0
4644 Operand1 -- CCR register
4645 Operand2 -- destination
4646 Operand3 -- source */
4649 output_condmove_single (rtx operands[], rtx insn)
4651 rtx dest = operands[2];
4652 rtx src = operands[3];
4654 if (GET_CODE (dest) == REG)
4656 int dest_regno = REGNO (dest);
4657 enum machine_mode mode = GET_MODE (dest);
4659 if (GPR_P (dest_regno))
4661 if (GET_CODE (src) == REG)
4663 /* gpr <- some sort of register */
4664 int src_regno = REGNO (src);
4666 if (GPR_P (src_regno))
4667 return "cmov %z3, %2, %1, %e0";
4669 else if (FPR_P (src_regno))
4670 return "cmovfg %3, %2, %1, %e0";
4673 else if (GET_CODE (src) == MEM)
4682 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4685 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4689 return "cld%I3%U3 %M3, %2, %1, %e0";
4693 else if (ZERO_P (src))
4694 return "cmov %., %2, %1, %e0";
4697 else if (FPR_P (dest_regno))
4699 if (GET_CODE (src) == REG)
4701 /* fpr <- some sort of register */
4702 int src_regno = REGNO (src);
4704 if (GPR_P (src_regno))
4705 return "cmovgf %3, %2, %1, %e0";
4707 else if (FPR_P (src_regno))
4709 if (TARGET_HARD_FLOAT)
4710 return "cfmovs %3,%2,%1,%e0";
4712 return "cmor %3, %3, %2, %1, %e0";
4716 else if (GET_CODE (src) == MEM)
4719 if (mode == SImode || mode == SFmode)
4720 return "cldf%I3%U3 %M3, %2, %1, %e0";
4723 else if (ZERO_P (src))
4724 return "cmovgf %., %2, %1, %e0";
4728 else if (GET_CODE (dest) == MEM)
4730 if (GET_CODE (src) == REG)
4732 int src_regno = REGNO (src);
4733 enum machine_mode mode = GET_MODE (dest);
4735 if (GPR_P (src_regno))
4743 return "cstb%I2%U2 %3, %M2, %1, %e0";
4746 return "csth%I2%U2 %3, %M2, %1, %e0";
4750 return "cst%I2%U2 %3, %M2, %1, %e0";
4754 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4755 return "cstf%I2%U2 %3, %M2, %1, %e0";
4758 else if (ZERO_P (src))
4760 enum machine_mode mode = GET_MODE (dest);
4767 return "cstb%I2%U2 %., %M2, %1, %e0";
4770 return "csth%I2%U2 %., %M2, %1, %e0";
4774 return "cst%I2%U2 %., %M2, %1, %e0";
4779 fatal_insn ("bad output_condmove_single operand", insn);
4784 /* Emit the appropriate code to do a comparison, returning the register the
4785 comparison was done it. */
4788 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4790 enum machine_mode cc_mode;
4793 /* Floating point doesn't have comparison against a constant. */
4794 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4795 op1 = force_reg (GET_MODE (op0), op1);
4797 /* Possibly disable using anything but a fixed register in order to work
4798 around cse moving comparisons past function calls. */
4799 cc_mode = SELECT_CC_MODE (test, op0, op1);
4800 cc_reg = ((TARGET_ALLOC_CC)
4801 ? gen_reg_rtx (cc_mode)
4802 : gen_rtx_REG (cc_mode,
4803 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4805 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4806 gen_rtx_COMPARE (cc_mode, op0, op1)));
4812 /* Emit code for a conditional branch.
4813 XXX: I originally wanted to add a clobber of a CCR register to use in
4814 conditional execution, but that confuses the rest of the compiler. */
4817 frv_emit_cond_branch (rtx operands[])
4822 enum rtx_code test = GET_CODE (operands[0]);
4823 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4824 enum machine_mode cc_mode = GET_MODE (cc_reg);
4826 /* Branches generate:
4828 (if_then_else (<test>, <cc_reg>, (const_int 0))
4829 (label_ref <branch_label>)
4831 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4832 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4833 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4834 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4839 /* Emit code to set a gpr to 1/0 based on a comparison. */
4842 frv_emit_scc (rtx operands[])
4848 enum rtx_code test = GET_CODE (operands[1]);
4849 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4851 /* SCC instructions generate:
4852 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4853 (clobber (<ccr_reg>))]) */
4854 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4855 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4857 cr_reg = ((TARGET_ALLOC_CC)
4858 ? gen_reg_rtx (CC_CCRmode)
4859 : gen_rtx_REG (CC_CCRmode,
4860 ((GET_MODE (cc_reg) == CC_FPmode)
4864 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4865 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4870 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4871 the separate insns. */
4874 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4880 /* Set the appropriate CCR bit. */
4881 emit_insn (gen_rtx_SET (VOIDmode,
4883 gen_rtx_fmt_ee (GET_CODE (test),
4888 /* Move the value into the destination. */
4889 emit_move_insn (dest, GEN_INT (value));
4891 /* Move 0 into the destination if the test failed */
4892 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4893 gen_rtx_EQ (GET_MODE (cr_reg),
4896 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4898 /* Finish up, return sequence. */
4905 /* Emit the code for a conditional move, return TRUE if we could do the
4909 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4916 enum rtx_code test = GET_CODE (test_rtx);
4917 rtx cc_reg = frv_emit_comparison (test,
4918 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4919 enum machine_mode cc_mode = GET_MODE (cc_reg);
4921 /* Conditional move instructions generate:
4922 (parallel [(set <target>
4923 (if_then_else (<test> <cc_reg> (const_int 0))
4926 (clobber (<ccr_reg>))]) */
4928 /* Handle various cases of conditional move involving two constants. */
4929 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4931 HOST_WIDE_INT value1 = INTVAL (src1);
4932 HOST_WIDE_INT value2 = INTVAL (src2);
4934 /* Having 0 as one of the constants can be done by loading the other
4935 constant, and optionally moving in gr0. */
4936 if (value1 == 0 || value2 == 0)
4939 /* If the first value is within an addi range and also the difference
4940 between the two fits in an addi's range, load up the difference, then
4941 conditionally move in 0, and then unconditionally add the first
4943 else if (IN_RANGE_P (value1, -2048, 2047)
4944 && IN_RANGE_P (value2 - value1, -2048, 2047))
4947 /* If neither condition holds, just force the constant into a
4951 src1 = force_reg (GET_MODE (dest), src1);
4952 src2 = force_reg (GET_MODE (dest), src2);
4956 /* If one value is a register, insure the other value is either 0 or a
4960 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4961 src1 = force_reg (GET_MODE (dest), src1);
4963 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4964 src2 = force_reg (GET_MODE (dest), src2);
4967 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4968 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4970 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4972 cr_reg = ((TARGET_ALLOC_CC)
4973 ? gen_reg_rtx (CC_CCRmode)
4974 : gen_rtx_REG (CC_CCRmode,
4975 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4977 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4978 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4983 /* Split a conditional move into constituent parts, returning a SEQUENCE
4984 containing all of the insns. */
4987 frv_split_cond_move (rtx operands[])
4989 rtx dest = operands[0];
4990 rtx test = operands[1];
4991 rtx cc_reg = operands[2];
4992 rtx src1 = operands[3];
4993 rtx src2 = operands[4];
4994 rtx cr_reg = operands[5];
4996 enum machine_mode cr_mode = GET_MODE (cr_reg);
5000 /* Set the appropriate CCR bit. */
5001 emit_insn (gen_rtx_SET (VOIDmode,
5003 gen_rtx_fmt_ee (GET_CODE (test),
5008 /* Handle various cases of conditional move involving two constants. */
5009 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
5011 HOST_WIDE_INT value1 = INTVAL (src1);
5012 HOST_WIDE_INT value2 = INTVAL (src2);
5014 /* Having 0 as one of the constants can be done by loading the other
5015 constant, and optionally moving in gr0. */
5018 emit_move_insn (dest, src2);
5019 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5020 gen_rtx_NE (cr_mode, cr_reg,
5022 gen_rtx_SET (VOIDmode, dest, src1)));
5025 else if (value2 == 0)
5027 emit_move_insn (dest, src1);
5028 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5029 gen_rtx_EQ (cr_mode, cr_reg,
5031 gen_rtx_SET (VOIDmode, dest, src2)));
5034 /* If the first value is within an addi range and also the difference
5035 between the two fits in an addi's range, load up the difference, then
5036 conditionally move in 0, and then unconditionally add the first
5038 else if (IN_RANGE_P (value1, -2048, 2047)
5039 && IN_RANGE_P (value2 - value1, -2048, 2047))
5041 rtx dest_si = ((GET_MODE (dest) == SImode)
5043 : gen_rtx_SUBREG (SImode, dest, 0));
5045 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5046 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5047 gen_rtx_NE (cr_mode, cr_reg,
5049 gen_rtx_SET (VOIDmode, dest_si,
5051 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5059 /* Emit the conditional move for the test being true if needed. */
5060 if (! rtx_equal_p (dest, src1))
5061 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5062 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5063 gen_rtx_SET (VOIDmode, dest, src1)));
5065 /* Emit the conditional move for the test being false if needed. */
5066 if (! rtx_equal_p (dest, src2))
5067 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5068 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5069 gen_rtx_SET (VOIDmode, dest, src2)));
5072 /* Finish up, return sequence. */
5079 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5080 memory location that is not known to be dword-aligned. */
5082 frv_split_double_load (rtx dest, rtx source)
5084 int regno = REGNO (dest);
5085 rtx dest1 = gen_highpart (SImode, dest);
5086 rtx dest2 = gen_lowpart (SImode, dest);
5087 rtx address = XEXP (source, 0);
5089 /* If the address is pre-modified, load the lower-numbered register
5090 first, then load the other register using an integer offset from
5091 the modified base register. This order should always be safe,
5092 since the pre-modification cannot affect the same registers as the
5095 The situation for other loads is more complicated. Loading one
5096 of the registers could affect the value of ADDRESS, so we must
5097 be careful which order we do them in. */
5098 if (GET_CODE (address) == PRE_MODIFY
5099 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5101 /* It is safe to load the lower-numbered register first. */
5102 emit_move_insn (dest1, change_address (source, SImode, NULL));
5103 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5107 /* ADDRESS is not pre-modified and the address depends on the
5108 lower-numbered register. Load the higher-numbered register
5110 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5111 emit_move_insn (dest1, change_address (source, SImode, NULL));
5115 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5116 and SOURCE is either a double register or the constant zero. */
5118 frv_split_double_store (rtx dest, rtx source)
5120 rtx dest1 = change_address (dest, SImode, NULL);
5121 rtx dest2 = frv_index_memory (dest, SImode, 1);
5122 if (ZERO_P (source))
5124 emit_move_insn (dest1, CONST0_RTX (SImode));
5125 emit_move_insn (dest2, CONST0_RTX (SImode));
5129 emit_move_insn (dest1, gen_highpart (SImode, source));
5130 emit_move_insn (dest2, gen_lowpart (SImode, source));
5135 /* Split a min/max operation returning a SEQUENCE containing all of the
5139 frv_split_minmax (rtx operands[])
5141 rtx dest = operands[0];
5142 rtx minmax = operands[1];
5143 rtx src1 = operands[2];
5144 rtx src2 = operands[3];
5145 rtx cc_reg = operands[4];
5146 rtx cr_reg = operands[5];
5148 enum rtx_code test_code;
5149 enum machine_mode cr_mode = GET_MODE (cr_reg);
5153 /* Figure out which test to use. */
5154 switch (GET_CODE (minmax))
5159 case SMIN: test_code = LT; break;
5160 case SMAX: test_code = GT; break;
5161 case UMIN: test_code = LTU; break;
5162 case UMAX: test_code = GTU; break;
5165 /* Issue the compare instruction. */
5166 emit_insn (gen_rtx_SET (VOIDmode,
5168 gen_rtx_COMPARE (GET_MODE (cc_reg),
5171 /* Set the appropriate CCR bit. */
5172 emit_insn (gen_rtx_SET (VOIDmode,
5174 gen_rtx_fmt_ee (test_code,
5179 /* If are taking the min/max of a nonzero constant, load that first, and
5180 then do a conditional move of the other value. */
5181 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5183 gcc_assert (!rtx_equal_p (dest, src1));
5185 emit_move_insn (dest, src2);
5186 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5187 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5188 gen_rtx_SET (VOIDmode, dest, src1)));
5191 /* Otherwise, do each half of the move. */
5194 /* Emit the conditional move for the test being true if needed. */
5195 if (! rtx_equal_p (dest, src1))
5196 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5197 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5198 gen_rtx_SET (VOIDmode, dest, src1)));
5200 /* Emit the conditional move for the test being false if needed. */
5201 if (! rtx_equal_p (dest, src2))
5202 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5203 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5204 gen_rtx_SET (VOIDmode, dest, src2)));
5207 /* Finish up, return sequence. */
5214 /* Split an integer abs operation returning a SEQUENCE containing all of the
5218 frv_split_abs (rtx operands[])
5220 rtx dest = operands[0];
5221 rtx src = operands[1];
5222 rtx cc_reg = operands[2];
5223 rtx cr_reg = operands[3];
5228 /* Issue the compare < 0 instruction. */
5229 emit_insn (gen_rtx_SET (VOIDmode,
5231 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5233 /* Set the appropriate CCR bit. */
5234 emit_insn (gen_rtx_SET (VOIDmode,
5236 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5238 /* Emit the conditional negate if the value is negative. */
5239 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5240 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5241 gen_negsi2 (dest, src)));
5243 /* Emit the conditional move for the test being false if needed. */
5244 if (! rtx_equal_p (dest, src))
5245 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5246 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5247 gen_rtx_SET (VOIDmode, dest, src)));
5249 /* Finish up, return sequence. */
5256 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5257 register used in an insn. */
5260 frv_clear_registers_used (rtx *ptr, void *data)
5262 if (GET_CODE (*ptr) == REG)
5264 int regno = REGNO (*ptr);
5265 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5267 if (regno < FIRST_PSEUDO_REGISTER)
5269 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5271 while (regno < reg_max)
5273 CLEAR_HARD_REG_BIT (*p_regs, regno);
5283 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5285 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5286 initialize the static storage. */
5288 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5290 frv_ifcvt.added_insns_list = NULL_RTX;
5291 frv_ifcvt.cur_scratch_regs = 0;
5292 frv_ifcvt.num_nested_cond_exec = 0;
5293 frv_ifcvt.cr_reg = NULL_RTX;
5294 frv_ifcvt.nested_cc_reg = NULL_RTX;
5295 frv_ifcvt.extra_int_cr = NULL_RTX;
5296 frv_ifcvt.extra_fp_cr = NULL_RTX;
5297 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5301 /* Internal function to add a potential insn to the list of insns to be inserted
5302 if the conditional execution conversion is successful. */
5305 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5307 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5309 link->jump = before_p; /* Mark to add this before or after insn. */
5310 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5311 frv_ifcvt.added_insns_list);
5313 if (TARGET_DEBUG_COND_EXEC)
5316 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5317 (before_p) ? "before" : "after",
5318 (int)INSN_UID (insn));
5320 debug_rtx (pattern);
5325 /* A C expression to modify the code described by the conditional if
5326 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5327 FALSE_EXPR for converting if-then and if-then-else code to conditional
5328 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5329 tests cannot be converted. */
5332 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5334 basic_block test_bb = ce_info->test_bb; /* test basic block */
5335 basic_block then_bb = ce_info->then_bb; /* THEN */
5336 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5337 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5338 rtx true_expr = *p_true;
5342 enum machine_mode mode = GET_MODE (true_expr);
5346 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5348 rtx sub_cond_exec_reg;
5350 enum rtx_code code_true;
5351 enum rtx_code code_false;
5352 enum reg_class cc_class;
5353 enum reg_class cr_class;
5356 reg_set_iterator rsi;
5358 /* Make sure we are only dealing with hard registers. Also honor the
5359 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5361 if (!reload_completed || !TARGET_COND_EXEC
5362 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5365 /* Figure out which registers we can allocate for our own purposes. Only
5366 consider registers that are not preserved across function calls and are
5367 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5368 if we did not need to use them in reloading other registers. */
5369 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5370 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5371 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5372 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5373 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5375 /* If this is a nested IF, we need to discover whether the CC registers that
5376 are set/used inside of the block are used anywhere else. If not, we can
5377 change them to be the CC register that is paired with the CR register that
5378 controls the outermost IF block. */
5379 if (ce_info->pass > 1)
5381 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5382 for (j = CC_FIRST; j <= CC_LAST; j++)
5383 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5385 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5389 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5393 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5396 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5400 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5401 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5403 frv_ifcvt.added_insns_list = NULL_RTX;
5404 frv_ifcvt.cur_scratch_regs = 0;
5406 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5407 * sizeof (basic_block));
5413 /* Remove anything live at the beginning of the join block from being
5414 available for allocation. */
5415 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5417 if (regno < FIRST_PSEUDO_REGISTER)
5418 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5422 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5424 if (ce_info->num_multiple_test_blocks)
5426 basic_block multiple_test_bb = ce_info->last_test_bb;
5428 while (multiple_test_bb != test_bb)
5430 bb[num_bb++] = multiple_test_bb;
5431 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5435 /* Add in the THEN and ELSE blocks to be scanned. */
5436 bb[num_bb++] = then_bb;
5438 bb[num_bb++] = else_bb;
5440 sub_cond_exec_reg = NULL_RTX;
5441 frv_ifcvt.num_nested_cond_exec = 0;
5443 /* Scan all of the blocks for registers that must not be allocated. */
5444 for (j = 0; j < num_bb; j++)
5446 rtx last_insn = BB_END (bb[j]);
5447 rtx insn = BB_HEAD (bb[j]);
5451 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5452 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5454 (int) INSN_UID (BB_HEAD (bb[j])),
5455 (int) INSN_UID (BB_END (bb[j])));
5457 /* Anything live at the beginning of the block is obviously unavailable
5459 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5461 if (regno < FIRST_PSEUDO_REGISTER)
5462 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5465 /* Loop through the insns in the block. */
5468 /* Mark any new registers that are created as being unavailable for
5469 allocation. Also see if the CC register used in nested IFs can be
5475 int skip_nested_if = FALSE;
5477 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5478 (void *)&tmp_reg->regs);
5480 pattern = PATTERN (insn);
5481 if (GET_CODE (pattern) == COND_EXEC)
5483 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5485 if (reg != sub_cond_exec_reg)
5487 sub_cond_exec_reg = reg;
5488 frv_ifcvt.num_nested_cond_exec++;
5492 set = single_set_pattern (pattern);
5495 rtx dest = SET_DEST (set);
5496 rtx src = SET_SRC (set);
5498 if (GET_CODE (dest) == REG)
5500 int regno = REGNO (dest);
5501 enum rtx_code src_code = GET_CODE (src);
5503 if (CC_P (regno) && src_code == COMPARE)
5504 skip_nested_if = TRUE;
5506 else if (CR_P (regno)
5507 && (src_code == IF_THEN_ELSE
5508 || COMPARISON_P (src)))
5509 skip_nested_if = TRUE;
5513 if (! skip_nested_if)
5514 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5515 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5518 if (insn == last_insn)
5521 insn = NEXT_INSN (insn);
5525 /* If this is a nested if, rewrite the CC registers that are available to
5526 include the ones that can be rewritten, to increase the chance of being
5527 able to allocate a paired CC/CR register combination. */
5528 if (ce_info->pass > 1)
5530 for (j = CC_FIRST; j <= CC_LAST; j++)
5531 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5532 SET_HARD_REG_BIT (tmp_reg->regs, j);
5534 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5540 fprintf (dump_file, "Available GPRs: ");
5542 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5543 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5545 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5546 if (++num_gprs > GPR_TEMP_NUM+2)
5550 fprintf (dump_file, "%s\nAvailable CRs: ",
5551 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5553 for (j = CR_FIRST; j <= CR_LAST; j++)
5554 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5555 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5557 fputs ("\n", dump_file);
5559 if (ce_info->pass > 1)
5561 fprintf (dump_file, "Modifiable CCs: ");
5562 for (j = CC_FIRST; j <= CC_LAST; j++)
5563 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5564 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5566 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5567 frv_ifcvt.num_nested_cond_exec);
5571 /* Allocate the appropriate temporary condition code register. Try to
5572 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5573 that conditional cmp's can be done. */
5574 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5576 cr_class = ICR_REGS;
5577 cc_class = ICC_REGS;
5578 cc_first = ICC_FIRST;
5581 else if (mode == CC_FPmode)
5583 cr_class = FCR_REGS;
5584 cc_class = FCC_REGS;
5585 cc_first = FCC_FIRST;
5590 cc_first = cc_last = 0;
5591 cr_class = cc_class = NO_REGS;
5594 cc = XEXP (true_expr, 0);
5595 nested_cc = cr = NULL_RTX;
5596 if (cc_class != NO_REGS)
5598 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5599 so we can execute a csubcc/caddcc/cfcmps instruction. */
5602 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5604 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5606 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5607 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5609 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5610 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5613 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5614 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5624 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5631 "Will use %s for conditional execution, %s for nested comparisons\n",
5632 reg_names[ REGNO (cr)],
5633 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5635 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5636 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5637 bit being true. We don't do this for floating point, because of NaNs. */
5638 code = GET_CODE (true_expr);
5639 if (GET_MODE (cc) != CC_FPmode)
5641 code = reverse_condition (code);
5651 check_insn = gen_rtx_SET (VOIDmode, cr,
5652 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5654 /* Record the check insn to be inserted later. */
5655 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5657 /* Update the tests. */
5658 frv_ifcvt.cr_reg = cr;
5659 frv_ifcvt.nested_cc_reg = nested_cc;
5660 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5661 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5664 /* Fail, don't do this conditional execution. */
5667 *p_false = NULL_RTX;
5669 fprintf (dump_file, "Disabling this conditional execution.\n");
5675 /* A C expression to modify the code described by the conditional if
5676 information CE_INFO, for the basic block BB, possibly updating the tests in
5677 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5678 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5679 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5681 /* p_true and p_false are given expressions of the form:
5683 (and (eq:CC_CCR (reg:CC_CCR)
5689 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5694 rtx old_true = XEXP (*p_true, 0);
5695 rtx old_false = XEXP (*p_false, 0);
5696 rtx true_expr = XEXP (*p_true, 1);
5697 rtx false_expr = XEXP (*p_false, 1);
5700 rtx cr = XEXP (old_true, 0);
5702 rtx new_cr = NULL_RTX;
5703 rtx *p_new_cr = (rtx *)0;
5707 enum reg_class cr_class;
5708 enum machine_mode mode = GET_MODE (true_expr);
5709 rtx (*logical_func)(rtx, rtx, rtx);
5711 if (TARGET_DEBUG_COND_EXEC)
5714 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5715 ce_info->and_and_p ? "&&" : "||");
5717 debug_rtx (*p_true);
5719 fputs ("\nfalse insn:\n", stderr);
5720 debug_rtx (*p_false);
5723 if (!TARGET_MULTI_CE)
5726 if (GET_CODE (cr) != REG)
5729 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5731 cr_class = ICR_REGS;
5732 p_new_cr = &frv_ifcvt.extra_int_cr;
5734 else if (mode == CC_FPmode)
5736 cr_class = FCR_REGS;
5737 p_new_cr = &frv_ifcvt.extra_fp_cr;
5742 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5743 more &&/|| tests. */
5747 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5748 CC_CCRmode, TRUE, TRUE);
5753 if (ce_info->and_and_p)
5755 old_test = old_false;
5756 test_expr = true_expr;
5757 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5758 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5759 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5763 old_test = old_false;
5764 test_expr = false_expr;
5765 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5766 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5767 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5770 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5771 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5773 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5775 /* Now add the conditional check insn. */
5776 cc = XEXP (test_expr, 0);
5777 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5778 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5780 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5782 /* Add the new check insn to the list of check insns that need to be
5784 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5786 if (TARGET_DEBUG_COND_EXEC)
5788 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5791 debug_rtx (*p_true);
5793 fputs ("\nfalse insn:\n", stderr);
5794 debug_rtx (*p_false);
5800 *p_true = *p_false = NULL_RTX;
5802 /* If we allocated a CR register, release it. */
5805 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5806 *p_new_cr = NULL_RTX;
5809 if (TARGET_DEBUG_COND_EXEC)
5810 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5816 /* Return a register which will be loaded with a value if an IF block is
5817 converted to conditional execution. This is used to rewrite instructions
5818 that use constants to ones that just use registers. */
5821 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5823 int num_alloc = frv_ifcvt.cur_scratch_regs;
5827 /* We know gr0 == 0, so replace any errant uses. */
5828 if (value == const0_rtx)
5829 return gen_rtx_REG (SImode, GPR_FIRST);
5831 /* First search all registers currently loaded to see if we have an
5832 applicable constant. */
5833 if (CONSTANT_P (value)
5834 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5836 for (i = 0; i < num_alloc; i++)
5838 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5839 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5843 /* Have we exhausted the number of registers available? */
5844 if (num_alloc >= GPR_TEMP_NUM)
5847 fprintf (dump_file, "Too many temporary registers allocated\n");
5852 /* Allocate the new register. */
5853 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5857 fputs ("Could not find a scratch register\n", dump_file);
5862 frv_ifcvt.cur_scratch_regs++;
5863 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5867 if (GET_CODE (value) == CONST_INT)
5868 fprintf (dump_file, "Register %s will hold %ld\n",
5869 reg_names[ REGNO (reg)], (long)INTVAL (value));
5871 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5872 fprintf (dump_file, "Register %s will hold LR\n",
5873 reg_names[ REGNO (reg)]);
5876 fprintf (dump_file, "Register %s will hold a saved value\n",
5877 reg_names[ REGNO (reg)]);
5884 /* Update a MEM used in conditional code that might contain an offset to put
5885 the offset into a scratch register, so that the conditional load/store
5886 operations can be used. This function returns the original pointer if the
5887 MEM is valid to use in conditional code, NULL if we can't load up the offset
5888 into a temporary register, or the new MEM if we were successful. */
5891 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5893 rtx addr = XEXP (mem, 0);
5895 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5897 if (GET_CODE (addr) == PLUS)
5899 rtx addr_op0 = XEXP (addr, 0);
5900 rtx addr_op1 = XEXP (addr, 1);
5902 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5904 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5908 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5915 else if (CONSTANT_P (addr))
5916 addr = frv_ifcvt_load_value (addr, insn);
5921 if (addr == NULL_RTX)
5924 else if (XEXP (mem, 0) != addr)
5925 return change_address (mem, mode, addr);
5932 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5933 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5936 single_set_pattern (rtx pattern)
5941 if (GET_CODE (pattern) == COND_EXEC)
5942 pattern = COND_EXEC_CODE (pattern);
5944 if (GET_CODE (pattern) == SET)
5947 else if (GET_CODE (pattern) == PARALLEL)
5949 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5951 rtx sub = XVECEXP (pattern, 0, i);
5953 switch (GET_CODE (sub))
5977 /* A C expression to modify the code described by the conditional if
5978 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5979 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5980 insn cannot be converted to be executed conditionally. */
5983 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5987 rtx orig_ce_pattern = pattern;
5993 gcc_assert (GET_CODE (pattern) == COND_EXEC);
5995 test = COND_EXEC_TEST (pattern);
5996 if (GET_CODE (test) == AND)
5998 rtx cr = frv_ifcvt.cr_reg;
6001 op0 = XEXP (test, 0);
6002 if (! rtx_equal_p (cr, XEXP (op0, 0)))
6005 op1 = XEXP (test, 1);
6006 test_reg = XEXP (op1, 0);
6007 if (GET_CODE (test_reg) != REG)
6010 /* Is this the first nested if block in this sequence? If so, generate
6011 an andcr or andncr. */
6012 if (! frv_ifcvt.last_nested_if_cr)
6016 frv_ifcvt.last_nested_if_cr = test_reg;
6017 if (GET_CODE (op0) == NE)
6018 and_op = gen_andcr (test_reg, cr, test_reg);
6020 and_op = gen_andncr (test_reg, cr, test_reg);
6022 frv_ifcvt_add_insn (and_op, insn, TRUE);
6025 /* If this isn't the first statement in the nested if sequence, see if we
6026 are dealing with the same register. */
6027 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6030 COND_EXEC_TEST (pattern) = test = op1;
6033 /* If this isn't a nested if, reset state variables. */
6036 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6039 set = single_set_pattern (pattern);
6042 rtx dest = SET_DEST (set);
6043 rtx src = SET_SRC (set);
6044 enum machine_mode mode = GET_MODE (dest);
6046 /* Check for normal binary operators. */
6047 if (mode == SImode && ARITHMETIC_P (src))
6049 op0 = XEXP (src, 0);
6050 op1 = XEXP (src, 1);
6052 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6054 op1 = frv_ifcvt_load_value (op1, insn);
6056 COND_EXEC_CODE (pattern)
6057 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6065 /* For multiply by a constant, we need to handle the sign extending
6066 correctly. Add a USE of the value after the multiply to prevent flow
6067 from cratering because only one register out of the two were used. */
6068 else if (mode == DImode && GET_CODE (src) == MULT)
6070 op0 = XEXP (src, 0);
6071 op1 = XEXP (src, 1);
6072 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6074 op1 = frv_ifcvt_load_value (op1, insn);
6077 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6078 COND_EXEC_CODE (pattern)
6079 = gen_rtx_SET (VOIDmode, dest,
6080 gen_rtx_MULT (DImode, op0, op1));
6086 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6089 /* If we are just loading a constant created for a nested conditional
6090 execution statement, just load the constant without any conditional
6091 execution, since we know that the constant will not interfere with any
6093 else if (frv_ifcvt.scratch_insns_bitmap
6094 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6096 && REG_P (SET_DEST (set))
6097 /* We must not unconditionally set a scratch reg chosen
6098 for a nested if-converted block if its incoming
6099 value from the TEST block (or the result of the THEN
6100 branch) could/should propagate to the JOIN block.
6101 It suffices to test whether the register is live at
6102 the JOIN point: if it's live there, we can infer
6103 that we set it in the former JOIN block of the
6104 nested if-converted block (otherwise it wouldn't
6105 have been available as a scratch register), and it
6106 is either propagated through or set in the other
6107 conditional block. It's probably not worth trying
6108 to catch the latter case, and it could actually
6109 limit scheduling of the combined block quite
6112 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6113 REGNO (SET_DEST (set))))
6114 /* Similarly, we must not unconditionally set a reg
6115 used as scratch in the THEN branch if the same reg
6116 is live in the ELSE branch. */
6117 && (! ce_info->else_bb
6118 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6119 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6120 REGNO (SET_DEST (set))))))
6123 else if (mode == QImode || mode == HImode || mode == SImode
6126 int changed_p = FALSE;
6128 /* Check for just loading up a constant */
6129 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6131 src = frv_ifcvt_load_value (src, insn);
6138 /* See if we need to fix up stores */
6139 if (GET_CODE (dest) == MEM)
6141 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6146 else if (new_mem != dest)
6153 /* See if we need to fix up loads */
6154 if (GET_CODE (src) == MEM)
6156 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6161 else if (new_mem != src)
6168 /* If either src or destination changed, redo SET. */
6170 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6173 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6174 rewriting the CC register to be the same as the paired CC/CR register
6176 else if (mode == CC_CCRmode && COMPARISON_P (src))
6178 int regno = REGNO (XEXP (src, 0));
6181 if (ce_info->pass > 1
6182 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6183 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6185 src = gen_rtx_fmt_ee (GET_CODE (src),
6187 frv_ifcvt.nested_cc_reg,
6191 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6192 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6195 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6196 else if (ce_info->pass > 1
6197 && GET_CODE (dest) == REG
6198 && CC_P (REGNO (dest))
6199 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6200 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6202 && GET_CODE (src) == COMPARE)
6204 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6205 COND_EXEC_CODE (pattern)
6206 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6210 if (TARGET_DEBUG_COND_EXEC)
6212 rtx orig_pattern = PATTERN (insn);
6214 PATTERN (insn) = pattern;
6216 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6220 PATTERN (insn) = orig_pattern;
6226 if (TARGET_DEBUG_COND_EXEC)
6228 rtx orig_pattern = PATTERN (insn);
6230 PATTERN (insn) = orig_ce_pattern;
6232 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6236 PATTERN (insn) = orig_pattern;
6243 /* A C expression to perform any final machine dependent modifications in
6244 converting code to conditional execution in the code described by the
6245 conditional if information CE_INFO. */
6248 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6252 rtx p = frv_ifcvt.added_insns_list;
6255 /* Loop inserting the check insns. The last check insn is the first test,
6256 and is the appropriate place to insert constants. */
6261 rtx check_and_insert_insns = XEXP (p, 0);
6264 check_insn = XEXP (check_and_insert_insns, 0);
6265 existing_insn = XEXP (check_and_insert_insns, 1);
6268 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6269 the existing insn, otherwise it is to be inserted AFTER. */
6270 if (check_and_insert_insns->jump)
6272 emit_insn_before (check_insn, existing_insn);
6273 check_and_insert_insns->jump = 0;
6276 emit_insn_after (check_insn, existing_insn);
6278 free_EXPR_LIST_node (check_and_insert_insns);
6279 free_EXPR_LIST_node (old_p);
6281 while (p != NULL_RTX);
6283 /* Load up any constants needed into temp gprs */
6284 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6286 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6287 if (! frv_ifcvt.scratch_insns_bitmap)
6288 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6289 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6290 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6293 frv_ifcvt.added_insns_list = NULL_RTX;
6294 frv_ifcvt.cur_scratch_regs = 0;
6298 /* A C expression to cancel any machine dependent modifications in converting
6299 code to conditional execution in the code described by the conditional if
6300 information CE_INFO. */
6303 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6306 rtx p = frv_ifcvt.added_insns_list;
6308 /* Loop freeing up the EXPR_LIST's allocated. */
6309 while (p != NULL_RTX)
6311 rtx check_and_jump = XEXP (p, 0);
6315 free_EXPR_LIST_node (check_and_jump);
6316 free_EXPR_LIST_node (old_p);
6319 /* Release any temporary gprs allocated. */
6320 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6321 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6323 frv_ifcvt.added_insns_list = NULL_RTX;
6324 frv_ifcvt.cur_scratch_regs = 0;
6328 /* A C expression for the size in bytes of the trampoline, as an integer.
6332 setlo #0, <static_chain>
6334 sethi #0, <static_chain>
6335 jmpl @(gr0,<jmp_reg>) */
6338 frv_trampoline_size (void)
6341 /* Allocate room for the function descriptor and the lddi
6344 return 5 /* instructions */ * 4 /* instruction size. */;
6348 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6349 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6350 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6351 should be passed to the function when it is called.
6356 setlo #0, <static_chain>
6358 sethi #0, <static_chain>
6359 jmpl @(gr0,<jmp_reg>) */
6362 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6364 rtx addr = XEXP (m_tramp, 0);
6365 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6366 rtx sc_reg = force_reg (Pmode, static_chain);
6368 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6371 GEN_INT (frv_trampoline_size ()), SImode,
6377 /* Many machines have some registers that cannot be copied directly to or from
6378 memory or even from other types of registers. An example is the `MQ'
6379 register, which on most machines, can only be copied to or from general
6380 registers, but not memory. Some machines allow copying all registers to and
6381 from memory, but require a scratch register for stores to some memory
6382 locations (e.g., those with symbolic address on the RT, and those with
6383 certain symbolic address on the SPARC when compiling PIC). In some cases,
6384 both an intermediate and a scratch register are required.
6386 You should define these macros to indicate to the reload phase that it may
6387 need to allocate at least one register for a reload in addition to the
6388 register to contain the data. Specifically, if copying X to a register
6389 RCLASS in MODE requires an intermediate register, you should define
6390 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6391 whose registers can be used as intermediate registers or scratch registers.
6393 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6394 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6395 largest register class required. If the requirements for input and output
6396 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6397 instead of defining both macros identically.
6399 The values returned by these macros are often `GENERAL_REGS'. Return
6400 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6401 to or from a register of RCLASS in MODE without requiring a scratch register.
6402 Do not define this macro if it would always return `NO_REGS'.
6404 If a scratch register is required (either with or without an intermediate
6405 register), you should define patterns for `reload_inM' or `reload_outM', as
6406 required.. These patterns, which will normally be implemented with a
6407 `define_expand', should be similar to the `movM' patterns, except that
6408 operand 2 is the scratch register.
6410 Define constraints for the reload register and scratch register that contain
6411 a single register class. If the original reload register (whose class is
6412 RCLASS) can meet the constraint given in the pattern, the value returned by
6413 these macros is used for the class of the scratch register. Otherwise, two
6414 additional reload registers are required. Their classes are obtained from
6415 the constraints in the insn pattern.
6417 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6418 either be in a hard register or in memory. Use `true_regnum' to find out;
6419 it will return -1 if the pseudo is in memory and the hard register number if
6420 it is in a register.
6422 These macros should not be used in the case where a particular class of
6423 registers can only be copied to memory and not to another class of
6424 registers. In that case, secondary reload registers are not needed and
6425 would not be helpful. Instead, a stack location must be used to perform the
6426 copy and the `movM' pattern should use memory as an intermediate storage.
6427 This case often occurs between floating-point and general registers. */
6430 frv_secondary_reload_class (enum reg_class rclass,
6431 enum machine_mode mode ATTRIBUTE_UNUSED,
6442 /* Accumulators/Accumulator guard registers need to go through floating
6448 if (x && GET_CODE (x) == REG)
6450 int regno = REGNO (x);
6452 if (ACC_P (regno) || ACCG_P (regno))
6457 /* Nonzero constants should be loaded into an FPR through a GPR. */
6461 if (x && CONSTANT_P (x) && !ZERO_P (x))
6467 /* All of these types need gpr registers. */
6479 /* The accumulators need fpr registers. */
6491 /* This hook exists to catch the case where secondary_reload_class() is
6492 called from init_reg_autoinc() in regclass.c - before the reload optabs
6493 have been initialised. */
6496 frv_secondary_reload (bool in_p, rtx x, enum reg_class reload_class,
6497 enum machine_mode reload_mode,
6498 secondary_reload_info * sri)
6500 enum reg_class rclass = NO_REGS;
6502 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6504 sri->icode = sri->prev_sri->t_icode;
6508 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6510 if (rclass != NO_REGS)
6512 enum insn_code icode = (in_p ? reload_in_optab[(int) reload_mode]
6513 : reload_out_optab[(int) reload_mode]);
6516 /* This happens when then the reload_[in|out]_optabs have
6517 not been initialised. */
6518 sri->t_icode = CODE_FOR_nothing;
6523 /* Fall back to the default secondary reload handler. */
6524 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6528 /* A C expression whose value is nonzero if pseudos that have been assigned to
6529 registers of class RCLASS would likely be spilled because registers of RCLASS
6530 are needed for spill registers.
6532 The default value of this macro returns 1 if RCLASS has exactly one register
6533 and zero otherwise. On most machines, this default should be used. Only
6534 define this macro to some other expression if pseudo allocated by
6535 `local-alloc.c' end up in memory because their hard registers were needed
6536 for spill registers. If this macro returns nonzero for those classes, those
6537 pseudos will only be allocated by `global.c', which knows how to reallocate
6538 the pseudo to another register. If there would not be another register
6539 available for reallocation, you should not change the definition of this
6540 macro since the only effect of such a definition would be to slow down
6541 register allocation. */
6544 frv_class_likely_spilled_p (enum reg_class rclass)
6554 case FDPIC_FPTR_REGS:
6576 /* An expression for the alignment of a structure field FIELD if the
6577 alignment computed in the usual way is COMPUTED. GCC uses this
6578 value instead of the value in `BIGGEST_ALIGNMENT' or
6579 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6581 /* The definition type of the bit field data is either char, short, long or
6582 long long. The maximum bit size is the number of bits of its own type.
6584 The bit field data is assigned to a storage unit that has an adequate size
6585 for bit field data retention and is located at the smallest address.
6587 Consecutive bit field data are packed at consecutive bits having the same
6588 storage unit, with regard to the type, beginning with the MSB and continuing
6591 If a field to be assigned lies over a bit field type boundary, its
6592 assignment is completed by aligning it with a boundary suitable for the
6595 When a bit field having a bit length of 0 is declared, it is forcibly
6596 assigned to the next storage unit.
6609 &x 00000000 00000000 00000000 00000000
6612 &x+4 00000000 00000000 00000000 00000000
6615 &x+8 00000000 00000000 00000000 00000000
6618 &x+12 00000000 00000000 00000000 00000000
6624 frv_adjust_field_align (tree field, int computed)
6626 /* Make sure that the bitfield is not wider than the type. */
6627 if (DECL_BIT_FIELD (field)
6628 && !DECL_ARTIFICIAL (field))
6630 tree parent = DECL_CONTEXT (field);
6631 tree prev = NULL_TREE;
6634 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6636 if (TREE_CODE (cur) != FIELD_DECL)
6644 /* If this isn't a :0 field and if the previous element is a bitfield
6645 also, see if the type is different, if so, we will need to align the
6646 bit-field to the next boundary. */
6648 && ! DECL_PACKED (field)
6649 && ! integer_zerop (DECL_SIZE (field))
6650 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6652 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6653 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6654 computed = (prev_align > cur_align) ? prev_align : cur_align;
6662 /* A C expression that is nonzero if it is permissible to store a value of mode
6663 MODE in hard register number REGNO (or in several registers starting with
6664 that one). For a machine where all registers are equivalent, a suitable
6667 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6669 It is not necessary for this macro to check for the numbers of fixed
6670 registers, because the allocation mechanism considers them to be always
6673 On some machines, double-precision values must be kept in even/odd register
6674 pairs. The way to implement that is to define this macro to reject odd
6675 register numbers for such modes.
6677 The minimum requirement for a mode to be OK in a register is that the
6678 `movMODE' instruction pattern support moves between the register and any
6679 other hard register for which the mode is OK; and that moving a value into
6680 the register and back out not alter it.
6682 Since the same instruction used to move `SImode' will work for all narrower
6683 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6684 to distinguish between these modes, provided you define patterns `movhi',
6685 etc., to take advantage of this. This is useful because of the interaction
6686 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6687 all integer modes to be tieable.
6689 Many machines have special registers for floating point arithmetic. Often
6690 people assume that floating point machine modes are allowed only in floating
6691 point registers. This is not true. Any registers that can hold integers
6692 can safely *hold* a floating point machine mode, whether or not floating
6693 arithmetic can be done on it in those registers. Integer move instructions
6694 can be used to move the values.
6696 On some machines, though, the converse is true: fixed-point machine modes
6697 may not go in floating registers. This is true if the floating registers
6698 normalize any value stored in them, because storing a non-floating value
6699 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6700 fixed-point machine modes in floating registers. But if the floating
6701 registers do not automatically normalize, if you can store any bit pattern
6702 in one and retrieve it unchanged without a trap, then any machine mode may
6703 go in a floating register, so you can define this macro to say so.
6705 The primary significance of special floating registers is rather that they
6706 are the registers acceptable in floating point arithmetic instructions.
6707 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6708 writing the proper constraints for those instructions.
6710 On some machines, the floating registers are especially slow to access, so
6711 that it is better to store a value in a stack frame than in such a register
6712 if floating point arithmetic is not being done. As long as the floating
6713 registers are not in class `GENERAL_REGS', they will not be used unless some
6714 pattern's constraint asks for one. */
6717 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6727 return ICC_P (regno) || GPR_P (regno);
6730 return CR_P (regno) || GPR_P (regno);
6733 return FCC_P (regno) || GPR_P (regno);
6739 /* Set BASE to the first register in REGNO's class. Set MASK to the
6740 bits that must be clear in (REGNO - BASE) for the register to be
6742 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6746 /* ACCGs store one byte. Two-byte quantities must start in
6747 even-numbered registers, four-byte ones in registers whose
6748 numbers are divisible by four, and so on. */
6750 mask = GET_MODE_SIZE (mode) - 1;
6754 /* The other registers store one word. */
6755 if (GPR_P (regno) || regno == AP_FIRST)
6758 else if (FPR_P (regno))
6761 else if (ACC_P (regno))
6764 else if (SPR_P (regno))
6765 return mode == SImode;
6767 /* Fill in the table. */
6771 /* Anything smaller than an SI is OK in any word-sized register. */
6772 if (GET_MODE_SIZE (mode) < 4)
6775 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6777 return (((regno - base) & mask) == 0);
6784 /* A C expression for the number of consecutive hard registers, starting at
6785 register number REGNO, required to hold a value of mode MODE.
6787 On a machine where all registers are exactly one word, a suitable definition
6790 #define HARD_REGNO_NREGS(REGNO, MODE) \
6791 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6792 / UNITS_PER_WORD)) */
6794 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6795 that we can build the appropriate instructions to properly reload the
6796 values. Also, make the byte-sized accumulator guards use one guard
6800 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6803 return GET_MODE_SIZE (mode);
6805 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6809 /* A C expression for the maximum number of consecutive registers of
6810 class RCLASS needed to hold a value of mode MODE.
6812 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6813 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6814 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6816 This macro helps control the handling of multiple-word values in
6819 This declaration is required. */
6822 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6824 if (rclass == ACCG_REGS)
6825 /* An N-byte value requires N accumulator guards. */
6826 return GET_MODE_SIZE (mode);
6828 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6832 /* A C expression that is nonzero if X is a legitimate constant for an
6833 immediate operand on the target machine. You can assume that X satisfies
6834 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6835 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6838 frv_legitimate_constant_p (rtx x)
6840 enum machine_mode mode = GET_MODE (x);
6842 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6843 means that the move expanders will be expected to deal with most
6844 kinds of constant, regardless of what we return here.
6846 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6847 a constant can be entered into reg_equiv_constant[]. If we return true,
6848 reload can create new instances of the constant whenever it likes.
6850 The idea is therefore to accept as many constants as possible (to give
6851 reload more freedom) while rejecting constants that can only be created
6852 at certain times. In particular, anything with a symbolic component will
6853 require use of the pseudo FDPIC register, which is only available before
6856 return LEGITIMATE_PIC_OPERAND_P (x);
6858 /* All of the integer constants are ok. */
6859 if (GET_CODE (x) != CONST_DOUBLE)
6862 /* double integer constants are ok. */
6863 if (mode == VOIDmode || mode == DImode)
6866 /* 0 is always ok. */
6867 if (x == CONST0_RTX (mode))
6870 /* If floating point is just emulated, allow any constant, since it will be
6871 constructed in the GPRs. */
6872 if (!TARGET_HAS_FPRS)
6875 if (mode == DFmode && !TARGET_DOUBLE)
6878 /* Otherwise store the constant away and do a load. */
6882 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6883 CC_NZ for comparisons against zero in which a single Z or N flag test
6884 is enough, CC_UNS for other unsigned comparisons, and CC for other
6885 signed comparisons. */
6888 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6890 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6899 return y == const0_rtx ? CC_NZmode : CCmode;
6905 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6912 /* A C expression for the cost of moving data from a register in class FROM to
6913 one in class TO. The classes are expressed using the enumeration values
6914 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6915 interpreted relative to that.
6917 It is not required that the cost always equal 2 when FROM is the same as TO;
6918 on some machines it is expensive to move between registers if they are not
6921 If reload sees an insn consisting of a single `set' between two hard
6922 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6923 value of 2, reload does not check to ensure that the constraints of the insn
6924 are met. Setting a cost of other than 2 will allow reload to verify that
6925 the constraints are met. You should do this if the `movM' pattern's
6926 constraints do not allow such copying. */
6928 #define HIGH_COST 40
6929 #define MEDIUM_COST 3
6933 frv_register_move_cost (enum reg_class from, enum reg_class to)
7017 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7018 use ".picptr" to generate safe relocations for PIC code. We also
7019 need a fixup entry for aligned (non-debugging) code. */
7022 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
7024 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
7026 if (GET_CODE (value) == CONST
7027 || GET_CODE (value) == SYMBOL_REF
7028 || GET_CODE (value) == LABEL_REF)
7030 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
7031 && SYMBOL_REF_FUNCTION_P (value))
7033 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
7034 output_addr_const (asm_out_file, value);
7035 fputs (")\n", asm_out_file);
7038 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7039 && frv_function_symbol_referenced_p (value))
7041 if (aligned_p && !TARGET_FDPIC)
7043 static int label_num = 0;
7047 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7048 p = (* targetm.strip_name_encoding) (buf);
7050 fprintf (asm_out_file, "%s:\n", p);
7051 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7052 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7053 fprintf (asm_out_file, "\t.previous\n");
7055 assemble_integer_with_op ("\t.picptr\t", value);
7060 /* We've set the unaligned SI op to NULL, so we always have to
7061 handle the unaligned case here. */
7062 assemble_integer_with_op ("\t.4byte\t", value);
7066 return default_assemble_integer (value, size, aligned_p);
7069 /* Function to set up the backend function structure. */
7071 static struct machine_function *
7072 frv_init_machine_status (void)
7074 return ggc_alloc_cleared_machine_function ();
7077 /* Implement TARGET_SCHED_ISSUE_RATE. */
7080 frv_issue_rate (void)
7085 switch (frv_cpu_type)
7089 case FRV_CPU_SIMPLE:
7097 case FRV_CPU_GENERIC:
7099 case FRV_CPU_TOMCAT:
7107 /* A for_each_rtx callback. If X refers to an accumulator, return
7108 ACC_GROUP_ODD if the bit 2 of the register number is set and
7109 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7113 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7117 if (ACC_P (REGNO (*x)))
7118 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7119 if (ACCG_P (REGNO (*x)))
7120 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7125 /* Return the value of INSN's acc_group attribute. */
7128 frv_acc_group (rtx insn)
7130 /* This distinction only applies to the FR550 packing constraints. */
7131 if (frv_cpu_type != FRV_CPU_FR550)
7132 return ACC_GROUP_NONE;
7133 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7136 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7137 INSN will try to claim first. Since this value depends only on the
7138 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7141 frv_insn_unit (rtx insn)
7143 enum attr_type type;
7145 type = get_attr_type (insn);
7146 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7148 /* We haven't seen this type of instruction before. */
7152 /* Issue the instruction on its own to see which unit it prefers. */
7153 state = alloca (state_size ());
7154 state_reset (state);
7155 state_transition (state, insn);
7157 /* Find out which unit was taken. */
7158 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7159 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7162 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7164 frv_type_to_unit[type] = unit;
7166 return frv_type_to_unit[type];
7169 /* Return true if INSN issues to a branch unit. */
7172 frv_issues_to_branch_unit_p (rtx insn)
7174 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7177 /* The current state of the packing pass, implemented by frv_pack_insns. */
7179 /* The state of the pipeline DFA. */
7182 /* Which hardware registers are set within the current packet,
7183 and the conditions under which they are set. */
7184 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7186 /* The memory locations that have been modified so far in this
7187 packet. MEM is the memref and COND is the regstate_t condition
7188 under which it is set. */
7194 /* The number of valid entries in MEMS. The value is larger than
7195 ARRAY_SIZE (mems) if there were too many mems to record. */
7196 unsigned int num_mems;
7198 /* The maximum number of instructions that can be packed together. */
7199 unsigned int issue_rate;
7201 /* The instructions in the packet, partitioned into groups. */
7202 struct frv_packet_group {
7203 /* How many instructions in the packet belong to this group. */
7204 unsigned int num_insns;
7206 /* A list of the instructions that belong to this group, in the order
7207 they appear in the rtl stream. */
7208 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7210 /* The contents of INSNS after they have been sorted into the correct
7211 assembly-language order. Element X issues to unit X. The list may
7212 contain extra nops. */
7213 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7215 /* The member of frv_nops[] to use in sorted[]. */
7217 } groups[NUM_GROUPS];
7219 /* The instructions that make up the current packet. */
7220 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7221 unsigned int num_insns;
7224 /* Return the regstate_t flags for the given COND_EXEC condition.
7225 Abort if the condition isn't in the right form. */
7228 frv_cond_flags (rtx cond)
7230 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7231 && GET_CODE (XEXP (cond, 0)) == REG
7232 && CR_P (REGNO (XEXP (cond, 0)))
7233 && XEXP (cond, 1) == const0_rtx);
7234 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7235 | (GET_CODE (cond) == NE
7237 : REGSTATE_IF_FALSE));
7241 /* Return true if something accessed under condition COND2 can
7242 conflict with something written under condition COND1. */
7245 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7247 /* If either reference was unconditional, we have a conflict. */
7248 if ((cond1 & REGSTATE_IF_EITHER) == 0
7249 || (cond2 & REGSTATE_IF_EITHER) == 0)
7252 /* The references might conflict if they were controlled by
7254 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7257 /* They definitely conflict if they are controlled by the
7259 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7266 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7267 the current packet. DATA points to a regstate_t that describes the
7268 condition under which *X might be set or used. */
7271 frv_registers_conflict_p_1 (rtx *x, void *data)
7273 unsigned int regno, i;
7276 cond = *(regstate_t *) data;
7278 if (GET_CODE (*x) == REG)
7279 FOR_EACH_REGNO (regno, *x)
7280 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7281 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7284 if (GET_CODE (*x) == MEM)
7286 /* If we ran out of memory slots, assume a conflict. */
7287 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7290 /* Check for output or true dependencies with earlier MEMs. */
7291 for (i = 0; i < frv_packet.num_mems; i++)
7292 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7294 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7298 if (output_dependence (frv_packet.mems[i].mem, *x))
7303 /* The return values of calls aren't significant: they describe
7304 the effect of the call as a whole, not of the insn itself. */
7305 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7307 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7312 /* Check subexpressions. */
7317 /* Return true if something in X might depend on an instruction
7318 in the current packet. */
7321 frv_registers_conflict_p (rtx x)
7326 if (GET_CODE (x) == COND_EXEC)
7328 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7331 flags |= frv_cond_flags (XEXP (x, 0));
7334 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7338 /* A note_stores callback. DATA points to the regstate_t condition
7339 under which X is modified. Update FRV_PACKET accordingly. */
7342 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7346 if (GET_CODE (x) == REG)
7347 FOR_EACH_REGNO (regno, x)
7348 frv_packet.regstate[regno] |= *(regstate_t *) data;
7350 if (GET_CODE (x) == MEM)
7352 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7354 frv_packet.mems[frv_packet.num_mems].mem = x;
7355 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7357 frv_packet.num_mems++;
7362 /* Update the register state information for an instruction whose
7366 frv_registers_update (rtx x)
7370 flags = REGSTATE_MODIFIED;
7371 if (GET_CODE (x) == COND_EXEC)
7373 flags |= frv_cond_flags (XEXP (x, 0));
7376 note_stores (x, frv_registers_update_1, &flags);
7380 /* Initialize frv_packet for the start of a new packet. */
7383 frv_start_packet (void)
7385 enum frv_insn_group group;
7387 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7388 frv_packet.num_mems = 0;
7389 frv_packet.num_insns = 0;
7390 for (group = 0; group < NUM_GROUPS; group++)
7391 frv_packet.groups[group].num_insns = 0;
7395 /* Likewise for the start of a new basic block. */
7398 frv_start_packet_block (void)
7400 state_reset (frv_packet.dfa_state);
7401 frv_start_packet ();
7405 /* Finish the current packet, if any, and start a new one. Call
7406 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7409 frv_finish_packet (void (*handle_packet) (void))
7411 if (frv_packet.num_insns > 0)
7414 state_transition (frv_packet.dfa_state, 0);
7415 frv_start_packet ();
7420 /* Return true if INSN can be added to the current packet. Update
7421 the DFA state on success. */
7424 frv_pack_insn_p (rtx insn)
7426 /* See if the packet is already as long as it can be. */
7427 if (frv_packet.num_insns == frv_packet.issue_rate)
7430 /* If the scheduler thought that an instruction should start a packet,
7431 it's usually a good idea to believe it. It knows much more about
7432 the latencies than we do.
7434 There are some exceptions though:
7436 - Conditional instructions are scheduled on the assumption that
7437 they will be executed. This is usually a good thing, since it
7438 tends to avoid unnecessary stalls in the conditional code.
7439 But we want to pack conditional instructions as tightly as
7440 possible, in order to optimize the case where they aren't
7443 - The scheduler will always put branches on their own, even
7444 if there's no real dependency.
7446 - There's no point putting a call in its own packet unless
7448 if (frv_packet.num_insns > 0
7449 && GET_CODE (insn) == INSN
7450 && GET_MODE (insn) == TImode
7451 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7454 /* Check for register conflicts. Don't do this for setlo since any
7455 conflict will be with the partnering sethi, with which it can
7457 if (get_attr_type (insn) != TYPE_SETLO)
7458 if (frv_registers_conflict_p (PATTERN (insn)))
7461 return state_transition (frv_packet.dfa_state, insn) < 0;
7465 /* Add instruction INSN to the current packet. */
7468 frv_add_insn_to_packet (rtx insn)
7470 struct frv_packet_group *packet_group;
7472 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7473 packet_group->insns[packet_group->num_insns++] = insn;
7474 frv_packet.insns[frv_packet.num_insns++] = insn;
7476 frv_registers_update (PATTERN (insn));
7480 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7481 packet ends in a branch or call, insert the nop before it, otherwise
7485 frv_insert_nop_in_packet (rtx insn)
7487 struct frv_packet_group *packet_group;
7490 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7491 last = frv_packet.insns[frv_packet.num_insns - 1];
7492 if (GET_CODE (last) != INSN)
7494 insn = emit_insn_before (PATTERN (insn), last);
7495 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7496 frv_packet.insns[frv_packet.num_insns++] = last;
7500 insn = emit_insn_after (PATTERN (insn), last);
7501 frv_packet.insns[frv_packet.num_insns++] = insn;
7503 packet_group->insns[packet_group->num_insns++] = insn;
7507 /* If packing is enabled, divide the instructions into packets and
7508 return true. Call HANDLE_PACKET for each complete packet. */
7511 frv_for_each_packet (void (*handle_packet) (void))
7513 rtx insn, next_insn;
7515 frv_packet.issue_rate = frv_issue_rate ();
7517 /* Early exit if we don't want to pack insns. */
7519 || !flag_schedule_insns_after_reload
7520 || !TARGET_VLIW_BRANCH
7521 || frv_packet.issue_rate == 1)
7524 /* Set up the initial packing state. */
7526 frv_packet.dfa_state = alloca (state_size ());
7528 frv_start_packet_block ();
7529 for (insn = get_insns (); insn != 0; insn = next_insn)
7534 code = GET_CODE (insn);
7535 next_insn = NEXT_INSN (insn);
7537 if (code == CODE_LABEL)
7539 frv_finish_packet (handle_packet);
7540 frv_start_packet_block ();
7544 switch (GET_CODE (PATTERN (insn)))
7553 /* Calls mustn't be packed on a TOMCAT. */
7554 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7555 frv_finish_packet (handle_packet);
7557 /* Since the last instruction in a packet determines the EH
7558 region, any exception-throwing instruction must come at
7559 the end of reordered packet. Insns that issue to a
7560 branch unit are bound to come last; for others it's
7561 too hard to predict. */
7562 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7563 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7564 frv_finish_packet (handle_packet);
7566 /* Finish the current packet if we can't add INSN to it.
7567 Simulate cycles until INSN is ready to issue. */
7568 if (!frv_pack_insn_p (insn))
7570 frv_finish_packet (handle_packet);
7571 while (!frv_pack_insn_p (insn))
7572 state_transition (frv_packet.dfa_state, 0);
7575 /* Add the instruction to the packet. */
7576 frv_add_insn_to_packet (insn);
7578 /* Calls and jumps end a packet, as do insns that throw
7580 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7581 frv_finish_packet (handle_packet);
7585 frv_finish_packet (handle_packet);
7590 /* Subroutine of frv_sort_insn_group. We are trying to sort
7591 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7592 language order. We have already picked a new position for
7593 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7594 These instructions will occupy elements [0, LOWER_SLOT) and
7595 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7596 the DFA state after issuing these instructions.
7598 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7599 of the unused instructions. Return true if one such permutation gives
7600 a valid ordering, leaving the successful permutation in sorted[].
7601 Do not modify sorted[] until a valid permutation is found. */
7604 frv_sort_insn_group_1 (enum frv_insn_group group,
7605 unsigned int lower_slot, unsigned int upper_slot,
7606 unsigned int issued, unsigned int num_insns,
7609 struct frv_packet_group *packet_group;
7615 /* Early success if we've filled all the slots. */
7616 if (lower_slot == upper_slot)
7619 packet_group = &frv_packet.groups[group];
7620 dfa_size = state_size ();
7621 test_state = alloca (dfa_size);
7623 /* Try issuing each unused instruction. */
7624 for (i = num_insns - 1; i + 1 != 0; i--)
7625 if (~issued & (1 << i))
7627 insn = packet_group->sorted[i];
7628 memcpy (test_state, state, dfa_size);
7629 if (state_transition (test_state, insn) < 0
7630 && cpu_unit_reservation_p (test_state,
7631 NTH_UNIT (group, upper_slot - 1))
7632 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7633 issued | (1 << i), num_insns,
7636 packet_group->sorted[upper_slot - 1] = insn;
7644 /* Compare two instructions by their frv_insn_unit. */
7647 frv_compare_insns (const void *first, const void *second)
7649 const rtx *const insn1 = (rtx const *) first,
7650 *const insn2 = (rtx const *) second;
7651 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7654 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7655 and sort it into assembly language order. See frv.md for a description of
7659 frv_sort_insn_group (enum frv_insn_group group)
7661 struct frv_packet_group *packet_group;
7662 unsigned int first, i, nop, max_unit, num_slots;
7663 state_t state, test_state;
7666 packet_group = &frv_packet.groups[group];
7668 /* Assume no nop is needed. */
7669 packet_group->nop = 0;
7671 if (packet_group->num_insns == 0)
7674 /* Copy insns[] to sorted[]. */
7675 memcpy (packet_group->sorted, packet_group->insns,
7676 sizeof (rtx) * packet_group->num_insns);
7678 /* Sort sorted[] by the unit that each insn tries to take first. */
7679 if (packet_group->num_insns > 1)
7680 qsort (packet_group->sorted, packet_group->num_insns,
7681 sizeof (rtx), frv_compare_insns);
7683 /* That's always enough for branch and control insns. */
7684 if (group == GROUP_B || group == GROUP_C)
7687 dfa_size = state_size ();
7688 state = alloca (dfa_size);
7689 test_state = alloca (dfa_size);
7691 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7692 consecutively and such that the DFA takes unit X when sorted[X]
7693 is added. Set STATE to the new DFA state. */
7694 state_reset (test_state);
7695 for (first = 0; first < packet_group->num_insns; first++)
7697 memcpy (state, test_state, dfa_size);
7698 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7699 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7703 /* If all the instructions issued in ascending order, we're done. */
7704 if (first == packet_group->num_insns)
7707 /* Add nops to the end of sorted[] and try each permutation until
7708 we find one that works. */
7709 for (nop = 0; nop < frv_num_nops; nop++)
7711 max_unit = frv_insn_unit (frv_nops[nop]);
7712 if (frv_unit_groups[max_unit] == group)
7714 packet_group->nop = frv_nops[nop];
7715 num_slots = UNIT_NUMBER (max_unit) + 1;
7716 for (i = packet_group->num_insns; i < num_slots; i++)
7717 packet_group->sorted[i] = frv_nops[nop];
7718 if (frv_sort_insn_group_1 (group, first, num_slots,
7719 (1 << first) - 1, num_slots, state))
7726 /* Sort the current packet into assembly-language order. Set packing
7727 flags as appropriate. */
7730 frv_reorder_packet (void)
7732 unsigned int cursor[NUM_GROUPS];
7733 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7734 unsigned int unit, to, from;
7735 enum frv_insn_group group;
7736 struct frv_packet_group *packet_group;
7738 /* First sort each group individually. */
7739 for (group = 0; group < NUM_GROUPS; group++)
7742 frv_sort_insn_group (group);
7745 /* Go through the unit template and try add an instruction from
7746 that unit's group. */
7748 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7750 group = frv_unit_groups[unit];
7751 packet_group = &frv_packet.groups[group];
7752 if (cursor[group] < packet_group->num_insns)
7754 /* frv_reorg should have added nops for us. */
7755 gcc_assert (packet_group->sorted[cursor[group]]
7756 != packet_group->nop);
7757 insns[to++] = packet_group->sorted[cursor[group]++];
7761 gcc_assert (to == frv_packet.num_insns);
7763 /* Clear the last instruction's packing flag, thus marking the end of
7764 a packet. Reorder the other instructions relative to it. */
7765 CLEAR_PACKING_FLAG (insns[to - 1]);
7766 for (from = 0; from < to - 1; from++)
7768 remove_insn (insns[from]);
7769 add_insn_before (insns[from], insns[to - 1], NULL);
7770 SET_PACKING_FLAG (insns[from]);
7775 /* Divide instructions into packets. Reorder the contents of each
7776 packet so that they are in the correct assembly-language order.
7778 Since this pass can change the raw meaning of the rtl stream, it must
7779 only be called at the last minute, just before the instructions are
7783 frv_pack_insns (void)
7785 if (frv_for_each_packet (frv_reorder_packet))
7786 frv_insn_packing_flag = 0;
7788 frv_insn_packing_flag = -1;
7791 /* See whether we need to add nops to group GROUP in order to
7792 make a valid packet. */
7795 frv_fill_unused_units (enum frv_insn_group group)
7797 unsigned int non_nops, nops, i;
7798 struct frv_packet_group *packet_group;
7800 packet_group = &frv_packet.groups[group];
7802 /* Sort the instructions into assembly-language order.
7803 Use nops to fill slots that are otherwise unused. */
7804 frv_sort_insn_group (group);
7806 /* See how many nops are needed before the final useful instruction. */
7808 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7809 while (packet_group->sorted[i++] == packet_group->nop)
7812 /* Insert that many nops into the instruction stream. */
7814 frv_insert_nop_in_packet (packet_group->nop);
7817 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7820 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7822 if (io1->const_address != 0 && io2->const_address != 0)
7823 return io1->const_address == io2->const_address;
7825 if (io1->var_address != 0 && io2->var_address != 0)
7826 return rtx_equal_p (io1->var_address, io2->var_address);
7831 /* Return true if operations IO1 and IO2 are guaranteed to complete
7835 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7837 /* The order of writes is always preserved. */
7838 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7841 /* The order of reads isn't preserved. */
7842 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7845 /* One operation is a write and the other is (or could be) a read.
7846 The order is only guaranteed if the accesses are to the same
7848 return frv_same_doubleword_p (io1, io2);
7851 /* Generalize I/O operation X so that it covers both X and Y. */
7854 frv_io_union (struct frv_io *x, const struct frv_io *y)
7856 if (x->type != y->type)
7857 x->type = FRV_IO_UNKNOWN;
7858 if (!frv_same_doubleword_p (x, y))
7860 x->const_address = 0;
7865 /* Fill IO with information about the load or store associated with
7866 membar instruction INSN. */
7869 frv_extract_membar (struct frv_io *io, rtx insn)
7871 extract_insn (insn);
7872 io->type = INTVAL (recog_data.operand[2]);
7873 io->const_address = INTVAL (recog_data.operand[1]);
7874 io->var_address = XEXP (recog_data.operand[0], 0);
7877 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7878 if X is a register and *DATA depends on X. */
7881 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7883 rtx *other = (rtx *) data;
7885 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7889 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7890 Remove every modified register from the set. */
7893 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7895 HARD_REG_SET *set = (HARD_REG_SET *) data;
7899 FOR_EACH_REGNO (regno, x)
7900 CLEAR_HARD_REG_BIT (*set, regno);
7903 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7904 Add every register in *X to the set. */
7907 frv_io_handle_use_1 (rtx *x, void *data)
7909 HARD_REG_SET *set = (HARD_REG_SET *) data;
7913 FOR_EACH_REGNO (regno, *x)
7914 SET_HARD_REG_BIT (*set, regno);
7919 /* A note_stores callback that applies frv_io_handle_use_1 to an
7920 entire rhs value. */
7923 frv_io_handle_use (rtx *x, void *data)
7925 for_each_rtx (x, frv_io_handle_use_1, data);
7928 /* Go through block BB looking for membars to remove. There are two
7929 cases where intra-block analysis is enough:
7931 - a membar is redundant if it occurs between two consecutive I/O
7932 operations and if those operations are guaranteed to complete
7935 - a membar for a __builtin_read is redundant if the result is
7936 used before the next I/O operation is issued.
7938 If the last membar in the block could not be removed, and there
7939 are guaranteed to be no I/O operations between that membar and
7940 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7943 Describe the block's first I/O operation in *NEXT_IO. Describe
7944 an unknown operation if the block doesn't do any I/O. */
7947 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7950 HARD_REG_SET used_regs;
7951 rtx next_membar, set, insn;
7954 /* NEXT_IO is the next I/O operation to be performed after the current
7955 instruction. It starts off as being an unknown operation. */
7956 memset (next_io, 0, sizeof (*next_io));
7958 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7959 next_is_end_p = true;
7961 /* If the current instruction is a __builtin_read or __builtin_write,
7962 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7963 is null if the membar has already been deleted.
7965 Note that the initialization here should only be needed to
7966 suppress warnings. */
7969 /* USED_REGS is the set of registers that are used before the
7970 next I/O instruction. */
7971 CLEAR_HARD_REG_SET (used_regs);
7973 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7974 if (GET_CODE (insn) == CALL_INSN)
7976 /* We can't predict what a call will do to volatile memory. */
7977 memset (next_io, 0, sizeof (struct frv_io));
7978 next_is_end_p = false;
7979 CLEAR_HARD_REG_SET (used_regs);
7981 else if (INSN_P (insn))
7982 switch (recog_memoized (insn))
7984 case CODE_FOR_optional_membar_qi:
7985 case CODE_FOR_optional_membar_hi:
7986 case CODE_FOR_optional_membar_si:
7987 case CODE_FOR_optional_membar_di:
7991 /* Local information isn't enough to decide whether this
7992 membar is needed. Stash it away for later. */
7993 *last_membar = insn;
7994 frv_extract_membar (next_io, insn);
7995 next_is_end_p = false;
7999 /* Check whether the I/O operation before INSN could be
8000 reordered with one described by NEXT_IO. If it can't,
8001 INSN will not be needed. */
8002 struct frv_io prev_io;
8004 frv_extract_membar (&prev_io, insn);
8005 if (frv_io_fixed_order_p (&prev_io, next_io))
8009 ";; [Local] Removing membar %d since order"
8010 " of accesses is guaranteed\n",
8011 INSN_UID (next_membar));
8013 insn = NEXT_INSN (insn);
8014 delete_insn (next_membar);
8022 /* Invalidate NEXT_IO's address if it depends on something that
8023 is clobbered by INSN. */
8024 if (next_io->var_address)
8025 note_stores (PATTERN (insn), frv_io_check_address,
8026 &next_io->var_address);
8028 /* If the next membar is associated with a __builtin_read,
8029 see if INSN reads from that address. If it does, and if
8030 the destination register is used before the next I/O access,
8031 there is no need for the membar. */
8032 set = PATTERN (insn);
8033 if (next_io->type == FRV_IO_READ
8034 && next_io->var_address != 0
8036 && GET_CODE (set) == SET
8037 && GET_CODE (SET_DEST (set)) == REG
8038 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8042 src = SET_SRC (set);
8043 if (GET_CODE (src) == ZERO_EXTEND)
8044 src = XEXP (src, 0);
8046 if (GET_CODE (src) == MEM
8047 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8051 ";; [Local] Removing membar %d since the target"
8052 " of %d is used before the I/O operation\n",
8053 INSN_UID (next_membar), INSN_UID (insn));
8055 if (next_membar == *last_membar)
8058 delete_insn (next_membar);
8063 /* If INSN has volatile references, forget about any registers
8064 that are used after it. Otherwise forget about uses that
8065 are (or might be) defined by INSN. */
8066 if (volatile_refs_p (PATTERN (insn)))
8067 CLEAR_HARD_REG_SET (used_regs);
8069 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8071 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8076 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8077 FIRST_IO[X] describes the first operation performed by basic block X. */
8080 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8083 struct frv_io this_io, next_io;
8087 /* We need to keep the membar if there is an edge to the exit block. */
8088 FOR_EACH_EDGE (succ, ei, bb->succs)
8089 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8090 if (succ->dest == EXIT_BLOCK_PTR)
8093 /* Work out the union of all successor blocks. */
8094 ei = ei_start (bb->succs);
8095 ei_cond (ei, &succ);
8096 /* next_io = first_io[bb->succ->dest->index]; */
8097 next_io = first_io[succ->dest->index];
8098 ei = ei_start (bb->succs);
8099 if (ei_cond (ei, &succ))
8101 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8102 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8103 frv_io_union (&next_io, &first_io[succ->dest->index]);
8108 frv_extract_membar (&this_io, membar);
8109 if (frv_io_fixed_order_p (&this_io, &next_io))
8113 ";; [Global] Removing membar %d since order of accesses"
8114 " is guaranteed\n", INSN_UID (membar));
8116 delete_insn (membar);
8120 /* Remove redundant membars from the current function. */
8123 frv_optimize_membar (void)
8126 struct frv_io *first_io;
8129 compute_bb_for_insn ();
8130 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8131 last_membar = XCNEWVEC (rtx, last_basic_block);
8134 frv_optimize_membar_local (bb, &first_io[bb->index],
8135 &last_membar[bb->index]);
8138 if (last_membar[bb->index] != 0)
8139 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8145 /* Used by frv_reorg to keep track of the current packet's address. */
8146 static unsigned int frv_packet_address;
8148 /* If the current packet falls through to a label, try to pad the packet
8149 with nops in order to fit the label's alignment requirements. */
8152 frv_align_label (void)
8154 unsigned int alignment, target, nop;
8155 rtx x, last, barrier, label;
8157 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8158 maximum alignment of that packet, LABEL to the last label between
8159 the packets, and BARRIER to the last barrier. */
8160 last = frv_packet.insns[frv_packet.num_insns - 1];
8161 label = barrier = 0;
8163 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8167 unsigned int subalign = 1 << label_to_alignment (x);
8168 alignment = MAX (alignment, subalign);
8175 /* If -malign-labels, and the packet falls through to an unaligned
8176 label, try introducing a nop to align that label to 8 bytes. */
8177 if (TARGET_ALIGN_LABELS
8180 && frv_packet.num_insns < frv_packet.issue_rate)
8181 alignment = MAX (alignment, 8);
8183 /* Advance the address to the end of the current packet. */
8184 frv_packet_address += frv_packet.num_insns * 4;
8186 /* Work out the target address, after alignment. */
8187 target = (frv_packet_address + alignment - 1) & -alignment;
8189 /* If the packet falls through to the label, try to find an efficient
8190 padding sequence. */
8193 /* First try adding nops to the current packet. */
8194 for (nop = 0; nop < frv_num_nops; nop++)
8195 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8197 frv_insert_nop_in_packet (frv_nops[nop]);
8198 frv_packet_address += 4;
8201 /* If we still haven't reached the target, add some new packets that
8202 contain only nops. If there are two types of nop, insert an
8203 alternating sequence of frv_nops[0] and frv_nops[1], which will
8204 lead to packets like:
8211 etc. Just emit frv_nops[0] if that's the only nop we have. */
8212 last = frv_packet.insns[frv_packet.num_insns - 1];
8214 while (frv_packet_address < target)
8216 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8217 frv_packet_address += 4;
8218 if (frv_num_nops > 1)
8223 frv_packet_address = target;
8226 /* Subroutine of frv_reorg, called after each packet has been constructed
8230 frv_reorg_packet (void)
8232 frv_fill_unused_units (GROUP_I);
8233 frv_fill_unused_units (GROUP_FM);
8237 /* Add an instruction with pattern NOP to frv_nops[]. */
8240 frv_register_nop (rtx nop)
8242 nop = make_insn_raw (nop);
8243 NEXT_INSN (nop) = 0;
8244 PREV_INSN (nop) = 0;
8245 frv_nops[frv_num_nops++] = nop;
8248 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8249 into packets and check whether we need to insert nops in order to
8250 fulfill the processor's issue requirements. Also, if the user has
8251 requested a certain alignment for a label, try to meet that alignment
8252 by inserting nops in the previous packet. */
8257 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8258 frv_optimize_membar ();
8261 frv_register_nop (gen_nop ());
8263 frv_register_nop (gen_mnop ());
8264 if (TARGET_HARD_FLOAT)
8265 frv_register_nop (gen_fnop ());
8267 /* Estimate the length of each branch. Although this may change after
8268 we've inserted nops, it will only do so in big functions. */
8269 shorten_branches (get_insns ());
8271 frv_packet_address = 0;
8272 frv_for_each_packet (frv_reorg_packet);
8275 #define def_builtin(name, type, code) \
8276 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8278 struct builtin_description
8280 enum insn_code icode;
8282 enum frv_builtins code;
8283 enum rtx_code comparison;
8287 /* Media intrinsics that take a single, constant argument. */
8289 static struct builtin_description bdesc_set[] =
8291 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8294 /* Media intrinsics that take just one argument. */
8296 static struct builtin_description bdesc_1arg[] =
8298 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8299 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8300 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8301 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8302 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8303 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8306 /* Media intrinsics that take two arguments. */
8308 static struct builtin_description bdesc_2arg[] =
8310 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8311 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8312 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8313 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8314 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8315 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8316 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8317 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8318 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8319 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8320 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8321 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8322 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8323 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8324 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8325 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8326 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8327 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8328 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8329 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8330 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8331 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8332 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8333 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8334 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8335 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8336 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8339 /* Integer intrinsics that take two arguments and have no return value. */
8341 static struct builtin_description bdesc_int_void2arg[] =
8343 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8344 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8345 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8348 static struct builtin_description bdesc_prefetches[] =
8350 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8351 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8354 /* Media intrinsics that take two arguments, the first being an ACC number. */
8356 static struct builtin_description bdesc_cut[] =
8358 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8359 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8360 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8363 /* Two-argument media intrinsics with an immediate second argument. */
8365 static struct builtin_description bdesc_2argimm[] =
8367 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8368 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8369 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8370 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8371 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8372 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8373 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8374 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8375 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8376 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8377 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8378 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8379 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8380 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8381 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8382 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8383 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8386 /* Media intrinsics that take two arguments and return void, the first argument
8387 being a pointer to 4 words in memory. */
8389 static struct builtin_description bdesc_void2arg[] =
8391 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8392 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8395 /* Media intrinsics that take three arguments, the first being a const_int that
8396 denotes an accumulator, and that return void. */
8398 static struct builtin_description bdesc_void3arg[] =
8400 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8401 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8402 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8403 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8404 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8405 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8406 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8407 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8408 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8409 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8410 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8411 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8412 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8413 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8414 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8415 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8416 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8417 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8418 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8419 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8420 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8421 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8422 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8423 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8424 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8427 /* Media intrinsics that take two accumulator numbers as argument and
8430 static struct builtin_description bdesc_voidacc[] =
8432 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8433 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8434 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8435 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8436 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8437 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8440 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8441 a normal move and the ICODE is for the membar. */
8443 static struct builtin_description bdesc_loads[] =
8445 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8446 FRV_BUILTIN_READ8, 0, 0 },
8447 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8448 FRV_BUILTIN_READ16, 0, 0 },
8449 { CODE_FOR_optional_membar_si, "__builtin_read32",
8450 FRV_BUILTIN_READ32, 0, 0 },
8451 { CODE_FOR_optional_membar_di, "__builtin_read64",
8452 FRV_BUILTIN_READ64, 0, 0 }
8455 /* Likewise stores. */
8457 static struct builtin_description bdesc_stores[] =
8459 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8460 FRV_BUILTIN_WRITE8, 0, 0 },
8461 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8462 FRV_BUILTIN_WRITE16, 0, 0 },
8463 { CODE_FOR_optional_membar_si, "__builtin_write32",
8464 FRV_BUILTIN_WRITE32, 0, 0 },
8465 { CODE_FOR_optional_membar_di, "__builtin_write64",
8466 FRV_BUILTIN_WRITE64, 0, 0 },
8469 /* Initialize media builtins. */
8472 frv_init_builtins (void)
8474 tree endlink = void_list_node;
8475 tree accumulator = integer_type_node;
8476 tree integer = integer_type_node;
8477 tree voidt = void_type_node;
8478 tree uhalf = short_unsigned_type_node;
8479 tree sword1 = long_integer_type_node;
8480 tree uword1 = long_unsigned_type_node;
8481 tree sword2 = long_long_integer_type_node;
8482 tree uword2 = long_long_unsigned_type_node;
8483 tree uword4 = build_pointer_type (uword1);
8484 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8485 tree ubyte = unsigned_char_type_node;
8486 tree iacc = integer_type_node;
8488 #define UNARY(RET, T1) \
8489 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8491 #define BINARY(RET, T1, T2) \
8492 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8493 tree_cons (NULL_TREE, T2, endlink)))
8495 #define TRINARY(RET, T1, T2, T3) \
8496 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8497 tree_cons (NULL_TREE, T2, \
8498 tree_cons (NULL_TREE, T3, endlink))))
8500 #define QUAD(RET, T1, T2, T3, T4) \
8501 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8502 tree_cons (NULL_TREE, T2, \
8503 tree_cons (NULL_TREE, T3, \
8504 tree_cons (NULL_TREE, T4, endlink)))))
8506 tree void_ftype_void = build_function_type (voidt, endlink);
8508 tree void_ftype_acc = UNARY (voidt, accumulator);
8509 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8510 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8511 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8512 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8513 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8514 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8515 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8516 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8518 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8519 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8520 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8521 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8522 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8523 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8524 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8525 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8526 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8527 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8528 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8530 tree sw1_ftype_int = UNARY (sword1, integer);
8531 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8532 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8534 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8535 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8536 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8537 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8538 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8539 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8541 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8542 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8543 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8544 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8545 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8546 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8547 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8548 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8549 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8550 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8551 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8552 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8553 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8554 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8555 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8556 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8557 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8559 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8560 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8561 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8562 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8563 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8564 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8565 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8566 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8567 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8568 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8569 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8570 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8571 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8572 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8573 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8574 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8575 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8576 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8577 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8578 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8579 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8580 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8581 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8582 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8583 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8584 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8585 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8586 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8587 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8588 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8589 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8590 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8591 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8592 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8593 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8594 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8595 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8596 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8597 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8598 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8599 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8600 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8601 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8602 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8603 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8604 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8605 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8606 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8607 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8608 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8609 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8610 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8611 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8612 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8613 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8614 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8615 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8616 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8617 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8618 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8619 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8620 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8621 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8622 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8623 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8624 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8625 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8626 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8627 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8628 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8629 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8630 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8631 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8632 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8633 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8634 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8635 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8636 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8637 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8638 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8639 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8640 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8641 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8642 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8643 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8644 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8645 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8646 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8647 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8648 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8649 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8650 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8651 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8652 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8653 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8654 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8655 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8656 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8657 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8658 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8659 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8660 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8661 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8662 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8663 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8664 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8665 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8666 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8668 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8669 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8670 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8671 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8679 /* Set the names for various arithmetic operations according to the
8682 frv_init_libfuncs (void)
8684 set_optab_libfunc (smod_optab, SImode, "__modi");
8685 set_optab_libfunc (umod_optab, SImode, "__umodi");
8687 set_optab_libfunc (add_optab, DImode, "__addll");
8688 set_optab_libfunc (sub_optab, DImode, "__subll");
8689 set_optab_libfunc (smul_optab, DImode, "__mulll");
8690 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8691 set_optab_libfunc (smod_optab, DImode, "__modll");
8692 set_optab_libfunc (umod_optab, DImode, "__umodll");
8693 set_optab_libfunc (and_optab, DImode, "__andll");
8694 set_optab_libfunc (ior_optab, DImode, "__orll");
8695 set_optab_libfunc (xor_optab, DImode, "__xorll");
8696 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8698 set_optab_libfunc (add_optab, SFmode, "__addf");
8699 set_optab_libfunc (sub_optab, SFmode, "__subf");
8700 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8701 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8703 set_optab_libfunc (add_optab, DFmode, "__addd");
8704 set_optab_libfunc (sub_optab, DFmode, "__subd");
8705 set_optab_libfunc (smul_optab, DFmode, "__muld");
8706 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8708 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8709 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8711 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8712 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8713 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8714 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8716 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8717 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8718 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8719 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8721 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8722 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8723 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8724 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8727 /* Convert an integer constant to an accumulator register. ICODE is the
8728 code of the target instruction, OPNUM is the number of the
8729 accumulator operand and OPVAL is the constant integer. Try both
8730 ACC and ACCG registers; only report an error if neither fit the
8734 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8739 /* ACCs and ACCGs are implicit global registers if media intrinsics
8740 are being used. We set up this lazily to avoid creating lots of
8741 unnecessary call_insn rtl in non-media code. */
8742 for (i = 0; i <= ACC_MASK; i++)
8743 if ((i & ACC_MASK) == i)
8744 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8746 if (GET_CODE (opval) != CONST_INT)
8748 error ("accumulator is not a constant integer");
8751 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8753 error ("accumulator number is out of bounds");
8757 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8758 ACC_FIRST + INTVAL (opval));
8759 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8760 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8762 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8764 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8770 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8773 static enum machine_mode
8774 frv_matching_accg_mode (enum machine_mode mode)
8792 /* Given that a __builtin_read or __builtin_write function is accessing
8793 address ADDRESS, return the value that should be used as operand 1
8797 frv_io_address_cookie (rtx address)
8799 return (GET_CODE (address) == CONST_INT
8800 ? GEN_INT (INTVAL (address) / 8 * 8)
8804 /* Return the accumulator guard that should be paired with accumulator
8805 register ACC. The mode of the returned register is in the same
8806 class as ACC, but is four times smaller. */
8809 frv_matching_accg_for_acc (rtx acc)
8811 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8812 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8815 /* Read the requested argument from the call EXP given by INDEX.
8816 Return the value as an rtx. */
8819 frv_read_argument (tree exp, unsigned int index)
8821 return expand_expr (CALL_EXPR_ARG (exp, index),
8822 NULL_RTX, VOIDmode, 0);
8825 /* Like frv_read_argument, but interpret the argument as the number
8826 of an IACC register and return a (reg:MODE ...) rtx for it. */
8829 frv_read_iacc_argument (enum machine_mode mode, tree call,
8835 op = frv_read_argument (call, index);
8836 if (GET_CODE (op) != CONST_INT
8838 || INTVAL (op) > IACC_LAST - IACC_FIRST
8839 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8841 error ("invalid IACC argument");
8845 /* IACCs are implicit global registers. We set up this lazily to
8846 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8848 regno = INTVAL (op) + IACC_FIRST;
8849 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8850 global_regs[regno + i] = 1;
8852 return gen_rtx_REG (mode, regno);
8855 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8856 The instruction should require a constant operand of some sort. The
8857 function prints an error if OPVAL is not valid. */
8860 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8862 if (GET_CODE (opval) != CONST_INT)
8864 error ("%qs expects a constant argument", insn_data[icode].name);
8867 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8869 error ("constant argument out of range for %qs", insn_data[icode].name);
8875 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8876 if it's not null, has the right mode, and satisfies operand 0's
8880 frv_legitimize_target (enum insn_code icode, rtx target)
8882 enum machine_mode mode = insn_data[icode].operand[0].mode;
8885 || GET_MODE (target) != mode
8886 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8887 return gen_reg_rtx (mode);
8892 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8893 check whether ARG satisfies the operand's constraints. If it doesn't,
8894 copy ARG to a temporary register and return that. Otherwise return ARG
8898 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8900 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8902 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8905 return copy_to_mode_reg (mode, arg);
8908 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8911 frv_volatile_memref (enum machine_mode mode, rtx arg)
8915 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8916 MEM_VOLATILE_P (mem) = 1;
8920 /* Expand builtins that take a single, constant argument. At the moment,
8921 only MHDSETS falls into this category. */
8924 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8927 rtx op0 = frv_read_argument (call, 0);
8929 if (! frv_check_constant_argument (icode, 1, op0))
8932 target = frv_legitimize_target (icode, target);
8933 pat = GEN_FCN (icode) (target, op0);
8941 /* Expand builtins that take one operand. */
8944 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8947 rtx op0 = frv_read_argument (call, 0);
8949 target = frv_legitimize_target (icode, target);
8950 op0 = frv_legitimize_argument (icode, 1, op0);
8951 pat = GEN_FCN (icode) (target, op0);
8959 /* Expand builtins that take two operands. */
8962 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8965 rtx op0 = frv_read_argument (call, 0);
8966 rtx op1 = frv_read_argument (call, 1);
8968 target = frv_legitimize_target (icode, target);
8969 op0 = frv_legitimize_argument (icode, 1, op0);
8970 op1 = frv_legitimize_argument (icode, 2, op1);
8971 pat = GEN_FCN (icode) (target, op0, op1);
8979 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8983 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8986 rtx op0 = frv_read_argument (call, 0);
8987 rtx op1 = frv_read_argument (call, 1);
8990 target = frv_legitimize_target (icode, target);
8991 op0 = frv_int_to_acc (icode, 1, op0);
8995 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8997 if (! frv_check_constant_argument (icode, 2, op1))
9001 op1 = frv_legitimize_argument (icode, 2, op1);
9003 op2 = frv_matching_accg_for_acc (op0);
9004 pat = GEN_FCN (icode) (target, op0, op1, op2);
9012 /* Expand builtins that take two operands and the second is immediate. */
9015 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
9018 rtx op0 = frv_read_argument (call, 0);
9019 rtx op1 = frv_read_argument (call, 1);
9021 if (! frv_check_constant_argument (icode, 2, op1))
9024 target = frv_legitimize_target (icode, target);
9025 op0 = frv_legitimize_argument (icode, 1, op0);
9026 pat = GEN_FCN (icode) (target, op0, op1);
9034 /* Expand builtins that take two operands, the first operand being a pointer to
9035 ints and return void. */
9038 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9041 rtx op0 = frv_read_argument (call, 0);
9042 rtx op1 = frv_read_argument (call, 1);
9043 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9046 if (GET_CODE (op0) != MEM)
9050 if (! offsettable_address_p (0, mode0, op0))
9052 reg = gen_reg_rtx (Pmode);
9053 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9056 op0 = gen_rtx_MEM (SImode, reg);
9059 addr = XEXP (op0, 0);
9060 if (! offsettable_address_p (0, mode0, addr))
9061 addr = copy_to_mode_reg (Pmode, op0);
9063 op0 = change_address (op0, V4SImode, addr);
9064 op1 = frv_legitimize_argument (icode, 1, op1);
9065 pat = GEN_FCN (icode) (op0, op1);
9073 /* Expand builtins that take two long operands and return void. */
9076 frv_expand_int_void2arg (enum insn_code icode, tree call)
9079 rtx op0 = frv_read_argument (call, 0);
9080 rtx op1 = frv_read_argument (call, 1);
9082 op0 = frv_legitimize_argument (icode, 1, op0);
9083 op1 = frv_legitimize_argument (icode, 1, op1);
9084 pat = GEN_FCN (icode) (op0, op1);
9092 /* Expand prefetch builtins. These take a single address as argument. */
9095 frv_expand_prefetches (enum insn_code icode, tree call)
9098 rtx op0 = frv_read_argument (call, 0);
9100 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9108 /* Expand builtins that take three operands and return void. The first
9109 argument must be a constant that describes a pair or quad accumulators. A
9110 fourth argument is created that is the accumulator guard register that
9111 corresponds to the accumulator. */
9114 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9117 rtx op0 = frv_read_argument (call, 0);
9118 rtx op1 = frv_read_argument (call, 1);
9119 rtx op2 = frv_read_argument (call, 2);
9122 op0 = frv_int_to_acc (icode, 0, op0);
9126 op1 = frv_legitimize_argument (icode, 1, op1);
9127 op2 = frv_legitimize_argument (icode, 2, op2);
9128 op3 = frv_matching_accg_for_acc (op0);
9129 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9137 /* Expand builtins that perform accumulator-to-accumulator operations.
9138 These builtins take two accumulator numbers as argument and return
9142 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9145 rtx op0 = frv_read_argument (call, 0);
9146 rtx op1 = frv_read_argument (call, 1);
9150 op0 = frv_int_to_acc (icode, 0, op0);
9154 op1 = frv_int_to_acc (icode, 1, op1);
9158 op2 = frv_matching_accg_for_acc (op0);
9159 op3 = frv_matching_accg_for_acc (op1);
9160 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9168 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9169 membar and TARGET_MODE is the mode that the loaded value should have. */
9172 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9173 tree call, rtx target)
9175 rtx op0 = frv_read_argument (call, 0);
9176 rtx cookie = frv_io_address_cookie (op0);
9178 if (target == 0 || !REG_P (target))
9179 target = gen_reg_rtx (target_mode);
9180 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9181 convert_move (target, op0, 1);
9182 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9183 cfun->machine->has_membar_p = 1;
9187 /* Likewise __builtin_write* functions. */
9190 frv_expand_store_builtin (enum insn_code icode, tree call)
9192 rtx op0 = frv_read_argument (call, 0);
9193 rtx op1 = frv_read_argument (call, 1);
9194 rtx cookie = frv_io_address_cookie (op0);
9196 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9197 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9198 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9199 cfun->machine->has_membar_p = 1;
9203 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9204 each argument forms one word of the two double-word input registers.
9205 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9206 to put the return value. */
9209 frv_expand_mdpackh_builtin (tree call, rtx target)
9211 enum insn_code icode = CODE_FOR_mdpackh;
9213 rtx arg1 = frv_read_argument (call, 0);
9214 rtx arg2 = frv_read_argument (call, 1);
9215 rtx arg3 = frv_read_argument (call, 2);
9216 rtx arg4 = frv_read_argument (call, 3);
9218 target = frv_legitimize_target (icode, target);
9219 op0 = gen_reg_rtx (DImode);
9220 op1 = gen_reg_rtx (DImode);
9222 /* The high half of each word is not explicitly initialized, so indicate
9223 that the input operands are not live before this point. */
9227 /* Move each argument into the low half of its associated input word. */
9228 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9229 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9230 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9231 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9233 pat = GEN_FCN (icode) (target, op0, op1);
9241 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9242 number as argument. */
9245 frv_expand_mclracc_builtin (tree call)
9247 enum insn_code icode = CODE_FOR_mclracc;
9249 rtx op0 = frv_read_argument (call, 0);
9251 op0 = frv_int_to_acc (icode, 0, op0);
9255 pat = GEN_FCN (icode) (op0);
9262 /* Expand builtins that take no arguments. */
9265 frv_expand_noargs_builtin (enum insn_code icode)
9267 rtx pat = GEN_FCN (icode) (const0_rtx);
9274 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9275 number or accumulator guard number as argument and return an SI integer. */
9278 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9281 rtx target = gen_reg_rtx (SImode);
9282 rtx op0 = frv_read_argument (call, 0);
9284 op0 = frv_int_to_acc (icode, 1, op0);
9288 pat = GEN_FCN (icode) (target, op0);
9296 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9297 accumulator guard as their first argument and an SImode value as their
9301 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9304 rtx op0 = frv_read_argument (call, 0);
9305 rtx op1 = frv_read_argument (call, 1);
9307 op0 = frv_int_to_acc (icode, 0, op0);
9311 op1 = frv_legitimize_argument (icode, 1, op1);
9312 pat = GEN_FCN (icode) (op0, op1);
9319 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9320 to move DImode values into and out of IACC0. */
9323 frv_split_iacc_move (rtx dest, rtx src)
9325 enum machine_mode inner;
9328 inner = GET_MODE (dest);
9329 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9330 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9331 simplify_gen_subreg (SImode, src, inner, i));
9334 /* Expand builtins. */
9337 frv_expand_builtin (tree exp,
9339 rtx subtarget ATTRIBUTE_UNUSED,
9340 enum machine_mode mode ATTRIBUTE_UNUSED,
9341 int ignore ATTRIBUTE_UNUSED)
9343 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9344 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9346 struct builtin_description *d;
9348 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9350 error ("media functions are not available unless -mmedia is used");
9356 case FRV_BUILTIN_MCOP1:
9357 case FRV_BUILTIN_MCOP2:
9358 case FRV_BUILTIN_MDUNPACKH:
9359 case FRV_BUILTIN_MBTOHE:
9360 if (! TARGET_MEDIA_REV1)
9362 error ("this media function is only available on the fr500");
9367 case FRV_BUILTIN_MQXMACHS:
9368 case FRV_BUILTIN_MQXMACXHS:
9369 case FRV_BUILTIN_MQMACXHS:
9370 case FRV_BUILTIN_MADDACCS:
9371 case FRV_BUILTIN_MSUBACCS:
9372 case FRV_BUILTIN_MASACCS:
9373 case FRV_BUILTIN_MDADDACCS:
9374 case FRV_BUILTIN_MDSUBACCS:
9375 case FRV_BUILTIN_MDASACCS:
9376 case FRV_BUILTIN_MABSHS:
9377 case FRV_BUILTIN_MDROTLI:
9378 case FRV_BUILTIN_MCPLHI:
9379 case FRV_BUILTIN_MCPLI:
9380 case FRV_BUILTIN_MDCUTSSI:
9381 case FRV_BUILTIN_MQSATHS:
9382 case FRV_BUILTIN_MHSETLOS:
9383 case FRV_BUILTIN_MHSETLOH:
9384 case FRV_BUILTIN_MHSETHIS:
9385 case FRV_BUILTIN_MHSETHIH:
9386 case FRV_BUILTIN_MHDSETS:
9387 case FRV_BUILTIN_MHDSETH:
9388 if (! TARGET_MEDIA_REV2)
9390 error ("this media function is only available on the fr400"
9396 case FRV_BUILTIN_SMASS:
9397 case FRV_BUILTIN_SMSSS:
9398 case FRV_BUILTIN_SMU:
9399 case FRV_BUILTIN_ADDSS:
9400 case FRV_BUILTIN_SUBSS:
9401 case FRV_BUILTIN_SLASS:
9402 case FRV_BUILTIN_SCUTSS:
9403 case FRV_BUILTIN_IACCreadll:
9404 case FRV_BUILTIN_IACCreadl:
9405 case FRV_BUILTIN_IACCsetll:
9406 case FRV_BUILTIN_IACCsetl:
9407 if (!TARGET_FR405_BUILTINS)
9409 error ("this builtin function is only available"
9410 " on the fr405 and fr450");
9415 case FRV_BUILTIN_PREFETCH:
9416 if (!TARGET_FR500_FR550_BUILTINS)
9418 error ("this builtin function is only available on the fr500"
9424 case FRV_BUILTIN_MQLCLRHS:
9425 case FRV_BUILTIN_MQLMTHS:
9426 case FRV_BUILTIN_MQSLLHI:
9427 case FRV_BUILTIN_MQSRAHI:
9428 if (!TARGET_MEDIA_FR450)
9430 error ("this builtin function is only available on the fr450");
9439 /* Expand unique builtins. */
9443 case FRV_BUILTIN_MTRAP:
9444 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9446 case FRV_BUILTIN_MCLRACC:
9447 return frv_expand_mclracc_builtin (exp);
9449 case FRV_BUILTIN_MCLRACCA:
9451 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9453 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9455 case FRV_BUILTIN_MRDACC:
9456 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9458 case FRV_BUILTIN_MRDACCG:
9459 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9461 case FRV_BUILTIN_MWTACC:
9462 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9464 case FRV_BUILTIN_MWTACCG:
9465 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9467 case FRV_BUILTIN_MDPACKH:
9468 return frv_expand_mdpackh_builtin (exp, target);
9470 case FRV_BUILTIN_IACCreadll:
9472 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9473 if (target == 0 || !REG_P (target))
9474 target = gen_reg_rtx (DImode);
9475 frv_split_iacc_move (target, src);
9479 case FRV_BUILTIN_IACCreadl:
9480 return frv_read_iacc_argument (SImode, exp, 0);
9482 case FRV_BUILTIN_IACCsetll:
9484 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9485 rtx src = frv_read_argument (exp, 1);
9486 frv_split_iacc_move (dest, force_reg (DImode, src));
9490 case FRV_BUILTIN_IACCsetl:
9492 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9493 rtx src = frv_read_argument (exp, 1);
9494 emit_move_insn (dest, force_reg (SImode, src));
9502 /* Expand groups of builtins. */
9504 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9505 if (d->code == fcode)
9506 return frv_expand_set_builtin (d->icode, exp, target);
9508 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9509 if (d->code == fcode)
9510 return frv_expand_unop_builtin (d->icode, exp, target);
9512 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9513 if (d->code == fcode)
9514 return frv_expand_binop_builtin (d->icode, exp, target);
9516 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9517 if (d->code == fcode)
9518 return frv_expand_cut_builtin (d->icode, exp, target);
9520 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9521 if (d->code == fcode)
9522 return frv_expand_binopimm_builtin (d->icode, exp, target);
9524 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9525 if (d->code == fcode)
9526 return frv_expand_voidbinop_builtin (d->icode, exp);
9528 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9529 if (d->code == fcode)
9530 return frv_expand_voidtriop_builtin (d->icode, exp);
9532 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9533 if (d->code == fcode)
9534 return frv_expand_voidaccop_builtin (d->icode, exp);
9536 for (i = 0, d = bdesc_int_void2arg;
9537 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9538 if (d->code == fcode)
9539 return frv_expand_int_void2arg (d->icode, exp);
9541 for (i = 0, d = bdesc_prefetches;
9542 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9543 if (d->code == fcode)
9544 return frv_expand_prefetches (d->icode, exp);
9546 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9547 if (d->code == fcode)
9548 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9551 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9552 if (d->code == fcode)
9553 return frv_expand_store_builtin (d->icode, exp);
9559 frv_in_small_data_p (const_tree decl)
9562 const_tree section_name;
9564 /* Don't apply the -G flag to internal compiler structures. We
9565 should leave such structures in the main data section, partly
9566 for efficiency and partly because the size of some of them
9567 (such as C++ typeinfos) is not known until later. */
9568 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9571 /* If we already know which section the decl should be in, see if
9572 it's a small data section. */
9573 section_name = DECL_SECTION_NAME (decl);
9576 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9577 if (frv_string_begins_with (section_name, ".sdata"))
9579 if (frv_string_begins_with (section_name, ".sbss"))
9584 size = int_size_in_bytes (TREE_TYPE (decl));
9585 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9592 frv_rtx_costs (rtx x,
9593 int code ATTRIBUTE_UNUSED,
9594 int outer_code ATTRIBUTE_UNUSED,
9596 bool speed ATTRIBUTE_UNUSED)
9598 if (outer_code == MEM)
9600 /* Don't differentiate between memory addresses. All the ones
9601 we accept have equal cost. */
9602 *total = COSTS_N_INSNS (0);
9609 /* Make 12-bit integers really cheap. */
9610 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9621 *total = COSTS_N_INSNS (2);
9635 if (GET_MODE (x) == SImode)
9636 *total = COSTS_N_INSNS (1);
9637 else if (GET_MODE (x) == DImode)
9638 *total = COSTS_N_INSNS (2);
9640 *total = COSTS_N_INSNS (3);
9644 if (GET_MODE (x) == SImode)
9645 *total = COSTS_N_INSNS (2);
9647 *total = COSTS_N_INSNS (6); /* guess */
9654 *total = COSTS_N_INSNS (18);
9658 *total = COSTS_N_INSNS (3);
9667 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9669 switch_to_section (ctors_section);
9670 assemble_align (POINTER_SIZE);
9673 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9678 assemble_integer_with_op ("\t.picptr\t", symbol);
9682 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9684 switch_to_section (dtors_section);
9685 assemble_align (POINTER_SIZE);
9688 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9693 assemble_integer_with_op ("\t.picptr\t", symbol);
9696 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9699 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9700 int incoming ATTRIBUTE_UNUSED)
9702 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9705 #define TLS_BIAS (2048 - 16)
9707 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9708 We need to emit DTP-relative relocations. */
9711 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9713 gcc_assert (size == 4);
9714 fputs ("\t.picptr\ttlsmoff(", file);
9715 /* We want the unbiased TLS offset, so add the bias to the
9716 expression, such that the implicit biasing cancels out. */
9717 output_addr_const (file, plus_constant (x, TLS_BIAS));