1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007,
2 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "basic-block.h"
49 #include "target-def.h"
50 #include "targhooks.h"
51 #include "integrate.h"
52 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Information about one __builtin_read or __builtin_write access, or
113 the combination of several such accesses. The most general value
114 is all-zeros (an unknown access to an unknown address). */
116 /* The type of access. FRV_IO_UNKNOWN means the access can be either
117 a read or a write. */
118 enum { FRV_IO_UNKNOWN, FRV_IO_READ, FRV_IO_WRITE } type;
120 /* The constant address being accessed, or zero if not known. */
121 HOST_WIDE_INT const_address;
123 /* The run-time address, as used in operand 0 of the membar pattern. */
127 /* Return true if instruction INSN should be packed with the following
129 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
131 /* Set the value of PACKING_FLAG_P(INSN). */
132 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
133 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
135 /* Loop with REG set to each hard register in rtx X. */
136 #define FOR_EACH_REGNO(REG, X) \
137 for (REG = REGNO (X); \
138 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
141 /* This structure contains machine specific function data. */
142 struct GTY(()) machine_function
144 /* True if we have created an rtx that relies on the stack frame. */
147 /* True if this function contains at least one __builtin_{read,write}*. */
151 /* Temporary register allocation support structure. */
152 typedef struct frv_tmp_reg_struct
154 HARD_REG_SET regs; /* possible registers to allocate */
155 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
159 /* Register state information for VLIW re-packing phase. */
160 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
161 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
162 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
163 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
165 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
167 typedef unsigned char regstate_t;
169 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
177 /* Information required by frv_frame_access. */
180 /* This field is FRV_LOAD if registers are to be loaded from the stack and
181 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
182 the move is being done by the prologue code while FRV_LOAD implies it
183 is being done by the epilogue. */
184 enum frv_stack_op op;
186 /* The base register to use when accessing the stack. This may be the
187 frame pointer, stack pointer, or a temporary. The choice of register
188 depends on which part of the frame is being accessed and how big the
192 /* The offset of BASE from the bottom of the current frame, in bytes. */
194 } frv_frame_accessor_t;
196 /* Conditional execution support gathered together in one structure. */
199 /* Linked list of insns to add if the conditional execution conversion was
200 successful. Each link points to an EXPR_LIST which points to the pattern
201 of the insn to add, and the insn to be inserted before. */
202 rtx added_insns_list;
204 /* Identify which registers are safe to allocate for if conversions to
205 conditional execution. We keep the last allocated register in the
206 register classes between COND_EXEC statements. This will mean we allocate
207 different registers for each different COND_EXEC group if we can. This
208 might allow the scheduler to intermix two different COND_EXEC sections. */
209 frv_tmp_reg_t tmp_reg;
211 /* For nested IFs, identify which CC registers are used outside of setting
212 via a compare isnsn, and using via a check insn. This will allow us to
213 know if we can rewrite the register to use a different register that will
214 be paired with the CR register controlling the nested IF-THEN blocks. */
215 HARD_REG_SET nested_cc_ok_rewrite;
217 /* Temporary registers allocated to hold constants during conditional
219 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
221 /* Current number of temp registers available. */
222 int cur_scratch_regs;
224 /* Number of nested conditional execution blocks. */
225 int num_nested_cond_exec;
227 /* Map of insns that set up constants in scratch registers. */
228 bitmap scratch_insns_bitmap;
230 /* Conditional execution test register (CC0..CC7). */
233 /* Conditional execution compare register that is paired with cr_reg, so that
234 nested compares can be done. The csubcc and caddcc instructions don't
235 have enough bits to specify both a CC register to be set and a CR register
236 to do the test on, so the same bit number is used for both. Needless to
237 say, this is rather inconvenient for GCC. */
240 /* Extra CR registers used for &&, ||. */
244 /* Previous CR used in nested if, to make sure we are dealing with the same
245 nested if as the previous statement. */
246 rtx last_nested_if_cr;
250 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
252 /* Map register number to smallest register class. */
253 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
255 /* Map class letter into register class. */
256 enum reg_class reg_class_from_letter[256];
258 /* Cached value of frv_stack_info. */
259 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
262 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
264 /* Forward references */
266 static bool frv_handle_option (size_t, const char *, int);
267 static void frv_option_override (void);
268 static bool frv_legitimate_address_p (enum machine_mode, rtx, bool);
269 static int frv_default_flags_for_cpu (void);
270 static int frv_string_begins_with (const_tree, const char *);
271 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
272 static void frv_print_operand (FILE *, rtx, int);
273 static void frv_print_operand_address (FILE *, rtx);
274 static bool frv_print_operand_punct_valid_p (unsigned char code);
275 static void frv_print_operand_memory_reference_reg
277 static void frv_print_operand_memory_reference (FILE *, rtx, int);
278 static int frv_print_operand_jump_hint (rtx);
279 static const char *comparison_string (enum rtx_code, rtx);
280 static rtx frv_function_value (const_tree, const_tree,
282 static rtx frv_libcall_value (enum machine_mode,
284 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
285 static rtx single_set_pattern (rtx);
286 static int frv_function_contains_far_jump (void);
287 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
291 static rtx frv_frame_offset_rtx (int);
292 static rtx frv_frame_mem (enum machine_mode, rtx, int);
293 static rtx frv_dwarf_store (rtx, int);
294 static void frv_frame_insn (rtx, rtx);
295 static void frv_frame_access (frv_frame_accessor_t*,
297 static void frv_frame_access_multi (frv_frame_accessor_t*,
299 static void frv_frame_access_standard_regs (enum frv_stack_op,
301 static struct machine_function *frv_init_machine_status (void);
302 static rtx frv_int_to_acc (enum insn_code, int, rtx);
303 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
304 static rtx frv_read_argument (tree, unsigned int);
305 static rtx frv_read_iacc_argument (enum machine_mode, tree, unsigned int);
306 static int frv_check_constant_argument (enum insn_code, int, rtx);
307 static rtx frv_legitimize_target (enum insn_code, rtx);
308 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
309 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
310 static rtx frv_legitimize_address (rtx, rtx, enum machine_mode);
311 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
312 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
313 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
314 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
315 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
316 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
317 static rtx frv_expand_int_void2arg (enum insn_code, tree);
318 static rtx frv_expand_prefetches (enum insn_code, tree);
319 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
320 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
321 static rtx frv_expand_mclracc_builtin (tree);
322 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
323 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
324 static rtx frv_expand_noargs_builtin (enum insn_code);
325 static void frv_split_iacc_move (rtx, rtx);
326 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
327 static int frv_clear_registers_used (rtx *, void *);
328 static void frv_ifcvt_add_insn (rtx, rtx, int);
329 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
330 static rtx frv_ifcvt_load_value (rtx, rtx);
331 static int frv_acc_group_1 (rtx *, void *);
332 static unsigned int frv_insn_unit (rtx);
333 static bool frv_issues_to_branch_unit_p (rtx);
334 static int frv_cond_flags (rtx);
335 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
336 static int frv_registers_conflict_p_1 (rtx *, void *);
337 static bool frv_registers_conflict_p (rtx);
338 static void frv_registers_update_1 (rtx, const_rtx, void *);
339 static void frv_registers_update (rtx);
340 static void frv_start_packet (void);
341 static void frv_start_packet_block (void);
342 static void frv_finish_packet (void (*) (void));
343 static bool frv_pack_insn_p (rtx);
344 static void frv_add_insn_to_packet (rtx);
345 static void frv_insert_nop_in_packet (rtx);
346 static bool frv_for_each_packet (void (*) (void));
347 static bool frv_sort_insn_group_1 (enum frv_insn_group,
348 unsigned int, unsigned int,
349 unsigned int, unsigned int,
351 static int frv_compare_insns (const void *, const void *);
352 static void frv_sort_insn_group (enum frv_insn_group);
353 static void frv_reorder_packet (void);
354 static void frv_fill_unused_units (enum frv_insn_group);
355 static void frv_align_label (void);
356 static void frv_reorg_packet (void);
357 static void frv_register_nop (rtx);
358 static void frv_reorg (void);
359 static void frv_pack_insns (void);
360 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
361 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
362 static bool frv_assemble_integer (rtx, unsigned, int);
363 static void frv_init_builtins (void);
364 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
365 static void frv_init_libfuncs (void);
366 static bool frv_in_small_data_p (const_tree);
367 static void frv_asm_output_mi_thunk
368 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
369 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
372 static rtx frv_expand_builtin_saveregs (void);
373 static void frv_expand_builtin_va_start (tree, rtx);
374 static bool frv_rtx_costs (rtx, int, int, int*, bool);
375 static int frv_register_move_cost (enum machine_mode,
376 reg_class_t, reg_class_t);
377 static int frv_memory_move_cost (enum machine_mode,
379 static void frv_asm_out_constructor (rtx, int);
380 static void frv_asm_out_destructor (rtx, int);
381 static bool frv_function_symbol_referenced_p (rtx);
382 static bool frv_cannot_force_const_mem (rtx);
383 static const char *unspec_got_name (int);
384 static void frv_output_const_unspec (FILE *,
385 const struct frv_unspec *);
386 static bool frv_function_ok_for_sibcall (tree, tree);
387 static rtx frv_struct_value_rtx (tree, int);
388 static bool frv_must_pass_in_stack (enum machine_mode mode, const_tree type);
389 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
391 static rtx frv_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
393 static rtx frv_function_incoming_arg (CUMULATIVE_ARGS *, enum machine_mode,
395 static void frv_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
397 static void frv_output_dwarf_dtprel (FILE *, int, rtx)
399 static reg_class_t frv_secondary_reload (bool, rtx, reg_class_t,
401 secondary_reload_info *);
402 static bool frv_frame_pointer_required (void);
403 static bool frv_can_eliminate (const int, const int);
404 static void frv_trampoline_init (rtx, tree, rtx);
405 static bool frv_class_likely_spilled_p (reg_class_t);
407 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
408 static const struct default_options frv_option_optimization_table[] =
410 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
411 { OPT_LEVELS_NONE, 0, NULL, 0 }
414 /* Allow us to easily change the default for -malloc-cc. */
415 #ifndef DEFAULT_NO_ALLOC_CC
416 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
418 #define MASK_DEFAULT_ALLOC_CC 0
421 /* Initialize the GCC target structure. */
422 #undef TARGET_PRINT_OPERAND
423 #define TARGET_PRINT_OPERAND frv_print_operand
424 #undef TARGET_PRINT_OPERAND_ADDRESS
425 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
426 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
427 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
428 #undef TARGET_ASM_FUNCTION_PROLOGUE
429 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
430 #undef TARGET_ASM_FUNCTION_EPILOGUE
431 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
432 #undef TARGET_ASM_INTEGER
433 #define TARGET_ASM_INTEGER frv_assemble_integer
434 #undef TARGET_DEFAULT_TARGET_FLAGS
435 #define TARGET_DEFAULT_TARGET_FLAGS \
436 (MASK_DEFAULT_ALLOC_CC \
443 #undef TARGET_HANDLE_OPTION
444 #define TARGET_HANDLE_OPTION frv_handle_option
445 #undef TARGET_OPTION_OVERRIDE
446 #define TARGET_OPTION_OVERRIDE frv_option_override
447 #undef TARGET_OPTION_OPTIMIZATION_TABLE
448 #define TARGET_OPTION_OPTIMIZATION_TABLE frv_option_optimization_table
449 #undef TARGET_INIT_BUILTINS
450 #define TARGET_INIT_BUILTINS frv_init_builtins
451 #undef TARGET_EXPAND_BUILTIN
452 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
453 #undef TARGET_INIT_LIBFUNCS
454 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
455 #undef TARGET_IN_SMALL_DATA_P
456 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
457 #undef TARGET_REGISTER_MOVE_COST
458 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
459 #undef TARGET_MEMORY_MOVE_COST
460 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
461 #undef TARGET_RTX_COSTS
462 #define TARGET_RTX_COSTS frv_rtx_costs
463 #undef TARGET_ASM_CONSTRUCTOR
464 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
465 #undef TARGET_ASM_DESTRUCTOR
466 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
468 #undef TARGET_ASM_OUTPUT_MI_THUNK
469 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
470 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
471 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
473 #undef TARGET_SCHED_ISSUE_RATE
474 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
476 #undef TARGET_LEGITIMIZE_ADDRESS
477 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
479 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
480 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
481 #undef TARGET_CANNOT_FORCE_CONST_MEM
482 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
484 #undef TARGET_HAVE_TLS
485 #define TARGET_HAVE_TLS HAVE_AS_TLS
487 #undef TARGET_STRUCT_VALUE_RTX
488 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
489 #undef TARGET_MUST_PASS_IN_STACK
490 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
491 #undef TARGET_PASS_BY_REFERENCE
492 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
493 #undef TARGET_ARG_PARTIAL_BYTES
494 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
495 #undef TARGET_FUNCTION_ARG
496 #define TARGET_FUNCTION_ARG frv_function_arg
497 #undef TARGET_FUNCTION_INCOMING_ARG
498 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
499 #undef TARGET_FUNCTION_ARG_ADVANCE
500 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
502 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
503 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
504 #undef TARGET_SETUP_INCOMING_VARARGS
505 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
506 #undef TARGET_MACHINE_DEPENDENT_REORG
507 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
509 #undef TARGET_EXPAND_BUILTIN_VA_START
510 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
513 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
514 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
517 #undef TARGET_CLASS_LIKELY_SPILLED_P
518 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
520 #undef TARGET_SECONDARY_RELOAD
521 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
523 #undef TARGET_LEGITIMATE_ADDRESS_P
524 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
526 #undef TARGET_FRAME_POINTER_REQUIRED
527 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
529 #undef TARGET_CAN_ELIMINATE
530 #define TARGET_CAN_ELIMINATE frv_can_eliminate
532 #undef TARGET_TRAMPOLINE_INIT
533 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
535 #undef TARGET_FUNCTION_VALUE
536 #define TARGET_FUNCTION_VALUE frv_function_value
537 #undef TARGET_LIBCALL_VALUE
538 #define TARGET_LIBCALL_VALUE frv_libcall_value
540 struct gcc_target targetm = TARGET_INITIALIZER;
542 #define FRV_SYMBOL_REF_TLS_P(RTX) \
543 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
546 /* Any function call that satisfies the machine-independent
547 requirements is eligible on FR-V. */
550 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
551 tree exp ATTRIBUTE_UNUSED)
556 /* Return true if SYMBOL is a small data symbol and relocation RELOC
557 can be used to access it directly in a load or store. */
559 static FRV_INLINE bool
560 frv_small_data_reloc_p (rtx symbol, int reloc)
562 return (GET_CODE (symbol) == SYMBOL_REF
563 && SYMBOL_REF_SMALL_P (symbol)
564 && (!TARGET_FDPIC || flag_pic == 1)
565 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
568 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
572 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
574 if (GET_CODE (x) == CONST)
578 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
580 unspec->offset += INTVAL (XEXP (x, 1));
583 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
585 unspec->symbol = XVECEXP (x, 0, 0);
586 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
588 if (unspec->offset == 0)
591 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
592 && unspec->offset > 0
593 && unspec->offset < g_switch_value)
600 /* Decide whether we can force certain constants to memory. If we
601 decide we can't, the caller should be able to cope with it in
604 We never allow constants to be forced into memory for TARGET_FDPIC.
605 This is necessary for several reasons:
607 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
608 target-independent code will try to force them into the constant
609 pool, thus leading to infinite recursion.
611 2. We can never introduce new constant pool references during reload.
612 Any such reference would require use of the pseudo FDPIC register.
614 3. We can't represent a constant added to a function pointer (which is
615 not the same as a pointer to a function+constant).
617 4. In many cases, it's more efficient to calculate the constant in-line. */
620 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
625 /* Implement TARGET_HANDLE_OPTION. */
628 frv_handle_option (size_t code, const char *arg, int value)
633 if (strcmp (arg, "simple") == 0)
634 frv_cpu_type = FRV_CPU_SIMPLE;
635 else if (strcmp (arg, "tomcat") == 0)
636 frv_cpu_type = FRV_CPU_TOMCAT;
637 else if (strcmp (arg, "fr550") == 0)
638 frv_cpu_type = FRV_CPU_FR550;
639 else if (strcmp (arg, "fr500") == 0)
640 frv_cpu_type = FRV_CPU_FR500;
641 else if (strcmp (arg, "fr450") == 0)
642 frv_cpu_type = FRV_CPU_FR450;
643 else if (strcmp (arg, "fr405") == 0)
644 frv_cpu_type = FRV_CPU_FR405;
645 else if (strcmp (arg, "fr400") == 0)
646 frv_cpu_type = FRV_CPU_FR400;
647 else if (strcmp (arg, "fr300") == 0)
648 frv_cpu_type = FRV_CPU_FR300;
649 else if (strcmp (arg, "frv") == 0)
650 frv_cpu_type = FRV_CPU_GENERIC;
661 frv_default_flags_for_cpu (void)
663 switch (frv_cpu_type)
665 case FRV_CPU_GENERIC:
666 return MASK_DEFAULT_FRV;
669 return MASK_DEFAULT_FR550;
673 return MASK_DEFAULT_FR500;
676 return MASK_DEFAULT_FR450;
680 return MASK_DEFAULT_FR400;
684 return MASK_DEFAULT_SIMPLE;
691 /* Implement TARGET_OPTION_OVERRIDE. */
694 frv_option_override (void)
699 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
701 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
702 linker about linking pic and non-pic code. */
705 if (!flag_pic) /* -fPIC */
708 if (!global_options_set.x_g_switch_value) /* -G0 */
714 /* A C expression whose value is a register class containing hard
715 register REGNO. In general there is more than one such class;
716 choose a class which is "minimal", meaning that no smaller class
717 also contains the register. */
719 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
721 enum reg_class rclass;
725 int gpr_reg = regno - GPR_FIRST;
727 if (gpr_reg == GR8_REG)
730 else if (gpr_reg == GR9_REG)
733 else if (gpr_reg == GR14_REG)
734 rclass = FDPIC_FPTR_REGS;
736 else if (gpr_reg == FDPIC_REGNO)
739 else if ((gpr_reg & 3) == 0)
742 else if ((gpr_reg & 1) == 0)
749 else if (FPR_P (regno))
751 int fpr_reg = regno - GPR_FIRST;
752 if ((fpr_reg & 3) == 0)
753 rclass = QUAD_FPR_REGS;
755 else if ((fpr_reg & 1) == 0)
762 else if (regno == LR_REGNO)
765 else if (regno == LCR_REGNO)
768 else if (ICC_P (regno))
771 else if (FCC_P (regno))
774 else if (ICR_P (regno))
777 else if (FCR_P (regno))
780 else if (ACC_P (regno))
782 int r = regno - ACC_FIRST;
784 rclass = QUAD_ACC_REGS;
785 else if ((r & 1) == 0)
786 rclass = EVEN_ACC_REGS;
791 else if (ACCG_P (regno))
797 regno_reg_class[regno] = rclass;
800 /* Check for small data option */
801 if (!global_options_set.x_g_switch_value && !TARGET_LIBPIC)
802 g_switch_value = SDATA_DEFAULT_SIZE;
804 /* A C expression which defines the machine-dependent operand
805 constraint letters for register classes. If CHAR is such a
806 letter, the value should be the register class corresponding to
807 it. Otherwise, the value should be `NO_REGS'. The register
808 letter `r', corresponding to class `GENERAL_REGS', will not be
809 passed to this macro; you do not need to handle it.
811 The following letters are unavailable, due to being used as
816 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
817 'Q', 'R', 'S', 'T', 'U'
819 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
821 for (i = 0; i < 256; i++)
822 reg_class_from_letter[i] = NO_REGS;
824 reg_class_from_letter['a'] = ACC_REGS;
825 reg_class_from_letter['b'] = EVEN_ACC_REGS;
826 reg_class_from_letter['c'] = CC_REGS;
827 reg_class_from_letter['d'] = GPR_REGS;
828 reg_class_from_letter['e'] = EVEN_REGS;
829 reg_class_from_letter['f'] = FPR_REGS;
830 reg_class_from_letter['h'] = FEVEN_REGS;
831 reg_class_from_letter['l'] = LR_REG;
832 reg_class_from_letter['q'] = QUAD_REGS;
833 reg_class_from_letter['t'] = ICC_REGS;
834 reg_class_from_letter['u'] = FCC_REGS;
835 reg_class_from_letter['v'] = ICR_REGS;
836 reg_class_from_letter['w'] = FCR_REGS;
837 reg_class_from_letter['x'] = QUAD_FPR_REGS;
838 reg_class_from_letter['y'] = LCR_REG;
839 reg_class_from_letter['z'] = SPR_REGS;
840 reg_class_from_letter['A'] = QUAD_ACC_REGS;
841 reg_class_from_letter['B'] = ACCG_REGS;
842 reg_class_from_letter['C'] = CR_REGS;
843 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
844 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
846 /* There is no single unaligned SI op for PIC code. Sometimes we
847 need to use ".4byte" and sometimes we need to use ".picptr".
848 See frv_assemble_integer for details. */
849 if (flag_pic || TARGET_FDPIC)
850 targetm.asm_out.unaligned_op.si = 0;
852 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
853 target_flags |= MASK_LINKED_FP;
855 if ((target_flags_explicit & MASK_OPTIMIZE_MEMBAR) == 0)
856 target_flags |= MASK_OPTIMIZE_MEMBAR;
858 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
859 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
861 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
862 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
864 init_machine_status = frv_init_machine_status;
868 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
871 frv_string_begins_with (const_tree name, const char *prefix)
873 const int prefix_len = strlen (prefix);
875 /* Remember: NAME's length includes the null terminator. */
876 return (TREE_STRING_LENGTH (name) > prefix_len
877 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
880 /* Zero or more C statements that may conditionally modify two variables
881 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
882 been initialized from the two preceding macros.
884 This is necessary in case the fixed or call-clobbered registers depend on
887 You need not define this macro if it has no work to do.
889 If the usage of an entire class of registers depends on the target flags,
890 you may indicate this to GCC by using this macro to modify `fixed_regs' and
891 `call_used_regs' to 1 for each of the registers in the classes which should
892 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
893 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
895 (However, if this class is not included in `GENERAL_REGS' and all of the
896 insn patterns whose constraints permit this class are controlled by target
897 switches, then GCC will automatically avoid using these registers when the
898 target switches are opposed to them.) */
901 frv_conditional_register_usage (void)
905 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
906 fixed_regs[i] = call_used_regs[i] = 1;
908 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
909 fixed_regs[i] = call_used_regs[i] = 1;
911 /* Reserve the registers used for conditional execution. At present, we need
912 1 ICC and 1 ICR register. */
913 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
914 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
918 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
919 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
920 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
921 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
925 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
926 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
929 /* If -fpic, SDA_BASE_REG is the PIC register. */
930 if (g_switch_value == 0 && !flag_pic)
931 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
934 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
940 * Compute the stack frame layout
943 * +---------------+-----------------------+-----------------------+
944 * |Register |type |caller-save/callee-save|
945 * +---------------+-----------------------+-----------------------+
946 * |GR0 |Zero register | - |
947 * |GR1 |Stack pointer(SP) | - |
948 * |GR2 |Frame pointer(FP) | - |
949 * |GR3 |Hidden parameter | caller save |
950 * |GR4-GR7 | - | caller save |
951 * |GR8-GR13 |Argument register | caller save |
952 * |GR14-GR15 | - | caller save |
953 * |GR16-GR31 | - | callee save |
954 * |GR32-GR47 | - | caller save |
955 * |GR48-GR63 | - | callee save |
956 * |FR0-FR15 | - | caller save |
957 * |FR16-FR31 | - | callee save |
958 * |FR32-FR47 | - | caller save |
959 * |FR48-FR63 | - | callee save |
960 * +---------------+-----------------------+-----------------------+
964 * SP-> |-----------------------------------|
966 * |-----------------------------------|
967 * | Register save area |
968 * |-----------------------------------|
969 * | Local variable save area |
970 * FP-> |-----------------------------------|
972 * |-----------------------------------|
973 * | Hidden parameter save area |
974 * |-----------------------------------|
975 * | Return address(LR) storage area |
976 * |-----------------------------------|
977 * | Padding for alignment |
978 * |-----------------------------------|
979 * | Register argument area |
980 * OLD SP-> |-----------------------------------|
982 * |-----------------------------------|
985 * Argument area/Parameter area:
987 * When a function is called, this area is used for argument transfer. When
988 * the argument is set up by the caller function, this area is referred to as
989 * the argument area. When the argument is referenced by the callee function,
990 * this area is referred to as the parameter area. The area is allocated when
991 * all arguments cannot be placed on the argument register at the time of
994 * Register save area:
996 * This is a register save area that must be guaranteed for the caller
997 * function. This area is not secured when the register save operation is not
1000 * Local variable save area:
1002 * This is the area for local variables and temporary variables.
1006 * This area stores the FP value of the caller function.
1008 * Hidden parameter save area:
1010 * This area stores the start address of the return value storage
1011 * area for a struct/union return function.
1012 * When a struct/union is used as the return value, the caller
1013 * function stores the return value storage area start address in
1014 * register GR3 and passes it to the caller function.
1015 * The callee function interprets the address stored in the GR3
1016 * as the return value storage area start address.
1017 * When register GR3 needs to be saved into memory, the callee
1018 * function saves it in the hidden parameter save area. This
1019 * area is not secured when the save operation is not needed.
1021 * Return address(LR) storage area:
1023 * This area saves the LR. The LR stores the address of a return to the caller
1024 * function for the purpose of function calling.
1026 * Argument register area:
1028 * This area saves the argument register. This area is not secured when the
1029 * save operation is not needed.
1033 * Arguments, the count of which equals the count of argument registers (6
1034 * words), are positioned in registers GR8 to GR13 and delivered to the callee
1035 * function. When a struct/union return function is called, the return value
1036 * area address is stored in register GR3. Arguments not placed in the
1037 * argument registers will be stored in the stack argument area for transfer
1038 * purposes. When an 8-byte type argument is to be delivered using registers,
1039 * it is divided into two and placed in two registers for transfer. When
1040 * argument registers must be saved to memory, the callee function secures an
1041 * argument register save area in the stack. In this case, a continuous
1042 * argument register save area must be established in the parameter area. The
1043 * argument register save area must be allocated as needed to cover the size of
1044 * the argument register to be saved. If the function has a variable count of
1045 * arguments, it saves all argument registers in the argument register save
1048 * Argument Extension Format:
1050 * When an argument is to be stored in the stack, its type is converted to an
1051 * extended type in accordance with the individual argument type. The argument
1052 * is freed by the caller function after the return from the callee function is
1055 * +-----------------------+---------------+------------------------+
1056 * | Argument Type |Extended Type |Stack Storage Size(byte)|
1057 * +-----------------------+---------------+------------------------+
1059 * |signed char |int | 4 |
1060 * |unsigned char |int | 4 |
1061 * |[signed] short int |int | 4 |
1062 * |unsigned short int |int | 4 |
1063 * |[signed] int |No extension | 4 |
1064 * |unsigned int |No extension | 4 |
1065 * |[signed] long int |No extension | 4 |
1066 * |unsigned long int |No extension | 4 |
1067 * |[signed] long long int |No extension | 8 |
1068 * |unsigned long long int |No extension | 8 |
1069 * |float |double | 8 |
1070 * |double |No extension | 8 |
1071 * |long double |No extension | 8 |
1072 * |pointer |No extension | 4 |
1073 * |struct/union |- | 4 (*1) |
1074 * +-----------------------+---------------+------------------------+
1076 * When a struct/union is to be delivered as an argument, the caller copies it
1077 * to the local variable area and delivers the address of that area.
1081 * +-------------------------------+----------------------+
1082 * |Return Value Type |Return Value Interface|
1083 * +-------------------------------+----------------------+
1085 * |[signed|unsigned] char |GR8 |
1086 * |[signed|unsigned] short int |GR8 |
1087 * |[signed|unsigned] int |GR8 |
1088 * |[signed|unsigned] long int |GR8 |
1090 * |[signed|unsigned] long long int|GR8 & GR9 |
1092 * |double |GR8 & GR9 |
1093 * |long double |GR8 & GR9 |
1094 * |struct/union |(*1) |
1095 * +-------------------------------+----------------------+
1097 * When a struct/union is used as the return value, the caller function stores
1098 * the start address of the return value storage area into GR3 and then passes
1099 * it to the callee function. The callee function interprets GR3 as the start
1100 * address of the return value storage area. When this address needs to be
1101 * saved in memory, the callee function secures the hidden parameter save area
1102 * and saves the address in that area.
1106 frv_stack_info (void)
1108 static frv_stack_t info, zero_info;
1109 frv_stack_t *info_ptr = &info;
1110 tree fndecl = current_function_decl;
1118 /* If we've already calculated the values and reload is complete,
1120 if (frv_stack_cache)
1121 return frv_stack_cache;
1123 /* Zero all fields. */
1126 /* Set up the register range information. */
1127 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1128 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1129 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1130 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1132 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1133 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1134 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1135 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1137 info_ptr->regs[STACK_REGS_LR].name = "lr";
1138 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1139 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1140 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1142 info_ptr->regs[STACK_REGS_CC].name = "cc";
1143 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1144 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1145 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1147 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1148 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1149 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1151 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1152 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1153 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1154 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1155 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1157 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1158 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1159 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1160 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1162 info_ptr->regs[STACK_REGS_FP].name = "fp";
1163 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1164 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1165 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1167 /* Determine if this is a stdarg function. If so, allocate space to store
1174 /* Find the last argument, and see if it is __builtin_va_alist. */
1175 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1177 next_arg = DECL_CHAIN (cur_arg);
1178 if (next_arg == (tree)0)
1180 if (DECL_NAME (cur_arg)
1181 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1189 /* Iterate over all of the register ranges. */
1190 for (range = 0; range < STACK_REGS_MAX; range++)
1192 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1193 int first = reg_ptr->first;
1194 int last = reg_ptr->last;
1196 int size_2words = 0;
1199 /* Calculate which registers need to be saved & save area size. */
1203 for (regno = first; regno <= last; regno++)
1205 if ((df_regs_ever_live_p (regno) && !call_used_regs[regno])
1206 || (crtl->calls_eh_return
1207 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1208 || (!TARGET_FDPIC && flag_pic
1209 && crtl->uses_pic_offset_table && regno == PIC_REGNO))
1211 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1212 size_1word += UNITS_PER_WORD;
1217 /* Calculate whether we need to create a frame after everything else
1218 has been processed. */
1223 if (df_regs_ever_live_p (LR_REGNO)
1225 /* This is set for __builtin_return_address, etc. */
1226 || cfun->machine->frame_needed
1227 || (TARGET_LINKED_FP && frame_pointer_needed)
1228 || (!TARGET_FDPIC && flag_pic
1229 && crtl->uses_pic_offset_table))
1231 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1232 size_1word += UNITS_PER_WORD;
1236 case STACK_REGS_STDARG:
1239 /* If this is a stdarg function with a non varardic
1240 argument split between registers and the stack,
1241 adjust the saved registers downward. */
1242 last -= (ADDR_ALIGN (crtl->args.pretend_args_size, UNITS_PER_WORD)
1245 for (regno = first; regno <= last; regno++)
1247 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1248 size_1word += UNITS_PER_WORD;
1251 info_ptr->stdarg_size = size_1word;
1255 case STACK_REGS_STRUCT:
1256 if (cfun->returns_struct)
1258 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1259 size_1word += UNITS_PER_WORD;
1267 /* If this is a field, it only takes one word. */
1268 if (reg_ptr->field_p)
1269 size_1word = UNITS_PER_WORD;
1271 /* Determine which register pairs can be saved together. */
1272 else if (reg_ptr->dword_p && TARGET_DWORD)
1274 for (regno = first; regno < last; regno += 2)
1276 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1278 size_2words += 2 * UNITS_PER_WORD;
1279 size_1word -= 2 * UNITS_PER_WORD;
1280 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1281 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1286 reg_ptr->size_1word = size_1word;
1287 reg_ptr->size_2words = size_2words;
1289 if (! reg_ptr->special_p)
1291 info_ptr->regs_size_1word += size_1word;
1292 info_ptr->regs_size_2words += size_2words;
1297 /* Set up the sizes of each each field in the frame body, making the sizes
1298 of each be divisible by the size of a dword if dword operations might
1299 be used, or the size of a word otherwise. */
1300 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1302 info_ptr->parameter_size = ADDR_ALIGN (crtl->outgoing_args_size, alignment);
1303 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1304 + info_ptr->regs_size_1word,
1306 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1308 info_ptr->pretend_size = crtl->args.pretend_args_size;
1310 /* Work out the size of the frame, excluding the header. Both the frame
1311 body and register parameter area will be dword-aligned. */
1312 info_ptr->total_size
1313 = (ADDR_ALIGN (info_ptr->parameter_size
1314 + info_ptr->regs_size
1315 + info_ptr->vars_size,
1317 + ADDR_ALIGN (info_ptr->pretend_size
1318 + info_ptr->stdarg_size,
1319 2 * UNITS_PER_WORD));
1321 /* See if we need to create a frame at all, if so add header area. */
1322 if (info_ptr->total_size > 0
1323 || frame_pointer_needed
1324 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1325 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1327 offset = info_ptr->parameter_size;
1328 info_ptr->header_size = 4 * UNITS_PER_WORD;
1329 info_ptr->total_size += 4 * UNITS_PER_WORD;
1331 /* Calculate the offsets to save normal register pairs. */
1332 for (range = 0; range < STACK_REGS_MAX; range++)
1334 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1335 if (! reg_ptr->special_p)
1337 int first = reg_ptr->first;
1338 int last = reg_ptr->last;
1341 for (regno = first; regno <= last; regno++)
1342 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1343 && regno != FRAME_POINTER_REGNUM
1344 && (regno < FIRST_ARG_REGNUM
1345 || regno > LAST_ARG_REGNUM))
1347 info_ptr->reg_offset[regno] = offset;
1348 offset += 2 * UNITS_PER_WORD;
1353 /* Calculate the offsets to save normal single registers. */
1354 for (range = 0; range < STACK_REGS_MAX; range++)
1356 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1357 if (! reg_ptr->special_p)
1359 int first = reg_ptr->first;
1360 int last = reg_ptr->last;
1363 for (regno = first; regno <= last; regno++)
1364 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1365 && regno != FRAME_POINTER_REGNUM
1366 && (regno < FIRST_ARG_REGNUM
1367 || regno > LAST_ARG_REGNUM))
1369 info_ptr->reg_offset[regno] = offset;
1370 offset += UNITS_PER_WORD;
1375 /* Calculate the offset to save the local variables at. */
1376 offset = ADDR_ALIGN (offset, alignment);
1377 if (info_ptr->vars_size)
1379 info_ptr->vars_offset = offset;
1380 offset += info_ptr->vars_size;
1383 /* Align header to a dword-boundary. */
1384 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1386 /* Calculate the offsets in the fixed frame. */
1387 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1388 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1389 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1391 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1392 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1393 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1395 if (cfun->returns_struct)
1397 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1398 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1399 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1402 /* Calculate the offsets to store the arguments passed in registers
1403 for stdarg functions. The register pairs are first and the single
1404 register if any is last. The register save area starts on a
1406 if (info_ptr->stdarg_size)
1408 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1409 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1412 /* Skip the header. */
1413 offset += 4 * UNITS_PER_WORD;
1414 for (regno = first; regno <= last; regno++)
1416 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1418 info_ptr->reg_offset[regno] = offset;
1419 offset += 2 * UNITS_PER_WORD;
1421 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1423 info_ptr->reg_offset[regno] = offset;
1424 offset += UNITS_PER_WORD;
1430 if (reload_completed)
1431 frv_stack_cache = info_ptr;
1437 /* Print the information about the frv stack offsets, etc. when debugging. */
1440 frv_debug_stack (frv_stack_t *info)
1445 info = frv_stack_info ();
1447 fprintf (stderr, "\nStack information for function %s:\n",
1448 ((current_function_decl && DECL_NAME (current_function_decl))
1449 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1452 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1453 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1454 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1455 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1456 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1458 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1459 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1460 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1461 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1463 for (range = 0; range < STACK_REGS_MAX; range++)
1465 frv_stack_regs_t *regs = &(info->regs[range]);
1466 if ((regs->size_1word + regs->size_2words) > 0)
1468 int first = regs->first;
1469 int last = regs->last;
1472 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1473 regs->name, regs->size_1word + regs->size_2words,
1474 regs->size_1word, regs->size_2words);
1476 for (regno = first; regno <= last; regno++)
1478 if (info->save_p[regno] == REG_SAVE_1WORD)
1479 fprintf (stderr, " %s (%d)", reg_names[regno],
1480 info->reg_offset[regno]);
1482 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1483 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1484 reg_names[regno+1], info->reg_offset[regno]);
1487 fputc ('\n', stderr);
1497 /* Used during final to control the packing of insns. The value is
1498 1 if the current instruction should be packed with the next one,
1499 0 if it shouldn't or -1 if packing is disabled altogether. */
1501 static int frv_insn_packing_flag;
1503 /* True if the current function contains a far jump. */
1506 frv_function_contains_far_jump (void)
1508 rtx insn = get_insns ();
1510 && !(GET_CODE (insn) == JUMP_INSN
1511 /* Ignore tablejump patterns. */
1512 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1513 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1514 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1515 insn = NEXT_INSN (insn);
1516 return (insn != NULL);
1519 /* For the FRV, this function makes sure that a function with far jumps
1520 will return correctly. It also does the VLIW packing. */
1523 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1525 /* If no frame was created, check whether the function uses a call
1526 instruction to implement a far jump. If so, save the link in gr3 and
1527 replace all returns to LR with returns to GR3. GR3 is used because it
1528 is call-clobbered, because is not available to the register allocator,
1529 and because all functions that take a hidden argument pointer will have
1531 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1535 /* Just to check that the above comment is true. */
1536 gcc_assert (!df_regs_ever_live_p (GPR_FIRST + 3));
1538 /* Generate the instruction that saves the link register. */
1539 fprintf (file, "\tmovsg lr,gr3\n");
1541 /* Replace the LR with GR3 in *return_internal patterns. The insn
1542 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1543 simply emit a different assembly directive because bralr and jmpl
1544 execute in different units. */
1545 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1546 if (GET_CODE (insn) == JUMP_INSN)
1548 rtx pattern = PATTERN (insn);
1549 if (GET_CODE (pattern) == PARALLEL
1550 && XVECLEN (pattern, 0) >= 2
1551 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1552 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1554 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1555 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1556 SET_REGNO (address, GPR_FIRST + 3);
1563 /* Allow the garbage collector to free the nops created by frv_reorg. */
1564 memset (frv_nops, 0, sizeof (frv_nops));
1568 /* Return the next available temporary register in a given class. */
1571 frv_alloc_temp_reg (
1572 frv_tmp_reg_t *info, /* which registers are available */
1573 enum reg_class rclass, /* register class desired */
1574 enum machine_mode mode, /* mode to allocate register with */
1575 int mark_as_used, /* register not available after allocation */
1576 int no_abort) /* return NULL instead of aborting */
1578 int regno = info->next_reg[ (int)rclass ];
1579 int orig_regno = regno;
1580 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)rclass ];
1585 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1586 && TEST_HARD_REG_BIT (info->regs, regno))
1589 if (++regno >= FIRST_PSEUDO_REGISTER)
1591 if (regno == orig_regno)
1593 gcc_assert (no_abort);
1598 nr = HARD_REGNO_NREGS (regno, mode);
1599 info->next_reg[ (int)rclass ] = regno + nr;
1602 for (i = 0; i < nr; i++)
1603 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1605 return gen_rtx_REG (mode, regno);
1609 /* Return an rtx with the value OFFSET, which will either be a register or a
1610 signed 12-bit integer. It can be used as the second operand in an "add"
1611 instruction, or as the index in a load or store.
1613 The function returns a constant rtx if OFFSET is small enough, otherwise
1614 it loads the constant into register OFFSET_REGNO and returns that. */
1616 frv_frame_offset_rtx (int offset)
1618 rtx offset_rtx = GEN_INT (offset);
1619 if (IN_RANGE_P (offset, -2048, 2047))
1623 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1624 if (IN_RANGE_P (offset, -32768, 32767))
1625 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1628 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1629 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1635 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1636 prologue and epilogue uses such expressions to access the stack. */
1638 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1640 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1642 frv_frame_offset_rtx (offset)));
1645 /* Generate a frame-related expression:
1647 (set REG (mem (plus (sp) (const_int OFFSET)))).
1649 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1650 instructions. Marking the expressions as frame-related is superfluous if
1651 the note contains just a single set. But if the note contains a PARALLEL
1652 or SEQUENCE that has several sets, each set must be individually marked
1653 as frame-related. */
1655 frv_dwarf_store (rtx reg, int offset)
1657 rtx set = gen_rtx_SET (VOIDmode,
1658 gen_rtx_MEM (GET_MODE (reg),
1659 plus_constant (stack_pointer_rtx,
1662 RTX_FRAME_RELATED_P (set) = 1;
1666 /* Emit a frame-related instruction whose pattern is PATTERN. The
1667 instruction is the last in a sequence that cumulatively performs the
1668 operation described by DWARF_PATTERN. The instruction is marked as
1669 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1672 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1674 rtx insn = emit_insn (pattern);
1675 RTX_FRAME_RELATED_P (insn) = 1;
1676 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1681 /* Emit instructions that transfer REG to or from the memory location (sp +
1682 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1683 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1684 function to store registers and only the epilogue uses it to load them.
1686 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1687 The generated instruction will use BASE as its base register. BASE may
1688 simply be the stack pointer, but if several accesses are being made to a
1689 region far away from the stack pointer, it may be more efficient to set
1690 up a temporary instead.
1692 Store instructions will be frame-related and will be annotated with the
1693 overall effect of the store. Load instructions will be followed by a
1694 (use) to prevent later optimizations from zapping them.
1696 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1697 as a temporary in such cases. */
1699 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1701 enum machine_mode mode = GET_MODE (reg);
1702 rtx mem = frv_frame_mem (mode,
1704 stack_offset - accessor->base_offset);
1706 if (accessor->op == FRV_LOAD)
1708 if (SPR_P (REGNO (reg)))
1710 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1711 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1712 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1716 /* We cannot use reg+reg addressing for DImode access. */
1718 && GET_CODE (XEXP (mem, 0)) == PLUS
1719 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1720 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1722 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1723 rtx insn = emit_move_insn (temp,
1724 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1725 XEXP (XEXP (mem, 0), 1)));
1726 mem = gen_rtx_MEM (DImode, temp);
1728 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1734 if (SPR_P (REGNO (reg)))
1736 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1737 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1738 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1739 frv_dwarf_store (reg, stack_offset));
1741 else if (mode == DImode)
1743 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1744 with a separate save for each register. */
1745 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1746 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1747 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1748 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1750 /* Also we cannot use reg+reg addressing. */
1751 if (GET_CODE (XEXP (mem, 0)) == PLUS
1752 && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
1753 && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
1755 rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
1756 rtx insn = emit_move_insn (temp,
1757 gen_rtx_PLUS (SImode, XEXP (XEXP (mem, 0), 0),
1758 XEXP (XEXP (mem, 0), 1)));
1759 mem = gen_rtx_MEM (DImode, temp);
1762 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1763 gen_rtx_PARALLEL (VOIDmode,
1764 gen_rtvec (2, set1, set2)));
1767 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1768 frv_dwarf_store (reg, stack_offset));
1772 /* A function that uses frv_frame_access to transfer a group of registers to
1773 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1774 is the stack information generated by frv_stack_info, and REG_SET is the
1775 number of the register set to transfer. */
1777 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1781 frv_stack_regs_t *regs_info;
1784 regs_info = &info->regs[reg_set];
1785 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1786 if (info->save_p[regno])
1787 frv_frame_access (accessor,
1788 info->save_p[regno] == REG_SAVE_2WORDS
1789 ? gen_rtx_REG (DImode, regno)
1790 : gen_rtx_REG (SImode, regno),
1791 info->reg_offset[regno]);
1794 /* Save or restore callee-saved registers that are kept outside the frame
1795 header. The function saves the registers if OP is FRV_STORE and restores
1796 them if OP is FRV_LOAD. INFO is the stack information generated by
1799 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1801 frv_frame_accessor_t accessor;
1804 accessor.base = stack_pointer_rtx;
1805 accessor.base_offset = 0;
1806 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1807 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1808 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1812 /* Called after register allocation to add any instructions needed for the
1813 prologue. Using a prologue insn is favored compared to putting all of the
1814 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1815 it allows the scheduler to intermix instructions with the saves of
1816 the caller saved registers. In some cases, it might be necessary
1817 to emit a barrier instruction as the last insn to prevent such
1820 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1821 so that the debug info generation code can handle them properly. */
1823 frv_expand_prologue (void)
1825 frv_stack_t *info = frv_stack_info ();
1826 rtx sp = stack_pointer_rtx;
1827 rtx fp = frame_pointer_rtx;
1828 frv_frame_accessor_t accessor;
1830 if (TARGET_DEBUG_STACK)
1831 frv_debug_stack (info);
1833 if (info->total_size == 0)
1836 /* We're interested in three areas of the frame here:
1838 A: the register save area
1840 C: the header after B
1842 If the frame pointer isn't used, we'll have to set up A, B and C
1843 using the stack pointer. If the frame pointer is used, we'll access
1847 B: set up using sp or a temporary (see below)
1850 We set up B using the stack pointer if the frame is small enough.
1851 Otherwise, it's more efficient to copy the old stack pointer into a
1852 temporary and use that.
1854 Note that it's important to make sure the prologue and epilogue use the
1855 same registers to access A and C, since doing otherwise will confuse
1856 the aliasing code. */
1858 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1859 isn't used, the same method will serve for C. */
1860 accessor.op = FRV_STORE;
1861 if (frame_pointer_needed && info->total_size > 2048)
1865 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1866 accessor.base_offset = info->total_size;
1867 insn = emit_insn (gen_movsi (accessor.base, sp));
1871 accessor.base = stack_pointer_rtx;
1872 accessor.base_offset = 0;
1875 /* Allocate the stack space. */
1877 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1878 rtx dwarf_offset = GEN_INT (-info->total_size);
1880 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1883 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1886 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1887 and point the new one to that location. */
1888 if (frame_pointer_needed)
1890 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1892 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1893 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1895 rtx asm_src = plus_constant (accessor.base,
1896 fp_offset - accessor.base_offset);
1897 rtx dwarf_src = plus_constant (sp, fp_offset);
1899 /* Store the old frame pointer at (sp + FP_OFFSET). */
1900 frv_frame_access (&accessor, fp, fp_offset);
1902 /* Set up the new frame pointer. */
1903 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1904 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1906 /* Access region C from the frame pointer. */
1908 accessor.base_offset = fp_offset;
1911 /* Set up region C. */
1912 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1913 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1914 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1916 /* Set up region A. */
1917 frv_frame_access_standard_regs (FRV_STORE, info);
1919 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1920 scheduler from moving loads before the stores saving the registers. */
1921 if (info->stdarg_size > 0)
1922 emit_insn (gen_blockage ());
1924 /* Set up pic register/small data register for this function. */
1925 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
1926 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1927 gen_rtx_REG (Pmode, LR_REGNO),
1928 gen_rtx_REG (SImode, OFFSET_REGNO)));
1932 /* Under frv, all of the work is done via frv_expand_epilogue, but
1933 this function provides a convenient place to do cleanup. */
1936 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1937 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1939 frv_stack_cache = (frv_stack_t *)0;
1941 /* Zap last used registers for conditional execution. */
1942 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1944 /* Release the bitmap of created insns. */
1945 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1949 /* Called after register allocation to add any instructions needed for the
1950 epilogue. Using an epilogue insn is favored compared to putting all of the
1951 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1952 it allows the scheduler to intermix instructions with the saves of
1953 the caller saved registers. In some cases, it might be necessary
1954 to emit a barrier instruction as the last insn to prevent such
1958 frv_expand_epilogue (bool emit_return)
1960 frv_stack_t *info = frv_stack_info ();
1961 rtx fp = frame_pointer_rtx;
1962 rtx sp = stack_pointer_rtx;
1966 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1968 /* Restore the stack pointer to its original value if alloca or the like
1970 if (! current_function_sp_is_unchanging)
1971 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1973 /* Restore the callee-saved registers that were used in this function. */
1974 frv_frame_access_standard_regs (FRV_LOAD, info);
1976 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1977 no return instruction should be emitted. */
1978 if (info->save_p[LR_REGNO])
1983 /* Use the same method to access the link register's slot as we did in
1984 the prologue. In other words, use the frame pointer if available,
1985 otherwise use the stack pointer.
1987 LR_OFFSET is the offset of the link register's slot from the start
1988 of the frame and MEM is a memory rtx for it. */
1989 lr_offset = info->reg_offset[LR_REGNO];
1990 if (frame_pointer_needed)
1991 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1993 mem = frv_frame_mem (Pmode, sp, lr_offset);
1995 /* Load the old link register into a GPR. */
1996 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1997 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
2000 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
2002 /* Restore the old frame pointer. Emit a USE afterwards to make sure
2003 the load is preserved. */
2004 if (frame_pointer_needed)
2006 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
2010 /* Deallocate the stack frame. */
2011 if (info->total_size != 0)
2013 rtx offset = frv_frame_offset_rtx (info->total_size);
2014 emit_insn (gen_stack_adjust (sp, sp, offset));
2017 /* If this function uses eh_return, add the final stack adjustment now. */
2018 if (crtl->calls_eh_return)
2019 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
2022 emit_jump_insn (gen_epilogue_return (return_addr));
2025 rtx lr = return_addr;
2027 if (REGNO (return_addr) != LR_REGNO)
2029 lr = gen_rtx_REG (Pmode, LR_REGNO);
2030 emit_move_insn (lr, return_addr);
2038 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
2041 frv_asm_output_mi_thunk (FILE *file,
2042 tree thunk_fndecl ATTRIBUTE_UNUSED,
2043 HOST_WIDE_INT delta,
2044 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2047 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
2048 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
2049 const char *name_jmp = reg_names[JUMP_REGNO];
2050 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
2052 /* Do the add using an addi if possible. */
2053 if (IN_RANGE_P (delta, -2048, 2047))
2054 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
2057 const char *const name_add = reg_names[TEMP_REGNO];
2058 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2059 parallel, delta, name_add);
2060 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
2062 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
2067 const char *name_pic = reg_names[FDPIC_REGNO];
2068 name_jmp = reg_names[FDPIC_FPTR_REGNO];
2072 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
2073 assemble_name (file, name_func);
2074 fprintf (file, "),%s\n", name_jmp);
2076 fprintf (file, "\tsetlo #gotofffuncdesclo(");
2077 assemble_name (file, name_func);
2078 fprintf (file, "),%s\n", name_jmp);
2080 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
2084 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
2085 assemble_name (file, name_func);
2086 fprintf (file, "\t)), %s\n", name_jmp);
2091 fprintf (file, "\tsethi%s #hi(", parallel);
2092 assemble_name (file, name_func);
2093 fprintf (file, "),%s\n", name_jmp);
2095 fprintf (file, "\tsetlo #lo(");
2096 assemble_name (file, name_func);
2097 fprintf (file, "),%s\n", name_jmp);
2101 /* Use JUMP_REGNO as a temporary PIC register. */
2102 const char *name_lr = reg_names[LR_REGNO];
2103 const char *name_gppic = name_jmp;
2104 const char *name_tmp = reg_names[TEMP_REGNO];
2106 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2107 fprintf (file, "\tcall 1f\n");
2108 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2109 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2110 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2111 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2112 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2114 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2115 assemble_name (file, name_func);
2116 fprintf (file, "),%s\n", name_tmp);
2118 fprintf (file, "\tsetlo #gprello(");
2119 assemble_name (file, name_func);
2120 fprintf (file, "),%s\n", name_tmp);
2122 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2125 /* Jump to the function address. */
2126 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2131 /* On frv, create a frame whenever we need to create stack. */
2134 frv_frame_pointer_required (void)
2136 /* If we forgoing the usual linkage requirements, we only need
2137 a frame pointer if the stack pointer might change. */
2138 if (!TARGET_LINKED_FP)
2139 return !current_function_sp_is_unchanging;
2141 if (! current_function_is_leaf)
2144 if (get_frame_size () != 0)
2150 if (!current_function_sp_is_unchanging)
2153 if (!TARGET_FDPIC && flag_pic && crtl->uses_pic_offset_table)
2159 if (cfun->machine->frame_needed)
2166 /* Worker function for TARGET_CAN_ELIMINATE. */
2169 frv_can_eliminate (const int from, const int to)
2171 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
2172 ? ! frame_pointer_needed
2176 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2177 initial difference between the specified pair of registers. This macro must
2178 be defined if `ELIMINABLE_REGS' is defined. */
2180 /* See frv_stack_info for more details on the frv stack frame. */
2183 frv_initial_elimination_offset (int from, int to)
2185 frv_stack_t *info = frv_stack_info ();
2188 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2189 ret = info->total_size - info->pretend_size;
2191 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2192 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2194 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2195 ret = (info->total_size
2196 - info->reg_offset[FRAME_POINTER_REGNUM]
2197 - info->pretend_size);
2202 if (TARGET_DEBUG_STACK)
2203 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2204 reg_names [from], reg_names[to], ret);
2210 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2213 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2214 enum machine_mode mode,
2215 tree type ATTRIBUTE_UNUSED,
2219 if (TARGET_DEBUG_ARG)
2221 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2222 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2226 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2229 frv_expand_builtin_saveregs (void)
2231 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2233 if (TARGET_DEBUG_ARG)
2234 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2237 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2241 /* Expand __builtin_va_start to do the va_start macro. */
2244 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2247 int num = crtl->args.info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2249 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2250 GEN_INT (UNITS_PER_WORD * num));
2252 if (TARGET_DEBUG_ARG)
2254 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2255 crtl->args.info, num);
2257 debug_rtx (nextarg);
2260 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist,
2261 fold_convert (TREE_TYPE (valist),
2262 make_tree (sizetype, nextarg)));
2263 TREE_SIDE_EFFECTS (t) = 1;
2265 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2269 /* Expand a block move operation, and return 1 if successful. Return 0
2270 if we should let the compiler generate normal code.
2272 operands[0] is the destination
2273 operands[1] is the source
2274 operands[2] is the length
2275 operands[3] is the alignment */
2277 /* Maximum number of loads to do before doing the stores */
2278 #ifndef MAX_MOVE_REG
2279 #define MAX_MOVE_REG 4
2282 /* Maximum number of total loads to do. */
2283 #ifndef TOTAL_MOVE_REG
2284 #define TOTAL_MOVE_REG 8
2288 frv_expand_block_move (rtx operands[])
2290 rtx orig_dest = operands[0];
2291 rtx orig_src = operands[1];
2292 rtx bytes_rtx = operands[2];
2293 rtx align_rtx = operands[3];
2294 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2307 rtx stores[MAX_MOVE_REG];
2309 enum machine_mode mode;
2311 /* If this is not a fixed size move, just call memcpy. */
2315 /* This should be a fixed size alignment. */
2316 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2318 align = INTVAL (align_rtx);
2320 /* Anything to move? */
2321 bytes = INTVAL (bytes_rtx);
2325 /* Don't support real large moves. */
2326 if (bytes > TOTAL_MOVE_REG*align)
2329 /* Move the address into scratch registers. */
2330 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2331 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2333 num_reg = offset = 0;
2334 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2336 /* Calculate the correct offset for src/dest. */
2340 dest_addr = dest_reg;
2344 src_addr = plus_constant (src_reg, offset);
2345 dest_addr = plus_constant (dest_reg, offset);
2348 /* Generate the appropriate load and store, saving the stores
2350 if (bytes >= 4 && align >= 4)
2352 else if (bytes >= 2 && align >= 2)
2357 move_bytes = GET_MODE_SIZE (mode);
2358 tmp_reg = gen_reg_rtx (mode);
2359 src_mem = change_address (orig_src, mode, src_addr);
2360 dest_mem = change_address (orig_dest, mode, dest_addr);
2361 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2362 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2364 if (num_reg >= MAX_MOVE_REG)
2366 for (i = 0; i < num_reg; i++)
2367 emit_insn (stores[i]);
2372 for (i = 0; i < num_reg; i++)
2373 emit_insn (stores[i]);
2379 /* Expand a block clear operation, and return 1 if successful. Return 0
2380 if we should let the compiler generate normal code.
2382 operands[0] is the destination
2383 operands[1] is the length
2384 operands[3] is the alignment */
2387 frv_expand_block_clear (rtx operands[])
2389 rtx orig_dest = operands[0];
2390 rtx bytes_rtx = operands[1];
2391 rtx align_rtx = operands[3];
2392 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2401 enum machine_mode mode;
2403 /* If this is not a fixed size move, just call memcpy. */
2407 /* This should be a fixed size alignment. */
2408 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
2410 align = INTVAL (align_rtx);
2412 /* Anything to move? */
2413 bytes = INTVAL (bytes_rtx);
2417 /* Don't support real large clears. */
2418 if (bytes > TOTAL_MOVE_REG*align)
2421 /* Move the address into a scratch register. */
2422 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2424 num_reg = offset = 0;
2425 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2427 /* Calculate the correct offset for src/dest. */
2428 dest_addr = ((offset == 0)
2430 : plus_constant (dest_reg, offset));
2432 /* Generate the appropriate store of gr0. */
2433 if (bytes >= 4 && align >= 4)
2435 else if (bytes >= 2 && align >= 2)
2440 clear_bytes = GET_MODE_SIZE (mode);
2441 dest_mem = change_address (orig_dest, mode, dest_addr);
2442 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2449 /* The following variable is used to output modifiers of assembler
2450 code of the current output insn. */
2452 static rtx *frv_insn_operands;
2454 /* The following function is used to add assembler insn code suffix .p
2455 if it is necessary. */
2458 frv_asm_output_opcode (FILE *f, const char *ptr)
2462 if (frv_insn_packing_flag <= 0)
2465 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2468 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2469 || (*ptr >= 'A' && *ptr <= 'Z')))
2471 int letter = *ptr++;
2474 frv_print_operand (f, frv_insn_operands [c], letter);
2475 while ((c = *ptr) >= '0' && c <= '9')
2487 /* Set up the packing bit for the current output insn. Note that this
2488 function is not called for asm insns. */
2491 frv_final_prescan_insn (rtx insn, rtx *opvec,
2492 int noperands ATTRIBUTE_UNUSED)
2496 if (frv_insn_packing_flag >= 0)
2498 frv_insn_operands = opvec;
2499 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2501 else if (recog_memoized (insn) >= 0
2502 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2503 /* Packing optimizations have been disabled, but INSN can only
2504 be issued in M1. Insert an mnop in M0. */
2505 fprintf (asm_out_file, "\tmnop.p\n");
2511 /* A C expression whose value is RTL representing the address in a stack frame
2512 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2513 an RTL expression for the address of the stack frame itself.
2515 If you don't define this macro, the default is to return the value of
2516 FRAMEADDR--that is, the stack frame address is also the address of the stack
2517 word that points to the previous frame. */
2519 /* The default is correct, but we need to make sure the frame gets created. */
2521 frv_dynamic_chain_address (rtx frame)
2523 cfun->machine->frame_needed = 1;
2528 /* A C expression whose value is RTL representing the value of the return
2529 address for the frame COUNT steps up from the current frame, after the
2530 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2531 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2534 The value of the expression must always be the correct address when COUNT is
2535 zero, but may be `NULL_RTX' if there is not way to determine the return
2536 address of other frames. */
2539 frv_return_addr_rtx (int count, rtx frame)
2543 cfun->machine->frame_needed = 1;
2544 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2547 /* Given a memory reference MEMREF, interpret the referenced memory as
2548 an array of MODE values, and return a reference to the element
2549 specified by INDEX. Assume that any pre-modification implicit in
2550 MEMREF has already happened.
2552 MEMREF must be a legitimate operand for modes larger than SImode.
2553 frv_legitimate_address_p forbids register+register addresses, which
2554 this function cannot handle. */
2556 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2558 rtx base = XEXP (memref, 0);
2559 if (GET_CODE (base) == PRE_MODIFY)
2560 base = XEXP (base, 0);
2561 return change_address (memref, mode,
2562 plus_constant (base, index * GET_MODE_SIZE (mode)));
2566 /* Print a memory address as an operand to reference that memory location. */
2568 frv_print_operand_address (FILE * stream, rtx x)
2570 if (GET_CODE (x) == MEM)
2573 switch (GET_CODE (x))
2576 fputs (reg_names [ REGNO (x)], stream);
2580 fprintf (stream, "%ld", (long) INTVAL (x));
2584 assemble_name (stream, XSTR (x, 0));
2589 output_addr_const (stream, x);
2593 /* Poorly constructed asm statements can trigger this alternative.
2594 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2595 frv_print_operand_memory_reference (stream, x, 0);
2602 fatal_insn ("bad insn to frv_print_operand_address:", x);
2607 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2609 int regno = true_regnum (x);
2611 fputs (reg_names[regno], stream);
2613 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x);
2616 /* Print a memory reference suitable for the ld/st instructions. */
2619 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2621 struct frv_unspec unspec;
2625 switch (GET_CODE (x))
2632 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2634 x1 = XEXP (XEXP (x, 1), 1);
2644 if (GET_CODE (x0) == CONST_INT)
2652 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2661 else if (GET_CODE (x1) != CONST_INT)
2662 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2665 fputs ("@(", stream);
2667 fputs (reg_names[GPR_R0], stream);
2668 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2669 frv_print_operand_memory_reference_reg (stream, x0);
2671 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2673 fputs (",", stream);
2675 fputs (reg_names [GPR_R0], stream);
2679 switch (GET_CODE (x1))
2683 frv_print_operand_memory_reference_reg (stream, x1);
2687 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2691 if (!frv_const_unspec_p (x1, &unspec))
2692 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1);
2693 frv_output_const_unspec (stream, &unspec);
2697 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
2701 fputs (")", stream);
2705 /* Return 2 for likely branches and 0 for non-likely branches */
2707 #define FRV_JUMP_LIKELY 2
2708 #define FRV_JUMP_NOT_LIKELY 0
2711 frv_print_operand_jump_hint (rtx insn)
2716 HOST_WIDE_INT prob = -1;
2717 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2719 gcc_assert (GET_CODE (insn) == JUMP_INSN);
2721 /* Assume any non-conditional jump is likely. */
2722 if (! any_condjump_p (insn))
2723 ret = FRV_JUMP_LIKELY;
2727 labelref = condjump_label (insn);
2730 rtx label = XEXP (labelref, 0);
2731 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2736 note = find_reg_note (insn, REG_BR_PROB, 0);
2738 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2742 prob = INTVAL (XEXP (note, 0));
2743 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2745 : FRV_JUMP_NOT_LIKELY);
2757 case UNKNOWN: direction = "unknown jump direction"; break;
2758 case BACKWARD: direction = "jump backward"; break;
2759 case FORWARD: direction = "jump forward"; break;
2763 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2764 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2765 (long)INSN_UID (insn), direction, (long)prob,
2766 (long)REG_BR_PROB_BASE, ret);
2774 /* Return the comparison operator to use for CODE given that the ICC
2778 comparison_string (enum rtx_code code, rtx op0)
2780 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2783 default: output_operand_lossage ("bad condition code");
2784 case EQ: return "eq";
2785 case NE: return "ne";
2786 case LT: return is_nz_p ? "n" : "lt";
2787 case LE: return "le";
2788 case GT: return "gt";
2789 case GE: return is_nz_p ? "p" : "ge";
2790 case LTU: return is_nz_p ? "no" : "c";
2791 case LEU: return is_nz_p ? "eq" : "ls";
2792 case GTU: return is_nz_p ? "ne" : "hi";
2793 case GEU: return is_nz_p ? "ra" : "nc";
2797 /* Print an operand to an assembler instruction.
2799 `%' followed by a letter and a digit says to output an operand in an
2800 alternate fashion. Four letters have standard, built-in meanings
2801 described below. The hook `TARGET_PRINT_OPERAND' can define
2802 additional letters with nonstandard meanings.
2804 `%cDIGIT' can be used to substitute an operand that is a constant value
2805 without the syntax that normally indicates an immediate operand.
2807 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2810 `%aDIGIT' can be used to substitute an operand as if it were a memory
2811 reference, with the actual operand treated as the address. This may be
2812 useful when outputting a "load address" instruction, because often the
2813 assembler syntax for such an instruction requires you to write the operand
2814 as if it were a memory reference.
2816 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2818 `%=' outputs a number which is unique to each instruction in the entire
2819 compilation. This is useful for making local labels to be referred to more
2820 than once in a single template that generates multiple assembler
2823 `%' followed by a punctuation character specifies a substitution that
2824 does not use an operand. Only one case is standard: `%%' outputs a
2825 `%' into the assembler code. Other nonstandard cases can be defined
2826 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2827 punctuation characters are valid with the
2828 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2831 frv_print_operand (FILE * file, rtx x, int code)
2833 struct frv_unspec unspec;
2834 HOST_WIDE_INT value;
2837 if (code != 0 && !ISALPHA (code))
2840 else if (GET_CODE (x) == CONST_INT)
2843 else if (GET_CODE (x) == CONST_DOUBLE)
2845 if (GET_MODE (x) == SFmode)
2850 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2851 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2855 else if (GET_MODE (x) == VOIDmode)
2856 value = CONST_DOUBLE_LOW (x);
2859 fatal_insn ("bad insn in frv_print_operand, bad const_double", x);
2870 fputs (reg_names[GPR_R0], file);
2874 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2878 /* Output small data area base register (gr16). */
2879 fputs (reg_names[SDA_BASE_REG], file);
2883 /* Output pic register (gr17). */
2884 fputs (reg_names[PIC_REGNO], file);
2888 /* Output the temporary integer CCR register. */
2889 fputs (reg_names[ICR_TEMP], file);
2893 /* Output the temporary integer CC register. */
2894 fputs (reg_names[ICC_TEMP], file);
2897 /* case 'a': print an address. */
2900 /* Print appropriate test for integer branch false operation. */
2901 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2902 XEXP (x, 0)), file);
2906 /* Print appropriate test for integer branch true operation. */
2907 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2911 /* Print 1 for a NE and 0 for an EQ to give the final argument
2912 for a conditional instruction. */
2913 if (GET_CODE (x) == NE)
2916 else if (GET_CODE (x) == EQ)
2920 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x);
2924 /* Print appropriate test for floating point branch false operation. */
2925 switch (GET_CODE (x))
2928 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x);
2930 case EQ: fputs ("ne", file); break;
2931 case NE: fputs ("eq", file); break;
2932 case LT: fputs ("uge", file); break;
2933 case LE: fputs ("ug", file); break;
2934 case GT: fputs ("ule", file); break;
2935 case GE: fputs ("ul", file); break;
2940 /* Print appropriate test for floating point branch true operation. */
2941 switch (GET_CODE (x))
2944 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x);
2946 case EQ: fputs ("eq", file); break;
2947 case NE: fputs ("ne", file); break;
2948 case LT: fputs ("lt", file); break;
2949 case LE: fputs ("le", file); break;
2950 case GT: fputs ("gt", file); break;
2951 case GE: fputs ("ge", file); break;
2956 /* Print appropriate GOT function. */
2957 if (GET_CODE (x) != CONST_INT)
2958 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
2959 fputs (unspec_got_name (INTVAL (x)), file);
2963 /* Print 'i' if the operand is a constant, or is a memory reference that
2965 if (GET_CODE (x) == MEM)
2966 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2967 ? XEXP (XEXP (x, 0), 1)
2969 else if (GET_CODE (x) == PLUS)
2972 switch (GET_CODE (x))
2986 /* For jump instructions, print 'i' if the operand is a constant or
2987 is an expression that adds a constant. */
2988 if (GET_CODE (x) == CONST_INT)
2993 if (GET_CODE (x) == CONST_INT
2994 || (GET_CODE (x) == PLUS
2995 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2996 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
3002 /* Print the lower register of a double word register pair */
3003 if (GET_CODE (x) == REG)
3004 fputs (reg_names[ REGNO (x)+1 ], file);
3006 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
3009 /* case 'l': print a LABEL_REF. */
3013 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
3014 for the second word of double memory operations. */
3015 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
3016 switch (GET_CODE (x))
3019 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x);
3022 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
3030 frv_print_operand_memory_reference (file, x, offset);
3036 /* Print the opcode of a command. */
3037 switch (GET_CODE (x))
3040 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x);
3042 case PLUS: fputs ("add", file); break;
3043 case MINUS: fputs ("sub", file); break;
3044 case AND: fputs ("and", file); break;
3045 case IOR: fputs ("or", file); break;
3046 case XOR: fputs ("xor", file); break;
3047 case ASHIFT: fputs ("sll", file); break;
3048 case ASHIFTRT: fputs ("sra", file); break;
3049 case LSHIFTRT: fputs ("srl", file); break;
3053 /* case 'n': negate and print a constant int. */
3056 /* Print PIC label using operand as the number. */
3057 if (GET_CODE (x) != CONST_INT)
3058 fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
3060 fprintf (file, ".LCF%ld", (long)INTVAL (x));
3064 /* Print 'u' if the operand is a update load/store. */
3065 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
3070 /* If value is 0, print gr0, otherwise it must be a register. */
3071 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
3072 fputs (reg_names[GPR_R0], file);
3074 else if (GET_CODE (x) == REG)
3075 fputs (reg_names [REGNO (x)], file);
3078 fatal_insn ("bad insn in frv_print_operand, z case", x);
3082 /* Print constant in hex. */
3083 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
3085 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
3092 if (GET_CODE (x) == REG)
3093 fputs (reg_names [REGNO (x)], file);
3095 else if (GET_CODE (x) == CONST_INT
3096 || GET_CODE (x) == CONST_DOUBLE)
3097 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3099 else if (frv_const_unspec_p (x, &unspec))
3100 frv_output_const_unspec (file, &unspec);
3102 else if (GET_CODE (x) == MEM)
3103 frv_print_operand_address (file, XEXP (x, 0));
3105 else if (CONSTANT_ADDRESS_P (x))
3106 frv_print_operand_address (file, x);
3109 fatal_insn ("bad insn in frv_print_operand, 0 case", x);
3114 fatal_insn ("frv_print_operand: unknown code", x);
3122 frv_print_operand_punct_valid_p (unsigned char code)
3124 return (code == '.' || code == '#' || code == '@' || code == '~'
3125 || code == '*' || code == '&');
3129 /* A C statement (sans semicolon) for initializing the variable CUM for the
3130 state at the beginning of the argument list. The variable has type
3131 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3132 of the function which will receive the args, or 0 if the args are to a
3133 compiler support library function. The value of INDIRECT is nonzero when
3134 processing an indirect call, for example a call through a function pointer.
3135 The value of INDIRECT is zero for a call to an explicitly named function, a
3136 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3137 arguments for the function being compiled.
3139 When processing a call to a compiler support library function, LIBNAME
3140 identifies which one. It is a `symbol_ref' rtx which contains the name of
3141 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3142 being processed. Thus, each time this macro is called, either LIBNAME or
3143 FNTYPE is nonzero, but never both of them at once. */
3146 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3152 *cum = FIRST_ARG_REGNUM;
3154 if (TARGET_DEBUG_ARG)
3156 fprintf (stderr, "\ninit_cumulative_args:");
3157 if (!fndecl && fntype)
3158 fputs (" indirect", stderr);
3161 fputs (" incoming", stderr);
3165 tree ret_type = TREE_TYPE (fntype);
3166 fprintf (stderr, " return=%s,",
3167 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3170 if (libname && GET_CODE (libname) == SYMBOL_REF)
3171 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3173 if (cfun->returns_struct)
3174 fprintf (stderr, " return-struct");
3176 putc ('\n', stderr);
3181 /* Return true if we should pass an argument on the stack rather than
3185 frv_must_pass_in_stack (enum machine_mode mode, const_tree type)
3187 if (mode == BLKmode)
3191 return AGGREGATE_TYPE_P (type);
3194 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3195 argument with the specified mode and type. If it is not defined,
3196 `PARM_BOUNDARY' is used for all arguments. */
3199 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3200 tree type ATTRIBUTE_UNUSED)
3202 return BITS_PER_WORD;
3206 frv_function_arg_1 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3207 const_tree type ATTRIBUTE_UNUSED, bool named,
3208 bool incoming ATTRIBUTE_UNUSED)
3210 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3215 /* Return a marker for use in the call instruction. */
3216 if (xmode == VOIDmode)
3222 else if (arg_num <= LAST_ARG_REGNUM)
3224 ret = gen_rtx_REG (xmode, arg_num);
3225 debstr = reg_names[arg_num];
3234 if (TARGET_DEBUG_ARG)
3236 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3237 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3243 frv_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3244 const_tree type, bool named)
3246 return frv_function_arg_1 (cum, mode, type, named, false);
3250 frv_function_incoming_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3251 const_tree type, bool named)
3253 return frv_function_arg_1 (cum, mode, type, named, true);
3257 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3258 advance past an argument in the argument list. The values MODE, TYPE and
3259 NAMED describe that argument. Once this is done, the variable CUM is
3260 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3262 This macro need not do anything if the argument in question was passed on
3263 the stack. The compiler knows how to track the amount of stack space used
3264 for arguments without any special help. */
3267 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3268 enum machine_mode mode,
3269 const_tree type ATTRIBUTE_UNUSED,
3272 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3273 int bytes = GET_MODE_SIZE (xmode);
3274 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3277 *cum = arg_num + words;
3279 if (TARGET_DEBUG_ARG)
3281 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3282 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3286 /* A C expression for the number of words, at the beginning of an argument,
3287 must be put in registers. The value must be zero for arguments that are
3288 passed entirely in registers or that are entirely pushed on the stack.
3290 On some machines, certain arguments must be passed partially in registers
3291 and partially in memory. On these machines, typically the first N words of
3292 arguments are passed in registers, and the rest on the stack. If a
3293 multi-word argument (a `double' or a structure) crosses that boundary, its
3294 first few words must be passed in registers and the rest must be pushed.
3295 This macro tells the compiler when this occurs, and how many of the words
3296 should go in registers.
3298 `FUNCTION_ARG' for these arguments should return the first register to be
3299 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3300 the called function. */
3303 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3304 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3306 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3307 int bytes = GET_MODE_SIZE (xmode);
3308 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3312 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3313 ? LAST_ARG_REGNUM - arg_num + 1
3315 ret *= UNITS_PER_WORD;
3317 if (TARGET_DEBUG_ARG && ret)
3318 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3324 /* Implements TARGET_FUNCTION_VALUE. */
3327 frv_function_value (const_tree valtype,
3328 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
3329 bool outgoing ATTRIBUTE_UNUSED)
3331 return gen_rtx_REG (TYPE_MODE (valtype), RETURN_VALUE_REGNUM);
3335 /* Implements TARGET_LIBCALL_VALUE. */
3338 frv_libcall_value (enum machine_mode mode,
3339 const_rtx fun ATTRIBUTE_UNUSED)
3341 return gen_rtx_REG (mode, RETURN_VALUE_REGNUM);
3345 /* Implements FUNCTION_VALUE_REGNO_P. */
3348 frv_function_value_regno_p (const unsigned int regno)
3350 return (regno == RETURN_VALUE_REGNUM);
3353 /* Return true if a register is ok to use as a base or index register. */
3355 static FRV_INLINE int
3356 frv_regno_ok_for_base_p (int regno, int strict_p)
3362 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3364 if (regno == ARG_POINTER_REGNUM)
3367 return (regno >= FIRST_PSEUDO_REGISTER);
3371 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3372 RTX) is a legitimate memory address on the target machine for a memory
3373 operand of mode MODE.
3375 It usually pays to define several simpler macros to serve as subroutines for
3376 this one. Otherwise it may be too complicated to understand.
3378 This macro must exist in two variants: a strict variant and a non-strict
3379 one. The strict variant is used in the reload pass. It must be defined so
3380 that any pseudo-register that has not been allocated a hard register is
3381 considered a memory reference. In contexts where some kind of register is
3382 required, a pseudo-register with no hard register must be rejected.
3384 The non-strict variant is used in other passes. It must be defined to
3385 accept all pseudo-registers in every context where some kind of register is
3388 Compiler source files that want to use the strict variant of this macro
3389 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3390 conditional to define the strict variant in that case and the non-strict
3393 Normally, constant addresses which are the sum of a `symbol_ref' and an
3394 integer are stored inside a `const' RTX to mark them as constant.
3395 Therefore, there is no need to recognize such sums specifically as
3396 legitimate addresses. Normally you would simply recognize any `const' as
3399 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3400 constant sums that are not marked with `const'. It assumes that a
3401 naked `plus' indicates indexing. If so, then you *must* reject such
3402 naked constant sums as illegitimate addresses, so that none of them
3403 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3406 frv_legitimate_address_p_1 (enum machine_mode mode,
3410 int allow_double_reg_p)
3414 HOST_WIDE_INT value;
3417 if (FRV_SYMBOL_REF_TLS_P (x))
3420 switch (GET_CODE (x))
3427 if (GET_CODE (x) != REG)
3433 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3439 if (GET_CODE (x0) != REG
3440 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3441 || GET_CODE (x1) != PLUS
3442 || ! rtx_equal_p (x0, XEXP (x1, 0))
3443 || GET_CODE (XEXP (x1, 1)) != REG
3444 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3451 /* 12-bit immediate */
3456 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3458 /* If we can't use load/store double operations, make sure we can
3459 address the second word. */
3460 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3461 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3470 if (GET_CODE (x0) == SUBREG)
3471 x0 = SUBREG_REG (x0);
3473 if (GET_CODE (x0) != REG)
3476 regno0 = REGNO (x0);
3477 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3480 switch (GET_CODE (x1))
3486 x1 = SUBREG_REG (x1);
3487 if (GET_CODE (x1) != REG)
3493 /* Do not allow reg+reg addressing for modes > 1 word if we
3494 can't depend on having move double instructions. */
3495 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3498 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3502 /* 12-bit immediate */
3507 value = INTVAL (x1);
3508 ret = IN_RANGE_P (value, -2048, 2047);
3510 /* If we can't use load/store double operations, make sure we can
3511 address the second word. */
3512 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3513 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3518 if (!condexec_p && got12_operand (x1, VOIDmode))
3526 if (TARGET_DEBUG_ADDR)
3528 fprintf (stderr, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3529 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3530 (condexec_p) ? ", inside conditional code" : "");
3538 frv_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
3540 return frv_legitimate_address_p_1 (mode, x, strict_p, FALSE, FALSE);
3543 /* Given an ADDR, generate code to inline the PLT. */
3545 gen_inlined_tls_plt (rtx addr)
3548 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3551 dest = gen_reg_rtx (DImode);
3558 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3559 calll #gettlsoff(ADDR)@(gr8, gr0)
3561 emit_insn (gen_tls_lddi (dest, addr, picreg));
3568 sethi.p #gottlsdeschi(ADDR), gr8
3569 setlo #gottlsdesclo(ADDR), gr8
3570 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3571 calll #gettlsoff(ADDR)@(gr8, gr0)
3573 rtx reguse = gen_reg_rtx (Pmode);
3574 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3575 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3578 retval = gen_reg_rtx (Pmode);
3579 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3583 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3584 the destination address. */
3586 gen_tlsmoff (rtx addr, rtx reg)
3588 rtx dest = gen_reg_rtx (Pmode);
3592 /* sethi.p #tlsmoffhi(x), grA
3593 setlo #tlsmofflo(x), grA
3595 dest = gen_reg_rtx (Pmode);
3596 emit_insn (gen_tlsoff_hilo (dest, addr,
3597 GEN_INT (R_FRV_TLSMOFFHI)));
3598 dest = gen_rtx_PLUS (Pmode, dest, reg);
3602 /* addi grB, #tlsmoff12(x), grC
3604 ld/st @(grB, #tlsmoff12(x)), grC
3606 dest = gen_reg_rtx (Pmode);
3607 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3608 GEN_INT (R_FRV_TLSMOFF12)));
3613 /* Generate code for a TLS address. */
3615 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3617 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3618 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3622 case TLS_MODEL_INITIAL_EXEC:
3626 ldi @(gr15, #gottlsoff12(x)), gr5
3628 dest = gen_reg_rtx (Pmode);
3629 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3630 dest = gen_rtx_PLUS (Pmode, tp, dest);
3634 /* -fPIC or anything else.
3636 sethi.p #gottlsoffhi(x), gr14
3637 setlo #gottlsofflo(x), gr14
3638 ld #tlsoff(x)@(gr15, gr14), gr9
3640 rtx tmp = gen_reg_rtx (Pmode);
3641 dest = gen_reg_rtx (Pmode);
3642 emit_insn (gen_tlsoff_hilo (tmp, addr,
3643 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3645 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3646 dest = gen_rtx_PLUS (Pmode, tp, dest);
3649 case TLS_MODEL_LOCAL_DYNAMIC:
3653 if (TARGET_INLINE_PLT)
3654 retval = gen_inlined_tls_plt (GEN_INT (0));
3657 /* call #gettlsoff(0) */
3658 retval = gen_reg_rtx (Pmode);
3659 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3662 reg = gen_reg_rtx (Pmode);
3663 emit_insn (gen_rtx_SET (VOIDmode, reg,
3664 gen_rtx_PLUS (Pmode,
3667 dest = gen_tlsmoff (addr, reg);
3670 dest = gen_reg_rtx (Pmode);
3671 emit_insn (gen_tlsoff_hilo (dest, addr,
3672 GEN_INT (R_FRV_TLSMOFFHI)));
3673 dest = gen_rtx_PLUS (Pmode, dest, reg);
3677 case TLS_MODEL_LOCAL_EXEC:
3678 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3680 case TLS_MODEL_GLOBAL_DYNAMIC:
3684 if (TARGET_INLINE_PLT)
3685 retval = gen_inlined_tls_plt (addr);
3688 /* call #gettlsoff(x) */
3689 retval = gen_reg_rtx (Pmode);
3690 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3692 dest = gen_rtx_PLUS (Pmode, retval, tp);
3703 frv_legitimize_address (rtx x,
3704 rtx oldx ATTRIBUTE_UNUSED,
3705 enum machine_mode mode ATTRIBUTE_UNUSED)
3707 if (GET_CODE (x) == SYMBOL_REF)
3709 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3711 return frv_legitimize_tls_address (x, model);
3717 /* Test whether a local function descriptor is canonical, i.e.,
3718 whether we can use FUNCDESC_GOTOFF to compute the address of the
3722 frv_local_funcdesc_p (rtx fnx)
3725 enum symbol_visibility vis;
3728 if (! SYMBOL_REF_LOCAL_P (fnx))
3731 fn = SYMBOL_REF_DECL (fnx);
3736 vis = DECL_VISIBILITY (fn);
3738 if (vis == VISIBILITY_PROTECTED)
3739 /* Private function descriptors for protected functions are not
3740 canonical. Temporarily change the visibility to global. */
3741 vis = VISIBILITY_DEFAULT;
3742 else if (flag_shlib)
3743 /* If we're already compiling for a shared library (that, unlike
3744 executables, can't assume that the existence of a definition
3745 implies local binding), we can skip the re-testing. */
3748 ret = default_binds_local_p_1 (fn, flag_pic);
3750 DECL_VISIBILITY (fn) = vis;
3755 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3759 frv_gen_GPsym2reg (rtx dest, rtx src)
3761 tree gp = get_identifier ("_gp");
3762 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3764 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3768 unspec_got_name (int i)
3772 case R_FRV_GOT12: return "got12";
3773 case R_FRV_GOTHI: return "gothi";
3774 case R_FRV_GOTLO: return "gotlo";
3775 case R_FRV_FUNCDESC: return "funcdesc";
3776 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3777 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3778 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3779 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3780 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3781 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3782 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3783 case R_FRV_GOTOFF12: return "gotoff12";
3784 case R_FRV_GOTOFFHI: return "gotoffhi";
3785 case R_FRV_GOTOFFLO: return "gotofflo";
3786 case R_FRV_GPREL12: return "gprel12";
3787 case R_FRV_GPRELHI: return "gprelhi";
3788 case R_FRV_GPRELLO: return "gprello";
3789 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3790 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3791 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3792 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3793 case R_FRV_TLSMOFF12: return "tlsmoff12";
3794 case R_FRV_TLSDESCHI: return "tlsdeschi";
3795 case R_FRV_TLSDESCLO: return "tlsdesclo";
3796 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3797 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3798 default: gcc_unreachable ();
3802 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3803 is added inside the relocation operator. */
3806 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3808 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3809 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3810 fputs (")", stream);
3813 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3814 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3815 otherwise return ORIG_X. */
3818 frv_find_base_term (rtx x)
3820 struct frv_unspec unspec;
3822 if (frv_const_unspec_p (x, &unspec)
3823 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3824 return plus_constant (unspec.symbol, unspec.offset);
3829 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3830 the operand is used by a predicated instruction. */
3833 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3835 return ((GET_MODE (op) == mode || mode == VOIDmode)
3836 && GET_CODE (op) == MEM
3837 && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
3838 reload_completed, condexec_p, FALSE));
3842 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3844 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3845 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3851 rvrtx = operands[0];
3855 addr = XEXP (operands[0], 0);
3857 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3858 any calls that would involve a PLT, but can't tell, since we
3859 don't know whether an extern function is going to be provided by
3860 a separate translation unit or imported from a separate module.
3861 When compiling for shared libraries, if the function has default
3862 visibility, we assume it's overridable, so we inline the PLT, but
3863 for executables, we don't really have a way to make a good
3864 decision: a function is as likely to be imported from a shared
3865 library as it is to be defined in the executable itself. We
3866 assume executables will get global functions defined locally,
3867 whereas shared libraries will have them potentially overridden,
3868 so we only inline PLTs when compiling for shared libraries.
3870 In order to mark a function as local to a shared library, any
3871 non-default visibility attribute suffices. Unfortunately,
3872 there's no simple way to tag a function declaration as ``in a
3873 different module'', which we could then use to trigger PLT
3874 inlining on executables. There's -minline-plt, but it affects
3875 all external functions, so one would have to also mark function
3876 declarations available in the same module with non-default
3877 visibility, which is advantageous in itself. */
3878 if (GET_CODE (addr) == SYMBOL_REF
3879 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3883 dest = gen_reg_rtx (SImode);
3885 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3886 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3888 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3889 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3891 crtl->uses_pic_offset_table = TRUE;
3894 else if (GET_CODE (addr) == SYMBOL_REF)
3896 /* These are always either local, or handled through a local
3899 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3900 operands[2], picreg, lr);
3902 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3906 else if (! ldd_address_operand (addr, Pmode))
3907 addr = force_reg (Pmode, addr);
3909 picreg = gen_reg_rtx (DImode);
3910 emit_insn (gen_movdi_ldd (picreg, addr));
3912 if (sibcall && ret_value)
3913 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3915 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3917 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3919 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3923 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3924 process these separately from any offsets, such that we add any
3925 offsets to the function descriptor (the actual pointer), not to the
3926 function address. */
3929 frv_function_symbol_referenced_p (rtx x)
3935 if (GET_CODE (x) == SYMBOL_REF)
3936 return SYMBOL_REF_FUNCTION_P (x);
3938 length = GET_RTX_LENGTH (GET_CODE (x));
3939 format = GET_RTX_FORMAT (GET_CODE (x));
3941 for (j = 0; j < length; ++j)
3946 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3952 if (XVEC (x, j) != 0)
3955 for (k = 0; k < XVECLEN (x, j); ++k)
3956 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3962 /* Nothing to do. */
3970 /* Return true if the memory operand is one that can be conditionally
3974 condexec_memory_operand (rtx op, enum machine_mode mode)
3976 enum machine_mode op_mode = GET_MODE (op);
3979 if (mode != VOIDmode && op_mode != mode)
3994 if (GET_CODE (op) != MEM)
3997 addr = XEXP (op, 0);
3998 return frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE);
4001 /* Return true if the bare return instruction can be used outside of the
4002 epilog code. For frv, we only do it if there was no stack allocation. */
4005 direct_return_p (void)
4009 if (!reload_completed)
4012 info = frv_stack_info ();
4013 return (info->total_size == 0);
4018 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
4020 if (GET_CODE (src) == SYMBOL_REF)
4022 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
4024 src = frv_legitimize_tls_address (src, model);
4030 if (frv_emit_movsi (dest, src))
4039 if (!reload_in_progress
4040 && !reload_completed
4041 && !register_operand (dest, mode)
4042 && !reg_or_0_operand (src, mode))
4043 src = copy_to_mode_reg (mode, src);
4050 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
4053 /* Emit code to handle a MOVSI, adding in the small data register or pic
4054 register if needed to load up addresses. Return TRUE if the appropriate
4055 instructions are emitted. */
4058 frv_emit_movsi (rtx dest, rtx src)
4060 int base_regno = -1;
4063 struct frv_unspec old_unspec;
4065 if (!reload_in_progress
4066 && !reload_completed
4067 && !register_operand (dest, SImode)
4068 && (!reg_or_0_operand (src, SImode)
4069 /* Virtual registers will almost always be replaced by an
4070 add instruction, so expose this to CSE by copying to
4071 an intermediate register. */
4072 || (GET_CODE (src) == REG
4073 && IN_RANGE_P (REGNO (src),
4074 FIRST_VIRTUAL_REGISTER,
4075 LAST_VIRTUAL_POINTER_REGISTER))))
4077 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
4081 /* Explicitly add in the PIC or small data register if needed. */
4082 switch (GET_CODE (src))
4091 /* Using GPREL12, we use a single GOT entry for all symbols
4092 in read-only sections, but trade sequences such as:
4094 sethi #gothi(label), gr#
4095 setlo #gotlo(label), gr#
4100 ld @(gr15,#got12(_gp)), gr#
4101 sethi #gprelhi(label), gr##
4102 setlo #gprello(label), gr##
4105 We may often be able to share gr# for multiple
4106 computations of GPREL addresses, and we may often fold
4107 the final add into the pair of registers of a load or
4108 store instruction, so it's often profitable. Even when
4109 optimizing for size, we're trading a GOT entry for an
4110 additional instruction, which trades GOT space
4111 (read-write) for code size (read-only, shareable), as
4112 long as the symbol is not used in more than two different
4115 With -fpie/-fpic, we'd be trading a single load for a
4116 sequence of 4 instructions, because the offset of the
4117 label can't be assumed to be addressable with 12 bits, so
4118 we don't do this. */
4119 if (TARGET_GPREL_RO)
4120 unspec = R_FRV_GPREL12;
4122 unspec = R_FRV_GOT12;
4125 base_regno = PIC_REGNO;
4130 if (frv_const_unspec_p (src, &old_unspec))
4133 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4136 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4137 emit_move_insn (dest, src);
4142 sym = XEXP (sym, 0);
4143 if (GET_CODE (sym) == PLUS
4144 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4145 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4146 sym = XEXP (sym, 0);
4147 if (GET_CODE (sym) == SYMBOL_REF)
4149 else if (GET_CODE (sym) == LABEL_REF)
4152 goto handle_whatever;
4160 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4164 src = frv_legitimize_tls_address (src, model);
4165 emit_move_insn (dest, src);
4169 if (SYMBOL_REF_FUNCTION_P (sym))
4171 if (frv_local_funcdesc_p (sym))
4172 unspec = R_FRV_FUNCDESC_GOTOFF12;
4174 unspec = R_FRV_FUNCDESC_GOT12;
4178 if (CONSTANT_POOL_ADDRESS_P (sym))
4179 switch (GET_CODE (get_pool_constant (sym)))
4186 unspec = R_FRV_GOTOFF12;
4191 if (TARGET_GPREL_RO)
4192 unspec = R_FRV_GPREL12;
4194 unspec = R_FRV_GOT12;
4197 else if (SYMBOL_REF_LOCAL_P (sym)
4198 && !SYMBOL_REF_EXTERNAL_P (sym)
4199 && SYMBOL_REF_DECL (sym)
4200 && (!DECL_P (SYMBOL_REF_DECL (sym))
4201 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4203 tree decl = SYMBOL_REF_DECL (sym);
4204 tree init = TREE_CODE (decl) == VAR_DECL
4205 ? DECL_INITIAL (decl)
4206 : TREE_CODE (decl) == CONSTRUCTOR
4209 bool named_section, readonly;
4211 if (init && init != error_mark_node)
4212 reloc = compute_reloc_for_constant (init);
4214 named_section = TREE_CODE (decl) == VAR_DECL
4215 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4216 readonly = decl_readonly_section (decl, reloc);
4219 unspec = R_FRV_GOT12;
4221 unspec = R_FRV_GOTOFF12;
4222 else if (readonly && TARGET_GPREL_RO)
4223 unspec = R_FRV_GPREL12;
4225 unspec = R_FRV_GOT12;
4228 unspec = R_FRV_GOT12;
4232 else if (SYMBOL_REF_SMALL_P (sym))
4233 base_regno = SDA_BASE_REG;
4236 base_regno = PIC_REGNO;
4241 if (base_regno >= 0)
4243 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4244 emit_insn (gen_symGOTOFF2reg (dest, src,
4245 gen_rtx_REG (Pmode, base_regno),
4246 GEN_INT (R_FRV_GPREL12)));
4248 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4249 gen_rtx_REG (Pmode, base_regno),
4250 GEN_INT (R_FRV_GPREL12)));
4251 if (base_regno == PIC_REGNO)
4252 crtl->uses_pic_offset_table = TRUE;
4260 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4261 new uses of it once reload has begun. */
4262 gcc_assert (!reload_in_progress && !reload_completed);
4266 case R_FRV_GOTOFF12:
4267 if (!frv_small_data_reloc_p (sym, unspec))
4268 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4271 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4274 if (!frv_small_data_reloc_p (sym, unspec))
4275 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4278 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4280 case R_FRV_FUNCDESC_GOTOFF12:
4282 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4285 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4289 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4292 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4296 crtl->uses_pic_offset_table = TRUE;
4305 /* Return a string to output a single word move. */
4308 output_move_single (rtx operands[], rtx insn)
4310 rtx dest = operands[0];
4311 rtx src = operands[1];
4313 if (GET_CODE (dest) == REG)
4315 int dest_regno = REGNO (dest);
4316 enum machine_mode mode = GET_MODE (dest);
4318 if (GPR_P (dest_regno))
4320 if (GET_CODE (src) == REG)
4322 /* gpr <- some sort of register */
4323 int src_regno = REGNO (src);
4325 if (GPR_P (src_regno))
4326 return "mov %1, %0";
4328 else if (FPR_P (src_regno))
4329 return "movfg %1, %0";
4331 else if (SPR_P (src_regno))
4332 return "movsg %1, %0";
4335 else if (GET_CODE (src) == MEM)
4344 return "ldsb%I1%U1 %M1,%0";
4347 return "ldsh%I1%U1 %M1,%0";
4351 return "ld%I1%U1 %M1, %0";
4355 else if (GET_CODE (src) == CONST_INT
4356 || GET_CODE (src) == CONST_DOUBLE)
4358 /* gpr <- integer/floating constant */
4359 HOST_WIDE_INT value;
4361 if (GET_CODE (src) == CONST_INT)
4362 value = INTVAL (src);
4364 else if (mode == SFmode)
4369 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4370 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4375 value = CONST_DOUBLE_LOW (src);
4377 if (IN_RANGE_P (value, -32768, 32767))
4378 return "setlos %1, %0";
4383 else if (GET_CODE (src) == SYMBOL_REF
4384 || GET_CODE (src) == LABEL_REF
4385 || GET_CODE (src) == CONST)
4391 else if (FPR_P (dest_regno))
4393 if (GET_CODE (src) == REG)
4395 /* fpr <- some sort of register */
4396 int src_regno = REGNO (src);
4398 if (GPR_P (src_regno))
4399 return "movgf %1, %0";
4401 else if (FPR_P (src_regno))
4403 if (TARGET_HARD_FLOAT)
4404 return "fmovs %1, %0";
4406 return "mor %1, %1, %0";
4410 else if (GET_CODE (src) == MEM)
4419 return "ldbf%I1%U1 %M1,%0";
4422 return "ldhf%I1%U1 %M1,%0";
4426 return "ldf%I1%U1 %M1, %0";
4430 else if (ZERO_P (src))
4431 return "movgf %., %0";
4434 else if (SPR_P (dest_regno))
4436 if (GET_CODE (src) == REG)
4438 /* spr <- some sort of register */
4439 int src_regno = REGNO (src);
4441 if (GPR_P (src_regno))
4442 return "movgs %1, %0";
4444 else if (ZERO_P (src))
4445 return "movgs %., %0";
4449 else if (GET_CODE (dest) == MEM)
4451 if (GET_CODE (src) == REG)
4453 int src_regno = REGNO (src);
4454 enum machine_mode mode = GET_MODE (dest);
4456 if (GPR_P (src_regno))
4464 return "stb%I0%U0 %1, %M0";
4467 return "sth%I0%U0 %1, %M0";
4471 return "st%I0%U0 %1, %M0";
4475 else if (FPR_P (src_regno))
4483 return "stbf%I0%U0 %1, %M0";
4486 return "sthf%I0%U0 %1, %M0";
4490 return "stf%I0%U0 %1, %M0";
4495 else if (ZERO_P (src))
4497 switch (GET_MODE (dest))
4503 return "stb%I0%U0 %., %M0";
4506 return "sth%I0%U0 %., %M0";
4510 return "st%I0%U0 %., %M0";
4515 fatal_insn ("bad output_move_single operand", insn);
4520 /* Return a string to output a double word move. */
4523 output_move_double (rtx operands[], rtx insn)
4525 rtx dest = operands[0];
4526 rtx src = operands[1];
4527 enum machine_mode mode = GET_MODE (dest);
4529 if (GET_CODE (dest) == REG)
4531 int dest_regno = REGNO (dest);
4533 if (GPR_P (dest_regno))
4535 if (GET_CODE (src) == REG)
4537 /* gpr <- some sort of register */
4538 int src_regno = REGNO (src);
4540 if (GPR_P (src_regno))
4543 else if (FPR_P (src_regno))
4545 if (((dest_regno - GPR_FIRST) & 1) == 0
4546 && ((src_regno - FPR_FIRST) & 1) == 0)
4547 return "movfgd %1, %0";
4553 else if (GET_CODE (src) == MEM)
4556 if (dbl_memory_one_insn_operand (src, mode))
4557 return "ldd%I1%U1 %M1, %0";
4562 else if (GET_CODE (src) == CONST_INT
4563 || GET_CODE (src) == CONST_DOUBLE)
4567 else if (FPR_P (dest_regno))
4569 if (GET_CODE (src) == REG)
4571 /* fpr <- some sort of register */
4572 int src_regno = REGNO (src);
4574 if (GPR_P (src_regno))
4576 if (((dest_regno - FPR_FIRST) & 1) == 0
4577 && ((src_regno - GPR_FIRST) & 1) == 0)
4578 return "movgfd %1, %0";
4583 else if (FPR_P (src_regno))
4586 && ((dest_regno - FPR_FIRST) & 1) == 0
4587 && ((src_regno - FPR_FIRST) & 1) == 0)
4588 return "fmovd %1, %0";
4594 else if (GET_CODE (src) == MEM)
4597 if (dbl_memory_one_insn_operand (src, mode))
4598 return "lddf%I1%U1 %M1, %0";
4603 else if (ZERO_P (src))
4608 else if (GET_CODE (dest) == MEM)
4610 if (GET_CODE (src) == REG)
4612 int src_regno = REGNO (src);
4614 if (GPR_P (src_regno))
4616 if (((src_regno - GPR_FIRST) & 1) == 0
4617 && dbl_memory_one_insn_operand (dest, mode))
4618 return "std%I0%U0 %1, %M0";
4623 if (FPR_P (src_regno))
4625 if (((src_regno - FPR_FIRST) & 1) == 0
4626 && dbl_memory_one_insn_operand (dest, mode))
4627 return "stdf%I0%U0 %1, %M0";
4633 else if (ZERO_P (src))
4635 if (dbl_memory_one_insn_operand (dest, mode))
4636 return "std%I0%U0 %., %M0";
4642 fatal_insn ("bad output_move_double operand", insn);
4647 /* Return a string to output a single word conditional move.
4648 Operand0 -- EQ/NE of ccr register and 0
4649 Operand1 -- CCR register
4650 Operand2 -- destination
4651 Operand3 -- source */
4654 output_condmove_single (rtx operands[], rtx insn)
4656 rtx dest = operands[2];
4657 rtx src = operands[3];
4659 if (GET_CODE (dest) == REG)
4661 int dest_regno = REGNO (dest);
4662 enum machine_mode mode = GET_MODE (dest);
4664 if (GPR_P (dest_regno))
4666 if (GET_CODE (src) == REG)
4668 /* gpr <- some sort of register */
4669 int src_regno = REGNO (src);
4671 if (GPR_P (src_regno))
4672 return "cmov %z3, %2, %1, %e0";
4674 else if (FPR_P (src_regno))
4675 return "cmovfg %3, %2, %1, %e0";
4678 else if (GET_CODE (src) == MEM)
4687 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4690 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4694 return "cld%I3%U3 %M3, %2, %1, %e0";
4698 else if (ZERO_P (src))
4699 return "cmov %., %2, %1, %e0";
4702 else if (FPR_P (dest_regno))
4704 if (GET_CODE (src) == REG)
4706 /* fpr <- some sort of register */
4707 int src_regno = REGNO (src);
4709 if (GPR_P (src_regno))
4710 return "cmovgf %3, %2, %1, %e0";
4712 else if (FPR_P (src_regno))
4714 if (TARGET_HARD_FLOAT)
4715 return "cfmovs %3,%2,%1,%e0";
4717 return "cmor %3, %3, %2, %1, %e0";
4721 else if (GET_CODE (src) == MEM)
4724 if (mode == SImode || mode == SFmode)
4725 return "cldf%I3%U3 %M3, %2, %1, %e0";
4728 else if (ZERO_P (src))
4729 return "cmovgf %., %2, %1, %e0";
4733 else if (GET_CODE (dest) == MEM)
4735 if (GET_CODE (src) == REG)
4737 int src_regno = REGNO (src);
4738 enum machine_mode mode = GET_MODE (dest);
4740 if (GPR_P (src_regno))
4748 return "cstb%I2%U2 %3, %M2, %1, %e0";
4751 return "csth%I2%U2 %3, %M2, %1, %e0";
4755 return "cst%I2%U2 %3, %M2, %1, %e0";
4759 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4760 return "cstf%I2%U2 %3, %M2, %1, %e0";
4763 else if (ZERO_P (src))
4765 enum machine_mode mode = GET_MODE (dest);
4772 return "cstb%I2%U2 %., %M2, %1, %e0";
4775 return "csth%I2%U2 %., %M2, %1, %e0";
4779 return "cst%I2%U2 %., %M2, %1, %e0";
4784 fatal_insn ("bad output_condmove_single operand", insn);
4789 /* Emit the appropriate code to do a comparison, returning the register the
4790 comparison was done it. */
4793 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4795 enum machine_mode cc_mode;
4798 /* Floating point doesn't have comparison against a constant. */
4799 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4800 op1 = force_reg (GET_MODE (op0), op1);
4802 /* Possibly disable using anything but a fixed register in order to work
4803 around cse moving comparisons past function calls. */
4804 cc_mode = SELECT_CC_MODE (test, op0, op1);
4805 cc_reg = ((TARGET_ALLOC_CC)
4806 ? gen_reg_rtx (cc_mode)
4807 : gen_rtx_REG (cc_mode,
4808 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4810 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4811 gen_rtx_COMPARE (cc_mode, op0, op1)));
4817 /* Emit code for a conditional branch.
4818 XXX: I originally wanted to add a clobber of a CCR register to use in
4819 conditional execution, but that confuses the rest of the compiler. */
4822 frv_emit_cond_branch (rtx operands[])
4827 enum rtx_code test = GET_CODE (operands[0]);
4828 rtx cc_reg = frv_emit_comparison (test, operands[1], operands[2]);
4829 enum machine_mode cc_mode = GET_MODE (cc_reg);
4831 /* Branches generate:
4833 (if_then_else (<test>, <cc_reg>, (const_int 0))
4834 (label_ref <branch_label>)
4836 label_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
4837 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4838 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4839 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4844 /* Emit code to set a gpr to 1/0 based on a comparison. */
4847 frv_emit_scc (rtx operands[])
4853 enum rtx_code test = GET_CODE (operands[1]);
4854 rtx cc_reg = frv_emit_comparison (test, operands[2], operands[3]);
4856 /* SCC instructions generate:
4857 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4858 (clobber (<ccr_reg>))]) */
4859 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4860 set = gen_rtx_SET (VOIDmode, operands[0], test_rtx);
4862 cr_reg = ((TARGET_ALLOC_CC)
4863 ? gen_reg_rtx (CC_CCRmode)
4864 : gen_rtx_REG (CC_CCRmode,
4865 ((GET_MODE (cc_reg) == CC_FPmode)
4869 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4870 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4875 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4876 the separate insns. */
4879 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4885 /* Set the appropriate CCR bit. */
4886 emit_insn (gen_rtx_SET (VOIDmode,
4888 gen_rtx_fmt_ee (GET_CODE (test),
4893 /* Move the value into the destination. */
4894 emit_move_insn (dest, GEN_INT (value));
4896 /* Move 0 into the destination if the test failed */
4897 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4898 gen_rtx_EQ (GET_MODE (cr_reg),
4901 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4903 /* Finish up, return sequence. */
4910 /* Emit the code for a conditional move, return TRUE if we could do the
4914 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4921 enum rtx_code test = GET_CODE (test_rtx);
4922 rtx cc_reg = frv_emit_comparison (test,
4923 XEXP (test_rtx, 0), XEXP (test_rtx, 1));
4924 enum machine_mode cc_mode = GET_MODE (cc_reg);
4926 /* Conditional move instructions generate:
4927 (parallel [(set <target>
4928 (if_then_else (<test> <cc_reg> (const_int 0))
4931 (clobber (<ccr_reg>))]) */
4933 /* Handle various cases of conditional move involving two constants. */
4934 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4936 HOST_WIDE_INT value1 = INTVAL (src1);
4937 HOST_WIDE_INT value2 = INTVAL (src2);
4939 /* Having 0 as one of the constants can be done by loading the other
4940 constant, and optionally moving in gr0. */
4941 if (value1 == 0 || value2 == 0)
4944 /* If the first value is within an addi range and also the difference
4945 between the two fits in an addi's range, load up the difference, then
4946 conditionally move in 0, and then unconditionally add the first
4948 else if (IN_RANGE_P (value1, -2048, 2047)
4949 && IN_RANGE_P (value2 - value1, -2048, 2047))
4952 /* If neither condition holds, just force the constant into a
4956 src1 = force_reg (GET_MODE (dest), src1);
4957 src2 = force_reg (GET_MODE (dest), src2);
4961 /* If one value is a register, insure the other value is either 0 or a
4965 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4966 src1 = force_reg (GET_MODE (dest), src1);
4968 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4969 src2 = force_reg (GET_MODE (dest), src2);
4972 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4973 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4975 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4977 cr_reg = ((TARGET_ALLOC_CC)
4978 ? gen_reg_rtx (CC_CCRmode)
4979 : gen_rtx_REG (CC_CCRmode,
4980 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4982 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4983 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4988 /* Split a conditional move into constituent parts, returning a SEQUENCE
4989 containing all of the insns. */
4992 frv_split_cond_move (rtx operands[])
4994 rtx dest = operands[0];
4995 rtx test = operands[1];
4996 rtx cc_reg = operands[2];
4997 rtx src1 = operands[3];
4998 rtx src2 = operands[4];
4999 rtx cr_reg = operands[5];
5001 enum machine_mode cr_mode = GET_MODE (cr_reg);
5005 /* Set the appropriate CCR bit. */
5006 emit_insn (gen_rtx_SET (VOIDmode,
5008 gen_rtx_fmt_ee (GET_CODE (test),
5013 /* Handle various cases of conditional move involving two constants. */
5014 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
5016 HOST_WIDE_INT value1 = INTVAL (src1);
5017 HOST_WIDE_INT value2 = INTVAL (src2);
5019 /* Having 0 as one of the constants can be done by loading the other
5020 constant, and optionally moving in gr0. */
5023 emit_move_insn (dest, src2);
5024 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5025 gen_rtx_NE (cr_mode, cr_reg,
5027 gen_rtx_SET (VOIDmode, dest, src1)));
5030 else if (value2 == 0)
5032 emit_move_insn (dest, src1);
5033 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5034 gen_rtx_EQ (cr_mode, cr_reg,
5036 gen_rtx_SET (VOIDmode, dest, src2)));
5039 /* If the first value is within an addi range and also the difference
5040 between the two fits in an addi's range, load up the difference, then
5041 conditionally move in 0, and then unconditionally add the first
5043 else if (IN_RANGE_P (value1, -2048, 2047)
5044 && IN_RANGE_P (value2 - value1, -2048, 2047))
5046 rtx dest_si = ((GET_MODE (dest) == SImode)
5048 : gen_rtx_SUBREG (SImode, dest, 0));
5050 emit_move_insn (dest_si, GEN_INT (value2 - value1));
5051 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5052 gen_rtx_NE (cr_mode, cr_reg,
5054 gen_rtx_SET (VOIDmode, dest_si,
5056 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
5064 /* Emit the conditional move for the test being true if needed. */
5065 if (! rtx_equal_p (dest, src1))
5066 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5067 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5068 gen_rtx_SET (VOIDmode, dest, src1)));
5070 /* Emit the conditional move for the test being false if needed. */
5071 if (! rtx_equal_p (dest, src2))
5072 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5073 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5074 gen_rtx_SET (VOIDmode, dest, src2)));
5077 /* Finish up, return sequence. */
5084 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5085 memory location that is not known to be dword-aligned. */
5087 frv_split_double_load (rtx dest, rtx source)
5089 int regno = REGNO (dest);
5090 rtx dest1 = gen_highpart (SImode, dest);
5091 rtx dest2 = gen_lowpart (SImode, dest);
5092 rtx address = XEXP (source, 0);
5094 /* If the address is pre-modified, load the lower-numbered register
5095 first, then load the other register using an integer offset from
5096 the modified base register. This order should always be safe,
5097 since the pre-modification cannot affect the same registers as the
5100 The situation for other loads is more complicated. Loading one
5101 of the registers could affect the value of ADDRESS, so we must
5102 be careful which order we do them in. */
5103 if (GET_CODE (address) == PRE_MODIFY
5104 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
5106 /* It is safe to load the lower-numbered register first. */
5107 emit_move_insn (dest1, change_address (source, SImode, NULL));
5108 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5112 /* ADDRESS is not pre-modified and the address depends on the
5113 lower-numbered register. Load the higher-numbered register
5115 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
5116 emit_move_insn (dest1, change_address (source, SImode, NULL));
5120 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5121 and SOURCE is either a double register or the constant zero. */
5123 frv_split_double_store (rtx dest, rtx source)
5125 rtx dest1 = change_address (dest, SImode, NULL);
5126 rtx dest2 = frv_index_memory (dest, SImode, 1);
5127 if (ZERO_P (source))
5129 emit_move_insn (dest1, CONST0_RTX (SImode));
5130 emit_move_insn (dest2, CONST0_RTX (SImode));
5134 emit_move_insn (dest1, gen_highpart (SImode, source));
5135 emit_move_insn (dest2, gen_lowpart (SImode, source));
5140 /* Split a min/max operation returning a SEQUENCE containing all of the
5144 frv_split_minmax (rtx operands[])
5146 rtx dest = operands[0];
5147 rtx minmax = operands[1];
5148 rtx src1 = operands[2];
5149 rtx src2 = operands[3];
5150 rtx cc_reg = operands[4];
5151 rtx cr_reg = operands[5];
5153 enum rtx_code test_code;
5154 enum machine_mode cr_mode = GET_MODE (cr_reg);
5158 /* Figure out which test to use. */
5159 switch (GET_CODE (minmax))
5164 case SMIN: test_code = LT; break;
5165 case SMAX: test_code = GT; break;
5166 case UMIN: test_code = LTU; break;
5167 case UMAX: test_code = GTU; break;
5170 /* Issue the compare instruction. */
5171 emit_insn (gen_rtx_SET (VOIDmode,
5173 gen_rtx_COMPARE (GET_MODE (cc_reg),
5176 /* Set the appropriate CCR bit. */
5177 emit_insn (gen_rtx_SET (VOIDmode,
5179 gen_rtx_fmt_ee (test_code,
5184 /* If are taking the min/max of a nonzero constant, load that first, and
5185 then do a conditional move of the other value. */
5186 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5188 gcc_assert (!rtx_equal_p (dest, src1));
5190 emit_move_insn (dest, src2);
5191 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5192 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5193 gen_rtx_SET (VOIDmode, dest, src1)));
5196 /* Otherwise, do each half of the move. */
5199 /* Emit the conditional move for the test being true if needed. */
5200 if (! rtx_equal_p (dest, src1))
5201 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5202 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5203 gen_rtx_SET (VOIDmode, dest, src1)));
5205 /* Emit the conditional move for the test being false if needed. */
5206 if (! rtx_equal_p (dest, src2))
5207 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5208 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5209 gen_rtx_SET (VOIDmode, dest, src2)));
5212 /* Finish up, return sequence. */
5219 /* Split an integer abs operation returning a SEQUENCE containing all of the
5223 frv_split_abs (rtx operands[])
5225 rtx dest = operands[0];
5226 rtx src = operands[1];
5227 rtx cc_reg = operands[2];
5228 rtx cr_reg = operands[3];
5233 /* Issue the compare < 0 instruction. */
5234 emit_insn (gen_rtx_SET (VOIDmode,
5236 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5238 /* Set the appropriate CCR bit. */
5239 emit_insn (gen_rtx_SET (VOIDmode,
5241 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5243 /* Emit the conditional negate if the value is negative. */
5244 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5245 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5246 gen_negsi2 (dest, src)));
5248 /* Emit the conditional move for the test being false if needed. */
5249 if (! rtx_equal_p (dest, src))
5250 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5251 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5252 gen_rtx_SET (VOIDmode, dest, src)));
5254 /* Finish up, return sequence. */
5261 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5262 register used in an insn. */
5265 frv_clear_registers_used (rtx *ptr, void *data)
5267 if (GET_CODE (*ptr) == REG)
5269 int regno = REGNO (*ptr);
5270 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5272 if (regno < FIRST_PSEUDO_REGISTER)
5274 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5276 while (regno < reg_max)
5278 CLEAR_HARD_REG_BIT (*p_regs, regno);
5288 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5290 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5291 initialize the static storage. */
5293 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5295 frv_ifcvt.added_insns_list = NULL_RTX;
5296 frv_ifcvt.cur_scratch_regs = 0;
5297 frv_ifcvt.num_nested_cond_exec = 0;
5298 frv_ifcvt.cr_reg = NULL_RTX;
5299 frv_ifcvt.nested_cc_reg = NULL_RTX;
5300 frv_ifcvt.extra_int_cr = NULL_RTX;
5301 frv_ifcvt.extra_fp_cr = NULL_RTX;
5302 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5306 /* Internal function to add a potential insn to the list of insns to be inserted
5307 if the conditional execution conversion is successful. */
5310 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5312 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5314 link->jump = before_p; /* Mark to add this before or after insn. */
5315 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5316 frv_ifcvt.added_insns_list);
5318 if (TARGET_DEBUG_COND_EXEC)
5321 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5322 (before_p) ? "before" : "after",
5323 (int)INSN_UID (insn));
5325 debug_rtx (pattern);
5330 /* A C expression to modify the code described by the conditional if
5331 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5332 FALSE_EXPR for converting if-then and if-then-else code to conditional
5333 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5334 tests cannot be converted. */
5337 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5339 basic_block test_bb = ce_info->test_bb; /* test basic block */
5340 basic_block then_bb = ce_info->then_bb; /* THEN */
5341 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5342 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5343 rtx true_expr = *p_true;
5347 enum machine_mode mode = GET_MODE (true_expr);
5351 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5353 rtx sub_cond_exec_reg;
5355 enum rtx_code code_true;
5356 enum rtx_code code_false;
5357 enum reg_class cc_class;
5358 enum reg_class cr_class;
5361 reg_set_iterator rsi;
5363 /* Make sure we are only dealing with hard registers. Also honor the
5364 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5366 if (!reload_completed || !TARGET_COND_EXEC
5367 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5370 /* Figure out which registers we can allocate for our own purposes. Only
5371 consider registers that are not preserved across function calls and are
5372 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5373 if we did not need to use them in reloading other registers. */
5374 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5375 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5376 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5377 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5378 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5380 /* If this is a nested IF, we need to discover whether the CC registers that
5381 are set/used inside of the block are used anywhere else. If not, we can
5382 change them to be the CC register that is paired with the CR register that
5383 controls the outermost IF block. */
5384 if (ce_info->pass > 1)
5386 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5387 for (j = CC_FIRST; j <= CC_LAST; j++)
5388 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5390 if (REGNO_REG_SET_P (df_get_live_in (then_bb), j))
5394 && REGNO_REG_SET_P (df_get_live_in (else_bb), j))
5398 && REGNO_REG_SET_P (df_get_live_in (join_bb), j))
5401 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5405 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5406 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5408 frv_ifcvt.added_insns_list = NULL_RTX;
5409 frv_ifcvt.cur_scratch_regs = 0;
5411 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5412 * sizeof (basic_block));
5418 /* Remove anything live at the beginning of the join block from being
5419 available for allocation. */
5420 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb), 0, regno, rsi)
5422 if (regno < FIRST_PSEUDO_REGISTER)
5423 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5427 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5429 if (ce_info->num_multiple_test_blocks)
5431 basic_block multiple_test_bb = ce_info->last_test_bb;
5433 while (multiple_test_bb != test_bb)
5435 bb[num_bb++] = multiple_test_bb;
5436 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5440 /* Add in the THEN and ELSE blocks to be scanned. */
5441 bb[num_bb++] = then_bb;
5443 bb[num_bb++] = else_bb;
5445 sub_cond_exec_reg = NULL_RTX;
5446 frv_ifcvt.num_nested_cond_exec = 0;
5448 /* Scan all of the blocks for registers that must not be allocated. */
5449 for (j = 0; j < num_bb; j++)
5451 rtx last_insn = BB_END (bb[j]);
5452 rtx insn = BB_HEAD (bb[j]);
5456 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5457 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5459 (int) INSN_UID (BB_HEAD (bb[j])),
5460 (int) INSN_UID (BB_END (bb[j])));
5462 /* Anything live at the beginning of the block is obviously unavailable
5464 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb[j]), 0, regno, rsi)
5466 if (regno < FIRST_PSEUDO_REGISTER)
5467 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5470 /* Loop through the insns in the block. */
5473 /* Mark any new registers that are created as being unavailable for
5474 allocation. Also see if the CC register used in nested IFs can be
5480 int skip_nested_if = FALSE;
5482 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5483 (void *)&tmp_reg->regs);
5485 pattern = PATTERN (insn);
5486 if (GET_CODE (pattern) == COND_EXEC)
5488 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5490 if (reg != sub_cond_exec_reg)
5492 sub_cond_exec_reg = reg;
5493 frv_ifcvt.num_nested_cond_exec++;
5497 set = single_set_pattern (pattern);
5500 rtx dest = SET_DEST (set);
5501 rtx src = SET_SRC (set);
5503 if (GET_CODE (dest) == REG)
5505 int regno = REGNO (dest);
5506 enum rtx_code src_code = GET_CODE (src);
5508 if (CC_P (regno) && src_code == COMPARE)
5509 skip_nested_if = TRUE;
5511 else if (CR_P (regno)
5512 && (src_code == IF_THEN_ELSE
5513 || COMPARISON_P (src)))
5514 skip_nested_if = TRUE;
5518 if (! skip_nested_if)
5519 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5520 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5523 if (insn == last_insn)
5526 insn = NEXT_INSN (insn);
5530 /* If this is a nested if, rewrite the CC registers that are available to
5531 include the ones that can be rewritten, to increase the chance of being
5532 able to allocate a paired CC/CR register combination. */
5533 if (ce_info->pass > 1)
5535 for (j = CC_FIRST; j <= CC_LAST; j++)
5536 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5537 SET_HARD_REG_BIT (tmp_reg->regs, j);
5539 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5545 fprintf (dump_file, "Available GPRs: ");
5547 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5548 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5550 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5551 if (++num_gprs > GPR_TEMP_NUM+2)
5555 fprintf (dump_file, "%s\nAvailable CRs: ",
5556 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5558 for (j = CR_FIRST; j <= CR_LAST; j++)
5559 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5560 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5562 fputs ("\n", dump_file);
5564 if (ce_info->pass > 1)
5566 fprintf (dump_file, "Modifiable CCs: ");
5567 for (j = CC_FIRST; j <= CC_LAST; j++)
5568 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5569 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5571 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5572 frv_ifcvt.num_nested_cond_exec);
5576 /* Allocate the appropriate temporary condition code register. Try to
5577 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5578 that conditional cmp's can be done. */
5579 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5581 cr_class = ICR_REGS;
5582 cc_class = ICC_REGS;
5583 cc_first = ICC_FIRST;
5586 else if (mode == CC_FPmode)
5588 cr_class = FCR_REGS;
5589 cc_class = FCC_REGS;
5590 cc_first = FCC_FIRST;
5595 cc_first = cc_last = 0;
5596 cr_class = cc_class = NO_REGS;
5599 cc = XEXP (true_expr, 0);
5600 nested_cc = cr = NULL_RTX;
5601 if (cc_class != NO_REGS)
5603 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5604 so we can execute a csubcc/caddcc/cfcmps instruction. */
5607 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5609 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5611 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5612 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5614 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5615 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5618 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5619 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5629 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5636 "Will use %s for conditional execution, %s for nested comparisons\n",
5637 reg_names[ REGNO (cr)],
5638 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5640 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5641 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5642 bit being true. We don't do this for floating point, because of NaNs. */
5643 code = GET_CODE (true_expr);
5644 if (GET_MODE (cc) != CC_FPmode)
5646 code = reverse_condition (code);
5656 check_insn = gen_rtx_SET (VOIDmode, cr,
5657 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5659 /* Record the check insn to be inserted later. */
5660 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5662 /* Update the tests. */
5663 frv_ifcvt.cr_reg = cr;
5664 frv_ifcvt.nested_cc_reg = nested_cc;
5665 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5666 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5669 /* Fail, don't do this conditional execution. */
5672 *p_false = NULL_RTX;
5674 fprintf (dump_file, "Disabling this conditional execution.\n");
5680 /* A C expression to modify the code described by the conditional if
5681 information CE_INFO, for the basic block BB, possibly updating the tests in
5682 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5683 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5684 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5686 /* p_true and p_false are given expressions of the form:
5688 (and (eq:CC_CCR (reg:CC_CCR)
5694 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5699 rtx old_true = XEXP (*p_true, 0);
5700 rtx old_false = XEXP (*p_false, 0);
5701 rtx true_expr = XEXP (*p_true, 1);
5702 rtx false_expr = XEXP (*p_false, 1);
5705 rtx cr = XEXP (old_true, 0);
5707 rtx new_cr = NULL_RTX;
5708 rtx *p_new_cr = (rtx *)0;
5712 enum reg_class cr_class;
5713 enum machine_mode mode = GET_MODE (true_expr);
5714 rtx (*logical_func)(rtx, rtx, rtx);
5716 if (TARGET_DEBUG_COND_EXEC)
5719 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5720 ce_info->and_and_p ? "&&" : "||");
5722 debug_rtx (*p_true);
5724 fputs ("\nfalse insn:\n", stderr);
5725 debug_rtx (*p_false);
5728 if (!TARGET_MULTI_CE)
5731 if (GET_CODE (cr) != REG)
5734 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5736 cr_class = ICR_REGS;
5737 p_new_cr = &frv_ifcvt.extra_int_cr;
5739 else if (mode == CC_FPmode)
5741 cr_class = FCR_REGS;
5742 p_new_cr = &frv_ifcvt.extra_fp_cr;
5747 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5748 more &&/|| tests. */
5752 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5753 CC_CCRmode, TRUE, TRUE);
5758 if (ce_info->and_and_p)
5760 old_test = old_false;
5761 test_expr = true_expr;
5762 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5763 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5764 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5768 old_test = old_false;
5769 test_expr = false_expr;
5770 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5771 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5772 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5775 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5776 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5778 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5780 /* Now add the conditional check insn. */
5781 cc = XEXP (test_expr, 0);
5782 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5783 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5785 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5787 /* Add the new check insn to the list of check insns that need to be
5789 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5791 if (TARGET_DEBUG_COND_EXEC)
5793 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5796 debug_rtx (*p_true);
5798 fputs ("\nfalse insn:\n", stderr);
5799 debug_rtx (*p_false);
5805 *p_true = *p_false = NULL_RTX;
5807 /* If we allocated a CR register, release it. */
5810 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5811 *p_new_cr = NULL_RTX;
5814 if (TARGET_DEBUG_COND_EXEC)
5815 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5821 /* Return a register which will be loaded with a value if an IF block is
5822 converted to conditional execution. This is used to rewrite instructions
5823 that use constants to ones that just use registers. */
5826 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5828 int num_alloc = frv_ifcvt.cur_scratch_regs;
5832 /* We know gr0 == 0, so replace any errant uses. */
5833 if (value == const0_rtx)
5834 return gen_rtx_REG (SImode, GPR_FIRST);
5836 /* First search all registers currently loaded to see if we have an
5837 applicable constant. */
5838 if (CONSTANT_P (value)
5839 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5841 for (i = 0; i < num_alloc; i++)
5843 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5844 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5848 /* Have we exhausted the number of registers available? */
5849 if (num_alloc >= GPR_TEMP_NUM)
5852 fprintf (dump_file, "Too many temporary registers allocated\n");
5857 /* Allocate the new register. */
5858 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5862 fputs ("Could not find a scratch register\n", dump_file);
5867 frv_ifcvt.cur_scratch_regs++;
5868 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5872 if (GET_CODE (value) == CONST_INT)
5873 fprintf (dump_file, "Register %s will hold %ld\n",
5874 reg_names[ REGNO (reg)], (long)INTVAL (value));
5876 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5877 fprintf (dump_file, "Register %s will hold LR\n",
5878 reg_names[ REGNO (reg)]);
5881 fprintf (dump_file, "Register %s will hold a saved value\n",
5882 reg_names[ REGNO (reg)]);
5889 /* Update a MEM used in conditional code that might contain an offset to put
5890 the offset into a scratch register, so that the conditional load/store
5891 operations can be used. This function returns the original pointer if the
5892 MEM is valid to use in conditional code, NULL if we can't load up the offset
5893 into a temporary register, or the new MEM if we were successful. */
5896 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5898 rtx addr = XEXP (mem, 0);
5900 if (!frv_legitimate_address_p_1 (mode, addr, reload_completed, TRUE, FALSE))
5902 if (GET_CODE (addr) == PLUS)
5904 rtx addr_op0 = XEXP (addr, 0);
5905 rtx addr_op1 = XEXP (addr, 1);
5907 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5909 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5913 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5920 else if (CONSTANT_P (addr))
5921 addr = frv_ifcvt_load_value (addr, insn);
5926 if (addr == NULL_RTX)
5929 else if (XEXP (mem, 0) != addr)
5930 return change_address (mem, mode, addr);
5937 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5938 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5941 single_set_pattern (rtx pattern)
5946 if (GET_CODE (pattern) == COND_EXEC)
5947 pattern = COND_EXEC_CODE (pattern);
5949 if (GET_CODE (pattern) == SET)
5952 else if (GET_CODE (pattern) == PARALLEL)
5954 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5956 rtx sub = XVECEXP (pattern, 0, i);
5958 switch (GET_CODE (sub))
5982 /* A C expression to modify the code described by the conditional if
5983 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5984 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5985 insn cannot be converted to be executed conditionally. */
5988 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5992 rtx orig_ce_pattern = pattern;
5998 gcc_assert (GET_CODE (pattern) == COND_EXEC);
6000 test = COND_EXEC_TEST (pattern);
6001 if (GET_CODE (test) == AND)
6003 rtx cr = frv_ifcvt.cr_reg;
6006 op0 = XEXP (test, 0);
6007 if (! rtx_equal_p (cr, XEXP (op0, 0)))
6010 op1 = XEXP (test, 1);
6011 test_reg = XEXP (op1, 0);
6012 if (GET_CODE (test_reg) != REG)
6015 /* Is this the first nested if block in this sequence? If so, generate
6016 an andcr or andncr. */
6017 if (! frv_ifcvt.last_nested_if_cr)
6021 frv_ifcvt.last_nested_if_cr = test_reg;
6022 if (GET_CODE (op0) == NE)
6023 and_op = gen_andcr (test_reg, cr, test_reg);
6025 and_op = gen_andncr (test_reg, cr, test_reg);
6027 frv_ifcvt_add_insn (and_op, insn, TRUE);
6030 /* If this isn't the first statement in the nested if sequence, see if we
6031 are dealing with the same register. */
6032 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
6035 COND_EXEC_TEST (pattern) = test = op1;
6038 /* If this isn't a nested if, reset state variables. */
6041 frv_ifcvt.last_nested_if_cr = NULL_RTX;
6044 set = single_set_pattern (pattern);
6047 rtx dest = SET_DEST (set);
6048 rtx src = SET_SRC (set);
6049 enum machine_mode mode = GET_MODE (dest);
6051 /* Check for normal binary operators. */
6052 if (mode == SImode && ARITHMETIC_P (src))
6054 op0 = XEXP (src, 0);
6055 op1 = XEXP (src, 1);
6057 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
6059 op1 = frv_ifcvt_load_value (op1, insn);
6061 COND_EXEC_CODE (pattern)
6062 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
6070 /* For multiply by a constant, we need to handle the sign extending
6071 correctly. Add a USE of the value after the multiply to prevent flow
6072 from cratering because only one register out of the two were used. */
6073 else if (mode == DImode && GET_CODE (src) == MULT)
6075 op0 = XEXP (src, 0);
6076 op1 = XEXP (src, 1);
6077 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
6079 op1 = frv_ifcvt_load_value (op1, insn);
6082 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
6083 COND_EXEC_CODE (pattern)
6084 = gen_rtx_SET (VOIDmode, dest,
6085 gen_rtx_MULT (DImode, op0, op1));
6091 frv_ifcvt_add_insn (gen_use (dest), insn, FALSE);
6094 /* If we are just loading a constant created for a nested conditional
6095 execution statement, just load the constant without any conditional
6096 execution, since we know that the constant will not interfere with any
6098 else if (frv_ifcvt.scratch_insns_bitmap
6099 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
6101 && REG_P (SET_DEST (set))
6102 /* We must not unconditionally set a scratch reg chosen
6103 for a nested if-converted block if its incoming
6104 value from the TEST block (or the result of the THEN
6105 branch) could/should propagate to the JOIN block.
6106 It suffices to test whether the register is live at
6107 the JOIN point: if it's live there, we can infer
6108 that we set it in the former JOIN block of the
6109 nested if-converted block (otherwise it wouldn't
6110 have been available as a scratch register), and it
6111 is either propagated through or set in the other
6112 conditional block. It's probably not worth trying
6113 to catch the latter case, and it could actually
6114 limit scheduling of the combined block quite
6117 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info->join_bb),
6118 REGNO (SET_DEST (set))))
6119 /* Similarly, we must not unconditionally set a reg
6120 used as scratch in the THEN branch if the same reg
6121 is live in the ELSE branch. */
6122 && (! ce_info->else_bb
6123 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6124 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info->else_bb),
6125 REGNO (SET_DEST (set))))))
6128 else if (mode == QImode || mode == HImode || mode == SImode
6131 int changed_p = FALSE;
6133 /* Check for just loading up a constant */
6134 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6136 src = frv_ifcvt_load_value (src, insn);
6143 /* See if we need to fix up stores */
6144 if (GET_CODE (dest) == MEM)
6146 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6151 else if (new_mem != dest)
6158 /* See if we need to fix up loads */
6159 if (GET_CODE (src) == MEM)
6161 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6166 else if (new_mem != src)
6173 /* If either src or destination changed, redo SET. */
6175 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6178 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6179 rewriting the CC register to be the same as the paired CC/CR register
6181 else if (mode == CC_CCRmode && COMPARISON_P (src))
6183 int regno = REGNO (XEXP (src, 0));
6186 if (ce_info->pass > 1
6187 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6188 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6190 src = gen_rtx_fmt_ee (GET_CODE (src),
6192 frv_ifcvt.nested_cc_reg,
6196 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6197 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6200 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6201 else if (ce_info->pass > 1
6202 && GET_CODE (dest) == REG
6203 && CC_P (REGNO (dest))
6204 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6205 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6207 && GET_CODE (src) == COMPARE)
6209 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6210 COND_EXEC_CODE (pattern)
6211 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6215 if (TARGET_DEBUG_COND_EXEC)
6217 rtx orig_pattern = PATTERN (insn);
6219 PATTERN (insn) = pattern;
6221 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6225 PATTERN (insn) = orig_pattern;
6231 if (TARGET_DEBUG_COND_EXEC)
6233 rtx orig_pattern = PATTERN (insn);
6235 PATTERN (insn) = orig_ce_pattern;
6237 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6241 PATTERN (insn) = orig_pattern;
6248 /* A C expression to perform any final machine dependent modifications in
6249 converting code to conditional execution in the code described by the
6250 conditional if information CE_INFO. */
6253 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6257 rtx p = frv_ifcvt.added_insns_list;
6260 /* Loop inserting the check insns. The last check insn is the first test,
6261 and is the appropriate place to insert constants. */
6266 rtx check_and_insert_insns = XEXP (p, 0);
6269 check_insn = XEXP (check_and_insert_insns, 0);
6270 existing_insn = XEXP (check_and_insert_insns, 1);
6273 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6274 the existing insn, otherwise it is to be inserted AFTER. */
6275 if (check_and_insert_insns->jump)
6277 emit_insn_before (check_insn, existing_insn);
6278 check_and_insert_insns->jump = 0;
6281 emit_insn_after (check_insn, existing_insn);
6283 free_EXPR_LIST_node (check_and_insert_insns);
6284 free_EXPR_LIST_node (old_p);
6286 while (p != NULL_RTX);
6288 /* Load up any constants needed into temp gprs */
6289 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6291 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6292 if (! frv_ifcvt.scratch_insns_bitmap)
6293 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6294 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6295 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6298 frv_ifcvt.added_insns_list = NULL_RTX;
6299 frv_ifcvt.cur_scratch_regs = 0;
6303 /* A C expression to cancel any machine dependent modifications in converting
6304 code to conditional execution in the code described by the conditional if
6305 information CE_INFO. */
6308 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6311 rtx p = frv_ifcvt.added_insns_list;
6313 /* Loop freeing up the EXPR_LIST's allocated. */
6314 while (p != NULL_RTX)
6316 rtx check_and_jump = XEXP (p, 0);
6320 free_EXPR_LIST_node (check_and_jump);
6321 free_EXPR_LIST_node (old_p);
6324 /* Release any temporary gprs allocated. */
6325 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6326 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6328 frv_ifcvt.added_insns_list = NULL_RTX;
6329 frv_ifcvt.cur_scratch_regs = 0;
6333 /* A C expression for the size in bytes of the trampoline, as an integer.
6337 setlo #0, <static_chain>
6339 sethi #0, <static_chain>
6340 jmpl @(gr0,<jmp_reg>) */
6343 frv_trampoline_size (void)
6346 /* Allocate room for the function descriptor and the lddi
6349 return 5 /* instructions */ * 4 /* instruction size. */;
6353 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6354 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6355 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6356 should be passed to the function when it is called.
6361 setlo #0, <static_chain>
6363 sethi #0, <static_chain>
6364 jmpl @(gr0,<jmp_reg>) */
6367 frv_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
6369 rtx addr = XEXP (m_tramp, 0);
6370 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6371 rtx sc_reg = force_reg (Pmode, static_chain);
6373 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6376 GEN_INT (frv_trampoline_size ()), SImode,
6382 /* Many machines have some registers that cannot be copied directly to or from
6383 memory or even from other types of registers. An example is the `MQ'
6384 register, which on most machines, can only be copied to or from general
6385 registers, but not memory. Some machines allow copying all registers to and
6386 from memory, but require a scratch register for stores to some memory
6387 locations (e.g., those with symbolic address on the RT, and those with
6388 certain symbolic address on the SPARC when compiling PIC). In some cases,
6389 both an intermediate and a scratch register are required.
6391 You should define these macros to indicate to the reload phase that it may
6392 need to allocate at least one register for a reload in addition to the
6393 register to contain the data. Specifically, if copying X to a register
6394 RCLASS in MODE requires an intermediate register, you should define
6395 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6396 whose registers can be used as intermediate registers or scratch registers.
6398 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6399 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6400 largest register class required. If the requirements for input and output
6401 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6402 instead of defining both macros identically.
6404 The values returned by these macros are often `GENERAL_REGS'. Return
6405 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6406 to or from a register of RCLASS in MODE without requiring a scratch register.
6407 Do not define this macro if it would always return `NO_REGS'.
6409 If a scratch register is required (either with or without an intermediate
6410 register), you should define patterns for `reload_inM' or `reload_outM', as
6411 required.. These patterns, which will normally be implemented with a
6412 `define_expand', should be similar to the `movM' patterns, except that
6413 operand 2 is the scratch register.
6415 Define constraints for the reload register and scratch register that contain
6416 a single register class. If the original reload register (whose class is
6417 RCLASS) can meet the constraint given in the pattern, the value returned by
6418 these macros is used for the class of the scratch register. Otherwise, two
6419 additional reload registers are required. Their classes are obtained from
6420 the constraints in the insn pattern.
6422 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6423 either be in a hard register or in memory. Use `true_regnum' to find out;
6424 it will return -1 if the pseudo is in memory and the hard register number if
6425 it is in a register.
6427 These macros should not be used in the case where a particular class of
6428 registers can only be copied to memory and not to another class of
6429 registers. In that case, secondary reload registers are not needed and
6430 would not be helpful. Instead, a stack location must be used to perform the
6431 copy and the `movM' pattern should use memory as an intermediate storage.
6432 This case often occurs between floating-point and general registers. */
6435 frv_secondary_reload_class (enum reg_class rclass,
6436 enum machine_mode mode ATTRIBUTE_UNUSED,
6447 /* Accumulators/Accumulator guard registers need to go through floating
6453 if (x && GET_CODE (x) == REG)
6455 int regno = REGNO (x);
6457 if (ACC_P (regno) || ACCG_P (regno))
6462 /* Nonzero constants should be loaded into an FPR through a GPR. */
6466 if (x && CONSTANT_P (x) && !ZERO_P (x))
6472 /* All of these types need gpr registers. */
6484 /* The accumulators need fpr registers. */
6496 /* This hook exists to catch the case where secondary_reload_class() is
6497 called from init_reg_autoinc() in regclass.c - before the reload optabs
6498 have been initialised. */
6501 frv_secondary_reload (bool in_p, rtx x, reg_class_t reload_class_i,
6502 enum machine_mode reload_mode,
6503 secondary_reload_info * sri)
6505 enum reg_class rclass = NO_REGS;
6506 enum reg_class reload_class = (enum reg_class) reload_class_i;
6508 if (sri->prev_sri && sri->prev_sri->t_icode != CODE_FOR_nothing)
6510 sri->icode = sri->prev_sri->t_icode;
6514 rclass = frv_secondary_reload_class (reload_class, reload_mode, x);
6516 if (rclass != NO_REGS)
6518 enum insn_code icode
6519 = direct_optab_handler (in_p ? reload_in_optab : reload_out_optab,
6523 /* This happens when then the reload_[in|out]_optabs have
6524 not been initialised. */
6525 sri->t_icode = CODE_FOR_nothing;
6530 /* Fall back to the default secondary reload handler. */
6531 return default_secondary_reload (in_p, x, reload_class, reload_mode, sri);
6535 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6538 frv_class_likely_spilled_p (reg_class_t rclass)
6548 case FDPIC_FPTR_REGS:
6570 /* An expression for the alignment of a structure field FIELD if the
6571 alignment computed in the usual way is COMPUTED. GCC uses this
6572 value instead of the value in `BIGGEST_ALIGNMENT' or
6573 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6575 /* The definition type of the bit field data is either char, short, long or
6576 long long. The maximum bit size is the number of bits of its own type.
6578 The bit field data is assigned to a storage unit that has an adequate size
6579 for bit field data retention and is located at the smallest address.
6581 Consecutive bit field data are packed at consecutive bits having the same
6582 storage unit, with regard to the type, beginning with the MSB and continuing
6585 If a field to be assigned lies over a bit field type boundary, its
6586 assignment is completed by aligning it with a boundary suitable for the
6589 When a bit field having a bit length of 0 is declared, it is forcibly
6590 assigned to the next storage unit.
6603 &x 00000000 00000000 00000000 00000000
6606 &x+4 00000000 00000000 00000000 00000000
6609 &x+8 00000000 00000000 00000000 00000000
6612 &x+12 00000000 00000000 00000000 00000000
6618 frv_adjust_field_align (tree field, int computed)
6620 /* Make sure that the bitfield is not wider than the type. */
6621 if (DECL_BIT_FIELD (field)
6622 && !DECL_ARTIFICIAL (field))
6624 tree parent = DECL_CONTEXT (field);
6625 tree prev = NULL_TREE;
6628 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = DECL_CHAIN (cur))
6630 if (TREE_CODE (cur) != FIELD_DECL)
6638 /* If this isn't a :0 field and if the previous element is a bitfield
6639 also, see if the type is different, if so, we will need to align the
6640 bit-field to the next boundary. */
6642 && ! DECL_PACKED (field)
6643 && ! integer_zerop (DECL_SIZE (field))
6644 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6646 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6647 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6648 computed = (prev_align > cur_align) ? prev_align : cur_align;
6656 /* A C expression that is nonzero if it is permissible to store a value of mode
6657 MODE in hard register number REGNO (or in several registers starting with
6658 that one). For a machine where all registers are equivalent, a suitable
6661 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6663 It is not necessary for this macro to check for the numbers of fixed
6664 registers, because the allocation mechanism considers them to be always
6667 On some machines, double-precision values must be kept in even/odd register
6668 pairs. The way to implement that is to define this macro to reject odd
6669 register numbers for such modes.
6671 The minimum requirement for a mode to be OK in a register is that the
6672 `movMODE' instruction pattern support moves between the register and any
6673 other hard register for which the mode is OK; and that moving a value into
6674 the register and back out not alter it.
6676 Since the same instruction used to move `SImode' will work for all narrower
6677 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6678 to distinguish between these modes, provided you define patterns `movhi',
6679 etc., to take advantage of this. This is useful because of the interaction
6680 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6681 all integer modes to be tieable.
6683 Many machines have special registers for floating point arithmetic. Often
6684 people assume that floating point machine modes are allowed only in floating
6685 point registers. This is not true. Any registers that can hold integers
6686 can safely *hold* a floating point machine mode, whether or not floating
6687 arithmetic can be done on it in those registers. Integer move instructions
6688 can be used to move the values.
6690 On some machines, though, the converse is true: fixed-point machine modes
6691 may not go in floating registers. This is true if the floating registers
6692 normalize any value stored in them, because storing a non-floating value
6693 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6694 fixed-point machine modes in floating registers. But if the floating
6695 registers do not automatically normalize, if you can store any bit pattern
6696 in one and retrieve it unchanged without a trap, then any machine mode may
6697 go in a floating register, so you can define this macro to say so.
6699 The primary significance of special floating registers is rather that they
6700 are the registers acceptable in floating point arithmetic instructions.
6701 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6702 writing the proper constraints for those instructions.
6704 On some machines, the floating registers are especially slow to access, so
6705 that it is better to store a value in a stack frame than in such a register
6706 if floating point arithmetic is not being done. As long as the floating
6707 registers are not in class `GENERAL_REGS', they will not be used unless some
6708 pattern's constraint asks for one. */
6711 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6721 return ICC_P (regno) || GPR_P (regno);
6724 return CR_P (regno) || GPR_P (regno);
6727 return FCC_P (regno) || GPR_P (regno);
6733 /* Set BASE to the first register in REGNO's class. Set MASK to the
6734 bits that must be clear in (REGNO - BASE) for the register to be
6736 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6740 /* ACCGs store one byte. Two-byte quantities must start in
6741 even-numbered registers, four-byte ones in registers whose
6742 numbers are divisible by four, and so on. */
6744 mask = GET_MODE_SIZE (mode) - 1;
6748 /* The other registers store one word. */
6749 if (GPR_P (regno) || regno == AP_FIRST)
6752 else if (FPR_P (regno))
6755 else if (ACC_P (regno))
6758 else if (SPR_P (regno))
6759 return mode == SImode;
6761 /* Fill in the table. */
6765 /* Anything smaller than an SI is OK in any word-sized register. */
6766 if (GET_MODE_SIZE (mode) < 4)
6769 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6771 return (((regno - base) & mask) == 0);
6778 /* A C expression for the number of consecutive hard registers, starting at
6779 register number REGNO, required to hold a value of mode MODE.
6781 On a machine where all registers are exactly one word, a suitable definition
6784 #define HARD_REGNO_NREGS(REGNO, MODE) \
6785 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6786 / UNITS_PER_WORD)) */
6788 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6789 that we can build the appropriate instructions to properly reload the
6790 values. Also, make the byte-sized accumulator guards use one guard
6794 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6797 return GET_MODE_SIZE (mode);
6799 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6803 /* A C expression for the maximum number of consecutive registers of
6804 class RCLASS needed to hold a value of mode MODE.
6806 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6807 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6808 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6810 This macro helps control the handling of multiple-word values in
6813 This declaration is required. */
6816 frv_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
6818 if (rclass == ACCG_REGS)
6819 /* An N-byte value requires N accumulator guards. */
6820 return GET_MODE_SIZE (mode);
6822 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6826 /* A C expression that is nonzero if X is a legitimate constant for an
6827 immediate operand on the target machine. You can assume that X satisfies
6828 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6829 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6832 frv_legitimate_constant_p (rtx x)
6834 enum machine_mode mode = GET_MODE (x);
6836 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6837 means that the move expanders will be expected to deal with most
6838 kinds of constant, regardless of what we return here.
6840 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6841 a constant can be entered into reg_equiv_constant[]. If we return true,
6842 reload can create new instances of the constant whenever it likes.
6844 The idea is therefore to accept as many constants as possible (to give
6845 reload more freedom) while rejecting constants that can only be created
6846 at certain times. In particular, anything with a symbolic component will
6847 require use of the pseudo FDPIC register, which is only available before
6850 return LEGITIMATE_PIC_OPERAND_P (x);
6852 /* All of the integer constants are ok. */
6853 if (GET_CODE (x) != CONST_DOUBLE)
6856 /* double integer constants are ok. */
6857 if (mode == VOIDmode || mode == DImode)
6860 /* 0 is always ok. */
6861 if (x == CONST0_RTX (mode))
6864 /* If floating point is just emulated, allow any constant, since it will be
6865 constructed in the GPRs. */
6866 if (!TARGET_HAS_FPRS)
6869 if (mode == DFmode && !TARGET_DOUBLE)
6872 /* Otherwise store the constant away and do a load. */
6876 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6877 CC_NZ for comparisons against zero in which a single Z or N flag test
6878 is enough, CC_UNS for other unsigned comparisons, and CC for other
6879 signed comparisons. */
6882 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6884 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6893 return y == const0_rtx ? CC_NZmode : CCmode;
6899 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6907 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6909 #define HIGH_COST 40
6910 #define MEDIUM_COST 3
6914 frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
6915 reg_class_t from, reg_class_t to)
6999 /* Worker function for TARGET_MEMORY_MOVE_COST. */
7002 frv_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
7003 reg_class_t rclass ATTRIBUTE_UNUSED,
7004 bool in ATTRIBUTE_UNUSED)
7010 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
7011 use ".picptr" to generate safe relocations for PIC code. We also
7012 need a fixup entry for aligned (non-debugging) code. */
7015 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
7017 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
7019 if (GET_CODE (value) == CONST
7020 || GET_CODE (value) == SYMBOL_REF
7021 || GET_CODE (value) == LABEL_REF)
7023 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
7024 && SYMBOL_REF_FUNCTION_P (value))
7026 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
7027 output_addr_const (asm_out_file, value);
7028 fputs (")\n", asm_out_file);
7031 else if (TARGET_FDPIC && GET_CODE (value) == CONST
7032 && frv_function_symbol_referenced_p (value))
7034 if (aligned_p && !TARGET_FDPIC)
7036 static int label_num = 0;
7040 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
7041 p = (* targetm.strip_name_encoding) (buf);
7043 fprintf (asm_out_file, "%s:\n", p);
7044 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
7045 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
7046 fprintf (asm_out_file, "\t.previous\n");
7048 assemble_integer_with_op ("\t.picptr\t", value);
7053 /* We've set the unaligned SI op to NULL, so we always have to
7054 handle the unaligned case here. */
7055 assemble_integer_with_op ("\t.4byte\t", value);
7059 return default_assemble_integer (value, size, aligned_p);
7062 /* Function to set up the backend function structure. */
7064 static struct machine_function *
7065 frv_init_machine_status (void)
7067 return ggc_alloc_cleared_machine_function ();
7070 /* Implement TARGET_SCHED_ISSUE_RATE. */
7073 frv_issue_rate (void)
7078 switch (frv_cpu_type)
7082 case FRV_CPU_SIMPLE:
7090 case FRV_CPU_GENERIC:
7092 case FRV_CPU_TOMCAT:
7100 /* A for_each_rtx callback. If X refers to an accumulator, return
7101 ACC_GROUP_ODD if the bit 2 of the register number is set and
7102 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
7106 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
7110 if (ACC_P (REGNO (*x)))
7111 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7112 if (ACCG_P (REGNO (*x)))
7113 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
7118 /* Return the value of INSN's acc_group attribute. */
7121 frv_acc_group (rtx insn)
7123 /* This distinction only applies to the FR550 packing constraints. */
7124 if (frv_cpu_type != FRV_CPU_FR550)
7125 return ACC_GROUP_NONE;
7126 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
7129 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7130 INSN will try to claim first. Since this value depends only on the
7131 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7134 frv_insn_unit (rtx insn)
7136 enum attr_type type;
7138 type = get_attr_type (insn);
7139 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
7141 /* We haven't seen this type of instruction before. */
7145 /* Issue the instruction on its own to see which unit it prefers. */
7146 state = alloca (state_size ());
7147 state_reset (state);
7148 state_transition (state, insn);
7150 /* Find out which unit was taken. */
7151 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7152 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7155 gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
7157 frv_type_to_unit[type] = unit;
7159 return frv_type_to_unit[type];
7162 /* Return true if INSN issues to a branch unit. */
7165 frv_issues_to_branch_unit_p (rtx insn)
7167 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7170 /* The current state of the packing pass, implemented by frv_pack_insns. */
7172 /* The state of the pipeline DFA. */
7175 /* Which hardware registers are set within the current packet,
7176 and the conditions under which they are set. */
7177 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7179 /* The memory locations that have been modified so far in this
7180 packet. MEM is the memref and COND is the regstate_t condition
7181 under which it is set. */
7187 /* The number of valid entries in MEMS. The value is larger than
7188 ARRAY_SIZE (mems) if there were too many mems to record. */
7189 unsigned int num_mems;
7191 /* The maximum number of instructions that can be packed together. */
7192 unsigned int issue_rate;
7194 /* The instructions in the packet, partitioned into groups. */
7195 struct frv_packet_group {
7196 /* How many instructions in the packet belong to this group. */
7197 unsigned int num_insns;
7199 /* A list of the instructions that belong to this group, in the order
7200 they appear in the rtl stream. */
7201 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7203 /* The contents of INSNS after they have been sorted into the correct
7204 assembly-language order. Element X issues to unit X. The list may
7205 contain extra nops. */
7206 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7208 /* The member of frv_nops[] to use in sorted[]. */
7210 } groups[NUM_GROUPS];
7212 /* The instructions that make up the current packet. */
7213 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7214 unsigned int num_insns;
7217 /* Return the regstate_t flags for the given COND_EXEC condition.
7218 Abort if the condition isn't in the right form. */
7221 frv_cond_flags (rtx cond)
7223 gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7224 && GET_CODE (XEXP (cond, 0)) == REG
7225 && CR_P (REGNO (XEXP (cond, 0)))
7226 && XEXP (cond, 1) == const0_rtx);
7227 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7228 | (GET_CODE (cond) == NE
7230 : REGSTATE_IF_FALSE));
7234 /* Return true if something accessed under condition COND2 can
7235 conflict with something written under condition COND1. */
7238 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7240 /* If either reference was unconditional, we have a conflict. */
7241 if ((cond1 & REGSTATE_IF_EITHER) == 0
7242 || (cond2 & REGSTATE_IF_EITHER) == 0)
7245 /* The references might conflict if they were controlled by
7247 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7250 /* They definitely conflict if they are controlled by the
7252 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7259 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7260 the current packet. DATA points to a regstate_t that describes the
7261 condition under which *X might be set or used. */
7264 frv_registers_conflict_p_1 (rtx *x, void *data)
7266 unsigned int regno, i;
7269 cond = *(regstate_t *) data;
7271 if (GET_CODE (*x) == REG)
7272 FOR_EACH_REGNO (regno, *x)
7273 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7274 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7277 if (GET_CODE (*x) == MEM)
7279 /* If we ran out of memory slots, assume a conflict. */
7280 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7283 /* Check for output or true dependencies with earlier MEMs. */
7284 for (i = 0; i < frv_packet.num_mems; i++)
7285 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7287 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7291 if (output_dependence (frv_packet.mems[i].mem, *x))
7296 /* The return values of calls aren't significant: they describe
7297 the effect of the call as a whole, not of the insn itself. */
7298 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7300 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7305 /* Check subexpressions. */
7310 /* Return true if something in X might depend on an instruction
7311 in the current packet. */
7314 frv_registers_conflict_p (rtx x)
7319 if (GET_CODE (x) == COND_EXEC)
7321 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7324 flags |= frv_cond_flags (XEXP (x, 0));
7327 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7331 /* A note_stores callback. DATA points to the regstate_t condition
7332 under which X is modified. Update FRV_PACKET accordingly. */
7335 frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7339 if (GET_CODE (x) == REG)
7340 FOR_EACH_REGNO (regno, x)
7341 frv_packet.regstate[regno] |= *(regstate_t *) data;
7343 if (GET_CODE (x) == MEM)
7345 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7347 frv_packet.mems[frv_packet.num_mems].mem = x;
7348 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7350 frv_packet.num_mems++;
7355 /* Update the register state information for an instruction whose
7359 frv_registers_update (rtx x)
7363 flags = REGSTATE_MODIFIED;
7364 if (GET_CODE (x) == COND_EXEC)
7366 flags |= frv_cond_flags (XEXP (x, 0));
7369 note_stores (x, frv_registers_update_1, &flags);
7373 /* Initialize frv_packet for the start of a new packet. */
7376 frv_start_packet (void)
7378 enum frv_insn_group group;
7380 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7381 frv_packet.num_mems = 0;
7382 frv_packet.num_insns = 0;
7383 for (group = 0; group < NUM_GROUPS; group++)
7384 frv_packet.groups[group].num_insns = 0;
7388 /* Likewise for the start of a new basic block. */
7391 frv_start_packet_block (void)
7393 state_reset (frv_packet.dfa_state);
7394 frv_start_packet ();
7398 /* Finish the current packet, if any, and start a new one. Call
7399 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7402 frv_finish_packet (void (*handle_packet) (void))
7404 if (frv_packet.num_insns > 0)
7407 state_transition (frv_packet.dfa_state, 0);
7408 frv_start_packet ();
7413 /* Return true if INSN can be added to the current packet. Update
7414 the DFA state on success. */
7417 frv_pack_insn_p (rtx insn)
7419 /* See if the packet is already as long as it can be. */
7420 if (frv_packet.num_insns == frv_packet.issue_rate)
7423 /* If the scheduler thought that an instruction should start a packet,
7424 it's usually a good idea to believe it. It knows much more about
7425 the latencies than we do.
7427 There are some exceptions though:
7429 - Conditional instructions are scheduled on the assumption that
7430 they will be executed. This is usually a good thing, since it
7431 tends to avoid unnecessary stalls in the conditional code.
7432 But we want to pack conditional instructions as tightly as
7433 possible, in order to optimize the case where they aren't
7436 - The scheduler will always put branches on their own, even
7437 if there's no real dependency.
7439 - There's no point putting a call in its own packet unless
7441 if (frv_packet.num_insns > 0
7442 && GET_CODE (insn) == INSN
7443 && GET_MODE (insn) == TImode
7444 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7447 /* Check for register conflicts. Don't do this for setlo since any
7448 conflict will be with the partnering sethi, with which it can
7450 if (get_attr_type (insn) != TYPE_SETLO)
7451 if (frv_registers_conflict_p (PATTERN (insn)))
7454 return state_transition (frv_packet.dfa_state, insn) < 0;
7458 /* Add instruction INSN to the current packet. */
7461 frv_add_insn_to_packet (rtx insn)
7463 struct frv_packet_group *packet_group;
7465 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7466 packet_group->insns[packet_group->num_insns++] = insn;
7467 frv_packet.insns[frv_packet.num_insns++] = insn;
7469 frv_registers_update (PATTERN (insn));
7473 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7474 packet ends in a branch or call, insert the nop before it, otherwise
7478 frv_insert_nop_in_packet (rtx insn)
7480 struct frv_packet_group *packet_group;
7483 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7484 last = frv_packet.insns[frv_packet.num_insns - 1];
7485 if (GET_CODE (last) != INSN)
7487 insn = emit_insn_before (PATTERN (insn), last);
7488 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7489 frv_packet.insns[frv_packet.num_insns++] = last;
7493 insn = emit_insn_after (PATTERN (insn), last);
7494 frv_packet.insns[frv_packet.num_insns++] = insn;
7496 packet_group->insns[packet_group->num_insns++] = insn;
7500 /* If packing is enabled, divide the instructions into packets and
7501 return true. Call HANDLE_PACKET for each complete packet. */
7504 frv_for_each_packet (void (*handle_packet) (void))
7506 rtx insn, next_insn;
7508 frv_packet.issue_rate = frv_issue_rate ();
7510 /* Early exit if we don't want to pack insns. */
7512 || !flag_schedule_insns_after_reload
7513 || !TARGET_VLIW_BRANCH
7514 || frv_packet.issue_rate == 1)
7517 /* Set up the initial packing state. */
7519 frv_packet.dfa_state = alloca (state_size ());
7521 frv_start_packet_block ();
7522 for (insn = get_insns (); insn != 0; insn = next_insn)
7527 code = GET_CODE (insn);
7528 next_insn = NEXT_INSN (insn);
7530 if (code == CODE_LABEL)
7532 frv_finish_packet (handle_packet);
7533 frv_start_packet_block ();
7537 switch (GET_CODE (PATTERN (insn)))
7546 /* Calls mustn't be packed on a TOMCAT. */
7547 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7548 frv_finish_packet (handle_packet);
7550 /* Since the last instruction in a packet determines the EH
7551 region, any exception-throwing instruction must come at
7552 the end of reordered packet. Insns that issue to a
7553 branch unit are bound to come last; for others it's
7554 too hard to predict. */
7555 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7556 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7557 frv_finish_packet (handle_packet);
7559 /* Finish the current packet if we can't add INSN to it.
7560 Simulate cycles until INSN is ready to issue. */
7561 if (!frv_pack_insn_p (insn))
7563 frv_finish_packet (handle_packet);
7564 while (!frv_pack_insn_p (insn))
7565 state_transition (frv_packet.dfa_state, 0);
7568 /* Add the instruction to the packet. */
7569 frv_add_insn_to_packet (insn);
7571 /* Calls and jumps end a packet, as do insns that throw
7573 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7574 frv_finish_packet (handle_packet);
7578 frv_finish_packet (handle_packet);
7583 /* Subroutine of frv_sort_insn_group. We are trying to sort
7584 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7585 language order. We have already picked a new position for
7586 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7587 These instructions will occupy elements [0, LOWER_SLOT) and
7588 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7589 the DFA state after issuing these instructions.
7591 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7592 of the unused instructions. Return true if one such permutation gives
7593 a valid ordering, leaving the successful permutation in sorted[].
7594 Do not modify sorted[] until a valid permutation is found. */
7597 frv_sort_insn_group_1 (enum frv_insn_group group,
7598 unsigned int lower_slot, unsigned int upper_slot,
7599 unsigned int issued, unsigned int num_insns,
7602 struct frv_packet_group *packet_group;
7608 /* Early success if we've filled all the slots. */
7609 if (lower_slot == upper_slot)
7612 packet_group = &frv_packet.groups[group];
7613 dfa_size = state_size ();
7614 test_state = alloca (dfa_size);
7616 /* Try issuing each unused instruction. */
7617 for (i = num_insns - 1; i + 1 != 0; i--)
7618 if (~issued & (1 << i))
7620 insn = packet_group->sorted[i];
7621 memcpy (test_state, state, dfa_size);
7622 if (state_transition (test_state, insn) < 0
7623 && cpu_unit_reservation_p (test_state,
7624 NTH_UNIT (group, upper_slot - 1))
7625 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7626 issued | (1 << i), num_insns,
7629 packet_group->sorted[upper_slot - 1] = insn;
7637 /* Compare two instructions by their frv_insn_unit. */
7640 frv_compare_insns (const void *first, const void *second)
7642 const rtx *const insn1 = (rtx const *) first,
7643 *const insn2 = (rtx const *) second;
7644 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7647 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7648 and sort it into assembly language order. See frv.md for a description of
7652 frv_sort_insn_group (enum frv_insn_group group)
7654 struct frv_packet_group *packet_group;
7655 unsigned int first, i, nop, max_unit, num_slots;
7656 state_t state, test_state;
7659 packet_group = &frv_packet.groups[group];
7661 /* Assume no nop is needed. */
7662 packet_group->nop = 0;
7664 if (packet_group->num_insns == 0)
7667 /* Copy insns[] to sorted[]. */
7668 memcpy (packet_group->sorted, packet_group->insns,
7669 sizeof (rtx) * packet_group->num_insns);
7671 /* Sort sorted[] by the unit that each insn tries to take first. */
7672 if (packet_group->num_insns > 1)
7673 qsort (packet_group->sorted, packet_group->num_insns,
7674 sizeof (rtx), frv_compare_insns);
7676 /* That's always enough for branch and control insns. */
7677 if (group == GROUP_B || group == GROUP_C)
7680 dfa_size = state_size ();
7681 state = alloca (dfa_size);
7682 test_state = alloca (dfa_size);
7684 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7685 consecutively and such that the DFA takes unit X when sorted[X]
7686 is added. Set STATE to the new DFA state. */
7687 state_reset (test_state);
7688 for (first = 0; first < packet_group->num_insns; first++)
7690 memcpy (state, test_state, dfa_size);
7691 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7692 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7696 /* If all the instructions issued in ascending order, we're done. */
7697 if (first == packet_group->num_insns)
7700 /* Add nops to the end of sorted[] and try each permutation until
7701 we find one that works. */
7702 for (nop = 0; nop < frv_num_nops; nop++)
7704 max_unit = frv_insn_unit (frv_nops[nop]);
7705 if (frv_unit_groups[max_unit] == group)
7707 packet_group->nop = frv_nops[nop];
7708 num_slots = UNIT_NUMBER (max_unit) + 1;
7709 for (i = packet_group->num_insns; i < num_slots; i++)
7710 packet_group->sorted[i] = frv_nops[nop];
7711 if (frv_sort_insn_group_1 (group, first, num_slots,
7712 (1 << first) - 1, num_slots, state))
7719 /* Sort the current packet into assembly-language order. Set packing
7720 flags as appropriate. */
7723 frv_reorder_packet (void)
7725 unsigned int cursor[NUM_GROUPS];
7726 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7727 unsigned int unit, to, from;
7728 enum frv_insn_group group;
7729 struct frv_packet_group *packet_group;
7731 /* First sort each group individually. */
7732 for (group = 0; group < NUM_GROUPS; group++)
7735 frv_sort_insn_group (group);
7738 /* Go through the unit template and try add an instruction from
7739 that unit's group. */
7741 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7743 group = frv_unit_groups[unit];
7744 packet_group = &frv_packet.groups[group];
7745 if (cursor[group] < packet_group->num_insns)
7747 /* frv_reorg should have added nops for us. */
7748 gcc_assert (packet_group->sorted[cursor[group]]
7749 != packet_group->nop);
7750 insns[to++] = packet_group->sorted[cursor[group]++];
7754 gcc_assert (to == frv_packet.num_insns);
7756 /* Clear the last instruction's packing flag, thus marking the end of
7757 a packet. Reorder the other instructions relative to it. */
7758 CLEAR_PACKING_FLAG (insns[to - 1]);
7759 for (from = 0; from < to - 1; from++)
7761 remove_insn (insns[from]);
7762 add_insn_before (insns[from], insns[to - 1], NULL);
7763 SET_PACKING_FLAG (insns[from]);
7768 /* Divide instructions into packets. Reorder the contents of each
7769 packet so that they are in the correct assembly-language order.
7771 Since this pass can change the raw meaning of the rtl stream, it must
7772 only be called at the last minute, just before the instructions are
7776 frv_pack_insns (void)
7778 if (frv_for_each_packet (frv_reorder_packet))
7779 frv_insn_packing_flag = 0;
7781 frv_insn_packing_flag = -1;
7784 /* See whether we need to add nops to group GROUP in order to
7785 make a valid packet. */
7788 frv_fill_unused_units (enum frv_insn_group group)
7790 unsigned int non_nops, nops, i;
7791 struct frv_packet_group *packet_group;
7793 packet_group = &frv_packet.groups[group];
7795 /* Sort the instructions into assembly-language order.
7796 Use nops to fill slots that are otherwise unused. */
7797 frv_sort_insn_group (group);
7799 /* See how many nops are needed before the final useful instruction. */
7801 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7802 while (packet_group->sorted[i++] == packet_group->nop)
7805 /* Insert that many nops into the instruction stream. */
7807 frv_insert_nop_in_packet (packet_group->nop);
7810 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7813 frv_same_doubleword_p (const struct frv_io *io1, const struct frv_io *io2)
7815 if (io1->const_address != 0 && io2->const_address != 0)
7816 return io1->const_address == io2->const_address;
7818 if (io1->var_address != 0 && io2->var_address != 0)
7819 return rtx_equal_p (io1->var_address, io2->var_address);
7824 /* Return true if operations IO1 and IO2 are guaranteed to complete
7828 frv_io_fixed_order_p (const struct frv_io *io1, const struct frv_io *io2)
7830 /* The order of writes is always preserved. */
7831 if (io1->type == FRV_IO_WRITE && io2->type == FRV_IO_WRITE)
7834 /* The order of reads isn't preserved. */
7835 if (io1->type != FRV_IO_WRITE && io2->type != FRV_IO_WRITE)
7838 /* One operation is a write and the other is (or could be) a read.
7839 The order is only guaranteed if the accesses are to the same
7841 return frv_same_doubleword_p (io1, io2);
7844 /* Generalize I/O operation X so that it covers both X and Y. */
7847 frv_io_union (struct frv_io *x, const struct frv_io *y)
7849 if (x->type != y->type)
7850 x->type = FRV_IO_UNKNOWN;
7851 if (!frv_same_doubleword_p (x, y))
7853 x->const_address = 0;
7858 /* Fill IO with information about the load or store associated with
7859 membar instruction INSN. */
7862 frv_extract_membar (struct frv_io *io, rtx insn)
7864 extract_insn (insn);
7865 io->type = INTVAL (recog_data.operand[2]);
7866 io->const_address = INTVAL (recog_data.operand[1]);
7867 io->var_address = XEXP (recog_data.operand[0], 0);
7870 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7871 if X is a register and *DATA depends on X. */
7874 frv_io_check_address (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7876 rtx *other = (rtx *) data;
7878 if (REG_P (x) && *other != 0 && reg_overlap_mentioned_p (x, *other))
7882 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7883 Remove every modified register from the set. */
7886 frv_io_handle_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
7888 HARD_REG_SET *set = (HARD_REG_SET *) data;
7892 FOR_EACH_REGNO (regno, x)
7893 CLEAR_HARD_REG_BIT (*set, regno);
7896 /* A for_each_rtx callback for which DATA points to a HARD_REG_SET.
7897 Add every register in *X to the set. */
7900 frv_io_handle_use_1 (rtx *x, void *data)
7902 HARD_REG_SET *set = (HARD_REG_SET *) data;
7906 FOR_EACH_REGNO (regno, *x)
7907 SET_HARD_REG_BIT (*set, regno);
7912 /* A note_stores callback that applies frv_io_handle_use_1 to an
7913 entire rhs value. */
7916 frv_io_handle_use (rtx *x, void *data)
7918 for_each_rtx (x, frv_io_handle_use_1, data);
7921 /* Go through block BB looking for membars to remove. There are two
7922 cases where intra-block analysis is enough:
7924 - a membar is redundant if it occurs between two consecutive I/O
7925 operations and if those operations are guaranteed to complete
7928 - a membar for a __builtin_read is redundant if the result is
7929 used before the next I/O operation is issued.
7931 If the last membar in the block could not be removed, and there
7932 are guaranteed to be no I/O operations between that membar and
7933 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7936 Describe the block's first I/O operation in *NEXT_IO. Describe
7937 an unknown operation if the block doesn't do any I/O. */
7940 frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
7943 HARD_REG_SET used_regs;
7944 rtx next_membar, set, insn;
7947 /* NEXT_IO is the next I/O operation to be performed after the current
7948 instruction. It starts off as being an unknown operation. */
7949 memset (next_io, 0, sizeof (*next_io));
7951 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7952 next_is_end_p = true;
7954 /* If the current instruction is a __builtin_read or __builtin_write,
7955 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7956 is null if the membar has already been deleted.
7958 Note that the initialization here should only be needed to
7959 suppress warnings. */
7962 /* USED_REGS is the set of registers that are used before the
7963 next I/O instruction. */
7964 CLEAR_HARD_REG_SET (used_regs);
7966 for (insn = BB_END (bb); insn != BB_HEAD (bb); insn = PREV_INSN (insn))
7967 if (GET_CODE (insn) == CALL_INSN)
7969 /* We can't predict what a call will do to volatile memory. */
7970 memset (next_io, 0, sizeof (struct frv_io));
7971 next_is_end_p = false;
7972 CLEAR_HARD_REG_SET (used_regs);
7974 else if (INSN_P (insn))
7975 switch (recog_memoized (insn))
7977 case CODE_FOR_optional_membar_qi:
7978 case CODE_FOR_optional_membar_hi:
7979 case CODE_FOR_optional_membar_si:
7980 case CODE_FOR_optional_membar_di:
7984 /* Local information isn't enough to decide whether this
7985 membar is needed. Stash it away for later. */
7986 *last_membar = insn;
7987 frv_extract_membar (next_io, insn);
7988 next_is_end_p = false;
7992 /* Check whether the I/O operation before INSN could be
7993 reordered with one described by NEXT_IO. If it can't,
7994 INSN will not be needed. */
7995 struct frv_io prev_io;
7997 frv_extract_membar (&prev_io, insn);
7998 if (frv_io_fixed_order_p (&prev_io, next_io))
8002 ";; [Local] Removing membar %d since order"
8003 " of accesses is guaranteed\n",
8004 INSN_UID (next_membar));
8006 insn = NEXT_INSN (insn);
8007 delete_insn (next_membar);
8015 /* Invalidate NEXT_IO's address if it depends on something that
8016 is clobbered by INSN. */
8017 if (next_io->var_address)
8018 note_stores (PATTERN (insn), frv_io_check_address,
8019 &next_io->var_address);
8021 /* If the next membar is associated with a __builtin_read,
8022 see if INSN reads from that address. If it does, and if
8023 the destination register is used before the next I/O access,
8024 there is no need for the membar. */
8025 set = PATTERN (insn);
8026 if (next_io->type == FRV_IO_READ
8027 && next_io->var_address != 0
8029 && GET_CODE (set) == SET
8030 && GET_CODE (SET_DEST (set)) == REG
8031 && TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
8035 src = SET_SRC (set);
8036 if (GET_CODE (src) == ZERO_EXTEND)
8037 src = XEXP (src, 0);
8039 if (GET_CODE (src) == MEM
8040 && rtx_equal_p (XEXP (src, 0), next_io->var_address))
8044 ";; [Local] Removing membar %d since the target"
8045 " of %d is used before the I/O operation\n",
8046 INSN_UID (next_membar), INSN_UID (insn));
8048 if (next_membar == *last_membar)
8051 delete_insn (next_membar);
8056 /* If INSN has volatile references, forget about any registers
8057 that are used after it. Otherwise forget about uses that
8058 are (or might be) defined by INSN. */
8059 if (volatile_refs_p (PATTERN (insn)))
8060 CLEAR_HARD_REG_SET (used_regs);
8062 note_stores (PATTERN (insn), frv_io_handle_set, &used_regs);
8064 note_uses (&PATTERN (insn), frv_io_handle_use, &used_regs);
8069 /* See if MEMBAR, the last membar instruction in BB, can be removed.
8070 FIRST_IO[X] describes the first operation performed by basic block X. */
8073 frv_optimize_membar_global (basic_block bb, struct frv_io *first_io,
8076 struct frv_io this_io, next_io;
8080 /* We need to keep the membar if there is an edge to the exit block. */
8081 FOR_EACH_EDGE (succ, ei, bb->succs)
8082 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
8083 if (succ->dest == EXIT_BLOCK_PTR)
8086 /* Work out the union of all successor blocks. */
8087 ei = ei_start (bb->succs);
8088 ei_cond (ei, &succ);
8089 /* next_io = first_io[bb->succ->dest->index]; */
8090 next_io = first_io[succ->dest->index];
8091 ei = ei_start (bb->succs);
8092 if (ei_cond (ei, &succ))
8094 for (ei_next (&ei); ei_cond (ei, &succ); ei_next (&ei))
8095 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
8096 frv_io_union (&next_io, &first_io[succ->dest->index]);
8101 frv_extract_membar (&this_io, membar);
8102 if (frv_io_fixed_order_p (&this_io, &next_io))
8106 ";; [Global] Removing membar %d since order of accesses"
8107 " is guaranteed\n", INSN_UID (membar));
8109 delete_insn (membar);
8113 /* Remove redundant membars from the current function. */
8116 frv_optimize_membar (void)
8119 struct frv_io *first_io;
8122 compute_bb_for_insn ();
8123 first_io = XCNEWVEC (struct frv_io, last_basic_block);
8124 last_membar = XCNEWVEC (rtx, last_basic_block);
8127 frv_optimize_membar_local (bb, &first_io[bb->index],
8128 &last_membar[bb->index]);
8131 if (last_membar[bb->index] != 0)
8132 frv_optimize_membar_global (bb, first_io, last_membar[bb->index]);
8138 /* Used by frv_reorg to keep track of the current packet's address. */
8139 static unsigned int frv_packet_address;
8141 /* If the current packet falls through to a label, try to pad the packet
8142 with nops in order to fit the label's alignment requirements. */
8145 frv_align_label (void)
8147 unsigned int alignment, target, nop;
8148 rtx x, last, barrier, label;
8150 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8151 maximum alignment of that packet, LABEL to the last label between
8152 the packets, and BARRIER to the last barrier. */
8153 last = frv_packet.insns[frv_packet.num_insns - 1];
8154 label = barrier = 0;
8156 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
8160 unsigned int subalign = 1 << label_to_alignment (x);
8161 alignment = MAX (alignment, subalign);
8168 /* If -malign-labels, and the packet falls through to an unaligned
8169 label, try introducing a nop to align that label to 8 bytes. */
8170 if (TARGET_ALIGN_LABELS
8173 && frv_packet.num_insns < frv_packet.issue_rate)
8174 alignment = MAX (alignment, 8);
8176 /* Advance the address to the end of the current packet. */
8177 frv_packet_address += frv_packet.num_insns * 4;
8179 /* Work out the target address, after alignment. */
8180 target = (frv_packet_address + alignment - 1) & -alignment;
8182 /* If the packet falls through to the label, try to find an efficient
8183 padding sequence. */
8186 /* First try adding nops to the current packet. */
8187 for (nop = 0; nop < frv_num_nops; nop++)
8188 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
8190 frv_insert_nop_in_packet (frv_nops[nop]);
8191 frv_packet_address += 4;
8194 /* If we still haven't reached the target, add some new packets that
8195 contain only nops. If there are two types of nop, insert an
8196 alternating sequence of frv_nops[0] and frv_nops[1], which will
8197 lead to packets like:
8204 etc. Just emit frv_nops[0] if that's the only nop we have. */
8205 last = frv_packet.insns[frv_packet.num_insns - 1];
8207 while (frv_packet_address < target)
8209 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
8210 frv_packet_address += 4;
8211 if (frv_num_nops > 1)
8216 frv_packet_address = target;
8219 /* Subroutine of frv_reorg, called after each packet has been constructed
8223 frv_reorg_packet (void)
8225 frv_fill_unused_units (GROUP_I);
8226 frv_fill_unused_units (GROUP_FM);
8230 /* Add an instruction with pattern NOP to frv_nops[]. */
8233 frv_register_nop (rtx nop)
8235 nop = make_insn_raw (nop);
8236 NEXT_INSN (nop) = 0;
8237 PREV_INSN (nop) = 0;
8238 frv_nops[frv_num_nops++] = nop;
8241 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8242 into packets and check whether we need to insert nops in order to
8243 fulfill the processor's issue requirements. Also, if the user has
8244 requested a certain alignment for a label, try to meet that alignment
8245 by inserting nops in the previous packet. */
8250 if (optimize > 0 && TARGET_OPTIMIZE_MEMBAR && cfun->machine->has_membar_p)
8251 frv_optimize_membar ();
8254 frv_register_nop (gen_nop ());
8256 frv_register_nop (gen_mnop ());
8257 if (TARGET_HARD_FLOAT)
8258 frv_register_nop (gen_fnop ());
8260 /* Estimate the length of each branch. Although this may change after
8261 we've inserted nops, it will only do so in big functions. */
8262 shorten_branches (get_insns ());
8264 frv_packet_address = 0;
8265 frv_for_each_packet (frv_reorg_packet);
8268 #define def_builtin(name, type, code) \
8269 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8271 struct builtin_description
8273 enum insn_code icode;
8275 enum frv_builtins code;
8276 enum rtx_code comparison;
8280 /* Media intrinsics that take a single, constant argument. */
8282 static struct builtin_description bdesc_set[] =
8284 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
8287 /* Media intrinsics that take just one argument. */
8289 static struct builtin_description bdesc_1arg[] =
8291 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
8292 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
8293 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
8294 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
8295 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
8296 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
8299 /* Media intrinsics that take two arguments. */
8301 static struct builtin_description bdesc_2arg[] =
8303 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
8304 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
8305 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
8306 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
8307 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
8308 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
8309 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
8310 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
8311 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
8312 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
8313 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
8314 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
8315 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
8316 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
8317 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
8318 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
8319 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
8320 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
8321 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
8322 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
8323 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
8324 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
8325 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
8326 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
8327 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
8328 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
8329 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
8332 /* Integer intrinsics that take two arguments and have no return value. */
8334 static struct builtin_description bdesc_int_void2arg[] =
8336 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
8337 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
8338 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
8341 static struct builtin_description bdesc_prefetches[] =
8343 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
8344 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
8347 /* Media intrinsics that take two arguments, the first being an ACC number. */
8349 static struct builtin_description bdesc_cut[] =
8351 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
8352 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
8353 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
8356 /* Two-argument media intrinsics with an immediate second argument. */
8358 static struct builtin_description bdesc_2argimm[] =
8360 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
8361 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
8362 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
8363 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
8364 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
8365 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
8366 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
8367 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
8368 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
8369 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
8370 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
8371 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
8372 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
8373 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
8374 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
8375 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
8376 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
8379 /* Media intrinsics that take two arguments and return void, the first argument
8380 being a pointer to 4 words in memory. */
8382 static struct builtin_description bdesc_void2arg[] =
8384 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
8385 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
8388 /* Media intrinsics that take three arguments, the first being a const_int that
8389 denotes an accumulator, and that return void. */
8391 static struct builtin_description bdesc_void3arg[] =
8393 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
8394 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
8395 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
8396 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
8397 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
8398 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
8399 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
8400 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
8401 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
8402 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
8403 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
8404 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
8405 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
8406 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
8407 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
8408 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
8409 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
8410 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
8411 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
8412 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
8413 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
8414 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
8415 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
8416 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
8417 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
8420 /* Media intrinsics that take two accumulator numbers as argument and
8423 static struct builtin_description bdesc_voidacc[] =
8425 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
8426 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
8427 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
8428 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
8429 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
8430 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
8433 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8434 a normal move and the ICODE is for the membar. */
8436 static struct builtin_description bdesc_loads[] =
8438 { CODE_FOR_optional_membar_qi, "__builtin_read8",
8439 FRV_BUILTIN_READ8, 0, 0 },
8440 { CODE_FOR_optional_membar_hi, "__builtin_read16",
8441 FRV_BUILTIN_READ16, 0, 0 },
8442 { CODE_FOR_optional_membar_si, "__builtin_read32",
8443 FRV_BUILTIN_READ32, 0, 0 },
8444 { CODE_FOR_optional_membar_di, "__builtin_read64",
8445 FRV_BUILTIN_READ64, 0, 0 }
8448 /* Likewise stores. */
8450 static struct builtin_description bdesc_stores[] =
8452 { CODE_FOR_optional_membar_qi, "__builtin_write8",
8453 FRV_BUILTIN_WRITE8, 0, 0 },
8454 { CODE_FOR_optional_membar_hi, "__builtin_write16",
8455 FRV_BUILTIN_WRITE16, 0, 0 },
8456 { CODE_FOR_optional_membar_si, "__builtin_write32",
8457 FRV_BUILTIN_WRITE32, 0, 0 },
8458 { CODE_FOR_optional_membar_di, "__builtin_write64",
8459 FRV_BUILTIN_WRITE64, 0, 0 },
8462 /* Initialize media builtins. */
8465 frv_init_builtins (void)
8467 tree endlink = void_list_node;
8468 tree accumulator = integer_type_node;
8469 tree integer = integer_type_node;
8470 tree voidt = void_type_node;
8471 tree uhalf = short_unsigned_type_node;
8472 tree sword1 = long_integer_type_node;
8473 tree uword1 = long_unsigned_type_node;
8474 tree sword2 = long_long_integer_type_node;
8475 tree uword2 = long_long_unsigned_type_node;
8476 tree uword4 = build_pointer_type (uword1);
8477 tree vptr = build_pointer_type (build_type_variant (void_type_node, 0, 1));
8478 tree ubyte = unsigned_char_type_node;
8479 tree iacc = integer_type_node;
8481 #define UNARY(RET, T1) \
8482 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
8484 #define BINARY(RET, T1, T2) \
8485 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8486 tree_cons (NULL_TREE, T2, endlink)))
8488 #define TRINARY(RET, T1, T2, T3) \
8489 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8490 tree_cons (NULL_TREE, T2, \
8491 tree_cons (NULL_TREE, T3, endlink))))
8493 #define QUAD(RET, T1, T2, T3, T4) \
8494 build_function_type (RET, tree_cons (NULL_TREE, T1, \
8495 tree_cons (NULL_TREE, T2, \
8496 tree_cons (NULL_TREE, T3, \
8497 tree_cons (NULL_TREE, T4, endlink)))))
8499 tree void_ftype_void = build_function_type (voidt, endlink);
8501 tree void_ftype_acc = UNARY (voidt, accumulator);
8502 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
8503 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
8504 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8505 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8506 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8507 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8508 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8509 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8511 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8512 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8513 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8514 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8515 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8516 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8517 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8518 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8519 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8520 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8521 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8523 tree sw1_ftype_int = UNARY (sword1, integer);
8524 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8525 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8527 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8528 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8529 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8530 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8531 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8532 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8534 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8535 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8536 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8537 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8538 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8539 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8540 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8541 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8542 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8543 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8544 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8545 tree uw1_ftype_vptr = UNARY (uword1, vptr);
8546 tree uw2_ftype_vptr = UNARY (uword2, vptr);
8547 tree void_ftype_vptr_ub = BINARY (voidt, vptr, ubyte);
8548 tree void_ftype_vptr_uh = BINARY (voidt, vptr, uhalf);
8549 tree void_ftype_vptr_uw1 = BINARY (voidt, vptr, uword1);
8550 tree void_ftype_vptr_uw2 = BINARY (voidt, vptr, uword2);
8552 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8553 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8554 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8555 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8556 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8557 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8558 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8559 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8560 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8561 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8562 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8563 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8564 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8565 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8566 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8567 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8568 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8569 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8570 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8571 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8572 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8573 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8574 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8575 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8576 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8577 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8578 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8579 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8580 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8581 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8582 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8583 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8584 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8585 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8586 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8587 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8588 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8589 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8590 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8591 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8592 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8593 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8594 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8595 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8596 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8597 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8598 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8599 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8600 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8601 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8602 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8603 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8604 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8605 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8606 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8607 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8608 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8609 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8610 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8611 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8612 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8613 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8614 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8615 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8616 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8617 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8618 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8619 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8620 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8621 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8622 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8623 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8624 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8625 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8626 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8627 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8628 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8629 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8630 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8631 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8632 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8633 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8634 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8635 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8636 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8637 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8638 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8639 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8640 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8641 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8642 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8643 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8644 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8645 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8646 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8647 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8648 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8649 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8650 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8651 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8652 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8653 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8654 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8655 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8656 def_builtin ("__builtin_read8", uw1_ftype_vptr, FRV_BUILTIN_READ8);
8657 def_builtin ("__builtin_read16", uw1_ftype_vptr, FRV_BUILTIN_READ16);
8658 def_builtin ("__builtin_read32", uw1_ftype_vptr, FRV_BUILTIN_READ32);
8659 def_builtin ("__builtin_read64", uw2_ftype_vptr, FRV_BUILTIN_READ64);
8661 def_builtin ("__builtin_write8", void_ftype_vptr_ub, FRV_BUILTIN_WRITE8);
8662 def_builtin ("__builtin_write16", void_ftype_vptr_uh, FRV_BUILTIN_WRITE16);
8663 def_builtin ("__builtin_write32", void_ftype_vptr_uw1, FRV_BUILTIN_WRITE32);
8664 def_builtin ("__builtin_write64", void_ftype_vptr_uw2, FRV_BUILTIN_WRITE64);
8672 /* Set the names for various arithmetic operations according to the
8675 frv_init_libfuncs (void)
8677 set_optab_libfunc (smod_optab, SImode, "__modi");
8678 set_optab_libfunc (umod_optab, SImode, "__umodi");
8680 set_optab_libfunc (add_optab, DImode, "__addll");
8681 set_optab_libfunc (sub_optab, DImode, "__subll");
8682 set_optab_libfunc (smul_optab, DImode, "__mulll");
8683 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8684 set_optab_libfunc (smod_optab, DImode, "__modll");
8685 set_optab_libfunc (umod_optab, DImode, "__umodll");
8686 set_optab_libfunc (and_optab, DImode, "__andll");
8687 set_optab_libfunc (ior_optab, DImode, "__orll");
8688 set_optab_libfunc (xor_optab, DImode, "__xorll");
8689 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8691 set_optab_libfunc (add_optab, SFmode, "__addf");
8692 set_optab_libfunc (sub_optab, SFmode, "__subf");
8693 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8694 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8696 set_optab_libfunc (add_optab, DFmode, "__addd");
8697 set_optab_libfunc (sub_optab, DFmode, "__subd");
8698 set_optab_libfunc (smul_optab, DFmode, "__muld");
8699 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8701 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8702 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8704 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8705 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8706 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8707 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8709 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8710 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8711 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8712 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8714 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8715 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8716 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8717 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8720 /* Convert an integer constant to an accumulator register. ICODE is the
8721 code of the target instruction, OPNUM is the number of the
8722 accumulator operand and OPVAL is the constant integer. Try both
8723 ACC and ACCG registers; only report an error if neither fit the
8727 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8732 /* ACCs and ACCGs are implicit global registers if media intrinsics
8733 are being used. We set up this lazily to avoid creating lots of
8734 unnecessary call_insn rtl in non-media code. */
8735 for (i = 0; i <= ACC_MASK; i++)
8736 if ((i & ACC_MASK) == i)
8737 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8739 if (GET_CODE (opval) != CONST_INT)
8741 error ("accumulator is not a constant integer");
8744 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8746 error ("accumulator number is out of bounds");
8750 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8751 ACC_FIRST + INTVAL (opval));
8752 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8753 SET_REGNO (reg, ACCG_FIRST + INTVAL (opval));
8755 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8757 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8763 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8766 static enum machine_mode
8767 frv_matching_accg_mode (enum machine_mode mode)
8785 /* Given that a __builtin_read or __builtin_write function is accessing
8786 address ADDRESS, return the value that should be used as operand 1
8790 frv_io_address_cookie (rtx address)
8792 return (GET_CODE (address) == CONST_INT
8793 ? GEN_INT (INTVAL (address) / 8 * 8)
8797 /* Return the accumulator guard that should be paired with accumulator
8798 register ACC. The mode of the returned register is in the same
8799 class as ACC, but is four times smaller. */
8802 frv_matching_accg_for_acc (rtx acc)
8804 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8805 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8808 /* Read the requested argument from the call EXP given by INDEX.
8809 Return the value as an rtx. */
8812 frv_read_argument (tree exp, unsigned int index)
8814 return expand_expr (CALL_EXPR_ARG (exp, index),
8815 NULL_RTX, VOIDmode, 0);
8818 /* Like frv_read_argument, but interpret the argument as the number
8819 of an IACC register and return a (reg:MODE ...) rtx for it. */
8822 frv_read_iacc_argument (enum machine_mode mode, tree call,
8828 op = frv_read_argument (call, index);
8829 if (GET_CODE (op) != CONST_INT
8831 || INTVAL (op) > IACC_LAST - IACC_FIRST
8832 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8834 error ("invalid IACC argument");
8838 /* IACCs are implicit global registers. We set up this lazily to
8839 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8841 regno = INTVAL (op) + IACC_FIRST;
8842 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8843 global_regs[regno + i] = 1;
8845 return gen_rtx_REG (mode, regno);
8848 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8849 The instruction should require a constant operand of some sort. The
8850 function prints an error if OPVAL is not valid. */
8853 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8855 if (GET_CODE (opval) != CONST_INT)
8857 error ("%qs expects a constant argument", insn_data[icode].name);
8860 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8862 error ("constant argument out of range for %qs", insn_data[icode].name);
8868 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8869 if it's not null, has the right mode, and satisfies operand 0's
8873 frv_legitimize_target (enum insn_code icode, rtx target)
8875 enum machine_mode mode = insn_data[icode].operand[0].mode;
8878 || GET_MODE (target) != mode
8879 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8880 return gen_reg_rtx (mode);
8885 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8886 check whether ARG satisfies the operand's constraints. If it doesn't,
8887 copy ARG to a temporary register and return that. Otherwise return ARG
8891 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8893 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8895 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8898 return copy_to_mode_reg (mode, arg);
8901 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8904 frv_volatile_memref (enum machine_mode mode, rtx arg)
8908 mem = gen_rtx_MEM (mode, memory_address (mode, arg));
8909 MEM_VOLATILE_P (mem) = 1;
8913 /* Expand builtins that take a single, constant argument. At the moment,
8914 only MHDSETS falls into this category. */
8917 frv_expand_set_builtin (enum insn_code icode, tree call, rtx target)
8920 rtx op0 = frv_read_argument (call, 0);
8922 if (! frv_check_constant_argument (icode, 1, op0))
8925 target = frv_legitimize_target (icode, target);
8926 pat = GEN_FCN (icode) (target, op0);
8934 /* Expand builtins that take one operand. */
8937 frv_expand_unop_builtin (enum insn_code icode, tree call, rtx target)
8940 rtx op0 = frv_read_argument (call, 0);
8942 target = frv_legitimize_target (icode, target);
8943 op0 = frv_legitimize_argument (icode, 1, op0);
8944 pat = GEN_FCN (icode) (target, op0);
8952 /* Expand builtins that take two operands. */
8955 frv_expand_binop_builtin (enum insn_code icode, tree call, rtx target)
8958 rtx op0 = frv_read_argument (call, 0);
8959 rtx op1 = frv_read_argument (call, 1);
8961 target = frv_legitimize_target (icode, target);
8962 op0 = frv_legitimize_argument (icode, 1, op0);
8963 op1 = frv_legitimize_argument (icode, 2, op1);
8964 pat = GEN_FCN (icode) (target, op0, op1);
8972 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8976 frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
8979 rtx op0 = frv_read_argument (call, 0);
8980 rtx op1 = frv_read_argument (call, 1);
8983 target = frv_legitimize_target (icode, target);
8984 op0 = frv_int_to_acc (icode, 1, op0);
8988 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8990 if (! frv_check_constant_argument (icode, 2, op1))
8994 op1 = frv_legitimize_argument (icode, 2, op1);
8996 op2 = frv_matching_accg_for_acc (op0);
8997 pat = GEN_FCN (icode) (target, op0, op1, op2);
9005 /* Expand builtins that take two operands and the second is immediate. */
9008 frv_expand_binopimm_builtin (enum insn_code icode, tree call, rtx target)
9011 rtx op0 = frv_read_argument (call, 0);
9012 rtx op1 = frv_read_argument (call, 1);
9014 if (! frv_check_constant_argument (icode, 2, op1))
9017 target = frv_legitimize_target (icode, target);
9018 op0 = frv_legitimize_argument (icode, 1, op0);
9019 pat = GEN_FCN (icode) (target, op0, op1);
9027 /* Expand builtins that take two operands, the first operand being a pointer to
9028 ints and return void. */
9031 frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
9034 rtx op0 = frv_read_argument (call, 0);
9035 rtx op1 = frv_read_argument (call, 1);
9036 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
9039 if (GET_CODE (op0) != MEM)
9043 if (! offsettable_address_p (0, mode0, op0))
9045 reg = gen_reg_rtx (Pmode);
9046 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
9049 op0 = gen_rtx_MEM (SImode, reg);
9052 addr = XEXP (op0, 0);
9053 if (! offsettable_address_p (0, mode0, addr))
9054 addr = copy_to_mode_reg (Pmode, op0);
9056 op0 = change_address (op0, V4SImode, addr);
9057 op1 = frv_legitimize_argument (icode, 1, op1);
9058 pat = GEN_FCN (icode) (op0, op1);
9066 /* Expand builtins that take two long operands and return void. */
9069 frv_expand_int_void2arg (enum insn_code icode, tree call)
9072 rtx op0 = frv_read_argument (call, 0);
9073 rtx op1 = frv_read_argument (call, 1);
9075 op0 = frv_legitimize_argument (icode, 1, op0);
9076 op1 = frv_legitimize_argument (icode, 1, op1);
9077 pat = GEN_FCN (icode) (op0, op1);
9085 /* Expand prefetch builtins. These take a single address as argument. */
9088 frv_expand_prefetches (enum insn_code icode, tree call)
9091 rtx op0 = frv_read_argument (call, 0);
9093 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
9101 /* Expand builtins that take three operands and return void. The first
9102 argument must be a constant that describes a pair or quad accumulators. A
9103 fourth argument is created that is the accumulator guard register that
9104 corresponds to the accumulator. */
9107 frv_expand_voidtriop_builtin (enum insn_code icode, tree call)
9110 rtx op0 = frv_read_argument (call, 0);
9111 rtx op1 = frv_read_argument (call, 1);
9112 rtx op2 = frv_read_argument (call, 2);
9115 op0 = frv_int_to_acc (icode, 0, op0);
9119 op1 = frv_legitimize_argument (icode, 1, op1);
9120 op2 = frv_legitimize_argument (icode, 2, op2);
9121 op3 = frv_matching_accg_for_acc (op0);
9122 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9130 /* Expand builtins that perform accumulator-to-accumulator operations.
9131 These builtins take two accumulator numbers as argument and return
9135 frv_expand_voidaccop_builtin (enum insn_code icode, tree call)
9138 rtx op0 = frv_read_argument (call, 0);
9139 rtx op1 = frv_read_argument (call, 1);
9143 op0 = frv_int_to_acc (icode, 0, op0);
9147 op1 = frv_int_to_acc (icode, 1, op1);
9151 op2 = frv_matching_accg_for_acc (op0);
9152 op3 = frv_matching_accg_for_acc (op1);
9153 pat = GEN_FCN (icode) (op0, op1, op2, op3);
9161 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9162 membar and TARGET_MODE is the mode that the loaded value should have. */
9165 frv_expand_load_builtin (enum insn_code icode, enum machine_mode target_mode,
9166 tree call, rtx target)
9168 rtx op0 = frv_read_argument (call, 0);
9169 rtx cookie = frv_io_address_cookie (op0);
9171 if (target == 0 || !REG_P (target))
9172 target = gen_reg_rtx (target_mode);
9173 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9174 convert_move (target, op0, 1);
9175 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_READ)));
9176 cfun->machine->has_membar_p = 1;
9180 /* Likewise __builtin_write* functions. */
9183 frv_expand_store_builtin (enum insn_code icode, tree call)
9185 rtx op0 = frv_read_argument (call, 0);
9186 rtx op1 = frv_read_argument (call, 1);
9187 rtx cookie = frv_io_address_cookie (op0);
9189 op0 = frv_volatile_memref (insn_data[icode].operand[0].mode, op0);
9190 convert_move (op0, force_reg (insn_data[icode].operand[0].mode, op1), 1);
9191 emit_insn (GEN_FCN (icode) (copy_rtx (op0), cookie, GEN_INT (FRV_IO_WRITE)));
9192 cfun->machine->has_membar_p = 1;
9196 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9197 each argument forms one word of the two double-word input registers.
9198 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9199 to put the return value. */
9202 frv_expand_mdpackh_builtin (tree call, rtx target)
9204 enum insn_code icode = CODE_FOR_mdpackh;
9206 rtx arg1 = frv_read_argument (call, 0);
9207 rtx arg2 = frv_read_argument (call, 1);
9208 rtx arg3 = frv_read_argument (call, 2);
9209 rtx arg4 = frv_read_argument (call, 3);
9211 target = frv_legitimize_target (icode, target);
9212 op0 = gen_reg_rtx (DImode);
9213 op1 = gen_reg_rtx (DImode);
9215 /* The high half of each word is not explicitly initialized, so indicate
9216 that the input operands are not live before this point. */
9220 /* Move each argument into the low half of its associated input word. */
9221 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
9222 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
9223 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
9224 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
9226 pat = GEN_FCN (icode) (target, op0, op1);
9234 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9235 number as argument. */
9238 frv_expand_mclracc_builtin (tree call)
9240 enum insn_code icode = CODE_FOR_mclracc;
9242 rtx op0 = frv_read_argument (call, 0);
9244 op0 = frv_int_to_acc (icode, 0, op0);
9248 pat = GEN_FCN (icode) (op0);
9255 /* Expand builtins that take no arguments. */
9258 frv_expand_noargs_builtin (enum insn_code icode)
9260 rtx pat = GEN_FCN (icode) (const0_rtx);
9267 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9268 number or accumulator guard number as argument and return an SI integer. */
9271 frv_expand_mrdacc_builtin (enum insn_code icode, tree call)
9274 rtx target = gen_reg_rtx (SImode);
9275 rtx op0 = frv_read_argument (call, 0);
9277 op0 = frv_int_to_acc (icode, 1, op0);
9281 pat = GEN_FCN (icode) (target, op0);
9289 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9290 accumulator guard as their first argument and an SImode value as their
9294 frv_expand_mwtacc_builtin (enum insn_code icode, tree call)
9297 rtx op0 = frv_read_argument (call, 0);
9298 rtx op1 = frv_read_argument (call, 1);
9300 op0 = frv_int_to_acc (icode, 0, op0);
9304 op1 = frv_legitimize_argument (icode, 1, op1);
9305 pat = GEN_FCN (icode) (op0, op1);
9312 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9313 to move DImode values into and out of IACC0. */
9316 frv_split_iacc_move (rtx dest, rtx src)
9318 enum machine_mode inner;
9321 inner = GET_MODE (dest);
9322 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
9323 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
9324 simplify_gen_subreg (SImode, src, inner, i));
9327 /* Expand builtins. */
9330 frv_expand_builtin (tree exp,
9332 rtx subtarget ATTRIBUTE_UNUSED,
9333 enum machine_mode mode ATTRIBUTE_UNUSED,
9334 int ignore ATTRIBUTE_UNUSED)
9336 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9337 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
9339 struct builtin_description *d;
9341 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
9343 error ("media functions are not available unless -mmedia is used");
9349 case FRV_BUILTIN_MCOP1:
9350 case FRV_BUILTIN_MCOP2:
9351 case FRV_BUILTIN_MDUNPACKH:
9352 case FRV_BUILTIN_MBTOHE:
9353 if (! TARGET_MEDIA_REV1)
9355 error ("this media function is only available on the fr500");
9360 case FRV_BUILTIN_MQXMACHS:
9361 case FRV_BUILTIN_MQXMACXHS:
9362 case FRV_BUILTIN_MQMACXHS:
9363 case FRV_BUILTIN_MADDACCS:
9364 case FRV_BUILTIN_MSUBACCS:
9365 case FRV_BUILTIN_MASACCS:
9366 case FRV_BUILTIN_MDADDACCS:
9367 case FRV_BUILTIN_MDSUBACCS:
9368 case FRV_BUILTIN_MDASACCS:
9369 case FRV_BUILTIN_MABSHS:
9370 case FRV_BUILTIN_MDROTLI:
9371 case FRV_BUILTIN_MCPLHI:
9372 case FRV_BUILTIN_MCPLI:
9373 case FRV_BUILTIN_MDCUTSSI:
9374 case FRV_BUILTIN_MQSATHS:
9375 case FRV_BUILTIN_MHSETLOS:
9376 case FRV_BUILTIN_MHSETLOH:
9377 case FRV_BUILTIN_MHSETHIS:
9378 case FRV_BUILTIN_MHSETHIH:
9379 case FRV_BUILTIN_MHDSETS:
9380 case FRV_BUILTIN_MHDSETH:
9381 if (! TARGET_MEDIA_REV2)
9383 error ("this media function is only available on the fr400"
9389 case FRV_BUILTIN_SMASS:
9390 case FRV_BUILTIN_SMSSS:
9391 case FRV_BUILTIN_SMU:
9392 case FRV_BUILTIN_ADDSS:
9393 case FRV_BUILTIN_SUBSS:
9394 case FRV_BUILTIN_SLASS:
9395 case FRV_BUILTIN_SCUTSS:
9396 case FRV_BUILTIN_IACCreadll:
9397 case FRV_BUILTIN_IACCreadl:
9398 case FRV_BUILTIN_IACCsetll:
9399 case FRV_BUILTIN_IACCsetl:
9400 if (!TARGET_FR405_BUILTINS)
9402 error ("this builtin function is only available"
9403 " on the fr405 and fr450");
9408 case FRV_BUILTIN_PREFETCH:
9409 if (!TARGET_FR500_FR550_BUILTINS)
9411 error ("this builtin function is only available on the fr500"
9417 case FRV_BUILTIN_MQLCLRHS:
9418 case FRV_BUILTIN_MQLMTHS:
9419 case FRV_BUILTIN_MQSLLHI:
9420 case FRV_BUILTIN_MQSRAHI:
9421 if (!TARGET_MEDIA_FR450)
9423 error ("this builtin function is only available on the fr450");
9432 /* Expand unique builtins. */
9436 case FRV_BUILTIN_MTRAP:
9437 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
9439 case FRV_BUILTIN_MCLRACC:
9440 return frv_expand_mclracc_builtin (exp);
9442 case FRV_BUILTIN_MCLRACCA:
9444 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
9446 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
9448 case FRV_BUILTIN_MRDACC:
9449 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, exp);
9451 case FRV_BUILTIN_MRDACCG:
9452 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, exp);
9454 case FRV_BUILTIN_MWTACC:
9455 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, exp);
9457 case FRV_BUILTIN_MWTACCG:
9458 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, exp);
9460 case FRV_BUILTIN_MDPACKH:
9461 return frv_expand_mdpackh_builtin (exp, target);
9463 case FRV_BUILTIN_IACCreadll:
9465 rtx src = frv_read_iacc_argument (DImode, exp, 0);
9466 if (target == 0 || !REG_P (target))
9467 target = gen_reg_rtx (DImode);
9468 frv_split_iacc_move (target, src);
9472 case FRV_BUILTIN_IACCreadl:
9473 return frv_read_iacc_argument (SImode, exp, 0);
9475 case FRV_BUILTIN_IACCsetll:
9477 rtx dest = frv_read_iacc_argument (DImode, exp, 0);
9478 rtx src = frv_read_argument (exp, 1);
9479 frv_split_iacc_move (dest, force_reg (DImode, src));
9483 case FRV_BUILTIN_IACCsetl:
9485 rtx dest = frv_read_iacc_argument (SImode, exp, 0);
9486 rtx src = frv_read_argument (exp, 1);
9487 emit_move_insn (dest, force_reg (SImode, src));
9495 /* Expand groups of builtins. */
9497 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
9498 if (d->code == fcode)
9499 return frv_expand_set_builtin (d->icode, exp, target);
9501 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9502 if (d->code == fcode)
9503 return frv_expand_unop_builtin (d->icode, exp, target);
9505 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9506 if (d->code == fcode)
9507 return frv_expand_binop_builtin (d->icode, exp, target);
9509 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
9510 if (d->code == fcode)
9511 return frv_expand_cut_builtin (d->icode, exp, target);
9513 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
9514 if (d->code == fcode)
9515 return frv_expand_binopimm_builtin (d->icode, exp, target);
9517 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
9518 if (d->code == fcode)
9519 return frv_expand_voidbinop_builtin (d->icode, exp);
9521 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
9522 if (d->code == fcode)
9523 return frv_expand_voidtriop_builtin (d->icode, exp);
9525 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
9526 if (d->code == fcode)
9527 return frv_expand_voidaccop_builtin (d->icode, exp);
9529 for (i = 0, d = bdesc_int_void2arg;
9530 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
9531 if (d->code == fcode)
9532 return frv_expand_int_void2arg (d->icode, exp);
9534 for (i = 0, d = bdesc_prefetches;
9535 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
9536 if (d->code == fcode)
9537 return frv_expand_prefetches (d->icode, exp);
9539 for (i = 0, d = bdesc_loads; i < ARRAY_SIZE (bdesc_loads); i++, d++)
9540 if (d->code == fcode)
9541 return frv_expand_load_builtin (d->icode, TYPE_MODE (TREE_TYPE (exp)),
9544 for (i = 0, d = bdesc_stores; i < ARRAY_SIZE (bdesc_stores); i++, d++)
9545 if (d->code == fcode)
9546 return frv_expand_store_builtin (d->icode, exp);
9552 frv_in_small_data_p (const_tree decl)
9555 const_tree section_name;
9557 /* Don't apply the -G flag to internal compiler structures. We
9558 should leave such structures in the main data section, partly
9559 for efficiency and partly because the size of some of them
9560 (such as C++ typeinfos) is not known until later. */
9561 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
9564 /* If we already know which section the decl should be in, see if
9565 it's a small data section. */
9566 section_name = DECL_SECTION_NAME (decl);
9569 gcc_assert (TREE_CODE (section_name) == STRING_CST);
9570 if (frv_string_begins_with (section_name, ".sdata"))
9572 if (frv_string_begins_with (section_name, ".sbss"))
9577 size = int_size_in_bytes (TREE_TYPE (decl));
9578 if (size > 0 && size <= g_switch_value)
9585 frv_rtx_costs (rtx x,
9586 int code ATTRIBUTE_UNUSED,
9587 int outer_code ATTRIBUTE_UNUSED,
9589 bool speed ATTRIBUTE_UNUSED)
9591 if (outer_code == MEM)
9593 /* Don't differentiate between memory addresses. All the ones
9594 we accept have equal cost. */
9595 *total = COSTS_N_INSNS (0);
9602 /* Make 12-bit integers really cheap. */
9603 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9614 *total = COSTS_N_INSNS (2);
9628 if (GET_MODE (x) == SImode)
9629 *total = COSTS_N_INSNS (1);
9630 else if (GET_MODE (x) == DImode)
9631 *total = COSTS_N_INSNS (2);
9633 *total = COSTS_N_INSNS (3);
9637 if (GET_MODE (x) == SImode)
9638 *total = COSTS_N_INSNS (2);
9640 *total = COSTS_N_INSNS (6); /* guess */
9647 *total = COSTS_N_INSNS (18);
9651 *total = COSTS_N_INSNS (3);
9660 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9662 switch_to_section (ctors_section);
9663 assemble_align (POINTER_SIZE);
9666 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9671 assemble_integer_with_op ("\t.picptr\t", symbol);
9675 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9677 switch_to_section (dtors_section);
9678 assemble_align (POINTER_SIZE);
9681 int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
9686 assemble_integer_with_op ("\t.picptr\t", symbol);
9689 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9692 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9693 int incoming ATTRIBUTE_UNUSED)
9695 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9698 #define TLS_BIAS (2048 - 16)
9700 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9701 We need to emit DTP-relative relocations. */
9704 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9706 gcc_assert (size == 4);
9707 fputs ("\t.picptr\ttlsmoff(", file);
9708 /* We want the unbiased TLS offset, so add the bias to the
9709 expression, such that the implicit biasing cancels out. */
9710 output_addr_const (file, plus_constant (x, TLS_BIAS));