1 /* Copyright (C) 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005
2 Free Software Foundation, Inc.
3 Contributed by Red Hat, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
45 #include "basic-block.h"
50 #include "target-def.h"
51 #include "targhooks.h"
52 #include "integrate.h"
53 #include "langhooks.h"
56 #define FRV_INLINE inline
59 /* The maximum number of distinct NOP patterns. There are three:
60 nop, fnop and mnop. */
61 #define NUM_NOP_PATTERNS 3
63 /* Classification of instructions and units: integer, floating-point/media,
64 branch and control. */
65 enum frv_insn_group { GROUP_I, GROUP_FM, GROUP_B, GROUP_C, NUM_GROUPS };
67 /* The DFA names of the units, in packet order. */
68 static const char *const frv_unit_names[] =
78 /* The classification of each unit in frv_unit_names[]. */
79 static const enum frv_insn_group frv_unit_groups[ARRAY_SIZE (frv_unit_names)] =
89 /* Return the DFA unit code associated with the Nth unit of integer
90 or floating-point group GROUP, */
91 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
93 /* Return the number of integer or floating-point unit UNIT
94 (1 for I1, 2 for F2, etc.). */
95 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
97 /* The DFA unit number for each unit in frv_unit_names[]. */
98 static int frv_unit_codes[ARRAY_SIZE (frv_unit_names)];
100 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
101 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
102 no instruction of type T has been seen. */
103 static unsigned int frv_type_to_unit[TYPE_UNKNOWN + 1];
105 /* An array of dummy nop INSNs, one for each type of nop that the
107 static GTY(()) rtx frv_nops[NUM_NOP_PATTERNS];
109 /* The number of nop instructions in frv_nops[]. */
110 static unsigned int frv_num_nops;
112 /* Return true if instruction INSN should be packed with the following
114 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
116 /* Set the value of PACKING_FLAG_P(INSN). */
117 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
118 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
120 /* Loop with REG set to each hard register in rtx X. */
121 #define FOR_EACH_REGNO(REG, X) \
122 for (REG = REGNO (X); \
123 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
126 /* Temporary register allocation support structure. */
127 typedef struct frv_tmp_reg_struct
129 HARD_REG_SET regs; /* possible registers to allocate */
130 int next_reg[N_REG_CLASSES]; /* next register to allocate per class */
134 /* Register state information for VLIW re-packing phase. */
135 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
136 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
137 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
138 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
140 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
142 typedef unsigned char regstate_t;
144 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
152 /* Information required by frv_frame_access. */
155 /* This field is FRV_LOAD if registers are to be loaded from the stack and
156 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
157 the move is being done by the prologue code while FRV_LOAD implies it
158 is being done by the epilogue. */
159 enum frv_stack_op op;
161 /* The base register to use when accessing the stack. This may be the
162 frame pointer, stack pointer, or a temporary. The choice of register
163 depends on which part of the frame is being accessed and how big the
167 /* The offset of BASE from the bottom of the current frame, in bytes. */
169 } frv_frame_accessor_t;
171 /* Define the information needed to generate branch and scc insns. This is
172 stored from the compare operation. */
176 /* Conditional execution support gathered together in one structure. */
179 /* Linked list of insns to add if the conditional execution conversion was
180 successful. Each link points to an EXPR_LIST which points to the pattern
181 of the insn to add, and the insn to be inserted before. */
182 rtx added_insns_list;
184 /* Identify which registers are safe to allocate for if conversions to
185 conditional execution. We keep the last allocated register in the
186 register classes between COND_EXEC statements. This will mean we allocate
187 different registers for each different COND_EXEC group if we can. This
188 might allow the scheduler to intermix two different COND_EXEC sections. */
189 frv_tmp_reg_t tmp_reg;
191 /* For nested IFs, identify which CC registers are used outside of setting
192 via a compare isnsn, and using via a check insn. This will allow us to
193 know if we can rewrite the register to use a different register that will
194 be paired with the CR register controlling the nested IF-THEN blocks. */
195 HARD_REG_SET nested_cc_ok_rewrite;
197 /* Temporary registers allocated to hold constants during conditional
199 rtx scratch_regs[FIRST_PSEUDO_REGISTER];
201 /* Current number of temp registers available. */
202 int cur_scratch_regs;
204 /* Number of nested conditional execution blocks. */
205 int num_nested_cond_exec;
207 /* Map of insns that set up constants in scratch registers. */
208 bitmap scratch_insns_bitmap;
210 /* Conditional execution test register (CC0..CC7). */
213 /* Conditional execution compare register that is paired with cr_reg, so that
214 nested compares can be done. The csubcc and caddcc instructions don't
215 have enough bits to specify both a CC register to be set and a CR register
216 to do the test on, so the same bit number is used for both. Needless to
217 say, this is rather inconvenient for GCC. */
220 /* Extra CR registers used for &&, ||. */
224 /* Previous CR used in nested if, to make sure we are dealing with the same
225 nested if as the previous statement. */
226 rtx last_nested_if_cr;
230 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt;
232 /* Map register number to smallest register class. */
233 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
235 /* Map class letter into register class. */
236 enum reg_class reg_class_from_letter[256];
238 /* Cached value of frv_stack_info. */
239 static frv_stack_t *frv_stack_cache = (frv_stack_t *)0;
242 frv_cpu_t frv_cpu_type = CPU_TYPE; /* value of -mcpu= */
244 /* Forward references */
246 static bool frv_handle_option (size_t, const char *, int);
247 static int frv_default_flags_for_cpu (void);
248 static int frv_string_begins_with (tree, const char *);
249 static FRV_INLINE bool frv_small_data_reloc_p (rtx, int);
250 static void frv_print_operand_memory_reference_reg
252 static void frv_print_operand_memory_reference (FILE *, rtx, int);
253 static int frv_print_operand_jump_hint (rtx);
254 static const char *comparison_string (enum rtx_code, rtx);
255 static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
256 static rtx single_set_pattern (rtx);
257 static int frv_function_contains_far_jump (void);
258 static rtx frv_alloc_temp_reg (frv_tmp_reg_t *,
262 static rtx frv_frame_offset_rtx (int);
263 static rtx frv_frame_mem (enum machine_mode, rtx, int);
264 static rtx frv_dwarf_store (rtx, int);
265 static void frv_frame_insn (rtx, rtx);
266 static void frv_frame_access (frv_frame_accessor_t*,
268 static void frv_frame_access_multi (frv_frame_accessor_t*,
270 static void frv_frame_access_standard_regs (enum frv_stack_op,
272 static struct machine_function *frv_init_machine_status (void);
273 static rtx frv_int_to_acc (enum insn_code, int, rtx);
274 static enum machine_mode frv_matching_accg_mode (enum machine_mode);
275 static rtx frv_read_argument (tree *);
276 static rtx frv_read_iacc_argument (enum machine_mode, tree *);
277 static int frv_check_constant_argument (enum insn_code, int, rtx);
278 static rtx frv_legitimize_target (enum insn_code, rtx);
279 static rtx frv_legitimize_argument (enum insn_code, int, rtx);
280 static rtx frv_legitimize_tls_address (rtx, enum tls_model);
281 static rtx frv_expand_set_builtin (enum insn_code, tree, rtx);
282 static rtx frv_expand_unop_builtin (enum insn_code, tree, rtx);
283 static rtx frv_expand_binop_builtin (enum insn_code, tree, rtx);
284 static rtx frv_expand_cut_builtin (enum insn_code, tree, rtx);
285 static rtx frv_expand_binopimm_builtin (enum insn_code, tree, rtx);
286 static rtx frv_expand_voidbinop_builtin (enum insn_code, tree);
287 static rtx frv_expand_int_void2arg (enum insn_code, tree);
288 static rtx frv_expand_prefetches (enum insn_code, tree);
289 static rtx frv_expand_voidtriop_builtin (enum insn_code, tree);
290 static rtx frv_expand_voidaccop_builtin (enum insn_code, tree);
291 static rtx frv_expand_mclracc_builtin (tree);
292 static rtx frv_expand_mrdacc_builtin (enum insn_code, tree);
293 static rtx frv_expand_mwtacc_builtin (enum insn_code, tree);
294 static rtx frv_expand_noargs_builtin (enum insn_code);
295 static void frv_split_iacc_move (rtx, rtx);
296 static rtx frv_emit_comparison (enum rtx_code, rtx, rtx);
297 static int frv_clear_registers_used (rtx *, void *);
298 static void frv_ifcvt_add_insn (rtx, rtx, int);
299 static rtx frv_ifcvt_rewrite_mem (rtx, enum machine_mode, rtx);
300 static rtx frv_ifcvt_load_value (rtx, rtx);
301 static int frv_acc_group_1 (rtx *, void *);
302 static unsigned int frv_insn_unit (rtx);
303 static bool frv_issues_to_branch_unit_p (rtx);
304 static int frv_cond_flags (rtx);
305 static bool frv_regstate_conflict_p (regstate_t, regstate_t);
306 static int frv_registers_conflict_p_1 (rtx *, void *);
307 static bool frv_registers_conflict_p (rtx);
308 static void frv_registers_update_1 (rtx, rtx, void *);
309 static void frv_registers_update (rtx);
310 static void frv_start_packet (void);
311 static void frv_start_packet_block (void);
312 static void frv_finish_packet (void (*) (void));
313 static bool frv_pack_insn_p (rtx);
314 static void frv_add_insn_to_packet (rtx);
315 static void frv_insert_nop_in_packet (rtx);
316 static bool frv_for_each_packet (void (*) (void));
317 static bool frv_sort_insn_group_1 (enum frv_insn_group,
318 unsigned int, unsigned int,
319 unsigned int, unsigned int,
321 static int frv_compare_insns (const void *, const void *);
322 static void frv_sort_insn_group (enum frv_insn_group);
323 static void frv_reorder_packet (void);
324 static void frv_fill_unused_units (enum frv_insn_group);
325 static void frv_align_label (void);
326 static void frv_reorg_packet (void);
327 static void frv_register_nop (rtx);
328 static void frv_reorg (void);
329 static void frv_pack_insns (void);
330 static void frv_function_prologue (FILE *, HOST_WIDE_INT);
331 static void frv_function_epilogue (FILE *, HOST_WIDE_INT);
332 static bool frv_assemble_integer (rtx, unsigned, int);
333 static void frv_init_builtins (void);
334 static rtx frv_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
335 static void frv_init_libfuncs (void);
336 static bool frv_in_small_data_p (tree);
337 static void frv_asm_output_mi_thunk
338 (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
339 static void frv_setup_incoming_varargs (CUMULATIVE_ARGS *,
342 static rtx frv_expand_builtin_saveregs (void);
343 static bool frv_rtx_costs (rtx, int, int, int*);
344 static void frv_asm_out_constructor (rtx, int);
345 static void frv_asm_out_destructor (rtx, int);
346 static bool frv_function_symbol_referenced_p (rtx);
347 static bool frv_cannot_force_const_mem (rtx);
348 static const char *unspec_got_name (int);
349 static void frv_output_const_unspec (FILE *,
350 const struct frv_unspec *);
351 static bool frv_function_ok_for_sibcall (tree, tree);
352 static rtx frv_struct_value_rtx (tree, int);
353 static bool frv_must_pass_in_stack (enum machine_mode mode, tree type);
354 static int frv_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
357 /* Allow us to easily change the default for -malloc-cc. */
358 #ifndef DEFAULT_NO_ALLOC_CC
359 #define MASK_DEFAULT_ALLOC_CC MASK_ALLOC_CC
361 #define MASK_DEFAULT_ALLOC_CC 0
364 /* Initialize the GCC target structure. */
365 #undef TARGET_ASM_FUNCTION_PROLOGUE
366 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
367 #undef TARGET_ASM_FUNCTION_EPILOGUE
368 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
369 #undef TARGET_ASM_INTEGER
370 #define TARGET_ASM_INTEGER frv_assemble_integer
371 #undef TARGET_DEFAULT_TARGET_FLAGS
372 #define TARGET_DEFAULT_TARGET_FLAGS \
373 (MASK_DEFAULT_ALLOC_CC \
380 #undef TARGET_HANDLE_OPTION
381 #define TARGET_HANDLE_OPTION frv_handle_option
382 #undef TARGET_INIT_BUILTINS
383 #define TARGET_INIT_BUILTINS frv_init_builtins
384 #undef TARGET_EXPAND_BUILTIN
385 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
386 #undef TARGET_INIT_LIBFUNCS
387 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
388 #undef TARGET_IN_SMALL_DATA_P
389 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
390 #undef TARGET_RTX_COSTS
391 #define TARGET_RTX_COSTS frv_rtx_costs
392 #undef TARGET_ASM_CONSTRUCTOR
393 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
394 #undef TARGET_ASM_DESTRUCTOR
395 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
397 #undef TARGET_ASM_OUTPUT_MI_THUNK
398 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
399 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
400 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
402 #undef TARGET_SCHED_ISSUE_RATE
403 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
405 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
406 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
407 #undef TARGET_CANNOT_FORCE_CONST_MEM
408 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
410 #undef TARGET_HAVE_TLS
411 #define TARGET_HAVE_TLS HAVE_AS_TLS
413 #undef TARGET_STRUCT_VALUE_RTX
414 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
415 #undef TARGET_MUST_PASS_IN_STACK
416 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
417 #undef TARGET_PASS_BY_REFERENCE
418 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
419 #undef TARGET_ARG_PARTIAL_BYTES
420 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
422 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
423 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
424 #undef TARGET_SETUP_INCOMING_VARARGS
425 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
426 #undef TARGET_MACHINE_DEPENDENT_REORG
427 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
429 struct gcc_target targetm = TARGET_INITIALIZER;
431 #define FRV_SYMBOL_REF_TLS_P(RTX) \
432 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
435 /* Any function call that satisfies the machine-independent
436 requirements is eligible on FR-V. */
439 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
440 tree exp ATTRIBUTE_UNUSED)
445 /* Return true if SYMBOL is a small data symbol and relocation RELOC
446 can be used to access it directly in a load or store. */
448 static FRV_INLINE bool
449 frv_small_data_reloc_p (rtx symbol, int reloc)
451 return (GET_CODE (symbol) == SYMBOL_REF
452 && SYMBOL_REF_SMALL_P (symbol)
453 && (!TARGET_FDPIC || flag_pic == 1)
454 && (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
457 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
461 frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
463 if (GET_CODE (x) == CONST)
467 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
469 unspec->offset += INTVAL (XEXP (x, 1));
472 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOT)
474 unspec->symbol = XVECEXP (x, 0, 0);
475 unspec->reloc = INTVAL (XVECEXP (x, 0, 1));
477 if (unspec->offset == 0)
480 if (frv_small_data_reloc_p (unspec->symbol, unspec->reloc)
481 && unspec->offset > 0
482 && (unsigned HOST_WIDE_INT) unspec->offset < g_switch_value)
489 /* Decide whether we can force certain constants to memory. If we
490 decide we can't, the caller should be able to cope with it in
493 We never allow constants to be forced into memory for TARGET_FDPIC.
494 This is necessary for several reasons:
496 1. Since LEGITIMATE_CONSTANT_P rejects constant pool addresses, the
497 target-independent code will try to force them into the constant
498 pool, thus leading to infinite recursion.
500 2. We can never introduce new constant pool references during reload.
501 Any such reference would require use of the pseudo FDPIC register.
503 3. We can't represent a constant added to a function pointer (which is
504 not the same as a pointer to a function+constant).
506 4. In many cases, it's more efficient to calculate the constant in-line. */
509 frv_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
514 /* Implement TARGET_HANDLE_OPTION. */
517 frv_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
522 if (strcmp (arg, "simple") == 0)
523 frv_cpu_type = FRV_CPU_SIMPLE;
524 else if (strcmp (arg, "tomcat") == 0)
525 frv_cpu_type = FRV_CPU_TOMCAT;
526 else if (strcmp (arg, "fr550") == 0)
527 frv_cpu_type = FRV_CPU_FR550;
528 else if (strcmp (arg, "fr500") == 0)
529 frv_cpu_type = FRV_CPU_FR500;
530 else if (strcmp (arg, "fr450") == 0)
531 frv_cpu_type = FRV_CPU_FR450;
532 else if (strcmp (arg, "fr405") == 0)
533 frv_cpu_type = FRV_CPU_FR405;
534 else if (strcmp (arg, "fr400") == 0)
535 frv_cpu_type = FRV_CPU_FR400;
536 else if (strcmp (arg, "fr300") == 0)
537 frv_cpu_type = FRV_CPU_FR300;
538 else if (strcmp (arg, "frv") == 0)
539 frv_cpu_type = FRV_CPU_GENERIC;
550 frv_default_flags_for_cpu (void)
552 switch (frv_cpu_type)
554 case FRV_CPU_GENERIC:
555 return MASK_DEFAULT_FRV;
558 return MASK_DEFAULT_FR550;
562 return MASK_DEFAULT_FR500;
565 return MASK_DEFAULT_FR450;
569 return MASK_DEFAULT_FR400;
573 return MASK_DEFAULT_SIMPLE;
578 /* Sometimes certain combinations of command options do not make
579 sense on a particular target machine. You can define a macro
580 `OVERRIDE_OPTIONS' to take account of this. This macro, if
581 defined, is executed once just after all the command options have
584 Don't use this macro to turn on various extra optimizations for
585 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
588 frv_override_options (void)
593 target_flags |= (frv_default_flags_for_cpu () & ~target_flags_explicit);
595 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
596 linker about linking pic and non-pic code. */
599 if (!flag_pic) /* -fPIC */
602 if (! g_switch_set) /* -G0 */
609 /* A C expression whose value is a register class containing hard
610 register REGNO. In general there is more than one such class;
611 choose a class which is "minimal", meaning that no smaller class
612 also contains the register. */
614 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
616 enum reg_class class;
620 int gpr_reg = regno - GPR_FIRST;
622 if (gpr_reg == GR8_REG)
625 else if (gpr_reg == GR9_REG)
628 else if (gpr_reg == GR14_REG)
629 class = FDPIC_FPTR_REGS;
631 else if (gpr_reg == FDPIC_REGNO)
634 else if ((gpr_reg & 3) == 0)
637 else if ((gpr_reg & 1) == 0)
644 else if (FPR_P (regno))
646 int fpr_reg = regno - GPR_FIRST;
647 if ((fpr_reg & 3) == 0)
648 class = QUAD_FPR_REGS;
650 else if ((fpr_reg & 1) == 0)
657 else if (regno == LR_REGNO)
660 else if (regno == LCR_REGNO)
663 else if (ICC_P (regno))
666 else if (FCC_P (regno))
669 else if (ICR_P (regno))
672 else if (FCR_P (regno))
675 else if (ACC_P (regno))
677 int r = regno - ACC_FIRST;
679 class = QUAD_ACC_REGS;
680 else if ((r & 1) == 0)
681 class = EVEN_ACC_REGS;
686 else if (ACCG_P (regno))
692 regno_reg_class[regno] = class;
695 /* Check for small data option */
697 g_switch_value = SDATA_DEFAULT_SIZE;
699 /* A C expression which defines the machine-dependent operand
700 constraint letters for register classes. If CHAR is such a
701 letter, the value should be the register class corresponding to
702 it. Otherwise, the value should be `NO_REGS'. The register
703 letter `r', corresponding to class `GENERAL_REGS', will not be
704 passed to this macro; you do not need to handle it.
706 The following letters are unavailable, due to being used as
711 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P'
712 'Q', 'R', 'S', 'T', 'U'
714 'g', 'i', 'm', 'n', 'o', 'p', 'r', 's' */
716 for (i = 0; i < 256; i++)
717 reg_class_from_letter[i] = NO_REGS;
719 reg_class_from_letter['a'] = ACC_REGS;
720 reg_class_from_letter['b'] = EVEN_ACC_REGS;
721 reg_class_from_letter['c'] = CC_REGS;
722 reg_class_from_letter['d'] = GPR_REGS;
723 reg_class_from_letter['e'] = EVEN_REGS;
724 reg_class_from_letter['f'] = FPR_REGS;
725 reg_class_from_letter['h'] = FEVEN_REGS;
726 reg_class_from_letter['l'] = LR_REG;
727 reg_class_from_letter['q'] = QUAD_REGS;
728 reg_class_from_letter['t'] = ICC_REGS;
729 reg_class_from_letter['u'] = FCC_REGS;
730 reg_class_from_letter['v'] = ICR_REGS;
731 reg_class_from_letter['w'] = FCR_REGS;
732 reg_class_from_letter['x'] = QUAD_FPR_REGS;
733 reg_class_from_letter['y'] = LCR_REG;
734 reg_class_from_letter['z'] = SPR_REGS;
735 reg_class_from_letter['A'] = QUAD_ACC_REGS;
736 reg_class_from_letter['B'] = ACCG_REGS;
737 reg_class_from_letter['C'] = CR_REGS;
738 reg_class_from_letter['W'] = FDPIC_CALL_REGS; /* gp14+15 */
739 reg_class_from_letter['Z'] = FDPIC_REGS; /* gp15 */
741 /* There is no single unaligned SI op for PIC code. Sometimes we
742 need to use ".4byte" and sometimes we need to use ".picptr".
743 See frv_assemble_integer for details. */
744 if (flag_pic || TARGET_FDPIC)
745 targetm.asm_out.unaligned_op.si = 0;
747 if ((target_flags_explicit & MASK_LINKED_FP) == 0)
748 target_flags |= MASK_LINKED_FP;
750 for (i = 0; i < ARRAY_SIZE (frv_unit_names); i++)
751 frv_unit_codes[i] = get_cpu_unit_code (frv_unit_names[i]);
753 for (i = 0; i < ARRAY_SIZE (frv_type_to_unit); i++)
754 frv_type_to_unit[i] = ARRAY_SIZE (frv_unit_codes);
756 init_machine_status = frv_init_machine_status;
760 /* Some machines may desire to change what optimizations are performed for
761 various optimization levels. This macro, if defined, is executed once just
762 after the optimization level is determined and before the remainder of the
763 command options have been parsed. Values set in this macro are used as the
764 default values for the other command line options.
766 LEVEL is the optimization level specified; 2 if `-O2' is specified, 1 if
767 `-O' is specified, and 0 if neither is specified.
769 SIZE is nonzero if `-Os' is specified, 0 otherwise.
771 You should not use this macro to change options that are not
772 machine-specific. These should uniformly selected by the same optimization
773 level on all supported machines. Use this macro to enable machine-specific
776 *Do not examine `write_symbols' in this macro!* The debugging options are
777 *not supposed to alter the generated code. */
779 /* On the FRV, possibly disable VLIW packing which is done by the 2nd
780 scheduling pass at the current time. */
782 frv_optimization_options (int level, int size ATTRIBUTE_UNUSED)
786 #ifdef DISABLE_SCHED2
787 flag_schedule_insns_after_reload = 0;
796 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
799 frv_string_begins_with (tree name, const char *prefix)
801 int prefix_len = strlen (prefix);
803 /* Remember: NAME's length includes the null terminator. */
804 return (TREE_STRING_LENGTH (name) > prefix_len
805 && strncmp (TREE_STRING_POINTER (name), prefix, prefix_len) == 0);
808 /* Zero or more C statements that may conditionally modify two variables
809 `fixed_regs' and `call_used_regs' (both of type `char []') after they have
810 been initialized from the two preceding macros.
812 This is necessary in case the fixed or call-clobbered registers depend on
815 You need not define this macro if it has no work to do.
817 If the usage of an entire class of registers depends on the target flags,
818 you may indicate this to GCC by using this macro to modify `fixed_regs' and
819 `call_used_regs' to 1 for each of the registers in the classes which should
820 not be used by GCC. Also define the macro `REG_CLASS_FROM_LETTER' to return
821 `NO_REGS' if it is called with a letter for a class that shouldn't be used.
823 (However, if this class is not included in `GENERAL_REGS' and all of the
824 insn patterns whose constraints permit this class are controlled by target
825 switches, then GCC will automatically avoid using these registers when the
826 target switches are opposed to them.) */
829 frv_conditional_register_usage (void)
833 for (i = GPR_FIRST + NUM_GPRS; i <= GPR_LAST; i++)
834 fixed_regs[i] = call_used_regs[i] = 1;
836 for (i = FPR_FIRST + NUM_FPRS; i <= FPR_LAST; i++)
837 fixed_regs[i] = call_used_regs[i] = 1;
839 /* Reserve the registers used for conditional execution. At present, we need
840 1 ICC and 1 ICR register. */
841 fixed_regs[ICC_TEMP] = call_used_regs[ICC_TEMP] = 1;
842 fixed_regs[ICR_TEMP] = call_used_regs[ICR_TEMP] = 1;
846 fixed_regs[ICC_FIRST] = call_used_regs[ICC_FIRST] = 1;
847 fixed_regs[FCC_FIRST] = call_used_regs[FCC_FIRST] = 1;
848 fixed_regs[ICR_FIRST] = call_used_regs[ICR_FIRST] = 1;
849 fixed_regs[FCR_FIRST] = call_used_regs[FCR_FIRST] = 1;
853 fixed_regs[GPR_FIRST + 16] = fixed_regs[GPR_FIRST + 17] =
854 call_used_regs[GPR_FIRST + 16] = call_used_regs[GPR_FIRST + 17] = 0;
857 /* If -fpic, SDA_BASE_REG is the PIC register. */
858 if (g_switch_value == 0 && !flag_pic)
859 fixed_regs[SDA_BASE_REG] = call_used_regs[SDA_BASE_REG] = 0;
862 fixed_regs[PIC_REGNO] = call_used_regs[PIC_REGNO] = 0;
868 * Compute the stack frame layout
871 * +---------------+-----------------------+-----------------------+
872 * |Register |type |caller-save/callee-save|
873 * +---------------+-----------------------+-----------------------+
874 * |GR0 |Zero register | - |
875 * |GR1 |Stack pointer(SP) | - |
876 * |GR2 |Frame pointer(FP) | - |
877 * |GR3 |Hidden parameter | caller save |
878 * |GR4-GR7 | - | caller save |
879 * |GR8-GR13 |Argument register | caller save |
880 * |GR14-GR15 | - | caller save |
881 * |GR16-GR31 | - | callee save |
882 * |GR32-GR47 | - | caller save |
883 * |GR48-GR63 | - | callee save |
884 * |FR0-FR15 | - | caller save |
885 * |FR16-FR31 | - | callee save |
886 * |FR32-FR47 | - | caller save |
887 * |FR48-FR63 | - | callee save |
888 * +---------------+-----------------------+-----------------------+
892 * SP-> |-----------------------------------|
894 * |-----------------------------------|
895 * | Register save area |
896 * |-----------------------------------|
897 * | Local variable save area |
898 * FP-> |-----------------------------------|
900 * |-----------------------------------|
901 * | Hidden parameter save area |
902 * |-----------------------------------|
903 * | Return address(LR) storage area |
904 * |-----------------------------------|
905 * | Padding for alignment |
906 * |-----------------------------------|
907 * | Register argument area |
908 * OLD SP-> |-----------------------------------|
910 * |-----------------------------------|
913 * Argument area/Parameter area:
915 * When a function is called, this area is used for argument transfer. When
916 * the argument is set up by the caller function, this area is referred to as
917 * the argument area. When the argument is referenced by the callee function,
918 * this area is referred to as the parameter area. The area is allocated when
919 * all arguments cannot be placed on the argument register at the time of
922 * Register save area:
924 * This is a register save area that must be guaranteed for the caller
925 * function. This area is not secured when the register save operation is not
928 * Local variable save area:
930 * This is the area for local variables and temporary variables.
934 * This area stores the FP value of the caller function.
936 * Hidden parameter save area:
938 * This area stores the start address of the return value storage
939 * area for a struct/union return function.
940 * When a struct/union is used as the return value, the caller
941 * function stores the return value storage area start address in
942 * register GR3 and passes it to the caller function.
943 * The callee function interprets the address stored in the GR3
944 * as the return value storage area start address.
945 * When register GR3 needs to be saved into memory, the callee
946 * function saves it in the hidden parameter save area. This
947 * area is not secured when the save operation is not needed.
949 * Return address(LR) storage area:
951 * This area saves the LR. The LR stores the address of a return to the caller
952 * function for the purpose of function calling.
954 * Argument register area:
956 * This area saves the argument register. This area is not secured when the
957 * save operation is not needed.
961 * Arguments, the count of which equals the count of argument registers (6
962 * words), are positioned in registers GR8 to GR13 and delivered to the callee
963 * function. When a struct/union return function is called, the return value
964 * area address is stored in register GR3. Arguments not placed in the
965 * argument registers will be stored in the stack argument area for transfer
966 * purposes. When an 8-byte type argument is to be delivered using registers,
967 * it is divided into two and placed in two registers for transfer. When
968 * argument registers must be saved to memory, the callee function secures an
969 * argument register save area in the stack. In this case, a continuous
970 * argument register save area must be established in the parameter area. The
971 * argument register save area must be allocated as needed to cover the size of
972 * the argument register to be saved. If the function has a variable count of
973 * arguments, it saves all argument registers in the argument register save
976 * Argument Extension Format:
978 * When an argument is to be stored in the stack, its type is converted to an
979 * extended type in accordance with the individual argument type. The argument
980 * is freed by the caller function after the return from the callee function is
983 * +-----------------------+---------------+------------------------+
984 * | Argument Type |Extended Type |Stack Storage Size(byte)|
985 * +-----------------------+---------------+------------------------+
987 * |signed char |int | 4 |
988 * |unsigned char |int | 4 |
989 * |[signed] short int |int | 4 |
990 * |unsigned short int |int | 4 |
991 * |[signed] int |No extension | 4 |
992 * |unsigned int |No extension | 4 |
993 * |[signed] long int |No extension | 4 |
994 * |unsigned long int |No extension | 4 |
995 * |[signed] long long int |No extension | 8 |
996 * |unsigned long long int |No extension | 8 |
997 * |float |double | 8 |
998 * |double |No extension | 8 |
999 * |long double |No extension | 8 |
1000 * |pointer |No extension | 4 |
1001 * |struct/union |- | 4 (*1) |
1002 * +-----------------------+---------------+------------------------+
1004 * When a struct/union is to be delivered as an argument, the caller copies it
1005 * to the local variable area and delivers the address of that area.
1009 * +-------------------------------+----------------------+
1010 * |Return Value Type |Return Value Interface|
1011 * +-------------------------------+----------------------+
1013 * |[signed|unsigned] char |GR8 |
1014 * |[signed|unsigned] short int |GR8 |
1015 * |[signed|unsigned] int |GR8 |
1016 * |[signed|unsigned] long int |GR8 |
1018 * |[signed|unsigned] long long int|GR8 & GR9 |
1020 * |double |GR8 & GR9 |
1021 * |long double |GR8 & GR9 |
1022 * |struct/union |(*1) |
1023 * +-------------------------------+----------------------+
1025 * When a struct/union is used as the return value, the caller function stores
1026 * the start address of the return value storage area into GR3 and then passes
1027 * it to the callee function. The callee function interprets GR3 as the start
1028 * address of the return value storage area. When this address needs to be
1029 * saved in memory, the callee function secures the hidden parameter save area
1030 * and saves the address in that area.
1034 frv_stack_info (void)
1036 static frv_stack_t info, zero_info;
1037 frv_stack_t *info_ptr = &info;
1038 tree fndecl = current_function_decl;
1046 /* If we've already calculated the values and reload is complete,
1048 if (frv_stack_cache)
1049 return frv_stack_cache;
1051 /* Zero all fields. */
1054 /* Set up the register range information. */
1055 info_ptr->regs[STACK_REGS_GPR].name = "gpr";
1056 info_ptr->regs[STACK_REGS_GPR].first = LAST_ARG_REGNUM + 1;
1057 info_ptr->regs[STACK_REGS_GPR].last = GPR_LAST;
1058 info_ptr->regs[STACK_REGS_GPR].dword_p = TRUE;
1060 info_ptr->regs[STACK_REGS_FPR].name = "fpr";
1061 info_ptr->regs[STACK_REGS_FPR].first = FPR_FIRST;
1062 info_ptr->regs[STACK_REGS_FPR].last = FPR_LAST;
1063 info_ptr->regs[STACK_REGS_FPR].dword_p = TRUE;
1065 info_ptr->regs[STACK_REGS_LR].name = "lr";
1066 info_ptr->regs[STACK_REGS_LR].first = LR_REGNO;
1067 info_ptr->regs[STACK_REGS_LR].last = LR_REGNO;
1068 info_ptr->regs[STACK_REGS_LR].special_p = 1;
1070 info_ptr->regs[STACK_REGS_CC].name = "cc";
1071 info_ptr->regs[STACK_REGS_CC].first = CC_FIRST;
1072 info_ptr->regs[STACK_REGS_CC].last = CC_LAST;
1073 info_ptr->regs[STACK_REGS_CC].field_p = TRUE;
1075 info_ptr->regs[STACK_REGS_LCR].name = "lcr";
1076 info_ptr->regs[STACK_REGS_LCR].first = LCR_REGNO;
1077 info_ptr->regs[STACK_REGS_LCR].last = LCR_REGNO;
1079 info_ptr->regs[STACK_REGS_STDARG].name = "stdarg";
1080 info_ptr->regs[STACK_REGS_STDARG].first = FIRST_ARG_REGNUM;
1081 info_ptr->regs[STACK_REGS_STDARG].last = LAST_ARG_REGNUM;
1082 info_ptr->regs[STACK_REGS_STDARG].dword_p = 1;
1083 info_ptr->regs[STACK_REGS_STDARG].special_p = 1;
1085 info_ptr->regs[STACK_REGS_STRUCT].name = "struct";
1086 info_ptr->regs[STACK_REGS_STRUCT].first = FRV_STRUCT_VALUE_REGNUM;
1087 info_ptr->regs[STACK_REGS_STRUCT].last = FRV_STRUCT_VALUE_REGNUM;
1088 info_ptr->regs[STACK_REGS_STRUCT].special_p = 1;
1090 info_ptr->regs[STACK_REGS_FP].name = "fp";
1091 info_ptr->regs[STACK_REGS_FP].first = FRAME_POINTER_REGNUM;
1092 info_ptr->regs[STACK_REGS_FP].last = FRAME_POINTER_REGNUM;
1093 info_ptr->regs[STACK_REGS_FP].special_p = 1;
1095 /* Determine if this is a stdarg function. If so, allocate space to store
1102 /* Find the last argument, and see if it is __builtin_va_alist. */
1103 for (cur_arg = DECL_ARGUMENTS (fndecl); cur_arg != (tree)0; cur_arg = next_arg)
1105 next_arg = TREE_CHAIN (cur_arg);
1106 if (next_arg == (tree)0)
1108 if (DECL_NAME (cur_arg)
1109 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)), "__builtin_va_alist"))
1117 /* Iterate over all of the register ranges. */
1118 for (range = 0; range < STACK_REGS_MAX; range++)
1120 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1121 int first = reg_ptr->first;
1122 int last = reg_ptr->last;
1124 int size_2words = 0;
1127 /* Calculate which registers need to be saved & save area size. */
1131 for (regno = first; regno <= last; regno++)
1133 if ((regs_ever_live[regno] && !call_used_regs[regno])
1134 || (current_function_calls_eh_return
1135 && (regno >= FIRST_EH_REGNUM && regno <= LAST_EH_REGNUM))
1136 || (!TARGET_FDPIC && flag_pic
1137 && cfun->uses_pic_offset_table && regno == PIC_REGNO))
1139 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1140 size_1word += UNITS_PER_WORD;
1145 /* Calculate whether we need to create a frame after everything else
1146 has been processed. */
1151 if (regs_ever_live[LR_REGNO]
1153 /* This is set for __builtin_return_address, etc. */
1154 || cfun->machine->frame_needed
1155 || (TARGET_LINKED_FP && frame_pointer_needed)
1156 || (!TARGET_FDPIC && flag_pic
1157 && cfun->uses_pic_offset_table))
1159 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1160 size_1word += UNITS_PER_WORD;
1164 case STACK_REGS_STDARG:
1167 /* If this is a stdarg function with a non varardic
1168 argument split between registers and the stack,
1169 adjust the saved registers downward. */
1170 last -= (ADDR_ALIGN (cfun->pretend_args_size, UNITS_PER_WORD)
1173 for (regno = first; regno <= last; regno++)
1175 info_ptr->save_p[regno] = REG_SAVE_1WORD;
1176 size_1word += UNITS_PER_WORD;
1179 info_ptr->stdarg_size = size_1word;
1183 case STACK_REGS_STRUCT:
1184 if (cfun->returns_struct)
1186 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1187 size_1word += UNITS_PER_WORD;
1195 /* If this is a field, it only takes one word. */
1196 if (reg_ptr->field_p)
1197 size_1word = UNITS_PER_WORD;
1199 /* Determine which register pairs can be saved together. */
1200 else if (reg_ptr->dword_p && TARGET_DWORD)
1202 for (regno = first; regno < last; regno += 2)
1204 if (info_ptr->save_p[regno] && info_ptr->save_p[regno+1])
1206 size_2words += 2 * UNITS_PER_WORD;
1207 size_1word -= 2 * UNITS_PER_WORD;
1208 info_ptr->save_p[regno] = REG_SAVE_2WORDS;
1209 info_ptr->save_p[regno+1] = REG_SAVE_NO_SAVE;
1214 reg_ptr->size_1word = size_1word;
1215 reg_ptr->size_2words = size_2words;
1217 if (! reg_ptr->special_p)
1219 info_ptr->regs_size_1word += size_1word;
1220 info_ptr->regs_size_2words += size_2words;
1225 /* Set up the sizes of each each field in the frame body, making the sizes
1226 of each be divisible by the size of a dword if dword operations might
1227 be used, or the size of a word otherwise. */
1228 alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
1230 info_ptr->parameter_size = ADDR_ALIGN (cfun->outgoing_args_size, alignment);
1231 info_ptr->regs_size = ADDR_ALIGN (info_ptr->regs_size_2words
1232 + info_ptr->regs_size_1word,
1234 info_ptr->vars_size = ADDR_ALIGN (get_frame_size (), alignment);
1236 info_ptr->pretend_size = cfun->pretend_args_size;
1238 /* Work out the size of the frame, excluding the header. Both the frame
1239 body and register parameter area will be dword-aligned. */
1240 info_ptr->total_size
1241 = (ADDR_ALIGN (info_ptr->parameter_size
1242 + info_ptr->regs_size
1243 + info_ptr->vars_size,
1245 + ADDR_ALIGN (info_ptr->pretend_size
1246 + info_ptr->stdarg_size,
1247 2 * UNITS_PER_WORD));
1249 /* See if we need to create a frame at all, if so add header area. */
1250 if (info_ptr->total_size > 0
1251 || frame_pointer_needed
1252 || info_ptr->regs[STACK_REGS_LR].size_1word > 0
1253 || info_ptr->regs[STACK_REGS_STRUCT].size_1word > 0)
1255 offset = info_ptr->parameter_size;
1256 info_ptr->header_size = 4 * UNITS_PER_WORD;
1257 info_ptr->total_size += 4 * UNITS_PER_WORD;
1259 /* Calculate the offsets to save normal register pairs. */
1260 for (range = 0; range < STACK_REGS_MAX; range++)
1262 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1263 if (! reg_ptr->special_p)
1265 int first = reg_ptr->first;
1266 int last = reg_ptr->last;
1269 for (regno = first; regno <= last; regno++)
1270 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS
1271 && regno != FRAME_POINTER_REGNUM
1272 && (regno < FIRST_ARG_REGNUM
1273 || regno > LAST_ARG_REGNUM))
1275 info_ptr->reg_offset[regno] = offset;
1276 offset += 2 * UNITS_PER_WORD;
1281 /* Calculate the offsets to save normal single registers. */
1282 for (range = 0; range < STACK_REGS_MAX; range++)
1284 frv_stack_regs_t *reg_ptr = &(info_ptr->regs[range]);
1285 if (! reg_ptr->special_p)
1287 int first = reg_ptr->first;
1288 int last = reg_ptr->last;
1291 for (regno = first; regno <= last; regno++)
1292 if (info_ptr->save_p[regno] == REG_SAVE_1WORD
1293 && regno != FRAME_POINTER_REGNUM
1294 && (regno < FIRST_ARG_REGNUM
1295 || regno > LAST_ARG_REGNUM))
1297 info_ptr->reg_offset[regno] = offset;
1298 offset += UNITS_PER_WORD;
1303 /* Calculate the offset to save the local variables at. */
1304 offset = ADDR_ALIGN (offset, alignment);
1305 if (info_ptr->vars_size)
1307 info_ptr->vars_offset = offset;
1308 offset += info_ptr->vars_size;
1311 /* Align header to a dword-boundary. */
1312 offset = ADDR_ALIGN (offset, 2 * UNITS_PER_WORD);
1314 /* Calculate the offsets in the fixed frame. */
1315 info_ptr->save_p[FRAME_POINTER_REGNUM] = REG_SAVE_1WORD;
1316 info_ptr->reg_offset[FRAME_POINTER_REGNUM] = offset;
1317 info_ptr->regs[STACK_REGS_FP].size_1word = UNITS_PER_WORD;
1319 info_ptr->save_p[LR_REGNO] = REG_SAVE_1WORD;
1320 info_ptr->reg_offset[LR_REGNO] = offset + 2*UNITS_PER_WORD;
1321 info_ptr->regs[STACK_REGS_LR].size_1word = UNITS_PER_WORD;
1323 if (cfun->returns_struct)
1325 info_ptr->save_p[FRV_STRUCT_VALUE_REGNUM] = REG_SAVE_1WORD;
1326 info_ptr->reg_offset[FRV_STRUCT_VALUE_REGNUM] = offset + UNITS_PER_WORD;
1327 info_ptr->regs[STACK_REGS_STRUCT].size_1word = UNITS_PER_WORD;
1330 /* Calculate the offsets to store the arguments passed in registers
1331 for stdarg functions. The register pairs are first and the single
1332 register if any is last. The register save area starts on a
1334 if (info_ptr->stdarg_size)
1336 int first = info_ptr->regs[STACK_REGS_STDARG].first;
1337 int last = info_ptr->regs[STACK_REGS_STDARG].last;
1340 /* Skip the header. */
1341 offset += 4 * UNITS_PER_WORD;
1342 for (regno = first; regno <= last; regno++)
1344 if (info_ptr->save_p[regno] == REG_SAVE_2WORDS)
1346 info_ptr->reg_offset[regno] = offset;
1347 offset += 2 * UNITS_PER_WORD;
1349 else if (info_ptr->save_p[regno] == REG_SAVE_1WORD)
1351 info_ptr->reg_offset[regno] = offset;
1352 offset += UNITS_PER_WORD;
1358 if (reload_completed)
1359 frv_stack_cache = info_ptr;
1365 /* Print the information about the frv stack offsets, etc. when debugging. */
1368 frv_debug_stack (frv_stack_t *info)
1373 info = frv_stack_info ();
1375 fprintf (stderr, "\nStack information for function %s:\n",
1376 ((current_function_decl && DECL_NAME (current_function_decl))
1377 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
1380 fprintf (stderr, "\ttotal_size\t= %6d\n", info->total_size);
1381 fprintf (stderr, "\tvars_size\t= %6d\n", info->vars_size);
1382 fprintf (stderr, "\tparam_size\t= %6d\n", info->parameter_size);
1383 fprintf (stderr, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1384 info->regs_size, info->regs_size_1word, info->regs_size_2words);
1386 fprintf (stderr, "\theader_size\t= %6d\n", info->header_size);
1387 fprintf (stderr, "\tpretend_size\t= %6d\n", info->pretend_size);
1388 fprintf (stderr, "\tvars_offset\t= %6d\n", info->vars_offset);
1389 fprintf (stderr, "\tregs_offset\t= %6d\n", info->regs_offset);
1391 for (range = 0; range < STACK_REGS_MAX; range++)
1393 frv_stack_regs_t *regs = &(info->regs[range]);
1394 if ((regs->size_1word + regs->size_2words) > 0)
1396 int first = regs->first;
1397 int last = regs->last;
1400 fprintf (stderr, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1401 regs->name, regs->size_1word + regs->size_2words,
1402 regs->size_1word, regs->size_2words);
1404 for (regno = first; regno <= last; regno++)
1406 if (info->save_p[regno] == REG_SAVE_1WORD)
1407 fprintf (stderr, " %s (%d)", reg_names[regno],
1408 info->reg_offset[regno]);
1410 else if (info->save_p[regno] == REG_SAVE_2WORDS)
1411 fprintf (stderr, " %s-%s (%d)", reg_names[regno],
1412 reg_names[regno+1], info->reg_offset[regno]);
1415 fputc ('\n', stderr);
1425 /* Used during final to control the packing of insns. The value is
1426 1 if the current instruction should be packed with the next one,
1427 0 if it shouldn't or -1 if packing is disabled altogether. */
1429 static int frv_insn_packing_flag;
1431 /* True if the current function contains a far jump. */
1434 frv_function_contains_far_jump (void)
1436 rtx insn = get_insns ();
1438 && !(GET_CODE (insn) == JUMP_INSN
1439 /* Ignore tablejump patterns. */
1440 && GET_CODE (PATTERN (insn)) != ADDR_VEC
1441 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
1442 && get_attr_far_jump (insn) == FAR_JUMP_YES))
1443 insn = NEXT_INSN (insn);
1444 return (insn != NULL);
1447 /* For the FRV, this function makes sure that a function with far jumps
1448 will return correctly. It also does the VLIW packing. */
1451 frv_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1453 /* If no frame was created, check whether the function uses a call
1454 instruction to implement a far jump. If so, save the link in gr3 and
1455 replace all returns to LR with returns to GR3. GR3 is used because it
1456 is call-clobbered, because is not available to the register allocator,
1457 and because all functions that take a hidden argument pointer will have
1459 if (frv_stack_info ()->total_size == 0 && frv_function_contains_far_jump ())
1463 /* Just to check that the above comment is true. */
1464 if (regs_ever_live[GPR_FIRST + 3])
1467 /* Generate the instruction that saves the link register. */
1468 fprintf (file, "\tmovsg lr,gr3\n");
1470 /* Replace the LR with GR3 in *return_internal patterns. The insn
1471 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1472 simply emit a different assembly directive because bralr and jmpl
1473 execute in different units. */
1474 for (insn = get_insns(); insn != NULL; insn = NEXT_INSN (insn))
1475 if (GET_CODE (insn) == JUMP_INSN)
1477 rtx pattern = PATTERN (insn);
1478 if (GET_CODE (pattern) == PARALLEL
1479 && XVECLEN (pattern, 0) >= 2
1480 && GET_CODE (XVECEXP (pattern, 0, 0)) == RETURN
1481 && GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
1483 rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
1484 if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
1485 REGNO (address) = GPR_FIRST + 3;
1492 /* Allow the garbage collector to free the nops created by frv_reorg. */
1493 memset (frv_nops, 0, sizeof (frv_nops));
1497 /* Return the next available temporary register in a given class. */
1500 frv_alloc_temp_reg (
1501 frv_tmp_reg_t *info, /* which registers are available */
1502 enum reg_class class, /* register class desired */
1503 enum machine_mode mode, /* mode to allocate register with */
1504 int mark_as_used, /* register not available after allocation */
1505 int no_abort) /* return NULL instead of aborting */
1507 int regno = info->next_reg[ (int)class ];
1508 int orig_regno = regno;
1509 HARD_REG_SET *reg_in_class = ®_class_contents[ (int)class ];
1514 if (TEST_HARD_REG_BIT (*reg_in_class, regno)
1515 && TEST_HARD_REG_BIT (info->regs, regno))
1518 if (++regno >= FIRST_PSEUDO_REGISTER)
1520 if (regno == orig_regno)
1529 nr = HARD_REGNO_NREGS (regno, mode);
1530 info->next_reg[ (int)class ] = regno + nr;
1533 for (i = 0; i < nr; i++)
1534 CLEAR_HARD_REG_BIT (info->regs, regno+i);
1536 return gen_rtx_REG (mode, regno);
1540 /* Return an rtx with the value OFFSET, which will either be a register or a
1541 signed 12-bit integer. It can be used as the second operand in an "add"
1542 instruction, or as the index in a load or store.
1544 The function returns a constant rtx if OFFSET is small enough, otherwise
1545 it loads the constant into register OFFSET_REGNO and returns that. */
1547 frv_frame_offset_rtx (int offset)
1549 rtx offset_rtx = GEN_INT (offset);
1550 if (IN_RANGE_P (offset, -2048, 2047))
1554 rtx reg_rtx = gen_rtx_REG (SImode, OFFSET_REGNO);
1555 if (IN_RANGE_P (offset, -32768, 32767))
1556 emit_insn (gen_movsi (reg_rtx, offset_rtx));
1559 emit_insn (gen_movsi_high (reg_rtx, offset_rtx));
1560 emit_insn (gen_movsi_lo_sum (reg_rtx, offset_rtx));
1566 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1567 prologue and epilogue uses such expressions to access the stack. */
1569 frv_frame_mem (enum machine_mode mode, rtx base, int offset)
1571 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode,
1573 frv_frame_offset_rtx (offset)));
1576 /* Generate a frame-related expression:
1578 (set REG (mem (plus (sp) (const_int OFFSET)))).
1580 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1581 instructions. Marking the expressions as frame-related is superfluous if
1582 the note contains just a single set. But if the note contains a PARALLEL
1583 or SEQUENCE that has several sets, each set must be individually marked
1584 as frame-related. */
1586 frv_dwarf_store (rtx reg, int offset)
1588 rtx set = gen_rtx_SET (VOIDmode,
1589 gen_rtx_MEM (GET_MODE (reg),
1590 plus_constant (stack_pointer_rtx,
1593 RTX_FRAME_RELATED_P (set) = 1;
1597 /* Emit a frame-related instruction whose pattern is PATTERN. The
1598 instruction is the last in a sequence that cumulatively performs the
1599 operation described by DWARF_PATTERN. The instruction is marked as
1600 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1603 frv_frame_insn (rtx pattern, rtx dwarf_pattern)
1605 rtx insn = emit_insn (pattern);
1606 RTX_FRAME_RELATED_P (insn) = 1;
1607 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1612 /* Emit instructions that transfer REG to or from the memory location (sp +
1613 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1614 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1615 function to store registers and only the epilogue uses it to load them.
1617 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1618 The generated instruction will use BASE as its base register. BASE may
1619 simply be the stack pointer, but if several accesses are being made to a
1620 region far away from the stack pointer, it may be more efficient to set
1621 up a temporary instead.
1623 Store instructions will be frame-related and will be annotated with the
1624 overall effect of the store. Load instructions will be followed by a
1625 (use) to prevent later optimizations from zapping them.
1627 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1628 as a temporary in such cases. */
1630 frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
1632 enum machine_mode mode = GET_MODE (reg);
1633 rtx mem = frv_frame_mem (mode,
1635 stack_offset - accessor->base_offset);
1637 if (accessor->op == FRV_LOAD)
1639 if (SPR_P (REGNO (reg)))
1641 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1642 emit_insn (gen_rtx_SET (VOIDmode, temp, mem));
1643 emit_insn (gen_rtx_SET (VOIDmode, reg, temp));
1646 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
1647 emit_insn (gen_rtx_USE (VOIDmode, reg));
1651 if (SPR_P (REGNO (reg)))
1653 rtx temp = gen_rtx_REG (mode, TEMP_REGNO);
1654 emit_insn (gen_rtx_SET (VOIDmode, temp, reg));
1655 frv_frame_insn (gen_rtx_SET (Pmode, mem, temp),
1656 frv_dwarf_store (reg, stack_offset));
1658 else if (GET_MODE (reg) == DImode)
1660 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1661 with a separate save for each register. */
1662 rtx reg1 = gen_rtx_REG (SImode, REGNO (reg));
1663 rtx reg2 = gen_rtx_REG (SImode, REGNO (reg) + 1);
1664 rtx set1 = frv_dwarf_store (reg1, stack_offset);
1665 rtx set2 = frv_dwarf_store (reg2, stack_offset + 4);
1666 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1667 gen_rtx_PARALLEL (VOIDmode,
1668 gen_rtvec (2, set1, set2)));
1671 frv_frame_insn (gen_rtx_SET (Pmode, mem, reg),
1672 frv_dwarf_store (reg, stack_offset));
1676 /* A function that uses frv_frame_access to transfer a group of registers to
1677 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1678 is the stack information generated by frv_stack_info, and REG_SET is the
1679 number of the register set to transfer. */
1681 frv_frame_access_multi (frv_frame_accessor_t *accessor,
1685 frv_stack_regs_t *regs_info;
1688 regs_info = &info->regs[reg_set];
1689 for (regno = regs_info->first; regno <= regs_info->last; regno++)
1690 if (info->save_p[regno])
1691 frv_frame_access (accessor,
1692 info->save_p[regno] == REG_SAVE_2WORDS
1693 ? gen_rtx_REG (DImode, regno)
1694 : gen_rtx_REG (SImode, regno),
1695 info->reg_offset[regno]);
1698 /* Save or restore callee-saved registers that are kept outside the frame
1699 header. The function saves the registers if OP is FRV_STORE and restores
1700 them if OP is FRV_LOAD. INFO is the stack information generated by
1703 frv_frame_access_standard_regs (enum frv_stack_op op, frv_stack_t *info)
1705 frv_frame_accessor_t accessor;
1708 accessor.base = stack_pointer_rtx;
1709 accessor.base_offset = 0;
1710 frv_frame_access_multi (&accessor, info, STACK_REGS_GPR);
1711 frv_frame_access_multi (&accessor, info, STACK_REGS_FPR);
1712 frv_frame_access_multi (&accessor, info, STACK_REGS_LCR);
1716 /* Called after register allocation to add any instructions needed for the
1717 prologue. Using a prologue insn is favored compared to putting all of the
1718 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1719 it allows the scheduler to intermix instructions with the saves of
1720 the caller saved registers. In some cases, it might be necessary
1721 to emit a barrier instruction as the last insn to prevent such
1724 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1725 so that the debug info generation code can handle them properly. */
1727 frv_expand_prologue (void)
1729 frv_stack_t *info = frv_stack_info ();
1730 rtx sp = stack_pointer_rtx;
1731 rtx fp = frame_pointer_rtx;
1732 frv_frame_accessor_t accessor;
1734 if (TARGET_DEBUG_STACK)
1735 frv_debug_stack (info);
1737 if (info->total_size == 0)
1740 /* We're interested in three areas of the frame here:
1742 A: the register save area
1744 C: the header after B
1746 If the frame pointer isn't used, we'll have to set up A, B and C
1747 using the stack pointer. If the frame pointer is used, we'll access
1751 B: set up using sp or a temporary (see below)
1754 We set up B using the stack pointer if the frame is small enough.
1755 Otherwise, it's more efficient to copy the old stack pointer into a
1756 temporary and use that.
1758 Note that it's important to make sure the prologue and epilogue use the
1759 same registers to access A and C, since doing otherwise will confuse
1760 the aliasing code. */
1762 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1763 isn't used, the same method will serve for C. */
1764 accessor.op = FRV_STORE;
1765 if (frame_pointer_needed && info->total_size > 2048)
1769 accessor.base = gen_rtx_REG (Pmode, OLD_SP_REGNO);
1770 accessor.base_offset = info->total_size;
1771 insn = emit_insn (gen_movsi (accessor.base, sp));
1775 accessor.base = stack_pointer_rtx;
1776 accessor.base_offset = 0;
1779 /* Allocate the stack space. */
1781 rtx asm_offset = frv_frame_offset_rtx (-info->total_size);
1782 rtx dwarf_offset = GEN_INT (-info->total_size);
1784 frv_frame_insn (gen_stack_adjust (sp, sp, asm_offset),
1787 gen_rtx_PLUS (Pmode, sp, dwarf_offset)));
1790 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1791 and point the new one to that location. */
1792 if (frame_pointer_needed)
1794 int fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1796 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1797 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1799 rtx asm_src = plus_constant (accessor.base,
1800 fp_offset - accessor.base_offset);
1801 rtx dwarf_src = plus_constant (sp, fp_offset);
1803 /* Store the old frame pointer at (sp + FP_OFFSET). */
1804 frv_frame_access (&accessor, fp, fp_offset);
1806 /* Set up the new frame pointer. */
1807 frv_frame_insn (gen_rtx_SET (VOIDmode, fp, asm_src),
1808 gen_rtx_SET (VOIDmode, fp, dwarf_src));
1810 /* Access region C from the frame pointer. */
1812 accessor.base_offset = fp_offset;
1815 /* Set up region C. */
1816 frv_frame_access_multi (&accessor, info, STACK_REGS_STRUCT);
1817 frv_frame_access_multi (&accessor, info, STACK_REGS_LR);
1818 frv_frame_access_multi (&accessor, info, STACK_REGS_STDARG);
1820 /* Set up region A. */
1821 frv_frame_access_standard_regs (FRV_STORE, info);
1823 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1824 scheduler from moving loads before the stores saving the registers. */
1825 if (info->stdarg_size > 0)
1826 emit_insn (gen_blockage ());
1828 /* Set up pic register/small data register for this function. */
1829 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
1830 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode, PIC_REGNO),
1831 gen_rtx_REG (Pmode, LR_REGNO),
1832 gen_rtx_REG (SImode, OFFSET_REGNO)));
1836 /* Under frv, all of the work is done via frv_expand_epilogue, but
1837 this function provides a convenient place to do cleanup. */
1840 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
1841 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1843 frv_stack_cache = (frv_stack_t *)0;
1845 /* Zap last used registers for conditional execution. */
1846 memset (&frv_ifcvt.tmp_reg, 0, sizeof (frv_ifcvt.tmp_reg));
1848 /* Release the bitmap of created insns. */
1849 BITMAP_FREE (frv_ifcvt.scratch_insns_bitmap);
1853 /* Called after register allocation to add any instructions needed for the
1854 epilogue. Using an epilogue insn is favored compared to putting all of the
1855 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1856 it allows the scheduler to intermix instructions with the saves of
1857 the caller saved registers. In some cases, it might be necessary
1858 to emit a barrier instruction as the last insn to prevent such
1862 frv_expand_epilogue (bool emit_return)
1864 frv_stack_t *info = frv_stack_info ();
1865 rtx fp = frame_pointer_rtx;
1866 rtx sp = stack_pointer_rtx;
1870 fp_offset = info->reg_offset[FRAME_POINTER_REGNUM];
1872 /* Restore the stack pointer to its original value if alloca or the like
1874 if (! current_function_sp_is_unchanging)
1875 emit_insn (gen_addsi3 (sp, fp, frv_frame_offset_rtx (-fp_offset)));
1877 /* Restore the callee-saved registers that were used in this function. */
1878 frv_frame_access_standard_regs (FRV_LOAD, info);
1880 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1881 no return instruction should be emitted. */
1882 if (info->save_p[LR_REGNO])
1887 /* Use the same method to access the link register's slot as we did in
1888 the prologue. In other words, use the frame pointer if available,
1889 otherwise use the stack pointer.
1891 LR_OFFSET is the offset of the link register's slot from the start
1892 of the frame and MEM is a memory rtx for it. */
1893 lr_offset = info->reg_offset[LR_REGNO];
1894 if (frame_pointer_needed)
1895 mem = frv_frame_mem (Pmode, fp, lr_offset - fp_offset);
1897 mem = frv_frame_mem (Pmode, sp, lr_offset);
1899 /* Load the old link register into a GPR. */
1900 return_addr = gen_rtx_REG (Pmode, TEMP_REGNO);
1901 emit_insn (gen_rtx_SET (VOIDmode, return_addr, mem));
1904 return_addr = gen_rtx_REG (Pmode, LR_REGNO);
1906 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1907 the load is preserved. */
1908 if (frame_pointer_needed)
1910 emit_insn (gen_rtx_SET (VOIDmode, fp, gen_rtx_MEM (Pmode, fp)));
1911 emit_insn (gen_rtx_USE (VOIDmode, fp));
1914 /* Deallocate the stack frame. */
1915 if (info->total_size != 0)
1917 rtx offset = frv_frame_offset_rtx (info->total_size);
1918 emit_insn (gen_stack_adjust (sp, sp, offset));
1921 /* If this function uses eh_return, add the final stack adjustment now. */
1922 if (current_function_calls_eh_return)
1923 emit_insn (gen_stack_adjust (sp, sp, EH_RETURN_STACKADJ_RTX));
1926 emit_jump_insn (gen_epilogue_return (return_addr));
1929 rtx lr = return_addr;
1931 if (REGNO (return_addr) != LR_REGNO)
1933 lr = gen_rtx_REG (Pmode, LR_REGNO);
1934 emit_move_insn (lr, return_addr);
1937 emit_insn (gen_rtx_USE (VOIDmode, lr));
1942 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1945 frv_asm_output_mi_thunk (FILE *file,
1946 tree thunk_fndecl ATTRIBUTE_UNUSED,
1947 HOST_WIDE_INT delta,
1948 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
1951 const char *name_func = XSTR (XEXP (DECL_RTL (function), 0), 0);
1952 const char *name_arg0 = reg_names[FIRST_ARG_REGNUM];
1953 const char *name_jmp = reg_names[JUMP_REGNO];
1954 const char *parallel = (frv_issue_rate () > 1 ? ".p" : "");
1956 /* Do the add using an addi if possible. */
1957 if (IN_RANGE_P (delta, -2048, 2047))
1958 fprintf (file, "\taddi %s,#%d,%s\n", name_arg0, (int) delta, name_arg0);
1961 const char *const name_add = reg_names[TEMP_REGNO];
1962 fprintf (file, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1963 parallel, delta, name_add);
1964 fprintf (file, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC "),%s\n",
1966 fprintf (file, "\tadd %s,%s,%s\n", name_add, name_arg0, name_arg0);
1971 const char *name_pic = reg_names[FDPIC_REGNO];
1972 name_jmp = reg_names[FDPIC_FPTR_REGNO];
1976 fprintf (file, "\tsethi%s #gotofffuncdeschi(", parallel);
1977 assemble_name (file, name_func);
1978 fprintf (file, "),%s\n", name_jmp);
1980 fprintf (file, "\tsetlo #gotofffuncdesclo(");
1981 assemble_name (file, name_func);
1982 fprintf (file, "),%s\n", name_jmp);
1984 fprintf (file, "\tldd @(%s,%s), %s\n", name_jmp, name_pic, name_jmp);
1988 fprintf (file, "\tlddo @(%s,#gotofffuncdesc12(", name_pic);
1989 assemble_name (file, name_func);
1990 fprintf (file, "\t)), %s\n", name_jmp);
1995 fprintf (file, "\tsethi%s #hi(", parallel);
1996 assemble_name (file, name_func);
1997 fprintf (file, "),%s\n", name_jmp);
1999 fprintf (file, "\tsetlo #lo(");
2000 assemble_name (file, name_func);
2001 fprintf (file, "),%s\n", name_jmp);
2005 /* Use JUMP_REGNO as a temporary PIC register. */
2006 const char *name_lr = reg_names[LR_REGNO];
2007 const char *name_gppic = name_jmp;
2008 const char *name_tmp = reg_names[TEMP_REGNO];
2010 fprintf (file, "\tmovsg %s,%s\n", name_lr, name_tmp);
2011 fprintf (file, "\tcall 1f\n");
2012 fprintf (file, "1:\tmovsg %s,%s\n", name_lr, name_gppic);
2013 fprintf (file, "\tmovgs %s,%s\n", name_tmp, name_lr);
2014 fprintf (file, "\tsethi%s #gprelhi(1b),%s\n", parallel, name_tmp);
2015 fprintf (file, "\tsetlo #gprello(1b),%s\n", name_tmp);
2016 fprintf (file, "\tsub %s,%s,%s\n", name_gppic, name_tmp, name_gppic);
2018 fprintf (file, "\tsethi%s #gprelhi(", parallel);
2019 assemble_name (file, name_func);
2020 fprintf (file, "),%s\n", name_tmp);
2022 fprintf (file, "\tsetlo #gprello(");
2023 assemble_name (file, name_func);
2024 fprintf (file, "),%s\n", name_tmp);
2026 fprintf (file, "\tadd %s,%s,%s\n", name_gppic, name_tmp, name_jmp);
2029 /* Jump to the function address. */
2030 fprintf (file, "\tjmpl @(%s,%s)\n", name_jmp, reg_names[GPR_FIRST+0]);
2034 /* A C expression which is nonzero if a function must have and use a frame
2035 pointer. This expression is evaluated in the reload pass. If its value is
2036 nonzero the function will have a frame pointer.
2038 The expression can in principle examine the current function and decide
2039 according to the facts, but on most machines the constant 0 or the constant
2040 1 suffices. Use 0 when the machine allows code to be generated with no
2041 frame pointer, and doing so saves some time or space. Use 1 when there is
2042 no possible advantage to avoiding a frame pointer.
2044 In certain cases, the compiler does not know how to produce valid code
2045 without a frame pointer. The compiler recognizes those cases and
2046 automatically gives the function a frame pointer regardless of what
2047 `FRAME_POINTER_REQUIRED' says. You don't need to worry about them.
2049 In a function that does not require a frame pointer, the frame pointer
2050 register can be allocated for ordinary usage, unless you mark it as a fixed
2051 register. See `FIXED_REGISTERS' for more information. */
2053 /* On frv, create a frame whenever we need to create stack. */
2056 frv_frame_pointer_required (void)
2058 /* If we forgoing the usual linkage requirements, we only need
2059 a frame pointer if the stack pointer might change. */
2060 if (!TARGET_LINKED_FP)
2061 return !current_function_sp_is_unchanging;
2063 if (! current_function_is_leaf)
2066 if (get_frame_size () != 0)
2072 if (!current_function_sp_is_unchanging)
2075 if (!TARGET_FDPIC && flag_pic && cfun->uses_pic_offset_table)
2081 if (cfun->machine->frame_needed)
2088 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2089 initial difference between the specified pair of registers. This macro must
2090 be defined if `ELIMINABLE_REGS' is defined. */
2092 /* See frv_stack_info for more details on the frv stack frame. */
2095 frv_initial_elimination_offset (int from, int to)
2097 frv_stack_t *info = frv_stack_info ();
2100 if (to == STACK_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2101 ret = info->total_size - info->pretend_size;
2103 else if (to == STACK_POINTER_REGNUM && from == FRAME_POINTER_REGNUM)
2104 ret = info->reg_offset[FRAME_POINTER_REGNUM];
2106 else if (to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM)
2107 ret = (info->total_size
2108 - info->reg_offset[FRAME_POINTER_REGNUM]
2109 - info->pretend_size);
2114 if (TARGET_DEBUG_STACK)
2115 fprintf (stderr, "Eliminate %s to %s by adding %d\n",
2116 reg_names [from], reg_names[to], ret);
2122 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2125 frv_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2126 enum machine_mode mode,
2127 tree type ATTRIBUTE_UNUSED,
2131 if (TARGET_DEBUG_ARG)
2133 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2134 *cum, GET_MODE_NAME (mode), *pretend_size, second_time);
2138 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2141 frv_expand_builtin_saveregs (void)
2143 int offset = UNITS_PER_WORD * FRV_NUM_ARG_REGS;
2145 if (TARGET_DEBUG_ARG)
2146 fprintf (stderr, "expand_builtin_saveregs: offset from ap = %d\n",
2149 return gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx, GEN_INT (- offset));
2153 /* Expand __builtin_va_start to do the va_start macro. */
2156 frv_expand_builtin_va_start (tree valist, rtx nextarg)
2159 int num = cfun->args_info - FIRST_ARG_REGNUM - FRV_NUM_ARG_REGS;
2161 nextarg = gen_rtx_PLUS (Pmode, virtual_incoming_args_rtx,
2162 GEN_INT (UNITS_PER_WORD * num));
2164 if (TARGET_DEBUG_ARG)
2166 fprintf (stderr, "va_start: args_info = %d, num = %d\n",
2167 cfun->args_info, num);
2169 debug_rtx (nextarg);
2172 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
2173 make_tree (ptr_type_node, nextarg));
2174 TREE_SIDE_EFFECTS (t) = 1;
2176 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2180 /* Expand a block move operation, and return 1 if successful. Return 0
2181 if we should let the compiler generate normal code.
2183 operands[0] is the destination
2184 operands[1] is the source
2185 operands[2] is the length
2186 operands[3] is the alignment */
2188 /* Maximum number of loads to do before doing the stores */
2189 #ifndef MAX_MOVE_REG
2190 #define MAX_MOVE_REG 4
2193 /* Maximum number of total loads to do. */
2194 #ifndef TOTAL_MOVE_REG
2195 #define TOTAL_MOVE_REG 8
2199 frv_expand_block_move (rtx operands[])
2201 rtx orig_dest = operands[0];
2202 rtx orig_src = operands[1];
2203 rtx bytes_rtx = operands[2];
2204 rtx align_rtx = operands[3];
2205 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2218 rtx stores[MAX_MOVE_REG];
2220 enum machine_mode mode;
2222 /* If this is not a fixed size move, just call memcpy. */
2226 /* If this is not a fixed size alignment, abort. */
2227 if (GET_CODE (align_rtx) != CONST_INT)
2230 align = INTVAL (align_rtx);
2232 /* Anything to move? */
2233 bytes = INTVAL (bytes_rtx);
2237 /* Don't support real large moves. */
2238 if (bytes > TOTAL_MOVE_REG*align)
2241 /* Move the address into scratch registers. */
2242 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2243 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2245 num_reg = offset = 0;
2246 for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes))
2248 /* Calculate the correct offset for src/dest. */
2252 dest_addr = dest_reg;
2256 src_addr = plus_constant (src_reg, offset);
2257 dest_addr = plus_constant (dest_reg, offset);
2260 /* Generate the appropriate load and store, saving the stores
2262 if (bytes >= 4 && align >= 4)
2264 else if (bytes >= 2 && align >= 2)
2269 move_bytes = GET_MODE_SIZE (mode);
2270 tmp_reg = gen_reg_rtx (mode);
2271 src_mem = change_address (orig_src, mode, src_addr);
2272 dest_mem = change_address (orig_dest, mode, dest_addr);
2273 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg, src_mem));
2274 stores[num_reg++] = gen_rtx_SET (VOIDmode, dest_mem, tmp_reg);
2276 if (num_reg >= MAX_MOVE_REG)
2278 for (i = 0; i < num_reg; i++)
2279 emit_insn (stores[i]);
2284 for (i = 0; i < num_reg; i++)
2285 emit_insn (stores[i]);
2291 /* Expand a block clear operation, and return 1 if successful. Return 0
2292 if we should let the compiler generate normal code.
2294 operands[0] is the destination
2295 operands[1] is the length
2296 operands[2] is the alignment */
2299 frv_expand_block_clear (rtx operands[])
2301 rtx orig_dest = operands[0];
2302 rtx bytes_rtx = operands[1];
2303 rtx align_rtx = operands[2];
2304 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
2313 enum machine_mode mode;
2315 /* If this is not a fixed size move, just call memcpy. */
2319 /* If this is not a fixed size alignment, abort. */
2320 if (GET_CODE (align_rtx) != CONST_INT)
2323 align = INTVAL (align_rtx);
2325 /* Anything to move? */
2326 bytes = INTVAL (bytes_rtx);
2330 /* Don't support real large clears. */
2331 if (bytes > TOTAL_MOVE_REG*align)
2334 /* Move the address into a scratch register. */
2335 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
2337 num_reg = offset = 0;
2338 for ( ; bytes > 0; (bytes -= clear_bytes), (offset += clear_bytes))
2340 /* Calculate the correct offset for src/dest. */
2341 dest_addr = ((offset == 0)
2343 : plus_constant (dest_reg, offset));
2345 /* Generate the appropriate store of gr0. */
2346 if (bytes >= 4 && align >= 4)
2348 else if (bytes >= 2 && align >= 2)
2353 clear_bytes = GET_MODE_SIZE (mode);
2354 dest_mem = change_address (orig_dest, mode, dest_addr);
2355 emit_insn (gen_rtx_SET (VOIDmode, dest_mem, const0_rtx));
2362 /* The following variable is used to output modifiers of assembler
2363 code of the current output insn. */
2365 static rtx *frv_insn_operands;
2367 /* The following function is used to add assembler insn code suffix .p
2368 if it is necessary. */
2371 frv_asm_output_opcode (FILE *f, const char *ptr)
2375 if (frv_insn_packing_flag <= 0)
2378 for (; *ptr && *ptr != ' ' && *ptr != '\t';)
2381 if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2382 || (*ptr >= 'A' && *ptr <= 'Z')))
2384 int letter = *ptr++;
2387 frv_print_operand (f, frv_insn_operands [c], letter);
2388 while ((c = *ptr) >= '0' && c <= '9')
2400 /* Set up the packing bit for the current output insn. Note that this
2401 function is not called for asm insns. */
2404 frv_final_prescan_insn (rtx insn, rtx *opvec,
2405 int noperands ATTRIBUTE_UNUSED)
2409 if (frv_insn_packing_flag >= 0)
2411 frv_insn_operands = opvec;
2412 frv_insn_packing_flag = PACKING_FLAG_P (insn);
2414 else if (recog_memoized (insn) >= 0
2415 && get_attr_acc_group (insn) == ACC_GROUP_ODD)
2416 /* Packing optimizations have been disabled, but INSN can only
2417 be issued in M1. Insert an mnop in M0. */
2418 fprintf (asm_out_file, "\tmnop.p\n");
2424 /* A C expression whose value is RTL representing the address in a stack frame
2425 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2426 an RTL expression for the address of the stack frame itself.
2428 If you don't define this macro, the default is to return the value of
2429 FRAMEADDR--that is, the stack frame address is also the address of the stack
2430 word that points to the previous frame. */
2432 /* The default is correct, but we need to make sure the frame gets created. */
2434 frv_dynamic_chain_address (rtx frame)
2436 cfun->machine->frame_needed = 1;
2441 /* A C expression whose value is RTL representing the value of the return
2442 address for the frame COUNT steps up from the current frame, after the
2443 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2444 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2447 The value of the expression must always be the correct address when COUNT is
2448 zero, but may be `NULL_RTX' if there is not way to determine the return
2449 address of other frames. */
2452 frv_return_addr_rtx (int count, rtx frame)
2456 cfun->machine->frame_needed = 1;
2457 return gen_rtx_MEM (Pmode, plus_constant (frame, 8));
2460 /* Given a memory reference MEMREF, interpret the referenced memory as
2461 an array of MODE values, and return a reference to the element
2462 specified by INDEX. Assume that any pre-modification implicit in
2463 MEMREF has already happened.
2465 MEMREF must be a legitimate operand for modes larger than SImode.
2466 GO_IF_LEGITIMATE_ADDRESS forbids register+register addresses, which
2467 this function cannot handle. */
2469 frv_index_memory (rtx memref, enum machine_mode mode, int index)
2471 rtx base = XEXP (memref, 0);
2472 if (GET_CODE (base) == PRE_MODIFY)
2473 base = XEXP (base, 0);
2474 return change_address (memref, mode,
2475 plus_constant (base, index * GET_MODE_SIZE (mode)));
2479 /* Print a memory address as an operand to reference that memory location. */
2481 frv_print_operand_address (FILE * stream, rtx x)
2483 if (GET_CODE (x) == MEM)
2486 switch (GET_CODE (x))
2489 fputs (reg_names [ REGNO (x)], stream);
2493 fprintf (stream, "%ld", (long) INTVAL (x));
2497 assemble_name (stream, XSTR (x, 0));
2502 output_addr_const (stream, x);
2509 fatal_insn ("Bad insn to frv_print_operand_address:", x);
2514 frv_print_operand_memory_reference_reg (FILE * stream, rtx x)
2516 int regno = true_regnum (x);
2518 fputs (reg_names[regno], stream);
2520 fatal_insn ("Bad register to frv_print_operand_memory_reference_reg:", x);
2523 /* Print a memory reference suitable for the ld/st instructions. */
2526 frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
2528 struct frv_unspec unspec;
2532 switch (GET_CODE (x))
2539 case PRE_MODIFY: /* (pre_modify (reg) (plus (reg) (reg))) */
2541 x1 = XEXP (XEXP (x, 1), 1);
2551 if (GET_CODE (x0) == CONST_INT)
2559 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2568 else if (GET_CODE (x1) != CONST_INT)
2569 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2572 fputs ("@(", stream);
2574 fputs (reg_names[GPR_R0], stream);
2575 else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
2576 frv_print_operand_memory_reference_reg (stream, x0);
2578 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2580 fputs (",", stream);
2582 fputs (reg_names [GPR_R0], stream);
2586 switch (GET_CODE (x1))
2590 frv_print_operand_memory_reference_reg (stream, x1);
2594 fprintf (stream, "%ld", (long) (INTVAL (x1) + addr_offset));
2598 if (!frv_const_unspec_p (x1, &unspec))
2599 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x1);
2600 frv_output_const_unspec (stream, &unspec);
2604 fatal_insn ("Bad insn to frv_print_operand_memory_reference:", x);
2608 fputs (")", stream);
2612 /* Return 2 for likely branches and 0 for non-likely branches */
2614 #define FRV_JUMP_LIKELY 2
2615 #define FRV_JUMP_NOT_LIKELY 0
2618 frv_print_operand_jump_hint (rtx insn)
2623 HOST_WIDE_INT prob = -1;
2624 enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
2626 if (GET_CODE (insn) != JUMP_INSN)
2629 /* Assume any non-conditional jump is likely. */
2630 if (! any_condjump_p (insn))
2631 ret = FRV_JUMP_LIKELY;
2635 labelref = condjump_label (insn);
2638 rtx label = XEXP (labelref, 0);
2639 jump_type = (insn_current_address > INSN_ADDRESSES (INSN_UID (label))
2644 note = find_reg_note (insn, REG_BR_PROB, 0);
2646 ret = ((jump_type == BACKWARD) ? FRV_JUMP_LIKELY : FRV_JUMP_NOT_LIKELY);
2650 prob = INTVAL (XEXP (note, 0));
2651 ret = ((prob >= (REG_BR_PROB_BASE / 2))
2653 : FRV_JUMP_NOT_LIKELY);
2665 case UNKNOWN: direction = "unknown jump direction"; break;
2666 case BACKWARD: direction = "jump backward"; break;
2667 case FORWARD: direction = "jump forward"; break;
2671 "%s: uid %ld, %s, probability = %ld, max prob. = %ld, hint = %d\n",
2672 IDENTIFIER_POINTER (DECL_NAME (current_function_decl)),
2673 (long)INSN_UID (insn), direction, (long)prob,
2674 (long)REG_BR_PROB_BASE, ret);
2682 /* Return the comparison operator to use for CODE given that the ICC
2686 comparison_string (enum rtx_code code, rtx op0)
2688 bool is_nz_p = GET_MODE (op0) == CC_NZmode;
2691 default: output_operand_lossage ("bad condition code");
2692 case EQ: return "eq";
2693 case NE: return "ne";
2694 case LT: return is_nz_p ? "n" : "lt";
2695 case LE: return "le";
2696 case GT: return "gt";
2697 case GE: return is_nz_p ? "p" : "ge";
2698 case LTU: return is_nz_p ? "no" : "c";
2699 case LEU: return is_nz_p ? "eq" : "ls";
2700 case GTU: return is_nz_p ? "ne" : "hi";
2701 case GEU: return is_nz_p ? "ra" : "nc";
2705 /* Print an operand to an assembler instruction.
2707 `%' followed by a letter and a digit says to output an operand in an
2708 alternate fashion. Four letters have standard, built-in meanings described
2709 below. The machine description macro `PRINT_OPERAND' can define additional
2710 letters with nonstandard meanings.
2712 `%cDIGIT' can be used to substitute an operand that is a constant value
2713 without the syntax that normally indicates an immediate operand.
2715 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2718 `%aDIGIT' can be used to substitute an operand as if it were a memory
2719 reference, with the actual operand treated as the address. This may be
2720 useful when outputting a "load address" instruction, because often the
2721 assembler syntax for such an instruction requires you to write the operand
2722 as if it were a memory reference.
2724 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2726 `%=' outputs a number which is unique to each instruction in the entire
2727 compilation. This is useful for making local labels to be referred to more
2728 than once in a single template that generates multiple assembler
2731 `%' followed by a punctuation character specifies a substitution that does
2732 not use an operand. Only one case is standard: `%%' outputs a `%' into the
2733 assembler code. Other nonstandard cases can be defined in the
2734 `PRINT_OPERAND' macro. You must also define which punctuation characters
2735 are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro. */
2738 frv_print_operand (FILE * file, rtx x, int code)
2740 struct frv_unspec unspec;
2741 HOST_WIDE_INT value;
2744 if (code != 0 && !isalpha (code))
2747 else if (GET_CODE (x) == CONST_INT)
2750 else if (GET_CODE (x) == CONST_DOUBLE)
2752 if (GET_MODE (x) == SFmode)
2757 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
2758 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2762 else if (GET_MODE (x) == VOIDmode)
2763 value = CONST_DOUBLE_LOW (x);
2766 fatal_insn ("Bad insn in frv_print_operand, bad const_double", x);
2777 fputs (reg_names[GPR_R0], file);
2781 fprintf (file, "%d", frv_print_operand_jump_hint (current_output_insn));
2785 /* Output small data area base register (gr16). */
2786 fputs (reg_names[SDA_BASE_REG], file);
2790 /* Output pic register (gr17). */
2791 fputs (reg_names[PIC_REGNO], file);
2795 /* Output the temporary integer CCR register. */
2796 fputs (reg_names[ICR_TEMP], file);
2800 /* Output the temporary integer CC register. */
2801 fputs (reg_names[ICC_TEMP], file);
2804 /* case 'a': print an address. */
2807 /* Print appropriate test for integer branch false operation. */
2808 fputs (comparison_string (reverse_condition (GET_CODE (x)),
2809 XEXP (x, 0)), file);
2813 /* Print appropriate test for integer branch true operation. */
2814 fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
2818 /* Print 1 for a NE and 0 for an EQ to give the final argument
2819 for a conditional instruction. */
2820 if (GET_CODE (x) == NE)
2823 else if (GET_CODE (x) == EQ)
2827 fatal_insn ("Bad insn to frv_print_operand, 'e' modifier:", x);
2831 /* Print appropriate test for floating point branch false operation. */
2832 switch (GET_CODE (x))
2835 fatal_insn ("Bad insn to frv_print_operand, 'F' modifier:", x);
2837 case EQ: fputs ("ne", file); break;
2838 case NE: fputs ("eq", file); break;
2839 case LT: fputs ("uge", file); break;
2840 case LE: fputs ("ug", file); break;
2841 case GT: fputs ("ule", file); break;
2842 case GE: fputs ("ul", file); break;
2847 /* Print appropriate test for floating point branch true operation. */
2848 switch (GET_CODE (x))
2851 fatal_insn ("Bad insn to frv_print_operand, 'f' modifier:", x);
2853 case EQ: fputs ("eq", file); break;
2854 case NE: fputs ("ne", file); break;
2855 case LT: fputs ("lt", file); break;
2856 case LE: fputs ("le", file); break;
2857 case GT: fputs ("gt", file); break;
2858 case GE: fputs ("ge", file); break;
2863 /* Print appropriate GOT function. */
2864 if (GET_CODE (x) != CONST_INT)
2865 fatal_insn ("Bad insn to frv_print_operand, 'g' modifier:", x);
2866 fputs (unspec_got_name (INTVAL (x)), file);
2870 /* Print 'i' if the operand is a constant, or is a memory reference that
2872 if (GET_CODE (x) == MEM)
2873 x = ((GET_CODE (XEXP (x, 0)) == PLUS)
2874 ? XEXP (XEXP (x, 0), 1)
2876 else if (GET_CODE (x) == PLUS)
2879 switch (GET_CODE (x))
2893 /* For jump instructions, print 'i' if the operand is a constant or
2894 is an expression that adds a constant. */
2895 if (GET_CODE (x) == CONST_INT)
2900 if (GET_CODE (x) == CONST_INT
2901 || (GET_CODE (x) == PLUS
2902 && (GET_CODE (XEXP (x, 1)) == CONST_INT
2903 || GET_CODE (XEXP (x, 0)) == CONST_INT)))
2909 /* Print the lower register of a double word register pair */
2910 if (GET_CODE (x) == REG)
2911 fputs (reg_names[ REGNO (x)+1 ], file);
2913 fatal_insn ("Bad insn to frv_print_operand, 'L' modifier:", x);
2916 /* case 'l': print a LABEL_REF. */
2920 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2921 for the second word of double memory operations. */
2922 offset = (code == 'M') ? 0 : UNITS_PER_WORD;
2923 switch (GET_CODE (x))
2926 fatal_insn ("Bad insn to frv_print_operand, 'M/N' modifier:", x);
2929 frv_print_operand_memory_reference (file, XEXP (x, 0), offset);
2937 frv_print_operand_memory_reference (file, x, offset);
2943 /* Print the opcode of a command. */
2944 switch (GET_CODE (x))
2947 fatal_insn ("Bad insn to frv_print_operand, 'O' modifier:", x);
2949 case PLUS: fputs ("add", file); break;
2950 case MINUS: fputs ("sub", file); break;
2951 case AND: fputs ("and", file); break;
2952 case IOR: fputs ("or", file); break;
2953 case XOR: fputs ("xor", file); break;
2954 case ASHIFT: fputs ("sll", file); break;
2955 case ASHIFTRT: fputs ("sra", file); break;
2956 case LSHIFTRT: fputs ("srl", file); break;
2960 /* case 'n': negate and print a constant int. */
2963 /* Print PIC label using operand as the number. */
2964 if (GET_CODE (x) != CONST_INT)
2965 fatal_insn ("Bad insn to frv_print_operand, P modifier:", x);
2967 fprintf (file, ".LCF%ld", (long)INTVAL (x));
2971 /* Print 'u' if the operand is a update load/store. */
2972 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
2977 /* If value is 0, print gr0, otherwise it must be a register. */
2978 if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
2979 fputs (reg_names[GPR_R0], file);
2981 else if (GET_CODE (x) == REG)
2982 fputs (reg_names [REGNO (x)], file);
2985 fatal_insn ("Bad insn in frv_print_operand, z case", x);
2989 /* Print constant in hex. */
2990 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2992 fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
2999 if (GET_CODE (x) == REG)
3000 fputs (reg_names [REGNO (x)], file);
3002 else if (GET_CODE (x) == CONST_INT
3003 || GET_CODE (x) == CONST_DOUBLE)
3004 fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
3006 else if (frv_const_unspec_p (x, &unspec))
3007 frv_output_const_unspec (file, &unspec);
3009 else if (GET_CODE (x) == MEM)
3010 frv_print_operand_address (file, XEXP (x, 0));
3012 else if (CONSTANT_ADDRESS_P (x))
3013 frv_print_operand_address (file, x);
3016 fatal_insn ("Bad insn in frv_print_operand, 0 case", x);
3021 fatal_insn ("frv_print_operand: unknown code", x);
3029 /* A C statement (sans semicolon) for initializing the variable CUM for the
3030 state at the beginning of the argument list. The variable has type
3031 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3032 of the function which will receive the args, or 0 if the args are to a
3033 compiler support library function. The value of INDIRECT is nonzero when
3034 processing an indirect call, for example a call through a function pointer.
3035 The value of INDIRECT is zero for a call to an explicitly named function, a
3036 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3037 arguments for the function being compiled.
3039 When processing a call to a compiler support library function, LIBNAME
3040 identifies which one. It is a `symbol_ref' rtx which contains the name of
3041 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3042 being processed. Thus, each time this macro is called, either LIBNAME or
3043 FNTYPE is nonzero, but never both of them at once. */
3046 frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
3052 *cum = FIRST_ARG_REGNUM;
3054 if (TARGET_DEBUG_ARG)
3056 fprintf (stderr, "\ninit_cumulative_args:");
3057 if (!fndecl && fntype)
3058 fputs (" indirect", stderr);
3061 fputs (" incoming", stderr);
3065 tree ret_type = TREE_TYPE (fntype);
3066 fprintf (stderr, " return=%s,",
3067 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3070 if (libname && GET_CODE (libname) == SYMBOL_REF)
3071 fprintf (stderr, " libname=%s", XSTR (libname, 0));
3073 if (cfun->returns_struct)
3074 fprintf (stderr, " return-struct");
3076 putc ('\n', stderr);
3081 /* Return true if we should pass an argument on the stack rather than
3085 frv_must_pass_in_stack (enum machine_mode mode, tree type)
3087 if (mode == BLKmode)
3091 return AGGREGATE_TYPE_P (type);
3094 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3095 argument with the specified mode and type. If it is not defined,
3096 `PARM_BOUNDARY' is used for all arguments. */
3099 frv_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
3100 tree type ATTRIBUTE_UNUSED)
3102 return BITS_PER_WORD;
3106 frv_function_arg (CUMULATIVE_ARGS *cum,
3107 enum machine_mode mode,
3108 tree type ATTRIBUTE_UNUSED,
3110 int incoming ATTRIBUTE_UNUSED)
3112 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3117 /* Return a marker for use in the call instruction. */
3118 if (xmode == VOIDmode)
3124 else if (arg_num <= LAST_ARG_REGNUM)
3126 ret = gen_rtx_REG (xmode, arg_num);
3127 debstr = reg_names[arg_num];
3136 if (TARGET_DEBUG_ARG)
3138 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3139 arg_num, GET_MODE_NAME (mode), named, GET_MODE_SIZE (mode), debstr);
3145 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3146 advance past an argument in the argument list. The values MODE, TYPE and
3147 NAMED describe that argument. Once this is done, the variable CUM is
3148 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3150 This macro need not do anything if the argument in question was passed on
3151 the stack. The compiler knows how to track the amount of stack space used
3152 for arguments without any special help. */
3155 frv_function_arg_advance (CUMULATIVE_ARGS *cum,
3156 enum machine_mode mode,
3157 tree type ATTRIBUTE_UNUSED,
3160 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3161 int bytes = GET_MODE_SIZE (xmode);
3162 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3165 *cum = arg_num + words;
3167 if (TARGET_DEBUG_ARG)
3169 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3170 arg_num, GET_MODE_NAME (mode), named, words * UNITS_PER_WORD);
3174 /* A C expression for the number of words, at the beginning of an argument,
3175 must be put in registers. The value must be zero for arguments that are
3176 passed entirely in registers or that are entirely pushed on the stack.
3178 On some machines, certain arguments must be passed partially in registers
3179 and partially in memory. On these machines, typically the first N words of
3180 arguments are passed in registers, and the rest on the stack. If a
3181 multi-word argument (a `double' or a structure) crosses that boundary, its
3182 first few words must be passed in registers and the rest must be pushed.
3183 This macro tells the compiler when this occurs, and how many of the words
3184 should go in registers.
3186 `FUNCTION_ARG' for these arguments should return the first register to be
3187 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3188 the called function. */
3191 frv_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3192 tree type ATTRIBUTE_UNUSED, bool named ATTRIBUTE_UNUSED)
3194 enum machine_mode xmode = (mode == BLKmode) ? SImode : mode;
3195 int bytes = GET_MODE_SIZE (xmode);
3196 int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3200 ret = ((arg_num <= LAST_ARG_REGNUM && arg_num + words > LAST_ARG_REGNUM+1)
3201 ? LAST_ARG_REGNUM - arg_num + 1
3203 ret *= UNITS_PER_WORD;
3205 if (TARGET_DEBUG_ARG && ret)
3206 fprintf (stderr, "frv_arg_partial_bytes: %d\n", ret);
3212 /* Return true if a register is ok to use as a base or index register. */
3214 static FRV_INLINE int
3215 frv_regno_ok_for_base_p (int regno, int strict_p)
3221 return (reg_renumber[regno] >= 0 && GPR_P (reg_renumber[regno]));
3223 if (regno == ARG_POINTER_REGNUM)
3226 return (regno >= FIRST_PSEUDO_REGISTER);
3230 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3231 RTX) is a legitimate memory address on the target machine for a memory
3232 operand of mode MODE.
3234 It usually pays to define several simpler macros to serve as subroutines for
3235 this one. Otherwise it may be too complicated to understand.
3237 This macro must exist in two variants: a strict variant and a non-strict
3238 one. The strict variant is used in the reload pass. It must be defined so
3239 that any pseudo-register that has not been allocated a hard register is
3240 considered a memory reference. In contexts where some kind of register is
3241 required, a pseudo-register with no hard register must be rejected.
3243 The non-strict variant is used in other passes. It must be defined to
3244 accept all pseudo-registers in every context where some kind of register is
3247 Compiler source files that want to use the strict variant of this macro
3248 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3249 conditional to define the strict variant in that case and the non-strict
3252 Subroutines to check for acceptable registers for various purposes (one for
3253 base registers, one for index registers, and so on) are typically among the
3254 subroutines used to define `GO_IF_LEGITIMATE_ADDRESS'. Then only these
3255 subroutine macros need have two variants; the higher levels of macros may be
3256 the same whether strict or not.
3258 Normally, constant addresses which are the sum of a `symbol_ref' and an
3259 integer are stored inside a `const' RTX to mark them as constant.
3260 Therefore, there is no need to recognize such sums specifically as
3261 legitimate addresses. Normally you would simply recognize any `const' as
3264 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle constant sums that
3265 are not marked with `const'. It assumes that a naked `plus' indicates
3266 indexing. If so, then you *must* reject such naked constant sums as
3267 illegitimate addresses, so that none of them will be given to
3268 `PRINT_OPERAND_ADDRESS'.
3270 On some machines, whether a symbolic address is legitimate depends on the
3271 section that the address refers to. On these machines, define the macro
3272 `ENCODE_SECTION_INFO' to store the information into the `symbol_ref', and
3273 then check for it here. When you see a `const', you will have to look
3274 inside it to find the `symbol_ref' in order to determine the section.
3276 The best way to modify the name string is by adding text to the beginning,
3277 with suitable punctuation to prevent any ambiguity. Allocate the new name
3278 in `saveable_obstack'. You will have to modify `ASM_OUTPUT_LABELREF' to
3279 remove and decode the added text and output the name accordingly, and define
3280 `(* targetm.strip_name_encoding)' to access the original name string.
3282 You can check the information stored here into the `symbol_ref' in the
3283 definitions of the macros `GO_IF_LEGITIMATE_ADDRESS' and
3284 `PRINT_OPERAND_ADDRESS'. */
3287 frv_legitimate_address_p (enum machine_mode mode,
3291 int allow_double_reg_p)
3295 HOST_WIDE_INT value;
3298 if (FRV_SYMBOL_REF_TLS_P (x))
3301 switch (GET_CODE (x))
3308 if (GET_CODE (x) != REG)
3314 ret = frv_regno_ok_for_base_p (REGNO (x), strict_p);
3320 if (GET_CODE (x0) != REG
3321 || ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
3322 || GET_CODE (x1) != PLUS
3323 || ! rtx_equal_p (x0, XEXP (x1, 0))
3324 || GET_CODE (XEXP (x1, 1)) != REG
3325 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
3332 /* 12 bit immediate */
3337 ret = IN_RANGE_P (INTVAL (x), -2048, 2047);
3339 /* If we can't use load/store double operations, make sure we can
3340 address the second word. */
3341 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3342 ret = IN_RANGE_P (INTVAL (x) + GET_MODE_SIZE (mode) - 1,
3351 if (GET_CODE (x0) == SUBREG)
3352 x0 = SUBREG_REG (x0);
3354 if (GET_CODE (x0) != REG)
3357 regno0 = REGNO (x0);
3358 if (!frv_regno_ok_for_base_p (regno0, strict_p))
3361 switch (GET_CODE (x1))
3367 x1 = SUBREG_REG (x1);
3368 if (GET_CODE (x1) != REG)
3374 /* Do not allow reg+reg addressing for modes > 1 word if we
3375 can't depend on having move double instructions. */
3376 if (!allow_double_reg_p && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3379 ret = frv_regno_ok_for_base_p (REGNO (x1), strict_p);
3383 /* 12 bit immediate */
3388 value = INTVAL (x1);
3389 ret = IN_RANGE_P (value, -2048, 2047);
3391 /* If we can't use load/store double operations, make sure we can
3392 address the second word. */
3393 if (ret && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3394 ret = IN_RANGE_P (value + GET_MODE_SIZE (mode) - 1, -2048, 2047);
3399 if (!condexec_p && got12_operand (x1, VOIDmode))
3407 if (TARGET_DEBUG_ADDR)
3409 fprintf (stderr, "\n========== GO_IF_LEGITIMATE_ADDRESS, mode = %s, result = %d, addresses are %sstrict%s\n",
3410 GET_MODE_NAME (mode), ret, (strict_p) ? "" : "not ",
3411 (condexec_p) ? ", inside conditional code" : "");
3418 /* Given an ADDR, generate code to inline the PLT. */
3420 gen_inlined_tls_plt (rtx addr)
3422 rtx mem, retval, dest;
3423 rtx picreg = get_hard_reg_initial_val (Pmode, FDPIC_REG);
3426 dest = gen_reg_rtx (DImode);
3433 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3434 calll #gettlsoff(ADDR)@(gr8, gr0)
3436 emit_insn (gen_tls_lddi (dest, addr, picreg));
3443 sethi.p #gottlsdeschi(ADDR), gr8
3444 setlo #gottlsdesclo(ADDR), gr8
3445 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3446 calll #gettlsoff(ADDR)@(gr8, gr0)
3448 rtx reguse = gen_reg_rtx (Pmode);
3449 emit_insn (gen_tlsoff_hilo (reguse, addr, GEN_INT (R_FRV_GOTTLSDESCHI)));
3450 emit_insn (gen_tls_tlsdesc_ldd (dest, picreg, reguse, addr));
3453 retval = gen_reg_rtx (Pmode);
3454 emit_insn (gen_tls_indirect_call (retval, addr, dest, picreg));
3458 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3459 the destination address. */
3461 gen_tlsmoff (rtx addr, rtx reg)
3463 rtx dest = gen_reg_rtx (Pmode);
3467 /* sethi.p #tlsmoffhi(x), grA
3468 setlo #tlsmofflo(x), grA
3470 dest = gen_reg_rtx (Pmode);
3471 emit_insn (gen_tlsoff_hilo (dest, addr,
3472 GEN_INT (R_FRV_TLSMOFFHI)));
3473 dest = gen_rtx_PLUS (Pmode, dest, reg);
3477 /* addi grB, #tlsmoff12(x), grC
3479 ld/st @(grB, #tlsmoff12(x)), grC
3481 dest = gen_reg_rtx (Pmode);
3482 emit_insn (gen_symGOTOFF2reg_i (dest, addr, reg,
3483 GEN_INT (R_FRV_TLSMOFF12)));
3488 /* Generate code for a TLS address. */
3490 frv_legitimize_tls_address (rtx addr, enum tls_model model)
3492 rtx dest, tp = gen_rtx_REG (Pmode, 29);
3493 rtx picreg = get_hard_reg_initial_val (Pmode, 15);
3497 case TLS_MODEL_INITIAL_EXEC:
3501 ldi @(gr15, #gottlsoff12(x)), gr5
3503 dest = gen_reg_rtx (Pmode);
3504 emit_insn (gen_tls_load_gottlsoff12 (dest, addr, picreg));
3505 dest = gen_rtx_PLUS (Pmode, tp, dest);
3509 /* -fPIC or anything else.
3511 sethi.p #gottlsoffhi(x), gr14
3512 setlo #gottlsofflo(x), gr14
3513 ld #tlsoff(x)@(gr15, gr14), gr9
3515 rtx tmp = gen_reg_rtx (Pmode);
3516 dest = gen_reg_rtx (Pmode);
3517 emit_insn (gen_tlsoff_hilo (tmp, addr,
3518 GEN_INT (R_FRV_GOTTLSOFF_HI)));
3520 emit_insn (gen_tls_tlsoff_ld (dest, picreg, tmp, addr));
3521 dest = gen_rtx_PLUS (Pmode, tp, dest);
3524 case TLS_MODEL_LOCAL_DYNAMIC:
3528 if (TARGET_INLINE_PLT)
3529 retval = gen_inlined_tls_plt (GEN_INT (0));
3532 /* call #gettlsoff(0) */
3533 retval = gen_reg_rtx (Pmode);
3534 emit_insn (gen_call_gettlsoff (retval, GEN_INT (0), picreg));
3537 reg = gen_reg_rtx (Pmode);
3538 emit_insn (gen_rtx_SET (VOIDmode, reg,
3539 gen_rtx_PLUS (Pmode,
3542 dest = gen_tlsmoff (addr, reg);
3545 dest = gen_reg_rtx (Pmode);
3546 emit_insn (gen_tlsoff_hilo (dest, addr,
3547 GEN_INT (R_FRV_TLSMOFFHI)));
3548 dest = gen_rtx_PLUS (Pmode, dest, reg);
3552 case TLS_MODEL_LOCAL_EXEC:
3553 dest = gen_tlsmoff (addr, gen_rtx_REG (Pmode, 29));
3555 case TLS_MODEL_GLOBAL_DYNAMIC:
3559 if (TARGET_INLINE_PLT)
3560 retval = gen_inlined_tls_plt (addr);
3563 /* call #gettlsoff(x) */
3564 retval = gen_reg_rtx (Pmode);
3565 emit_insn (gen_call_gettlsoff (retval, addr, picreg));
3567 dest = gen_rtx_PLUS (Pmode, retval, tp);
3578 frv_legitimize_address (rtx x,
3579 rtx oldx ATTRIBUTE_UNUSED,
3580 enum machine_mode mode ATTRIBUTE_UNUSED)
3582 if (GET_CODE (x) == SYMBOL_REF)
3584 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3586 return frv_legitimize_tls_address (x, model);
3592 /* Test whether a local function descriptor is canonical, i.e.,
3593 whether we can use FUNCDESC_GOTOFF to compute the address of the
3597 frv_local_funcdesc_p (rtx fnx)
3600 enum symbol_visibility vis;
3603 if (! SYMBOL_REF_LOCAL_P (fnx))
3606 fn = SYMBOL_REF_DECL (fnx);
3611 vis = DECL_VISIBILITY (fn);
3613 if (vis == VISIBILITY_PROTECTED)
3614 /* Private function descriptors for protected functions are not
3615 canonical. Temporarily change the visibility to global. */
3616 vis = VISIBILITY_DEFAULT;
3617 else if (flag_shlib)
3618 /* If we're already compiling for a shared library (that, unlike
3619 executables, can't assume that the existence of a definition
3620 implies local binding), we can skip the re-testing. */
3623 ret = default_binds_local_p_1 (fn, flag_pic);
3625 DECL_VISIBILITY (fn) = vis;
3630 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3634 frv_gen_GPsym2reg (rtx dest, rtx src)
3636 tree gp = get_identifier ("_gp");
3637 rtx gp_sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (gp));
3639 return gen_symGOT2reg (dest, gp_sym, src, GEN_INT (R_FRV_GOT12));
3643 unspec_got_name (int i)
3647 case R_FRV_GOT12: return "got12";
3648 case R_FRV_GOTHI: return "gothi";
3649 case R_FRV_GOTLO: return "gotlo";
3650 case R_FRV_FUNCDESC: return "funcdesc";
3651 case R_FRV_FUNCDESC_GOT12: return "gotfuncdesc12";
3652 case R_FRV_FUNCDESC_GOTHI: return "gotfuncdeschi";
3653 case R_FRV_FUNCDESC_GOTLO: return "gotfuncdesclo";
3654 case R_FRV_FUNCDESC_VALUE: return "funcdescvalue";
3655 case R_FRV_FUNCDESC_GOTOFF12: return "gotofffuncdesc12";
3656 case R_FRV_FUNCDESC_GOTOFFHI: return "gotofffuncdeschi";
3657 case R_FRV_FUNCDESC_GOTOFFLO: return "gotofffuncdesclo";
3658 case R_FRV_GOTOFF12: return "gotoff12";
3659 case R_FRV_GOTOFFHI: return "gotoffhi";
3660 case R_FRV_GOTOFFLO: return "gotofflo";
3661 case R_FRV_GPREL12: return "gprel12";
3662 case R_FRV_GPRELHI: return "gprelhi";
3663 case R_FRV_GPRELLO: return "gprello";
3664 case R_FRV_GOTTLSOFF_HI: return "gottlsoffhi";
3665 case R_FRV_GOTTLSOFF_LO: return "gottlsofflo";
3666 case R_FRV_TLSMOFFHI: return "tlsmoffhi";
3667 case R_FRV_TLSMOFFLO: return "tlsmofflo";
3668 case R_FRV_TLSMOFF12: return "tlsmoff12";
3669 case R_FRV_TLSDESCHI: return "tlsdeschi";
3670 case R_FRV_TLSDESCLO: return "tlsdesclo";
3671 case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
3672 case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
3677 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3678 is added inside the relocation operator. */
3681 frv_output_const_unspec (FILE *stream, const struct frv_unspec *unspec)
3683 fprintf (stream, "#%s(", unspec_got_name (unspec->reloc));
3684 output_addr_const (stream, plus_constant (unspec->symbol, unspec->offset));
3685 fputs (")", stream);
3688 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3689 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3690 otherwise return ORIG_X. */
3693 frv_find_base_term (rtx x)
3695 struct frv_unspec unspec;
3697 if (frv_const_unspec_p (x, &unspec)
3698 && frv_small_data_reloc_p (unspec.symbol, unspec.reloc))
3699 return plus_constant (unspec.symbol, unspec.offset);
3704 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3705 the operand is used by a predicated instruction. */
3708 frv_legitimate_memory_operand (rtx op, enum machine_mode mode, int condexec_p)
3710 return ((GET_MODE (op) == mode || mode == VOIDmode)
3711 && GET_CODE (op) == MEM
3712 && frv_legitimate_address_p (mode, XEXP (op, 0),
3713 reload_completed, condexec_p, FALSE));
3717 frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
3719 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
3720 rtx picreg = get_hard_reg_initial_val (SImode, FDPIC_REG);
3726 rvrtx = operands[0];
3730 addr = XEXP (operands[0], 0);
3732 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3733 any calls that would involve a PLT, but can't tell, since we
3734 don't know whether an extern function is going to be provided by
3735 a separate translation unit or imported from a separate module.
3736 When compiling for shared libraries, if the function has default
3737 visibility, we assume it's overridable, so we inline the PLT, but
3738 for executables, we don't really have a way to make a good
3739 decision: a function is as likely to be imported from a shared
3740 library as it is to be defined in the executable itself. We
3741 assume executables will get global functions defined locally,
3742 whereas shared libraries will have them potentially overridden,
3743 so we only inline PLTs when compiling for shared libraries.
3745 In order to mark a function as local to a shared library, any
3746 non-default visibility attribute suffices. Unfortunately,
3747 there's no simple way to tag a function declaration as ``in a
3748 different module'', which we could then use to trigger PLT
3749 inlining on executables. There's -minline-plt, but it affects
3750 all external functions, so one would have to also mark function
3751 declarations available in the same module with non-default
3752 visibility, which is advantageous in itself. */
3753 if (GET_CODE (addr) == SYMBOL_REF
3754 && ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
3758 dest = gen_reg_rtx (SImode);
3760 x = gen_symGOTOFF2reg_hilo (dest, addr, OUR_FDPIC_REG,
3761 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3763 x = gen_symGOTOFF2reg (dest, addr, OUR_FDPIC_REG,
3764 GEN_INT (R_FRV_FUNCDESC_GOTOFF12));
3766 cfun->uses_pic_offset_table = TRUE;
3769 else if (GET_CODE (addr) == SYMBOL_REF)
3771 /* These are always either local, or handled through a local
3774 c = gen_call_value_fdpicsi (rvrtx, addr, operands[1],
3775 operands[2], picreg, lr);
3777 c = gen_call_fdpicsi (addr, operands[1], operands[2], picreg, lr);
3781 else if (! ldd_address_operand (addr, Pmode))
3782 addr = force_reg (Pmode, addr);
3784 picreg = gen_reg_rtx (DImode);
3785 emit_insn (gen_movdi_ldd (picreg, addr));
3787 if (sibcall && ret_value)
3788 c = gen_sibcall_value_fdpicdi (rvrtx, picreg, const0_rtx);
3790 c = gen_sibcall_fdpicdi (picreg, const0_rtx);
3792 c = gen_call_value_fdpicdi (rvrtx, picreg, const0_rtx, lr);
3794 c = gen_call_fdpicdi (picreg, const0_rtx, lr);
3798 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3799 process these separately from any offsets, such that we add any
3800 offsets to the function descriptor (the actual pointer), not to the
3801 function address. */
3804 frv_function_symbol_referenced_p (rtx x)
3810 if (GET_CODE (x) == SYMBOL_REF)
3811 return SYMBOL_REF_FUNCTION_P (x);
3813 length = GET_RTX_LENGTH (GET_CODE (x));
3814 format = GET_RTX_FORMAT (GET_CODE (x));
3816 for (j = 0; j < length; ++j)
3821 if (frv_function_symbol_referenced_p (XEXP (x, j)))
3827 if (XVEC (x, j) != 0)
3830 for (k = 0; k < XVECLEN (x, j); ++k)
3831 if (frv_function_symbol_referenced_p (XVECEXP (x, j, k)))
3837 /* Nothing to do. */
3845 /* Return true if the memory operand is one that can be conditionally
3849 condexec_memory_operand (rtx op, enum machine_mode mode)
3851 enum machine_mode op_mode = GET_MODE (op);
3854 if (mode != VOIDmode && op_mode != mode)
3869 if (GET_CODE (op) != MEM)
3872 addr = XEXP (op, 0);
3873 return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
3876 /* Return true if the bare return instruction can be used outside of the
3877 epilog code. For frv, we only do it if there was no stack allocation. */
3880 direct_return_p (void)
3884 if (!reload_completed)
3887 info = frv_stack_info ();
3888 return (info->total_size == 0);
3893 frv_emit_move (enum machine_mode mode, rtx dest, rtx src)
3895 if (GET_CODE (src) == SYMBOL_REF)
3897 enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
3899 src = frv_legitimize_tls_address (src, model);
3905 if (frv_emit_movsi (dest, src))
3914 if (!reload_in_progress
3915 && !reload_completed
3916 && !register_operand (dest, mode)
3917 && !reg_or_0_operand (src, mode))
3918 src = copy_to_mode_reg (mode, src);
3925 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3928 /* Emit code to handle a MOVSI, adding in the small data register or pic
3929 register if needed to load up addresses. Return TRUE if the appropriate
3930 instructions are emitted. */
3933 frv_emit_movsi (rtx dest, rtx src)
3935 int base_regno = -1;
3938 struct frv_unspec old_unspec;
3940 if (!reload_in_progress
3941 && !reload_completed
3942 && !register_operand (dest, SImode)
3943 && (!reg_or_0_operand (src, SImode)
3944 /* Virtual registers will almost always be replaced by an
3945 add instruction, so expose this to CSE by copying to
3946 an intermediate register. */
3947 || (GET_CODE (src) == REG
3948 && IN_RANGE_P (REGNO (src),
3949 FIRST_VIRTUAL_REGISTER,
3950 LAST_VIRTUAL_REGISTER))))
3952 emit_insn (gen_rtx_SET (VOIDmode, dest, copy_to_mode_reg (SImode, src)));
3956 /* Explicitly add in the PIC or small data register if needed. */
3957 switch (GET_CODE (src))
3966 /* Using GPREL12, we use a single GOT entry for all symbols
3967 in read-only sections, but trade sequences such as:
3969 sethi #gothi(label), gr#
3970 setlo #gotlo(label), gr#
3975 ld @(gr15,#got12(_gp)), gr#
3976 sethi #gprelhi(label), gr##
3977 setlo #gprello(label), gr##
3980 We may often be able to share gr# for multiple
3981 computations of GPREL addresses, and we may often fold
3982 the final add into the pair of registers of a load or
3983 store instruction, so it's often profitable. Even when
3984 optimizing for size, we're trading a GOT entry for an
3985 additional instruction, which trades GOT space
3986 (read-write) for code size (read-only, shareable), as
3987 long as the symbol is not used in more than two different
3990 With -fpie/-fpic, we'd be trading a single load for a
3991 sequence of 4 instructions, because the offset of the
3992 label can't be assumed to be addressable with 12 bits, so
3993 we don't do this. */
3994 if (TARGET_GPREL_RO)
3995 unspec = R_FRV_GPREL12;
3997 unspec = R_FRV_GOT12;
4000 base_regno = PIC_REGNO;
4005 if (frv_const_unspec_p (src, &old_unspec))
4008 if (TARGET_FDPIC && frv_function_symbol_referenced_p (XEXP (src, 0)))
4011 src = force_reg (GET_MODE (XEXP (src, 0)), XEXP (src, 0));
4012 emit_move_insn (dest, src);
4017 sym = XEXP (sym, 0);
4018 if (GET_CODE (sym) == PLUS
4019 && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
4020 && GET_CODE (XEXP (sym, 1)) == CONST_INT)
4021 sym = XEXP (sym, 0);
4022 if (GET_CODE (sym) == SYMBOL_REF)
4024 else if (GET_CODE (sym) == LABEL_REF)
4027 goto handle_whatever;
4035 enum tls_model model = SYMBOL_REF_TLS_MODEL (sym);
4039 src = frv_legitimize_tls_address (src, model);
4040 emit_move_insn (dest, src);
4044 if (SYMBOL_REF_FUNCTION_P (sym))
4046 if (frv_local_funcdesc_p (sym))
4047 unspec = R_FRV_FUNCDESC_GOTOFF12;
4049 unspec = R_FRV_FUNCDESC_GOT12;
4053 if (CONSTANT_POOL_ADDRESS_P (sym))
4054 switch (GET_CODE (get_pool_constant (sym)))
4061 unspec = R_FRV_GOTOFF12;
4066 if (TARGET_GPREL_RO)
4067 unspec = R_FRV_GPREL12;
4069 unspec = R_FRV_GOT12;
4072 else if (SYMBOL_REF_LOCAL_P (sym)
4073 && !SYMBOL_REF_EXTERNAL_P (sym)
4074 && SYMBOL_REF_DECL (sym)
4075 && (!DECL_P (SYMBOL_REF_DECL (sym))
4076 || !DECL_COMMON (SYMBOL_REF_DECL (sym))))
4078 tree decl = SYMBOL_REF_DECL (sym);
4079 tree init = TREE_CODE (decl) == VAR_DECL
4080 ? DECL_INITIAL (decl)
4081 : TREE_CODE (decl) == CONSTRUCTOR
4084 bool named_section, readonly;
4086 if (init && init != error_mark_node)
4087 reloc = compute_reloc_for_constant (init);
4089 named_section = TREE_CODE (decl) == VAR_DECL
4090 && lookup_attribute ("section", DECL_ATTRIBUTES (decl));
4091 readonly = decl_readonly_section (decl, reloc);
4094 unspec = R_FRV_GOT12;
4096 unspec = R_FRV_GOTOFF12;
4097 else if (readonly && TARGET_GPREL_RO)
4098 unspec = R_FRV_GPREL12;
4100 unspec = R_FRV_GOT12;
4103 unspec = R_FRV_GOT12;
4107 else if (SYMBOL_REF_SMALL_P (sym))
4108 base_regno = SDA_BASE_REG;
4111 base_regno = PIC_REGNO;
4116 if (base_regno >= 0)
4118 if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
4119 emit_insn (gen_symGOTOFF2reg (dest, src,
4120 gen_rtx_REG (Pmode, base_regno),
4121 GEN_INT (R_FRV_GPREL12)));
4123 emit_insn (gen_symGOTOFF2reg_hilo (dest, src,
4124 gen_rtx_REG (Pmode, base_regno),
4125 GEN_INT (R_FRV_GPREL12)));
4126 if (base_regno == PIC_REGNO)
4127 cfun->uses_pic_offset_table = TRUE;
4135 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4136 new uses of it once reload has begun. */
4137 if (reload_in_progress || reload_completed)
4142 case R_FRV_GOTOFF12:
4143 if (!frv_small_data_reloc_p (sym, unspec))
4144 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4147 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4150 if (!frv_small_data_reloc_p (sym, unspec))
4151 x = gen_symGPREL2reg_hilo (dest, src, OUR_FDPIC_REG,
4154 x = gen_symGPREL2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4156 case R_FRV_FUNCDESC_GOTOFF12:
4158 x = gen_symGOTOFF2reg_hilo (dest, src, OUR_FDPIC_REG,
4161 x = gen_symGOTOFF2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4165 x = gen_symGOT2reg_hilo (dest, src, OUR_FDPIC_REG,
4168 x = gen_symGOT2reg (dest, src, OUR_FDPIC_REG, GEN_INT (unspec));
4172 cfun->uses_pic_offset_table = TRUE;
4181 /* Return a string to output a single word move. */
4184 output_move_single (rtx operands[], rtx insn)
4186 rtx dest = operands[0];
4187 rtx src = operands[1];
4189 if (GET_CODE (dest) == REG)
4191 int dest_regno = REGNO (dest);
4192 enum machine_mode mode = GET_MODE (dest);
4194 if (GPR_P (dest_regno))
4196 if (GET_CODE (src) == REG)
4198 /* gpr <- some sort of register */
4199 int src_regno = REGNO (src);
4201 if (GPR_P (src_regno))
4202 return "mov %1, %0";
4204 else if (FPR_P (src_regno))
4205 return "movfg %1, %0";
4207 else if (SPR_P (src_regno))
4208 return "movsg %1, %0";
4211 else if (GET_CODE (src) == MEM)
4220 return "ldsb%I1%U1 %M1,%0";
4223 return "ldsh%I1%U1 %M1,%0";
4227 return "ld%I1%U1 %M1, %0";
4231 else if (GET_CODE (src) == CONST_INT
4232 || GET_CODE (src) == CONST_DOUBLE)
4234 /* gpr <- integer/floating constant */
4235 HOST_WIDE_INT value;
4237 if (GET_CODE (src) == CONST_INT)
4238 value = INTVAL (src);
4240 else if (mode == SFmode)
4245 REAL_VALUE_FROM_CONST_DOUBLE (rv, src);
4246 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4251 value = CONST_DOUBLE_LOW (src);
4253 if (IN_RANGE_P (value, -32768, 32767))
4254 return "setlos %1, %0";
4259 else if (GET_CODE (src) == SYMBOL_REF
4260 || GET_CODE (src) == LABEL_REF
4261 || GET_CODE (src) == CONST)
4267 else if (FPR_P (dest_regno))
4269 if (GET_CODE (src) == REG)
4271 /* fpr <- some sort of register */
4272 int src_regno = REGNO (src);
4274 if (GPR_P (src_regno))
4275 return "movgf %1, %0";
4277 else if (FPR_P (src_regno))
4279 if (TARGET_HARD_FLOAT)
4280 return "fmovs %1, %0";
4282 return "mor %1, %1, %0";
4286 else if (GET_CODE (src) == MEM)
4295 return "ldbf%I1%U1 %M1,%0";
4298 return "ldhf%I1%U1 %M1,%0";
4302 return "ldf%I1%U1 %M1, %0";
4306 else if (ZERO_P (src))
4307 return "movgf %., %0";
4310 else if (SPR_P (dest_regno))
4312 if (GET_CODE (src) == REG)
4314 /* spr <- some sort of register */
4315 int src_regno = REGNO (src);
4317 if (GPR_P (src_regno))
4318 return "movgs %1, %0";
4320 else if (ZERO_P (src))
4321 return "movgs %., %0";
4325 else if (GET_CODE (dest) == MEM)
4327 if (GET_CODE (src) == REG)
4329 int src_regno = REGNO (src);
4330 enum machine_mode mode = GET_MODE (dest);
4332 if (GPR_P (src_regno))
4340 return "stb%I0%U0 %1, %M0";
4343 return "sth%I0%U0 %1, %M0";
4347 return "st%I0%U0 %1, %M0";
4351 else if (FPR_P (src_regno))
4359 return "stbf%I0%U0 %1, %M0";
4362 return "sthf%I0%U0 %1, %M0";
4366 return "stf%I0%U0 %1, %M0";
4371 else if (ZERO_P (src))
4373 switch (GET_MODE (dest))
4379 return "stb%I0%U0 %., %M0";
4382 return "sth%I0%U0 %., %M0";
4386 return "st%I0%U0 %., %M0";
4391 fatal_insn ("Bad output_move_single operand", insn);
4396 /* Return a string to output a double word move. */
4399 output_move_double (rtx operands[], rtx insn)
4401 rtx dest = operands[0];
4402 rtx src = operands[1];
4403 enum machine_mode mode = GET_MODE (dest);
4405 if (GET_CODE (dest) == REG)
4407 int dest_regno = REGNO (dest);
4409 if (GPR_P (dest_regno))
4411 if (GET_CODE (src) == REG)
4413 /* gpr <- some sort of register */
4414 int src_regno = REGNO (src);
4416 if (GPR_P (src_regno))
4419 else if (FPR_P (src_regno))
4421 if (((dest_regno - GPR_FIRST) & 1) == 0
4422 && ((src_regno - FPR_FIRST) & 1) == 0)
4423 return "movfgd %1, %0";
4429 else if (GET_CODE (src) == MEM)
4432 if (dbl_memory_one_insn_operand (src, mode))
4433 return "ldd%I1%U1 %M1, %0";
4438 else if (GET_CODE (src) == CONST_INT
4439 || GET_CODE (src) == CONST_DOUBLE)
4443 else if (FPR_P (dest_regno))
4445 if (GET_CODE (src) == REG)
4447 /* fpr <- some sort of register */
4448 int src_regno = REGNO (src);
4450 if (GPR_P (src_regno))
4452 if (((dest_regno - FPR_FIRST) & 1) == 0
4453 && ((src_regno - GPR_FIRST) & 1) == 0)
4454 return "movgfd %1, %0";
4459 else if (FPR_P (src_regno))
4462 && ((dest_regno - FPR_FIRST) & 1) == 0
4463 && ((src_regno - FPR_FIRST) & 1) == 0)
4464 return "fmovd %1, %0";
4470 else if (GET_CODE (src) == MEM)
4473 if (dbl_memory_one_insn_operand (src, mode))
4474 return "lddf%I1%U1 %M1, %0";
4479 else if (ZERO_P (src))
4484 else if (GET_CODE (dest) == MEM)
4486 if (GET_CODE (src) == REG)
4488 int src_regno = REGNO (src);
4490 if (GPR_P (src_regno))
4492 if (((src_regno - GPR_FIRST) & 1) == 0
4493 && dbl_memory_one_insn_operand (dest, mode))
4494 return "std%I0%U0 %1, %M0";
4499 if (FPR_P (src_regno))
4501 if (((src_regno - FPR_FIRST) & 1) == 0
4502 && dbl_memory_one_insn_operand (dest, mode))
4503 return "stdf%I0%U0 %1, %M0";
4509 else if (ZERO_P (src))
4511 if (dbl_memory_one_insn_operand (dest, mode))
4512 return "std%I0%U0 %., %M0";
4518 fatal_insn ("Bad output_move_double operand", insn);
4523 /* Return a string to output a single word conditional move.
4524 Operand0 -- EQ/NE of ccr register and 0
4525 Operand1 -- CCR register
4526 Operand2 -- destination
4527 Operand3 -- source */
4530 output_condmove_single (rtx operands[], rtx insn)
4532 rtx dest = operands[2];
4533 rtx src = operands[3];
4535 if (GET_CODE (dest) == REG)
4537 int dest_regno = REGNO (dest);
4538 enum machine_mode mode = GET_MODE (dest);
4540 if (GPR_P (dest_regno))
4542 if (GET_CODE (src) == REG)
4544 /* gpr <- some sort of register */
4545 int src_regno = REGNO (src);
4547 if (GPR_P (src_regno))
4548 return "cmov %z3, %2, %1, %e0";
4550 else if (FPR_P (src_regno))
4551 return "cmovfg %3, %2, %1, %e0";
4554 else if (GET_CODE (src) == MEM)
4563 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4566 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4570 return "cld%I3%U3 %M3, %2, %1, %e0";
4574 else if (ZERO_P (src))
4575 return "cmov %., %2, %1, %e0";
4578 else if (FPR_P (dest_regno))
4580 if (GET_CODE (src) == REG)
4582 /* fpr <- some sort of register */
4583 int src_regno = REGNO (src);
4585 if (GPR_P (src_regno))
4586 return "cmovgf %3, %2, %1, %e0";
4588 else if (FPR_P (src_regno))
4590 if (TARGET_HARD_FLOAT)
4591 return "cfmovs %3,%2,%1,%e0";
4593 return "cmor %3, %3, %2, %1, %e0";
4597 else if (GET_CODE (src) == MEM)
4600 if (mode == SImode || mode == SFmode)
4601 return "cldf%I3%U3 %M3, %2, %1, %e0";
4604 else if (ZERO_P (src))
4605 return "cmovgf %., %2, %1, %e0";
4609 else if (GET_CODE (dest) == MEM)
4611 if (GET_CODE (src) == REG)
4613 int src_regno = REGNO (src);
4614 enum machine_mode mode = GET_MODE (dest);
4616 if (GPR_P (src_regno))
4624 return "cstb%I2%U2 %3, %M2, %1, %e0";
4627 return "csth%I2%U2 %3, %M2, %1, %e0";
4631 return "cst%I2%U2 %3, %M2, %1, %e0";
4635 else if (FPR_P (src_regno) && (mode == SImode || mode == SFmode))
4636 return "cstf%I2%U2 %3, %M2, %1, %e0";
4639 else if (ZERO_P (src))
4641 enum machine_mode mode = GET_MODE (dest);
4648 return "cstb%I2%U2 %., %M2, %1, %e0";
4651 return "csth%I2%U2 %., %M2, %1, %e0";
4655 return "cst%I2%U2 %., %M2, %1, %e0";
4660 fatal_insn ("Bad output_condmove_single operand", insn);
4665 /* Emit the appropriate code to do a comparison, returning the register the
4666 comparison was done it. */
4669 frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
4671 enum machine_mode cc_mode;
4674 /* Floating point doesn't have comparison against a constant. */
4675 if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
4676 op1 = force_reg (GET_MODE (op0), op1);
4678 /* Possibly disable using anything but a fixed register in order to work
4679 around cse moving comparisons past function calls. */
4680 cc_mode = SELECT_CC_MODE (test, op0, op1);
4681 cc_reg = ((TARGET_ALLOC_CC)
4682 ? gen_reg_rtx (cc_mode)
4683 : gen_rtx_REG (cc_mode,
4684 (cc_mode == CC_FPmode) ? FCC_FIRST : ICC_FIRST));
4686 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4687 gen_rtx_COMPARE (cc_mode, op0, op1)));
4693 /* Emit code for a conditional branch. The comparison operands were previously
4694 stored in frv_compare_op0 and frv_compare_op1.
4696 XXX: I originally wanted to add a clobber of a CCR register to use in
4697 conditional execution, but that confuses the rest of the compiler. */
4700 frv_emit_cond_branch (enum rtx_code test, rtx label)
4705 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4706 enum machine_mode cc_mode = GET_MODE (cc_reg);
4708 /* Branches generate:
4710 (if_then_else (<test>, <cc_reg>, (const_int 0))
4711 (label_ref <branch_label>)
4713 label_ref = gen_rtx_LABEL_REF (VOIDmode, label);
4714 test_rtx = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4715 if_else = gen_rtx_IF_THEN_ELSE (cc_mode, test_rtx, label_ref, pc_rtx);
4716 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_else));
4721 /* Emit code to set a gpr to 1/0 based on a comparison. The comparison
4722 operands were previously stored in frv_compare_op0 and frv_compare_op1. */
4725 frv_emit_scc (enum rtx_code test, rtx target)
4731 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4733 /* SCC instructions generate:
4734 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4735 (clobber (<ccr_reg>))]) */
4736 test_rtx = gen_rtx_fmt_ee (test, SImode, cc_reg, const0_rtx);
4737 set = gen_rtx_SET (VOIDmode, target, test_rtx);
4739 cr_reg = ((TARGET_ALLOC_CC)
4740 ? gen_reg_rtx (CC_CCRmode)
4741 : gen_rtx_REG (CC_CCRmode,
4742 ((GET_MODE (cc_reg) == CC_FPmode)
4746 clobber = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4747 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
4752 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4753 the separate insns. */
4756 frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
4762 /* Set the appropriate CCR bit. */
4763 emit_insn (gen_rtx_SET (VOIDmode,
4765 gen_rtx_fmt_ee (GET_CODE (test),
4770 /* Move the value into the destination. */
4771 emit_move_insn (dest, GEN_INT (value));
4773 /* Move 0 into the destination if the test failed */
4774 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4775 gen_rtx_EQ (GET_MODE (cr_reg),
4778 gen_rtx_SET (VOIDmode, dest, const0_rtx)));
4780 /* Finish up, return sequence. */
4787 /* Emit the code for a conditional move, return TRUE if we could do the
4791 frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
4798 enum rtx_code test = GET_CODE (test_rtx);
4799 rtx cc_reg = frv_emit_comparison (test, frv_compare_op0, frv_compare_op1);
4800 enum machine_mode cc_mode = GET_MODE (cc_reg);
4802 /* Conditional move instructions generate:
4803 (parallel [(set <target>
4804 (if_then_else (<test> <cc_reg> (const_int 0))
4807 (clobber (<ccr_reg>))]) */
4809 /* Handle various cases of conditional move involving two constants. */
4810 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4812 HOST_WIDE_INT value1 = INTVAL (src1);
4813 HOST_WIDE_INT value2 = INTVAL (src2);
4815 /* Having 0 as one of the constants can be done by loading the other
4816 constant, and optionally moving in gr0. */
4817 if (value1 == 0 || value2 == 0)
4820 /* If the first value is within an addi range and also the difference
4821 between the two fits in an addi's range, load up the difference, then
4822 conditionally move in 0, and then unconditionally add the first
4824 else if (IN_RANGE_P (value1, -2048, 2047)
4825 && IN_RANGE_P (value2 - value1, -2048, 2047))
4828 /* If neither condition holds, just force the constant into a
4832 src1 = force_reg (GET_MODE (dest), src1);
4833 src2 = force_reg (GET_MODE (dest), src2);
4837 /* If one value is a register, insure the other value is either 0 or a
4841 if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
4842 src1 = force_reg (GET_MODE (dest), src1);
4844 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
4845 src2 = force_reg (GET_MODE (dest), src2);
4848 test2 = gen_rtx_fmt_ee (test, cc_mode, cc_reg, const0_rtx);
4849 if_rtx = gen_rtx_IF_THEN_ELSE (GET_MODE (dest), test2, src1, src2);
4851 set = gen_rtx_SET (VOIDmode, dest, if_rtx);
4853 cr_reg = ((TARGET_ALLOC_CC)
4854 ? gen_reg_rtx (CC_CCRmode)
4855 : gen_rtx_REG (CC_CCRmode,
4856 (cc_mode == CC_FPmode) ? FCR_FIRST : ICR_FIRST));
4858 clobber_cc = gen_rtx_CLOBBER (VOIDmode, cr_reg);
4859 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber_cc)));
4864 /* Split a conditional move into constituent parts, returning a SEQUENCE
4865 containing all of the insns. */
4868 frv_split_cond_move (rtx operands[])
4870 rtx dest = operands[0];
4871 rtx test = operands[1];
4872 rtx cc_reg = operands[2];
4873 rtx src1 = operands[3];
4874 rtx src2 = operands[4];
4875 rtx cr_reg = operands[5];
4877 enum machine_mode cr_mode = GET_MODE (cr_reg);
4881 /* Set the appropriate CCR bit. */
4882 emit_insn (gen_rtx_SET (VOIDmode,
4884 gen_rtx_fmt_ee (GET_CODE (test),
4889 /* Handle various cases of conditional move involving two constants. */
4890 if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
4892 HOST_WIDE_INT value1 = INTVAL (src1);
4893 HOST_WIDE_INT value2 = INTVAL (src2);
4895 /* Having 0 as one of the constants can be done by loading the other
4896 constant, and optionally moving in gr0. */
4899 emit_move_insn (dest, src2);
4900 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4901 gen_rtx_NE (cr_mode, cr_reg,
4903 gen_rtx_SET (VOIDmode, dest, src1)));
4906 else if (value2 == 0)
4908 emit_move_insn (dest, src1);
4909 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4910 gen_rtx_EQ (cr_mode, cr_reg,
4912 gen_rtx_SET (VOIDmode, dest, src2)));
4915 /* If the first value is within an addi range and also the difference
4916 between the two fits in an addi's range, load up the difference, then
4917 conditionally move in 0, and then unconditionally add the first
4919 else if (IN_RANGE_P (value1, -2048, 2047)
4920 && IN_RANGE_P (value2 - value1, -2048, 2047))
4922 rtx dest_si = ((GET_MODE (dest) == SImode)
4924 : gen_rtx_SUBREG (SImode, dest, 0));
4926 emit_move_insn (dest_si, GEN_INT (value2 - value1));
4927 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4928 gen_rtx_NE (cr_mode, cr_reg,
4930 gen_rtx_SET (VOIDmode, dest_si,
4932 emit_insn (gen_addsi3 (dest_si, dest_si, src1));
4940 /* Emit the conditional move for the test being true if needed. */
4941 if (! rtx_equal_p (dest, src1))
4942 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4943 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
4944 gen_rtx_SET (VOIDmode, dest, src1)));
4946 /* Emit the conditional move for the test being false if needed. */
4947 if (! rtx_equal_p (dest, src2))
4948 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
4949 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
4950 gen_rtx_SET (VOIDmode, dest, src2)));
4953 /* Finish up, return sequence. */
4960 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
4961 memory location that is not known to be dword-aligned. */
4963 frv_split_double_load (rtx dest, rtx source)
4965 int regno = REGNO (dest);
4966 rtx dest1 = gen_highpart (SImode, dest);
4967 rtx dest2 = gen_lowpart (SImode, dest);
4968 rtx address = XEXP (source, 0);
4970 /* If the address is pre-modified, load the lower-numbered register
4971 first, then load the other register using an integer offset from
4972 the modified base register. This order should always be safe,
4973 since the pre-modification cannot affect the same registers as the
4976 The situation for other loads is more complicated. Loading one
4977 of the registers could affect the value of ADDRESS, so we must
4978 be careful which order we do them in. */
4979 if (GET_CODE (address) == PRE_MODIFY
4980 || ! refers_to_regno_p (regno, regno + 1, address, NULL))
4982 /* It is safe to load the lower-numbered register first. */
4983 emit_move_insn (dest1, change_address (source, SImode, NULL));
4984 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
4988 /* ADDRESS is not pre-modified and the address depends on the
4989 lower-numbered register. Load the higher-numbered register
4991 emit_move_insn (dest2, frv_index_memory (source, SImode, 1));
4992 emit_move_insn (dest1, change_address (source, SImode, NULL));
4996 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
4997 and SOURCE is either a double register or the constant zero. */
4999 frv_split_double_store (rtx dest, rtx source)
5001 rtx dest1 = change_address (dest, SImode, NULL);
5002 rtx dest2 = frv_index_memory (dest, SImode, 1);
5003 if (ZERO_P (source))
5005 emit_move_insn (dest1, CONST0_RTX (SImode));
5006 emit_move_insn (dest2, CONST0_RTX (SImode));
5010 emit_move_insn (dest1, gen_highpart (SImode, source));
5011 emit_move_insn (dest2, gen_lowpart (SImode, source));
5016 /* Split a min/max operation returning a SEQUENCE containing all of the
5020 frv_split_minmax (rtx operands[])
5022 rtx dest = operands[0];
5023 rtx minmax = operands[1];
5024 rtx src1 = operands[2];
5025 rtx src2 = operands[3];
5026 rtx cc_reg = operands[4];
5027 rtx cr_reg = operands[5];
5029 enum rtx_code test_code;
5030 enum machine_mode cr_mode = GET_MODE (cr_reg);
5034 /* Figure out which test to use. */
5035 switch (GET_CODE (minmax))
5040 case SMIN: test_code = LT; break;
5041 case SMAX: test_code = GT; break;
5042 case UMIN: test_code = LTU; break;
5043 case UMAX: test_code = GTU; break;
5046 /* Issue the compare instruction. */
5047 emit_insn (gen_rtx_SET (VOIDmode,
5049 gen_rtx_COMPARE (GET_MODE (cc_reg),
5052 /* Set the appropriate CCR bit. */
5053 emit_insn (gen_rtx_SET (VOIDmode,
5055 gen_rtx_fmt_ee (test_code,
5060 /* If are taking the min/max of a nonzero constant, load that first, and
5061 then do a conditional move of the other value. */
5062 if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
5064 if (rtx_equal_p (dest, src1))
5067 emit_move_insn (dest, src2);
5068 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5069 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5070 gen_rtx_SET (VOIDmode, dest, src1)));
5073 /* Otherwise, do each half of the move. */
5076 /* Emit the conditional move for the test being true if needed. */
5077 if (! rtx_equal_p (dest, src1))
5078 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5079 gen_rtx_NE (cr_mode, cr_reg, const0_rtx),
5080 gen_rtx_SET (VOIDmode, dest, src1)));
5082 /* Emit the conditional move for the test being false if needed. */
5083 if (! rtx_equal_p (dest, src2))
5084 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5085 gen_rtx_EQ (cr_mode, cr_reg, const0_rtx),
5086 gen_rtx_SET (VOIDmode, dest, src2)));
5089 /* Finish up, return sequence. */
5096 /* Split an integer abs operation returning a SEQUENCE containing all of the
5100 frv_split_abs (rtx operands[])
5102 rtx dest = operands[0];
5103 rtx src = operands[1];
5104 rtx cc_reg = operands[2];
5105 rtx cr_reg = operands[3];
5110 /* Issue the compare < 0 instruction. */
5111 emit_insn (gen_rtx_SET (VOIDmode,
5113 gen_rtx_COMPARE (CCmode, src, const0_rtx)));
5115 /* Set the appropriate CCR bit. */
5116 emit_insn (gen_rtx_SET (VOIDmode,
5118 gen_rtx_fmt_ee (LT, CC_CCRmode, cc_reg, const0_rtx)));
5120 /* Emit the conditional negate if the value is negative. */
5121 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5122 gen_rtx_NE (CC_CCRmode, cr_reg, const0_rtx),
5123 gen_negsi2 (dest, src)));
5125 /* Emit the conditional move for the test being false if needed. */
5126 if (! rtx_equal_p (dest, src))
5127 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
5128 gen_rtx_EQ (CC_CCRmode, cr_reg, const0_rtx),
5129 gen_rtx_SET (VOIDmode, dest, src)));
5131 /* Finish up, return sequence. */
5138 /* An internal function called by for_each_rtx to clear in a hard_reg set each
5139 register used in an insn. */
5142 frv_clear_registers_used (rtx *ptr, void *data)
5144 if (GET_CODE (*ptr) == REG)
5146 int regno = REGNO (*ptr);
5147 HARD_REG_SET *p_regs = (HARD_REG_SET *)data;
5149 if (regno < FIRST_PSEUDO_REGISTER)
5151 int reg_max = regno + HARD_REGNO_NREGS (regno, GET_MODE (*ptr));
5153 while (regno < reg_max)
5155 CLEAR_HARD_REG_BIT (*p_regs, regno);
5165 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */
5167 /* On the FR-V, we don't have any extra fields per se, but it is useful hook to
5168 initialize the static storage. */
5170 frv_ifcvt_init_extra_fields (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
5172 frv_ifcvt.added_insns_list = NULL_RTX;
5173 frv_ifcvt.cur_scratch_regs = 0;
5174 frv_ifcvt.num_nested_cond_exec = 0;
5175 frv_ifcvt.cr_reg = NULL_RTX;
5176 frv_ifcvt.nested_cc_reg = NULL_RTX;
5177 frv_ifcvt.extra_int_cr = NULL_RTX;
5178 frv_ifcvt.extra_fp_cr = NULL_RTX;
5179 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5183 /* Internal function to add a potential insn to the list of insns to be inserted
5184 if the conditional execution conversion is successful. */
5187 frv_ifcvt_add_insn (rtx pattern, rtx insn, int before_p)
5189 rtx link = alloc_EXPR_LIST (VOIDmode, pattern, insn);
5191 link->jump = before_p; /* Mark to add this before or after insn. */
5192 frv_ifcvt.added_insns_list = alloc_EXPR_LIST (VOIDmode, link,
5193 frv_ifcvt.added_insns_list);
5195 if (TARGET_DEBUG_COND_EXEC)
5198 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5199 (before_p) ? "before" : "after",
5200 (int)INSN_UID (insn));
5202 debug_rtx (pattern);
5207 /* A C expression to modify the code described by the conditional if
5208 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5209 FALSE_EXPR for converting if-then and if-then-else code to conditional
5210 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5211 tests cannot be converted. */
5214 frv_ifcvt_modify_tests (ce_if_block_t *ce_info, rtx *p_true, rtx *p_false)
5216 basic_block test_bb = ce_info->test_bb; /* test basic block */
5217 basic_block then_bb = ce_info->then_bb; /* THEN */
5218 basic_block else_bb = ce_info->else_bb; /* ELSE or NULL */
5219 basic_block join_bb = ce_info->join_bb; /* join block or NULL */
5220 rtx true_expr = *p_true;
5224 enum machine_mode mode = GET_MODE (true_expr);
5228 frv_tmp_reg_t *tmp_reg = &frv_ifcvt.tmp_reg;
5230 rtx sub_cond_exec_reg;
5232 enum rtx_code code_true;
5233 enum rtx_code code_false;
5234 enum reg_class cc_class;
5235 enum reg_class cr_class;
5238 reg_set_iterator rsi;
5240 /* Make sure we are only dealing with hard registers. Also honor the
5241 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5243 if (!reload_completed || !TARGET_COND_EXEC
5244 || (!TARGET_NESTED_CE && ce_info->pass > 1))
5247 /* Figure out which registers we can allocate for our own purposes. Only
5248 consider registers that are not preserved across function calls and are
5249 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5250 if we did not need to use them in reloading other registers. */
5251 memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
5252 COPY_HARD_REG_SET (tmp_reg->regs, call_used_reg_set);
5253 AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
5254 SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
5255 SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
5257 /* If this is a nested IF, we need to discover whether the CC registers that
5258 are set/used inside of the block are used anywhere else. If not, we can
5259 change them to be the CC register that is paired with the CR register that
5260 controls the outermost IF block. */
5261 if (ce_info->pass > 1)
5263 CLEAR_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite);
5264 for (j = CC_FIRST; j <= CC_LAST; j++)
5265 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5267 if (REGNO_REG_SET_P (then_bb->global_live_at_start, j))
5270 if (else_bb && REGNO_REG_SET_P (else_bb->global_live_at_start, j))
5273 if (join_bb && REGNO_REG_SET_P (join_bb->global_live_at_start, j))
5276 SET_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j);
5280 for (j = 0; j < frv_ifcvt.cur_scratch_regs; j++)
5281 frv_ifcvt.scratch_regs[j] = NULL_RTX;
5283 frv_ifcvt.added_insns_list = NULL_RTX;
5284 frv_ifcvt.cur_scratch_regs = 0;
5286 bb = (basic_block *) alloca ((2 + ce_info->num_multiple_test_blocks)
5287 * sizeof (basic_block));
5293 /* Remove anything live at the beginning of the join block from being
5294 available for allocation. */
5295 EXECUTE_IF_SET_IN_REG_SET (join_bb->global_live_at_start, 0, regno, rsi)
5297 if (regno < FIRST_PSEUDO_REGISTER)
5298 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5302 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5304 if (ce_info->num_multiple_test_blocks)
5306 basic_block multiple_test_bb = ce_info->last_test_bb;
5308 while (multiple_test_bb != test_bb)
5310 bb[num_bb++] = multiple_test_bb;
5311 multiple_test_bb = EDGE_PRED (multiple_test_bb, 0)->src;
5315 /* Add in the THEN and ELSE blocks to be scanned. */
5316 bb[num_bb++] = then_bb;
5318 bb[num_bb++] = else_bb;
5320 sub_cond_exec_reg = NULL_RTX;
5321 frv_ifcvt.num_nested_cond_exec = 0;
5323 /* Scan all of the blocks for registers that must not be allocated. */
5324 for (j = 0; j < num_bb; j++)
5326 rtx last_insn = BB_END (bb[j]);
5327 rtx insn = BB_HEAD (bb[j]);
5331 fprintf (dump_file, "Scanning %s block %d, start %d, end %d\n",
5332 (bb[j] == else_bb) ? "else" : ((bb[j] == then_bb) ? "then" : "test"),
5334 (int) INSN_UID (BB_HEAD (bb[j])),
5335 (int) INSN_UID (BB_END (bb[j])));
5337 /* Anything live at the beginning of the block is obviously unavailable
5339 EXECUTE_IF_SET_IN_REG_SET (bb[j]->global_live_at_start, 0, regno, rsi)
5341 if (regno < FIRST_PSEUDO_REGISTER)
5342 CLEAR_HARD_REG_BIT (tmp_reg->regs, regno);
5345 /* Loop through the insns in the block. */
5348 /* Mark any new registers that are created as being unavailable for
5349 allocation. Also see if the CC register used in nested IFs can be
5355 int skip_nested_if = FALSE;
5357 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5358 (void *)&tmp_reg->regs);
5360 pattern = PATTERN (insn);
5361 if (GET_CODE (pattern) == COND_EXEC)
5363 rtx reg = XEXP (COND_EXEC_TEST (pattern), 0);
5365 if (reg != sub_cond_exec_reg)
5367 sub_cond_exec_reg = reg;
5368 frv_ifcvt.num_nested_cond_exec++;
5372 set = single_set_pattern (pattern);
5375 rtx dest = SET_DEST (set);
5376 rtx src = SET_SRC (set);
5378 if (GET_CODE (dest) == REG)
5380 int regno = REGNO (dest);
5381 enum rtx_code src_code = GET_CODE (src);
5383 if (CC_P (regno) && src_code == COMPARE)
5384 skip_nested_if = TRUE;
5386 else if (CR_P (regno)
5387 && (src_code == IF_THEN_ELSE
5388 || COMPARISON_P (src)))
5389 skip_nested_if = TRUE;
5393 if (! skip_nested_if)
5394 for_each_rtx (&PATTERN (insn), frv_clear_registers_used,
5395 (void *)&frv_ifcvt.nested_cc_ok_rewrite);
5398 if (insn == last_insn)
5401 insn = NEXT_INSN (insn);
5405 /* If this is a nested if, rewrite the CC registers that are available to
5406 include the ones that can be rewritten, to increase the chance of being
5407 able to allocate a paired CC/CR register combination. */
5408 if (ce_info->pass > 1)
5410 for (j = CC_FIRST; j <= CC_LAST; j++)
5411 if (TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, j))
5412 SET_HARD_REG_BIT (tmp_reg->regs, j);
5414 CLEAR_HARD_REG_BIT (tmp_reg->regs, j);
5420 fprintf (dump_file, "Available GPRs: ");
5422 for (j = GPR_FIRST; j <= GPR_LAST; j++)
5423 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5425 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5426 if (++num_gprs > GPR_TEMP_NUM+2)
5430 fprintf (dump_file, "%s\nAvailable CRs: ",
5431 (num_gprs > GPR_TEMP_NUM+2) ? " ..." : "");
5433 for (j = CR_FIRST; j <= CR_LAST; j++)
5434 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5435 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5437 fputs ("\n", dump_file);
5439 if (ce_info->pass > 1)
5441 fprintf (dump_file, "Modifiable CCs: ");
5442 for (j = CC_FIRST; j <= CC_LAST; j++)
5443 if (TEST_HARD_REG_BIT (tmp_reg->regs, j))
5444 fprintf (dump_file, " %d [%s]", j, reg_names[j]);
5446 fprintf (dump_file, "\n%d nested COND_EXEC statements\n",
5447 frv_ifcvt.num_nested_cond_exec);
5451 /* Allocate the appropriate temporary condition code register. Try to
5452 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5453 that conditional cmp's can be done. */
5454 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5456 cr_class = ICR_REGS;
5457 cc_class = ICC_REGS;
5458 cc_first = ICC_FIRST;
5461 else if (mode == CC_FPmode)
5463 cr_class = FCR_REGS;
5464 cc_class = FCC_REGS;
5465 cc_first = FCC_FIRST;
5470 cc_first = cc_last = 0;
5471 cr_class = cc_class = NO_REGS;
5474 cc = XEXP (true_expr, 0);
5475 nested_cc = cr = NULL_RTX;
5476 if (cc_class != NO_REGS)
5478 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5479 so we can execute a csubcc/caddcc/cfcmps instruction. */
5482 for (cc_regno = cc_first; cc_regno <= cc_last; cc_regno++)
5484 int cr_regno = cc_regno - CC_FIRST + CR_FIRST;
5486 if (TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cc_regno)
5487 && TEST_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, cr_regno))
5489 frv_ifcvt.tmp_reg.next_reg[ (int)cr_class ] = cr_regno;
5490 cr = frv_alloc_temp_reg (tmp_reg, cr_class, CC_CCRmode, TRUE,
5493 frv_ifcvt.tmp_reg.next_reg[ (int)cc_class ] = cc_regno;
5494 nested_cc = frv_alloc_temp_reg (tmp_reg, cc_class, CCmode,
5504 fprintf (dump_file, "Could not allocate a CR temporary register\n");
5511 "Will use %s for conditional execution, %s for nested comparisons\n",
5512 reg_names[ REGNO (cr)],
5513 (nested_cc) ? reg_names[ REGNO (nested_cc) ] : "<none>");
5515 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5516 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5517 bit being true. We don't do this for floating point, because of NaNs. */
5518 code = GET_CODE (true_expr);
5519 if (GET_MODE (cc) != CC_FPmode)
5521 code = reverse_condition (code);
5531 check_insn = gen_rtx_SET (VOIDmode, cr,
5532 gen_rtx_fmt_ee (code, CC_CCRmode, cc, const0_rtx));
5534 /* Record the check insn to be inserted later. */
5535 frv_ifcvt_add_insn (check_insn, BB_END (test_bb), TRUE);
5537 /* Update the tests. */
5538 frv_ifcvt.cr_reg = cr;
5539 frv_ifcvt.nested_cc_reg = nested_cc;
5540 *p_true = gen_rtx_fmt_ee (code_true, CC_CCRmode, cr, const0_rtx);
5541 *p_false = gen_rtx_fmt_ee (code_false, CC_CCRmode, cr, const0_rtx);
5544 /* Fail, don't do this conditional execution. */
5547 *p_false = NULL_RTX;
5549 fprintf (dump_file, "Disabling this conditional execution.\n");
5555 /* A C expression to modify the code described by the conditional if
5556 information CE_INFO, for the basic block BB, possibly updating the tests in
5557 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5558 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5559 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5561 /* p_true and p_false are given expressions of the form:
5563 (and (eq:CC_CCR (reg:CC_CCR)
5569 frv_ifcvt_modify_multiple_tests (ce_if_block_t *ce_info,
5574 rtx old_true = XEXP (*p_true, 0);
5575 rtx old_false = XEXP (*p_false, 0);
5576 rtx true_expr = XEXP (*p_true, 1);
5577 rtx false_expr = XEXP (*p_false, 1);
5580 rtx cr = XEXP (old_true, 0);
5582 rtx new_cr = NULL_RTX;
5583 rtx *p_new_cr = (rtx *)0;
5587 enum reg_class cr_class;
5588 enum machine_mode mode = GET_MODE (true_expr);
5589 rtx (*logical_func)(rtx, rtx, rtx);
5591 if (TARGET_DEBUG_COND_EXEC)
5594 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5595 ce_info->and_and_p ? "&&" : "||");
5597 debug_rtx (*p_true);
5599 fputs ("\nfalse insn:\n", stderr);
5600 debug_rtx (*p_false);
5603 if (!TARGET_MULTI_CE)
5606 if (GET_CODE (cr) != REG)
5609 if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
5611 cr_class = ICR_REGS;
5612 p_new_cr = &frv_ifcvt.extra_int_cr;
5614 else if (mode == CC_FPmode)
5616 cr_class = FCR_REGS;
5617 p_new_cr = &frv_ifcvt.extra_fp_cr;
5622 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5623 more &&/|| tests. */
5627 new_cr = *p_new_cr = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, cr_class,
5628 CC_CCRmode, TRUE, TRUE);
5633 if (ce_info->and_and_p)
5635 old_test = old_false;
5636 test_expr = true_expr;
5637 logical_func = (GET_CODE (old_true) == EQ) ? gen_andcr : gen_andncr;
5638 *p_true = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5639 *p_false = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5643 old_test = old_false;
5644 test_expr = false_expr;
5645 logical_func = (GET_CODE (old_false) == EQ) ? gen_orcr : gen_orncr;
5646 *p_true = gen_rtx_EQ (CC_CCRmode, cr, const0_rtx);
5647 *p_false = gen_rtx_NE (CC_CCRmode, cr, const0_rtx);
5650 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5651 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5653 frv_ifcvt_add_insn ((*logical_func) (cr, cr, new_cr), BB_END (bb), TRUE);
5655 /* Now add the conditional check insn. */
5656 cc = XEXP (test_expr, 0);
5657 compare = gen_rtx_fmt_ee (GET_CODE (test_expr), CC_CCRmode, cc, const0_rtx);
5658 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, old_test, compare, const0_rtx);
5660 check_insn = gen_rtx_SET (VOIDmode, new_cr, if_else);
5662 /* Add the new check insn to the list of check insns that need to be
5664 frv_ifcvt_add_insn (check_insn, BB_END (bb), TRUE);
5666 if (TARGET_DEBUG_COND_EXEC)
5668 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5671 debug_rtx (*p_true);
5673 fputs ("\nfalse insn:\n", stderr);
5674 debug_rtx (*p_false);
5680 *p_true = *p_false = NULL_RTX;
5682 /* If we allocated a CR register, release it. */
5685 CLEAR_HARD_REG_BIT (frv_ifcvt.tmp_reg.regs, REGNO (new_cr));
5686 *p_new_cr = NULL_RTX;
5689 if (TARGET_DEBUG_COND_EXEC)
5690 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr);
5696 /* Return a register which will be loaded with a value if an IF block is
5697 converted to conditional execution. This is used to rewrite instructions
5698 that use constants to ones that just use registers. */
5701 frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
5703 int num_alloc = frv_ifcvt.cur_scratch_regs;
5707 /* We know gr0 == 0, so replace any errant uses. */
5708 if (value == const0_rtx)
5709 return gen_rtx_REG (SImode, GPR_FIRST);
5711 /* First search all registers currently loaded to see if we have an
5712 applicable constant. */
5713 if (CONSTANT_P (value)
5714 || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
5716 for (i = 0; i < num_alloc; i++)
5718 if (rtx_equal_p (SET_SRC (frv_ifcvt.scratch_regs[i]), value))
5719 return SET_DEST (frv_ifcvt.scratch_regs[i]);
5723 /* Have we exhausted the number of registers available? */
5724 if (num_alloc >= GPR_TEMP_NUM)
5727 fprintf (dump_file, "Too many temporary registers allocated\n");
5732 /* Allocate the new register. */
5733 reg = frv_alloc_temp_reg (&frv_ifcvt.tmp_reg, GPR_REGS, SImode, TRUE, TRUE);
5737 fputs ("Could not find a scratch register\n", dump_file);
5742 frv_ifcvt.cur_scratch_regs++;
5743 frv_ifcvt.scratch_regs[num_alloc] = gen_rtx_SET (VOIDmode, reg, value);
5747 if (GET_CODE (value) == CONST_INT)
5748 fprintf (dump_file, "Register %s will hold %ld\n",
5749 reg_names[ REGNO (reg)], (long)INTVAL (value));
5751 else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
5752 fprintf (dump_file, "Register %s will hold LR\n",
5753 reg_names[ REGNO (reg)]);
5756 fprintf (dump_file, "Register %s will hold a saved value\n",
5757 reg_names[ REGNO (reg)]);
5764 /* Update a MEM used in conditional code that might contain an offset to put
5765 the offset into a scratch register, so that the conditional load/store
5766 operations can be used. This function returns the original pointer if the
5767 MEM is valid to use in conditional code, NULL if we can't load up the offset
5768 into a temporary register, or the new MEM if we were successful. */
5771 frv_ifcvt_rewrite_mem (rtx mem, enum machine_mode mode, rtx insn)
5773 rtx addr = XEXP (mem, 0);
5775 if (!frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE))
5777 if (GET_CODE (addr) == PLUS)
5779 rtx addr_op0 = XEXP (addr, 0);
5780 rtx addr_op1 = XEXP (addr, 1);
5782 if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
5784 rtx reg = frv_ifcvt_load_value (addr_op1, insn);
5788 addr = gen_rtx_PLUS (Pmode, addr_op0, reg);
5795 else if (CONSTANT_P (addr))
5796 addr = frv_ifcvt_load_value (addr, insn);
5801 if (addr == NULL_RTX)
5804 else if (XEXP (mem, 0) != addr)
5805 return change_address (mem, mode, addr);
5812 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5813 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5816 single_set_pattern (rtx pattern)
5821 if (GET_CODE (pattern) == COND_EXEC)
5822 pattern = COND_EXEC_CODE (pattern);
5824 if (GET_CODE (pattern) == SET)
5827 else if (GET_CODE (pattern) == PARALLEL)
5829 for (i = 0, set = 0; i < XVECLEN (pattern, 0); i++)
5831 rtx sub = XVECEXP (pattern, 0, i);
5833 switch (GET_CODE (sub))
5857 /* A C expression to modify the code described by the conditional if
5858 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5859 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5860 insn cannot be converted to be executed conditionally. */
5863 frv_ifcvt_modify_insn (ce_if_block_t *ce_info,
5867 rtx orig_ce_pattern = pattern;
5873 if (GET_CODE (pattern) != COND_EXEC)
5876 test = COND_EXEC_TEST (pattern);
5877 if (GET_CODE (test) == AND)
5879 rtx cr = frv_ifcvt.cr_reg;
5882 op0 = XEXP (test, 0);
5883 if (! rtx_equal_p (cr, XEXP (op0, 0)))
5886 op1 = XEXP (test, 1);
5887 test_reg = XEXP (op1, 0);
5888 if (GET_CODE (test_reg) != REG)
5891 /* Is this the first nested if block in this sequence? If so, generate
5892 an andcr or andncr. */
5893 if (! frv_ifcvt.last_nested_if_cr)
5897 frv_ifcvt.last_nested_if_cr = test_reg;
5898 if (GET_CODE (op0) == NE)
5899 and_op = gen_andcr (test_reg, cr, test_reg);
5901 and_op = gen_andncr (test_reg, cr, test_reg);
5903 frv_ifcvt_add_insn (and_op, insn, TRUE);
5906 /* If this isn't the first statement in the nested if sequence, see if we
5907 are dealing with the same register. */
5908 else if (! rtx_equal_p (test_reg, frv_ifcvt.last_nested_if_cr))
5911 COND_EXEC_TEST (pattern) = test = op1;
5914 /* If this isn't a nested if, reset state variables. */
5917 frv_ifcvt.last_nested_if_cr = NULL_RTX;
5920 set = single_set_pattern (pattern);
5923 rtx dest = SET_DEST (set);
5924 rtx src = SET_SRC (set);
5925 enum machine_mode mode = GET_MODE (dest);
5927 /* Check for normal binary operators. */
5928 if (mode == SImode && ARITHMETIC_P (src))
5930 op0 = XEXP (src, 0);
5931 op1 = XEXP (src, 1);
5933 if (integer_register_operand (op0, SImode) && CONSTANT_P (op1))
5935 op1 = frv_ifcvt_load_value (op1, insn);
5937 COND_EXEC_CODE (pattern)
5938 = gen_rtx_SET (VOIDmode, dest, gen_rtx_fmt_ee (GET_CODE (src),
5946 /* For multiply by a constant, we need to handle the sign extending
5947 correctly. Add a USE of the value after the multiply to prevent flow
5948 from cratering because only one register out of the two were used. */
5949 else if (mode == DImode && GET_CODE (src) == MULT)
5951 op0 = XEXP (src, 0);
5952 op1 = XEXP (src, 1);
5953 if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
5955 op1 = frv_ifcvt_load_value (op1, insn);
5958 op1 = gen_rtx_SIGN_EXTEND (DImode, op1);
5959 COND_EXEC_CODE (pattern)
5960 = gen_rtx_SET (VOIDmode, dest,
5961 gen_rtx_MULT (DImode, op0, op1));
5967 frv_ifcvt_add_insn (gen_rtx_USE (VOIDmode, dest), insn, FALSE);
5970 /* If we are just loading a constant created for a nested conditional
5971 execution statement, just load the constant without any conditional
5972 execution, since we know that the constant will not interfere with any
5974 else if (frv_ifcvt.scratch_insns_bitmap
5975 && bitmap_bit_p (frv_ifcvt.scratch_insns_bitmap,
5977 && REG_P (SET_DEST (set))
5978 /* We must not unconditionally set a scratch reg chosen
5979 for a nested if-converted block if its incoming
5980 value from the TEST block (or the result of the THEN
5981 branch) could/should propagate to the JOIN block.
5982 It suffices to test whether the register is live at
5983 the JOIN point: if it's live there, we can infer
5984 that we set it in the former JOIN block of the
5985 nested if-converted block (otherwise it wouldn't
5986 have been available as a scratch register), and it
5987 is either propagated through or set in the other
5988 conditional block. It's probably not worth trying
5989 to catch the latter case, and it could actually
5990 limit scheduling of the combined block quite
5993 && ! (REGNO_REG_SET_P
5994 (ce_info->join_bb->global_live_at_start,
5995 REGNO (SET_DEST (set))))
5996 /* Similarly, we must not unconditionally set a reg
5997 used as scratch in the THEN branch if the same reg
5998 is live in the ELSE branch. */
5999 && (! ce_info->else_bb
6000 || BLOCK_FOR_INSN (insn) == ce_info->else_bb
6001 || ! (REGNO_REG_SET_P
6002 (ce_info->else_bb->global_live_at_start,
6003 REGNO (SET_DEST (set))))))
6006 else if (mode == QImode || mode == HImode || mode == SImode
6009 int changed_p = FALSE;
6011 /* Check for just loading up a constant */
6012 if (CONSTANT_P (src) && integer_register_operand (dest, mode))
6014 src = frv_ifcvt_load_value (src, insn);
6021 /* See if we need to fix up stores */
6022 if (GET_CODE (dest) == MEM)
6024 rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
6029 else if (new_mem != dest)
6036 /* See if we need to fix up loads */
6037 if (GET_CODE (src) == MEM)
6039 rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
6044 else if (new_mem != src)
6051 /* If either src or destination changed, redo SET. */
6053 COND_EXEC_CODE (pattern) = gen_rtx_SET (VOIDmode, dest, src);
6056 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6057 rewriting the CC register to be the same as the paired CC/CR register
6059 else if (mode == CC_CCRmode && COMPARISON_P (src))
6061 int regno = REGNO (XEXP (src, 0));
6064 if (ce_info->pass > 1
6065 && regno != (int)REGNO (frv_ifcvt.nested_cc_reg)
6066 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite, regno))
6068 src = gen_rtx_fmt_ee (GET_CODE (src),
6070 frv_ifcvt.nested_cc_reg,
6074 if_else = gen_rtx_IF_THEN_ELSE (CC_CCRmode, test, src, const0_rtx);
6075 pattern = gen_rtx_SET (VOIDmode, dest, if_else);
6078 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6079 else if (ce_info->pass > 1
6080 && GET_CODE (dest) == REG
6081 && CC_P (REGNO (dest))
6082 && REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
6083 && TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
6085 && GET_CODE (src) == COMPARE)
6087 PUT_MODE (frv_ifcvt.nested_cc_reg, GET_MODE (dest));
6088 COND_EXEC_CODE (pattern)
6089 = gen_rtx_SET (VOIDmode, frv_ifcvt.nested_cc_reg, copy_rtx (src));
6093 if (TARGET_DEBUG_COND_EXEC)
6095 rtx orig_pattern = PATTERN (insn);
6097 PATTERN (insn) = pattern;
6099 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6103 PATTERN (insn) = orig_pattern;
6109 if (TARGET_DEBUG_COND_EXEC)
6111 rtx orig_pattern = PATTERN (insn);
6113 PATTERN (insn) = orig_ce_pattern;
6115 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6119 PATTERN (insn) = orig_pattern;
6126 /* A C expression to perform any final machine dependent modifications in
6127 converting code to conditional execution in the code described by the
6128 conditional if information CE_INFO. */
6131 frv_ifcvt_modify_final (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6135 rtx p = frv_ifcvt.added_insns_list;
6138 /* Loop inserting the check insns. The last check insn is the first test,
6139 and is the appropriate place to insert constants. */
6145 rtx check_and_insert_insns = XEXP (p, 0);
6148 check_insn = XEXP (check_and_insert_insns, 0);
6149 existing_insn = XEXP (check_and_insert_insns, 1);
6152 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6153 the existing insn, otherwise it is to be inserted AFTER. */
6154 if (check_and_insert_insns->jump)
6156 emit_insn_before (check_insn, existing_insn);
6157 check_and_insert_insns->jump = 0;
6160 emit_insn_after (check_insn, existing_insn);
6162 free_EXPR_LIST_node (check_and_insert_insns);
6163 free_EXPR_LIST_node (old_p);
6165 while (p != NULL_RTX);
6167 /* Load up any constants needed into temp gprs */
6168 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6170 rtx insn = emit_insn_before (frv_ifcvt.scratch_regs[i], existing_insn);
6171 if (! frv_ifcvt.scratch_insns_bitmap)
6172 frv_ifcvt.scratch_insns_bitmap = BITMAP_ALLOC (NULL);
6173 bitmap_set_bit (frv_ifcvt.scratch_insns_bitmap, INSN_UID (insn));
6174 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6177 frv_ifcvt.added_insns_list = NULL_RTX;
6178 frv_ifcvt.cur_scratch_regs = 0;
6182 /* A C expression to cancel any machine dependent modifications in converting
6183 code to conditional execution in the code described by the conditional if
6184 information CE_INFO. */
6187 frv_ifcvt_modify_cancel (ce_if_block_t *ce_info ATTRIBUTE_UNUSED)
6190 rtx p = frv_ifcvt.added_insns_list;
6192 /* Loop freeing up the EXPR_LIST's allocated. */
6193 while (p != NULL_RTX)
6195 rtx check_and_jump = XEXP (p, 0);
6199 free_EXPR_LIST_node (check_and_jump);
6200 free_EXPR_LIST_node (old_p);
6203 /* Release any temporary gprs allocated. */
6204 for (i = 0; i < frv_ifcvt.cur_scratch_regs; i++)
6205 frv_ifcvt.scratch_regs[i] = NULL_RTX;
6207 frv_ifcvt.added_insns_list = NULL_RTX;
6208 frv_ifcvt.cur_scratch_regs = 0;
6212 /* A C expression for the size in bytes of the trampoline, as an integer.
6216 setlo #0, <static_chain>
6218 sethi #0, <static_chain>
6219 jmpl @(gr0,<jmp_reg>) */
6222 frv_trampoline_size (void)
6225 /* Allocate room for the function descriptor and the lddi
6228 return 5 /* instructions */ * 4 /* instruction size. */;
6232 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6233 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6234 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6235 should be passed to the function when it is called.
6240 setlo #0, <static_chain>
6242 sethi #0, <static_chain>
6243 jmpl @(gr0,<jmp_reg>) */
6246 frv_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
6248 rtx sc_reg = force_reg (Pmode, static_chain);
6250 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
6253 GEN_INT (frv_trampoline_size ()), SImode,
6259 /* Many machines have some registers that cannot be copied directly to or from
6260 memory or even from other types of registers. An example is the `MQ'
6261 register, which on most machines, can only be copied to or from general
6262 registers, but not memory. Some machines allow copying all registers to and
6263 from memory, but require a scratch register for stores to some memory
6264 locations (e.g., those with symbolic address on the RT, and those with
6265 certain symbolic address on the SPARC when compiling PIC). In some cases,
6266 both an intermediate and a scratch register are required.
6268 You should define these macros to indicate to the reload phase that it may
6269 need to allocate at least one register for a reload in addition to the
6270 register to contain the data. Specifically, if copying X to a register
6271 CLASS in MODE requires an intermediate register, you should define
6272 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6273 whose registers can be used as intermediate registers or scratch registers.
6275 If copying a register CLASS in MODE to X requires an intermediate or scratch
6276 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6277 largest register class required. If the requirements for input and output
6278 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6279 instead of defining both macros identically.
6281 The values returned by these macros are often `GENERAL_REGS'. Return
6282 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6283 to or from a register of CLASS in MODE without requiring a scratch register.
6284 Do not define this macro if it would always return `NO_REGS'.
6286 If a scratch register is required (either with or without an intermediate
6287 register), you should define patterns for `reload_inM' or `reload_outM', as
6288 required.. These patterns, which will normally be implemented with a
6289 `define_expand', should be similar to the `movM' patterns, except that
6290 operand 2 is the scratch register.
6292 Define constraints for the reload register and scratch register that contain
6293 a single register class. If the original reload register (whose class is
6294 CLASS) can meet the constraint given in the pattern, the value returned by
6295 these macros is used for the class of the scratch register. Otherwise, two
6296 additional reload registers are required. Their classes are obtained from
6297 the constraints in the insn pattern.
6299 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6300 either be in a hard register or in memory. Use `true_regnum' to find out;
6301 it will return -1 if the pseudo is in memory and the hard register number if
6302 it is in a register.
6304 These macros should not be used in the case where a particular class of
6305 registers can only be copied to memory and not to another class of
6306 registers. In that case, secondary reload registers are not needed and
6307 would not be helpful. Instead, a stack location must be used to perform the
6308 copy and the `movM' pattern should use memory as an intermediate storage.
6309 This case often occurs between floating-point and general registers. */
6312 frv_secondary_reload_class (enum reg_class class,
6313 enum machine_mode mode ATTRIBUTE_UNUSED,
6315 int in_p ATTRIBUTE_UNUSED)
6325 /* Accumulators/Accumulator guard registers need to go through floating
6331 if (x && GET_CODE (x) == REG)
6333 int regno = REGNO (x);
6335 if (ACC_P (regno) || ACCG_P (regno))
6340 /* Nonzero constants should be loaded into an FPR through a GPR. */
6344 if (x && CONSTANT_P (x) && !ZERO_P (x))
6350 /* All of these types need gpr registers. */
6362 /* The accumulators need fpr registers */
6375 /* A C expression whose value is nonzero if pseudos that have been assigned to
6376 registers of class CLASS would likely be spilled because registers of CLASS
6377 are needed for spill registers.
6379 The default value of this macro returns 1 if CLASS has exactly one register
6380 and zero otherwise. On most machines, this default should be used. Only
6381 define this macro to some other expression if pseudo allocated by
6382 `local-alloc.c' end up in memory because their hard registers were needed
6383 for spill registers. If this macro returns nonzero for those classes, those
6384 pseudos will only be allocated by `global.c', which knows how to reallocate
6385 the pseudo to another register. If there would not be another register
6386 available for reallocation, you should not change the definition of this
6387 macro since the only effect of such a definition would be to slow down
6388 register allocation. */
6391 frv_class_likely_spilled_p (enum reg_class class)
6401 case FDPIC_FPTR_REGS:
6423 /* An expression for the alignment of a structure field FIELD if the
6424 alignment computed in the usual way is COMPUTED. GCC uses this
6425 value instead of the value in `BIGGEST_ALIGNMENT' or
6426 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6428 /* The definition type of the bit field data is either char, short, long or
6429 long long. The maximum bit size is the number of bits of its own type.
6431 The bit field data is assigned to a storage unit that has an adequate size
6432 for bit field data retention and is located at the smallest address.
6434 Consecutive bit field data are packed at consecutive bits having the same
6435 storage unit, with regard to the type, beginning with the MSB and continuing
6438 If a field to be assigned lies over a bit field type boundary, its
6439 assignment is completed by aligning it with a boundary suitable for the
6442 When a bit field having a bit length of 0 is declared, it is forcibly
6443 assigned to the next storage unit.
6456 &x 00000000 00000000 00000000 00000000
6459 &x+4 00000000 00000000 00000000 00000000
6462 &x+8 00000000 00000000 00000000 00000000
6465 &x+12 00000000 00000000 00000000 00000000
6471 frv_adjust_field_align (tree field, int computed)
6473 /* Make sure that the bitfield is not wider than the type. */
6474 if (DECL_BIT_FIELD (field)
6475 && !DECL_ARTIFICIAL (field))
6477 tree parent = DECL_CONTEXT (field);
6478 tree prev = NULL_TREE;
6481 for (cur = TYPE_FIELDS (parent); cur && cur != field; cur = TREE_CHAIN (cur))
6483 if (TREE_CODE (cur) != FIELD_DECL)
6492 /* If this isn't a :0 field and if the previous element is a bitfield
6493 also, see if the type is different, if so, we will need to align the
6494 bit-field to the next boundary. */
6496 && ! DECL_PACKED (field)
6497 && ! integer_zerop (DECL_SIZE (field))
6498 && DECL_BIT_FIELD_TYPE (field) != DECL_BIT_FIELD_TYPE (prev))
6500 int prev_align = TYPE_ALIGN (TREE_TYPE (prev));
6501 int cur_align = TYPE_ALIGN (TREE_TYPE (field));
6502 computed = (prev_align > cur_align) ? prev_align : cur_align;
6510 /* A C expression that is nonzero if it is permissible to store a value of mode
6511 MODE in hard register number REGNO (or in several registers starting with
6512 that one). For a machine where all registers are equivalent, a suitable
6515 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6517 It is not necessary for this macro to check for the numbers of fixed
6518 registers, because the allocation mechanism considers them to be always
6521 On some machines, double-precision values must be kept in even/odd register
6522 pairs. The way to implement that is to define this macro to reject odd
6523 register numbers for such modes.
6525 The minimum requirement for a mode to be OK in a register is that the
6526 `movMODE' instruction pattern support moves between the register and any
6527 other hard register for which the mode is OK; and that moving a value into
6528 the register and back out not alter it.
6530 Since the same instruction used to move `SImode' will work for all narrower
6531 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6532 to distinguish between these modes, provided you define patterns `movhi',
6533 etc., to take advantage of this. This is useful because of the interaction
6534 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6535 all integer modes to be tieable.
6537 Many machines have special registers for floating point arithmetic. Often
6538 people assume that floating point machine modes are allowed only in floating
6539 point registers. This is not true. Any registers that can hold integers
6540 can safely *hold* a floating point machine mode, whether or not floating
6541 arithmetic can be done on it in those registers. Integer move instructions
6542 can be used to move the values.
6544 On some machines, though, the converse is true: fixed-point machine modes
6545 may not go in floating registers. This is true if the floating registers
6546 normalize any value stored in them, because storing a non-floating value
6547 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6548 fixed-point machine modes in floating registers. But if the floating
6549 registers do not automatically normalize, if you can store any bit pattern
6550 in one and retrieve it unchanged without a trap, then any machine mode may
6551 go in a floating register, so you can define this macro to say so.
6553 The primary significance of special floating registers is rather that they
6554 are the registers acceptable in floating point arithmetic instructions.
6555 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6556 writing the proper constraints for those instructions.
6558 On some machines, the floating registers are especially slow to access, so
6559 that it is better to store a value in a stack frame than in such a register
6560 if floating point arithmetic is not being done. As long as the floating
6561 registers are not in class `GENERAL_REGS', they will not be used unless some
6562 pattern's constraint asks for one. */
6565 frv_hard_regno_mode_ok (int regno, enum machine_mode mode)
6575 return ICC_P (regno) || GPR_P (regno);
6578 return CR_P (regno) || GPR_P (regno);
6581 return FCC_P (regno) || GPR_P (regno);
6587 /* Set BASE to the first register in REGNO's class. Set MASK to the
6588 bits that must be clear in (REGNO - BASE) for the register to be
6590 if (INTEGRAL_MODE_P (mode) || FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode))
6594 /* ACCGs store one byte. Two-byte quantities must start in
6595 even-numbered registers, four-byte ones in registers whose
6596 numbers are divisible by four, and so on. */
6598 mask = GET_MODE_SIZE (mode) - 1;
6602 /* The other registers store one word. */
6603 if (GPR_P (regno) || regno == AP_FIRST)
6606 else if (FPR_P (regno))
6609 else if (ACC_P (regno))
6612 else if (SPR_P (regno))
6613 return mode == SImode;
6615 /* Fill in the table. */
6619 /* Anything smaller than an SI is OK in any word-sized register. */
6620 if (GET_MODE_SIZE (mode) < 4)
6623 mask = (GET_MODE_SIZE (mode) / 4) - 1;
6625 return (((regno - base) & mask) == 0);
6632 /* A C expression for the number of consecutive hard registers, starting at
6633 register number REGNO, required to hold a value of mode MODE.
6635 On a machine where all registers are exactly one word, a suitable definition
6638 #define HARD_REGNO_NREGS(REGNO, MODE) \
6639 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6640 / UNITS_PER_WORD)) */
6642 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6643 that we can build the appropriate instructions to properly reload the
6644 values. Also, make the byte-sized accumulator guards use one guard
6648 frv_hard_regno_nregs (int regno, enum machine_mode mode)
6651 return GET_MODE_SIZE (mode);
6653 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6657 /* A C expression for the maximum number of consecutive registers of
6658 class CLASS needed to hold a value of mode MODE.
6660 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6661 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of
6662 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS.
6664 This macro helps control the handling of multiple-word values in
6667 This declaration is required. */
6670 frv_class_max_nregs (enum reg_class class, enum machine_mode mode)
6672 if (class == ACCG_REGS)
6673 /* An N-byte value requires N accumulator guards. */
6674 return GET_MODE_SIZE (mode);
6676 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6680 /* A C expression that is nonzero if X is a legitimate constant for an
6681 immediate operand on the target machine. You can assume that X satisfies
6682 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6683 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6686 frv_legitimate_constant_p (rtx x)
6688 enum machine_mode mode = GET_MODE (x);
6690 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6691 means that the move expanders will be expected to deal with most
6692 kinds of constant, regardless of what we return here.
6694 However, among its other duties, LEGITIMATE_CONSTANT_P decides whether
6695 a constant can be entered into reg_equiv_constant[]. If we return true,
6696 reload can create new instances of the constant whenever it likes.
6698 The idea is therefore to accept as many constants as possible (to give
6699 reload more freedom) while rejecting constants that can only be created
6700 at certain times. In particular, anything with a symbolic component will
6701 require use of the pseudo FDPIC register, which is only available before
6704 return LEGITIMATE_PIC_OPERAND_P (x);
6706 /* All of the integer constants are ok. */
6707 if (GET_CODE (x) != CONST_DOUBLE)
6710 /* double integer constants are ok. */
6711 if (mode == VOIDmode || mode == DImode)
6714 /* 0 is always ok. */
6715 if (x == CONST0_RTX (mode))
6718 /* If floating point is just emulated, allow any constant, since it will be
6719 constructed in the GPRs. */
6720 if (!TARGET_HAS_FPRS)
6723 if (mode == DFmode && !TARGET_DOUBLE)
6726 /* Otherwise store the constant away and do a load. */
6730 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6731 CC_NZ for comparisons against zero in which a single Z or N flag test
6732 is enough, CC_UNS for other unsigned comparisons, and CC for other
6733 signed comparisons. */
6736 frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
6738 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6747 return y == const0_rtx ? CC_NZmode : CCmode;
6753 return y == const0_rtx ? CC_NZmode : CC_UNSmode;
6760 /* A C expression for the cost of moving data from a register in class FROM to
6761 one in class TO. The classes are expressed using the enumeration values
6762 such as `GENERAL_REGS'. A value of 4 is the default; other values are
6763 interpreted relative to that.
6765 It is not required that the cost always equal 2 when FROM is the same as TO;
6766 on some machines it is expensive to move between registers if they are not
6769 If reload sees an insn consisting of a single `set' between two hard
6770 registers, and if `REGISTER_MOVE_COST' applied to their classes returns a
6771 value of 2, reload does not check to ensure that the constraints of the insn
6772 are met. Setting a cost of other than 2 will allow reload to verify that
6773 the constraints are met. You should do this if the `movM' pattern's
6774 constraints do not allow such copying. */
6776 #define HIGH_COST 40
6777 #define MEDIUM_COST 3
6781 frv_register_move_cost (enum reg_class from, enum reg_class to)
6865 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6866 use ".picptr" to generate safe relocations for PIC code. We also
6867 need a fixup entry for aligned (non-debugging) code. */
6870 frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
6872 if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
6874 if (GET_CODE (value) == CONST
6875 || GET_CODE (value) == SYMBOL_REF
6876 || GET_CODE (value) == LABEL_REF)
6878 if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
6879 && SYMBOL_REF_FUNCTION_P (value))
6881 fputs ("\t.picptr\tfuncdesc(", asm_out_file);
6882 output_addr_const (asm_out_file, value);
6883 fputs (")\n", asm_out_file);
6886 else if (TARGET_FDPIC && GET_CODE (value) == CONST
6887 && frv_function_symbol_referenced_p (value))
6889 if (aligned_p && !TARGET_FDPIC)
6891 static int label_num = 0;
6895 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", label_num++);
6896 p = (* targetm.strip_name_encoding) (buf);
6898 fprintf (asm_out_file, "%s:\n", p);
6899 fprintf (asm_out_file, "%s\n", FIXUP_SECTION_ASM_OP);
6900 fprintf (asm_out_file, "\t.picptr\t%s\n", p);
6901 fprintf (asm_out_file, "\t.previous\n");
6903 assemble_integer_with_op ("\t.picptr\t", value);
6908 /* We've set the unaligned SI op to NULL, so we always have to
6909 handle the unaligned case here. */
6910 assemble_integer_with_op ("\t.4byte\t", value);
6914 return default_assemble_integer (value, size, aligned_p);
6917 /* Function to set up the backend function structure. */
6919 static struct machine_function *
6920 frv_init_machine_status (void)
6922 return ggc_alloc_cleared (sizeof (struct machine_function));
6925 /* Implement TARGET_SCHED_ISSUE_RATE. */
6928 frv_issue_rate (void)
6933 switch (frv_cpu_type)
6937 case FRV_CPU_SIMPLE:
6945 case FRV_CPU_GENERIC:
6947 case FRV_CPU_TOMCAT:
6955 /* A for_each_rtx callback. If X refers to an accumulator, return
6956 ACC_GROUP_ODD if the bit 2 of the register number is set and
6957 ACC_GROUP_EVEN if it is clear. Return 0 (ACC_GROUP_NONE)
6961 frv_acc_group_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
6965 if (ACC_P (REGNO (*x)))
6966 return (REGNO (*x) - ACC_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
6967 if (ACCG_P (REGNO (*x)))
6968 return (REGNO (*x) - ACCG_FIRST) & 4 ? ACC_GROUP_ODD : ACC_GROUP_EVEN;
6973 /* Return the value of INSN's acc_group attribute. */
6976 frv_acc_group (rtx insn)
6978 /* This distinction only applies to the FR550 packing constraints. */
6979 if (frv_cpu_type != FRV_CPU_FR550)
6980 return ACC_GROUP_NONE;
6981 return for_each_rtx (&PATTERN (insn), frv_acc_group_1, 0);
6984 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
6985 INSN will try to claim first. Since this value depends only on the
6986 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
6989 frv_insn_unit (rtx insn)
6991 enum attr_type type;
6993 type = get_attr_type (insn);
6994 if (frv_type_to_unit[type] == ARRAY_SIZE (frv_unit_codes))
6996 /* We haven't seen this type of instruction before. */
7000 /* Issue the instruction on its own to see which unit it prefers. */
7001 state = alloca (state_size ());
7002 state_reset (state);
7003 state_transition (state, insn);
7005 /* Find out which unit was taken. */
7006 for (unit = 0; unit < ARRAY_SIZE (frv_unit_codes); unit++)
7007 if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
7010 if (unit == ARRAY_SIZE (frv_unit_codes))
7013 frv_type_to_unit[type] = unit;
7015 return frv_type_to_unit[type];
7018 /* Return true if INSN issues to a branch unit. */
7021 frv_issues_to_branch_unit_p (rtx insn)
7023 return frv_unit_groups[frv_insn_unit (insn)] == GROUP_B;
7026 /* The current state of the packing pass, implemented by frv_pack_insns. */
7028 /* The state of the pipeline DFA. */
7031 /* Which hardware registers are set within the current packet,
7032 and the conditions under which they are set. */
7033 regstate_t regstate[FIRST_PSEUDO_REGISTER];
7035 /* The memory locations that have been modified so far in this
7036 packet. MEM is the memref and COND is the regstate_t condition
7037 under which it is set. */
7043 /* The number of valid entries in MEMS. The value is larger than
7044 ARRAY_SIZE (mems) if there were too many mems to record. */
7045 unsigned int num_mems;
7047 /* The maximum number of instructions that can be packed together. */
7048 unsigned int issue_rate;
7050 /* The instructions in the packet, partitioned into groups. */
7051 struct frv_packet_group {
7052 /* How many instructions in the packet belong to this group. */
7053 unsigned int num_insns;
7055 /* A list of the instructions that belong to this group, in the order
7056 they appear in the rtl stream. */
7057 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7059 /* The contents of INSNS after they have been sorted into the correct
7060 assembly-language order. Element X issues to unit X. The list may
7061 contain extra nops. */
7062 rtx sorted[ARRAY_SIZE (frv_unit_codes)];
7064 /* The member of frv_nops[] to use in sorted[]. */
7066 } groups[NUM_GROUPS];
7068 /* The instructions that make up the current packet. */
7069 rtx insns[ARRAY_SIZE (frv_unit_codes)];
7070 unsigned int num_insns;
7073 /* Return the regstate_t flags for the given COND_EXEC condition.
7074 Abort if the condition isn't in the right form. */
7077 frv_cond_flags (rtx cond)
7079 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
7080 && GET_CODE (XEXP (cond, 0)) == REG
7081 && CR_P (REGNO (XEXP (cond, 0)))
7082 && XEXP (cond, 1) == const0_rtx)
7083 return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
7084 | (GET_CODE (cond) == NE
7086 : REGSTATE_IF_FALSE));
7091 /* Return true if something accessed under condition COND2 can
7092 conflict with something written under condition COND1. */
7095 frv_regstate_conflict_p (regstate_t cond1, regstate_t cond2)
7097 /* If either reference was unconditional, we have a conflict. */
7098 if ((cond1 & REGSTATE_IF_EITHER) == 0
7099 || (cond2 & REGSTATE_IF_EITHER) == 0)
7102 /* The references might conflict if they were controlled by
7104 if ((cond1 & REGSTATE_CC_MASK) != (cond2 & REGSTATE_CC_MASK))
7107 /* They definitely conflict if they are controlled by the
7109 if ((cond1 & cond2 & REGSTATE_IF_EITHER) != 0)
7116 /* A for_each_rtx callback. Return 1 if *X depends on an instruction in
7117 the current packet. DATA points to a regstate_t that describes the
7118 condition under which *X might be set or used. */
7121 frv_registers_conflict_p_1 (rtx *x, void *data)
7123 unsigned int regno, i;
7126 cond = *(regstate_t *) data;
7128 if (GET_CODE (*x) == REG)
7129 FOR_EACH_REGNO (regno, *x)
7130 if ((frv_packet.regstate[regno] & REGSTATE_MODIFIED) != 0)
7131 if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
7134 if (GET_CODE (*x) == MEM)
7136 /* If we ran out of memory slots, assume a conflict. */
7137 if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
7140 /* Check for output or true dependencies with earlier MEMs. */
7141 for (i = 0; i < frv_packet.num_mems; i++)
7142 if (frv_regstate_conflict_p (frv_packet.mems[i].cond, cond))
7144 if (true_dependence (frv_packet.mems[i].mem, VOIDmode,
7148 if (output_dependence (frv_packet.mems[i].mem, *x))
7153 /* The return values of calls aren't significant: they describe
7154 the effect of the call as a whole, not of the insn itself. */
7155 if (GET_CODE (*x) == SET && GET_CODE (SET_SRC (*x)) == CALL)
7157 if (for_each_rtx (&SET_SRC (*x), frv_registers_conflict_p_1, data))
7162 /* Check subexpressions. */
7167 /* Return true if something in X might depend on an instruction
7168 in the current packet. */
7171 frv_registers_conflict_p (rtx x)
7176 if (GET_CODE (x) == COND_EXEC)
7178 if (for_each_rtx (&XEXP (x, 0), frv_registers_conflict_p_1, &flags))
7181 flags |= frv_cond_flags (XEXP (x, 0));
7184 return for_each_rtx (&x, frv_registers_conflict_p_1, &flags);
7188 /* A note_stores callback. DATA points to the regstate_t condition
7189 under which X is modified. Update FRV_PACKET accordingly. */
7192 frv_registers_update_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
7196 if (GET_CODE (x) == REG)
7197 FOR_EACH_REGNO (regno, x)
7198 frv_packet.regstate[regno] |= *(regstate_t *) data;
7200 if (GET_CODE (x) == MEM)
7202 if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
7204 frv_packet.mems[frv_packet.num_mems].mem = x;
7205 frv_packet.mems[frv_packet.num_mems].cond = *(regstate_t *) data;
7207 frv_packet.num_mems++;
7212 /* Update the register state information for an instruction whose
7216 frv_registers_update (rtx x)
7220 flags = REGSTATE_MODIFIED;
7221 if (GET_CODE (x) == COND_EXEC)
7223 flags |= frv_cond_flags (XEXP (x, 0));
7226 note_stores (x, frv_registers_update_1, &flags);
7230 /* Initialize frv_packet for the start of a new packet. */
7233 frv_start_packet (void)
7235 enum frv_insn_group group;
7237 memset (frv_packet.regstate, 0, sizeof (frv_packet.regstate));
7238 frv_packet.num_mems = 0;
7239 frv_packet.num_insns = 0;
7240 for (group = 0; group < NUM_GROUPS; group++)
7241 frv_packet.groups[group].num_insns = 0;
7245 /* Likewise for the start of a new basic block. */
7248 frv_start_packet_block (void)
7250 state_reset (frv_packet.dfa_state);
7251 frv_start_packet ();
7255 /* Finish the current packet, if any, and start a new one. Call
7256 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7259 frv_finish_packet (void (*handle_packet) (void))
7261 if (frv_packet.num_insns > 0)
7264 state_transition (frv_packet.dfa_state, 0);
7265 frv_start_packet ();
7270 /* Return true if INSN can be added to the current packet. Update
7271 the DFA state on success. */
7274 frv_pack_insn_p (rtx insn)
7276 /* See if the packet is already as long as it can be. */
7277 if (frv_packet.num_insns == frv_packet.issue_rate)
7280 /* If the scheduler thought that an instruction should start a packet,
7281 it's usually a good idea to believe it. It knows much more about
7282 the latencies than we do.
7284 There are some exceptions though:
7286 - Conditional instructions are scheduled on the assumption that
7287 they will be executed. This is usually a good thing, since it
7288 tends to avoid unnecessary stalls in the conditional code.
7289 But we want to pack conditional instructions as tightly as
7290 possible, in order to optimize the case where they aren't
7293 - The scheduler will always put branches on their own, even
7294 if there's no real dependency.
7296 - There's no point putting a call in its own packet unless
7298 if (frv_packet.num_insns > 0
7299 && GET_CODE (insn) == INSN
7300 && GET_MODE (insn) == TImode
7301 && GET_CODE (PATTERN (insn)) != COND_EXEC)
7304 /* Check for register conflicts. Don't do this for setlo since any
7305 conflict will be with the partnering sethi, with which it can
7307 if (get_attr_type (insn) != TYPE_SETLO)
7308 if (frv_registers_conflict_p (PATTERN (insn)))
7311 return state_transition (frv_packet.dfa_state, insn) < 0;
7315 /* Add instruction INSN to the current packet. */
7318 frv_add_insn_to_packet (rtx insn)
7320 struct frv_packet_group *packet_group;
7322 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7323 packet_group->insns[packet_group->num_insns++] = insn;
7324 frv_packet.insns[frv_packet.num_insns++] = insn;
7326 frv_registers_update (PATTERN (insn));
7330 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7331 packet ends in a branch or call, insert the nop before it, otherwise
7335 frv_insert_nop_in_packet (rtx insn)
7337 struct frv_packet_group *packet_group;
7340 packet_group = &frv_packet.groups[frv_unit_groups[frv_insn_unit (insn)]];
7341 last = frv_packet.insns[frv_packet.num_insns - 1];
7342 if (GET_CODE (last) != INSN)
7344 insn = emit_insn_before (PATTERN (insn), last);
7345 frv_packet.insns[frv_packet.num_insns - 1] = insn;
7346 frv_packet.insns[frv_packet.num_insns++] = last;
7350 insn = emit_insn_after (PATTERN (insn), last);
7351 frv_packet.insns[frv_packet.num_insns++] = insn;
7353 packet_group->insns[packet_group->num_insns++] = insn;
7357 /* If packing is enabled, divide the instructions into packets and
7358 return true. Call HANDLE_PACKET for each complete packet. */
7361 frv_for_each_packet (void (*handle_packet) (void))
7363 rtx insn, next_insn;
7365 frv_packet.issue_rate = frv_issue_rate ();
7367 /* Early exit if we don't want to pack insns. */
7369 || !flag_schedule_insns_after_reload
7370 || !TARGET_VLIW_BRANCH
7371 || frv_packet.issue_rate == 1)
7374 /* Set up the initial packing state. */
7376 frv_packet.dfa_state = alloca (state_size ());
7378 frv_start_packet_block ();
7379 for (insn = get_insns (); insn != 0; insn = next_insn)
7384 code = GET_CODE (insn);
7385 next_insn = NEXT_INSN (insn);
7387 if (code == CODE_LABEL)
7389 frv_finish_packet (handle_packet);
7390 frv_start_packet_block ();
7394 switch (GET_CODE (PATTERN (insn)))
7403 /* Calls mustn't be packed on a TOMCAT. */
7404 if (GET_CODE (insn) == CALL_INSN && frv_cpu_type == FRV_CPU_TOMCAT)
7405 frv_finish_packet (handle_packet);
7407 /* Since the last instruction in a packet determines the EH
7408 region, any exception-throwing instruction must come at
7409 the end of reordered packet. Insns that issue to a
7410 branch unit are bound to come last; for others it's
7411 too hard to predict. */
7412 eh_insn_p = (find_reg_note (insn, REG_EH_REGION, NULL) != NULL);
7413 if (eh_insn_p && !frv_issues_to_branch_unit_p (insn))
7414 frv_finish_packet (handle_packet);
7416 /* Finish the current packet if we can't add INSN to it.
7417 Simulate cycles until INSN is ready to issue. */
7418 if (!frv_pack_insn_p (insn))
7420 frv_finish_packet (handle_packet);
7421 while (!frv_pack_insn_p (insn))
7422 state_transition (frv_packet.dfa_state, 0);
7425 /* Add the instruction to the packet. */
7426 frv_add_insn_to_packet (insn);
7428 /* Calls and jumps end a packet, as do insns that throw
7430 if (code == CALL_INSN || code == JUMP_INSN || eh_insn_p)
7431 frv_finish_packet (handle_packet);
7435 frv_finish_packet (handle_packet);
7440 /* Subroutine of frv_sort_insn_group. We are trying to sort
7441 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7442 language order. We have already picked a new position for
7443 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7444 These instructions will occupy elements [0, LOWER_SLOT) and
7445 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7446 the DFA state after issuing these instructions.
7448 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7449 of the unused instructions. Return true if one such permutation gives
7450 a valid ordering, leaving the successful permutation in sorted[].
7451 Do not modify sorted[] until a valid permutation is found. */
7454 frv_sort_insn_group_1 (enum frv_insn_group group,
7455 unsigned int lower_slot, unsigned int upper_slot,
7456 unsigned int issued, unsigned int num_insns,
7459 struct frv_packet_group *packet_group;
7465 /* Early success if we've filled all the slots. */
7466 if (lower_slot == upper_slot)
7469 packet_group = &frv_packet.groups[group];
7470 dfa_size = state_size ();
7471 test_state = alloca (dfa_size);
7473 /* Try issuing each unused instruction. */
7474 for (i = num_insns - 1; i + 1 != 0; i--)
7475 if (~issued & (1 << i))
7477 insn = packet_group->sorted[i];
7478 memcpy (test_state, state, dfa_size);
7479 if (state_transition (test_state, insn) < 0
7480 && cpu_unit_reservation_p (test_state,
7481 NTH_UNIT (group, upper_slot - 1))
7482 && frv_sort_insn_group_1 (group, lower_slot, upper_slot - 1,
7483 issued | (1 << i), num_insns,
7486 packet_group->sorted[upper_slot - 1] = insn;
7494 /* Compare two instructions by their frv_insn_unit. */
7497 frv_compare_insns (const void *first, const void *second)
7499 const rtx *insn1 = first, *insn2 = second;
7500 return frv_insn_unit (*insn1) - frv_insn_unit (*insn2);
7503 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7504 and sort it into assembly language order. See frv.md for a description of
7508 frv_sort_insn_group (enum frv_insn_group group)
7510 struct frv_packet_group *packet_group;
7511 unsigned int first, i, nop, max_unit, num_slots;
7512 state_t state, test_state;
7515 packet_group = &frv_packet.groups[group];
7517 /* Assume no nop is needed. */
7518 packet_group->nop = 0;
7520 if (packet_group->num_insns == 0)
7523 /* Copy insns[] to sorted[]. */
7524 memcpy (packet_group->sorted, packet_group->insns,
7525 sizeof (rtx) * packet_group->num_insns);
7527 /* Sort sorted[] by the unit that each insn tries to take first. */
7528 if (packet_group->num_insns > 1)
7529 qsort (packet_group->sorted, packet_group->num_insns,
7530 sizeof (rtx), frv_compare_insns);
7532 /* That's always enough for branch and control insns. */
7533 if (group == GROUP_B || group == GROUP_C)
7536 dfa_size = state_size ();
7537 state = alloca (dfa_size);
7538 test_state = alloca (dfa_size);
7540 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7541 consecutively and such that the DFA takes unit X when sorted[X]
7542 is added. Set STATE to the new DFA state. */
7543 state_reset (test_state);
7544 for (first = 0; first < packet_group->num_insns; first++)
7546 memcpy (state, test_state, dfa_size);
7547 if (state_transition (test_state, packet_group->sorted[first]) >= 0
7548 || !cpu_unit_reservation_p (test_state, NTH_UNIT (group, first)))
7552 /* If all the instructions issued in ascending order, we're done. */
7553 if (first == packet_group->num_insns)
7556 /* Add nops to the end of sorted[] and try each permutation until
7557 we find one that works. */
7558 for (nop = 0; nop < frv_num_nops; nop++)
7560 max_unit = frv_insn_unit (frv_nops[nop]);
7561 if (frv_unit_groups[max_unit] == group)
7563 packet_group->nop = frv_nops[nop];
7564 num_slots = UNIT_NUMBER (max_unit) + 1;
7565 for (i = packet_group->num_insns; i < num_slots; i++)
7566 packet_group->sorted[i] = frv_nops[nop];
7567 if (frv_sort_insn_group_1 (group, first, num_slots,
7568 (1 << first) - 1, num_slots, state))
7575 /* Sort the current packet into assembly-language order. Set packing
7576 flags as appropriate. */
7579 frv_reorder_packet (void)
7581 unsigned int cursor[NUM_GROUPS];
7582 rtx insns[ARRAY_SIZE (frv_unit_groups)];
7583 unsigned int unit, to, from;
7584 enum frv_insn_group group;
7585 struct frv_packet_group *packet_group;
7587 /* First sort each group individually. */
7588 for (group = 0; group < NUM_GROUPS; group++)
7591 frv_sort_insn_group (group);
7594 /* Go through the unit template and try add an instruction from
7595 that unit's group. */
7597 for (unit = 0; unit < ARRAY_SIZE (frv_unit_groups); unit++)
7599 group = frv_unit_groups[unit];
7600 packet_group = &frv_packet.groups[group];
7601 if (cursor[group] < packet_group->num_insns)
7603 /* frv_reorg should have added nops for us. */
7604 if (packet_group->sorted[cursor[group]] == packet_group->nop)
7606 insns[to++] = packet_group->sorted[cursor[group]++];
7610 if (to != frv_packet.num_insns)
7613 /* Clear the last instruction's packing flag, thus marking the end of
7614 a packet. Reorder the other instructions relative to it. */
7615 CLEAR_PACKING_FLAG (insns[to - 1]);
7616 for (from = 0; from < to - 1; from++)
7618 remove_insn (insns[from]);
7619 add_insn_before (insns[from], insns[to - 1]);
7620 SET_PACKING_FLAG (insns[from]);
7625 /* Divide instructions into packets. Reorder the contents of each
7626 packet so that they are in the correct assembly-language order.
7628 Since this pass can change the raw meaning of the rtl stream, it must
7629 only be called at the last minute, just before the instructions are
7633 frv_pack_insns (void)
7635 if (frv_for_each_packet (frv_reorder_packet))
7636 frv_insn_packing_flag = 0;
7638 frv_insn_packing_flag = -1;
7641 /* See whether we need to add nops to group GROUP in order to
7642 make a valid packet. */
7645 frv_fill_unused_units (enum frv_insn_group group)
7647 unsigned int non_nops, nops, i;
7648 struct frv_packet_group *packet_group;
7650 packet_group = &frv_packet.groups[group];
7652 /* Sort the instructions into assembly-language order.
7653 Use nops to fill slots that are otherwise unused. */
7654 frv_sort_insn_group (group);
7656 /* See how many nops are needed before the final useful instruction. */
7658 for (non_nops = 0; non_nops < packet_group->num_insns; non_nops++)
7659 while (packet_group->sorted[i++] == packet_group->nop)
7662 /* Insert that many nops into the instruction stream. */
7664 frv_insert_nop_in_packet (packet_group->nop);
7667 /* Used by frv_reorg to keep track of the current packet's address. */
7668 static unsigned int frv_packet_address;
7670 /* If the current packet falls through to a label, try to pad the packet
7671 with nops in order to fit the label's alignment requirements. */
7674 frv_align_label (void)
7676 unsigned int alignment, target, nop;
7677 rtx x, last, barrier, label;
7679 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
7680 maximum alignment of that packet, LABEL to the last label between
7681 the packets, and BARRIER to the last barrier. */
7682 last = frv_packet.insns[frv_packet.num_insns - 1];
7683 label = barrier = 0;
7685 for (x = NEXT_INSN (last); x != 0 && !INSN_P (x); x = NEXT_INSN (x))
7689 unsigned int subalign = 1 << label_to_alignment (x);
7690 alignment = MAX (alignment, subalign);
7697 /* If -malign-labels, and the packet falls through to an unaligned
7698 label, try introducing a nop to align that label to 8 bytes. */
7699 if (TARGET_ALIGN_LABELS
7702 && frv_packet.num_insns < frv_packet.issue_rate)
7703 alignment = MAX (alignment, 8);
7705 /* Advance the address to the end of the current packet. */
7706 frv_packet_address += frv_packet.num_insns * 4;
7708 /* Work out the target address, after alignment. */
7709 target = (frv_packet_address + alignment - 1) & -alignment;
7711 /* If the packet falls through to the label, try to find an efficient
7712 padding sequence. */
7715 /* First try adding nops to the current packet. */
7716 for (nop = 0; nop < frv_num_nops; nop++)
7717 while (frv_packet_address < target && frv_pack_insn_p (frv_nops[nop]))
7719 frv_insert_nop_in_packet (frv_nops[nop]);
7720 frv_packet_address += 4;
7723 /* If we still haven't reached the target, add some new packets that
7724 contain only nops. If there are two types of nop, insert an
7725 alternating sequence of frv_nops[0] and frv_nops[1], which will
7726 lead to packets like:
7733 etc. Just emit frv_nops[0] if that's the only nop we have. */
7734 last = frv_packet.insns[frv_packet.num_insns - 1];
7736 while (frv_packet_address < target)
7738 last = emit_insn_after (PATTERN (frv_nops[nop]), last);
7739 frv_packet_address += 4;
7740 if (frv_num_nops > 1)
7745 frv_packet_address = target;
7748 /* Subroutine of frv_reorg, called after each packet has been constructed
7752 frv_reorg_packet (void)
7754 frv_fill_unused_units (GROUP_I);
7755 frv_fill_unused_units (GROUP_FM);
7759 /* Add an instruction with pattern NOP to frv_nops[]. */
7762 frv_register_nop (rtx nop)
7764 nop = make_insn_raw (nop);
7765 NEXT_INSN (nop) = 0;
7766 PREV_INSN (nop) = 0;
7767 frv_nops[frv_num_nops++] = nop;
7770 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
7771 into packets and check whether we need to insert nops in order to
7772 fulfill the processor's issue requirements. Also, if the user has
7773 requested a certain alignment for a label, try to meet that alignment
7774 by inserting nops in the previous packet. */
7780 frv_register_nop (gen_nop ());
7782 frv_register_nop (gen_mnop ());
7783 if (TARGET_HARD_FLOAT)
7784 frv_register_nop (gen_fnop ());
7786 /* Estimate the length of each branch. Although this may change after
7787 we've inserted nops, it will only do so in big functions. */
7788 shorten_branches (get_insns ());
7790 frv_packet_address = 0;
7791 frv_for_each_packet (frv_reorg_packet);
7794 #define def_builtin(name, type, code) \
7795 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
7797 struct builtin_description
7799 enum insn_code icode;
7801 enum frv_builtins code;
7802 enum rtx_code comparison;
7806 /* Media intrinsics that take a single, constant argument. */
7808 static struct builtin_description bdesc_set[] =
7810 { CODE_FOR_mhdsets, "__MHDSETS", FRV_BUILTIN_MHDSETS, 0, 0 }
7813 /* Media intrinsics that take just one argument. */
7815 static struct builtin_description bdesc_1arg[] =
7817 { CODE_FOR_mnot, "__MNOT", FRV_BUILTIN_MNOT, 0, 0 },
7818 { CODE_FOR_munpackh, "__MUNPACKH", FRV_BUILTIN_MUNPACKH, 0, 0 },
7819 { CODE_FOR_mbtoh, "__MBTOH", FRV_BUILTIN_MBTOH, 0, 0 },
7820 { CODE_FOR_mhtob, "__MHTOB", FRV_BUILTIN_MHTOB, 0, 0 },
7821 { CODE_FOR_mabshs, "__MABSHS", FRV_BUILTIN_MABSHS, 0, 0 },
7822 { CODE_FOR_scutss, "__SCUTSS", FRV_BUILTIN_SCUTSS, 0, 0 }
7825 /* Media intrinsics that take two arguments. */
7827 static struct builtin_description bdesc_2arg[] =
7829 { CODE_FOR_mand, "__MAND", FRV_BUILTIN_MAND, 0, 0 },
7830 { CODE_FOR_mor, "__MOR", FRV_BUILTIN_MOR, 0, 0 },
7831 { CODE_FOR_mxor, "__MXOR", FRV_BUILTIN_MXOR, 0, 0 },
7832 { CODE_FOR_maveh, "__MAVEH", FRV_BUILTIN_MAVEH, 0, 0 },
7833 { CODE_FOR_msaths, "__MSATHS", FRV_BUILTIN_MSATHS, 0, 0 },
7834 { CODE_FOR_msathu, "__MSATHU", FRV_BUILTIN_MSATHU, 0, 0 },
7835 { CODE_FOR_maddhss, "__MADDHSS", FRV_BUILTIN_MADDHSS, 0, 0 },
7836 { CODE_FOR_maddhus, "__MADDHUS", FRV_BUILTIN_MADDHUS, 0, 0 },
7837 { CODE_FOR_msubhss, "__MSUBHSS", FRV_BUILTIN_MSUBHSS, 0, 0 },
7838 { CODE_FOR_msubhus, "__MSUBHUS", FRV_BUILTIN_MSUBHUS, 0, 0 },
7839 { CODE_FOR_mqaddhss, "__MQADDHSS", FRV_BUILTIN_MQADDHSS, 0, 0 },
7840 { CODE_FOR_mqaddhus, "__MQADDHUS", FRV_BUILTIN_MQADDHUS, 0, 0 },
7841 { CODE_FOR_mqsubhss, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS, 0, 0 },
7842 { CODE_FOR_mqsubhus, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS, 0, 0 },
7843 { CODE_FOR_mpackh, "__MPACKH", FRV_BUILTIN_MPACKH, 0, 0 },
7844 { CODE_FOR_mcop1, "__Mcop1", FRV_BUILTIN_MCOP1, 0, 0 },
7845 { CODE_FOR_mcop2, "__Mcop2", FRV_BUILTIN_MCOP2, 0, 0 },
7846 { CODE_FOR_mwcut, "__MWCUT", FRV_BUILTIN_MWCUT, 0, 0 },
7847 { CODE_FOR_mqsaths, "__MQSATHS", FRV_BUILTIN_MQSATHS, 0, 0 },
7848 { CODE_FOR_mqlclrhs, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS, 0, 0 },
7849 { CODE_FOR_mqlmths, "__MQLMTHS", FRV_BUILTIN_MQLMTHS, 0, 0 },
7850 { CODE_FOR_smul, "__SMUL", FRV_BUILTIN_SMUL, 0, 0 },
7851 { CODE_FOR_umul, "__UMUL", FRV_BUILTIN_UMUL, 0, 0 },
7852 { CODE_FOR_addss, "__ADDSS", FRV_BUILTIN_ADDSS, 0, 0 },
7853 { CODE_FOR_subss, "__SUBSS", FRV_BUILTIN_SUBSS, 0, 0 },
7854 { CODE_FOR_slass, "__SLASS", FRV_BUILTIN_SLASS, 0, 0 },
7855 { CODE_FOR_scan, "__SCAN", FRV_BUILTIN_SCAN, 0, 0 }
7858 /* Integer intrinsics that take two arguments and have no return value. */
7860 static struct builtin_description bdesc_int_void2arg[] =
7862 { CODE_FOR_smass, "__SMASS", FRV_BUILTIN_SMASS, 0, 0 },
7863 { CODE_FOR_smsss, "__SMSSS", FRV_BUILTIN_SMSSS, 0, 0 },
7864 { CODE_FOR_smu, "__SMU", FRV_BUILTIN_SMU, 0, 0 }
7867 static struct builtin_description bdesc_prefetches[] =
7869 { CODE_FOR_frv_prefetch0, "__data_prefetch0", FRV_BUILTIN_PREFETCH0, 0, 0 },
7870 { CODE_FOR_frv_prefetch, "__data_prefetch", FRV_BUILTIN_PREFETCH, 0, 0 }
7873 /* Media intrinsics that take two arguments, the first being an ACC number. */
7875 static struct builtin_description bdesc_cut[] =
7877 { CODE_FOR_mcut, "__MCUT", FRV_BUILTIN_MCUT, 0, 0 },
7878 { CODE_FOR_mcutss, "__MCUTSS", FRV_BUILTIN_MCUTSS, 0, 0 },
7879 { CODE_FOR_mdcutssi, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI, 0, 0 }
7882 /* Two-argument media intrinsics with an immediate second argument. */
7884 static struct builtin_description bdesc_2argimm[] =
7886 { CODE_FOR_mrotli, "__MROTLI", FRV_BUILTIN_MROTLI, 0, 0 },
7887 { CODE_FOR_mrotri, "__MROTRI", FRV_BUILTIN_MROTRI, 0, 0 },
7888 { CODE_FOR_msllhi, "__MSLLHI", FRV_BUILTIN_MSLLHI, 0, 0 },
7889 { CODE_FOR_msrlhi, "__MSRLHI", FRV_BUILTIN_MSRLHI, 0, 0 },
7890 { CODE_FOR_msrahi, "__MSRAHI", FRV_BUILTIN_MSRAHI, 0, 0 },
7891 { CODE_FOR_mexpdhw, "__MEXPDHW", FRV_BUILTIN_MEXPDHW, 0, 0 },
7892 { CODE_FOR_mexpdhd, "__MEXPDHD", FRV_BUILTIN_MEXPDHD, 0, 0 },
7893 { CODE_FOR_mdrotli, "__MDROTLI", FRV_BUILTIN_MDROTLI, 0, 0 },
7894 { CODE_FOR_mcplhi, "__MCPLHI", FRV_BUILTIN_MCPLHI, 0, 0 },
7895 { CODE_FOR_mcpli, "__MCPLI", FRV_BUILTIN_MCPLI, 0, 0 },
7896 { CODE_FOR_mhsetlos, "__MHSETLOS", FRV_BUILTIN_MHSETLOS, 0, 0 },
7897 { CODE_FOR_mhsetloh, "__MHSETLOH", FRV_BUILTIN_MHSETLOH, 0, 0 },
7898 { CODE_FOR_mhsethis, "__MHSETHIS", FRV_BUILTIN_MHSETHIS, 0, 0 },
7899 { CODE_FOR_mhsethih, "__MHSETHIH", FRV_BUILTIN_MHSETHIH, 0, 0 },
7900 { CODE_FOR_mhdseth, "__MHDSETH", FRV_BUILTIN_MHDSETH, 0, 0 },
7901 { CODE_FOR_mqsllhi, "__MQSLLHI", FRV_BUILTIN_MQSLLHI, 0, 0 },
7902 { CODE_FOR_mqsrahi, "__MQSRAHI", FRV_BUILTIN_MQSRAHI, 0, 0 }
7905 /* Media intrinsics that take two arguments and return void, the first argument
7906 being a pointer to 4 words in memory. */
7908 static struct builtin_description bdesc_void2arg[] =
7910 { CODE_FOR_mdunpackh, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH, 0, 0 },
7911 { CODE_FOR_mbtohe, "__MBTOHE", FRV_BUILTIN_MBTOHE, 0, 0 },
7914 /* Media intrinsics that take three arguments, the first being a const_int that
7915 denotes an accumulator, and that return void. */
7917 static struct builtin_description bdesc_void3arg[] =
7919 { CODE_FOR_mcpxrs, "__MCPXRS", FRV_BUILTIN_MCPXRS, 0, 0 },
7920 { CODE_FOR_mcpxru, "__MCPXRU", FRV_BUILTIN_MCPXRU, 0, 0 },
7921 { CODE_FOR_mcpxis, "__MCPXIS", FRV_BUILTIN_MCPXIS, 0, 0 },
7922 { CODE_FOR_mcpxiu, "__MCPXIU", FRV_BUILTIN_MCPXIU, 0, 0 },
7923 { CODE_FOR_mmulhs, "__MMULHS", FRV_BUILTIN_MMULHS, 0, 0 },
7924 { CODE_FOR_mmulhu, "__MMULHU", FRV_BUILTIN_MMULHU, 0, 0 },
7925 { CODE_FOR_mmulxhs, "__MMULXHS", FRV_BUILTIN_MMULXHS, 0, 0 },
7926 { CODE_FOR_mmulxhu, "__MMULXHU", FRV_BUILTIN_MMULXHU, 0, 0 },
7927 { CODE_FOR_mmachs, "__MMACHS", FRV_BUILTIN_MMACHS, 0, 0 },
7928 { CODE_FOR_mmachu, "__MMACHU", FRV_BUILTIN_MMACHU, 0, 0 },
7929 { CODE_FOR_mmrdhs, "__MMRDHS", FRV_BUILTIN_MMRDHS, 0, 0 },
7930 { CODE_FOR_mmrdhu, "__MMRDHU", FRV_BUILTIN_MMRDHU, 0, 0 },
7931 { CODE_FOR_mqcpxrs, "__MQCPXRS", FRV_BUILTIN_MQCPXRS, 0, 0 },
7932 { CODE_FOR_mqcpxru, "__MQCPXRU", FRV_BUILTIN_MQCPXRU, 0, 0 },
7933 { CODE_FOR_mqcpxis, "__MQCPXIS", FRV_BUILTIN_MQCPXIS, 0, 0 },
7934 { CODE_FOR_mqcpxiu, "__MQCPXIU", FRV_BUILTIN_MQCPXIU, 0, 0 },
7935 { CODE_FOR_mqmulhs, "__MQMULHS", FRV_BUILTIN_MQMULHS, 0, 0 },
7936 { CODE_FOR_mqmulhu, "__MQMULHU", FRV_BUILTIN_MQMULHU, 0, 0 },
7937 { CODE_FOR_mqmulxhs, "__MQMULXHS", FRV_BUILTIN_MQMULXHS, 0, 0 },
7938 { CODE_FOR_mqmulxhu, "__MQMULXHU", FRV_BUILTIN_MQMULXHU, 0, 0 },
7939 { CODE_FOR_mqmachs, "__MQMACHS", FRV_BUILTIN_MQMACHS, 0, 0 },
7940 { CODE_FOR_mqmachu, "__MQMACHU", FRV_BUILTIN_MQMACHU, 0, 0 },
7941 { CODE_FOR_mqxmachs, "__MQXMACHS", FRV_BUILTIN_MQXMACHS, 0, 0 },
7942 { CODE_FOR_mqxmacxhs, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS, 0, 0 },
7943 { CODE_FOR_mqmacxhs, "__MQMACXHS", FRV_BUILTIN_MQMACXHS, 0, 0 }
7946 /* Media intrinsics that take two accumulator numbers as argument and
7949 static struct builtin_description bdesc_voidacc[] =
7951 { CODE_FOR_maddaccs, "__MADDACCS", FRV_BUILTIN_MADDACCS, 0, 0 },
7952 { CODE_FOR_msubaccs, "__MSUBACCS", FRV_BUILTIN_MSUBACCS, 0, 0 },
7953 { CODE_FOR_masaccs, "__MASACCS", FRV_BUILTIN_MASACCS, 0, 0 },
7954 { CODE_FOR_mdaddaccs, "__MDADDACCS", FRV_BUILTIN_MDADDACCS, 0, 0 },
7955 { CODE_FOR_mdsubaccs, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS, 0, 0 },
7956 { CODE_FOR_mdasaccs, "__MDASACCS", FRV_BUILTIN_MDASACCS, 0, 0 }
7959 /* Initialize media builtins. */
7962 frv_init_builtins (void)
7964 tree endlink = void_list_node;
7965 tree accumulator = integer_type_node;
7966 tree integer = integer_type_node;
7967 tree voidt = void_type_node;
7968 tree uhalf = short_unsigned_type_node;
7969 tree sword1 = long_integer_type_node;
7970 tree uword1 = long_unsigned_type_node;
7971 tree sword2 = long_long_integer_type_node;
7972 tree uword2 = long_long_unsigned_type_node;
7973 tree uword4 = build_pointer_type (uword1);
7974 tree iacc = integer_type_node;
7976 #define UNARY(RET, T1) \
7977 build_function_type (RET, tree_cons (NULL_TREE, T1, endlink))
7979 #define BINARY(RET, T1, T2) \
7980 build_function_type (RET, tree_cons (NULL_TREE, T1, \
7981 tree_cons (NULL_TREE, T2, endlink)))
7983 #define TRINARY(RET, T1, T2, T3) \
7984 build_function_type (RET, tree_cons (NULL_TREE, T1, \
7985 tree_cons (NULL_TREE, T2, \
7986 tree_cons (NULL_TREE, T3, endlink))))
7988 #define QUAD(RET, T1, T2, T3, T4) \
7989 build_function_type (RET, tree_cons (NULL_TREE, T1, \
7990 tree_cons (NULL_TREE, T2, \
7991 tree_cons (NULL_TREE, T3, \
7992 tree_cons (NULL_TREE, T4, endlink)))))
7994 tree void_ftype_void = build_function_type (voidt, endlink);
7996 tree void_ftype_acc = UNARY (voidt, accumulator);
7997 tree void_ftype_uw4_uw1 = BINARY (voidt, uword4, uword1);
7998 tree void_ftype_uw4_uw2 = BINARY (voidt, uword4, uword2);
7999 tree void_ftype_acc_uw1 = BINARY (voidt, accumulator, uword1);
8000 tree void_ftype_acc_acc = BINARY (voidt, accumulator, accumulator);
8001 tree void_ftype_acc_uw1_uw1 = TRINARY (voidt, accumulator, uword1, uword1);
8002 tree void_ftype_acc_sw1_sw1 = TRINARY (voidt, accumulator, sword1, sword1);
8003 tree void_ftype_acc_uw2_uw2 = TRINARY (voidt, accumulator, uword2, uword2);
8004 tree void_ftype_acc_sw2_sw2 = TRINARY (voidt, accumulator, sword2, sword2);
8006 tree uw1_ftype_uw1 = UNARY (uword1, uword1);
8007 tree uw1_ftype_sw1 = UNARY (uword1, sword1);
8008 tree uw1_ftype_uw2 = UNARY (uword1, uword2);
8009 tree uw1_ftype_acc = UNARY (uword1, accumulator);
8010 tree uw1_ftype_uh_uh = BINARY (uword1, uhalf, uhalf);
8011 tree uw1_ftype_uw1_uw1 = BINARY (uword1, uword1, uword1);
8012 tree uw1_ftype_uw1_int = BINARY (uword1, uword1, integer);
8013 tree uw1_ftype_acc_uw1 = BINARY (uword1, accumulator, uword1);
8014 tree uw1_ftype_acc_sw1 = BINARY (uword1, accumulator, sword1);
8015 tree uw1_ftype_uw2_uw1 = BINARY (uword1, uword2, uword1);
8016 tree uw1_ftype_uw2_int = BINARY (uword1, uword2, integer);
8018 tree sw1_ftype_int = UNARY (sword1, integer);
8019 tree sw1_ftype_sw1_sw1 = BINARY (sword1, sword1, sword1);
8020 tree sw1_ftype_sw1_int = BINARY (sword1, sword1, integer);
8022 tree uw2_ftype_uw1 = UNARY (uword2, uword1);
8023 tree uw2_ftype_uw1_int = BINARY (uword2, uword1, integer);
8024 tree uw2_ftype_uw2_uw2 = BINARY (uword2, uword2, uword2);
8025 tree uw2_ftype_uw2_int = BINARY (uword2, uword2, integer);
8026 tree uw2_ftype_acc_int = BINARY (uword2, accumulator, integer);
8027 tree uw2_ftype_uh_uh_uh_uh = QUAD (uword2, uhalf, uhalf, uhalf, uhalf);
8029 tree sw2_ftype_sw2_sw2 = BINARY (sword2, sword2, sword2);
8030 tree sw2_ftype_sw2_int = BINARY (sword2, sword2, integer);
8031 tree uw2_ftype_uw1_uw1 = BINARY (uword2, uword1, uword1);
8032 tree sw2_ftype_sw1_sw1 = BINARY (sword2, sword1, sword1);
8033 tree void_ftype_sw1_sw1 = BINARY (voidt, sword1, sword1);
8034 tree void_ftype_iacc_sw2 = BINARY (voidt, iacc, sword2);
8035 tree void_ftype_iacc_sw1 = BINARY (voidt, iacc, sword1);
8036 tree sw1_ftype_sw1 = UNARY (sword1, sword1);
8037 tree sw2_ftype_iacc = UNARY (sword2, iacc);
8038 tree sw1_ftype_iacc = UNARY (sword1, iacc);
8039 tree void_ftype_ptr = UNARY (voidt, const_ptr_type_node);
8041 def_builtin ("__MAND", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAND);
8042 def_builtin ("__MOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MOR);
8043 def_builtin ("__MXOR", uw1_ftype_uw1_uw1, FRV_BUILTIN_MXOR);
8044 def_builtin ("__MNOT", uw1_ftype_uw1, FRV_BUILTIN_MNOT);
8045 def_builtin ("__MROTLI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTLI);
8046 def_builtin ("__MROTRI", uw1_ftype_uw1_int, FRV_BUILTIN_MROTRI);
8047 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1, FRV_BUILTIN_MWCUT);
8048 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1, FRV_BUILTIN_MAVEH);
8049 def_builtin ("__MSLLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSLLHI);
8050 def_builtin ("__MSRLHI", uw1_ftype_uw1_int, FRV_BUILTIN_MSRLHI);
8051 def_builtin ("__MSRAHI", sw1_ftype_sw1_int, FRV_BUILTIN_MSRAHI);
8052 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSATHS);
8053 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSATHU);
8054 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MADDHSS);
8055 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MADDHUS);
8056 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_MSUBHSS);
8057 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1, FRV_BUILTIN_MSUBHUS);
8058 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULHS);
8059 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULHU);
8060 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMULXHS);
8061 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMULXHU);
8062 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMACHS);
8063 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMACHU);
8064 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MMRDHS);
8065 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MMRDHU);
8066 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQADDHSS);
8067 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQADDHUS);
8068 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSUBHSS);
8069 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2, FRV_BUILTIN_MQSUBHUS);
8070 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULHS);
8071 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULHU);
8072 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMULXHS);
8073 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMULXHU);
8074 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACHS);
8075 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQMACHU);
8076 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXRS);
8077 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXRU);
8078 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1, FRV_BUILTIN_MCPXIS);
8079 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1, FRV_BUILTIN_MCPXIU);
8080 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXRS);
8081 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXRU);
8082 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQCPXIS);
8083 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2, FRV_BUILTIN_MQCPXIU);
8084 def_builtin ("__MCUT", uw1_ftype_acc_uw1, FRV_BUILTIN_MCUT);
8085 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1, FRV_BUILTIN_MCUTSS);
8086 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int, FRV_BUILTIN_MEXPDHW);
8087 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int, FRV_BUILTIN_MEXPDHD);
8088 def_builtin ("__MPACKH", uw1_ftype_uh_uh, FRV_BUILTIN_MPACKH);
8089 def_builtin ("__MUNPACKH", uw2_ftype_uw1, FRV_BUILTIN_MUNPACKH);
8090 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh, FRV_BUILTIN_MDPACKH);
8091 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2, FRV_BUILTIN_MDUNPACKH);
8092 def_builtin ("__MBTOH", uw2_ftype_uw1, FRV_BUILTIN_MBTOH);
8093 def_builtin ("__MHTOB", uw1_ftype_uw2, FRV_BUILTIN_MHTOB);
8094 def_builtin ("__MBTOHE", void_ftype_uw4_uw1, FRV_BUILTIN_MBTOHE);
8095 def_builtin ("__MCLRACC", void_ftype_acc, FRV_BUILTIN_MCLRACC);
8096 def_builtin ("__MCLRACCA", void_ftype_void, FRV_BUILTIN_MCLRACCA);
8097 def_builtin ("__MRDACC", uw1_ftype_acc, FRV_BUILTIN_MRDACC);
8098 def_builtin ("__MRDACCG", uw1_ftype_acc, FRV_BUILTIN_MRDACCG);
8099 def_builtin ("__MWTACC", void_ftype_acc_uw1, FRV_BUILTIN_MWTACC);
8100 def_builtin ("__MWTACCG", void_ftype_acc_uw1, FRV_BUILTIN_MWTACCG);
8101 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP1);
8102 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1, FRV_BUILTIN_MCOP2);
8103 def_builtin ("__MTRAP", void_ftype_void, FRV_BUILTIN_MTRAP);
8104 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACHS);
8105 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQXMACXHS);
8106 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2, FRV_BUILTIN_MQMACXHS);
8107 def_builtin ("__MADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MADDACCS);
8108 def_builtin ("__MSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MSUBACCS);
8109 def_builtin ("__MASACCS", void_ftype_acc_acc, FRV_BUILTIN_MASACCS);
8110 def_builtin ("__MDADDACCS", void_ftype_acc_acc, FRV_BUILTIN_MDADDACCS);
8111 def_builtin ("__MDSUBACCS", void_ftype_acc_acc, FRV_BUILTIN_MDSUBACCS);
8112 def_builtin ("__MDASACCS", void_ftype_acc_acc, FRV_BUILTIN_MDASACCS);
8113 def_builtin ("__MABSHS", uw1_ftype_sw1, FRV_BUILTIN_MABSHS);
8114 def_builtin ("__MDROTLI", uw2_ftype_uw2_int, FRV_BUILTIN_MDROTLI);
8115 def_builtin ("__MCPLHI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLHI);
8116 def_builtin ("__MCPLI", uw1_ftype_uw2_int, FRV_BUILTIN_MCPLI);
8117 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int, FRV_BUILTIN_MDCUTSSI);
8118 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQSATHS);
8119 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETLOS);
8120 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int, FRV_BUILTIN_MHSETHIS);
8121 def_builtin ("__MHDSETS", sw1_ftype_int, FRV_BUILTIN_MHDSETS);
8122 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETLOH);
8123 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int, FRV_BUILTIN_MHSETHIH);
8124 def_builtin ("__MHDSETH", uw1_ftype_uw1_int, FRV_BUILTIN_MHDSETH);
8125 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLCLRHS);
8126 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2, FRV_BUILTIN_MQLMTHS);
8127 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int, FRV_BUILTIN_MQSLLHI);
8128 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int, FRV_BUILTIN_MQSRAHI);
8129 def_builtin ("__SMUL", sw2_ftype_sw1_sw1, FRV_BUILTIN_SMUL);
8130 def_builtin ("__UMUL", uw2_ftype_uw1_uw1, FRV_BUILTIN_UMUL);
8131 def_builtin ("__SMASS", void_ftype_sw1_sw1, FRV_BUILTIN_SMASS);
8132 def_builtin ("__SMSSS", void_ftype_sw1_sw1, FRV_BUILTIN_SMSSS);
8133 def_builtin ("__SMU", void_ftype_sw1_sw1, FRV_BUILTIN_SMU);
8134 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_ADDSS);
8135 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SUBSS);
8136 def_builtin ("__SLASS", sw1_ftype_sw1_sw1, FRV_BUILTIN_SLASS);
8137 def_builtin ("__SCAN", sw1_ftype_sw1_sw1, FRV_BUILTIN_SCAN);
8138 def_builtin ("__SCUTSS", sw1_ftype_sw1, FRV_BUILTIN_SCUTSS);
8139 def_builtin ("__IACCreadll", sw2_ftype_iacc, FRV_BUILTIN_IACCreadll);
8140 def_builtin ("__IACCreadl", sw1_ftype_iacc, FRV_BUILTIN_IACCreadl);
8141 def_builtin ("__IACCsetll", void_ftype_iacc_sw2, FRV_BUILTIN_IACCsetll);
8142 def_builtin ("__IACCsetl", void_ftype_iacc_sw1, FRV_BUILTIN_IACCsetl);
8143 def_builtin ("__data_prefetch0", void_ftype_ptr, FRV_BUILTIN_PREFETCH0);
8144 def_builtin ("__data_prefetch", void_ftype_ptr, FRV_BUILTIN_PREFETCH);
8152 /* Set the names for various arithmetic operations according to the
8155 frv_init_libfuncs (void)
8157 set_optab_libfunc (smod_optab, SImode, "__modi");
8158 set_optab_libfunc (umod_optab, SImode, "__umodi");
8160 set_optab_libfunc (add_optab, DImode, "__addll");
8161 set_optab_libfunc (sub_optab, DImode, "__subll");
8162 set_optab_libfunc (smul_optab, DImode, "__mulll");
8163 set_optab_libfunc (sdiv_optab, DImode, "__divll");
8164 set_optab_libfunc (smod_optab, DImode, "__modll");
8165 set_optab_libfunc (umod_optab, DImode, "__umodll");
8166 set_optab_libfunc (and_optab, DImode, "__andll");
8167 set_optab_libfunc (ior_optab, DImode, "__orll");
8168 set_optab_libfunc (xor_optab, DImode, "__xorll");
8169 set_optab_libfunc (one_cmpl_optab, DImode, "__notll");
8171 set_optab_libfunc (add_optab, SFmode, "__addf");
8172 set_optab_libfunc (sub_optab, SFmode, "__subf");
8173 set_optab_libfunc (smul_optab, SFmode, "__mulf");
8174 set_optab_libfunc (sdiv_optab, SFmode, "__divf");
8176 set_optab_libfunc (add_optab, DFmode, "__addd");
8177 set_optab_libfunc (sub_optab, DFmode, "__subd");
8178 set_optab_libfunc (smul_optab, DFmode, "__muld");
8179 set_optab_libfunc (sdiv_optab, DFmode, "__divd");
8181 set_conv_libfunc (sext_optab, DFmode, SFmode, "__ftod");
8182 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__dtof");
8184 set_conv_libfunc (sfix_optab, SImode, SFmode, "__ftoi");
8185 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8186 set_conv_libfunc (sfix_optab, SImode, DFmode, "__dtoi");
8187 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8189 set_conv_libfunc (ufix_optab, SImode, SFmode, "__ftoui");
8190 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8191 set_conv_libfunc (ufix_optab, SImode, DFmode, "__dtoui");
8192 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8194 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__itof");
8195 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__lltof");
8196 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__itod");
8197 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__lltod");
8200 /* Convert an integer constant to an accumulator register. ICODE is the
8201 code of the target instruction, OPNUM is the number of the
8202 accumulator operand and OPVAL is the constant integer. Try both
8203 ACC and ACCG registers; only report an error if neither fit the
8207 frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
8212 /* ACCs and ACCGs are implicity global registers if media intrinsics
8213 are being used. We set up this lazily to avoid creating lots of
8214 unnecessary call_insn rtl in non-media code. */
8215 for (i = 0; i <= ACC_MASK; i++)
8216 if ((i & ACC_MASK) == i)
8217 global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
8219 if (GET_CODE (opval) != CONST_INT)
8221 error ("accumulator is not a constant integer");
8224 if ((INTVAL (opval) & ~ACC_MASK) != 0)
8226 error ("accumulator number is out of bounds");
8230 reg = gen_rtx_REG (insn_data[icode].operand[opnum].mode,
8231 ACC_FIRST + INTVAL (opval));
8232 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8233 REGNO (reg) = ACCG_FIRST + INTVAL (opval);
8235 if (! (*insn_data[icode].operand[opnum].predicate) (reg, VOIDmode))
8237 error ("inappropriate accumulator for %qs", insn_data[icode].name);
8243 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8246 static enum machine_mode
8247 frv_matching_accg_mode (enum machine_mode mode)
8265 /* Return the accumulator guard that should be paired with accumulator
8266 register ACC. The mode of the returned register is in the same
8267 class as ACC, but is four times smaller. */
8270 frv_matching_accg_for_acc (rtx acc)
8272 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc)),
8273 REGNO (acc) - ACC_FIRST + ACCG_FIRST);
8276 /* Read a value from the head of the tree list pointed to by ARGLISTPTR.
8277 Return the value as an rtx and replace *ARGLISTPTR with the tail of the
8281 frv_read_argument (tree *arglistptr)
8283 tree next = TREE_VALUE (*arglistptr);
8284 *arglistptr = TREE_CHAIN (*arglistptr);
8285 return expand_expr (next, NULL_RTX, VOIDmode, 0);
8288 /* Like frv_read_argument, but interpret the argument as the number
8289 of an IACC register and return a (reg:MODE ...) rtx for it. */
8292 frv_read_iacc_argument (enum machine_mode mode, tree *arglistptr)
8297 op = frv_read_argument (arglistptr);
8298 if (GET_CODE (op) != CONST_INT
8300 || INTVAL (op) > IACC_LAST - IACC_FIRST
8301 || ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
8303 error ("invalid IACC argument");
8307 /* IACCs are implicity global registers. We set up this lazily to
8308 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8310 regno = INTVAL (op) + IACC_FIRST;
8311 for (i = 0; i < HARD_REGNO_NREGS (regno, mode); i++)
8312 global_regs[regno + i] = 1;
8314 return gen_rtx_REG (mode, regno);
8317 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8318 The instruction should require a constant operand of some sort. The
8319 function prints an error if OPVAL is not valid. */
8322 frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
8324 if (GET_CODE (opval) != CONST_INT)
8326 error ("%qs expects a constant argument", insn_data[icode].name);
8329 if (! (*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
8331 error ("constant argument out of range for %qs", insn_data[icode].name);
8337 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8338 if it's not null, has the right mode, and satisfies operand 0's
8342 frv_legitimize_target (enum insn_code icode, rtx target)
8344 enum machine_mode mode = insn_data[icode].operand[0].mode;
8347 || GET_MODE (target) != mode
8348 || ! (*insn_data[icode].operand[0].predicate) (target, mode))
8349 return gen_reg_rtx (mode);
8354 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8355 check whether ARG satisfies the operand's constraints. If it doesn't,
8356 copy ARG to a temporary register and return that. Otherwise return ARG
8360 frv_legitimize_argument (enum insn_code icode, int opnum, rtx arg)
8362 enum machine_mode mode = insn_data[icode].operand[opnum].mode;
8364 if ((*insn_data[icode].operand[opnum].predicate) (arg, mode))
8367 return copy_to_mode_reg (mode, arg);
8370 /* Expand builtins that take a single, constant argument. At the moment,
8371 only MHDSETS falls into this category. */
8374 frv_expand_set_builtin (enum insn_code icode, tree arglist, rtx target)
8377 rtx op0 = frv_read_argument (&arglist);
8379 if (! frv_check_constant_argument (icode, 1, op0))
8382 target = frv_legitimize_target (icode, target);
8383 pat = GEN_FCN (icode) (target, op0);
8391 /* Expand builtins that take one operand. */
8394 frv_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
8397 rtx op0 = frv_read_argument (&arglist);
8399 target = frv_legitimize_target (icode, target);
8400 op0 = frv_legitimize_argument (icode, 1, op0);
8401 pat = GEN_FCN (icode) (target, op0);
8409 /* Expand builtins that take two operands. */
8412 frv_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
8415 rtx op0 = frv_read_argument (&arglist);
8416 rtx op1 = frv_read_argument (&arglist);
8418 target = frv_legitimize_target (icode, target);
8419 op0 = frv_legitimize_argument (icode, 1, op0);
8420 op1 = frv_legitimize_argument (icode, 2, op1);
8421 pat = GEN_FCN (icode) (target, op0, op1);
8429 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8433 frv_expand_cut_builtin (enum insn_code icode, tree arglist, rtx target)
8436 rtx op0 = frv_read_argument (&arglist);
8437 rtx op1 = frv_read_argument (&arglist);
8440 target = frv_legitimize_target (icode, target);
8441 op0 = frv_int_to_acc (icode, 1, op0);
8445 if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
8447 if (! frv_check_constant_argument (icode, 2, op1))
8451 op1 = frv_legitimize_argument (icode, 2, op1);
8453 op2 = frv_matching_accg_for_acc (op0);
8454 pat = GEN_FCN (icode) (target, op0, op1, op2);
8462 /* Expand builtins that take two operands and the second is immediate. */
8465 frv_expand_binopimm_builtin (enum insn_code icode, tree arglist, rtx target)
8468 rtx op0 = frv_read_argument (&arglist);
8469 rtx op1 = frv_read_argument (&arglist);
8471 if (! frv_check_constant_argument (icode, 2, op1))
8474 target = frv_legitimize_target (icode, target);
8475 op0 = frv_legitimize_argument (icode, 1, op0);
8476 pat = GEN_FCN (icode) (target, op0, op1);
8484 /* Expand builtins that take two operands, the first operand being a pointer to
8485 ints and return void. */
8488 frv_expand_voidbinop_builtin (enum insn_code icode, tree arglist)
8491 rtx op0 = frv_read_argument (&arglist);
8492 rtx op1 = frv_read_argument (&arglist);
8493 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
8496 if (GET_CODE (op0) != MEM)
8500 if (! offsettable_address_p (0, mode0, op0))
8502 reg = gen_reg_rtx (Pmode);
8503 emit_insn (gen_rtx_SET (VOIDmode, reg, op0));
8506 op0 = gen_rtx_MEM (SImode, reg);
8509 addr = XEXP (op0, 0);
8510 if (! offsettable_address_p (0, mode0, addr))
8511 addr = copy_to_mode_reg (Pmode, op0);
8513 op0 = change_address (op0, V4SImode, addr);
8514 op1 = frv_legitimize_argument (icode, 1, op1);
8515 pat = GEN_FCN (icode) (op0, op1);
8523 /* Expand builtins that take two long operands and return void. */
8526 frv_expand_int_void2arg (enum insn_code icode, tree arglist)
8529 rtx op0 = frv_read_argument (&arglist);
8530 rtx op1 = frv_read_argument (&arglist);
8532 op0 = frv_legitimize_argument (icode, 1, op0);
8533 op1 = frv_legitimize_argument (icode, 1, op1);
8534 pat = GEN_FCN (icode) (op0, op1);
8542 /* Expand prefetch builtins. These take a single address as argument. */
8545 frv_expand_prefetches (enum insn_code icode, tree arglist)
8548 rtx op0 = frv_read_argument (&arglist);
8550 pat = GEN_FCN (icode) (force_reg (Pmode, op0));
8558 /* Expand builtins that take three operands and return void. The first
8559 argument must be a constant that describes a pair or quad accumulators. A
8560 fourth argument is created that is the accumulator guard register that
8561 corresponds to the accumulator. */
8564 frv_expand_voidtriop_builtin (enum insn_code icode, tree arglist)
8567 rtx op0 = frv_read_argument (&arglist);
8568 rtx op1 = frv_read_argument (&arglist);
8569 rtx op2 = frv_read_argument (&arglist);
8572 op0 = frv_int_to_acc (icode, 0, op0);
8576 op1 = frv_legitimize_argument (icode, 1, op1);
8577 op2 = frv_legitimize_argument (icode, 2, op2);
8578 op3 = frv_matching_accg_for_acc (op0);
8579 pat = GEN_FCN (icode) (op0, op1, op2, op3);
8587 /* Expand builtins that perform accumulator-to-accumulator operations.
8588 These builtins take two accumulator numbers as argument and return
8592 frv_expand_voidaccop_builtin (enum insn_code icode, tree arglist)
8595 rtx op0 = frv_read_argument (&arglist);
8596 rtx op1 = frv_read_argument (&arglist);
8600 op0 = frv_int_to_acc (icode, 0, op0);
8604 op1 = frv_int_to_acc (icode, 1, op1);
8608 op2 = frv_matching_accg_for_acc (op0);
8609 op3 = frv_matching_accg_for_acc (op1);
8610 pat = GEN_FCN (icode) (op0, op1, op2, op3);
8618 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
8619 each argument forms one word of the two double-word input registers.
8620 ARGLIST is a TREE_LIST of the arguments and TARGET, if nonnull,
8621 suggests a good place to put the return value. */
8624 frv_expand_mdpackh_builtin (tree arglist, rtx target)
8626 enum insn_code icode = CODE_FOR_mdpackh;
8628 rtx arg1 = frv_read_argument (&arglist);
8629 rtx arg2 = frv_read_argument (&arglist);
8630 rtx arg3 = frv_read_argument (&arglist);
8631 rtx arg4 = frv_read_argument (&arglist);
8633 target = frv_legitimize_target (icode, target);
8634 op0 = gen_reg_rtx (DImode);
8635 op1 = gen_reg_rtx (DImode);
8637 /* The high half of each word is not explicitly initialised, so indicate
8638 that the input operands are not live before this point. */
8639 emit_insn (gen_rtx_CLOBBER (DImode, op0));
8640 emit_insn (gen_rtx_CLOBBER (DImode, op1));
8642 /* Move each argument into the low half of its associated input word. */
8643 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 2), arg1);
8644 emit_move_insn (simplify_gen_subreg (HImode, op0, DImode, 6), arg2);
8645 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 2), arg3);
8646 emit_move_insn (simplify_gen_subreg (HImode, op1, DImode, 6), arg4);
8648 pat = GEN_FCN (icode) (target, op0, op1);
8656 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
8657 number as argument. */
8660 frv_expand_mclracc_builtin (tree arglist)
8662 enum insn_code icode = CODE_FOR_mclracc;
8664 rtx op0 = frv_read_argument (&arglist);
8666 op0 = frv_int_to_acc (icode, 0, op0);
8670 pat = GEN_FCN (icode) (op0);
8677 /* Expand builtins that take no arguments. */
8680 frv_expand_noargs_builtin (enum insn_code icode)
8682 rtx pat = GEN_FCN (icode) (const0_rtx);
8689 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
8690 number or accumulator guard number as argument and return an SI integer. */
8693 frv_expand_mrdacc_builtin (enum insn_code icode, tree arglist)
8696 rtx target = gen_reg_rtx (SImode);
8697 rtx op0 = frv_read_argument (&arglist);
8699 op0 = frv_int_to_acc (icode, 1, op0);
8703 pat = GEN_FCN (icode) (target, op0);
8711 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
8712 accumulator guard as their first argument and an SImode value as their
8716 frv_expand_mwtacc_builtin (enum insn_code icode, tree arglist)
8719 rtx op0 = frv_read_argument (&arglist);
8720 rtx op1 = frv_read_argument (&arglist);
8722 op0 = frv_int_to_acc (icode, 0, op0);
8726 op1 = frv_legitimize_argument (icode, 1, op1);
8727 pat = GEN_FCN (icode) (op0, op1);
8734 /* Emit a move from SRC to DEST in SImode chunks. This can be used
8735 to move DImode values into and out of IACC0. */
8738 frv_split_iacc_move (rtx dest, rtx src)
8740 enum machine_mode inner;
8743 inner = GET_MODE (dest);
8744 for (i = 0; i < GET_MODE_SIZE (inner); i += GET_MODE_SIZE (SImode))
8745 emit_move_insn (simplify_gen_subreg (SImode, dest, inner, i),
8746 simplify_gen_subreg (SImode, src, inner, i));
8749 /* Expand builtins. */
8752 frv_expand_builtin (tree exp,
8754 rtx subtarget ATTRIBUTE_UNUSED,
8755 enum machine_mode mode ATTRIBUTE_UNUSED,
8756 int ignore ATTRIBUTE_UNUSED)
8758 tree arglist = TREE_OPERAND (exp, 1);
8759 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8760 unsigned fcode = (unsigned)DECL_FUNCTION_CODE (fndecl);
8762 struct builtin_description *d;
8764 if (fcode < FRV_BUILTIN_FIRST_NONMEDIA && !TARGET_MEDIA)
8766 error ("media functions are not available unless -mmedia is used");
8772 case FRV_BUILTIN_MCOP1:
8773 case FRV_BUILTIN_MCOP2:
8774 case FRV_BUILTIN_MDUNPACKH:
8775 case FRV_BUILTIN_MBTOHE:
8776 if (! TARGET_MEDIA_REV1)
8778 error ("this media function is only available on the fr500");
8783 case FRV_BUILTIN_MQXMACHS:
8784 case FRV_BUILTIN_MQXMACXHS:
8785 case FRV_BUILTIN_MQMACXHS:
8786 case FRV_BUILTIN_MADDACCS:
8787 case FRV_BUILTIN_MSUBACCS:
8788 case FRV_BUILTIN_MASACCS:
8789 case FRV_BUILTIN_MDADDACCS:
8790 case FRV_BUILTIN_MDSUBACCS:
8791 case FRV_BUILTIN_MDASACCS:
8792 case FRV_BUILTIN_MABSHS:
8793 case FRV_BUILTIN_MDROTLI:
8794 case FRV_BUILTIN_MCPLHI:
8795 case FRV_BUILTIN_MCPLI:
8796 case FRV_BUILTIN_MDCUTSSI:
8797 case FRV_BUILTIN_MQSATHS:
8798 case FRV_BUILTIN_MHSETLOS:
8799 case FRV_BUILTIN_MHSETLOH:
8800 case FRV_BUILTIN_MHSETHIS:
8801 case FRV_BUILTIN_MHSETHIH:
8802 case FRV_BUILTIN_MHDSETS:
8803 case FRV_BUILTIN_MHDSETH:
8804 if (! TARGET_MEDIA_REV2)
8806 error ("this media function is only available on the fr400"
8812 case FRV_BUILTIN_SMASS:
8813 case FRV_BUILTIN_SMSSS:
8814 case FRV_BUILTIN_SMU:
8815 case FRV_BUILTIN_ADDSS:
8816 case FRV_BUILTIN_SUBSS:
8817 case FRV_BUILTIN_SLASS:
8818 case FRV_BUILTIN_SCUTSS:
8819 case FRV_BUILTIN_IACCreadll:
8820 case FRV_BUILTIN_IACCreadl:
8821 case FRV_BUILTIN_IACCsetll:
8822 case FRV_BUILTIN_IACCsetl:
8823 if (!TARGET_FR405_BUILTINS)
8825 error ("this builtin function is only available"
8826 " on the fr405 and fr450");
8831 case FRV_BUILTIN_PREFETCH:
8832 if (!TARGET_FR500_FR550_BUILTINS)
8834 error ("this builtin function is only available on the fr500"
8840 case FRV_BUILTIN_MQLCLRHS:
8841 case FRV_BUILTIN_MQLMTHS:
8842 case FRV_BUILTIN_MQSLLHI:
8843 case FRV_BUILTIN_MQSRAHI:
8844 if (!TARGET_MEDIA_FR450)
8846 error ("this builtin function is only available on the fr450");
8855 /* Expand unique builtins. */
8859 case FRV_BUILTIN_MTRAP:
8860 return frv_expand_noargs_builtin (CODE_FOR_mtrap);
8862 case FRV_BUILTIN_MCLRACC:
8863 return frv_expand_mclracc_builtin (arglist);
8865 case FRV_BUILTIN_MCLRACCA:
8867 return frv_expand_noargs_builtin (CODE_FOR_mclracca8);
8869 return frv_expand_noargs_builtin (CODE_FOR_mclracca4);
8871 case FRV_BUILTIN_MRDACC:
8872 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc, arglist);
8874 case FRV_BUILTIN_MRDACCG:
8875 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg, arglist);
8877 case FRV_BUILTIN_MWTACC:
8878 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc, arglist);
8880 case FRV_BUILTIN_MWTACCG:
8881 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg, arglist);
8883 case FRV_BUILTIN_MDPACKH:
8884 return frv_expand_mdpackh_builtin (arglist, target);
8886 case FRV_BUILTIN_IACCreadll:
8888 rtx src = frv_read_iacc_argument (DImode, &arglist);
8889 if (target == 0 || !REG_P (target))
8890 target = gen_reg_rtx (DImode);
8891 frv_split_iacc_move (target, src);
8895 case FRV_BUILTIN_IACCreadl:
8896 return frv_read_iacc_argument (SImode, &arglist);
8898 case FRV_BUILTIN_IACCsetll:
8900 rtx dest = frv_read_iacc_argument (DImode, &arglist);
8901 rtx src = frv_read_argument (&arglist);
8902 frv_split_iacc_move (dest, force_reg (DImode, src));
8906 case FRV_BUILTIN_IACCsetl:
8908 rtx dest = frv_read_iacc_argument (SImode, &arglist);
8909 rtx src = frv_read_argument (&arglist);
8910 emit_move_insn (dest, force_reg (SImode, src));
8918 /* Expand groups of builtins. */
8920 for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
8921 if (d->code == fcode)
8922 return frv_expand_set_builtin (d->icode, arglist, target);
8924 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8925 if (d->code == fcode)
8926 return frv_expand_unop_builtin (d->icode, arglist, target);
8928 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8929 if (d->code == fcode)
8930 return frv_expand_binop_builtin (d->icode, arglist, target);
8932 for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
8933 if (d->code == fcode)
8934 return frv_expand_cut_builtin (d->icode, arglist, target);
8936 for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
8937 if (d->code == fcode)
8938 return frv_expand_binopimm_builtin (d->icode, arglist, target);
8940 for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
8941 if (d->code == fcode)
8942 return frv_expand_voidbinop_builtin (d->icode, arglist);
8944 for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
8945 if (d->code == fcode)
8946 return frv_expand_voidtriop_builtin (d->icode, arglist);
8948 for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
8949 if (d->code == fcode)
8950 return frv_expand_voidaccop_builtin (d->icode, arglist);
8952 for (i = 0, d = bdesc_int_void2arg;
8953 i < ARRAY_SIZE (bdesc_int_void2arg); i++, d++)
8954 if (d->code == fcode)
8955 return frv_expand_int_void2arg (d->icode, arglist);
8957 for (i = 0, d = bdesc_prefetches;
8958 i < ARRAY_SIZE (bdesc_prefetches); i++, d++)
8959 if (d->code == fcode)
8960 return frv_expand_prefetches (d->icode, arglist);
8966 frv_in_small_data_p (tree decl)
8971 /* Don't apply the -G flag to internal compiler structures. We
8972 should leave such structures in the main data section, partly
8973 for efficiency and partly because the size of some of them
8974 (such as C++ typeinfos) is not known until later. */
8975 if (TREE_CODE (decl) != VAR_DECL || DECL_ARTIFICIAL (decl))
8978 /* If we already know which section the decl should be in, see if
8979 it's a small data section. */
8980 section_name = DECL_SECTION_NAME (decl);
8983 if (TREE_CODE (section_name) != STRING_CST)
8985 if (frv_string_begins_with (section_name, ".sdata"))
8987 if (frv_string_begins_with (section_name, ".sbss"))
8992 size = int_size_in_bytes (TREE_TYPE (decl));
8993 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
9000 frv_rtx_costs (rtx x,
9001 int code ATTRIBUTE_UNUSED,
9002 int outer_code ATTRIBUTE_UNUSED,
9005 if (outer_code == MEM)
9007 /* Don't differentiate between memory addresses. All the ones
9008 we accept have equal cost. */
9009 *total = COSTS_N_INSNS (0);
9016 /* Make 12 bit integers really cheap. */
9017 if (IN_RANGE_P (INTVAL (x), -2048, 2047))
9028 *total = COSTS_N_INSNS (2);
9042 if (GET_MODE (x) == SImode)
9043 *total = COSTS_N_INSNS (1);
9044 else if (GET_MODE (x) == DImode)
9045 *total = COSTS_N_INSNS (2);
9047 *total = COSTS_N_INSNS (3);
9051 if (GET_MODE (x) == SImode)
9052 *total = COSTS_N_INSNS (2);
9054 *total = COSTS_N_INSNS (6); /* guess */
9061 *total = COSTS_N_INSNS (18);
9065 *total = COSTS_N_INSNS (3);
9074 frv_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9077 assemble_align (POINTER_SIZE);
9080 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
9084 assemble_integer_with_op ("\t.picptr\t", symbol);
9088 frv_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9091 assemble_align (POINTER_SIZE);
9094 if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
9098 assemble_integer_with_op ("\t.picptr\t", symbol);
9101 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9104 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9105 int incoming ATTRIBUTE_UNUSED)
9107 return gen_rtx_REG (Pmode, FRV_STRUCT_VALUE_REGNUM);
9110 #define TLS_BIAS (2048 - 16)
9112 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9113 We need to emit DTP-relative relocations. */
9116 frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
9120 fputs ("\t.picptr\ttlsmoff(", file);
9121 /* We want the unbiased TLS offset, so add the bias to the
9122 expression, such that the implicit biasing cancels out. */
9123 output_addr_const (file, plus_constant (x, TLS_BIAS));